1a23fd118Syl150051 /* 2a23fd118Syl150051 * CDDL HEADER START 3a23fd118Syl150051 * 4a23fd118Syl150051 * The contents of this file are subject to the terms of the 5a23fd118Syl150051 * Common Development and Distribution License (the "License"). 6a23fd118Syl150051 * You may not use this file except in compliance with the License. 7a23fd118Syl150051 * 8a23fd118Syl150051 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9a23fd118Syl150051 * or http://www.opensolaris.org/os/licensing. 10a23fd118Syl150051 * See the License for the specific language governing permissions 11a23fd118Syl150051 * and limitations under the License. 12a23fd118Syl150051 * 13a23fd118Syl150051 * When distributing Covered Code, include this CDDL HEADER in each 14a23fd118Syl150051 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15a23fd118Syl150051 * If applicable, add the following below this CDDL HEADER, with the 16a23fd118Syl150051 * fields enclosed by brackets "[]" replaced with your own identifying 17a23fd118Syl150051 * information: Portions Copyright [yyyy] [name of copyright owner] 18a23fd118Syl150051 * 19a23fd118Syl150051 * CDDL HEADER END 20a23fd118Syl150051 */ 21a23fd118Syl150051 22a23fd118Syl150051 /* 23*7eced415Sxw161283 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24a23fd118Syl150051 * Use is subject to license terms. 25a23fd118Syl150051 */ 26a23fd118Syl150051 27a23fd118Syl150051 /* 28a23fd118Syl150051 * Copyright (c) 2002-2005 Neterion, Inc. 29a23fd118Syl150051 * All right Reserved. 30a23fd118Syl150051 * 31a23fd118Syl150051 * FileName : xge_osdep.h 32a23fd118Syl150051 * 33a23fd118Syl150051 * Description: OSPAL - Solaris 34a23fd118Syl150051 * 35a23fd118Syl150051 */ 36a23fd118Syl150051 37a23fd118Syl150051 #ifndef _SYS_XGE_OSDEP_H 38a23fd118Syl150051 #define _SYS_XGE_OSDEP_H 39a23fd118Syl150051 40a23fd118Syl150051 #pragma ident "%Z%%M% %I% %E% SMI" 41a23fd118Syl150051 42a23fd118Syl150051 #include <sys/ddi.h> 43a23fd118Syl150051 #include <sys/sunddi.h> 44a23fd118Syl150051 #include <sys/varargs.h> 45a23fd118Syl150051 #include <sys/atomic.h> 46a23fd118Syl150051 #include <sys/policy.h> 47a23fd118Syl150051 #include <sys/int_fmtio.h> 48a23fd118Syl150051 #include <sys/thread.h> 49a23fd118Syl150051 #include <sys/cpuvar.h> 50a23fd118Syl150051 51a23fd118Syl150051 #include <inet/common.h> 52a23fd118Syl150051 #include <inet/ip.h> 53a23fd118Syl150051 #include <inet/mi.h> 54a23fd118Syl150051 #include <inet/nd.h> 55a23fd118Syl150051 56a23fd118Syl150051 #ifdef __cplusplus 57a23fd118Syl150051 extern "C" { 58a23fd118Syl150051 #endif 59a23fd118Syl150051 60a23fd118Syl150051 /* ------------------------- includes and defines ------------------------- */ 61a23fd118Syl150051 62a23fd118Syl150051 #define XGE_HAL_TX_MULTI_POST_IRQ 1 63a23fd118Syl150051 #define XGE_HAL_TX_MULTI_RESERVE_IRQ 1 64a23fd118Syl150051 #define XGE_HAL_TX_MULTI_FREE_IRQ 1 65a23fd118Syl150051 #define XGE_HAL_DMA_DTR_CONSISTENT 1 66a23fd118Syl150051 #define XGE_HAL_DMA_STATS_STREAMING 1 67a23fd118Syl150051 68a23fd118Syl150051 #if defined(__sparc) 69a23fd118Syl150051 #define XGE_OS_DMA_REQUIRES_SYNC 1 70a23fd118Syl150051 #endif 71a23fd118Syl150051 728347601bSyl150051 #define XGE_HAL_ALIGN_XMIT 1 738347601bSyl150051 74a23fd118Syl150051 #ifdef _BIG_ENDIAN 75a23fd118Syl150051 #define XGE_OS_HOST_BIG_ENDIAN 1 76a23fd118Syl150051 #else 77a23fd118Syl150051 #define XGE_OS_HOST_LITTLE_ENDIAN 1 78a23fd118Syl150051 #endif 79a23fd118Syl150051 80*7eced415Sxw161283 #if defined(__sparc) 81*7eced415Sxw161283 #define XGE_OS_HOST_PAGE_SIZE 8192 82*7eced415Sxw161283 #else 83*7eced415Sxw161283 #define XGE_OS_HOST_PAGE_SIZE 4096 84*7eced415Sxw161283 #endif 85*7eced415Sxw161283 86a23fd118Syl150051 #if defined(_LP64) 87a23fd118Syl150051 #define XGE_OS_PLATFORM_64BIT 1 88a23fd118Syl150051 #else 89a23fd118Syl150051 #define XGE_OS_PLATFORM_32BIT 1 90a23fd118Syl150051 #endif 91a23fd118Syl150051 92a23fd118Syl150051 #define XGE_OS_HAS_SNPRINTF 1 93a23fd118Syl150051 948347601bSyl150051 /* LRO defines */ 958347601bSyl150051 #define XGE_LL_IP_FAST_CSUM(hdr, len) 0 /* ip_ocsum(hdr, len>>1, 0); */ 968347601bSyl150051 97a23fd118Syl150051 /* ---------------------- fixed size primitive types ----------------------- */ 98a23fd118Syl150051 99a23fd118Syl150051 #define u8 uint8_t 100a23fd118Syl150051 #define u16 uint16_t 101a23fd118Syl150051 #define u32 uint32_t 102a23fd118Syl150051 #define u64 uint64_t 103a23fd118Syl150051 typedef u64 dma_addr_t; 104a23fd118Syl150051 #define ulong_t ulong_t 105a23fd118Syl150051 #define ptrdiff_t ptrdiff_t 106a23fd118Syl150051 typedef kmutex_t spinlock_t; 107a23fd118Syl150051 typedef dev_info_t *pci_dev_h; 108a23fd118Syl150051 typedef ddi_acc_handle_t pci_reg_h; 109a23fd118Syl150051 typedef ddi_acc_handle_t pci_cfg_h; 110*7eced415Sxw161283 typedef uint_t pci_irq_h; 111a23fd118Syl150051 typedef ddi_dma_handle_t pci_dma_h; 112a23fd118Syl150051 typedef ddi_acc_handle_t pci_dma_acc_h; 113a23fd118Syl150051 1148347601bSyl150051 /* LRO types */ 1158347601bSyl150051 #define OS_NETSTACK_BUF mblk_t * 1168347601bSyl150051 #define OS_LL_HEADER uint8_t * 1178347601bSyl150051 #define OS_IP_HEADER uint8_t * 1188347601bSyl150051 #define OS_TL_HEADER uint8_t * 1198347601bSyl150051 120a23fd118Syl150051 /* -------------------------- "libc" functionality ------------------------- */ 121a23fd118Syl150051 122*7eced415Sxw161283 #define xge_os_strlcpy (void) strlcpy 123a23fd118Syl150051 #define xge_os_strlen strlen 124a23fd118Syl150051 #define xge_os_snprintf snprintf 125a23fd118Syl150051 #define xge_os_memzero(addr, size) bzero(addr, size) 126a23fd118Syl150051 #define xge_os_memcpy(dst, src, size) bcopy(src, dst, size) 127a23fd118Syl150051 #define xge_os_memcmp(src1, src2, size) bcmp(src1, src2, size) 1288347601bSyl150051 #define xge_os_ntohl ntohl 1298347601bSyl150051 #define xge_os_htons htons 1308347601bSyl150051 #define xge_os_ntohs ntohs 131a23fd118Syl150051 132a23fd118Syl150051 #ifdef __GNUC__ 133a23fd118Syl150051 #define xge_os_printf(fmt...) cmn_err(CE_CONT, fmt) 134a23fd118Syl150051 #define xge_os_sprintf(buf, fmt...) strlen(sprintf(buf, fmt)) 135a23fd118Syl150051 #else 136a23fd118Syl150051 #define xge_os_vaprintf(fmt) { \ 137a23fd118Syl150051 va_list va; \ 138a23fd118Syl150051 va_start(va, fmt); \ 139a23fd118Syl150051 vcmn_err(CE_CONT, fmt, va); \ 140a23fd118Syl150051 va_end(va); \ 141a23fd118Syl150051 } 142a23fd118Syl150051 143a23fd118Syl150051 static inline void xge_os_printf(char *fmt, ...) { 144a23fd118Syl150051 xge_os_vaprintf(fmt); 145a23fd118Syl150051 } 146a23fd118Syl150051 147a23fd118Syl150051 #define xge_os_vasprintf(buf, fmt) { \ 148a23fd118Syl150051 va_list va; \ 149a23fd118Syl150051 va_start(va, fmt); \ 150a23fd118Syl150051 (void) vsprintf(buf, fmt, va); \ 151a23fd118Syl150051 va_end(va); \ 152a23fd118Syl150051 } 153a23fd118Syl150051 154a23fd118Syl150051 static inline int xge_os_sprintf(char *buf, char *fmt, ...) { 155a23fd118Syl150051 xge_os_vasprintf(buf, fmt); 156a23fd118Syl150051 return (strlen(buf)); 157a23fd118Syl150051 } 158a23fd118Syl150051 #endif 159a23fd118Syl150051 160a23fd118Syl150051 #define xge_os_timestamp(buf) { \ 161a23fd118Syl150051 todinfo_t todinfo = utc_to_tod(ddi_get_time()); \ 162*7eced415Sxw161283 (void) xge_os_sprintf(buf, "%02d/%02d/%02d.%02d:%02d:%02d: ", \ 163a23fd118Syl150051 todinfo.tod_day, todinfo.tod_month, \ 164a23fd118Syl150051 (1970 + todinfo.tod_year - 70), \ 165a23fd118Syl150051 todinfo.tod_hour, todinfo.tod_min, todinfo.tod_sec); \ 166a23fd118Syl150051 } 167a23fd118Syl150051 168a23fd118Syl150051 #define xge_os_println xge_os_printf 169a23fd118Syl150051 170a23fd118Syl150051 /* -------------------- synchronization primitives ------------------------- */ 171a23fd118Syl150051 172a23fd118Syl150051 #define xge_os_spin_lock_init(lockp, ctxh) \ 173a23fd118Syl150051 mutex_init(lockp, NULL, MUTEX_DRIVER, NULL) 174a23fd118Syl150051 #define xge_os_spin_lock_init_irq(lockp, irqh) \ 175*7eced415Sxw161283 mutex_init(lockp, NULL, MUTEX_DRIVER, DDI_INTR_PRI(irqh)) 176a23fd118Syl150051 #define xge_os_spin_lock_destroy(lockp, cthx) \ 177a23fd118Syl150051 (cthx = cthx, mutex_destroy(lockp)) 178a23fd118Syl150051 #define xge_os_spin_lock_destroy_irq(lockp, cthx) \ 179a23fd118Syl150051 (cthx = cthx, mutex_destroy(lockp)) 180a23fd118Syl150051 #define xge_os_spin_lock(lockp) mutex_enter(lockp) 181a23fd118Syl150051 #define xge_os_spin_unlock(lockp) mutex_exit(lockp) 182a23fd118Syl150051 #define xge_os_spin_lock_irq(lockp, flags) (flags = flags, mutex_enter(lockp)) 183a23fd118Syl150051 #define xge_os_spin_unlock_irq(lockp, flags) mutex_exit(lockp) 184a23fd118Syl150051 185a23fd118Syl150051 /* x86 arch will never re-order writes, Sparc can */ 186a23fd118Syl150051 #define xge_os_wmb() membar_producer() 187a23fd118Syl150051 188a23fd118Syl150051 #define xge_os_udelay(us) drv_usecwait(us) 189a23fd118Syl150051 #define xge_os_mdelay(ms) drv_usecwait(ms * 1000) 190a23fd118Syl150051 191a23fd118Syl150051 #define xge_os_cmpxchg(targetp, cmp, newval) \ 192a23fd118Syl150051 sizeof (*(targetp)) == 4 ? \ 193a23fd118Syl150051 cas32((uint32_t *)targetp, cmp, newval) : \ 194a23fd118Syl150051 cas64((uint64_t *)targetp, cmp, newval) 195a23fd118Syl150051 196a23fd118Syl150051 /* ------------------------- misc primitives ------------------------------- */ 197a23fd118Syl150051 198a23fd118Syl150051 #define xge_os_unlikely(x) (x) 199a23fd118Syl150051 #define xge_os_prefetch(a) (a = a) 200a23fd118Syl150051 #define xge_os_prefetchw 201a23fd118Syl150051 #ifdef __GNUC__ 202a23fd118Syl150051 #define xge_os_bug(fmt...) cmn_err(CE_PANIC, fmt) 203a23fd118Syl150051 #else 204a23fd118Syl150051 static inline void xge_os_bug(char *fmt, ...) { 205a23fd118Syl150051 va_list ap; 206a23fd118Syl150051 207a23fd118Syl150051 va_start(ap, fmt); 208a23fd118Syl150051 vcmn_err(CE_PANIC, fmt, ap); 209a23fd118Syl150051 va_end(ap); 210a23fd118Syl150051 } 211a23fd118Syl150051 #endif 212a23fd118Syl150051 213a23fd118Syl150051 /* -------------------------- compiler stuffs ------------------------------ */ 214a23fd118Syl150051 215a23fd118Syl150051 #if defined(__i386) 216a23fd118Syl150051 #define __xge_os_cacheline_size 64 /* L1-cache line size: x86_64 */ 217a23fd118Syl150051 #else 218a23fd118Syl150051 #define __xge_os_cacheline_size 64 /* L1-cache line size: sparcv9 */ 219a23fd118Syl150051 #endif 220a23fd118Syl150051 221a23fd118Syl150051 #ifdef __GNUC__ 222a23fd118Syl150051 #define __xge_os_attr_cacheline_aligned \ 223a23fd118Syl150051 __attribute__((__aligned__(__xge_os_cacheline_size))) 224a23fd118Syl150051 #else 225a23fd118Syl150051 #define __xge_os_attr_cacheline_aligned 226a23fd118Syl150051 #endif 227a23fd118Syl150051 228a23fd118Syl150051 /* ---------------------- memory primitives -------------------------------- */ 229a23fd118Syl150051 230a23fd118Syl150051 static inline void *__xge_os_malloc(pci_dev_h pdev, unsigned long size, 231a23fd118Syl150051 char *file, int line) 232a23fd118Syl150051 { 233a23fd118Syl150051 void *vaddr = kmem_alloc(size, KM_SLEEP); 234a23fd118Syl150051 235a23fd118Syl150051 XGE_OS_MEMORY_CHECK_MALLOC(vaddr, size, file, line); 236a23fd118Syl150051 return (vaddr); 237a23fd118Syl150051 } 238a23fd118Syl150051 239a23fd118Syl150051 static inline void xge_os_free(pci_dev_h pdev, const void *vaddr, 240a23fd118Syl150051 unsigned long size) 241a23fd118Syl150051 { 242a23fd118Syl150051 XGE_OS_MEMORY_CHECK_FREE(vaddr, size); 243a23fd118Syl150051 kmem_free((void*)vaddr, size); 244a23fd118Syl150051 } 245a23fd118Syl150051 246a23fd118Syl150051 #define xge_os_malloc(pdev, size) \ 247a23fd118Syl150051 __xge_os_malloc(pdev, size, __FILE__, __LINE__) 248a23fd118Syl150051 249a23fd118Syl150051 static inline void *__xge_os_dma_malloc(pci_dev_h pdev, unsigned long size, 250a23fd118Syl150051 int dma_flags, pci_dma_h *p_dmah, pci_dma_acc_h *p_dma_acch, char *file, 251a23fd118Syl150051 int line) 252a23fd118Syl150051 { 253a23fd118Syl150051 void *vaddr; 254a23fd118Syl150051 int ret; 255a23fd118Syl150051 size_t real_size; 256a23fd118Syl150051 extern ddi_device_acc_attr_t *p_xge_dev_attr; 257a23fd118Syl150051 extern struct ddi_dma_attr *p_hal_dma_attr; 258a23fd118Syl150051 259*7eced415Sxw161283 ret = ddi_dma_alloc_handle(pdev, p_hal_dma_attr, 260a23fd118Syl150051 DDI_DMA_DONTWAIT, 0, p_dmah); 261a23fd118Syl150051 if (ret != DDI_SUCCESS) { 262a23fd118Syl150051 return (NULL); 263a23fd118Syl150051 } 264a23fd118Syl150051 265a23fd118Syl150051 ret = ddi_dma_mem_alloc(*p_dmah, size, p_xge_dev_attr, 266a23fd118Syl150051 (dma_flags & XGE_OS_DMA_CONSISTENT ? 2678347601bSyl150051 DDI_DMA_CONSISTENT : DDI_DMA_STREAMING), DDI_DMA_DONTWAIT, 0, 2688347601bSyl150051 (caddr_t *)&vaddr, &real_size, p_dma_acch); 269a23fd118Syl150051 if (ret != DDI_SUCCESS) { 270a23fd118Syl150051 ddi_dma_free_handle(p_dmah); 271a23fd118Syl150051 return (NULL); 272a23fd118Syl150051 } 273a23fd118Syl150051 274a23fd118Syl150051 if (size > real_size) { 275a23fd118Syl150051 ddi_dma_mem_free(p_dma_acch); 276a23fd118Syl150051 ddi_dma_free_handle(p_dmah); 277a23fd118Syl150051 return (NULL); 278a23fd118Syl150051 } 279a23fd118Syl150051 280a23fd118Syl150051 XGE_OS_MEMORY_CHECK_MALLOC(vaddr, size, file, line); 281a23fd118Syl150051 282a23fd118Syl150051 return (vaddr); 283a23fd118Syl150051 } 284a23fd118Syl150051 285a23fd118Syl150051 #define xge_os_dma_malloc(pdev, size, dma_flags, p_dmah, p_dma_acch) \ 286a23fd118Syl150051 __xge_os_dma_malloc(pdev, size, dma_flags, p_dmah, p_dma_acch, \ 287a23fd118Syl150051 __FILE__, __LINE__) 288a23fd118Syl150051 289a23fd118Syl150051 static inline void xge_os_dma_free(pci_dev_h pdev, const void *vaddr, int size, 290a23fd118Syl150051 pci_dma_acc_h *p_dma_acch, pci_dma_h *p_dmah) 291a23fd118Syl150051 { 292a23fd118Syl150051 XGE_OS_MEMORY_CHECK_FREE(vaddr, 0); 293a23fd118Syl150051 ddi_dma_mem_free(p_dma_acch); 294a23fd118Syl150051 ddi_dma_free_handle(p_dmah); 295a23fd118Syl150051 } 296a23fd118Syl150051 297a23fd118Syl150051 298a23fd118Syl150051 /* --------------------------- pci primitives ------------------------------ */ 299a23fd118Syl150051 300a23fd118Syl150051 #define xge_os_pci_read8(pdev, cfgh, where, val) \ 301a23fd118Syl150051 (*(val) = pci_config_get8(cfgh, where)) 302a23fd118Syl150051 303a23fd118Syl150051 #define xge_os_pci_write8(pdev, cfgh, where, val) \ 304a23fd118Syl150051 pci_config_put8(cfgh, where, val) 305a23fd118Syl150051 306a23fd118Syl150051 #define xge_os_pci_read16(pdev, cfgh, where, val) \ 307a23fd118Syl150051 (*(val) = pci_config_get16(cfgh, where)) 308a23fd118Syl150051 309a23fd118Syl150051 #define xge_os_pci_write16(pdev, cfgh, where, val) \ 310a23fd118Syl150051 pci_config_put16(cfgh, where, val) 311a23fd118Syl150051 312a23fd118Syl150051 #define xge_os_pci_read32(pdev, cfgh, where, val) \ 313a23fd118Syl150051 (*(val) = pci_config_get32(cfgh, where)) 314a23fd118Syl150051 315a23fd118Syl150051 #define xge_os_pci_write32(pdev, cfgh, where, val) \ 316a23fd118Syl150051 pci_config_put32(cfgh, where, val) 317a23fd118Syl150051 318a23fd118Syl150051 /* --------------------------- io primitives ------------------------------- */ 319a23fd118Syl150051 320a23fd118Syl150051 #define xge_os_pio_mem_read8(pdev, regh, addr) \ 321a23fd118Syl150051 (ddi_get8(regh, (uint8_t *)(addr))) 322a23fd118Syl150051 323a23fd118Syl150051 #define xge_os_pio_mem_write8(pdev, regh, val, addr) \ 324a23fd118Syl150051 (ddi_put8(regh, (uint8_t *)(addr), val)) 325a23fd118Syl150051 326a23fd118Syl150051 #define xge_os_pio_mem_read16(pdev, regh, addr) \ 327a23fd118Syl150051 (ddi_get16(regh, (uint16_t *)(addr))) 328a23fd118Syl150051 329a23fd118Syl150051 #define xge_os_pio_mem_write16(pdev, regh, val, addr) \ 330a23fd118Syl150051 (ddi_put16(regh, (uint16_t *)(addr), val)) 331a23fd118Syl150051 332a23fd118Syl150051 #define xge_os_pio_mem_read32(pdev, regh, addr) \ 333a23fd118Syl150051 (ddi_get32(regh, (uint32_t *)(addr))) 334a23fd118Syl150051 335a23fd118Syl150051 #define xge_os_pio_mem_write32(pdev, regh, val, addr) \ 336a23fd118Syl150051 (ddi_put32(regh, (uint32_t *)(addr), val)) 337a23fd118Syl150051 338a23fd118Syl150051 #define xge_os_pio_mem_read64(pdev, regh, addr) \ 339a23fd118Syl150051 (ddi_get64(regh, (uint64_t *)(addr))) 340a23fd118Syl150051 341a23fd118Syl150051 #define xge_os_pio_mem_write64(pdev, regh, val, addr) \ 342a23fd118Syl150051 (ddi_put64(regh, (uint64_t *)(addr), val)) 343a23fd118Syl150051 344a23fd118Syl150051 #define xge_os_flush_bridge xge_os_pio_mem_read64 345a23fd118Syl150051 346a23fd118Syl150051 /* --------------------------- dma primitives ----------------------------- */ 347a23fd118Syl150051 348a23fd118Syl150051 #define XGE_OS_DMA_DIR_TODEVICE DDI_DMA_SYNC_FORDEV 349a23fd118Syl150051 #define XGE_OS_DMA_DIR_FROMDEVICE DDI_DMA_SYNC_FORKERNEL 350a23fd118Syl150051 #define XGE_OS_DMA_DIR_BIDIRECTIONAL -1 351a23fd118Syl150051 #if defined(__x86) 352a23fd118Syl150051 #define XGE_OS_DMA_USES_IOMMU 0 353a23fd118Syl150051 #else 354a23fd118Syl150051 #define XGE_OS_DMA_USES_IOMMU 1 355a23fd118Syl150051 #endif 356a23fd118Syl150051 357a23fd118Syl150051 #define XGE_OS_INVALID_DMA_ADDR ((dma_addr_t)0) 358a23fd118Syl150051 359a23fd118Syl150051 static inline dma_addr_t xge_os_dma_map(pci_dev_h pdev, pci_dma_h dmah, 360a23fd118Syl150051 void *vaddr, size_t size, int dir, int dma_flags) { 361a23fd118Syl150051 int ret; 362a23fd118Syl150051 uint_t flags; 363a23fd118Syl150051 uint_t ncookies; 364a23fd118Syl150051 ddi_dma_cookie_t dma_cookie; 365a23fd118Syl150051 366a23fd118Syl150051 switch (dir) { 367a23fd118Syl150051 case XGE_OS_DMA_DIR_TODEVICE: 368a23fd118Syl150051 flags = DDI_DMA_WRITE; 369a23fd118Syl150051 break; 370a23fd118Syl150051 case XGE_OS_DMA_DIR_FROMDEVICE: 371a23fd118Syl150051 flags = DDI_DMA_READ; 372a23fd118Syl150051 break; 373a23fd118Syl150051 case XGE_OS_DMA_DIR_BIDIRECTIONAL: 374a23fd118Syl150051 flags = DDI_DMA_RDWR; 375a23fd118Syl150051 break; 376a23fd118Syl150051 default: 377a23fd118Syl150051 return (0); 378a23fd118Syl150051 } 379a23fd118Syl150051 380a23fd118Syl150051 flags |= (dma_flags & XGE_OS_DMA_CONSISTENT) ? 381a23fd118Syl150051 DDI_DMA_CONSISTENT : DDI_DMA_STREAMING; 382a23fd118Syl150051 383a23fd118Syl150051 ret = ddi_dma_addr_bind_handle(dmah, NULL, vaddr, size, flags, 384a23fd118Syl150051 DDI_DMA_SLEEP, 0, &dma_cookie, &ncookies); 385a23fd118Syl150051 if (ret != DDI_SUCCESS) { 386a23fd118Syl150051 return (0); 387a23fd118Syl150051 } 388a23fd118Syl150051 389a23fd118Syl150051 if (ncookies != 1 || dma_cookie.dmac_size < size) { 390a23fd118Syl150051 (void) ddi_dma_unbind_handle(dmah); 391a23fd118Syl150051 return (0); 392a23fd118Syl150051 } 393a23fd118Syl150051 394a23fd118Syl150051 return (dma_cookie.dmac_laddress); 395a23fd118Syl150051 } 396a23fd118Syl150051 397a23fd118Syl150051 static inline void xge_os_dma_unmap(pci_dev_h pdev, pci_dma_h dmah, 398a23fd118Syl150051 dma_addr_t dma_addr, size_t size, int dir) 399a23fd118Syl150051 { 400a23fd118Syl150051 (void) ddi_dma_unbind_handle(dmah); 401a23fd118Syl150051 } 402a23fd118Syl150051 403a23fd118Syl150051 static inline void xge_os_dma_sync(pci_dev_h pdev, pci_dma_h dmah, 404a23fd118Syl150051 dma_addr_t dma_addr, u64 dma_offset, size_t length, int dir) 405a23fd118Syl150051 { 406a23fd118Syl150051 (void) ddi_dma_sync(dmah, dma_offset, length, dir); 407a23fd118Syl150051 } 408a23fd118Syl150051 409a23fd118Syl150051 #ifdef __cplusplus 410a23fd118Syl150051 } 411a23fd118Syl150051 #endif 412a23fd118Syl150051 413a23fd118Syl150051 #endif /* _SYS_XGE_OSDEP_H */ 414