1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Universal Host Controller Driver (UHCI) 30 * 31 * The UHCI driver is a driver which interfaces to the Universal 32 * Serial Bus Driver (USBA) and the Host Controller (HC). The interface to 33 * the Host Controller is defined by the UHCI. 34 * This file contains misc functions. 35 */ 36 #include <sys/usb/hcd/uhci/uhcid.h> 37 #include <sys/usb/hcd/uhci/uhciutil.h> 38 #include <sys/usb/hcd/uhci/uhcipolled.h> 39 40 #include <sys/disp.h> 41 42 /* Globals */ 43 extern uint_t uhci_td_pool_size; /* Num TDs */ 44 extern uint_t uhci_qh_pool_size; /* Num QHs */ 45 extern ushort_t uhci_tree_bottom_nodes[]; 46 extern void *uhci_statep; 47 48 /* function prototypes */ 49 static void uhci_build_interrupt_lattice(uhci_state_t *uhcip); 50 static int uhci_init_frame_lst_table(dev_info_t *dip, uhci_state_t *uhcip); 51 52 static uint_t uhci_lattice_height(uint_t bandwidth); 53 static uint_t uhci_lattice_parent(uint_t node); 54 static uint_t uhci_leftmost_leaf(uint_t node, uint_t height); 55 static uint_t uhci_compute_total_bandwidth(usb_ep_descr_t *endpoint, 56 usb_port_status_t port_status); 57 58 static int uhci_bandwidth_adjust(uhci_state_t *uhcip, 59 usb_ep_descr_t *endpoint, usb_port_status_t port_status); 60 61 static uhci_td_t *uhci_allocate_td_from_pool(uhci_state_t *uhcip); 62 static void uhci_fill_in_td(uhci_state_t *uhcip, 63 uhci_td_t *td, uhci_td_t *current_dummy, 64 uint32_t buffer_offset, size_t length, 65 uhci_pipe_private_t *pp, uchar_t PID, 66 usb_req_attrs_t attrs, uhci_trans_wrapper_t *tw); 67 static uint32_t uhci_get_tw_paddr_by_offs(uhci_state_t *uhcip, 68 uint32_t buffer_offset, size_t length, 69 uhci_trans_wrapper_t *tw); 70 static uhci_trans_wrapper_t *uhci_create_transfer_wrapper( 71 uhci_state_t *uhcip, uhci_pipe_private_t *pp, 72 size_t length, usb_flags_t usb_flags); 73 static uhci_trans_wrapper_t *uhci_create_isoc_transfer_wrapper( 74 uhci_state_t *uhcip, uhci_pipe_private_t *pp, 75 usb_isoc_req_t *req, size_t length, 76 usb_flags_t usb_flags); 77 78 static int uhci_create_setup_pkt(uhci_state_t *uhcip, 79 uhci_pipe_private_t *pp, uhci_trans_wrapper_t *tw); 80 static void uhci_insert_ctrl_qh(uhci_state_t *uhcip, 81 uhci_pipe_private_t *pp); 82 static void uhci_remove_ctrl_qh(uhci_state_t *uhcip, 83 uhci_pipe_private_t *pp); 84 static void uhci_insert_intr_qh(uhci_state_t *uhcip, 85 uhci_pipe_private_t *pp); 86 static void uhci_remove_intr_qh(uhci_state_t *uhcip, 87 uhci_pipe_private_t *pp); 88 static void uhci_remove_bulk_qh(uhci_state_t *uhcip, 89 uhci_pipe_private_t *pp); 90 static void uhci_insert_bulk_qh(uhci_state_t *uhcip, 91 uhci_pipe_private_t *pp); 92 static void uhci_handle_bulk_td_errors(uhci_state_t *uhcip, uhci_td_t *td); 93 static int uhci_alloc_memory_for_tds(uhci_state_t *uhcip, uint_t num_tds, 94 uhci_bulk_isoc_xfer_t *info); 95 static int uhci_alloc_bulk_isoc_tds(uhci_state_t *uhcip, uint_t num_tds, 96 uhci_bulk_isoc_xfer_t *info); 97 static void uhci_get_isoc_td_by_index(uhci_state_t *uhcip, 98 uhci_bulk_isoc_xfer_t *info, uint_t index, 99 uhci_td_t **tdpp, uhci_bulk_isoc_td_pool_t **td_pool_pp); 100 static void uhci_get_bulk_td_by_paddr(uhci_state_t *uhcip, 101 uhci_bulk_isoc_xfer_t *info, uint32_t paddr, 102 uhci_bulk_isoc_td_pool_t **td_pool_pp); 103 104 static int uhci_handle_isoc_receive(uhci_state_t *uhcip, 105 uhci_pipe_private_t *pp, uhci_trans_wrapper_t *tw); 106 static void uhci_delete_isoc_td(uhci_state_t *uhcip, 107 uhci_td_t *td); 108 #ifdef DEBUG 109 static void uhci_print_td(uhci_state_t *uhcip, uhci_td_t *td); 110 static void uhci_print_qh(uhci_state_t *uhcip, queue_head_t *qh); 111 #endif 112 113 114 /* 115 * uhci_build_interrupt_lattice: 116 * 117 * Construct the interrupt lattice tree using static Queue Head pointers. 118 * This interrupt lattice tree will have total of 63 queue heads and the 119 * Host Controller (HC) processes queue heads every frame. 120 */ 121 static void 122 uhci_build_interrupt_lattice(uhci_state_t *uhcip) 123 { 124 int half_list = NUM_INTR_QH_LISTS / 2; 125 uint16_t i, j, k; 126 uhci_td_t *sof_td, *isoc_td; 127 uintptr_t addr; 128 queue_head_t *list_array = uhcip->uhci_qh_pool_addr; 129 queue_head_t *tmp_qh; 130 frame_lst_table_t *frame_lst_tablep = 131 uhcip->uhci_frame_lst_tablep; 132 133 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 134 "uhci_build_interrupt_lattice:"); 135 136 /* 137 * Reserve the first 63 queue head structures in the pool as static 138 * queue heads & these are required for constructing interrupt 139 * lattice tree. 140 */ 141 for (i = 0; i < NUM_INTR_QH_LISTS; i++) { 142 SetQH32(uhcip, list_array[i].link_ptr, HC_END_OF_LIST); 143 SetQH32(uhcip, list_array[i].element_ptr, HC_END_OF_LIST); 144 list_array[i].qh_flag = QUEUE_HEAD_FLAG_STATIC; 145 list_array[i].node = i; 146 } 147 148 /* Build the interrupt lattice tree */ 149 for (i = 0; i < half_list - 1; i++) { 150 /* 151 * The next pointer in the host controller queue head 152 * descriptor must contain an iommu address. Calculate 153 * the offset into the cpu address and add this to the 154 * starting iommu address. 155 */ 156 addr = QH_PADDR(&list_array[i]) | HC_QUEUE_HEAD; 157 158 SetQH32(uhcip, list_array[2*i + 1].link_ptr, addr); 159 SetQH32(uhcip, list_array[2*i + 2].link_ptr, addr); 160 } 161 162 /* 163 * Initialize the interrupt list in the Frame list Table 164 * so that it points to the bottom of the tree. 165 */ 166 for (i = 0, j = 0; i < pow_2(TREE_HEIGHT); i++) { 167 addr = QH_PADDR(&list_array[half_list + i - 1]); 168 for (k = 0; k < pow_2(VIRTUAL_TREE_HEIGHT); k++) { 169 SetFL32(uhcip, 170 frame_lst_tablep[uhci_tree_bottom_nodes[j++]], 171 addr | HC_QUEUE_HEAD); 172 } 173 } 174 175 /* 176 * Create a controller and bulk Queue heads 177 */ 178 uhcip->uhci_ctrl_xfers_q_head = uhci_alloc_queue_head(uhcip); 179 tmp_qh = uhcip->uhci_ctrl_xfers_q_tail = uhcip->uhci_ctrl_xfers_q_head; 180 181 SetQH32(uhcip, list_array[0].link_ptr, 182 (QH_PADDR(tmp_qh) | HC_QUEUE_HEAD)); 183 184 uhcip->uhci_bulk_xfers_q_head = uhci_alloc_queue_head(uhcip); 185 uhcip->uhci_bulk_xfers_q_tail = uhcip->uhci_bulk_xfers_q_head; 186 SetQH32(uhcip, tmp_qh->link_ptr, 187 (QH_PADDR(uhcip->uhci_bulk_xfers_q_head)|HC_QUEUE_HEAD)); 188 189 SetQH32(uhcip, uhcip->uhci_bulk_xfers_q_head->link_ptr, HC_END_OF_LIST); 190 191 /* 192 * Add a dummy TD to the static queue head 0. THis is used 193 * to generate an at the end of frame. 194 */ 195 sof_td = uhci_allocate_td_from_pool(uhcip); 196 197 SetQH32(uhcip, list_array[0].element_ptr, 198 TD_PADDR(sof_td) | HC_TD_HEAD); 199 SetTD32(uhcip, sof_td->link_ptr, HC_END_OF_LIST); 200 uhcip->uhci_sof_td = sof_td; 201 202 /* 203 * Add a dummy td that is used to generate an interrupt for 204 * every 1024 frames. 205 */ 206 isoc_td = uhci_allocate_td_from_pool(uhcip); 207 SetTD32(uhcip, isoc_td->link_ptr, HC_END_OF_LIST); 208 uhcip->uhci_isoc_td = isoc_td; 209 210 uhcip->uhci_isoc_qh = uhci_alloc_queue_head(uhcip); 211 SetQH32(uhcip, uhcip->uhci_isoc_qh->link_ptr, 212 GetFL32(uhcip, uhcip->uhci_frame_lst_tablep[MAX_FRAME_NUM])); 213 SetQH32(uhcip, uhcip->uhci_isoc_qh->element_ptr, TD_PADDR(isoc_td)); 214 SetFL32(uhcip, uhcip->uhci_frame_lst_tablep[MAX_FRAME_NUM], 215 QH_PADDR(uhcip->uhci_isoc_qh) | HC_QUEUE_HEAD); 216 } 217 218 219 /* 220 * uhci_allocate_pools: 221 * Allocate the system memory for the Queue Heads Descriptor and 222 * for the Transfer Descriptor (TD) pools. Both QH and TD structures 223 * must be aligned to a 16 byte boundary. 224 */ 225 int 226 uhci_allocate_pools(uhci_state_t *uhcip) 227 { 228 dev_info_t *dip = uhcip->uhci_dip; 229 size_t real_length; 230 int i, result; 231 uint_t ccount; 232 ddi_device_acc_attr_t dev_attr; 233 234 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 235 "uhci_allocate_pools:"); 236 237 /* The host controller will be little endian */ 238 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 239 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 240 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 241 242 /* Allocate the TD pool DMA handle */ 243 if (ddi_dma_alloc_handle(dip, &uhcip->uhci_dma_attr, DDI_DMA_SLEEP, 0, 244 &uhcip->uhci_td_pool_dma_handle) != DDI_SUCCESS) { 245 246 return (USB_FAILURE); 247 } 248 249 /* Allocate the memory for the TD pool */ 250 if (ddi_dma_mem_alloc(uhcip->uhci_td_pool_dma_handle, 251 uhci_td_pool_size * sizeof (uhci_td_t), 252 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 0, 253 (caddr_t *)&uhcip->uhci_td_pool_addr, &real_length, 254 &uhcip->uhci_td_pool_mem_handle)) { 255 256 return (USB_FAILURE); 257 } 258 259 /* Map the TD pool into the I/O address space */ 260 result = ddi_dma_addr_bind_handle(uhcip->uhci_td_pool_dma_handle, 261 NULL, (caddr_t)uhcip->uhci_td_pool_addr, real_length, 262 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 263 NULL, &uhcip->uhci_td_pool_cookie, &ccount); 264 265 bzero((void *)uhcip->uhci_td_pool_addr, 266 uhci_td_pool_size * sizeof (uhci_td_t)); 267 268 /* Process the result */ 269 if (result == DDI_DMA_MAPPED) { 270 /* The cookie count should be 1 */ 271 if (ccount != 1) { 272 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 273 "uhci_allocate_pools: More than 1 cookie"); 274 275 return (USB_FAILURE); 276 } 277 } else { 278 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 279 "uhci_allocate_pools: Result = %d", result); 280 281 uhci_decode_ddi_dma_addr_bind_handle_result(uhcip, result); 282 283 return (USB_FAILURE); 284 } 285 286 uhcip->uhci_dma_addr_bind_flag |= UHCI_TD_POOL_BOUND; 287 288 /* Initialize the TD pool */ 289 for (i = 0; i < uhci_td_pool_size; i++) { 290 uhcip->uhci_td_pool_addr[i].flag = TD_FLAG_FREE; 291 } 292 293 /* Allocate the TD pool DMA handle */ 294 if (ddi_dma_alloc_handle(dip, &uhcip->uhci_dma_attr, DDI_DMA_SLEEP, 295 0, &uhcip->uhci_qh_pool_dma_handle) != DDI_SUCCESS) { 296 297 return (USB_FAILURE); 298 } 299 300 /* Allocate the memory for the QH pool */ 301 if (ddi_dma_mem_alloc(uhcip->uhci_qh_pool_dma_handle, 302 uhci_qh_pool_size * sizeof (queue_head_t), 303 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 0, 304 (caddr_t *)&uhcip->uhci_qh_pool_addr, &real_length, 305 &uhcip->uhci_qh_pool_mem_handle) != DDI_SUCCESS) { 306 307 return (USB_FAILURE); 308 } 309 310 result = ddi_dma_addr_bind_handle(uhcip->uhci_qh_pool_dma_handle, 311 NULL, (caddr_t)uhcip->uhci_qh_pool_addr, real_length, 312 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 313 &uhcip->uhci_qh_pool_cookie, &ccount); 314 315 /* Process the result */ 316 if (result == DDI_DMA_MAPPED) { 317 /* The cookie count should be 1 */ 318 if (ccount != 1) { 319 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 320 "uhci_allocate_pools: More than 1 cookie"); 321 322 return (USB_FAILURE); 323 } 324 } else { 325 uhci_decode_ddi_dma_addr_bind_handle_result(uhcip, result); 326 327 return (USB_FAILURE); 328 } 329 330 uhcip->uhci_dma_addr_bind_flag |= UHCI_QH_POOL_BOUND; 331 332 bzero((void *)uhcip->uhci_qh_pool_addr, 333 uhci_qh_pool_size * sizeof (queue_head_t)); 334 335 /* Initialize the QH pool */ 336 for (i = 0; i < uhci_qh_pool_size; i ++) { 337 uhcip->uhci_qh_pool_addr[i].qh_flag = QUEUE_HEAD_FLAG_FREE; 338 } 339 340 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 341 "uhci_allocate_pools: Completed"); 342 343 return (USB_SUCCESS); 344 } 345 346 347 /* 348 * uhci_free_pools: 349 * Cleanup on attach failure or detach 350 */ 351 void 352 uhci_free_pools(uhci_state_t *uhcip) 353 { 354 int i, flag, rval; 355 uhci_td_t *td; 356 uhci_trans_wrapper_t *tw; 357 358 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 359 "uhci_free_pools:"); 360 361 if (uhcip->uhci_td_pool_addr && uhcip->uhci_td_pool_mem_handle) { 362 for (i = 0; i < uhci_td_pool_size; i ++) { 363 td = &uhcip->uhci_td_pool_addr[i]; 364 365 flag = uhcip->uhci_td_pool_addr[i].flag; 366 if ((flag != TD_FLAG_FREE) && 367 (flag != TD_FLAG_DUMMY) && (td->tw != NULL)) { 368 tw = td->tw; 369 uhci_free_tw(uhcip, tw); 370 } 371 372 } 373 374 if (uhcip->uhci_dma_addr_bind_flag & UHCI_TD_POOL_BOUND) { 375 rval = ddi_dma_unbind_handle( 376 uhcip->uhci_td_pool_dma_handle); 377 ASSERT(rval == DDI_SUCCESS); 378 } 379 380 ddi_dma_mem_free(&uhcip->uhci_td_pool_mem_handle); 381 } 382 383 /* Free the TD pool */ 384 if (uhcip->uhci_td_pool_dma_handle) { 385 ddi_dma_free_handle(&uhcip->uhci_td_pool_dma_handle); 386 } 387 388 if (uhcip->uhci_qh_pool_addr && uhcip->uhci_qh_pool_mem_handle) { 389 if (uhcip->uhci_dma_addr_bind_flag & UHCI_QH_POOL_BOUND) { 390 rval = ddi_dma_unbind_handle( 391 uhcip->uhci_qh_pool_dma_handle); 392 ASSERT(rval == DDI_SUCCESS); 393 } 394 ddi_dma_mem_free(&uhcip->uhci_qh_pool_mem_handle); 395 } 396 397 /* Free the QH pool */ 398 if (uhcip->uhci_qh_pool_dma_handle) { 399 ddi_dma_free_handle(&uhcip->uhci_qh_pool_dma_handle); 400 } 401 402 /* Free the Frame list Table area */ 403 if (uhcip->uhci_frame_lst_tablep && uhcip->uhci_flt_mem_handle) { 404 if (uhcip->uhci_dma_addr_bind_flag & UHCI_FLA_POOL_BOUND) { 405 rval = ddi_dma_unbind_handle( 406 uhcip->uhci_flt_dma_handle); 407 ASSERT(rval == DDI_SUCCESS); 408 } 409 ddi_dma_mem_free(&uhcip->uhci_flt_mem_handle); 410 } 411 412 if (uhcip->uhci_flt_dma_handle) { 413 ddi_dma_free_handle(&uhcip->uhci_flt_dma_handle); 414 } 415 } 416 417 418 /* 419 * uhci_decode_ddi_dma_addr_bind_handle_result: 420 * Process the return values of ddi_dma_addr_bind_handle() 421 */ 422 void 423 uhci_decode_ddi_dma_addr_bind_handle_result(uhci_state_t *uhcip, int result) 424 { 425 char *msg; 426 427 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 428 "uhci_decode_ddi_dma_addr_bind_handle_result:"); 429 430 switch (result) { 431 case DDI_DMA_PARTIAL_MAP: 432 msg = "Partial transfers not allowed"; 433 break; 434 case DDI_DMA_INUSE: 435 msg = "Handle is in use"; 436 break; 437 case DDI_DMA_NORESOURCES: 438 msg = "No resources"; 439 break; 440 case DDI_DMA_NOMAPPING: 441 msg = "No mapping"; 442 break; 443 case DDI_DMA_TOOBIG: 444 msg = "Object is too big"; 445 break; 446 default: 447 msg = "Unknown dma error"; 448 } 449 450 USB_DPRINTF_L4(PRINT_MASK_ALL, uhcip->uhci_log_hdl, "%s", msg); 451 } 452 453 454 /* 455 * uhci_init_ctlr: 456 * Initialize the Host Controller (HC). 457 */ 458 int 459 uhci_init_ctlr(uhci_state_t *uhcip) 460 { 461 dev_info_t *dip = uhcip->uhci_dip; 462 uint_t cmd_reg; 463 uint_t frame_base_addr; 464 465 mutex_enter(&uhcip->uhci_int_mutex); 466 467 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, "uhci_init_ctlr:"); 468 469 /* 470 * When USB legacy mode is enabled, the BIOS manages the USB keyboard 471 * attached to the UHCI controller. It has been observed that some 472 * times the BIOS does not clear the interrupts in the legacy mode 473 * register in the PCI configuration space. So, disable the SMI intrs 474 * and route the intrs to PIRQD here. 475 */ 476 pci_config_put16(uhcip->uhci_config_handle, 477 LEGACYMODE_REG_OFFSET, LEGACYMODE_REG_INIT_VALUE); 478 479 /* 480 * Disable all the interrupts. 481 */ 482 Set_OpReg16(USBINTR, DISABLE_ALL_INTRS); 483 484 cmd_reg = Get_OpReg16(USBCMD); 485 cmd_reg &= (~USBCMD_REG_HC_RUN); 486 487 /* Stop the controller */ 488 Set_OpReg16(USBCMD, cmd_reg); 489 490 /* Reset the host controller */ 491 Set_OpReg16(USBCMD, USBCMD_REG_GBL_RESET); 492 493 /* Wait 10ms for reset to complete */ 494 mutex_exit(&uhcip->uhci_int_mutex); 495 delay(drv_usectohz(UHCI_RESET_DELAY)); 496 mutex_enter(&uhcip->uhci_int_mutex); 497 498 Set_OpReg16(USBCMD, 0); 499 500 /* Set the frame number to zero */ 501 Set_OpReg16(FRNUM, 0); 502 503 if (uhcip->uhci_hc_soft_state == UHCI_CTLR_INIT_STATE) { 504 /* Initialize the Frame list base address area */ 505 if (uhci_init_frame_lst_table(dip, uhcip) != USB_SUCCESS) { 506 mutex_exit(&uhcip->uhci_int_mutex); 507 508 return (USB_FAILURE); 509 } 510 } 511 512 /* Save the contents of the Frame Interval Registers */ 513 uhcip->uhci_frame_interval = Get_OpReg8(SOFMOD); 514 515 frame_base_addr = uhcip->uhci_flt_cookie.dmac_address; 516 517 /* Set the Frame list base address */ 518 Set_OpReg32(FRBASEADD, frame_base_addr); 519 520 /* 521 * Begin sending SOFs 522 * Set the Host Controller Functional State to Operational 523 */ 524 cmd_reg = Get_OpReg16(USBCMD); 525 cmd_reg |= (USBCMD_REG_HC_RUN | USBCMD_REG_MAXPKT_64 | 526 USBCMD_REG_CONFIG_FLAG); 527 528 Set_OpReg16(USBCMD, cmd_reg); 529 530 /* 531 * Verify the Command and interrupt enable registers, 532 * a sanity check whether actually initialized or not 533 */ 534 cmd_reg = Get_OpReg16(USBCMD); 535 536 if (!(cmd_reg & (USBCMD_REG_HC_RUN | USBCMD_REG_MAXPKT_64 | 537 USBCMD_REG_CONFIG_FLAG))) { 538 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 539 "uhci_init_ctlr: Controller initialization failed"); 540 mutex_exit(&uhcip->uhci_int_mutex); 541 542 return (USB_FAILURE); 543 } 544 545 /* 546 * Set the ioc bit of the isoc intr td. This enables 547 * the generation of an interrupt for every 1024 frames. 548 */ 549 SetTD_ioc(uhcip, uhcip->uhci_isoc_td, 1); 550 551 /* Set host controller soft state to operational */ 552 uhcip->uhci_hc_soft_state = UHCI_CTLR_OPERATIONAL_STATE; 553 mutex_exit(&uhcip->uhci_int_mutex); 554 555 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 556 "uhci_init_ctlr: Completed"); 557 558 return (USB_SUCCESS); 559 } 560 561 562 /* 563 * uhci_uninit_ctlr: 564 * uninitialize the Host Controller (HC). 565 */ 566 void 567 uhci_uninit_ctlr(uhci_state_t *uhcip) 568 { 569 if (uhcip->uhci_regs_handle) { 570 /* Disable all the interrupts. */ 571 Set_OpReg16(USBINTR, DISABLE_ALL_INTRS); 572 573 /* Complete the current transaction and then halt. */ 574 Set_OpReg16(USBCMD, 0); 575 576 /* Wait for sometime */ 577 mutex_exit(&uhcip->uhci_int_mutex); 578 delay(drv_usectohz(UHCI_TIMEWAIT)); 579 mutex_enter(&uhcip->uhci_int_mutex); 580 } 581 } 582 583 584 /* 585 * uhci_map_regs: 586 * The Host Controller (HC) contains a set of on-chip operational 587 * registers and which should be mapped into a non-cacheable 588 * portion of the system addressable space. 589 */ 590 int 591 uhci_map_regs(uhci_state_t *uhcip) 592 { 593 dev_info_t *dip = uhcip->uhci_dip; 594 int index; 595 uint32_t regs_prop_len; 596 int32_t *regs_list; 597 uint16_t command_reg; 598 ddi_device_acc_attr_t attr; 599 600 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, "uhci_map_regs:"); 601 602 /* The host controller will be little endian */ 603 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 604 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 605 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 606 607 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, uhcip->uhci_dip, 608 DDI_PROP_DONTPASS, "reg", ®s_list, ®s_prop_len) != 609 DDI_PROP_SUCCESS) { 610 611 return (USB_FAILURE); 612 } 613 614 for (index = 0; index * 5 < regs_prop_len; index++) { 615 if (regs_list[index * 5] & UHCI_PROP_MASK) { 616 break; 617 } 618 } 619 620 /* 621 * Deallocate the memory allocated by the ddi_prop_lookup_int_array 622 */ 623 ddi_prop_free(regs_list); 624 625 if (index * 5 >= regs_prop_len) { 626 627 return (USB_FAILURE); 628 } 629 630 /* Map in operational registers */ 631 if (ddi_regs_map_setup(dip, index, (caddr_t *)&uhcip->uhci_regsp, 632 0, sizeof (hc_regs_t), &attr, &uhcip->uhci_regs_handle) != 633 DDI_SUCCESS) { 634 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 635 "ddi_regs_map_setup: failed"); 636 637 return (USB_FAILURE); 638 } 639 640 if (pci_config_setup(dip, &uhcip->uhci_config_handle) != DDI_SUCCESS) { 641 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 642 "uhci_map_regs: Config error"); 643 644 return (USB_FAILURE); 645 } 646 647 /* Make sure Memory Access Enable and Master Enable are set */ 648 command_reg = pci_config_get16(uhcip->uhci_config_handle, 649 PCI_CONF_COMM); 650 if (!(command_reg & (PCI_COMM_MAE | PCI_COMM_ME))) { 651 USB_DPRINTF_L3(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 652 "uhci_map_regs: No MAE/ME"); 653 } 654 655 command_reg |= PCI_COMM_MAE | PCI_COMM_ME; 656 pci_config_put16(uhcip->uhci_config_handle, PCI_CONF_COMM, command_reg); 657 658 /* 659 * Check whether I/O base address is configured and enabled. 660 */ 661 if (!(command_reg & PCI_COMM_IO)) { 662 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 663 "I/O Base address access disabled"); 664 665 return (USB_FAILURE); 666 } 667 /* 668 * Get the IO base address of the controller 669 */ 670 uhcip->uhci_iobase = (pci_config_get16(uhcip->uhci_config_handle, 671 PCI_CONF_IOBASE) & PCI_CONF_IOBASE_MASK); 672 673 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 674 "uhci_map_regs: Completed"); 675 676 return (USB_SUCCESS); 677 } 678 679 680 void 681 uhci_unmap_regs(uhci_state_t *uhcip) 682 { 683 /* Unmap the UHCI registers */ 684 if (uhcip->uhci_regs_handle) { 685 /* Reset the host controller */ 686 Set_OpReg16(USBCMD, USBCMD_REG_GBL_RESET); 687 688 ddi_regs_map_free(&uhcip->uhci_regs_handle); 689 } 690 691 if (uhcip->uhci_config_handle) { 692 pci_config_teardown(&uhcip->uhci_config_handle); 693 } 694 } 695 696 697 /* 698 * uhci_set_dma_attributes: 699 * Set the limits in the DMA attributes structure. Most of the values used 700 * in the DMA limit structres are the default values as specified by the 701 * Writing PCI device drivers document. 702 */ 703 void 704 uhci_set_dma_attributes(uhci_state_t *uhcip) 705 { 706 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 707 "uhci_set_dma_attributes:"); 708 709 /* Initialize the DMA attributes */ 710 uhcip->uhci_dma_attr.dma_attr_version = DMA_ATTR_V0; 711 uhcip->uhci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 712 uhcip->uhci_dma_attr.dma_attr_addr_hi = 0xfffffff0ull; 713 714 /* 32 bit addressing */ 715 uhcip->uhci_dma_attr.dma_attr_count_max = 0xffffffull; 716 717 /* 718 * Setting the dam_att_align to 512, some times fails the 719 * binding handle. I dont know why ? But setting to 16 will 720 * be right for our case (16 byte alignment required per 721 * UHCI spec for TD descriptors). 722 */ 723 724 /* 16 byte alignment */ 725 uhcip->uhci_dma_attr.dma_attr_align = 0x10; 726 727 /* 728 * Since PCI specification is byte alignment, the 729 * burstsize field should be set to 1 for PCI devices. 730 */ 731 uhcip->uhci_dma_attr.dma_attr_burstsizes = 0x1; 732 733 uhcip->uhci_dma_attr.dma_attr_minxfer = 0x1; 734 uhcip->uhci_dma_attr.dma_attr_maxxfer = 0xffffffull; 735 uhcip->uhci_dma_attr.dma_attr_seg = 0xffffffffull; 736 uhcip->uhci_dma_attr.dma_attr_sgllen = 1; 737 uhcip->uhci_dma_attr.dma_attr_granular = 1; 738 uhcip->uhci_dma_attr.dma_attr_flags = 0; 739 } 740 741 742 uint_t 743 pow_2(uint_t x) 744 { 745 return ((x == 0) ? 1 : (1 << x)); 746 } 747 748 749 uint_t 750 log_2(uint_t x) 751 { 752 int ret_val = 0; 753 754 while (x != 1) { 755 ret_val++; 756 x = x >> 1; 757 } 758 759 return (ret_val); 760 } 761 762 763 /* 764 * uhci_obtain_state: 765 */ 766 uhci_state_t * 767 uhci_obtain_state(dev_info_t *dip) 768 { 769 int instance = ddi_get_instance(dip); 770 uhci_state_t *state = ddi_get_soft_state(uhci_statep, instance); 771 772 ASSERT(state != NULL); 773 774 return (state); 775 } 776 777 778 /* 779 * uhci_alloc_hcdi_ops: 780 * The HCDI interfaces or entry points are the software interfaces used by 781 * the Universal Serial Bus Driver (USBA) to access the services of the 782 * Host Controller Driver (HCD). During HCD initialization, inform USBA 783 * about all available HCDI interfaces or entry points. 784 */ 785 usba_hcdi_ops_t * 786 uhci_alloc_hcdi_ops(uhci_state_t *uhcip) 787 { 788 usba_hcdi_ops_t *hcdi_ops; 789 790 USB_DPRINTF_L4(PRINT_MASK_HCDI, uhcip->uhci_log_hdl, 791 "uhci_alloc_hcdi_ops:"); 792 793 hcdi_ops = usba_alloc_hcdi_ops(); 794 795 hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION_1; 796 797 hcdi_ops->usba_hcdi_pipe_open = uhci_hcdi_pipe_open; 798 hcdi_ops->usba_hcdi_pipe_close = uhci_hcdi_pipe_close; 799 hcdi_ops->usba_hcdi_pipe_reset = uhci_hcdi_pipe_reset; 800 801 hcdi_ops->usba_hcdi_pipe_ctrl_xfer = uhci_hcdi_pipe_ctrl_xfer; 802 hcdi_ops->usba_hcdi_pipe_bulk_xfer = uhci_hcdi_pipe_bulk_xfer; 803 hcdi_ops->usba_hcdi_pipe_intr_xfer = uhci_hcdi_pipe_intr_xfer; 804 hcdi_ops->usba_hcdi_pipe_isoc_xfer = uhci_hcdi_pipe_isoc_xfer; 805 806 hcdi_ops->usba_hcdi_bulk_transfer_size = uhci_hcdi_bulk_transfer_size; 807 hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 808 uhci_hcdi_pipe_stop_intr_polling; 809 hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 810 uhci_hcdi_pipe_stop_isoc_polling; 811 812 hcdi_ops->usba_hcdi_get_current_frame_number = 813 uhci_hcdi_get_current_frame_number; 814 hcdi_ops->usba_hcdi_get_max_isoc_pkts = uhci_hcdi_get_max_isoc_pkts; 815 816 hcdi_ops->usba_hcdi_console_input_init = uhci_hcdi_polled_input_init; 817 hcdi_ops->usba_hcdi_console_input_enter = uhci_hcdi_polled_input_enter; 818 hcdi_ops->usba_hcdi_console_read = uhci_hcdi_polled_read; 819 hcdi_ops->usba_hcdi_console_input_exit = uhci_hcdi_polled_input_exit; 820 hcdi_ops->usba_hcdi_console_input_fini = uhci_hcdi_polled_input_fini; 821 822 hcdi_ops->usba_hcdi_console_output_init = uhci_hcdi_polled_output_init; 823 hcdi_ops->usba_hcdi_console_output_enter = 824 uhci_hcdi_polled_output_enter; 825 hcdi_ops->usba_hcdi_console_write = uhci_hcdi_polled_write; 826 hcdi_ops->usba_hcdi_console_output_exit = uhci_hcdi_polled_output_exit; 827 hcdi_ops->usba_hcdi_console_output_fini = uhci_hcdi_polled_output_fini; 828 829 return (hcdi_ops); 830 } 831 832 833 /* 834 * uhci_init_frame_lst_table : 835 * Allocate the system memory and initialize Host Controller 836 * Frame list table area The starting of the Frame list Table 837 * area must be 4096 byte aligned. 838 */ 839 static int 840 uhci_init_frame_lst_table(dev_info_t *dip, uhci_state_t *uhcip) 841 { 842 int result; 843 uint_t ccount; 844 size_t real_length; 845 ddi_device_acc_attr_t dev_attr; 846 847 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 848 849 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 850 "uhci_init_frame_lst_table:"); 851 852 /* The host controller will be little endian */ 853 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 854 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 855 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 856 857 /* 4K alignment required */ 858 uhcip->uhci_dma_attr.dma_attr_align = 0x1000; 859 860 /* Create space for the HCCA block */ 861 if (ddi_dma_alloc_handle(dip, &uhcip->uhci_dma_attr, DDI_DMA_SLEEP, 862 0, &uhcip->uhci_flt_dma_handle) != DDI_SUCCESS) { 863 864 return (USB_FAILURE); 865 } 866 867 /* Reset to default 16 bytes */ 868 uhcip->uhci_dma_attr.dma_attr_align = 0x10; 869 870 if (ddi_dma_mem_alloc(uhcip->uhci_flt_dma_handle, 871 SIZE_OF_FRAME_LST_TABLE, &dev_attr, DDI_DMA_CONSISTENT, 872 DDI_DMA_SLEEP, 0, (caddr_t *)&uhcip->uhci_frame_lst_tablep, 873 &real_length, &uhcip->uhci_flt_mem_handle)) { 874 875 return (USB_FAILURE); 876 } 877 878 /* Map the whole Frame list base area into the I/O address space */ 879 result = ddi_dma_addr_bind_handle(uhcip->uhci_flt_dma_handle, 880 NULL, (caddr_t)uhcip->uhci_frame_lst_tablep, real_length, 881 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 882 &uhcip->uhci_flt_cookie, &ccount); 883 884 if (result == DDI_DMA_MAPPED) { 885 /* The cookie count should be 1 */ 886 if (ccount != 1) { 887 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 888 "uhci_init_frame_list_table: More than 1 cookie"); 889 890 return (USB_FAILURE); 891 } 892 } else { 893 uhci_decode_ddi_dma_addr_bind_handle_result(uhcip, result); 894 895 return (USB_FAILURE); 896 } 897 898 uhcip->uhci_dma_addr_bind_flag |= UHCI_FLA_POOL_BOUND; 899 900 bzero((void *)uhcip->uhci_frame_lst_tablep, real_length); 901 902 /* Initialize the interrupt lists */ 903 uhci_build_interrupt_lattice(uhcip); 904 905 return (USB_SUCCESS); 906 } 907 908 909 /* 910 * uhci_alloc_queue_head: 911 * Allocate a queue head 912 */ 913 queue_head_t * 914 uhci_alloc_queue_head(uhci_state_t *uhcip) 915 { 916 int index; 917 uhci_td_t *dummy_td; 918 queue_head_t *queue_head; 919 920 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 921 "uhci_alloc_queue_head"); 922 923 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 924 925 /* Allocate a dummy td first. */ 926 if ((dummy_td = uhci_allocate_td_from_pool(uhcip)) == NULL) { 927 928 USB_DPRINTF_L2(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 929 "uhci_alloc_queue_head: allocate td from pool failed"); 930 931 return (NULL); 932 } 933 934 /* 935 * The first 63 queue heads in the Queue Head (QH) 936 * buffer pool are reserved for building interrupt lattice 937 * tree. Search for a blank Queue head in the QH buffer pool. 938 */ 939 for (index = NUM_STATIC_NODES; index < uhci_qh_pool_size; index++) { 940 if (uhcip->uhci_qh_pool_addr[index].qh_flag == 941 QUEUE_HEAD_FLAG_FREE) { 942 break; 943 } 944 } 945 946 USB_DPRINTF_L3(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 947 "uhci_alloc_queue_head: Allocated %d", index); 948 949 if (index == uhci_qh_pool_size) { 950 USB_DPRINTF_L2(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 951 "uhci_alloc_queue_head: All QH exhausted"); 952 953 /* Free the dummy td allocated for this qh. */ 954 dummy_td->flag = TD_FLAG_FREE; 955 956 return (NULL); 957 } 958 959 queue_head = &uhcip->uhci_qh_pool_addr[index]; 960 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 961 "uhci_alloc_queue_head: Allocated address 0x%p", queue_head); 962 963 bzero((void *)queue_head, sizeof (queue_head_t)); 964 SetQH32(uhcip, queue_head->link_ptr, HC_END_OF_LIST); 965 SetQH32(uhcip, queue_head->element_ptr, HC_END_OF_LIST); 966 queue_head->prev_qh = NULL; 967 queue_head->qh_flag = QUEUE_HEAD_FLAG_BUSY; 968 969 bzero((char *)dummy_td, sizeof (uhci_td_t)); 970 queue_head->td_tailp = dummy_td; 971 SetQH32(uhcip, queue_head->element_ptr, TD_PADDR(dummy_td)); 972 973 return (queue_head); 974 } 975 976 977 /* 978 * uhci_allocate_bandwidth: 979 * Figure out whether or not this interval may be supported. Return 980 * the index into the lattice if it can be supported. Return 981 * allocation failure if it can not be supported. 982 */ 983 int 984 uhci_allocate_bandwidth( 985 uhci_state_t *uhcip, 986 usba_pipe_handle_data_t *pipe_handle, 987 uint_t *node) 988 { 989 int bandwidth; /* Requested bandwidth */ 990 uint_t min, min_index; 991 uint_t i; 992 uint_t height; /* Bandwidth's height in the tree */ 993 uint_t leftmost; 994 uint_t length; 995 uint32_t paddr; 996 queue_head_t *tmp_qh; 997 usb_ep_descr_t *endpoint = &pipe_handle->p_ep; 998 999 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 1000 1001 /* 1002 * Calculate the length in bytes of a transaction on this 1003 * periodic endpoint. 1004 */ 1005 mutex_enter(&pipe_handle->p_usba_device->usb_mutex); 1006 1007 length = uhci_compute_total_bandwidth(endpoint, 1008 pipe_handle->p_usba_device->usb_port_status); 1009 mutex_exit(&pipe_handle->p_usba_device->usb_mutex); 1010 1011 /* 1012 * If the length in bytes plus the allocated bandwidth exceeds 1013 * the maximum, return bandwidth allocation failure. 1014 */ 1015 if ((length + uhcip->uhci_bandwidth_intr_min + 1016 uhcip->uhci_bandwidth_isoch_sum) > (MAX_PERIODIC_BANDWIDTH)) { 1017 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1018 "uhci_allocate_bandwidth: " 1019 "Reached maximum bandwidth value and cannot allocate " 1020 "bandwidth for a given Interrupt/Isoch endpoint"); 1021 1022 return (USB_NO_BANDWIDTH); 1023 } 1024 1025 /* 1026 * ISOC xfers are not supported at this point type 1027 */ 1028 if (UHCI_XFER_TYPE(endpoint) == USB_EP_ATTR_ISOCH) { 1029 uhcip->uhci_bandwidth_isoch_sum += length; 1030 1031 return (USB_SUCCESS); 1032 } 1033 1034 /* 1035 * This is an interrupt endpoint. 1036 * Adjust bandwidth to be a power of 2 1037 */ 1038 mutex_enter(&pipe_handle->p_usba_device->usb_mutex); 1039 bandwidth = uhci_bandwidth_adjust(uhcip, endpoint, 1040 pipe_handle->p_usba_device->usb_port_status); 1041 mutex_exit(&pipe_handle->p_usba_device->usb_mutex); 1042 1043 /* 1044 * If this bandwidth can't be supported, 1045 * return allocation failure. 1046 */ 1047 if (bandwidth == USB_FAILURE) { 1048 1049 return (USB_FAILURE); 1050 } 1051 1052 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl, 1053 "The new bandwidth is %d", bandwidth); 1054 1055 /* Find the leaf with the smallest allocated bandwidth */ 1056 min_index = 0; 1057 min = uhcip->uhci_bandwidth[0]; 1058 1059 for (i = 1; i < NUM_FRAME_LST_ENTRIES; i++) { 1060 if (uhcip->uhci_bandwidth[i] < min) { 1061 min_index = i; 1062 min = uhcip->uhci_bandwidth[i]; 1063 } 1064 } 1065 1066 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl, 1067 "The leaf with minimal bandwidth %d, " 1068 "The smallest bandwidth %d", min_index, min); 1069 1070 /* 1071 * Find the index into the lattice given the 1072 * leaf with the smallest allocated bandwidth. 1073 */ 1074 height = uhci_lattice_height(bandwidth); 1075 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl, 1076 "The height is %d", height); 1077 1078 *node = uhci_tree_bottom_nodes[min_index]; 1079 1080 /* check if there are isocs TDs scheduled for this frame */ 1081 if (uhcip->uhci_isoc_q_tailp[*node]) { 1082 paddr = (uhcip->uhci_isoc_q_tailp[*node]->link_ptr & 1083 FRAME_LST_PTR_MASK); 1084 } else { 1085 paddr = (uhcip->uhci_frame_lst_tablep[*node] & 1086 FRAME_LST_PTR_MASK); 1087 } 1088 1089 tmp_qh = QH_VADDR(paddr); 1090 *node = tmp_qh->node; 1091 for (i = 0; i < height; i++) { 1092 *node = uhci_lattice_parent(*node); 1093 } 1094 1095 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl, 1096 "The real node is %d", *node); 1097 1098 /* 1099 * Find the leftmost leaf in the subtree specified by the node. 1100 */ 1101 leftmost = uhci_leftmost_leaf(*node, height); 1102 USB_DPRINTF_L3(PRINT_MASK_BW, uhcip->uhci_log_hdl, 1103 "Leftmost %d", leftmost); 1104 1105 for (i = leftmost; i < leftmost + 1106 (NUM_FRAME_LST_ENTRIES/bandwidth); i ++) { 1107 1108 if ((length + uhcip->uhci_bandwidth_isoch_sum + 1109 uhcip->uhci_bandwidth[i]) > MAX_PERIODIC_BANDWIDTH) { 1110 1111 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1112 "uhci_allocate_bandwidth: " 1113 "Reached maximum bandwidth value and cannot " 1114 "allocate bandwidth for Interrupt endpoint"); 1115 1116 return (USB_NO_BANDWIDTH); 1117 } 1118 } 1119 1120 /* 1121 * All the leaves for this node must be updated with the bandwidth. 1122 */ 1123 for (i = leftmost; i < leftmost + 1124 (NUM_FRAME_LST_ENTRIES/bandwidth); i ++) { 1125 uhcip->uhci_bandwidth[i] += length; 1126 } 1127 1128 /* Find the leaf with the smallest allocated bandwidth */ 1129 min_index = 0; 1130 min = uhcip->uhci_bandwidth[0]; 1131 1132 for (i = 1; i < NUM_FRAME_LST_ENTRIES; i++) { 1133 if (uhcip->uhci_bandwidth[i] < min) { 1134 min_index = i; 1135 min = uhcip->uhci_bandwidth[i]; 1136 } 1137 } 1138 1139 /* Save the minimum for later use */ 1140 uhcip->uhci_bandwidth_intr_min = min; 1141 1142 return (USB_SUCCESS); 1143 } 1144 1145 1146 /* 1147 * uhci_deallocate_bandwidth: 1148 * Deallocate bandwidth for the given node in the lattice 1149 * and the length of transfer. 1150 */ 1151 void 1152 uhci_deallocate_bandwidth(uhci_state_t *uhcip, 1153 usba_pipe_handle_data_t *pipe_handle) 1154 { 1155 uint_t bandwidth; 1156 uint_t height; 1157 uint_t leftmost; 1158 uint_t i; 1159 uint_t min; 1160 usb_ep_descr_t *endpoint = &pipe_handle->p_ep; 1161 uint_t node, length; 1162 uhci_pipe_private_t *pp = 1163 (uhci_pipe_private_t *)pipe_handle->p_hcd_private; 1164 1165 /* This routine is protected by the uhci_int_mutex */ 1166 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 1167 1168 /* Obtain the length */ 1169 mutex_enter(&pipe_handle->p_usba_device->usb_mutex); 1170 length = uhci_compute_total_bandwidth(endpoint, 1171 pipe_handle->p_usba_device->usb_port_status); 1172 mutex_exit(&pipe_handle->p_usba_device->usb_mutex); 1173 1174 /* 1175 * If this is an isochronous endpoint, just delete endpoint's 1176 * bandwidth from the total allocated isochronous bandwidth. 1177 */ 1178 if (UHCI_XFER_TYPE(endpoint) == USB_EP_ATTR_ISOCH) { 1179 uhcip->uhci_bandwidth_isoch_sum -= length; 1180 1181 return; 1182 } 1183 1184 /* Obtain the node */ 1185 node = pp->pp_node; 1186 1187 /* Adjust bandwidth to be a power of 2 */ 1188 mutex_enter(&pipe_handle->p_usba_device->usb_mutex); 1189 bandwidth = uhci_bandwidth_adjust(uhcip, endpoint, 1190 pipe_handle->p_usba_device->usb_port_status); 1191 mutex_exit(&pipe_handle->p_usba_device->usb_mutex); 1192 1193 /* Find the height in the tree */ 1194 height = uhci_lattice_height(bandwidth); 1195 1196 /* 1197 * Find the leftmost leaf in the subtree specified by the node 1198 */ 1199 leftmost = uhci_leftmost_leaf(node, height); 1200 1201 /* Delete the bandwith from the appropriate lists */ 1202 for (i = leftmost; i < leftmost + (NUM_FRAME_LST_ENTRIES/bandwidth); 1203 i ++) { 1204 uhcip->uhci_bandwidth[i] -= length; 1205 } 1206 1207 min = uhcip->uhci_bandwidth[0]; 1208 1209 /* Recompute the minimum */ 1210 for (i = 1; i < NUM_FRAME_LST_ENTRIES; i++) { 1211 if (uhcip->uhci_bandwidth[i] < min) { 1212 min = uhcip->uhci_bandwidth[i]; 1213 } 1214 } 1215 1216 /* Save the minimum for later use */ 1217 uhcip->uhci_bandwidth_intr_min = min; 1218 } 1219 1220 1221 /* 1222 * uhci_compute_total_bandwidth: 1223 * 1224 * Given a periodic endpoint (interrupt or isochronous) determine the total 1225 * bandwidth for one transaction. The UHCI host controller traverses the 1226 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 1227 * services an endpoint, only a single transaction attempt is made. The HC 1228 * moves to the next Endpoint Descriptor after the first transaction attempt 1229 * rather than finishing the entire Transfer Descriptor. Therefore, when a 1230 * Transfer Descriptor is inserted into the lattice, we will only count the 1231 * number of bytes for one transaction. 1232 * 1233 * The following are the formulas used for calculating bandwidth in terms 1234 * bytes and it is for the single USB full speed and low speed transaction 1235 * respectively. The protocol overheads will be different for each of type 1236 * of USB transfer and all these formulas & protocol overheads are derived 1237 * from the 5.9.3 section of USB Specification & with the help of Bandwidth 1238 * Analysis white paper which is posted on the USB developer forum. 1239 * 1240 * Full-Speed: 1241 * Protocol overhead + ((MaxPacketSize * 7)/6 ) + Host_Delay 1242 * 1243 * Low-Speed: 1244 * Protocol overhead + Hub LS overhead + 1245 * (Low-Speed clock * ((MaxPacketSize * 7)/6 )) + Host_Delay 1246 */ 1247 static uint_t 1248 uhci_compute_total_bandwidth(usb_ep_descr_t *endpoint, 1249 usb_port_status_t port_status) 1250 { 1251 uint_t bandwidth; 1252 ushort_t MaxPacketSize = endpoint->wMaxPacketSize; 1253 1254 /* Add Host Controller specific delay to required bandwidth */ 1255 bandwidth = HOST_CONTROLLER_DELAY; 1256 1257 /* Add bit-stuffing overhead */ 1258 MaxPacketSize = (ushort_t)((MaxPacketSize * 7) / 6); 1259 1260 /* Low Speed interrupt transaction */ 1261 if (port_status == USBA_LOW_SPEED_DEV) { 1262 /* Low Speed interrupt transaction */ 1263 bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 1264 HUB_LOW_SPEED_PROTO_OVERHEAD + 1265 (LOW_SPEED_CLOCK * MaxPacketSize)); 1266 } else { 1267 /* Full Speed transaction */ 1268 bandwidth += MaxPacketSize; 1269 1270 if (UHCI_XFER_TYPE(endpoint) == USB_EP_ATTR_INTR) { 1271 /* Full Speed interrupt transaction */ 1272 bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 1273 } else { 1274 /* Isochronus and input transaction */ 1275 if (UHCI_XFER_DIR(endpoint) == USB_EP_DIR_IN) { 1276 bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 1277 } else { 1278 /* Isochronus and output transaction */ 1279 bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 1280 } 1281 } 1282 } 1283 1284 return (bandwidth); 1285 } 1286 1287 1288 /* 1289 * uhci_bandwidth_adjust: 1290 */ 1291 static int 1292 uhci_bandwidth_adjust( 1293 uhci_state_t *uhcip, 1294 usb_ep_descr_t *endpoint, 1295 usb_port_status_t port_status) 1296 { 1297 int i = 0; 1298 uint_t interval; 1299 1300 /* 1301 * Get the polling interval from the endpoint descriptor 1302 */ 1303 interval = endpoint->bInterval; 1304 1305 /* 1306 * The bInterval value in the endpoint descriptor can range 1307 * from 1 to 255ms. The interrupt lattice has 32 leaf nodes, 1308 * and the host controller cycles through these nodes every 1309 * 32ms. The longest polling interval that the controller 1310 * supports is 32ms. 1311 */ 1312 1313 /* 1314 * Return an error if the polling interval is less than 1ms 1315 * and greater than 255ms 1316 */ 1317 if ((interval < MIN_POLL_INTERVAL) || (interval > MAX_POLL_INTERVAL)) { 1318 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1319 "uhci_bandwidth_adjust: Endpoint's poll interval must be " 1320 "between %d and %d ms", MIN_POLL_INTERVAL, 1321 MAX_POLL_INTERVAL); 1322 1323 return (USB_FAILURE); 1324 } 1325 1326 /* 1327 * According USB Specifications, a full-speed endpoint can 1328 * specify a desired polling interval 1ms to 255ms and a low 1329 * speed endpoints are limited to specifying only 10ms to 1330 * 255ms. But some old keyboards & mice uses polling interval 1331 * of 8ms. For compatibility purpose, we are using polling 1332 * interval between 8ms & 255ms for low speed endpoints. 1333 */ 1334 if ((port_status == USBA_LOW_SPEED_DEV) && 1335 (interval < MIN_LOW_SPEED_POLL_INTERVAL)) { 1336 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1337 "uhci_bandwidth_adjust: Low speed endpoint's poll interval " 1338 "must be >= %d ms, adjusted", 1339 MIN_LOW_SPEED_POLL_INTERVAL); 1340 1341 interval = MIN_LOW_SPEED_POLL_INTERVAL; 1342 } 1343 1344 /* 1345 * If polling interval is greater than 32ms, 1346 * adjust polling interval equal to 32ms. 1347 */ 1348 if (interval > 32) { 1349 interval = 32; 1350 } 1351 1352 /* 1353 * Find the nearest power of 2 that's less 1354 * than interval. 1355 */ 1356 while ((pow_2(i)) <= interval) { 1357 i++; 1358 } 1359 1360 return (pow_2((i - 1))); 1361 } 1362 1363 1364 /* 1365 * uhci_lattice_height: 1366 * Given the requested bandwidth, find the height in the tree at 1367 * which the nodes for this bandwidth fall. The height is measured 1368 * as the number of nodes from the leaf to the level specified by 1369 * bandwidth The root of the tree is at height TREE_HEIGHT. 1370 */ 1371 static uint_t 1372 uhci_lattice_height(uint_t bandwidth) 1373 { 1374 return (TREE_HEIGHT - (log_2(bandwidth))); 1375 } 1376 1377 1378 static uint_t 1379 uhci_lattice_parent(uint_t node) 1380 { 1381 return (((node % 2) == 0) ? ((node/2) - 1) : (node/2)); 1382 } 1383 1384 1385 /* 1386 * uhci_leftmost_leaf: 1387 * Find the leftmost leaf in the subtree specified by the node. 1388 * Height refers to number of nodes from the bottom of the tree 1389 * to the node, including the node. 1390 */ 1391 static uint_t 1392 uhci_leftmost_leaf(uint_t node, uint_t height) 1393 { 1394 node = pow_2(height + VIRTUAL_TREE_HEIGHT) * (node+1) - 1395 NUM_FRAME_LST_ENTRIES; 1396 return (node); 1397 } 1398 1399 1400 /* 1401 * uhci_insert_qh: 1402 * Add the Queue Head (QH) into the Host Controller's (HC) 1403 * appropriate queue head list. 1404 */ 1405 void 1406 uhci_insert_qh(uhci_state_t *uhcip, usba_pipe_handle_data_t *ph) 1407 { 1408 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private; 1409 1410 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1411 "uhci_insert_qh:"); 1412 1413 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 1414 1415 switch (UHCI_XFER_TYPE(&ph->p_ep)) { 1416 case USB_EP_ATTR_CONTROL: 1417 uhci_insert_ctrl_qh(uhcip, pp); 1418 break; 1419 case USB_EP_ATTR_BULK: 1420 uhci_insert_bulk_qh(uhcip, pp); 1421 break; 1422 case USB_EP_ATTR_INTR: 1423 uhci_insert_intr_qh(uhcip, pp); 1424 break; 1425 case USB_EP_ATTR_ISOCH: 1426 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 1427 "uhci_insert_qh: Illegal request"); 1428 break; 1429 } 1430 } 1431 1432 1433 /* 1434 * uhci_insert_ctrl_qh: 1435 * Insert a control QH into the Host Controller's (HC) control QH list. 1436 */ 1437 static void 1438 uhci_insert_ctrl_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp) 1439 { 1440 queue_head_t *qh = pp->pp_qh; 1441 1442 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1443 "uhci_insert_ctrl_qh:"); 1444 1445 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 1446 1447 if (uhcip->uhci_ctrl_xfers_q_head == uhcip->uhci_ctrl_xfers_q_tail) { 1448 uhcip->uhci_ctrl_xfers_q_head->prev_qh = UHCI_INVALID_PTR; 1449 } 1450 1451 SetQH32(uhcip, qh->link_ptr, 1452 GetQH32(uhcip, uhcip->uhci_ctrl_xfers_q_tail->link_ptr)); 1453 qh->prev_qh = uhcip->uhci_ctrl_xfers_q_tail; 1454 SetQH32(uhcip, uhcip->uhci_ctrl_xfers_q_tail->link_ptr, 1455 QH_PADDR(qh) | HC_QUEUE_HEAD); 1456 uhcip->uhci_ctrl_xfers_q_tail = qh; 1457 1458 } 1459 1460 1461 /* 1462 * uhci_insert_bulk_qh: 1463 * Insert a bulk QH into the Host Controller's (HC) bulk QH list. 1464 */ 1465 static void 1466 uhci_insert_bulk_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp) 1467 { 1468 queue_head_t *qh = pp->pp_qh; 1469 1470 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1471 "uhci_insert_bulk_qh:"); 1472 1473 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 1474 1475 if (uhcip->uhci_bulk_xfers_q_head == uhcip->uhci_bulk_xfers_q_tail) { 1476 uhcip->uhci_bulk_xfers_q_head->prev_qh = UHCI_INVALID_PTR; 1477 } else if (uhcip->uhci_bulk_xfers_q_head->link_ptr == 1478 uhcip->uhci_bulk_xfers_q_tail->link_ptr) { 1479 1480 /* If there is already a loop, we should keep the loop. */ 1481 qh->link_ptr = uhcip->uhci_bulk_xfers_q_tail->link_ptr; 1482 } 1483 1484 qh->prev_qh = uhcip->uhci_bulk_xfers_q_tail; 1485 SetQH32(uhcip, uhcip->uhci_bulk_xfers_q_tail->link_ptr, 1486 QH_PADDR(qh) | HC_QUEUE_HEAD); 1487 uhcip->uhci_bulk_xfers_q_tail = qh; 1488 } 1489 1490 1491 /* 1492 * uhci_insert_intr_qh: 1493 * Insert a periodic Queue head i.e Interrupt queue head into the 1494 * Host Controller's (HC) interrupt lattice tree. 1495 */ 1496 static void 1497 uhci_insert_intr_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp) 1498 { 1499 uint_t node = pp->pp_node; /* The appropriate node was */ 1500 /* found during the opening */ 1501 /* of the pipe. */ 1502 queue_head_t *qh = pp->pp_qh; 1503 queue_head_t *next_lattice_qh, *lattice_qh; 1504 1505 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1506 "uhci_insert_intr_qh:"); 1507 1508 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 1509 1510 /* Find the lattice queue head */ 1511 lattice_qh = &uhcip->uhci_qh_pool_addr[node]; 1512 next_lattice_qh = 1513 QH_VADDR(GetQH32(uhcip, lattice_qh->link_ptr) & QH_LINK_PTR_MASK); 1514 1515 next_lattice_qh->prev_qh = qh; 1516 qh->link_ptr = lattice_qh->link_ptr; 1517 qh->prev_qh = lattice_qh; 1518 SetQH32(uhcip, lattice_qh->link_ptr, QH_PADDR(qh) | HC_QUEUE_HEAD); 1519 pp->pp_data_toggle = 0; 1520 } 1521 1522 1523 /* 1524 * uhci_insert_intr_td: 1525 * Create a TD and a data buffer for an interrupt endpoint. 1526 */ 1527 int 1528 uhci_insert_intr_td( 1529 uhci_state_t *uhcip, 1530 usba_pipe_handle_data_t *ph, 1531 usb_intr_req_t *req, 1532 usb_flags_t flags) 1533 { 1534 int error, pipe_dir; 1535 uint_t length, mps; 1536 uint32_t buf_offs; 1537 uhci_td_t *tmp_td; 1538 usb_intr_req_t *intr_reqp; 1539 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private; 1540 uhci_trans_wrapper_t *tw; 1541 1542 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1543 "uhci_insert_intr_td: req: 0x%p", req); 1544 1545 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 1546 1547 /* Get the interrupt pipe direction */ 1548 pipe_dir = UHCI_XFER_DIR(&ph->p_ep); 1549 1550 /* Get the current interrupt request pointer */ 1551 if (req) { 1552 length = req->intr_len; 1553 } else { 1554 ASSERT(pipe_dir == USB_EP_DIR_IN); 1555 length = (pp->pp_client_periodic_in_reqp) ? 1556 (((usb_intr_req_t *)pp-> 1557 pp_client_periodic_in_reqp)->intr_len) : 1558 ph->p_ep.wMaxPacketSize; 1559 } 1560 1561 /* Check the size of interrupt request */ 1562 if (length > UHCI_MAX_TD_XFER_SIZE) { 1563 1564 /* the length shouldn't exceed 8K */ 1565 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1566 "uhci_insert_intr_td: Intr request size 0x%lx is " 1567 "more than 0x%x", length, UHCI_MAX_TD_XFER_SIZE); 1568 1569 return (USB_INVALID_REQUEST); 1570 } 1571 1572 USB_DPRINTF_L3(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1573 "uhci_insert_intr_td: length: 0x%lx", length); 1574 1575 /* Allocate a transaction wrapper */ 1576 if ((tw = uhci_create_transfer_wrapper(uhcip, pp, length, flags)) == 1577 NULL) { 1578 1579 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1580 "uhci_insert_intr_td: TW allocation failed"); 1581 1582 return (USB_NO_RESOURCES); 1583 } 1584 1585 /* 1586 * Initialize the callback and any callback 1587 * data for when the td completes. 1588 */ 1589 tw->tw_handle_td = uhci_handle_intr_td; 1590 tw->tw_handle_callback_value = NULL; 1591 tw->tw_direction = (pipe_dir == USB_EP_DIR_OUT) ? 1592 PID_OUT : PID_IN; 1593 tw->tw_curr_xfer_reqp = (usb_opaque_t)req; 1594 1595 /* 1596 * If it is an Interrupt IN request and interrupt request is NULL, 1597 * allocate the usb interrupt request structure for the current 1598 * interrupt polling request. 1599 */ 1600 if (tw->tw_direction == PID_IN) { 1601 if ((error = uhci_allocate_periodic_in_resource(uhcip, 1602 pp, tw, flags)) != USB_SUCCESS) { 1603 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1604 "uhci_insert_intr_td: Interrupt request structure " 1605 "allocation failed"); 1606 1607 /* free the transfer wrapper */ 1608 uhci_deallocate_tw(uhcip, pp, tw); 1609 1610 return (error); 1611 } 1612 } 1613 1614 intr_reqp = (usb_intr_req_t *)tw->tw_curr_xfer_reqp; 1615 ASSERT(tw->tw_curr_xfer_reqp != NULL); 1616 1617 tw->tw_timeout_cnt = (intr_reqp->intr_attributes & USB_ATTRS_ONE_XFER) ? 1618 intr_reqp->intr_timeout : 0; 1619 1620 /* DATA IN */ 1621 if (tw->tw_direction == PID_IN) { 1622 /* Insert the td onto the queue head */ 1623 error = uhci_insert_hc_td(uhcip, 0, 1624 length, pp, tw, PID_IN, intr_reqp->intr_attributes); 1625 1626 if (error != USB_SUCCESS) { 1627 1628 uhci_deallocate_periodic_in_resource(uhcip, pp, tw); 1629 /* free the transfer wrapper */ 1630 uhci_deallocate_tw(uhcip, pp, tw); 1631 1632 return (USB_NO_RESOURCES); 1633 } 1634 tw->tw_bytes_xfered = 0; 1635 1636 return (USB_SUCCESS); 1637 } 1638 1639 if (req->intr_len) { 1640 /* DATA OUT */ 1641 ASSERT(req->intr_data != NULL); 1642 1643 /* Copy the data into the message */ 1644 ddi_rep_put8(tw->tw_accesshandle, req->intr_data->b_rptr, 1645 (uint8_t *)tw->tw_buf, req->intr_len, DDI_DEV_AUTOINCR); 1646 } 1647 1648 /* set tw->tw_claim flag, so that nobody else works on this tw. */ 1649 tw->tw_claim = UHCI_INTR_HDLR_CLAIMED; 1650 1651 mps = ph->p_ep.wMaxPacketSize; 1652 buf_offs = 0; 1653 1654 /* Insert tds onto the queue head */ 1655 while (length > 0) { 1656 1657 error = uhci_insert_hc_td(uhcip, buf_offs, 1658 (length > mps) ? mps : length, 1659 pp, tw, PID_OUT, 1660 intr_reqp->intr_attributes); 1661 1662 if (error != USB_SUCCESS) { 1663 /* no resource. */ 1664 break; 1665 } 1666 1667 if (length <= mps) { 1668 /* inserted all data. */ 1669 length = 0; 1670 1671 } else { 1672 1673 buf_offs += mps; 1674 length -= mps; 1675 } 1676 } 1677 1678 if (error != USB_SUCCESS) { 1679 1680 USB_DPRINTF_L2(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 1681 "uhci_insert_intr_td: allocate td failed, free resource"); 1682 1683 /* remove all the tds */ 1684 while (tw->tw_hctd_head != NULL) { 1685 uhci_delete_td(uhcip, tw->tw_hctd_head); 1686 } 1687 1688 tw->tw_claim = UHCI_NOT_CLAIMED; 1689 uhci_deallocate_tw(uhcip, pp, tw); 1690 1691 return (error); 1692 } 1693 1694 /* allow HC to xfer the tds of this tw */ 1695 tmp_td = tw->tw_hctd_head; 1696 while (tmp_td != NULL) { 1697 1698 SetTD_status(uhcip, tmp_td, UHCI_TD_ACTIVE); 1699 tmp_td = tmp_td->tw_td_next; 1700 } 1701 1702 tw->tw_bytes_xfered = 0; 1703 tw->tw_claim = UHCI_NOT_CLAIMED; 1704 1705 return (error); 1706 } 1707 1708 1709 /* 1710 * uhci_create_transfer_wrapper: 1711 * Create a Transaction Wrapper (TW) for non-isoc transfer types. 1712 * This involves the allocating of DMA resources. 1713 * 1714 * For non-isoc transfers, one DMA handle and one DMA buffer are 1715 * allocated per transfer. The DMA buffer may contain multiple 1716 * DMA cookies and the cookies should meet certain alignment 1717 * requirement to be able to fit in the multiple TDs. The alignment 1718 * needs to ensure: 1719 * 1. the size of a cookie be larger than max TD length (0x500) 1720 * 2. the size of a cookie be a multiple of wMaxPacketSize of the 1721 * ctrl/bulk pipes 1722 * 1723 * wMaxPacketSize for ctrl and bulk pipes may be 8, 16, 32 or 64 bytes. 1724 * So the alignment should be a multiple of 64. wMaxPacketSize for intr 1725 * pipes is a little different since it only specifies the max to be 1726 * 64 bytes, but as long as an intr transfer is limited to max TD length, 1727 * any alignment can work if the cookie size is larger than max TD length. 1728 * 1729 * Considering the above conditions, 2K alignment is used. 4K alignment 1730 * should also be fine. 1731 */ 1732 static uhci_trans_wrapper_t * 1733 uhci_create_transfer_wrapper( 1734 uhci_state_t *uhcip, 1735 uhci_pipe_private_t *pp, 1736 size_t length, 1737 usb_flags_t usb_flags) 1738 { 1739 size_t real_length; 1740 uhci_trans_wrapper_t *tw; 1741 ddi_device_acc_attr_t dev_attr; 1742 ddi_dma_attr_t dma_attr; 1743 int kmem_flag; 1744 int (*dmamem_wait)(caddr_t); 1745 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 1746 1747 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1748 "uhci_create_transfer_wrapper: length = 0x%lx flags = 0x%x", 1749 length, usb_flags); 1750 1751 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 1752 1753 /* isochronous pipe should not call into this function */ 1754 if (UHCI_XFER_TYPE(&ph->p_ep) == USB_EP_ATTR_ISOCH) { 1755 1756 return (NULL); 1757 } 1758 1759 /* SLEEP flag should not be used in interrupt context */ 1760 if (servicing_interrupt()) { 1761 kmem_flag = KM_NOSLEEP; 1762 dmamem_wait = DDI_DMA_DONTWAIT; 1763 } else { 1764 kmem_flag = KM_SLEEP; 1765 dmamem_wait = DDI_DMA_SLEEP; 1766 } 1767 1768 /* Allocate space for the transfer wrapper */ 1769 if ((tw = kmem_zalloc(sizeof (uhci_trans_wrapper_t), kmem_flag)) == 1770 NULL) { 1771 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1772 "uhci_create_transfer_wrapper: kmem_alloc failed"); 1773 1774 return (NULL); 1775 } 1776 1777 /* zero-length packet doesn't need to allocate dma memory */ 1778 if (length == 0) { 1779 1780 goto dmadone; 1781 } 1782 1783 /* allow sg lists for transfer wrapper dma memory */ 1784 bcopy(&uhcip->uhci_dma_attr, &dma_attr, sizeof (ddi_dma_attr_t)); 1785 dma_attr.dma_attr_sgllen = UHCI_DMA_ATTR_SGLLEN; 1786 dma_attr.dma_attr_align = UHCI_DMA_ATTR_ALIGN; 1787 1788 /* Store the transfer length */ 1789 tw->tw_length = length; 1790 1791 /* Allocate the DMA handle */ 1792 if (ddi_dma_alloc_handle(uhcip->uhci_dip, &dma_attr, dmamem_wait, 1793 0, &tw->tw_dmahandle) != DDI_SUCCESS) { 1794 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1795 "uhci_create_transfer_wrapper: Alloc handle failed"); 1796 kmem_free(tw, sizeof (uhci_trans_wrapper_t)); 1797 1798 return (NULL); 1799 } 1800 1801 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1802 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1803 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1804 1805 /* Allocate the memory */ 1806 if (ddi_dma_mem_alloc(tw->tw_dmahandle, tw->tw_length, &dev_attr, 1807 DDI_DMA_CONSISTENT, dmamem_wait, NULL, (caddr_t *)&tw->tw_buf, 1808 &real_length, &tw->tw_accesshandle) != DDI_SUCCESS) { 1809 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1810 "uhci_create_transfer_wrapper: dma_mem_alloc fail"); 1811 ddi_dma_free_handle(&tw->tw_dmahandle); 1812 kmem_free(tw, sizeof (uhci_trans_wrapper_t)); 1813 1814 return (NULL); 1815 } 1816 1817 ASSERT(real_length >= length); 1818 1819 /* Bind the handle */ 1820 if (ddi_dma_addr_bind_handle(tw->tw_dmahandle, NULL, 1821 (caddr_t)tw->tw_buf, real_length, DDI_DMA_RDWR|DDI_DMA_CONSISTENT, 1822 dmamem_wait, NULL, &tw->tw_cookie, &tw->tw_ncookies) != 1823 DDI_DMA_MAPPED) { 1824 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1825 "uhci_create_transfer_wrapper: Bind handle failed"); 1826 ddi_dma_mem_free(&tw->tw_accesshandle); 1827 ddi_dma_free_handle(&tw->tw_dmahandle); 1828 kmem_free(tw, sizeof (uhci_trans_wrapper_t)); 1829 1830 return (NULL); 1831 } 1832 1833 tw->tw_cookie_idx = 0; 1834 tw->tw_dma_offs = 0; 1835 1836 dmadone: 1837 /* 1838 * Only allow one wrapper to be added at a time. Insert the 1839 * new transaction wrapper into the list for this pipe. 1840 */ 1841 if (pp->pp_tw_head == NULL) { 1842 pp->pp_tw_head = tw; 1843 pp->pp_tw_tail = tw; 1844 } else { 1845 pp->pp_tw_tail->tw_next = tw; 1846 pp->pp_tw_tail = tw; 1847 ASSERT(tw->tw_next == NULL); 1848 } 1849 1850 /* Store a back pointer to the pipe private structure */ 1851 tw->tw_pipe_private = pp; 1852 1853 /* Store the transfer type - synchronous or asynchronous */ 1854 tw->tw_flags = usb_flags; 1855 1856 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 1857 "uhci_create_transfer_wrapper: tw = 0x%p, ncookies = %u", 1858 tw, tw->tw_ncookies); 1859 1860 return (tw); 1861 } 1862 1863 1864 /* 1865 * uhci_insert_hc_td: 1866 * Insert a Transfer Descriptor (TD) on an QH. 1867 */ 1868 int 1869 uhci_insert_hc_td( 1870 uhci_state_t *uhcip, 1871 uint32_t buffer_offset, 1872 size_t hcgtd_length, 1873 uhci_pipe_private_t *pp, 1874 uhci_trans_wrapper_t *tw, 1875 uchar_t PID, 1876 usb_req_attrs_t attrs) 1877 { 1878 uhci_td_t *td, *current_dummy; 1879 queue_head_t *qh = pp->pp_qh; 1880 1881 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 1882 1883 if ((td = uhci_allocate_td_from_pool(uhcip)) == NULL) { 1884 1885 return (USB_NO_RESOURCES); 1886 } 1887 1888 current_dummy = qh->td_tailp; 1889 1890 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 1891 "uhci_insert_hc_td: td %p, attrs = 0x%x", td, attrs); 1892 1893 /* 1894 * Fill in the current dummy td and 1895 * add the new dummy to the end. 1896 */ 1897 uhci_fill_in_td(uhcip, td, current_dummy, buffer_offset, 1898 hcgtd_length, pp, PID, attrs, tw); 1899 1900 /* 1901 * Allow HC hardware xfer the td, except interrupt out td. 1902 */ 1903 if ((tw->tw_handle_td != uhci_handle_intr_td) || (PID != PID_OUT)) { 1904 1905 SetTD_status(uhcip, current_dummy, UHCI_TD_ACTIVE); 1906 } 1907 1908 /* Insert this td onto the tw */ 1909 1910 if (tw->tw_hctd_head == NULL) { 1911 ASSERT(tw->tw_hctd_tail == NULL); 1912 tw->tw_hctd_head = current_dummy; 1913 tw->tw_hctd_tail = current_dummy; 1914 } else { 1915 /* Add the td to the end of the list */ 1916 tw->tw_hctd_tail->tw_td_next = current_dummy; 1917 tw->tw_hctd_tail = current_dummy; 1918 } 1919 1920 /* 1921 * Insert the TD on to the QH. When this occurs, 1922 * the Host Controller will see the newly filled in TD 1923 */ 1924 current_dummy->outst_td_next = NULL; 1925 current_dummy->outst_td_prev = uhcip->uhci_outst_tds_tail; 1926 if (uhcip->uhci_outst_tds_head == NULL) { 1927 uhcip->uhci_outst_tds_head = current_dummy; 1928 } else { 1929 uhcip->uhci_outst_tds_tail->outst_td_next = current_dummy; 1930 } 1931 uhcip->uhci_outst_tds_tail = current_dummy; 1932 current_dummy->tw = tw; 1933 1934 return (USB_SUCCESS); 1935 } 1936 1937 1938 /* 1939 * uhci_fill_in_td: 1940 * Fill in the fields of a Transfer Descriptor (TD). 1941 */ 1942 static void 1943 uhci_fill_in_td( 1944 uhci_state_t *uhcip, 1945 uhci_td_t *td, 1946 uhci_td_t *current_dummy, 1947 uint32_t buffer_offset, 1948 size_t length, 1949 uhci_pipe_private_t *pp, 1950 uchar_t PID, 1951 usb_req_attrs_t attrs, 1952 uhci_trans_wrapper_t *tw) 1953 { 1954 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 1955 uint32_t buf_addr; 1956 1957 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 1958 "uhci_fill_in_td: td 0x%p buf_offs 0x%x len 0x%lx " 1959 "attrs 0x%x", td, buffer_offset, length, attrs); 1960 1961 /* 1962 * If this is an isochronous TD, just return 1963 */ 1964 if (UHCI_XFER_TYPE(&ph->p_ep) == USB_EP_ATTR_ISOCH) { 1965 1966 return; 1967 } 1968 1969 /* The maximum transfer length of UHCI cannot exceed 0x500 bytes */ 1970 ASSERT(length <= UHCI_MAX_TD_XFER_SIZE); 1971 1972 bzero((char *)td, sizeof (uhci_td_t)); /* Clear the TD */ 1973 SetTD32(uhcip, current_dummy->link_ptr, TD_PADDR(td)); 1974 1975 if (attrs & USB_ATTRS_SHORT_XFER_OK) { 1976 SetTD_spd(uhcip, current_dummy, 1); 1977 } 1978 1979 mutex_enter(&ph->p_usba_device->usb_mutex); 1980 if (ph->p_usba_device->usb_port_status == USBA_LOW_SPEED_DEV) { 1981 SetTD_ls(uhcip, current_dummy, LOW_SPEED_DEVICE); 1982 } 1983 1984 SetTD_c_err(uhcip, current_dummy, UHCI_MAX_ERR_COUNT); 1985 SetTD_mlen(uhcip, current_dummy, 1986 (length == 0) ? ZERO_LENGTH : (length - 1)); 1987 SetTD_dtogg(uhcip, current_dummy, pp->pp_data_toggle); 1988 1989 /* Adjust the data toggle bit */ 1990 ADJ_DATA_TOGGLE(pp); 1991 1992 SetTD_devaddr(uhcip, current_dummy, ph->p_usba_device->usb_addr); 1993 SetTD_endpt(uhcip, current_dummy, 1994 ph->p_ep.bEndpointAddress & END_POINT_ADDRESS_MASK); 1995 SetTD_PID(uhcip, current_dummy, PID); 1996 SetTD_ioc(uhcip, current_dummy, INTERRUPT_ON_COMPLETION); 1997 1998 buf_addr = uhci_get_tw_paddr_by_offs(uhcip, buffer_offset, length, tw); 1999 SetTD32(uhcip, current_dummy->buffer_address, buf_addr); 2000 2001 td->qh_td_prev = current_dummy; 2002 current_dummy->qh_td_prev = NULL; 2003 pp->pp_qh->td_tailp = td; 2004 mutex_exit(&ph->p_usba_device->usb_mutex); 2005 } 2006 2007 /* 2008 * uhci_get_tw_paddr_by_offs: 2009 * Walk through the DMA cookies of a TW buffer to retrieve 2010 * the device address used for a TD. 2011 * 2012 * buffer_offset - the starting offset into the TW buffer, where the 2013 * TD should transfer from. When a TW has more than 2014 * one TD, the TDs must be filled in increasing order. 2015 */ 2016 static uint32_t 2017 uhci_get_tw_paddr_by_offs( 2018 uhci_state_t *uhcip, 2019 uint32_t buffer_offset, 2020 size_t length, 2021 uhci_trans_wrapper_t *tw) 2022 { 2023 uint32_t buf_addr; 2024 int rem_len; 2025 2026 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 2027 "uhci_get_tw_paddr_by_offs: buf_offs 0x%x len 0x%lx", 2028 buffer_offset, length); 2029 2030 /* 2031 * TDs must be filled in increasing DMA offset order. 2032 * tw_dma_offs is initialized to be 0 at TW creation and 2033 * is only increased in this function. 2034 */ 2035 ASSERT(length == 0 || buffer_offset >= tw->tw_dma_offs); 2036 2037 if (length == 0) { 2038 buf_addr = 0; 2039 2040 return (buf_addr); 2041 } 2042 2043 /* 2044 * Advance to the next DMA cookie until finding the cookie 2045 * that buffer_offset falls in. 2046 * It is very likely this loop will never repeat more than 2047 * once. It is here just to accommodate the case buffer_offset 2048 * is increased by multiple cookies during two consecutive 2049 * calls into this function. In that case, the interim DMA 2050 * buffer is allowed to be skipped. 2051 */ 2052 while ((tw->tw_dma_offs + tw->tw_cookie.dmac_size) <= 2053 buffer_offset) { 2054 /* 2055 * tw_dma_offs always points to the starting offset 2056 * of a cookie 2057 */ 2058 tw->tw_dma_offs += tw->tw_cookie.dmac_size; 2059 ddi_dma_nextcookie(tw->tw_dmahandle, &tw->tw_cookie); 2060 tw->tw_cookie_idx++; 2061 ASSERT(tw->tw_cookie_idx < tw->tw_ncookies); 2062 } 2063 2064 /* 2065 * Counting the remained buffer length to be filled in 2066 * the TDs for current DMA cookie 2067 */ 2068 rem_len = (tw->tw_dma_offs + tw->tw_cookie.dmac_size) - 2069 buffer_offset; 2070 2071 /* Calculate the beginning address of the buffer */ 2072 ASSERT(length <= rem_len); 2073 buf_addr = (buffer_offset - tw->tw_dma_offs) + 2074 tw->tw_cookie.dmac_address; 2075 2076 USB_DPRINTF_L3(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 2077 "uhci_get_tw_paddr_by_offs: dmac_addr 0x%p dmac_size " 2078 "0x%lx idx %d", buf_addr, tw->tw_cookie.dmac_size, 2079 tw->tw_cookie_idx); 2080 2081 return (buf_addr); 2082 } 2083 2084 2085 /* 2086 * uhci_modify_td_active_bits: 2087 * Sets active bit in all the tds of QH to INACTIVE so that 2088 * the HC stops processing the TD's related to the QH. 2089 */ 2090 void 2091 uhci_modify_td_active_bits( 2092 uhci_state_t *uhcip, 2093 uhci_pipe_private_t *pp) 2094 { 2095 uhci_td_t *td_head; 2096 usb_ep_descr_t *ept = &pp->pp_pipe_handle->p_ep; 2097 uhci_trans_wrapper_t *tw_head = pp->pp_tw_head; 2098 2099 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 2100 "uhci_modify_td_active_bits: tw head %p", (void *)tw_head); 2101 2102 while (tw_head != NULL) { 2103 tw_head->tw_claim = UHCI_MODIFY_TD_BITS_CLAIMED; 2104 td_head = tw_head->tw_hctd_head; 2105 2106 while (td_head) { 2107 if (UHCI_XFER_TYPE(ept) == USB_EP_ATTR_ISOCH) { 2108 SetTD_status(uhcip, td_head, 2109 GetTD_status(uhcip, td_head) & TD_INACTIVE); 2110 } else { 2111 SetTD32(uhcip, td_head->link_ptr, 2112 GetTD32(uhcip, td_head->link_ptr) | 2113 HC_END_OF_LIST); 2114 } 2115 2116 td_head = td_head->tw_td_next; 2117 } 2118 tw_head = tw_head->tw_next; 2119 } 2120 } 2121 2122 2123 /* 2124 * uhci_insert_ctrl_td: 2125 * Create a TD and a data buffer for a control Queue Head. 2126 */ 2127 int 2128 uhci_insert_ctrl_td( 2129 uhci_state_t *uhcip, 2130 usba_pipe_handle_data_t *ph, 2131 usb_ctrl_req_t *ctrl_reqp, 2132 usb_flags_t flags) 2133 { 2134 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private; 2135 uhci_trans_wrapper_t *tw; 2136 size_t ctrl_buf_size; 2137 2138 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 2139 "uhci_insert_ctrl_td: timeout: 0x%x", ctrl_reqp->ctrl_timeout); 2140 2141 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 2142 2143 /* 2144 * If we have a control data phase, make the data buffer start 2145 * on the next 64-byte boundary so as to ensure the DMA cookie 2146 * can fit in the multiple TDs. The buffer in the range of 2147 * [SETUP_SIZE, UHCI_CTRL_EPT_MAX_SIZE) is just for padding 2148 * and not to be transferred. 2149 */ 2150 if (ctrl_reqp->ctrl_wLength) { 2151 ctrl_buf_size = UHCI_CTRL_EPT_MAX_SIZE + 2152 ctrl_reqp->ctrl_wLength; 2153 } else { 2154 ctrl_buf_size = SETUP_SIZE; 2155 } 2156 2157 /* Allocate a transaction wrapper */ 2158 if ((tw = uhci_create_transfer_wrapper(uhcip, pp, 2159 ctrl_buf_size, flags)) == NULL) { 2160 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 2161 "uhci_insert_ctrl_td: TW allocation failed"); 2162 2163 return (USB_NO_RESOURCES); 2164 } 2165 2166 pp->pp_data_toggle = 0; 2167 2168 tw->tw_curr_xfer_reqp = (usb_opaque_t)ctrl_reqp; 2169 tw->tw_bytes_xfered = 0; 2170 tw->tw_bytes_pending = ctrl_reqp->ctrl_wLength; 2171 tw->tw_timeout_cnt = max(UHCI_CTRL_TIMEOUT, ctrl_reqp->ctrl_timeout); 2172 2173 /* 2174 * Initialize the callback and any callback 2175 * data for when the td completes. 2176 */ 2177 tw->tw_handle_td = uhci_handle_ctrl_td; 2178 tw->tw_handle_callback_value = NULL; 2179 2180 if ((uhci_create_setup_pkt(uhcip, pp, tw)) != USB_SUCCESS) { 2181 tw->tw_ctrl_state = 0; 2182 2183 /* free the transfer wrapper */ 2184 uhci_deallocate_tw(uhcip, pp, tw); 2185 2186 return (USB_NO_RESOURCES); 2187 } 2188 2189 tw->tw_ctrl_state = SETUP; 2190 2191 return (USB_SUCCESS); 2192 } 2193 2194 2195 /* 2196 * uhci_create_setup_pkt: 2197 * create a setup packet to initiate a control transfer. 2198 * 2199 * OHCI driver has seen the case where devices fail if there is 2200 * more than one control transfer to the device within a frame. 2201 * So, the UHCI ensures that only one TD will be put on the control 2202 * pipe to one device (to be consistent with OHCI driver). 2203 */ 2204 static int 2205 uhci_create_setup_pkt( 2206 uhci_state_t *uhcip, 2207 uhci_pipe_private_t *pp, 2208 uhci_trans_wrapper_t *tw) 2209 { 2210 int sdata; 2211 usb_ctrl_req_t *req = (usb_ctrl_req_t *)tw->tw_curr_xfer_reqp; 2212 2213 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 2214 "uhci_create_setup_pkt: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%p", 2215 req->ctrl_bmRequestType, req->ctrl_bRequest, req->ctrl_wValue, 2216 req->ctrl_wIndex, req->ctrl_wLength, (void *)req->ctrl_data); 2217 2218 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 2219 ASSERT(tw != NULL); 2220 2221 /* Create the first four bytes of the setup packet */ 2222 sdata = (req->ctrl_bmRequestType | (req->ctrl_bRequest << 8) | 2223 (req->ctrl_wValue << 16)); 2224 ddi_put32(tw->tw_accesshandle, (uint_t *)tw->tw_buf, sdata); 2225 2226 /* Create the second four bytes */ 2227 sdata = (uint32_t)(req->ctrl_wIndex | (req->ctrl_wLength << 16)); 2228 ddi_put32(tw->tw_accesshandle, 2229 (uint_t *)(tw->tw_buf + sizeof (uint_t)), sdata); 2230 2231 /* 2232 * The TD's are placed on the QH one at a time. 2233 * Once this TD is placed on the done list, the 2234 * data or status phase TD will be enqueued. 2235 */ 2236 if ((uhci_insert_hc_td(uhcip, 0, SETUP_SIZE, 2237 pp, tw, PID_SETUP, req->ctrl_attributes)) != USB_SUCCESS) { 2238 2239 return (USB_NO_RESOURCES); 2240 } 2241 2242 USB_DPRINTF_L3(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 2243 "Create_setup: pp = 0x%p, attrs = 0x%x", pp, req->ctrl_attributes); 2244 2245 /* 2246 * If this control transfer has a data phase, record the 2247 * direction. If the data phase is an OUT transaction , 2248 * copy the data into the buffer of the transfer wrapper. 2249 */ 2250 if (req->ctrl_wLength != 0) { 2251 /* There is a data stage. Find the direction */ 2252 if (req->ctrl_bmRequestType & USB_DEV_REQ_DEV_TO_HOST) { 2253 tw->tw_direction = PID_IN; 2254 } else { 2255 tw->tw_direction = PID_OUT; 2256 2257 /* Copy the data into the buffer */ 2258 ddi_rep_put8(tw->tw_accesshandle, 2259 req->ctrl_data->b_rptr, 2260 (uint8_t *)(tw->tw_buf + UHCI_CTRL_EPT_MAX_SIZE), 2261 req->ctrl_wLength, 2262 DDI_DEV_AUTOINCR); 2263 } 2264 } 2265 2266 return (USB_SUCCESS); 2267 } 2268 2269 2270 /* 2271 * uhci_create_stats: 2272 * Allocate and initialize the uhci kstat structures 2273 */ 2274 void 2275 uhci_create_stats(uhci_state_t *uhcip) 2276 { 2277 int i; 2278 char kstatname[KSTAT_STRLEN]; 2279 char *usbtypes[USB_N_COUNT_KSTATS] = 2280 {"ctrl", "isoch", "bulk", "intr"}; 2281 uint_t instance = uhcip->uhci_instance; 2282 const char *dname = ddi_driver_name(uhcip->uhci_dip); 2283 uhci_intrs_stats_t *isp; 2284 2285 if (UHCI_INTRS_STATS(uhcip) == NULL) { 2286 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 2287 dname, instance); 2288 UHCI_INTRS_STATS(uhcip) = kstat_create("usba", instance, 2289 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 2290 sizeof (uhci_intrs_stats_t) / sizeof (kstat_named_t), 2291 KSTAT_FLAG_PERSISTENT); 2292 2293 if (UHCI_INTRS_STATS(uhcip) != NULL) { 2294 isp = UHCI_INTRS_STATS_DATA(uhcip); 2295 kstat_named_init(&isp->uhci_intrs_hc_halted, 2296 "HC Halted", KSTAT_DATA_UINT64); 2297 kstat_named_init(&isp->uhci_intrs_hc_process_err, 2298 "HC Process Errors", KSTAT_DATA_UINT64); 2299 kstat_named_init(&isp->uhci_intrs_host_sys_err, 2300 "Host Sys Errors", KSTAT_DATA_UINT64); 2301 kstat_named_init(&isp->uhci_intrs_resume_detected, 2302 "Resume Detected", KSTAT_DATA_UINT64); 2303 kstat_named_init(&isp->uhci_intrs_usb_err_intr, 2304 "USB Error", KSTAT_DATA_UINT64); 2305 kstat_named_init(&isp->uhci_intrs_usb_intr, 2306 "USB Interrupts", KSTAT_DATA_UINT64); 2307 kstat_named_init(&isp->uhci_intrs_total, 2308 "Total Interrupts", KSTAT_DATA_UINT64); 2309 kstat_named_init(&isp->uhci_intrs_not_claimed, 2310 "Not Claimed", KSTAT_DATA_UINT64); 2311 2312 UHCI_INTRS_STATS(uhcip)->ks_private = uhcip; 2313 UHCI_INTRS_STATS(uhcip)->ks_update = nulldev; 2314 kstat_install(UHCI_INTRS_STATS(uhcip)); 2315 } 2316 } 2317 2318 if (UHCI_TOTAL_STATS(uhcip) == NULL) { 2319 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 2320 dname, instance); 2321 UHCI_TOTAL_STATS(uhcip) = kstat_create("usba", instance, 2322 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 2323 KSTAT_FLAG_PERSISTENT); 2324 2325 if (UHCI_TOTAL_STATS(uhcip) != NULL) { 2326 kstat_install(UHCI_TOTAL_STATS(uhcip)); 2327 } 2328 } 2329 2330 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 2331 if (uhcip->uhci_count_stats[i] == NULL) { 2332 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 2333 dname, instance, usbtypes[i]); 2334 uhcip->uhci_count_stats[i] = kstat_create("usba", 2335 instance, kstatname, "usb_byte_count", 2336 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 2337 2338 if (uhcip->uhci_count_stats[i] != NULL) { 2339 kstat_install(uhcip->uhci_count_stats[i]); 2340 } 2341 } 2342 } 2343 } 2344 2345 2346 /* 2347 * uhci_destroy_stats: 2348 * Clean up uhci kstat structures 2349 */ 2350 void 2351 uhci_destroy_stats(uhci_state_t *uhcip) 2352 { 2353 int i; 2354 2355 if (UHCI_INTRS_STATS(uhcip)) { 2356 kstat_delete(UHCI_INTRS_STATS(uhcip)); 2357 UHCI_INTRS_STATS(uhcip) = NULL; 2358 } 2359 2360 if (UHCI_TOTAL_STATS(uhcip)) { 2361 kstat_delete(UHCI_TOTAL_STATS(uhcip)); 2362 UHCI_TOTAL_STATS(uhcip) = NULL; 2363 } 2364 2365 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 2366 if (uhcip->uhci_count_stats[i]) { 2367 kstat_delete(uhcip->uhci_count_stats[i]); 2368 uhcip->uhci_count_stats[i] = NULL; 2369 } 2370 } 2371 } 2372 2373 2374 void 2375 uhci_do_intrs_stats(uhci_state_t *uhcip, int val) 2376 { 2377 if (UHCI_INTRS_STATS(uhcip) == NULL) { 2378 2379 return; 2380 } 2381 2382 UHCI_INTRS_STATS_DATA(uhcip)->uhci_intrs_total.value.ui64++; 2383 switch (val) { 2384 case USBSTS_REG_HC_HALTED: 2385 UHCI_INTRS_STATS_DATA(uhcip)->uhci_intrs_hc_halted.value.ui64++; 2386 break; 2387 case USBSTS_REG_HC_PROCESS_ERR: 2388 UHCI_INTRS_STATS_DATA(uhcip)-> 2389 uhci_intrs_hc_process_err.value.ui64++; 2390 break; 2391 case USBSTS_REG_HOST_SYS_ERR: 2392 UHCI_INTRS_STATS_DATA(uhcip)-> 2393 uhci_intrs_host_sys_err.value.ui64++; 2394 break; 2395 case USBSTS_REG_RESUME_DETECT: 2396 UHCI_INTRS_STATS_DATA(uhcip)-> 2397 uhci_intrs_resume_detected.value.ui64++; 2398 break; 2399 case USBSTS_REG_USB_ERR_INTR: 2400 UHCI_INTRS_STATS_DATA(uhcip)-> 2401 uhci_intrs_usb_err_intr.value.ui64++; 2402 break; 2403 case USBSTS_REG_USB_INTR: 2404 UHCI_INTRS_STATS_DATA(uhcip)->uhci_intrs_usb_intr.value.ui64++; 2405 break; 2406 default: 2407 UHCI_INTRS_STATS_DATA(uhcip)-> 2408 uhci_intrs_not_claimed.value.ui64++; 2409 break; 2410 } 2411 } 2412 2413 2414 void 2415 uhci_do_byte_stats(uhci_state_t *uhcip, size_t len, uint8_t attr, uint8_t addr) 2416 { 2417 uint8_t type = attr & USB_EP_ATTR_MASK; 2418 uint8_t dir = addr & USB_EP_DIR_MASK; 2419 2420 switch (dir) { 2421 case USB_EP_DIR_IN: 2422 UHCI_TOTAL_STATS_DATA(uhcip)->reads++; 2423 UHCI_TOTAL_STATS_DATA(uhcip)->nread += len; 2424 switch (type) { 2425 case USB_EP_ATTR_CONTROL: 2426 UHCI_CTRL_STATS(uhcip)->reads++; 2427 UHCI_CTRL_STATS(uhcip)->nread += len; 2428 break; 2429 case USB_EP_ATTR_BULK: 2430 UHCI_BULK_STATS(uhcip)->reads++; 2431 UHCI_BULK_STATS(uhcip)->nread += len; 2432 break; 2433 case USB_EP_ATTR_INTR: 2434 UHCI_INTR_STATS(uhcip)->reads++; 2435 UHCI_INTR_STATS(uhcip)->nread += len; 2436 break; 2437 case USB_EP_ATTR_ISOCH: 2438 UHCI_ISOC_STATS(uhcip)->reads++; 2439 UHCI_ISOC_STATS(uhcip)->nread += len; 2440 break; 2441 } 2442 break; 2443 case USB_EP_DIR_OUT: 2444 UHCI_TOTAL_STATS_DATA(uhcip)->writes++; 2445 UHCI_TOTAL_STATS_DATA(uhcip)->nwritten += len; 2446 switch (type) { 2447 case USB_EP_ATTR_CONTROL: 2448 UHCI_CTRL_STATS(uhcip)->writes++; 2449 UHCI_CTRL_STATS(uhcip)->nwritten += len; 2450 break; 2451 case USB_EP_ATTR_BULK: 2452 UHCI_BULK_STATS(uhcip)->writes++; 2453 UHCI_BULK_STATS(uhcip)->nwritten += len; 2454 break; 2455 case USB_EP_ATTR_INTR: 2456 UHCI_INTR_STATS(uhcip)->writes++; 2457 UHCI_INTR_STATS(uhcip)->nwritten += len; 2458 break; 2459 case USB_EP_ATTR_ISOCH: 2460 UHCI_ISOC_STATS(uhcip)->writes++; 2461 UHCI_ISOC_STATS(uhcip)->nwritten += len; 2462 break; 2463 } 2464 break; 2465 } 2466 } 2467 2468 2469 /* 2470 * uhci_free_tw: 2471 * Free the Transfer Wrapper (TW). 2472 */ 2473 void 2474 uhci_free_tw(uhci_state_t *uhcip, uhci_trans_wrapper_t *tw) 2475 { 2476 int rval, i; 2477 2478 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, "uhci_free_tw:"); 2479 2480 ASSERT(tw != NULL); 2481 2482 if (tw->tw_isoc_strtlen > 0) { 2483 ASSERT(tw->tw_isoc_bufs != NULL); 2484 for (i = 0; i < tw->tw_ncookies; i++) { 2485 rval = ddi_dma_unbind_handle( 2486 tw->tw_isoc_bufs[i].dma_handle); 2487 ASSERT(rval == USB_SUCCESS); 2488 ddi_dma_mem_free(&tw->tw_isoc_bufs[i].mem_handle); 2489 ddi_dma_free_handle(&tw->tw_isoc_bufs[i].dma_handle); 2490 } 2491 kmem_free(tw->tw_isoc_bufs, tw->tw_isoc_strtlen); 2492 } else if (tw->tw_dmahandle != NULL) { 2493 rval = ddi_dma_unbind_handle(tw->tw_dmahandle); 2494 ASSERT(rval == DDI_SUCCESS); 2495 2496 ddi_dma_mem_free(&tw->tw_accesshandle); 2497 ddi_dma_free_handle(&tw->tw_dmahandle); 2498 } 2499 2500 kmem_free(tw, sizeof (uhci_trans_wrapper_t)); 2501 } 2502 2503 2504 /* 2505 * uhci_deallocate_tw: 2506 * Deallocate of a Transaction Wrapper (TW) and this involves 2507 * the freeing of DMA resources. 2508 */ 2509 void 2510 uhci_deallocate_tw(uhci_state_t *uhcip, 2511 uhci_pipe_private_t *pp, uhci_trans_wrapper_t *tw) 2512 { 2513 uhci_trans_wrapper_t *head; 2514 2515 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 2516 "uhci_deallocate_tw:"); 2517 2518 /* 2519 * If the transfer wrapper has no Host Controller (HC) 2520 * Transfer Descriptors (TD) associated with it, then 2521 * remove the transfer wrapper. The transfers are done 2522 * in FIFO order, so this should be the first transfer 2523 * wrapper on the list. 2524 */ 2525 if (tw->tw_hctd_head != NULL) { 2526 ASSERT(tw->tw_hctd_tail != NULL); 2527 2528 return; 2529 } 2530 2531 ASSERT(tw->tw_hctd_tail == NULL); 2532 ASSERT(pp->pp_tw_head != NULL); 2533 2534 /* 2535 * If pp->pp_tw_head is NULL, set the tail also to NULL. 2536 */ 2537 head = pp->pp_tw_head; 2538 2539 if (head == tw) { 2540 pp->pp_tw_head = head->tw_next; 2541 if (pp->pp_tw_head == NULL) { 2542 pp->pp_tw_tail = NULL; 2543 } 2544 } else { 2545 while (head->tw_next != tw) 2546 head = head->tw_next; 2547 head->tw_next = tw->tw_next; 2548 if (tw->tw_next == NULL) { 2549 pp->pp_tw_tail = head; 2550 } 2551 } 2552 uhci_free_tw(uhcip, tw); 2553 } 2554 2555 2556 void 2557 uhci_delete_td(uhci_state_t *uhcip, uhci_td_t *td) 2558 { 2559 uhci_td_t *tmp_td; 2560 uhci_trans_wrapper_t *tw = td->tw; 2561 2562 if ((td->outst_td_next == NULL) && (td->outst_td_prev == NULL)) { 2563 uhcip->uhci_outst_tds_head = NULL; 2564 uhcip->uhci_outst_tds_tail = NULL; 2565 } else if (td->outst_td_next == NULL) { 2566 td->outst_td_prev->outst_td_next = NULL; 2567 uhcip->uhci_outst_tds_tail = td->outst_td_prev; 2568 } else if (td->outst_td_prev == NULL) { 2569 td->outst_td_next->outst_td_prev = NULL; 2570 uhcip->uhci_outst_tds_head = td->outst_td_next; 2571 } else { 2572 td->outst_td_prev->outst_td_next = td->outst_td_next; 2573 td->outst_td_next->outst_td_prev = td->outst_td_prev; 2574 } 2575 2576 tmp_td = tw->tw_hctd_head; 2577 2578 if (tmp_td != td) { 2579 while (tmp_td->tw_td_next != td) { 2580 tmp_td = tmp_td->tw_td_next; 2581 } 2582 ASSERT(tmp_td); 2583 tmp_td->tw_td_next = td->tw_td_next; 2584 if (td->tw_td_next == NULL) { 2585 tw->tw_hctd_tail = tmp_td; 2586 } 2587 } else { 2588 tw->tw_hctd_head = tw->tw_hctd_head->tw_td_next; 2589 if (tw->tw_hctd_head == NULL) { 2590 tw->tw_hctd_tail = NULL; 2591 } 2592 } 2593 2594 td->flag = TD_FLAG_FREE; 2595 } 2596 2597 2598 void 2599 uhci_remove_tds_tws( 2600 uhci_state_t *uhcip, 2601 usba_pipe_handle_data_t *ph) 2602 { 2603 usb_opaque_t curr_reqp; 2604 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private; 2605 usb_ep_descr_t *ept = &pp->pp_pipe_handle->p_ep; 2606 uhci_trans_wrapper_t *tw_tmp; 2607 uhci_trans_wrapper_t *tw_head = pp->pp_tw_head; 2608 2609 while (tw_head != NULL) { 2610 tw_tmp = tw_head; 2611 tw_head = tw_head->tw_next; 2612 2613 curr_reqp = tw_tmp->tw_curr_xfer_reqp; 2614 if (curr_reqp) { 2615 /* do this for control/bulk/intr */ 2616 if ((tw_tmp->tw_direction == PID_IN) && 2617 (UHCI_XFER_TYPE(ept) == USB_EP_ATTR_INTR)) { 2618 uhci_deallocate_periodic_in_resource(uhcip, 2619 pp, tw_tmp); 2620 } else { 2621 uhci_hcdi_callback(uhcip, pp, 2622 pp->pp_pipe_handle, tw_tmp, USB_CR_FLUSHED); 2623 } 2624 } /* end of curr_reqp */ 2625 2626 if (tw_tmp->tw_claim != UHCI_MODIFY_TD_BITS_CLAIMED) { 2627 continue; 2628 } 2629 2630 while (tw_tmp->tw_hctd_head != NULL) { 2631 uhci_delete_td(uhcip, tw_tmp->tw_hctd_head); 2632 } 2633 2634 uhci_deallocate_tw(uhcip, pp, tw_tmp); 2635 } 2636 } 2637 2638 2639 /* 2640 * uhci_remove_qh: 2641 * Remove the Queue Head from the Host Controller's 2642 * appropriate QH list. 2643 */ 2644 void 2645 uhci_remove_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp) 2646 { 2647 uhci_td_t *dummy_td; 2648 2649 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 2650 2651 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 2652 "uhci_remove_qh:"); 2653 2654 dummy_td = pp->pp_qh->td_tailp; 2655 dummy_td->flag = TD_FLAG_FREE; 2656 2657 switch (UHCI_XFER_TYPE(&pp->pp_pipe_handle->p_ep)) { 2658 case USB_EP_ATTR_CONTROL: 2659 uhci_remove_ctrl_qh(uhcip, pp); 2660 break; 2661 case USB_EP_ATTR_BULK: 2662 uhci_remove_bulk_qh(uhcip, pp); 2663 break; 2664 case USB_EP_ATTR_INTR: 2665 uhci_remove_intr_qh(uhcip, pp); 2666 break; 2667 } 2668 } 2669 2670 2671 static void 2672 uhci_remove_intr_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp) 2673 { 2674 queue_head_t *qh = pp->pp_qh; 2675 queue_head_t *next_lattice_qh = 2676 QH_VADDR(GetQH32(uhcip, qh->link_ptr) & QH_LINK_PTR_MASK); 2677 2678 qh->prev_qh->link_ptr = qh->link_ptr; 2679 next_lattice_qh->prev_qh = qh->prev_qh; 2680 qh->qh_flag = QUEUE_HEAD_FLAG_FREE; 2681 2682 } 2683 2684 /* 2685 * uhci_remove_bulk_qh: 2686 * Remove a bulk QH from the Host Controller's QH list. There may be a 2687 * loop for bulk QHs, we must care about this while removing a bulk QH. 2688 */ 2689 static void 2690 uhci_remove_bulk_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp) 2691 { 2692 queue_head_t *qh = pp->pp_qh; 2693 queue_head_t *next_lattice_qh; 2694 uint32_t paddr; 2695 2696 paddr = (GetQH32(uhcip, qh->link_ptr) & QH_LINK_PTR_MASK); 2697 next_lattice_qh = (qh == uhcip->uhci_bulk_xfers_q_tail) ? 2698 0 : QH_VADDR(paddr); 2699 2700 if ((qh == uhcip->uhci_bulk_xfers_q_tail) && 2701 (qh->prev_qh == uhcip->uhci_bulk_xfers_q_head)) { 2702 SetQH32(uhcip, qh->prev_qh->link_ptr, HC_END_OF_LIST); 2703 } else { 2704 qh->prev_qh->link_ptr = qh->link_ptr; 2705 } 2706 2707 if (next_lattice_qh == NULL) { 2708 uhcip->uhci_bulk_xfers_q_tail = qh->prev_qh; 2709 } else { 2710 next_lattice_qh->prev_qh = qh->prev_qh; 2711 } 2712 2713 qh->qh_flag = QUEUE_HEAD_FLAG_FREE; 2714 2715 } 2716 2717 2718 static void 2719 uhci_remove_ctrl_qh(uhci_state_t *uhcip, uhci_pipe_private_t *pp) 2720 { 2721 queue_head_t *qh = pp->pp_qh; 2722 queue_head_t *next_lattice_qh = 2723 QH_VADDR(GetQH32(uhcip, qh->link_ptr) & QH_LINK_PTR_MASK); 2724 2725 qh->prev_qh->link_ptr = qh->link_ptr; 2726 if (next_lattice_qh->prev_qh != NULL) { 2727 next_lattice_qh->prev_qh = qh->prev_qh; 2728 } else { 2729 uhcip->uhci_ctrl_xfers_q_tail = qh->prev_qh; 2730 } 2731 2732 qh->qh_flag = QUEUE_HEAD_FLAG_FREE; 2733 } 2734 2735 2736 /* 2737 * uhci_allocate_td_from_pool: 2738 * Allocate a Transfer Descriptor (TD) from the TD buffer pool. 2739 */ 2740 static uhci_td_t * 2741 uhci_allocate_td_from_pool(uhci_state_t *uhcip) 2742 { 2743 int index; 2744 uhci_td_t *td; 2745 2746 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 2747 2748 /* 2749 * Search for a blank Transfer Descriptor (TD) 2750 * in the TD buffer pool. 2751 */ 2752 for (index = 0; index < uhci_td_pool_size; index ++) { 2753 if (uhcip->uhci_td_pool_addr[index].flag == TD_FLAG_FREE) { 2754 break; 2755 } 2756 } 2757 2758 if (index == uhci_td_pool_size) { 2759 USB_DPRINTF_L2(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 2760 "uhci_allocate_td_from_pool: TD exhausted"); 2761 2762 return (NULL); 2763 } 2764 2765 USB_DPRINTF_L4(PRINT_MASK_ALLOC, uhcip->uhci_log_hdl, 2766 "uhci_allocate_td_from_pool: Allocated %d", index); 2767 2768 /* Create a new dummy for the end of the TD list */ 2769 td = &uhcip->uhci_td_pool_addr[index]; 2770 2771 /* Mark the newly allocated TD as a dummy */ 2772 td->flag = TD_FLAG_DUMMY; 2773 td->qh_td_prev = NULL; 2774 2775 return (td); 2776 } 2777 2778 2779 /* 2780 * uhci_insert_bulk_td: 2781 */ 2782 int 2783 uhci_insert_bulk_td( 2784 uhci_state_t *uhcip, 2785 usba_pipe_handle_data_t *ph, 2786 usb_bulk_req_t *req, 2787 usb_flags_t flags) 2788 { 2789 size_t length; 2790 uint_t mps; /* MaxPacketSize */ 2791 uint_t num_bulk_tds, i, j; 2792 uint32_t buf_offs; 2793 uhci_td_t *bulk_td_ptr; 2794 uhci_td_t *current_dummy, *tmp_td; 2795 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private; 2796 uhci_trans_wrapper_t *tw; 2797 uhci_bulk_isoc_xfer_t *bulk_xfer_info; 2798 uhci_bulk_isoc_td_pool_t *td_pool_ptr; 2799 2800 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 2801 "uhci_insert_bulk_td: req: 0x%p, flags = 0x%x", req, flags); 2802 2803 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 2804 2805 /* 2806 * Create transfer wrapper 2807 */ 2808 if ((tw = uhci_create_transfer_wrapper(uhcip, pp, req->bulk_len, 2809 flags)) == NULL) { 2810 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 2811 "uhci_insert_bulk_td: TW allocation failed"); 2812 2813 return (USB_NO_RESOURCES); 2814 } 2815 2816 tw->tw_bytes_xfered = 0; 2817 tw->tw_bytes_pending = req->bulk_len; 2818 tw->tw_handle_td = uhci_handle_bulk_td; 2819 tw->tw_handle_callback_value = (usb_opaque_t)req->bulk_data; 2820 tw->tw_timeout_cnt = req->bulk_timeout; 2821 tw->tw_data = req->bulk_data; 2822 tw->tw_curr_xfer_reqp = (usb_opaque_t)req; 2823 2824 /* Get the bulk pipe direction */ 2825 tw->tw_direction = (UHCI_XFER_DIR(&ph->p_ep) == USB_EP_DIR_OUT) ? 2826 PID_OUT : PID_IN; 2827 2828 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 2829 "uhci_insert_bulk_td: direction: 0x%x", tw->tw_direction); 2830 2831 /* If the DATA OUT, copy the data into transfer buffer. */ 2832 if (tw->tw_direction == PID_OUT) { 2833 if (req->bulk_len) { 2834 ASSERT(req->bulk_data != NULL); 2835 2836 /* Copy the data into the message */ 2837 ddi_rep_put8(tw->tw_accesshandle, 2838 req->bulk_data->b_rptr, 2839 (uint8_t *)tw->tw_buf, 2840 req->bulk_len, DDI_DEV_AUTOINCR); 2841 } 2842 } 2843 2844 /* Get the max packet size. */ 2845 length = mps = pp->pp_pipe_handle->p_ep.wMaxPacketSize; 2846 2847 /* 2848 * Calculate number of TD's to insert in the current frame interval. 2849 * Max number TD's allowed (driver implementation) is 128 2850 * in one frame interval. Once all the TD's are completed 2851 * then the remaining TD's will be inserted into the lattice 2852 * in the uhci_handle_bulk_td(). 2853 */ 2854 if ((tw->tw_bytes_pending / mps) >= MAX_NUM_BULK_TDS_PER_XFER) { 2855 num_bulk_tds = MAX_NUM_BULK_TDS_PER_XFER; 2856 } else { 2857 num_bulk_tds = (tw->tw_bytes_pending / mps); 2858 2859 if (tw->tw_bytes_pending % mps || tw->tw_bytes_pending == 0) { 2860 num_bulk_tds++; 2861 length = (tw->tw_bytes_pending % mps); 2862 } 2863 } 2864 2865 /* 2866 * Allocate memory for the bulk xfer information structure 2867 */ 2868 if ((bulk_xfer_info = kmem_zalloc( 2869 sizeof (uhci_bulk_isoc_xfer_t), KM_NOSLEEP)) == NULL) { 2870 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 2871 "uhci_insert_bulk_td: kmem_zalloc failed"); 2872 2873 /* Free the transfer wrapper */ 2874 uhci_deallocate_tw(uhcip, pp, tw); 2875 2876 return (USB_FAILURE); 2877 } 2878 2879 /* Allocate memory for the bulk TD's */ 2880 if (uhci_alloc_bulk_isoc_tds(uhcip, num_bulk_tds, bulk_xfer_info) != 2881 USB_SUCCESS) { 2882 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 2883 "uhci_insert_bulk_td: alloc_bulk_isoc_tds failed"); 2884 2885 kmem_free(bulk_xfer_info, sizeof (uhci_bulk_isoc_xfer_t)); 2886 2887 /* Free the transfer wrapper */ 2888 uhci_deallocate_tw(uhcip, pp, tw); 2889 2890 return (USB_FAILURE); 2891 } 2892 2893 td_pool_ptr = &bulk_xfer_info->td_pools[0]; 2894 bulk_td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr; 2895 bulk_td_ptr[0].qh_td_prev = NULL; 2896 current_dummy = pp->pp_qh->td_tailp; 2897 buf_offs = 0; 2898 pp->pp_qh->bulk_xfer_info = bulk_xfer_info; 2899 2900 /* Fill up all the bulk TD's */ 2901 for (i = 0; i < bulk_xfer_info->num_pools; i++) { 2902 for (j = 0; j < (td_pool_ptr->num_tds - 1); j++) { 2903 uhci_fill_in_bulk_isoc_td(uhcip, &bulk_td_ptr[j], 2904 &bulk_td_ptr[j+1], BULKTD_PADDR(td_pool_ptr, 2905 &bulk_td_ptr[j+1]), ph, buf_offs, mps, tw); 2906 buf_offs += mps; 2907 } 2908 2909 /* fill in the last TD */ 2910 if (i == (bulk_xfer_info->num_pools - 1)) { 2911 uhci_fill_in_bulk_isoc_td(uhcip, &bulk_td_ptr[j], 2912 current_dummy, TD_PADDR(current_dummy), 2913 ph, buf_offs, length, tw); 2914 } else { 2915 /* fill in the TD at the tail of a pool */ 2916 tmp_td = &bulk_td_ptr[j]; 2917 td_pool_ptr = &bulk_xfer_info->td_pools[i + 1]; 2918 bulk_td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr; 2919 uhci_fill_in_bulk_isoc_td(uhcip, tmp_td, 2920 &bulk_td_ptr[0], BULKTD_PADDR(td_pool_ptr, 2921 &bulk_td_ptr[0]), ph, buf_offs, mps, tw); 2922 buf_offs += mps; 2923 } 2924 } 2925 2926 bulk_xfer_info->num_tds = num_bulk_tds; 2927 2928 /* 2929 * Point the end of the lattice tree to the start of the bulk xfers 2930 * queue head. This allows the HC to execute the same Queue Head/TD 2931 * in the same frame. There are some bulk devices, which NAKs after 2932 * completing each TD. As a result, the performance on such devices 2933 * is very bad. This loop will provide a chance to execute NAk'ed 2934 * bulk TDs again in the same frame. 2935 */ 2936 if (uhcip->uhci_pending_bulk_cmds++ == 0) { 2937 uhcip->uhci_bulk_xfers_q_tail->link_ptr = 2938 uhcip->uhci_bulk_xfers_q_head->link_ptr; 2939 USB_DPRINTF_L3(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 2940 "uhci_insert_bulk_td: count = %d no tds %d", 2941 uhcip->uhci_pending_bulk_cmds, num_bulk_tds); 2942 } 2943 2944 /* Insert on the bulk queue head for the execution by HC */ 2945 SetQH32(uhcip, pp->pp_qh->element_ptr, 2946 bulk_xfer_info->td_pools[0].cookie.dmac_address); 2947 2948 return (USB_SUCCESS); 2949 } 2950 2951 2952 /* 2953 * uhci_fill_in_bulk_isoc_td 2954 * Fills the bulk/isoc TD 2955 * 2956 * offset - different meanings for bulk and isoc TDs: 2957 * starting offset into the TW buffer for a bulk TD 2958 * and the index into the isoc packet list for an isoc TD 2959 */ 2960 void 2961 uhci_fill_in_bulk_isoc_td(uhci_state_t *uhcip, uhci_td_t *current_td, 2962 uhci_td_t *next_td, 2963 uint32_t next_td_paddr, 2964 usba_pipe_handle_data_t *ph, 2965 uint_t offset, 2966 uint_t length, 2967 uhci_trans_wrapper_t *tw) 2968 { 2969 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private; 2970 usb_ep_descr_t *ept = &pp->pp_pipe_handle->p_ep; 2971 uint32_t buf_addr; 2972 2973 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 2974 "uhci_fill_in_bulk_isoc_td: tw 0x%p offs 0x%x length 0x%x", 2975 tw, offset, length); 2976 2977 bzero((char *)current_td, sizeof (uhci_td_t)); 2978 SetTD32(uhcip, current_td->link_ptr, next_td_paddr | HC_DEPTH_FIRST); 2979 2980 switch (UHCI_XFER_TYPE(ept)) { 2981 case USB_EP_ATTR_ISOCH: 2982 if (((usb_isoc_req_t *)tw->tw_curr_xfer_reqp)->isoc_attributes 2983 & USB_ATTRS_SHORT_XFER_OK) { 2984 SetTD_spd(uhcip, current_td, 1); 2985 } 2986 break; 2987 case USB_EP_ATTR_BULK: 2988 if (((usb_bulk_req_t *)tw->tw_curr_xfer_reqp)->bulk_attributes 2989 & USB_ATTRS_SHORT_XFER_OK) { 2990 SetTD_spd(uhcip, current_td, 1); 2991 } 2992 break; 2993 } 2994 2995 mutex_enter(&ph->p_usba_device->usb_mutex); 2996 2997 SetTD_c_err(uhcip, current_td, UHCI_MAX_ERR_COUNT); 2998 SetTD_status(uhcip, current_td, UHCI_TD_ACTIVE); 2999 SetTD_ioc(uhcip, current_td, INTERRUPT_ON_COMPLETION); 3000 SetTD_mlen(uhcip, current_td, 3001 (length == 0) ? ZERO_LENGTH : (length - 1)); 3002 SetTD_dtogg(uhcip, current_td, pp->pp_data_toggle); 3003 SetTD_devaddr(uhcip, current_td, ph->p_usba_device->usb_addr); 3004 SetTD_endpt(uhcip, current_td, ph->p_ep.bEndpointAddress & 3005 END_POINT_ADDRESS_MASK); 3006 SetTD_PID(uhcip, current_td, tw->tw_direction); 3007 3008 /* Get the right buffer address for the current TD */ 3009 switch (UHCI_XFER_TYPE(ept)) { 3010 case USB_EP_ATTR_ISOCH: 3011 buf_addr = tw->tw_isoc_bufs[offset].cookie.dmac_address; 3012 break; 3013 case USB_EP_ATTR_BULK: 3014 buf_addr = uhci_get_tw_paddr_by_offs(uhcip, offset, 3015 length, tw); 3016 break; 3017 } 3018 SetTD32(uhcip, current_td->buffer_address, buf_addr); 3019 3020 /* 3021 * Adjust the data toggle. 3022 * The data toggle bit must always be 0 for isoc transfers. 3023 * And set the "iso" bit in the TD for isoc transfers. 3024 */ 3025 if (UHCI_XFER_TYPE(ept) == USB_EP_ATTR_ISOCH) { 3026 pp->pp_data_toggle = 0; 3027 SetTD_iso(uhcip, current_td, 1); 3028 } else { 3029 ADJ_DATA_TOGGLE(pp); 3030 next_td->qh_td_prev = current_td; 3031 pp->pp_qh->td_tailp = next_td; 3032 } 3033 3034 current_td->outst_td_next = NULL; 3035 current_td->outst_td_prev = uhcip->uhci_outst_tds_tail; 3036 if (uhcip->uhci_outst_tds_head == NULL) { 3037 uhcip->uhci_outst_tds_head = current_td; 3038 } else { 3039 uhcip->uhci_outst_tds_tail->outst_td_next = current_td; 3040 } 3041 uhcip->uhci_outst_tds_tail = current_td; 3042 current_td->tw = tw; 3043 3044 if (tw->tw_hctd_head == NULL) { 3045 ASSERT(tw->tw_hctd_tail == NULL); 3046 tw->tw_hctd_head = current_td; 3047 tw->tw_hctd_tail = current_td; 3048 } else { 3049 /* Add the td to the end of the list */ 3050 tw->tw_hctd_tail->tw_td_next = current_td; 3051 tw->tw_hctd_tail = current_td; 3052 } 3053 3054 mutex_exit(&ph->p_usba_device->usb_mutex); 3055 } 3056 3057 3058 /* 3059 * uhci_alloc_bulk_isoc_tds: 3060 * - Allocates the isoc/bulk TD pools. It will allocate one whole 3061 * pool to store all the TDs if the system allows. Only when the 3062 * first allocation fails, it tries to allocate several small 3063 * pools with each pool limited in physical page size. 3064 */ 3065 static int 3066 uhci_alloc_bulk_isoc_tds( 3067 uhci_state_t *uhcip, 3068 uint_t num_tds, 3069 uhci_bulk_isoc_xfer_t *info) 3070 { 3071 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3072 "uhci_alloc_bulk_isoc_tds: num_tds: 0x%x info: 0x%p", 3073 num_tds, info); 3074 3075 info->num_pools = 1; 3076 /* allocate as a whole pool at the first time */ 3077 if (uhci_alloc_memory_for_tds(uhcip, num_tds, info) != 3078 USB_SUCCESS) { 3079 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3080 "alloc_memory_for_tds failed: num_tds %d num_pools %d", 3081 num_tds, info->num_pools); 3082 3083 /* reduce the td number per pool and alloc again */ 3084 info->num_pools = num_tds / UHCI_MAX_TD_NUM_PER_POOL; 3085 if (num_tds % UHCI_MAX_TD_NUM_PER_POOL) { 3086 info->num_pools++; 3087 } 3088 3089 if (uhci_alloc_memory_for_tds(uhcip, num_tds, info) != 3090 USB_SUCCESS) { 3091 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3092 "alloc_memory_for_tds failed: num_tds %d " 3093 "num_pools %d", num_tds, info->num_pools); 3094 3095 return (USB_NO_RESOURCES); 3096 } 3097 } 3098 3099 return (USB_SUCCESS); 3100 } 3101 3102 3103 /* 3104 * uhci_alloc_memory_for_tds: 3105 * - Allocates memory for the isoc/bulk td pools. 3106 */ 3107 static int 3108 uhci_alloc_memory_for_tds( 3109 uhci_state_t *uhcip, 3110 uint_t num_tds, 3111 uhci_bulk_isoc_xfer_t *info) 3112 { 3113 int result, i, j, err; 3114 size_t real_length; 3115 uint_t ccount, num; 3116 ddi_device_acc_attr_t dev_attr; 3117 uhci_bulk_isoc_td_pool_t *td_pool_ptr1, *td_pool_ptr2; 3118 3119 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 3120 "uhci_alloc_memory_for_tds: num_tds: 0x%x info: 0x%p " 3121 "num_pools: %u", num_tds, info, info->num_pools); 3122 3123 /* The host controller will be little endian */ 3124 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 3125 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 3126 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 3127 3128 /* Allocate the TD pool structures */ 3129 if ((info->td_pools = kmem_zalloc( 3130 (sizeof (uhci_bulk_isoc_td_pool_t) * info->num_pools), 3131 KM_SLEEP)) == NULL) { 3132 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 3133 "uhci_alloc_memory_for_tds: alloc td_pools failed"); 3134 3135 return (USB_FAILURE); 3136 } 3137 3138 for (i = 0; i < info->num_pools; i++) { 3139 if (info->num_pools == 1) { 3140 num = num_tds; 3141 } else if (i < (info->num_pools - 1)) { 3142 num = UHCI_MAX_TD_NUM_PER_POOL; 3143 } else { 3144 num = (num_tds % UHCI_MAX_TD_NUM_PER_POOL); 3145 } 3146 3147 td_pool_ptr1 = &info->td_pools[i]; 3148 3149 /* Allocate the bulk TD pool DMA handle */ 3150 if (ddi_dma_alloc_handle(uhcip->uhci_dip, 3151 &uhcip->uhci_dma_attr, DDI_DMA_SLEEP, 0, 3152 &td_pool_ptr1->dma_handle) != DDI_SUCCESS) { 3153 3154 for (j = 0; j < i; j++) { 3155 td_pool_ptr2 = &info->td_pools[j]; 3156 result = ddi_dma_unbind_handle( 3157 td_pool_ptr2->dma_handle); 3158 ASSERT(result == DDI_SUCCESS); 3159 ddi_dma_mem_free(&td_pool_ptr2->mem_handle); 3160 ddi_dma_free_handle(&td_pool_ptr2->dma_handle); 3161 } 3162 3163 kmem_free(info->td_pools, 3164 (sizeof (uhci_bulk_isoc_td_pool_t) * 3165 info->num_pools)); 3166 3167 return (USB_FAILURE); 3168 } 3169 3170 /* Allocate the memory for the bulk TD pool */ 3171 if (ddi_dma_mem_alloc(td_pool_ptr1->dma_handle, 3172 num * sizeof (uhci_td_t), &dev_attr, 3173 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 0, 3174 &td_pool_ptr1->pool_addr, &real_length, 3175 &td_pool_ptr1->mem_handle) != DDI_SUCCESS) { 3176 3177 ddi_dma_free_handle(&td_pool_ptr1->dma_handle); 3178 3179 for (j = 0; j < i; j++) { 3180 td_pool_ptr2 = &info->td_pools[j]; 3181 result = ddi_dma_unbind_handle( 3182 td_pool_ptr2->dma_handle); 3183 ASSERT(result == DDI_SUCCESS); 3184 ddi_dma_mem_free(&td_pool_ptr2->mem_handle); 3185 ddi_dma_free_handle(&td_pool_ptr2->dma_handle); 3186 } 3187 3188 kmem_free(info->td_pools, 3189 (sizeof (uhci_bulk_isoc_td_pool_t) * 3190 info->num_pools)); 3191 3192 return (USB_FAILURE); 3193 } 3194 3195 /* Map the bulk TD pool into the I/O address space */ 3196 result = ddi_dma_addr_bind_handle(td_pool_ptr1->dma_handle, 3197 NULL, (caddr_t)td_pool_ptr1->pool_addr, real_length, 3198 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 3199 &td_pool_ptr1->cookie, &ccount); 3200 3201 /* Process the result */ 3202 err = USB_SUCCESS; 3203 3204 if (result != DDI_DMA_MAPPED) { 3205 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 3206 "uhci_allocate_memory_for_tds: Result = %d", 3207 result); 3208 uhci_decode_ddi_dma_addr_bind_handle_result(uhcip, 3209 result); 3210 3211 err = USB_FAILURE; 3212 } 3213 3214 if ((result == DDI_DMA_MAPPED) && (ccount != 1)) { 3215 /* The cookie count should be 1 */ 3216 USB_DPRINTF_L2(PRINT_MASK_ATTA, 3217 uhcip->uhci_log_hdl, 3218 "uhci_allocate_memory_for_tds: " 3219 "More than 1 cookie"); 3220 3221 result = ddi_dma_unbind_handle( 3222 td_pool_ptr1->dma_handle); 3223 ASSERT(result == DDI_SUCCESS); 3224 3225 err = USB_FAILURE; 3226 } 3227 3228 if (err == USB_FAILURE) { 3229 3230 ddi_dma_mem_free(&td_pool_ptr1->mem_handle); 3231 ddi_dma_free_handle(&td_pool_ptr1->dma_handle); 3232 3233 for (j = 0; j < i; j++) { 3234 td_pool_ptr2 = &info->td_pools[j]; 3235 result = ddi_dma_unbind_handle( 3236 td_pool_ptr2->dma_handle); 3237 ASSERT(result == DDI_SUCCESS); 3238 ddi_dma_mem_free(&td_pool_ptr2->mem_handle); 3239 ddi_dma_free_handle(&td_pool_ptr2->dma_handle); 3240 } 3241 3242 kmem_free(info->td_pools, 3243 (sizeof (uhci_bulk_isoc_td_pool_t) * 3244 info->num_pools)); 3245 3246 return (USB_FAILURE); 3247 } 3248 3249 bzero((void *)td_pool_ptr1->pool_addr, 3250 num * sizeof (uhci_td_t)); 3251 td_pool_ptr1->num_tds = num; 3252 } 3253 3254 return (USB_SUCCESS); 3255 } 3256 3257 3258 /* 3259 * uhci_handle_bulk_td: 3260 * 3261 * Handles the completed bulk transfer descriptors 3262 */ 3263 void 3264 uhci_handle_bulk_td(uhci_state_t *uhcip, uhci_td_t *td) 3265 { 3266 uint_t num_bulk_tds, index, td_count, j; 3267 usb_cr_t error; 3268 uint_t length, bytes_xfered; 3269 ushort_t MaxPacketSize; 3270 uint32_t buf_offs, paddr; 3271 uhci_td_t *bulk_td_ptr, *current_dummy, *td_head; 3272 uhci_td_t *tmp_td; 3273 queue_head_t *qh, *next_qh; 3274 uhci_trans_wrapper_t *tw = td->tw; 3275 uhci_pipe_private_t *pp = tw->tw_pipe_private; 3276 uhci_bulk_isoc_xfer_t *bulk_xfer_info; 3277 uhci_bulk_isoc_td_pool_t *td_pool_ptr; 3278 usba_pipe_handle_data_t *ph; 3279 3280 USB_DPRINTF_L4(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 3281 "uhci_handle_bulk_td: td = 0x%p tw = 0x%p", td, tw); 3282 3283 /* 3284 * Update the tw_bytes_pending, and tw_bytes_xfered 3285 */ 3286 bytes_xfered = ZERO_LENGTH; 3287 3288 /* 3289 * Check whether there are any errors occurred in the xfer. 3290 * If so, update the data_toggle for the queue head and 3291 * return error to the upper layer. 3292 */ 3293 if (GetTD_status(uhcip, td) & TD_STATUS_MASK) { 3294 uhci_handle_bulk_td_errors(uhcip, td); 3295 3296 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3297 "uhci_handle_bulk_td: error; data toggle: 0x%x", 3298 pp->pp_data_toggle); 3299 3300 return; 3301 } 3302 3303 /* 3304 * Update the tw_bytes_pending, and tw_bytes_xfered 3305 */ 3306 bytes_xfered = GetTD_alen(uhcip, td); 3307 if (bytes_xfered != ZERO_LENGTH) { 3308 tw->tw_bytes_pending -= (bytes_xfered + 1); 3309 tw->tw_bytes_xfered += (bytes_xfered + 1); 3310 } 3311 3312 /* 3313 * Get Bulk pipe information and pipe handle 3314 */ 3315 bulk_xfer_info = pp->pp_qh->bulk_xfer_info; 3316 ph = tw->tw_pipe_private->pp_pipe_handle; 3317 3318 /* 3319 * Check whether data underrun occurred. 3320 * If so, complete the transfer 3321 * Update the data toggle bit 3322 */ 3323 if (bytes_xfered != GetTD_mlen(uhcip, td)) { 3324 bulk_xfer_info->num_tds = 1; 3325 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 3326 "uhci_handle_bulk_td: Data underrun occured"); 3327 3328 pp->pp_data_toggle = GetTD_dtogg(uhcip, td) == 0 ? 1 : 0; 3329 } 3330 3331 /* 3332 * If the TD's in the current frame are completed, then check 3333 * whether we have any more bytes to xfer. If so, insert TD's. 3334 * If no more bytes needs to be transferred, then do callback to the 3335 * upper layer. 3336 * If the TD's in the current frame are not completed, then 3337 * just delete the TD from the linked lists. 3338 */ 3339 USB_DPRINTF_L3(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3340 "uhci_handle_bulk_td: completed TD data toggle: 0x%x", 3341 GetTD_dtogg(uhcip, td)); 3342 3343 if (--bulk_xfer_info->num_tds == 0) { 3344 uhci_delete_td(uhcip, td); 3345 3346 if ((tw->tw_bytes_pending) && 3347 (GetTD_mlen(uhcip, td) - GetTD_alen(uhcip, td) == 0)) { 3348 3349 MaxPacketSize = pp->pp_pipe_handle->p_ep.wMaxPacketSize; 3350 length = MaxPacketSize; 3351 3352 qh = pp->pp_qh; 3353 paddr = GetQH32(uhcip, qh->link_ptr) & QH_LINK_PTR_MASK; 3354 if (GetQH32(uhcip, qh->link_ptr) != 3355 GetQH32(uhcip, 3356 uhcip->uhci_bulk_xfers_q_head->link_ptr)) { 3357 next_qh = QH_VADDR(paddr); 3358 SetQH32(uhcip, qh->prev_qh->link_ptr, 3359 paddr|(0x2)); 3360 next_qh->prev_qh = qh->prev_qh; 3361 SetQH32(uhcip, qh->link_ptr, 3362 GetQH32(uhcip, 3363 uhcip->uhci_bulk_xfers_q_head->link_ptr)); 3364 qh->prev_qh = uhcip->uhci_bulk_xfers_q_tail; 3365 SetQH32(uhcip, 3366 uhcip->uhci_bulk_xfers_q_tail->link_ptr, 3367 QH_PADDR(qh) | 0x2); 3368 uhcip->uhci_bulk_xfers_q_tail = qh; 3369 } 3370 3371 if ((tw->tw_bytes_pending / MaxPacketSize) >= 3372 MAX_NUM_BULK_TDS_PER_XFER) { 3373 num_bulk_tds = MAX_NUM_BULK_TDS_PER_XFER; 3374 } else { 3375 num_bulk_tds = 3376 (tw->tw_bytes_pending / MaxPacketSize); 3377 if (tw->tw_bytes_pending % MaxPacketSize) { 3378 num_bulk_tds++; 3379 length = (tw->tw_bytes_pending % 3380 MaxPacketSize); 3381 } 3382 } 3383 3384 current_dummy = pp->pp_qh->td_tailp; 3385 td_pool_ptr = &bulk_xfer_info->td_pools[0]; 3386 bulk_td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr; 3387 buf_offs = tw->tw_bytes_xfered; 3388 td_count = num_bulk_tds; 3389 index = 0; 3390 3391 /* reuse the TDs to transfer more data */ 3392 while (td_count > 0) { 3393 for (j = 0; 3394 (j < (td_pool_ptr->num_tds - 1)) && 3395 (td_count > 1); j++, td_count--) { 3396 uhci_fill_in_bulk_isoc_td(uhcip, 3397 &bulk_td_ptr[j], &bulk_td_ptr[j+1], 3398 BULKTD_PADDR(td_pool_ptr, 3399 &bulk_td_ptr[j+1]), ph, buf_offs, 3400 MaxPacketSize, tw); 3401 buf_offs += MaxPacketSize; 3402 } 3403 3404 if (td_count == 1) { 3405 uhci_fill_in_bulk_isoc_td(uhcip, 3406 &bulk_td_ptr[j], current_dummy, 3407 TD_PADDR(current_dummy), ph, 3408 buf_offs, length, tw); 3409 3410 break; 3411 } else { 3412 tmp_td = &bulk_td_ptr[j]; 3413 ASSERT(index < 3414 (bulk_xfer_info->num_pools - 1)); 3415 td_pool_ptr = &bulk_xfer_info-> 3416 td_pools[index + 1]; 3417 bulk_td_ptr = (uhci_td_t *) 3418 td_pool_ptr->pool_addr; 3419 uhci_fill_in_bulk_isoc_td(uhcip, 3420 tmp_td, &bulk_td_ptr[0], 3421 BULKTD_PADDR(td_pool_ptr, 3422 &bulk_td_ptr[0]), ph, buf_offs, 3423 MaxPacketSize, tw); 3424 buf_offs += MaxPacketSize; 3425 td_count--; 3426 index++; 3427 } 3428 } 3429 3430 pp->pp_qh->bulk_xfer_info = bulk_xfer_info; 3431 bulk_xfer_info->num_tds = num_bulk_tds; 3432 SetQH32(uhcip, pp->pp_qh->element_ptr, 3433 bulk_xfer_info->td_pools[0].cookie.dmac_address); 3434 } else { 3435 usba_pipe_handle_data_t *usb_pp = pp->pp_pipe_handle; 3436 3437 pp->pp_qh->bulk_xfer_info = NULL; 3438 3439 if (tw->tw_bytes_pending) { 3440 /* Update the element pointer */ 3441 SetQH32(uhcip, pp->pp_qh->element_ptr, 3442 TD_PADDR(pp->pp_qh->td_tailp)); 3443 3444 /* Remove all the tds */ 3445 td_head = tw->tw_hctd_head; 3446 while (td_head != NULL) { 3447 uhci_delete_td(uhcip, td_head); 3448 td_head = tw->tw_hctd_head; 3449 } 3450 } 3451 3452 if (tw->tw_direction == PID_IN) { 3453 usb_req_attrs_t attrs = ((usb_bulk_req_t *) 3454 tw->tw_curr_xfer_reqp)->bulk_attributes; 3455 3456 error = USB_CR_OK; 3457 3458 /* Data run occurred */ 3459 if (tw->tw_bytes_pending && 3460 (!(attrs & USB_ATTRS_SHORT_XFER_OK))) { 3461 error = USB_CR_DATA_UNDERRUN; 3462 } 3463 3464 uhci_sendup_td_message(uhcip, error, tw); 3465 } else { 3466 uhci_do_byte_stats(uhcip, tw->tw_length, 3467 usb_pp->p_ep.bmAttributes, 3468 usb_pp->p_ep.bEndpointAddress); 3469 3470 /* Data underrun occurred */ 3471 if (tw->tw_bytes_pending) { 3472 3473 tw->tw_data->b_rptr += 3474 tw->tw_bytes_xfered; 3475 3476 USB_DPRINTF_L2(PRINT_MASK_ATTA, 3477 uhcip->uhci_log_hdl, 3478 "uhci_handle_bulk_td: " 3479 "data underrun occurred"); 3480 3481 uhci_hcdi_callback(uhcip, pp, 3482 tw->tw_pipe_private->pp_pipe_handle, 3483 tw, USB_CR_DATA_UNDERRUN); 3484 } else { 3485 uhci_hcdi_callback(uhcip, pp, 3486 tw->tw_pipe_private->pp_pipe_handle, 3487 tw, USB_CR_OK); 3488 } 3489 } /* direction */ 3490 3491 /* Deallocate DMA memory */ 3492 uhci_deallocate_tw(uhcip, pp, tw); 3493 for (j = 0; j < bulk_xfer_info->num_pools; j++) { 3494 td_pool_ptr = &bulk_xfer_info->td_pools[j]; 3495 (void) ddi_dma_unbind_handle( 3496 td_pool_ptr->dma_handle); 3497 ddi_dma_mem_free(&td_pool_ptr->mem_handle); 3498 ddi_dma_free_handle(&td_pool_ptr->dma_handle); 3499 } 3500 kmem_free(bulk_xfer_info->td_pools, 3501 (sizeof (uhci_bulk_isoc_td_pool_t) * 3502 bulk_xfer_info->num_pools)); 3503 kmem_free(bulk_xfer_info, 3504 sizeof (uhci_bulk_isoc_xfer_t)); 3505 3506 /* 3507 * When there are no pending bulk commands, point the 3508 * end of the lattice tree to NULL. This will make sure 3509 * that the HC control does not loop anymore and PCI 3510 * bus is not affected. 3511 */ 3512 if (--uhcip->uhci_pending_bulk_cmds == 0) { 3513 uhcip->uhci_bulk_xfers_q_tail->link_ptr = 3514 HC_END_OF_LIST; 3515 USB_DPRINTF_L3(PRINT_MASK_ATTA, 3516 uhcip->uhci_log_hdl, 3517 "uhci_handle_bulk_td: count = %d", 3518 uhcip->uhci_pending_bulk_cmds); 3519 } 3520 } 3521 } else { 3522 uhci_delete_td(uhcip, td); 3523 } 3524 } 3525 3526 3527 void 3528 uhci_handle_bulk_td_errors(uhci_state_t *uhcip, uhci_td_t *td) 3529 { 3530 usb_cr_t usb_err; 3531 uint32_t paddr_tail, element_ptr, paddr; 3532 uhci_td_t *next_td; 3533 uhci_pipe_private_t *pp; 3534 uhci_trans_wrapper_t *tw = td->tw; 3535 usba_pipe_handle_data_t *ph; 3536 uhci_bulk_isoc_td_pool_t *td_pool_ptr = NULL; 3537 3538 USB_DPRINTF_L2(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 3539 "uhci_handle_bulk_td_errors: td = %p", (void *)td); 3540 3541 #ifdef DEBUG 3542 uhci_print_td(uhcip, td); 3543 #endif 3544 3545 tw = td->tw; 3546 ph = tw->tw_pipe_private->pp_pipe_handle; 3547 pp = (uhci_pipe_private_t *)ph->p_hcd_private; 3548 3549 /* 3550 * Find the type of error occurred and return the error 3551 * to the upper layer. And adjust the data toggle. 3552 */ 3553 element_ptr = GetQH32(uhcip, pp->pp_qh->element_ptr) & 3554 QH_ELEMENT_PTR_MASK; 3555 paddr_tail = TD_PADDR(pp->pp_qh->td_tailp); 3556 3557 /* 3558 * If a timeout occurs before a transfer has completed, 3559 * the timeout handler sets the CRC/Timeout bit and clears the Active 3560 * bit in the link_ptr for each td in the transfer. 3561 * It then waits (at least) 1 ms so that any tds the controller might 3562 * have been executing will have completed. 3563 * So at this point element_ptr will point to either: 3564 * 1) the next td for the transfer (which has not been executed, 3565 * and has the CRC/Timeout status bit set and Active bit cleared), 3566 * 2) the dummy td for this qh. 3567 * So if the element_ptr does not point to the dummy td, we know 3568 * it points to the next td that would have been executed. 3569 * That td has the data toggle we want to save. 3570 * All outstanding tds have been marked as CRC/Timeout, 3571 * so it doesn't matter which td we pass to uhci_parse_td_error 3572 * for the error status. 3573 */ 3574 if (element_ptr != paddr_tail) { 3575 paddr = (element_ptr & QH_ELEMENT_PTR_MASK); 3576 uhci_get_bulk_td_by_paddr(uhcip, pp->pp_qh->bulk_xfer_info, 3577 paddr, &td_pool_ptr); 3578 next_td = BULKTD_VADDR(td_pool_ptr, paddr); 3579 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3580 "uhci_handle_bulk_td_errors: next td = %p", 3581 (void *)next_td); 3582 3583 usb_err = uhci_parse_td_error(uhcip, pp, next_td); 3584 } else { 3585 usb_err = uhci_parse_td_error(uhcip, pp, td); 3586 } 3587 3588 /* 3589 * Update the link pointer. 3590 */ 3591 SetQH32(uhcip, pp->pp_qh->element_ptr, TD_PADDR(pp->pp_qh->td_tailp)); 3592 3593 /* 3594 * Send up number of bytes transferred before the error condition. 3595 */ 3596 if ((tw->tw_direction == PID_OUT) && tw->tw_data) { 3597 tw->tw_data->b_rptr += tw->tw_bytes_xfered; 3598 } 3599 3600 uhci_remove_bulk_tds_tws(uhcip, tw->tw_pipe_private, UHCI_IN_ERROR); 3601 3602 /* 3603 * When there are no pending bulk commands, point the end of the 3604 * lattice tree to NULL. This will make sure that the HC control 3605 * does not loop anymore and PCI bus is not affected. 3606 */ 3607 if (--uhcip->uhci_pending_bulk_cmds == 0) { 3608 uhcip->uhci_bulk_xfers_q_tail->link_ptr = HC_END_OF_LIST; 3609 USB_DPRINTF_L3(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 3610 "uhci_handle_bulk_td_errors: count = %d", 3611 uhcip->uhci_pending_bulk_cmds); 3612 } 3613 3614 uhci_hcdi_callback(uhcip, pp, ph, tw, usb_err); 3615 uhci_deallocate_tw(uhcip, pp, tw); 3616 } 3617 3618 3619 /* 3620 * uhci_get_bulk_td_by_paddr: 3621 * Obtain the address of the TD pool the physical address falls in. 3622 * 3623 * td_pool_pp - pointer to the address of the TD pool containing the paddr 3624 */ 3625 /* ARGSUSED */ 3626 static void 3627 uhci_get_bulk_td_by_paddr( 3628 uhci_state_t *uhcip, 3629 uhci_bulk_isoc_xfer_t *info, 3630 uint32_t paddr, 3631 uhci_bulk_isoc_td_pool_t **td_pool_pp) 3632 { 3633 uint_t i = 0; 3634 3635 while (i < info->num_pools) { 3636 *td_pool_pp = &info->td_pools[i]; 3637 if (((*td_pool_pp)->cookie.dmac_address <= paddr) && 3638 (((*td_pool_pp)->cookie.dmac_address + 3639 (*td_pool_pp)->cookie.dmac_size) > paddr)) { 3640 3641 break; 3642 } 3643 i++; 3644 } 3645 3646 ASSERT(i < info->num_pools); 3647 } 3648 3649 3650 void 3651 uhci_remove_bulk_tds_tws( 3652 uhci_state_t *uhcip, 3653 uhci_pipe_private_t *pp, 3654 int what) 3655 { 3656 uint_t rval, i; 3657 uhci_td_t *head; 3658 uhci_td_t *head_next; 3659 usb_opaque_t curr_reqp; 3660 uhci_bulk_isoc_xfer_t *info; 3661 uhci_bulk_isoc_td_pool_t *td_pool_ptr; 3662 3663 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 3664 3665 if ((info = pp->pp_qh->bulk_xfer_info) == NULL) { 3666 3667 return; 3668 } 3669 3670 head = uhcip->uhci_outst_tds_head; 3671 3672 while (head) { 3673 uhci_trans_wrapper_t *tw_tmp = head->tw; 3674 head_next = head->outst_td_next; 3675 3676 if (pp->pp_qh == tw_tmp->tw_pipe_private->pp_qh) { 3677 curr_reqp = tw_tmp->tw_curr_xfer_reqp; 3678 if (curr_reqp && 3679 ((what == UHCI_IN_CLOSE) || 3680 (what == UHCI_IN_RESET))) { 3681 uhci_hcdi_callback(uhcip, pp, 3682 pp->pp_pipe_handle, 3683 tw_tmp, USB_CR_FLUSHED); 3684 } /* end of curr_reqp */ 3685 3686 uhci_delete_td(uhcip, head); 3687 3688 if (what == UHCI_IN_CLOSE || what == UHCI_IN_RESET) { 3689 ASSERT(info->num_tds > 0); 3690 if (--info->num_tds == 0) { 3691 uhci_deallocate_tw(uhcip, pp, tw_tmp); 3692 3693 /* 3694 * This will make sure that the HC 3695 * does not loop anymore when there 3696 * are no pending bulk commands. 3697 */ 3698 if (--uhcip->uhci_pending_bulk_cmds 3699 == 0) { 3700 uhcip->uhci_bulk_xfers_q_tail-> 3701 link_ptr = HC_END_OF_LIST; 3702 USB_DPRINTF_L3(PRINT_MASK_ATTA, 3703 uhcip->uhci_log_hdl, 3704 "uhci_remove_bulk_tds_tws:" 3705 " count = %d", 3706 uhcip-> 3707 uhci_pending_bulk_cmds); 3708 } 3709 } 3710 } 3711 } 3712 3713 head = head_next; 3714 } 3715 3716 if (what == UHCI_IN_CLOSE || what == UHCI_IN_RESET) { 3717 ASSERT(info->num_tds == 0); 3718 } 3719 3720 for (i = 0; i < info->num_pools; i++) { 3721 td_pool_ptr = &info->td_pools[i]; 3722 rval = ddi_dma_unbind_handle(td_pool_ptr->dma_handle); 3723 ASSERT(rval == DDI_SUCCESS); 3724 ddi_dma_mem_free(&td_pool_ptr->mem_handle); 3725 ddi_dma_free_handle(&td_pool_ptr->dma_handle); 3726 } 3727 kmem_free(info->td_pools, (sizeof (uhci_bulk_isoc_td_pool_t) * 3728 info->num_pools)); 3729 kmem_free(info, sizeof (uhci_bulk_isoc_xfer_t)); 3730 pp->pp_qh->bulk_xfer_info = NULL; 3731 } 3732 3733 3734 /* 3735 * uhci_save_data_toggle () 3736 * Save the data toggle in the usba_device structure 3737 */ 3738 void 3739 uhci_save_data_toggle(uhci_pipe_private_t *pp) 3740 { 3741 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 3742 3743 /* Save the data toggle in the usb devices structure. */ 3744 mutex_enter(&ph->p_mutex); 3745 usba_hcdi_set_data_toggle(ph->p_usba_device, ph->p_ep.bEndpointAddress, 3746 pp->pp_data_toggle); 3747 mutex_exit(&ph->p_mutex); 3748 } 3749 3750 /* 3751 * uhci_create_isoc_transfer_wrapper: 3752 * Create a Transaction Wrapper (TW) for isoc transfer. 3753 * This involves the allocating of DMA resources. 3754 * 3755 * For isoc transfers, one isoc transfer includes multiple packets 3756 * and each packet may have a different length. So each packet is 3757 * transfered by one TD. We only know the individual packet length 3758 * won't exceed 1023 bytes, but we don't know exactly the lengths. 3759 * It is hard to make one physically discontiguous DMA buffer which 3760 * can fit in all the TDs like what can be done to the ctrl/bulk/ 3761 * intr transfers. It is also undesirable to make one physically 3762 * contiguous DMA buffer for all the packets, since this may easily 3763 * fail when the system is in low memory. So an individual DMA 3764 * buffer is allocated for an individual isoc packet and each DMA 3765 * buffer is physically contiguous. An extra structure is allocated 3766 * to save the multiple DMA handles. 3767 */ 3768 static uhci_trans_wrapper_t * 3769 uhci_create_isoc_transfer_wrapper( 3770 uhci_state_t *uhcip, 3771 uhci_pipe_private_t *pp, 3772 usb_isoc_req_t *req, 3773 size_t length, 3774 usb_flags_t usb_flags) 3775 { 3776 int result; 3777 size_t real_length, strtlen, xfer_size; 3778 uhci_trans_wrapper_t *tw; 3779 ddi_device_acc_attr_t dev_attr; 3780 ddi_dma_attr_t dma_attr; 3781 int kmem_flag; 3782 int (*dmamem_wait)(caddr_t); 3783 uint_t i, j, ccount; 3784 usb_isoc_req_t *tmp_req = req; 3785 3786 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 3787 3788 if (UHCI_XFER_TYPE(&pp->pp_pipe_handle->p_ep) != USB_EP_ATTR_ISOCH) { 3789 3790 return (NULL); 3791 } 3792 3793 if ((req == NULL) && (UHCI_XFER_DIR(&pp->pp_pipe_handle->p_ep) == 3794 USB_EP_DIR_IN)) { 3795 tmp_req = (usb_isoc_req_t *)pp->pp_client_periodic_in_reqp; 3796 } 3797 3798 if (tmp_req == NULL) { 3799 3800 return (NULL); 3801 } 3802 3803 3804 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3805 "uhci_create_isoc_transfer_wrapper: length = 0x%lx flags = 0x%x", 3806 length, usb_flags); 3807 3808 /* SLEEP flag should not be used in interrupt context */ 3809 if (servicing_interrupt()) { 3810 kmem_flag = KM_NOSLEEP; 3811 dmamem_wait = DDI_DMA_DONTWAIT; 3812 } else { 3813 kmem_flag = KM_SLEEP; 3814 dmamem_wait = DDI_DMA_SLEEP; 3815 } 3816 3817 /* Allocate space for the transfer wrapper */ 3818 if ((tw = kmem_zalloc(sizeof (uhci_trans_wrapper_t), kmem_flag)) == 3819 NULL) { 3820 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3821 "uhci_create_isoc_transfer_wrapper: kmem_alloc failed"); 3822 3823 return (NULL); 3824 } 3825 3826 /* Allocate space for the isoc buffer handles */ 3827 strtlen = sizeof (uhci_isoc_buf_t) * tmp_req->isoc_pkts_count; 3828 if ((tw->tw_isoc_bufs = kmem_zalloc(strtlen, kmem_flag)) == NULL) { 3829 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3830 "uhci_create_isoc_transfer_wrapper: kmem_alloc " 3831 "isoc buffer failed"); 3832 kmem_free(tw, sizeof (uhci_trans_wrapper_t)); 3833 3834 return (NULL); 3835 } 3836 3837 bcopy(&uhcip->uhci_dma_attr, &dma_attr, sizeof (ddi_dma_attr_t)); 3838 dma_attr.dma_attr_sgllen = 1; 3839 3840 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 3841 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 3842 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 3843 3844 /* Store the transfer length */ 3845 tw->tw_length = length; 3846 3847 for (i = 0; i < tmp_req->isoc_pkts_count; i++) { 3848 tw->tw_isoc_bufs[i].index = i; 3849 3850 /* Allocate the DMA handle */ 3851 if ((result = ddi_dma_alloc_handle(uhcip->uhci_dip, &dma_attr, 3852 dmamem_wait, 0, &tw->tw_isoc_bufs[i].dma_handle)) != 3853 DDI_SUCCESS) { 3854 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3855 "uhci_create_isoc_transfer_wrapper: " 3856 "Alloc handle %d failed", i); 3857 3858 for (j = 0; j < i; j++) { 3859 result = ddi_dma_unbind_handle( 3860 tw->tw_isoc_bufs[j].dma_handle); 3861 ASSERT(result == USB_SUCCESS); 3862 ddi_dma_mem_free(&tw->tw_isoc_bufs[j]. 3863 mem_handle); 3864 ddi_dma_free_handle(&tw->tw_isoc_bufs[j]. 3865 dma_handle); 3866 } 3867 kmem_free(tw->tw_isoc_bufs, strtlen); 3868 kmem_free(tw, sizeof (uhci_trans_wrapper_t)); 3869 3870 return (NULL); 3871 } 3872 3873 /* Allocate the memory */ 3874 xfer_size = tmp_req->isoc_pkt_descr[i].isoc_pkt_length; 3875 if ((result = ddi_dma_mem_alloc(tw->tw_isoc_bufs[i].dma_handle, 3876 xfer_size, &dev_attr, DDI_DMA_CONSISTENT, dmamem_wait, 3877 NULL, (caddr_t *)&tw->tw_isoc_bufs[i].buf_addr, 3878 &real_length, &tw->tw_isoc_bufs[i].mem_handle)) != 3879 DDI_SUCCESS) { 3880 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3881 "uhci_create_isoc_transfer_wrapper: " 3882 "dma_mem_alloc %d fail", i); 3883 ddi_dma_free_handle(&tw->tw_isoc_bufs[i].dma_handle); 3884 3885 for (j = 0; j < i; j++) { 3886 result = ddi_dma_unbind_handle( 3887 tw->tw_isoc_bufs[j].dma_handle); 3888 ASSERT(result == USB_SUCCESS); 3889 ddi_dma_mem_free(&tw->tw_isoc_bufs[j]. 3890 mem_handle); 3891 ddi_dma_free_handle(&tw->tw_isoc_bufs[j]. 3892 dma_handle); 3893 } 3894 kmem_free(tw->tw_isoc_bufs, strtlen); 3895 kmem_free(tw, sizeof (uhci_trans_wrapper_t)); 3896 3897 return (NULL); 3898 } 3899 3900 ASSERT(real_length >= xfer_size); 3901 3902 /* Bind the handle */ 3903 result = ddi_dma_addr_bind_handle( 3904 tw->tw_isoc_bufs[i].dma_handle, NULL, 3905 (caddr_t)tw->tw_isoc_bufs[i].buf_addr, real_length, 3906 DDI_DMA_RDWR|DDI_DMA_CONSISTENT, dmamem_wait, NULL, 3907 &tw->tw_isoc_bufs[i].cookie, &ccount); 3908 3909 if ((result == DDI_DMA_MAPPED) && (ccount == 1)) { 3910 tw->tw_isoc_bufs[i].length = xfer_size; 3911 3912 continue; 3913 } else { 3914 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3915 "uhci_create_isoc_transfer_wrapper: " 3916 "Bind handle %d failed", i); 3917 if (result == DDI_DMA_MAPPED) { 3918 result = ddi_dma_unbind_handle( 3919 tw->tw_isoc_bufs[i].dma_handle); 3920 ASSERT(result == USB_SUCCESS); 3921 } 3922 ddi_dma_mem_free(&tw->tw_isoc_bufs[i].mem_handle); 3923 ddi_dma_free_handle(&tw->tw_isoc_bufs[i].dma_handle); 3924 3925 for (j = 0; j < i; j++) { 3926 result = ddi_dma_unbind_handle( 3927 tw->tw_isoc_bufs[j].dma_handle); 3928 ASSERT(result == USB_SUCCESS); 3929 ddi_dma_mem_free(&tw->tw_isoc_bufs[j]. 3930 mem_handle); 3931 ddi_dma_free_handle(&tw->tw_isoc_bufs[j]. 3932 dma_handle); 3933 } 3934 kmem_free(tw->tw_isoc_bufs, strtlen); 3935 kmem_free(tw, sizeof (uhci_trans_wrapper_t)); 3936 3937 return (NULL); 3938 } 3939 } 3940 3941 tw->tw_ncookies = tmp_req->isoc_pkts_count; 3942 tw->tw_isoc_strtlen = strtlen; 3943 3944 /* 3945 * Only allow one wrapper to be added at a time. Insert the 3946 * new transaction wrapper into the list for this pipe. 3947 */ 3948 if (pp->pp_tw_head == NULL) { 3949 pp->pp_tw_head = tw; 3950 pp->pp_tw_tail = tw; 3951 } else { 3952 pp->pp_tw_tail->tw_next = tw; 3953 pp->pp_tw_tail = tw; 3954 ASSERT(tw->tw_next == NULL); 3955 } 3956 3957 /* Store a back pointer to the pipe private structure */ 3958 tw->tw_pipe_private = pp; 3959 3960 /* Store the transfer type - synchronous or asynchronous */ 3961 tw->tw_flags = usb_flags; 3962 3963 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 3964 "uhci_create_isoc_transfer_wrapper: tw = 0x%p, ncookies = %u", 3965 tw, tw->tw_ncookies); 3966 3967 return (tw); 3968 } 3969 3970 /* 3971 * uhci_insert_isoc_td: 3972 * - Create transfer wrapper 3973 * - Allocate memory for the isoc td's 3974 * - Fill up all the TD's and submit to the HC 3975 * - Update all the linked lists 3976 */ 3977 int 3978 uhci_insert_isoc_td( 3979 uhci_state_t *uhcip, 3980 usba_pipe_handle_data_t *ph, 3981 usb_isoc_req_t *isoc_req, 3982 size_t length, 3983 usb_flags_t flags) 3984 { 3985 int rval = USB_SUCCESS; 3986 int error; 3987 uint_t ddic; 3988 uint32_t i, j, index; 3989 uint32_t bytes_to_xfer; 3990 uint32_t expired_frames = 0; 3991 usb_frame_number_t start_frame, end_frame, current_frame; 3992 uhci_td_t *td_ptr; 3993 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private; 3994 uhci_trans_wrapper_t *tw; 3995 uhci_bulk_isoc_xfer_t *isoc_xfer_info; 3996 uhci_bulk_isoc_td_pool_t *td_pool_ptr; 3997 3998 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 3999 "uhci_insert_isoc_td: ph = 0x%p isoc req = %p length = %lu", 4000 ph, (void *)isoc_req, length); 4001 4002 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4003 4004 /* Allocate a transfer wrapper */ 4005 if ((tw = uhci_create_isoc_transfer_wrapper(uhcip, pp, isoc_req, 4006 length, flags)) == NULL) { 4007 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4008 "uhci_insert_isoc_td: TW allocation failed"); 4009 4010 return (USB_NO_RESOURCES); 4011 } 4012 4013 /* Save current isochronous request pointer */ 4014 tw->tw_curr_xfer_reqp = (usb_opaque_t)isoc_req; 4015 4016 /* 4017 * Initialize the transfer wrapper. These values are useful 4018 * for sending back the reply. 4019 */ 4020 tw->tw_handle_td = uhci_handle_isoc_td; 4021 tw->tw_handle_callback_value = NULL; 4022 tw->tw_direction = (UHCI_XFER_DIR(&ph->p_ep) == USB_EP_DIR_OUT) ? 4023 PID_OUT : PID_IN; 4024 4025 /* 4026 * If the transfer isoc send, then copy the data from the request 4027 * to the transfer wrapper. 4028 */ 4029 if ((tw->tw_direction == PID_OUT) && length) { 4030 uchar_t *p; 4031 4032 ASSERT(isoc_req->isoc_data != NULL); 4033 p = isoc_req->isoc_data->b_rptr; 4034 4035 /* Copy the data into the message */ 4036 for (i = 0; i < isoc_req->isoc_pkts_count; i++) { 4037 ddi_rep_put8(tw->tw_isoc_bufs[i].mem_handle, 4038 p, (uint8_t *)tw->tw_isoc_bufs[i].buf_addr, 4039 isoc_req->isoc_pkt_descr[i].isoc_pkt_length, 4040 DDI_DEV_AUTOINCR); 4041 p += isoc_req->isoc_pkt_descr[i].isoc_pkt_length; 4042 } 4043 } 4044 4045 if (tw->tw_direction == PID_IN) { 4046 if ((rval = uhci_allocate_periodic_in_resource(uhcip, pp, tw, 4047 flags)) != USB_SUCCESS) { 4048 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4049 "uhci_insert_isoc_td: isoc_req_t alloc failed"); 4050 uhci_deallocate_tw(uhcip, pp, tw); 4051 4052 return (rval); 4053 } 4054 4055 isoc_req = (usb_isoc_req_t *)tw->tw_curr_xfer_reqp; 4056 } 4057 4058 tw->tw_isoc_req = (usb_isoc_req_t *)tw->tw_curr_xfer_reqp; 4059 4060 /* Get the pointer to the isoc_xfer_info structure */ 4061 isoc_xfer_info = (uhci_bulk_isoc_xfer_t *)&tw->tw_xfer_info; 4062 isoc_xfer_info->num_tds = isoc_req->isoc_pkts_count; 4063 4064 /* 4065 * Allocate memory for isoc tds 4066 */ 4067 if ((rval = uhci_alloc_bulk_isoc_tds(uhcip, isoc_req->isoc_pkts_count, 4068 isoc_xfer_info)) != USB_SUCCESS) { 4069 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4070 "uhci_alloc_bulk_isoc_td: Memory allocation failure"); 4071 4072 if (tw->tw_direction == PID_IN) { 4073 uhci_deallocate_periodic_in_resource(uhcip, pp, tw); 4074 } 4075 uhci_deallocate_tw(uhcip, pp, tw); 4076 4077 return (rval); 4078 } 4079 4080 /* 4081 * Get the isoc td pool address, buffer address and 4082 * max packet size that the device supports. 4083 */ 4084 td_pool_ptr = &isoc_xfer_info->td_pools[0]; 4085 td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr; 4086 index = 0; 4087 4088 /* 4089 * Fill up the isoc tds 4090 */ 4091 USB_DPRINTF_L3(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4092 "uhci_insert_isoc_td : isoc pkts %d", isoc_req->isoc_pkts_count); 4093 4094 for (i = 0; i < isoc_xfer_info->num_pools; i++) { 4095 for (j = 0; j < td_pool_ptr->num_tds; j++) { 4096 bytes_to_xfer = 4097 isoc_req->isoc_pkt_descr[index].isoc_pkt_length; 4098 4099 uhci_fill_in_bulk_isoc_td(uhcip, &td_ptr[j], 4100 (uhci_td_t *)NULL, HC_END_OF_LIST, ph, index, 4101 bytes_to_xfer, tw); 4102 td_ptr[j].isoc_pkt_index = index; 4103 index++; 4104 } 4105 4106 if (i < (isoc_xfer_info->num_pools - 1)) { 4107 td_pool_ptr = &isoc_xfer_info->td_pools[i + 1]; 4108 td_ptr = (uhci_td_t *)td_pool_ptr->pool_addr; 4109 } 4110 } 4111 4112 /* 4113 * Get the starting frame number. 4114 * The client drivers sets the flag USB_ATTRS_ISOC_XFER_ASAP to inform 4115 * the HCD to care of starting frame number. 4116 * 4117 * Following code is very time critical. So, perform atomic execution. 4118 */ 4119 ddic = ddi_enter_critical(); 4120 current_frame = uhci_get_sw_frame_number(uhcip); 4121 4122 if (isoc_req->isoc_attributes & USB_ATTRS_ISOC_START_FRAME) { 4123 start_frame = isoc_req->isoc_frame_no; 4124 end_frame = start_frame + isoc_req->isoc_pkts_count; 4125 4126 /* Check available frames */ 4127 if ((end_frame - current_frame) < UHCI_MAX_ISOC_FRAMES) { 4128 if (current_frame > start_frame) { 4129 if ((current_frame + FRNUM_OFFSET) < 4130 end_frame) { 4131 expired_frames = current_frame + 4132 FRNUM_OFFSET - start_frame; 4133 start_frame = current_frame + 4134 FRNUM_OFFSET; 4135 } else { 4136 rval = USB_INVALID_START_FRAME; 4137 } 4138 } 4139 } else { 4140 rval = USB_INVALID_START_FRAME; 4141 } 4142 4143 } else if (isoc_req->isoc_attributes & USB_ATTRS_ISOC_XFER_ASAP) { 4144 start_frame = pp->pp_frame_num; 4145 4146 if (start_frame == INVALID_FRNUM) { 4147 start_frame = current_frame + FRNUM_OFFSET; 4148 } else if (current_frame > start_frame) { 4149 start_frame = current_frame + FRNUM_OFFSET; 4150 } 4151 4152 end_frame = start_frame + isoc_req->isoc_pkts_count; 4153 isoc_req->isoc_frame_no = start_frame; 4154 4155 } 4156 4157 if (rval != USB_SUCCESS) { 4158 4159 /* Exit the critical */ 4160 ddi_exit_critical(ddic); 4161 4162 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4163 "uhci_insert_isoc_td: Invalid starting frame number"); 4164 4165 if (tw->tw_direction == PID_IN) { 4166 uhci_deallocate_periodic_in_resource(uhcip, pp, tw); 4167 } 4168 4169 while (tw->tw_hctd_head) { 4170 uhci_delete_td(uhcip, tw->tw_hctd_head); 4171 } 4172 4173 for (i = 0; i < isoc_xfer_info->num_pools; i++) { 4174 td_pool_ptr = &isoc_xfer_info->td_pools[i]; 4175 error = ddi_dma_unbind_handle(td_pool_ptr->dma_handle); 4176 ASSERT(error == DDI_SUCCESS); 4177 ddi_dma_mem_free(&td_pool_ptr->mem_handle); 4178 ddi_dma_free_handle(&td_pool_ptr->dma_handle); 4179 } 4180 kmem_free(isoc_xfer_info->td_pools, 4181 (sizeof (uhci_bulk_isoc_td_pool_t) * 4182 isoc_xfer_info->num_pools)); 4183 4184 uhci_deallocate_tw(uhcip, pp, tw); 4185 4186 return (rval); 4187 } 4188 4189 for (i = 0; i < expired_frames; i++) { 4190 isoc_req->isoc_pkt_descr[i].isoc_pkt_status = 4191 USB_CR_NOT_ACCESSED; 4192 isoc_req->isoc_pkt_descr[i].isoc_pkt_actual_length = 4193 isoc_req->isoc_pkt_descr[i].isoc_pkt_length; 4194 uhci_get_isoc_td_by_index(uhcip, isoc_xfer_info, i, 4195 &td_ptr, &td_pool_ptr); 4196 uhci_delete_td(uhcip, td_ptr); 4197 --isoc_xfer_info->num_tds; 4198 } 4199 4200 /* 4201 * Add the TD's to the HC list 4202 */ 4203 start_frame = (start_frame & 0x3ff); 4204 for (; i < isoc_req->isoc_pkts_count; i++) { 4205 uhci_get_isoc_td_by_index(uhcip, isoc_xfer_info, i, 4206 &td_ptr, &td_pool_ptr); 4207 if (uhcip->uhci_isoc_q_tailp[start_frame]) { 4208 td_ptr->isoc_prev = 4209 uhcip->uhci_isoc_q_tailp[start_frame]; 4210 td_ptr->isoc_next = NULL; 4211 td_ptr->link_ptr = 4212 uhcip->uhci_isoc_q_tailp[start_frame]->link_ptr; 4213 uhcip->uhci_isoc_q_tailp[start_frame]->isoc_next = 4214 td_ptr; 4215 SetTD32(uhcip, 4216 uhcip->uhci_isoc_q_tailp[start_frame]->link_ptr, 4217 ISOCTD_PADDR(td_pool_ptr, td_ptr)); 4218 uhcip->uhci_isoc_q_tailp[start_frame] = td_ptr; 4219 } else { 4220 uhcip->uhci_isoc_q_tailp[start_frame] = td_ptr; 4221 td_ptr->isoc_next = NULL; 4222 td_ptr->isoc_prev = NULL; 4223 SetTD32(uhcip, td_ptr->link_ptr, 4224 GetFL32(uhcip, 4225 uhcip->uhci_frame_lst_tablep[start_frame])); 4226 SetFL32(uhcip, 4227 uhcip->uhci_frame_lst_tablep[start_frame], 4228 ISOCTD_PADDR(td_pool_ptr, td_ptr)); 4229 } 4230 td_ptr->starting_frame = start_frame; 4231 4232 if (++start_frame == NUM_FRAME_LST_ENTRIES) 4233 start_frame = 0; 4234 } 4235 4236 ddi_exit_critical(ddic); 4237 pp->pp_frame_num = end_frame; 4238 4239 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4240 "uhci_insert_isoc_td: current frame number 0x%llx, pipe frame num" 4241 " 0x%llx", current_frame, pp->pp_frame_num); 4242 4243 return (rval); 4244 } 4245 4246 4247 /* 4248 * uhci_get_isoc_td_by_index: 4249 * Obtain the addresses of the TD pool and the TD at the index. 4250 * 4251 * tdpp - pointer to the address of the TD at the isoc packet index 4252 * td_pool_pp - pointer to the address of the TD pool containing 4253 * the specified TD 4254 */ 4255 /* ARGSUSED */ 4256 static void 4257 uhci_get_isoc_td_by_index( 4258 uhci_state_t *uhcip, 4259 uhci_bulk_isoc_xfer_t *info, 4260 uint_t index, 4261 uhci_td_t **tdpp, 4262 uhci_bulk_isoc_td_pool_t **td_pool_pp) 4263 { 4264 uint_t i = 0, j = 0; 4265 uhci_td_t *td_ptr; 4266 4267 while (j < info->num_pools) { 4268 if ((i + info->td_pools[j].num_tds) <= index) { 4269 i += info->td_pools[j].num_tds; 4270 j++; 4271 } else { 4272 i = index - i; 4273 4274 break; 4275 } 4276 } 4277 4278 ASSERT(j < info->num_pools); 4279 *td_pool_pp = &info->td_pools[j]; 4280 td_ptr = (uhci_td_t *)((*td_pool_pp)->pool_addr); 4281 *tdpp = &td_ptr[i]; 4282 } 4283 4284 4285 /* 4286 * uhci_handle_isoc_td: 4287 * Handles the completed isoc tds 4288 */ 4289 void 4290 uhci_handle_isoc_td(uhci_state_t *uhcip, uhci_td_t *td) 4291 { 4292 uint_t rval, i; 4293 uint32_t pkt_index = td->isoc_pkt_index; 4294 usb_cr_t cr; 4295 uhci_trans_wrapper_t *tw = td->tw; 4296 usb_isoc_req_t *isoc_req = (usb_isoc_req_t *)tw->tw_isoc_req; 4297 uhci_pipe_private_t *pp = tw->tw_pipe_private; 4298 uhci_bulk_isoc_xfer_t *isoc_xfer_info = &tw->tw_xfer_info; 4299 usba_pipe_handle_data_t *usb_pp; 4300 uhci_bulk_isoc_td_pool_t *td_pool_ptr; 4301 4302 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4303 "uhci_handle_isoc_td: td = 0x%p, pp = 0x%p, tw = 0x%p, req = 0x%p, " 4304 "index = %x", td, pp, tw, isoc_req, pkt_index); 4305 4306 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4307 4308 usb_pp = pp->pp_pipe_handle; 4309 4310 /* 4311 * Check whether there are any errors occurred. If so, update error 4312 * count and return it to the upper.But never return a non zero 4313 * completion reason. 4314 */ 4315 cr = USB_CR_OK; 4316 if (GetTD_status(uhcip, td) & TD_STATUS_MASK) { 4317 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4318 "uhci_handle_isoc_td: Error Occurred: TD Status = %x", 4319 GetTD_status(uhcip, td)); 4320 isoc_req->isoc_error_count++; 4321 } 4322 4323 if (isoc_req != NULL) { 4324 isoc_req->isoc_pkt_descr[pkt_index].isoc_pkt_status = cr; 4325 isoc_req->isoc_pkt_descr[pkt_index].isoc_pkt_actual_length = 4326 (GetTD_alen(uhcip, td) == ZERO_LENGTH) ? 0 : 4327 GetTD_alen(uhcip, td) + 1; 4328 } 4329 4330 uhci_delete_isoc_td(uhcip, td); 4331 4332 if (--isoc_xfer_info->num_tds != 0) { 4333 USB_DPRINTF_L3(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4334 "uhci_handle_isoc_td: Number of TDs %d", 4335 isoc_xfer_info->num_tds); 4336 4337 return; 4338 } 4339 4340 tw->tw_claim = UHCI_INTR_HDLR_CLAIMED; 4341 if (tw->tw_direction == PID_IN) { 4342 uhci_sendup_td_message(uhcip, cr, tw); 4343 4344 if ((uhci_handle_isoc_receive(uhcip, pp, tw)) != USB_SUCCESS) { 4345 USB_DPRINTF_L3(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4346 "uhci_handle_isoc_td: Drop message"); 4347 } 4348 4349 } else { 4350 /* update kstats only for OUT. sendup_td_msg() does it for IN */ 4351 uhci_do_byte_stats(uhcip, tw->tw_length, 4352 usb_pp->p_ep.bmAttributes, usb_pp->p_ep.bEndpointAddress); 4353 4354 uhci_hcdi_callback(uhcip, pp, usb_pp, tw, USB_CR_OK); 4355 } 4356 4357 for (i = 0; i < isoc_xfer_info->num_pools; i++) { 4358 td_pool_ptr = &isoc_xfer_info->td_pools[i]; 4359 rval = ddi_dma_unbind_handle(td_pool_ptr->dma_handle); 4360 ASSERT(rval == DDI_SUCCESS); 4361 ddi_dma_mem_free(&td_pool_ptr->mem_handle); 4362 ddi_dma_free_handle(&td_pool_ptr->dma_handle); 4363 } 4364 kmem_free(isoc_xfer_info->td_pools, 4365 (sizeof (uhci_bulk_isoc_td_pool_t) * 4366 isoc_xfer_info->num_pools)); 4367 uhci_deallocate_tw(uhcip, pp, tw); 4368 } 4369 4370 4371 /* 4372 * uhci_handle_isoc_receive: 4373 * - Sends the isoc data to the client 4374 * - Inserts another isoc receive request 4375 */ 4376 static int 4377 uhci_handle_isoc_receive( 4378 uhci_state_t *uhcip, 4379 uhci_pipe_private_t *pp, 4380 uhci_trans_wrapper_t *tw) 4381 { 4382 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4383 "uhci_handle_isoc_receive: tw = 0x%p", tw); 4384 4385 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4386 4387 /* 4388 * -- check for pipe state being polling before 4389 * inserting a new request. Check when is TD 4390 * de-allocation being done? (so we can reuse the same TD) 4391 */ 4392 if (uhci_start_isoc_receive_polling(uhcip, 4393 pp->pp_pipe_handle, (usb_isoc_req_t *)tw->tw_curr_xfer_reqp, 4394 0) != USB_SUCCESS) { 4395 USB_DPRINTF_L2(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4396 "uhci_handle_isoc_receive: receive polling failed"); 4397 4398 return (USB_FAILURE); 4399 } 4400 4401 return (USB_SUCCESS); 4402 } 4403 4404 4405 /* 4406 * uhci_delete_isoc_td: 4407 * - Delete from the outstanding command queue 4408 * - Delete from the tw queue 4409 * - Delete from the isoc queue 4410 * - Delete from the HOST CONTROLLER list 4411 */ 4412 static void 4413 uhci_delete_isoc_td(uhci_state_t *uhcip, uhci_td_t *td) 4414 { 4415 uint32_t starting_frame = td->starting_frame; 4416 4417 if ((td->isoc_next == NULL) && (td->isoc_prev == NULL)) { 4418 SetFL32(uhcip, uhcip->uhci_frame_lst_tablep[starting_frame], 4419 GetTD32(uhcip, td->link_ptr)); 4420 uhcip->uhci_isoc_q_tailp[starting_frame] = 0; 4421 } else if (td->isoc_next == NULL) { 4422 td->isoc_prev->link_ptr = td->link_ptr; 4423 td->isoc_prev->isoc_next = NULL; 4424 uhcip->uhci_isoc_q_tailp[starting_frame] = td->isoc_prev; 4425 } else if (td->isoc_prev == NULL) { 4426 td->isoc_next->isoc_prev = NULL; 4427 SetFL32(uhcip, uhcip->uhci_frame_lst_tablep[starting_frame], 4428 GetTD32(uhcip, td->link_ptr)); 4429 } else { 4430 td->isoc_prev->isoc_next = td->isoc_next; 4431 td->isoc_next->isoc_prev = td->isoc_prev; 4432 td->isoc_prev->link_ptr = td->link_ptr; 4433 } 4434 4435 uhci_delete_td(uhcip, td); 4436 } 4437 4438 4439 /* 4440 * uhci_send_isoc_receive 4441 * - Allocates usb_isoc_request 4442 * - Updates the isoc request 4443 * - Inserts the isoc td's into the HC processing list. 4444 */ 4445 int 4446 uhci_start_isoc_receive_polling( 4447 uhci_state_t *uhcip, 4448 usba_pipe_handle_data_t *ph, 4449 usb_isoc_req_t *isoc_req, 4450 usb_flags_t usb_flags) 4451 { 4452 int ii, error; 4453 size_t max_isoc_xfer_size, length, isoc_pkts_length; 4454 ushort_t isoc_pkt_count; 4455 uhci_pipe_private_t *pp = (uhci_pipe_private_t *)ph->p_hcd_private; 4456 usb_isoc_pkt_descr_t *isoc_pkt_descr; 4457 4458 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4459 "uhci_start_isoc_receive_polling: usb_flags = %x", usb_flags); 4460 4461 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4462 4463 max_isoc_xfer_size = ph->p_ep.wMaxPacketSize * UHCI_MAX_ISOC_PKTS; 4464 4465 if (isoc_req) { 4466 isoc_pkt_descr = isoc_req->isoc_pkt_descr; 4467 isoc_pkt_count = isoc_req->isoc_pkts_count; 4468 isoc_pkts_length = isoc_req->isoc_pkts_length; 4469 } else { 4470 isoc_pkt_descr = ((usb_isoc_req_t *) 4471 pp->pp_client_periodic_in_reqp)->isoc_pkt_descr; 4472 isoc_pkt_count = ((usb_isoc_req_t *) 4473 pp->pp_client_periodic_in_reqp)->isoc_pkts_count; 4474 isoc_pkts_length = ((usb_isoc_req_t *) 4475 pp->pp_client_periodic_in_reqp)->isoc_pkts_length; 4476 } 4477 4478 for (ii = 0, length = 0; ii < isoc_pkt_count; ii++) { 4479 length += isoc_pkt_descr->isoc_pkt_length; 4480 isoc_pkt_descr++; 4481 } 4482 4483 if ((isoc_pkts_length) && (isoc_pkts_length != length)) { 4484 4485 USB_DPRINTF_L2(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 4486 "uhci_start_isoc_receive_polling: isoc_pkts_length 0x%x " 4487 "is not equal to the sum of all pkt lengths 0x%x in " 4488 "an isoc request", isoc_pkts_length, length); 4489 4490 return (USB_FAILURE); 4491 } 4492 4493 /* Check the size of isochronous request */ 4494 if (length > max_isoc_xfer_size) { 4495 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4496 "uhci_start_isoc_receive_polling: " 4497 "Max isoc request size = %lx, Given isoc req size = %lx", 4498 max_isoc_xfer_size, length); 4499 4500 return (USB_FAILURE); 4501 } 4502 4503 /* Add the TD into the Host Controller's isoc list */ 4504 error = uhci_insert_isoc_td(uhcip, ph, isoc_req, length, usb_flags); 4505 4506 return (error); 4507 } 4508 4509 4510 /* 4511 * uhci_remove_isoc_tds_tws 4512 * This routine scans the pipe and removes all the td's 4513 * and transfer wrappers and deallocates the memory 4514 * associated with those td's and tw's. 4515 */ 4516 void 4517 uhci_remove_isoc_tds_tws(uhci_state_t *uhcip, uhci_pipe_private_t *pp) 4518 { 4519 uint_t rval, i; 4520 uhci_td_t *tmp_td, *td_head; 4521 usb_isoc_req_t *isoc_req; 4522 uhci_trans_wrapper_t *tmp_tw, *tw_head; 4523 uhci_bulk_isoc_xfer_t *isoc_xfer_info; 4524 uhci_bulk_isoc_td_pool_t *td_pool_ptr; 4525 4526 USB_DPRINTF_L4(PRINT_MASK_ISOC, uhcip->uhci_log_hdl, 4527 "uhci_remove_isoc_tds_tws: pp = %p", (void *)pp); 4528 4529 tw_head = pp->pp_tw_head; 4530 while (tw_head) { 4531 tmp_tw = tw_head; 4532 tw_head = tw_head->tw_next; 4533 td_head = tmp_tw->tw_hctd_head; 4534 if (tmp_tw->tw_direction == PID_IN) { 4535 uhci_deallocate_periodic_in_resource(uhcip, pp, 4536 tmp_tw); 4537 } else if (tmp_tw->tw_direction == PID_OUT) { 4538 uhci_hcdi_callback(uhcip, pp, pp->pp_pipe_handle, 4539 tmp_tw, USB_CR_FLUSHED); 4540 } 4541 4542 while (td_head) { 4543 tmp_td = td_head; 4544 td_head = td_head->tw_td_next; 4545 uhci_delete_isoc_td(uhcip, tmp_td); 4546 } 4547 4548 isoc_req = (usb_isoc_req_t *)tmp_tw->tw_isoc_req; 4549 if (isoc_req) { 4550 usb_free_isoc_req(isoc_req); 4551 } 4552 4553 ASSERT(tmp_tw->tw_hctd_head == NULL); 4554 4555 if (tmp_tw->tw_xfer_info.td_pools) { 4556 isoc_xfer_info = 4557 (uhci_bulk_isoc_xfer_t *)&tmp_tw->tw_xfer_info; 4558 for (i = 0; i < isoc_xfer_info->num_pools; i++) { 4559 td_pool_ptr = &isoc_xfer_info->td_pools[i]; 4560 rval = ddi_dma_unbind_handle( 4561 td_pool_ptr->dma_handle); 4562 ASSERT(rval == DDI_SUCCESS); 4563 ddi_dma_mem_free(&td_pool_ptr->mem_handle); 4564 ddi_dma_free_handle(&td_pool_ptr->dma_handle); 4565 } 4566 kmem_free(isoc_xfer_info->td_pools, 4567 (sizeof (uhci_bulk_isoc_td_pool_t) * 4568 isoc_xfer_info->num_pools)); 4569 } 4570 4571 uhci_deallocate_tw(uhcip, pp, tmp_tw); 4572 } 4573 } 4574 4575 4576 /* 4577 * uhci_isoc_update_sw_frame_number() 4578 * to avoid code duplication, call uhci_get_sw_frame_number() 4579 */ 4580 void 4581 uhci_isoc_update_sw_frame_number(uhci_state_t *uhcip) 4582 { 4583 (void) uhci_get_sw_frame_number(uhcip); 4584 } 4585 4586 4587 /* 4588 * uhci_get_sw_frame_number: 4589 * Hold the uhci_int_mutex before calling this routine. 4590 */ 4591 uint64_t 4592 uhci_get_sw_frame_number(uhci_state_t *uhcip) 4593 { 4594 uint64_t sw_frnum, hw_frnum, current_frnum; 4595 4596 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4597 4598 sw_frnum = uhcip->uhci_sw_frnum; 4599 hw_frnum = Get_OpReg16(FRNUM); 4600 4601 /* 4602 * Check bit 10 in the software counter and hardware frame counter. 4603 * If both are same, then don't increment the software frame counter 4604 * (Bit 10 of hw frame counter toggle for every 1024 frames) 4605 * The lower 11 bits of software counter contains the hardware frame 4606 * counter value. The MSB (bit 10) of software counter is incremented 4607 * for every 1024 frames either here or in get frame number routine. 4608 */ 4609 if ((sw_frnum & UHCI_BIT_10_MASK) == (hw_frnum & UHCI_BIT_10_MASK)) { 4610 /* The MSB of hw counter did not toggle */ 4611 current_frnum = ((sw_frnum & (SW_FRNUM_MASK)) | hw_frnum); 4612 } else { 4613 /* 4614 * The hw counter wrapped around. And the interrupt handler 4615 * did not get a chance to update the sw frame counter. 4616 * So, update the sw frame counter and return correct frame no. 4617 */ 4618 sw_frnum >>= UHCI_SIZE_OF_HW_FRNUM - 1; 4619 current_frnum = 4620 ((++sw_frnum << (UHCI_SIZE_OF_HW_FRNUM - 1)) | hw_frnum); 4621 } 4622 uhcip->uhci_sw_frnum = current_frnum; 4623 4624 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 4625 "uhci_get_sw_frame_number: sw=%ld hd=%ld", 4626 uhcip->uhci_sw_frnum, hw_frnum); 4627 4628 return (current_frnum); 4629 } 4630 4631 4632 /* 4633 * uhci_cmd_timeout_hdlr: 4634 * This routine will get called for every second. It checks for 4635 * timed out control commands/bulk commands. Timeout any commands 4636 * that exceeds the time out period specified by the pipe policy. 4637 */ 4638 void 4639 uhci_cmd_timeout_hdlr(void *arg) 4640 { 4641 uint_t flag = B_FALSE; 4642 uhci_td_t *head, *tmp_td; 4643 uhci_state_t *uhcip = (uhci_state_t *)arg; 4644 uhci_pipe_private_t *pp; 4645 4646 /* 4647 * Check whether any of the control xfers are timed out. 4648 * If so, complete those commands with time out as reason. 4649 */ 4650 mutex_enter(&uhcip->uhci_int_mutex); 4651 head = uhcip->uhci_outst_tds_head; 4652 4653 while (head) { 4654 /* 4655 * If timeout out is zero, then dont timeout command. 4656 */ 4657 if (head->tw->tw_timeout_cnt == 0) { 4658 head = head->outst_td_next; 4659 continue; 4660 } 4661 4662 if (!(head->tw->tw_flags & TW_TIMEOUT_FLAG)) { 4663 head->tw->tw_flags |= TW_TIMEOUT_FLAG; 4664 --head->tw->tw_timeout_cnt; 4665 } 4666 4667 /* only do it for bulk and control TDs */ 4668 if ((head->tw->tw_timeout_cnt == 0) && 4669 (head->tw->tw_handle_td != uhci_handle_isoc_td)) { 4670 4671 USB_DPRINTF_L3(PRINT_MASK_ATTA, uhcip->uhci_log_hdl, 4672 "Command timed out: td = %p", (void *)head); 4673 4674 head->tw->tw_claim = UHCI_TIMEOUT_HDLR_CLAIMED; 4675 4676 /* 4677 * Check finally whether the command completed 4678 */ 4679 if (GetTD_status(uhcip, head) & UHCI_TD_ACTIVE) { 4680 SetTD32(uhcip, head->link_ptr, 4681 GetTD32(uhcip, head->link_ptr) | 4682 HC_END_OF_LIST); 4683 pp = head->tw->tw_pipe_private; 4684 SetQH32(uhcip, pp->pp_qh->element_ptr, 4685 GetQH32(uhcip, pp->pp_qh->element_ptr) | 4686 HC_END_OF_LIST); 4687 } 4688 4689 flag = B_TRUE; 4690 } 4691 4692 head = head->outst_td_next; 4693 } 4694 4695 if (flag) { 4696 (void) uhci_wait_for_sof(uhcip); 4697 } 4698 4699 head = uhcip->uhci_outst_tds_head; 4700 while (head) { 4701 if (head->tw->tw_flags & TW_TIMEOUT_FLAG) { 4702 head->tw->tw_flags &= ~TW_TIMEOUT_FLAG; 4703 } 4704 if (head->tw->tw_claim == UHCI_TIMEOUT_HDLR_CLAIMED) { 4705 head->tw->tw_claim = UHCI_NOT_CLAIMED; 4706 tmp_td = head->tw->tw_hctd_head; 4707 while (tmp_td) { 4708 SetTD_status(uhcip, tmp_td, 4709 UHCI_TD_CRC_TIMEOUT); 4710 tmp_td = tmp_td->tw_td_next; 4711 } 4712 } 4713 head = head->outst_td_next; 4714 } 4715 4716 /* 4717 * Process the td which was completed before shifting from normal 4718 * mode to polled mode 4719 */ 4720 if (uhcip->uhci_polled_flag == UHCI_POLLED_FLAG_TRUE) { 4721 uhci_process_submitted_td_queue(uhcip); 4722 uhcip->uhci_polled_flag = UHCI_POLLED_FLAG_FALSE; 4723 } else if (flag) { 4724 /* Process the completed/timed out commands */ 4725 uhci_process_submitted_td_queue(uhcip); 4726 } 4727 4728 /* Re-register the control/bulk/intr commands' timeout handler */ 4729 if (uhcip->uhci_cmd_timeout_id) { 4730 uhcip->uhci_cmd_timeout_id = timeout(uhci_cmd_timeout_hdlr, 4731 (void *)uhcip, UHCI_ONE_SECOND); 4732 } 4733 4734 mutex_exit(&uhcip->uhci_int_mutex); 4735 } 4736 4737 4738 /* 4739 * uhci_wait_for_sof: 4740 * Wait for the start of the next frame (implying any changes made in the 4741 * lattice have now taken effect). 4742 * To be sure this is the case, we wait for the completion of the current 4743 * frame (which might have already been pending), then another complete 4744 * frame to ensure everything has taken effect. 4745 */ 4746 int 4747 uhci_wait_for_sof(uhci_state_t *uhcip) 4748 { 4749 int n, error; 4750 ushort_t cmd_reg; 4751 usb_frame_number_t before_frame_number, after_frame_number; 4752 clock_t time, rval; 4753 USB_DPRINTF_L4(PRINT_MASK_LISTS, uhcip->uhci_log_hdl, 4754 "uhci_wait_for_sof: uhcip = %p", uhcip); 4755 4756 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4757 4758 error = uhci_state_is_operational(uhcip); 4759 4760 if (error != USB_SUCCESS) { 4761 4762 return (error); 4763 } 4764 4765 before_frame_number = uhci_get_sw_frame_number(uhcip); 4766 for (n = 0; n < MAX_SOF_WAIT_COUNT; n++) { 4767 SetTD_ioc(uhcip, uhcip->uhci_sof_td, 1); 4768 uhcip->uhci_cv_signal = B_TRUE; 4769 4770 time = ddi_get_lbolt() + UHCI_ONE_SECOND; 4771 rval = cv_timedwait(&uhcip->uhci_cv_SOF, 4772 &uhcip->uhci_int_mutex, time); 4773 4774 after_frame_number = uhci_get_sw_frame_number(uhcip); 4775 if ((rval == -1) && 4776 (after_frame_number <= before_frame_number)) { 4777 cmd_reg = Get_OpReg16(USBCMD); 4778 Set_OpReg16(USBCMD, (cmd_reg | USBCMD_REG_HC_RUN)); 4779 Set_OpReg16(USBINTR, ENABLE_ALL_INTRS); 4780 after_frame_number = uhci_get_sw_frame_number(uhcip); 4781 } 4782 before_frame_number = after_frame_number; 4783 } 4784 4785 SetTD_ioc(uhcip, uhcip->uhci_sof_td, 0); 4786 4787 return (uhcip->uhci_cv_signal ? USB_FAILURE : USB_SUCCESS); 4788 4789 } 4790 4791 /* 4792 * uhci_allocate_periodic_in_resource: 4793 * Allocate interrupt/isochronous request structure for the 4794 * interrupt/isochronous IN transfer. 4795 */ 4796 int 4797 uhci_allocate_periodic_in_resource( 4798 uhci_state_t *uhcip, 4799 uhci_pipe_private_t *pp, 4800 uhci_trans_wrapper_t *tw, 4801 usb_flags_t flags) 4802 { 4803 size_t length = 0; 4804 usb_opaque_t client_periodic_in_reqp; 4805 usb_intr_req_t *cur_intr_req; 4806 usb_isoc_req_t *curr_isoc_reqp; 4807 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 4808 4809 USB_DPRINTF_L4(PRINT_MASK_HCDI, uhcip->uhci_log_hdl, 4810 "uhci_allocate_periodic_in_resource:\n\t" 4811 "ph = 0x%p, pp = 0x%p, tw = 0x%p, flags = 0x%x", ph, pp, tw, flags); 4812 4813 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4814 4815 /* Check the current periodic in request pointer */ 4816 if (tw->tw_curr_xfer_reqp) { 4817 USB_DPRINTF_L2(PRINT_MASK_HCDI, uhcip->uhci_log_hdl, 4818 "uhci_allocate_periodic_in_resource: Interrupt " 4819 "request structure already exists: " 4820 "allocation failed"); 4821 4822 return (USB_SUCCESS); 4823 } 4824 4825 /* Get the client periodic in request pointer */ 4826 client_periodic_in_reqp = pp->pp_client_periodic_in_reqp; 4827 4828 /* 4829 * If it a periodic IN request and periodic request is NULL, 4830 * allocate corresponding usb periodic IN request for the 4831 * current periodic polling request and copy the information 4832 * from the saved periodic request structure. 4833 */ 4834 if (UHCI_XFER_TYPE(&ph->p_ep) == USB_EP_ATTR_INTR) { 4835 /* Get the interrupt transfer length */ 4836 length = ((usb_intr_req_t *)client_periodic_in_reqp)-> 4837 intr_len; 4838 4839 cur_intr_req = usba_hcdi_dup_intr_req(ph->p_dip, 4840 (usb_intr_req_t *)client_periodic_in_reqp, length, flags); 4841 if (cur_intr_req == NULL) { 4842 USB_DPRINTF_L2(PRINT_MASK_HCDI, uhcip->uhci_log_hdl, 4843 "uhci_allocate_periodic_in_resource: Interrupt " 4844 "request structure allocation failed"); 4845 4846 return (USB_NO_RESOURCES); 4847 } 4848 4849 /* Check and save the timeout value */ 4850 tw->tw_timeout_cnt = (cur_intr_req->intr_attributes & 4851 USB_ATTRS_ONE_XFER) ? cur_intr_req->intr_timeout: 0; 4852 tw->tw_curr_xfer_reqp = (usb_opaque_t)cur_intr_req; 4853 tw->tw_length = cur_intr_req->intr_len; 4854 } else { 4855 ASSERT(client_periodic_in_reqp != NULL); 4856 4857 if ((curr_isoc_reqp = usba_hcdi_dup_isoc_req(ph->p_dip, 4858 (usb_isoc_req_t *)client_periodic_in_reqp, flags)) == 4859 NULL) { 4860 USB_DPRINTF_L2(PRINT_MASK_HCDI, uhcip->uhci_log_hdl, 4861 "uhci_allocate_periodic_in_resource: Isochronous " 4862 "request structure allocation failed"); 4863 4864 return (USB_NO_RESOURCES); 4865 } 4866 4867 /* 4868 * Save the client's isochronous request pointer and 4869 * length of isochronous transfer in transfer wrapper. 4870 * The dup'ed request is saved in pp_client_periodic_in_reqp 4871 */ 4872 tw->tw_curr_xfer_reqp = 4873 (usb_opaque_t)pp->pp_client_periodic_in_reqp; 4874 pp->pp_client_periodic_in_reqp = (usb_opaque_t)curr_isoc_reqp; 4875 } 4876 4877 mutex_enter(&ph->p_mutex); 4878 ph->p_req_count++; 4879 mutex_exit(&ph->p_mutex); 4880 4881 return (USB_SUCCESS); 4882 } 4883 4884 4885 /* 4886 * uhci_deallocate_periodic_in_resource: 4887 * Deallocate interrupt/isochronous request structure for the 4888 * interrupt/isochronous IN transfer. 4889 */ 4890 void 4891 uhci_deallocate_periodic_in_resource( 4892 uhci_state_t *uhcip, 4893 uhci_pipe_private_t *pp, 4894 uhci_trans_wrapper_t *tw) 4895 { 4896 usb_opaque_t curr_xfer_reqp; 4897 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 4898 4899 USB_DPRINTF_L4(PRINT_MASK_HCDI, uhcip->uhci_log_hdl, 4900 "uhci_deallocate_periodic_in_resource: " 4901 "pp = 0x%p tw = 0x%p", pp, tw); 4902 4903 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4904 4905 curr_xfer_reqp = tw->tw_curr_xfer_reqp; 4906 if (curr_xfer_reqp) { 4907 /* 4908 * Reset periodic in request usb isoch 4909 * packet request pointers to null. 4910 */ 4911 tw->tw_curr_xfer_reqp = NULL; 4912 tw->tw_isoc_req = NULL; 4913 4914 mutex_enter(&ph->p_mutex); 4915 ph->p_req_count--; 4916 mutex_exit(&ph->p_mutex); 4917 4918 /* 4919 * Free pre-allocated interrupt or isochronous requests. 4920 */ 4921 switch (UHCI_XFER_TYPE(&ph->p_ep)) { 4922 case USB_EP_ATTR_INTR: 4923 usb_free_intr_req((usb_intr_req_t *)curr_xfer_reqp); 4924 break; 4925 case USB_EP_ATTR_ISOCH: 4926 usb_free_isoc_req((usb_isoc_req_t *)curr_xfer_reqp); 4927 break; 4928 } 4929 } 4930 } 4931 4932 4933 /* 4934 * uhci_hcdi_callback() 4935 * convenience wrapper around usba_hcdi_callback() 4936 */ 4937 void 4938 uhci_hcdi_callback(uhci_state_t *uhcip, uhci_pipe_private_t *pp, 4939 usba_pipe_handle_data_t *ph, uhci_trans_wrapper_t *tw, usb_cr_t cr) 4940 { 4941 usb_opaque_t curr_xfer_reqp; 4942 4943 USB_DPRINTF_L4(PRINT_MASK_HCDI, uhcip->uhci_log_hdl, 4944 "uhci_hcdi_callback: ph = 0x%p, tw = 0x%p, cr = 0x%x", ph, tw, cr); 4945 4946 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4947 4948 if (tw && tw->tw_curr_xfer_reqp) { 4949 curr_xfer_reqp = tw->tw_curr_xfer_reqp; 4950 tw->tw_curr_xfer_reqp = NULL; 4951 tw->tw_isoc_req = NULL; 4952 } else { 4953 ASSERT(pp->pp_client_periodic_in_reqp != NULL); 4954 4955 curr_xfer_reqp = pp->pp_client_periodic_in_reqp; 4956 pp->pp_client_periodic_in_reqp = NULL; 4957 } 4958 4959 ASSERT(curr_xfer_reqp != NULL); 4960 4961 mutex_exit(&uhcip->uhci_int_mutex); 4962 usba_hcdi_cb(ph, curr_xfer_reqp, cr); 4963 mutex_enter(&uhcip->uhci_int_mutex); 4964 } 4965 4966 4967 /* 4968 * uhci_state_is_operational: 4969 * 4970 * Check the Host controller state and return proper values. 4971 */ 4972 int 4973 uhci_state_is_operational(uhci_state_t *uhcip) 4974 { 4975 int val; 4976 4977 ASSERT(mutex_owned(&uhcip->uhci_int_mutex)); 4978 4979 switch (uhcip->uhci_hc_soft_state) { 4980 case UHCI_CTLR_INIT_STATE: 4981 case UHCI_CTLR_SUSPEND_STATE: 4982 val = USB_FAILURE; 4983 break; 4984 case UHCI_CTLR_OPERATIONAL_STATE: 4985 val = USB_SUCCESS; 4986 break; 4987 case UHCI_CTLR_ERROR_STATE: 4988 val = USB_HC_HARDWARE_ERROR; 4989 break; 4990 default: 4991 val = USB_FAILURE; 4992 break; 4993 } 4994 4995 return (val); 4996 } 4997 4998 4999 #ifdef DEBUG 5000 static void 5001 uhci_print_td(uhci_state_t *uhcip, uhci_td_t *td) 5002 { 5003 uint_t *ptr = (uint_t *)td; 5004 5005 #ifndef lint 5006 _NOTE(NO_COMPETING_THREADS_NOW); 5007 #endif 5008 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl, 5009 "\tDWORD 1 0x%x\t DWORD 2 0x%x", ptr[0], ptr[1]); 5010 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl, 5011 "\tDWORD 3 0x%x\t DWORD 4 0x%x", ptr[2], ptr[3]); 5012 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl, 5013 "\tBytes xfered = %d", td->tw->tw_bytes_xfered); 5014 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl, 5015 "\tBytes Pending = %d", td->tw->tw_bytes_pending); 5016 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl, 5017 "Queue Head Details:"); 5018 uhci_print_qh(uhcip, td->tw->tw_pipe_private->pp_qh); 5019 5020 #ifndef lint 5021 _NOTE(COMPETING_THREADS_NOW); 5022 #endif 5023 } 5024 5025 5026 static void 5027 uhci_print_qh(uhci_state_t *uhcip, queue_head_t *qh) 5028 { 5029 uint_t *ptr = (uint_t *)qh; 5030 5031 USB_DPRINTF_L3(PRINT_MASK_DUMPING, uhcip->uhci_log_hdl, 5032 "\tLink Ptr = %x Element Ptr = %x", ptr[0], ptr[1]); 5033 } 5034 #endif 5035