1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Open Host Controller Driver (OHCI) 30 * 31 * The USB Open Host Controller driver is a software driver which interfaces 32 * to the Universal Serial Bus layer (USBA) and the USB Open Host Controller. 33 * The interface to USB Open Host Controller is defined by the OpenHCI Host 34 * Controller Interface. 35 * 36 * NOTE: 37 * 38 * Currently OHCI driver does not support the following features 39 * 40 * - Handle request with multiple TDs under short xfer conditions except for 41 * bulk transfers. 42 */ 43 #include <sys/usb/hcd/openhci/ohcid.h> 44 45 #include <sys/disp.h> 46 47 /* Pointer to the state structure */ 48 static void *ohci_statep; 49 50 int force_ohci_off = 1; 51 52 /* Number of instances */ 53 #define OHCI_INSTS 1 54 55 /* Adjustable variables for the size of the pools */ 56 int ohci_ed_pool_size = OHCI_ED_POOL_SIZE; 57 int ohci_td_pool_size = OHCI_TD_POOL_SIZE; 58 59 /* 60 * Initialize the values which are used for setting up head pointers for 61 * the 32ms scheduling lists which starts from the HCCA. 62 */ 63 static uchar_t ohci_index[NUM_INTR_ED_LISTS / 2] = {0x0, 0x8, 0x4, 0xc, 64 0x2, 0xa, 0x6, 0xe, 65 0x1, 0x9, 0x5, 0xd, 66 0x3, 0xb, 0x7, 0xf}; 67 /* Debugging information */ 68 uint_t ohci_errmask = (uint_t)PRINT_MASK_ALL; 69 uint_t ohci_errlevel = USB_LOG_L2; 70 uint_t ohci_instance_debug = (uint_t)-1; 71 72 /* 73 * OHCI MSI tunable: 74 * 75 * By default MSI is enabled on all supported platforms. 76 */ 77 boolean_t ohci_enable_msi = B_TRUE; 78 79 /* 80 * HCDI entry points 81 * 82 * The Host Controller Driver Interfaces (HCDI) are the software interfaces 83 * between the Universal Serial Bus Driver (USBA) and the Host Controller 84 * Driver (HCD). The HCDI interfaces or entry points are subject to change. 85 */ 86 static int ohci_hcdi_pipe_open( 87 usba_pipe_handle_data_t *ph, 88 usb_flags_t usb_flags); 89 static int ohci_hcdi_pipe_close( 90 usba_pipe_handle_data_t *ph, 91 usb_flags_t usb_flags); 92 static int ohci_hcdi_pipe_reset( 93 usba_pipe_handle_data_t *ph, 94 usb_flags_t usb_flags); 95 static int ohci_hcdi_pipe_ctrl_xfer( 96 usba_pipe_handle_data_t *ph, 97 usb_ctrl_req_t *ctrl_reqp, 98 usb_flags_t usb_flags); 99 static int ohci_hcdi_bulk_transfer_size( 100 usba_device_t *usba_device, 101 size_t *size); 102 static int ohci_hcdi_pipe_bulk_xfer( 103 usba_pipe_handle_data_t *ph, 104 usb_bulk_req_t *bulk_reqp, 105 usb_flags_t usb_flags); 106 static int ohci_hcdi_pipe_intr_xfer( 107 usba_pipe_handle_data_t *ph, 108 usb_intr_req_t *intr_req, 109 usb_flags_t usb_flags); 110 static int ohci_hcdi_pipe_stop_intr_polling( 111 usba_pipe_handle_data_t *ph, 112 usb_flags_t usb_flags); 113 static int ohci_hcdi_get_current_frame_number( 114 usba_device_t *usba_device, 115 usb_frame_number_t *frame_number); 116 static int ohci_hcdi_get_max_isoc_pkts( 117 usba_device_t *usba_device, 118 uint_t *max_isoc_pkts_per_request); 119 static int ohci_hcdi_pipe_isoc_xfer( 120 usba_pipe_handle_data_t *ph, 121 usb_isoc_req_t *isoc_reqp, 122 usb_flags_t usb_flags); 123 static int ohci_hcdi_pipe_stop_isoc_polling( 124 usba_pipe_handle_data_t *ph, 125 usb_flags_t usb_flags); 126 127 /* 128 * Internal Function Prototypes 129 */ 130 131 /* Host Controller Driver (HCD) initialization functions */ 132 static void ohci_set_dma_attributes(ohci_state_t *ohcip); 133 static int ohci_allocate_pools(ohci_state_t *ohcip); 134 static void ohci_decode_ddi_dma_addr_bind_handle_result( 135 ohci_state_t *ohcip, 136 int result); 137 static int ohci_map_regs(ohci_state_t *ohcip); 138 static int ohci_register_intrs_and_init_mutex( 139 ohci_state_t *ohcip); 140 static int ohci_add_intrs(ohci_state_t *ohcip, 141 int intr_type); 142 static int ohci_init_ctlr(ohci_state_t *ohcip); 143 static int ohci_init_hcca(ohci_state_t *ohcip); 144 static void ohci_build_interrupt_lattice( 145 ohci_state_t *ohcip); 146 static int ohci_take_control(ohci_state_t *ohcip); 147 static usba_hcdi_ops_t *ohci_alloc_hcdi_ops( 148 ohci_state_t *ohcip); 149 150 /* Host Controller Driver (HCD) deinitialization functions */ 151 static int ohci_cleanup(ohci_state_t *ohcip); 152 static void ohci_rem_intrs(ohci_state_t *ohcip); 153 static int ohci_cpr_suspend(ohci_state_t *ohcip); 154 static int ohci_cpr_resume(ohci_state_t *ohcip); 155 156 /* Bandwidth Allocation functions */ 157 static int ohci_allocate_bandwidth(ohci_state_t *ohcip, 158 usba_pipe_handle_data_t *ph, 159 uint_t *node); 160 static void ohci_deallocate_bandwidth(ohci_state_t *ohcip, 161 usba_pipe_handle_data_t *ph); 162 static int ohci_compute_total_bandwidth( 163 usb_ep_descr_t *endpoint, 164 usb_port_status_t port_status, 165 uint_t *bandwidth); 166 static int ohci_adjust_polling_interval( 167 ohci_state_t *ohcip, 168 usb_ep_descr_t *endpoint, 169 usb_port_status_t port_status); 170 static uint_t ohci_lattice_height(uint_t interval); 171 static uint_t ohci_lattice_parent(uint_t node); 172 static uint_t ohci_leftmost_leaf(uint_t node, 173 uint_t height); 174 static uint_t ohci_hcca_intr_index( 175 uint_t node); 176 static uint_t ohci_hcca_leaf_index( 177 uint_t leaf); 178 static uint_t ohci_pow_2(uint_t x); 179 static uint_t ohci_log_2(uint_t x); 180 181 /* Endpoint Descriptor (ED) related functions */ 182 static uint_t ohci_unpack_endpoint(ohci_state_t *ohcip, 183 usba_pipe_handle_data_t *ph); 184 static void ohci_insert_ed(ohci_state_t *ohcip, 185 usba_pipe_handle_data_t *ph); 186 static void ohci_insert_ctrl_ed( 187 ohci_state_t *ohcip, 188 ohci_pipe_private_t *pp); 189 static void ohci_insert_bulk_ed( 190 ohci_state_t *ohcip, 191 ohci_pipe_private_t *pp); 192 static void ohci_insert_intr_ed( 193 ohci_state_t *ohcip, 194 ohci_pipe_private_t *pp); 195 static void ohci_insert_isoc_ed( 196 ohci_state_t *ohcip, 197 ohci_pipe_private_t *pp); 198 static void ohci_modify_sKip_bit(ohci_state_t *ohcip, 199 ohci_pipe_private_t *pp, 200 skip_bit_t action, 201 usb_flags_t flag); 202 static void ohci_remove_ed(ohci_state_t *ohcip, 203 ohci_pipe_private_t *pp); 204 static void ohci_remove_ctrl_ed( 205 ohci_state_t *ohcip, 206 ohci_pipe_private_t *pp); 207 static void ohci_remove_bulk_ed( 208 ohci_state_t *ohcip, 209 ohci_pipe_private_t *pp); 210 static void ohci_remove_periodic_ed( 211 ohci_state_t *ohcip, 212 ohci_pipe_private_t *pp); 213 static void ohci_insert_ed_on_reclaim_list( 214 ohci_state_t *ohcip, 215 ohci_pipe_private_t *pp); 216 static void ohci_detach_ed_from_list( 217 ohci_state_t *ohcip, 218 ohci_ed_t *ept, 219 uint_t ept_type); 220 static ohci_ed_t *ohci_ed_iommu_to_cpu( 221 ohci_state_t *ohcip, 222 uintptr_t addr); 223 224 /* Transfer Descriptor (TD) related functions */ 225 static int ohci_initialize_dummy(ohci_state_t *ohcip, 226 ohci_ed_t *ept); 227 static ohci_trans_wrapper_t *ohci_allocate_ctrl_resources( 228 ohci_state_t *ohcip, 229 ohci_pipe_private_t *pp, 230 usb_ctrl_req_t *ctrl_reqp, 231 usb_flags_t usb_flags); 232 static void ohci_insert_ctrl_req( 233 ohci_state_t *ohcip, 234 usba_pipe_handle_data_t *ph, 235 usb_ctrl_req_t *ctrl_reqp, 236 ohci_trans_wrapper_t *tw, 237 usb_flags_t usb_flags); 238 static ohci_trans_wrapper_t *ohci_allocate_bulk_resources( 239 ohci_state_t *ohcip, 240 ohci_pipe_private_t *pp, 241 usb_bulk_req_t *bulk_reqp, 242 usb_flags_t usb_flags); 243 static void ohci_insert_bulk_req(ohci_state_t *ohcip, 244 usba_pipe_handle_data_t *ph, 245 usb_bulk_req_t *bulk_reqp, 246 ohci_trans_wrapper_t *tw, 247 usb_flags_t flags); 248 static int ohci_start_pipe_polling(ohci_state_t *ohcip, 249 usba_pipe_handle_data_t *ph, 250 usb_flags_t flags); 251 static void ohci_set_periodic_pipe_polling( 252 ohci_state_t *ohcip, 253 usba_pipe_handle_data_t *ph); 254 static ohci_trans_wrapper_t *ohci_allocate_intr_resources( 255 ohci_state_t *ohcip, 256 usba_pipe_handle_data_t *ph, 257 usb_intr_req_t *intr_reqp, 258 usb_flags_t usb_flags); 259 static void ohci_insert_intr_req(ohci_state_t *ohcip, 260 ohci_pipe_private_t *pp, 261 ohci_trans_wrapper_t *tw, 262 usb_flags_t flags); 263 static int ohci_stop_periodic_pipe_polling( 264 ohci_state_t *ohcip, 265 usba_pipe_handle_data_t *ph, 266 usb_flags_t flags); 267 static ohci_trans_wrapper_t *ohci_allocate_isoc_resources( 268 ohci_state_t *ohcip, 269 usba_pipe_handle_data_t *ph, 270 usb_isoc_req_t *isoc_reqp, 271 usb_flags_t usb_flags); 272 static int ohci_insert_isoc_req(ohci_state_t *ohcip, 273 ohci_pipe_private_t *pp, 274 ohci_trans_wrapper_t *tw, 275 uint_t flags); 276 static int ohci_insert_hc_td(ohci_state_t *ohcip, 277 uint_t hctd_ctrl, 278 uint32_t hctd_dma_offs, 279 size_t hctd_length, 280 uint32_t hctd_ctrl_phase, 281 ohci_pipe_private_t *pp, 282 ohci_trans_wrapper_t *tw); 283 static ohci_td_t *ohci_allocate_td_from_pool( 284 ohci_state_t *ohcip); 285 static void ohci_fill_in_td(ohci_state_t *ohcip, 286 ohci_td_t *td, 287 ohci_td_t *new_dummy, 288 uint_t hctd_ctrl, 289 uint32_t hctd_dma_offs, 290 size_t hctd_length, 291 uint32_t hctd_ctrl_phase, 292 ohci_pipe_private_t *pp, 293 ohci_trans_wrapper_t *tw); 294 static void ohci_init_itd( 295 ohci_state_t *ohcip, 296 ohci_trans_wrapper_t *tw, 297 uint_t hctd_ctrl, 298 uint32_t index, 299 ohci_td_t *td); 300 static int ohci_insert_td_with_frame_number( 301 ohci_state_t *ohcip, 302 ohci_pipe_private_t *pp, 303 ohci_trans_wrapper_t *tw, 304 ohci_td_t *current_td, 305 ohci_td_t *dummy_td); 306 static void ohci_insert_td_on_tw(ohci_state_t *ohcip, 307 ohci_trans_wrapper_t *tw, 308 ohci_td_t *td); 309 static void ohci_done_list_tds(ohci_state_t *ohcip, 310 usba_pipe_handle_data_t *ph); 311 312 /* Transfer Wrapper (TW) functions */ 313 static ohci_trans_wrapper_t *ohci_create_transfer_wrapper( 314 ohci_state_t *ohcip, 315 ohci_pipe_private_t *pp, 316 size_t length, 317 uint_t usb_flags); 318 static ohci_trans_wrapper_t *ohci_create_isoc_transfer_wrapper( 319 ohci_state_t *ohcip, 320 ohci_pipe_private_t *pp, 321 size_t length, 322 usb_isoc_pkt_descr_t *descr, 323 ushort_t pkt_count, 324 size_t td_count, 325 uint_t usb_flags); 326 static int ohci_allocate_tds_for_tw( 327 ohci_state_t *ohcip, 328 ohci_trans_wrapper_t *tw, 329 size_t td_count); 330 static ohci_trans_wrapper_t *ohci_allocate_tw_resources( 331 ohci_state_t *ohcip, 332 ohci_pipe_private_t *pp, 333 size_t length, 334 usb_flags_t usb_flags, 335 size_t td_count); 336 static void ohci_free_tw_tds_resources( 337 ohci_state_t *ohcip, 338 ohci_trans_wrapper_t *tw); 339 static void ohci_start_xfer_timer( 340 ohci_state_t *ohcip, 341 ohci_pipe_private_t *pp, 342 ohci_trans_wrapper_t *tw); 343 static void ohci_stop_xfer_timer( 344 ohci_state_t *ohcip, 345 ohci_trans_wrapper_t *tw, 346 uint_t flag); 347 static void ohci_xfer_timeout_handler(void *arg); 348 static void ohci_remove_tw_from_timeout_list( 349 ohci_state_t *ohcip, 350 ohci_trans_wrapper_t *tw); 351 static void ohci_start_timer(ohci_state_t *ohcip); 352 static void ohci_free_dma_resources(ohci_state_t *ohcip, 353 usba_pipe_handle_data_t *ph); 354 static void ohci_free_tw(ohci_state_t *ohcip, 355 ohci_trans_wrapper_t *tw); 356 static int ohci_tw_rebind_cookie( 357 ohci_state_t *ohcip, 358 ohci_pipe_private_t *pp, 359 ohci_trans_wrapper_t *tw); 360 361 /* Interrupt Handling functions */ 362 static uint_t ohci_intr(caddr_t arg1, 363 caddr_t arg2); 364 static void ohci_handle_missed_intr( 365 ohci_state_t *ohcip); 366 static void ohci_handle_ue(ohci_state_t *ohcip); 367 static void ohci_handle_endpoint_reclaimation( 368 ohci_state_t *ohcip); 369 static void ohci_traverse_done_list( 370 ohci_state_t *ohcip, 371 ohci_td_t *head_done_list); 372 static ohci_td_t *ohci_reverse_done_list( 373 ohci_state_t *ohcip, 374 ohci_td_t *head_done_list); 375 static usb_cr_t ohci_parse_error(ohci_state_t *ohcip, 376 ohci_td_t *td); 377 static void ohci_parse_isoc_error( 378 ohci_state_t *ohcip, 379 ohci_pipe_private_t *pp, 380 ohci_trans_wrapper_t *tw, 381 ohci_td_t *td); 382 static usb_cr_t ohci_check_for_error( 383 ohci_state_t *ohcip, 384 ohci_pipe_private_t *pp, 385 ohci_trans_wrapper_t *tw, 386 ohci_td_t *td, 387 uint_t ctrl); 388 static void ohci_handle_error( 389 ohci_state_t *ohcip, 390 ohci_td_t *td, 391 usb_cr_t error); 392 static int ohci_cleanup_data_underrun( 393 ohci_state_t *ohcip, 394 ohci_pipe_private_t *pp, 395 ohci_trans_wrapper_t *tw, 396 ohci_td_t *td); 397 static void ohci_handle_normal_td( 398 ohci_state_t *ohcip, 399 ohci_td_t *td, 400 ohci_trans_wrapper_t *tw); 401 static void ohci_handle_ctrl_td(ohci_state_t *ohcip, 402 ohci_pipe_private_t *pp, 403 ohci_trans_wrapper_t *tw, 404 ohci_td_t *td, 405 void *); 406 static void ohci_handle_bulk_td(ohci_state_t *ohcip, 407 ohci_pipe_private_t *pp, 408 ohci_trans_wrapper_t *tw, 409 ohci_td_t *td, 410 void *); 411 static void ohci_handle_intr_td(ohci_state_t *ohcip, 412 ohci_pipe_private_t *pp, 413 ohci_trans_wrapper_t *tw, 414 ohci_td_t *td, 415 void *); 416 static void ohci_handle_one_xfer_completion( 417 ohci_state_t *ohcip, 418 ohci_trans_wrapper_t *tw); 419 static void ohci_handle_isoc_td(ohci_state_t *ohcip, 420 ohci_pipe_private_t *pp, 421 ohci_trans_wrapper_t *tw, 422 ohci_td_t *td, 423 void *); 424 static void ohci_sendup_td_message( 425 ohci_state_t *ohcip, 426 ohci_pipe_private_t *pp, 427 ohci_trans_wrapper_t *tw, 428 ohci_td_t *td, 429 usb_cr_t error); 430 static int ohci_check_done_head( 431 ohci_state_t *ohcip, 432 ohci_td_t *done_head); 433 434 /* Miscillaneous functions */ 435 static void ohci_cpr_cleanup( 436 ohci_state_t *ohcip); 437 static usb_req_attrs_t ohci_get_xfer_attrs(ohci_state_t *ohcip, 438 ohci_pipe_private_t *pp, 439 ohci_trans_wrapper_t *tw); 440 static int ohci_allocate_periodic_in_resource( 441 ohci_state_t *ohcip, 442 ohci_pipe_private_t *pp, 443 ohci_trans_wrapper_t *tw, 444 usb_flags_t flags); 445 static int ohci_wait_for_sof( 446 ohci_state_t *ohcip); 447 static void ohci_pipe_cleanup( 448 ohci_state_t *ohcip, 449 usba_pipe_handle_data_t *ph); 450 static void ohci_wait_for_transfers_completion( 451 ohci_state_t *ohcip, 452 ohci_pipe_private_t *pp); 453 static void ohci_check_for_transfers_completion( 454 ohci_state_t *ohcip, 455 ohci_pipe_private_t *pp); 456 static void ohci_save_data_toggle(ohci_state_t *ohcip, 457 usba_pipe_handle_data_t *ph); 458 static void ohci_restore_data_toggle(ohci_state_t *ohcip, 459 usba_pipe_handle_data_t *ph); 460 static void ohci_deallocate_periodic_in_resource( 461 ohci_state_t *ohcip, 462 ohci_pipe_private_t *pp, 463 ohci_trans_wrapper_t *tw); 464 static void ohci_do_client_periodic_in_req_callback( 465 ohci_state_t *ohcip, 466 ohci_pipe_private_t *pp, 467 usb_cr_t completion_reason); 468 static void ohci_hcdi_callback( 469 usba_pipe_handle_data_t *ph, 470 ohci_trans_wrapper_t *tw, 471 usb_cr_t completion_reason); 472 473 /* Kstat Support */ 474 static void ohci_create_stats(ohci_state_t *ohcip); 475 static void ohci_destroy_stats(ohci_state_t *ohcip); 476 static void ohci_do_byte_stats( 477 ohci_state_t *ohcip, 478 size_t len, 479 uint8_t attr, 480 uint8_t addr); 481 static void ohci_do_intrs_stats( 482 ohci_state_t *ohcip, 483 int val); 484 static void ohci_print_op_regs(ohci_state_t *ohcip); 485 static void ohci_print_ed(ohci_state_t *ohcip, 486 ohci_ed_t *ed); 487 static void ohci_print_td(ohci_state_t *ohcip, 488 ohci_td_t *td); 489 490 /* extern */ 491 int usba_hubdi_root_hub_power(dev_info_t *dip, int comp, int level); 492 493 /* 494 * Device operations (dev_ops) entries function prototypes. 495 * 496 * We use the hub cbops since all nexus ioctl operations defined so far will 497 * be executed by the root hub. The following are the Host Controller Driver 498 * (HCD) entry points. 499 * 500 * the open/close/ioctl functions call the corresponding usba_hubdi_* 501 * calls after looking up the dip thru the dev_t. 502 */ 503 static int ohci_open(dev_t *devp, int flags, int otyp, cred_t *credp); 504 static int ohci_close(dev_t dev, int flag, int otyp, cred_t *credp); 505 static int ohci_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, 506 cred_t *credp, int *rvalp); 507 508 static int ohci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 509 static int ohci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 510 static int ohci_info(dev_info_t *dip, ddi_info_cmd_t infocmd, 511 void *arg, void **result); 512 513 static struct cb_ops ohci_cb_ops = { 514 ohci_open, /* Open */ 515 ohci_close, /* Close */ 516 nodev, /* Strategy */ 517 nodev, /* Print */ 518 nodev, /* Dump */ 519 nodev, /* Read */ 520 nodev, /* Write */ 521 ohci_ioctl, /* Ioctl */ 522 nodev, /* Devmap */ 523 nodev, /* Mmap */ 524 nodev, /* Segmap */ 525 nochpoll, /* Poll */ 526 ddi_prop_op, /* cb_prop_op */ 527 NULL, /* Streamtab */ 528 D_MP /* Driver compatibility flag */ 529 }; 530 531 static struct dev_ops ohci_ops = { 532 DEVO_REV, /* Devo_rev */ 533 0, /* Refcnt */ 534 ohci_info, /* Info */ 535 nulldev, /* Identify */ 536 nulldev, /* Probe */ 537 ohci_attach, /* Attach */ 538 ohci_detach, /* Detach */ 539 nodev, /* Reset */ 540 &ohci_cb_ops, /* Driver operations */ 541 &usba_hubdi_busops, /* Bus operations */ 542 usba_hubdi_root_hub_power /* Power */ 543 }; 544 545 /* 546 * The USBA library must be loaded for this driver. 547 */ 548 static struct modldrv modldrv = { 549 &mod_driverops, /* Type of module. This one is a driver */ 550 "USB OpenHCI Driver %I%", /* Name of the module. */ 551 &ohci_ops, /* Driver ops */ 552 }; 553 554 static struct modlinkage modlinkage = { 555 MODREV_1, (void *)&modldrv, NULL 556 }; 557 558 559 int 560 _init(void) 561 { 562 int error; 563 564 /* Initialize the soft state structures */ 565 if ((error = ddi_soft_state_init(&ohci_statep, sizeof (ohci_state_t), 566 OHCI_INSTS)) != 0) { 567 return (error); 568 } 569 570 /* Install the loadable module */ 571 if ((error = mod_install(&modlinkage)) != 0) { 572 ddi_soft_state_fini(&ohci_statep); 573 } 574 575 return (error); 576 } 577 578 579 int 580 _info(struct modinfo *modinfop) 581 { 582 return (mod_info(&modlinkage, modinfop)); 583 } 584 585 586 int 587 _fini(void) 588 { 589 int error; 590 591 if ((error = mod_remove(&modlinkage)) == 0) { 592 /* Release per module resources */ 593 ddi_soft_state_fini(&ohci_statep); 594 } 595 596 return (error); 597 } 598 599 600 /* 601 * Host Controller Driver (HCD) entry points 602 */ 603 604 /* 605 * ohci_attach: 606 */ 607 static int 608 ohci_attach(dev_info_t *dip, 609 ddi_attach_cmd_t cmd) 610 { 611 int instance; 612 ohci_state_t *ohcip = NULL; 613 usba_hcdi_register_args_t hcdi_args; 614 615 switch (cmd) { 616 case DDI_ATTACH: 617 break; 618 case DDI_RESUME: 619 ohcip = ohci_obtain_state(dip); 620 621 return (ohci_cpr_resume(ohcip)); 622 default: 623 return (DDI_FAILURE); 624 } 625 626 /* Get the instance and create soft state */ 627 instance = ddi_get_instance(dip); 628 629 if (ddi_soft_state_zalloc(ohci_statep, instance) != 0) { 630 631 return (DDI_FAILURE); 632 } 633 634 ohcip = ddi_get_soft_state(ohci_statep, instance); 635 if (ohcip == NULL) { 636 637 return (DDI_FAILURE); 638 } 639 640 ohcip->ohci_flags = OHCI_ATTACH; 641 642 ohcip->ohci_log_hdl = usb_alloc_log_hdl(dip, "ohci", &ohci_errlevel, 643 &ohci_errmask, &ohci_instance_debug, 0); 644 645 ohcip->ohci_flags |= OHCI_ZALLOC; 646 647 /* Set host controller soft state to initilization */ 648 ohcip->ohci_hc_soft_state = OHCI_CTLR_INIT_STATE; 649 650 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 651 "ohcip = 0x%p", (void *)ohcip); 652 653 /* Initialize the DMA attributes */ 654 ohci_set_dma_attributes(ohcip); 655 656 /* Save the dip and instance */ 657 ohcip->ohci_dip = dip; 658 ohcip->ohci_instance = instance; 659 660 /* Initialize the kstat structures */ 661 ohci_create_stats(ohcip); 662 663 /* Create the td and ed pools */ 664 if (ohci_allocate_pools(ohcip) != DDI_SUCCESS) { 665 (void) ohci_cleanup(ohcip); 666 667 return (DDI_FAILURE); 668 } 669 670 /* Map the registers */ 671 if (ohci_map_regs(ohcip) != DDI_SUCCESS) { 672 (void) ohci_cleanup(ohcip); 673 674 return (DDI_FAILURE); 675 } 676 677 /* Register interrupts */ 678 if (ohci_register_intrs_and_init_mutex(ohcip) != DDI_SUCCESS) { 679 (void) ohci_cleanup(ohcip); 680 681 return (DDI_FAILURE); 682 } 683 684 mutex_enter(&ohcip->ohci_int_mutex); 685 686 /* Initialize the controller */ 687 if (ohci_init_ctlr(ohcip) != DDI_SUCCESS) { 688 mutex_exit(&ohcip->ohci_int_mutex); 689 (void) ohci_cleanup(ohcip); 690 691 return (DDI_FAILURE); 692 } 693 694 /* 695 * At this point, the hardware wiil be okay. 696 * Initialize the usba_hcdi structure 697 */ 698 ohcip->ohci_hcdi_ops = ohci_alloc_hcdi_ops(ohcip); 699 700 mutex_exit(&ohcip->ohci_int_mutex); 701 702 /* 703 * Make this HCD instance known to USBA 704 * (dma_attr must be passed for USBA busctl's) 705 */ 706 hcdi_args.usba_hcdi_register_version = HCDI_REGISTER_VERSION; 707 hcdi_args.usba_hcdi_register_dip = dip; 708 hcdi_args.usba_hcdi_register_ops = ohcip->ohci_hcdi_ops; 709 hcdi_args.usba_hcdi_register_dma_attr = &ohcip->ohci_dma_attr; 710 711 /* 712 * Priority and iblock_cookie are one and the same 713 * (However, retaining hcdi_soft_iblock_cookie for now 714 * assigning it w/ priority. In future all iblock_cookie 715 * could just go) 716 */ 717 hcdi_args.usba_hcdi_register_iblock_cookie = 718 (ddi_iblock_cookie_t)(uintptr_t)ohcip->ohci_intr_pri; 719 720 if (usba_hcdi_register(&hcdi_args, 0) != DDI_SUCCESS) { 721 (void) ohci_cleanup(ohcip); 722 723 return (DDI_FAILURE); 724 } 725 ohcip->ohci_flags |= OHCI_USBAREG; 726 727 mutex_enter(&ohcip->ohci_int_mutex); 728 729 if ((ohci_init_root_hub(ohcip)) != USB_SUCCESS) { 730 mutex_exit(&ohcip->ohci_int_mutex); 731 (void) ohci_cleanup(ohcip); 732 733 return (DDI_FAILURE); 734 } 735 736 mutex_exit(&ohcip->ohci_int_mutex); 737 738 /* Finally load the root hub driver */ 739 if (ohci_load_root_hub_driver(ohcip) != USB_SUCCESS) { 740 (void) ohci_cleanup(ohcip); 741 742 return (DDI_FAILURE); 743 } 744 ohcip->ohci_flags |= OHCI_RHREG; 745 746 /* Display information in the banner */ 747 ddi_report_dev(dip); 748 749 mutex_enter(&ohcip->ohci_int_mutex); 750 751 /* Reset the ohci initilization flag */ 752 ohcip->ohci_flags &= ~OHCI_ATTACH; 753 754 /* Print the Host Control's Operational registers */ 755 ohci_print_op_regs(ohcip); 756 757 /* For RIO we need to call pci_report_pmcap */ 758 if (OHCI_IS_RIO(ohcip)) { 759 760 (void) pci_report_pmcap(dip, PCI_PM_IDLESPEED, (void *)4000); 761 } 762 763 mutex_exit(&ohcip->ohci_int_mutex); 764 765 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 766 "ohci_attach: dip = 0x%p done", (void *)dip); 767 768 return (DDI_SUCCESS); 769 } 770 771 772 /* 773 * ohci_detach: 774 */ 775 int 776 ohci_detach(dev_info_t *dip, 777 ddi_detach_cmd_t cmd) 778 { 779 ohci_state_t *ohcip = ohci_obtain_state(dip); 780 781 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, "ohci_detach:"); 782 783 switch (cmd) { 784 case DDI_DETACH: 785 786 return (ohci_cleanup(ohcip)); 787 788 case DDI_SUSPEND: 789 790 return (ohci_cpr_suspend(ohcip)); 791 default: 792 793 return (DDI_FAILURE); 794 } 795 } 796 797 798 /* 799 * ohci_info: 800 */ 801 /* ARGSUSED */ 802 static int 803 ohci_info(dev_info_t *dip, 804 ddi_info_cmd_t infocmd, 805 void *arg, 806 void **result) 807 { 808 dev_t dev; 809 ohci_state_t *ohcip; 810 int instance; 811 int error = DDI_FAILURE; 812 813 switch (infocmd) { 814 case DDI_INFO_DEVT2DEVINFO: 815 dev = (dev_t)arg; 816 instance = OHCI_UNIT(dev); 817 ohcip = ddi_get_soft_state(ohci_statep, instance); 818 if (ohcip != NULL) { 819 *result = (void *)ohcip->ohci_dip; 820 if (*result != NULL) { 821 error = DDI_SUCCESS; 822 } 823 } else { 824 *result = NULL; 825 } 826 827 break; 828 case DDI_INFO_DEVT2INSTANCE: 829 dev = (dev_t)arg; 830 instance = OHCI_UNIT(dev); 831 *result = (void *)(uintptr_t)instance; 832 error = DDI_SUCCESS; 833 break; 834 default: 835 break; 836 } 837 838 return (error); 839 } 840 841 842 /* 843 * cb_ops entry points 844 */ 845 static dev_info_t * 846 ohci_get_dip(dev_t dev) 847 { 848 int instance = OHCI_UNIT(dev); 849 ohci_state_t *ohcip = ddi_get_soft_state(ohci_statep, instance); 850 851 if (ohcip) { 852 853 return (ohcip->ohci_dip); 854 } else { 855 856 return (NULL); 857 } 858 } 859 860 861 static int 862 ohci_open(dev_t *devp, 863 int flags, 864 int otyp, 865 cred_t *credp) 866 { 867 dev_info_t *dip = ohci_get_dip(*devp); 868 869 return (usba_hubdi_open(dip, devp, flags, otyp, credp)); 870 } 871 872 873 static int 874 ohci_close(dev_t dev, 875 int flag, 876 int otyp, 877 cred_t *credp) 878 { 879 dev_info_t *dip = ohci_get_dip(dev); 880 881 return (usba_hubdi_close(dip, dev, flag, otyp, credp)); 882 } 883 884 885 static int 886 ohci_ioctl(dev_t dev, 887 int cmd, 888 intptr_t arg, 889 int mode, 890 cred_t *credp, 891 int *rvalp) 892 { 893 dev_info_t *dip = ohci_get_dip(dev); 894 895 return (usba_hubdi_ioctl(dip, 896 dev, cmd, arg, mode, credp, rvalp)); 897 } 898 899 900 /* 901 * Host Controller Driver (HCD) initialization functions 902 */ 903 904 /* 905 * ohci_set_dma_attributes: 906 * 907 * Set the limits in the DMA attributes structure. Most of the values used 908 * in the DMA limit structres are the default values as specified by the 909 * Writing PCI device drivers document. 910 */ 911 static void 912 ohci_set_dma_attributes(ohci_state_t *ohcip) 913 { 914 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 915 "ohci_set_dma_attributes:"); 916 917 /* Initialize the DMA attributes */ 918 ohcip->ohci_dma_attr.dma_attr_version = DMA_ATTR_V0; 919 ohcip->ohci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 920 ohcip->ohci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 921 922 /* 32 bit addressing */ 923 ohcip->ohci_dma_attr.dma_attr_count_max = OHCI_DMA_ATTR_COUNT_MAX; 924 925 /* Byte alignment */ 926 ohcip->ohci_dma_attr.dma_attr_align = OHCI_DMA_ATTR_ALIGNMENT; 927 928 /* 929 * Since PCI specification is byte alignment, the 930 * burstsize field should be set to 1 for PCI devices. 931 */ 932 ohcip->ohci_dma_attr.dma_attr_burstsizes = 0x1; 933 934 ohcip->ohci_dma_attr.dma_attr_minxfer = 0x1; 935 ohcip->ohci_dma_attr.dma_attr_maxxfer = OHCI_DMA_ATTR_MAX_XFER; 936 ohcip->ohci_dma_attr.dma_attr_seg = 0xffffffffull; 937 ohcip->ohci_dma_attr.dma_attr_sgllen = 1; 938 ohcip->ohci_dma_attr.dma_attr_granular = OHCI_DMA_ATTR_GRANULAR; 939 ohcip->ohci_dma_attr.dma_attr_flags = 0; 940 } 941 942 943 /* 944 * ohci_allocate_pools: 945 * 946 * Allocate the system memory for the Endpoint Descriptor (ED) and for the 947 * Transfer Descriptor (TD) pools. Both ED and TD structures must be aligned 948 * to a 16 byte boundary. 949 */ 950 static int 951 ohci_allocate_pools(ohci_state_t *ohcip) 952 { 953 ddi_device_acc_attr_t dev_attr; 954 size_t real_length; 955 int result; 956 uint_t ccount; 957 int i; 958 959 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 960 "ohci_allocate_pools:"); 961 962 /* The host controller will be little endian */ 963 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 964 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 965 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 966 967 /* Byte alignment to TD alignment */ 968 ohcip->ohci_dma_attr.dma_attr_align = OHCI_DMA_ATTR_TD_ALIGNMENT; 969 970 /* Allocate the TD pool DMA handle */ 971 if (ddi_dma_alloc_handle(ohcip->ohci_dip, &ohcip->ohci_dma_attr, 972 DDI_DMA_SLEEP, 0, 973 &ohcip->ohci_td_pool_dma_handle) != DDI_SUCCESS) { 974 975 return (DDI_FAILURE); 976 } 977 978 /* Allocate the memory for the TD pool */ 979 if (ddi_dma_mem_alloc(ohcip->ohci_td_pool_dma_handle, 980 ohci_td_pool_size * sizeof (ohci_td_t), 981 &dev_attr, 982 DDI_DMA_CONSISTENT, 983 DDI_DMA_SLEEP, 984 0, 985 (caddr_t *)&ohcip->ohci_td_pool_addr, 986 &real_length, 987 &ohcip->ohci_td_pool_mem_handle)) { 988 989 return (DDI_FAILURE); 990 } 991 992 /* Map the TD pool into the I/O address space */ 993 result = ddi_dma_addr_bind_handle( 994 ohcip->ohci_td_pool_dma_handle, 995 NULL, 996 (caddr_t)ohcip->ohci_td_pool_addr, 997 real_length, 998 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 999 DDI_DMA_SLEEP, 1000 NULL, 1001 &ohcip->ohci_td_pool_cookie, 1002 &ccount); 1003 1004 bzero((void *)ohcip->ohci_td_pool_addr, 1005 ohci_td_pool_size * sizeof (ohci_td_t)); 1006 1007 /* Process the result */ 1008 if (result == DDI_DMA_MAPPED) { 1009 /* The cookie count should be 1 */ 1010 if (ccount != 1) { 1011 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1012 "ohci_allocate_pools: More than 1 cookie"); 1013 1014 return (DDI_FAILURE); 1015 } 1016 } else { 1017 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1018 "ohci_allocate_pools: Result = %d", result); 1019 1020 ohci_decode_ddi_dma_addr_bind_handle_result(ohcip, result); 1021 1022 return (DDI_FAILURE); 1023 } 1024 1025 /* 1026 * DMA addresses for TD pools are bound 1027 */ 1028 ohcip->ohci_dma_addr_bind_flag |= OHCI_TD_POOL_BOUND; 1029 1030 /* Initialize the TD pool */ 1031 for (i = 0; i < ohci_td_pool_size; i ++) { 1032 Set_TD(ohcip->ohci_td_pool_addr[i].hctd_state, HC_TD_FREE); 1033 } 1034 1035 /* Byte alignment to ED alignment */ 1036 ohcip->ohci_dma_attr.dma_attr_align = OHCI_DMA_ATTR_ED_ALIGNMENT; 1037 1038 /* Allocate the ED pool DMA handle */ 1039 if (ddi_dma_alloc_handle(ohcip->ohci_dip, 1040 &ohcip->ohci_dma_attr, 1041 DDI_DMA_SLEEP, 1042 0, 1043 &ohcip->ohci_ed_pool_dma_handle) != DDI_SUCCESS) { 1044 1045 return (DDI_FAILURE); 1046 } 1047 1048 /* Allocate the memory for the ED pool */ 1049 if (ddi_dma_mem_alloc(ohcip->ohci_ed_pool_dma_handle, 1050 ohci_ed_pool_size * sizeof (ohci_ed_t), 1051 &dev_attr, 1052 DDI_DMA_CONSISTENT, 1053 DDI_DMA_SLEEP, 1054 0, 1055 (caddr_t *)&ohcip->ohci_ed_pool_addr, 1056 &real_length, 1057 &ohcip->ohci_ed_pool_mem_handle) != DDI_SUCCESS) { 1058 1059 return (DDI_FAILURE); 1060 } 1061 1062 result = ddi_dma_addr_bind_handle(ohcip->ohci_ed_pool_dma_handle, 1063 NULL, 1064 (caddr_t)ohcip->ohci_ed_pool_addr, 1065 real_length, 1066 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1067 DDI_DMA_SLEEP, 1068 NULL, 1069 &ohcip->ohci_ed_pool_cookie, 1070 &ccount); 1071 1072 bzero((void *)ohcip->ohci_ed_pool_addr, 1073 ohci_ed_pool_size * sizeof (ohci_ed_t)); 1074 1075 /* Process the result */ 1076 if (result == DDI_DMA_MAPPED) { 1077 /* The cookie count should be 1 */ 1078 if (ccount != 1) { 1079 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1080 "ohci_allocate_pools: More than 1 cookie"); 1081 1082 return (DDI_FAILURE); 1083 } 1084 } else { 1085 ohci_decode_ddi_dma_addr_bind_handle_result(ohcip, result); 1086 1087 return (DDI_FAILURE); 1088 } 1089 1090 /* 1091 * DMA addresses for ED pools are bound 1092 */ 1093 ohcip->ohci_dma_addr_bind_flag |= OHCI_ED_POOL_BOUND; 1094 1095 /* Initialize the ED pool */ 1096 for (i = 0; i < ohci_ed_pool_size; i ++) { 1097 Set_ED(ohcip->ohci_ed_pool_addr[i].hced_state, HC_EPT_FREE); 1098 } 1099 1100 return (DDI_SUCCESS); 1101 } 1102 1103 1104 /* 1105 * ohci_decode_ddi_dma_addr_bind_handle_result: 1106 * 1107 * Process the return values of ddi_dma_addr_bind_handle() 1108 */ 1109 static void 1110 ohci_decode_ddi_dma_addr_bind_handle_result( 1111 ohci_state_t *ohcip, 1112 int result) 1113 { 1114 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 1115 "ohci_decode_ddi_dma_addr_bind_handle_result:"); 1116 1117 switch (result) { 1118 case DDI_DMA_PARTIAL_MAP: 1119 USB_DPRINTF_L2(PRINT_MASK_ALL, ohcip->ohci_log_hdl, 1120 "Partial transfers not allowed"); 1121 break; 1122 case DDI_DMA_INUSE: 1123 USB_DPRINTF_L2(PRINT_MASK_ALL, ohcip->ohci_log_hdl, 1124 "Handle is in use"); 1125 break; 1126 case DDI_DMA_NORESOURCES: 1127 USB_DPRINTF_L2(PRINT_MASK_ALL, ohcip->ohci_log_hdl, 1128 "No resources"); 1129 break; 1130 case DDI_DMA_NOMAPPING: 1131 USB_DPRINTF_L2(PRINT_MASK_ALL, ohcip->ohci_log_hdl, 1132 "No mapping"); 1133 break; 1134 case DDI_DMA_TOOBIG: 1135 USB_DPRINTF_L2(PRINT_MASK_ALL, ohcip->ohci_log_hdl, 1136 "Object is too big"); 1137 break; 1138 default: 1139 USB_DPRINTF_L2(PRINT_MASK_ALL, ohcip->ohci_log_hdl, 1140 "Unknown dma error"); 1141 } 1142 } 1143 1144 1145 /* 1146 * ohci_map_regs: 1147 * 1148 * The Host Controller (HC) contains a set of on-chip operational registers 1149 * and which should be mapped into a non-cacheable portion of the system 1150 * addressable space. 1151 */ 1152 static int 1153 ohci_map_regs(ohci_state_t *ohcip) 1154 { 1155 ddi_device_acc_attr_t attr; 1156 uint16_t cmd_reg; 1157 1158 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, "ohci_map_regs:"); 1159 1160 /* The host controller will be little endian */ 1161 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1162 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1163 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1164 1165 /* Map in operational registers */ 1166 if (ddi_regs_map_setup(ohcip->ohci_dip, 1, 1167 (caddr_t *)&ohcip->ohci_regsp, 0, 1168 sizeof (ohci_regs_t), &attr, 1169 &ohcip->ohci_regs_handle) != DDI_SUCCESS) { 1170 1171 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1172 "ohci_map_regs: Map setup error"); 1173 1174 return (DDI_FAILURE); 1175 } 1176 1177 if (pci_config_setup(ohcip->ohci_dip, 1178 &ohcip->ohci_config_handle) != DDI_SUCCESS) { 1179 1180 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1181 "ohci_map_regs: Config error"); 1182 1183 return (DDI_FAILURE); 1184 } 1185 1186 /* Make sure Memory Access Enable and Master Enable are set */ 1187 cmd_reg = pci_config_get16(ohcip->ohci_config_handle, PCI_CONF_COMM); 1188 1189 if (!(cmd_reg & PCI_COMM_MAE)) { 1190 1191 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1192 "ohci_map_regs: Memory base address access disabled"); 1193 1194 return (DDI_FAILURE); 1195 } 1196 1197 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 1198 1199 pci_config_put16(ohcip->ohci_config_handle, PCI_CONF_COMM, cmd_reg); 1200 1201 return (DDI_SUCCESS); 1202 } 1203 1204 /* 1205 * The following simulated polling is for debugging purposes only. 1206 * It is activated on x86 by setting usb-polling=true in GRUB or ohci.conf. 1207 */ 1208 static int 1209 ohci_is_polled(dev_info_t *dip) 1210 { 1211 int ret; 1212 char *propval; 1213 1214 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 1215 "usb-polling", &propval) != DDI_SUCCESS) 1216 1217 return (0); 1218 1219 ret = (strcmp(propval, "true") == 0); 1220 ddi_prop_free(propval); 1221 1222 return (ret); 1223 } 1224 1225 static void 1226 ohci_poll_intr(void *arg) 1227 { 1228 /* poll every millisecond */ 1229 for (;;) { 1230 (void) ohci_intr(arg, NULL); 1231 delay(drv_usectohz(1000)); 1232 } 1233 } 1234 1235 /* 1236 * ohci_register_intrs_and_init_mutex: 1237 * 1238 * Register interrupts and initialize each mutex and condition variables 1239 */ 1240 static int 1241 ohci_register_intrs_and_init_mutex(ohci_state_t *ohcip) 1242 { 1243 int intr_types; 1244 1245 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1246 "ohci_register_intrs_and_init_mutex:"); 1247 1248 if (ohci_is_polled(ohcip->ohci_dip)) { 1249 extern pri_t maxclsyspri; 1250 1251 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1252 "ohci_register_intrs_and_init_mutex: " 1253 "running in simulated polled mode"); 1254 1255 (void) thread_create(NULL, 0, ohci_poll_intr, ohcip, 0, &p0, 1256 TS_RUN, maxclsyspri); 1257 1258 goto skip_intr; 1259 } 1260 1261 /* Get supported interrupt types */ 1262 if (ddi_intr_get_supported_types(ohcip->ohci_dip, 1263 &intr_types) != DDI_SUCCESS) { 1264 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1265 "ohci_register_intrs_and_init_mutex: " 1266 "ddi_intr_get_supported_types failed"); 1267 1268 return (DDI_FAILURE); 1269 } 1270 1271 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1272 "ohci_register_intrs_and_init_mutex: " 1273 "supported interrupt types 0x%x", intr_types); 1274 1275 if ((intr_types & DDI_INTR_TYPE_MSI) && ohci_enable_msi) { 1276 if (ohci_add_intrs(ohcip, DDI_INTR_TYPE_MSI) 1277 != DDI_SUCCESS) { 1278 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1279 "ohci_register_intrs_and_init_mutex: MSI " 1280 "registration failed, trying FIXED interrupt \n"); 1281 } else { 1282 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1283 "ohci_register_intrs_and_init_mutex: " 1284 "Using MSI interrupt type\n"); 1285 1286 ohcip->ohci_intr_type = DDI_INTR_TYPE_MSI; 1287 ohcip->ohci_flags |= OHCI_INTR; 1288 } 1289 } 1290 1291 if ((!(ohcip->ohci_flags & OHCI_INTR)) && 1292 (intr_types & DDI_INTR_TYPE_FIXED)) { 1293 if (ohci_add_intrs(ohcip, DDI_INTR_TYPE_FIXED) 1294 != DDI_SUCCESS) { 1295 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1296 "ohci_register_intrs_and_init_mutex: " 1297 "FIXED interrupt registration failed\n"); 1298 1299 return (DDI_FAILURE); 1300 } 1301 1302 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1303 "ohci_register_intrs_and_init_mutex: " 1304 "Using FIXED interrupt type\n"); 1305 1306 ohcip->ohci_intr_type = DDI_INTR_TYPE_FIXED; 1307 ohcip->ohci_flags |= OHCI_INTR; 1308 } 1309 1310 skip_intr: 1311 /* Create prototype for SOF condition variable */ 1312 cv_init(&ohcip->ohci_SOF_cv, NULL, CV_DRIVER, NULL); 1313 1314 /* Semaphore to serialize opens and closes */ 1315 sema_init(&ohcip->ohci_ocsem, 1, NULL, SEMA_DRIVER, NULL); 1316 1317 return (DDI_SUCCESS); 1318 } 1319 1320 1321 /* 1322 * ohci_add_intrs: 1323 * 1324 * Register FIXED or MSI interrupts. 1325 */ 1326 static int 1327 ohci_add_intrs(ohci_state_t *ohcip, 1328 int intr_type) 1329 { 1330 int actual, avail, intr_size, count = 0; 1331 int i, flag, ret; 1332 1333 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1334 "ohci_add_intrs: interrupt type 0x%x", intr_type); 1335 1336 /* Get number of interrupts */ 1337 ret = ddi_intr_get_nintrs(ohcip->ohci_dip, intr_type, &count); 1338 if ((ret != DDI_SUCCESS) || (count == 0)) { 1339 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1340 "ohci_add_intrs: ddi_intr_get_nintrs() failure, " 1341 "ret: %d, count: %d", ret, count); 1342 1343 return (DDI_FAILURE); 1344 } 1345 1346 /* Get number of available interrupts */ 1347 ret = ddi_intr_get_navail(ohcip->ohci_dip, intr_type, &avail); 1348 if ((ret != DDI_SUCCESS) || (avail == 0)) { 1349 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1350 "ohci_add_intrs: ddi_intr_get_navail() failure, " 1351 "ret: %d, count: %d", ret, count); 1352 1353 return (DDI_FAILURE); 1354 } 1355 1356 if (avail < count) { 1357 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1358 "ohci_add_intrs: ohci_add_intrs: nintrs () " 1359 "returned %d, navail returned %d\n", count, avail); 1360 } 1361 1362 /* Allocate an array of interrupt handles */ 1363 intr_size = count * sizeof (ddi_intr_handle_t); 1364 ohcip->ohci_htable = kmem_zalloc(intr_size, KM_SLEEP); 1365 1366 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 1367 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 1368 1369 /* call ddi_intr_alloc() */ 1370 ret = ddi_intr_alloc(ohcip->ohci_dip, ohcip->ohci_htable, 1371 intr_type, 0, count, &actual, flag); 1372 1373 if ((ret != DDI_SUCCESS) || (actual == 0)) { 1374 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1375 "ohci_add_intrs: ddi_intr_alloc() failed %d", ret); 1376 1377 kmem_free(ohcip->ohci_htable, intr_size); 1378 1379 return (DDI_FAILURE); 1380 } 1381 1382 if (actual < count) { 1383 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1384 "ohci_add_intrs: Requested: %d, Received: %d\n", 1385 count, actual); 1386 1387 for (i = 0; i < actual; i++) 1388 (void) ddi_intr_free(ohcip->ohci_htable[i]); 1389 1390 kmem_free(ohcip->ohci_htable, intr_size); 1391 1392 return (DDI_FAILURE); 1393 } 1394 1395 ohcip->ohci_intr_cnt = actual; 1396 1397 if ((ret = ddi_intr_get_pri(ohcip->ohci_htable[0], 1398 &ohcip->ohci_intr_pri)) != DDI_SUCCESS) { 1399 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1400 "ohci_add_intrs: ddi_intr_get_pri() failed %d", ret); 1401 1402 for (i = 0; i < actual; i++) 1403 (void) ddi_intr_free(ohcip->ohci_htable[i]); 1404 1405 kmem_free(ohcip->ohci_htable, intr_size); 1406 1407 return (DDI_FAILURE); 1408 } 1409 1410 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1411 "ohci_add_intrs: Supported Interrupt priority 0x%x", 1412 ohcip->ohci_intr_pri); 1413 1414 /* Test for high level mutex */ 1415 if (ohcip->ohci_intr_pri >= ddi_intr_get_hilevel_pri()) { 1416 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1417 "ohci_add_intrs: Hi level interrupt not supported"); 1418 1419 for (i = 0; i < actual; i++) 1420 (void) ddi_intr_free(ohcip->ohci_htable[i]); 1421 1422 kmem_free(ohcip->ohci_htable, intr_size); 1423 1424 return (DDI_FAILURE); 1425 } 1426 1427 /* Initialize the mutex */ 1428 mutex_init(&ohcip->ohci_int_mutex, NULL, MUTEX_DRIVER, 1429 DDI_INTR_PRI(ohcip->ohci_intr_pri)); 1430 1431 /* Call ddi_intr_add_handler() */ 1432 for (i = 0; i < actual; i++) { 1433 if ((ret = ddi_intr_add_handler(ohcip->ohci_htable[i], 1434 ohci_intr, (caddr_t)ohcip, 1435 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 1436 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1437 "ohci_add_intrs: ddi_intr_add_handler() " 1438 "failed %d", ret); 1439 1440 for (i = 0; i < actual; i++) 1441 (void) ddi_intr_free(ohcip->ohci_htable[i]); 1442 1443 mutex_destroy(&ohcip->ohci_int_mutex); 1444 kmem_free(ohcip->ohci_htable, intr_size); 1445 1446 return (DDI_FAILURE); 1447 } 1448 } 1449 1450 if ((ret = ddi_intr_get_cap(ohcip->ohci_htable[0], 1451 &ohcip->ohci_intr_cap)) != DDI_SUCCESS) { 1452 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1453 "ohci_add_intrs: ddi_intr_get_cap() failed %d", ret); 1454 1455 for (i = 0; i < actual; i++) { 1456 (void) ddi_intr_remove_handler(ohcip->ohci_htable[i]); 1457 (void) ddi_intr_free(ohcip->ohci_htable[i]); 1458 } 1459 1460 mutex_destroy(&ohcip->ohci_int_mutex); 1461 kmem_free(ohcip->ohci_htable, intr_size); 1462 1463 return (DDI_FAILURE); 1464 } 1465 1466 /* Enable all interrupts */ 1467 if (ohcip->ohci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1468 /* Call ddi_intr_block_enable() for MSI interrupts */ 1469 (void) ddi_intr_block_enable(ohcip->ohci_htable, 1470 ohcip->ohci_intr_cnt); 1471 } else { 1472 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 1473 for (i = 0; i < ohcip->ohci_intr_cnt; i++) 1474 (void) ddi_intr_enable(ohcip->ohci_htable[i]); 1475 } 1476 1477 return (DDI_SUCCESS); 1478 } 1479 1480 1481 /* 1482 * ohci_init_ctlr: 1483 * 1484 * Initialize the Host Controller (HC). 1485 */ 1486 static int 1487 ohci_init_ctlr(ohci_state_t *ohcip) 1488 { 1489 int revision, curr_control, max_packet = 0; 1490 clock_t sof_time_wait; 1491 int retry = 0; 1492 int ohci_frame_interval; 1493 1494 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, "ohci_init_ctlr:"); 1495 1496 if (ohci_take_control(ohcip) != DDI_SUCCESS) { 1497 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1498 "ohci_init_ctlr: ohci_take_control failed\n"); 1499 1500 return (DDI_FAILURE); 1501 } 1502 1503 /* 1504 * Soft reset the host controller. 1505 * 1506 * On soft reset, the ohci host controller moves to the 1507 * USB Suspend state in which most of the ohci operational 1508 * registers are reset except stated ones. The soft reset 1509 * doesn't cause a reset to the ohci root hub and even no 1510 * subsequent reset signaling should be asserterd to its 1511 * down stream. 1512 */ 1513 Set_OpReg(hcr_cmd_status, HCR_STATUS_RESET); 1514 1515 mutex_exit(&ohcip->ohci_int_mutex); 1516 /* Wait 10ms for reset to complete */ 1517 delay(drv_usectohz(OHCI_RESET_TIMEWAIT)); 1518 mutex_enter(&ohcip->ohci_int_mutex); 1519 1520 /* 1521 * Do hard reset the host controller. 1522 * 1523 * Now perform USB reset in order to reset the ohci root 1524 * hub. 1525 */ 1526 Set_OpReg(hcr_control, HCR_CONTROL_RESET); 1527 1528 /* 1529 * According to Section 5.1.2.3 of the specification, the 1530 * host controller will go into suspend state immediately 1531 * after the reset. 1532 */ 1533 1534 /* Verify the version number */ 1535 revision = Get_OpReg(hcr_revision); 1536 1537 if ((revision & HCR_REVISION_MASK) != HCR_REVISION_1_0) { 1538 1539 return (DDI_FAILURE); 1540 } 1541 1542 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1543 "ohci_init_ctlr: Revision verified"); 1544 1545 /* hcca area need not be initialized on resume */ 1546 if (ohcip->ohci_hc_soft_state == OHCI_CTLR_INIT_STATE) { 1547 1548 /* Get the ohci chip vendor and device id */ 1549 ohcip->ohci_vendor_id = pci_config_get16( 1550 ohcip->ohci_config_handle, PCI_CONF_VENID); 1551 ohcip->ohci_device_id = pci_config_get16( 1552 ohcip->ohci_config_handle, PCI_CONF_DEVID); 1553 ohcip->ohci_rev_id = pci_config_get8( 1554 ohcip->ohci_config_handle, PCI_CONF_REVID); 1555 1556 /* Initialize the hcca area */ 1557 if (ohci_init_hcca(ohcip) != DDI_SUCCESS) { 1558 1559 return (DDI_FAILURE); 1560 } 1561 } 1562 1563 /* 1564 * Workaround for ULI1575 chipset. Following OHCI Operational Memory 1565 * Registers are not cleared to their default value on reset. 1566 * Explicitly set the registers to default value. 1567 */ 1568 if (ohcip->ohci_vendor_id == PCI_ULI1575_VENID && 1569 ohcip->ohci_device_id == PCI_ULI1575_DEVID) { 1570 Set_OpReg(hcr_control, HCR_CONTROL_DEFAULT); 1571 Set_OpReg(hcr_intr_enable, HCR_INT_ENABLE_DEFAULT); 1572 Set_OpReg(hcr_HCCA, HCR_HCCA_DEFAULT); 1573 Set_OpReg(hcr_ctrl_head, HCR_CONTROL_HEAD_ED_DEFAULT); 1574 Set_OpReg(hcr_bulk_head, HCR_BULK_HEAD_ED_DEFAULT); 1575 Set_OpReg(hcr_frame_interval, HCR_FRAME_INTERVAL_DEFAULT); 1576 Set_OpReg(hcr_periodic_strt, HCR_PERIODIC_START_DEFAULT); 1577 } 1578 1579 /* Set the HcHCCA to the physical address of the HCCA block */ 1580 Set_OpReg(hcr_HCCA, (uint_t)ohcip->ohci_hcca_cookie.dmac_address); 1581 1582 /* 1583 * Set HcInterruptEnable to enable all interrupts except Root 1584 * Hub Status change and SOF interrupts. 1585 */ 1586 Set_OpReg(hcr_intr_enable, HCR_INTR_SO | HCR_INTR_WDH | 1587 HCR_INTR_RD | HCR_INTR_UE | HCR_INTR_FNO | HCR_INTR_MIE); 1588 1589 /* 1590 * For non-periodic transfers, reserve atleast for one low-speed 1591 * device transaction. According to USB Bandwidth Analysis white 1592 * paper and also as per OHCI Specification 1.0a, section 7.3.5, 1593 * page 123, one low-speed transaction takes 0x628h full speed 1594 * bits (197 bytes), which comes to around 13% of USB frame time. 1595 * 1596 * The periodic transfers will get around 87% of USB frame time. 1597 */ 1598 Set_OpReg(hcr_periodic_strt, 1599 ((PERIODIC_XFER_STARTS * BITS_PER_BYTE) - 1)); 1600 1601 /* Save the contents of the Frame Interval Registers */ 1602 ohcip->ohci_frame_interval = Get_OpReg(hcr_frame_interval); 1603 1604 /* 1605 * Initialize the FSLargestDataPacket value in the frame interval 1606 * register. The controller compares the value of MaxPacketSize to 1607 * this value to see if the entire packet may be sent out before 1608 * the EOF. 1609 */ 1610 max_packet = ((((ohcip->ohci_frame_interval - 1611 MAX_OVERHEAD) * 6) / 7) << HCR_FRME_FSMPS_SHFT); 1612 1613 Set_OpReg(hcr_frame_interval, 1614 (max_packet | ohcip->ohci_frame_interval)); 1615 1616 /* 1617 * Sometimes the HcFmInterval register in OHCI controller does not 1618 * maintain its value after the first write. This problem is found 1619 * on ULI M1575 South Bridge. To workaround the hardware problem, 1620 * check the value after write and retry if the last write failed. 1621 */ 1622 if (ohcip->ohci_vendor_id == PCI_ULI1575_VENID && 1623 ohcip->ohci_device_id == PCI_ULI1575_DEVID) { 1624 ohci_frame_interval = Get_OpReg(hcr_frame_interval); 1625 while ((ohci_frame_interval != (max_packet | 1626 ohcip->ohci_frame_interval))) { 1627 if (retry >= 10) { 1628 USB_DPRINTF_L1(PRINT_MASK_ATTA, 1629 ohcip->ohci_log_hdl, "Failed to program" 1630 " Frame Interval Register."); 1631 1632 return (DDI_FAILURE); 1633 } 1634 retry++; 1635 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1636 "ohci_init_ctlr: Failed to program Frame" 1637 " Interval Register, retry=%d", retry); 1638 Set_OpReg(hcr_frame_interval, 1639 (max_packet | ohcip->ohci_frame_interval)); 1640 ohci_frame_interval = Get_OpReg(hcr_frame_interval); 1641 } 1642 } 1643 1644 /* Begin sending SOFs */ 1645 curr_control = Get_OpReg(hcr_control); 1646 1647 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1648 "ohci_init_ctlr: curr_control=0x%x", curr_control); 1649 1650 /* Set the state to operational */ 1651 curr_control = (curr_control & 1652 (~HCR_CONTROL_HCFS)) | HCR_CONTROL_OPERAT; 1653 1654 Set_OpReg(hcr_control, curr_control); 1655 1656 ASSERT((Get_OpReg(hcr_control) & 1657 HCR_CONTROL_HCFS) == HCR_CONTROL_OPERAT); 1658 1659 /* Set host controller soft state to operational */ 1660 ohcip->ohci_hc_soft_state = OHCI_CTLR_OPERATIONAL_STATE; 1661 1662 /* Get the number of clock ticks to wait */ 1663 sof_time_wait = drv_usectohz(OHCI_MAX_SOF_TIMEWAIT * 1000000); 1664 1665 /* Clear ohci_sof_flag indicating waiting for SOF interrupt */ 1666 ohcip->ohci_sof_flag = B_FALSE; 1667 1668 /* Enable the SOF interrupt */ 1669 Set_OpReg(hcr_intr_enable, HCR_INTR_SOF); 1670 1671 ASSERT(Get_OpReg(hcr_intr_enable) & HCR_INTR_SOF); 1672 1673 (void) cv_timedwait(&ohcip->ohci_SOF_cv, 1674 &ohcip->ohci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1675 1676 /* Wait for the SOF or timeout event */ 1677 if (ohcip->ohci_sof_flag == B_FALSE) { 1678 1679 /* Set host controller soft state to error */ 1680 ohcip->ohci_hc_soft_state = OHCI_CTLR_ERROR_STATE; 1681 1682 USB_DPRINTF_L0(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1683 "No SOF interrupts have been received, this USB OHCI host" 1684 "controller is unusable"); 1685 return (DDI_FAILURE); 1686 } 1687 1688 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1689 "ohci_init_ctlr: SOF's have started"); 1690 1691 return (DDI_SUCCESS); 1692 } 1693 1694 1695 /* 1696 * ohci_init_hcca: 1697 * 1698 * Allocate the system memory and initialize Host Controller Communication 1699 * Area (HCCA). The HCCA structure must be aligned to a 256-byte boundary. 1700 */ 1701 static int 1702 ohci_init_hcca(ohci_state_t *ohcip) 1703 { 1704 ddi_device_acc_attr_t dev_attr; 1705 size_t real_length; 1706 uint_t mask, ccount; 1707 int result; 1708 uintptr_t addr; 1709 1710 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 1711 1712 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, "ohci_init_hcca:"); 1713 1714 /* The host controller will be little endian */ 1715 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1716 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1717 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1718 1719 /* Byte alignment to HCCA alignment */ 1720 ohcip->ohci_dma_attr.dma_attr_align = OHCI_DMA_ATTR_HCCA_ALIGNMENT; 1721 1722 /* Create space for the HCCA block */ 1723 if (ddi_dma_alloc_handle(ohcip->ohci_dip, &ohcip->ohci_dma_attr, 1724 DDI_DMA_SLEEP, 1725 0, 1726 &ohcip->ohci_hcca_dma_handle) 1727 != DDI_SUCCESS) { 1728 1729 return (DDI_FAILURE); 1730 } 1731 1732 if (ddi_dma_mem_alloc(ohcip->ohci_hcca_dma_handle, 1733 2 * sizeof (ohci_hcca_t), 1734 &dev_attr, 1735 DDI_DMA_CONSISTENT, 1736 DDI_DMA_SLEEP, 1737 0, 1738 (caddr_t *)&ohcip->ohci_hccap, 1739 &real_length, 1740 &ohcip->ohci_hcca_mem_handle)) { 1741 1742 return (DDI_FAILURE); 1743 } 1744 1745 bzero((void *)ohcip->ohci_hccap, real_length); 1746 1747 /* Figure out the alignment requirements */ 1748 Set_OpReg(hcr_HCCA, 0xFFFFFFFF); 1749 1750 /* 1751 * Read the hcr_HCCA register until 1752 * contenets are non-zero. 1753 */ 1754 mask = Get_OpReg(hcr_HCCA); 1755 1756 mutex_exit(&ohcip->ohci_int_mutex); 1757 while (mask == 0) { 1758 delay(drv_usectohz(OHCI_TIMEWAIT)); 1759 mask = Get_OpReg(hcr_HCCA); 1760 } 1761 mutex_enter(&ohcip->ohci_int_mutex); 1762 1763 ASSERT(mask != 0); 1764 1765 addr = (uintptr_t)ohcip->ohci_hccap; 1766 1767 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1768 "ohci_init_hcca: addr=0x%lx, mask=0x%x", addr, mask); 1769 1770 while (addr & (~mask)) { 1771 addr++; 1772 } 1773 1774 ohcip->ohci_hccap = (ohci_hcca_t *)addr; 1775 1776 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1777 "ohci_init_hcca: Real length %lu", real_length); 1778 1779 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1780 "ohci_init_hcca: virtual hcca 0x%p", (void *)ohcip->ohci_hccap); 1781 1782 /* Map the whole HCCA into the I/O address space */ 1783 result = ddi_dma_addr_bind_handle(ohcip->ohci_hcca_dma_handle, 1784 NULL, 1785 (caddr_t)ohcip->ohci_hccap, 1786 real_length, 1787 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1788 DDI_DMA_SLEEP, NULL, 1789 &ohcip->ohci_hcca_cookie, 1790 &ccount); 1791 1792 if (result == DDI_DMA_MAPPED) { 1793 /* The cookie count should be 1 */ 1794 if (ccount != 1) { 1795 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1796 "ohci_init_hcca: More than 1 cookie"); 1797 1798 return (DDI_FAILURE); 1799 } 1800 } else { 1801 ohci_decode_ddi_dma_addr_bind_handle_result(ohcip, result); 1802 1803 return (DDI_FAILURE); 1804 } 1805 1806 /* 1807 * DMA addresses for HCCA are bound 1808 */ 1809 ohcip->ohci_dma_addr_bind_flag |= OHCI_HCCA_DMA_BOUND; 1810 1811 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1812 "ohci_init_hcca: physical 0x%p", 1813 (void *)(uintptr_t)ohcip->ohci_hcca_cookie.dmac_address); 1814 1815 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1816 "ohci_init_hcca: size %lu", ohcip->ohci_hcca_cookie.dmac_size); 1817 1818 /* Initialize the interrupt lists */ 1819 ohci_build_interrupt_lattice(ohcip); 1820 1821 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1822 "ohci_init_hcca: End"); 1823 1824 return (DDI_SUCCESS); 1825 } 1826 1827 1828 /* 1829 * ohci_build_interrupt_lattice: 1830 * 1831 * Construct the interrupt lattice tree using static Endpoint Descriptors 1832 * (ED). This interrupt lattice tree will have total of 32 interrupt ED 1833 * lists and the Host Controller (HC) processes one interrupt ED list in 1834 * every frame. The lower five bits of the current frame number indexes 1835 * into an array of 32 interrupt Endpoint Descriptor lists found in the 1836 * HCCA. 1837 */ 1838 static void 1839 ohci_build_interrupt_lattice(ohci_state_t *ohcip) 1840 { 1841 ohci_ed_t *list_array = ohcip->ohci_ed_pool_addr; 1842 int half_list = NUM_INTR_ED_LISTS / 2; 1843 ohci_hcca_t *hccap = ohcip->ohci_hccap; 1844 uintptr_t addr; 1845 int i; 1846 1847 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1848 "ohci_build_interrupt_lattice:"); 1849 1850 /* 1851 * Reserve the first 31 Endpoint Descriptor (ED) structures 1852 * in the pool as static endpoints & these are required for 1853 * constructing interrupt lattice tree. 1854 */ 1855 for (i = 0; i < NUM_STATIC_NODES; i++) { 1856 Set_ED(list_array[i].hced_ctrl, HC_EPT_sKip); 1857 1858 Set_ED(list_array[i].hced_state, HC_EPT_STATIC); 1859 } 1860 1861 /* Build the interrupt lattice tree */ 1862 for (i = 0; i < half_list - 1; i++) { 1863 1864 /* 1865 * The next pointer in the host controller endpoint 1866 * descriptor must contain an iommu address. Calculate 1867 * the offset into the cpu address and add this to the 1868 * starting iommu address. 1869 */ 1870 addr = ohci_ed_cpu_to_iommu(ohcip, (ohci_ed_t *)&list_array[i]); 1871 1872 Set_ED(list_array[2*i + 1].hced_next, addr); 1873 Set_ED(list_array[2*i + 2].hced_next, addr); 1874 } 1875 1876 /* 1877 * Initialize the interrupt list in the HCCA so that it points 1878 * to the bottom of the tree. 1879 */ 1880 for (i = 0; i < half_list; i++) { 1881 addr = ohci_ed_cpu_to_iommu(ohcip, 1882 (ohci_ed_t *)&list_array[half_list - 1 + ohci_index[i]]); 1883 1884 ASSERT(Get_ED(list_array[half_list - 1 + 1885 ohci_index[i]].hced_ctrl)); 1886 1887 ASSERT(addr != 0); 1888 1889 Set_HCCA(hccap->HccaIntTble[i], addr); 1890 Set_HCCA(hccap->HccaIntTble[i + half_list], addr); 1891 } 1892 } 1893 1894 1895 /* 1896 * ohci_take_control: 1897 * 1898 * Take control of the host controller. OpenHCI allows for optional support 1899 * of legacy devices through the use of System Management Mode software and 1900 * system Management interrupt hardware. See section 5.1.1.3 of the OpenHCI 1901 * spec for more details. 1902 */ 1903 static int 1904 ohci_take_control(ohci_state_t *ohcip) 1905 { 1906 #if defined(__x86) 1907 uint32_t hcr_control_val; 1908 uint32_t hcr_cmd_status_val; 1909 int wait; 1910 #endif /* __x86 */ 1911 1912 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1913 "ohci_take_control:"); 1914 1915 #if defined(__x86) 1916 /* 1917 * On x86, we must tell the BIOS we want the controller, 1918 * and wait for it to respond that we can have it. 1919 */ 1920 hcr_control_val = Get_OpReg(hcr_control); 1921 if ((hcr_control_val & HCR_CONTROL_IR) == 0) { 1922 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1923 "ohci_take_control: InterruptRouting off\n"); 1924 1925 return (DDI_SUCCESS); 1926 } 1927 1928 /* attempt the OwnershipChange request */ 1929 hcr_cmd_status_val = Get_OpReg(hcr_cmd_status); 1930 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1931 "ohci_take_control: hcr_cmd_status: 0x%x\n", 1932 hcr_cmd_status_val); 1933 hcr_cmd_status_val |= HCR_STATUS_OCR; 1934 1935 Set_OpReg(hcr_cmd_status, hcr_cmd_status_val); 1936 1937 1938 mutex_exit(&ohcip->ohci_int_mutex); 1939 /* now wait for 5 seconds for InterruptRouting to go away */ 1940 for (wait = 0; wait < 5000; wait++) { 1941 if ((Get_OpReg(hcr_control) & HCR_CONTROL_IR) == 0) 1942 break; 1943 delay(drv_usectohz(1000)); 1944 } 1945 mutex_enter(&ohcip->ohci_int_mutex); 1946 1947 if (wait >= 5000) { 1948 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1949 "ohci_take_control: couldn't take control from BIOS\n"); 1950 1951 return (DDI_FAILURE); 1952 } 1953 #else /* __x86 */ 1954 /* 1955 * On Sparc, there won't be special System Management Mode 1956 * hardware for legacy devices, while the x86 platforms may 1957 * have to deal with this. This function may be platform 1958 * specific. 1959 * 1960 * The interrupt routing bit should not be set. 1961 */ 1962 if (Get_OpReg(hcr_control) & HCR_CONTROL_IR) { 1963 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1964 "ohci_take_control: Routing bit set"); 1965 1966 return (DDI_FAILURE); 1967 } 1968 #endif /* __x86 */ 1969 1970 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 1971 "ohci_take_control: End"); 1972 1973 return (DDI_SUCCESS); 1974 } 1975 1976 /* 1977 * ohci_pm_support: 1978 * always return success since PM has been quite reliable on ohci 1979 */ 1980 /*ARGSUSED*/ 1981 int 1982 ohci_hcdi_pm_support(dev_info_t *dip) 1983 { 1984 return (USB_SUCCESS); 1985 } 1986 1987 /* 1988 * ohci_alloc_hcdi_ops: 1989 * 1990 * The HCDI interfaces or entry points are the software interfaces used by 1991 * the Universal Serial Bus Driver (USBA) to access the services of the 1992 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1993 * about all available HCDI interfaces or entry points. 1994 */ 1995 static usba_hcdi_ops_t * 1996 ohci_alloc_hcdi_ops(ohci_state_t *ohcip) 1997 { 1998 usba_hcdi_ops_t *usba_hcdi_ops; 1999 2000 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2001 "ohci_alloc_hcdi_ops:"); 2002 2003 usba_hcdi_ops = usba_alloc_hcdi_ops(); 2004 2005 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 2006 2007 usba_hcdi_ops->usba_hcdi_pm_support = ohci_hcdi_pm_support; 2008 usba_hcdi_ops->usba_hcdi_pipe_open = ohci_hcdi_pipe_open; 2009 usba_hcdi_ops->usba_hcdi_pipe_close = ohci_hcdi_pipe_close; 2010 2011 usba_hcdi_ops->usba_hcdi_pipe_reset = ohci_hcdi_pipe_reset; 2012 2013 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ohci_hcdi_pipe_ctrl_xfer; 2014 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ohci_hcdi_pipe_bulk_xfer; 2015 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ohci_hcdi_pipe_intr_xfer; 2016 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ohci_hcdi_pipe_isoc_xfer; 2017 2018 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 2019 ohci_hcdi_bulk_transfer_size; 2020 2021 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 2022 ohci_hcdi_pipe_stop_intr_polling; 2023 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 2024 ohci_hcdi_pipe_stop_isoc_polling; 2025 2026 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 2027 ohci_hcdi_get_current_frame_number; 2028 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 2029 ohci_hcdi_get_max_isoc_pkts; 2030 usba_hcdi_ops->usba_hcdi_console_input_init = 2031 ohci_hcdi_polled_input_init; 2032 usba_hcdi_ops->usba_hcdi_console_input_enter = 2033 ohci_hcdi_polled_input_enter; 2034 usba_hcdi_ops->usba_hcdi_console_read = ohci_hcdi_polled_read; 2035 usba_hcdi_ops->usba_hcdi_console_input_exit = 2036 ohci_hcdi_polled_input_exit; 2037 usba_hcdi_ops->usba_hcdi_console_input_fini = 2038 ohci_hcdi_polled_input_fini; 2039 2040 return (usba_hcdi_ops); 2041 } 2042 2043 2044 /* 2045 * Host Controller Driver (HCD) deinitialization functions 2046 */ 2047 2048 /* 2049 * ohci_cleanup: 2050 * 2051 * Cleanup on attach failure or detach 2052 */ 2053 static int 2054 ohci_cleanup(ohci_state_t *ohcip) 2055 { 2056 ohci_trans_wrapper_t *tw; 2057 ohci_pipe_private_t *pp; 2058 ohci_td_t *td; 2059 int i, state, rval; 2060 int flags = ohcip->ohci_flags; 2061 2062 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, "ohci_cleanup:"); 2063 2064 if (flags & OHCI_RHREG) { 2065 /* Unload the root hub driver */ 2066 if (ohci_unload_root_hub_driver(ohcip) != USB_SUCCESS) { 2067 2068 return (DDI_FAILURE); 2069 } 2070 } 2071 2072 if (flags & OHCI_USBAREG) { 2073 /* Unregister this HCD instance with USBA */ 2074 usba_hcdi_unregister(ohcip->ohci_dip); 2075 } 2076 2077 if (flags & OHCI_INTR) { 2078 2079 mutex_enter(&ohcip->ohci_int_mutex); 2080 2081 /* Disable all HC ED list processing */ 2082 Set_OpReg(hcr_control, 2083 (Get_OpReg(hcr_control) & ~(HCR_CONTROL_CLE | 2084 HCR_CONTROL_BLE | HCR_CONTROL_PLE | HCR_CONTROL_IE))); 2085 2086 /* Disable all HC interrupts */ 2087 Set_OpReg(hcr_intr_disable, 2088 (HCR_INTR_SO | HCR_INTR_WDH | HCR_INTR_RD | HCR_INTR_UE)); 2089 2090 /* Wait for the next SOF */ 2091 (void) ohci_wait_for_sof(ohcip); 2092 2093 /* Disable Master and SOF interrupts */ 2094 Set_OpReg(hcr_intr_disable, (HCR_INTR_MIE | HCR_INTR_SOF)); 2095 2096 /* Set the Host Controller Functional State to Reset */ 2097 Set_OpReg(hcr_control, ((Get_OpReg(hcr_control) & 2098 (~HCR_CONTROL_HCFS)) | HCR_CONTROL_RESET)); 2099 2100 mutex_exit(&ohcip->ohci_int_mutex); 2101 /* Wait for sometime */ 2102 delay(drv_usectohz(OHCI_TIMEWAIT)); 2103 mutex_enter(&ohcip->ohci_int_mutex); 2104 2105 /* 2106 * Workaround for ULI1575 chipset. Following OHCI Operational 2107 * Memory Registers are not cleared to their default value 2108 * on reset. Explicitly set the registers to default value. 2109 */ 2110 if (ohcip->ohci_vendor_id == PCI_ULI1575_VENID && 2111 ohcip->ohci_device_id == PCI_ULI1575_DEVID) { 2112 Set_OpReg(hcr_control, HCR_CONTROL_DEFAULT); 2113 Set_OpReg(hcr_intr_enable, HCR_INT_ENABLE_DEFAULT); 2114 Set_OpReg(hcr_HCCA, HCR_HCCA_DEFAULT); 2115 Set_OpReg(hcr_ctrl_head, HCR_CONTROL_HEAD_ED_DEFAULT); 2116 Set_OpReg(hcr_bulk_head, HCR_BULK_HEAD_ED_DEFAULT); 2117 Set_OpReg(hcr_frame_interval, 2118 HCR_FRAME_INTERVAL_DEFAULT); 2119 Set_OpReg(hcr_periodic_strt, 2120 HCR_PERIODIC_START_DEFAULT); 2121 } 2122 2123 mutex_exit(&ohcip->ohci_int_mutex); 2124 2125 ohci_rem_intrs(ohcip); 2126 } 2127 2128 /* Unmap the OHCI registers */ 2129 if (ohcip->ohci_regs_handle) { 2130 /* Reset the host controller */ 2131 Set_OpReg(hcr_cmd_status, HCR_STATUS_RESET); 2132 2133 ddi_regs_map_free(&ohcip->ohci_regs_handle); 2134 } 2135 2136 if (ohcip->ohci_config_handle) { 2137 pci_config_teardown(&ohcip->ohci_config_handle); 2138 } 2139 2140 /* Free all the buffers */ 2141 if (ohcip->ohci_td_pool_addr && ohcip->ohci_td_pool_mem_handle) { 2142 for (i = 0; i < ohci_td_pool_size; i ++) { 2143 td = &ohcip->ohci_td_pool_addr[i]; 2144 state = Get_TD(ohcip->ohci_td_pool_addr[i].hctd_state); 2145 2146 if ((state != HC_TD_FREE) && (state != HC_TD_DUMMY) && 2147 (td->hctd_trans_wrapper)) { 2148 2149 mutex_enter(&ohcip->ohci_int_mutex); 2150 2151 tw = (ohci_trans_wrapper_t *) 2152 OHCI_LOOKUP_ID((uint32_t) 2153 Get_TD(td->hctd_trans_wrapper)); 2154 2155 /* Obtain the pipe private structure */ 2156 pp = tw->tw_pipe_private; 2157 2158 /* Stop the the transfer timer */ 2159 ohci_stop_xfer_timer(ohcip, tw, 2160 OHCI_REMOVE_XFER_ALWAYS); 2161 2162 ohci_deallocate_tw_resources(ohcip, pp, tw); 2163 2164 mutex_exit(&ohcip->ohci_int_mutex); 2165 } 2166 } 2167 2168 /* 2169 * If OHCI_TD_POOL_BOUND flag is set, then unbind 2170 * the handle for TD pools. 2171 */ 2172 if ((ohcip->ohci_dma_addr_bind_flag & 2173 OHCI_TD_POOL_BOUND) == OHCI_TD_POOL_BOUND) { 2174 2175 rval = ddi_dma_unbind_handle( 2176 ohcip->ohci_td_pool_dma_handle); 2177 2178 ASSERT(rval == DDI_SUCCESS); 2179 } 2180 ddi_dma_mem_free(&ohcip->ohci_td_pool_mem_handle); 2181 } 2182 2183 /* Free the TD pool */ 2184 if (ohcip->ohci_td_pool_dma_handle) { 2185 ddi_dma_free_handle(&ohcip->ohci_td_pool_dma_handle); 2186 } 2187 2188 if (ohcip->ohci_ed_pool_addr && ohcip->ohci_ed_pool_mem_handle) { 2189 /* 2190 * If OHCI_ED_POOL_BOUND flag is set, then unbind 2191 * the handle for ED pools. 2192 */ 2193 if ((ohcip->ohci_dma_addr_bind_flag & 2194 OHCI_ED_POOL_BOUND) == OHCI_ED_POOL_BOUND) { 2195 2196 rval = ddi_dma_unbind_handle( 2197 ohcip->ohci_ed_pool_dma_handle); 2198 2199 ASSERT(rval == DDI_SUCCESS); 2200 } 2201 2202 ddi_dma_mem_free(&ohcip->ohci_ed_pool_mem_handle); 2203 } 2204 2205 /* Free the ED pool */ 2206 if (ohcip->ohci_ed_pool_dma_handle) { 2207 ddi_dma_free_handle(&ohcip->ohci_ed_pool_dma_handle); 2208 } 2209 2210 /* Free the HCCA area */ 2211 if (ohcip->ohci_hccap && ohcip->ohci_hcca_mem_handle) { 2212 /* 2213 * If OHCI_HCCA_DMA_BOUND flag is set, then unbind 2214 * the handle for HCCA. 2215 */ 2216 if ((ohcip->ohci_dma_addr_bind_flag & 2217 OHCI_HCCA_DMA_BOUND) == OHCI_HCCA_DMA_BOUND) { 2218 2219 rval = ddi_dma_unbind_handle( 2220 ohcip->ohci_hcca_dma_handle); 2221 2222 ASSERT(rval == DDI_SUCCESS); 2223 } 2224 2225 ddi_dma_mem_free(&ohcip->ohci_hcca_mem_handle); 2226 } 2227 2228 if (ohcip->ohci_hcca_dma_handle) { 2229 ddi_dma_free_handle(&ohcip->ohci_hcca_dma_handle); 2230 } 2231 2232 if (flags & OHCI_INTR) { 2233 2234 /* Destroy the mutex */ 2235 mutex_destroy(&ohcip->ohci_int_mutex); 2236 2237 /* Destroy the SOF condition varibale */ 2238 cv_destroy(&ohcip->ohci_SOF_cv); 2239 2240 /* Destroy the serialize opens and closes semaphore */ 2241 sema_destroy(&ohcip->ohci_ocsem); 2242 } 2243 2244 /* clean up kstat structs */ 2245 ohci_destroy_stats(ohcip); 2246 2247 /* Free ohci hcdi ops */ 2248 if (ohcip->ohci_hcdi_ops) { 2249 usba_free_hcdi_ops(ohcip->ohci_hcdi_ops); 2250 } 2251 2252 if (flags & OHCI_ZALLOC) { 2253 2254 usb_free_log_hdl(ohcip->ohci_log_hdl); 2255 2256 /* Remove all properties that might have been created */ 2257 ddi_prop_remove_all(ohcip->ohci_dip); 2258 2259 /* Free the soft state */ 2260 ddi_soft_state_free(ohci_statep, 2261 ddi_get_instance(ohcip->ohci_dip)); 2262 } 2263 2264 return (DDI_SUCCESS); 2265 } 2266 2267 2268 /* 2269 * ohci_rem_intrs: 2270 * 2271 * Unregister FIXED or MSI interrupts 2272 */ 2273 static void 2274 ohci_rem_intrs(ohci_state_t *ohcip) 2275 { 2276 int i; 2277 2278 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2279 "ohci_rem_intrs: interrupt type 0x%x", ohcip->ohci_intr_type); 2280 2281 /* Disable all interrupts */ 2282 if (ohcip->ohci_intr_cap & DDI_INTR_FLAG_BLOCK) { 2283 (void) ddi_intr_block_disable(ohcip->ohci_htable, 2284 ohcip->ohci_intr_cnt); 2285 } else { 2286 for (i = 0; i < ohcip->ohci_intr_cnt; i++) { 2287 (void) ddi_intr_disable(ohcip->ohci_htable[i]); 2288 } 2289 } 2290 2291 /* Call ddi_intr_remove_handler() */ 2292 for (i = 0; i < ohcip->ohci_intr_cnt; i++) { 2293 (void) ddi_intr_remove_handler(ohcip->ohci_htable[i]); 2294 (void) ddi_intr_free(ohcip->ohci_htable[i]); 2295 } 2296 2297 kmem_free(ohcip->ohci_htable, 2298 ohcip->ohci_intr_cnt * sizeof (ddi_intr_handle_t)); 2299 } 2300 2301 2302 /* 2303 * ohci_cpr_suspend 2304 */ 2305 static int 2306 ohci_cpr_suspend(ohci_state_t *ohcip) 2307 { 2308 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2309 "ohci_cpr_suspend:"); 2310 2311 /* Call into the root hub and suspend it */ 2312 if (usba_hubdi_detach(ohcip->ohci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 2313 2314 return (DDI_FAILURE); 2315 } 2316 2317 /* Only root hub's intr pipe should be open at this time */ 2318 mutex_enter(&ohcip->ohci_int_mutex); 2319 2320 if (ohcip->ohci_open_pipe_count > 1) { 2321 2322 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2323 "ohci_cpr_suspend: fails as open pipe count = %d", 2324 ohcip->ohci_open_pipe_count); 2325 2326 mutex_exit(&ohcip->ohci_int_mutex); 2327 2328 return (DDI_FAILURE); 2329 } 2330 2331 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2332 "ohci_cpr_suspend: Disable HC ED list processing"); 2333 2334 /* Disable all HC ED list processing */ 2335 Set_OpReg(hcr_control, (Get_OpReg(hcr_control) & ~(HCR_CONTROL_CLE | 2336 HCR_CONTROL_BLE | HCR_CONTROL_PLE | HCR_CONTROL_IE))); 2337 2338 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2339 "ohci_cpr_suspend: Disable HC interrupts"); 2340 2341 /* Disable all HC interrupts */ 2342 Set_OpReg(hcr_intr_disable, ~(HCR_INTR_MIE|HCR_INTR_SOF)); 2343 2344 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2345 "ohci_cpr_suspend: Wait for the next SOF"); 2346 2347 /* Wait for the next SOF */ 2348 if (ohci_wait_for_sof(ohcip) != USB_SUCCESS) { 2349 2350 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2351 "ohci_cpr_suspend: ohci host controller suspend failed"); 2352 2353 mutex_exit(&ohcip->ohci_int_mutex); 2354 return (DDI_FAILURE); 2355 } 2356 2357 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2358 "ohci_cpr_suspend: Disable Master interrupt"); 2359 2360 /* 2361 * Disable Master interrupt so that ohci driver don't 2362 * get any ohci interrupts. 2363 */ 2364 Set_OpReg(hcr_intr_disable, HCR_INTR_MIE); 2365 2366 /* 2367 * Suspend the ohci host controller 2368 * if usb keyboard is not connected. 2369 */ 2370 if (ohcip->ohci_polled_kbd_count == 0 || force_ohci_off != 0) { 2371 Set_OpReg(hcr_control, HCR_CONTROL_SUSPD); 2372 } 2373 2374 /* Set host controller soft state to suspend */ 2375 ohcip->ohci_hc_soft_state = OHCI_CTLR_SUSPEND_STATE; 2376 2377 mutex_exit(&ohcip->ohci_int_mutex); 2378 2379 return (DDI_SUCCESS); 2380 } 2381 2382 2383 /* 2384 * ohci_cpr_resume 2385 */ 2386 static int 2387 ohci_cpr_resume(ohci_state_t *ohcip) 2388 { 2389 mutex_enter(&ohcip->ohci_int_mutex); 2390 2391 USB_DPRINTF_L4(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2392 "ohci_cpr_resume: Restart the controller"); 2393 2394 /* Cleanup ohci specific information across cpr */ 2395 ohci_cpr_cleanup(ohcip); 2396 2397 /* Restart the controller */ 2398 if (ohci_init_ctlr(ohcip) != DDI_SUCCESS) { 2399 2400 USB_DPRINTF_L2(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 2401 "ohci_cpr_resume: ohci host controller resume failed "); 2402 2403 mutex_exit(&ohcip->ohci_int_mutex); 2404 2405 return (DDI_FAILURE); 2406 } 2407 2408 mutex_exit(&ohcip->ohci_int_mutex); 2409 2410 /* Now resume the root hub */ 2411 if (usba_hubdi_attach(ohcip->ohci_dip, DDI_RESUME) != DDI_SUCCESS) { 2412 2413 return (DDI_FAILURE); 2414 } 2415 2416 return (DDI_SUCCESS); 2417 } 2418 2419 2420 /* 2421 * HCDI entry points 2422 * 2423 * The Host Controller Driver Interfaces (HCDI) are the software interfaces 2424 * between the Universal Serial Bus Layer (USBA) and the Host Controller 2425 * Driver (HCD). The HCDI interfaces or entry points are subject to change. 2426 */ 2427 2428 /* 2429 * ohci_hcdi_pipe_open: 2430 * 2431 * Member of HCD Ops structure and called during client specific pipe open 2432 * Add the pipe to the data structure representing the device and allocate 2433 * bandwidth for the pipe if it is a interrupt or isochronous endpoint. 2434 */ 2435 static int 2436 ohci_hcdi_pipe_open( 2437 usba_pipe_handle_data_t *ph, 2438 usb_flags_t flags) 2439 { 2440 ohci_state_t *ohcip = ohci_obtain_state( 2441 ph->p_usba_device->usb_root_hub_dip); 2442 usb_ep_descr_t *epdt = &ph->p_ep; 2443 int rval, error = USB_SUCCESS; 2444 int kmflag = (flags & USB_FLAGS_SLEEP) ? 2445 KM_SLEEP : KM_NOSLEEP; 2446 uint_t node = 0; 2447 ohci_pipe_private_t *pp; 2448 2449 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2450 "ohci_hcdi_pipe_open: addr = 0x%x, ep%d", 2451 ph->p_usba_device->usb_addr, 2452 epdt->bEndpointAddress & USB_EP_NUM_MASK); 2453 2454 sema_p(&ohcip->ohci_ocsem); 2455 2456 mutex_enter(&ohcip->ohci_int_mutex); 2457 rval = ohci_state_is_operational(ohcip); 2458 mutex_exit(&ohcip->ohci_int_mutex); 2459 2460 if (rval != USB_SUCCESS) { 2461 sema_v(&ohcip->ohci_ocsem); 2462 2463 return (rval); 2464 } 2465 2466 /* 2467 * Check and handle root hub pipe open. 2468 */ 2469 if (ph->p_usba_device->usb_addr == ROOT_HUB_ADDR) { 2470 2471 mutex_enter(&ohcip->ohci_int_mutex); 2472 error = ohci_handle_root_hub_pipe_open(ph, flags); 2473 mutex_exit(&ohcip->ohci_int_mutex); 2474 sema_v(&ohcip->ohci_ocsem); 2475 2476 return (error); 2477 } 2478 2479 /* 2480 * Opening of other pipes excluding root hub pipe are 2481 * handled below. Check whether pipe is already opened. 2482 */ 2483 if (ph->p_hcd_private) { 2484 USB_DPRINTF_L2(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2485 "ohci_hcdi_pipe_open: Pipe is already opened"); 2486 2487 sema_v(&ohcip->ohci_ocsem); 2488 2489 return (USB_FAILURE); 2490 } 2491 2492 /* 2493 * A portion of the bandwidth is reserved for the non-periodic 2494 * transfers, i.e control and bulk transfers in each of one 2495 * millisecond frame period & usually it will be 10% of frame 2496 * period. Hence there is no need to check for the available 2497 * bandwidth before adding the control or bulk endpoints. 2498 * 2499 * There is a need to check for the available bandwidth before 2500 * adding the periodic transfers, i.e interrupt & isochronous, 2501 * since all these periodic transfers are guaranteed transfers. 2502 * Usually 90% of the total frame time is reserved for periodic 2503 * transfers. 2504 */ 2505 if (OHCI_PERIODIC_ENDPOINT(epdt)) { 2506 2507 mutex_enter(&ohcip->ohci_int_mutex); 2508 mutex_enter(&ph->p_mutex); 2509 2510 error = ohci_allocate_bandwidth(ohcip, ph, &node); 2511 2512 if (error != USB_SUCCESS) { 2513 2514 USB_DPRINTF_L2(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2515 "ohci_hcdi_pipe_open: Bandwidth allocation failed"); 2516 2517 mutex_exit(&ph->p_mutex); 2518 mutex_exit(&ohcip->ohci_int_mutex); 2519 sema_v(&ohcip->ohci_ocsem); 2520 2521 return (error); 2522 } 2523 2524 mutex_exit(&ph->p_mutex); 2525 mutex_exit(&ohcip->ohci_int_mutex); 2526 } 2527 2528 /* Create the HCD pipe private structure */ 2529 pp = kmem_zalloc(sizeof (ohci_pipe_private_t), kmflag); 2530 2531 /* 2532 * Return failure if ohci pipe private 2533 * structure allocation fails. 2534 */ 2535 if (pp == NULL) { 2536 2537 mutex_enter(&ohcip->ohci_int_mutex); 2538 2539 /* Deallocate bandwidth */ 2540 if (OHCI_PERIODIC_ENDPOINT(epdt)) { 2541 2542 mutex_enter(&ph->p_mutex); 2543 ohci_deallocate_bandwidth(ohcip, ph); 2544 mutex_exit(&ph->p_mutex); 2545 } 2546 2547 mutex_exit(&ohcip->ohci_int_mutex); 2548 sema_v(&ohcip->ohci_ocsem); 2549 2550 return (USB_NO_RESOURCES); 2551 } 2552 2553 mutex_enter(&ohcip->ohci_int_mutex); 2554 2555 /* Store the node in the interrupt lattice */ 2556 pp->pp_node = node; 2557 2558 /* Create prototype for xfer completion condition variable */ 2559 cv_init(&pp->pp_xfer_cmpl_cv, NULL, CV_DRIVER, NULL); 2560 2561 /* Set the state of pipe as idle */ 2562 pp->pp_state = OHCI_PIPE_STATE_IDLE; 2563 2564 /* Store a pointer to the pipe handle */ 2565 pp->pp_pipe_handle = ph; 2566 2567 mutex_enter(&ph->p_mutex); 2568 2569 /* Store the pointer in the pipe handle */ 2570 ph->p_hcd_private = (usb_opaque_t)pp; 2571 2572 /* Store a copy of the pipe policy */ 2573 bcopy(&ph->p_policy, &pp->pp_policy, sizeof (usb_pipe_policy_t)); 2574 2575 mutex_exit(&ph->p_mutex); 2576 2577 /* Allocate the host controller endpoint descriptor */ 2578 pp->pp_ept = ohci_alloc_hc_ed(ohcip, ph); 2579 2580 if (pp->pp_ept == NULL) { 2581 USB_DPRINTF_L2(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2582 "ohci_hcdi_pipe_open: ED allocation failed"); 2583 2584 mutex_enter(&ph->p_mutex); 2585 2586 /* Deallocate bandwidth */ 2587 if (OHCI_PERIODIC_ENDPOINT(epdt)) { 2588 2589 ohci_deallocate_bandwidth(ohcip, ph); 2590 } 2591 2592 /* Destroy the xfer completion condition varibale */ 2593 cv_destroy(&pp->pp_xfer_cmpl_cv); 2594 2595 /* 2596 * Deallocate the hcd private portion 2597 * of the pipe handle. 2598 */ 2599 kmem_free(ph->p_hcd_private, sizeof (ohci_pipe_private_t)); 2600 2601 /* 2602 * Set the private structure in the 2603 * pipe handle equal to NULL. 2604 */ 2605 ph->p_hcd_private = NULL; 2606 mutex_exit(&ph->p_mutex); 2607 2608 mutex_exit(&ohcip->ohci_int_mutex); 2609 sema_v(&ohcip->ohci_ocsem); 2610 2611 return (USB_NO_RESOURCES); 2612 } 2613 2614 /* Restore the data toggle information */ 2615 ohci_restore_data_toggle(ohcip, ph); 2616 2617 /* 2618 * Insert the endpoint onto the host controller's 2619 * appropriate endpoint list. The host controller 2620 * will not schedule this endpoint and will not have 2621 * any TD's to process. 2622 */ 2623 ohci_insert_ed(ohcip, ph); 2624 2625 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2626 "ohci_hcdi_pipe_open: ph = 0x%p", (void *)ph); 2627 2628 ohcip->ohci_open_pipe_count++; 2629 2630 mutex_exit(&ohcip->ohci_int_mutex); 2631 2632 sema_v(&ohcip->ohci_ocsem); 2633 2634 return (USB_SUCCESS); 2635 } 2636 2637 2638 /* 2639 * ohci_hcdi_pipe_close: 2640 * 2641 * Member of HCD Ops structure and called during the client specific pipe 2642 * close. Remove the pipe and the data structure representing the device. 2643 * Deallocate bandwidth for the pipe if it is a interrupt or isochronous 2644 * endpoint. 2645 */ 2646 /* ARGSUSED */ 2647 static int 2648 ohci_hcdi_pipe_close( 2649 usba_pipe_handle_data_t *ph, 2650 usb_flags_t flags) 2651 { 2652 ohci_state_t *ohcip = ohci_obtain_state( 2653 ph->p_usba_device->usb_root_hub_dip); 2654 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 2655 usb_ep_descr_t *eptd = &ph->p_ep; 2656 int error = USB_SUCCESS; 2657 2658 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2659 "ohci_hcdi_pipe_close: addr = 0x%x, ep%d", 2660 ph->p_usba_device->usb_addr, 2661 eptd->bEndpointAddress & USB_EP_NUM_MASK); 2662 2663 sema_p(&ohcip->ohci_ocsem); 2664 2665 /* Check and handle root hub pipe close */ 2666 if (ph->p_usba_device->usb_addr == ROOT_HUB_ADDR) { 2667 2668 mutex_enter(&ohcip->ohci_int_mutex); 2669 error = ohci_handle_root_hub_pipe_close(ph); 2670 mutex_exit(&ohcip->ohci_int_mutex); 2671 sema_v(&ohcip->ohci_ocsem); 2672 2673 return (error); 2674 } 2675 2676 ASSERT(ph->p_hcd_private != NULL); 2677 2678 mutex_enter(&ohcip->ohci_int_mutex); 2679 2680 /* Set pipe state to pipe close */ 2681 pp->pp_state = OHCI_PIPE_STATE_CLOSE; 2682 2683 ohci_pipe_cleanup(ohcip, ph); 2684 2685 /* 2686 * Remove the endoint descriptor from Host 2687 * Controller's appropriate endpoint list. 2688 */ 2689 ohci_remove_ed(ohcip, pp); 2690 2691 /* Deallocate bandwidth */ 2692 if (OHCI_PERIODIC_ENDPOINT(eptd)) { 2693 2694 mutex_enter(&ph->p_mutex); 2695 ohci_deallocate_bandwidth(ohcip, ph); 2696 mutex_exit(&ph->p_mutex); 2697 } 2698 2699 mutex_enter(&ph->p_mutex); 2700 2701 /* Destroy the xfer completion condition varibale */ 2702 cv_destroy(&pp->pp_xfer_cmpl_cv); 2703 2704 /* 2705 * Deallocate the hcd private portion 2706 * of the pipe handle. 2707 */ 2708 kmem_free(ph->p_hcd_private, sizeof (ohci_pipe_private_t)); 2709 ph->p_hcd_private = NULL; 2710 2711 mutex_exit(&ph->p_mutex); 2712 2713 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2714 "ohci_hcdi_pipe_close: ph = 0x%p", (void *)ph); 2715 2716 ohcip->ohci_open_pipe_count--; 2717 2718 mutex_exit(&ohcip->ohci_int_mutex); 2719 sema_v(&ohcip->ohci_ocsem); 2720 2721 return (error); 2722 } 2723 2724 2725 /* 2726 * ohci_hcdi_pipe_reset: 2727 */ 2728 /* ARGSUSED */ 2729 static int 2730 ohci_hcdi_pipe_reset( 2731 usba_pipe_handle_data_t *ph, 2732 usb_flags_t usb_flags) 2733 { 2734 ohci_state_t *ohcip = ohci_obtain_state( 2735 ph->p_usba_device->usb_root_hub_dip); 2736 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 2737 int error = USB_SUCCESS; 2738 2739 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2740 "ohci_hcdi_pipe_reset: ph = 0x%p ", (void *)ph); 2741 2742 /* 2743 * Check and handle root hub pipe reset. 2744 */ 2745 if (ph->p_usba_device->usb_addr == ROOT_HUB_ADDR) { 2746 2747 error = ohci_handle_root_hub_pipe_reset(ph, usb_flags); 2748 return (error); 2749 } 2750 2751 mutex_enter(&ohcip->ohci_int_mutex); 2752 2753 /* Set pipe state to pipe reset */ 2754 pp->pp_state = OHCI_PIPE_STATE_RESET; 2755 2756 ohci_pipe_cleanup(ohcip, ph); 2757 2758 mutex_exit(&ohcip->ohci_int_mutex); 2759 2760 return (error); 2761 } 2762 2763 2764 /* 2765 * ohci_hcdi_pipe_ctrl_xfer: 2766 */ 2767 static int 2768 ohci_hcdi_pipe_ctrl_xfer( 2769 usba_pipe_handle_data_t *ph, 2770 usb_ctrl_req_t *ctrl_reqp, 2771 usb_flags_t usb_flags) 2772 { 2773 ohci_state_t *ohcip = ohci_obtain_state( 2774 ph->p_usba_device->usb_root_hub_dip); 2775 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 2776 int rval; 2777 int error = USB_SUCCESS; 2778 ohci_trans_wrapper_t *tw; 2779 2780 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2781 "ohci_hcdi_pipe_ctrl_xfer: ph = 0x%p reqp = 0x%p flags = 0x%x", 2782 (void *)ph, ctrl_reqp, usb_flags); 2783 2784 mutex_enter(&ohcip->ohci_int_mutex); 2785 rval = ohci_state_is_operational(ohcip); 2786 mutex_exit(&ohcip->ohci_int_mutex); 2787 2788 if (rval != USB_SUCCESS) { 2789 2790 return (rval); 2791 } 2792 2793 /* 2794 * Check and handle root hub control request. 2795 */ 2796 if (ph->p_usba_device->usb_addr == ROOT_HUB_ADDR) { 2797 2798 error = ohci_handle_root_hub_request(ohcip, ph, ctrl_reqp); 2799 2800 return (error); 2801 } 2802 2803 mutex_enter(&ohcip->ohci_int_mutex); 2804 2805 /* 2806 * Check whether pipe is in halted state. 2807 */ 2808 if (pp->pp_state == OHCI_PIPE_STATE_ERROR) { 2809 2810 USB_DPRINTF_L2(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2811 "ohci_hcdi_pipe_ctrl_xfer:" 2812 "Pipe is in error state, need pipe reset to continue"); 2813 2814 mutex_exit(&ohcip->ohci_int_mutex); 2815 2816 return (USB_FAILURE); 2817 } 2818 2819 /* Allocate a transfer wrapper */ 2820 if ((tw = ohci_allocate_ctrl_resources(ohcip, pp, ctrl_reqp, 2821 usb_flags)) == NULL) { 2822 2823 error = USB_NO_RESOURCES; 2824 } else { 2825 /* Insert the td's on the endpoint */ 2826 ohci_insert_ctrl_req(ohcip, ph, ctrl_reqp, tw, usb_flags); 2827 } 2828 2829 mutex_exit(&ohcip->ohci_int_mutex); 2830 2831 return (error); 2832 } 2833 2834 2835 /* 2836 * ohci_hcdi_bulk_transfer_size: 2837 * 2838 * Return maximum bulk transfer size 2839 */ 2840 2841 /* ARGSUSED */ 2842 static int 2843 ohci_hcdi_bulk_transfer_size( 2844 usba_device_t *usba_device, 2845 size_t *size) 2846 { 2847 ohci_state_t *ohcip = ohci_obtain_state( 2848 usba_device->usb_root_hub_dip); 2849 int rval; 2850 2851 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2852 "ohci_hcdi_bulk_transfer_size:"); 2853 2854 mutex_enter(&ohcip->ohci_int_mutex); 2855 rval = ohci_state_is_operational(ohcip); 2856 mutex_exit(&ohcip->ohci_int_mutex); 2857 2858 if (rval != USB_SUCCESS) { 2859 2860 return (rval); 2861 } 2862 2863 *size = OHCI_MAX_BULK_XFER_SIZE; 2864 2865 return (USB_SUCCESS); 2866 } 2867 2868 2869 /* 2870 * ohci_hcdi_pipe_bulk_xfer: 2871 */ 2872 static int 2873 ohci_hcdi_pipe_bulk_xfer( 2874 usba_pipe_handle_data_t *ph, 2875 usb_bulk_req_t *bulk_reqp, 2876 usb_flags_t usb_flags) 2877 { 2878 ohci_state_t *ohcip = ohci_obtain_state( 2879 ph->p_usba_device->usb_root_hub_dip); 2880 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 2881 int rval, error = USB_SUCCESS; 2882 ohci_trans_wrapper_t *tw; 2883 2884 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2885 "ohci_hcdi_pipe_bulk_xfer: ph = 0x%p reqp = 0x%p flags = 0x%x", 2886 (void *)ph, bulk_reqp, usb_flags); 2887 2888 mutex_enter(&ohcip->ohci_int_mutex); 2889 rval = ohci_state_is_operational(ohcip); 2890 2891 if (rval != USB_SUCCESS) { 2892 mutex_exit(&ohcip->ohci_int_mutex); 2893 2894 return (rval); 2895 } 2896 2897 /* 2898 * Check whether pipe is in halted state. 2899 */ 2900 if (pp->pp_state == OHCI_PIPE_STATE_ERROR) { 2901 2902 USB_DPRINTF_L2(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2903 "ohci_hcdi_pipe_bulk_xfer:" 2904 "Pipe is in error state, need pipe reset to continue"); 2905 2906 mutex_exit(&ohcip->ohci_int_mutex); 2907 2908 return (USB_FAILURE); 2909 } 2910 2911 /* Allocate a transfer wrapper */ 2912 if ((tw = ohci_allocate_bulk_resources(ohcip, pp, bulk_reqp, 2913 usb_flags)) == NULL) { 2914 2915 error = USB_NO_RESOURCES; 2916 } else { 2917 /* Add the TD into the Host Controller's bulk list */ 2918 ohci_insert_bulk_req(ohcip, ph, bulk_reqp, tw, usb_flags); 2919 } 2920 2921 mutex_exit(&ohcip->ohci_int_mutex); 2922 2923 return (error); 2924 } 2925 2926 2927 /* 2928 * ohci_hcdi_pipe_intr_xfer: 2929 */ 2930 static int 2931 ohci_hcdi_pipe_intr_xfer( 2932 usba_pipe_handle_data_t *ph, 2933 usb_intr_req_t *intr_reqp, 2934 usb_flags_t usb_flags) 2935 { 2936 ohci_state_t *ohcip = ohci_obtain_state( 2937 ph->p_usba_device->usb_root_hub_dip); 2938 int pipe_dir, rval, error = USB_SUCCESS; 2939 ohci_trans_wrapper_t *tw; 2940 2941 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2942 "ohci_hcdi_pipe_intr_xfer: ph = 0x%p reqp = 0x%p flags = 0x%x", 2943 (void *)ph, intr_reqp, usb_flags); 2944 2945 mutex_enter(&ohcip->ohci_int_mutex); 2946 rval = ohci_state_is_operational(ohcip); 2947 2948 if (rval != USB_SUCCESS) { 2949 mutex_exit(&ohcip->ohci_int_mutex); 2950 2951 return (rval); 2952 } 2953 2954 /* Get the pipe direction */ 2955 pipe_dir = ph->p_ep.bEndpointAddress & USB_EP_DIR_MASK; 2956 2957 if (pipe_dir == USB_EP_DIR_IN) { 2958 error = ohci_start_periodic_pipe_polling(ohcip, ph, 2959 (usb_opaque_t)intr_reqp, usb_flags); 2960 } else { 2961 /* Allocate transaction resources */ 2962 if ((tw = ohci_allocate_intr_resources(ohcip, ph, 2963 intr_reqp, usb_flags)) == NULL) { 2964 error = USB_NO_RESOURCES; 2965 } else { 2966 ohci_insert_intr_req(ohcip, 2967 (ohci_pipe_private_t *)ph->p_hcd_private, 2968 tw, usb_flags); 2969 } 2970 } 2971 2972 mutex_exit(&ohcip->ohci_int_mutex); 2973 2974 return (error); 2975 } 2976 2977 2978 /* 2979 * ohci_hcdi_pipe_stop_intr_polling() 2980 */ 2981 static int 2982 ohci_hcdi_pipe_stop_intr_polling( 2983 usba_pipe_handle_data_t *ph, 2984 usb_flags_t flags) 2985 { 2986 ohci_state_t *ohcip = ohci_obtain_state( 2987 ph->p_usba_device->usb_root_hub_dip); 2988 int error = USB_SUCCESS; 2989 2990 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 2991 "ohci_hcdi_pipe_stop_intr_polling: ph = 0x%p fl = 0x%x", 2992 ph, flags); 2993 2994 mutex_enter(&ohcip->ohci_int_mutex); 2995 2996 error = ohci_stop_periodic_pipe_polling(ohcip, ph, flags); 2997 2998 mutex_exit(&ohcip->ohci_int_mutex); 2999 3000 return (error); 3001 } 3002 3003 3004 /* 3005 * ohci_hcdi_get_current_frame_number: 3006 * 3007 * Get the current usb frame number. 3008 * Return whether the request is handled successfully. 3009 */ 3010 static int 3011 ohci_hcdi_get_current_frame_number( 3012 usba_device_t *usba_device, 3013 usb_frame_number_t *frame_number) 3014 { 3015 ohci_state_t *ohcip = ohci_obtain_state( 3016 usba_device->usb_root_hub_dip); 3017 int rval; 3018 3019 ohcip = ohci_obtain_state(usba_device->usb_root_hub_dip); 3020 3021 mutex_enter(&ohcip->ohci_int_mutex); 3022 rval = ohci_state_is_operational(ohcip); 3023 3024 if (rval != USB_SUCCESS) { 3025 mutex_exit(&ohcip->ohci_int_mutex); 3026 3027 return (rval); 3028 } 3029 3030 *frame_number = ohci_get_current_frame_number(ohcip); 3031 3032 mutex_exit(&ohcip->ohci_int_mutex); 3033 3034 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 3035 "ohci_hcdi_get_current_frame_number:" 3036 "Current frame number 0x%llx", frame_number); 3037 3038 return (rval); 3039 } 3040 3041 3042 /* 3043 * ohci_hcdi_get_max_isoc_pkts: 3044 * 3045 * Get maximum isochronous packets per usb isochronous request. 3046 * Return whether the request is handled successfully. 3047 */ 3048 static int 3049 ohci_hcdi_get_max_isoc_pkts( 3050 usba_device_t *usba_device, 3051 uint_t *max_isoc_pkts_per_request) 3052 { 3053 ohci_state_t *ohcip = ohci_obtain_state( 3054 usba_device->usb_root_hub_dip); 3055 int rval; 3056 3057 mutex_enter(&ohcip->ohci_int_mutex); 3058 rval = ohci_state_is_operational(ohcip); 3059 mutex_exit(&ohcip->ohci_int_mutex); 3060 3061 if (rval != USB_SUCCESS) { 3062 3063 return (rval); 3064 } 3065 3066 *max_isoc_pkts_per_request = OHCI_MAX_ISOC_PKTS_PER_XFER; 3067 3068 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 3069 "ohci_hcdi_get_max_isoc_pkts: maximum isochronous" 3070 "packets per usb isochronous request = 0x%x", 3071 max_isoc_pkts_per_request); 3072 3073 return (rval); 3074 } 3075 3076 3077 /* 3078 * ohci_hcdi_pipe_isoc_xfer: 3079 */ 3080 static int 3081 ohci_hcdi_pipe_isoc_xfer( 3082 usba_pipe_handle_data_t *ph, 3083 usb_isoc_req_t *isoc_reqp, 3084 usb_flags_t usb_flags) 3085 { 3086 ohci_state_t *ohcip = ohci_obtain_state( 3087 ph->p_usba_device->usb_root_hub_dip); 3088 int error = USB_SUCCESS; 3089 int pipe_dir, rval; 3090 ohci_trans_wrapper_t *tw; 3091 3092 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 3093 "ohci_hcdi_pipe_isoc_xfer: ph = 0x%p reqp = 0x%p flags = 0x%x", 3094 (void *)ph, isoc_reqp, usb_flags); 3095 3096 mutex_enter(&ohcip->ohci_int_mutex); 3097 rval = ohci_state_is_operational(ohcip); 3098 3099 if (rval != USB_SUCCESS) { 3100 mutex_exit(&ohcip->ohci_int_mutex); 3101 3102 return (rval); 3103 } 3104 3105 /* Get the isochronous pipe direction */ 3106 pipe_dir = ph->p_ep.bEndpointAddress & USB_EP_DIR_MASK; 3107 3108 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 3109 "ohci_hcdi_pipe_isoc_xfer: isoc_reqp = 0x%p, uf = 0x%x", 3110 isoc_reqp, usb_flags); 3111 3112 if (pipe_dir == USB_EP_DIR_IN) { 3113 error = ohci_start_periodic_pipe_polling(ohcip, ph, 3114 (usb_opaque_t)isoc_reqp, usb_flags); 3115 } else { 3116 /* Allocate transaction resources */ 3117 if ((tw = ohci_allocate_isoc_resources(ohcip, ph, 3118 isoc_reqp, usb_flags)) == NULL) { 3119 error = USB_NO_RESOURCES; 3120 } else { 3121 error = ohci_insert_isoc_req(ohcip, 3122 (ohci_pipe_private_t *)ph->p_hcd_private, 3123 tw, usb_flags); 3124 } 3125 } 3126 3127 mutex_exit(&ohcip->ohci_int_mutex); 3128 3129 return (error); 3130 } 3131 3132 3133 /* 3134 * ohci_hcdi_pipe_stop_isoc_polling() 3135 */ 3136 static int 3137 ohci_hcdi_pipe_stop_isoc_polling( 3138 usba_pipe_handle_data_t *ph, 3139 usb_flags_t flags) 3140 { 3141 ohci_state_t *ohcip = ohci_obtain_state( 3142 ph->p_usba_device->usb_root_hub_dip); 3143 int rval, error = USB_SUCCESS; 3144 3145 USB_DPRINTF_L4(PRINT_MASK_HCDI, ohcip->ohci_log_hdl, 3146 "ohci_hcdi_pipe_stop_isoc_polling: ph = 0x%p fl = 0x%x", 3147 (void *)ph, flags); 3148 3149 mutex_enter(&ohcip->ohci_int_mutex); 3150 rval = ohci_state_is_operational(ohcip); 3151 3152 if (rval != USB_SUCCESS) { 3153 mutex_exit(&ohcip->ohci_int_mutex); 3154 return (rval); 3155 } 3156 3157 error = ohci_stop_periodic_pipe_polling(ohcip, ph, flags); 3158 3159 mutex_exit(&ohcip->ohci_int_mutex); 3160 return (error); 3161 } 3162 3163 3164 /* 3165 * Bandwidth Allocation functions 3166 */ 3167 3168 /* 3169 * ohci_allocate_bandwidth: 3170 * 3171 * Figure out whether or not this interval may be supported. Return the index 3172 * into the lattice if it can be supported. Return allocation failure if it 3173 * can not be supported. 3174 * 3175 * The lattice structure looks like this with the bottom leaf actually 3176 * being an array. There is a total of 63 nodes in this tree. The lattice tree 3177 * itself is 0 based, while the bottom leaf array is 0 based. The 0 bucket in 3178 * the bottom leaf array is used to store the smalled allocated bandwidth of all 3179 * the leaves. 3180 * 3181 * 0 3182 * 1 2 3183 * 3 4 5 6 3184 * ... 3185 * (32 33 ... 62 63) <-- last row does not exist in lattice, but an array 3186 * 0 1 2 3 ... 30 31 3187 * 3188 * We keep track of the bandwidth that each leaf uses. First we search for the 3189 * first leaf with the smallest used bandwidth. Based on that leaf we find the 3190 * parent node of that leaf based on the interval time. 3191 * 3192 * From the parent node, we find all the leafs of that subtree and update the 3193 * additional bandwidth needed. In order to balance the load the leaves are not 3194 * executed directly from left to right, but scattered. For a better picture 3195 * refer to Section 3.3.2 in the OpenHCI 1.0 spec, there should be a figure 3196 * showing the Interrupt ED Structure. 3197 */ 3198 static int 3199 ohci_allocate_bandwidth( 3200 ohci_state_t *ohcip, 3201 usba_pipe_handle_data_t *ph, 3202 uint_t *node) 3203 { 3204 int interval, error, i; 3205 uint_t min, min_index, height; 3206 uint_t leftmost, list, bandwidth; 3207 usb_ep_descr_t *endpoint = &ph->p_ep; 3208 3209 /* This routine is protected by the ohci_int_mutex */ 3210 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 3211 3212 /* 3213 * Calculate the length in bytes of a transaction on this 3214 * periodic endpoint. 3215 */ 3216 mutex_enter(&ph->p_usba_device->usb_mutex); 3217 error = ohci_compute_total_bandwidth( 3218 endpoint, ph->p_usba_device->usb_port_status, &bandwidth); 3219 mutex_exit(&ph->p_usba_device->usb_mutex); 3220 3221 /* 3222 * If length is zero, then, it means endpoint maximum packet 3223 * supported is zero. In that case, return failure without 3224 * allocating any bandwidth. 3225 */ 3226 if (error != USB_SUCCESS) { 3227 USB_DPRINTF_L2(PRINT_MASK_BW, ohcip->ohci_log_hdl, 3228 "ohci_allocate_bandwidth: Periodic endpoint with " 3229 "zero endpoint maximum packet size is not supported"); 3230 3231 return (USB_NOT_SUPPORTED); 3232 } 3233 3234 /* 3235 * If the length in bytes plus the allocated bandwidth exceeds 3236 * the maximum, return bandwidth allocation failure. 3237 */ 3238 if ((ohcip->ohci_periodic_minimum_bandwidth + bandwidth) > 3239 (MAX_PERIODIC_BANDWIDTH)) { 3240 3241 USB_DPRINTF_L2(PRINT_MASK_BW, ohcip->ohci_log_hdl, 3242 "ohci_allocate_bandwidth: Reached maximum " 3243 "bandwidth value and cannot allocate bandwidth " 3244 "for a given periodic endpoint"); 3245 3246 return (USB_NO_BANDWIDTH); 3247 } 3248 3249 /* Adjust polling interval to be a power of 2 */ 3250 mutex_enter(&ph->p_usba_device->usb_mutex); 3251 interval = ohci_adjust_polling_interval(ohcip, 3252 endpoint, ph->p_usba_device->usb_port_status); 3253 mutex_exit(&ph->p_usba_device->usb_mutex); 3254 3255 /* 3256 * If this interval can't be supported, 3257 * return allocation failure. 3258 */ 3259 if (interval == USB_FAILURE) { 3260 3261 return (USB_FAILURE); 3262 } 3263 3264 USB_DPRINTF_L4(PRINT_MASK_BW, ohcip->ohci_log_hdl, 3265 "The new interval is %d", interval); 3266 3267 /* Find the leaf with the smallest allocated bandwidth */ 3268 min_index = 0; 3269 min = ohcip->ohci_periodic_bandwidth[0]; 3270 3271 for (i = 1; i < NUM_INTR_ED_LISTS; i++) { 3272 if (ohcip->ohci_periodic_bandwidth[i] < min) { 3273 min_index = i; 3274 min = ohcip->ohci_periodic_bandwidth[i]; 3275 } 3276 } 3277 3278 USB_DPRINTF_L4(PRINT_MASK_BW, ohcip->ohci_log_hdl, 3279 "The leaf %d for minimal bandwidth %d", min_index, min); 3280 3281 /* Adjust min for the lattice */ 3282 min_index = min_index + NUM_INTR_ED_LISTS - 1; 3283 3284 /* 3285 * Find the index into the lattice given the 3286 * leaf with the smallest allocated bandwidth. 3287 */ 3288 height = ohci_lattice_height(interval); 3289 3290 USB_DPRINTF_L4(PRINT_MASK_BW, ohcip->ohci_log_hdl, 3291 "The height is %d", height); 3292 3293 *node = min_index; 3294 3295 for (i = 0; i < height; i++) { 3296 *node = ohci_lattice_parent(*node); 3297 } 3298 3299 USB_DPRINTF_L4(PRINT_MASK_BW, ohcip->ohci_log_hdl, 3300 "Real node is %d", *node); 3301 3302 /* 3303 * Find the leftmost leaf in the subtree 3304 * specified by the node. 3305 */ 3306 leftmost = ohci_leftmost_leaf(*node, height); 3307 3308 USB_DPRINTF_L4(PRINT_MASK_BW, ohcip->ohci_log_hdl, 3309 "Leftmost %d", leftmost); 3310 3311 for (i = 0; i < (NUM_INTR_ED_LISTS/interval); i++) { 3312 list = ohci_hcca_leaf_index(leftmost + i); 3313 if ((ohcip->ohci_periodic_bandwidth[list] + 3314 bandwidth) > MAX_PERIODIC_BANDWIDTH) { 3315 3316 USB_DPRINTF_L2(PRINT_MASK_BW, ohcip->ohci_log_hdl, 3317 "ohci_allocate_bandwidth: Reached maximum " 3318 "bandwidth value and cannot allocate bandwidth " 3319 "for periodic endpoint"); 3320 3321 return (USB_NO_BANDWIDTH); 3322 } 3323 } 3324 3325 /* 3326 * All the leaves for this node must be updated with the bandwidth. 3327 */ 3328 for (i = 0; i < (NUM_INTR_ED_LISTS/interval); i++) { 3329 list = ohci_hcca_leaf_index(leftmost + i); 3330 ohcip->ohci_periodic_bandwidth[list] += bandwidth; 3331 } 3332 3333 /* Find the leaf with the smallest allocated bandwidth */ 3334 min_index = 0; 3335 min = ohcip->ohci_periodic_bandwidth[0]; 3336 3337 for (i = 1; i < NUM_INTR_ED_LISTS; i++) { 3338 if (ohcip->ohci_periodic_bandwidth[i] < min) { 3339 min_index = i; 3340 min = ohcip->ohci_periodic_bandwidth[i]; 3341 } 3342 } 3343 3344 /* Save the minimum for later use */ 3345 ohcip->ohci_periodic_minimum_bandwidth = min; 3346 3347 return (USB_SUCCESS); 3348 } 3349 3350 3351 /* 3352 * ohci_deallocate_bandwidth: 3353 * 3354 * Deallocate bandwidth for the given node in the lattice and the length 3355 * of transfer. 3356 */ 3357 static void 3358 ohci_deallocate_bandwidth( 3359 ohci_state_t *ohcip, 3360 usba_pipe_handle_data_t *ph) 3361 { 3362 uint_t min, node, bandwidth; 3363 uint_t height, leftmost, list; 3364 int i, interval; 3365 usb_ep_descr_t *endpoint = &ph->p_ep; 3366 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 3367 3368 /* This routine is protected by the ohci_int_mutex */ 3369 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 3370 3371 /* Obtain the length */ 3372 mutex_enter(&ph->p_usba_device->usb_mutex); 3373 (void) ohci_compute_total_bandwidth( 3374 endpoint, ph->p_usba_device->usb_port_status, &bandwidth); 3375 mutex_exit(&ph->p_usba_device->usb_mutex); 3376 3377 /* Obtain the node */ 3378 node = pp->pp_node; 3379 3380 /* Adjust polling interval to be a power of 2 */ 3381 mutex_enter(&ph->p_usba_device->usb_mutex); 3382 interval = ohci_adjust_polling_interval(ohcip, 3383 endpoint, ph->p_usba_device->usb_port_status); 3384 mutex_exit(&ph->p_usba_device->usb_mutex); 3385 3386 /* Find the height in the tree */ 3387 height = ohci_lattice_height(interval); 3388 3389 /* 3390 * Find the leftmost leaf in the subtree specified by the node 3391 */ 3392 leftmost = ohci_leftmost_leaf(node, height); 3393 3394 /* Delete the bandwith from the appropriate lists */ 3395 for (i = 0; i < (NUM_INTR_ED_LISTS/interval); i++) { 3396 list = ohci_hcca_leaf_index(leftmost + i); 3397 ohcip->ohci_periodic_bandwidth[list] -= bandwidth; 3398 } 3399 3400 min = ohcip->ohci_periodic_bandwidth[0]; 3401 3402 /* Recompute the minimum */ 3403 for (i = 1; i < NUM_INTR_ED_LISTS; i++) { 3404 if (ohcip->ohci_periodic_bandwidth[i] < min) { 3405 min = ohcip->ohci_periodic_bandwidth[i]; 3406 } 3407 } 3408 3409 /* Save the minimum for later use */ 3410 ohcip->ohci_periodic_minimum_bandwidth = min; 3411 } 3412 3413 3414 /* 3415 * ohci_compute_total_bandwidth: 3416 * 3417 * Given a periodic endpoint (interrupt or isochronous) determine the total 3418 * bandwidth for one transaction. The OpenHCI host controller traverses the 3419 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 3420 * services an endpoint, only a single transaction attempt is made. The HC 3421 * moves to the next Endpoint Descriptor after the first transaction attempt 3422 * rather than finishing the entire Transfer Descriptor. Therefore, when a 3423 * Transfer Descriptor is inserted into the lattice, we will only count the 3424 * number of bytes for one transaction. 3425 * 3426 * The following are the formulas used for calculating bandwidth in terms 3427 * bytes and it is for the single USB full speed and low speed transaction 3428 * respectively. The protocol overheads will be different for each of type 3429 * of USB transfer and all these formulas & protocol overheads are derived 3430 * from the 5.9.3 section of USB Specification & with the help of Bandwidth 3431 * Analysis white paper which is posted on the USB developer forum. 3432 * 3433 * Full-Speed: 3434 * Protocol overhead + ((MaxPacketSize * 7)/6 ) + Host_Delay 3435 * 3436 * Low-Speed: 3437 * Protocol overhead + Hub LS overhead + 3438 * (Low-Speed clock * ((MaxPacketSize * 7)/6 )) + Host_Delay 3439 */ 3440 static int 3441 ohci_compute_total_bandwidth( 3442 usb_ep_descr_t *endpoint, 3443 usb_port_status_t port_status, 3444 uint_t *bandwidth) 3445 { 3446 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 3447 3448 /* 3449 * If endpoint maximum packet is zero, then return immediately. 3450 */ 3451 if (maxpacketsize == 0) { 3452 3453 return (USB_NOT_SUPPORTED); 3454 } 3455 3456 /* Add Host Controller specific delay to required bandwidth */ 3457 *bandwidth = HOST_CONTROLLER_DELAY; 3458 3459 /* Add bit-stuffing overhead */ 3460 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 3461 3462 /* Low Speed interrupt transaction */ 3463 if (port_status == USBA_LOW_SPEED_DEV) { 3464 /* Low Speed interrupt transaction */ 3465 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 3466 HUB_LOW_SPEED_PROTO_OVERHEAD + 3467 (LOW_SPEED_CLOCK * maxpacketsize)); 3468 } else { 3469 /* Full Speed transaction */ 3470 *bandwidth += maxpacketsize; 3471 3472 if ((endpoint->bmAttributes & 3473 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 3474 /* Full Speed interrupt transaction */ 3475 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 3476 } else { 3477 /* Isochronous and input transaction */ 3478 if ((endpoint->bEndpointAddress & 3479 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 3480 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 3481 } else { 3482 /* Isochronous and output transaction */ 3483 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 3484 } 3485 } 3486 } 3487 3488 return (USB_SUCCESS); 3489 } 3490 3491 3492 /* 3493 * ohci_adjust_polling_interval: 3494 */ 3495 static int 3496 ohci_adjust_polling_interval( 3497 ohci_state_t *ohcip, 3498 usb_ep_descr_t *endpoint, 3499 usb_port_status_t port_status) 3500 { 3501 uint_t interval; 3502 int i = 0; 3503 3504 /* 3505 * Get the polling interval from the endpoint descriptor 3506 */ 3507 interval = endpoint->bInterval; 3508 3509 /* 3510 * The bInterval value in the endpoint descriptor can range 3511 * from 1 to 255ms. The interrupt lattice has 32 leaf nodes, 3512 * and the host controller cycles through these nodes every 3513 * 32ms. The longest polling interval that the controller 3514 * supports is 32ms. 3515 */ 3516 3517 /* 3518 * Return an error if the polling interval is less than 1ms 3519 * and greater than 255ms 3520 */ 3521 if ((interval < MIN_POLL_INTERVAL) || 3522 (interval > MAX_POLL_INTERVAL)) { 3523 3524 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 3525 "ohci_adjust_polling_interval: " 3526 "Endpoint's poll interval must be between %d and %d ms", 3527 MIN_POLL_INTERVAL, MAX_POLL_INTERVAL); 3528 3529 return (USB_FAILURE); 3530 } 3531 3532 /* 3533 * According USB Specifications, a full-speed endpoint can 3534 * specify a desired polling interval 1ms to 255ms and a low 3535 * speed endpoints are limited to specifying only 10ms to 3536 * 255ms. But some old keyboards & mice uses polling interval 3537 * of 8ms. For compatibility purpose, we are using polling 3538 * interval between 8ms & 255ms for low speed endpoints. But 3539 * ohci driver will reject the any low speed endpoints which 3540 * request polling interval less than 8ms. 3541 */ 3542 if ((port_status == USBA_LOW_SPEED_DEV) && 3543 (interval < MIN_LOW_SPEED_POLL_INTERVAL)) { 3544 3545 USB_DPRINTF_L2(PRINT_MASK_BW, ohcip->ohci_log_hdl, 3546 "ohci_adjust_polling_interval: " 3547 "Low speed endpoint's poll interval of %d ms " 3548 "is below threshold. Rounding up to %d ms", 3549 interval, MIN_LOW_SPEED_POLL_INTERVAL); 3550 3551 interval = MIN_LOW_SPEED_POLL_INTERVAL; 3552 } 3553 3554 /* 3555 * If polling interval is greater than 32ms, 3556 * adjust polling interval equal to 32ms. 3557 */ 3558 if (interval > NUM_INTR_ED_LISTS) { 3559 interval = NUM_INTR_ED_LISTS; 3560 } 3561 3562 /* 3563 * Find the nearest power of 2 that'sless 3564 * than interval. 3565 */ 3566 while ((ohci_pow_2(i)) <= interval) { 3567 i++; 3568 } 3569 3570 return (ohci_pow_2((i - 1))); 3571 } 3572 3573 3574 /* 3575 * ohci_lattice_height: 3576 * 3577 * Given the requested bandwidth, find the height in the tree at which the 3578 * nodes for this bandwidth fall. The height is measured as the number of 3579 * nodes from the leaf to the level specified by bandwidth The root of the 3580 * tree is at height TREE_HEIGHT. 3581 */ 3582 static uint_t 3583 ohci_lattice_height(uint_t interval) 3584 { 3585 return (TREE_HEIGHT - (ohci_log_2(interval))); 3586 } 3587 3588 3589 /* 3590 * ohci_lattice_parent: 3591 */ 3592 static uint_t 3593 ohci_lattice_parent(uint_t node) 3594 { 3595 if ((node % 2) == 0) { 3596 return ((node/2) - 1); 3597 } else { 3598 return ((node + 1)/2 - 1); 3599 } 3600 } 3601 3602 3603 /* 3604 * ohci_leftmost_leaf: 3605 * 3606 * Find the leftmost leaf in the subtree specified by the node. Height refers 3607 * to number of nodes from the bottom of the tree to the node, including the 3608 * node. 3609 * 3610 * The formula for a zero based tree is: 3611 * 2^H * Node + 2^H - 1 3612 * The leaf of the tree is an array, convert the number for the array. 3613 * Subtract the size of nodes not in the array 3614 * 2^H * Node + 2^H - 1 - (NUM_INTR_ED_LIST - 1) = 3615 * 2^H * Node + 2^H - NUM_INTR_ED_LIST = 3616 * 2^H * (Node + 1) - NUM_INTR_ED_LIST 3617 * 0 3618 * 1 2 3619 * 0 1 2 3 3620 */ 3621 static uint_t 3622 ohci_leftmost_leaf( 3623 uint_t node, 3624 uint_t height) 3625 { 3626 return ((ohci_pow_2(height) * (node + 1)) - NUM_INTR_ED_LISTS); 3627 } 3628 3629 /* 3630 * ohci_hcca_intr_index: 3631 * 3632 * Given a node in the lattice, find the index for the hcca interrupt table 3633 */ 3634 static uint_t 3635 ohci_hcca_intr_index(uint_t node) 3636 { 3637 /* 3638 * Adjust the node to the array representing 3639 * the bottom of the tree. 3640 */ 3641 node = node - NUM_STATIC_NODES; 3642 3643 if ((node % 2) == 0) { 3644 return (ohci_index[node / 2]); 3645 } else { 3646 return (ohci_index[node / 2] + (NUM_INTR_ED_LISTS / 2)); 3647 } 3648 } 3649 3650 /* 3651 * ohci_hcca_leaf_index: 3652 * 3653 * Given a node in the bottom leaf array of the lattice, find the index 3654 * for the hcca interrupt table 3655 */ 3656 static uint_t 3657 ohci_hcca_leaf_index(uint_t leaf) 3658 { 3659 if ((leaf % 2) == 0) { 3660 return (ohci_index[leaf / 2]); 3661 } else { 3662 return (ohci_index[leaf / 2] + (NUM_INTR_ED_LISTS / 2)); 3663 } 3664 } 3665 3666 /* 3667 * ohci_pow_2: 3668 * 3669 * Compute 2 to the power 3670 */ 3671 static uint_t 3672 ohci_pow_2(uint_t x) 3673 { 3674 if (x == 0) { 3675 return (1); 3676 } else { 3677 return (2 << (x - 1)); 3678 } 3679 } 3680 3681 3682 /* 3683 * ohci_log_2: 3684 * 3685 * Compute log base 2 of x 3686 */ 3687 static uint_t 3688 ohci_log_2(uint_t x) 3689 { 3690 int i = 0; 3691 3692 while (x != 1) { 3693 x = x >> 1; 3694 i++; 3695 } 3696 3697 return (i); 3698 } 3699 3700 3701 /* 3702 * Endpoint Descriptor (ED) manipulations functions 3703 */ 3704 3705 /* 3706 * ohci_alloc_hc_ed: 3707 * NOTE: This function is also called from POLLED MODE. 3708 * 3709 * Allocate an endpoint descriptor (ED) 3710 */ 3711 ohci_ed_t * 3712 ohci_alloc_hc_ed( 3713 ohci_state_t *ohcip, 3714 usba_pipe_handle_data_t *ph) 3715 { 3716 int i, state; 3717 ohci_ed_t *hc_ed; 3718 3719 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 3720 "ohci_alloc_hc_ed: ph = 0x%p", (void *)ph); 3721 3722 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 3723 3724 /* 3725 * The first 31 endpoints in the Endpoint Descriptor (ED) 3726 * buffer pool are reserved for building interrupt lattice 3727 * tree. Search for a blank endpoint descriptor in the ED 3728 * buffer pool. 3729 */ 3730 for (i = NUM_STATIC_NODES; i < ohci_ed_pool_size; i ++) { 3731 state = Get_ED(ohcip->ohci_ed_pool_addr[i].hced_state); 3732 3733 if (state == HC_EPT_FREE) { 3734 break; 3735 } 3736 } 3737 3738 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 3739 "ohci_alloc_hc_ed: Allocated %d", i); 3740 3741 if (i == ohci_ed_pool_size) { 3742 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 3743 "ohci_alloc_hc_ed: ED exhausted"); 3744 3745 return (NULL); 3746 } else { 3747 3748 hc_ed = &ohcip->ohci_ed_pool_addr[i]; 3749 3750 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 3751 "ohci_alloc_hc_ed: Allocated address 0x%p", (void *)hc_ed); 3752 3753 ohci_print_ed(ohcip, hc_ed); 3754 3755 /* Unpack the endpoint descriptor into a control field */ 3756 if (ph) { 3757 if ((ohci_initialize_dummy(ohcip, 3758 hc_ed)) == USB_NO_RESOURCES) { 3759 bzero((void *)hc_ed, sizeof (ohci_ed_t)); 3760 Set_ED(hc_ed->hced_state, HC_EPT_FREE); 3761 return (NULL); 3762 } 3763 3764 Set_ED(hc_ed->hced_prev, NULL); 3765 Set_ED(hc_ed->hced_next, NULL); 3766 3767 /* Change ED's state Active */ 3768 Set_ED(hc_ed->hced_state, HC_EPT_ACTIVE); 3769 3770 Set_ED(hc_ed->hced_ctrl, 3771 ohci_unpack_endpoint(ohcip, ph)); 3772 } else { 3773 Set_ED(hc_ed->hced_ctrl, HC_EPT_sKip); 3774 3775 /* Change ED's state Static */ 3776 Set_ED(hc_ed->hced_state, HC_EPT_STATIC); 3777 } 3778 3779 return (hc_ed); 3780 } 3781 } 3782 3783 3784 /* 3785 * ohci_unpack_endpoint: 3786 * 3787 * Unpack the information in the pipe handle and create the first byte 3788 * of the Host Controller's (HC) Endpoint Descriptor (ED). 3789 */ 3790 static uint_t 3791 ohci_unpack_endpoint( 3792 ohci_state_t *ohcip, 3793 usba_pipe_handle_data_t *ph) 3794 { 3795 usb_ep_descr_t *endpoint = &ph->p_ep; 3796 uint_t maxpacketsize, addr, ctrl = 0; 3797 3798 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 3799 "ohci_unpack_endpoint:"); 3800 3801 ctrl = ph->p_usba_device->usb_addr; 3802 3803 addr = endpoint->bEndpointAddress; 3804 3805 /* Assign the endpoint's address */ 3806 ctrl = ctrl | ((addr & USB_EP_NUM_MASK) << HC_EPT_EP_SHFT); 3807 3808 /* 3809 * Assign the direction. If the endpoint is a control endpoint, 3810 * the direction is assigned by the Transfer Descriptor (TD). 3811 */ 3812 if ((endpoint->bmAttributes & 3813 USB_EP_ATTR_MASK) != USB_EP_ATTR_CONTROL) { 3814 if (addr & USB_EP_DIR_MASK) { 3815 /* The direction is IN */ 3816 ctrl = ctrl | HC_EPT_DF_IN; 3817 } else { 3818 /* The direction is OUT */ 3819 ctrl = ctrl | HC_EPT_DF_OUT; 3820 } 3821 } 3822 3823 /* Assign the speed */ 3824 mutex_enter(&ph->p_usba_device->usb_mutex); 3825 if (ph->p_usba_device->usb_port_status == USBA_LOW_SPEED_DEV) { 3826 ctrl = ctrl | HC_EPT_Speed; 3827 } 3828 mutex_exit(&ph->p_usba_device->usb_mutex); 3829 3830 /* Assign the format */ 3831 if ((endpoint->bmAttributes & 3832 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 3833 ctrl = ctrl | HC_EPT_Format; 3834 } 3835 3836 maxpacketsize = endpoint->wMaxPacketSize; 3837 maxpacketsize = maxpacketsize << HC_EPT_MAXPKTSZ; 3838 ctrl = ctrl | (maxpacketsize & HC_EPT_MPS); 3839 3840 return (ctrl); 3841 } 3842 3843 3844 /* 3845 * ohci_insert_ed: 3846 * 3847 * Add the Endpoint Descriptor (ED) into the Host Controller's 3848 * (HC) appropriate endpoint list. 3849 */ 3850 static void 3851 ohci_insert_ed( 3852 ohci_state_t *ohcip, 3853 usba_pipe_handle_data_t *ph) 3854 { 3855 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 3856 3857 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 3858 "ohci_insert_ed:"); 3859 3860 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 3861 3862 switch (ph->p_ep.bmAttributes & USB_EP_ATTR_MASK) { 3863 case USB_EP_ATTR_CONTROL: 3864 ohci_insert_ctrl_ed(ohcip, pp); 3865 break; 3866 case USB_EP_ATTR_BULK: 3867 ohci_insert_bulk_ed(ohcip, pp); 3868 break; 3869 case USB_EP_ATTR_INTR: 3870 ohci_insert_intr_ed(ohcip, pp); 3871 break; 3872 case USB_EP_ATTR_ISOCH: 3873 ohci_insert_isoc_ed(ohcip, pp); 3874 break; 3875 } 3876 } 3877 3878 3879 /* 3880 * ohci_insert_ctrl_ed: 3881 * 3882 * Insert a control endpoint into the Host Controller's (HC) 3883 * control endpoint list. 3884 */ 3885 static void 3886 ohci_insert_ctrl_ed( 3887 ohci_state_t *ohcip, 3888 ohci_pipe_private_t *pp) 3889 { 3890 ohci_ed_t *ept = pp->pp_ept; 3891 ohci_ed_t *prev_ept; 3892 3893 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 3894 "ohci_insert_ctrl_ed:"); 3895 3896 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 3897 3898 /* Obtain a ptr to the head of the list */ 3899 if (Get_OpReg(hcr_ctrl_head)) { 3900 prev_ept = ohci_ed_iommu_to_cpu(ohcip, 3901 Get_OpReg(hcr_ctrl_head)); 3902 3903 /* Set up the backwards pointer */ 3904 Set_ED(prev_ept->hced_prev, ohci_ed_cpu_to_iommu(ohcip, ept)); 3905 } 3906 3907 /* The new endpoint points to the head of the list */ 3908 Set_ED(ept->hced_next, Get_OpReg(hcr_ctrl_head)); 3909 3910 /* Set the head ptr to the new endpoint */ 3911 Set_OpReg(hcr_ctrl_head, ohci_ed_cpu_to_iommu(ohcip, ept)); 3912 3913 /* 3914 * Enable Control list processing if control open 3915 * pipe count is zero. 3916 */ 3917 if (!ohcip->ohci_open_ctrl_pipe_count) { 3918 /* Start Control list processing */ 3919 Set_OpReg(hcr_control, 3920 (Get_OpReg(hcr_control) | HCR_CONTROL_CLE)); 3921 } 3922 3923 ohcip->ohci_open_ctrl_pipe_count++; 3924 } 3925 3926 3927 /* 3928 * ohci_insert_bulk_ed: 3929 * 3930 * Insert a bulk endpoint into the Host Controller's (HC) bulk endpoint list. 3931 */ 3932 static void 3933 ohci_insert_bulk_ed( 3934 ohci_state_t *ohcip, 3935 ohci_pipe_private_t *pp) 3936 { 3937 ohci_ed_t *ept = pp->pp_ept; 3938 ohci_ed_t *prev_ept; 3939 3940 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 3941 "ohci_insert_bulk_ed:"); 3942 3943 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 3944 3945 /* Obtain a ptr to the head of the Bulk list */ 3946 if (Get_OpReg(hcr_bulk_head)) { 3947 prev_ept = ohci_ed_iommu_to_cpu(ohcip, 3948 Get_OpReg(hcr_bulk_head)); 3949 3950 /* Set up the backwards pointer */ 3951 Set_ED(prev_ept->hced_prev, ohci_ed_cpu_to_iommu(ohcip, ept)); 3952 } 3953 3954 /* The new endpoint points to the head of the Bulk list */ 3955 Set_ED(ept->hced_next, Get_OpReg(hcr_bulk_head)); 3956 3957 /* Set the Bulk head ptr to the new endpoint */ 3958 Set_OpReg(hcr_bulk_head, ohci_ed_cpu_to_iommu(ohcip, ept)); 3959 3960 /* 3961 * Enable Bulk list processing if bulk open pipe 3962 * count is zero. 3963 */ 3964 if (!ohcip->ohci_open_bulk_pipe_count) { 3965 /* Start Bulk list processing */ 3966 Set_OpReg(hcr_control, 3967 (Get_OpReg(hcr_control) | HCR_CONTROL_BLE)); 3968 } 3969 3970 ohcip->ohci_open_bulk_pipe_count++; 3971 } 3972 3973 3974 /* 3975 * ohci_insert_intr_ed: 3976 * 3977 * Insert a interrupt endpoint into the Host Controller's (HC) interrupt 3978 * lattice tree. 3979 */ 3980 static void 3981 ohci_insert_intr_ed( 3982 ohci_state_t *ohcip, 3983 ohci_pipe_private_t *pp) 3984 { 3985 ohci_ed_t *ept = pp->pp_ept; 3986 ohci_ed_t *next_lattice_ept, *lattice_ept; 3987 uint_t node; 3988 3989 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 3990 3991 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 3992 "ohci_insert_intr_ed:"); 3993 3994 /* 3995 * The appropriate node was found 3996 * during the opening of the pipe. 3997 */ 3998 node = pp->pp_node; 3999 4000 if (node >= NUM_STATIC_NODES) { 4001 /* Get the hcca interrupt table index */ 4002 node = ohci_hcca_intr_index(node); 4003 4004 /* Get the first endpoint on the list */ 4005 next_lattice_ept = ohci_ed_iommu_to_cpu(ohcip, 4006 Get_HCCA(ohcip->ohci_hccap->HccaIntTble[node])); 4007 4008 /* Update this endpoint to point to it */ 4009 Set_ED(ept->hced_next, 4010 ohci_ed_cpu_to_iommu(ohcip, next_lattice_ept)); 4011 4012 /* Put this endpoint at the head of the list */ 4013 Set_HCCA(ohcip->ohci_hccap->HccaIntTble[node], 4014 ohci_ed_cpu_to_iommu(ohcip, ept)); 4015 4016 /* The previous pointer is NULL */ 4017 Set_ED(ept->hced_prev, NULL); 4018 4019 /* Update the previous pointer of ept->hced_next */ 4020 if (Get_ED(next_lattice_ept->hced_state) != HC_EPT_STATIC) { 4021 Set_ED(next_lattice_ept->hced_prev, 4022 ohci_ed_cpu_to_iommu(ohcip, ept)); 4023 } 4024 } else { 4025 /* Find the lattice endpoint */ 4026 lattice_ept = &ohcip->ohci_ed_pool_addr[node]; 4027 4028 /* Find the next lattice endpoint */ 4029 next_lattice_ept = ohci_ed_iommu_to_cpu( 4030 ohcip, Get_ED(lattice_ept->hced_next)); 4031 4032 /* 4033 * Update this endpoint to point to the next one in the 4034 * lattice. 4035 */ 4036 Set_ED(ept->hced_next, Get_ED(lattice_ept->hced_next)); 4037 4038 /* Insert this endpoint into the lattice */ 4039 Set_ED(lattice_ept->hced_next, 4040 ohci_ed_cpu_to_iommu(ohcip, ept)); 4041 4042 /* Update the previous pointer */ 4043 Set_ED(ept->hced_prev, 4044 ohci_ed_cpu_to_iommu(ohcip, lattice_ept)); 4045 4046 /* Update the previous pointer of ept->hced_next */ 4047 if ((next_lattice_ept) && 4048 (Get_ED(next_lattice_ept->hced_state) != HC_EPT_STATIC)) { 4049 4050 Set_ED(next_lattice_ept->hced_prev, 4051 ohci_ed_cpu_to_iommu(ohcip, ept)); 4052 } 4053 } 4054 4055 /* 4056 * Enable periodic list processing if periodic (interrupt 4057 * and isochronous) open pipe count is zero. 4058 */ 4059 if (!ohcip->ohci_open_periodic_pipe_count) { 4060 ASSERT(!ohcip->ohci_open_isoch_pipe_count); 4061 4062 Set_OpReg(hcr_control, 4063 (Get_OpReg(hcr_control) | HCR_CONTROL_PLE)); 4064 } 4065 4066 ohcip->ohci_open_periodic_pipe_count++; 4067 } 4068 4069 4070 /* 4071 * ohci_insert_isoc_ed: 4072 * 4073 * Insert a isochronous endpoint into the Host Controller's (HC) interrupt 4074 * lattice tree. A isochronous endpoint will be inserted at the end of the 4075 * 1ms interrupt endpoint list. 4076 */ 4077 static void 4078 ohci_insert_isoc_ed( 4079 ohci_state_t *ohcip, 4080 ohci_pipe_private_t *pp) 4081 { 4082 ohci_ed_t *next_lattice_ept, *lattice_ept; 4083 ohci_ed_t *ept = pp->pp_ept; 4084 uint_t node; 4085 4086 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4087 4088 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4089 "ohci_insert_isoc_ed:"); 4090 4091 /* 4092 * The appropriate node was found during the opening of the pipe. 4093 * This node must be root of the interrupt lattice tree. 4094 */ 4095 node = pp->pp_node; 4096 4097 ASSERT(node == 0); 4098 4099 /* Find the 1ms interrupt lattice endpoint */ 4100 lattice_ept = &ohcip->ohci_ed_pool_addr[node]; 4101 4102 /* Find the next lattice endpoint */ 4103 next_lattice_ept = ohci_ed_iommu_to_cpu( 4104 ohcip, Get_ED(lattice_ept->hced_next)); 4105 4106 while (next_lattice_ept) { 4107 lattice_ept = next_lattice_ept; 4108 4109 /* Find the next lattice endpoint */ 4110 next_lattice_ept = ohci_ed_iommu_to_cpu( 4111 ohcip, Get_ED(lattice_ept->hced_next)); 4112 } 4113 4114 /* The next pointer is NULL */ 4115 Set_ED(ept->hced_next, NULL); 4116 4117 /* Update the previous pointer */ 4118 Set_ED(ept->hced_prev, ohci_ed_cpu_to_iommu(ohcip, lattice_ept)); 4119 4120 /* Insert this endpoint into the lattice */ 4121 Set_ED(lattice_ept->hced_next, ohci_ed_cpu_to_iommu(ohcip, ept)); 4122 4123 /* 4124 * Enable periodic and isoch lists processing if isoch 4125 * open pipe count is zero. 4126 */ 4127 if (!ohcip->ohci_open_isoch_pipe_count) { 4128 4129 Set_OpReg(hcr_control, (Get_OpReg(hcr_control) | 4130 HCR_CONTROL_PLE | HCR_CONTROL_IE)); 4131 } 4132 4133 ohcip->ohci_open_periodic_pipe_count++; 4134 ohcip->ohci_open_isoch_pipe_count++; 4135 } 4136 4137 4138 /* 4139 * ohci_modify_sKip_bit: 4140 * 4141 * Modify the sKip bit on the Host Controller (HC) Endpoint Descriptor (ED). 4142 */ 4143 static void 4144 ohci_modify_sKip_bit( 4145 ohci_state_t *ohcip, 4146 ohci_pipe_private_t *pp, 4147 skip_bit_t action, 4148 usb_flags_t flag) 4149 { 4150 ohci_ed_t *ept = pp->pp_ept; 4151 4152 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4153 "ohci_modify_sKip_bit: action = 0x%x flag = 0x%x", 4154 action, flag); 4155 4156 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4157 4158 if (action == CLEAR_sKip) { 4159 /* 4160 * If the skip bit is to be cleared, just clear it. 4161 * there shouldn't be any race condition problems. 4162 * If the host controller reads the bit before the 4163 * driver has a chance to set the bit, the bit will 4164 * be reread on the next frame. 4165 */ 4166 Set_ED(ept->hced_ctrl, (Get_ED(ept->hced_ctrl) & ~HC_EPT_sKip)); 4167 } else { 4168 /* Sync ED and TD pool */ 4169 if (flag & OHCI_FLAGS_DMA_SYNC) { 4170 Sync_ED_TD_Pool(ohcip); 4171 } 4172 4173 /* Check Halt or Skip bit is already set */ 4174 if ((Get_ED(ept->hced_headp) & HC_EPT_Halt) || 4175 (Get_ED(ept->hced_ctrl) & HC_EPT_sKip)) { 4176 4177 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4178 "ohci_modify_sKip_bit: " 4179 "Halt or Skip bit is already set"); 4180 } else { 4181 /* 4182 * The action is to set the skip bit. In order to 4183 * be sure that the HCD has seen the sKip bit, wait 4184 * for the next start of frame. 4185 */ 4186 Set_ED(ept->hced_ctrl, 4187 (Get_ED(ept->hced_ctrl) | HC_EPT_sKip)); 4188 4189 if (flag & OHCI_FLAGS_SLEEP) { 4190 /* Wait for the next SOF */ 4191 (void) ohci_wait_for_sof(ohcip); 4192 4193 /* Sync ED and TD pool */ 4194 if (flag & OHCI_FLAGS_DMA_SYNC) { 4195 Sync_ED_TD_Pool(ohcip); 4196 } 4197 } 4198 } 4199 } 4200 } 4201 4202 4203 /* 4204 * ohci_remove_ed: 4205 * 4206 * Remove the Endpoint Descriptor (ED) from the Host Controller's appropriate 4207 * endpoint list. 4208 */ 4209 static void 4210 ohci_remove_ed( 4211 ohci_state_t *ohcip, 4212 ohci_pipe_private_t *pp) 4213 { 4214 uchar_t attributes; 4215 4216 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4217 4218 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4219 "ohci_remove_ed:"); 4220 4221 attributes = pp->pp_pipe_handle->p_ep.bmAttributes & USB_EP_ATTR_MASK; 4222 4223 switch (attributes) { 4224 case USB_EP_ATTR_CONTROL: 4225 ohci_remove_ctrl_ed(ohcip, pp); 4226 break; 4227 case USB_EP_ATTR_BULK: 4228 ohci_remove_bulk_ed(ohcip, pp); 4229 break; 4230 case USB_EP_ATTR_INTR: 4231 case USB_EP_ATTR_ISOCH: 4232 ohci_remove_periodic_ed(ohcip, pp); 4233 break; 4234 } 4235 } 4236 4237 4238 /* 4239 * ohci_remove_ctrl_ed: 4240 * 4241 * Remove a control Endpoint Descriptor (ED) from the Host Controller's (HC) 4242 * control endpoint list. 4243 */ 4244 static void 4245 ohci_remove_ctrl_ed( 4246 ohci_state_t *ohcip, 4247 ohci_pipe_private_t *pp) 4248 { 4249 ohci_ed_t *ept = pp->pp_ept; /* ept to be removed */ 4250 4251 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4252 "ohci_remove_ctrl_ed:"); 4253 4254 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4255 4256 /* The control list should already be stopped */ 4257 ASSERT(!(Get_OpReg(hcr_control) & HCR_CONTROL_CLE)); 4258 4259 ohcip->ohci_open_ctrl_pipe_count--; 4260 4261 /* Detach the endpoint from the list that it's on */ 4262 ohci_detach_ed_from_list(ohcip, ept, USB_EP_ATTR_CONTROL); 4263 4264 /* 4265 * If next endpoint pointed by endpoint to be removed is not NULL 4266 * then set current control pointer to the next endpoint pointed by 4267 * endpoint to be removed. Otherwise set current control pointer to 4268 * the beginning of the control list. 4269 */ 4270 if (Get_ED(ept->hced_next)) { 4271 Set_OpReg(hcr_ctrl_curr, Get_ED(ept->hced_next)); 4272 } else { 4273 Set_OpReg(hcr_ctrl_curr, Get_OpReg(hcr_ctrl_head)); 4274 } 4275 4276 if (ohcip->ohci_open_ctrl_pipe_count) { 4277 ASSERT(Get_OpReg(hcr_ctrl_head)); 4278 4279 /* Reenable the control list */ 4280 Set_OpReg(hcr_control, 4281 (Get_OpReg(hcr_control) | HCR_CONTROL_CLE)); 4282 } 4283 4284 ohci_insert_ed_on_reclaim_list(ohcip, pp); 4285 } 4286 4287 4288 /* 4289 * ohci_remove_bulk_ed: 4290 * 4291 * Remove free the bulk Endpoint Descriptor (ED) from the Host Controller's 4292 * (HC) bulk endpoint list. 4293 */ 4294 static void 4295 ohci_remove_bulk_ed( 4296 ohci_state_t *ohcip, 4297 ohci_pipe_private_t *pp) 4298 { 4299 ohci_ed_t *ept = pp->pp_ept; /* ept to be removed */ 4300 4301 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4302 "ohci_remove_bulk_ed:"); 4303 4304 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4305 4306 /* The bulk list should already be stopped */ 4307 ASSERT(!(Get_OpReg(hcr_control) & HCR_CONTROL_BLE)); 4308 4309 ohcip->ohci_open_bulk_pipe_count--; 4310 4311 /* Detach the endpoint from the bulk list */ 4312 ohci_detach_ed_from_list(ohcip, ept, USB_EP_ATTR_BULK); 4313 4314 /* 4315 * If next endpoint pointed by endpoint to be removed is not NULL 4316 * then set current bulk pointer to the next endpoint pointed by 4317 * endpoint to be removed. Otherwise set current bulk pointer to 4318 * the beginning of the bulk list. 4319 */ 4320 if (Get_ED(ept->hced_next)) { 4321 Set_OpReg(hcr_bulk_curr, Get_ED(ept->hced_next)); 4322 } else { 4323 Set_OpReg(hcr_bulk_curr, Get_OpReg(hcr_bulk_head)); 4324 } 4325 4326 if (ohcip->ohci_open_bulk_pipe_count) { 4327 ASSERT(Get_OpReg(hcr_bulk_head)); 4328 4329 /* Re-enable the bulk list */ 4330 Set_OpReg(hcr_control, 4331 (Get_OpReg(hcr_control) | HCR_CONTROL_BLE)); 4332 } 4333 4334 ohci_insert_ed_on_reclaim_list(ohcip, pp); 4335 } 4336 4337 4338 /* 4339 * ohci_remove_periodic_ed: 4340 * 4341 * Set up an periodic endpoint to be removed from the Host Controller's (HC) 4342 * interrupt lattice tree. The Endpoint Descriptor (ED) will be freed in the 4343 * interrupt handler. 4344 */ 4345 static void 4346 ohci_remove_periodic_ed( 4347 ohci_state_t *ohcip, 4348 ohci_pipe_private_t *pp) 4349 { 4350 ohci_ed_t *ept = pp->pp_ept; /* ept to be removed */ 4351 uint_t ept_type; 4352 4353 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4354 "ohci_remove_periodic_ed:"); 4355 4356 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4357 4358 ASSERT((Get_ED(ept->hced_tailp) & HC_EPT_TD_TAIL) == 4359 (Get_ED(ept->hced_headp) & HC_EPT_TD_HEAD)); 4360 4361 ohcip->ohci_open_periodic_pipe_count--; 4362 4363 ept_type = pp->pp_pipe_handle-> 4364 p_ep.bmAttributes & USB_EP_ATTR_MASK; 4365 4366 if (ept_type == USB_EP_ATTR_ISOCH) { 4367 ohcip->ohci_open_isoch_pipe_count--; 4368 } 4369 4370 /* Store the node number */ 4371 Set_ED(ept->hced_node, pp->pp_node); 4372 4373 /* Remove the endpoint from interrupt lattice tree */ 4374 ohci_detach_ed_from_list(ohcip, ept, ept_type); 4375 4376 /* 4377 * Disable isoch list processing if isoch open pipe count 4378 * is zero. 4379 */ 4380 if (!ohcip->ohci_open_isoch_pipe_count) { 4381 Set_OpReg(hcr_control, 4382 (Get_OpReg(hcr_control) & ~(HCR_CONTROL_IE))); 4383 } 4384 4385 /* 4386 * Disable periodic list processing if periodic (interrupt 4387 * and isochrous) open pipe count is zero. 4388 */ 4389 if (!ohcip->ohci_open_periodic_pipe_count) { 4390 ASSERT(!ohcip->ohci_open_isoch_pipe_count); 4391 4392 Set_OpReg(hcr_control, 4393 (Get_OpReg(hcr_control) & ~(HCR_CONTROL_PLE))); 4394 } 4395 4396 ohci_insert_ed_on_reclaim_list(ohcip, pp); 4397 } 4398 4399 4400 /* 4401 * ohci_detach_ed_from_list: 4402 * 4403 * Remove the Endpoint Descriptor (ED) from the appropriate Host Controller's 4404 * (HC) endpoint list. 4405 */ 4406 static void 4407 ohci_detach_ed_from_list( 4408 ohci_state_t *ohcip, 4409 ohci_ed_t *ept, 4410 uint_t ept_type) 4411 { 4412 ohci_ed_t *prev_ept; /* Previous endpoint */ 4413 ohci_ed_t *next_ept; /* Endpoint after one to be removed */ 4414 uint_t node; 4415 4416 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4417 "ohci_detach_ed_from_list:"); 4418 4419 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4420 4421 prev_ept = ohci_ed_iommu_to_cpu(ohcip, Get_ED(ept->hced_prev)); 4422 next_ept = ohci_ed_iommu_to_cpu(ohcip, Get_ED(ept->hced_next)); 4423 4424 /* 4425 * If there is no previous endpoint, then this 4426 * endpoint is at the head of the endpoint list. 4427 */ 4428 if (prev_ept == NULL) { 4429 if (next_ept) { 4430 /* 4431 * If this endpoint is the first element of the 4432 * list and there is more than one endpoint on 4433 * the list then perform specific actions based 4434 * on the type of endpoint list. 4435 */ 4436 switch (ept_type) { 4437 case USB_EP_ATTR_CONTROL: 4438 /* Set the head of list to next ept */ 4439 Set_OpReg(hcr_ctrl_head, 4440 Get_ED(ept->hced_next)); 4441 4442 /* Clear prev ptr of next endpoint */ 4443 Set_ED(next_ept->hced_prev, NULL); 4444 break; 4445 case USB_EP_ATTR_BULK: 4446 /* Set the head of list to next ept */ 4447 Set_OpReg(hcr_bulk_head, 4448 Get_ED(ept->hced_next)); 4449 4450 /* Clear prev ptr of next endpoint */ 4451 Set_ED(next_ept->hced_prev, NULL); 4452 break; 4453 case USB_EP_ATTR_INTR: 4454 /* 4455 * HCCA area should point 4456 * directly to this ept. 4457 */ 4458 ASSERT(Get_ED(ept->hced_node) >= 4459 NUM_STATIC_NODES); 4460 4461 /* Get the hcca interrupt table index */ 4462 node = ohci_hcca_intr_index( 4463 Get_ED(ept->hced_node)); 4464 4465 /* 4466 * Delete the ept from the 4467 * bottom of the tree. 4468 */ 4469 Set_HCCA(ohcip->ohci_hccap-> 4470 HccaIntTble[node], Get_ED(ept->hced_next)); 4471 4472 /* 4473 * Update the previous pointer 4474 * of ept->hced_next 4475 */ 4476 if (Get_ED(next_ept->hced_state) != 4477 HC_EPT_STATIC) { 4478 4479 Set_ED(next_ept->hced_prev, NULL); 4480 } 4481 4482 break; 4483 case USB_EP_ATTR_ISOCH: 4484 default: 4485 break; 4486 } 4487 } else { 4488 /* 4489 * If there was only one element on the list 4490 * perform specific actions based on the type 4491 * of the list. 4492 */ 4493 switch (ept_type) { 4494 case USB_EP_ATTR_CONTROL: 4495 /* Set the head to NULL */ 4496 Set_OpReg(hcr_ctrl_head, NULL); 4497 break; 4498 case USB_EP_ATTR_BULK: 4499 /* Set the head to NULL */ 4500 Set_OpReg(hcr_bulk_head, NULL); 4501 break; 4502 case USB_EP_ATTR_INTR: 4503 case USB_EP_ATTR_ISOCH: 4504 default: 4505 break; 4506 } 4507 } 4508 } else { 4509 /* The previous ept points to the next one */ 4510 Set_ED(prev_ept->hced_next, Get_ED(ept->hced_next)); 4511 4512 /* 4513 * Set the previous ptr of the next_ept to prev_ept 4514 * if this isn't the last endpoint on the list 4515 */ 4516 if ((next_ept) && 4517 (Get_ED(next_ept->hced_state) != HC_EPT_STATIC)) { 4518 4519 /* Set the previous ptr of the next one */ 4520 Set_ED(next_ept->hced_prev, Get_ED(ept->hced_prev)); 4521 } 4522 } 4523 } 4524 4525 4526 /* 4527 * ohci_insert_ed_on_reclaim_list: 4528 * 4529 * Insert Endpoint onto the reclaim list 4530 */ 4531 static void 4532 ohci_insert_ed_on_reclaim_list( 4533 ohci_state_t *ohcip, 4534 ohci_pipe_private_t *pp) 4535 { 4536 ohci_ed_t *ept = pp->pp_ept; /* ept to be removed */ 4537 ohci_ed_t *next_ept, *prev_ept; 4538 usb_frame_number_t frame_number; 4539 4540 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4541 4542 /* 4543 * Read current usb frame number and add appropriate number of 4544 * usb frames needs to wait before reclaiming current endpoint. 4545 */ 4546 frame_number = 4547 ohci_get_current_frame_number(ohcip) + MAX_SOF_WAIT_COUNT; 4548 4549 /* Store 32bit ID */ 4550 Set_ED(ept->hced_reclaim_frame, 4551 ((uint32_t)(OHCI_GET_ID((void *)(uintptr_t)frame_number)))); 4552 4553 /* Insert the endpoint onto the reclaimation list */ 4554 if (ohcip->ohci_reclaim_list) { 4555 next_ept = ohcip->ohci_reclaim_list; 4556 4557 while (next_ept) { 4558 prev_ept = next_ept; 4559 next_ept = ohci_ed_iommu_to_cpu(ohcip, 4560 Get_ED(next_ept->hced_reclaim_next)); 4561 } 4562 4563 Set_ED(prev_ept->hced_reclaim_next, 4564 ohci_ed_cpu_to_iommu(ohcip, ept)); 4565 } else { 4566 ohcip->ohci_reclaim_list = ept; 4567 } 4568 4569 ASSERT(Get_ED(ept->hced_reclaim_next) == NULL); 4570 4571 /* Enable the SOF interrupt */ 4572 Set_OpReg(hcr_intr_enable, HCR_INTR_SOF); 4573 } 4574 4575 4576 /* 4577 * ohci_deallocate_ed: 4578 * NOTE: This function is also called from POLLED MODE. 4579 * 4580 * Deallocate a Host Controller's (HC) Endpoint Descriptor (ED). 4581 */ 4582 void 4583 ohci_deallocate_ed( 4584 ohci_state_t *ohcip, 4585 ohci_ed_t *old_ed) 4586 { 4587 ohci_td_t *dummy_td; 4588 4589 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 4590 "ohci_deallocate_ed:"); 4591 4592 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4593 4594 dummy_td = ohci_td_iommu_to_cpu(ohcip, Get_ED(old_ed->hced_headp)); 4595 4596 if (dummy_td) { 4597 4598 ASSERT(Get_TD(dummy_td->hctd_state) == HC_TD_DUMMY); 4599 ohci_deallocate_td(ohcip, dummy_td); 4600 } 4601 4602 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 4603 "ohci_deallocate_ed: Deallocated 0x%p", (void *)old_ed); 4604 4605 bzero((void *)old_ed, sizeof (ohci_ed_t)); 4606 Set_ED(old_ed->hced_state, HC_EPT_FREE); 4607 } 4608 4609 4610 /* 4611 * ohci_ed_cpu_to_iommu: 4612 * NOTE: This function is also called from POLLED MODE. 4613 * 4614 * This function converts for the given Endpoint Descriptor (ED) CPU address 4615 * to IO address. 4616 */ 4617 uint32_t 4618 ohci_ed_cpu_to_iommu( 4619 ohci_state_t *ohcip, 4620 ohci_ed_t *addr) 4621 { 4622 uint32_t ed; 4623 4624 ed = (uint32_t)ohcip->ohci_ed_pool_cookie.dmac_address + 4625 (uint32_t)((uintptr_t)addr - (uintptr_t)(ohcip->ohci_ed_pool_addr)); 4626 4627 ASSERT(ed >= ohcip->ohci_ed_pool_cookie.dmac_address); 4628 ASSERT(ed <= ohcip->ohci_ed_pool_cookie.dmac_address + 4629 sizeof (ohci_ed_t) * ohci_ed_pool_size); 4630 4631 return (ed); 4632 } 4633 4634 4635 /* 4636 * ohci_ed_iommu_to_cpu: 4637 * 4638 * This function converts for the given Endpoint Descriptor (ED) IO address 4639 * to CPU address. 4640 */ 4641 static ohci_ed_t * 4642 ohci_ed_iommu_to_cpu( 4643 ohci_state_t *ohcip, 4644 uintptr_t addr) 4645 { 4646 ohci_ed_t *ed; 4647 4648 if (addr == NULL) { 4649 4650 return (NULL); 4651 } 4652 4653 ed = (ohci_ed_t *)((uintptr_t) 4654 (addr - ohcip->ohci_ed_pool_cookie.dmac_address) + 4655 (uintptr_t)ohcip->ohci_ed_pool_addr); 4656 4657 ASSERT(ed >= ohcip->ohci_ed_pool_addr); 4658 ASSERT((uintptr_t)ed <= (uintptr_t)ohcip->ohci_ed_pool_addr + 4659 (uintptr_t)(sizeof (ohci_ed_t) * ohci_ed_pool_size)); 4660 4661 return (ed); 4662 } 4663 4664 4665 /* 4666 * Transfer Descriptor manipulations functions 4667 */ 4668 4669 /* 4670 * ohci_initialize_dummy: 4671 * 4672 * An Endpoint Descriptor (ED) has a dummy Transfer Descriptor (TD) on the 4673 * end of its TD list. Initially, both the head and tail pointers of the ED 4674 * point to the dummy TD. 4675 */ 4676 static int 4677 ohci_initialize_dummy( 4678 ohci_state_t *ohcip, 4679 ohci_ed_t *ept) 4680 { 4681 ohci_td_t *dummy; 4682 4683 /* Obtain a dummy TD */ 4684 dummy = ohci_allocate_td_from_pool(ohcip); 4685 4686 if (dummy == NULL) { 4687 return (USB_NO_RESOURCES); 4688 } 4689 4690 /* 4691 * Both the head and tail pointers of an ED point 4692 * to this new dummy TD. 4693 */ 4694 Set_ED(ept->hced_headp, (ohci_td_cpu_to_iommu(ohcip, dummy))); 4695 Set_ED(ept->hced_tailp, (ohci_td_cpu_to_iommu(ohcip, dummy))); 4696 4697 return (USB_SUCCESS); 4698 } 4699 4700 /* 4701 * ohci_allocate_ctrl_resources: 4702 * 4703 * Calculates the number of tds necessary for a ctrl transfer, and allocates 4704 * all the resources necessary. 4705 * 4706 * Returns NULL if there is insufficient resources otherwise TW. 4707 */ 4708 static ohci_trans_wrapper_t * 4709 ohci_allocate_ctrl_resources( 4710 ohci_state_t *ohcip, 4711 ohci_pipe_private_t *pp, 4712 usb_ctrl_req_t *ctrl_reqp, 4713 usb_flags_t usb_flags) 4714 { 4715 size_t td_count = 2; 4716 size_t ctrl_buf_size; 4717 ohci_trans_wrapper_t *tw; 4718 4719 /* Add one more td for data phase */ 4720 if (ctrl_reqp->ctrl_wLength) { 4721 td_count++; 4722 } 4723 4724 /* 4725 * If we have a control data phase, the data buffer starts 4726 * on the next 4K page boundary. So the TW buffer is allocated 4727 * to be larger than required. The buffer in the range of 4728 * [SETUP_SIZE, OHCI_MAX_TD_BUF_SIZE) is just for padding 4729 * and not to be transferred. 4730 */ 4731 if (ctrl_reqp->ctrl_wLength) { 4732 ctrl_buf_size = OHCI_MAX_TD_BUF_SIZE + 4733 ctrl_reqp->ctrl_wLength; 4734 } else { 4735 ctrl_buf_size = SETUP_SIZE; 4736 } 4737 4738 tw = ohci_allocate_tw_resources(ohcip, pp, ctrl_buf_size, 4739 usb_flags, td_count); 4740 4741 return (tw); 4742 } 4743 4744 /* 4745 * ohci_insert_ctrl_req: 4746 * 4747 * Create a Transfer Descriptor (TD) and a data buffer for a control endpoint. 4748 */ 4749 /* ARGSUSED */ 4750 static void 4751 ohci_insert_ctrl_req( 4752 ohci_state_t *ohcip, 4753 usba_pipe_handle_data_t *ph, 4754 usb_ctrl_req_t *ctrl_reqp, 4755 ohci_trans_wrapper_t *tw, 4756 usb_flags_t usb_flags) 4757 { 4758 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 4759 uchar_t bmRequestType = ctrl_reqp->ctrl_bmRequestType; 4760 uchar_t bRequest = ctrl_reqp->ctrl_bRequest; 4761 uint16_t wValue = ctrl_reqp->ctrl_wValue; 4762 uint16_t wIndex = ctrl_reqp->ctrl_wIndex; 4763 uint16_t wLength = ctrl_reqp->ctrl_wLength; 4764 mblk_t *data = ctrl_reqp->ctrl_data; 4765 uint32_t ctrl = 0; 4766 int sdata; 4767 4768 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4769 "ohci_insert_ctrl_req:"); 4770 4771 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4772 4773 /* 4774 * Save current control request pointer and timeout values 4775 * in transfer wrapper. 4776 */ 4777 tw->tw_curr_xfer_reqp = (usb_opaque_t)ctrl_reqp; 4778 tw->tw_timeout = ctrl_reqp->ctrl_timeout ? 4779 ctrl_reqp->ctrl_timeout : OHCI_DEFAULT_XFER_TIMEOUT; 4780 4781 /* 4782 * Initialize the callback and any callback data for when 4783 * the td completes. 4784 */ 4785 tw->tw_handle_td = ohci_handle_ctrl_td; 4786 tw->tw_handle_callback_value = NULL; 4787 4788 /* Create the first four bytes of the setup packet */ 4789 sdata = (bmRequestType << 24) | (bRequest << 16) | 4790 (((wValue >> 8) | (wValue << 8)) & 0x0000FFFF); 4791 4792 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4793 "ohci_create_setup_pkt: sdata = 0x%x", sdata); 4794 4795 ddi_put32(tw->tw_accesshandle, (uint_t *)tw->tw_buf, sdata); 4796 4797 /* Create the second four bytes */ 4798 sdata = (uint32_t)(((((wIndex >> 8) | 4799 (wIndex << 8)) << 16) & 0xFFFF0000) | 4800 (((wLength >> 8) | (wLength << 8)) & 0x0000FFFF)); 4801 4802 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 4803 "ohci_create_setup_pkt: sdata = 0x%x", sdata); 4804 4805 ddi_put32(tw->tw_accesshandle, 4806 (uint_t *)(tw->tw_buf + sizeof (uint_t)), sdata); 4807 4808 ctrl = HC_TD_SETUP|HC_TD_MS_DT|HC_TD_DT_0|HC_TD_6I; 4809 4810 /* 4811 * The TD's are placed on the ED one at a time. 4812 * Once this TD is placed on the done list, the 4813 * data or status phase TD will be enqueued. 4814 */ 4815 (void) ohci_insert_hc_td(ohcip, ctrl, 0, SETUP_SIZE, 4816 OHCI_CTRL_SETUP_PHASE, pp, tw); 4817 4818 USB_DPRINTF_L3(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 4819 "Create_setup: pp 0x%p", (void *)pp); 4820 4821 /* 4822 * If this control transfer has a data phase, record the 4823 * direction. If the data phase is an OUT transaction, 4824 * copy the data into the buffer of the transfer wrapper. 4825 */ 4826 if (wLength != 0) { 4827 /* There is a data stage. Find the direction */ 4828 if (bmRequestType & USB_DEV_REQ_DEV_TO_HOST) { 4829 tw->tw_direction = HC_TD_IN; 4830 } else { 4831 tw->tw_direction = HC_TD_OUT; 4832 4833 /* Copy the data into the message */ 4834 ddi_rep_put8(tw->tw_accesshandle, data->b_rptr, 4835 (uint8_t *)(tw->tw_buf + OHCI_MAX_TD_BUF_SIZE), 4836 wLength, DDI_DEV_AUTOINCR); 4837 4838 } 4839 4840 ctrl = (ctrl_reqp->ctrl_attributes & USB_ATTRS_SHORT_XFER_OK) ? 4841 HC_TD_R : 0; 4842 4843 /* 4844 * There is a data stage. 4845 * Find the direction. 4846 */ 4847 if (tw->tw_direction == HC_TD_IN) { 4848 ctrl = ctrl|HC_TD_IN|HC_TD_MS_DT|HC_TD_DT_1|HC_TD_6I; 4849 } else { 4850 ctrl = ctrl|HC_TD_OUT|HC_TD_MS_DT|HC_TD_DT_1|HC_TD_6I; 4851 } 4852 4853 /* 4854 * Create the TD. If this is an OUT transaction, 4855 * the data is already in the buffer of the TW. 4856 */ 4857 (void) ohci_insert_hc_td(ohcip, ctrl, OHCI_MAX_TD_BUF_SIZE, 4858 wLength, OHCI_CTRL_DATA_PHASE, pp, tw); 4859 4860 /* 4861 * The direction of the STATUS TD depends on 4862 * the direction of the transfer. 4863 */ 4864 if (tw->tw_direction == HC_TD_IN) { 4865 ctrl = HC_TD_OUT|HC_TD_MS_DT|HC_TD_DT_1|HC_TD_1I; 4866 } else { 4867 ctrl = HC_TD_IN|HC_TD_MS_DT|HC_TD_DT_1|HC_TD_1I; 4868 } 4869 } else { 4870 ctrl = HC_TD_IN|HC_TD_MS_DT|HC_TD_DT_1|HC_TD_1I; 4871 } 4872 4873 /* Status stage */ 4874 (void) ohci_insert_hc_td(ohcip, ctrl, 0, 4875 0, OHCI_CTRL_STATUS_PHASE, pp, tw); 4876 4877 /* Indicate that the control list is filled */ 4878 Set_OpReg(hcr_cmd_status, HCR_STATUS_CLF); 4879 4880 /* Start the timer for this control transfer */ 4881 ohci_start_xfer_timer(ohcip, pp, tw); 4882 } 4883 4884 /* 4885 * ohci_allocate_bulk_resources: 4886 * 4887 * Calculates the number of tds necessary for a ctrl transfer, and allocates 4888 * all the resources necessary. 4889 * 4890 * Returns NULL if there is insufficient resources otherwise TW. 4891 */ 4892 static ohci_trans_wrapper_t * 4893 ohci_allocate_bulk_resources( 4894 ohci_state_t *ohcip, 4895 ohci_pipe_private_t *pp, 4896 usb_bulk_req_t *bulk_reqp, 4897 usb_flags_t usb_flags) 4898 { 4899 size_t td_count = 0; 4900 ohci_trans_wrapper_t *tw; 4901 4902 /* Check the size of bulk request */ 4903 if (bulk_reqp->bulk_len > OHCI_MAX_BULK_XFER_SIZE) { 4904 4905 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4906 "ohci_allocate_bulk_resources: Bulk request size 0x%x is " 4907 "more than 0x%x", bulk_reqp->bulk_len, 4908 OHCI_MAX_BULK_XFER_SIZE); 4909 4910 return (NULL); 4911 } 4912 4913 /* Get the required bulk packet size */ 4914 td_count = bulk_reqp->bulk_len / OHCI_MAX_TD_XFER_SIZE; 4915 if (bulk_reqp->bulk_len % OHCI_MAX_TD_XFER_SIZE || 4916 bulk_reqp->bulk_len == 0) { 4917 td_count++; 4918 } 4919 4920 tw = ohci_allocate_tw_resources(ohcip, pp, bulk_reqp->bulk_len, 4921 usb_flags, td_count); 4922 4923 return (tw); 4924 } 4925 4926 /* 4927 * ohci_insert_bulk_req: 4928 * 4929 * Create a Transfer Descriptor (TD) and a data buffer for a bulk 4930 * endpoint. 4931 */ 4932 /* ARGSUSED */ 4933 static void 4934 ohci_insert_bulk_req( 4935 ohci_state_t *ohcip, 4936 usba_pipe_handle_data_t *ph, 4937 usb_bulk_req_t *bulk_reqp, 4938 ohci_trans_wrapper_t *tw, 4939 usb_flags_t flags) 4940 { 4941 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 4942 uint_t bulk_pkt_size, count; 4943 size_t residue = 0, len = 0; 4944 uint32_t ctrl = 0; 4945 int pipe_dir; 4946 4947 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4948 "ohci_insert_bulk_req: bulk_reqp = 0x%p flags = 0x%x", 4949 bulk_reqp, flags); 4950 4951 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 4952 4953 /* Get the bulk pipe direction */ 4954 pipe_dir = ph->p_ep.bEndpointAddress & USB_EP_DIR_MASK; 4955 4956 /* Get the required bulk packet size */ 4957 bulk_pkt_size = min(bulk_reqp->bulk_len, OHCI_MAX_TD_XFER_SIZE); 4958 4959 if (bulk_pkt_size) 4960 residue = tw->tw_length % bulk_pkt_size; 4961 4962 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 4963 "ohci_insert_bulk_req: bulk_pkt_size = %d", bulk_pkt_size); 4964 4965 /* 4966 * Save current bulk request pointer and timeout values 4967 * in transfer wrapper. 4968 */ 4969 tw->tw_curr_xfer_reqp = (usb_opaque_t)bulk_reqp; 4970 tw->tw_timeout = bulk_reqp->bulk_timeout; 4971 4972 /* 4973 * Initialize the callback and any callback 4974 * data required when the td completes. 4975 */ 4976 tw->tw_handle_td = ohci_handle_bulk_td; 4977 tw->tw_handle_callback_value = NULL; 4978 4979 tw->tw_direction = 4980 (pipe_dir == USB_EP_DIR_OUT) ? HC_TD_OUT : HC_TD_IN; 4981 4982 if (tw->tw_direction == HC_TD_OUT && bulk_reqp->bulk_len) { 4983 4984 ASSERT(bulk_reqp->bulk_data != NULL); 4985 4986 /* Copy the data into the message */ 4987 ddi_rep_put8(tw->tw_accesshandle, 4988 bulk_reqp->bulk_data->b_rptr, (uint8_t *)tw->tw_buf, 4989 bulk_reqp->bulk_len, DDI_DEV_AUTOINCR); 4990 } 4991 4992 ctrl = tw->tw_direction|HC_TD_DT_0|HC_TD_6I; 4993 4994 /* Insert all the bulk TDs */ 4995 for (count = 0; count < tw->tw_num_tds; count++) { 4996 4997 /* Check for last td */ 4998 if (count == (tw->tw_num_tds - 1)) { 4999 5000 ctrl = ((ctrl & ~HC_TD_DI) | HC_TD_1I); 5001 5002 /* Check for inserting residue data */ 5003 if (residue) { 5004 bulk_pkt_size = residue; 5005 } 5006 5007 /* 5008 * Only set the round bit on the last TD, to ensure 5009 * the controller will always HALT the ED in case of 5010 * a short transfer. 5011 */ 5012 if (bulk_reqp->bulk_attributes & 5013 USB_ATTRS_SHORT_XFER_OK) { 5014 ctrl |= HC_TD_R; 5015 } 5016 } 5017 5018 /* Insert the TD onto the endpoint */ 5019 (void) ohci_insert_hc_td(ohcip, ctrl, len, 5020 bulk_pkt_size, 0, pp, tw); 5021 5022 len = len + bulk_pkt_size; 5023 } 5024 5025 /* Indicate that the bulk list is filled */ 5026 Set_OpReg(hcr_cmd_status, HCR_STATUS_BLF); 5027 5028 /* Start the timer for this bulk transfer */ 5029 ohci_start_xfer_timer(ohcip, pp, tw); 5030 } 5031 5032 5033 /* 5034 * ohci_start_periodic_pipe_polling: 5035 * NOTE: This function is also called from POLLED MODE. 5036 */ 5037 int 5038 ohci_start_periodic_pipe_polling( 5039 ohci_state_t *ohcip, 5040 usba_pipe_handle_data_t *ph, 5041 usb_opaque_t periodic_in_reqp, 5042 usb_flags_t flags) 5043 { 5044 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 5045 usb_ep_descr_t *eptd = &ph->p_ep; 5046 int error = USB_SUCCESS; 5047 5048 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5049 "ohci_start_periodic_pipe_polling: ep%d", 5050 ph->p_ep.bEndpointAddress & USB_EP_NUM_MASK); 5051 5052 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5053 5054 /* 5055 * Check and handle start polling on root hub interrupt pipe. 5056 */ 5057 if ((ph->p_usba_device->usb_addr == ROOT_HUB_ADDR) && 5058 ((eptd->bmAttributes & USB_EP_ATTR_MASK) == 5059 USB_EP_ATTR_INTR)) { 5060 5061 error = ohci_handle_root_hub_pipe_start_intr_polling(ph, 5062 (usb_intr_req_t *)periodic_in_reqp, flags); 5063 5064 return (error); 5065 } 5066 5067 switch (pp->pp_state) { 5068 case OHCI_PIPE_STATE_IDLE: 5069 /* Save the Original client's Periodic IN request */ 5070 pp->pp_client_periodic_in_reqp = periodic_in_reqp; 5071 5072 /* 5073 * This pipe is uninitialized or if a valid TD is 5074 * not found then insert a TD on the interrupt or 5075 * isochronous IN endpoint. 5076 */ 5077 error = ohci_start_pipe_polling(ohcip, ph, flags); 5078 5079 if (error != USB_SUCCESS) { 5080 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5081 "ohci_start_periodic_pipe_polling: " 5082 "Start polling failed"); 5083 5084 pp->pp_client_periodic_in_reqp = NULL; 5085 5086 return (error); 5087 } 5088 5089 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 5090 "ohci_start_periodic_pipe_polling: PP = 0x%p", pp); 5091 5092 ASSERT((pp->pp_tw_head != NULL) && (pp->pp_tw_tail != NULL)); 5093 5094 break; 5095 case OHCI_PIPE_STATE_ACTIVE: 5096 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5097 "ohci_start_periodic_pipe_polling: " 5098 "Polling is already in progress"); 5099 5100 error = USB_FAILURE; 5101 break; 5102 case OHCI_PIPE_STATE_ERROR: 5103 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5104 "ohci_start_periodic_pipe_polling: " 5105 "Pipe is halted and perform reset before restart polling"); 5106 5107 error = USB_FAILURE; 5108 break; 5109 default: 5110 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5111 "ohci_start_periodic_pipe_polling: Undefined state"); 5112 5113 error = USB_FAILURE; 5114 break; 5115 } 5116 5117 return (error); 5118 } 5119 5120 5121 /* 5122 * ohci_start_pipe_polling: 5123 * 5124 * Insert the number of periodic requests corresponding to polling 5125 * interval as calculated during pipe open. 5126 */ 5127 static int 5128 ohci_start_pipe_polling( 5129 ohci_state_t *ohcip, 5130 usba_pipe_handle_data_t *ph, 5131 usb_flags_t flags) 5132 { 5133 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 5134 usb_ep_descr_t *eptd = &ph->p_ep; 5135 ohci_trans_wrapper_t *tw_list, *tw; 5136 int i, total_tws; 5137 int error = USB_SUCCESS; 5138 5139 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5140 "ohci_start_pipe_polling:"); 5141 5142 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5143 5144 /* 5145 * For the start polling, pp_max_periodic_req_cnt will be zero 5146 * and for the restart polling request, it will be non zero. 5147 * 5148 * In case of start polling request, find out number of requests 5149 * required for the Interrupt IN endpoints corresponding to the 5150 * endpoint polling interval. For Isochronous IN endpoints, it is 5151 * always fixed since its polling interval will be one ms. 5152 */ 5153 if (pp->pp_max_periodic_req_cnt == 0) { 5154 5155 ohci_set_periodic_pipe_polling(ohcip, ph); 5156 } 5157 5158 ASSERT(pp->pp_max_periodic_req_cnt != 0); 5159 5160 /* Allocate all the necessary resources for the IN transfer */ 5161 tw_list = NULL; 5162 total_tws = pp->pp_max_periodic_req_cnt - pp->pp_cur_periodic_req_cnt; 5163 for (i = 0; i < total_tws; i++) { 5164 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 5165 case USB_EP_ATTR_INTR: 5166 tw = ohci_allocate_intr_resources( 5167 ohcip, ph, NULL, flags); 5168 break; 5169 case USB_EP_ATTR_ISOCH: 5170 tw = ohci_allocate_isoc_resources( 5171 ohcip, ph, NULL, flags); 5172 break; 5173 } 5174 if (tw == NULL) { 5175 error = USB_NO_RESOURCES; 5176 /* There are not enough resources, deallocate the TWs */ 5177 tw = tw_list; 5178 while (tw != NULL) { 5179 tw_list = tw->tw_next; 5180 ohci_deallocate_periodic_in_resource( 5181 ohcip, pp, tw); 5182 ohci_deallocate_tw_resources(ohcip, pp, tw); 5183 tw = tw_list; 5184 } 5185 return (error); 5186 } else { 5187 if (tw_list == NULL) { 5188 tw_list = tw; 5189 } 5190 } 5191 } 5192 5193 i = 0; 5194 while (pp->pp_cur_periodic_req_cnt < pp->pp_max_periodic_req_cnt) { 5195 5196 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5197 "ohci_start_pipe_polling: max = %d curr = %d tw = %p:", 5198 pp->pp_max_periodic_req_cnt, pp->pp_cur_periodic_req_cnt, 5199 tw_list); 5200 5201 tw = tw_list; 5202 tw_list = tw->tw_next; 5203 5204 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 5205 case USB_EP_ATTR_INTR: 5206 ohci_insert_intr_req(ohcip, pp, tw, flags); 5207 break; 5208 case USB_EP_ATTR_ISOCH: 5209 error = ohci_insert_isoc_req(ohcip, pp, tw, flags); 5210 break; 5211 } 5212 if (error == USB_SUCCESS) { 5213 pp->pp_cur_periodic_req_cnt++; 5214 } else { 5215 /* 5216 * Deallocate the remaining tw 5217 * The current tw should have already been deallocated 5218 */ 5219 tw = tw_list; 5220 while (tw != NULL) { 5221 tw_list = tw->tw_next; 5222 ohci_deallocate_periodic_in_resource( 5223 ohcip, pp, tw); 5224 ohci_deallocate_tw_resources(ohcip, pp, tw); 5225 tw = tw_list; 5226 } 5227 /* 5228 * If this is the first req return an error. 5229 * Otherwise return success. 5230 */ 5231 if (i != 0) { 5232 error = USB_SUCCESS; 5233 } 5234 5235 break; 5236 } 5237 i++; 5238 } 5239 5240 return (error); 5241 } 5242 5243 5244 /* 5245 * ohci_set_periodic_pipe_polling: 5246 * 5247 * Calculate the number of periodic requests needed corresponding to the 5248 * interrupt/isochronous IN endpoints polling interval. Table below gives 5249 * the number of periodic requests needed for the interrupt/isochronous 5250 * IN endpoints according to endpoint polling interval. 5251 * 5252 * Polling interval Number of periodic requests 5253 * 5254 * 1ms 4 5255 * 2ms 2 5256 * 4ms to 32ms 1 5257 */ 5258 static void 5259 ohci_set_periodic_pipe_polling( 5260 ohci_state_t *ohcip, 5261 usba_pipe_handle_data_t *ph) 5262 { 5263 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 5264 usb_ep_descr_t *endpoint = &ph->p_ep; 5265 uchar_t ep_attr = endpoint->bmAttributes; 5266 uint_t interval; 5267 5268 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5269 "ohci_set_periodic_pipe_polling:"); 5270 5271 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5272 5273 pp->pp_cur_periodic_req_cnt = 0; 5274 5275 /* 5276 * Check usb flag whether USB_FLAGS_ONE_TIME_POLL flag is 5277 * set and if so, set pp->pp_max_periodic_req_cnt to one. 5278 */ 5279 if (((ep_attr & USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) && 5280 (pp->pp_client_periodic_in_reqp)) { 5281 usb_intr_req_t *intr_reqp = 5282 (usb_intr_req_t *)pp->pp_client_periodic_in_reqp; 5283 5284 if (intr_reqp->intr_attributes & 5285 USB_ATTRS_ONE_XFER) { 5286 5287 pp->pp_max_periodic_req_cnt = INTR_XMS_REQS; 5288 5289 return; 5290 } 5291 } 5292 5293 mutex_enter(&ph->p_usba_device->usb_mutex); 5294 5295 /* 5296 * The ohci_adjust_polling_interval function will not fail 5297 * at this instance since bandwidth allocation is already 5298 * done. Here we are getting only the periodic interval. 5299 */ 5300 interval = ohci_adjust_polling_interval(ohcip, endpoint, 5301 ph->p_usba_device->usb_port_status); 5302 5303 mutex_exit(&ph->p_usba_device->usb_mutex); 5304 5305 switch (interval) { 5306 case INTR_1MS_POLL: 5307 pp->pp_max_periodic_req_cnt = INTR_1MS_REQS; 5308 break; 5309 case INTR_2MS_POLL: 5310 pp->pp_max_periodic_req_cnt = INTR_2MS_REQS; 5311 break; 5312 default: 5313 pp->pp_max_periodic_req_cnt = INTR_XMS_REQS; 5314 break; 5315 } 5316 5317 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5318 "ohci_set_periodic_pipe_polling: Max periodic requests = %d", 5319 pp->pp_max_periodic_req_cnt); 5320 } 5321 5322 /* 5323 * ohci_allocate_intr_resources: 5324 * 5325 * Calculates the number of tds necessary for a intr transfer, and allocates 5326 * all the necessary resources. 5327 * 5328 * Returns NULL if there is insufficient resources otherwise TW. 5329 */ 5330 static ohci_trans_wrapper_t * 5331 ohci_allocate_intr_resources( 5332 ohci_state_t *ohcip, 5333 usba_pipe_handle_data_t *ph, 5334 usb_intr_req_t *intr_reqp, 5335 usb_flags_t flags) 5336 { 5337 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 5338 int pipe_dir; 5339 size_t td_count = 1; 5340 size_t tw_length; 5341 ohci_trans_wrapper_t *tw; 5342 5343 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5344 "ohci_allocate_intr_resources:"); 5345 5346 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5347 5348 pipe_dir = ph->p_ep.bEndpointAddress & USB_EP_DIR_MASK; 5349 5350 /* Get the length of interrupt transfer & alloc data */ 5351 if (intr_reqp) { 5352 tw_length = intr_reqp->intr_len; 5353 } else { 5354 ASSERT(pipe_dir == USB_EP_DIR_IN); 5355 tw_length = (pp->pp_client_periodic_in_reqp) ? 5356 (((usb_intr_req_t *)pp-> 5357 pp_client_periodic_in_reqp)->intr_len) : 5358 ph->p_ep.wMaxPacketSize; 5359 } 5360 5361 /* Check the size of interrupt request */ 5362 if (tw_length > OHCI_MAX_TD_XFER_SIZE) { 5363 5364 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5365 "ohci_allocate_intr_resources: Intr request size 0x%lx is " 5366 "more than 0x%x", tw_length, OHCI_MAX_TD_XFER_SIZE); 5367 5368 return (NULL); 5369 } 5370 5371 if ((tw = ohci_allocate_tw_resources(ohcip, pp, tw_length, 5372 flags, td_count)) == NULL) { 5373 5374 return (NULL); 5375 } 5376 5377 if (pipe_dir == USB_EP_DIR_IN) { 5378 if (ohci_allocate_periodic_in_resource(ohcip, pp, tw, flags) != 5379 USB_SUCCESS) { 5380 5381 ohci_deallocate_tw_resources(ohcip, pp, tw); 5382 return (NULL); 5383 } 5384 tw->tw_direction = HC_TD_IN; 5385 } else { 5386 if (tw_length) { 5387 ASSERT(intr_reqp->intr_data != NULL); 5388 5389 /* Copy the data into the message */ 5390 ddi_rep_put8(tw->tw_accesshandle, 5391 intr_reqp->intr_data->b_rptr, (uint8_t *)tw->tw_buf, 5392 intr_reqp->intr_len, DDI_DEV_AUTOINCR); 5393 } 5394 5395 tw->tw_curr_xfer_reqp = (usb_opaque_t)intr_reqp; 5396 tw->tw_direction = HC_TD_OUT; 5397 } 5398 5399 if (intr_reqp) { 5400 tw->tw_timeout = intr_reqp->intr_timeout; 5401 } 5402 5403 /* 5404 * Initialize the callback and any callback 5405 * data required when the td completes. 5406 */ 5407 tw->tw_handle_td = ohci_handle_intr_td; 5408 tw->tw_handle_callback_value = NULL; 5409 5410 return (tw); 5411 } 5412 5413 /* 5414 * ohci_insert_intr_req: 5415 * 5416 * Insert an Interrupt request into the Host Controller's periodic list. 5417 */ 5418 /* ARGSUSED */ 5419 static void 5420 ohci_insert_intr_req( 5421 ohci_state_t *ohcip, 5422 ohci_pipe_private_t *pp, 5423 ohci_trans_wrapper_t *tw, 5424 usb_flags_t flags) 5425 { 5426 usb_intr_req_t *curr_intr_reqp = NULL; 5427 uint_t ctrl = 0; 5428 5429 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5430 5431 ASSERT(tw->tw_curr_xfer_reqp != NULL); 5432 5433 /* Get the current interrupt request pointer */ 5434 curr_intr_reqp = (usb_intr_req_t *)tw->tw_curr_xfer_reqp; 5435 5436 ctrl = tw->tw_direction | HC_TD_DT_0 | HC_TD_1I; 5437 5438 if (curr_intr_reqp->intr_attributes & USB_ATTRS_SHORT_XFER_OK) { 5439 ctrl |= HC_TD_R; 5440 } 5441 5442 /* Insert another interrupt TD */ 5443 (void) ohci_insert_hc_td(ohcip, ctrl, 0, tw->tw_length, 0, pp, tw); 5444 5445 /* Start the timer for this Interrupt transfer */ 5446 ohci_start_xfer_timer(ohcip, pp, tw); 5447 } 5448 5449 5450 /* 5451 * ohci_stop_periodic_pipe_polling: 5452 */ 5453 /* ARGSUSED */ 5454 static int 5455 ohci_stop_periodic_pipe_polling( 5456 ohci_state_t *ohcip, 5457 usba_pipe_handle_data_t *ph, 5458 usb_flags_t flags) 5459 { 5460 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 5461 usb_ep_descr_t *eptd = &ph->p_ep; 5462 5463 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5464 "ohci_stop_periodic_pipe_polling: Flags = 0x%x", flags); 5465 5466 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5467 5468 /* 5469 * Check and handle stop polling on root hub interrupt pipe. 5470 */ 5471 if ((ph->p_usba_device->usb_addr == ROOT_HUB_ADDR) && 5472 ((eptd->bmAttributes & USB_EP_ATTR_MASK) == 5473 USB_EP_ATTR_INTR)) { 5474 5475 ohci_handle_root_hub_pipe_stop_intr_polling( 5476 ph, flags); 5477 return (USB_SUCCESS); 5478 } 5479 5480 if (pp->pp_state != OHCI_PIPE_STATE_ACTIVE) { 5481 5482 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5483 "ohci_stop_periodic_pipe_polling: Polling already stopped"); 5484 5485 return (USB_SUCCESS); 5486 } 5487 5488 /* Set pipe state to pipe stop polling */ 5489 pp->pp_state = OHCI_PIPE_STATE_STOP_POLLING; 5490 5491 ohci_pipe_cleanup(ohcip, ph); 5492 5493 return (USB_SUCCESS); 5494 } 5495 5496 /* 5497 * ohci_allocate_isoc_resources: 5498 * 5499 * Calculates the number of tds necessary for a intr transfer, and allocates 5500 * all the necessary resources. 5501 * 5502 * Returns NULL if there is insufficient resources otherwise TW. 5503 */ 5504 static ohci_trans_wrapper_t * 5505 ohci_allocate_isoc_resources( 5506 ohci_state_t *ohcip, 5507 usba_pipe_handle_data_t *ph, 5508 usb_isoc_req_t *isoc_reqp, 5509 usb_flags_t flags) 5510 { 5511 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 5512 int pipe_dir; 5513 uint_t max_pkt_size = ph->p_ep.wMaxPacketSize; 5514 uint_t max_isoc_xfer_size; 5515 usb_isoc_pkt_descr_t *isoc_pkt_descr, *start_isoc_pkt_descr; 5516 ushort_t isoc_pkt_count; 5517 size_t count, td_count; 5518 size_t tw_length; 5519 size_t isoc_pkts_length; 5520 ohci_trans_wrapper_t *tw; 5521 5522 5523 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5524 "ohci_allocate_isoc_resources: flags = ox%x", flags); 5525 5526 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5527 5528 /* 5529 * Check whether pipe is in halted state. 5530 */ 5531 if (pp->pp_state == OHCI_PIPE_STATE_ERROR) { 5532 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5533 "ohci_allocate_isoc_resources:" 5534 "Pipe is in error state, need pipe reset to continue"); 5535 5536 return (NULL); 5537 } 5538 5539 pipe_dir = ph->p_ep.bEndpointAddress & USB_EP_DIR_MASK; 5540 5541 /* Calculate the maximum isochronous transfer size */ 5542 max_isoc_xfer_size = OHCI_MAX_ISOC_PKTS_PER_XFER * max_pkt_size; 5543 5544 if (isoc_reqp) { 5545 isoc_pkt_descr = isoc_reqp->isoc_pkt_descr; 5546 isoc_pkt_count = isoc_reqp->isoc_pkts_count; 5547 isoc_pkts_length = isoc_reqp->isoc_pkts_length; 5548 } else { 5549 isoc_pkt_descr = ((usb_isoc_req_t *) 5550 pp->pp_client_periodic_in_reqp)->isoc_pkt_descr; 5551 5552 isoc_pkt_count = ((usb_isoc_req_t *) 5553 pp->pp_client_periodic_in_reqp)->isoc_pkts_count; 5554 5555 isoc_pkts_length = ((usb_isoc_req_t *) 5556 pp->pp_client_periodic_in_reqp)->isoc_pkts_length; 5557 } 5558 5559 start_isoc_pkt_descr = isoc_pkt_descr; 5560 5561 /* 5562 * For isochronous IN pipe, get value of number of isochronous 5563 * packets per usb isochronous request 5564 */ 5565 if (pipe_dir == USB_EP_DIR_IN) { 5566 for (count = 0, tw_length = 0; 5567 count < isoc_pkt_count; count++) { 5568 tw_length += isoc_pkt_descr->isoc_pkt_length; 5569 isoc_pkt_descr++; 5570 } 5571 5572 if ((isoc_pkts_length) && (isoc_pkts_length != tw_length)) { 5573 5574 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5575 "ohci_allocate_isoc_resources: " 5576 "isoc_pkts_length 0x%x is not equal to the sum of " 5577 "all pkt lengths 0x%x in an isoc request", 5578 isoc_pkts_length, tw_length); 5579 5580 return (NULL); 5581 } 5582 5583 } else { 5584 ASSERT(isoc_reqp != NULL); 5585 tw_length = isoc_reqp->isoc_data->b_wptr - 5586 isoc_reqp->isoc_data->b_rptr; 5587 } 5588 5589 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5590 "ohci_allocate_isoc_resources: length = 0x%lx", tw_length); 5591 5592 /* Check the size of isochronous request */ 5593 if (tw_length > max_isoc_xfer_size) { 5594 5595 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5596 "ohci_allocate_isoc_resources: Maximum isoc request" 5597 "size 0x%x Given isoc request size 0x%lx", 5598 max_isoc_xfer_size, tw_length); 5599 5600 return (NULL); 5601 } 5602 5603 /* 5604 * Each isochronous TD can hold data upto eight isochronous 5605 * data packets. Calculate the number of isochronous TDs needs 5606 * to be insert to complete current isochronous request. 5607 */ 5608 td_count = isoc_pkt_count / OHCI_ISOC_PKTS_PER_TD; 5609 5610 if (isoc_pkt_count % OHCI_ISOC_PKTS_PER_TD) { 5611 td_count++; 5612 } 5613 5614 tw = ohci_create_isoc_transfer_wrapper(ohcip, pp, tw_length, 5615 start_isoc_pkt_descr, isoc_pkt_count, td_count, flags); 5616 5617 if (tw == NULL) { 5618 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5619 "ohci_create_isoc_transfer_wrapper: " 5620 "Unable to allocate TW"); 5621 5622 return (NULL); 5623 } 5624 5625 if (ohci_allocate_tds_for_tw(ohcip, tw, td_count) == 5626 USB_SUCCESS) { 5627 tw->tw_num_tds = td_count; 5628 } else { 5629 ohci_deallocate_tw_resources(ohcip, pp, tw); 5630 5631 return (NULL); 5632 } 5633 5634 if (pipe_dir == USB_EP_DIR_IN) { 5635 if (ohci_allocate_periodic_in_resource(ohcip, pp, tw, flags) != 5636 USB_SUCCESS) { 5637 5638 ohci_deallocate_tw_resources(ohcip, pp, tw); 5639 return (NULL); 5640 } 5641 tw->tw_direction = HC_TD_IN; 5642 } else { 5643 if (tw->tw_length) { 5644 uchar_t *p; 5645 int i; 5646 5647 ASSERT(isoc_reqp->isoc_data != NULL); 5648 p = isoc_reqp->isoc_data->b_rptr; 5649 5650 /* Copy the data into the message */ 5651 for (i = 0; i < td_count; i++) { 5652 ddi_rep_put8( 5653 tw->tw_isoc_bufs[i].mem_handle, p, 5654 (uint8_t *)tw->tw_isoc_bufs[i].buf_addr, 5655 tw->tw_isoc_bufs[i].length, 5656 DDI_DEV_AUTOINCR); 5657 p += tw->tw_isoc_bufs[i].length; 5658 } 5659 } 5660 tw->tw_curr_xfer_reqp = (usb_opaque_t)isoc_reqp; 5661 tw->tw_direction = HC_TD_OUT; 5662 } 5663 5664 /* 5665 * Initialize the callback and any callback 5666 * data required when the td completes. 5667 */ 5668 tw->tw_handle_td = ohci_handle_isoc_td; 5669 tw->tw_handle_callback_value = NULL; 5670 5671 return (tw); 5672 } 5673 5674 /* 5675 * ohci_insert_isoc_req: 5676 * 5677 * Insert an isochronous request into the Host Controller's 5678 * isochronous list. If there is an error is will appropriately 5679 * deallocate the unused resources. 5680 */ 5681 static int 5682 ohci_insert_isoc_req( 5683 ohci_state_t *ohcip, 5684 ohci_pipe_private_t *pp, 5685 ohci_trans_wrapper_t *tw, 5686 uint_t flags) 5687 { 5688 size_t curr_isoc_xfer_offset, curr_isoc_xfer_len; 5689 uint_t isoc_pkts, residue, count; 5690 uint_t i, ctrl, frame_count; 5691 uint_t error = USB_SUCCESS; 5692 usb_isoc_req_t *curr_isoc_reqp; 5693 usb_isoc_pkt_descr_t *curr_isoc_pkt_descr; 5694 5695 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5696 "ohci_insert_isoc_req: flags = 0x%x", flags); 5697 5698 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5699 5700 /* 5701 * Get the current isochronous request and packet 5702 * descriptor pointers. 5703 */ 5704 curr_isoc_reqp = (usb_isoc_req_t *)tw->tw_curr_xfer_reqp; 5705 curr_isoc_pkt_descr = curr_isoc_reqp->isoc_pkt_descr; 5706 5707 ASSERT(curr_isoc_reqp != NULL); 5708 ASSERT(curr_isoc_reqp->isoc_pkt_descr != NULL); 5709 5710 /* 5711 * Save address of first usb isochronous packet descriptor. 5712 */ 5713 tw->tw_curr_isoc_pktp = curr_isoc_reqp->isoc_pkt_descr; 5714 5715 /* Insert all the isochronous TDs */ 5716 for (count = 0, curr_isoc_xfer_offset = 0, 5717 isoc_pkts = 0; count < tw->tw_num_tds; count++) { 5718 5719 residue = curr_isoc_reqp->isoc_pkts_count - isoc_pkts; 5720 5721 /* Check for inserting residue data */ 5722 if ((count == (tw->tw_num_tds - 1)) && 5723 (residue < OHCI_ISOC_PKTS_PER_TD)) { 5724 frame_count = residue; 5725 } else { 5726 frame_count = OHCI_ISOC_PKTS_PER_TD; 5727 } 5728 5729 curr_isoc_pkt_descr = tw->tw_curr_isoc_pktp; 5730 5731 /* 5732 * Calculate length of isochronous transfer 5733 * for the current TD. 5734 */ 5735 for (i = 0, curr_isoc_xfer_len = 0; 5736 i < frame_count; i++, curr_isoc_pkt_descr++) { 5737 curr_isoc_xfer_len += 5738 curr_isoc_pkt_descr->isoc_pkt_length; 5739 } 5740 5741 /* 5742 * Programm td control field by checking whether this 5743 * is last td. 5744 */ 5745 if (count == (tw->tw_num_tds - 1)) { 5746 ctrl = ((((frame_count - 1) << HC_ITD_FC_SHIFT) & 5747 HC_ITD_FC) | HC_TD_DT_0 | HC_TD_0I); 5748 } else { 5749 ctrl = ((((frame_count - 1) << HC_ITD_FC_SHIFT) & 5750 HC_ITD_FC) | HC_TD_DT_0 | HC_TD_6I); 5751 } 5752 5753 /* Insert the TD into the endpoint */ 5754 if ((error = ohci_insert_hc_td(ohcip, ctrl, count, 5755 curr_isoc_xfer_len, 0, pp, tw)) != 5756 USB_SUCCESS) { 5757 tw->tw_num_tds = count; 5758 tw->tw_length = curr_isoc_xfer_offset; 5759 break; 5760 } 5761 5762 isoc_pkts += frame_count; 5763 tw->tw_curr_isoc_pktp += frame_count; 5764 curr_isoc_xfer_offset += curr_isoc_xfer_len; 5765 } 5766 5767 if (error != USB_SUCCESS) { 5768 /* Free periodic in resources */ 5769 if (tw->tw_direction == USB_EP_DIR_IN) { 5770 ohci_deallocate_periodic_in_resource(ohcip, pp, tw); 5771 } 5772 5773 /* Free all resources if IN or if count == 0(for both IN/OUT) */ 5774 if (tw->tw_direction == USB_EP_DIR_IN || count == 0) { 5775 5776 ohci_deallocate_tw_resources(ohcip, pp, tw); 5777 5778 if (pp->pp_cur_periodic_req_cnt) { 5779 /* 5780 * Set pipe state to stop polling and 5781 * error to no resource. Don't insert 5782 * any more isochronous polling requests. 5783 */ 5784 pp->pp_state = OHCI_PIPE_STATE_STOP_POLLING; 5785 pp->pp_error = error; 5786 } else { 5787 /* Set periodic in pipe state to idle */ 5788 pp->pp_state = OHCI_PIPE_STATE_IDLE; 5789 } 5790 } 5791 } else { 5792 5793 /* 5794 * Reset back to the address of first usb isochronous 5795 * packet descriptor. 5796 */ 5797 tw->tw_curr_isoc_pktp = curr_isoc_reqp->isoc_pkt_descr; 5798 5799 /* Reset the CONTINUE flag */ 5800 pp->pp_flag &= ~OHCI_ISOC_XFER_CONTINUE; 5801 } 5802 5803 return (error); 5804 } 5805 5806 5807 /* 5808 * ohci_insert_hc_td: 5809 * 5810 * Insert a Transfer Descriptor (TD) on an Endpoint Descriptor (ED). 5811 * Always returns USB_SUCCESS, except for ISOCH. 5812 */ 5813 static int 5814 ohci_insert_hc_td( 5815 ohci_state_t *ohcip, 5816 uint_t hctd_ctrl, 5817 uint32_t hctd_dma_offs, 5818 size_t hctd_length, 5819 uint32_t hctd_ctrl_phase, 5820 ohci_pipe_private_t *pp, 5821 ohci_trans_wrapper_t *tw) 5822 { 5823 ohci_td_t *new_dummy; 5824 ohci_td_t *cpu_current_dummy; 5825 ohci_ed_t *ept = pp->pp_ept; 5826 int error; 5827 5828 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5829 5830 /* Retrieve preallocated td from the TW */ 5831 new_dummy = tw->tw_hctd_free_list; 5832 5833 ASSERT(new_dummy != NULL); 5834 5835 tw->tw_hctd_free_list = ohci_td_iommu_to_cpu(ohcip, 5836 Get_TD(new_dummy->hctd_tw_next_td)); 5837 Set_TD(new_dummy->hctd_tw_next_td, NULL); 5838 5839 /* Fill in the current dummy */ 5840 cpu_current_dummy = (ohci_td_t *) 5841 (ohci_td_iommu_to_cpu(ohcip, Get_ED(ept->hced_tailp))); 5842 5843 /* 5844 * Fill in the current dummy td and 5845 * add the new dummy to the end. 5846 */ 5847 ohci_fill_in_td(ohcip, cpu_current_dummy, new_dummy, 5848 hctd_ctrl, hctd_dma_offs, hctd_length, hctd_ctrl_phase, pp, tw); 5849 5850 /* 5851 * If this is an isochronous TD, first write proper 5852 * starting usb frame number in which this TD must 5853 * can be processed. After writing the frame number 5854 * insert this TD into the ED's list. 5855 */ 5856 if ((pp->pp_pipe_handle->p_ep.bmAttributes & 5857 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 5858 5859 error = ohci_insert_td_with_frame_number( 5860 ohcip, pp, tw, cpu_current_dummy, new_dummy); 5861 5862 if (error != USB_SUCCESS) { 5863 /* Reset the current dummy back to a dummy */ 5864 bzero((char *)cpu_current_dummy, sizeof (ohci_td_t)); 5865 Set_TD(cpu_current_dummy->hctd_state, HC_TD_DUMMY); 5866 5867 /* return the new dummy back to the free list */ 5868 bzero((char *)new_dummy, sizeof (ohci_td_t)); 5869 Set_TD(new_dummy->hctd_state, HC_TD_DUMMY); 5870 if (tw->tw_hctd_free_list != NULL) { 5871 Set_TD(new_dummy->hctd_tw_next_td, 5872 ohci_td_cpu_to_iommu(ohcip, 5873 tw->tw_hctd_free_list)); 5874 } 5875 tw->tw_hctd_free_list = new_dummy; 5876 5877 return (error); 5878 } 5879 } else { 5880 /* 5881 * For control, bulk and interrupt TD, just 5882 * add the new dummy to the ED's list. When 5883 * this occurs, the Host Controller ill see 5884 * the newly filled in dummy TD. 5885 */ 5886 Set_ED(ept->hced_tailp, 5887 (ohci_td_cpu_to_iommu(ohcip, new_dummy))); 5888 } 5889 5890 /* Insert this td onto the tw */ 5891 ohci_insert_td_on_tw(ohcip, tw, cpu_current_dummy); 5892 5893 return (USB_SUCCESS); 5894 } 5895 5896 5897 /* 5898 * ohci_allocate_td_from_pool: 5899 * 5900 * Allocate a Transfer Descriptor (TD) from the TD buffer pool. 5901 */ 5902 static ohci_td_t * 5903 ohci_allocate_td_from_pool(ohci_state_t *ohcip) 5904 { 5905 int i, state; 5906 ohci_td_t *td; 5907 5908 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 5909 5910 /* 5911 * Search for a blank Transfer Descriptor (TD) 5912 * in the TD buffer pool. 5913 */ 5914 for (i = 0; i < ohci_td_pool_size; i ++) { 5915 state = Get_TD(ohcip->ohci_td_pool_addr[i].hctd_state); 5916 if (state == HC_TD_FREE) { 5917 break; 5918 } 5919 } 5920 5921 if (i >= ohci_td_pool_size) { 5922 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 5923 "ohci_allocate_td_from_pool: TD exhausted"); 5924 5925 return (NULL); 5926 } 5927 5928 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 5929 "ohci_allocate_td_from_pool: Allocated %d", i); 5930 5931 /* Create a new dummy for the end of the TD list */ 5932 td = &ohcip->ohci_td_pool_addr[i]; 5933 5934 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5935 "ohci_allocate_td_from_pool: td 0x%p", (void *)td); 5936 5937 /* Mark the newly allocated TD as a dummy */ 5938 Set_TD(td->hctd_state, HC_TD_DUMMY); 5939 5940 return (td); 5941 } 5942 5943 /* 5944 * ohci_fill_in_td: 5945 * 5946 * Fill in the fields of a Transfer Descriptor (TD). 5947 * 5948 * hctd_dma_offs - different meanings for non-isoc and isoc TDs: 5949 * starting offset into the TW buffer for a non-isoc TD 5950 * and the index into the isoc TD list for an isoc TD. 5951 * For non-isoc TDs, the starting offset should be 4k 5952 * aligned and the TDs in one transfer must be filled in 5953 * increasing order. 5954 */ 5955 static void 5956 ohci_fill_in_td( 5957 ohci_state_t *ohcip, 5958 ohci_td_t *td, 5959 ohci_td_t *new_dummy, 5960 uint_t hctd_ctrl, 5961 uint32_t hctd_dma_offs, 5962 size_t hctd_length, 5963 uint32_t hctd_ctrl_phase, 5964 ohci_pipe_private_t *pp, 5965 ohci_trans_wrapper_t *tw) 5966 { 5967 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 5968 "ohci_fill_in_td: td 0x%p bufoffs 0x%x len 0x%lx", 5969 td, hctd_dma_offs, hctd_length); 5970 5971 /* Assert that the td to be filled in is a dummy */ 5972 ASSERT(Get_TD(td->hctd_state) == HC_TD_DUMMY); 5973 5974 /* Change TD's state Active */ 5975 Set_TD(td->hctd_state, HC_TD_ACTIVE); 5976 5977 /* Update the TD special fields */ 5978 if ((pp->pp_pipe_handle->p_ep.bmAttributes & 5979 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 5980 ohci_init_itd(ohcip, tw, hctd_ctrl, hctd_dma_offs, td); 5981 } else { 5982 /* Update the dummy with control information */ 5983 Set_TD(td->hctd_ctrl, (hctd_ctrl | HC_TD_CC_NA)); 5984 5985 ohci_init_td(ohcip, tw, hctd_dma_offs, hctd_length, td); 5986 } 5987 5988 /* The current dummy now points to the new dummy */ 5989 Set_TD(td->hctd_next_td, (ohci_td_cpu_to_iommu(ohcip, new_dummy))); 5990 5991 /* 5992 * For Control transfer, hctd_ctrl_phase is a valid field. 5993 */ 5994 if (hctd_ctrl_phase) { 5995 Set_TD(td->hctd_ctrl_phase, hctd_ctrl_phase); 5996 } 5997 5998 /* Print the td */ 5999 ohci_print_td(ohcip, td); 6000 6001 /* Fill in the wrapper portion of the TD */ 6002 6003 /* Set the transfer wrapper */ 6004 ASSERT(tw != NULL); 6005 ASSERT(tw->tw_id != NULL); 6006 6007 Set_TD(td->hctd_trans_wrapper, (uint32_t)tw->tw_id); 6008 Set_TD(td->hctd_tw_next_td, NULL); 6009 } 6010 6011 6012 /* 6013 * ohci_init_td: 6014 * 6015 * Initialize the buffer address portion of non-isoc Transfer 6016 * Descriptor (TD). 6017 */ 6018 void 6019 ohci_init_td( 6020 ohci_state_t *ohcip, 6021 ohci_trans_wrapper_t *tw, 6022 uint32_t hctd_dma_offs, 6023 size_t hctd_length, 6024 ohci_td_t *td) 6025 { 6026 uint32_t page_addr, start_addr = 0, end_addr = 0; 6027 size_t buf_len = hctd_length; 6028 int rem_len, i; 6029 6030 /* 6031 * TDs must be filled in increasing DMA offset order. 6032 * tw_dma_offs is initialized to be 0 at TW creation and 6033 * is only increased in this function. 6034 */ 6035 ASSERT(buf_len == 0 || hctd_dma_offs >= tw->tw_dma_offs); 6036 6037 Set_TD(td->hctd_xfer_offs, hctd_dma_offs); 6038 Set_TD(td->hctd_xfer_len, buf_len); 6039 6040 /* Computing the starting buffer address and end buffer address */ 6041 for (i = 0; (i < 2) && (buf_len > 0); i++) { 6042 /* Advance to the next DMA cookie if necessary */ 6043 if ((tw->tw_dma_offs + tw->tw_cookie.dmac_size) <= 6044 hctd_dma_offs) { 6045 /* 6046 * tw_dma_offs always points to the starting offset 6047 * of a cookie 6048 */ 6049 tw->tw_dma_offs += tw->tw_cookie.dmac_size; 6050 ddi_dma_nextcookie(tw->tw_dmahandle, &tw->tw_cookie); 6051 tw->tw_cookie_idx++; 6052 ASSERT(tw->tw_cookie_idx < tw->tw_ncookies); 6053 } 6054 6055 ASSERT((tw->tw_dma_offs + tw->tw_cookie.dmac_size) > 6056 hctd_dma_offs); 6057 6058 /* 6059 * Counting the remained buffer length to be filled in 6060 * the TD for current DMA cookie 6061 */ 6062 rem_len = (tw->tw_dma_offs + tw->tw_cookie.dmac_size) - 6063 hctd_dma_offs; 6064 6065 /* Get the beginning address of the buffer */ 6066 page_addr = (hctd_dma_offs - tw->tw_dma_offs) + 6067 tw->tw_cookie.dmac_address; 6068 ASSERT((page_addr % OHCI_4K_ALIGN) == 0); 6069 6070 if (i == 0) { 6071 start_addr = page_addr; 6072 } 6073 6074 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6075 "ohci_init_td: page_addr 0x%p dmac_size " 6076 "0x%lx idx %d", page_addr, tw->tw_cookie.dmac_size, 6077 tw->tw_cookie_idx); 6078 6079 if (buf_len <= OHCI_MAX_TD_BUF_SIZE) { 6080 ASSERT(buf_len <= rem_len); 6081 end_addr = page_addr + buf_len - 1; 6082 buf_len = 0; 6083 break; 6084 } else { 6085 ASSERT(rem_len >= OHCI_MAX_TD_BUF_SIZE); 6086 buf_len -= OHCI_MAX_TD_BUF_SIZE; 6087 hctd_dma_offs += OHCI_MAX_TD_BUF_SIZE; 6088 } 6089 } 6090 6091 ASSERT(buf_len == 0); 6092 6093 Set_TD(td->hctd_cbp, start_addr); 6094 Set_TD(td->hctd_buf_end, end_addr); 6095 } 6096 6097 6098 /* 6099 * ohci_init_itd: 6100 * 6101 * Initialize the buffer address portion of isoc Transfer Descriptor (TD). 6102 */ 6103 static void 6104 ohci_init_itd( 6105 ohci_state_t *ohcip, 6106 ohci_trans_wrapper_t *tw, 6107 uint_t hctd_ctrl, 6108 uint32_t index, 6109 ohci_td_t *td) 6110 { 6111 uint32_t start_addr, end_addr, offset, offset_addr; 6112 ohci_isoc_buf_t *bufp; 6113 size_t buf_len; 6114 uint_t buf, fc, toggle, flag; 6115 usb_isoc_pkt_descr_t *temp_pkt_descr; 6116 int i; 6117 6118 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 6119 6120 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6121 "ohci_init_itd: ctrl = 0x%x", hctd_ctrl); 6122 6123 /* 6124 * Write control information except starting 6125 * usb frame number. 6126 */ 6127 Set_TD(td->hctd_ctrl, (hctd_ctrl | HC_TD_CC_NA)); 6128 6129 bufp = &tw->tw_isoc_bufs[index]; 6130 Set_TD(td->hctd_xfer_offs, index); 6131 Set_TD(td->hctd_xfer_len, bufp->length); 6132 6133 start_addr = bufp->cookie.dmac_address; 6134 ASSERT((start_addr % OHCI_4K_ALIGN) == 0); 6135 6136 buf_len = bufp->length; 6137 if (bufp->ncookies == OHCI_DMA_ATTR_TD_SGLLEN) { 6138 buf_len = bufp->length - bufp->cookie.dmac_size; 6139 ddi_dma_nextcookie(bufp->dma_handle, &bufp->cookie); 6140 } 6141 end_addr = bufp->cookie.dmac_address + buf_len - 1; 6142 6143 /* 6144 * For an isochronous transfer, the hctd_cbp contains, 6145 * the 4k page, and not the actual start of the buffer. 6146 */ 6147 Set_TD(td->hctd_cbp, ((uint32_t)start_addr & HC_ITD_PAGE_MASK)); 6148 Set_TD(td->hctd_buf_end, end_addr); 6149 6150 fc = (hctd_ctrl & HC_ITD_FC) >> HC_ITD_FC_SHIFT; 6151 toggle = 0; 6152 buf = start_addr; 6153 6154 /* 6155 * Get the address of first isochronous data packet 6156 * for the current isochronous TD. 6157 */ 6158 temp_pkt_descr = tw->tw_curr_isoc_pktp; 6159 6160 /* The offsets are actually offsets into the page */ 6161 for (i = 0; i <= fc; i++) { 6162 offset_addr = (uint32_t)((buf & 6163 HC_ITD_OFFSET_ADDR) | (HC_ITD_OFFSET_CC)); 6164 6165 flag = ((start_addr & 6166 HC_ITD_PAGE_MASK) ^ (buf & HC_ITD_PAGE_MASK)); 6167 6168 if (flag) { 6169 offset_addr |= HC_ITD_4KBOUNDARY_CROSS; 6170 } 6171 6172 if (toggle) { 6173 offset = (uint32_t)((offset_addr << 6174 HC_ITD_OFFSET_SHIFT) & HC_ITD_ODD_OFFSET); 6175 6176 Set_TD(td->hctd_offsets[i / 2], 6177 Get_TD(td->hctd_offsets[i / 2]) | offset); 6178 toggle = 0; 6179 } else { 6180 offset = (uint32_t)(offset_addr & HC_ITD_EVEN_OFFSET); 6181 6182 Set_TD(td->hctd_offsets[i / 2], 6183 Get_TD(td->hctd_offsets[i / 2]) | offset); 6184 toggle = 1; 6185 } 6186 6187 buf = (uint32_t)(buf + temp_pkt_descr->isoc_pkt_length); 6188 temp_pkt_descr++; 6189 } 6190 } 6191 6192 6193 /* 6194 * ohci_insert_td_with_frame_number: 6195 * 6196 * Insert current isochronous TD into the ED's list. with proper 6197 * usb frame number in which this TD can be processed. 6198 */ 6199 static int 6200 ohci_insert_td_with_frame_number( 6201 ohci_state_t *ohcip, 6202 ohci_pipe_private_t *pp, 6203 ohci_trans_wrapper_t *tw, 6204 ohci_td_t *current_td, 6205 ohci_td_t *dummy_td) 6206 { 6207 usb_isoc_req_t *isoc_reqp = 6208 (usb_isoc_req_t *)tw->tw_curr_xfer_reqp; 6209 usb_frame_number_t current_frame_number, start_frame_number; 6210 uint_t ddic, ctrl, isoc_pkts; 6211 ohci_ed_t *ept = pp->pp_ept; 6212 6213 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6214 "ohci_insert_td_with_frame_number:" 6215 "isoc flags 0x%x", isoc_reqp->isoc_attributes); 6216 6217 /* Get the TD ctrl information */ 6218 isoc_pkts = ((Get_TD(current_td->hctd_ctrl) & 6219 HC_ITD_FC) >> HC_ITD_FC_SHIFT) + 1; 6220 6221 /* 6222 * Enter critical, while programming the usb frame number 6223 * and inserting current isochronous TD into the ED's list. 6224 */ 6225 ddic = ddi_enter_critical(); 6226 6227 /* Get the current frame number */ 6228 current_frame_number = ohci_get_current_frame_number(ohcip); 6229 6230 /* Check the given isochronous flags */ 6231 switch (isoc_reqp->isoc_attributes & 6232 (USB_ATTRS_ISOC_START_FRAME | USB_ATTRS_ISOC_XFER_ASAP)) { 6233 case USB_ATTRS_ISOC_START_FRAME: 6234 /* Starting frame number is specified */ 6235 if (pp->pp_flag & OHCI_ISOC_XFER_CONTINUE) { 6236 /* Get the starting usb frame number */ 6237 start_frame_number = pp->pp_next_frame_number; 6238 } else { 6239 /* Check for the Starting usb frame number */ 6240 if ((isoc_reqp->isoc_frame_no == 0) || 6241 ((isoc_reqp->isoc_frame_no + 6242 isoc_reqp->isoc_pkts_count) < 6243 current_frame_number)) { 6244 6245 /* Exit the critical */ 6246 ddi_exit_critical(ddic); 6247 6248 USB_DPRINTF_L2(PRINT_MASK_LISTS, 6249 ohcip->ohci_log_hdl, 6250 "ohci_insert_td_with_frame_number:" 6251 "Invalid starting frame number"); 6252 6253 return (USB_INVALID_START_FRAME); 6254 } 6255 6256 /* Get the starting usb frame number */ 6257 start_frame_number = isoc_reqp->isoc_frame_no; 6258 6259 pp->pp_next_frame_number = 0; 6260 } 6261 break; 6262 case USB_ATTRS_ISOC_XFER_ASAP: 6263 /* ohci has to specify starting frame number */ 6264 if ((pp->pp_next_frame_number) && 6265 (pp->pp_next_frame_number > current_frame_number)) { 6266 /* 6267 * Get the next usb frame number. 6268 */ 6269 start_frame_number = pp->pp_next_frame_number; 6270 } else { 6271 /* 6272 * Add appropriate offset to the current usb 6273 * frame number and use it as a starting frame 6274 * number. 6275 */ 6276 start_frame_number = 6277 current_frame_number + OHCI_FRAME_OFFSET; 6278 } 6279 6280 if (!(pp->pp_flag & OHCI_ISOC_XFER_CONTINUE)) { 6281 isoc_reqp->isoc_frame_no = start_frame_number; 6282 } 6283 break; 6284 default: 6285 /* Exit the critical */ 6286 ddi_exit_critical(ddic); 6287 6288 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6289 "ohci_insert_td_with_frame_number: Either starting " 6290 "frame number or ASAP flags are not set, attrs = 0x%x", 6291 isoc_reqp->isoc_attributes); 6292 6293 return (USB_NO_FRAME_NUMBER); 6294 } 6295 6296 /* Get the TD ctrl information */ 6297 ctrl = Get_TD(current_td->hctd_ctrl) & (~(HC_ITD_SF)); 6298 6299 /* Set the frame number field */ 6300 Set_TD(current_td->hctd_ctrl, ctrl | (start_frame_number & HC_ITD_SF)); 6301 6302 /* 6303 * Add the new dummy to the ED's list. When this occurs, 6304 * the Host Controller will see newly filled in dummy TD. 6305 */ 6306 Set_ED(ept->hced_tailp, (ohci_td_cpu_to_iommu(ohcip, dummy_td))); 6307 6308 /* Exit the critical */ 6309 ddi_exit_critical(ddic); 6310 6311 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6312 "ohci_insert_td_with_frame_number:" 6313 "current frame number 0x%llx start frame number 0x%llx", 6314 current_frame_number, start_frame_number); 6315 6316 /* 6317 * Increment this saved frame number by current number 6318 * of data packets needs to be transfer. 6319 */ 6320 pp->pp_next_frame_number = start_frame_number + isoc_pkts; 6321 6322 /* 6323 * Set OHCI_ISOC_XFER_CONTINUE flag in order to send other 6324 * isochronous packets, part of the current isoch request 6325 * in the subsequent frames. 6326 */ 6327 pp->pp_flag |= OHCI_ISOC_XFER_CONTINUE; 6328 6329 return (USB_SUCCESS); 6330 } 6331 6332 6333 /* 6334 * ohci_insert_td_on_tw: 6335 * 6336 * The transfer wrapper keeps a list of all Transfer Descriptors (TD) that 6337 * are allocated for this transfer. Insert a TD onto this list. The list 6338 * of TD's does not include the dummy TD that is at the end of the list of 6339 * TD's for the endpoint. 6340 */ 6341 static void 6342 ohci_insert_td_on_tw( 6343 ohci_state_t *ohcip, 6344 ohci_trans_wrapper_t *tw, 6345 ohci_td_t *td) 6346 { 6347 /* 6348 * Set the next pointer to NULL because 6349 * this is the last TD on list. 6350 */ 6351 Set_TD(td->hctd_tw_next_td, NULL); 6352 6353 if (tw->tw_hctd_head == NULL) { 6354 ASSERT(tw->tw_hctd_tail == NULL); 6355 tw->tw_hctd_head = td; 6356 tw->tw_hctd_tail = td; 6357 } else { 6358 ohci_td_t *dummy = (ohci_td_t *)tw->tw_hctd_tail; 6359 6360 ASSERT(dummy != NULL); 6361 ASSERT(dummy != td); 6362 ASSERT(Get_TD(td->hctd_state) != HC_TD_DUMMY); 6363 6364 /* Add the td to the end of the list */ 6365 Set_TD(dummy->hctd_tw_next_td, 6366 ohci_td_cpu_to_iommu(ohcip, td)); 6367 6368 tw->tw_hctd_tail = td; 6369 6370 ASSERT(Get_TD(td->hctd_tw_next_td) == NULL); 6371 } 6372 } 6373 6374 6375 /* 6376 * ohci_traverse_tds: 6377 * NOTE: This function is also called from POLLED MODE. 6378 * 6379 * Traverse the list of TD's for an endpoint. Since the endpoint is marked 6380 * as sKipped, the Host Controller (HC) is no longer accessing these TD's. 6381 * Remove all the TD's that are attached to the endpoint. 6382 */ 6383 void 6384 ohci_traverse_tds( 6385 ohci_state_t *ohcip, 6386 usba_pipe_handle_data_t *ph) 6387 { 6388 ohci_trans_wrapper_t *tw; 6389 ohci_ed_t *ept; 6390 ohci_pipe_private_t *pp; 6391 uint32_t addr; 6392 ohci_td_t *tailp, *headp, *next; 6393 6394 pp = (ohci_pipe_private_t *)ph->p_hcd_private; 6395 ept = pp->pp_ept; 6396 6397 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6398 "ohci_traverse_tds: ph = 0x%p ept = 0x%p", 6399 (void *)ph, (void *)ept); 6400 6401 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 6402 6403 addr = Get_ED(ept->hced_headp) & (uint32_t)HC_EPT_TD_HEAD; 6404 6405 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6406 "ohci_traverse_tds: addr (head) = 0x%x", addr); 6407 6408 headp = (ohci_td_t *)(ohci_td_iommu_to_cpu(ohcip, addr)); 6409 6410 addr = Get_ED(ept->hced_tailp) & (uint32_t)HC_EPT_TD_TAIL; 6411 6412 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6413 "ohci_traverse_tds: addr (tail) = 0x%x", addr); 6414 6415 tailp = (ohci_td_t *)(ohci_td_iommu_to_cpu(ohcip, addr)); 6416 6417 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6418 "ohci_traverse_tds: cpu head = 0x%p cpu tail = 0x%p", 6419 (void *)headp, (void *)tailp); 6420 6421 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6422 "ohci_traverse_tds: iommu head = 0x%x iommu tail = 0x%x", 6423 ohci_td_cpu_to_iommu(ohcip, headp), 6424 ohci_td_cpu_to_iommu(ohcip, tailp)); 6425 6426 /* 6427 * Traverse the list of TD's that are currently on the endpoint. 6428 * These TD's have not been processed and will not be processed 6429 * because the endpoint processing is stopped. 6430 */ 6431 while (headp != tailp) { 6432 next = (ohci_td_t *)(ohci_td_iommu_to_cpu(ohcip, 6433 (Get_TD(headp->hctd_next_td) & HC_EPT_TD_TAIL))); 6434 6435 tw = (ohci_trans_wrapper_t *)OHCI_LOOKUP_ID( 6436 (uint32_t)Get_TD(headp->hctd_trans_wrapper)); 6437 6438 /* Stop the the transfer timer */ 6439 ohci_stop_xfer_timer(ohcip, tw, OHCI_REMOVE_XFER_ALWAYS); 6440 6441 ohci_deallocate_td(ohcip, headp); 6442 headp = next; 6443 } 6444 6445 /* Both head and tail pointers must be same */ 6446 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6447 "ohci_traverse_tds: head = 0x%p tail = 0x%p", 6448 (void *)headp, (void *)tailp); 6449 6450 /* Update the pointer in the endpoint descriptor */ 6451 Set_ED(ept->hced_headp, (ohci_td_cpu_to_iommu(ohcip, headp))); 6452 6453 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6454 "ohci_traverse_tds: new head = 0x%x", 6455 (ohci_td_cpu_to_iommu(ohcip, headp))); 6456 6457 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6458 "ohci_traverse_tds: tailp = 0x%x headp = 0x%x", 6459 (Get_ED(ept->hced_tailp) & HC_EPT_TD_TAIL), 6460 (Get_ED(ept->hced_headp) & HC_EPT_TD_HEAD)); 6461 6462 ASSERT((Get_ED(ept->hced_tailp) & HC_EPT_TD_TAIL) == 6463 (Get_ED(ept->hced_headp) & HC_EPT_TD_HEAD)); 6464 } 6465 6466 6467 /* 6468 * ohci_done_list_tds: 6469 * 6470 * There may be TD's on the done list that have not been processed yet. Walk 6471 * through these TD's and mark them as RECLAIM. All the mappings for the TD 6472 * will be torn down, so the interrupt handle is alerted of this fact through 6473 * the RECLAIM flag. 6474 */ 6475 static void 6476 ohci_done_list_tds( 6477 ohci_state_t *ohcip, 6478 usba_pipe_handle_data_t *ph) 6479 { 6480 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 6481 ohci_trans_wrapper_t *head_tw = pp->pp_tw_head; 6482 ohci_trans_wrapper_t *next_tw; 6483 ohci_td_t *head_td, *next_td; 6484 6485 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 6486 6487 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6488 "ohci_done_list_tds:"); 6489 6490 /* Process the transfer wrappers for this pipe */ 6491 next_tw = head_tw; 6492 while (next_tw) { 6493 head_td = (ohci_td_t *)next_tw->tw_hctd_head; 6494 next_td = head_td; 6495 6496 if (head_td) { 6497 /* 6498 * Walk through each TD for this transfer 6499 * wrapper. If a TD still exists, then it 6500 * is currently on the done list. 6501 */ 6502 while (next_td) { 6503 6504 /* To free TD, set TD state to RECLAIM */ 6505 Set_TD(next_td->hctd_state, HC_TD_RECLAIM); 6506 6507 Set_TD(next_td->hctd_trans_wrapper, NULL); 6508 6509 next_td = ohci_td_iommu_to_cpu(ohcip, 6510 Get_TD(next_td->hctd_tw_next_td)); 6511 } 6512 } 6513 6514 /* Stop the the transfer timer */ 6515 ohci_stop_xfer_timer(ohcip, next_tw, OHCI_REMOVE_XFER_ALWAYS); 6516 6517 next_tw = next_tw->tw_next; 6518 } 6519 } 6520 6521 6522 /* 6523 * Remove old_td from tw and update the links. 6524 */ 6525 void 6526 ohci_unlink_td_from_tw( 6527 ohci_state_t *ohcip, 6528 ohci_td_t *old_td, 6529 ohci_trans_wrapper_t *tw) 6530 { 6531 ohci_td_t *next, *head, *tail; 6532 6533 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 6534 "ohci_unlink_td_from_tw: ohcip = 0x%p, old_td = 0x%p, tw = 0x%p", 6535 (void *)ohcip, (void *)old_td, (void *)tw); 6536 6537 if (old_td == NULL || tw == NULL) { 6538 6539 return; 6540 } 6541 6542 head = tw->tw_hctd_head; 6543 tail = tw->tw_hctd_tail; 6544 6545 if (head == NULL) { 6546 6547 return; 6548 } 6549 6550 /* if this old_td is on head */ 6551 if (old_td == head) { 6552 if (old_td == tail) { 6553 tw->tw_hctd_head = NULL; 6554 tw->tw_hctd_tail = NULL; 6555 } else { 6556 tw->tw_hctd_head = ohci_td_iommu_to_cpu(ohcip, 6557 Get_TD(head->hctd_tw_next_td)); 6558 } 6559 6560 return; 6561 } 6562 6563 /* find this old_td's position in the tw */ 6564 next = ohci_td_iommu_to_cpu(ohcip, Get_TD(head->hctd_tw_next_td)); 6565 while (next && (old_td != next)) { 6566 head = next; 6567 next = ohci_td_iommu_to_cpu(ohcip, 6568 Get_TD(next->hctd_tw_next_td)); 6569 } 6570 6571 /* unlink the found old_td from the tw */ 6572 if (old_td == next) { 6573 Set_TD(head->hctd_tw_next_td, Get_TD(next->hctd_tw_next_td)); 6574 if (old_td == tail) { 6575 tw->tw_hctd_tail = head; 6576 } 6577 } 6578 } 6579 6580 6581 /* 6582 * ohci_deallocate_td: 6583 * NOTE: This function is also called from POLLED MODE. 6584 * 6585 * Deallocate a Host Controller's (HC) Transfer Descriptor (TD). 6586 */ 6587 void 6588 ohci_deallocate_td( 6589 ohci_state_t *ohcip, 6590 ohci_td_t *old_td) 6591 { 6592 ohci_trans_wrapper_t *tw; 6593 6594 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 6595 "ohci_deallocate_td: old_td = 0x%p", (void *)old_td); 6596 6597 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 6598 6599 /* 6600 * Obtain the transaction wrapper and tw will be 6601 * NULL for the dummy and for the reclaim TD's. 6602 */ 6603 if ((Get_TD(old_td->hctd_state) == HC_TD_DUMMY) || 6604 (Get_TD(old_td->hctd_state) == HC_TD_RECLAIM)) { 6605 tw = (ohci_trans_wrapper_t *)((uintptr_t) 6606 Get_TD(old_td->hctd_trans_wrapper)); 6607 ASSERT(tw == NULL); 6608 } else { 6609 tw = (ohci_trans_wrapper_t *) 6610 OHCI_LOOKUP_ID((uint32_t) 6611 Get_TD(old_td->hctd_trans_wrapper)); 6612 ASSERT(tw != NULL); 6613 } 6614 6615 /* 6616 * If this TD should be reclaimed, don't try to access its 6617 * transfer wrapper. 6618 */ 6619 if ((Get_TD(old_td->hctd_state) != HC_TD_RECLAIM) && tw) { 6620 6621 ohci_unlink_td_from_tw(ohcip, old_td, tw); 6622 } 6623 6624 bzero((void *)old_td, sizeof (ohci_td_t)); 6625 Set_TD(old_td->hctd_state, HC_TD_FREE); 6626 6627 USB_DPRINTF_L3(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 6628 "ohci_deallocate_td: td 0x%p", (void *)old_td); 6629 } 6630 6631 6632 /* 6633 * ohci_td_cpu_to_iommu: 6634 * NOTE: This function is also called from POLLED MODE. 6635 * 6636 * This function converts for the given Transfer Descriptor (TD) CPU address 6637 * to IO address. 6638 */ 6639 uint32_t 6640 ohci_td_cpu_to_iommu( 6641 ohci_state_t *ohcip, 6642 ohci_td_t *addr) 6643 { 6644 uint32_t td; 6645 6646 td = (uint32_t)ohcip->ohci_td_pool_cookie.dmac_address + 6647 (uint32_t)((uintptr_t)addr - (uintptr_t)(ohcip->ohci_td_pool_addr)); 6648 6649 ASSERT((ohcip->ohci_td_pool_cookie.dmac_address + 6650 (uint32_t) (sizeof (ohci_td_t) * 6651 (addr - ohcip->ohci_td_pool_addr))) == 6652 (ohcip->ohci_td_pool_cookie.dmac_address + 6653 (uint32_t)((uintptr_t)addr - (uintptr_t) 6654 (ohcip->ohci_td_pool_addr)))); 6655 6656 ASSERT(td >= ohcip->ohci_td_pool_cookie.dmac_address); 6657 ASSERT(td <= ohcip->ohci_td_pool_cookie.dmac_address + 6658 sizeof (ohci_td_t) * ohci_td_pool_size); 6659 6660 return (td); 6661 } 6662 6663 6664 /* 6665 * ohci_td_iommu_to_cpu: 6666 * NOTE: This function is also called from POLLED MODE. 6667 * 6668 * This function converts for the given Transfer Descriptor (TD) IO address 6669 * to CPU address. 6670 */ 6671 ohci_td_t * 6672 ohci_td_iommu_to_cpu( 6673 ohci_state_t *ohcip, 6674 uintptr_t addr) 6675 { 6676 ohci_td_t *td; 6677 6678 if (addr == NULL) { 6679 6680 return (NULL); 6681 } 6682 6683 td = (ohci_td_t *)((uintptr_t) 6684 (addr - ohcip->ohci_td_pool_cookie.dmac_address) + 6685 (uintptr_t)ohcip->ohci_td_pool_addr); 6686 6687 ASSERT(td >= ohcip->ohci_td_pool_addr); 6688 ASSERT((uintptr_t)td <= (uintptr_t)ohcip->ohci_td_pool_addr + 6689 (uintptr_t)(sizeof (ohci_td_t) * ohci_td_pool_size)); 6690 6691 return (td); 6692 } 6693 6694 /* 6695 * ohci_allocate_tds_for_tw: 6696 * 6697 * Allocate n Transfer Descriptors (TD) from the TD buffer pool and places it 6698 * into the TW. 6699 * 6700 * Returns USB_NO_RESOURCES if it was not able to allocate all the requested TD 6701 * otherwise USB_SUCCESS. 6702 */ 6703 static int 6704 ohci_allocate_tds_for_tw( 6705 ohci_state_t *ohcip, 6706 ohci_trans_wrapper_t *tw, 6707 size_t td_count) 6708 { 6709 ohci_td_t *td; 6710 uint32_t td_addr; 6711 int i; 6712 int error = USB_SUCCESS; 6713 6714 for (i = 0; i < td_count; i++) { 6715 td = ohci_allocate_td_from_pool(ohcip); 6716 if (td == NULL) { 6717 error = USB_NO_RESOURCES; 6718 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6719 "ohci_allocate_tds_for_tw: " 6720 "Unable to allocate %lu TDs", 6721 td_count); 6722 break; 6723 } 6724 if (tw->tw_hctd_free_list != NULL) { 6725 td_addr = ohci_td_cpu_to_iommu(ohcip, 6726 tw->tw_hctd_free_list); 6727 Set_TD(td->hctd_tw_next_td, td_addr); 6728 } 6729 tw->tw_hctd_free_list = td; 6730 } 6731 6732 return (error); 6733 } 6734 6735 /* 6736 * ohci_allocate_tw_resources: 6737 * 6738 * Allocate a Transaction Wrapper (TW) and n Transfer Descriptors (TD) 6739 * from the TD buffer pool and places it into the TW. It does an all 6740 * or nothing transaction. 6741 * 6742 * Returns NULL if there is insufficient resources otherwise TW. 6743 */ 6744 static ohci_trans_wrapper_t * 6745 ohci_allocate_tw_resources( 6746 ohci_state_t *ohcip, 6747 ohci_pipe_private_t *pp, 6748 size_t tw_length, 6749 usb_flags_t usb_flags, 6750 size_t td_count) 6751 { 6752 ohci_trans_wrapper_t *tw; 6753 6754 tw = ohci_create_transfer_wrapper(ohcip, pp, tw_length, usb_flags); 6755 6756 if (tw == NULL) { 6757 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 6758 "ohci_allocate_tw_resources: Unable to allocate TW"); 6759 } else { 6760 if (ohci_allocate_tds_for_tw(ohcip, tw, td_count) == 6761 USB_SUCCESS) { 6762 tw->tw_num_tds = td_count; 6763 } else { 6764 ohci_deallocate_tw_resources(ohcip, pp, tw); 6765 tw = NULL; 6766 } 6767 } 6768 6769 return (tw); 6770 } 6771 6772 /* 6773 * ohci_free_tw_tds_resources: 6774 * 6775 * Free all allocated resources for Transaction Wrapper (TW). 6776 * Does not free the TW itself. 6777 */ 6778 static void 6779 ohci_free_tw_tds_resources( 6780 ohci_state_t *ohcip, 6781 ohci_trans_wrapper_t *tw) 6782 { 6783 ohci_td_t *td; 6784 ohci_td_t *temp_td; 6785 6786 td = tw->tw_hctd_free_list; 6787 while (td != NULL) { 6788 /* Save the pointer to the next td before destroying it */ 6789 temp_td = ohci_td_iommu_to_cpu(ohcip, 6790 Get_TD(td->hctd_tw_next_td)); 6791 ohci_deallocate_td(ohcip, td); 6792 td = temp_td; 6793 } 6794 tw->tw_hctd_free_list = NULL; 6795 } 6796 6797 6798 /* 6799 * Transfer Wrapper functions 6800 * 6801 * ohci_create_transfer_wrapper: 6802 * 6803 * Create a Transaction Wrapper (TW) for non-isoc transfer types 6804 * and this involves the allocating of DMA resources. 6805 */ 6806 static ohci_trans_wrapper_t * 6807 ohci_create_transfer_wrapper( 6808 ohci_state_t *ohcip, 6809 ohci_pipe_private_t *pp, 6810 size_t length, 6811 uint_t usb_flags) 6812 { 6813 ddi_device_acc_attr_t dev_attr; 6814 int result; 6815 size_t real_length; 6816 ohci_trans_wrapper_t *tw; 6817 ddi_dma_attr_t dma_attr; 6818 int kmem_flag; 6819 int (*dmamem_wait)(caddr_t); 6820 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 6821 6822 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 6823 "ohci_create_transfer_wrapper: length = 0x%lx flags = 0x%x", 6824 length, usb_flags); 6825 6826 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 6827 6828 /* isochronous pipe should not call into this function */ 6829 if ((ph->p_ep.bmAttributes & USB_EP_ATTR_MASK) == 6830 USB_EP_ATTR_ISOCH) { 6831 6832 return (NULL); 6833 } 6834 6835 /* SLEEP flag should not be used in interrupt context */ 6836 if (servicing_interrupt()) { 6837 kmem_flag = KM_NOSLEEP; 6838 dmamem_wait = DDI_DMA_DONTWAIT; 6839 } else { 6840 kmem_flag = KM_SLEEP; 6841 dmamem_wait = DDI_DMA_SLEEP; 6842 } 6843 6844 /* Allocate space for the transfer wrapper */ 6845 tw = kmem_zalloc(sizeof (ohci_trans_wrapper_t), kmem_flag); 6846 6847 if (tw == NULL) { 6848 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 6849 "ohci_create_transfer_wrapper: kmem_zalloc failed"); 6850 6851 return (NULL); 6852 } 6853 6854 /* zero-length packet doesn't need to allocate dma memory */ 6855 if (length == 0) { 6856 6857 goto dmadone; 6858 } 6859 6860 /* allow sg lists for transfer wrapper dma memory */ 6861 bcopy(&ohcip->ohci_dma_attr, &dma_attr, sizeof (ddi_dma_attr_t)); 6862 dma_attr.dma_attr_sgllen = OHCI_DMA_ATTR_TW_SGLLEN; 6863 dma_attr.dma_attr_align = OHCI_DMA_ATTR_ALIGNMENT; 6864 6865 /* Allocate the DMA handle */ 6866 result = ddi_dma_alloc_handle(ohcip->ohci_dip, 6867 &dma_attr, dmamem_wait, 0, &tw->tw_dmahandle); 6868 6869 if (result != DDI_SUCCESS) { 6870 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 6871 "ohci_create_transfer_wrapper: Alloc handle failed"); 6872 6873 kmem_free(tw, sizeof (ohci_trans_wrapper_t)); 6874 6875 return (NULL); 6876 } 6877 6878 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 6879 6880 /* The host controller will be little endian */ 6881 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_BE_ACC; 6882 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 6883 6884 /* Allocate the memory */ 6885 result = ddi_dma_mem_alloc(tw->tw_dmahandle, length, 6886 &dev_attr, DDI_DMA_CONSISTENT, dmamem_wait, NULL, 6887 (caddr_t *)&tw->tw_buf, &real_length, &tw->tw_accesshandle); 6888 6889 if (result != DDI_SUCCESS) { 6890 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 6891 "ohci_create_transfer_wrapper: dma_mem_alloc fail"); 6892 6893 ddi_dma_free_handle(&tw->tw_dmahandle); 6894 kmem_free(tw, sizeof (ohci_trans_wrapper_t)); 6895 6896 return (NULL); 6897 } 6898 6899 ASSERT(real_length >= length); 6900 6901 /* Bind the handle */ 6902 result = ddi_dma_addr_bind_handle(tw->tw_dmahandle, NULL, 6903 (caddr_t)tw->tw_buf, real_length, DDI_DMA_RDWR|DDI_DMA_CONSISTENT, 6904 dmamem_wait, NULL, &tw->tw_cookie, &tw->tw_ncookies); 6905 6906 if (result != DDI_DMA_MAPPED) { 6907 ohci_decode_ddi_dma_addr_bind_handle_result(ohcip, result); 6908 6909 ddi_dma_mem_free(&tw->tw_accesshandle); 6910 ddi_dma_free_handle(&tw->tw_dmahandle); 6911 kmem_free(tw, sizeof (ohci_trans_wrapper_t)); 6912 6913 return (NULL); 6914 } 6915 6916 tw->tw_cookie_idx = 0; 6917 tw->tw_dma_offs = 0; 6918 6919 dmadone: 6920 /* 6921 * Only allow one wrapper to be added at a time. Insert the 6922 * new transaction wrapper into the list for this pipe. 6923 */ 6924 if (pp->pp_tw_head == NULL) { 6925 pp->pp_tw_head = tw; 6926 pp->pp_tw_tail = tw; 6927 } else { 6928 pp->pp_tw_tail->tw_next = tw; 6929 pp->pp_tw_tail = tw; 6930 } 6931 6932 /* Store the transfer length */ 6933 tw->tw_length = length; 6934 6935 /* Store a back pointer to the pipe private structure */ 6936 tw->tw_pipe_private = pp; 6937 6938 /* Store the transfer type - synchronous or asynchronous */ 6939 tw->tw_flags = usb_flags; 6940 6941 /* Get and Store 32bit ID */ 6942 tw->tw_id = OHCI_GET_ID((void *)tw); 6943 6944 ASSERT(tw->tw_id != NULL); 6945 6946 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 6947 "ohci_create_transfer_wrapper: tw = 0x%p, ncookies = %u", 6948 tw, tw->tw_ncookies); 6949 6950 return (tw); 6951 } 6952 6953 6954 /* 6955 * Transfer Wrapper functions 6956 * 6957 * ohci_create_isoc_transfer_wrapper: 6958 * 6959 * Create a Transaction Wrapper (TW) for isoc transfer 6960 * and this involves the allocating of DMA resources. 6961 */ 6962 static ohci_trans_wrapper_t * 6963 ohci_create_isoc_transfer_wrapper( 6964 ohci_state_t *ohcip, 6965 ohci_pipe_private_t *pp, 6966 size_t length, 6967 usb_isoc_pkt_descr_t *descr, 6968 ushort_t pkt_count, 6969 size_t td_count, 6970 uint_t usb_flags) 6971 { 6972 ddi_device_acc_attr_t dev_attr; 6973 int result; 6974 size_t real_length, xfer_size; 6975 uint_t ccount; 6976 ohci_trans_wrapper_t *tw; 6977 ddi_dma_attr_t dma_attr; 6978 int kmem_flag; 6979 uint_t i, j, frame_count, residue; 6980 int (*dmamem_wait)(caddr_t); 6981 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 6982 usb_isoc_pkt_descr_t *isoc_pkt_descr = descr; 6983 6984 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 6985 "ohci_create_isoc_transfer_wrapper: length = 0x%lx flags = 0x%x", 6986 length, usb_flags); 6987 6988 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 6989 6990 /* non-isochronous pipe should not call into this function */ 6991 if ((ph->p_ep.bmAttributes & USB_EP_ATTR_MASK) != 6992 USB_EP_ATTR_ISOCH) { 6993 6994 return (NULL); 6995 } 6996 6997 /* SLEEP flag should not be used in interrupt context */ 6998 if (servicing_interrupt()) { 6999 kmem_flag = KM_NOSLEEP; 7000 dmamem_wait = DDI_DMA_DONTWAIT; 7001 } else { 7002 kmem_flag = KM_SLEEP; 7003 dmamem_wait = DDI_DMA_SLEEP; 7004 } 7005 7006 /* Allocate space for the transfer wrapper */ 7007 tw = kmem_zalloc(sizeof (ohci_trans_wrapper_t), kmem_flag); 7008 7009 if (tw == NULL) { 7010 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 7011 "ohci_create_transfer_wrapper: kmem_zalloc failed"); 7012 7013 return (NULL); 7014 } 7015 7016 /* Allocate space for the isoc buffer handles */ 7017 tw->tw_isoc_strtlen = sizeof (ohci_isoc_buf_t) * td_count; 7018 if ((tw->tw_isoc_bufs = kmem_zalloc(tw->tw_isoc_strtlen, 7019 kmem_flag)) == NULL) { 7020 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 7021 "ohci_create_isoc_transfer_wrapper: kmem_alloc " 7022 "isoc buffer failed"); 7023 kmem_free(tw, sizeof (ohci_trans_wrapper_t)); 7024 7025 return (NULL); 7026 } 7027 7028 /* allow sg lists for transfer wrapper dma memory */ 7029 bcopy(&ohcip->ohci_dma_attr, &dma_attr, sizeof (ddi_dma_attr_t)); 7030 dma_attr.dma_attr_sgllen = OHCI_DMA_ATTR_TD_SGLLEN; 7031 dma_attr.dma_attr_align = OHCI_DMA_ATTR_ALIGNMENT; 7032 7033 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 7034 7035 /* The host controller will be little endian */ 7036 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_BE_ACC; 7037 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 7038 7039 residue = pkt_count % OHCI_ISOC_PKTS_PER_TD; 7040 7041 for (i = 0; i < td_count; i++) { 7042 tw->tw_isoc_bufs[i].index = i; 7043 7044 if ((i == (td_count - 1)) && (residue != 0)) { 7045 frame_count = residue; 7046 } else { 7047 frame_count = OHCI_ISOC_PKTS_PER_TD; 7048 } 7049 7050 /* Allocate the DMA handle */ 7051 result = ddi_dma_alloc_handle(ohcip->ohci_dip, &dma_attr, 7052 dmamem_wait, 0, &tw->tw_isoc_bufs[i].dma_handle); 7053 7054 if (result != DDI_SUCCESS) { 7055 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 7056 "ohci_create_isoc_transfer_wrapper: " 7057 "Alloc handle failed"); 7058 7059 for (j = 0; j < i; j++) { 7060 result = ddi_dma_unbind_handle( 7061 tw->tw_isoc_bufs[j].dma_handle); 7062 ASSERT(result == USB_SUCCESS); 7063 ddi_dma_mem_free(&tw->tw_isoc_bufs[j]. 7064 mem_handle); 7065 ddi_dma_free_handle(&tw->tw_isoc_bufs[j]. 7066 dma_handle); 7067 } 7068 kmem_free(tw->tw_isoc_bufs, tw->tw_isoc_strtlen); 7069 kmem_free(tw, sizeof (ohci_trans_wrapper_t)); 7070 7071 return (NULL); 7072 } 7073 7074 /* Compute the memory length */ 7075 for (xfer_size = 0, j = 0; j < frame_count; j++) { 7076 ASSERT(isoc_pkt_descr != NULL); 7077 xfer_size += isoc_pkt_descr->isoc_pkt_length; 7078 isoc_pkt_descr++; 7079 } 7080 7081 /* Allocate the memory */ 7082 result = ddi_dma_mem_alloc(tw->tw_isoc_bufs[i].dma_handle, 7083 xfer_size, &dev_attr, DDI_DMA_CONSISTENT, dmamem_wait, 7084 NULL, (caddr_t *)&tw->tw_isoc_bufs[i].buf_addr, 7085 &real_length, &tw->tw_isoc_bufs[i].mem_handle); 7086 7087 if (result != DDI_SUCCESS) { 7088 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 7089 "ohci_create_isoc_transfer_wrapper: " 7090 "dma_mem_alloc %d fail", i); 7091 ddi_dma_free_handle(&tw->tw_isoc_bufs[i].dma_handle); 7092 7093 for (j = 0; j < i; j++) { 7094 result = ddi_dma_unbind_handle( 7095 tw->tw_isoc_bufs[j].dma_handle); 7096 ASSERT(result == USB_SUCCESS); 7097 ddi_dma_mem_free(&tw->tw_isoc_bufs[j]. 7098 mem_handle); 7099 ddi_dma_free_handle(&tw->tw_isoc_bufs[j]. 7100 dma_handle); 7101 } 7102 kmem_free(tw->tw_isoc_bufs, tw->tw_isoc_strtlen); 7103 kmem_free(tw, sizeof (ohci_trans_wrapper_t)); 7104 7105 return (NULL); 7106 } 7107 7108 ASSERT(real_length >= xfer_size); 7109 7110 /* Bind the handle */ 7111 result = ddi_dma_addr_bind_handle( 7112 tw->tw_isoc_bufs[i].dma_handle, NULL, 7113 (caddr_t)tw->tw_isoc_bufs[i].buf_addr, real_length, 7114 DDI_DMA_RDWR|DDI_DMA_CONSISTENT, dmamem_wait, NULL, 7115 &tw->tw_isoc_bufs[i].cookie, &ccount); 7116 7117 if ((result == DDI_DMA_MAPPED) && 7118 (ccount <= OHCI_DMA_ATTR_TD_SGLLEN)) { 7119 tw->tw_isoc_bufs[i].length = xfer_size; 7120 tw->tw_isoc_bufs[i].ncookies = ccount; 7121 7122 continue; 7123 } else { 7124 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 7125 "ohci_create_isoc_transfer_wrapper: " 7126 "Bind handle %d failed", i); 7127 if (result == DDI_DMA_MAPPED) { 7128 result = ddi_dma_unbind_handle( 7129 tw->tw_isoc_bufs[i].dma_handle); 7130 ASSERT(result == USB_SUCCESS); 7131 } 7132 ddi_dma_mem_free(&tw->tw_isoc_bufs[i].mem_handle); 7133 ddi_dma_free_handle(&tw->tw_isoc_bufs[i].dma_handle); 7134 7135 for (j = 0; j < i; j++) { 7136 result = ddi_dma_unbind_handle( 7137 tw->tw_isoc_bufs[j].dma_handle); 7138 ASSERT(result == USB_SUCCESS); 7139 ddi_dma_mem_free(&tw->tw_isoc_bufs[j]. 7140 mem_handle); 7141 ddi_dma_free_handle(&tw->tw_isoc_bufs[j]. 7142 dma_handle); 7143 } 7144 kmem_free(tw->tw_isoc_bufs, tw->tw_isoc_strtlen); 7145 kmem_free(tw, sizeof (ohci_trans_wrapper_t)); 7146 7147 return (NULL); 7148 } 7149 } 7150 7151 /* 7152 * Only allow one wrapper to be added at a time. Insert the 7153 * new transaction wrapper into the list for this pipe. 7154 */ 7155 if (pp->pp_tw_head == NULL) { 7156 pp->pp_tw_head = tw; 7157 pp->pp_tw_tail = tw; 7158 } else { 7159 pp->pp_tw_tail->tw_next = tw; 7160 pp->pp_tw_tail = tw; 7161 } 7162 7163 /* Store the transfer length */ 7164 tw->tw_length = length; 7165 7166 /* Store the td numbers */ 7167 tw->tw_ncookies = td_count; 7168 7169 /* Store a back pointer to the pipe private structure */ 7170 tw->tw_pipe_private = pp; 7171 7172 /* Store the transfer type - synchronous or asynchronous */ 7173 tw->tw_flags = usb_flags; 7174 7175 /* Get and Store 32bit ID */ 7176 tw->tw_id = OHCI_GET_ID((void *)tw); 7177 7178 ASSERT(tw->tw_id != NULL); 7179 7180 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 7181 "ohci_create_isoc_transfer_wrapper: tw = 0x%p", tw); 7182 7183 return (tw); 7184 } 7185 7186 7187 /* 7188 * ohci_start_xfer_timer: 7189 * 7190 * Start the timer for the control, bulk and for one time interrupt 7191 * transfers. 7192 */ 7193 /* ARGSUSED */ 7194 static void 7195 ohci_start_xfer_timer( 7196 ohci_state_t *ohcip, 7197 ohci_pipe_private_t *pp, 7198 ohci_trans_wrapper_t *tw) 7199 { 7200 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 7201 "ohci_start_xfer_timer: tw = 0x%p", tw); 7202 7203 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 7204 7205 /* 7206 * The timeout handling is done only for control, bulk and for 7207 * one time Interrupt transfers. 7208 * 7209 * NOTE: If timeout is zero; Assume infinite timeout and don't 7210 * insert this transfer on the timeout list. 7211 */ 7212 if (tw->tw_timeout) { 7213 /* 7214 * Increase timeout value by one second and this extra one 7215 * second is used to halt the endpoint if given transfer 7216 * times out. 7217 */ 7218 tw->tw_timeout++; 7219 7220 /* 7221 * Add this transfer wrapper into the transfer timeout list. 7222 */ 7223 if (ohcip->ohci_timeout_list) { 7224 tw->tw_timeout_next = ohcip->ohci_timeout_list; 7225 } 7226 7227 ohcip->ohci_timeout_list = tw; 7228 ohci_start_timer(ohcip); 7229 } 7230 } 7231 7232 7233 /* 7234 * ohci_stop_xfer_timer: 7235 * 7236 * Start the timer for the control, bulk and for one time interrupt 7237 * transfers. 7238 */ 7239 void 7240 ohci_stop_xfer_timer( 7241 ohci_state_t *ohcip, 7242 ohci_trans_wrapper_t *tw, 7243 uint_t flag) 7244 { 7245 timeout_id_t timer_id; 7246 7247 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 7248 "ohci_stop_xfer_timer: tw = 0x%p", tw); 7249 7250 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 7251 7252 /* 7253 * The timeout handling is done only for control, bulk 7254 * and for one time Interrupt transfers. 7255 */ 7256 if (ohcip->ohci_timeout_list == NULL) { 7257 return; 7258 } 7259 7260 switch (flag) { 7261 case OHCI_REMOVE_XFER_IFLAST: 7262 if (tw->tw_hctd_head != tw->tw_hctd_tail) { 7263 break; 7264 } 7265 /* FALLTHRU */ 7266 case OHCI_REMOVE_XFER_ALWAYS: 7267 ohci_remove_tw_from_timeout_list(ohcip, tw); 7268 7269 if ((ohcip->ohci_timeout_list == NULL) && 7270 (ohcip->ohci_timer_id)) { 7271 7272 timer_id = ohcip->ohci_timer_id; 7273 7274 /* Reset the timer id to zero */ 7275 ohcip->ohci_timer_id = 0; 7276 7277 mutex_exit(&ohcip->ohci_int_mutex); 7278 7279 (void) untimeout(timer_id); 7280 7281 mutex_enter(&ohcip->ohci_int_mutex); 7282 } 7283 break; 7284 default: 7285 break; 7286 } 7287 } 7288 7289 7290 /* 7291 * ohci_xfer_timeout_handler: 7292 * 7293 * Control or bulk transfer timeout handler. 7294 */ 7295 static void 7296 ohci_xfer_timeout_handler(void *arg) 7297 { 7298 ohci_state_t *ohcip = (ohci_state_t *)arg; 7299 ohci_trans_wrapper_t *exp_xfer_list_head = NULL; 7300 ohci_trans_wrapper_t *exp_xfer_list_tail = NULL; 7301 ohci_trans_wrapper_t *tw, *next; 7302 ohci_td_t *td; 7303 usb_flags_t flags; 7304 7305 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 7306 "ohci_xfer_timeout_handler: ohcip = 0x%p", ohcip); 7307 7308 mutex_enter(&ohcip->ohci_int_mutex); 7309 7310 /* Set the required flags */ 7311 flags = OHCI_FLAGS_NOSLEEP | OHCI_FLAGS_DMA_SYNC; 7312 7313 /* 7314 * Check whether still timeout handler is valid. 7315 */ 7316 if (ohcip->ohci_timer_id) { 7317 7318 /* Reset the timer id to zero */ 7319 ohcip->ohci_timer_id = 0; 7320 } else { 7321 mutex_exit(&ohcip->ohci_int_mutex); 7322 7323 return; 7324 } 7325 7326 /* Get the transfer timeout list head */ 7327 tw = ohcip->ohci_timeout_list; 7328 7329 /* 7330 * Process ohci timeout list and look whether the timer 7331 * has expired for any transfers. Create a temporary list 7332 * of expired transfers and process them later. 7333 */ 7334 while (tw) { 7335 /* Get the transfer on the timeout list */ 7336 next = tw->tw_timeout_next; 7337 7338 tw->tw_timeout--; 7339 7340 /* 7341 * Set the sKip bit to stop all transactions on 7342 * this pipe 7343 */ 7344 if (tw->tw_timeout == 1) { 7345 ohci_modify_sKip_bit(ohcip, 7346 tw->tw_pipe_private, SET_sKip, flags); 7347 7348 /* Reset dma sync flag */ 7349 flags &= ~OHCI_FLAGS_DMA_SYNC; 7350 } 7351 7352 /* Remove tw from the timeout list */ 7353 if (tw->tw_timeout <= 0) { 7354 7355 ohci_remove_tw_from_timeout_list(ohcip, tw); 7356 7357 /* Add tw to the end of expire list */ 7358 if (exp_xfer_list_head) { 7359 exp_xfer_list_tail->tw_timeout_next = tw; 7360 } else { 7361 exp_xfer_list_head = tw; 7362 } 7363 exp_xfer_list_tail = tw; 7364 tw->tw_timeout_next = NULL; 7365 } 7366 7367 tw = next; 7368 } 7369 7370 /* Get the expired transfer timeout list head */ 7371 tw = exp_xfer_list_head; 7372 7373 if (tw && (flags & OHCI_FLAGS_DMA_SYNC)) { 7374 /* Sync ED and TD pool */ 7375 Sync_ED_TD_Pool(ohcip); 7376 } 7377 7378 /* 7379 * Process the expired transfers by notifing the corrsponding 7380 * client driver through the exception callback. 7381 */ 7382 while (tw) { 7383 /* Get the transfer on the expired transfer timeout list */ 7384 next = tw->tw_timeout_next; 7385 7386 td = tw->tw_hctd_head; 7387 7388 while (td) { 7389 /* Set TD state to TIMEOUT */ 7390 Set_TD(td->hctd_state, HC_TD_TIMEOUT); 7391 7392 /* Get the next TD from the wrapper */ 7393 td = ohci_td_iommu_to_cpu(ohcip, 7394 Get_TD(td->hctd_tw_next_td)); 7395 } 7396 7397 ohci_handle_error(ohcip, tw->tw_hctd_head, USB_CR_TIMEOUT); 7398 7399 tw = next; 7400 } 7401 7402 ohci_start_timer(ohcip); 7403 mutex_exit(&ohcip->ohci_int_mutex); 7404 } 7405 7406 7407 /* 7408 * ohci_remove_tw_from_timeout_list: 7409 * 7410 * Remove Control or bulk transfer from the timeout list. 7411 */ 7412 static void 7413 ohci_remove_tw_from_timeout_list( 7414 ohci_state_t *ohcip, 7415 ohci_trans_wrapper_t *tw) 7416 { 7417 ohci_trans_wrapper_t *prev, *next; 7418 7419 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 7420 "ohci_remove_tw_from_timeout_list: tw = 0x%p", tw); 7421 7422 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 7423 7424 if (ohcip->ohci_timeout_list == tw) { 7425 ohcip->ohci_timeout_list = tw->tw_timeout_next; 7426 } else { 7427 prev = ohcip->ohci_timeout_list; 7428 next = prev->tw_timeout_next; 7429 7430 while (next && (next != tw)) { 7431 prev = next; 7432 next = next->tw_timeout_next; 7433 } 7434 7435 if (next == tw) { 7436 prev->tw_timeout_next = next->tw_timeout_next; 7437 } 7438 } 7439 7440 /* Reset the xfer timeout */ 7441 tw->tw_timeout_next = NULL; 7442 } 7443 7444 7445 /* 7446 * ohci_start_timer: 7447 * 7448 * Start the ohci timer 7449 */ 7450 static void 7451 ohci_start_timer(ohci_state_t *ohcip) 7452 { 7453 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 7454 "ohci_start_timer: ohcip = 0x%p", ohcip); 7455 7456 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 7457 7458 /* 7459 * Start the global timer only if currently timer is not 7460 * running and if there are any transfers on the timeout 7461 * list. This timer will be per USB Host Controller. 7462 */ 7463 if ((!ohcip->ohci_timer_id) && (ohcip->ohci_timeout_list)) { 7464 ohcip->ohci_timer_id = timeout(ohci_xfer_timeout_handler, 7465 (void *)ohcip, drv_usectohz(1000000)); 7466 } 7467 } 7468 7469 7470 /* 7471 * ohci_deallocate_tw_resources: 7472 * NOTE: This function is also called from POLLED MODE. 7473 * 7474 * Deallocate of a Transaction Wrapper (TW) and this involves the freeing of 7475 * of DMA resources. 7476 */ 7477 void 7478 ohci_deallocate_tw_resources( 7479 ohci_state_t *ohcip, 7480 ohci_pipe_private_t *pp, 7481 ohci_trans_wrapper_t *tw) 7482 { 7483 ohci_trans_wrapper_t *prev, *next; 7484 7485 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 7486 "ohci_deallocate_tw_resources: tw = 0x%p", tw); 7487 7488 /* 7489 * If the transfer wrapper has no Host Controller (HC) 7490 * Transfer Descriptors (TD) associated with it, then 7491 * remove the transfer wrapper. 7492 */ 7493 if (tw->tw_hctd_head) { 7494 ASSERT(tw->tw_hctd_tail != NULL); 7495 7496 return; 7497 } 7498 7499 ASSERT(tw->tw_hctd_tail == NULL); 7500 7501 /* Make sure we return all the unused td's to the pool as well */ 7502 ohci_free_tw_tds_resources(ohcip, tw); 7503 7504 /* 7505 * If pp->pp_tw_head and pp->pp_tw_tail are pointing to 7506 * given TW then set the head and tail equal to NULL. 7507 * Otherwise search for this TW in the linked TW's list 7508 * and then remove this TW from the list. 7509 */ 7510 if (pp->pp_tw_head == tw) { 7511 if (pp->pp_tw_tail == tw) { 7512 pp->pp_tw_head = NULL; 7513 pp->pp_tw_tail = NULL; 7514 } else { 7515 pp->pp_tw_head = tw->tw_next; 7516 } 7517 } else { 7518 prev = pp->pp_tw_head; 7519 next = prev->tw_next; 7520 7521 while (next && (next != tw)) { 7522 prev = next; 7523 next = next->tw_next; 7524 } 7525 7526 if (next == tw) { 7527 prev->tw_next = next->tw_next; 7528 7529 if (pp->pp_tw_tail == tw) { 7530 pp->pp_tw_tail = prev; 7531 } 7532 } 7533 } 7534 7535 ohci_free_tw(ohcip, tw); 7536 } 7537 7538 7539 /* 7540 * ohci_free_dma_resources: 7541 * 7542 * Free dma resources of a Transfer Wrapper (TW) and also free the TW. 7543 */ 7544 static void 7545 ohci_free_dma_resources( 7546 ohci_state_t *ohcip, 7547 usba_pipe_handle_data_t *ph) 7548 { 7549 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 7550 ohci_trans_wrapper_t *head_tw = pp->pp_tw_head; 7551 ohci_trans_wrapper_t *next_tw, *tw; 7552 7553 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 7554 "ohci_free_dma_resources: ph = 0x%p", (void *)ph); 7555 7556 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 7557 7558 /* Process the Transfer Wrappers */ 7559 next_tw = head_tw; 7560 while (next_tw) { 7561 tw = next_tw; 7562 next_tw = tw->tw_next; 7563 7564 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 7565 "ohci_free_dma_resources: Free TW = 0x%p", (void *)tw); 7566 7567 ohci_free_tw(ohcip, tw); 7568 } 7569 7570 /* Adjust the head and tail pointers */ 7571 pp->pp_tw_head = NULL; 7572 pp->pp_tw_tail = NULL; 7573 } 7574 7575 7576 /* 7577 * ohci_free_tw: 7578 * 7579 * Free the Transfer Wrapper (TW). 7580 */ 7581 static void 7582 ohci_free_tw( 7583 ohci_state_t *ohcip, 7584 ohci_trans_wrapper_t *tw) 7585 { 7586 int rval, i; 7587 7588 USB_DPRINTF_L4(PRINT_MASK_ALLOC, ohcip->ohci_log_hdl, 7589 "ohci_free_tw: tw = 0x%p", tw); 7590 7591 ASSERT(tw != NULL); 7592 ASSERT(tw->tw_id != NULL); 7593 7594 /* Free 32bit ID */ 7595 OHCI_FREE_ID((uint32_t)tw->tw_id); 7596 7597 if (tw->tw_isoc_strtlen > 0) { 7598 ASSERT(tw->tw_isoc_bufs != NULL); 7599 for (i = 0; i < tw->tw_ncookies; i++) { 7600 if (tw->tw_isoc_bufs[i].ncookies > 0) { 7601 rval = ddi_dma_unbind_handle( 7602 tw->tw_isoc_bufs[i].dma_handle); 7603 ASSERT(rval == USB_SUCCESS); 7604 } 7605 ddi_dma_mem_free(&tw->tw_isoc_bufs[i].mem_handle); 7606 ddi_dma_free_handle(&tw->tw_isoc_bufs[i].dma_handle); 7607 } 7608 kmem_free(tw->tw_isoc_bufs, tw->tw_isoc_strtlen); 7609 } else if (tw->tw_dmahandle != NULL) { 7610 if (tw->tw_ncookies > 0) { 7611 rval = ddi_dma_unbind_handle(tw->tw_dmahandle); 7612 ASSERT(rval == DDI_SUCCESS); 7613 } 7614 ddi_dma_mem_free(&tw->tw_accesshandle); 7615 ddi_dma_free_handle(&tw->tw_dmahandle); 7616 } 7617 7618 /* Free transfer wrapper */ 7619 kmem_free(tw, sizeof (ohci_trans_wrapper_t)); 7620 } 7621 7622 7623 /* 7624 * Interrupt Handling functions 7625 */ 7626 7627 /* 7628 * ohci_intr: 7629 * 7630 * OpenHCI (OHCI) interrupt handling routine. 7631 */ 7632 static uint_t 7633 ohci_intr(caddr_t arg1, caddr_t arg2) 7634 { 7635 ohci_state_t *ohcip = (ohci_state_t *)arg1; 7636 uint_t intr; 7637 ohci_td_t *done_head = NULL; 7638 ohci_save_intr_sts_t *ohci_intr_sts = &ohcip->ohci_save_intr_sts; 7639 7640 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7641 "ohci_intr: Interrupt occurred, arg1 0x%p arg2 0x%p", arg1, arg2); 7642 7643 mutex_enter(&ohcip->ohci_int_mutex); 7644 7645 /* Any interrupt is not handled for the suspended device. */ 7646 if (ohcip->ohci_hc_soft_state == OHCI_CTLR_SUSPEND_STATE) { 7647 mutex_exit(&ohcip->ohci_int_mutex); 7648 7649 return (DDI_INTR_UNCLAIMED); 7650 } 7651 7652 /* 7653 * Suppose if we switched to the polled mode from the normal 7654 * mode when interrupt handler is executing then we need to 7655 * save the interrupt status information in the polled mode 7656 * to avoid race conditions. The following flag will be set 7657 * and reset on entering & exiting of ohci interrupt handler 7658 * respectively. This flag will be used in the polled mode 7659 * to check whether the interrupt handler was running when we 7660 * switched to the polled mode from the normal mode. 7661 */ 7662 ohci_intr_sts->ohci_intr_flag = OHCI_INTR_HANDLING; 7663 7664 /* Temporarily turn off interrupts */ 7665 Set_OpReg(hcr_intr_disable, HCR_INTR_MIE); 7666 7667 /* 7668 * Handle any missed ohci interrupt especially WriteDoneHead 7669 * and SOF interrupts because of previous polled mode switch. 7670 */ 7671 ohci_handle_missed_intr(ohcip); 7672 7673 /* 7674 * Now process the actual ohci interrupt events that caused 7675 * invocation of this ohci interrupt handler. 7676 */ 7677 7678 /* 7679 * Updating the WriteDoneHead interrupt: 7680 * 7681 * (a) Host Controller 7682 * 7683 * - First Host controller (HC) checks whether WDH bit 7684 * in the interrupt status register is cleared. 7685 * 7686 * - If WDH bit is cleared then HC writes new done head 7687 * list information into the HCCA done head field. 7688 * 7689 * - Set WDH bit in the interrupt status register. 7690 * 7691 * (b) Host Controller Driver (HCD) 7692 * 7693 * - First read the interrupt status register. The HCCA 7694 * done head and WDH bit may be set or may not be set 7695 * while reading the interrupt status register. 7696 * 7697 * - Read the HCCA done head list. By this time may be 7698 * HC has updated HCCA done head and WDH bit in ohci 7699 * interrupt status register. 7700 * 7701 * - If done head is non-null and if WDH bit is not set 7702 * then Host Controller has updated HCCA done head & 7703 * WDH bit in the interrupt stats register in between 7704 * reading the interrupt status register & HCCA done 7705 * head. In that case, definitely WDH bit will be set 7706 * in the interrupt status register & driver can take 7707 * it for granted. 7708 * 7709 * Now read the Interrupt Status & Interrupt enable register 7710 * to determine the exact interrupt events. 7711 */ 7712 intr = ohci_intr_sts->ohci_curr_intr_sts = 7713 (Get_OpReg(hcr_intr_status) & Get_OpReg(hcr_intr_enable)); 7714 7715 if (ohcip->ohci_hccap) { 7716 /* Sync HCCA area */ 7717 Sync_HCCA(ohcip); 7718 7719 /* Read and Save the HCCA DoneHead value */ 7720 done_head = ohci_intr_sts->ohci_curr_done_lst = 7721 (ohci_td_t *)(uintptr_t) 7722 (Get_HCCA(ohcip->ohci_hccap->HccaDoneHead) & 7723 HCCA_DONE_HEAD_MASK); 7724 7725 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7726 "ohci_intr: Done head! 0x%p", (void *)done_head); 7727 } 7728 7729 /* Update kstat values */ 7730 ohci_do_intrs_stats(ohcip, intr); 7731 7732 /* 7733 * Look at the HccaDoneHead, if it is a non-zero valid address, 7734 * a done list update interrupt is indicated. Otherwise, this 7735 * intr bit is cleared. 7736 */ 7737 if (ohci_check_done_head(ohcip, done_head) == USB_SUCCESS) { 7738 7739 /* Set the WriteDoneHead bit in the interrupt events */ 7740 intr |= HCR_INTR_WDH; 7741 } else { 7742 7743 /* Clear the WriteDoneHead bit */ 7744 intr &= ~HCR_INTR_WDH; 7745 } 7746 7747 /* 7748 * We could have gotten a spurious interrupts. If so, do not 7749 * claim it. This is quite possible on some architectures 7750 * where more than one PCI slots share the IRQs. If so, the 7751 * associated driver's interrupt routine may get called even 7752 * if the interrupt is not meant for them. 7753 * 7754 * By unclaiming the interrupt, the other driver gets chance 7755 * to service its interrupt. 7756 */ 7757 if (!intr) { 7758 7759 /* Reset the interrupt handler flag */ 7760 ohci_intr_sts->ohci_intr_flag &= ~OHCI_INTR_HANDLING; 7761 7762 Set_OpReg(hcr_intr_enable, HCR_INTR_MIE); 7763 mutex_exit(&ohcip->ohci_int_mutex); 7764 return (DDI_INTR_UNCLAIMED); 7765 } 7766 7767 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7768 "Interrupt status 0x%x", intr); 7769 7770 /* 7771 * Check for Frame Number Overflow. 7772 */ 7773 if (intr & HCR_INTR_FNO) { 7774 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7775 "ohci_intr: Frame Number Overflow"); 7776 7777 ohci_handle_frame_number_overflow(ohcip); 7778 } 7779 7780 if (intr & HCR_INTR_SOF) { 7781 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7782 "ohci_intr: Start of Frame"); 7783 7784 /* Set ohci_sof_flag indicating SOF interrupt occurred */ 7785 ohcip->ohci_sof_flag = B_TRUE; 7786 7787 /* Disabel SOF interrupt */ 7788 Set_OpReg(hcr_intr_disable, HCR_INTR_SOF); 7789 7790 /* 7791 * Call cv_broadcast on every SOF interrupt to wakeup 7792 * all the threads that are waiting the SOF. Calling 7793 * cv_broadcast on every SOF has no effect even if no 7794 * threads are waiting for the SOF. 7795 */ 7796 cv_broadcast(&ohcip->ohci_SOF_cv); 7797 } 7798 7799 if (intr & HCR_INTR_SO) { 7800 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7801 "ohci_intr: Schedule overrun"); 7802 7803 ohcip->ohci_so_error++; 7804 } 7805 7806 if ((intr & HCR_INTR_WDH) && (done_head)) { 7807 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7808 "ohci_intr: Done Head"); 7809 7810 /* 7811 * Currently if we are processing one WriteDoneHead 7812 * interrupt and also if we switched to the polled 7813 * mode at least once during this time, then there 7814 * may be chance that Host Controller generates one 7815 * more Write DoneHead or Start of Frame interrupts 7816 * for the normal since the polled code clears WDH & 7817 * SOF interrupt bits before returning to the normal 7818 * mode. Under this condition, we must not clear the 7819 * HCCA done head field & also we must not clear WDH 7820 * interrupt bit in the interrupt status register. 7821 */ 7822 if (done_head == (ohci_td_t *)(uintptr_t) 7823 (Get_HCCA(ohcip->ohci_hccap->HccaDoneHead) & 7824 HCCA_DONE_HEAD_MASK)) { 7825 7826 /* Reset the done head to NULL */ 7827 Set_HCCA(ohcip->ohci_hccap->HccaDoneHead, NULL); 7828 } else { 7829 intr &= ~HCR_INTR_WDH; 7830 } 7831 7832 /* Clear the current done head field */ 7833 ohci_intr_sts->ohci_curr_done_lst = NULL; 7834 7835 ohci_traverse_done_list(ohcip, done_head); 7836 } 7837 7838 /* Process endpoint reclaimation list */ 7839 if (ohcip->ohci_reclaim_list) { 7840 ohci_handle_endpoint_reclaimation(ohcip); 7841 } 7842 7843 if (intr & HCR_INTR_RD) { 7844 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7845 "ohci_intr: Resume Detected"); 7846 } 7847 7848 if (intr & HCR_INTR_RHSC) { 7849 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7850 "ohci_intr: Root hub status change"); 7851 } 7852 7853 if (intr & HCR_INTR_OC) { 7854 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7855 "ohci_intr: Change ownership"); 7856 7857 } 7858 7859 if (intr & HCR_INTR_UE) { 7860 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7861 "ohci_intr: Unrecoverable error"); 7862 7863 ohci_handle_ue(ohcip); 7864 } 7865 7866 /* Acknowledge the interrupt */ 7867 Set_OpReg(hcr_intr_status, intr); 7868 7869 /* Clear the current interrupt event field */ 7870 ohci_intr_sts->ohci_curr_intr_sts = 0; 7871 7872 /* 7873 * Reset the following flag indicating exiting the interrupt 7874 * handler and this flag will be used in the polled mode to 7875 * do some extra processing. 7876 */ 7877 ohci_intr_sts->ohci_intr_flag &= ~OHCI_INTR_HANDLING; 7878 7879 Set_OpReg(hcr_intr_enable, HCR_INTR_MIE); 7880 7881 /* 7882 * Read interrupt status register to make sure that any PIO 7883 * store to clear the ISR has made it on the PCI bus before 7884 * returning from its interrupt handler. 7885 */ 7886 (void) Get_OpReg(hcr_intr_status); 7887 7888 mutex_exit(&ohcip->ohci_int_mutex); 7889 7890 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7891 "Interrupt handling completed"); 7892 7893 return (DDI_INTR_CLAIMED); 7894 } 7895 7896 /* 7897 * Check whether done_head is a valid td point address. 7898 * It should be non-zero, 16-byte aligned, and fall in ohci_td_pool. 7899 */ 7900 static int 7901 ohci_check_done_head(ohci_state_t *ohcip, ohci_td_t *done_head) 7902 { 7903 uintptr_t lower, upper, headp; 7904 lower = ohcip->ohci_td_pool_cookie.dmac_address; 7905 upper = lower + ohcip->ohci_td_pool_cookie.dmac_size; 7906 headp = (uintptr_t)done_head; 7907 7908 if (headp && !(headp & ~HCCA_DONE_HEAD_MASK) && 7909 (headp >= lower) && (headp < upper)) { 7910 7911 return (USB_SUCCESS); 7912 } else { 7913 7914 return (USB_FAILURE); 7915 } 7916 } 7917 7918 /* 7919 * ohci_handle_missed_intr: 7920 * 7921 * Handle any ohci missed interrupts because of polled mode switch. 7922 */ 7923 static void 7924 ohci_handle_missed_intr(ohci_state_t *ohcip) 7925 { 7926 ohci_save_intr_sts_t *ohci_intr_sts = 7927 &ohcip->ohci_save_intr_sts; 7928 ohci_td_t *done_head; 7929 uint_t intr; 7930 7931 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 7932 7933 /* 7934 * Check whether we have missed any ohci interrupts because 7935 * of the polled mode switch during previous ohci interrupt 7936 * handler execution. Only Write Done Head & SOF interrupts 7937 * saved in the polled mode. First process these interrupts 7938 * before processing actual interrupts that caused invocation 7939 * of ohci interrupt handler. 7940 */ 7941 if (!ohci_intr_sts->ohci_missed_intr_sts) { 7942 /* No interrupts are missed, simply return */ 7943 7944 return; 7945 } 7946 7947 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 7948 "ohci_handle_missed_intr: Handle ohci missed interrupts"); 7949 7950 /* 7951 * The functionality and importance of critical code section 7952 * in the normal mode ohci interrupt handler & its usage in 7953 * the polled mode is explained below. 7954 * 7955 * (a) Normal mode: 7956 * 7957 * - Set the flag indicating that processing critical 7958 * code in ohci interrupt handler. 7959 * 7960 * - Process the missed ohci interrupts by copying the 7961 * miised interrupt events and done head list fields 7962 * information to the critical interrupt event & done 7963 * list fields. 7964 * 7965 * - Reset the missed ohci interrupt events & done head 7966 * list fields so that the new missed interrupt event 7967 * and done head list information can be saved. 7968 * 7969 * - All above steps will be executed with in critical 7970 * section of the interrupt handler.Then ohci missed 7971 * interrupt handler will be called to service missed 7972 * ohci interrupts. 7973 * 7974 * (b) Polled mode: 7975 * 7976 * - On entering the polled code,it checks for critical 7977 * section code execution within the normal mode ohci 7978 * interrupt handler. 7979 * 7980 * - If the critical section code is executing in normal 7981 * mode ohci interrupt handler and if copying of ohci 7982 * missed interrupt events & done head list fields to 7983 * the critical fields is finished then save the "any 7984 * missed interrupt events & done head list" because 7985 * of current polled mode switch into "critical missed 7986 * interrupt events & done list fields" instead actual 7987 * missed events and done list fields. 7988 * 7989 * - Otherwise save "any missed interrupt events & done 7990 * list" because of this current polled mode switch 7991 * in the actual missed interrupt events & done head 7992 * list fields. 7993 */ 7994 7995 /* 7996 * Set flag indicating that interrupt handler is processing 7997 * critical interrupt code, so that polled mode code checks 7998 * for this condition & will do extra processing as explained 7999 * above in order to aviod the race conditions. 8000 */ 8001 ohci_intr_sts->ohci_intr_flag |= OHCI_INTR_CRITICAL; 8002 ohci_intr_sts->ohci_critical_intr_sts |= 8003 ohci_intr_sts->ohci_missed_intr_sts; 8004 8005 if (ohci_intr_sts->ohci_missed_done_lst) { 8006 8007 ohci_intr_sts->ohci_critical_done_lst = 8008 ohci_intr_sts->ohci_missed_done_lst; 8009 } 8010 8011 ohci_intr_sts->ohci_missed_intr_sts = 0; 8012 ohci_intr_sts->ohci_missed_done_lst = NULL; 8013 ohci_intr_sts->ohci_intr_flag &= ~OHCI_INTR_CRITICAL; 8014 8015 intr = ohci_intr_sts->ohci_critical_intr_sts; 8016 done_head = ohci_intr_sts->ohci_critical_done_lst; 8017 8018 if (intr & HCR_INTR_SOF) { 8019 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8020 "ohci_handle_missed_intr: Start of Frame"); 8021 8022 /* 8023 * Call cv_broadcast on every SOF interrupt to wakeup 8024 * all the threads that are waiting the SOF. Calling 8025 * cv_broadcast on every SOF has no effect even if no 8026 * threads are waiting for the SOF. 8027 */ 8028 cv_broadcast(&ohcip->ohci_SOF_cv); 8029 } 8030 8031 if ((intr & HCR_INTR_WDH) && (done_head)) { 8032 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8033 "ohci_handle_missed_intr: Done Head"); 8034 8035 /* Clear the critical done head field */ 8036 ohci_intr_sts->ohci_critical_done_lst = NULL; 8037 8038 ohci_traverse_done_list(ohcip, done_head); 8039 } 8040 8041 /* Clear the critical interrupt event field */ 8042 ohci_intr_sts->ohci_critical_intr_sts = 0; 8043 } 8044 8045 8046 /* 8047 * ohci_handle_ue: 8048 * 8049 * Handling of Unrecoverable Error interrupt (UE). 8050 */ 8051 static void 8052 ohci_handle_ue(ohci_state_t *ohcip) 8053 { 8054 usb_frame_number_t before_frame_number, after_frame_number; 8055 8056 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8057 8058 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8059 "ohci_handle_ue: Handling of UE interrupt"); 8060 8061 /* 8062 * First check whether current UE error occured due to USB or 8063 * due to some other subsystem. This can be verified by reading 8064 * usb frame numbers before & after a delay of few milliseconds. 8065 * If usb frame number read after delay is greater than the one 8066 * read before delay, then, USB subsystem is fine. In this case, 8067 * disable UE error interrupt and return without shutdowning the 8068 * USB subsystem. 8069 * 8070 * Otherwise, if usb frame number read after delay is less than 8071 * or equal to one read before the delay, then, current UE error 8072 * occured from USB susbsystem. In this case,go ahead with actual 8073 * UE error recovery procedure. 8074 * 8075 * Get the current usb frame number before waiting for few 8076 * milliseconds. 8077 */ 8078 before_frame_number = ohci_get_current_frame_number(ohcip); 8079 8080 /* Wait for few milliseconds */ 8081 drv_usecwait(OHCI_TIMEWAIT); 8082 8083 /* 8084 * Get the current usb frame number after waiting for 8085 * milliseconds. 8086 */ 8087 after_frame_number = ohci_get_current_frame_number(ohcip); 8088 8089 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8090 "ohci_handle_ue: Before Frm No 0x%llx After Frm No 0x%llx", 8091 before_frame_number, after_frame_number); 8092 8093 if (after_frame_number > before_frame_number) { 8094 8095 /* Disable UE interrupt */ 8096 Set_OpReg(hcr_intr_disable, HCR_INTR_UE); 8097 8098 return; 8099 } 8100 8101 /* 8102 * This UE is due to USB hardware error. Reset ohci controller 8103 * and reprogram to bring it back to functional state. 8104 */ 8105 if ((ohci_do_soft_reset(ohcip)) != USB_SUCCESS) { 8106 USB_DPRINTF_L0(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8107 "Unrecoverable USB Hardware Error"); 8108 8109 /* Disable UE interrupt */ 8110 Set_OpReg(hcr_intr_disable, HCR_INTR_UE); 8111 8112 /* Set host controller soft state to error */ 8113 ohcip->ohci_hc_soft_state = OHCI_CTLR_ERROR_STATE; 8114 } 8115 } 8116 8117 8118 /* 8119 * ohci_handle_frame_number_overflow: 8120 * 8121 * Update software based usb frame number part on every frame number 8122 * overflow interrupt. 8123 * 8124 * NOTE: This function is also called from POLLED MODE. 8125 * 8126 * Refer ohci spec 1.0a, section 5.3, page 81 for more details. 8127 */ 8128 void 8129 ohci_handle_frame_number_overflow(ohci_state_t *ohcip) 8130 { 8131 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8132 "ohci_handle_frame_number_overflow:"); 8133 8134 ohcip->ohci_fno += (0x10000 - 8135 (((Get_HCCA(ohcip->ohci_hccap->HccaFrameNo) & 8136 0xFFFF) ^ ohcip->ohci_fno) & 0x8000)); 8137 8138 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8139 "ohci_handle_frame_number_overflow:" 8140 "Frame Number Higher Part 0x%llx\n", ohcip->ohci_fno); 8141 } 8142 8143 8144 /* 8145 * ohci_handle_endpoint_reclaimation: 8146 * 8147 * Reclamation of Host Controller (HC) Endpoint Descriptors (ED). 8148 */ 8149 static void 8150 ohci_handle_endpoint_reclaimation(ohci_state_t *ohcip) 8151 { 8152 usb_frame_number_t current_frame_number; 8153 usb_frame_number_t endpoint_frame_number; 8154 ohci_ed_t *reclaim_ed; 8155 8156 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8157 "ohci_handle_endpoint_reclaimation:"); 8158 8159 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8160 8161 current_frame_number = ohci_get_current_frame_number(ohcip); 8162 8163 /* 8164 * Deallocate all Endpoint Descriptors (ED) which are on the 8165 * reclaimation list. These ED's are already removed from the 8166 * interrupt lattice tree. 8167 */ 8168 while (ohcip->ohci_reclaim_list) { 8169 reclaim_ed = ohcip->ohci_reclaim_list; 8170 8171 endpoint_frame_number = (usb_frame_number_t)(uintptr_t) 8172 (OHCI_LOOKUP_ID(Get_ED(reclaim_ed->hced_reclaim_frame))); 8173 8174 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8175 "ohci_handle_endpoint_reclaimation:" 8176 "current frame number 0x%llx endpoint frame number 0x%llx", 8177 current_frame_number, endpoint_frame_number); 8178 8179 /* 8180 * Deallocate current endpoint only if endpoint's usb frame 8181 * number is less than or equal to current usb frame number. 8182 * 8183 * If endpoint's usb frame number is greater than the current 8184 * usb frame number, ignore rest of the endpoints in the list 8185 * since rest of the endpoints are inserted into the reclaim 8186 * list later than the current reclaim endpoint. 8187 */ 8188 if (endpoint_frame_number > current_frame_number) { 8189 break; 8190 } 8191 8192 /* Get the next endpoint from the rec. list */ 8193 ohcip->ohci_reclaim_list = ohci_ed_iommu_to_cpu(ohcip, 8194 Get_ED(reclaim_ed->hced_reclaim_next)); 8195 8196 /* Free 32bit ID */ 8197 OHCI_FREE_ID((uint32_t)Get_ED(reclaim_ed->hced_reclaim_frame)); 8198 8199 /* Deallocate the endpoint */ 8200 ohci_deallocate_ed(ohcip, reclaim_ed); 8201 } 8202 } 8203 8204 8205 /* 8206 * ohci_traverse_done_list: 8207 */ 8208 static void 8209 ohci_traverse_done_list( 8210 ohci_state_t *ohcip, 8211 ohci_td_t *head_done_list) 8212 { 8213 uint_t state; /* TD state */ 8214 ohci_td_t *td, *old_td; /* TD pointers */ 8215 usb_cr_t error; /* Error from TD */ 8216 ohci_trans_wrapper_t *tw = NULL; /* Transfer wrapper */ 8217 ohci_pipe_private_t *pp = NULL; /* Pipe private field */ 8218 8219 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8220 "ohci_traverse_done_list:"); 8221 8222 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8223 8224 /* Sync ED and TD pool */ 8225 Sync_ED_TD_Pool(ohcip); 8226 8227 /* Reverse the done list */ 8228 td = ohci_reverse_done_list(ohcip, head_done_list); 8229 8230 /* Traverse the list of transfer descriptors */ 8231 while (td) { 8232 /* Check for TD state */ 8233 state = Get_TD(td->hctd_state); 8234 8235 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8236 "ohci_traverse_done_list:\n\t" 8237 "td = 0x%p state = 0x%x", (void *)td, state); 8238 8239 /* 8240 * Obtain the transfer wrapper only if the TD is 8241 * not marked as RECLAIM. 8242 * 8243 * A TD that is marked as RECLAIM has had its DMA 8244 * mappings, ED, TD and pipe private structure are 8245 * ripped down. Just deallocate this TD. 8246 */ 8247 if (state != HC_TD_RECLAIM) { 8248 8249 tw = (ohci_trans_wrapper_t *)OHCI_LOOKUP_ID( 8250 (uint32_t)Get_TD(td->hctd_trans_wrapper)); 8251 8252 ASSERT(tw != NULL); 8253 8254 pp = tw->tw_pipe_private; 8255 8256 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8257 "ohci_traverse_done_list: PP = 0x%p TW = 0x%p", 8258 pp, tw); 8259 } 8260 8261 /* 8262 * Don't process the TD if its state is marked as 8263 * either RECLAIM or TIMEOUT. 8264 * 8265 * A TD that is marked as TIMEOUT has already been 8266 * processed by TD timeout handler & client driver 8267 * has been informed through exception callback. 8268 */ 8269 if ((state != HC_TD_RECLAIM) && (state != HC_TD_TIMEOUT)) { 8270 8271 /* Look at the error status */ 8272 error = ohci_parse_error(ohcip, td); 8273 8274 if (error == USB_CR_OK) { 8275 ohci_handle_normal_td(ohcip, td, tw); 8276 } else { 8277 /* handle the error condition */ 8278 ohci_handle_error(ohcip, td, error); 8279 } 8280 } else { 8281 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8282 "ohci_traverse_done_list: TD State = %d", state); 8283 } 8284 8285 /* 8286 * Save a pointer to the current transfer descriptor 8287 */ 8288 old_td = td; 8289 8290 td = ohci_td_iommu_to_cpu(ohcip, Get_TD(td->hctd_next_td)); 8291 8292 /* Deallocate this transfer descriptor */ 8293 ohci_deallocate_td(ohcip, old_td); 8294 8295 /* 8296 * Deallocate the transfer wrapper if there are no more 8297 * TD's for the transfer wrapper. ohci_deallocate_tw_resources() 8298 * will not deallocate the tw for a periodic endpoint 8299 * since it will always have a TD attached to it. 8300 * 8301 * Do not deallocate the TW if it is a isoc or intr pipe in. 8302 * The tw's are reused. 8303 * 8304 * An TD that is marked as reclaim doesn't have a pipe 8305 * or a TW associated with it anymore so don't call this 8306 * function. 8307 */ 8308 if (state != HC_TD_RECLAIM) { 8309 ASSERT(tw != NULL); 8310 ohci_deallocate_tw_resources(ohcip, pp, tw); 8311 } 8312 } 8313 } 8314 8315 8316 /* 8317 * ohci_reverse_done_list: 8318 * 8319 * Reverse the order of the Transfer Descriptor (TD) Done List. 8320 */ 8321 static ohci_td_t * 8322 ohci_reverse_done_list( 8323 ohci_state_t *ohcip, 8324 ohci_td_t *head_done_list) 8325 { 8326 ohci_td_t *cpu_new_tail, *cpu_new_head, *cpu_save; 8327 8328 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8329 "ohci_reverse_done_list:"); 8330 8331 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8332 ASSERT(head_done_list != NULL); 8333 8334 /* At first, both the tail and head pointers point to the same elem */ 8335 cpu_new_tail = cpu_new_head = 8336 ohci_td_iommu_to_cpu(ohcip, (uintptr_t)head_done_list); 8337 8338 /* See if the list has only one element */ 8339 if (Get_TD(cpu_new_head->hctd_next_td) == NULL) { 8340 8341 return (cpu_new_head); 8342 } 8343 8344 /* Advance the head pointer */ 8345 cpu_new_head = (ohci_td_t *) 8346 ohci_td_iommu_to_cpu(ohcip, Get_TD(cpu_new_head->hctd_next_td)); 8347 8348 /* The new tail now points to nothing */ 8349 Set_TD(cpu_new_tail->hctd_next_td, NULL); 8350 8351 cpu_save = (ohci_td_t *) 8352 ohci_td_iommu_to_cpu(ohcip, Get_TD(cpu_new_head->hctd_next_td)); 8353 8354 /* Reverse the list and store the pointers as CPU addresses */ 8355 while (cpu_save) { 8356 Set_TD(cpu_new_head->hctd_next_td, 8357 ohci_td_cpu_to_iommu(ohcip, cpu_new_tail)); 8358 8359 cpu_new_tail = cpu_new_head; 8360 cpu_new_head = cpu_save; 8361 8362 cpu_save = (ohci_td_t *) 8363 ohci_td_iommu_to_cpu(ohcip, 8364 Get_TD(cpu_new_head->hctd_next_td)); 8365 } 8366 8367 Set_TD(cpu_new_head->hctd_next_td, 8368 ohci_td_cpu_to_iommu(ohcip, cpu_new_tail)); 8369 8370 return (cpu_new_head); 8371 } 8372 8373 8374 /* 8375 * ohci_parse_error: 8376 * 8377 * Parse the result for any errors. 8378 */ 8379 static usb_cr_t 8380 ohci_parse_error( 8381 ohci_state_t *ohcip, 8382 ohci_td_t *td) 8383 { 8384 uint_t ctrl; 8385 usb_ep_descr_t *eptd; 8386 ohci_trans_wrapper_t *tw; 8387 ohci_pipe_private_t *pp; 8388 uint_t flag; 8389 usb_cr_t error; 8390 8391 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8392 "ohci_parse_error:"); 8393 8394 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8395 8396 ASSERT(td != NULL); 8397 8398 /* Obtain the transfer wrapper from the TD */ 8399 tw = (ohci_trans_wrapper_t *) 8400 OHCI_LOOKUP_ID((uint32_t)Get_TD(td->hctd_trans_wrapper)); 8401 8402 ASSERT(tw != NULL); 8403 8404 /* Obtain the pipe private structure */ 8405 pp = tw->tw_pipe_private; 8406 8407 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8408 "ohci_parse_error: PP 0x%p TW 0x%p", pp, tw); 8409 8410 eptd = &pp->pp_pipe_handle->p_ep; 8411 8412 ctrl = (uint_t)Get_TD(td->hctd_ctrl) & (uint32_t)HC_TD_CC; 8413 8414 /* 8415 * Check the condition code of completed TD and report errors 8416 * if any. This checking will be done both for the general and 8417 * the isochronous TDs. 8418 */ 8419 if ((error = ohci_check_for_error(ohcip, pp, tw, td, ctrl)) != 8420 USB_CR_OK) { 8421 flag = OHCI_REMOVE_XFER_ALWAYS; 8422 } else { 8423 flag = OHCI_REMOVE_XFER_IFLAST; 8424 } 8425 8426 /* Stop the the transfer timer */ 8427 ohci_stop_xfer_timer(ohcip, tw, flag); 8428 8429 /* 8430 * The isochronous endpoint needs additional error checking 8431 * and special processing. 8432 */ 8433 if ((eptd->bmAttributes & USB_EP_ATTR_MASK) == 8434 USB_EP_ATTR_ISOCH) { 8435 8436 ohci_parse_isoc_error(ohcip, pp, tw, td); 8437 8438 /* always reset error */ 8439 error = USB_CR_OK; 8440 } 8441 8442 return (error); 8443 } 8444 8445 8446 /* 8447 * ohci_parse_isoc_error: 8448 * 8449 * Check for any errors in the isochronous data packets. Also fillup 8450 * the status for each of the isochrnous data packets. 8451 */ 8452 void 8453 ohci_parse_isoc_error( 8454 ohci_state_t *ohcip, 8455 ohci_pipe_private_t *pp, 8456 ohci_trans_wrapper_t *tw, 8457 ohci_td_t *td) 8458 { 8459 usb_isoc_req_t *isoc_reqp; 8460 usb_isoc_pkt_descr_t *isoc_pkt_descr; 8461 uint_t toggle = 0, fc, ctrl, psw; 8462 int i; 8463 8464 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8465 "ohci_parse_isoc_error: td 0x%p", td); 8466 8467 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8468 8469 fc = ((uint_t)Get_TD(td->hctd_ctrl) & 8470 HC_ITD_FC) >> HC_ITD_FC_SHIFT; 8471 8472 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 8473 "ohci_parse_isoc_error: frame count %d", fc); 8474 8475 /* 8476 * Get the address of current usb isochronous request 8477 * and array of packet descriptors. 8478 */ 8479 isoc_reqp = (usb_isoc_req_t *)tw->tw_curr_xfer_reqp; 8480 isoc_pkt_descr = isoc_reqp->isoc_pkt_descr; 8481 isoc_pkt_descr += tw->tw_pkt_idx; 8482 8483 for (i = 0; i <= fc; i++) { 8484 8485 psw = Get_TD(td->hctd_offsets[i / 2]); 8486 8487 if (toggle) { 8488 ctrl = psw & HC_ITD_ODD_OFFSET; 8489 toggle = 0; 8490 } else { 8491 ctrl = (psw & HC_ITD_EVEN_OFFSET) << 8492 HC_ITD_OFFSET_SHIFT; 8493 toggle = 1; 8494 } 8495 8496 isoc_pkt_descr->isoc_pkt_actual_length = 8497 (ctrl >> HC_ITD_OFFSET_SHIFT) & HC_ITD_OFFSET_ADDR; 8498 8499 ctrl = (uint_t)(ctrl & (uint32_t)HC_TD_CC); 8500 8501 /* Write the status of isoc data packet */ 8502 isoc_pkt_descr->isoc_pkt_status = 8503 ohci_check_for_error(ohcip, pp, tw, td, ctrl); 8504 8505 if (isoc_pkt_descr->isoc_pkt_status) { 8506 /* Increment isoc data packet error count */ 8507 isoc_reqp->isoc_error_count++; 8508 } 8509 8510 /* 8511 * Get the address of next isoc data packet descriptor. 8512 */ 8513 isoc_pkt_descr++; 8514 } 8515 tw->tw_pkt_idx = tw->tw_pkt_idx + fc + 1; 8516 8517 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 8518 "ohci_parse_isoc_error: tw_pkt_idx %d", tw->tw_pkt_idx); 8519 8520 } 8521 8522 8523 /* 8524 * ohci_check_for_error: 8525 * 8526 * Check for any errors. 8527 */ 8528 static usb_cr_t 8529 ohci_check_for_error( 8530 ohci_state_t *ohcip, 8531 ohci_pipe_private_t *pp, 8532 ohci_trans_wrapper_t *tw, 8533 ohci_td_t *td, 8534 uint_t ctrl) 8535 { 8536 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 8537 uchar_t ep_attrs = ph->p_ep.bmAttributes; 8538 usb_cr_t error = USB_CR_OK; 8539 usb_req_attrs_t xfer_attrs; 8540 8541 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8542 "ohci_check_for_error: td = 0x%p ctrl = 0x%x", 8543 td, ctrl); 8544 8545 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8546 8547 switch (ctrl) { 8548 case HC_TD_CC_NO_E: 8549 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8550 "ohci_check_for_error: No Error"); 8551 error = USB_CR_OK; 8552 break; 8553 case HC_TD_CC_CRC: 8554 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8555 "ohci_check_for_error: CRC error"); 8556 error = USB_CR_CRC; 8557 break; 8558 case HC_TD_CC_BS: 8559 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8560 "ohci_check_for_error: Bit stuffing"); 8561 error = USB_CR_BITSTUFFING; 8562 break; 8563 case HC_TD_CC_DTM: 8564 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8565 "ohci_check_for_error: Data Toggle Mismatch"); 8566 error = USB_CR_DATA_TOGGLE_MM; 8567 break; 8568 case HC_TD_CC_STALL: 8569 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8570 "ohci_check_for_error: Stall"); 8571 error = USB_CR_STALL; 8572 break; 8573 case HC_TD_CC_DNR: 8574 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8575 "ohci_check_for_error: Device not responding"); 8576 error = USB_CR_DEV_NOT_RESP; 8577 break; 8578 case HC_TD_CC_PCF: 8579 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8580 "ohci_check_for_error: PID check failure"); 8581 error = USB_CR_PID_CHECKFAILURE; 8582 break; 8583 case HC_TD_CC_UPID: 8584 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8585 "ohci_check_for_error: Unexpected PID"); 8586 error = USB_CR_UNEXP_PID; 8587 break; 8588 case HC_TD_CC_DO: 8589 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8590 "ohci_check_for_error: Data overrrun"); 8591 error = USB_CR_DATA_OVERRUN; 8592 break; 8593 case HC_TD_CC_DU: 8594 /* 8595 * Check whether short packets are acceptable. 8596 * If so don't report error to client drivers 8597 * and restart the endpoint. Otherwise report 8598 * data underrun error to client driver. 8599 */ 8600 xfer_attrs = ohci_get_xfer_attrs(ohcip, pp, tw); 8601 8602 if (xfer_attrs & USB_ATTRS_SHORT_XFER_OK) { 8603 error = USB_CR_OK; 8604 if ((ep_attrs & USB_EP_ATTR_MASK) != 8605 USB_EP_ATTR_ISOCH) { 8606 /* 8607 * Cleanup the remaining resources that may have 8608 * been allocated for this transfer. 8609 */ 8610 if (ohci_cleanup_data_underrun(ohcip, pp, tw, 8611 td) == USB_SUCCESS) { 8612 /* Clear the halt bit */ 8613 Set_ED(pp->pp_ept->hced_headp, 8614 (Get_ED(pp->pp_ept->hced_headp) & 8615 ~HC_EPT_Halt)); 8616 } else { 8617 error = USB_CR_UNSPECIFIED_ERR; 8618 } 8619 } 8620 } else { 8621 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8622 "ohci_check_for_error: Data underrun"); 8623 8624 error = USB_CR_DATA_UNDERRUN; 8625 } 8626 8627 break; 8628 case HC_TD_CC_BO: 8629 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8630 "ohci_check_for_error: Buffer overrun"); 8631 error = USB_CR_BUFFER_OVERRUN; 8632 break; 8633 case HC_TD_CC_BU: 8634 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8635 "ohci_check_for_error: Buffer underrun"); 8636 error = USB_CR_BUFFER_UNDERRUN; 8637 break; 8638 case HC_TD_CC_NA: 8639 default: 8640 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8641 "ohci_check_for_error: Not accessed"); 8642 error = USB_CR_NOT_ACCESSED; 8643 break; 8644 } 8645 8646 if (error) { 8647 uint_t hced_ctrl = Get_ED(pp->pp_ept->hced_ctrl); 8648 8649 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8650 "ohci_check_for_error: Error %d Device address %d " 8651 "Endpoint number %d", error, (hced_ctrl & HC_EPT_FUNC), 8652 ((hced_ctrl & HC_EPT_EP) >> HC_EPT_EP_SHFT)); 8653 } 8654 8655 return (error); 8656 } 8657 8658 8659 /* 8660 * ohci_handle_error: 8661 * 8662 * Inform USBA about occured transaction errors by calling the USBA callback 8663 * routine. 8664 */ 8665 static void 8666 ohci_handle_error( 8667 ohci_state_t *ohcip, 8668 ohci_td_t *td, 8669 usb_cr_t error) 8670 { 8671 ohci_trans_wrapper_t *tw; 8672 usba_pipe_handle_data_t *ph; 8673 ohci_pipe_private_t *pp; 8674 mblk_t *mp = NULL; 8675 size_t length = 0; 8676 uchar_t attributes; 8677 usb_intr_req_t *curr_intr_reqp; 8678 8679 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8680 "ohci_handle_error: error = 0x%x", error); 8681 8682 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8683 8684 ASSERT(td != NULL); 8685 8686 /* Print the values in the td */ 8687 ohci_print_td(ohcip, td); 8688 8689 /* Obtain the transfer wrapper from the TD */ 8690 tw = (ohci_trans_wrapper_t *) 8691 OHCI_LOOKUP_ID((uint32_t)Get_TD(td->hctd_trans_wrapper)); 8692 8693 ASSERT(tw != NULL); 8694 8695 /* Obtain the pipe private structure */ 8696 pp = tw->tw_pipe_private; 8697 8698 ph = tw->tw_pipe_private->pp_pipe_handle; 8699 attributes = ph->p_ep.bmAttributes & USB_EP_ATTR_MASK; 8700 8701 /* 8702 * Special error handling 8703 */ 8704 if (tw->tw_direction == HC_TD_IN) { 8705 8706 switch (attributes) { 8707 case USB_EP_ATTR_CONTROL: 8708 if (((ph->p_ep.bmAttributes & 8709 USB_EP_ATTR_MASK) == 8710 USB_EP_ATTR_CONTROL) && 8711 (Get_TD(td->hctd_ctrl_phase) == 8712 OHCI_CTRL_SETUP_PHASE)) { 8713 8714 break; 8715 } 8716 /* FALLTHROUGH */ 8717 case USB_EP_ATTR_BULK: 8718 /* 8719 * Call ohci_sendup_td_message 8720 * to send message to upstream. 8721 */ 8722 ohci_sendup_td_message(ohcip, pp, tw, td, error); 8723 8724 return; 8725 case USB_EP_ATTR_INTR: 8726 curr_intr_reqp = 8727 (usb_intr_req_t *)tw->tw_curr_xfer_reqp; 8728 8729 if (curr_intr_reqp->intr_attributes & 8730 USB_ATTRS_ONE_XFER) { 8731 8732 ohci_handle_one_xfer_completion(ohcip, tw); 8733 } 8734 8735 /* Decrement periodic in request count */ 8736 pp->pp_cur_periodic_req_cnt--; 8737 break; 8738 case USB_EP_ATTR_ISOCH: 8739 default: 8740 break; 8741 } 8742 } else { 8743 switch (attributes) { 8744 case USB_EP_ATTR_BULK: 8745 case USB_EP_ATTR_INTR: 8746 /* 8747 * If "CurrentBufferPointer" of Transfer 8748 * Descriptor (TD) is not equal to zero, 8749 * then we sent less data to the device 8750 * than requested by client. In that case, 8751 * return the mblk after updating the 8752 * data->r_ptr. 8753 */ 8754 if (Get_TD(td->hctd_cbp)) { 8755 usb_opaque_t xfer_reqp = tw->tw_curr_xfer_reqp; 8756 size_t residue; 8757 8758 residue = ohci_get_td_residue(ohcip, td); 8759 length = Get_TD(td->hctd_xfer_offs) + 8760 Get_TD(td->hctd_xfer_len) - residue; 8761 8762 USB_DPRINTF_L2(PRINT_MASK_INTR, 8763 ohcip->ohci_log_hdl, 8764 "ohci_handle_error: requested data %lu " 8765 "sent data %lu", tw->tw_length, length); 8766 8767 if (attributes == USB_EP_ATTR_BULK) { 8768 mp = (mblk_t *)((usb_bulk_req_t *) 8769 (xfer_reqp))->bulk_data; 8770 } else { 8771 mp = (mblk_t *)((usb_intr_req_t *) 8772 (xfer_reqp))->intr_data; 8773 } 8774 8775 /* Increment the read pointer */ 8776 mp->b_rptr = mp->b_rptr + length; 8777 } 8778 break; 8779 default: 8780 break; 8781 } 8782 } 8783 8784 /* 8785 * Callback the client with the 8786 * failure reason. 8787 */ 8788 ohci_hcdi_callback(ph, tw, error); 8789 8790 /* Check anybody is waiting for transfers completion event */ 8791 ohci_check_for_transfers_completion(ohcip, pp); 8792 } 8793 8794 /* 8795 * ohci_cleanup_data_underrun: 8796 * 8797 * Cleans up resources when a short xfer occurs 8798 */ 8799 static int 8800 ohci_cleanup_data_underrun( 8801 ohci_state_t *ohcip, 8802 ohci_pipe_private_t *pp, 8803 ohci_trans_wrapper_t *tw, 8804 ohci_td_t *td) 8805 { 8806 ohci_td_t *next_td; 8807 ohci_td_t *last_td; 8808 ohci_td_t *temp_td; 8809 uint32_t last_td_addr; 8810 uint_t hced_head; 8811 8812 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8813 "ohci_cleanup_data_underrun: td 0x%p, tw 0x%p", td, tw); 8814 8815 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8816 ASSERT(tw->tw_hctd_head == td); 8817 8818 /* Check if this TD is the last td in the tw */ 8819 last_td = tw->tw_hctd_tail; 8820 if (td == last_td) { 8821 /* There is no need for cleanup */ 8822 return (USB_SUCCESS); 8823 } 8824 8825 /* 8826 * Make sure the ED is halted before we change any td's. 8827 * If for some reason it is not halted, return error to client 8828 * driver so they can reset the port. 8829 */ 8830 hced_head = Get_ED(pp->pp_ept->hced_headp); 8831 if (!(hced_head & HC_EPT_Halt)) { 8832 uint_t hced_ctrl = Get_ED(pp->pp_ept->hced_ctrl); 8833 8834 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8835 "ohci_cleanup_data_underrun: Unable to clean up a short " 8836 "xfer error. Client might send/receive irrelevant data." 8837 " Device address %d Endpoint number %d", 8838 (hced_ctrl & HC_EPT_FUNC), 8839 ((hced_ctrl & HC_EPT_EP) >> HC_EPT_EP_SHFT)); 8840 8841 Set_ED(pp->pp_ept->hced_headp, hced_head | HC_EPT_Halt); 8842 8843 return (USB_FAILURE); 8844 } 8845 8846 /* 8847 * Get the address of the first td of the next transfer (tw). 8848 * This td, may currently be a dummy td, but when a new request 8849 * arrives, it will be transformed into a regular td. 8850 */ 8851 last_td_addr = Get_TD(last_td->hctd_next_td); 8852 /* Set ED head to this last td */ 8853 Set_ED(pp->pp_ept->hced_headp, 8854 (last_td_addr & HC_EPT_TD_HEAD) | 8855 (hced_head & ~HC_EPT_TD_HEAD)); 8856 8857 /* 8858 * Start removing all the unused TD's from the TW, 8859 * but keep the first one. 8860 */ 8861 tw->tw_hctd_tail = td; 8862 8863 /* 8864 * Get the last_td, the next td in the tw list. 8865 * Afterwards completely disassociate the current td from other tds 8866 */ 8867 next_td = (ohci_td_t *)ohci_td_iommu_to_cpu(ohcip, 8868 Get_TD(td->hctd_tw_next_td)); 8869 Set_TD(td->hctd_tw_next_td, NULL); 8870 8871 /* 8872 * Iterate down the tw list and deallocate them 8873 */ 8874 while (next_td != NULL) { 8875 tw->tw_num_tds--; 8876 /* Disassociate this td from it's TW and set to RECLAIM */ 8877 Set_TD(next_td->hctd_trans_wrapper, NULL); 8878 Set_TD(next_td->hctd_state, HC_TD_RECLAIM); 8879 8880 temp_td = next_td; 8881 8882 next_td = (ohci_td_t *)ohci_td_iommu_to_cpu(ohcip, 8883 Get_TD(next_td->hctd_tw_next_td)); 8884 8885 ohci_deallocate_td(ohcip, temp_td); 8886 } 8887 8888 ASSERT(tw->tw_num_tds == 1); 8889 8890 return (USB_SUCCESS); 8891 } 8892 8893 /* 8894 * ohci_handle_normal_td: 8895 */ 8896 static void 8897 ohci_handle_normal_td( 8898 ohci_state_t *ohcip, 8899 ohci_td_t *td, 8900 ohci_trans_wrapper_t *tw) 8901 { 8902 ohci_pipe_private_t *pp; /* Pipe private field */ 8903 8904 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8905 "ohci_handle_normal_td:"); 8906 8907 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8908 ASSERT(tw != NULL); 8909 8910 /* Obtain the pipe private structure */ 8911 pp = tw->tw_pipe_private; 8912 8913 (*tw->tw_handle_td)(ohcip, pp, tw, 8914 td, tw->tw_handle_callback_value); 8915 8916 /* Check anybody is waiting for transfers completion event */ 8917 ohci_check_for_transfers_completion(ohcip, pp); 8918 } 8919 8920 8921 /* 8922 * ohci_handle_ctrl_td: 8923 * 8924 * Handle a control Transfer Descriptor (TD). 8925 */ 8926 /* ARGSUSED */ 8927 static void 8928 ohci_handle_ctrl_td( 8929 ohci_state_t *ohcip, 8930 ohci_pipe_private_t *pp, 8931 ohci_trans_wrapper_t *tw, 8932 ohci_td_t *td, 8933 void *tw_handle_callback_value) 8934 { 8935 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 8936 8937 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8938 "ohci_handle_ctrl_td: pp = 0x%p tw = 0x%p td = 0x%p state = 0x%x", 8939 (void *)pp, (void *)tw, (void *)td, Get_TD(td->hctd_ctrl_phase)); 8940 8941 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 8942 8943 /* 8944 * Check which control transfer phase got completed. 8945 */ 8946 tw->tw_num_tds--; 8947 switch (Get_TD(td->hctd_ctrl_phase)) { 8948 case OHCI_CTRL_SETUP_PHASE: 8949 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8950 "Setup complete: pp 0x%p td 0x%p", (void *)pp, (void *)td); 8951 8952 break; 8953 case OHCI_CTRL_DATA_PHASE: 8954 /* 8955 * If "CurrentBufferPointer" of Transfer Descriptor (TD) 8956 * is not equal to zero, then we received less data from 8957 * the device than requested by us. In that case, get the 8958 * actual received data size. 8959 */ 8960 if (Get_TD(td->hctd_cbp)) { 8961 size_t length, residue; 8962 8963 residue = ohci_get_td_residue(ohcip, td); 8964 length = Get_TD(td->hctd_xfer_offs) + 8965 Get_TD(td->hctd_xfer_len) - residue; 8966 8967 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8968 "ohci_handle_ctrl_qtd: requested data %lu " 8969 "received data %lu", tw->tw_length, length); 8970 8971 /* Save actual received data length */ 8972 tw->tw_length = length; 8973 } 8974 8975 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 8976 "Data complete: pp 0x%p td 0x%p", 8977 (void *)pp, (void *)td); 8978 8979 break; 8980 case OHCI_CTRL_STATUS_PHASE: 8981 if ((tw->tw_length != 0) && 8982 (tw->tw_direction == HC_TD_IN)) { 8983 8984 /* 8985 * Call ohci_sendup_td_message 8986 * to send message to upstream. 8987 */ 8988 ohci_sendup_td_message(ohcip, 8989 pp, tw, td, USB_CR_OK); 8990 } else { 8991 ohci_do_byte_stats(ohcip, 8992 tw->tw_length - OHCI_MAX_TD_BUF_SIZE, 8993 ph->p_ep.bmAttributes, 8994 ph->p_ep.bEndpointAddress); 8995 8996 ohci_hcdi_callback(ph, tw, USB_CR_OK); 8997 } 8998 8999 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9000 "Status complete: pp 0x%p td 0x%p", (void *)pp, (void *)td); 9001 9002 break; 9003 } 9004 } 9005 9006 9007 /* 9008 * ohci_handle_bulk_td: 9009 * 9010 * Handle a bulk Transfer Descriptor (TD). 9011 */ 9012 /* ARGSUSED */ 9013 static void 9014 ohci_handle_bulk_td( 9015 ohci_state_t *ohcip, 9016 ohci_pipe_private_t *pp, 9017 ohci_trans_wrapper_t *tw, 9018 ohci_td_t *td, 9019 void *tw_handle_callback_value) 9020 { 9021 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 9022 usb_ep_descr_t *eptd = &ph->p_ep; 9023 9024 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9025 "ohci_handle_bulk_td:"); 9026 9027 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9028 9029 /* 9030 * Decrement the TDs counter and check whether all the bulk 9031 * data has been send or received. If TDs counter reaches 9032 * zero then inform client driver about completion current 9033 * bulk request. Other wise wait for completion of other bulk 9034 * TDs or transactions on this pipe. 9035 */ 9036 if (--tw->tw_num_tds != 0) { 9037 9038 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9039 "ohci_handle_bulk_td: Number of TDs %d", tw->tw_num_tds); 9040 9041 return; 9042 } 9043 9044 /* 9045 * If this is a bulk in pipe, return the data to the client. 9046 * For a bulk out pipe, there is no need to do anything. 9047 */ 9048 if ((eptd->bEndpointAddress & 9049 USB_EP_DIR_MASK) == USB_EP_DIR_OUT) { 9050 9051 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9052 "ohci_handle_bulk_td: Bulk out pipe"); 9053 9054 ohci_do_byte_stats(ohcip, tw->tw_length, 9055 eptd->bmAttributes, eptd->bEndpointAddress); 9056 9057 /* Do the callback */ 9058 ohci_hcdi_callback(ph, tw, USB_CR_OK); 9059 9060 return; 9061 } 9062 9063 /* Call ohci_sendup_td_message to send message to upstream */ 9064 ohci_sendup_td_message(ohcip, pp, tw, td, USB_CR_OK); 9065 } 9066 9067 9068 /* 9069 * ohci_handle_intr_td: 9070 * 9071 * Handle a interrupt Transfer Descriptor (TD). 9072 */ 9073 /* ARGSUSED */ 9074 static void 9075 ohci_handle_intr_td( 9076 ohci_state_t *ohcip, 9077 ohci_pipe_private_t *pp, 9078 ohci_trans_wrapper_t *tw, 9079 ohci_td_t *td, 9080 void *tw_handle_callback_value) 9081 { 9082 usb_intr_req_t *curr_intr_reqp = 9083 (usb_intr_req_t *)tw->tw_curr_xfer_reqp; 9084 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 9085 usb_ep_descr_t *eptd = &ph->p_ep; 9086 usb_req_attrs_t attrs; 9087 int error = USB_SUCCESS; 9088 9089 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9090 "ohci_handle_intr_td: pp=0x%p tw=0x%p td=0x%p" 9091 "intr_reqp=0%p data=0x%p", pp, tw, td, curr_intr_reqp, 9092 curr_intr_reqp->intr_data); 9093 9094 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9095 9096 /* Get the interrupt xfer attributes */ 9097 attrs = curr_intr_reqp->intr_attributes; 9098 9099 /* 9100 * For a Interrupt OUT pipe, we just callback and we are done 9101 */ 9102 if ((eptd->bEndpointAddress & USB_EP_DIR_MASK) == USB_EP_DIR_OUT) { 9103 9104 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9105 "ohci_handle_intr_td: Intr out pipe, intr_reqp=0x%p," 9106 "data=0x%p", curr_intr_reqp, curr_intr_reqp->intr_data); 9107 9108 ohci_do_byte_stats(ohcip, tw->tw_length, 9109 eptd->bmAttributes, eptd->bEndpointAddress); 9110 9111 /* Do the callback */ 9112 ohci_hcdi_callback(ph, tw, USB_CR_OK); 9113 9114 return; 9115 } 9116 9117 /* Decrement number of interrupt request count */ 9118 pp->pp_cur_periodic_req_cnt--; 9119 9120 /* 9121 * Check usb flag whether USB_FLAGS_ONE_XFER flag is set 9122 * and if so, free duplicate request. 9123 */ 9124 if (attrs & USB_ATTRS_ONE_XFER) { 9125 ohci_handle_one_xfer_completion(ohcip, tw); 9126 } 9127 9128 /* Call ohci_sendup_td_message to callback into client */ 9129 ohci_sendup_td_message(ohcip, pp, tw, td, USB_CR_OK); 9130 9131 /* 9132 * If interrupt pipe state is still active, insert next Interrupt 9133 * request into the Host Controller's Interrupt list. Otherwise 9134 * you are done. 9135 */ 9136 if (pp->pp_state != OHCI_PIPE_STATE_ACTIVE) { 9137 return; 9138 } 9139 9140 if ((error = ohci_allocate_periodic_in_resource(ohcip, pp, tw, 0)) == 9141 USB_SUCCESS) { 9142 curr_intr_reqp = (usb_intr_req_t *)tw->tw_curr_xfer_reqp; 9143 9144 ASSERT(curr_intr_reqp != NULL); 9145 9146 tw->tw_num_tds = 1; 9147 9148 if (ohci_tw_rebind_cookie(ohcip, pp, tw) != USB_SUCCESS) { 9149 ohci_deallocate_periodic_in_resource(ohcip, pp, tw); 9150 error = USB_FAILURE; 9151 } else if (ohci_allocate_tds_for_tw(ohcip, tw, 9152 tw->tw_num_tds) != USB_SUCCESS) { 9153 ohci_deallocate_periodic_in_resource(ohcip, pp, tw); 9154 error = USB_FAILURE; 9155 } 9156 } 9157 9158 if (error != USB_SUCCESS) { 9159 /* 9160 * Set pipe state to stop polling and error to no 9161 * resource. Don't insert any more interrupt polling 9162 * requests. 9163 */ 9164 pp->pp_state = OHCI_PIPE_STATE_STOP_POLLING; 9165 pp->pp_error = USB_CR_NO_RESOURCES; 9166 } else { 9167 ohci_insert_intr_req(ohcip, pp, tw, 0); 9168 9169 /* Increment number of interrupt request count */ 9170 pp->pp_cur_periodic_req_cnt++; 9171 9172 ASSERT(pp->pp_cur_periodic_req_cnt == 9173 pp->pp_max_periodic_req_cnt); 9174 } 9175 } 9176 9177 9178 /* 9179 * ohci_handle_one_xfer_completion: 9180 */ 9181 static void 9182 ohci_handle_one_xfer_completion( 9183 ohci_state_t *ohcip, 9184 ohci_trans_wrapper_t *tw) 9185 { 9186 usba_pipe_handle_data_t *ph = tw->tw_pipe_private->pp_pipe_handle; 9187 ohci_pipe_private_t *pp = tw->tw_pipe_private; 9188 usb_intr_req_t *curr_intr_reqp = 9189 (usb_intr_req_t *)tw->tw_curr_xfer_reqp; 9190 9191 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9192 "ohci_handle_one_xfer_completion: tw = 0x%p", tw); 9193 9194 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9195 ASSERT(curr_intr_reqp->intr_attributes & USB_ATTRS_ONE_XFER); 9196 9197 pp->pp_state = OHCI_PIPE_STATE_IDLE; 9198 9199 /* 9200 * For one xfer, we need to copy back data ptr 9201 * and free current request 9202 */ 9203 ((usb_intr_req_t *)(pp->pp_client_periodic_in_reqp))-> 9204 intr_data = ((usb_intr_req_t *) 9205 (tw->tw_curr_xfer_reqp))->intr_data; 9206 9207 ((usb_intr_req_t *)tw->tw_curr_xfer_reqp)->intr_data = NULL; 9208 9209 /* Now free duplicate current request */ 9210 usb_free_intr_req((usb_intr_req_t *)tw-> tw_curr_xfer_reqp); 9211 9212 mutex_enter(&ph->p_mutex); 9213 ph->p_req_count--; 9214 mutex_exit(&ph->p_mutex); 9215 9216 /* Make client's request the current request */ 9217 tw->tw_curr_xfer_reqp = pp->pp_client_periodic_in_reqp; 9218 pp->pp_client_periodic_in_reqp = NULL; 9219 } 9220 9221 9222 /* 9223 * ohci_handle_isoc_td: 9224 * 9225 * Handle an isochronous Transfer Descriptor (TD). 9226 */ 9227 /* ARGSUSED */ 9228 static void 9229 ohci_handle_isoc_td( 9230 ohci_state_t *ohcip, 9231 ohci_pipe_private_t *pp, 9232 ohci_trans_wrapper_t *tw, 9233 ohci_td_t *td, 9234 void *tw_handle_callback_value) 9235 { 9236 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 9237 usb_ep_descr_t *eptd = &ph->p_ep; 9238 usb_isoc_req_t *curr_isoc_reqp = 9239 (usb_isoc_req_t *)tw->tw_curr_xfer_reqp; 9240 int error = USB_SUCCESS; 9241 9242 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9243 "ohci_handle_isoc_td: pp=0x%p tw=0x%p td=0x%p" 9244 "isoc_reqp=0%p data=0x%p", pp, tw, td, curr_isoc_reqp, 9245 curr_isoc_reqp->isoc_data); 9246 9247 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9248 9249 /* 9250 * Decrement the TDs counter and check whether all the isoc 9251 * data has been send or received. If TDs counter reaches 9252 * zero then inform client driver about completion current 9253 * isoc request. Otherwise wait for completion of other isoc 9254 * TDs or transactions on this pipe. 9255 */ 9256 if (--tw->tw_num_tds != 0) { 9257 9258 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9259 "ohci_handle_isoc_td: Number of TDs %d", tw->tw_num_tds); 9260 9261 return; 9262 } 9263 9264 /* 9265 * If this is a isoc in pipe, return the data to the client. 9266 * For a isoc out pipe, there is no need to do anything. 9267 */ 9268 if ((eptd->bEndpointAddress & USB_EP_DIR_MASK) == USB_EP_DIR_OUT) { 9269 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9270 "ohci_handle_isoc_td: Isoc out pipe, isoc_reqp=0x%p," 9271 "data=0x%p", curr_isoc_reqp, curr_isoc_reqp->isoc_data); 9272 9273 ohci_do_byte_stats(ohcip, tw->tw_length, 9274 eptd->bmAttributes, eptd->bEndpointAddress); 9275 9276 /* Do the callback */ 9277 ohci_hcdi_callback(ph, tw, USB_CR_OK); 9278 9279 return; 9280 } 9281 9282 /* Decrement number of IN isochronous request count */ 9283 pp->pp_cur_periodic_req_cnt--; 9284 9285 /* Call ohci_sendup_td_message to send message to upstream */ 9286 ohci_sendup_td_message(ohcip, pp, tw, td, USB_CR_OK); 9287 9288 /* 9289 * If isochronous pipe state is still active, insert next isochronous 9290 * request into the Host Controller's isochronous list. 9291 */ 9292 if (pp->pp_state != OHCI_PIPE_STATE_ACTIVE) { 9293 return; 9294 } 9295 9296 if ((error = ohci_allocate_periodic_in_resource(ohcip, pp, tw, 0)) == 9297 USB_SUCCESS) { 9298 curr_isoc_reqp = (usb_isoc_req_t *)tw->tw_curr_xfer_reqp; 9299 9300 ASSERT(curr_isoc_reqp != NULL); 9301 9302 tw->tw_num_tds = 9303 curr_isoc_reqp->isoc_pkts_count / OHCI_ISOC_PKTS_PER_TD; 9304 if (curr_isoc_reqp->isoc_pkts_count % OHCI_ISOC_PKTS_PER_TD) { 9305 tw->tw_num_tds++; 9306 } 9307 9308 if (ohci_tw_rebind_cookie(ohcip, pp, tw) != USB_SUCCESS) { 9309 ohci_deallocate_periodic_in_resource(ohcip, pp, tw); 9310 error = USB_FAILURE; 9311 } else if (ohci_allocate_tds_for_tw(ohcip, tw, 9312 tw->tw_num_tds) != USB_SUCCESS) { 9313 ohci_deallocate_periodic_in_resource(ohcip, pp, tw); 9314 error = USB_FAILURE; 9315 } 9316 } 9317 9318 if (error != USB_SUCCESS || 9319 ohci_insert_isoc_req(ohcip, pp, tw, 0) != USB_SUCCESS) { 9320 /* 9321 * Set pipe state to stop polling and error to no 9322 * resource. Don't insert any more isoch polling 9323 * requests. 9324 */ 9325 pp->pp_state = OHCI_PIPE_STATE_STOP_POLLING; 9326 pp->pp_error = USB_CR_NO_RESOURCES; 9327 9328 } else { 9329 /* Increment number of IN isochronous request count */ 9330 pp->pp_cur_periodic_req_cnt++; 9331 9332 ASSERT(pp->pp_cur_periodic_req_cnt == 9333 pp->pp_max_periodic_req_cnt); 9334 } 9335 } 9336 9337 9338 /* 9339 * ohci_tw_rebind_cookie: 9340 * 9341 * If the cookie associated with a DMA buffer has been walked, the cookie 9342 * is not usable any longer. To reuse the DMA buffer, the DMA handle needs 9343 * to rebind for cookies. 9344 */ 9345 static int 9346 ohci_tw_rebind_cookie( 9347 ohci_state_t *ohcip, 9348 ohci_pipe_private_t *pp, 9349 ohci_trans_wrapper_t *tw) 9350 { 9351 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 9352 int rval, i; 9353 uint_t ccount; 9354 9355 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9356 "ohci_tw_rebind_cookie:"); 9357 9358 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9359 9360 if ((eptd->bmAttributes & USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 9361 ASSERT(tw->tw_num_tds == tw->tw_ncookies); 9362 9363 for (i = 0; i < tw->tw_num_tds; i++) { 9364 if (tw->tw_isoc_bufs[i].ncookies == 1) { 9365 9366 /* 9367 * no need to rebind when there is 9368 * only one cookie in a buffer 9369 */ 9370 continue; 9371 } 9372 9373 /* unbind the DMA handle before rebinding */ 9374 rval = ddi_dma_unbind_handle( 9375 tw->tw_isoc_bufs[i].dma_handle); 9376 ASSERT(rval == USB_SUCCESS); 9377 tw->tw_isoc_bufs[i].ncookies = 0; 9378 9379 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9380 "rebind dma_handle %d", i); 9381 9382 /* rebind the handle to get cookies */ 9383 rval = ddi_dma_addr_bind_handle( 9384 tw->tw_isoc_bufs[i].dma_handle, NULL, 9385 (caddr_t)tw->tw_isoc_bufs[i].buf_addr, 9386 tw->tw_isoc_bufs[i].length, 9387 DDI_DMA_RDWR|DDI_DMA_CONSISTENT, 9388 DDI_DMA_DONTWAIT, NULL, 9389 &tw->tw_isoc_bufs[i].cookie, &ccount); 9390 9391 if ((rval == DDI_DMA_MAPPED) && 9392 (ccount <= OHCI_DMA_ATTR_TD_SGLLEN)) { 9393 tw->tw_isoc_bufs[i].ncookies = ccount; 9394 } else { 9395 9396 return (USB_NO_RESOURCES); 9397 } 9398 } 9399 } else { 9400 if (tw->tw_cookie_idx != 0) { 9401 /* unbind the DMA handle before rebinding */ 9402 rval = ddi_dma_unbind_handle(tw->tw_dmahandle); 9403 ASSERT(rval == DDI_SUCCESS); 9404 tw->tw_ncookies = 0; 9405 9406 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9407 "rebind dma_handle"); 9408 9409 /* rebind the handle to get cookies */ 9410 rval = ddi_dma_addr_bind_handle( 9411 tw->tw_dmahandle, NULL, 9412 (caddr_t)tw->tw_buf, tw->tw_length, 9413 DDI_DMA_RDWR|DDI_DMA_CONSISTENT, 9414 DDI_DMA_DONTWAIT, NULL, 9415 &tw->tw_cookie, &ccount); 9416 9417 if (rval == DDI_DMA_MAPPED) { 9418 tw->tw_ncookies = ccount; 9419 tw->tw_dma_offs = 0; 9420 tw->tw_cookie_idx = 0; 9421 } else { 9422 9423 return (USB_NO_RESOURCES); 9424 } 9425 } 9426 } 9427 9428 return (USB_SUCCESS); 9429 } 9430 9431 9432 /* 9433 * ohci_sendup_td_message: 9434 * copy data, if necessary and do callback 9435 */ 9436 static void 9437 ohci_sendup_td_message( 9438 ohci_state_t *ohcip, 9439 ohci_pipe_private_t *pp, 9440 ohci_trans_wrapper_t *tw, 9441 ohci_td_t *td, 9442 usb_cr_t error) 9443 { 9444 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 9445 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 9446 size_t length = 0, skip_len = 0, residue; 9447 mblk_t *mp; 9448 uchar_t *buf; 9449 usb_opaque_t curr_xfer_reqp = tw->tw_curr_xfer_reqp; 9450 9451 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9452 9453 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9454 "ohci_sendup_td_message:"); 9455 9456 ASSERT(tw != NULL); 9457 9458 length = tw->tw_length; 9459 9460 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 9461 case USB_EP_ATTR_CONTROL: 9462 /* 9463 * Get the correct length, adjust it for the setup size 9464 * which is not part of the data length in control end 9465 * points. Update tw->tw_length for future references. 9466 */ 9467 if (((usb_ctrl_req_t *)curr_xfer_reqp)->ctrl_wLength) { 9468 tw->tw_length = length = length - OHCI_MAX_TD_BUF_SIZE; 9469 } else { 9470 tw->tw_length = length = length - SETUP_SIZE; 9471 } 9472 9473 /* Set the length of the buffer to skip */ 9474 skip_len = OHCI_MAX_TD_BUF_SIZE; 9475 9476 if (Get_TD(td->hctd_ctrl_phase) != OHCI_CTRL_DATA_PHASE) { 9477 break; 9478 } 9479 /* FALLTHRU */ 9480 case USB_EP_ATTR_BULK: 9481 case USB_EP_ATTR_INTR: 9482 /* 9483 * If error is "data overrun", do not check for the 9484 * "CurrentBufferPointer" and return whatever data 9485 * received to the client driver. 9486 */ 9487 if (error == USB_CR_DATA_OVERRUN) { 9488 break; 9489 } 9490 9491 /* 9492 * If "CurrentBufferPointer" of Transfer Descriptor 9493 * (TD) is not equal to zero, then we received less 9494 * data from the device than requested by us. In that 9495 * case, get the actual received data size. 9496 */ 9497 if (Get_TD(td->hctd_cbp)) { 9498 residue = ohci_get_td_residue(ohcip, td); 9499 length = Get_TD(td->hctd_xfer_offs) + 9500 Get_TD(td->hctd_xfer_len) - residue - skip_len; 9501 9502 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9503 "ohci_sendup_qtd_message: requested data %lu " 9504 "received data %lu", tw->tw_length, length); 9505 } 9506 9507 break; 9508 case USB_EP_ATTR_ISOCH: 9509 default: 9510 break; 9511 } 9512 9513 /* Copy the data into the mblk_t */ 9514 buf = (uchar_t *)tw->tw_buf + skip_len; 9515 9516 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9517 "ohci_sendup_qtd_message: length %lu error %d", length, error); 9518 9519 /* Get the message block */ 9520 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 9521 case USB_EP_ATTR_CONTROL: 9522 mp = ((usb_ctrl_req_t *)curr_xfer_reqp)->ctrl_data; 9523 break; 9524 case USB_EP_ATTR_BULK: 9525 mp = ((usb_bulk_req_t *)curr_xfer_reqp)->bulk_data; 9526 break; 9527 case USB_EP_ATTR_INTR: 9528 mp = ((usb_intr_req_t *)curr_xfer_reqp)->intr_data; 9529 break; 9530 case USB_EP_ATTR_ISOCH: 9531 mp = ((usb_isoc_req_t *)curr_xfer_reqp)->isoc_data; 9532 break; 9533 } 9534 9535 ASSERT(mp != NULL); 9536 9537 if (length) { 9538 int i; 9539 uchar_t *p = mp->b_rptr; 9540 9541 /* 9542 * Update kstat byte counts 9543 * The control endpoints don't have direction bits so in 9544 * order for control stats to be counted correctly an in 9545 * bit must be faked on a control read. 9546 */ 9547 if ((eptd->bmAttributes & USB_EP_ATTR_MASK) == 9548 USB_EP_ATTR_CONTROL) { 9549 ohci_do_byte_stats(ohcip, length, 9550 eptd->bmAttributes, USB_EP_DIR_IN); 9551 } else { 9552 ohci_do_byte_stats(ohcip, length, 9553 eptd->bmAttributes, eptd->bEndpointAddress); 9554 } 9555 9556 if ((eptd->bmAttributes & USB_EP_ATTR_MASK) == 9557 USB_EP_ATTR_ISOCH) { 9558 for (i = 0; i < tw->tw_ncookies; i++) { 9559 Sync_IO_Buffer( 9560 tw->tw_isoc_bufs[i].dma_handle, 9561 tw->tw_isoc_bufs[i].length); 9562 9563 ddi_rep_get8(tw->tw_isoc_bufs[i].mem_handle, 9564 p, (uint8_t *)tw->tw_isoc_bufs[i].buf_addr, 9565 tw->tw_isoc_bufs[i].length, 9566 DDI_DEV_AUTOINCR); 9567 p += tw->tw_isoc_bufs[i].length; 9568 } 9569 tw->tw_pkt_idx = 0; 9570 } else { 9571 /* Sync IO buffer */ 9572 Sync_IO_Buffer(tw->tw_dmahandle, (skip_len + length)); 9573 9574 /* Copy the data into the message */ 9575 ddi_rep_get8(tw->tw_accesshandle, 9576 mp->b_rptr, buf, length, DDI_DEV_AUTOINCR); 9577 } 9578 9579 /* Increment the write pointer */ 9580 mp->b_wptr = mp->b_wptr + length; 9581 } else { 9582 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9583 "ohci_sendup_td_message: Zero length packet"); 9584 } 9585 9586 ohci_hcdi_callback(ph, tw, error); 9587 } 9588 9589 9590 /* 9591 * ohci_get_td_residue: 9592 * 9593 * Calculate the bytes not transfered by the TD 9594 */ 9595 size_t 9596 ohci_get_td_residue( 9597 ohci_state_t *ohcip, 9598 ohci_td_t *td) 9599 { 9600 uint32_t buf_addr, end_addr; 9601 size_t residue; 9602 9603 buf_addr = Get_TD(td->hctd_cbp); 9604 end_addr = Get_TD(td->hctd_buf_end); 9605 9606 if ((buf_addr & 0xfffff000) == 9607 (end_addr & 0xfffff000)) { 9608 residue = end_addr - buf_addr + 1; 9609 } else { 9610 residue = OHCI_MAX_TD_BUF_SIZE - 9611 (buf_addr & 0x00000fff) + 9612 (end_addr & 0x00000fff) + 1; 9613 } 9614 9615 return (residue); 9616 } 9617 9618 9619 /* 9620 * Miscellaneous functions 9621 */ 9622 9623 /* 9624 * ohci_obtain_state: 9625 * NOTE: This function is also called from POLLED MODE. 9626 */ 9627 ohci_state_t * 9628 ohci_obtain_state(dev_info_t *dip) 9629 { 9630 int instance = ddi_get_instance(dip); 9631 ohci_state_t *state = ddi_get_soft_state( 9632 ohci_statep, instance); 9633 9634 ASSERT(state != NULL); 9635 9636 return (state); 9637 } 9638 9639 9640 /* 9641 * ohci_state_is_operational: 9642 * 9643 * Check the Host controller state and return proper values. 9644 */ 9645 int 9646 ohci_state_is_operational(ohci_state_t *ohcip) 9647 { 9648 int val; 9649 9650 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9651 9652 switch (ohcip->ohci_hc_soft_state) { 9653 case OHCI_CTLR_INIT_STATE: 9654 case OHCI_CTLR_SUSPEND_STATE: 9655 val = USB_FAILURE; 9656 break; 9657 case OHCI_CTLR_OPERATIONAL_STATE: 9658 val = USB_SUCCESS; 9659 break; 9660 case OHCI_CTLR_ERROR_STATE: 9661 val = USB_HC_HARDWARE_ERROR; 9662 break; 9663 default: 9664 val = USB_FAILURE; 9665 break; 9666 } 9667 9668 return (val); 9669 } 9670 9671 9672 /* 9673 * ohci_do_soft_reset 9674 * 9675 * Do soft reset of ohci host controller. 9676 */ 9677 int 9678 ohci_do_soft_reset(ohci_state_t *ohcip) 9679 { 9680 usb_frame_number_t before_frame_number, after_frame_number; 9681 timeout_id_t xfer_timer_id, rh_timer_id; 9682 ohci_regs_t *ohci_save_regs; 9683 ohci_td_t *done_head; 9684 9685 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9686 9687 /* Increment host controller error count */ 9688 ohcip->ohci_hc_error++; 9689 9690 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9691 "ohci_do_soft_reset:" 9692 "Reset ohci host controller 0x%x", ohcip->ohci_hc_error); 9693 9694 /* 9695 * Allocate space for saving current Host Controller 9696 * registers. Don't do any recovery if allocation 9697 * fails. 9698 */ 9699 ohci_save_regs = (ohci_regs_t *) 9700 kmem_zalloc(sizeof (ohci_regs_t), KM_NOSLEEP); 9701 9702 if (ohci_save_regs == NULL) { 9703 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9704 "ohci_do_soft_reset: kmem_zalloc failed"); 9705 9706 return (USB_FAILURE); 9707 } 9708 9709 /* Save current ohci registers */ 9710 ohci_save_regs->hcr_control = Get_OpReg(hcr_control); 9711 ohci_save_regs->hcr_cmd_status = Get_OpReg(hcr_cmd_status); 9712 ohci_save_regs->hcr_intr_enable = Get_OpReg(hcr_intr_enable); 9713 ohci_save_regs->hcr_periodic_strt = Get_OpReg(hcr_periodic_strt); 9714 ohci_save_regs->hcr_frame_interval = Get_OpReg(hcr_frame_interval); 9715 ohci_save_regs->hcr_HCCA = Get_OpReg(hcr_HCCA); 9716 ohci_save_regs->hcr_bulk_head = Get_OpReg(hcr_bulk_head); 9717 ohci_save_regs->hcr_ctrl_head = Get_OpReg(hcr_ctrl_head); 9718 9719 USB_DPRINTF_L4(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9720 "ohci_do_soft_reset: Save reg = 0x%p", ohci_save_regs); 9721 9722 /* Disable all list processing and interrupts */ 9723 Set_OpReg(hcr_control, (Get_OpReg(hcr_control) & ~(HCR_CONTROL_CLE | 9724 HCR_CONTROL_BLE | HCR_CONTROL_PLE | HCR_CONTROL_IE))); 9725 9726 Set_OpReg(hcr_intr_disable, HCR_INTR_SO | 9727 HCR_INTR_WDH | HCR_INTR_RD | HCR_INTR_UE | 9728 HCR_INTR_FNO | HCR_INTR_SOF | HCR_INTR_MIE); 9729 9730 /* Wait for few milliseconds */ 9731 drv_usecwait(OHCI_TIMEWAIT); 9732 9733 /* Root hub interrupt pipe timeout id */ 9734 rh_timer_id = ohcip->ohci_root_hub.rh_intr_pipe_timer_id; 9735 9736 /* Stop the root hub interrupt timer */ 9737 if (rh_timer_id) { 9738 ohcip->ohci_root_hub.rh_intr_pipe_timer_id = 0; 9739 ohcip->ohci_root_hub.rh_intr_pipe_state = 9740 OHCI_PIPE_STATE_IDLE; 9741 9742 mutex_exit(&ohcip->ohci_int_mutex); 9743 (void) untimeout(rh_timer_id); 9744 mutex_enter(&ohcip->ohci_int_mutex); 9745 } 9746 9747 /* Transfer timeout id */ 9748 xfer_timer_id = ohcip->ohci_timer_id; 9749 9750 /* Stop the global transfer timer */ 9751 if (xfer_timer_id) { 9752 ohcip->ohci_timer_id = 0; 9753 mutex_exit(&ohcip->ohci_int_mutex); 9754 (void) untimeout(xfer_timer_id); 9755 mutex_enter(&ohcip->ohci_int_mutex); 9756 } 9757 9758 /* Process any pending HCCA DoneHead */ 9759 done_head = (ohci_td_t *)(uintptr_t) 9760 (Get_HCCA(ohcip->ohci_hccap->HccaDoneHead) & HCCA_DONE_HEAD_MASK); 9761 9762 if (ohci_check_done_head(ohcip, done_head) == USB_SUCCESS) { 9763 /* Reset the done head to NULL */ 9764 Set_HCCA(ohcip->ohci_hccap->HccaDoneHead, NULL); 9765 9766 ohci_traverse_done_list(ohcip, done_head); 9767 } 9768 9769 /* Process any pending hcr_done_head value */ 9770 done_head = (ohci_td_t *)(uintptr_t) 9771 (Get_OpReg(hcr_done_head) & HCCA_DONE_HEAD_MASK); 9772 if (ohci_check_done_head(ohcip, done_head) == USB_SUCCESS) { 9773 9774 ohci_traverse_done_list(ohcip, done_head); 9775 } 9776 9777 /* Do soft reset of ohci host controller */ 9778 Set_OpReg(hcr_cmd_status, HCR_STATUS_RESET); 9779 9780 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9781 "ohci_do_soft_reset: Reset in progress"); 9782 9783 /* Wait for reset to complete */ 9784 drv_usecwait(OHCI_RESET_TIMEWAIT); 9785 9786 /* Reset HCCA HcFrameNumber */ 9787 Set_HCCA(ohcip->ohci_hccap->HccaFrameNo, 0x00000000); 9788 9789 /* 9790 * Restore previous saved HC register value 9791 * into the current HC registers. 9792 */ 9793 Set_OpReg(hcr_periodic_strt, (uint32_t) 9794 ohci_save_regs->hcr_periodic_strt); 9795 9796 Set_OpReg(hcr_frame_interval, (uint32_t) 9797 ohci_save_regs->hcr_frame_interval); 9798 9799 Set_OpReg(hcr_done_head, 0x0); 9800 9801 Set_OpReg(hcr_bulk_curr, 0x0); 9802 9803 Set_OpReg(hcr_bulk_head, (uint32_t) 9804 ohci_save_regs->hcr_bulk_head); 9805 9806 Set_OpReg(hcr_ctrl_curr, 0x0); 9807 9808 Set_OpReg(hcr_ctrl_head, (uint32_t) 9809 ohci_save_regs->hcr_ctrl_head); 9810 9811 Set_OpReg(hcr_periodic_curr, 0x0); 9812 9813 Set_OpReg(hcr_HCCA, (uint32_t) 9814 ohci_save_regs->hcr_HCCA); 9815 9816 Set_OpReg(hcr_intr_status, 0x0); 9817 9818 /* 9819 * Set HcInterruptEnable to enable all interrupts except 9820 * Root Hub Status change interrupt. 9821 */ 9822 Set_OpReg(hcr_intr_enable, 9823 HCR_INTR_SO | HCR_INTR_WDH | HCR_INTR_RD | HCR_INTR_UE | 9824 HCR_INTR_FNO | HCR_INTR_SOF | HCR_INTR_MIE); 9825 9826 /* Start Control and Bulk list processing */ 9827 Set_OpReg(hcr_cmd_status, (HCR_STATUS_CLF | HCR_STATUS_BLF)); 9828 9829 /* 9830 * Start up Control, Bulk, Periodic and Isochronous lists 9831 * processing. 9832 */ 9833 Set_OpReg(hcr_control, (uint32_t) 9834 (ohci_save_regs->hcr_control & (~HCR_CONTROL_HCFS))); 9835 9836 /* 9837 * Deallocate the space that allocated for saving 9838 * HC registers. 9839 */ 9840 kmem_free((void *) ohci_save_regs, sizeof (ohci_regs_t)); 9841 9842 /* Resume the host controller */ 9843 Set_OpReg(hcr_control, ((Get_OpReg(hcr_control) & 9844 (~HCR_CONTROL_HCFS)) | HCR_CONTROL_RESUME)); 9845 9846 /* Wait for resume to complete */ 9847 drv_usecwait(OHCI_RESUME_TIMEWAIT); 9848 9849 /* Set the Host Controller Functional State to Operational */ 9850 Set_OpReg(hcr_control, ((Get_OpReg(hcr_control) & 9851 (~HCR_CONTROL_HCFS)) | HCR_CONTROL_OPERAT)); 9852 9853 /* Wait 10ms for HC to start sending SOF */ 9854 drv_usecwait(OHCI_TIMEWAIT); 9855 9856 /* 9857 * Get the current usb frame number before waiting for few 9858 * milliseconds. 9859 */ 9860 before_frame_number = ohci_get_current_frame_number(ohcip); 9861 9862 /* Wait for few milliseconds */ 9863 drv_usecwait(OHCI_TIMEWAIT); 9864 9865 /* 9866 * Get the current usb frame number after waiting for few 9867 * milliseconds. 9868 */ 9869 after_frame_number = ohci_get_current_frame_number(ohcip); 9870 9871 USB_DPRINTF_L3(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9872 "ohci_do_soft_reset: Before Frm No 0x%llx After Frm No 0x%llx", 9873 before_frame_number, after_frame_number); 9874 9875 if (after_frame_number <= before_frame_number) { 9876 9877 USB_DPRINTF_L2(PRINT_MASK_INTR, ohcip->ohci_log_hdl, 9878 "ohci_do_soft_reset: Soft reset failed"); 9879 9880 return (USB_FAILURE); 9881 } 9882 9883 /* Start the timer for the root hub interrupt pipe polling */ 9884 if (rh_timer_id) { 9885 ohcip->ohci_root_hub.rh_intr_pipe_timer_id = 9886 timeout(ohci_handle_root_hub_status_change, 9887 (void *)ohcip, drv_usectohz(OHCI_RH_POLL_TIME)); 9888 9889 ohcip->ohci_root_hub. 9890 rh_intr_pipe_state = OHCI_PIPE_STATE_ACTIVE; 9891 } 9892 9893 /* Start the global timer */ 9894 if (xfer_timer_id) { 9895 ohcip->ohci_timer_id = timeout(ohci_xfer_timeout_handler, 9896 (void *)ohcip, drv_usectohz(1000000)); 9897 } 9898 9899 return (USB_SUCCESS); 9900 } 9901 9902 9903 /* 9904 * ohci_get_current_frame_number: 9905 * 9906 * Get the current software based usb frame number. 9907 */ 9908 usb_frame_number_t 9909 ohci_get_current_frame_number(ohci_state_t *ohcip) 9910 { 9911 usb_frame_number_t usb_frame_number; 9912 usb_frame_number_t ohci_fno, frame_number; 9913 ohci_save_intr_sts_t *ohci_intr_sts = 9914 &ohcip->ohci_save_intr_sts; 9915 9916 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9917 9918 /* 9919 * Sync HCCA area only if this function 9920 * is invoked in non interrupt context. 9921 */ 9922 if (!(ohci_intr_sts->ohci_intr_flag & 9923 OHCI_INTR_HANDLING)) { 9924 9925 /* Sync HCCA area */ 9926 Sync_HCCA(ohcip); 9927 } 9928 9929 ohci_fno = ohcip->ohci_fno; 9930 frame_number = Get_HCCA(ohcip->ohci_hccap->HccaFrameNo); 9931 9932 /* 9933 * Calculate current software based usb frame number. 9934 * 9935 * This code accounts for the fact that frame number is 9936 * updated by the Host Controller before the ohci driver 9937 * gets an FrameNumberOverflow (FNO) interrupt that will 9938 * adjust Frame higher part. 9939 * 9940 * Refer ohci specification 1.0a, section 5.4, page 86. 9941 */ 9942 usb_frame_number = ((frame_number & 0x7FFF) | ohci_fno) + 9943 (((frame_number & 0xFFFF) ^ ohci_fno) & 0x8000); 9944 9945 return (usb_frame_number); 9946 } 9947 9948 9949 /* 9950 * ohci_cpr_cleanup: 9951 * 9952 * Cleanup ohci state and other ohci specific informations across 9953 * Check Point Resume (CPR). 9954 */ 9955 static void 9956 ohci_cpr_cleanup(ohci_state_t *ohcip) 9957 { 9958 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9959 9960 /* Reset software part of usb frame number */ 9961 ohcip->ohci_fno = 0; 9962 9963 /* Reset Schedule Overrrun Error Counter */ 9964 ohcip->ohci_so_error = 0; 9965 9966 /* Reset HCCA HcFrameNumber */ 9967 Set_HCCA(ohcip->ohci_hccap->HccaFrameNo, 0x00000000); 9968 } 9969 9970 9971 /* 9972 * ohci_get_xfer_attrs: 9973 * 9974 * Get the attributes of a particular xfer. 9975 */ 9976 static usb_req_attrs_t 9977 ohci_get_xfer_attrs( 9978 ohci_state_t *ohcip, 9979 ohci_pipe_private_t *pp, 9980 ohci_trans_wrapper_t *tw) 9981 { 9982 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 9983 usb_req_attrs_t attrs = 0; 9984 9985 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 9986 "ohci_get_xfer_attrs:"); 9987 9988 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 9989 9990 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 9991 case USB_EP_ATTR_CONTROL: 9992 attrs = ((usb_ctrl_req_t *) 9993 tw->tw_curr_xfer_reqp)->ctrl_attributes; 9994 break; 9995 case USB_EP_ATTR_BULK: 9996 attrs = ((usb_bulk_req_t *) 9997 tw->tw_curr_xfer_reqp)->bulk_attributes; 9998 break; 9999 case USB_EP_ATTR_INTR: 10000 attrs = ((usb_intr_req_t *) 10001 tw->tw_curr_xfer_reqp)->intr_attributes; 10002 break; 10003 case USB_EP_ATTR_ISOCH: 10004 attrs = ((usb_isoc_req_t *) 10005 tw->tw_curr_xfer_reqp)->isoc_attributes; 10006 break; 10007 } 10008 10009 return (attrs); 10010 } 10011 10012 10013 /* 10014 * ohci_allocate_periodic_in_resource 10015 * 10016 * Allocate interrupt/isochronous request structure for the 10017 * interrupt/isochronous IN transfer. 10018 */ 10019 static int 10020 ohci_allocate_periodic_in_resource( 10021 ohci_state_t *ohcip, 10022 ohci_pipe_private_t *pp, 10023 ohci_trans_wrapper_t *tw, 10024 usb_flags_t flags) 10025 { 10026 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 10027 uchar_t ep_attr = ph->p_ep.bmAttributes; 10028 usb_intr_req_t *curr_intr_reqp; 10029 usb_isoc_req_t *curr_isoc_reqp; 10030 usb_opaque_t client_periodic_in_reqp; 10031 size_t length = 0; 10032 10033 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10034 "ohci_allocate_periodic_in_resource:" 10035 "pp = 0x%p tw = 0x%p flags = 0x%x", pp, tw, flags); 10036 10037 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10038 ASSERT(tw->tw_curr_xfer_reqp == NULL); 10039 10040 /* Get the client periodic in request pointer */ 10041 client_periodic_in_reqp = pp->pp_client_periodic_in_reqp; 10042 10043 /* 10044 * If it a periodic IN request and periodic request is NULL, 10045 * allocate corresponding usb periodic IN request for the 10046 * current periodic polling request and copy the information 10047 * from the saved periodic request structure. 10048 */ 10049 if ((ep_attr & USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 10050 10051 if (client_periodic_in_reqp) { 10052 10053 /* Get the interrupt transfer length */ 10054 length = ((usb_intr_req_t *) 10055 client_periodic_in_reqp)->intr_len; 10056 10057 curr_intr_reqp = usba_hcdi_dup_intr_req( 10058 ph->p_dip, (usb_intr_req_t *) 10059 client_periodic_in_reqp, length, flags); 10060 } else { 10061 curr_intr_reqp = usb_alloc_intr_req( 10062 ph->p_dip, length, flags); 10063 } 10064 10065 if (curr_intr_reqp == NULL) { 10066 10067 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10068 "ohci_allocate_periodic_in_resource: Interrupt " 10069 "request structure allocation failed"); 10070 10071 return (USB_NO_RESOURCES); 10072 } 10073 10074 if (client_periodic_in_reqp == NULL) { 10075 /* For polled mode */ 10076 curr_intr_reqp-> 10077 intr_attributes = USB_ATTRS_SHORT_XFER_OK; 10078 curr_intr_reqp-> 10079 intr_len = ph->p_ep.wMaxPacketSize; 10080 } else { 10081 /* Check and save the timeout value */ 10082 tw->tw_timeout = (curr_intr_reqp->intr_attributes & 10083 USB_ATTRS_ONE_XFER) ? 10084 curr_intr_reqp->intr_timeout: 0; 10085 } 10086 10087 tw->tw_curr_xfer_reqp = (usb_opaque_t)curr_intr_reqp; 10088 tw->tw_length = curr_intr_reqp->intr_len; 10089 } else { 10090 ASSERT(client_periodic_in_reqp != NULL); 10091 10092 curr_isoc_reqp = usba_hcdi_dup_isoc_req(ph->p_dip, 10093 (usb_isoc_req_t *)client_periodic_in_reqp, flags); 10094 10095 if (curr_isoc_reqp == NULL) { 10096 10097 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10098 "ohci_allocate_periodic_in_resource: Isochronous" 10099 "request structure allocation failed"); 10100 10101 return (USB_NO_RESOURCES); 10102 } 10103 10104 /* 10105 * Save the client's isochronous request pointer and 10106 * length of isochronous transfer in transfer wrapper. 10107 * The dup'ed request is saved in pp_client_periodic_in_reqp 10108 */ 10109 tw->tw_curr_xfer_reqp = 10110 (usb_opaque_t)pp->pp_client_periodic_in_reqp; 10111 pp->pp_client_periodic_in_reqp = (usb_opaque_t)curr_isoc_reqp; 10112 } 10113 10114 mutex_enter(&ph->p_mutex); 10115 ph->p_req_count++; 10116 mutex_exit(&ph->p_mutex); 10117 10118 pp->pp_state = OHCI_PIPE_STATE_ACTIVE; 10119 10120 return (USB_SUCCESS); 10121 } 10122 10123 10124 /* 10125 * ohci_wait_for_sof: 10126 * 10127 * Wait for couple of SOF interrupts 10128 */ 10129 static int 10130 ohci_wait_for_sof(ohci_state_t *ohcip) 10131 { 10132 usb_frame_number_t before_frame_number, after_frame_number; 10133 clock_t sof_time_wait; 10134 int rval, sof_wait_count; 10135 10136 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10137 "ohci_wait_for_sof"); 10138 10139 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10140 10141 rval = ohci_state_is_operational(ohcip); 10142 10143 if (rval != USB_SUCCESS) { 10144 10145 return (rval); 10146 } 10147 10148 /* Get the number of clock ticks to wait */ 10149 sof_time_wait = drv_usectohz(OHCI_MAX_SOF_TIMEWAIT * 1000000); 10150 10151 sof_wait_count = 0; 10152 10153 /* 10154 * Get the current usb frame number before waiting for the 10155 * SOF interrupt event. 10156 */ 10157 before_frame_number = ohci_get_current_frame_number(ohcip); 10158 10159 while (sof_wait_count < MAX_SOF_WAIT_COUNT) { 10160 /* Enable the SOF interrupt */ 10161 Set_OpReg(hcr_intr_enable, HCR_INTR_SOF); 10162 10163 ASSERT(Get_OpReg(hcr_intr_enable) & HCR_INTR_SOF); 10164 10165 /* Wait for the SOF or timeout event */ 10166 rval = cv_timedwait(&ohcip->ohci_SOF_cv, 10167 &ohcip->ohci_int_mutex, ddi_get_lbolt() + sof_time_wait); 10168 10169 /* 10170 * Get the current usb frame number after woken up either 10171 * from SOF interrupt or timer expired event. 10172 */ 10173 after_frame_number = ohci_get_current_frame_number(ohcip); 10174 10175 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10176 "ohci_wait_for_sof: before 0x%llx, after 0x%llx", 10177 before_frame_number, after_frame_number); 10178 10179 /* 10180 * Return failure, if we are woken up becuase of timer expired 10181 * event and if usb frame number has not been changed. 10182 */ 10183 if ((rval == -1) && 10184 (after_frame_number <= before_frame_number)) { 10185 10186 if ((ohci_do_soft_reset(ohcip)) != USB_SUCCESS) { 10187 10188 USB_DPRINTF_L0(PRINT_MASK_LISTS, 10189 ohcip->ohci_log_hdl, "No SOF interrupts"); 10190 10191 /* Set host controller soft state to error */ 10192 ohcip->ohci_hc_soft_state = 10193 OHCI_CTLR_ERROR_STATE; 10194 10195 return (USB_FAILURE); 10196 } 10197 10198 /* Get new usb frame number */ 10199 after_frame_number = before_frame_number = 10200 ohci_get_current_frame_number(ohcip); 10201 } 10202 10203 ASSERT(after_frame_number >= before_frame_number); 10204 10205 before_frame_number = after_frame_number; 10206 sof_wait_count++; 10207 } 10208 10209 return (USB_SUCCESS); 10210 } 10211 10212 10213 /* 10214 * ohci_pipe_cleanup 10215 * 10216 * Cleanup ohci pipe. 10217 */ 10218 static void 10219 ohci_pipe_cleanup( 10220 ohci_state_t *ohcip, 10221 usba_pipe_handle_data_t *ph) 10222 { 10223 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 10224 usb_ep_descr_t *eptd = &ph->p_ep; 10225 usb_cr_t completion_reason; 10226 uint_t pipe_state = pp->pp_state; 10227 uint_t bit = 0; 10228 10229 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10230 "ohci_pipe_cleanup: ph = 0x%p", ph); 10231 10232 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10233 10234 switch (pipe_state) { 10235 case OHCI_PIPE_STATE_CLOSE: 10236 if (OHCI_NON_PERIODIC_ENDPOINT(eptd)) { 10237 10238 bit = ((eptd->bmAttributes & 10239 USB_EP_ATTR_MASK) == USB_EP_ATTR_CONTROL) ? 10240 HCR_CONTROL_CLE: HCR_CONTROL_BLE; 10241 10242 Set_OpReg(hcr_control, 10243 (Get_OpReg(hcr_control) & ~(bit))); 10244 10245 /* Wait for the next SOF */ 10246 (void) ohci_wait_for_sof(ohcip); 10247 10248 break; 10249 } 10250 /* FALLTHROUGH */ 10251 case OHCI_PIPE_STATE_RESET: 10252 case OHCI_PIPE_STATE_STOP_POLLING: 10253 /* 10254 * Set the sKip bit to stop all transactions on 10255 * this pipe 10256 */ 10257 ohci_modify_sKip_bit(ohcip, pp, SET_sKip, 10258 OHCI_FLAGS_SLEEP | OHCI_FLAGS_DMA_SYNC); 10259 10260 break; 10261 default: 10262 return; 10263 } 10264 10265 /* 10266 * Wait for processing all completed transfers and 10267 * to send results to upstream. 10268 */ 10269 ohci_wait_for_transfers_completion(ohcip, pp); 10270 10271 /* Save the data toggle information */ 10272 ohci_save_data_toggle(ohcip, ph); 10273 10274 /* 10275 * Traverse the list of TD's on this endpoint and 10276 * these TD's have outstanding transfer requests. 10277 * Since the list processing is stopped, these tds 10278 * can be deallocated. 10279 */ 10280 ohci_traverse_tds(ohcip, ph); 10281 10282 /* 10283 * If all of the endpoint's TD's have been deallocated, 10284 * then the DMA mappings can be torn down. If not there 10285 * are some TD's on the done list that have not been 10286 * processed. Tag these TD's so that they are thrown 10287 * away when the done list is processed. 10288 */ 10289 ohci_done_list_tds(ohcip, ph); 10290 10291 /* Do callbacks for all unfinished requests */ 10292 ohci_handle_outstanding_requests(ohcip, pp); 10293 10294 /* Free DMA resources */ 10295 ohci_free_dma_resources(ohcip, ph); 10296 10297 switch (pipe_state) { 10298 case OHCI_PIPE_STATE_CLOSE: 10299 completion_reason = USB_CR_PIPE_CLOSING; 10300 break; 10301 case OHCI_PIPE_STATE_RESET: 10302 case OHCI_PIPE_STATE_STOP_POLLING: 10303 /* Set completion reason */ 10304 completion_reason = (pipe_state == 10305 OHCI_PIPE_STATE_RESET) ? 10306 USB_CR_PIPE_RESET: USB_CR_STOPPED_POLLING; 10307 10308 /* Restore the data toggle information */ 10309 ohci_restore_data_toggle(ohcip, ph); 10310 10311 /* 10312 * Clear the sKip bit to restart all the 10313 * transactions on this pipe. 10314 */ 10315 ohci_modify_sKip_bit(ohcip, pp, 10316 CLEAR_sKip, OHCI_FLAGS_NOSLEEP); 10317 10318 /* Set pipe state to idle */ 10319 pp->pp_state = OHCI_PIPE_STATE_IDLE; 10320 10321 break; 10322 } 10323 10324 ASSERT((Get_ED(pp->pp_ept->hced_tailp) & HC_EPT_TD_TAIL) == 10325 (Get_ED(pp->pp_ept->hced_headp) & HC_EPT_TD_HEAD)); 10326 10327 ASSERT((pp->pp_tw_head == NULL) && (pp->pp_tw_tail == NULL)); 10328 10329 /* 10330 * Do the callback for the original client 10331 * periodic IN request. 10332 */ 10333 if ((OHCI_PERIODIC_ENDPOINT(eptd)) && 10334 ((ph->p_ep.bEndpointAddress & USB_EP_DIR_MASK) == 10335 USB_EP_DIR_IN)) { 10336 10337 ohci_do_client_periodic_in_req_callback( 10338 ohcip, pp, completion_reason); 10339 } 10340 } 10341 10342 10343 /* 10344 * ohci_wait_for_transfers_completion: 10345 * 10346 * Wait for processing all completed transfers and to send results 10347 * to upstream. 10348 */ 10349 static void 10350 ohci_wait_for_transfers_completion( 10351 ohci_state_t *ohcip, 10352 ohci_pipe_private_t *pp) 10353 { 10354 ohci_trans_wrapper_t *head_tw = pp->pp_tw_head; 10355 ohci_trans_wrapper_t *next_tw; 10356 clock_t xfer_cmpl_time_wait; 10357 ohci_td_t *tailp, *headp, *nextp; 10358 ohci_td_t *head_td, *next_td; 10359 ohci_ed_t *ept = pp->pp_ept; 10360 int rval; 10361 10362 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10363 "ohci_wait_for_transfers_completion: pp = 0x%p", pp); 10364 10365 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10366 10367 headp = (ohci_td_t *)(ohci_td_iommu_to_cpu(ohcip, 10368 Get_ED(ept->hced_headp) & (uint32_t)HC_EPT_TD_HEAD)); 10369 10370 tailp = (ohci_td_t *)(ohci_td_iommu_to_cpu(ohcip, 10371 Get_ED(ept->hced_tailp) & (uint32_t)HC_EPT_TD_TAIL)); 10372 10373 rval = ohci_state_is_operational(ohcip); 10374 10375 if (rval != USB_SUCCESS) { 10376 10377 return; 10378 } 10379 10380 pp->pp_count_done_tds = 0; 10381 10382 /* Process the transfer wrappers for this pipe */ 10383 next_tw = head_tw; 10384 while (next_tw) { 10385 head_td = (ohci_td_t *)next_tw->tw_hctd_head; 10386 next_td = head_td; 10387 10388 if (head_td) { 10389 /* 10390 * Walk through each TD for this transfer 10391 * wrapper. If a TD still exists, then it 10392 * is currently on the done list. 10393 */ 10394 while (next_td) { 10395 10396 nextp = headp; 10397 10398 while (nextp != tailp) { 10399 10400 /* TD is on the ED */ 10401 if (nextp == next_td) { 10402 break; 10403 } 10404 10405 nextp = (ohci_td_t *) 10406 (ohci_td_iommu_to_cpu(ohcip, 10407 (Get_TD(nextp->hctd_next_td) & 10408 HC_EPT_TD_TAIL))); 10409 } 10410 10411 if (nextp == tailp) { 10412 pp->pp_count_done_tds++; 10413 } 10414 10415 next_td = ohci_td_iommu_to_cpu(ohcip, 10416 Get_TD(next_td->hctd_tw_next_td)); 10417 } 10418 } 10419 10420 next_tw = next_tw->tw_next; 10421 } 10422 10423 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10424 "ohci_wait_for_transfers_completion: count_done_tds = 0x%x", 10425 pp->pp_count_done_tds); 10426 10427 if (!pp->pp_count_done_tds) { 10428 10429 return; 10430 } 10431 10432 /* Get the number of clock ticks to wait */ 10433 xfer_cmpl_time_wait = drv_usectohz(OHCI_XFER_CMPL_TIMEWAIT * 1000000); 10434 10435 (void) cv_timedwait(&pp->pp_xfer_cmpl_cv, 10436 &ohcip->ohci_int_mutex, 10437 ddi_get_lbolt() + xfer_cmpl_time_wait); 10438 10439 if (pp->pp_count_done_tds) { 10440 10441 USB_DPRINTF_L2(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10442 "ohci_wait_for_transfers_completion: No transfers " 10443 "completion confirmation received for 0x%x requests", 10444 pp->pp_count_done_tds); 10445 } 10446 } 10447 10448 10449 /* 10450 * ohci_check_for_transfers_completion: 10451 * 10452 * Check whether anybody is waiting for transfers completion event. If so, send 10453 * this event and also stop initiating any new transfers on this pipe. 10454 */ 10455 static void 10456 ohci_check_for_transfers_completion( 10457 ohci_state_t *ohcip, 10458 ohci_pipe_private_t *pp) 10459 { 10460 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10461 "ohci_check_for_transfers_completion: pp = 0x%p", pp); 10462 10463 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10464 10465 if ((pp->pp_state == OHCI_PIPE_STATE_STOP_POLLING) && 10466 (pp->pp_error == USB_CR_NO_RESOURCES) && 10467 (pp->pp_cur_periodic_req_cnt == 0)) { 10468 10469 /* Reset pipe error to zero */ 10470 pp->pp_error = 0; 10471 10472 /* Do callback for original request */ 10473 ohci_do_client_periodic_in_req_callback( 10474 ohcip, pp, USB_CR_NO_RESOURCES); 10475 } 10476 10477 if (pp->pp_count_done_tds) { 10478 10479 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10480 "ohci_check_for_transfers_completion:" 10481 "count_done_tds = 0x%x", pp->pp_count_done_tds); 10482 10483 /* Decrement the done td count */ 10484 pp->pp_count_done_tds--; 10485 10486 if (!pp->pp_count_done_tds) { 10487 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10488 "ohci_check_for_transfers_completion:" 10489 "Sent transfers completion event pp = 0x%p", pp); 10490 10491 /* Send the transfer completion signal */ 10492 cv_signal(&pp->pp_xfer_cmpl_cv); 10493 } 10494 } 10495 } 10496 10497 10498 /* 10499 * ohci_save_data_toggle: 10500 * 10501 * Save the data toggle information. 10502 */ 10503 static void 10504 ohci_save_data_toggle( 10505 ohci_state_t *ohcip, 10506 usba_pipe_handle_data_t *ph) 10507 { 10508 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 10509 usb_ep_descr_t *eptd = &ph->p_ep; 10510 uint_t data_toggle; 10511 usb_cr_t error = pp->pp_error; 10512 ohci_ed_t *ed = pp->pp_ept; 10513 ohci_td_t *headp, *tailp; 10514 10515 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10516 "ohci_save_data_toggle: ph = 0x%p", ph); 10517 10518 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10519 10520 /* Reset the pipe error value */ 10521 pp->pp_error = USB_CR_OK; 10522 10523 /* Return immediately if it is a control or isoc pipe */ 10524 if (((eptd->bmAttributes & USB_EP_ATTR_MASK) == 10525 USB_EP_ATTR_CONTROL) || ((eptd->bmAttributes & 10526 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) { 10527 10528 return; 10529 } 10530 10531 headp = (ohci_td_t *)(ohci_td_iommu_to_cpu(ohcip, 10532 Get_ED(ed->hced_headp) & (uint32_t)HC_EPT_TD_HEAD)); 10533 10534 tailp = (ohci_td_t *)(ohci_td_iommu_to_cpu(ohcip, 10535 Get_ED(ed->hced_tailp) & (uint32_t)HC_EPT_TD_TAIL)); 10536 10537 /* 10538 * Retrieve the data toggle information either from the endpoint 10539 * (ED) or from the transfer descriptor (TD) depending on the 10540 * situation. 10541 */ 10542 if ((Get_ED(ed->hced_headp) & HC_EPT_Halt) || (headp == tailp)) { 10543 10544 /* Get the data toggle information from the endpoint */ 10545 data_toggle = (Get_ED(ed->hced_headp) & 10546 HC_EPT_Carry)? DATA1:DATA0; 10547 } else { 10548 /* 10549 * Retrieve the data toggle information depending on the 10550 * master data toggle information saved in the transfer 10551 * descriptor (TD) at the head of the endpoint (ED). 10552 * 10553 * Check for master data toggle information . 10554 */ 10555 if (Get_TD(headp->hctd_ctrl) & HC_TD_MS_DT) { 10556 /* Get the data toggle information from td */ 10557 data_toggle = (Get_TD(headp->hctd_ctrl) & 10558 HC_TD_DT_1) ? DATA1:DATA0; 10559 } else { 10560 /* Get the data toggle information from the endpoint */ 10561 data_toggle = (Get_ED(ed->hced_headp) & 10562 HC_EPT_Carry)? DATA1:DATA0; 10563 } 10564 } 10565 10566 /* 10567 * If error is STALL, then, set 10568 * data toggle to zero. 10569 */ 10570 if (error == USB_CR_STALL) { 10571 data_toggle = DATA0; 10572 } 10573 10574 /* 10575 * Save the data toggle information 10576 * in the usb device structure. 10577 */ 10578 mutex_enter(&ph->p_mutex); 10579 usba_hcdi_set_data_toggle(ph->p_usba_device, ph->p_ep.bEndpointAddress, 10580 data_toggle); 10581 mutex_exit(&ph->p_mutex); 10582 } 10583 10584 10585 /* 10586 * ohci_restore_data_toggle: 10587 * 10588 * Restore the data toggle information. 10589 */ 10590 static void 10591 ohci_restore_data_toggle( 10592 ohci_state_t *ohcip, 10593 usba_pipe_handle_data_t *ph) 10594 { 10595 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 10596 usb_ep_descr_t *eptd = &ph->p_ep; 10597 uint_t data_toggle = 0; 10598 10599 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10600 "ohci_restore_data_toggle: ph = 0x%p", ph); 10601 10602 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10603 10604 /* 10605 * Return immediately if it is a control or isoc pipe. 10606 */ 10607 if (((eptd->bmAttributes & USB_EP_ATTR_MASK) == 10608 USB_EP_ATTR_CONTROL) || ((eptd->bmAttributes & 10609 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH)) { 10610 10611 return; 10612 } 10613 10614 mutex_enter(&ph->p_mutex); 10615 10616 data_toggle = usba_hcdi_get_data_toggle(ph->p_usba_device, 10617 ph->p_ep.bEndpointAddress); 10618 usba_hcdi_set_data_toggle(ph->p_usba_device, ph->p_ep.bEndpointAddress, 10619 0); 10620 10621 mutex_exit(&ph->p_mutex); 10622 10623 /* 10624 * Restore the data toggle bit depending on the 10625 * previous data toggle information. 10626 */ 10627 if (data_toggle) { 10628 Set_ED(pp->pp_ept->hced_headp, 10629 Get_ED(pp->pp_ept->hced_headp) | HC_EPT_Carry); 10630 } else { 10631 Set_ED(pp->pp_ept->hced_headp, 10632 Get_ED(pp->pp_ept->hced_headp) & (~HC_EPT_Carry)); 10633 } 10634 } 10635 10636 10637 /* 10638 * ohci_handle_outstanding_requests 10639 * NOTE: This function is also called from POLLED MODE. 10640 * 10641 * Deallocate interrupt/isochronous request structure for the 10642 * interrupt/isochronous IN transfer. Do the callbacks for all 10643 * unfinished requests. 10644 */ 10645 void 10646 ohci_handle_outstanding_requests( 10647 ohci_state_t *ohcip, 10648 ohci_pipe_private_t *pp) 10649 { 10650 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 10651 usb_ep_descr_t *eptd = &ph->p_ep; 10652 ohci_trans_wrapper_t *curr_tw; 10653 ohci_trans_wrapper_t *next_tw; 10654 usb_opaque_t curr_xfer_reqp; 10655 10656 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10657 "ohci_handle_outstanding_requests: pp = 0x%p", pp); 10658 10659 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10660 10661 /* 10662 * Deallocate all the pre-allocated interrupt requests 10663 */ 10664 next_tw = pp->pp_tw_head; 10665 10666 while (next_tw) { 10667 curr_tw = next_tw; 10668 next_tw = curr_tw->tw_next; 10669 10670 curr_xfer_reqp = curr_tw->tw_curr_xfer_reqp; 10671 10672 /* Deallocate current interrupt request */ 10673 if (curr_xfer_reqp) { 10674 10675 if ((OHCI_PERIODIC_ENDPOINT(eptd)) && 10676 (curr_tw->tw_direction == HC_TD_IN)) { 10677 10678 /* Decrement periodic in request count */ 10679 pp->pp_cur_periodic_req_cnt--; 10680 10681 ohci_deallocate_periodic_in_resource( 10682 ohcip, pp, curr_tw); 10683 } else { 10684 ohci_hcdi_callback(ph, 10685 curr_tw, USB_CR_FLUSHED); 10686 } 10687 } 10688 } 10689 } 10690 10691 10692 /* 10693 * ohci_deallocate_periodic_in_resource 10694 * 10695 * Deallocate interrupt/isochronous request structure for the 10696 * interrupt/isochronous IN transfer. 10697 */ 10698 static void 10699 ohci_deallocate_periodic_in_resource( 10700 ohci_state_t *ohcip, 10701 ohci_pipe_private_t *pp, 10702 ohci_trans_wrapper_t *tw) 10703 { 10704 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 10705 uchar_t ep_attr = ph->p_ep.bmAttributes; 10706 usb_opaque_t curr_xfer_reqp; 10707 10708 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10709 "ohci_deallocate_periodic_in_resource: " 10710 "pp = 0x%p tw = 0x%p", pp, tw); 10711 10712 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10713 10714 curr_xfer_reqp = tw->tw_curr_xfer_reqp; 10715 10716 /* Check the current periodic in request pointer */ 10717 if (curr_xfer_reqp) { 10718 /* 10719 * Reset periodic in request usb isoch 10720 * packet request pointers to null. 10721 */ 10722 tw->tw_curr_xfer_reqp = NULL; 10723 tw->tw_curr_isoc_pktp = NULL; 10724 10725 mutex_enter(&ph->p_mutex); 10726 ph->p_req_count--; 10727 mutex_exit(&ph->p_mutex); 10728 10729 /* 10730 * Free pre-allocated interrupt 10731 * or isochronous requests. 10732 */ 10733 switch (ep_attr & USB_EP_ATTR_MASK) { 10734 case USB_EP_ATTR_INTR: 10735 usb_free_intr_req( 10736 (usb_intr_req_t *)curr_xfer_reqp); 10737 break; 10738 case USB_EP_ATTR_ISOCH: 10739 usb_free_isoc_req( 10740 (usb_isoc_req_t *)curr_xfer_reqp); 10741 break; 10742 } 10743 } 10744 } 10745 10746 10747 /* 10748 * ohci_do_client_periodic_in_req_callback 10749 * 10750 * Do callback for the original client periodic IN request. 10751 */ 10752 static void 10753 ohci_do_client_periodic_in_req_callback( 10754 ohci_state_t *ohcip, 10755 ohci_pipe_private_t *pp, 10756 usb_cr_t completion_reason) 10757 { 10758 usba_pipe_handle_data_t *ph = pp->pp_pipe_handle; 10759 10760 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10761 "ohci_do_client_periodic_in_req_callback: " 10762 "pp = 0x%p cc = 0x%x", pp, completion_reason); 10763 10764 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10765 10766 /* 10767 * Check for Interrupt/Isochronous IN, whether we need to do 10768 * callback for the original client's periodic IN request. 10769 */ 10770 if (pp->pp_client_periodic_in_reqp) { 10771 ASSERT(pp->pp_cur_periodic_req_cnt == 0); 10772 ohci_hcdi_callback(ph, NULL, completion_reason); 10773 } 10774 } 10775 10776 10777 /* 10778 * ohci_hcdi_callback() 10779 * 10780 * Convenience wrapper around usba_hcdi_cb() other than root hub. 10781 */ 10782 static void 10783 ohci_hcdi_callback( 10784 usba_pipe_handle_data_t *ph, 10785 ohci_trans_wrapper_t *tw, 10786 usb_cr_t completion_reason) 10787 { 10788 ohci_state_t *ohcip = ohci_obtain_state( 10789 ph->p_usba_device->usb_root_hub_dip); 10790 uchar_t attributes = ph->p_ep.bmAttributes & 10791 USB_EP_ATTR_MASK; 10792 ohci_pipe_private_t *pp = (ohci_pipe_private_t *)ph->p_hcd_private; 10793 usb_opaque_t curr_xfer_reqp; 10794 uint_t pipe_state = 0; 10795 10796 USB_DPRINTF_L4(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 10797 "ohci_hcdi_callback: ph = 0x%p, tw = 0x%p, cr = 0x%x", 10798 ph, tw, completion_reason); 10799 10800 ASSERT(mutex_owned(&ohcip->ohci_int_mutex)); 10801 10802 /* Set the pipe state as per completion reason */ 10803 switch (completion_reason) { 10804 case USB_CR_OK: 10805 pipe_state = pp->pp_state; 10806 break; 10807 case USB_CR_NO_RESOURCES: 10808 case USB_CR_NOT_SUPPORTED: 10809 case USB_CR_STOPPED_POLLING: 10810 case USB_CR_PIPE_RESET: 10811 pipe_state = OHCI_PIPE_STATE_IDLE; 10812 break; 10813 case USB_CR_PIPE_CLOSING: 10814 break; 10815 default: 10816 /* 10817 * Set the pipe state to error 10818 * except for the isoc pipe. 10819 */ 10820 if (attributes != USB_EP_ATTR_ISOCH) { 10821 pipe_state = OHCI_PIPE_STATE_ERROR; 10822 pp->pp_error = completion_reason; 10823 } 10824 break; 10825 10826 } 10827 10828 pp->pp_state = pipe_state; 10829 10830 if (tw && tw->tw_curr_xfer_reqp) { 10831 curr_xfer_reqp = tw->tw_curr_xfer_reqp; 10832 tw->tw_curr_xfer_reqp = NULL; 10833 tw->tw_curr_isoc_pktp = NULL; 10834 } else { 10835 ASSERT(pp->pp_client_periodic_in_reqp != NULL); 10836 10837 curr_xfer_reqp = pp->pp_client_periodic_in_reqp; 10838 pp->pp_client_periodic_in_reqp = NULL; 10839 } 10840 10841 ASSERT(curr_xfer_reqp != NULL); 10842 10843 mutex_exit(&ohcip->ohci_int_mutex); 10844 10845 usba_hcdi_cb(ph, curr_xfer_reqp, completion_reason); 10846 10847 mutex_enter(&ohcip->ohci_int_mutex); 10848 } 10849 10850 10851 /* 10852 * ohci kstat functions 10853 */ 10854 10855 /* 10856 * ohci_create_stats: 10857 * 10858 * Allocate and initialize the ohci kstat structures 10859 */ 10860 static void 10861 ohci_create_stats(ohci_state_t *ohcip) 10862 { 10863 char kstatname[KSTAT_STRLEN]; 10864 const char *dname = ddi_driver_name(ohcip->ohci_dip); 10865 char *usbtypes[USB_N_COUNT_KSTATS] = 10866 {"ctrl", "isoch", "bulk", "intr"}; 10867 uint_t instance = ohcip->ohci_instance; 10868 ohci_intrs_stats_t *isp; 10869 int i; 10870 10871 if (OHCI_INTRS_STATS(ohcip) == NULL) { 10872 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 10873 dname, instance); 10874 OHCI_INTRS_STATS(ohcip) = kstat_create("usba", instance, 10875 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 10876 sizeof (ohci_intrs_stats_t) / sizeof (kstat_named_t), 10877 KSTAT_FLAG_PERSISTENT); 10878 10879 if (OHCI_INTRS_STATS(ohcip)) { 10880 isp = OHCI_INTRS_STATS_DATA(ohcip); 10881 kstat_named_init(&isp->ohci_hcr_intr_total, 10882 "Interrupts Total", KSTAT_DATA_UINT64); 10883 kstat_named_init(&isp->ohci_hcr_intr_not_claimed, 10884 "Not Claimed", KSTAT_DATA_UINT64); 10885 kstat_named_init(&isp->ohci_hcr_intr_so, 10886 "Schedule Overruns", KSTAT_DATA_UINT64); 10887 kstat_named_init(&isp->ohci_hcr_intr_wdh, 10888 "Writeback Done Head", KSTAT_DATA_UINT64); 10889 kstat_named_init(&isp->ohci_hcr_intr_sof, 10890 "Start Of Frame", KSTAT_DATA_UINT64); 10891 kstat_named_init(&isp->ohci_hcr_intr_rd, 10892 "Resume Detected", KSTAT_DATA_UINT64); 10893 kstat_named_init(&isp->ohci_hcr_intr_ue, 10894 "Unrecoverable Error", KSTAT_DATA_UINT64); 10895 kstat_named_init(&isp->ohci_hcr_intr_fno, 10896 "Frame No. Overflow", KSTAT_DATA_UINT64); 10897 kstat_named_init(&isp->ohci_hcr_intr_rhsc, 10898 "Root Hub Status Change", KSTAT_DATA_UINT64); 10899 kstat_named_init(&isp->ohci_hcr_intr_oc, 10900 "Change In Ownership", KSTAT_DATA_UINT64); 10901 10902 OHCI_INTRS_STATS(ohcip)->ks_private = ohcip; 10903 OHCI_INTRS_STATS(ohcip)->ks_update = nulldev; 10904 kstat_install(OHCI_INTRS_STATS(ohcip)); 10905 } 10906 } 10907 10908 if (OHCI_TOTAL_STATS(ohcip) == NULL) { 10909 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 10910 dname, instance); 10911 OHCI_TOTAL_STATS(ohcip) = kstat_create("usba", instance, 10912 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 10913 KSTAT_FLAG_PERSISTENT); 10914 10915 if (OHCI_TOTAL_STATS(ohcip)) { 10916 kstat_install(OHCI_TOTAL_STATS(ohcip)); 10917 } 10918 } 10919 10920 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 10921 if (ohcip->ohci_count_stats[i] == NULL) { 10922 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 10923 dname, instance, usbtypes[i]); 10924 ohcip->ohci_count_stats[i] = kstat_create("usba", 10925 instance, kstatname, "usb_byte_count", 10926 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 10927 10928 if (ohcip->ohci_count_stats[i]) { 10929 kstat_install(ohcip->ohci_count_stats[i]); 10930 } 10931 } 10932 } 10933 } 10934 10935 10936 /* 10937 * ohci_destroy_stats: 10938 * 10939 * Clean up ohci kstat structures 10940 */ 10941 static void 10942 ohci_destroy_stats(ohci_state_t *ohcip) 10943 { 10944 int i; 10945 10946 if (OHCI_INTRS_STATS(ohcip)) { 10947 kstat_delete(OHCI_INTRS_STATS(ohcip)); 10948 OHCI_INTRS_STATS(ohcip) = NULL; 10949 } 10950 10951 if (OHCI_TOTAL_STATS(ohcip)) { 10952 kstat_delete(OHCI_TOTAL_STATS(ohcip)); 10953 OHCI_TOTAL_STATS(ohcip) = NULL; 10954 } 10955 10956 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 10957 if (ohcip->ohci_count_stats[i]) { 10958 kstat_delete(ohcip->ohci_count_stats[i]); 10959 ohcip->ohci_count_stats[i] = NULL; 10960 } 10961 } 10962 } 10963 10964 10965 /* 10966 * ohci_do_intrs_stats: 10967 * 10968 * ohci status information 10969 */ 10970 static void 10971 ohci_do_intrs_stats( 10972 ohci_state_t *ohcip, 10973 int val) 10974 { 10975 if (OHCI_INTRS_STATS(ohcip)) { 10976 OHCI_INTRS_STATS_DATA(ohcip)->ohci_hcr_intr_total.value.ui64++; 10977 switch (val) { 10978 case HCR_INTR_SO: 10979 OHCI_INTRS_STATS_DATA(ohcip)-> 10980 ohci_hcr_intr_so.value.ui64++; 10981 break; 10982 case HCR_INTR_WDH: 10983 OHCI_INTRS_STATS_DATA(ohcip)-> 10984 ohci_hcr_intr_wdh.value.ui64++; 10985 break; 10986 case HCR_INTR_SOF: 10987 OHCI_INTRS_STATS_DATA(ohcip)-> 10988 ohci_hcr_intr_sof.value.ui64++; 10989 break; 10990 case HCR_INTR_RD: 10991 OHCI_INTRS_STATS_DATA(ohcip)-> 10992 ohci_hcr_intr_rd.value.ui64++; 10993 break; 10994 case HCR_INTR_UE: 10995 OHCI_INTRS_STATS_DATA(ohcip)-> 10996 ohci_hcr_intr_ue.value.ui64++; 10997 break; 10998 case HCR_INTR_FNO: 10999 OHCI_INTRS_STATS_DATA(ohcip)-> 11000 ohci_hcr_intr_fno.value.ui64++; 11001 break; 11002 case HCR_INTR_RHSC: 11003 OHCI_INTRS_STATS_DATA(ohcip)-> 11004 ohci_hcr_intr_rhsc.value.ui64++; 11005 break; 11006 case HCR_INTR_OC: 11007 OHCI_INTRS_STATS_DATA(ohcip)-> 11008 ohci_hcr_intr_oc.value.ui64++; 11009 break; 11010 default: 11011 OHCI_INTRS_STATS_DATA(ohcip)-> 11012 ohci_hcr_intr_not_claimed.value.ui64++; 11013 break; 11014 } 11015 } 11016 } 11017 11018 11019 /* 11020 * ohci_do_byte_stats: 11021 * 11022 * ohci data xfer information 11023 */ 11024 static void 11025 ohci_do_byte_stats( 11026 ohci_state_t *ohcip, 11027 size_t len, 11028 uint8_t attr, 11029 uint8_t addr) 11030 { 11031 uint8_t type = attr & USB_EP_ATTR_MASK; 11032 uint8_t dir = addr & USB_EP_DIR_MASK; 11033 11034 if (dir == USB_EP_DIR_IN) { 11035 OHCI_TOTAL_STATS_DATA(ohcip)->reads++; 11036 OHCI_TOTAL_STATS_DATA(ohcip)->nread += len; 11037 switch (type) { 11038 case USB_EP_ATTR_CONTROL: 11039 OHCI_CTRL_STATS(ohcip)->reads++; 11040 OHCI_CTRL_STATS(ohcip)->nread += len; 11041 break; 11042 case USB_EP_ATTR_BULK: 11043 OHCI_BULK_STATS(ohcip)->reads++; 11044 OHCI_BULK_STATS(ohcip)->nread += len; 11045 break; 11046 case USB_EP_ATTR_INTR: 11047 OHCI_INTR_STATS(ohcip)->reads++; 11048 OHCI_INTR_STATS(ohcip)->nread += len; 11049 break; 11050 case USB_EP_ATTR_ISOCH: 11051 OHCI_ISOC_STATS(ohcip)->reads++; 11052 OHCI_ISOC_STATS(ohcip)->nread += len; 11053 break; 11054 } 11055 } else if (dir == USB_EP_DIR_OUT) { 11056 OHCI_TOTAL_STATS_DATA(ohcip)->writes++; 11057 OHCI_TOTAL_STATS_DATA(ohcip)->nwritten += len; 11058 switch (type) { 11059 case USB_EP_ATTR_CONTROL: 11060 OHCI_CTRL_STATS(ohcip)->writes++; 11061 OHCI_CTRL_STATS(ohcip)->nwritten += len; 11062 break; 11063 case USB_EP_ATTR_BULK: 11064 OHCI_BULK_STATS(ohcip)->writes++; 11065 OHCI_BULK_STATS(ohcip)->nwritten += len; 11066 break; 11067 case USB_EP_ATTR_INTR: 11068 OHCI_INTR_STATS(ohcip)->writes++; 11069 OHCI_INTR_STATS(ohcip)->nwritten += len; 11070 break; 11071 case USB_EP_ATTR_ISOCH: 11072 OHCI_ISOC_STATS(ohcip)->writes++; 11073 OHCI_ISOC_STATS(ohcip)->nwritten += len; 11074 break; 11075 } 11076 } 11077 } 11078 11079 11080 /* 11081 * ohci_print_op_regs: 11082 * 11083 * Print Host Controller's (HC) Operational registers. 11084 */ 11085 static void 11086 ohci_print_op_regs(ohci_state_t *ohcip) 11087 { 11088 uint_t i; 11089 11090 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11091 "\n\tOHCI%d Operational Registers\n", 11092 ddi_get_instance(ohcip->ohci_dip)); 11093 11094 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11095 "\thcr_revision: 0x%x \t\thcr_control: 0x%x", 11096 Get_OpReg(hcr_revision), Get_OpReg(hcr_control)); 11097 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11098 "\thcr_cmd_status: 0x%x \t\thcr_intr_enable: 0x%x", 11099 Get_OpReg(hcr_cmd_status), Get_OpReg(hcr_intr_enable)); 11100 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11101 "\thcr_intr_disable: 0x%x \thcr_HCCA: 0x%x", 11102 Get_OpReg(hcr_intr_disable), Get_OpReg(hcr_HCCA)); 11103 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11104 "\thcr_periodic_curr: 0x%x \t\thcr_ctrl_head: 0x%x", 11105 Get_OpReg(hcr_periodic_curr), Get_OpReg(hcr_ctrl_head)); 11106 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11107 "\thcr_ctrl_curr: 0x%x \t\thcr_bulk_head: 0x%x", 11108 Get_OpReg(hcr_ctrl_curr), Get_OpReg(hcr_bulk_head)); 11109 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11110 "\thcr_bulk_curr: 0x%x \t\thcr_done_head: 0x%x", 11111 Get_OpReg(hcr_bulk_curr), Get_OpReg(hcr_done_head)); 11112 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11113 "\thcr_frame_interval: 0x%x " 11114 "\thcr_frame_remaining: 0x%x", Get_OpReg(hcr_frame_interval), 11115 Get_OpReg(hcr_frame_remaining)); 11116 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11117 "\thcr_frame_number: 0x%x \thcr_periodic_strt: 0x%x", 11118 Get_OpReg(hcr_frame_number), Get_OpReg(hcr_periodic_strt)); 11119 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11120 "\thcr_transfer_ls: 0x%x \t\thcr_rh_descriptorA: 0x%x", 11121 Get_OpReg(hcr_transfer_ls), Get_OpReg(hcr_rh_descriptorA)); 11122 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11123 "\thcr_rh_descriptorB: 0x%x \thcr_rh_status: 0x%x", 11124 Get_OpReg(hcr_rh_descriptorB), Get_OpReg(hcr_rh_status)); 11125 11126 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11127 "\tRoot hub port status"); 11128 11129 for (i = 0; i < (Get_OpReg(hcr_rh_descriptorA) & HCR_RHA_NDP); i++) { 11130 USB_DPRINTF_L3(PRINT_MASK_ATTA, ohcip->ohci_log_hdl, 11131 "\thcr_rh_portstatus 0x%x: 0x%x ", i, 11132 Get_OpReg(hcr_rh_portstatus[i])); 11133 } 11134 } 11135 11136 11137 /* 11138 * ohci_print_ed: 11139 */ 11140 static void 11141 ohci_print_ed( 11142 ohci_state_t *ohcip, 11143 ohci_ed_t *ed) 11144 { 11145 uint_t ctrl = Get_ED(ed->hced_ctrl); 11146 11147 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11148 "ohci_print_ed: ed = 0x%p", (void *)ed); 11149 11150 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11151 "\thced_ctrl: 0x%x %s", ctrl, 11152 ((Get_ED(ed->hced_headp) & HC_EPT_Halt) ? "halted": "")); 11153 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11154 "\ttoggle carry: 0x%x", Get_ED(ed->hced_headp) & HC_EPT_Carry); 11155 11156 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11157 "\tctrl: 0x%x", Get_ED(ed->hced_ctrl)); 11158 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11159 "\ttailp: 0x%x", Get_ED(ed->hced_tailp)); 11160 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11161 "\theadp: 0x%x", Get_ED(ed->hced_headp)); 11162 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11163 "\tnext: 0x%x", Get_ED(ed->hced_next)); 11164 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11165 "\tprev: 0x%x", Get_ED(ed->hced_prev)); 11166 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11167 "\tnode: 0x%x", Get_ED(ed->hced_node)); 11168 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11169 "\treclaim_next: 0x%x", Get_ED(ed->hced_reclaim_next)); 11170 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11171 "\treclaim_frame: 0x%x", Get_ED(ed->hced_reclaim_frame)); 11172 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11173 "\tstate: 0x%x", Get_ED(ed->hced_state)); 11174 } 11175 11176 11177 /* 11178 * ohci_print_td: 11179 */ 11180 static void 11181 ohci_print_td( 11182 ohci_state_t *ohcip, 11183 ohci_td_t *td) 11184 { 11185 uint_t i; 11186 uint_t ctrl = Get_TD(td->hctd_ctrl); 11187 11188 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11189 "ohci_print_td: td = 0x%p", (void *)td); 11190 11191 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11192 "\tPID: 0x%x ", ctrl & HC_TD_PID); 11193 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11194 "\tDelay Intr: 0x%x ", ctrl & HC_TD_DI); 11195 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11196 "\tData Toggle: 0x%x ", ctrl & HC_TD_DT); 11197 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11198 "\tError Count: 0x%x ", ctrl & HC_TD_EC); 11199 11200 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11201 "\tctrl: 0x%x ", Get_TD(td->hctd_ctrl)); 11202 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11203 "\tcbp: 0x%x ", Get_TD(td->hctd_cbp)); 11204 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11205 "\tnext_td: 0x%x ", Get_TD(td->hctd_next_td)); 11206 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11207 "\tbuf_end: 0x%x ", Get_TD(td->hctd_buf_end)); 11208 11209 for (i = 0; i < 4; i++) { 11210 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11211 "\toffset[%d]: 0x%x ", i, Get_TD(td->hctd_offsets[i])); 11212 } 11213 11214 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11215 "\ttrans_wrapper: 0x%x ", Get_TD(td->hctd_trans_wrapper)); 11216 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11217 "\tstate: 0x%x ", Get_TD(td->hctd_state)); 11218 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11219 "\ttw_next_td: 0x%x ", Get_TD(td->hctd_tw_next_td)); 11220 USB_DPRINTF_L3(PRINT_MASK_LISTS, ohcip->ohci_log_hdl, 11221 "\tctrl_phase: 0x%x ", Get_TD(td->hctd_ctrl_phase)); 11222 } 11223