1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27 /* 28 * EHCI Host Controller Driver (EHCI) 29 * 30 * The EHCI driver is a software driver which interfaces to the Universal 31 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 32 * the Host Controller is defined by the EHCI Host Controller Interface. 33 * 34 * This module contains the main EHCI driver code which handles all USB 35 * transfers, bandwidth allocations and other general functionalities. 36 */ 37 38 #include <sys/usb/hcd/ehci/ehcid.h> 39 #include <sys/usb/hcd/ehci/ehci_isoch.h> 40 #include <sys/usb/hcd/ehci/ehci_xfer.h> 41 42 /* 43 * EHCI MSI tunable: 44 * 45 * By default MSI is enabled on all supported platforms except for the 46 * EHCI controller of ULI1575 South bridge. 47 */ 48 boolean_t ehci_enable_msi = B_TRUE; 49 50 /* Pointer to the state structure */ 51 extern void *ehci_statep; 52 53 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 54 55 extern uint_t ehci_vt62x2_workaround; 56 extern int force_ehci_off; 57 58 /* Adjustable variables for the size of the pools */ 59 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 60 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 61 62 /* 63 * Initialize the values which the order of 32ms intr qh are executed 64 * by the host controller in the lattice tree. 65 */ 66 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 67 {0x00, 0x10, 0x08, 0x18, 68 0x04, 0x14, 0x0c, 0x1c, 69 0x02, 0x12, 0x0a, 0x1a, 70 0x06, 0x16, 0x0e, 0x1e, 71 0x01, 0x11, 0x09, 0x19, 72 0x05, 0x15, 0x0d, 0x1d, 73 0x03, 0x13, 0x0b, 0x1b, 74 0x07, 0x17, 0x0f, 0x1f}; 75 76 /* 77 * Initialize the values which are used to calculate start split mask 78 * for the low/full/high speed interrupt and isochronous endpoints. 79 */ 80 static uint_t ehci_start_split_mask[15] = { 81 /* 82 * For high/full/low speed usb devices. For high speed 83 * device with polling interval greater than or equal 84 * to 8us (125us). 85 */ 86 0x01, /* 00000001 */ 87 0x02, /* 00000010 */ 88 0x04, /* 00000100 */ 89 0x08, /* 00001000 */ 90 0x10, /* 00010000 */ 91 0x20, /* 00100000 */ 92 0x40, /* 01000000 */ 93 0x80, /* 10000000 */ 94 95 /* Only for high speed devices with polling interval 4us */ 96 0x11, /* 00010001 */ 97 0x22, /* 00100010 */ 98 0x44, /* 01000100 */ 99 0x88, /* 10001000 */ 100 101 /* Only for high speed devices with polling interval 2us */ 102 0x55, /* 01010101 */ 103 0xaa, /* 10101010 */ 104 105 /* Only for high speed devices with polling interval 1us */ 106 0xff /* 11111111 */ 107 }; 108 109 /* 110 * Initialize the values which are used to calculate complete split mask 111 * for the low/full speed interrupt and isochronous endpoints. 112 */ 113 static uint_t ehci_intr_complete_split_mask[7] = { 114 /* Only full/low speed devices */ 115 0x1c, /* 00011100 */ 116 0x38, /* 00111000 */ 117 0x70, /* 01110000 */ 118 0xe0, /* 11100000 */ 119 0x00, /* Need FSTN feature */ 120 0x00, /* Need FSTN feature */ 121 0x00 /* Need FSTN feature */ 122 }; 123 124 125 /* 126 * EHCI Internal Function Prototypes 127 */ 128 129 /* Host Controller Driver (HCD) initialization functions */ 130 void ehci_set_dma_attributes(ehci_state_t *ehcip); 131 int ehci_allocate_pools(ehci_state_t *ehcip); 132 void ehci_decode_ddi_dma_addr_bind_handle_result( 133 ehci_state_t *ehcip, 134 int result); 135 int ehci_map_regs(ehci_state_t *ehcip); 136 int ehci_register_intrs_and_init_mutex( 137 ehci_state_t *ehcip); 138 static int ehci_add_intrs(ehci_state_t *ehcip, 139 int intr_type); 140 int ehci_init_ctlr(ehci_state_t *ehcip, 141 int init_type); 142 static int ehci_take_control(ehci_state_t *ehcip); 143 static int ehci_init_periodic_frame_lst_table( 144 ehci_state_t *ehcip); 145 static void ehci_build_interrupt_lattice( 146 ehci_state_t *ehcip); 147 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 148 149 /* Host Controller Driver (HCD) deinitialization functions */ 150 int ehci_cleanup(ehci_state_t *ehcip); 151 static void ehci_rem_intrs(ehci_state_t *ehcip); 152 int ehci_cpr_suspend(ehci_state_t *ehcip); 153 int ehci_cpr_resume(ehci_state_t *ehcip); 154 155 /* Bandwidth Allocation functions */ 156 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 157 usba_pipe_handle_data_t *ph, 158 uint_t *pnode, 159 uchar_t *smask, 160 uchar_t *cmask); 161 static int ehci_allocate_high_speed_bandwidth( 162 ehci_state_t *ehcip, 163 usba_pipe_handle_data_t *ph, 164 uint_t *hnode, 165 uchar_t *smask, 166 uchar_t *cmask); 167 static int ehci_allocate_classic_tt_bandwidth( 168 ehci_state_t *ehcip, 169 usba_pipe_handle_data_t *ph, 170 uint_t pnode); 171 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 172 usba_pipe_handle_data_t *ph, 173 uint_t pnode, 174 uchar_t smask, 175 uchar_t cmask); 176 static void ehci_deallocate_high_speed_bandwidth( 177 ehci_state_t *ehcip, 178 usba_pipe_handle_data_t *ph, 179 uint_t hnode, 180 uchar_t smask, 181 uchar_t cmask); 182 static void ehci_deallocate_classic_tt_bandwidth( 183 ehci_state_t *ehcip, 184 usba_pipe_handle_data_t *ph, 185 uint_t pnode); 186 static int ehci_compute_high_speed_bandwidth( 187 ehci_state_t *ehcip, 188 usb_ep_descr_t *endpoint, 189 usb_port_status_t port_status, 190 uint_t *sbandwidth, 191 uint_t *cbandwidth); 192 static int ehci_compute_classic_bandwidth( 193 usb_ep_descr_t *endpoint, 194 usb_port_status_t port_status, 195 uint_t *bandwidth); 196 int ehci_adjust_polling_interval( 197 ehci_state_t *ehcip, 198 usb_ep_descr_t *endpoint, 199 usb_port_status_t port_status); 200 static int ehci_adjust_high_speed_polling_interval( 201 ehci_state_t *ehcip, 202 usb_ep_descr_t *endpoint); 203 static uint_t ehci_lattice_height(uint_t interval); 204 static uint_t ehci_lattice_parent(uint_t node); 205 static uint_t ehci_find_periodic_node( 206 uint_t leaf, 207 int interval); 208 static uint_t ehci_leftmost_leaf(uint_t node, 209 uint_t height); 210 static uint_t ehci_pow_2(uint_t x); 211 static uint_t ehci_log_2(uint_t x); 212 static int ehci_find_bestfit_hs_mask( 213 ehci_state_t *ehcip, 214 uchar_t *smask, 215 uint_t *pnode, 216 usb_ep_descr_t *endpoint, 217 uint_t bandwidth, 218 int interval); 219 static int ehci_find_bestfit_ls_intr_mask( 220 ehci_state_t *ehcip, 221 uchar_t *smask, 222 uchar_t *cmask, 223 uint_t *pnode, 224 uint_t sbandwidth, 225 uint_t cbandwidth, 226 int interval); 227 static int ehci_find_bestfit_sitd_in_mask( 228 ehci_state_t *ehcip, 229 uchar_t *smask, 230 uchar_t *cmask, 231 uint_t *pnode, 232 uint_t sbandwidth, 233 uint_t cbandwidth, 234 int interval); 235 static int ehci_find_bestfit_sitd_out_mask( 236 ehci_state_t *ehcip, 237 uchar_t *smask, 238 uint_t *pnode, 239 uint_t sbandwidth, 240 int interval); 241 static uint_t ehci_calculate_bw_availability_mask( 242 ehci_state_t *ehcip, 243 uint_t bandwidth, 244 int leaf, 245 int leaf_count, 246 uchar_t *bw_mask); 247 static void ehci_update_bw_availability( 248 ehci_state_t *ehcip, 249 int bandwidth, 250 int leftmost_leaf, 251 int leaf_count, 252 uchar_t mask); 253 254 /* Miscellaneous functions */ 255 ehci_state_t *ehci_obtain_state( 256 dev_info_t *dip); 257 int ehci_state_is_operational( 258 ehci_state_t *ehcip); 259 int ehci_do_soft_reset( 260 ehci_state_t *ehcip); 261 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 262 ehci_pipe_private_t *pp, 263 ehci_trans_wrapper_t *tw); 264 usb_frame_number_t ehci_get_current_frame_number( 265 ehci_state_t *ehcip); 266 static void ehci_cpr_cleanup( 267 ehci_state_t *ehcip); 268 int ehci_wait_for_sof( 269 ehci_state_t *ehcip); 270 void ehci_toggle_scheduler( 271 ehci_state_t *ehcip); 272 void ehci_print_caps(ehci_state_t *ehcip); 273 void ehci_print_regs(ehci_state_t *ehcip); 274 void ehci_print_qh(ehci_state_t *ehcip, 275 ehci_qh_t *qh); 276 void ehci_print_qtd(ehci_state_t *ehcip, 277 ehci_qtd_t *qtd); 278 void ehci_create_stats(ehci_state_t *ehcip); 279 void ehci_destroy_stats(ehci_state_t *ehcip); 280 void ehci_do_intrs_stats(ehci_state_t *ehcip, 281 int val); 282 void ehci_do_byte_stats(ehci_state_t *ehcip, 283 size_t len, 284 uint8_t attr, 285 uint8_t addr); 286 287 /* 288 * check if this ehci controller can support PM 289 */ 290 int 291 ehci_hcdi_pm_support(dev_info_t *dip) 292 { 293 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 294 ddi_get_instance(dip)); 295 296 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 297 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 298 299 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 300 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 301 302 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 303 304 return (USB_SUCCESS); 305 } 306 307 return (USB_FAILURE); 308 } 309 310 void 311 ehci_dma_attr_workaround(ehci_state_t *ehcip) 312 { 313 /* 314 * Some Nvidia chips can not handle qh dma address above 2G. 315 * The bit 31 of the dma address might be omitted and it will 316 * cause system crash or other unpredicable result. So force 317 * the dma address allocated below 2G to make ehci work. 318 */ 319 if (PCI_VENDOR_NVIDIA == ehcip->ehci_vendor_id) { 320 switch (ehcip->ehci_device_id) { 321 case PCI_DEVICE_NVIDIA_CK804: 322 case PCI_DEVICE_NVIDIA_MCP04: 323 USB_DPRINTF_L2(PRINT_MASK_ATTA, 324 ehcip->ehci_log_hdl, 325 "ehci_dma_attr_workaround: NVIDIA dma " 326 "workaround enabled, force dma address " 327 "to be allocated below 2G"); 328 ehcip->ehci_dma_attr.dma_attr_addr_hi = 329 0x7fffffffull; 330 break; 331 default: 332 break; 333 334 } 335 } 336 } 337 338 /* 339 * Host Controller Driver (HCD) initialization functions 340 */ 341 342 /* 343 * ehci_set_dma_attributes: 344 * 345 * Set the limits in the DMA attributes structure. Most of the values used 346 * in the DMA limit structures are the default values as specified by the 347 * Writing PCI device drivers document. 348 */ 349 void 350 ehci_set_dma_attributes(ehci_state_t *ehcip) 351 { 352 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 353 "ehci_set_dma_attributes:"); 354 355 /* Initialize the DMA attributes */ 356 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 357 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 358 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 359 360 /* 32 bit addressing */ 361 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 362 363 /* Byte alignment */ 364 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 365 366 /* 367 * Since PCI specification is byte alignment, the 368 * burst size field should be set to 1 for PCI devices. 369 */ 370 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 371 372 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 373 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 374 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 375 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 376 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 377 ehcip->ehci_dma_attr.dma_attr_flags = 0; 378 ehci_dma_attr_workaround(ehcip); 379 } 380 381 382 /* 383 * ehci_allocate_pools: 384 * 385 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 386 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 387 * to a 16 byte boundary. 388 */ 389 int 390 ehci_allocate_pools(ehci_state_t *ehcip) 391 { 392 ddi_device_acc_attr_t dev_attr; 393 size_t real_length; 394 int result; 395 uint_t ccount; 396 int i; 397 398 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 399 "ehci_allocate_pools:"); 400 401 /* The host controller will be little endian */ 402 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 403 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 404 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 405 406 /* Byte alignment */ 407 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 408 409 /* Allocate the QTD pool DMA handle */ 410 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 411 DDI_DMA_SLEEP, 0, 412 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 413 414 goto failure; 415 } 416 417 /* Allocate the memory for the QTD pool */ 418 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 419 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 420 &dev_attr, 421 DDI_DMA_CONSISTENT, 422 DDI_DMA_SLEEP, 423 0, 424 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 425 &real_length, 426 &ehcip->ehci_qtd_pool_mem_handle)) { 427 428 goto failure; 429 } 430 431 /* Map the QTD pool into the I/O address space */ 432 result = ddi_dma_addr_bind_handle( 433 ehcip->ehci_qtd_pool_dma_handle, 434 NULL, 435 (caddr_t)ehcip->ehci_qtd_pool_addr, 436 real_length, 437 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 438 DDI_DMA_SLEEP, 439 NULL, 440 &ehcip->ehci_qtd_pool_cookie, 441 &ccount); 442 443 bzero((void *)ehcip->ehci_qtd_pool_addr, 444 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 445 446 /* Process the result */ 447 if (result == DDI_DMA_MAPPED) { 448 /* The cookie count should be 1 */ 449 if (ccount != 1) { 450 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 451 "ehci_allocate_pools: More than 1 cookie"); 452 453 goto failure; 454 } 455 } else { 456 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 457 "ehci_allocate_pools: Result = %d", result); 458 459 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 460 461 goto failure; 462 } 463 464 /* 465 * DMA addresses for QTD pools are bound 466 */ 467 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 468 469 /* Initialize the QTD pool */ 470 for (i = 0; i < ehci_qtd_pool_size; i ++) { 471 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 472 qtd_state, EHCI_QTD_FREE); 473 } 474 475 /* Allocate the QTD pool DMA handle */ 476 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 477 &ehcip->ehci_dma_attr, 478 DDI_DMA_SLEEP, 479 0, 480 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 481 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 482 "ehci_allocate_pools: ddi_dma_alloc_handle failed"); 483 484 goto failure; 485 } 486 487 /* Allocate the memory for the QH pool */ 488 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 489 ehci_qh_pool_size * sizeof (ehci_qh_t), 490 &dev_attr, 491 DDI_DMA_CONSISTENT, 492 DDI_DMA_SLEEP, 493 0, 494 (caddr_t *)&ehcip->ehci_qh_pool_addr, 495 &real_length, 496 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 497 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 498 "ehci_allocate_pools: ddi_dma_mem_alloc failed"); 499 500 goto failure; 501 } 502 503 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 504 NULL, 505 (caddr_t)ehcip->ehci_qh_pool_addr, 506 real_length, 507 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 508 DDI_DMA_SLEEP, 509 NULL, 510 &ehcip->ehci_qh_pool_cookie, 511 &ccount); 512 513 bzero((void *)ehcip->ehci_qh_pool_addr, 514 ehci_qh_pool_size * sizeof (ehci_qh_t)); 515 516 /* Process the result */ 517 if (result == DDI_DMA_MAPPED) { 518 /* The cookie count should be 1 */ 519 if (ccount != 1) { 520 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 521 "ehci_allocate_pools: More than 1 cookie"); 522 523 goto failure; 524 } 525 } else { 526 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 527 528 goto failure; 529 } 530 531 /* 532 * DMA addresses for QH pools are bound 533 */ 534 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 535 536 /* Initialize the QH pool */ 537 for (i = 0; i < ehci_qh_pool_size; i ++) { 538 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 539 } 540 541 /* Byte alignment */ 542 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 543 544 return (DDI_SUCCESS); 545 546 failure: 547 /* Byte alignment */ 548 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 549 550 return (DDI_FAILURE); 551 } 552 553 554 /* 555 * ehci_decode_ddi_dma_addr_bind_handle_result: 556 * 557 * Process the return values of ddi_dma_addr_bind_handle() 558 */ 559 void 560 ehci_decode_ddi_dma_addr_bind_handle_result( 561 ehci_state_t *ehcip, 562 int result) 563 { 564 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 565 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 566 567 switch (result) { 568 case DDI_DMA_PARTIAL_MAP: 569 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 570 "Partial transfers not allowed"); 571 break; 572 case DDI_DMA_INUSE: 573 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 574 "Handle is in use"); 575 break; 576 case DDI_DMA_NORESOURCES: 577 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 578 "No resources"); 579 break; 580 case DDI_DMA_NOMAPPING: 581 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 582 "No mapping"); 583 break; 584 case DDI_DMA_TOOBIG: 585 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 586 "Object is too big"); 587 break; 588 default: 589 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 590 "Unknown dma error"); 591 } 592 } 593 594 595 /* 596 * ehci_map_regs: 597 * 598 * The Host Controller (HC) contains a set of on-chip operational registers 599 * and which should be mapped into a non-cacheable portion of the system 600 * addressable space. 601 */ 602 int 603 ehci_map_regs(ehci_state_t *ehcip) 604 { 605 ddi_device_acc_attr_t attr; 606 uint16_t cmd_reg; 607 uint_t length; 608 609 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 610 611 /* Check to make sure we have memory access */ 612 if (pci_config_setup(ehcip->ehci_dip, 613 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 614 615 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 616 "ehci_map_regs: Config error"); 617 618 return (DDI_FAILURE); 619 } 620 621 /* Make sure Memory Access Enable is set */ 622 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 623 624 if (!(cmd_reg & PCI_COMM_MAE)) { 625 626 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 627 "ehci_map_regs: Memory base address access disabled"); 628 629 return (DDI_FAILURE); 630 } 631 632 /* The host controller will be little endian */ 633 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 634 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 635 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 636 637 /* Map in EHCI Capability registers */ 638 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 639 (caddr_t *)&ehcip->ehci_capsp, 0, 640 sizeof (ehci_caps_t), &attr, 641 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 642 643 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 644 "ehci_map_regs: Map setup error"); 645 646 return (DDI_FAILURE); 647 } 648 649 length = ddi_get8(ehcip->ehci_caps_handle, 650 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 651 652 /* Free the original mapping */ 653 ddi_regs_map_free(&ehcip->ehci_caps_handle); 654 655 /* Re-map in EHCI Capability and Operational registers */ 656 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 657 (caddr_t *)&ehcip->ehci_capsp, 0, 658 length + sizeof (ehci_regs_t), &attr, 659 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 660 661 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 662 "ehci_map_regs: Map setup error"); 663 664 return (DDI_FAILURE); 665 } 666 667 /* Get the pointer to EHCI Operational Register */ 668 ehcip->ehci_regsp = (ehci_regs_t *) 669 ((uintptr_t)ehcip->ehci_capsp + length); 670 671 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 672 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 673 (void *)ehcip->ehci_capsp, (void *)ehcip->ehci_regsp); 674 675 return (DDI_SUCCESS); 676 } 677 678 /* 679 * The following simulated polling is for debugging purposes only. 680 * It is activated on x86 by setting usb-polling=true in GRUB or ehci.conf. 681 */ 682 static int 683 ehci_is_polled(dev_info_t *dip) 684 { 685 int ret; 686 char *propval; 687 688 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 689 "usb-polling", &propval) != DDI_SUCCESS) 690 691 return (0); 692 693 ret = (strcmp(propval, "true") == 0); 694 ddi_prop_free(propval); 695 696 return (ret); 697 } 698 699 static void 700 ehci_poll_intr(void *arg) 701 { 702 /* poll every msec */ 703 for (;;) { 704 (void) ehci_intr(arg, NULL); 705 delay(drv_usectohz(1000)); 706 } 707 } 708 709 /* 710 * ehci_register_intrs_and_init_mutex: 711 * 712 * Register interrupts and initialize each mutex and condition variables 713 */ 714 int 715 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 716 { 717 int intr_types; 718 719 #if defined(__x86) 720 uint8_t iline; 721 #endif 722 723 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 724 "ehci_register_intrs_and_init_mutex:"); 725 726 /* 727 * There is a known MSI hardware bug with the EHCI controller 728 * of ULI1575 southbridge. Hence MSI is disabled for this chip. 729 */ 730 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 731 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) { 732 ehcip->ehci_msi_enabled = B_FALSE; 733 } else { 734 /* Set the MSI enable flag from the global EHCI MSI tunable */ 735 ehcip->ehci_msi_enabled = ehci_enable_msi; 736 } 737 738 /* launch polling thread instead of enabling pci interrupt */ 739 if (ehci_is_polled(ehcip->ehci_dip)) { 740 extern pri_t maxclsyspri; 741 742 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 743 "ehci_register_intrs_and_init_mutex: " 744 "running in simulated polled mode"); 745 746 (void) thread_create(NULL, 0, ehci_poll_intr, ehcip, 0, &p0, 747 TS_RUN, maxclsyspri); 748 749 goto skip_intr; 750 } 751 752 #if defined(__x86) 753 /* 754 * Make sure that the interrupt pin is connected to the 755 * interrupt controller on x86. Interrupt line 255 means 756 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 757 * If we would return failure when interrupt line equals 255, then 758 * high speed devices will be routed to companion host controllers. 759 * However, it is not necessary to return failure here, and 760 * o/uhci codes don't check the interrupt line either. 761 * But it's good to log a message here for debug purposes. 762 */ 763 iline = pci_config_get8(ehcip->ehci_config_handle, 764 PCI_CONF_ILINE); 765 766 if (iline == 255) { 767 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 768 "ehci_register_intrs_and_init_mutex: " 769 "interrupt line value out of range (%d)", 770 iline); 771 } 772 #endif /* __x86 */ 773 774 /* Get supported interrupt types */ 775 if (ddi_intr_get_supported_types(ehcip->ehci_dip, 776 &intr_types) != DDI_SUCCESS) { 777 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 778 "ehci_register_intrs_and_init_mutex: " 779 "ddi_intr_get_supported_types failed"); 780 781 return (DDI_FAILURE); 782 } 783 784 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 785 "ehci_register_intrs_and_init_mutex: " 786 "supported interrupt types 0x%x", intr_types); 787 788 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) { 789 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI) 790 != DDI_SUCCESS) { 791 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 792 "ehci_register_intrs_and_init_mutex: MSI " 793 "registration failed, trying FIXED interrupt \n"); 794 } else { 795 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 796 "ehci_register_intrs_and_init_mutex: " 797 "Using MSI interrupt type\n"); 798 799 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI; 800 ehcip->ehci_flags |= EHCI_INTR; 801 } 802 } 803 804 if ((!(ehcip->ehci_flags & EHCI_INTR)) && 805 (intr_types & DDI_INTR_TYPE_FIXED)) { 806 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED) 807 != DDI_SUCCESS) { 808 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 809 "ehci_register_intrs_and_init_mutex: " 810 "FIXED interrupt registration failed\n"); 811 812 return (DDI_FAILURE); 813 } 814 815 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 816 "ehci_register_intrs_and_init_mutex: " 817 "Using FIXED interrupt type\n"); 818 819 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED; 820 ehcip->ehci_flags |= EHCI_INTR; 821 } 822 823 skip_intr: 824 /* Create prototype for advance on async schedule */ 825 cv_init(&ehcip->ehci_async_schedule_advance_cv, 826 NULL, CV_DRIVER, NULL); 827 828 return (DDI_SUCCESS); 829 } 830 831 832 /* 833 * ehci_add_intrs: 834 * 835 * Register FIXED or MSI interrupts. 836 */ 837 static int 838 ehci_add_intrs(ehci_state_t *ehcip, 839 int intr_type) 840 { 841 int actual, avail, intr_size, count = 0; 842 int i, flag, ret; 843 844 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 845 "ehci_add_intrs: interrupt type 0x%x", intr_type); 846 847 /* Get number of interrupts */ 848 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count); 849 if ((ret != DDI_SUCCESS) || (count == 0)) { 850 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 851 "ehci_add_intrs: ddi_intr_get_nintrs() failure, " 852 "ret: %d, count: %d", ret, count); 853 854 return (DDI_FAILURE); 855 } 856 857 /* Get number of available interrupts */ 858 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail); 859 if ((ret != DDI_SUCCESS) || (avail == 0)) { 860 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 861 "ehci_add_intrs: ddi_intr_get_navail() failure, " 862 "ret: %d, count: %d", ret, count); 863 864 return (DDI_FAILURE); 865 } 866 867 if (avail < count) { 868 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 869 "ehci_add_intrs: ehci_add_intrs: nintrs () " 870 "returned %d, navail returned %d\n", count, avail); 871 } 872 873 /* Allocate an array of interrupt handles */ 874 intr_size = count * sizeof (ddi_intr_handle_t); 875 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP); 876 877 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 878 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 879 880 /* call ddi_intr_alloc() */ 881 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 882 intr_type, 0, count, &actual, flag); 883 884 if ((ret != DDI_SUCCESS) || (actual == 0)) { 885 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 886 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret); 887 888 kmem_free(ehcip->ehci_htable, intr_size); 889 890 return (DDI_FAILURE); 891 } 892 893 if (actual < count) { 894 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 895 "ehci_add_intrs: Requested: %d, Received: %d\n", 896 count, actual); 897 898 for (i = 0; i < actual; i++) 899 (void) ddi_intr_free(ehcip->ehci_htable[i]); 900 901 kmem_free(ehcip->ehci_htable, intr_size); 902 903 return (DDI_FAILURE); 904 } 905 906 ehcip->ehci_intr_cnt = actual; 907 908 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0], 909 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) { 910 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 911 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret); 912 913 for (i = 0; i < actual; i++) 914 (void) ddi_intr_free(ehcip->ehci_htable[i]); 915 916 kmem_free(ehcip->ehci_htable, intr_size); 917 918 return (DDI_FAILURE); 919 } 920 921 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 922 "ehci_add_intrs: Supported Interrupt priority 0x%x", 923 ehcip->ehci_intr_pri); 924 925 /* Test for high level mutex */ 926 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 927 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 928 "ehci_add_intrs: Hi level interrupt not supported"); 929 930 for (i = 0; i < actual; i++) 931 (void) ddi_intr_free(ehcip->ehci_htable[i]); 932 933 kmem_free(ehcip->ehci_htable, intr_size); 934 935 return (DDI_FAILURE); 936 } 937 938 /* Initialize the mutex */ 939 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 940 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 941 942 /* Call ddi_intr_add_handler() */ 943 for (i = 0; i < actual; i++) { 944 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i], 945 ehci_intr, (caddr_t)ehcip, 946 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 947 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 948 "ehci_add_intrs:ddi_intr_add_handler() " 949 "failed %d", ret); 950 951 for (i = 0; i < actual; i++) 952 (void) ddi_intr_free(ehcip->ehci_htable[i]); 953 954 mutex_destroy(&ehcip->ehci_int_mutex); 955 kmem_free(ehcip->ehci_htable, intr_size); 956 957 return (DDI_FAILURE); 958 } 959 } 960 961 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0], 962 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) { 963 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 964 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret); 965 966 for (i = 0; i < actual; i++) { 967 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 968 (void) ddi_intr_free(ehcip->ehci_htable[i]); 969 } 970 971 mutex_destroy(&ehcip->ehci_int_mutex); 972 kmem_free(ehcip->ehci_htable, intr_size); 973 974 return (DDI_FAILURE); 975 } 976 977 /* Enable all interrupts */ 978 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 979 /* Call ddi_intr_block_enable() for MSI interrupts */ 980 (void) ddi_intr_block_enable(ehcip->ehci_htable, 981 ehcip->ehci_intr_cnt); 982 } else { 983 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 984 for (i = 0; i < ehcip->ehci_intr_cnt; i++) 985 (void) ddi_intr_enable(ehcip->ehci_htable[i]); 986 } 987 988 return (DDI_SUCCESS); 989 } 990 991 992 /* 993 * ehci_init_hardware 994 * 995 * take control from BIOS, reset EHCI host controller, and check version, etc. 996 */ 997 int 998 ehci_init_hardware(ehci_state_t *ehcip) 999 { 1000 int revision; 1001 uint16_t cmd_reg; 1002 int abort_on_BIOS_take_over_failure; 1003 1004 /* Take control from the BIOS */ 1005 if (ehci_take_control(ehcip) != USB_SUCCESS) { 1006 1007 /* read .conf file properties */ 1008 abort_on_BIOS_take_over_failure = 1009 ddi_prop_get_int(DDI_DEV_T_ANY, 1010 ehcip->ehci_dip, DDI_PROP_DONTPASS, 1011 "abort-on-BIOS-take-over-failure", 0); 1012 1013 if (abort_on_BIOS_take_over_failure) { 1014 1015 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1016 "Unable to take control from BIOS."); 1017 1018 return (DDI_FAILURE); 1019 } 1020 1021 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1022 "Unable to take control from BIOS. Failure is ignored."); 1023 } 1024 1025 /* set Memory Master Enable */ 1026 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 1027 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 1028 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 1029 1030 /* Reset the EHCI host controller */ 1031 Set_OpReg(ehci_command, 1032 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 1033 1034 /* Wait 10ms for reset to complete */ 1035 drv_usecwait(EHCI_RESET_TIMEWAIT); 1036 1037 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 1038 1039 /* Verify the version number */ 1040 revision = Get_16Cap(ehci_version); 1041 1042 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1043 "ehci_init_hardware: Revision 0x%x", revision); 1044 1045 /* 1046 * EHCI driver supports EHCI host controllers compliant to 1047 * 0.95 and higher revisions of EHCI specifications. 1048 */ 1049 if (revision < EHCI_REVISION_0_95) { 1050 1051 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1052 "Revision 0x%x is not supported", revision); 1053 1054 return (DDI_FAILURE); 1055 } 1056 1057 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 1058 1059 /* Initialize the Frame list base address area */ 1060 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 1061 1062 return (DDI_FAILURE); 1063 } 1064 1065 /* 1066 * For performance reasons, do not insert anything into the 1067 * asynchronous list or activate the asynch list schedule until 1068 * there is a valid QH. 1069 */ 1070 ehcip->ehci_head_of_async_sched_list = NULL; 1071 1072 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 1073 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 1074 /* 1075 * The driver is unable to reliably stop the asynch 1076 * list schedule on VIA VT6202 controllers, so we 1077 * always keep a dummy QH on the list. 1078 */ 1079 ehci_qh_t *dummy_async_qh = 1080 ehci_alloc_qh(ehcip, NULL, NULL); 1081 1082 Set_QH(dummy_async_qh->qh_link_ptr, 1083 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 1084 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 1085 1086 /* Set this QH to be the "head" of the circular list */ 1087 Set_QH(dummy_async_qh->qh_ctrl, 1088 Get_QH(dummy_async_qh->qh_ctrl) | 1089 EHCI_QH_CTRL_RECLAIM_HEAD); 1090 1091 Set_QH(dummy_async_qh->qh_next_qtd, 1092 EHCI_QH_NEXT_QTD_PTR_VALID); 1093 Set_QH(dummy_async_qh->qh_alt_next_qtd, 1094 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1095 1096 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 1097 ehcip->ehci_open_async_count++; 1098 } 1099 } 1100 1101 return (DDI_SUCCESS); 1102 } 1103 1104 1105 /* 1106 * ehci_init_workaround 1107 * 1108 * some workarounds during initializing ehci 1109 */ 1110 int 1111 ehci_init_workaround(ehci_state_t *ehcip) 1112 { 1113 /* 1114 * Acer Labs Inc. M5273 EHCI controller does not send 1115 * interrupts unless the Root hub ports are routed to the EHCI 1116 * host controller; so route the ports now, before we test for 1117 * the presence of SOFs interrupts. 1118 */ 1119 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1120 /* Route all Root hub ports to EHCI host controller */ 1121 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1122 } 1123 1124 /* 1125 * VIA chips have some issues and may not work reliably. 1126 * Revisions >= 0x80 are part of a southbridge and appear 1127 * to be reliable with the workaround. 1128 * For revisions < 0x80, if we were bound using class 1129 * complain, else proceed. This will allow the user to 1130 * bind ehci specifically to this chip and not have the 1131 * warnings 1132 */ 1133 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 1134 1135 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 1136 1137 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1138 "ehci_init_workaround: Applying VIA workarounds " 1139 "for the 6212 chip."); 1140 1141 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1142 "pciclass,0c0320") == 0) { 1143 1144 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1145 "Due to recently discovered incompatibilities"); 1146 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1147 "with this USB controller, USB2.x transfer"); 1148 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1149 "support has been disabled. This device will"); 1150 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1151 "continue to function as a USB1.x controller."); 1152 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1153 "If you are interested in enabling USB2.x"); 1154 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1155 "support please, refer to the ehci(7D) man page."); 1156 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1157 "Please also refer to www.sun.com/io for"); 1158 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1159 "Solaris Ready products and to"); 1160 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1161 "www.sun.com/bigadmin/hcl for additional"); 1162 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1163 "compatible USB products."); 1164 1165 return (DDI_FAILURE); 1166 1167 } else if (ehci_vt62x2_workaround) { 1168 1169 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1170 "Applying VIA workarounds"); 1171 } 1172 } 1173 1174 return (DDI_SUCCESS); 1175 } 1176 1177 1178 /* 1179 * ehci_init_check_status 1180 * 1181 * Check if EHCI host controller is running 1182 */ 1183 int 1184 ehci_init_check_status(ehci_state_t *ehcip) 1185 { 1186 clock_t sof_time_wait; 1187 1188 /* 1189 * Get the number of clock ticks to wait. 1190 * This is based on the maximum time it takes for a frame list rollover 1191 * and maximum time wait for SOFs to begin. 1192 */ 1193 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1194 EHCI_SOF_TIMEWAIT); 1195 1196 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1197 ehcip->ehci_flags |= EHCI_CV_INTR; 1198 1199 /* We need to add a delay to allow the chip time to start running */ 1200 (void) cv_timedwait(&ehcip->ehci_async_schedule_advance_cv, 1201 &ehcip->ehci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1202 1203 /* 1204 * Check EHCI host controller is running, otherwise return failure. 1205 */ 1206 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1207 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1208 1209 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1210 "No SOF interrupts have been received, this USB EHCI host" 1211 "controller is unusable"); 1212 1213 /* 1214 * Route all Root hub ports to Classic host 1215 * controller, in case this is an unusable ALI M5273 1216 * EHCI controller. 1217 */ 1218 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1219 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1220 } 1221 1222 return (DDI_FAILURE); 1223 } 1224 1225 return (DDI_SUCCESS); 1226 } 1227 1228 1229 /* 1230 * ehci_init_ctlr: 1231 * 1232 * Initialize the Host Controller (HC). 1233 */ 1234 int 1235 ehci_init_ctlr(ehci_state_t *ehcip, 1236 int init_type) 1237 { 1238 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 1239 1240 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1241 1242 if (ehci_init_hardware(ehcip) != DDI_SUCCESS) { 1243 1244 return (DDI_FAILURE); 1245 } 1246 } 1247 1248 /* 1249 * Check for Asynchronous schedule park capability feature. If this 1250 * feature is supported, then, program ehci command register with 1251 * appropriate values.. 1252 */ 1253 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 1254 1255 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1256 "ehci_init_ctlr: Async park mode is supported"); 1257 1258 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1259 (EHCI_CMD_ASYNC_PARK_ENABLE | 1260 EHCI_CMD_ASYNC_PARK_COUNT_3))); 1261 } 1262 1263 /* 1264 * Check for programmable periodic frame list feature. If this 1265 * feature is supported, then, program ehci command register with 1266 * 1024 frame list value. 1267 */ 1268 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 1269 1270 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1271 "ehci_init_ctlr: Variable programmable periodic " 1272 "frame list is supported"); 1273 1274 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1275 EHCI_CMD_FRAME_1024_SIZE)); 1276 } 1277 1278 /* 1279 * Currently EHCI driver doesn't support 64 bit addressing. 1280 * 1281 * If we are using 64 bit addressing capability, then, program 1282 * ehci_ctrl_segment register with 4 Gigabyte segment where all 1283 * of the interface data structures are allocated. 1284 */ 1285 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 1286 1287 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1288 "ehci_init_ctlr: EHCI driver doesn't support " 1289 "64 bit addressing"); 1290 } 1291 1292 /* 64 bit addressing is not support */ 1293 Set_OpReg(ehci_ctrl_segment, 0x00000000); 1294 1295 /* Turn on/off the schedulers */ 1296 ehci_toggle_scheduler(ehcip); 1297 1298 /* Set host controller soft state to operational */ 1299 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1300 1301 /* 1302 * Set the Periodic Frame List Base Address register with the 1303 * starting physical address of the Periodic Frame List. 1304 */ 1305 Set_OpReg(ehci_periodic_list_base, 1306 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 1307 EHCI_PERIODIC_LIST_BASE)); 1308 1309 /* 1310 * Set ehci_interrupt to enable all interrupts except Root 1311 * Hub Status change interrupt. 1312 */ 1313 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 1314 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 1315 EHCI_INTR_USB); 1316 1317 /* 1318 * Set the desired interrupt threshold and turn on EHCI host controller. 1319 */ 1320 Set_OpReg(ehci_command, 1321 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 1322 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 1323 1324 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 1325 1326 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1327 1328 if (ehci_init_workaround(ehcip) != DDI_SUCCESS) { 1329 1330 /* Set host controller soft state to error */ 1331 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 1332 1333 return (DDI_FAILURE); 1334 } 1335 1336 if (ehci_init_check_status(ehcip) != DDI_SUCCESS) { 1337 1338 /* Set host controller soft state to error */ 1339 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 1340 1341 return (DDI_FAILURE); 1342 } 1343 1344 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1345 "ehci_init_ctlr: SOF's have started"); 1346 } 1347 1348 /* Route all Root hub ports to EHCI host controller */ 1349 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1350 1351 return (DDI_SUCCESS); 1352 } 1353 1354 /* 1355 * ehci_take_control: 1356 * 1357 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1358 * x86 machines, because sparc doesn't have a BIOS. 1359 * On x86 machine, the take control process includes 1360 * o get the base address of the extended capability list 1361 * o find out the capability for handoff synchronization in the list. 1362 * o check if BIOS has owned the host controller. 1363 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1364 * o wait for a constant time and check if BIOS has relinquished control. 1365 */ 1366 /* ARGSUSED */ 1367 static int 1368 ehci_take_control(ehci_state_t *ehcip) 1369 { 1370 #if defined(__x86) 1371 uint32_t extended_cap; 1372 uint32_t extended_cap_offset; 1373 uint32_t extended_cap_id; 1374 uint_t retry; 1375 1376 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1377 "ehci_take_control:"); 1378 1379 /* 1380 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1381 * register. 1382 */ 1383 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1384 EHCI_HCC_EECP_SHIFT; 1385 1386 /* 1387 * According EHCI Spec 2.2.4, if the extended capability offset is 1388 * less than 40h then its not valid. This means we don't need to 1389 * worry about BIOS handoff. 1390 */ 1391 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1392 1393 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1394 "ehci_take_control: Hardware doesn't support legacy."); 1395 1396 goto success; 1397 } 1398 1399 /* 1400 * According EHCI Spec 2.1.7, A zero offset indicates the 1401 * end of the extended capability list. 1402 */ 1403 while (extended_cap_offset) { 1404 1405 /* Get the extended capability value. */ 1406 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1407 extended_cap_offset); 1408 1409 /* Get the capability ID */ 1410 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1411 EHCI_EX_CAP_ID_SHIFT; 1412 1413 /* Check if the card support legacy */ 1414 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1415 break; 1416 } 1417 1418 /* Get the offset of the next capability */ 1419 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1420 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1421 } 1422 1423 /* 1424 * Unable to find legacy support in hardware's extended capability list. 1425 * This means we don't need to worry about BIOS handoff. 1426 */ 1427 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1428 1429 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1430 "ehci_take_control: Hardware doesn't support legacy"); 1431 1432 goto success; 1433 } 1434 1435 /* Check if BIOS has owned it. */ 1436 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1437 1438 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1439 "ehci_take_control: BIOS does not own EHCI"); 1440 1441 goto success; 1442 } 1443 1444 /* 1445 * According EHCI Spec 5.1, The OS driver initiates an ownership 1446 * request by setting the OS Owned semaphore to a one. The OS 1447 * waits for the BIOS Owned bit to go to a zero before attempting 1448 * to use the EHCI controller. The time that OS must wait for BIOS 1449 * to respond to the request for ownership is beyond the scope of 1450 * this specification. 1451 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1452 * for BIOS to release the ownership. 1453 */ 1454 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1455 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1456 extended_cap); 1457 1458 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1459 1460 /* wait a special interval */ 1461 #ifndef __lock_lint 1462 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1463 #endif 1464 /* Check to see if the BIOS has released the ownership */ 1465 extended_cap = pci_config_get32( 1466 ehcip->ehci_config_handle, extended_cap_offset); 1467 1468 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1469 1470 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1471 ehcip->ehci_log_hdl, 1472 "ehci_take_control: BIOS has released " 1473 "the ownership. retry = %d", retry); 1474 1475 goto success; 1476 } 1477 1478 } 1479 1480 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1481 "ehci_take_control: take control from BIOS failed."); 1482 1483 return (USB_FAILURE); 1484 1485 success: 1486 1487 #endif /* __x86 */ 1488 return (USB_SUCCESS); 1489 } 1490 1491 1492 /* 1493 * ehci_init_periodic_frame_list_table : 1494 * 1495 * Allocate the system memory and initialize Host Controller 1496 * Periodic Frame List table area. The starting of the Periodic 1497 * Frame List Table area must be 4096 byte aligned. 1498 */ 1499 static int 1500 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1501 { 1502 ddi_device_acc_attr_t dev_attr; 1503 size_t real_length; 1504 uint_t ccount; 1505 int result; 1506 1507 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1508 1509 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1510 "ehci_init_periodic_frame_lst_table:"); 1511 1512 /* The host controller will be little endian */ 1513 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1514 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1515 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1516 1517 /* Force the required 4K restrictive alignment */ 1518 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1519 1520 /* Create space for the Periodic Frame List */ 1521 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1522 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1523 1524 goto failure; 1525 } 1526 1527 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1528 sizeof (ehci_periodic_frame_list_t), 1529 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1530 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1531 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1532 1533 goto failure; 1534 } 1535 1536 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1537 "ehci_init_periodic_frame_lst_table: " 1538 "Real length %lu", real_length); 1539 1540 /* Map the whole Periodic Frame List into the I/O address space */ 1541 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1542 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1543 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1544 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1545 1546 if (result == DDI_DMA_MAPPED) { 1547 /* The cookie count should be 1 */ 1548 if (ccount != 1) { 1549 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1550 "ehci_init_periodic_frame_lst_table: " 1551 "More than 1 cookie"); 1552 1553 goto failure; 1554 } 1555 } else { 1556 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1557 1558 goto failure; 1559 } 1560 1561 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1562 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1563 (void *)ehcip->ehci_periodic_frame_list_tablep, 1564 ehcip->ehci_pflt_cookie.dmac_address); 1565 1566 /* 1567 * DMA addresses for Periodic Frame List are bound. 1568 */ 1569 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1570 1571 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1572 1573 /* Initialize the Periodic Frame List */ 1574 ehci_build_interrupt_lattice(ehcip); 1575 1576 /* Reset Byte Alignment to Default */ 1577 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1578 1579 return (DDI_SUCCESS); 1580 failure: 1581 /* Byte alignment */ 1582 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1583 1584 return (DDI_FAILURE); 1585 } 1586 1587 1588 /* 1589 * ehci_build_interrupt_lattice: 1590 * 1591 * Construct the interrupt lattice tree using static Endpoint Descriptors 1592 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1593 * lists and the Host Controller (HC) processes one interrupt QH list in 1594 * every frame. The Host Controller traverses the periodic schedule by 1595 * constructing an array offset reference from the Periodic List Base Address 1596 * register and bits 12 to 3 of Frame Index register. It fetches the element 1597 * and begins traversing the graph of linked schedule data structures. 1598 */ 1599 static void 1600 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1601 { 1602 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1603 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1604 ehci_periodic_frame_list_t *periodic_frame_list = 1605 ehcip->ehci_periodic_frame_list_tablep; 1606 ushort_t *temp, num_of_nodes; 1607 uintptr_t addr; 1608 int i, j, k; 1609 1610 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1611 "ehci_build_interrupt_lattice:"); 1612 1613 /* 1614 * Reserve the first 63 Endpoint Descriptor (QH) structures 1615 * in the pool as static endpoints & these are required for 1616 * constructing interrupt lattice tree. 1617 */ 1618 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1619 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1620 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1621 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1622 Set_QH(list_array[i].qh_alt_next_qtd, 1623 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1624 } 1625 1626 /* 1627 * Make sure that last Endpoint on the periodic frame list terminates 1628 * periodic schedule. 1629 */ 1630 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1631 1632 /* Build the interrupt lattice tree */ 1633 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1634 /* 1635 * The next pointer in the host controller endpoint 1636 * descriptor must contain an iommu address. Calculate 1637 * the offset into the cpu address and add this to the 1638 * starting iommu address. 1639 */ 1640 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1641 1642 Set_QH(list_array[2*i + 1].qh_link_ptr, 1643 addr | EHCI_QH_LINK_REF_QH); 1644 Set_QH(list_array[2*i + 2].qh_link_ptr, 1645 addr | EHCI_QH_LINK_REF_QH); 1646 } 1647 1648 /* Build the tree bottom */ 1649 temp = (unsigned short *) 1650 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1651 1652 num_of_nodes = 1; 1653 1654 /* 1655 * Initialize the values which are used for setting up head pointers 1656 * for the 32ms scheduling lists which starts from the Periodic Frame 1657 * List. 1658 */ 1659 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1660 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1661 ehci_index[j++] = temp[k]; 1662 ehci_index[j] = temp[k] + ehci_pow_2(i); 1663 } 1664 1665 num_of_nodes *= 2; 1666 for (k = 0; k < num_of_nodes; k++) 1667 temp[k] = ehci_index[k]; 1668 } 1669 1670 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1671 1672 /* 1673 * Initialize the interrupt list in the Periodic Frame List Table 1674 * so that it points to the bottom of the tree. 1675 */ 1676 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1677 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1678 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1679 1680 ASSERT(addr); 1681 1682 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1683 Set_PFLT(periodic_frame_list-> 1684 ehci_periodic_frame_list_table[ehci_index[j++]], 1685 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1686 } 1687 } 1688 } 1689 1690 1691 /* 1692 * ehci_alloc_hcdi_ops: 1693 * 1694 * The HCDI interfaces or entry points are the software interfaces used by 1695 * the Universal Serial Bus Driver (USBA) to access the services of the 1696 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1697 * about all available HCDI interfaces or entry points. 1698 */ 1699 usba_hcdi_ops_t * 1700 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1701 { 1702 usba_hcdi_ops_t *usba_hcdi_ops; 1703 1704 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1705 "ehci_alloc_hcdi_ops:"); 1706 1707 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1708 1709 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1710 1711 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1712 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1713 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1714 1715 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1716 1717 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1718 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1719 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1720 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1721 1722 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1723 ehci_hcdi_bulk_transfer_size; 1724 1725 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1726 ehci_hcdi_pipe_stop_intr_polling; 1727 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1728 ehci_hcdi_pipe_stop_isoc_polling; 1729 1730 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1731 ehci_hcdi_get_current_frame_number; 1732 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1733 ehci_hcdi_get_max_isoc_pkts; 1734 1735 usba_hcdi_ops->usba_hcdi_console_input_init = 1736 ehci_hcdi_polled_input_init; 1737 usba_hcdi_ops->usba_hcdi_console_input_enter = 1738 ehci_hcdi_polled_input_enter; 1739 usba_hcdi_ops->usba_hcdi_console_read = 1740 ehci_hcdi_polled_read; 1741 usba_hcdi_ops->usba_hcdi_console_input_exit = 1742 ehci_hcdi_polled_input_exit; 1743 usba_hcdi_ops->usba_hcdi_console_input_fini = 1744 ehci_hcdi_polled_input_fini; 1745 return (usba_hcdi_ops); 1746 } 1747 1748 1749 /* 1750 * Host Controller Driver (HCD) deinitialization functions 1751 */ 1752 1753 /* 1754 * ehci_cleanup: 1755 * 1756 * Cleanup on attach failure or detach 1757 */ 1758 int 1759 ehci_cleanup(ehci_state_t *ehcip) 1760 { 1761 ehci_trans_wrapper_t *tw; 1762 ehci_pipe_private_t *pp; 1763 ehci_qtd_t *qtd; 1764 int i, ctrl, rval; 1765 int flags = ehcip->ehci_flags; 1766 1767 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1768 1769 if (flags & EHCI_RHREG) { 1770 /* Unload the root hub driver */ 1771 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1772 1773 return (DDI_FAILURE); 1774 } 1775 } 1776 1777 if (flags & EHCI_USBAREG) { 1778 /* Unregister this HCD instance with USBA */ 1779 usba_hcdi_unregister(ehcip->ehci_dip); 1780 } 1781 1782 if (flags & EHCI_INTR) { 1783 1784 mutex_enter(&ehcip->ehci_int_mutex); 1785 1786 /* Disable all EHCI QH list processing */ 1787 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1788 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1789 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1790 1791 /* Disable all EHCI interrupts */ 1792 Set_OpReg(ehci_interrupt, 0); 1793 1794 /* wait for the next SOF */ 1795 (void) ehci_wait_for_sof(ehcip); 1796 1797 /* Route all Root hub ports to Classic host controller */ 1798 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1799 1800 /* Stop the EHCI host controller */ 1801 Set_OpReg(ehci_command, 1802 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1803 1804 mutex_exit(&ehcip->ehci_int_mutex); 1805 1806 /* Wait for sometime */ 1807 delay(drv_usectohz(EHCI_TIMEWAIT)); 1808 1809 ehci_rem_intrs(ehcip); 1810 } 1811 1812 /* Unmap the EHCI registers */ 1813 if (ehcip->ehci_caps_handle) { 1814 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1815 } 1816 1817 if (ehcip->ehci_config_handle) { 1818 pci_config_teardown(&ehcip->ehci_config_handle); 1819 } 1820 1821 /* Free all the buffers */ 1822 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1823 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1824 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1825 ctrl = Get_QTD(ehcip-> 1826 ehci_qtd_pool_addr[i].qtd_state); 1827 1828 if ((ctrl != EHCI_QTD_FREE) && 1829 (ctrl != EHCI_QTD_DUMMY) && 1830 (qtd->qtd_trans_wrapper)) { 1831 1832 mutex_enter(&ehcip->ehci_int_mutex); 1833 1834 tw = (ehci_trans_wrapper_t *) 1835 EHCI_LOOKUP_ID((uint32_t) 1836 Get_QTD(qtd->qtd_trans_wrapper)); 1837 1838 /* Obtain the pipe private structure */ 1839 pp = tw->tw_pipe_private; 1840 1841 /* Stop the the transfer timer */ 1842 ehci_stop_xfer_timer(ehcip, tw, 1843 EHCI_REMOVE_XFER_ALWAYS); 1844 1845 ehci_deallocate_tw(ehcip, pp, tw); 1846 1847 mutex_exit(&ehcip->ehci_int_mutex); 1848 } 1849 } 1850 1851 /* 1852 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1853 * the handle for QTD pools. 1854 */ 1855 if ((ehcip->ehci_dma_addr_bind_flag & 1856 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1857 1858 rval = ddi_dma_unbind_handle( 1859 ehcip->ehci_qtd_pool_dma_handle); 1860 1861 ASSERT(rval == DDI_SUCCESS); 1862 } 1863 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1864 } 1865 1866 /* Free the QTD pool */ 1867 if (ehcip->ehci_qtd_pool_dma_handle) { 1868 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1869 } 1870 1871 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1872 /* 1873 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1874 * the handle for QH pools. 1875 */ 1876 if ((ehcip->ehci_dma_addr_bind_flag & 1877 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1878 1879 rval = ddi_dma_unbind_handle( 1880 ehcip->ehci_qh_pool_dma_handle); 1881 1882 ASSERT(rval == DDI_SUCCESS); 1883 } 1884 1885 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1886 } 1887 1888 /* Free the QH pool */ 1889 if (ehcip->ehci_qh_pool_dma_handle) { 1890 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1891 } 1892 1893 /* Free the Periodic frame list table (PFLT) area */ 1894 if (ehcip->ehci_periodic_frame_list_tablep && 1895 ehcip->ehci_pflt_mem_handle) { 1896 /* 1897 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1898 * the handle for PFLT. 1899 */ 1900 if ((ehcip->ehci_dma_addr_bind_flag & 1901 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1902 1903 rval = ddi_dma_unbind_handle( 1904 ehcip->ehci_pflt_dma_handle); 1905 1906 ASSERT(rval == DDI_SUCCESS); 1907 } 1908 1909 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1910 } 1911 1912 (void) ehci_isoc_cleanup(ehcip); 1913 1914 if (ehcip->ehci_pflt_dma_handle) { 1915 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1916 } 1917 1918 if (flags & EHCI_INTR) { 1919 /* Destroy the mutex */ 1920 mutex_destroy(&ehcip->ehci_int_mutex); 1921 1922 /* Destroy the async schedule advance condition variable */ 1923 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1924 } 1925 1926 /* clean up kstat structs */ 1927 ehci_destroy_stats(ehcip); 1928 1929 /* Free ehci hcdi ops */ 1930 if (ehcip->ehci_hcdi_ops) { 1931 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1932 } 1933 1934 if (flags & EHCI_ZALLOC) { 1935 1936 usb_free_log_hdl(ehcip->ehci_log_hdl); 1937 1938 /* Remove all properties that might have been created */ 1939 ddi_prop_remove_all(ehcip->ehci_dip); 1940 1941 /* Free the soft state */ 1942 ddi_soft_state_free(ehci_statep, 1943 ddi_get_instance(ehcip->ehci_dip)); 1944 } 1945 1946 return (DDI_SUCCESS); 1947 } 1948 1949 1950 /* 1951 * ehci_rem_intrs: 1952 * 1953 * Unregister FIXED or MSI interrupts 1954 */ 1955 static void 1956 ehci_rem_intrs(ehci_state_t *ehcip) 1957 { 1958 int i; 1959 1960 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1961 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type); 1962 1963 /* Disable all interrupts */ 1964 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1965 (void) ddi_intr_block_disable(ehcip->ehci_htable, 1966 ehcip->ehci_intr_cnt); 1967 } else { 1968 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1969 (void) ddi_intr_disable(ehcip->ehci_htable[i]); 1970 } 1971 } 1972 1973 /* Call ddi_intr_remove_handler() */ 1974 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1975 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 1976 (void) ddi_intr_free(ehcip->ehci_htable[i]); 1977 } 1978 1979 kmem_free(ehcip->ehci_htable, 1980 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t)); 1981 } 1982 1983 1984 /* 1985 * ehci_cpr_suspend 1986 */ 1987 int 1988 ehci_cpr_suspend(ehci_state_t *ehcip) 1989 { 1990 int i; 1991 1992 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1993 "ehci_cpr_suspend:"); 1994 1995 /* Call into the root hub and suspend it */ 1996 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 1997 1998 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1999 "ehci_cpr_suspend: root hub fails to suspend"); 2000 2001 return (DDI_FAILURE); 2002 } 2003 2004 /* Only root hub's intr pipe should be open at this time */ 2005 mutex_enter(&ehcip->ehci_int_mutex); 2006 2007 ASSERT(ehcip->ehci_open_pipe_count == 0); 2008 2009 /* Just wait till all resources are reclaimed */ 2010 i = 0; 2011 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 2012 ehci_handle_endpoint_reclaimation(ehcip); 2013 (void) ehci_wait_for_sof(ehcip); 2014 } 2015 ASSERT(ehcip->ehci_reclaim_list == NULL); 2016 2017 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2018 "ehci_cpr_suspend: Disable HC QH list processing"); 2019 2020 /* Disable all EHCI QH list processing */ 2021 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 2022 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 2023 2024 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2025 "ehci_cpr_suspend: Disable HC interrupts"); 2026 2027 /* Disable all EHCI interrupts */ 2028 Set_OpReg(ehci_interrupt, 0); 2029 2030 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2031 "ehci_cpr_suspend: Wait for the next SOF"); 2032 2033 /* Wait for the next SOF */ 2034 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 2035 2036 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2037 "ehci_cpr_suspend: ehci host controller suspend failed"); 2038 2039 mutex_exit(&ehcip->ehci_int_mutex); 2040 return (DDI_FAILURE); 2041 } 2042 2043 /* 2044 * Stop the ehci host controller 2045 * if usb keyboard is not connected. 2046 */ 2047 if (ehcip->ehci_polled_kbd_count == 0 || force_ehci_off != 0) { 2048 Set_OpReg(ehci_command, 2049 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 2050 } 2051 2052 /* Set host controller soft state to suspend */ 2053 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 2054 2055 mutex_exit(&ehcip->ehci_int_mutex); 2056 2057 return (DDI_SUCCESS); 2058 } 2059 2060 2061 /* 2062 * ehci_cpr_resume 2063 */ 2064 int 2065 ehci_cpr_resume(ehci_state_t *ehcip) 2066 { 2067 mutex_enter(&ehcip->ehci_int_mutex); 2068 2069 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2070 "ehci_cpr_resume: Restart the controller"); 2071 2072 /* Cleanup ehci specific information across cpr */ 2073 ehci_cpr_cleanup(ehcip); 2074 2075 /* Restart the controller */ 2076 if (ehci_init_ctlr(ehcip, EHCI_NORMAL_INITIALIZATION) != DDI_SUCCESS) { 2077 2078 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2079 "ehci_cpr_resume: ehci host controller resume failed "); 2080 2081 mutex_exit(&ehcip->ehci_int_mutex); 2082 2083 return (DDI_FAILURE); 2084 } 2085 2086 mutex_exit(&ehcip->ehci_int_mutex); 2087 2088 /* Now resume the root hub */ 2089 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 2090 2091 return (DDI_FAILURE); 2092 } 2093 2094 return (DDI_SUCCESS); 2095 } 2096 2097 2098 /* 2099 * Bandwidth Allocation functions 2100 */ 2101 2102 /* 2103 * ehci_allocate_bandwidth: 2104 * 2105 * Figure out whether or not this interval may be supported. Return the index 2106 * into the lattice if it can be supported. Return allocation failure if it 2107 * can not be supported. 2108 */ 2109 int 2110 ehci_allocate_bandwidth( 2111 ehci_state_t *ehcip, 2112 usba_pipe_handle_data_t *ph, 2113 uint_t *pnode, 2114 uchar_t *smask, 2115 uchar_t *cmask) 2116 { 2117 int error = USB_SUCCESS; 2118 2119 /* This routine is protected by the ehci_int_mutex */ 2120 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2121 2122 /* Reset the pnode to the last checked pnode */ 2123 *pnode = 0; 2124 2125 /* Allocate high speed bandwidth */ 2126 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 2127 ph, pnode, smask, cmask)) != USB_SUCCESS) { 2128 2129 return (error); 2130 } 2131 2132 /* 2133 * For low/full speed usb devices, allocate classic TT bandwidth 2134 * in additional to high speed bandwidth. 2135 */ 2136 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2137 2138 /* Allocate classic TT bandwidth */ 2139 if ((error = ehci_allocate_classic_tt_bandwidth( 2140 ehcip, ph, *pnode)) != USB_SUCCESS) { 2141 2142 /* Deallocate high speed bandwidth */ 2143 ehci_deallocate_high_speed_bandwidth( 2144 ehcip, ph, *pnode, *smask, *cmask); 2145 } 2146 } 2147 2148 return (error); 2149 } 2150 2151 2152 /* 2153 * ehci_allocate_high_speed_bandwidth: 2154 * 2155 * Allocate high speed bandwidth for the low/full/high speed interrupt and 2156 * isochronous endpoints. 2157 */ 2158 static int 2159 ehci_allocate_high_speed_bandwidth( 2160 ehci_state_t *ehcip, 2161 usba_pipe_handle_data_t *ph, 2162 uint_t *pnode, 2163 uchar_t *smask, 2164 uchar_t *cmask) 2165 { 2166 uint_t sbandwidth, cbandwidth; 2167 int interval; 2168 usb_ep_descr_t *endpoint = &ph->p_ep; 2169 usba_device_t *child_ud; 2170 usb_port_status_t port_status; 2171 int error; 2172 2173 /* This routine is protected by the ehci_int_mutex */ 2174 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2175 2176 /* Get child's usba device structure */ 2177 child_ud = ph->p_usba_device; 2178 2179 mutex_enter(&child_ud->usb_mutex); 2180 2181 /* Get the current usb device's port status */ 2182 port_status = ph->p_usba_device->usb_port_status; 2183 2184 mutex_exit(&child_ud->usb_mutex); 2185 2186 /* 2187 * Calculate the length in bytes of a transaction on this 2188 * periodic endpoint. Return failure if maximum packet is 2189 * zero. 2190 */ 2191 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2192 port_status, &sbandwidth, &cbandwidth); 2193 if (error != USB_SUCCESS) { 2194 2195 return (error); 2196 } 2197 2198 /* 2199 * Adjust polling interval to be a power of 2. 2200 * If this interval can't be supported, return 2201 * allocation failure. 2202 */ 2203 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2204 if (interval == USB_FAILURE) { 2205 2206 return (USB_FAILURE); 2207 } 2208 2209 if (port_status == USBA_HIGH_SPEED_DEV) { 2210 /* Allocate bandwidth for high speed devices */ 2211 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2212 USB_EP_ATTR_ISOCH) { 2213 error = USB_SUCCESS; 2214 } else { 2215 2216 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 2217 endpoint, sbandwidth, interval); 2218 } 2219 2220 *cmask = 0x00; 2221 2222 } else { 2223 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2224 USB_EP_ATTR_INTR) { 2225 2226 /* Allocate bandwidth for low speed interrupt */ 2227 error = ehci_find_bestfit_ls_intr_mask(ehcip, 2228 smask, cmask, pnode, sbandwidth, cbandwidth, 2229 interval); 2230 } else { 2231 if ((endpoint->bEndpointAddress & 2232 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2233 2234 /* Allocate bandwidth for sitd in */ 2235 error = ehci_find_bestfit_sitd_in_mask(ehcip, 2236 smask, cmask, pnode, sbandwidth, cbandwidth, 2237 interval); 2238 } else { 2239 2240 /* Allocate bandwidth for sitd out */ 2241 error = ehci_find_bestfit_sitd_out_mask(ehcip, 2242 smask, pnode, sbandwidth, interval); 2243 *cmask = 0x00; 2244 } 2245 } 2246 } 2247 2248 if (error != USB_SUCCESS) { 2249 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2250 "ehci_allocate_high_speed_bandwidth: Reached maximum " 2251 "bandwidth value and cannot allocate bandwidth for a " 2252 "given high-speed periodic endpoint"); 2253 2254 return (USB_NO_BANDWIDTH); 2255 } 2256 2257 return (error); 2258 } 2259 2260 2261 /* 2262 * ehci_allocate_classic_tt_speed_bandwidth: 2263 * 2264 * Allocate classic TT bandwidth for the low/full speed interrupt and 2265 * isochronous endpoints. 2266 */ 2267 static int 2268 ehci_allocate_classic_tt_bandwidth( 2269 ehci_state_t *ehcip, 2270 usba_pipe_handle_data_t *ph, 2271 uint_t pnode) 2272 { 2273 uint_t bandwidth, min; 2274 uint_t height, leftmost, list; 2275 usb_ep_descr_t *endpoint = &ph->p_ep; 2276 usba_device_t *child_ud, *parent_ud; 2277 usb_port_status_t port_status; 2278 int i, interval; 2279 2280 /* This routine is protected by the ehci_int_mutex */ 2281 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2282 2283 /* Get child's usba device structure */ 2284 child_ud = ph->p_usba_device; 2285 2286 mutex_enter(&child_ud->usb_mutex); 2287 2288 /* Get the current usb device's port status */ 2289 port_status = child_ud->usb_port_status; 2290 2291 /* Get the parent high speed hub's usba device structure */ 2292 parent_ud = child_ud->usb_hs_hub_usba_dev; 2293 2294 mutex_exit(&child_ud->usb_mutex); 2295 2296 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2297 "ehci_allocate_classic_tt_bandwidth: " 2298 "child_ud 0x%p parent_ud 0x%p", 2299 (void *)child_ud, (void *)parent_ud); 2300 2301 /* 2302 * Calculate the length in bytes of a transaction on this 2303 * periodic endpoint. Return failure if maximum packet is 2304 * zero. 2305 */ 2306 if (ehci_compute_classic_bandwidth(endpoint, 2307 port_status, &bandwidth) != USB_SUCCESS) { 2308 2309 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2310 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2311 "with zero endpoint maximum packet size is not supported"); 2312 2313 return (USB_NOT_SUPPORTED); 2314 } 2315 2316 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2317 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2318 2319 mutex_enter(&parent_ud->usb_mutex); 2320 2321 /* 2322 * If the length in bytes plus the allocated bandwidth exceeds 2323 * the maximum, return bandwidth allocation failure. 2324 */ 2325 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2326 FS_PERIODIC_BANDWIDTH) { 2327 2328 mutex_exit(&parent_ud->usb_mutex); 2329 2330 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2331 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2332 "bandwidth value and cannot allocate bandwidth for a " 2333 "given low/full speed periodic endpoint"); 2334 2335 return (USB_NO_BANDWIDTH); 2336 } 2337 2338 mutex_exit(&parent_ud->usb_mutex); 2339 2340 /* Adjust polling interval to be a power of 2 */ 2341 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2342 2343 /* Find the height in the tree */ 2344 height = ehci_lattice_height(interval); 2345 2346 /* Find the leftmost leaf in the subtree specified by the node. */ 2347 leftmost = ehci_leftmost_leaf(pnode, height); 2348 2349 mutex_enter(&parent_ud->usb_mutex); 2350 2351 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2352 list = ehci_index[leftmost + i]; 2353 2354 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2355 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2356 2357 mutex_exit(&parent_ud->usb_mutex); 2358 2359 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2360 "ehci_allocate_classic_tt_bandwidth: Reached " 2361 "maximum bandwidth value and cannot allocate " 2362 "bandwidth for low/full periodic endpoint"); 2363 2364 return (USB_NO_BANDWIDTH); 2365 } 2366 } 2367 2368 /* 2369 * All the leaves for this node must be updated with the bandwidth. 2370 */ 2371 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2372 list = ehci_index[leftmost + i]; 2373 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2374 } 2375 2376 /* Find the leaf with the smallest allocated bandwidth */ 2377 min = parent_ud->usb_hs_hub_bandwidth[0]; 2378 2379 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2380 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2381 min = parent_ud->usb_hs_hub_bandwidth[i]; 2382 } 2383 } 2384 2385 /* Save the minimum for later use */ 2386 parent_ud->usb_hs_hub_min_bandwidth = min; 2387 2388 mutex_exit(&parent_ud->usb_mutex); 2389 2390 return (USB_SUCCESS); 2391 } 2392 2393 2394 /* 2395 * ehci_deallocate_bandwidth: 2396 * 2397 * Deallocate bandwidth for the given node in the lattice and the length 2398 * of transfer. 2399 */ 2400 void 2401 ehci_deallocate_bandwidth( 2402 ehci_state_t *ehcip, 2403 usba_pipe_handle_data_t *ph, 2404 uint_t pnode, 2405 uchar_t smask, 2406 uchar_t cmask) 2407 { 2408 /* This routine is protected by the ehci_int_mutex */ 2409 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2410 2411 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2412 2413 /* 2414 * For low/full speed usb devices, deallocate classic TT bandwidth 2415 * in additional to high speed bandwidth. 2416 */ 2417 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2418 2419 /* Deallocate classic TT bandwidth */ 2420 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2421 } 2422 } 2423 2424 2425 /* 2426 * ehci_deallocate_high_speed_bandwidth: 2427 * 2428 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2429 */ 2430 static void 2431 ehci_deallocate_high_speed_bandwidth( 2432 ehci_state_t *ehcip, 2433 usba_pipe_handle_data_t *ph, 2434 uint_t pnode, 2435 uchar_t smask, 2436 uchar_t cmask) 2437 { 2438 uint_t height, leftmost; 2439 uint_t list_count; 2440 uint_t sbandwidth, cbandwidth; 2441 int interval; 2442 usb_ep_descr_t *endpoint = &ph->p_ep; 2443 usba_device_t *child_ud; 2444 usb_port_status_t port_status; 2445 2446 /* This routine is protected by the ehci_int_mutex */ 2447 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2448 2449 /* Get child's usba device structure */ 2450 child_ud = ph->p_usba_device; 2451 2452 mutex_enter(&child_ud->usb_mutex); 2453 2454 /* Get the current usb device's port status */ 2455 port_status = ph->p_usba_device->usb_port_status; 2456 2457 mutex_exit(&child_ud->usb_mutex); 2458 2459 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2460 port_status, &sbandwidth, &cbandwidth); 2461 2462 /* Adjust polling interval to be a power of 2 */ 2463 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2464 2465 /* Find the height in the tree */ 2466 height = ehci_lattice_height(interval); 2467 2468 /* 2469 * Find the leftmost leaf in the subtree specified by the node 2470 */ 2471 leftmost = ehci_leftmost_leaf(pnode, height); 2472 2473 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2474 2475 /* Delete the bandwidth from the appropriate lists */ 2476 if (port_status == USBA_HIGH_SPEED_DEV) { 2477 2478 ehci_update_bw_availability(ehcip, -sbandwidth, 2479 leftmost, list_count, smask); 2480 } else { 2481 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2482 USB_EP_ATTR_INTR) { 2483 2484 ehci_update_bw_availability(ehcip, -sbandwidth, 2485 leftmost, list_count, smask); 2486 ehci_update_bw_availability(ehcip, -cbandwidth, 2487 leftmost, list_count, cmask); 2488 } else { 2489 if ((endpoint->bEndpointAddress & 2490 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2491 2492 ehci_update_bw_availability(ehcip, -sbandwidth, 2493 leftmost, list_count, smask); 2494 ehci_update_bw_availability(ehcip, 2495 -MAX_UFRAME_SITD_XFER, leftmost, 2496 list_count, cmask); 2497 } else { 2498 2499 ehci_update_bw_availability(ehcip, 2500 -MAX_UFRAME_SITD_XFER, leftmost, 2501 list_count, smask); 2502 } 2503 } 2504 } 2505 } 2506 2507 /* 2508 * ehci_deallocate_classic_tt_bandwidth: 2509 * 2510 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2511 */ 2512 static void 2513 ehci_deallocate_classic_tt_bandwidth( 2514 ehci_state_t *ehcip, 2515 usba_pipe_handle_data_t *ph, 2516 uint_t pnode) 2517 { 2518 uint_t bandwidth, height, leftmost, list, min; 2519 int i, interval; 2520 usb_ep_descr_t *endpoint = &ph->p_ep; 2521 usba_device_t *child_ud, *parent_ud; 2522 usb_port_status_t port_status; 2523 2524 /* This routine is protected by the ehci_int_mutex */ 2525 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2526 2527 /* Get child's usba device structure */ 2528 child_ud = ph->p_usba_device; 2529 2530 mutex_enter(&child_ud->usb_mutex); 2531 2532 /* Get the current usb device's port status */ 2533 port_status = child_ud->usb_port_status; 2534 2535 /* Get the parent high speed hub's usba device structure */ 2536 parent_ud = child_ud->usb_hs_hub_usba_dev; 2537 2538 mutex_exit(&child_ud->usb_mutex); 2539 2540 /* Obtain the bandwidth */ 2541 (void) ehci_compute_classic_bandwidth(endpoint, 2542 port_status, &bandwidth); 2543 2544 /* Adjust polling interval to be a power of 2 */ 2545 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2546 2547 /* Find the height in the tree */ 2548 height = ehci_lattice_height(interval); 2549 2550 /* Find the leftmost leaf in the subtree specified by the node */ 2551 leftmost = ehci_leftmost_leaf(pnode, height); 2552 2553 mutex_enter(&parent_ud->usb_mutex); 2554 2555 /* Delete the bandwidth from the appropriate lists */ 2556 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2557 list = ehci_index[leftmost + i]; 2558 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2559 } 2560 2561 /* Find the leaf with the smallest allocated bandwidth */ 2562 min = parent_ud->usb_hs_hub_bandwidth[0]; 2563 2564 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2565 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2566 min = parent_ud->usb_hs_hub_bandwidth[i]; 2567 } 2568 } 2569 2570 /* Save the minimum for later use */ 2571 parent_ud->usb_hs_hub_min_bandwidth = min; 2572 2573 mutex_exit(&parent_ud->usb_mutex); 2574 } 2575 2576 2577 /* 2578 * ehci_compute_high_speed_bandwidth: 2579 * 2580 * Given a periodic endpoint (interrupt or isochronous) determine the total 2581 * bandwidth for one transaction. The EHCI host controller traverses the 2582 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2583 * services an endpoint, only a single transaction attempt is made. The HC 2584 * moves to the next Endpoint Descriptor after the first transaction attempt 2585 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2586 * Transfer Descriptor is inserted into the lattice, we will only count the 2587 * number of bytes for one transaction. 2588 * 2589 * The following are the formulas used for calculating bandwidth in terms 2590 * bytes and it is for the single USB high speed transaction. The protocol 2591 * overheads will be different for each of type of USB transfer & all these 2592 * formulas & protocol overheads are derived from the 5.11.3 section of the 2593 * USB 2.0 Specification. 2594 * 2595 * High-Speed: 2596 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2597 * 2598 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2599 * 2600 * Protocol overhead + Split transaction overhead + 2601 * ((MaxPktSz * 7)/6) + Host_Delay; 2602 */ 2603 /* ARGSUSED */ 2604 static int 2605 ehci_compute_high_speed_bandwidth( 2606 ehci_state_t *ehcip, 2607 usb_ep_descr_t *endpoint, 2608 usb_port_status_t port_status, 2609 uint_t *sbandwidth, 2610 uint_t *cbandwidth) 2611 { 2612 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2613 2614 /* Return failure if endpoint maximum packet is zero */ 2615 if (maxpacketsize == 0) { 2616 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2617 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2618 "with zero endpoint maximum packet size is not supported"); 2619 2620 return (USB_NOT_SUPPORTED); 2621 } 2622 2623 /* Add bit-stuffing overhead */ 2624 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2625 2626 /* Add Host Controller specific delay to required bandwidth */ 2627 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2628 2629 /* Add xfer specific protocol overheads */ 2630 if ((endpoint->bmAttributes & 2631 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2632 /* High speed interrupt transaction */ 2633 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2634 } else { 2635 /* Isochronous transaction */ 2636 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2637 } 2638 2639 /* 2640 * For low/full speed devices, add split transaction specific 2641 * overheads. 2642 */ 2643 if (port_status != USBA_HIGH_SPEED_DEV) { 2644 /* 2645 * Add start and complete split transaction 2646 * tokens overheads. 2647 */ 2648 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2649 *sbandwidth += START_SPLIT_OVERHEAD; 2650 2651 /* Add data overhead depending on data direction */ 2652 if ((endpoint->bEndpointAddress & 2653 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2654 *cbandwidth += maxpacketsize; 2655 } else { 2656 if ((endpoint->bmAttributes & 2657 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2658 /* There is no compete splits for out */ 2659 *cbandwidth = 0; 2660 } 2661 *sbandwidth += maxpacketsize; 2662 } 2663 } else { 2664 uint_t xactions; 2665 2666 /* Get the max transactions per microframe */ 2667 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2668 USB_EP_MAX_XACTS_SHIFT) + 1; 2669 2670 /* High speed transaction */ 2671 *sbandwidth += maxpacketsize; 2672 2673 /* Calculate bandwidth per micro-frame */ 2674 *sbandwidth *= xactions; 2675 2676 *cbandwidth = 0; 2677 } 2678 2679 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2680 "ehci_allocate_high_speed_bandwidth: " 2681 "Start split bandwidth %d Complete split bandwidth %d", 2682 *sbandwidth, *cbandwidth); 2683 2684 return (USB_SUCCESS); 2685 } 2686 2687 2688 /* 2689 * ehci_compute_classic_bandwidth: 2690 * 2691 * Given a periodic endpoint (interrupt or isochronous) determine the total 2692 * bandwidth for one transaction. The EHCI host controller traverses the 2693 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2694 * services an endpoint, only a single transaction attempt is made. The HC 2695 * moves to the next Endpoint Descriptor after the first transaction attempt 2696 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2697 * Transfer Descriptor is inserted into the lattice, we will only count the 2698 * number of bytes for one transaction. 2699 * 2700 * The following are the formulas used for calculating bandwidth in terms 2701 * bytes and it is for the single USB high speed transaction. The protocol 2702 * overheads will be different for each of type of USB transfer & all these 2703 * formulas & protocol overheads are derived from the 5.11.3 section of the 2704 * USB 2.0 Specification. 2705 * 2706 * Low-Speed: 2707 * Protocol overhead + Hub LS overhead + 2708 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2709 * 2710 * Full-Speed: 2711 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2712 */ 2713 /* ARGSUSED */ 2714 static int 2715 ehci_compute_classic_bandwidth( 2716 usb_ep_descr_t *endpoint, 2717 usb_port_status_t port_status, 2718 uint_t *bandwidth) 2719 { 2720 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2721 2722 /* 2723 * If endpoint maximum packet is zero, then return immediately. 2724 */ 2725 if (maxpacketsize == 0) { 2726 2727 return (USB_NOT_SUPPORTED); 2728 } 2729 2730 /* Add TT delay to required bandwidth */ 2731 *bandwidth = TT_DELAY; 2732 2733 /* Add bit-stuffing overhead */ 2734 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2735 2736 switch (port_status) { 2737 case USBA_LOW_SPEED_DEV: 2738 /* Low speed interrupt transaction */ 2739 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2740 HUB_LOW_SPEED_PROTO_OVERHEAD + 2741 (LOW_SPEED_CLOCK * maxpacketsize)); 2742 break; 2743 case USBA_FULL_SPEED_DEV: 2744 /* Full speed transaction */ 2745 *bandwidth += maxpacketsize; 2746 2747 /* Add xfer specific protocol overheads */ 2748 if ((endpoint->bmAttributes & 2749 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2750 /* Full speed interrupt transaction */ 2751 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2752 } else { 2753 /* Isochronous and input transaction */ 2754 if ((endpoint->bEndpointAddress & 2755 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2756 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2757 } else { 2758 /* Isochronous and output transaction */ 2759 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2760 } 2761 } 2762 break; 2763 } 2764 2765 return (USB_SUCCESS); 2766 } 2767 2768 2769 /* 2770 * ehci_adjust_polling_interval: 2771 * 2772 * Adjust bandwidth according usb device speed. 2773 */ 2774 /* ARGSUSED */ 2775 int 2776 ehci_adjust_polling_interval( 2777 ehci_state_t *ehcip, 2778 usb_ep_descr_t *endpoint, 2779 usb_port_status_t port_status) 2780 { 2781 uint_t interval; 2782 int i = 0; 2783 2784 /* Get the polling interval */ 2785 interval = endpoint->bInterval; 2786 2787 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2788 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2789 2790 /* 2791 * According USB 2.0 Specifications, a high-speed endpoint's 2792 * polling intervals are specified interms of 125us or micro 2793 * frame, where as full/low endpoint's polling intervals are 2794 * specified in milliseconds. 2795 * 2796 * A high speed interrupt/isochronous endpoints can specify 2797 * desired polling interval between 1 to 16 micro-frames, 2798 * where as full/low endpoints can specify between 1 to 255 2799 * milliseconds. 2800 */ 2801 switch (port_status) { 2802 case USBA_LOW_SPEED_DEV: 2803 /* 2804 * Low speed endpoints are limited to specifying 2805 * only 8ms to 255ms in this driver. If a device 2806 * reports a polling interval that is less than 8ms, 2807 * it will use 8 ms instead. 2808 */ 2809 if (interval < LS_MIN_POLL_INTERVAL) { 2810 2811 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2812 "Low speed endpoint's poll interval of %d ms " 2813 "is below threshold. Rounding up to %d ms", 2814 interval, LS_MIN_POLL_INTERVAL); 2815 2816 interval = LS_MIN_POLL_INTERVAL; 2817 } 2818 2819 /* 2820 * Return an error if the polling interval is greater 2821 * than 255ms. 2822 */ 2823 if (interval > LS_MAX_POLL_INTERVAL) { 2824 2825 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2826 "Low speed endpoint's poll interval is " 2827 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2828 2829 return (USB_FAILURE); 2830 } 2831 break; 2832 2833 case USBA_FULL_SPEED_DEV: 2834 /* 2835 * Return an error if the polling interval is less 2836 * than 1ms and greater than 255ms. 2837 */ 2838 if ((interval < FS_MIN_POLL_INTERVAL) && 2839 (interval > FS_MAX_POLL_INTERVAL)) { 2840 2841 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2842 "Full speed endpoint's poll interval must " 2843 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2844 FS_MAX_POLL_INTERVAL); 2845 2846 return (USB_FAILURE); 2847 } 2848 break; 2849 case USBA_HIGH_SPEED_DEV: 2850 /* 2851 * Return an error if the polling interval is less 1 2852 * and greater than 16. Convert this value to 125us 2853 * units using 2^(bInterval -1). refer usb 2.0 spec 2854 * page 51 for details. 2855 */ 2856 if ((interval < HS_MIN_POLL_INTERVAL) && 2857 (interval > HS_MAX_POLL_INTERVAL)) { 2858 2859 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2860 "High speed endpoint's poll interval " 2861 "must be between %d and %d units", 2862 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2863 2864 return (USB_FAILURE); 2865 } 2866 2867 /* Adjust high speed device polling interval */ 2868 interval = 2869 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2870 2871 break; 2872 } 2873 2874 /* 2875 * If polling interval is greater than 32ms, 2876 * adjust polling interval equal to 32ms. 2877 */ 2878 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2879 interval = EHCI_NUM_INTR_QH_LISTS; 2880 } 2881 2882 /* 2883 * Find the nearest power of 2 that's less 2884 * than interval. 2885 */ 2886 while ((ehci_pow_2(i)) <= interval) { 2887 i++; 2888 } 2889 2890 return (ehci_pow_2((i - 1))); 2891 } 2892 2893 2894 /* 2895 * ehci_adjust_high_speed_polling_interval: 2896 */ 2897 /* ARGSUSED */ 2898 static int 2899 ehci_adjust_high_speed_polling_interval( 2900 ehci_state_t *ehcip, 2901 usb_ep_descr_t *endpoint) 2902 { 2903 uint_t interval; 2904 2905 /* Get the polling interval */ 2906 interval = ehci_pow_2(endpoint->bInterval - 1); 2907 2908 /* 2909 * Convert polling interval from micro seconds 2910 * to milli seconds. 2911 */ 2912 if (interval <= EHCI_MAX_UFRAMES) { 2913 interval = 1; 2914 } else { 2915 interval = interval/EHCI_MAX_UFRAMES; 2916 } 2917 2918 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2919 "ehci_adjust_high_speed_polling_interval: " 2920 "High speed adjusted interval 0x%x", interval); 2921 2922 return (interval); 2923 } 2924 2925 2926 /* 2927 * ehci_lattice_height: 2928 * 2929 * Given the requested bandwidth, find the height in the tree at which the 2930 * nodes for this bandwidth fall. The height is measured as the number of 2931 * nodes from the leaf to the level specified by bandwidth The root of the 2932 * tree is at height TREE_HEIGHT. 2933 */ 2934 static uint_t 2935 ehci_lattice_height(uint_t interval) 2936 { 2937 return (TREE_HEIGHT - (ehci_log_2(interval))); 2938 } 2939 2940 2941 /* 2942 * ehci_lattice_parent: 2943 * 2944 * Given a node in the lattice, find the index of the parent node 2945 */ 2946 static uint_t 2947 ehci_lattice_parent(uint_t node) 2948 { 2949 if ((node % 2) == 0) { 2950 2951 return ((node/2) - 1); 2952 } else { 2953 2954 return ((node + 1)/2 - 1); 2955 } 2956 } 2957 2958 2959 /* 2960 * ehci_find_periodic_node: 2961 * 2962 * Based on the "real" array leaf node and interval, get the periodic node. 2963 */ 2964 static uint_t 2965 ehci_find_periodic_node(uint_t leaf, int interval) { 2966 uint_t lattice_leaf; 2967 uint_t height = ehci_lattice_height(interval); 2968 uint_t pnode; 2969 int i; 2970 2971 /* Get the leaf number in the lattice */ 2972 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2973 2974 /* Get the node in the lattice based on the height and leaf */ 2975 pnode = lattice_leaf; 2976 for (i = 0; i < height; i++) { 2977 pnode = ehci_lattice_parent(pnode); 2978 } 2979 2980 return (pnode); 2981 } 2982 2983 2984 /* 2985 * ehci_leftmost_leaf: 2986 * 2987 * Find the leftmost leaf in the subtree specified by the node. Height refers 2988 * to number of nodes from the bottom of the tree to the node, including the 2989 * node. 2990 * 2991 * The formula for a zero based tree is: 2992 * 2^H * Node + 2^H - 1 2993 * The leaf of the tree is an array, convert the number for the array. 2994 * Subtract the size of nodes not in the array 2995 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 2996 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 2997 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 2998 * 0 2999 * 1 2 3000 * 0 1 2 3 3001 */ 3002 static uint_t 3003 ehci_leftmost_leaf( 3004 uint_t node, 3005 uint_t height) 3006 { 3007 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 3008 } 3009 3010 3011 /* 3012 * ehci_pow_2: 3013 * 3014 * Compute 2 to the power 3015 */ 3016 static uint_t 3017 ehci_pow_2(uint_t x) 3018 { 3019 if (x == 0) { 3020 3021 return (1); 3022 } else { 3023 3024 return (2 << (x - 1)); 3025 } 3026 } 3027 3028 3029 /* 3030 * ehci_log_2: 3031 * 3032 * Compute log base 2 of x 3033 */ 3034 static uint_t 3035 ehci_log_2(uint_t x) 3036 { 3037 int i = 0; 3038 3039 while (x != 1) { 3040 x = x >> 1; 3041 i++; 3042 } 3043 3044 return (i); 3045 } 3046 3047 3048 /* 3049 * ehci_find_bestfit_hs_mask: 3050 * 3051 * Find the smask and cmask in the bandwidth allocation, and update the 3052 * bandwidth allocation. 3053 */ 3054 static int 3055 ehci_find_bestfit_hs_mask( 3056 ehci_state_t *ehcip, 3057 uchar_t *smask, 3058 uint_t *pnode, 3059 usb_ep_descr_t *endpoint, 3060 uint_t bandwidth, 3061 int interval) 3062 { 3063 int i; 3064 uint_t elements, index; 3065 int array_leaf, best_array_leaf; 3066 uint_t node_bandwidth, best_node_bandwidth; 3067 uint_t leaf_count; 3068 uchar_t bw_mask; 3069 uchar_t best_smask; 3070 3071 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3072 "ehci_find_bestfit_hs_mask: "); 3073 3074 /* Get all the valid smasks */ 3075 switch (ehci_pow_2(endpoint->bInterval - 1)) { 3076 case EHCI_INTR_1US_POLL: 3077 index = EHCI_1US_MASK_INDEX; 3078 elements = EHCI_INTR_1US_POLL; 3079 break; 3080 case EHCI_INTR_2US_POLL: 3081 index = EHCI_2US_MASK_INDEX; 3082 elements = EHCI_INTR_2US_POLL; 3083 break; 3084 case EHCI_INTR_4US_POLL: 3085 index = EHCI_4US_MASK_INDEX; 3086 elements = EHCI_INTR_4US_POLL; 3087 break; 3088 case EHCI_INTR_XUS_POLL: 3089 default: 3090 index = EHCI_XUS_MASK_INDEX; 3091 elements = EHCI_INTR_XUS_POLL; 3092 break; 3093 } 3094 3095 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3096 3097 /* 3098 * Because of the way the leaves are setup, we will automatically 3099 * hit the leftmost leaf of every possible node with this interval. 3100 */ 3101 best_smask = 0x00; 3102 best_node_bandwidth = 0; 3103 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3104 /* Find the bandwidth mask */ 3105 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 3106 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 3107 3108 /* 3109 * If this node cannot support our requirements skip to the 3110 * next leaf. 3111 */ 3112 if (bw_mask == 0x00) { 3113 continue; 3114 } 3115 3116 /* 3117 * Now make sure our bandwidth requirements can be 3118 * satisfied with one of smasks in this node. 3119 */ 3120 *smask = 0x00; 3121 for (i = index; i < (index + elements); i++) { 3122 /* Check the start split mask value */ 3123 if (ehci_start_split_mask[index] & bw_mask) { 3124 *smask = ehci_start_split_mask[index]; 3125 break; 3126 } 3127 } 3128 3129 /* 3130 * If an appropriate smask is found save the information if: 3131 * o best_smask has not been found yet. 3132 * - or - 3133 * o This is the node with the least amount of bandwidth 3134 */ 3135 if ((*smask != 0x00) && 3136 ((best_smask == 0x00) || 3137 (best_node_bandwidth > node_bandwidth))) { 3138 3139 best_node_bandwidth = node_bandwidth; 3140 best_array_leaf = array_leaf; 3141 best_smask = *smask; 3142 } 3143 } 3144 3145 /* 3146 * If we find node that can handle the bandwidth populate the 3147 * appropriate variables and return success. 3148 */ 3149 if (best_smask) { 3150 *smask = best_smask; 3151 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3152 interval); 3153 ehci_update_bw_availability(ehcip, bandwidth, 3154 ehci_index[best_array_leaf], leaf_count, best_smask); 3155 3156 return (USB_SUCCESS); 3157 } 3158 3159 return (USB_FAILURE); 3160 } 3161 3162 3163 /* 3164 * ehci_find_bestfit_ls_intr_mask: 3165 * 3166 * Find the smask and cmask in the bandwidth allocation. 3167 */ 3168 static int 3169 ehci_find_bestfit_ls_intr_mask( 3170 ehci_state_t *ehcip, 3171 uchar_t *smask, 3172 uchar_t *cmask, 3173 uint_t *pnode, 3174 uint_t sbandwidth, 3175 uint_t cbandwidth, 3176 int interval) 3177 { 3178 int i; 3179 uint_t elements, index; 3180 int array_leaf, best_array_leaf; 3181 uint_t node_sbandwidth, node_cbandwidth; 3182 uint_t best_node_bandwidth; 3183 uint_t leaf_count; 3184 uchar_t bw_smask, bw_cmask; 3185 uchar_t best_smask, best_cmask; 3186 3187 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3188 "ehci_find_bestfit_ls_intr_mask: "); 3189 3190 /* For low and full speed devices */ 3191 index = EHCI_XUS_MASK_INDEX; 3192 elements = EHCI_INTR_4MS_POLL; 3193 3194 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3195 3196 /* 3197 * Because of the way the leaves are setup, we will automatically 3198 * hit the leftmost leaf of every possible node with this interval. 3199 */ 3200 best_smask = 0x00; 3201 best_node_bandwidth = 0; 3202 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3203 /* Find the bandwidth mask */ 3204 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3205 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3206 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3207 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 3208 3209 /* 3210 * If this node cannot support our requirements skip to the 3211 * next leaf. 3212 */ 3213 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3214 continue; 3215 } 3216 3217 /* 3218 * Now make sure our bandwidth requirements can be 3219 * satisfied with one of smasks in this node. 3220 */ 3221 *smask = 0x00; 3222 *cmask = 0x00; 3223 for (i = index; i < (index + elements); i++) { 3224 /* Check the start split mask value */ 3225 if ((ehci_start_split_mask[index] & bw_smask) && 3226 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 3227 *smask = ehci_start_split_mask[index]; 3228 *cmask = ehci_intr_complete_split_mask[index]; 3229 break; 3230 } 3231 } 3232 3233 /* 3234 * If an appropriate smask is found save the information if: 3235 * o best_smask has not been found yet. 3236 * - or - 3237 * o This is the node with the least amount of bandwidth 3238 */ 3239 if ((*smask != 0x00) && 3240 ((best_smask == 0x00) || 3241 (best_node_bandwidth > 3242 (node_sbandwidth + node_cbandwidth)))) { 3243 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3244 best_array_leaf = array_leaf; 3245 best_smask = *smask; 3246 best_cmask = *cmask; 3247 } 3248 } 3249 3250 /* 3251 * If we find node that can handle the bandwidth populate the 3252 * appropriate variables and return success. 3253 */ 3254 if (best_smask) { 3255 *smask = best_smask; 3256 *cmask = best_cmask; 3257 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3258 interval); 3259 ehci_update_bw_availability(ehcip, sbandwidth, 3260 ehci_index[best_array_leaf], leaf_count, best_smask); 3261 ehci_update_bw_availability(ehcip, cbandwidth, 3262 ehci_index[best_array_leaf], leaf_count, best_cmask); 3263 3264 return (USB_SUCCESS); 3265 } 3266 3267 return (USB_FAILURE); 3268 } 3269 3270 3271 /* 3272 * ehci_find_bestfit_sitd_in_mask: 3273 * 3274 * Find the smask and cmask in the bandwidth allocation. 3275 */ 3276 static int 3277 ehci_find_bestfit_sitd_in_mask( 3278 ehci_state_t *ehcip, 3279 uchar_t *smask, 3280 uchar_t *cmask, 3281 uint_t *pnode, 3282 uint_t sbandwidth, 3283 uint_t cbandwidth, 3284 int interval) 3285 { 3286 int i, uFrames, found; 3287 int array_leaf, best_array_leaf; 3288 uint_t node_sbandwidth, node_cbandwidth; 3289 uint_t best_node_bandwidth; 3290 uint_t leaf_count; 3291 uchar_t bw_smask, bw_cmask; 3292 uchar_t best_smask, best_cmask; 3293 3294 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3295 "ehci_find_bestfit_sitd_in_mask: "); 3296 3297 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3298 3299 /* 3300 * Because of the way the leaves are setup, we will automatically 3301 * hit the leftmost leaf of every possible node with this interval. 3302 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3303 */ 3304 /* 3305 * Need to add an additional 2 uFrames, if the "L"ast 3306 * complete split is before uFrame 6. See section 3307 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3308 * the "Back Ptr" which means we support on IN of 3309 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3310 */ 3311 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3312 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3313 uFrames++; 3314 } 3315 if (uFrames > 6) { 3316 3317 return (USB_FAILURE); 3318 } 3319 *smask = 0x1; 3320 *cmask = 0x00; 3321 for (i = 0; i < uFrames; i++) { 3322 *cmask = *cmask << 1; 3323 *cmask |= 0x1; 3324 } 3325 /* cmask must start 2 frames after the smask */ 3326 *cmask = *cmask << 2; 3327 3328 found = 0; 3329 best_smask = 0x00; 3330 best_node_bandwidth = 0; 3331 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3332 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3333 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3334 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3335 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3336 &bw_cmask); 3337 3338 /* 3339 * If this node cannot support our requirements skip to the 3340 * next leaf. 3341 */ 3342 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3343 continue; 3344 } 3345 3346 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3347 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3348 found = 1; 3349 break; 3350 } 3351 *smask = *smask << 1; 3352 *cmask = *cmask << 1; 3353 } 3354 3355 /* 3356 * If an appropriate smask is found save the information if: 3357 * o best_smask has not been found yet. 3358 * - or - 3359 * o This is the node with the least amount of bandwidth 3360 */ 3361 if (found && 3362 ((best_smask == 0x00) || 3363 (best_node_bandwidth > 3364 (node_sbandwidth + node_cbandwidth)))) { 3365 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3366 best_array_leaf = array_leaf; 3367 best_smask = *smask; 3368 best_cmask = *cmask; 3369 } 3370 } 3371 3372 /* 3373 * If we find node that can handle the bandwidth populate the 3374 * appropriate variables and return success. 3375 */ 3376 if (best_smask) { 3377 *smask = best_smask; 3378 *cmask = best_cmask; 3379 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3380 interval); 3381 ehci_update_bw_availability(ehcip, sbandwidth, 3382 ehci_index[best_array_leaf], leaf_count, best_smask); 3383 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3384 ehci_index[best_array_leaf], leaf_count, best_cmask); 3385 3386 return (USB_SUCCESS); 3387 } 3388 3389 return (USB_FAILURE); 3390 } 3391 3392 3393 /* 3394 * ehci_find_bestfit_sitd_out_mask: 3395 * 3396 * Find the smask in the bandwidth allocation. 3397 */ 3398 static int 3399 ehci_find_bestfit_sitd_out_mask( 3400 ehci_state_t *ehcip, 3401 uchar_t *smask, 3402 uint_t *pnode, 3403 uint_t sbandwidth, 3404 int interval) 3405 { 3406 int i, uFrames, found; 3407 int array_leaf, best_array_leaf; 3408 uint_t node_sbandwidth; 3409 uint_t best_node_bandwidth; 3410 uint_t leaf_count; 3411 uchar_t bw_smask; 3412 uchar_t best_smask; 3413 3414 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3415 "ehci_find_bestfit_sitd_out_mask: "); 3416 3417 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3418 3419 /* 3420 * Because of the way the leaves are setup, we will automatically 3421 * hit the leftmost leaf of every possible node with this interval. 3422 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3423 */ 3424 *smask = 0x00; 3425 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3426 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3427 uFrames++; 3428 } 3429 for (i = 0; i < uFrames; i++) { 3430 *smask = *smask << 1; 3431 *smask |= 0x1; 3432 } 3433 3434 found = 0; 3435 best_smask = 0x00; 3436 best_node_bandwidth = 0; 3437 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3438 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3439 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3440 &bw_smask); 3441 3442 /* 3443 * If this node cannot support our requirements skip to the 3444 * next leaf. 3445 */ 3446 if (bw_smask == 0x00) { 3447 continue; 3448 } 3449 3450 /* You cannot have a start split on the 8th uFrame */ 3451 for (i = 0; (*smask & 0x80) == 0; i++) { 3452 if (*smask & bw_smask) { 3453 found = 1; 3454 break; 3455 } 3456 *smask = *smask << 1; 3457 } 3458 3459 /* 3460 * If an appropriate smask is found save the information if: 3461 * o best_smask has not been found yet. 3462 * - or - 3463 * o This is the node with the least amount of bandwidth 3464 */ 3465 if (found && 3466 ((best_smask == 0x00) || 3467 (best_node_bandwidth > node_sbandwidth))) { 3468 best_node_bandwidth = node_sbandwidth; 3469 best_array_leaf = array_leaf; 3470 best_smask = *smask; 3471 } 3472 } 3473 3474 /* 3475 * If we find node that can handle the bandwidth populate the 3476 * appropriate variables and return success. 3477 */ 3478 if (best_smask) { 3479 *smask = best_smask; 3480 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3481 interval); 3482 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3483 ehci_index[best_array_leaf], leaf_count, best_smask); 3484 3485 return (USB_SUCCESS); 3486 } 3487 3488 return (USB_FAILURE); 3489 } 3490 3491 3492 /* 3493 * ehci_calculate_bw_availability_mask: 3494 * 3495 * Returns the "total bandwidth used" in this node. 3496 * Populates bw_mask with the uFrames that can support the bandwidth. 3497 * 3498 * If all the Frames cannot support this bandwidth, then bw_mask 3499 * will return 0x00 and the "total bandwidth used" will be invalid. 3500 */ 3501 static uint_t 3502 ehci_calculate_bw_availability_mask( 3503 ehci_state_t *ehcip, 3504 uint_t bandwidth, 3505 int leaf, 3506 int leaf_count, 3507 uchar_t *bw_mask) 3508 { 3509 int i, j; 3510 uchar_t bw_uframe; 3511 int uframe_total; 3512 ehci_frame_bandwidth_t *fbp; 3513 uint_t total_bandwidth = 0; 3514 3515 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3516 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3517 leaf, leaf_count); 3518 3519 /* Start by saying all uFrames are available */ 3520 *bw_mask = 0xFF; 3521 3522 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3523 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3524 3525 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3526 3527 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3528 /* 3529 * If the uFrame in bw_mask is available check to see if 3530 * it can support the additional bandwidth. 3531 */ 3532 bw_uframe = (*bw_mask & (0x1 << j)); 3533 uframe_total = 3534 fbp->ehci_micro_frame_bandwidth[j] + 3535 bandwidth; 3536 if ((bw_uframe) && 3537 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3538 *bw_mask = *bw_mask & ~bw_uframe; 3539 } 3540 } 3541 } 3542 3543 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3544 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3545 *bw_mask); 3546 3547 return (total_bandwidth); 3548 } 3549 3550 3551 /* 3552 * ehci_update_bw_availability: 3553 * 3554 * The leftmost leaf needs to be in terms of array position and 3555 * not the actual lattice position. 3556 */ 3557 static void 3558 ehci_update_bw_availability( 3559 ehci_state_t *ehcip, 3560 int bandwidth, 3561 int leftmost_leaf, 3562 int leaf_count, 3563 uchar_t mask) 3564 { 3565 int i, j; 3566 ehci_frame_bandwidth_t *fbp; 3567 int uFrame_bandwidth[8]; 3568 3569 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3570 "ehci_update_bw_availability: " 3571 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3572 leftmost_leaf, leaf_count, bandwidth, mask); 3573 3574 ASSERT(leftmost_leaf < 32); 3575 ASSERT(leftmost_leaf >= 0); 3576 3577 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3578 if (mask & 0x1) { 3579 uFrame_bandwidth[j] = bandwidth; 3580 } else { 3581 uFrame_bandwidth[j] = 0; 3582 } 3583 3584 mask = mask >> 1; 3585 } 3586 3587 /* Updated all the effected leafs with the bandwidth */ 3588 for (i = 0; i < leaf_count; i++) { 3589 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3590 3591 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3592 fbp->ehci_micro_frame_bandwidth[j] += 3593 uFrame_bandwidth[j]; 3594 fbp->ehci_allocated_frame_bandwidth += 3595 uFrame_bandwidth[j]; 3596 } 3597 } 3598 } 3599 3600 /* 3601 * Miscellaneous functions 3602 */ 3603 3604 /* 3605 * ehci_obtain_state: 3606 * 3607 * NOTE: This function is also called from POLLED MODE. 3608 */ 3609 ehci_state_t * 3610 ehci_obtain_state(dev_info_t *dip) 3611 { 3612 int instance = ddi_get_instance(dip); 3613 3614 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3615 3616 ASSERT(state != NULL); 3617 3618 return (state); 3619 } 3620 3621 3622 /* 3623 * ehci_state_is_operational: 3624 * 3625 * Check the Host controller state and return proper values. 3626 */ 3627 int 3628 ehci_state_is_operational(ehci_state_t *ehcip) 3629 { 3630 int val; 3631 3632 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3633 3634 switch (ehcip->ehci_hc_soft_state) { 3635 case EHCI_CTLR_INIT_STATE: 3636 case EHCI_CTLR_SUSPEND_STATE: 3637 val = USB_FAILURE; 3638 break; 3639 case EHCI_CTLR_OPERATIONAL_STATE: 3640 val = USB_SUCCESS; 3641 break; 3642 case EHCI_CTLR_ERROR_STATE: 3643 val = USB_HC_HARDWARE_ERROR; 3644 break; 3645 default: 3646 val = USB_FAILURE; 3647 break; 3648 } 3649 3650 return (val); 3651 } 3652 3653 3654 /* 3655 * ehci_do_soft_reset 3656 * 3657 * Do soft reset of ehci host controller. 3658 */ 3659 int 3660 ehci_do_soft_reset(ehci_state_t *ehcip) 3661 { 3662 usb_frame_number_t before_frame_number, after_frame_number; 3663 ehci_regs_t *ehci_save_regs; 3664 3665 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3666 3667 /* Increment host controller error count */ 3668 ehcip->ehci_hc_error++; 3669 3670 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3671 "ehci_do_soft_reset:" 3672 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3673 3674 /* 3675 * Allocate space for saving current Host Controller 3676 * registers. Don't do any recovery if allocation 3677 * fails. 3678 */ 3679 ehci_save_regs = (ehci_regs_t *) 3680 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3681 3682 if (ehci_save_regs == NULL) { 3683 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3684 "ehci_do_soft_reset: kmem_zalloc failed"); 3685 3686 return (USB_FAILURE); 3687 } 3688 3689 /* Save current ehci registers */ 3690 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3691 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3692 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3693 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3694 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3695 ehci_save_regs->ehci_periodic_list_base = 3696 Get_OpReg(ehci_periodic_list_base); 3697 3698 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3699 "ehci_do_soft_reset: Save reg = 0x%p", (void *)ehci_save_regs); 3700 3701 /* Disable all list processing and interrupts */ 3702 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3703 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3704 3705 /* Disable all EHCI interrupts */ 3706 Set_OpReg(ehci_interrupt, 0); 3707 3708 /* Wait for few milliseconds */ 3709 drv_usecwait(EHCI_SOF_TIMEWAIT); 3710 3711 /* Do light soft reset of ehci host controller */ 3712 Set_OpReg(ehci_command, 3713 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3714 3715 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3716 "ehci_do_soft_reset: Reset in progress"); 3717 3718 /* Wait for reset to complete */ 3719 drv_usecwait(EHCI_RESET_TIMEWAIT); 3720 3721 /* 3722 * Restore previous saved EHCI register value 3723 * into the current EHCI registers. 3724 */ 3725 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3726 ehci_save_regs->ehci_ctrl_segment); 3727 3728 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3729 ehci_save_regs->ehci_periodic_list_base); 3730 3731 Set_OpReg(ehci_async_list_addr, (uint32_t) 3732 ehci_save_regs->ehci_async_list_addr); 3733 3734 /* 3735 * For some reason this register might get nulled out by 3736 * the Uli M1575 South Bridge. To workaround the hardware 3737 * problem, check the value after write and retry if the 3738 * last write fails. 3739 */ 3740 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 3741 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 3742 (ehci_save_regs->ehci_async_list_addr != 3743 Get_OpReg(ehci_async_list_addr))) { 3744 int retry = 0; 3745 3746 Set_OpRegRetry(ehci_async_list_addr, (uint32_t) 3747 ehci_save_regs->ehci_async_list_addr, retry); 3748 if (retry >= EHCI_MAX_RETRY) { 3749 USB_DPRINTF_L2(PRINT_MASK_ATTA, 3750 ehcip->ehci_log_hdl, "ehci_do_soft_reset:" 3751 " ASYNCLISTADDR write failed."); 3752 3753 return (USB_FAILURE); 3754 } 3755 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3756 "ehci_do_soft_reset: ASYNCLISTADDR " 3757 "write failed, retry=%d", retry); 3758 } 3759 3760 Set_OpReg(ehci_config_flag, (uint32_t) 3761 ehci_save_regs->ehci_config_flag); 3762 3763 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3764 ehci_toggle_scheduler(ehcip); 3765 3766 /* 3767 * Set ehci_interrupt to enable all interrupts except Root 3768 * Hub Status change and frame list rollover interrupts. 3769 */ 3770 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3771 EHCI_INTR_FRAME_LIST_ROLLOVER | 3772 EHCI_INTR_USB_ERROR | 3773 EHCI_INTR_USB); 3774 3775 /* 3776 * Deallocate the space that allocated for saving 3777 * HC registers. 3778 */ 3779 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3780 3781 /* 3782 * Set the desired interrupt threshold, frame list size (if 3783 * applicable) and turn EHCI host controller. 3784 */ 3785 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3786 ~EHCI_CMD_INTR_THRESHOLD) | 3787 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3788 3789 /* Wait 10ms for EHCI to start sending SOF */ 3790 drv_usecwait(EHCI_RESET_TIMEWAIT); 3791 3792 /* 3793 * Get the current usb frame number before waiting for 3794 * few milliseconds. 3795 */ 3796 before_frame_number = ehci_get_current_frame_number(ehcip); 3797 3798 /* Wait for few milliseconds */ 3799 drv_usecwait(EHCI_SOF_TIMEWAIT); 3800 3801 /* 3802 * Get the current usb frame number after waiting for 3803 * few milliseconds. 3804 */ 3805 after_frame_number = ehci_get_current_frame_number(ehcip); 3806 3807 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3808 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3809 "After Frame Number 0x%llx", 3810 (unsigned long long)before_frame_number, 3811 (unsigned long long)after_frame_number); 3812 3813 if ((after_frame_number <= before_frame_number) && 3814 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3815 3816 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3817 "ehci_do_soft_reset: Soft reset failed"); 3818 3819 return (USB_FAILURE); 3820 } 3821 3822 return (USB_SUCCESS); 3823 } 3824 3825 3826 /* 3827 * ehci_get_xfer_attrs: 3828 * 3829 * Get the attributes of a particular xfer. 3830 * 3831 * NOTE: This function is also called from POLLED MODE. 3832 */ 3833 usb_req_attrs_t 3834 ehci_get_xfer_attrs( 3835 ehci_state_t *ehcip, 3836 ehci_pipe_private_t *pp, 3837 ehci_trans_wrapper_t *tw) 3838 { 3839 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3840 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3841 3842 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3843 "ehci_get_xfer_attrs:"); 3844 3845 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3846 case USB_EP_ATTR_CONTROL: 3847 attrs = ((usb_ctrl_req_t *) 3848 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3849 break; 3850 case USB_EP_ATTR_BULK: 3851 attrs = ((usb_bulk_req_t *) 3852 tw->tw_curr_xfer_reqp)->bulk_attributes; 3853 break; 3854 case USB_EP_ATTR_INTR: 3855 attrs = ((usb_intr_req_t *) 3856 tw->tw_curr_xfer_reqp)->intr_attributes; 3857 break; 3858 } 3859 3860 return (attrs); 3861 } 3862 3863 3864 /* 3865 * ehci_get_current_frame_number: 3866 * 3867 * Get the current software based usb frame number. 3868 */ 3869 usb_frame_number_t 3870 ehci_get_current_frame_number(ehci_state_t *ehcip) 3871 { 3872 usb_frame_number_t usb_frame_number; 3873 usb_frame_number_t ehci_fno, micro_frame_number; 3874 3875 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3876 3877 ehci_fno = ehcip->ehci_fno; 3878 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3879 3880 /* 3881 * Calculate current software based usb frame number. 3882 * 3883 * This code accounts for the fact that frame number is 3884 * updated by the Host Controller before the ehci driver 3885 * gets an FrameListRollover interrupt that will adjust 3886 * Frame higher part. 3887 * 3888 * Refer ehci specification 1.0, section 2.3.2, page 21. 3889 */ 3890 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3891 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3892 ehci_fno) & 0x2000); 3893 3894 /* 3895 * Micro Frame number is equivalent to 125 usec. Eight 3896 * Micro Frame numbers are equivalent to one millsecond 3897 * or one usb frame number. 3898 */ 3899 usb_frame_number = micro_frame_number >> 3900 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3901 3902 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3903 "ehci_get_current_frame_number: " 3904 "Current usb uframe number = 0x%llx " 3905 "Current usb frame number = 0x%llx", 3906 (unsigned long long)micro_frame_number, 3907 (unsigned long long)usb_frame_number); 3908 3909 return (usb_frame_number); 3910 } 3911 3912 3913 /* 3914 * ehci_cpr_cleanup: 3915 * 3916 * Cleanup ehci state and other ehci specific informations across 3917 * Check Point Resume (CPR). 3918 */ 3919 static void 3920 ehci_cpr_cleanup(ehci_state_t *ehcip) 3921 { 3922 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3923 3924 /* Reset software part of usb frame number */ 3925 ehcip->ehci_fno = 0; 3926 } 3927 3928 3929 /* 3930 * ehci_wait_for_sof: 3931 * 3932 * Wait for couple of SOF interrupts 3933 */ 3934 int 3935 ehci_wait_for_sof(ehci_state_t *ehcip) 3936 { 3937 usb_frame_number_t before_frame_number, after_frame_number; 3938 int error = USB_SUCCESS; 3939 3940 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3941 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3942 3943 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3944 3945 error = ehci_state_is_operational(ehcip); 3946 3947 if (error != USB_SUCCESS) { 3948 3949 return (error); 3950 } 3951 3952 /* Get the current usb frame number before waiting for two SOFs */ 3953 before_frame_number = ehci_get_current_frame_number(ehcip); 3954 3955 mutex_exit(&ehcip->ehci_int_mutex); 3956 3957 /* Wait for few milliseconds */ 3958 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3959 3960 mutex_enter(&ehcip->ehci_int_mutex); 3961 3962 /* Get the current usb frame number after woken up */ 3963 after_frame_number = ehci_get_current_frame_number(ehcip); 3964 3965 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3966 "ehci_wait_for_sof: framenumber: before 0x%llx " 3967 "after 0x%llx", 3968 (unsigned long long)before_frame_number, 3969 (unsigned long long)after_frame_number); 3970 3971 /* Return failure, if usb frame number has not been changed */ 3972 if (after_frame_number <= before_frame_number) { 3973 3974 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3975 3976 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3977 ehcip->ehci_log_hdl, "No SOF interrupts"); 3978 3979 /* Set host controller soft state to error */ 3980 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 3981 3982 return (USB_FAILURE); 3983 } 3984 3985 } 3986 3987 return (USB_SUCCESS); 3988 } 3989 3990 3991 /* 3992 * ehci_toggle_scheduler: 3993 * 3994 * Turn scheduler based on pipe open count. 3995 */ 3996 void 3997 ehci_toggle_scheduler(ehci_state_t *ehcip) { 3998 uint_t temp_reg, cmd_reg; 3999 4000 cmd_reg = Get_OpReg(ehci_command); 4001 temp_reg = cmd_reg; 4002 4003 /* 4004 * Enable/Disable asynchronous scheduler, and 4005 * turn on/off async list door bell 4006 */ 4007 if (ehcip->ehci_open_async_count) { 4008 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 4009 /* 4010 * For some reason this address might get nulled out by 4011 * the ehci chip. Set it here just in case it is null. 4012 */ 4013 Set_OpReg(ehci_async_list_addr, 4014 ehci_qh_cpu_to_iommu(ehcip, 4015 ehcip->ehci_head_of_async_sched_list)); 4016 4017 /* 4018 * For some reason this register might get nulled out by 4019 * the Uli M1575 Southbridge. To workaround the HW 4020 * problem, check the value after write and retry if the 4021 * last write fails. 4022 * 4023 * If the ASYNCLISTADDR remains "stuck" after 4024 * EHCI_MAX_RETRY retries, then the M1575 is broken 4025 * and is stuck in an inconsistent state and is about 4026 * to crash the machine with a trn_oor panic when it 4027 * does a DMA read from 0x0. It is better to panic 4028 * now rather than wait for the trn_oor crash; this 4029 * way Customer Service will have a clean signature 4030 * that indicts the M1575 chip rather than a 4031 * mysterious and hard-to-diagnose trn_oor panic. 4032 */ 4033 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 4034 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 4035 (ehci_qh_cpu_to_iommu(ehcip, 4036 ehcip->ehci_head_of_async_sched_list) != 4037 Get_OpReg(ehci_async_list_addr))) { 4038 int retry = 0; 4039 4040 Set_OpRegRetry(ehci_async_list_addr, 4041 ehci_qh_cpu_to_iommu(ehcip, 4042 ehcip->ehci_head_of_async_sched_list), 4043 retry); 4044 if (retry >= EHCI_MAX_RETRY) 4045 cmn_err(CE_PANIC, 4046 "ehci_toggle_scheduler: " 4047 "ASYNCLISTADDR write failed."); 4048 4049 USB_DPRINTF_L2(PRINT_MASK_ATTA, 4050 ehcip->ehci_log_hdl, 4051 "ehci_toggle_scheduler: ASYNCLISTADDR " 4052 "write failed, retry=%d", retry); 4053 } 4054 } 4055 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 4056 } else { 4057 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 4058 } 4059 4060 if (ehcip->ehci_open_periodic_count) { 4061 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 4062 /* 4063 * For some reason this address get's nulled out by 4064 * the ehci chip. Set it here just in case it is null. 4065 */ 4066 Set_OpReg(ehci_periodic_list_base, 4067 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 4068 0xFFFFF000)); 4069 } 4070 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 4071 } else { 4072 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 4073 } 4074 4075 /* Just an optimization */ 4076 if (temp_reg != cmd_reg) { 4077 Set_OpReg(ehci_command, cmd_reg); 4078 } 4079 } 4080 4081 /* 4082 * ehci print functions 4083 */ 4084 4085 /* 4086 * ehci_print_caps: 4087 */ 4088 void 4089 ehci_print_caps(ehci_state_t *ehcip) 4090 { 4091 uint_t i; 4092 4093 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4094 "\n\tUSB 2.0 Host Controller Characteristics\n"); 4095 4096 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4097 "Caps Length: 0x%x Version: 0x%x\n", 4098 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 4099 4100 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4101 "Structural Parameters\n"); 4102 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4103 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 4104 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 4105 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4106 "No of Classic host controllers: 0x%x", 4107 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 4108 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 4109 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4110 "No of ports per Classic host controller: 0x%x", 4111 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 4112 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 4113 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4114 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 4115 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 4116 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4117 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 4118 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 4119 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4120 "No of root hub ports: 0x%x\n", 4121 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 4122 4123 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4124 "Capability Parameters\n"); 4125 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4126 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 4127 EHCI_HCC_EECP) ? "Yes" : "No"); 4128 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4129 "Isoch schedule threshold: 0x%x", 4130 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 4131 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4132 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 4133 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 4134 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4135 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 4136 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 4137 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4138 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 4139 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 4140 4141 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4142 "Classic Port Route Description"); 4143 4144 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4145 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4146 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 4147 } 4148 } 4149 4150 4151 /* 4152 * ehci_print_regs: 4153 */ 4154 void 4155 ehci_print_regs(ehci_state_t *ehcip) 4156 { 4157 uint_t i; 4158 4159 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4160 "\n\tEHCI%d Operational Registers\n", 4161 ddi_get_instance(ehcip->ehci_dip)); 4162 4163 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4164 "Command: 0x%x Status: 0x%x", 4165 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 4166 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4167 "Interrupt: 0x%x Frame Index: 0x%x", 4168 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 4169 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4170 "Control Segment: 0x%x Periodic List Base: 0x%x", 4171 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 4172 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4173 "Async List Addr: 0x%x Config Flag: 0x%x", 4174 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 4175 4176 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4177 "Root Hub Port Status"); 4178 4179 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4180 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4181 "\tPort Status 0x%x: 0x%x ", i, 4182 Get_OpReg(ehci_rh_port_status[i])); 4183 } 4184 } 4185 4186 4187 /* 4188 * ehci_print_qh: 4189 */ 4190 void 4191 ehci_print_qh( 4192 ehci_state_t *ehcip, 4193 ehci_qh_t *qh) 4194 { 4195 uint_t i; 4196 4197 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4198 "ehci_print_qh: qh = 0x%p", (void *)qh); 4199 4200 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4201 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 4202 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4203 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 4204 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4205 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 4206 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4207 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 4208 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4209 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 4210 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4211 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 4212 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4213 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 4214 4215 for (i = 0; i < 5; i++) { 4216 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4217 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 4218 } 4219 4220 for (i = 0; i < 5; i++) { 4221 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4222 "\tqh_buf_high[%d]: 0x%x ", 4223 i, Get_QH(qh->qh_buf_high[i])); 4224 } 4225 4226 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4227 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 4228 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4229 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 4230 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4231 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 4232 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4233 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 4234 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4235 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 4236 } 4237 4238 4239 /* 4240 * ehci_print_qtd: 4241 */ 4242 void 4243 ehci_print_qtd( 4244 ehci_state_t *ehcip, 4245 ehci_qtd_t *qtd) 4246 { 4247 uint_t i; 4248 4249 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4250 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 4251 4252 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4253 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 4254 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4255 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 4256 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4257 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 4258 4259 for (i = 0; i < 5; i++) { 4260 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4261 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 4262 } 4263 4264 for (i = 0; i < 5; i++) { 4265 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4266 "\tqtd_buf_high[%d]: 0x%x ", 4267 i, Get_QTD(qtd->qtd_buf_high[i])); 4268 } 4269 4270 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4271 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 4272 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4273 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 4274 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4275 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 4276 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4277 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 4278 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4279 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 4280 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4281 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 4282 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4283 "\tqtd_xfer_offs: 0x%x ", Get_QTD(qtd->qtd_xfer_offs)); 4284 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4285 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 4286 } 4287 4288 /* 4289 * ehci kstat functions 4290 */ 4291 4292 /* 4293 * ehci_create_stats: 4294 * 4295 * Allocate and initialize the ehci kstat structures 4296 */ 4297 void 4298 ehci_create_stats(ehci_state_t *ehcip) 4299 { 4300 char kstatname[KSTAT_STRLEN]; 4301 const char *dname = ddi_driver_name(ehcip->ehci_dip); 4302 char *usbtypes[USB_N_COUNT_KSTATS] = 4303 {"ctrl", "isoch", "bulk", "intr"}; 4304 uint_t instance = ehcip->ehci_instance; 4305 ehci_intrs_stats_t *isp; 4306 int i; 4307 4308 if (EHCI_INTRS_STATS(ehcip) == NULL) { 4309 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 4310 dname, instance); 4311 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 4312 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 4313 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 4314 KSTAT_FLAG_PERSISTENT); 4315 4316 if (EHCI_INTRS_STATS(ehcip)) { 4317 isp = EHCI_INTRS_STATS_DATA(ehcip); 4318 kstat_named_init(&isp->ehci_sts_total, 4319 "Interrupts Total", KSTAT_DATA_UINT64); 4320 kstat_named_init(&isp->ehci_sts_not_claimed, 4321 "Not Claimed", KSTAT_DATA_UINT64); 4322 kstat_named_init(&isp->ehci_sts_async_sched_status, 4323 "Async schedule status", KSTAT_DATA_UINT64); 4324 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 4325 "Periodic sched status", KSTAT_DATA_UINT64); 4326 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 4327 "Empty async schedule", KSTAT_DATA_UINT64); 4328 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 4329 "Host controller Halted", KSTAT_DATA_UINT64); 4330 kstat_named_init(&isp->ehci_sts_async_advance_intr, 4331 "Intr on async advance", KSTAT_DATA_UINT64); 4332 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 4333 "Host system error", KSTAT_DATA_UINT64); 4334 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 4335 "Frame list rollover", KSTAT_DATA_UINT64); 4336 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 4337 "Port change detect", KSTAT_DATA_UINT64); 4338 kstat_named_init(&isp->ehci_sts_usb_error_intr, 4339 "USB error interrupt", KSTAT_DATA_UINT64); 4340 kstat_named_init(&isp->ehci_sts_usb_intr, 4341 "USB interrupt", KSTAT_DATA_UINT64); 4342 4343 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 4344 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 4345 kstat_install(EHCI_INTRS_STATS(ehcip)); 4346 } 4347 } 4348 4349 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 4350 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 4351 dname, instance); 4352 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 4353 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 4354 KSTAT_FLAG_PERSISTENT); 4355 4356 if (EHCI_TOTAL_STATS(ehcip)) { 4357 kstat_install(EHCI_TOTAL_STATS(ehcip)); 4358 } 4359 } 4360 4361 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4362 if (ehcip->ehci_count_stats[i] == NULL) { 4363 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4364 dname, instance, usbtypes[i]); 4365 ehcip->ehci_count_stats[i] = kstat_create("usba", 4366 instance, kstatname, "usb_byte_count", 4367 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4368 4369 if (ehcip->ehci_count_stats[i]) { 4370 kstat_install(ehcip->ehci_count_stats[i]); 4371 } 4372 } 4373 } 4374 } 4375 4376 4377 /* 4378 * ehci_destroy_stats: 4379 * 4380 * Clean up ehci kstat structures 4381 */ 4382 void 4383 ehci_destroy_stats(ehci_state_t *ehcip) 4384 { 4385 int i; 4386 4387 if (EHCI_INTRS_STATS(ehcip)) { 4388 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4389 EHCI_INTRS_STATS(ehcip) = NULL; 4390 } 4391 4392 if (EHCI_TOTAL_STATS(ehcip)) { 4393 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4394 EHCI_TOTAL_STATS(ehcip) = NULL; 4395 } 4396 4397 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4398 if (ehcip->ehci_count_stats[i]) { 4399 kstat_delete(ehcip->ehci_count_stats[i]); 4400 ehcip->ehci_count_stats[i] = NULL; 4401 } 4402 } 4403 } 4404 4405 4406 /* 4407 * ehci_do_intrs_stats: 4408 * 4409 * ehci status information 4410 */ 4411 void 4412 ehci_do_intrs_stats( 4413 ehci_state_t *ehcip, 4414 int val) 4415 { 4416 if (EHCI_INTRS_STATS(ehcip)) { 4417 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4418 switch (val) { 4419 case EHCI_STS_ASYNC_SCHED_STATUS: 4420 EHCI_INTRS_STATS_DATA(ehcip)-> 4421 ehci_sts_async_sched_status.value.ui64++; 4422 break; 4423 case EHCI_STS_PERIODIC_SCHED_STATUS: 4424 EHCI_INTRS_STATS_DATA(ehcip)-> 4425 ehci_sts_periodic_sched_status.value.ui64++; 4426 break; 4427 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4428 EHCI_INTRS_STATS_DATA(ehcip)-> 4429 ehci_sts_empty_async_schedule.value.ui64++; 4430 break; 4431 case EHCI_STS_HOST_CTRL_HALTED: 4432 EHCI_INTRS_STATS_DATA(ehcip)-> 4433 ehci_sts_host_ctrl_halted.value.ui64++; 4434 break; 4435 case EHCI_STS_ASYNC_ADVANCE_INTR: 4436 EHCI_INTRS_STATS_DATA(ehcip)-> 4437 ehci_sts_async_advance_intr.value.ui64++; 4438 break; 4439 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4440 EHCI_INTRS_STATS_DATA(ehcip)-> 4441 ehci_sts_host_system_error_intr.value.ui64++; 4442 break; 4443 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4444 EHCI_INTRS_STATS_DATA(ehcip)-> 4445 ehci_sts_frm_list_rollover_intr.value.ui64++; 4446 break; 4447 case EHCI_STS_RH_PORT_CHANGE_INTR: 4448 EHCI_INTRS_STATS_DATA(ehcip)-> 4449 ehci_sts_rh_port_change_intr.value.ui64++; 4450 break; 4451 case EHCI_STS_USB_ERROR_INTR: 4452 EHCI_INTRS_STATS_DATA(ehcip)-> 4453 ehci_sts_usb_error_intr.value.ui64++; 4454 break; 4455 case EHCI_STS_USB_INTR: 4456 EHCI_INTRS_STATS_DATA(ehcip)-> 4457 ehci_sts_usb_intr.value.ui64++; 4458 break; 4459 default: 4460 EHCI_INTRS_STATS_DATA(ehcip)-> 4461 ehci_sts_not_claimed.value.ui64++; 4462 break; 4463 } 4464 } 4465 } 4466 4467 4468 /* 4469 * ehci_do_byte_stats: 4470 * 4471 * ehci data xfer information 4472 */ 4473 void 4474 ehci_do_byte_stats( 4475 ehci_state_t *ehcip, 4476 size_t len, 4477 uint8_t attr, 4478 uint8_t addr) 4479 { 4480 uint8_t type = attr & USB_EP_ATTR_MASK; 4481 uint8_t dir = addr & USB_EP_DIR_MASK; 4482 4483 if (dir == USB_EP_DIR_IN) { 4484 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4485 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4486 switch (type) { 4487 case USB_EP_ATTR_CONTROL: 4488 EHCI_CTRL_STATS(ehcip)->reads++; 4489 EHCI_CTRL_STATS(ehcip)->nread += len; 4490 break; 4491 case USB_EP_ATTR_BULK: 4492 EHCI_BULK_STATS(ehcip)->reads++; 4493 EHCI_BULK_STATS(ehcip)->nread += len; 4494 break; 4495 case USB_EP_ATTR_INTR: 4496 EHCI_INTR_STATS(ehcip)->reads++; 4497 EHCI_INTR_STATS(ehcip)->nread += len; 4498 break; 4499 case USB_EP_ATTR_ISOCH: 4500 EHCI_ISOC_STATS(ehcip)->reads++; 4501 EHCI_ISOC_STATS(ehcip)->nread += len; 4502 break; 4503 } 4504 } else if (dir == USB_EP_DIR_OUT) { 4505 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4506 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4507 switch (type) { 4508 case USB_EP_ATTR_CONTROL: 4509 EHCI_CTRL_STATS(ehcip)->writes++; 4510 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4511 break; 4512 case USB_EP_ATTR_BULK: 4513 EHCI_BULK_STATS(ehcip)->writes++; 4514 EHCI_BULK_STATS(ehcip)->nwritten += len; 4515 break; 4516 case USB_EP_ATTR_INTR: 4517 EHCI_INTR_STATS(ehcip)->writes++; 4518 EHCI_INTR_STATS(ehcip)->nwritten += len; 4519 break; 4520 case USB_EP_ATTR_ISOCH: 4521 EHCI_ISOC_STATS(ehcip)->writes++; 4522 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4523 break; 4524 } 4525 } 4526 } 4527