1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 27 /* 28 * EHCI Host Controller Driver (EHCI) 29 * 30 * The EHCI driver is a software driver which interfaces to the Universal 31 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 32 * the Host Controller is defined by the EHCI Host Controller Interface. 33 * 34 * This module contains the main EHCI driver code which handles all USB 35 * transfers, bandwidth allocations and other general functionalities. 36 */ 37 38 #include <sys/usb/hcd/ehci/ehcid.h> 39 #include <sys/usb/hcd/ehci/ehci_isoch.h> 40 #include <sys/usb/hcd/ehci/ehci_xfer.h> 41 42 /* 43 * EHCI MSI tunable: 44 * 45 * By default MSI is enabled on all supported platforms except for the 46 * EHCI controller of ULI1575 South bridge. 47 */ 48 boolean_t ehci_enable_msi = B_TRUE; 49 50 /* Pointer to the state structure */ 51 extern void *ehci_statep; 52 53 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 54 55 extern uint_t ehci_vt62x2_workaround; 56 extern int force_ehci_off; 57 58 /* Adjustable variables for the size of the pools */ 59 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 60 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 61 62 /* 63 * Initialize the values which the order of 32ms intr qh are executed 64 * by the host controller in the lattice tree. 65 */ 66 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 67 {0x00, 0x10, 0x08, 0x18, 68 0x04, 0x14, 0x0c, 0x1c, 69 0x02, 0x12, 0x0a, 0x1a, 70 0x06, 0x16, 0x0e, 0x1e, 71 0x01, 0x11, 0x09, 0x19, 72 0x05, 0x15, 0x0d, 0x1d, 73 0x03, 0x13, 0x0b, 0x1b, 74 0x07, 0x17, 0x0f, 0x1f}; 75 76 /* 77 * Initialize the values which are used to calculate start split mask 78 * for the low/full/high speed interrupt and isochronous endpoints. 79 */ 80 static uint_t ehci_start_split_mask[15] = { 81 /* 82 * For high/full/low speed usb devices. For high speed 83 * device with polling interval greater than or equal 84 * to 8us (125us). 85 */ 86 0x01, /* 00000001 */ 87 0x02, /* 00000010 */ 88 0x04, /* 00000100 */ 89 0x08, /* 00001000 */ 90 0x10, /* 00010000 */ 91 0x20, /* 00100000 */ 92 0x40, /* 01000000 */ 93 0x80, /* 10000000 */ 94 95 /* Only for high speed devices with polling interval 4us */ 96 0x11, /* 00010001 */ 97 0x22, /* 00100010 */ 98 0x44, /* 01000100 */ 99 0x88, /* 10001000 */ 100 101 /* Only for high speed devices with polling interval 2us */ 102 0x55, /* 01010101 */ 103 0xaa, /* 10101010 */ 104 105 /* Only for high speed devices with polling interval 1us */ 106 0xff /* 11111111 */ 107 }; 108 109 /* 110 * Initialize the values which are used to calculate complete split mask 111 * for the low/full speed interrupt and isochronous endpoints. 112 */ 113 static uint_t ehci_intr_complete_split_mask[7] = { 114 /* Only full/low speed devices */ 115 0x1c, /* 00011100 */ 116 0x38, /* 00111000 */ 117 0x70, /* 01110000 */ 118 0xe0, /* 11100000 */ 119 0x00, /* Need FSTN feature */ 120 0x00, /* Need FSTN feature */ 121 0x00 /* Need FSTN feature */ 122 }; 123 124 125 /* 126 * EHCI Internal Function Prototypes 127 */ 128 129 /* Host Controller Driver (HCD) initialization functions */ 130 void ehci_set_dma_attributes(ehci_state_t *ehcip); 131 int ehci_allocate_pools(ehci_state_t *ehcip); 132 void ehci_decode_ddi_dma_addr_bind_handle_result( 133 ehci_state_t *ehcip, 134 int result); 135 int ehci_map_regs(ehci_state_t *ehcip); 136 int ehci_register_intrs_and_init_mutex( 137 ehci_state_t *ehcip); 138 static int ehci_add_intrs(ehci_state_t *ehcip, 139 int intr_type); 140 int ehci_init_ctlr(ehci_state_t *ehcip, 141 int init_type); 142 static int ehci_take_control(ehci_state_t *ehcip); 143 static int ehci_init_periodic_frame_lst_table( 144 ehci_state_t *ehcip); 145 static void ehci_build_interrupt_lattice( 146 ehci_state_t *ehcip); 147 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 148 149 /* Host Controller Driver (HCD) deinitialization functions */ 150 int ehci_cleanup(ehci_state_t *ehcip); 151 static void ehci_rem_intrs(ehci_state_t *ehcip); 152 int ehci_cpr_suspend(ehci_state_t *ehcip); 153 int ehci_cpr_resume(ehci_state_t *ehcip); 154 155 /* Bandwidth Allocation functions */ 156 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 157 usba_pipe_handle_data_t *ph, 158 uint_t *pnode, 159 uchar_t *smask, 160 uchar_t *cmask); 161 static int ehci_allocate_high_speed_bandwidth( 162 ehci_state_t *ehcip, 163 usba_pipe_handle_data_t *ph, 164 uint_t *hnode, 165 uchar_t *smask, 166 uchar_t *cmask); 167 static int ehci_allocate_classic_tt_bandwidth( 168 ehci_state_t *ehcip, 169 usba_pipe_handle_data_t *ph, 170 uint_t pnode); 171 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 172 usba_pipe_handle_data_t *ph, 173 uint_t pnode, 174 uchar_t smask, 175 uchar_t cmask); 176 static void ehci_deallocate_high_speed_bandwidth( 177 ehci_state_t *ehcip, 178 usba_pipe_handle_data_t *ph, 179 uint_t hnode, 180 uchar_t smask, 181 uchar_t cmask); 182 static void ehci_deallocate_classic_tt_bandwidth( 183 ehci_state_t *ehcip, 184 usba_pipe_handle_data_t *ph, 185 uint_t pnode); 186 static int ehci_compute_high_speed_bandwidth( 187 ehci_state_t *ehcip, 188 usb_ep_descr_t *endpoint, 189 usb_port_status_t port_status, 190 uint_t *sbandwidth, 191 uint_t *cbandwidth); 192 static int ehci_compute_classic_bandwidth( 193 usb_ep_descr_t *endpoint, 194 usb_port_status_t port_status, 195 uint_t *bandwidth); 196 int ehci_adjust_polling_interval( 197 ehci_state_t *ehcip, 198 usb_ep_descr_t *endpoint, 199 usb_port_status_t port_status); 200 static int ehci_adjust_high_speed_polling_interval( 201 ehci_state_t *ehcip, 202 usb_ep_descr_t *endpoint); 203 static uint_t ehci_lattice_height(uint_t interval); 204 static uint_t ehci_lattice_parent(uint_t node); 205 static uint_t ehci_find_periodic_node( 206 uint_t leaf, 207 int interval); 208 static uint_t ehci_leftmost_leaf(uint_t node, 209 uint_t height); 210 static uint_t ehci_pow_2(uint_t x); 211 static uint_t ehci_log_2(uint_t x); 212 static int ehci_find_bestfit_hs_mask( 213 ehci_state_t *ehcip, 214 uchar_t *smask, 215 uint_t *pnode, 216 usb_ep_descr_t *endpoint, 217 uint_t bandwidth, 218 int interval); 219 static int ehci_find_bestfit_ls_intr_mask( 220 ehci_state_t *ehcip, 221 uchar_t *smask, 222 uchar_t *cmask, 223 uint_t *pnode, 224 uint_t sbandwidth, 225 uint_t cbandwidth, 226 int interval); 227 static int ehci_find_bestfit_sitd_in_mask( 228 ehci_state_t *ehcip, 229 uchar_t *smask, 230 uchar_t *cmask, 231 uint_t *pnode, 232 uint_t sbandwidth, 233 uint_t cbandwidth, 234 int interval); 235 static int ehci_find_bestfit_sitd_out_mask( 236 ehci_state_t *ehcip, 237 uchar_t *smask, 238 uint_t *pnode, 239 uint_t sbandwidth, 240 int interval); 241 static uint_t ehci_calculate_bw_availability_mask( 242 ehci_state_t *ehcip, 243 uint_t bandwidth, 244 int leaf, 245 int leaf_count, 246 uchar_t *bw_mask); 247 static void ehci_update_bw_availability( 248 ehci_state_t *ehcip, 249 int bandwidth, 250 int leftmost_leaf, 251 int leaf_count, 252 uchar_t mask); 253 254 /* Miscellaneous functions */ 255 ehci_state_t *ehci_obtain_state( 256 dev_info_t *dip); 257 int ehci_state_is_operational( 258 ehci_state_t *ehcip); 259 int ehci_do_soft_reset( 260 ehci_state_t *ehcip); 261 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 262 ehci_pipe_private_t *pp, 263 ehci_trans_wrapper_t *tw); 264 usb_frame_number_t ehci_get_current_frame_number( 265 ehci_state_t *ehcip); 266 static void ehci_cpr_cleanup( 267 ehci_state_t *ehcip); 268 int ehci_wait_for_sof( 269 ehci_state_t *ehcip); 270 void ehci_toggle_scheduler( 271 ehci_state_t *ehcip); 272 void ehci_print_caps(ehci_state_t *ehcip); 273 void ehci_print_regs(ehci_state_t *ehcip); 274 void ehci_print_qh(ehci_state_t *ehcip, 275 ehci_qh_t *qh); 276 void ehci_print_qtd(ehci_state_t *ehcip, 277 ehci_qtd_t *qtd); 278 void ehci_create_stats(ehci_state_t *ehcip); 279 void ehci_destroy_stats(ehci_state_t *ehcip); 280 void ehci_do_intrs_stats(ehci_state_t *ehcip, 281 int val); 282 void ehci_do_byte_stats(ehci_state_t *ehcip, 283 size_t len, 284 uint8_t attr, 285 uint8_t addr); 286 287 /* 288 * check if this ehci controller can support PM 289 */ 290 int 291 ehci_hcdi_pm_support(dev_info_t *dip) 292 { 293 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 294 ddi_get_instance(dip)); 295 296 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 297 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 298 299 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 300 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 301 302 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 303 304 return (USB_SUCCESS); 305 } 306 307 return (USB_FAILURE); 308 } 309 310 void 311 ehci_dma_attr_workaround(ehci_state_t *ehcip) 312 { 313 /* 314 * Some Nvidia chips can not handle qh dma address above 2G. 315 * The bit 31 of the dma address might be omitted and it will 316 * cause system crash or other unpredicable result. So force 317 * the dma address allocated below 2G to make ehci work. 318 */ 319 if (PCI_VENDOR_NVIDIA == ehcip->ehci_vendor_id) { 320 switch (ehcip->ehci_device_id) { 321 case PCI_DEVICE_NVIDIA_CK804: 322 case PCI_DEVICE_NVIDIA_MCP04: 323 USB_DPRINTF_L2(PRINT_MASK_ATTA, 324 ehcip->ehci_log_hdl, 325 "ehci_dma_attr_workaround: NVIDIA dma " 326 "workaround enabled, force dma address " 327 "to be allocated below 2G"); 328 ehcip->ehci_dma_attr.dma_attr_addr_hi = 329 0x7fffffffull; 330 break; 331 default: 332 break; 333 334 } 335 } 336 } 337 338 /* 339 * Host Controller Driver (HCD) initialization functions 340 */ 341 342 /* 343 * ehci_set_dma_attributes: 344 * 345 * Set the limits in the DMA attributes structure. Most of the values used 346 * in the DMA limit structures are the default values as specified by the 347 * Writing PCI device drivers document. 348 */ 349 void 350 ehci_set_dma_attributes(ehci_state_t *ehcip) 351 { 352 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 353 "ehci_set_dma_attributes:"); 354 355 /* Initialize the DMA attributes */ 356 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 357 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 358 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 359 360 /* 32 bit addressing */ 361 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 362 363 /* Byte alignment */ 364 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 365 366 /* 367 * Since PCI specification is byte alignment, the 368 * burst size field should be set to 1 for PCI devices. 369 */ 370 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 371 372 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 373 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 374 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 375 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 376 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 377 ehcip->ehci_dma_attr.dma_attr_flags = 0; 378 ehci_dma_attr_workaround(ehcip); 379 } 380 381 382 /* 383 * ehci_allocate_pools: 384 * 385 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 386 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 387 * to a 16 byte boundary. 388 */ 389 int 390 ehci_allocate_pools(ehci_state_t *ehcip) 391 { 392 ddi_device_acc_attr_t dev_attr; 393 size_t real_length; 394 int result; 395 uint_t ccount; 396 int i; 397 398 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 399 "ehci_allocate_pools:"); 400 401 /* The host controller will be little endian */ 402 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 403 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 404 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 405 406 /* Byte alignment */ 407 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 408 409 /* Allocate the QTD pool DMA handle */ 410 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 411 DDI_DMA_SLEEP, 0, 412 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 413 414 goto failure; 415 } 416 417 /* Allocate the memory for the QTD pool */ 418 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 419 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 420 &dev_attr, 421 DDI_DMA_CONSISTENT, 422 DDI_DMA_SLEEP, 423 0, 424 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 425 &real_length, 426 &ehcip->ehci_qtd_pool_mem_handle)) { 427 428 goto failure; 429 } 430 431 /* Map the QTD pool into the I/O address space */ 432 result = ddi_dma_addr_bind_handle( 433 ehcip->ehci_qtd_pool_dma_handle, 434 NULL, 435 (caddr_t)ehcip->ehci_qtd_pool_addr, 436 real_length, 437 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 438 DDI_DMA_SLEEP, 439 NULL, 440 &ehcip->ehci_qtd_pool_cookie, 441 &ccount); 442 443 bzero((void *)ehcip->ehci_qtd_pool_addr, 444 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 445 446 /* Process the result */ 447 if (result == DDI_DMA_MAPPED) { 448 /* The cookie count should be 1 */ 449 if (ccount != 1) { 450 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 451 "ehci_allocate_pools: More than 1 cookie"); 452 453 goto failure; 454 } 455 } else { 456 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 457 "ehci_allocate_pools: Result = %d", result); 458 459 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 460 461 goto failure; 462 } 463 464 /* 465 * DMA addresses for QTD pools are bound 466 */ 467 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 468 469 /* Initialize the QTD pool */ 470 for (i = 0; i < ehci_qtd_pool_size; i ++) { 471 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 472 qtd_state, EHCI_QTD_FREE); 473 } 474 475 /* Allocate the QTD pool DMA handle */ 476 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 477 &ehcip->ehci_dma_attr, 478 DDI_DMA_SLEEP, 479 0, 480 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 481 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 482 "ehci_allocate_pools: ddi_dma_alloc_handle failed"); 483 484 goto failure; 485 } 486 487 /* Allocate the memory for the QH pool */ 488 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 489 ehci_qh_pool_size * sizeof (ehci_qh_t), 490 &dev_attr, 491 DDI_DMA_CONSISTENT, 492 DDI_DMA_SLEEP, 493 0, 494 (caddr_t *)&ehcip->ehci_qh_pool_addr, 495 &real_length, 496 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 497 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 498 "ehci_allocate_pools: ddi_dma_mem_alloc failed"); 499 500 goto failure; 501 } 502 503 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 504 NULL, 505 (caddr_t)ehcip->ehci_qh_pool_addr, 506 real_length, 507 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 508 DDI_DMA_SLEEP, 509 NULL, 510 &ehcip->ehci_qh_pool_cookie, 511 &ccount); 512 513 bzero((void *)ehcip->ehci_qh_pool_addr, 514 ehci_qh_pool_size * sizeof (ehci_qh_t)); 515 516 /* Process the result */ 517 if (result == DDI_DMA_MAPPED) { 518 /* The cookie count should be 1 */ 519 if (ccount != 1) { 520 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 521 "ehci_allocate_pools: More than 1 cookie"); 522 523 goto failure; 524 } 525 } else { 526 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 527 528 goto failure; 529 } 530 531 /* 532 * DMA addresses for QH pools are bound 533 */ 534 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 535 536 /* Initialize the QH pool */ 537 for (i = 0; i < ehci_qh_pool_size; i ++) { 538 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 539 } 540 541 /* Byte alignment */ 542 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 543 544 return (DDI_SUCCESS); 545 546 failure: 547 /* Byte alignment */ 548 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 549 550 return (DDI_FAILURE); 551 } 552 553 554 /* 555 * ehci_decode_ddi_dma_addr_bind_handle_result: 556 * 557 * Process the return values of ddi_dma_addr_bind_handle() 558 */ 559 void 560 ehci_decode_ddi_dma_addr_bind_handle_result( 561 ehci_state_t *ehcip, 562 int result) 563 { 564 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 565 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 566 567 switch (result) { 568 case DDI_DMA_PARTIAL_MAP: 569 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 570 "Partial transfers not allowed"); 571 break; 572 case DDI_DMA_INUSE: 573 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 574 "Handle is in use"); 575 break; 576 case DDI_DMA_NORESOURCES: 577 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 578 "No resources"); 579 break; 580 case DDI_DMA_NOMAPPING: 581 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 582 "No mapping"); 583 break; 584 case DDI_DMA_TOOBIG: 585 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 586 "Object is too big"); 587 break; 588 default: 589 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 590 "Unknown dma error"); 591 } 592 } 593 594 595 /* 596 * ehci_map_regs: 597 * 598 * The Host Controller (HC) contains a set of on-chip operational registers 599 * and which should be mapped into a non-cacheable portion of the system 600 * addressable space. 601 */ 602 int 603 ehci_map_regs(ehci_state_t *ehcip) 604 { 605 ddi_device_acc_attr_t attr; 606 uint16_t cmd_reg; 607 uint_t length; 608 609 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 610 611 /* Check to make sure we have memory access */ 612 if (pci_config_setup(ehcip->ehci_dip, 613 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 614 615 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 616 "ehci_map_regs: Config error"); 617 618 return (DDI_FAILURE); 619 } 620 621 /* Make sure Memory Access Enable is set */ 622 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 623 624 if (!(cmd_reg & PCI_COMM_MAE)) { 625 626 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 627 "ehci_map_regs: Memory base address access disabled"); 628 629 return (DDI_FAILURE); 630 } 631 632 /* The host controller will be little endian */ 633 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 634 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 635 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 636 637 /* Map in EHCI Capability registers */ 638 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 639 (caddr_t *)&ehcip->ehci_capsp, 0, 640 sizeof (ehci_caps_t), &attr, 641 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 642 643 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 644 "ehci_map_regs: Map setup error"); 645 646 return (DDI_FAILURE); 647 } 648 649 length = ddi_get8(ehcip->ehci_caps_handle, 650 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 651 652 /* Free the original mapping */ 653 ddi_regs_map_free(&ehcip->ehci_caps_handle); 654 655 /* Re-map in EHCI Capability and Operational registers */ 656 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 657 (caddr_t *)&ehcip->ehci_capsp, 0, 658 length + sizeof (ehci_regs_t), &attr, 659 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 660 661 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 662 "ehci_map_regs: Map setup error"); 663 664 return (DDI_FAILURE); 665 } 666 667 /* Get the pointer to EHCI Operational Register */ 668 ehcip->ehci_regsp = (ehci_regs_t *) 669 ((uintptr_t)ehcip->ehci_capsp + length); 670 671 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 672 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 673 (void *)ehcip->ehci_capsp, (void *)ehcip->ehci_regsp); 674 675 return (DDI_SUCCESS); 676 } 677 678 /* 679 * The following simulated polling is for debugging purposes only. 680 * It is activated on x86 by setting usb-polling=true in GRUB or ehci.conf. 681 */ 682 static int 683 ehci_is_polled(dev_info_t *dip) 684 { 685 int ret; 686 char *propval; 687 688 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 689 "usb-polling", &propval) != DDI_SUCCESS) 690 691 return (0); 692 693 ret = (strcmp(propval, "true") == 0); 694 ddi_prop_free(propval); 695 696 return (ret); 697 } 698 699 static void 700 ehci_poll_intr(void *arg) 701 { 702 /* poll every msec */ 703 for (;;) { 704 (void) ehci_intr(arg, NULL); 705 delay(drv_usectohz(1000)); 706 } 707 } 708 709 /* 710 * ehci_register_intrs_and_init_mutex: 711 * 712 * Register interrupts and initialize each mutex and condition variables 713 */ 714 int 715 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 716 { 717 int intr_types; 718 719 #if defined(__x86) 720 uint8_t iline; 721 #endif 722 723 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 724 "ehci_register_intrs_and_init_mutex:"); 725 726 /* 727 * There is a known MSI hardware bug with the EHCI controller 728 * of ULI1575 southbridge. Hence MSI is disabled for this chip. 729 */ 730 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 731 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) { 732 ehcip->ehci_msi_enabled = B_FALSE; 733 } else { 734 /* Set the MSI enable flag from the global EHCI MSI tunable */ 735 ehcip->ehci_msi_enabled = ehci_enable_msi; 736 } 737 738 /* launch polling thread instead of enabling pci interrupt */ 739 if (ehci_is_polled(ehcip->ehci_dip)) { 740 extern pri_t maxclsyspri; 741 742 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 743 "ehci_register_intrs_and_init_mutex: " 744 "running in simulated polled mode"); 745 746 (void) thread_create(NULL, 0, ehci_poll_intr, ehcip, 0, &p0, 747 TS_RUN, maxclsyspri); 748 749 goto skip_intr; 750 } 751 752 #if defined(__x86) 753 /* 754 * Make sure that the interrupt pin is connected to the 755 * interrupt controller on x86. Interrupt line 255 means 756 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 757 * If we would return failure when interrupt line equals 255, then 758 * high speed devices will be routed to companion host controllers. 759 * However, it is not necessary to return failure here, and 760 * o/uhci codes don't check the interrupt line either. 761 * But it's good to log a message here for debug purposes. 762 */ 763 iline = pci_config_get8(ehcip->ehci_config_handle, 764 PCI_CONF_ILINE); 765 766 if (iline == 255) { 767 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 768 "ehci_register_intrs_and_init_mutex: " 769 "interrupt line value out of range (%d)", 770 iline); 771 } 772 #endif /* __x86 */ 773 774 /* Get supported interrupt types */ 775 if (ddi_intr_get_supported_types(ehcip->ehci_dip, 776 &intr_types) != DDI_SUCCESS) { 777 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 778 "ehci_register_intrs_and_init_mutex: " 779 "ddi_intr_get_supported_types failed"); 780 781 return (DDI_FAILURE); 782 } 783 784 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 785 "ehci_register_intrs_and_init_mutex: " 786 "supported interrupt types 0x%x", intr_types); 787 788 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) { 789 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI) 790 != DDI_SUCCESS) { 791 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 792 "ehci_register_intrs_and_init_mutex: MSI " 793 "registration failed, trying FIXED interrupt \n"); 794 } else { 795 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 796 "ehci_register_intrs_and_init_mutex: " 797 "Using MSI interrupt type\n"); 798 799 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI; 800 ehcip->ehci_flags |= EHCI_INTR; 801 } 802 } 803 804 if ((!(ehcip->ehci_flags & EHCI_INTR)) && 805 (intr_types & DDI_INTR_TYPE_FIXED)) { 806 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED) 807 != DDI_SUCCESS) { 808 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 809 "ehci_register_intrs_and_init_mutex: " 810 "FIXED interrupt registration failed\n"); 811 812 return (DDI_FAILURE); 813 } 814 815 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 816 "ehci_register_intrs_and_init_mutex: " 817 "Using FIXED interrupt type\n"); 818 819 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED; 820 ehcip->ehci_flags |= EHCI_INTR; 821 } 822 823 skip_intr: 824 /* Create prototype for advance on async schedule */ 825 cv_init(&ehcip->ehci_async_schedule_advance_cv, 826 NULL, CV_DRIVER, NULL); 827 828 return (DDI_SUCCESS); 829 } 830 831 832 /* 833 * ehci_add_intrs: 834 * 835 * Register FIXED or MSI interrupts. 836 */ 837 static int 838 ehci_add_intrs(ehci_state_t *ehcip, 839 int intr_type) 840 { 841 int actual, avail, intr_size, count = 0; 842 int i, flag, ret; 843 844 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 845 "ehci_add_intrs: interrupt type 0x%x", intr_type); 846 847 /* Get number of interrupts */ 848 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count); 849 if ((ret != DDI_SUCCESS) || (count == 0)) { 850 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 851 "ehci_add_intrs: ddi_intr_get_nintrs() failure, " 852 "ret: %d, count: %d", ret, count); 853 854 return (DDI_FAILURE); 855 } 856 857 /* Get number of available interrupts */ 858 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail); 859 if ((ret != DDI_SUCCESS) || (avail == 0)) { 860 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 861 "ehci_add_intrs: ddi_intr_get_navail() failure, " 862 "ret: %d, count: %d", ret, count); 863 864 return (DDI_FAILURE); 865 } 866 867 if (avail < count) { 868 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 869 "ehci_add_intrs: ehci_add_intrs: nintrs () " 870 "returned %d, navail returned %d\n", count, avail); 871 } 872 873 /* Allocate an array of interrupt handles */ 874 intr_size = count * sizeof (ddi_intr_handle_t); 875 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP); 876 877 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 878 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 879 880 /* call ddi_intr_alloc() */ 881 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 882 intr_type, 0, count, &actual, flag); 883 884 if ((ret != DDI_SUCCESS) || (actual == 0)) { 885 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 886 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret); 887 888 kmem_free(ehcip->ehci_htable, intr_size); 889 890 return (DDI_FAILURE); 891 } 892 893 if (actual < count) { 894 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 895 "ehci_add_intrs: Requested: %d, Received: %d\n", 896 count, actual); 897 898 for (i = 0; i < actual; i++) 899 (void) ddi_intr_free(ehcip->ehci_htable[i]); 900 901 kmem_free(ehcip->ehci_htable, intr_size); 902 903 return (DDI_FAILURE); 904 } 905 906 ehcip->ehci_intr_cnt = actual; 907 908 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0], 909 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) { 910 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 911 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret); 912 913 for (i = 0; i < actual; i++) 914 (void) ddi_intr_free(ehcip->ehci_htable[i]); 915 916 kmem_free(ehcip->ehci_htable, intr_size); 917 918 return (DDI_FAILURE); 919 } 920 921 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 922 "ehci_add_intrs: Supported Interrupt priority 0x%x", 923 ehcip->ehci_intr_pri); 924 925 /* Test for high level mutex */ 926 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 927 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 928 "ehci_add_intrs: Hi level interrupt not supported"); 929 930 for (i = 0; i < actual; i++) 931 (void) ddi_intr_free(ehcip->ehci_htable[i]); 932 933 kmem_free(ehcip->ehci_htable, intr_size); 934 935 return (DDI_FAILURE); 936 } 937 938 /* Initialize the mutex */ 939 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 940 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 941 942 /* Call ddi_intr_add_handler() */ 943 for (i = 0; i < actual; i++) { 944 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i], 945 ehci_intr, (caddr_t)ehcip, 946 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 947 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 948 "ehci_add_intrs:ddi_intr_add_handler() " 949 "failed %d", ret); 950 951 for (i = 0; i < actual; i++) 952 (void) ddi_intr_free(ehcip->ehci_htable[i]); 953 954 mutex_destroy(&ehcip->ehci_int_mutex); 955 kmem_free(ehcip->ehci_htable, intr_size); 956 957 return (DDI_FAILURE); 958 } 959 } 960 961 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0], 962 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) { 963 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 964 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret); 965 966 for (i = 0; i < actual; i++) { 967 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 968 (void) ddi_intr_free(ehcip->ehci_htable[i]); 969 } 970 971 mutex_destroy(&ehcip->ehci_int_mutex); 972 kmem_free(ehcip->ehci_htable, intr_size); 973 974 return (DDI_FAILURE); 975 } 976 977 /* Enable all interrupts */ 978 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 979 /* Call ddi_intr_block_enable() for MSI interrupts */ 980 (void) ddi_intr_block_enable(ehcip->ehci_htable, 981 ehcip->ehci_intr_cnt); 982 } else { 983 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 984 for (i = 0; i < ehcip->ehci_intr_cnt; i++) 985 (void) ddi_intr_enable(ehcip->ehci_htable[i]); 986 } 987 988 return (DDI_SUCCESS); 989 } 990 991 992 /* 993 * ehci_init_hardware 994 * 995 * take control from BIOS, reset EHCI host controller, and check version, etc. 996 */ 997 int 998 ehci_init_hardware(ehci_state_t *ehcip) 999 { 1000 int revision; 1001 uint16_t cmd_reg; 1002 int abort_on_BIOS_take_over_failure; 1003 1004 /* Take control from the BIOS */ 1005 if (ehci_take_control(ehcip) != USB_SUCCESS) { 1006 1007 /* read .conf file properties */ 1008 abort_on_BIOS_take_over_failure = 1009 ddi_prop_get_int(DDI_DEV_T_ANY, 1010 ehcip->ehci_dip, DDI_PROP_DONTPASS, 1011 "abort-on-BIOS-take-over-failure", 0); 1012 1013 if (abort_on_BIOS_take_over_failure) { 1014 1015 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1016 "Unable to take control from BIOS."); 1017 1018 return (DDI_FAILURE); 1019 } 1020 1021 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1022 "Unable to take control from BIOS. Failure is ignored."); 1023 } 1024 1025 /* set Memory Master Enable */ 1026 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 1027 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 1028 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 1029 1030 /* Reset the EHCI host controller */ 1031 Set_OpReg(ehci_command, 1032 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 1033 1034 /* Wait 10ms for reset to complete */ 1035 drv_usecwait(EHCI_RESET_TIMEWAIT); 1036 1037 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 1038 1039 /* Verify the version number */ 1040 revision = Get_16Cap(ehci_version); 1041 1042 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1043 "ehci_init_hardware: Revision 0x%x", revision); 1044 1045 /* 1046 * EHCI driver supports EHCI host controllers compliant to 1047 * 0.95 and higher revisions of EHCI specifications. 1048 */ 1049 if (revision < EHCI_REVISION_0_95) { 1050 1051 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1052 "Revision 0x%x is not supported", revision); 1053 1054 return (DDI_FAILURE); 1055 } 1056 1057 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 1058 1059 /* Initialize the Frame list base address area */ 1060 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 1061 1062 return (DDI_FAILURE); 1063 } 1064 1065 /* 1066 * For performance reasons, do not insert anything into the 1067 * asynchronous list or activate the asynch list schedule until 1068 * there is a valid QH. 1069 */ 1070 ehcip->ehci_head_of_async_sched_list = NULL; 1071 1072 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 1073 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 1074 /* 1075 * The driver is unable to reliably stop the asynch 1076 * list schedule on VIA VT6202 controllers, so we 1077 * always keep a dummy QH on the list. 1078 */ 1079 ehci_qh_t *dummy_async_qh = 1080 ehci_alloc_qh(ehcip, NULL, NULL); 1081 1082 Set_QH(dummy_async_qh->qh_link_ptr, 1083 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 1084 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 1085 1086 /* Set this QH to be the "head" of the circular list */ 1087 Set_QH(dummy_async_qh->qh_ctrl, 1088 Get_QH(dummy_async_qh->qh_ctrl) | 1089 EHCI_QH_CTRL_RECLAIM_HEAD); 1090 1091 Set_QH(dummy_async_qh->qh_next_qtd, 1092 EHCI_QH_NEXT_QTD_PTR_VALID); 1093 Set_QH(dummy_async_qh->qh_alt_next_qtd, 1094 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1095 1096 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 1097 ehcip->ehci_open_async_count++; 1098 } 1099 } 1100 1101 return (DDI_SUCCESS); 1102 } 1103 1104 1105 /* 1106 * ehci_init_workaround 1107 * 1108 * some workarounds during initializing ehci 1109 */ 1110 int 1111 ehci_init_workaround(ehci_state_t *ehcip) 1112 { 1113 /* 1114 * Acer Labs Inc. M5273 EHCI controller does not send 1115 * interrupts unless the Root hub ports are routed to the EHCI 1116 * host controller; so route the ports now, before we test for 1117 * the presence of SOFs interrupts. 1118 */ 1119 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1120 /* Route all Root hub ports to EHCI host controller */ 1121 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1122 } 1123 1124 /* 1125 * VIA chips have some issues and may not work reliably. 1126 * Revisions >= 0x80 are part of a southbridge and appear 1127 * to be reliable with the workaround. 1128 * For revisions < 0x80, if we were bound using class 1129 * complain, else proceed. This will allow the user to 1130 * bind ehci specifically to this chip and not have the 1131 * warnings 1132 */ 1133 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 1134 1135 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 1136 1137 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1138 "ehci_init_workaround: Applying VIA workarounds " 1139 "for the 6212 chip."); 1140 1141 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1142 "pciclass,0c0320") == 0) { 1143 1144 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1145 "Due to recently discovered incompatibilities"); 1146 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1147 "with this USB controller, USB2.x transfer"); 1148 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1149 "support has been disabled. This device will"); 1150 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1151 "continue to function as a USB1.x controller."); 1152 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1153 "If you are interested in enabling USB2.x"); 1154 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1155 "support please, refer to the ehci(7D) man page."); 1156 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1157 "Please also refer to www.sun.com/io for"); 1158 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1159 "Solaris Ready products and to"); 1160 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1161 "www.sun.com/bigadmin/hcl for additional"); 1162 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1163 "compatible USB products."); 1164 1165 return (DDI_FAILURE); 1166 1167 } else if (ehci_vt62x2_workaround) { 1168 1169 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1170 "Applying VIA workarounds"); 1171 } 1172 } 1173 1174 return (DDI_SUCCESS); 1175 } 1176 1177 1178 /* 1179 * ehci_init_check_status 1180 * 1181 * Check if EHCI host controller is running 1182 */ 1183 int 1184 ehci_init_check_status(ehci_state_t *ehcip) 1185 { 1186 clock_t sof_time_wait; 1187 1188 /* 1189 * Get the number of clock ticks to wait. 1190 * This is based on the maximum time it takes for a frame list rollover 1191 * and maximum time wait for SOFs to begin. 1192 */ 1193 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1194 EHCI_SOF_TIMEWAIT); 1195 1196 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1197 ehcip->ehci_flags |= EHCI_CV_INTR; 1198 1199 /* We need to add a delay to allow the chip time to start running */ 1200 (void) cv_timedwait(&ehcip->ehci_async_schedule_advance_cv, 1201 &ehcip->ehci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1202 1203 /* 1204 * Check EHCI host controller is running, otherwise return failure. 1205 */ 1206 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1207 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1208 1209 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1210 "No SOF interrupts have been received, this USB EHCI host" 1211 "controller is unusable"); 1212 1213 /* 1214 * Route all Root hub ports to Classic host 1215 * controller, in case this is an unusable ALI M5273 1216 * EHCI controller. 1217 */ 1218 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1219 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1220 } 1221 1222 return (DDI_FAILURE); 1223 } 1224 1225 return (DDI_SUCCESS); 1226 } 1227 1228 1229 /* 1230 * ehci_init_ctlr: 1231 * 1232 * Initialize the Host Controller (HC). 1233 */ 1234 int 1235 ehci_init_ctlr(ehci_state_t *ehcip, 1236 int init_type) 1237 { 1238 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 1239 1240 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1241 1242 if (ehci_init_hardware(ehcip) != DDI_SUCCESS) { 1243 1244 return (DDI_FAILURE); 1245 } 1246 } 1247 1248 /* 1249 * Check for Asynchronous schedule park capability feature. If this 1250 * feature is supported, then, program ehci command register with 1251 * appropriate values.. 1252 */ 1253 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 1254 1255 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1256 "ehci_init_ctlr: Async park mode is supported"); 1257 1258 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1259 (EHCI_CMD_ASYNC_PARK_ENABLE | 1260 EHCI_CMD_ASYNC_PARK_COUNT_3))); 1261 } 1262 1263 /* 1264 * Check for programmable periodic frame list feature. If this 1265 * feature is supported, then, program ehci command register with 1266 * 1024 frame list value. 1267 */ 1268 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 1269 1270 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1271 "ehci_init_ctlr: Variable programmable periodic " 1272 "frame list is supported"); 1273 1274 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1275 EHCI_CMD_FRAME_1024_SIZE)); 1276 } 1277 1278 /* 1279 * Currently EHCI driver doesn't support 64 bit addressing. 1280 * 1281 * If we are using 64 bit addressing capability, then, program 1282 * ehci_ctrl_segment register with 4 Gigabyte segment where all 1283 * of the interface data structures are allocated. 1284 */ 1285 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 1286 1287 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1288 "ehci_init_ctlr: EHCI driver doesn't support " 1289 "64 bit addressing"); 1290 } 1291 1292 /* 64 bit addressing is not support */ 1293 Set_OpReg(ehci_ctrl_segment, 0x00000000); 1294 1295 /* Turn on/off the schedulers */ 1296 ehci_toggle_scheduler(ehcip); 1297 1298 /* Set host controller soft state to operational */ 1299 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1300 1301 /* 1302 * Set the Periodic Frame List Base Address register with the 1303 * starting physical address of the Periodic Frame List. 1304 */ 1305 Set_OpReg(ehci_periodic_list_base, 1306 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 1307 EHCI_PERIODIC_LIST_BASE)); 1308 1309 /* 1310 * Set ehci_interrupt to enable all interrupts except Root 1311 * Hub Status change interrupt. 1312 */ 1313 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 1314 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 1315 EHCI_INTR_USB); 1316 1317 /* 1318 * Set the desired interrupt threshold and turn on EHCI host controller. 1319 */ 1320 Set_OpReg(ehci_command, 1321 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 1322 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 1323 1324 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 1325 1326 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1327 1328 if (ehci_init_workaround(ehcip) != DDI_SUCCESS) { 1329 1330 /* Set host controller soft state to error */ 1331 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 1332 1333 return (DDI_FAILURE); 1334 } 1335 1336 if (ehci_init_check_status(ehcip) != DDI_SUCCESS) { 1337 1338 /* Set host controller soft state to error */ 1339 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 1340 1341 return (DDI_FAILURE); 1342 } 1343 1344 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1345 "ehci_init_ctlr: SOF's have started"); 1346 } 1347 1348 /* Route all Root hub ports to EHCI host controller */ 1349 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1350 1351 return (DDI_SUCCESS); 1352 } 1353 1354 /* 1355 * ehci_take_control: 1356 * 1357 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1358 * x86 machines, because sparc doesn't have a BIOS. 1359 * On x86 machine, the take control process includes 1360 * o get the base address of the extended capability list 1361 * o find out the capability for handoff synchronization in the list. 1362 * o check if BIOS has owned the host controller. 1363 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1364 * o wait for a constant time and check if BIOS has relinquished control. 1365 */ 1366 /* ARGSUSED */ 1367 static int 1368 ehci_take_control(ehci_state_t *ehcip) 1369 { 1370 #if defined(__x86) 1371 uint32_t extended_cap; 1372 uint32_t extended_cap_offset; 1373 uint32_t extended_cap_id; 1374 uint_t retry; 1375 1376 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1377 "ehci_take_control:"); 1378 1379 /* 1380 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1381 * register. 1382 */ 1383 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1384 EHCI_HCC_EECP_SHIFT; 1385 1386 /* 1387 * According EHCI Spec 2.2.4, if the extended capability offset is 1388 * less than 40h then its not valid. This means we don't need to 1389 * worry about BIOS handoff. 1390 */ 1391 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1392 1393 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1394 "ehci_take_control: Hardware doesn't support legacy."); 1395 1396 goto success; 1397 } 1398 1399 /* 1400 * According EHCI Spec 2.1.7, A zero offset indicates the 1401 * end of the extended capability list. 1402 */ 1403 while (extended_cap_offset) { 1404 1405 /* Get the extended capability value. */ 1406 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1407 extended_cap_offset); 1408 1409 /* Get the capability ID */ 1410 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1411 EHCI_EX_CAP_ID_SHIFT; 1412 1413 /* Check if the card support legacy */ 1414 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1415 break; 1416 } 1417 1418 /* Get the offset of the next capability */ 1419 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1420 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1421 } 1422 1423 /* 1424 * Unable to find legacy support in hardware's extended capability list. 1425 * This means we don't need to worry about BIOS handoff. 1426 */ 1427 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1428 1429 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1430 "ehci_take_control: Hardware doesn't support legacy"); 1431 1432 goto success; 1433 } 1434 1435 /* Check if BIOS has owned it. */ 1436 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1437 1438 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1439 "ehci_take_control: BIOS does not own EHCI"); 1440 1441 goto success; 1442 } 1443 1444 /* 1445 * According EHCI Spec 5.1, The OS driver initiates an ownership 1446 * request by setting the OS Owned semaphore to a one. The OS 1447 * waits for the BIOS Owned bit to go to a zero before attempting 1448 * to use the EHCI controller. The time that OS must wait for BIOS 1449 * to respond to the request for ownership is beyond the scope of 1450 * this specification. 1451 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1452 * for BIOS to release the ownership. 1453 */ 1454 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1455 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1456 extended_cap); 1457 1458 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1459 1460 /* wait a special interval */ 1461 #ifndef __lock_lint 1462 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1463 #endif 1464 /* Check to see if the BIOS has released the ownership */ 1465 extended_cap = pci_config_get32( 1466 ehcip->ehci_config_handle, extended_cap_offset); 1467 1468 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1469 1470 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1471 ehcip->ehci_log_hdl, 1472 "ehci_take_control: BIOS has released " 1473 "the ownership. retry = %d", retry); 1474 1475 goto success; 1476 } 1477 1478 } 1479 1480 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1481 "ehci_take_control: take control from BIOS failed."); 1482 1483 return (USB_FAILURE); 1484 1485 success: 1486 1487 #endif /* __x86 */ 1488 return (USB_SUCCESS); 1489 } 1490 1491 1492 /* 1493 * ehci_init_periodic_frame_list_table : 1494 * 1495 * Allocate the system memory and initialize Host Controller 1496 * Periodic Frame List table area. The starting of the Periodic 1497 * Frame List Table area must be 4096 byte aligned. 1498 */ 1499 static int 1500 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1501 { 1502 ddi_device_acc_attr_t dev_attr; 1503 size_t real_length; 1504 uint_t ccount; 1505 int result; 1506 1507 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1508 1509 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1510 "ehci_init_periodic_frame_lst_table:"); 1511 1512 /* The host controller will be little endian */ 1513 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1514 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1515 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1516 1517 /* Force the required 4K restrictive alignment */ 1518 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1519 1520 /* Create space for the Periodic Frame List */ 1521 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1522 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1523 1524 goto failure; 1525 } 1526 1527 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1528 sizeof (ehci_periodic_frame_list_t), 1529 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1530 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1531 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1532 1533 goto failure; 1534 } 1535 1536 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1537 "ehci_init_periodic_frame_lst_table: " 1538 "Real length %lu", real_length); 1539 1540 /* Map the whole Periodic Frame List into the I/O address space */ 1541 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1542 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1543 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1544 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1545 1546 if (result == DDI_DMA_MAPPED) { 1547 /* The cookie count should be 1 */ 1548 if (ccount != 1) { 1549 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1550 "ehci_init_periodic_frame_lst_table: " 1551 "More than 1 cookie"); 1552 1553 goto failure; 1554 } 1555 } else { 1556 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1557 1558 goto failure; 1559 } 1560 1561 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1562 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1563 (void *)ehcip->ehci_periodic_frame_list_tablep, 1564 ehcip->ehci_pflt_cookie.dmac_address); 1565 1566 /* 1567 * DMA addresses for Periodic Frame List are bound. 1568 */ 1569 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1570 1571 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1572 1573 /* Initialize the Periodic Frame List */ 1574 ehci_build_interrupt_lattice(ehcip); 1575 1576 /* Reset Byte Alignment to Default */ 1577 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1578 1579 return (DDI_SUCCESS); 1580 failure: 1581 /* Byte alignment */ 1582 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1583 1584 return (DDI_FAILURE); 1585 } 1586 1587 1588 /* 1589 * ehci_build_interrupt_lattice: 1590 * 1591 * Construct the interrupt lattice tree using static Endpoint Descriptors 1592 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1593 * lists and the Host Controller (HC) processes one interrupt QH list in 1594 * every frame. The Host Controller traverses the periodic schedule by 1595 * constructing an array offset reference from the Periodic List Base Address 1596 * register and bits 12 to 3 of Frame Index register. It fetches the element 1597 * and begins traversing the graph of linked schedule data structures. 1598 */ 1599 static void 1600 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1601 { 1602 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1603 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1604 ehci_periodic_frame_list_t *periodic_frame_list = 1605 ehcip->ehci_periodic_frame_list_tablep; 1606 ushort_t *temp, num_of_nodes; 1607 uintptr_t addr; 1608 int i, j, k; 1609 1610 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1611 "ehci_build_interrupt_lattice:"); 1612 1613 /* 1614 * Reserve the first 63 Endpoint Descriptor (QH) structures 1615 * in the pool as static endpoints & these are required for 1616 * constructing interrupt lattice tree. 1617 */ 1618 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1619 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1620 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1621 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1622 Set_QH(list_array[i].qh_alt_next_qtd, 1623 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1624 } 1625 1626 /* 1627 * Make sure that last Endpoint on the periodic frame list terminates 1628 * periodic schedule. 1629 */ 1630 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1631 1632 /* Build the interrupt lattice tree */ 1633 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1634 /* 1635 * The next pointer in the host controller endpoint 1636 * descriptor must contain an iommu address. Calculate 1637 * the offset into the cpu address and add this to the 1638 * starting iommu address. 1639 */ 1640 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1641 1642 Set_QH(list_array[2*i + 1].qh_link_ptr, 1643 addr | EHCI_QH_LINK_REF_QH); 1644 Set_QH(list_array[2*i + 2].qh_link_ptr, 1645 addr | EHCI_QH_LINK_REF_QH); 1646 } 1647 1648 /* Build the tree bottom */ 1649 temp = (unsigned short *) 1650 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1651 1652 num_of_nodes = 1; 1653 1654 /* 1655 * Initialize the values which are used for setting up head pointers 1656 * for the 32ms scheduling lists which starts from the Periodic Frame 1657 * List. 1658 */ 1659 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1660 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1661 ehci_index[j++] = temp[k]; 1662 ehci_index[j] = temp[k] + ehci_pow_2(i); 1663 } 1664 1665 num_of_nodes *= 2; 1666 for (k = 0; k < num_of_nodes; k++) 1667 temp[k] = ehci_index[k]; 1668 } 1669 1670 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1671 1672 /* 1673 * Initialize the interrupt list in the Periodic Frame List Table 1674 * so that it points to the bottom of the tree. 1675 */ 1676 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1677 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1678 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1679 1680 ASSERT(addr); 1681 1682 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1683 Set_PFLT(periodic_frame_list-> 1684 ehci_periodic_frame_list_table[ehci_index[j++]], 1685 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1686 } 1687 } 1688 } 1689 1690 1691 /* 1692 * ehci_alloc_hcdi_ops: 1693 * 1694 * The HCDI interfaces or entry points are the software interfaces used by 1695 * the Universal Serial Bus Driver (USBA) to access the services of the 1696 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1697 * about all available HCDI interfaces or entry points. 1698 */ 1699 usba_hcdi_ops_t * 1700 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1701 { 1702 usba_hcdi_ops_t *usba_hcdi_ops; 1703 1704 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1705 "ehci_alloc_hcdi_ops:"); 1706 1707 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1708 1709 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1710 1711 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1712 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1713 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1714 1715 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1716 usba_hcdi_ops->usba_hcdi_pipe_reset_data_toggle = 1717 ehci_hcdi_pipe_reset_data_toggle; 1718 1719 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1720 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1721 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1722 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1723 1724 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1725 ehci_hcdi_bulk_transfer_size; 1726 1727 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1728 ehci_hcdi_pipe_stop_intr_polling; 1729 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1730 ehci_hcdi_pipe_stop_isoc_polling; 1731 1732 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1733 ehci_hcdi_get_current_frame_number; 1734 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1735 ehci_hcdi_get_max_isoc_pkts; 1736 1737 usba_hcdi_ops->usba_hcdi_console_input_init = 1738 ehci_hcdi_polled_input_init; 1739 usba_hcdi_ops->usba_hcdi_console_input_enter = 1740 ehci_hcdi_polled_input_enter; 1741 usba_hcdi_ops->usba_hcdi_console_read = 1742 ehci_hcdi_polled_read; 1743 usba_hcdi_ops->usba_hcdi_console_input_exit = 1744 ehci_hcdi_polled_input_exit; 1745 usba_hcdi_ops->usba_hcdi_console_input_fini = 1746 ehci_hcdi_polled_input_fini; 1747 return (usba_hcdi_ops); 1748 } 1749 1750 1751 /* 1752 * Host Controller Driver (HCD) deinitialization functions 1753 */ 1754 1755 /* 1756 * ehci_cleanup: 1757 * 1758 * Cleanup on attach failure or detach 1759 */ 1760 int 1761 ehci_cleanup(ehci_state_t *ehcip) 1762 { 1763 ehci_trans_wrapper_t *tw; 1764 ehci_pipe_private_t *pp; 1765 ehci_qtd_t *qtd; 1766 int i, ctrl, rval; 1767 int flags = ehcip->ehci_flags; 1768 1769 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1770 1771 if (flags & EHCI_RHREG) { 1772 /* Unload the root hub driver */ 1773 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1774 1775 return (DDI_FAILURE); 1776 } 1777 } 1778 1779 if (flags & EHCI_USBAREG) { 1780 /* Unregister this HCD instance with USBA */ 1781 usba_hcdi_unregister(ehcip->ehci_dip); 1782 } 1783 1784 if (flags & EHCI_INTR) { 1785 1786 mutex_enter(&ehcip->ehci_int_mutex); 1787 1788 /* Disable all EHCI QH list processing */ 1789 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1790 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1791 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1792 1793 /* Disable all EHCI interrupts */ 1794 Set_OpReg(ehci_interrupt, 0); 1795 1796 /* wait for the next SOF */ 1797 (void) ehci_wait_for_sof(ehcip); 1798 1799 /* Route all Root hub ports to Classic host controller */ 1800 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1801 1802 /* Stop the EHCI host controller */ 1803 Set_OpReg(ehci_command, 1804 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1805 1806 mutex_exit(&ehcip->ehci_int_mutex); 1807 1808 /* Wait for sometime */ 1809 delay(drv_usectohz(EHCI_TIMEWAIT)); 1810 1811 ehci_rem_intrs(ehcip); 1812 } 1813 1814 /* Unmap the EHCI registers */ 1815 if (ehcip->ehci_caps_handle) { 1816 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1817 } 1818 1819 if (ehcip->ehci_config_handle) { 1820 pci_config_teardown(&ehcip->ehci_config_handle); 1821 } 1822 1823 /* Free all the buffers */ 1824 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1825 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1826 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1827 ctrl = Get_QTD(ehcip-> 1828 ehci_qtd_pool_addr[i].qtd_state); 1829 1830 if ((ctrl != EHCI_QTD_FREE) && 1831 (ctrl != EHCI_QTD_DUMMY) && 1832 (qtd->qtd_trans_wrapper)) { 1833 1834 mutex_enter(&ehcip->ehci_int_mutex); 1835 1836 tw = (ehci_trans_wrapper_t *) 1837 EHCI_LOOKUP_ID((uint32_t) 1838 Get_QTD(qtd->qtd_trans_wrapper)); 1839 1840 /* Obtain the pipe private structure */ 1841 pp = tw->tw_pipe_private; 1842 1843 /* Stop the the transfer timer */ 1844 ehci_stop_xfer_timer(ehcip, tw, 1845 EHCI_REMOVE_XFER_ALWAYS); 1846 1847 ehci_deallocate_tw(ehcip, pp, tw); 1848 1849 mutex_exit(&ehcip->ehci_int_mutex); 1850 } 1851 } 1852 1853 /* 1854 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1855 * the handle for QTD pools. 1856 */ 1857 if ((ehcip->ehci_dma_addr_bind_flag & 1858 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1859 1860 rval = ddi_dma_unbind_handle( 1861 ehcip->ehci_qtd_pool_dma_handle); 1862 1863 ASSERT(rval == DDI_SUCCESS); 1864 } 1865 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1866 } 1867 1868 /* Free the QTD pool */ 1869 if (ehcip->ehci_qtd_pool_dma_handle) { 1870 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1871 } 1872 1873 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1874 /* 1875 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1876 * the handle for QH pools. 1877 */ 1878 if ((ehcip->ehci_dma_addr_bind_flag & 1879 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1880 1881 rval = ddi_dma_unbind_handle( 1882 ehcip->ehci_qh_pool_dma_handle); 1883 1884 ASSERT(rval == DDI_SUCCESS); 1885 } 1886 1887 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1888 } 1889 1890 /* Free the QH pool */ 1891 if (ehcip->ehci_qh_pool_dma_handle) { 1892 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1893 } 1894 1895 /* Free the Periodic frame list table (PFLT) area */ 1896 if (ehcip->ehci_periodic_frame_list_tablep && 1897 ehcip->ehci_pflt_mem_handle) { 1898 /* 1899 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1900 * the handle for PFLT. 1901 */ 1902 if ((ehcip->ehci_dma_addr_bind_flag & 1903 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1904 1905 rval = ddi_dma_unbind_handle( 1906 ehcip->ehci_pflt_dma_handle); 1907 1908 ASSERT(rval == DDI_SUCCESS); 1909 } 1910 1911 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1912 } 1913 1914 (void) ehci_isoc_cleanup(ehcip); 1915 1916 if (ehcip->ehci_pflt_dma_handle) { 1917 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1918 } 1919 1920 if (flags & EHCI_INTR) { 1921 /* Destroy the mutex */ 1922 mutex_destroy(&ehcip->ehci_int_mutex); 1923 1924 /* Destroy the async schedule advance condition variable */ 1925 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1926 } 1927 1928 /* clean up kstat structs */ 1929 ehci_destroy_stats(ehcip); 1930 1931 /* Free ehci hcdi ops */ 1932 if (ehcip->ehci_hcdi_ops) { 1933 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1934 } 1935 1936 if (flags & EHCI_ZALLOC) { 1937 1938 usb_free_log_hdl(ehcip->ehci_log_hdl); 1939 1940 /* Remove all properties that might have been created */ 1941 ddi_prop_remove_all(ehcip->ehci_dip); 1942 1943 /* Free the soft state */ 1944 ddi_soft_state_free(ehci_statep, 1945 ddi_get_instance(ehcip->ehci_dip)); 1946 } 1947 1948 return (DDI_SUCCESS); 1949 } 1950 1951 1952 /* 1953 * ehci_rem_intrs: 1954 * 1955 * Unregister FIXED or MSI interrupts 1956 */ 1957 static void 1958 ehci_rem_intrs(ehci_state_t *ehcip) 1959 { 1960 int i; 1961 1962 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1963 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type); 1964 1965 /* Disable all interrupts */ 1966 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1967 (void) ddi_intr_block_disable(ehcip->ehci_htable, 1968 ehcip->ehci_intr_cnt); 1969 } else { 1970 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1971 (void) ddi_intr_disable(ehcip->ehci_htable[i]); 1972 } 1973 } 1974 1975 /* Call ddi_intr_remove_handler() */ 1976 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1977 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 1978 (void) ddi_intr_free(ehcip->ehci_htable[i]); 1979 } 1980 1981 kmem_free(ehcip->ehci_htable, 1982 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t)); 1983 } 1984 1985 1986 /* 1987 * ehci_cpr_suspend 1988 */ 1989 int 1990 ehci_cpr_suspend(ehci_state_t *ehcip) 1991 { 1992 int i; 1993 1994 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1995 "ehci_cpr_suspend:"); 1996 1997 /* Call into the root hub and suspend it */ 1998 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 1999 2000 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2001 "ehci_cpr_suspend: root hub fails to suspend"); 2002 2003 return (DDI_FAILURE); 2004 } 2005 2006 /* Only root hub's intr pipe should be open at this time */ 2007 mutex_enter(&ehcip->ehci_int_mutex); 2008 2009 ASSERT(ehcip->ehci_open_pipe_count == 0); 2010 2011 /* Just wait till all resources are reclaimed */ 2012 i = 0; 2013 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 2014 ehci_handle_endpoint_reclaimation(ehcip); 2015 (void) ehci_wait_for_sof(ehcip); 2016 } 2017 ASSERT(ehcip->ehci_reclaim_list == NULL); 2018 2019 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2020 "ehci_cpr_suspend: Disable HC QH list processing"); 2021 2022 /* Disable all EHCI QH list processing */ 2023 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 2024 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 2025 2026 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2027 "ehci_cpr_suspend: Disable HC interrupts"); 2028 2029 /* Disable all EHCI interrupts */ 2030 Set_OpReg(ehci_interrupt, 0); 2031 2032 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2033 "ehci_cpr_suspend: Wait for the next SOF"); 2034 2035 /* Wait for the next SOF */ 2036 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 2037 2038 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2039 "ehci_cpr_suspend: ehci host controller suspend failed"); 2040 2041 mutex_exit(&ehcip->ehci_int_mutex); 2042 return (DDI_FAILURE); 2043 } 2044 2045 /* 2046 * Stop the ehci host controller 2047 * if usb keyboard is not connected. 2048 */ 2049 if (ehcip->ehci_polled_kbd_count == 0 || force_ehci_off != 0) { 2050 Set_OpReg(ehci_command, 2051 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 2052 } 2053 2054 /* Set host controller soft state to suspend */ 2055 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 2056 2057 mutex_exit(&ehcip->ehci_int_mutex); 2058 2059 return (DDI_SUCCESS); 2060 } 2061 2062 2063 /* 2064 * ehci_cpr_resume 2065 */ 2066 int 2067 ehci_cpr_resume(ehci_state_t *ehcip) 2068 { 2069 mutex_enter(&ehcip->ehci_int_mutex); 2070 2071 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2072 "ehci_cpr_resume: Restart the controller"); 2073 2074 /* Cleanup ehci specific information across cpr */ 2075 ehci_cpr_cleanup(ehcip); 2076 2077 /* Restart the controller */ 2078 if (ehci_init_ctlr(ehcip, EHCI_NORMAL_INITIALIZATION) != DDI_SUCCESS) { 2079 2080 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2081 "ehci_cpr_resume: ehci host controller resume failed "); 2082 2083 mutex_exit(&ehcip->ehci_int_mutex); 2084 2085 return (DDI_FAILURE); 2086 } 2087 2088 mutex_exit(&ehcip->ehci_int_mutex); 2089 2090 /* Now resume the root hub */ 2091 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 2092 2093 return (DDI_FAILURE); 2094 } 2095 2096 return (DDI_SUCCESS); 2097 } 2098 2099 2100 /* 2101 * Bandwidth Allocation functions 2102 */ 2103 2104 /* 2105 * ehci_allocate_bandwidth: 2106 * 2107 * Figure out whether or not this interval may be supported. Return the index 2108 * into the lattice if it can be supported. Return allocation failure if it 2109 * can not be supported. 2110 */ 2111 int 2112 ehci_allocate_bandwidth( 2113 ehci_state_t *ehcip, 2114 usba_pipe_handle_data_t *ph, 2115 uint_t *pnode, 2116 uchar_t *smask, 2117 uchar_t *cmask) 2118 { 2119 int error = USB_SUCCESS; 2120 2121 /* This routine is protected by the ehci_int_mutex */ 2122 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2123 2124 /* Reset the pnode to the last checked pnode */ 2125 *pnode = 0; 2126 2127 /* Allocate high speed bandwidth */ 2128 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 2129 ph, pnode, smask, cmask)) != USB_SUCCESS) { 2130 2131 return (error); 2132 } 2133 2134 /* 2135 * For low/full speed usb devices, allocate classic TT bandwidth 2136 * in additional to high speed bandwidth. 2137 */ 2138 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2139 2140 /* Allocate classic TT bandwidth */ 2141 if ((error = ehci_allocate_classic_tt_bandwidth( 2142 ehcip, ph, *pnode)) != USB_SUCCESS) { 2143 2144 /* Deallocate high speed bandwidth */ 2145 ehci_deallocate_high_speed_bandwidth( 2146 ehcip, ph, *pnode, *smask, *cmask); 2147 } 2148 } 2149 2150 return (error); 2151 } 2152 2153 2154 /* 2155 * ehci_allocate_high_speed_bandwidth: 2156 * 2157 * Allocate high speed bandwidth for the low/full/high speed interrupt and 2158 * isochronous endpoints. 2159 */ 2160 static int 2161 ehci_allocate_high_speed_bandwidth( 2162 ehci_state_t *ehcip, 2163 usba_pipe_handle_data_t *ph, 2164 uint_t *pnode, 2165 uchar_t *smask, 2166 uchar_t *cmask) 2167 { 2168 uint_t sbandwidth, cbandwidth; 2169 int interval; 2170 usb_ep_descr_t *endpoint = &ph->p_ep; 2171 usba_device_t *child_ud; 2172 usb_port_status_t port_status; 2173 int error; 2174 2175 /* This routine is protected by the ehci_int_mutex */ 2176 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2177 2178 /* Get child's usba device structure */ 2179 child_ud = ph->p_usba_device; 2180 2181 mutex_enter(&child_ud->usb_mutex); 2182 2183 /* Get the current usb device's port status */ 2184 port_status = ph->p_usba_device->usb_port_status; 2185 2186 mutex_exit(&child_ud->usb_mutex); 2187 2188 /* 2189 * Calculate the length in bytes of a transaction on this 2190 * periodic endpoint. Return failure if maximum packet is 2191 * zero. 2192 */ 2193 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2194 port_status, &sbandwidth, &cbandwidth); 2195 if (error != USB_SUCCESS) { 2196 2197 return (error); 2198 } 2199 2200 /* 2201 * Adjust polling interval to be a power of 2. 2202 * If this interval can't be supported, return 2203 * allocation failure. 2204 */ 2205 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2206 if (interval == USB_FAILURE) { 2207 2208 return (USB_FAILURE); 2209 } 2210 2211 if (port_status == USBA_HIGH_SPEED_DEV) { 2212 /* Allocate bandwidth for high speed devices */ 2213 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2214 USB_EP_ATTR_ISOCH) { 2215 error = USB_SUCCESS; 2216 } else { 2217 2218 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 2219 endpoint, sbandwidth, interval); 2220 } 2221 2222 *cmask = 0x00; 2223 2224 } else { 2225 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2226 USB_EP_ATTR_INTR) { 2227 2228 /* Allocate bandwidth for low speed interrupt */ 2229 error = ehci_find_bestfit_ls_intr_mask(ehcip, 2230 smask, cmask, pnode, sbandwidth, cbandwidth, 2231 interval); 2232 } else { 2233 if ((endpoint->bEndpointAddress & 2234 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2235 2236 /* Allocate bandwidth for sitd in */ 2237 error = ehci_find_bestfit_sitd_in_mask(ehcip, 2238 smask, cmask, pnode, sbandwidth, cbandwidth, 2239 interval); 2240 } else { 2241 2242 /* Allocate bandwidth for sitd out */ 2243 error = ehci_find_bestfit_sitd_out_mask(ehcip, 2244 smask, pnode, sbandwidth, interval); 2245 *cmask = 0x00; 2246 } 2247 } 2248 } 2249 2250 if (error != USB_SUCCESS) { 2251 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2252 "ehci_allocate_high_speed_bandwidth: Reached maximum " 2253 "bandwidth value and cannot allocate bandwidth for a " 2254 "given high-speed periodic endpoint"); 2255 2256 return (USB_NO_BANDWIDTH); 2257 } 2258 2259 return (error); 2260 } 2261 2262 2263 /* 2264 * ehci_allocate_classic_tt_speed_bandwidth: 2265 * 2266 * Allocate classic TT bandwidth for the low/full speed interrupt and 2267 * isochronous endpoints. 2268 */ 2269 static int 2270 ehci_allocate_classic_tt_bandwidth( 2271 ehci_state_t *ehcip, 2272 usba_pipe_handle_data_t *ph, 2273 uint_t pnode) 2274 { 2275 uint_t bandwidth, min; 2276 uint_t height, leftmost, list; 2277 usb_ep_descr_t *endpoint = &ph->p_ep; 2278 usba_device_t *child_ud, *parent_ud; 2279 usb_port_status_t port_status; 2280 int i, interval; 2281 2282 /* This routine is protected by the ehci_int_mutex */ 2283 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2284 2285 /* Get child's usba device structure */ 2286 child_ud = ph->p_usba_device; 2287 2288 mutex_enter(&child_ud->usb_mutex); 2289 2290 /* Get the current usb device's port status */ 2291 port_status = child_ud->usb_port_status; 2292 2293 /* Get the parent high speed hub's usba device structure */ 2294 parent_ud = child_ud->usb_hs_hub_usba_dev; 2295 2296 mutex_exit(&child_ud->usb_mutex); 2297 2298 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2299 "ehci_allocate_classic_tt_bandwidth: " 2300 "child_ud 0x%p parent_ud 0x%p", 2301 (void *)child_ud, (void *)parent_ud); 2302 2303 /* 2304 * Calculate the length in bytes of a transaction on this 2305 * periodic endpoint. Return failure if maximum packet is 2306 * zero. 2307 */ 2308 if (ehci_compute_classic_bandwidth(endpoint, 2309 port_status, &bandwidth) != USB_SUCCESS) { 2310 2311 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2312 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2313 "with zero endpoint maximum packet size is not supported"); 2314 2315 return (USB_NOT_SUPPORTED); 2316 } 2317 2318 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2319 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2320 2321 mutex_enter(&parent_ud->usb_mutex); 2322 2323 /* 2324 * If the length in bytes plus the allocated bandwidth exceeds 2325 * the maximum, return bandwidth allocation failure. 2326 */ 2327 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2328 FS_PERIODIC_BANDWIDTH) { 2329 2330 mutex_exit(&parent_ud->usb_mutex); 2331 2332 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2333 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2334 "bandwidth value and cannot allocate bandwidth for a " 2335 "given low/full speed periodic endpoint"); 2336 2337 return (USB_NO_BANDWIDTH); 2338 } 2339 2340 mutex_exit(&parent_ud->usb_mutex); 2341 2342 /* Adjust polling interval to be a power of 2 */ 2343 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2344 2345 /* Find the height in the tree */ 2346 height = ehci_lattice_height(interval); 2347 2348 /* Find the leftmost leaf in the subtree specified by the node. */ 2349 leftmost = ehci_leftmost_leaf(pnode, height); 2350 2351 mutex_enter(&parent_ud->usb_mutex); 2352 2353 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2354 list = ehci_index[leftmost + i]; 2355 2356 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2357 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2358 2359 mutex_exit(&parent_ud->usb_mutex); 2360 2361 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2362 "ehci_allocate_classic_tt_bandwidth: Reached " 2363 "maximum bandwidth value and cannot allocate " 2364 "bandwidth for low/full periodic endpoint"); 2365 2366 return (USB_NO_BANDWIDTH); 2367 } 2368 } 2369 2370 /* 2371 * All the leaves for this node must be updated with the bandwidth. 2372 */ 2373 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2374 list = ehci_index[leftmost + i]; 2375 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2376 } 2377 2378 /* Find the leaf with the smallest allocated bandwidth */ 2379 min = parent_ud->usb_hs_hub_bandwidth[0]; 2380 2381 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2382 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2383 min = parent_ud->usb_hs_hub_bandwidth[i]; 2384 } 2385 } 2386 2387 /* Save the minimum for later use */ 2388 parent_ud->usb_hs_hub_min_bandwidth = min; 2389 2390 mutex_exit(&parent_ud->usb_mutex); 2391 2392 return (USB_SUCCESS); 2393 } 2394 2395 2396 /* 2397 * ehci_deallocate_bandwidth: 2398 * 2399 * Deallocate bandwidth for the given node in the lattice and the length 2400 * of transfer. 2401 */ 2402 void 2403 ehci_deallocate_bandwidth( 2404 ehci_state_t *ehcip, 2405 usba_pipe_handle_data_t *ph, 2406 uint_t pnode, 2407 uchar_t smask, 2408 uchar_t cmask) 2409 { 2410 /* This routine is protected by the ehci_int_mutex */ 2411 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2412 2413 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2414 2415 /* 2416 * For low/full speed usb devices, deallocate classic TT bandwidth 2417 * in additional to high speed bandwidth. 2418 */ 2419 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2420 2421 /* Deallocate classic TT bandwidth */ 2422 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2423 } 2424 } 2425 2426 2427 /* 2428 * ehci_deallocate_high_speed_bandwidth: 2429 * 2430 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2431 */ 2432 static void 2433 ehci_deallocate_high_speed_bandwidth( 2434 ehci_state_t *ehcip, 2435 usba_pipe_handle_data_t *ph, 2436 uint_t pnode, 2437 uchar_t smask, 2438 uchar_t cmask) 2439 { 2440 uint_t height, leftmost; 2441 uint_t list_count; 2442 uint_t sbandwidth, cbandwidth; 2443 int interval; 2444 usb_ep_descr_t *endpoint = &ph->p_ep; 2445 usba_device_t *child_ud; 2446 usb_port_status_t port_status; 2447 2448 /* This routine is protected by the ehci_int_mutex */ 2449 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2450 2451 /* Get child's usba device structure */ 2452 child_ud = ph->p_usba_device; 2453 2454 mutex_enter(&child_ud->usb_mutex); 2455 2456 /* Get the current usb device's port status */ 2457 port_status = ph->p_usba_device->usb_port_status; 2458 2459 mutex_exit(&child_ud->usb_mutex); 2460 2461 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2462 port_status, &sbandwidth, &cbandwidth); 2463 2464 /* Adjust polling interval to be a power of 2 */ 2465 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2466 2467 /* Find the height in the tree */ 2468 height = ehci_lattice_height(interval); 2469 2470 /* 2471 * Find the leftmost leaf in the subtree specified by the node 2472 */ 2473 leftmost = ehci_leftmost_leaf(pnode, height); 2474 2475 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2476 2477 /* Delete the bandwidth from the appropriate lists */ 2478 if (port_status == USBA_HIGH_SPEED_DEV) { 2479 2480 ehci_update_bw_availability(ehcip, -sbandwidth, 2481 leftmost, list_count, smask); 2482 } else { 2483 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2484 USB_EP_ATTR_INTR) { 2485 2486 ehci_update_bw_availability(ehcip, -sbandwidth, 2487 leftmost, list_count, smask); 2488 ehci_update_bw_availability(ehcip, -cbandwidth, 2489 leftmost, list_count, cmask); 2490 } else { 2491 if ((endpoint->bEndpointAddress & 2492 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2493 2494 ehci_update_bw_availability(ehcip, -sbandwidth, 2495 leftmost, list_count, smask); 2496 ehci_update_bw_availability(ehcip, 2497 -MAX_UFRAME_SITD_XFER, leftmost, 2498 list_count, cmask); 2499 } else { 2500 2501 ehci_update_bw_availability(ehcip, 2502 -MAX_UFRAME_SITD_XFER, leftmost, 2503 list_count, smask); 2504 } 2505 } 2506 } 2507 } 2508 2509 /* 2510 * ehci_deallocate_classic_tt_bandwidth: 2511 * 2512 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2513 */ 2514 static void 2515 ehci_deallocate_classic_tt_bandwidth( 2516 ehci_state_t *ehcip, 2517 usba_pipe_handle_data_t *ph, 2518 uint_t pnode) 2519 { 2520 uint_t bandwidth, height, leftmost, list, min; 2521 int i, interval; 2522 usb_ep_descr_t *endpoint = &ph->p_ep; 2523 usba_device_t *child_ud, *parent_ud; 2524 usb_port_status_t port_status; 2525 2526 /* This routine is protected by the ehci_int_mutex */ 2527 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2528 2529 /* Get child's usba device structure */ 2530 child_ud = ph->p_usba_device; 2531 2532 mutex_enter(&child_ud->usb_mutex); 2533 2534 /* Get the current usb device's port status */ 2535 port_status = child_ud->usb_port_status; 2536 2537 /* Get the parent high speed hub's usba device structure */ 2538 parent_ud = child_ud->usb_hs_hub_usba_dev; 2539 2540 mutex_exit(&child_ud->usb_mutex); 2541 2542 /* Obtain the bandwidth */ 2543 (void) ehci_compute_classic_bandwidth(endpoint, 2544 port_status, &bandwidth); 2545 2546 /* Adjust polling interval to be a power of 2 */ 2547 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2548 2549 /* Find the height in the tree */ 2550 height = ehci_lattice_height(interval); 2551 2552 /* Find the leftmost leaf in the subtree specified by the node */ 2553 leftmost = ehci_leftmost_leaf(pnode, height); 2554 2555 mutex_enter(&parent_ud->usb_mutex); 2556 2557 /* Delete the bandwidth from the appropriate lists */ 2558 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2559 list = ehci_index[leftmost + i]; 2560 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2561 } 2562 2563 /* Find the leaf with the smallest allocated bandwidth */ 2564 min = parent_ud->usb_hs_hub_bandwidth[0]; 2565 2566 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2567 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2568 min = parent_ud->usb_hs_hub_bandwidth[i]; 2569 } 2570 } 2571 2572 /* Save the minimum for later use */ 2573 parent_ud->usb_hs_hub_min_bandwidth = min; 2574 2575 mutex_exit(&parent_ud->usb_mutex); 2576 } 2577 2578 2579 /* 2580 * ehci_compute_high_speed_bandwidth: 2581 * 2582 * Given a periodic endpoint (interrupt or isochronous) determine the total 2583 * bandwidth for one transaction. The EHCI host controller traverses the 2584 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2585 * services an endpoint, only a single transaction attempt is made. The HC 2586 * moves to the next Endpoint Descriptor after the first transaction attempt 2587 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2588 * Transfer Descriptor is inserted into the lattice, we will only count the 2589 * number of bytes for one transaction. 2590 * 2591 * The following are the formulas used for calculating bandwidth in terms 2592 * bytes and it is for the single USB high speed transaction. The protocol 2593 * overheads will be different for each of type of USB transfer & all these 2594 * formulas & protocol overheads are derived from the 5.11.3 section of the 2595 * USB 2.0 Specification. 2596 * 2597 * High-Speed: 2598 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2599 * 2600 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2601 * 2602 * Protocol overhead + Split transaction overhead + 2603 * ((MaxPktSz * 7)/6) + Host_Delay; 2604 */ 2605 /* ARGSUSED */ 2606 static int 2607 ehci_compute_high_speed_bandwidth( 2608 ehci_state_t *ehcip, 2609 usb_ep_descr_t *endpoint, 2610 usb_port_status_t port_status, 2611 uint_t *sbandwidth, 2612 uint_t *cbandwidth) 2613 { 2614 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2615 2616 /* Return failure if endpoint maximum packet is zero */ 2617 if (maxpacketsize == 0) { 2618 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2619 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2620 "with zero endpoint maximum packet size is not supported"); 2621 2622 return (USB_NOT_SUPPORTED); 2623 } 2624 2625 /* Add bit-stuffing overhead */ 2626 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2627 2628 /* Add Host Controller specific delay to required bandwidth */ 2629 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2630 2631 /* Add xfer specific protocol overheads */ 2632 if ((endpoint->bmAttributes & 2633 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2634 /* High speed interrupt transaction */ 2635 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2636 } else { 2637 /* Isochronous transaction */ 2638 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2639 } 2640 2641 /* 2642 * For low/full speed devices, add split transaction specific 2643 * overheads. 2644 */ 2645 if (port_status != USBA_HIGH_SPEED_DEV) { 2646 /* 2647 * Add start and complete split transaction 2648 * tokens overheads. 2649 */ 2650 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2651 *sbandwidth += START_SPLIT_OVERHEAD; 2652 2653 /* Add data overhead depending on data direction */ 2654 if ((endpoint->bEndpointAddress & 2655 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2656 *cbandwidth += maxpacketsize; 2657 } else { 2658 if ((endpoint->bmAttributes & 2659 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2660 /* There is no compete splits for out */ 2661 *cbandwidth = 0; 2662 } 2663 *sbandwidth += maxpacketsize; 2664 } 2665 } else { 2666 uint_t xactions; 2667 2668 /* Get the max transactions per microframe */ 2669 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2670 USB_EP_MAX_XACTS_SHIFT) + 1; 2671 2672 /* High speed transaction */ 2673 *sbandwidth += maxpacketsize; 2674 2675 /* Calculate bandwidth per micro-frame */ 2676 *sbandwidth *= xactions; 2677 2678 *cbandwidth = 0; 2679 } 2680 2681 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2682 "ehci_allocate_high_speed_bandwidth: " 2683 "Start split bandwidth %d Complete split bandwidth %d", 2684 *sbandwidth, *cbandwidth); 2685 2686 return (USB_SUCCESS); 2687 } 2688 2689 2690 /* 2691 * ehci_compute_classic_bandwidth: 2692 * 2693 * Given a periodic endpoint (interrupt or isochronous) determine the total 2694 * bandwidth for one transaction. The EHCI host controller traverses the 2695 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2696 * services an endpoint, only a single transaction attempt is made. The HC 2697 * moves to the next Endpoint Descriptor after the first transaction attempt 2698 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2699 * Transfer Descriptor is inserted into the lattice, we will only count the 2700 * number of bytes for one transaction. 2701 * 2702 * The following are the formulas used for calculating bandwidth in terms 2703 * bytes and it is for the single USB high speed transaction. The protocol 2704 * overheads will be different for each of type of USB transfer & all these 2705 * formulas & protocol overheads are derived from the 5.11.3 section of the 2706 * USB 2.0 Specification. 2707 * 2708 * Low-Speed: 2709 * Protocol overhead + Hub LS overhead + 2710 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2711 * 2712 * Full-Speed: 2713 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2714 */ 2715 /* ARGSUSED */ 2716 static int 2717 ehci_compute_classic_bandwidth( 2718 usb_ep_descr_t *endpoint, 2719 usb_port_status_t port_status, 2720 uint_t *bandwidth) 2721 { 2722 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2723 2724 /* 2725 * If endpoint maximum packet is zero, then return immediately. 2726 */ 2727 if (maxpacketsize == 0) { 2728 2729 return (USB_NOT_SUPPORTED); 2730 } 2731 2732 /* Add TT delay to required bandwidth */ 2733 *bandwidth = TT_DELAY; 2734 2735 /* Add bit-stuffing overhead */ 2736 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2737 2738 switch (port_status) { 2739 case USBA_LOW_SPEED_DEV: 2740 /* Low speed interrupt transaction */ 2741 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2742 HUB_LOW_SPEED_PROTO_OVERHEAD + 2743 (LOW_SPEED_CLOCK * maxpacketsize)); 2744 break; 2745 case USBA_FULL_SPEED_DEV: 2746 /* Full speed transaction */ 2747 *bandwidth += maxpacketsize; 2748 2749 /* Add xfer specific protocol overheads */ 2750 if ((endpoint->bmAttributes & 2751 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2752 /* Full speed interrupt transaction */ 2753 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2754 } else { 2755 /* Isochronous and input transaction */ 2756 if ((endpoint->bEndpointAddress & 2757 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2758 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2759 } else { 2760 /* Isochronous and output transaction */ 2761 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2762 } 2763 } 2764 break; 2765 } 2766 2767 return (USB_SUCCESS); 2768 } 2769 2770 2771 /* 2772 * ehci_adjust_polling_interval: 2773 * 2774 * Adjust bandwidth according usb device speed. 2775 */ 2776 /* ARGSUSED */ 2777 int 2778 ehci_adjust_polling_interval( 2779 ehci_state_t *ehcip, 2780 usb_ep_descr_t *endpoint, 2781 usb_port_status_t port_status) 2782 { 2783 uint_t interval; 2784 int i = 0; 2785 2786 /* Get the polling interval */ 2787 interval = endpoint->bInterval; 2788 2789 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2790 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2791 2792 /* 2793 * According USB 2.0 Specifications, a high-speed endpoint's 2794 * polling intervals are specified interms of 125us or micro 2795 * frame, where as full/low endpoint's polling intervals are 2796 * specified in milliseconds. 2797 * 2798 * A high speed interrupt/isochronous endpoints can specify 2799 * desired polling interval between 1 to 16 micro-frames, 2800 * where as full/low endpoints can specify between 1 to 255 2801 * milliseconds. 2802 */ 2803 switch (port_status) { 2804 case USBA_LOW_SPEED_DEV: 2805 /* 2806 * Low speed endpoints are limited to specifying 2807 * only 8ms to 255ms in this driver. If a device 2808 * reports a polling interval that is less than 8ms, 2809 * it will use 8 ms instead. 2810 */ 2811 if (interval < LS_MIN_POLL_INTERVAL) { 2812 2813 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2814 "Low speed endpoint's poll interval of %d ms " 2815 "is below threshold. Rounding up to %d ms", 2816 interval, LS_MIN_POLL_INTERVAL); 2817 2818 interval = LS_MIN_POLL_INTERVAL; 2819 } 2820 2821 /* 2822 * Return an error if the polling interval is greater 2823 * than 255ms. 2824 */ 2825 if (interval > LS_MAX_POLL_INTERVAL) { 2826 2827 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2828 "Low speed endpoint's poll interval is " 2829 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2830 2831 return (USB_FAILURE); 2832 } 2833 break; 2834 2835 case USBA_FULL_SPEED_DEV: 2836 /* 2837 * Return an error if the polling interval is less 2838 * than 1ms and greater than 255ms. 2839 */ 2840 if ((interval < FS_MIN_POLL_INTERVAL) && 2841 (interval > FS_MAX_POLL_INTERVAL)) { 2842 2843 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2844 "Full speed endpoint's poll interval must " 2845 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2846 FS_MAX_POLL_INTERVAL); 2847 2848 return (USB_FAILURE); 2849 } 2850 break; 2851 case USBA_HIGH_SPEED_DEV: 2852 /* 2853 * Return an error if the polling interval is less 1 2854 * and greater than 16. Convert this value to 125us 2855 * units using 2^(bInterval -1). refer usb 2.0 spec 2856 * page 51 for details. 2857 */ 2858 if ((interval < HS_MIN_POLL_INTERVAL) && 2859 (interval > HS_MAX_POLL_INTERVAL)) { 2860 2861 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2862 "High speed endpoint's poll interval " 2863 "must be between %d and %d units", 2864 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2865 2866 return (USB_FAILURE); 2867 } 2868 2869 /* Adjust high speed device polling interval */ 2870 interval = 2871 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2872 2873 break; 2874 } 2875 2876 /* 2877 * If polling interval is greater than 32ms, 2878 * adjust polling interval equal to 32ms. 2879 */ 2880 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2881 interval = EHCI_NUM_INTR_QH_LISTS; 2882 } 2883 2884 /* 2885 * Find the nearest power of 2 that's less 2886 * than interval. 2887 */ 2888 while ((ehci_pow_2(i)) <= interval) { 2889 i++; 2890 } 2891 2892 return (ehci_pow_2((i - 1))); 2893 } 2894 2895 2896 /* 2897 * ehci_adjust_high_speed_polling_interval: 2898 */ 2899 /* ARGSUSED */ 2900 static int 2901 ehci_adjust_high_speed_polling_interval( 2902 ehci_state_t *ehcip, 2903 usb_ep_descr_t *endpoint) 2904 { 2905 uint_t interval; 2906 2907 /* Get the polling interval */ 2908 interval = ehci_pow_2(endpoint->bInterval - 1); 2909 2910 /* 2911 * Convert polling interval from micro seconds 2912 * to milli seconds. 2913 */ 2914 if (interval <= EHCI_MAX_UFRAMES) { 2915 interval = 1; 2916 } else { 2917 interval = interval/EHCI_MAX_UFRAMES; 2918 } 2919 2920 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2921 "ehci_adjust_high_speed_polling_interval: " 2922 "High speed adjusted interval 0x%x", interval); 2923 2924 return (interval); 2925 } 2926 2927 2928 /* 2929 * ehci_lattice_height: 2930 * 2931 * Given the requested bandwidth, find the height in the tree at which the 2932 * nodes for this bandwidth fall. The height is measured as the number of 2933 * nodes from the leaf to the level specified by bandwidth The root of the 2934 * tree is at height TREE_HEIGHT. 2935 */ 2936 static uint_t 2937 ehci_lattice_height(uint_t interval) 2938 { 2939 return (TREE_HEIGHT - (ehci_log_2(interval))); 2940 } 2941 2942 2943 /* 2944 * ehci_lattice_parent: 2945 * 2946 * Given a node in the lattice, find the index of the parent node 2947 */ 2948 static uint_t 2949 ehci_lattice_parent(uint_t node) 2950 { 2951 if ((node % 2) == 0) { 2952 2953 return ((node/2) - 1); 2954 } else { 2955 2956 return ((node + 1)/2 - 1); 2957 } 2958 } 2959 2960 2961 /* 2962 * ehci_find_periodic_node: 2963 * 2964 * Based on the "real" array leaf node and interval, get the periodic node. 2965 */ 2966 static uint_t 2967 ehci_find_periodic_node(uint_t leaf, int interval) { 2968 uint_t lattice_leaf; 2969 uint_t height = ehci_lattice_height(interval); 2970 uint_t pnode; 2971 int i; 2972 2973 /* Get the leaf number in the lattice */ 2974 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2975 2976 /* Get the node in the lattice based on the height and leaf */ 2977 pnode = lattice_leaf; 2978 for (i = 0; i < height; i++) { 2979 pnode = ehci_lattice_parent(pnode); 2980 } 2981 2982 return (pnode); 2983 } 2984 2985 2986 /* 2987 * ehci_leftmost_leaf: 2988 * 2989 * Find the leftmost leaf in the subtree specified by the node. Height refers 2990 * to number of nodes from the bottom of the tree to the node, including the 2991 * node. 2992 * 2993 * The formula for a zero based tree is: 2994 * 2^H * Node + 2^H - 1 2995 * The leaf of the tree is an array, convert the number for the array. 2996 * Subtract the size of nodes not in the array 2997 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 2998 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 2999 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 3000 * 0 3001 * 1 2 3002 * 0 1 2 3 3003 */ 3004 static uint_t 3005 ehci_leftmost_leaf( 3006 uint_t node, 3007 uint_t height) 3008 { 3009 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 3010 } 3011 3012 3013 /* 3014 * ehci_pow_2: 3015 * 3016 * Compute 2 to the power 3017 */ 3018 static uint_t 3019 ehci_pow_2(uint_t x) 3020 { 3021 if (x == 0) { 3022 3023 return (1); 3024 } else { 3025 3026 return (2 << (x - 1)); 3027 } 3028 } 3029 3030 3031 /* 3032 * ehci_log_2: 3033 * 3034 * Compute log base 2 of x 3035 */ 3036 static uint_t 3037 ehci_log_2(uint_t x) 3038 { 3039 int i = 0; 3040 3041 while (x != 1) { 3042 x = x >> 1; 3043 i++; 3044 } 3045 3046 return (i); 3047 } 3048 3049 3050 /* 3051 * ehci_find_bestfit_hs_mask: 3052 * 3053 * Find the smask and cmask in the bandwidth allocation, and update the 3054 * bandwidth allocation. 3055 */ 3056 static int 3057 ehci_find_bestfit_hs_mask( 3058 ehci_state_t *ehcip, 3059 uchar_t *smask, 3060 uint_t *pnode, 3061 usb_ep_descr_t *endpoint, 3062 uint_t bandwidth, 3063 int interval) 3064 { 3065 int i; 3066 uint_t elements, index; 3067 int array_leaf, best_array_leaf; 3068 uint_t node_bandwidth, best_node_bandwidth; 3069 uint_t leaf_count; 3070 uchar_t bw_mask; 3071 uchar_t best_smask; 3072 3073 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3074 "ehci_find_bestfit_hs_mask: "); 3075 3076 /* Get all the valid smasks */ 3077 switch (ehci_pow_2(endpoint->bInterval - 1)) { 3078 case EHCI_INTR_1US_POLL: 3079 index = EHCI_1US_MASK_INDEX; 3080 elements = EHCI_INTR_1US_POLL; 3081 break; 3082 case EHCI_INTR_2US_POLL: 3083 index = EHCI_2US_MASK_INDEX; 3084 elements = EHCI_INTR_2US_POLL; 3085 break; 3086 case EHCI_INTR_4US_POLL: 3087 index = EHCI_4US_MASK_INDEX; 3088 elements = EHCI_INTR_4US_POLL; 3089 break; 3090 case EHCI_INTR_XUS_POLL: 3091 default: 3092 index = EHCI_XUS_MASK_INDEX; 3093 elements = EHCI_INTR_XUS_POLL; 3094 break; 3095 } 3096 3097 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3098 3099 /* 3100 * Because of the way the leaves are setup, we will automatically 3101 * hit the leftmost leaf of every possible node with this interval. 3102 */ 3103 best_smask = 0x00; 3104 best_node_bandwidth = 0; 3105 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3106 /* Find the bandwidth mask */ 3107 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 3108 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 3109 3110 /* 3111 * If this node cannot support our requirements skip to the 3112 * next leaf. 3113 */ 3114 if (bw_mask == 0x00) { 3115 continue; 3116 } 3117 3118 /* 3119 * Now make sure our bandwidth requirements can be 3120 * satisfied with one of smasks in this node. 3121 */ 3122 *smask = 0x00; 3123 for (i = index; i < (index + elements); i++) { 3124 /* Check the start split mask value */ 3125 if (ehci_start_split_mask[index] & bw_mask) { 3126 *smask = ehci_start_split_mask[index]; 3127 break; 3128 } 3129 } 3130 3131 /* 3132 * If an appropriate smask is found save the information if: 3133 * o best_smask has not been found yet. 3134 * - or - 3135 * o This is the node with the least amount of bandwidth 3136 */ 3137 if ((*smask != 0x00) && 3138 ((best_smask == 0x00) || 3139 (best_node_bandwidth > node_bandwidth))) { 3140 3141 best_node_bandwidth = node_bandwidth; 3142 best_array_leaf = array_leaf; 3143 best_smask = *smask; 3144 } 3145 } 3146 3147 /* 3148 * If we find node that can handle the bandwidth populate the 3149 * appropriate variables and return success. 3150 */ 3151 if (best_smask) { 3152 *smask = best_smask; 3153 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3154 interval); 3155 ehci_update_bw_availability(ehcip, bandwidth, 3156 ehci_index[best_array_leaf], leaf_count, best_smask); 3157 3158 return (USB_SUCCESS); 3159 } 3160 3161 return (USB_FAILURE); 3162 } 3163 3164 3165 /* 3166 * ehci_find_bestfit_ls_intr_mask: 3167 * 3168 * Find the smask and cmask in the bandwidth allocation. 3169 */ 3170 static int 3171 ehci_find_bestfit_ls_intr_mask( 3172 ehci_state_t *ehcip, 3173 uchar_t *smask, 3174 uchar_t *cmask, 3175 uint_t *pnode, 3176 uint_t sbandwidth, 3177 uint_t cbandwidth, 3178 int interval) 3179 { 3180 int i; 3181 uint_t elements, index; 3182 int array_leaf, best_array_leaf; 3183 uint_t node_sbandwidth, node_cbandwidth; 3184 uint_t best_node_bandwidth; 3185 uint_t leaf_count; 3186 uchar_t bw_smask, bw_cmask; 3187 uchar_t best_smask, best_cmask; 3188 3189 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3190 "ehci_find_bestfit_ls_intr_mask: "); 3191 3192 /* For low and full speed devices */ 3193 index = EHCI_XUS_MASK_INDEX; 3194 elements = EHCI_INTR_4MS_POLL; 3195 3196 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3197 3198 /* 3199 * Because of the way the leaves are setup, we will automatically 3200 * hit the leftmost leaf of every possible node with this interval. 3201 */ 3202 best_smask = 0x00; 3203 best_node_bandwidth = 0; 3204 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3205 /* Find the bandwidth mask */ 3206 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3207 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3208 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3209 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 3210 3211 /* 3212 * If this node cannot support our requirements skip to the 3213 * next leaf. 3214 */ 3215 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3216 continue; 3217 } 3218 3219 /* 3220 * Now make sure our bandwidth requirements can be 3221 * satisfied with one of smasks in this node. 3222 */ 3223 *smask = 0x00; 3224 *cmask = 0x00; 3225 for (i = index; i < (index + elements); i++) { 3226 /* Check the start split mask value */ 3227 if ((ehci_start_split_mask[index] & bw_smask) && 3228 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 3229 *smask = ehci_start_split_mask[index]; 3230 *cmask = ehci_intr_complete_split_mask[index]; 3231 break; 3232 } 3233 } 3234 3235 /* 3236 * If an appropriate smask is found save the information if: 3237 * o best_smask has not been found yet. 3238 * - or - 3239 * o This is the node with the least amount of bandwidth 3240 */ 3241 if ((*smask != 0x00) && 3242 ((best_smask == 0x00) || 3243 (best_node_bandwidth > 3244 (node_sbandwidth + node_cbandwidth)))) { 3245 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3246 best_array_leaf = array_leaf; 3247 best_smask = *smask; 3248 best_cmask = *cmask; 3249 } 3250 } 3251 3252 /* 3253 * If we find node that can handle the bandwidth populate the 3254 * appropriate variables and return success. 3255 */ 3256 if (best_smask) { 3257 *smask = best_smask; 3258 *cmask = best_cmask; 3259 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3260 interval); 3261 ehci_update_bw_availability(ehcip, sbandwidth, 3262 ehci_index[best_array_leaf], leaf_count, best_smask); 3263 ehci_update_bw_availability(ehcip, cbandwidth, 3264 ehci_index[best_array_leaf], leaf_count, best_cmask); 3265 3266 return (USB_SUCCESS); 3267 } 3268 3269 return (USB_FAILURE); 3270 } 3271 3272 3273 /* 3274 * ehci_find_bestfit_sitd_in_mask: 3275 * 3276 * Find the smask and cmask in the bandwidth allocation. 3277 */ 3278 static int 3279 ehci_find_bestfit_sitd_in_mask( 3280 ehci_state_t *ehcip, 3281 uchar_t *smask, 3282 uchar_t *cmask, 3283 uint_t *pnode, 3284 uint_t sbandwidth, 3285 uint_t cbandwidth, 3286 int interval) 3287 { 3288 int i, uFrames, found; 3289 int array_leaf, best_array_leaf; 3290 uint_t node_sbandwidth, node_cbandwidth; 3291 uint_t best_node_bandwidth; 3292 uint_t leaf_count; 3293 uchar_t bw_smask, bw_cmask; 3294 uchar_t best_smask, best_cmask; 3295 3296 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3297 "ehci_find_bestfit_sitd_in_mask: "); 3298 3299 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3300 3301 /* 3302 * Because of the way the leaves are setup, we will automatically 3303 * hit the leftmost leaf of every possible node with this interval. 3304 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3305 */ 3306 /* 3307 * Need to add an additional 2 uFrames, if the "L"ast 3308 * complete split is before uFrame 6. See section 3309 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3310 * the "Back Ptr" which means we support on IN of 3311 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3312 */ 3313 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3314 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3315 uFrames++; 3316 } 3317 if (uFrames > 6) { 3318 3319 return (USB_FAILURE); 3320 } 3321 *smask = 0x1; 3322 *cmask = 0x00; 3323 for (i = 0; i < uFrames; i++) { 3324 *cmask = *cmask << 1; 3325 *cmask |= 0x1; 3326 } 3327 /* cmask must start 2 frames after the smask */ 3328 *cmask = *cmask << 2; 3329 3330 found = 0; 3331 best_smask = 0x00; 3332 best_node_bandwidth = 0; 3333 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3334 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3335 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3336 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3337 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3338 &bw_cmask); 3339 3340 /* 3341 * If this node cannot support our requirements skip to the 3342 * next leaf. 3343 */ 3344 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3345 continue; 3346 } 3347 3348 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3349 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3350 found = 1; 3351 break; 3352 } 3353 *smask = *smask << 1; 3354 *cmask = *cmask << 1; 3355 } 3356 3357 /* 3358 * If an appropriate smask is found save the information if: 3359 * o best_smask has not been found yet. 3360 * - or - 3361 * o This is the node with the least amount of bandwidth 3362 */ 3363 if (found && 3364 ((best_smask == 0x00) || 3365 (best_node_bandwidth > 3366 (node_sbandwidth + node_cbandwidth)))) { 3367 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3368 best_array_leaf = array_leaf; 3369 best_smask = *smask; 3370 best_cmask = *cmask; 3371 } 3372 } 3373 3374 /* 3375 * If we find node that can handle the bandwidth populate the 3376 * appropriate variables and return success. 3377 */ 3378 if (best_smask) { 3379 *smask = best_smask; 3380 *cmask = best_cmask; 3381 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3382 interval); 3383 ehci_update_bw_availability(ehcip, sbandwidth, 3384 ehci_index[best_array_leaf], leaf_count, best_smask); 3385 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3386 ehci_index[best_array_leaf], leaf_count, best_cmask); 3387 3388 return (USB_SUCCESS); 3389 } 3390 3391 return (USB_FAILURE); 3392 } 3393 3394 3395 /* 3396 * ehci_find_bestfit_sitd_out_mask: 3397 * 3398 * Find the smask in the bandwidth allocation. 3399 */ 3400 static int 3401 ehci_find_bestfit_sitd_out_mask( 3402 ehci_state_t *ehcip, 3403 uchar_t *smask, 3404 uint_t *pnode, 3405 uint_t sbandwidth, 3406 int interval) 3407 { 3408 int i, uFrames, found; 3409 int array_leaf, best_array_leaf; 3410 uint_t node_sbandwidth; 3411 uint_t best_node_bandwidth; 3412 uint_t leaf_count; 3413 uchar_t bw_smask; 3414 uchar_t best_smask; 3415 3416 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3417 "ehci_find_bestfit_sitd_out_mask: "); 3418 3419 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3420 3421 /* 3422 * Because of the way the leaves are setup, we will automatically 3423 * hit the leftmost leaf of every possible node with this interval. 3424 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3425 */ 3426 *smask = 0x00; 3427 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3428 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3429 uFrames++; 3430 } 3431 for (i = 0; i < uFrames; i++) { 3432 *smask = *smask << 1; 3433 *smask |= 0x1; 3434 } 3435 3436 found = 0; 3437 best_smask = 0x00; 3438 best_node_bandwidth = 0; 3439 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3440 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3441 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3442 &bw_smask); 3443 3444 /* 3445 * If this node cannot support our requirements skip to the 3446 * next leaf. 3447 */ 3448 if (bw_smask == 0x00) { 3449 continue; 3450 } 3451 3452 /* You cannot have a start split on the 8th uFrame */ 3453 for (i = 0; (*smask & 0x80) == 0; i++) { 3454 if (*smask & bw_smask) { 3455 found = 1; 3456 break; 3457 } 3458 *smask = *smask << 1; 3459 } 3460 3461 /* 3462 * If an appropriate smask is found save the information if: 3463 * o best_smask has not been found yet. 3464 * - or - 3465 * o This is the node with the least amount of bandwidth 3466 */ 3467 if (found && 3468 ((best_smask == 0x00) || 3469 (best_node_bandwidth > node_sbandwidth))) { 3470 best_node_bandwidth = node_sbandwidth; 3471 best_array_leaf = array_leaf; 3472 best_smask = *smask; 3473 } 3474 } 3475 3476 /* 3477 * If we find node that can handle the bandwidth populate the 3478 * appropriate variables and return success. 3479 */ 3480 if (best_smask) { 3481 *smask = best_smask; 3482 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3483 interval); 3484 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3485 ehci_index[best_array_leaf], leaf_count, best_smask); 3486 3487 return (USB_SUCCESS); 3488 } 3489 3490 return (USB_FAILURE); 3491 } 3492 3493 3494 /* 3495 * ehci_calculate_bw_availability_mask: 3496 * 3497 * Returns the "total bandwidth used" in this node. 3498 * Populates bw_mask with the uFrames that can support the bandwidth. 3499 * 3500 * If all the Frames cannot support this bandwidth, then bw_mask 3501 * will return 0x00 and the "total bandwidth used" will be invalid. 3502 */ 3503 static uint_t 3504 ehci_calculate_bw_availability_mask( 3505 ehci_state_t *ehcip, 3506 uint_t bandwidth, 3507 int leaf, 3508 int leaf_count, 3509 uchar_t *bw_mask) 3510 { 3511 int i, j; 3512 uchar_t bw_uframe; 3513 int uframe_total; 3514 ehci_frame_bandwidth_t *fbp; 3515 uint_t total_bandwidth = 0; 3516 3517 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3518 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3519 leaf, leaf_count); 3520 3521 /* Start by saying all uFrames are available */ 3522 *bw_mask = 0xFF; 3523 3524 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3525 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3526 3527 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3528 3529 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3530 /* 3531 * If the uFrame in bw_mask is available check to see if 3532 * it can support the additional bandwidth. 3533 */ 3534 bw_uframe = (*bw_mask & (0x1 << j)); 3535 uframe_total = 3536 fbp->ehci_micro_frame_bandwidth[j] + 3537 bandwidth; 3538 if ((bw_uframe) && 3539 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3540 *bw_mask = *bw_mask & ~bw_uframe; 3541 } 3542 } 3543 } 3544 3545 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3546 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3547 *bw_mask); 3548 3549 return (total_bandwidth); 3550 } 3551 3552 3553 /* 3554 * ehci_update_bw_availability: 3555 * 3556 * The leftmost leaf needs to be in terms of array position and 3557 * not the actual lattice position. 3558 */ 3559 static void 3560 ehci_update_bw_availability( 3561 ehci_state_t *ehcip, 3562 int bandwidth, 3563 int leftmost_leaf, 3564 int leaf_count, 3565 uchar_t mask) 3566 { 3567 int i, j; 3568 ehci_frame_bandwidth_t *fbp; 3569 int uFrame_bandwidth[8]; 3570 3571 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3572 "ehci_update_bw_availability: " 3573 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3574 leftmost_leaf, leaf_count, bandwidth, mask); 3575 3576 ASSERT(leftmost_leaf < 32); 3577 ASSERT(leftmost_leaf >= 0); 3578 3579 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3580 if (mask & 0x1) { 3581 uFrame_bandwidth[j] = bandwidth; 3582 } else { 3583 uFrame_bandwidth[j] = 0; 3584 } 3585 3586 mask = mask >> 1; 3587 } 3588 3589 /* Updated all the effected leafs with the bandwidth */ 3590 for (i = 0; i < leaf_count; i++) { 3591 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3592 3593 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3594 fbp->ehci_micro_frame_bandwidth[j] += 3595 uFrame_bandwidth[j]; 3596 fbp->ehci_allocated_frame_bandwidth += 3597 uFrame_bandwidth[j]; 3598 } 3599 } 3600 } 3601 3602 /* 3603 * Miscellaneous functions 3604 */ 3605 3606 /* 3607 * ehci_obtain_state: 3608 * 3609 * NOTE: This function is also called from POLLED MODE. 3610 */ 3611 ehci_state_t * 3612 ehci_obtain_state(dev_info_t *dip) 3613 { 3614 int instance = ddi_get_instance(dip); 3615 3616 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3617 3618 ASSERT(state != NULL); 3619 3620 return (state); 3621 } 3622 3623 3624 /* 3625 * ehci_state_is_operational: 3626 * 3627 * Check the Host controller state and return proper values. 3628 */ 3629 int 3630 ehci_state_is_operational(ehci_state_t *ehcip) 3631 { 3632 int val; 3633 3634 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3635 3636 switch (ehcip->ehci_hc_soft_state) { 3637 case EHCI_CTLR_INIT_STATE: 3638 case EHCI_CTLR_SUSPEND_STATE: 3639 val = USB_FAILURE; 3640 break; 3641 case EHCI_CTLR_OPERATIONAL_STATE: 3642 val = USB_SUCCESS; 3643 break; 3644 case EHCI_CTLR_ERROR_STATE: 3645 val = USB_HC_HARDWARE_ERROR; 3646 break; 3647 default: 3648 val = USB_FAILURE; 3649 break; 3650 } 3651 3652 return (val); 3653 } 3654 3655 3656 /* 3657 * ehci_do_soft_reset 3658 * 3659 * Do soft reset of ehci host controller. 3660 */ 3661 int 3662 ehci_do_soft_reset(ehci_state_t *ehcip) 3663 { 3664 usb_frame_number_t before_frame_number, after_frame_number; 3665 ehci_regs_t *ehci_save_regs; 3666 3667 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3668 3669 /* Increment host controller error count */ 3670 ehcip->ehci_hc_error++; 3671 3672 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3673 "ehci_do_soft_reset:" 3674 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3675 3676 /* 3677 * Allocate space for saving current Host Controller 3678 * registers. Don't do any recovery if allocation 3679 * fails. 3680 */ 3681 ehci_save_regs = (ehci_regs_t *) 3682 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3683 3684 if (ehci_save_regs == NULL) { 3685 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3686 "ehci_do_soft_reset: kmem_zalloc failed"); 3687 3688 return (USB_FAILURE); 3689 } 3690 3691 /* Save current ehci registers */ 3692 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3693 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3694 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3695 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3696 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3697 ehci_save_regs->ehci_periodic_list_base = 3698 Get_OpReg(ehci_periodic_list_base); 3699 3700 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3701 "ehci_do_soft_reset: Save reg = 0x%p", (void *)ehci_save_regs); 3702 3703 /* Disable all list processing and interrupts */ 3704 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3705 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3706 3707 /* Disable all EHCI interrupts */ 3708 Set_OpReg(ehci_interrupt, 0); 3709 3710 /* Wait for few milliseconds */ 3711 drv_usecwait(EHCI_SOF_TIMEWAIT); 3712 3713 /* Do light soft reset of ehci host controller */ 3714 Set_OpReg(ehci_command, 3715 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3716 3717 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3718 "ehci_do_soft_reset: Reset in progress"); 3719 3720 /* Wait for reset to complete */ 3721 drv_usecwait(EHCI_RESET_TIMEWAIT); 3722 3723 /* 3724 * Restore previous saved EHCI register value 3725 * into the current EHCI registers. 3726 */ 3727 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3728 ehci_save_regs->ehci_ctrl_segment); 3729 3730 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3731 ehci_save_regs->ehci_periodic_list_base); 3732 3733 Set_OpReg(ehci_async_list_addr, (uint32_t) 3734 ehci_save_regs->ehci_async_list_addr); 3735 3736 /* 3737 * For some reason this register might get nulled out by 3738 * the Uli M1575 South Bridge. To workaround the hardware 3739 * problem, check the value after write and retry if the 3740 * last write fails. 3741 */ 3742 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 3743 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 3744 (ehci_save_regs->ehci_async_list_addr != 3745 Get_OpReg(ehci_async_list_addr))) { 3746 int retry = 0; 3747 3748 Set_OpRegRetry(ehci_async_list_addr, (uint32_t) 3749 ehci_save_regs->ehci_async_list_addr, retry); 3750 if (retry >= EHCI_MAX_RETRY) { 3751 USB_DPRINTF_L2(PRINT_MASK_ATTA, 3752 ehcip->ehci_log_hdl, "ehci_do_soft_reset:" 3753 " ASYNCLISTADDR write failed."); 3754 3755 return (USB_FAILURE); 3756 } 3757 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3758 "ehci_do_soft_reset: ASYNCLISTADDR " 3759 "write failed, retry=%d", retry); 3760 } 3761 3762 Set_OpReg(ehci_config_flag, (uint32_t) 3763 ehci_save_regs->ehci_config_flag); 3764 3765 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3766 ehci_toggle_scheduler(ehcip); 3767 3768 /* 3769 * Set ehci_interrupt to enable all interrupts except Root 3770 * Hub Status change and frame list rollover interrupts. 3771 */ 3772 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3773 EHCI_INTR_FRAME_LIST_ROLLOVER | 3774 EHCI_INTR_USB_ERROR | 3775 EHCI_INTR_USB); 3776 3777 /* 3778 * Deallocate the space that allocated for saving 3779 * HC registers. 3780 */ 3781 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3782 3783 /* 3784 * Set the desired interrupt threshold, frame list size (if 3785 * applicable) and turn EHCI host controller. 3786 */ 3787 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3788 ~EHCI_CMD_INTR_THRESHOLD) | 3789 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3790 3791 /* Wait 10ms for EHCI to start sending SOF */ 3792 drv_usecwait(EHCI_RESET_TIMEWAIT); 3793 3794 /* 3795 * Get the current usb frame number before waiting for 3796 * few milliseconds. 3797 */ 3798 before_frame_number = ehci_get_current_frame_number(ehcip); 3799 3800 /* Wait for few milliseconds */ 3801 drv_usecwait(EHCI_SOF_TIMEWAIT); 3802 3803 /* 3804 * Get the current usb frame number after waiting for 3805 * few milliseconds. 3806 */ 3807 after_frame_number = ehci_get_current_frame_number(ehcip); 3808 3809 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3810 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3811 "After Frame Number 0x%llx", 3812 (unsigned long long)before_frame_number, 3813 (unsigned long long)after_frame_number); 3814 3815 if ((after_frame_number <= before_frame_number) && 3816 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3817 3818 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3819 "ehci_do_soft_reset: Soft reset failed"); 3820 3821 return (USB_FAILURE); 3822 } 3823 3824 return (USB_SUCCESS); 3825 } 3826 3827 3828 /* 3829 * ehci_get_xfer_attrs: 3830 * 3831 * Get the attributes of a particular xfer. 3832 * 3833 * NOTE: This function is also called from POLLED MODE. 3834 */ 3835 usb_req_attrs_t 3836 ehci_get_xfer_attrs( 3837 ehci_state_t *ehcip, 3838 ehci_pipe_private_t *pp, 3839 ehci_trans_wrapper_t *tw) 3840 { 3841 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3842 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3843 3844 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3845 "ehci_get_xfer_attrs:"); 3846 3847 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3848 case USB_EP_ATTR_CONTROL: 3849 attrs = ((usb_ctrl_req_t *) 3850 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3851 break; 3852 case USB_EP_ATTR_BULK: 3853 attrs = ((usb_bulk_req_t *) 3854 tw->tw_curr_xfer_reqp)->bulk_attributes; 3855 break; 3856 case USB_EP_ATTR_INTR: 3857 attrs = ((usb_intr_req_t *) 3858 tw->tw_curr_xfer_reqp)->intr_attributes; 3859 break; 3860 } 3861 3862 return (attrs); 3863 } 3864 3865 3866 /* 3867 * ehci_get_current_frame_number: 3868 * 3869 * Get the current software based usb frame number. 3870 */ 3871 usb_frame_number_t 3872 ehci_get_current_frame_number(ehci_state_t *ehcip) 3873 { 3874 usb_frame_number_t usb_frame_number; 3875 usb_frame_number_t ehci_fno, micro_frame_number; 3876 3877 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3878 3879 ehci_fno = ehcip->ehci_fno; 3880 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3881 3882 /* 3883 * Calculate current software based usb frame number. 3884 * 3885 * This code accounts for the fact that frame number is 3886 * updated by the Host Controller before the ehci driver 3887 * gets an FrameListRollover interrupt that will adjust 3888 * Frame higher part. 3889 * 3890 * Refer ehci specification 1.0, section 2.3.2, page 21. 3891 */ 3892 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3893 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3894 ehci_fno) & 0x2000); 3895 3896 /* 3897 * Micro Frame number is equivalent to 125 usec. Eight 3898 * Micro Frame numbers are equivalent to one millsecond 3899 * or one usb frame number. 3900 */ 3901 usb_frame_number = micro_frame_number >> 3902 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3903 3904 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3905 "ehci_get_current_frame_number: " 3906 "Current usb uframe number = 0x%llx " 3907 "Current usb frame number = 0x%llx", 3908 (unsigned long long)micro_frame_number, 3909 (unsigned long long)usb_frame_number); 3910 3911 return (usb_frame_number); 3912 } 3913 3914 3915 /* 3916 * ehci_cpr_cleanup: 3917 * 3918 * Cleanup ehci state and other ehci specific informations across 3919 * Check Point Resume (CPR). 3920 */ 3921 static void 3922 ehci_cpr_cleanup(ehci_state_t *ehcip) 3923 { 3924 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3925 3926 /* Reset software part of usb frame number */ 3927 ehcip->ehci_fno = 0; 3928 } 3929 3930 3931 /* 3932 * ehci_wait_for_sof: 3933 * 3934 * Wait for couple of SOF interrupts 3935 */ 3936 int 3937 ehci_wait_for_sof(ehci_state_t *ehcip) 3938 { 3939 usb_frame_number_t before_frame_number, after_frame_number; 3940 int error = USB_SUCCESS; 3941 3942 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3943 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3944 3945 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3946 3947 error = ehci_state_is_operational(ehcip); 3948 3949 if (error != USB_SUCCESS) { 3950 3951 return (error); 3952 } 3953 3954 /* Get the current usb frame number before waiting for two SOFs */ 3955 before_frame_number = ehci_get_current_frame_number(ehcip); 3956 3957 mutex_exit(&ehcip->ehci_int_mutex); 3958 3959 /* Wait for few milliseconds */ 3960 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3961 3962 mutex_enter(&ehcip->ehci_int_mutex); 3963 3964 /* Get the current usb frame number after woken up */ 3965 after_frame_number = ehci_get_current_frame_number(ehcip); 3966 3967 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3968 "ehci_wait_for_sof: framenumber: before 0x%llx " 3969 "after 0x%llx", 3970 (unsigned long long)before_frame_number, 3971 (unsigned long long)after_frame_number); 3972 3973 /* Return failure, if usb frame number has not been changed */ 3974 if (after_frame_number <= before_frame_number) { 3975 3976 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3977 3978 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3979 ehcip->ehci_log_hdl, "No SOF interrupts"); 3980 3981 /* Set host controller soft state to error */ 3982 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 3983 3984 return (USB_FAILURE); 3985 } 3986 3987 } 3988 3989 return (USB_SUCCESS); 3990 } 3991 3992 3993 /* 3994 * ehci_toggle_scheduler: 3995 * 3996 * Turn scheduler based on pipe open count. 3997 */ 3998 void 3999 ehci_toggle_scheduler(ehci_state_t *ehcip) { 4000 uint_t temp_reg, cmd_reg; 4001 4002 cmd_reg = Get_OpReg(ehci_command); 4003 temp_reg = cmd_reg; 4004 4005 /* 4006 * Enable/Disable asynchronous scheduler, and 4007 * turn on/off async list door bell 4008 */ 4009 if (ehcip->ehci_open_async_count) { 4010 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 4011 /* 4012 * For some reason this address might get nulled out by 4013 * the ehci chip. Set it here just in case it is null. 4014 */ 4015 Set_OpReg(ehci_async_list_addr, 4016 ehci_qh_cpu_to_iommu(ehcip, 4017 ehcip->ehci_head_of_async_sched_list)); 4018 4019 /* 4020 * For some reason this register might get nulled out by 4021 * the Uli M1575 Southbridge. To workaround the HW 4022 * problem, check the value after write and retry if the 4023 * last write fails. 4024 * 4025 * If the ASYNCLISTADDR remains "stuck" after 4026 * EHCI_MAX_RETRY retries, then the M1575 is broken 4027 * and is stuck in an inconsistent state and is about 4028 * to crash the machine with a trn_oor panic when it 4029 * does a DMA read from 0x0. It is better to panic 4030 * now rather than wait for the trn_oor crash; this 4031 * way Customer Service will have a clean signature 4032 * that indicts the M1575 chip rather than a 4033 * mysterious and hard-to-diagnose trn_oor panic. 4034 */ 4035 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 4036 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 4037 (ehci_qh_cpu_to_iommu(ehcip, 4038 ehcip->ehci_head_of_async_sched_list) != 4039 Get_OpReg(ehci_async_list_addr))) { 4040 int retry = 0; 4041 4042 Set_OpRegRetry(ehci_async_list_addr, 4043 ehci_qh_cpu_to_iommu(ehcip, 4044 ehcip->ehci_head_of_async_sched_list), 4045 retry); 4046 if (retry >= EHCI_MAX_RETRY) 4047 cmn_err(CE_PANIC, 4048 "ehci_toggle_scheduler: " 4049 "ASYNCLISTADDR write failed."); 4050 4051 USB_DPRINTF_L2(PRINT_MASK_ATTA, 4052 ehcip->ehci_log_hdl, 4053 "ehci_toggle_scheduler: ASYNCLISTADDR " 4054 "write failed, retry=%d", retry); 4055 } 4056 } 4057 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 4058 } else { 4059 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 4060 } 4061 4062 if (ehcip->ehci_open_periodic_count) { 4063 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 4064 /* 4065 * For some reason this address get's nulled out by 4066 * the ehci chip. Set it here just in case it is null. 4067 */ 4068 Set_OpReg(ehci_periodic_list_base, 4069 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 4070 0xFFFFF000)); 4071 } 4072 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 4073 } else { 4074 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 4075 } 4076 4077 /* Just an optimization */ 4078 if (temp_reg != cmd_reg) { 4079 Set_OpReg(ehci_command, cmd_reg); 4080 } 4081 } 4082 4083 /* 4084 * ehci print functions 4085 */ 4086 4087 /* 4088 * ehci_print_caps: 4089 */ 4090 void 4091 ehci_print_caps(ehci_state_t *ehcip) 4092 { 4093 uint_t i; 4094 4095 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4096 "\n\tUSB 2.0 Host Controller Characteristics\n"); 4097 4098 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4099 "Caps Length: 0x%x Version: 0x%x\n", 4100 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 4101 4102 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4103 "Structural Parameters\n"); 4104 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4105 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 4106 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 4107 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4108 "No of Classic host controllers: 0x%x", 4109 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 4110 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 4111 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4112 "No of ports per Classic host controller: 0x%x", 4113 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 4114 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 4115 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4116 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 4117 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 4118 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4119 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 4120 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 4121 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4122 "No of root hub ports: 0x%x\n", 4123 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 4124 4125 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4126 "Capability Parameters\n"); 4127 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4128 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 4129 EHCI_HCC_EECP) ? "Yes" : "No"); 4130 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4131 "Isoch schedule threshold: 0x%x", 4132 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 4133 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4134 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 4135 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 4136 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4137 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 4138 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 4139 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4140 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 4141 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 4142 4143 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4144 "Classic Port Route Description"); 4145 4146 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4147 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4148 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 4149 } 4150 } 4151 4152 4153 /* 4154 * ehci_print_regs: 4155 */ 4156 void 4157 ehci_print_regs(ehci_state_t *ehcip) 4158 { 4159 uint_t i; 4160 4161 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4162 "\n\tEHCI%d Operational Registers\n", 4163 ddi_get_instance(ehcip->ehci_dip)); 4164 4165 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4166 "Command: 0x%x Status: 0x%x", 4167 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 4168 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4169 "Interrupt: 0x%x Frame Index: 0x%x", 4170 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 4171 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4172 "Control Segment: 0x%x Periodic List Base: 0x%x", 4173 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 4174 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4175 "Async List Addr: 0x%x Config Flag: 0x%x", 4176 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 4177 4178 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4179 "Root Hub Port Status"); 4180 4181 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4182 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4183 "\tPort Status 0x%x: 0x%x ", i, 4184 Get_OpReg(ehci_rh_port_status[i])); 4185 } 4186 } 4187 4188 4189 /* 4190 * ehci_print_qh: 4191 */ 4192 void 4193 ehci_print_qh( 4194 ehci_state_t *ehcip, 4195 ehci_qh_t *qh) 4196 { 4197 uint_t i; 4198 4199 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4200 "ehci_print_qh: qh = 0x%p", (void *)qh); 4201 4202 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4203 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 4204 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4205 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 4206 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4207 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 4208 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4209 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 4210 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4211 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 4212 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4213 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 4214 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4215 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 4216 4217 for (i = 0; i < 5; i++) { 4218 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4219 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 4220 } 4221 4222 for (i = 0; i < 5; i++) { 4223 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4224 "\tqh_buf_high[%d]: 0x%x ", 4225 i, Get_QH(qh->qh_buf_high[i])); 4226 } 4227 4228 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4229 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 4230 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4231 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 4232 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4233 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 4234 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4235 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 4236 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4237 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 4238 } 4239 4240 4241 /* 4242 * ehci_print_qtd: 4243 */ 4244 void 4245 ehci_print_qtd( 4246 ehci_state_t *ehcip, 4247 ehci_qtd_t *qtd) 4248 { 4249 uint_t i; 4250 4251 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4252 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 4253 4254 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4255 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 4256 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4257 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 4258 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4259 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 4260 4261 for (i = 0; i < 5; i++) { 4262 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4263 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 4264 } 4265 4266 for (i = 0; i < 5; i++) { 4267 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4268 "\tqtd_buf_high[%d]: 0x%x ", 4269 i, Get_QTD(qtd->qtd_buf_high[i])); 4270 } 4271 4272 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4273 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 4274 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4275 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 4276 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4277 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 4278 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4279 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 4280 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4281 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 4282 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4283 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 4284 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4285 "\tqtd_xfer_offs: 0x%x ", Get_QTD(qtd->qtd_xfer_offs)); 4286 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4287 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 4288 } 4289 4290 /* 4291 * ehci kstat functions 4292 */ 4293 4294 /* 4295 * ehci_create_stats: 4296 * 4297 * Allocate and initialize the ehci kstat structures 4298 */ 4299 void 4300 ehci_create_stats(ehci_state_t *ehcip) 4301 { 4302 char kstatname[KSTAT_STRLEN]; 4303 const char *dname = ddi_driver_name(ehcip->ehci_dip); 4304 char *usbtypes[USB_N_COUNT_KSTATS] = 4305 {"ctrl", "isoch", "bulk", "intr"}; 4306 uint_t instance = ehcip->ehci_instance; 4307 ehci_intrs_stats_t *isp; 4308 int i; 4309 4310 if (EHCI_INTRS_STATS(ehcip) == NULL) { 4311 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 4312 dname, instance); 4313 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 4314 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 4315 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 4316 KSTAT_FLAG_PERSISTENT); 4317 4318 if (EHCI_INTRS_STATS(ehcip)) { 4319 isp = EHCI_INTRS_STATS_DATA(ehcip); 4320 kstat_named_init(&isp->ehci_sts_total, 4321 "Interrupts Total", KSTAT_DATA_UINT64); 4322 kstat_named_init(&isp->ehci_sts_not_claimed, 4323 "Not Claimed", KSTAT_DATA_UINT64); 4324 kstat_named_init(&isp->ehci_sts_async_sched_status, 4325 "Async schedule status", KSTAT_DATA_UINT64); 4326 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 4327 "Periodic sched status", KSTAT_DATA_UINT64); 4328 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 4329 "Empty async schedule", KSTAT_DATA_UINT64); 4330 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 4331 "Host controller Halted", KSTAT_DATA_UINT64); 4332 kstat_named_init(&isp->ehci_sts_async_advance_intr, 4333 "Intr on async advance", KSTAT_DATA_UINT64); 4334 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 4335 "Host system error", KSTAT_DATA_UINT64); 4336 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 4337 "Frame list rollover", KSTAT_DATA_UINT64); 4338 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 4339 "Port change detect", KSTAT_DATA_UINT64); 4340 kstat_named_init(&isp->ehci_sts_usb_error_intr, 4341 "USB error interrupt", KSTAT_DATA_UINT64); 4342 kstat_named_init(&isp->ehci_sts_usb_intr, 4343 "USB interrupt", KSTAT_DATA_UINT64); 4344 4345 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 4346 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 4347 kstat_install(EHCI_INTRS_STATS(ehcip)); 4348 } 4349 } 4350 4351 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 4352 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 4353 dname, instance); 4354 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 4355 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 4356 KSTAT_FLAG_PERSISTENT); 4357 4358 if (EHCI_TOTAL_STATS(ehcip)) { 4359 kstat_install(EHCI_TOTAL_STATS(ehcip)); 4360 } 4361 } 4362 4363 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4364 if (ehcip->ehci_count_stats[i] == NULL) { 4365 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4366 dname, instance, usbtypes[i]); 4367 ehcip->ehci_count_stats[i] = kstat_create("usba", 4368 instance, kstatname, "usb_byte_count", 4369 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4370 4371 if (ehcip->ehci_count_stats[i]) { 4372 kstat_install(ehcip->ehci_count_stats[i]); 4373 } 4374 } 4375 } 4376 } 4377 4378 4379 /* 4380 * ehci_destroy_stats: 4381 * 4382 * Clean up ehci kstat structures 4383 */ 4384 void 4385 ehci_destroy_stats(ehci_state_t *ehcip) 4386 { 4387 int i; 4388 4389 if (EHCI_INTRS_STATS(ehcip)) { 4390 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4391 EHCI_INTRS_STATS(ehcip) = NULL; 4392 } 4393 4394 if (EHCI_TOTAL_STATS(ehcip)) { 4395 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4396 EHCI_TOTAL_STATS(ehcip) = NULL; 4397 } 4398 4399 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4400 if (ehcip->ehci_count_stats[i]) { 4401 kstat_delete(ehcip->ehci_count_stats[i]); 4402 ehcip->ehci_count_stats[i] = NULL; 4403 } 4404 } 4405 } 4406 4407 4408 /* 4409 * ehci_do_intrs_stats: 4410 * 4411 * ehci status information 4412 */ 4413 void 4414 ehci_do_intrs_stats( 4415 ehci_state_t *ehcip, 4416 int val) 4417 { 4418 if (EHCI_INTRS_STATS(ehcip)) { 4419 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4420 switch (val) { 4421 case EHCI_STS_ASYNC_SCHED_STATUS: 4422 EHCI_INTRS_STATS_DATA(ehcip)-> 4423 ehci_sts_async_sched_status.value.ui64++; 4424 break; 4425 case EHCI_STS_PERIODIC_SCHED_STATUS: 4426 EHCI_INTRS_STATS_DATA(ehcip)-> 4427 ehci_sts_periodic_sched_status.value.ui64++; 4428 break; 4429 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4430 EHCI_INTRS_STATS_DATA(ehcip)-> 4431 ehci_sts_empty_async_schedule.value.ui64++; 4432 break; 4433 case EHCI_STS_HOST_CTRL_HALTED: 4434 EHCI_INTRS_STATS_DATA(ehcip)-> 4435 ehci_sts_host_ctrl_halted.value.ui64++; 4436 break; 4437 case EHCI_STS_ASYNC_ADVANCE_INTR: 4438 EHCI_INTRS_STATS_DATA(ehcip)-> 4439 ehci_sts_async_advance_intr.value.ui64++; 4440 break; 4441 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4442 EHCI_INTRS_STATS_DATA(ehcip)-> 4443 ehci_sts_host_system_error_intr.value.ui64++; 4444 break; 4445 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4446 EHCI_INTRS_STATS_DATA(ehcip)-> 4447 ehci_sts_frm_list_rollover_intr.value.ui64++; 4448 break; 4449 case EHCI_STS_RH_PORT_CHANGE_INTR: 4450 EHCI_INTRS_STATS_DATA(ehcip)-> 4451 ehci_sts_rh_port_change_intr.value.ui64++; 4452 break; 4453 case EHCI_STS_USB_ERROR_INTR: 4454 EHCI_INTRS_STATS_DATA(ehcip)-> 4455 ehci_sts_usb_error_intr.value.ui64++; 4456 break; 4457 case EHCI_STS_USB_INTR: 4458 EHCI_INTRS_STATS_DATA(ehcip)-> 4459 ehci_sts_usb_intr.value.ui64++; 4460 break; 4461 default: 4462 EHCI_INTRS_STATS_DATA(ehcip)-> 4463 ehci_sts_not_claimed.value.ui64++; 4464 break; 4465 } 4466 } 4467 } 4468 4469 4470 /* 4471 * ehci_do_byte_stats: 4472 * 4473 * ehci data xfer information 4474 */ 4475 void 4476 ehci_do_byte_stats( 4477 ehci_state_t *ehcip, 4478 size_t len, 4479 uint8_t attr, 4480 uint8_t addr) 4481 { 4482 uint8_t type = attr & USB_EP_ATTR_MASK; 4483 uint8_t dir = addr & USB_EP_DIR_MASK; 4484 4485 if (dir == USB_EP_DIR_IN) { 4486 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4487 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4488 switch (type) { 4489 case USB_EP_ATTR_CONTROL: 4490 EHCI_CTRL_STATS(ehcip)->reads++; 4491 EHCI_CTRL_STATS(ehcip)->nread += len; 4492 break; 4493 case USB_EP_ATTR_BULK: 4494 EHCI_BULK_STATS(ehcip)->reads++; 4495 EHCI_BULK_STATS(ehcip)->nread += len; 4496 break; 4497 case USB_EP_ATTR_INTR: 4498 EHCI_INTR_STATS(ehcip)->reads++; 4499 EHCI_INTR_STATS(ehcip)->nread += len; 4500 break; 4501 case USB_EP_ATTR_ISOCH: 4502 EHCI_ISOC_STATS(ehcip)->reads++; 4503 EHCI_ISOC_STATS(ehcip)->nread += len; 4504 break; 4505 } 4506 } else if (dir == USB_EP_DIR_OUT) { 4507 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4508 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4509 switch (type) { 4510 case USB_EP_ATTR_CONTROL: 4511 EHCI_CTRL_STATS(ehcip)->writes++; 4512 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4513 break; 4514 case USB_EP_ATTR_BULK: 4515 EHCI_BULK_STATS(ehcip)->writes++; 4516 EHCI_BULK_STATS(ehcip)->nwritten += len; 4517 break; 4518 case USB_EP_ATTR_INTR: 4519 EHCI_INTR_STATS(ehcip)->writes++; 4520 EHCI_INTR_STATS(ehcip)->nwritten += len; 4521 break; 4522 case USB_EP_ATTR_ISOCH: 4523 EHCI_ISOC_STATS(ehcip)->writes++; 4524 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4525 break; 4526 } 4527 } 4528 } 4529