1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * EHCI Host Controller Driver (EHCI) 30 * 31 * The EHCI driver is a software driver which interfaces to the Universal 32 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 33 * the Host Controller is defined by the EHCI Host Controller Interface. 34 * 35 * This module contains the main EHCI driver code which handles all USB 36 * transfers, bandwidth allocations and other general functionalities. 37 */ 38 39 #include <sys/usb/hcd/ehci/ehcid.h> 40 #include <sys/usb/hcd/ehci/ehci_isoch.h> 41 #include <sys/usb/hcd/ehci/ehci_xfer.h> 42 43 /* 44 * EHCI MSI tunable: 45 * 46 * By default MSI is enabled on all supported platforms except for the 47 * EHCI controller of ULI1575 South bridge. 48 */ 49 boolean_t ehci_enable_msi = B_TRUE; 50 51 /* Pointer to the state structure */ 52 extern void *ehci_statep; 53 54 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 55 56 extern uint_t ehci_vt62x2_workaround; 57 58 /* Adjustable variables for the size of the pools */ 59 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 60 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 61 62 /* 63 * Initialize the values which the order of 32ms intr qh are executed 64 * by the host controller in the lattice tree. 65 */ 66 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 67 {0x00, 0x10, 0x08, 0x18, 68 0x04, 0x14, 0x0c, 0x1c, 69 0x02, 0x12, 0x0a, 0x1a, 70 0x06, 0x16, 0x0e, 0x1e, 71 0x01, 0x11, 0x09, 0x19, 72 0x05, 0x15, 0x0d, 0x1d, 73 0x03, 0x13, 0x0b, 0x1b, 74 0x07, 0x17, 0x0f, 0x1f}; 75 76 /* 77 * Initialize the values which are used to calculate start split mask 78 * for the low/full/high speed interrupt and isochronous endpoints. 79 */ 80 static uint_t ehci_start_split_mask[15] = { 81 /* 82 * For high/full/low speed usb devices. For high speed 83 * device with polling interval greater than or equal 84 * to 8us (125us). 85 */ 86 0x01, /* 00000001 */ 87 0x02, /* 00000010 */ 88 0x04, /* 00000100 */ 89 0x08, /* 00001000 */ 90 0x10, /* 00010000 */ 91 0x20, /* 00100000 */ 92 0x40, /* 01000000 */ 93 0x80, /* 10000000 */ 94 95 /* Only for high speed devices with polling interval 4us */ 96 0x11, /* 00010001 */ 97 0x22, /* 00100010 */ 98 0x44, /* 01000100 */ 99 0x88, /* 10001000 */ 100 101 /* Only for high speed devices with polling interval 2us */ 102 0x55, /* 01010101 */ 103 0xaa, /* 10101010 */ 104 105 /* Only for high speed devices with polling interval 1us */ 106 0xff /* 11111111 */ 107 }; 108 109 /* 110 * Initialize the values which are used to calculate complete split mask 111 * for the low/full speed interrupt and isochronous endpoints. 112 */ 113 static uint_t ehci_intr_complete_split_mask[7] = { 114 /* Only full/low speed devices */ 115 0x1c, /* 00011100 */ 116 0x38, /* 00111000 */ 117 0x70, /* 01110000 */ 118 0xe0, /* 11100000 */ 119 0x00, /* Need FSTN feature */ 120 0x00, /* Need FSTN feature */ 121 0x00 /* Need FSTN feature */ 122 }; 123 124 125 /* 126 * EHCI Internal Function Prototypes 127 */ 128 129 /* Host Controller Driver (HCD) initialization functions */ 130 void ehci_set_dma_attributes(ehci_state_t *ehcip); 131 int ehci_allocate_pools(ehci_state_t *ehcip); 132 void ehci_decode_ddi_dma_addr_bind_handle_result( 133 ehci_state_t *ehcip, 134 int result); 135 int ehci_map_regs(ehci_state_t *ehcip); 136 int ehci_register_intrs_and_init_mutex( 137 ehci_state_t *ehcip); 138 static int ehci_add_intrs(ehci_state_t *ehcip, 139 int intr_type); 140 int ehci_init_ctlr(ehci_state_t *ehcip, 141 int init_type); 142 static int ehci_take_control(ehci_state_t *ehcip); 143 static int ehci_init_periodic_frame_lst_table( 144 ehci_state_t *ehcip); 145 static void ehci_build_interrupt_lattice( 146 ehci_state_t *ehcip); 147 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 148 149 /* Host Controller Driver (HCD) deinitialization functions */ 150 int ehci_cleanup(ehci_state_t *ehcip); 151 static void ehci_rem_intrs(ehci_state_t *ehcip); 152 int ehci_cpr_suspend(ehci_state_t *ehcip); 153 int ehci_cpr_resume(ehci_state_t *ehcip); 154 155 /* Bandwidth Allocation functions */ 156 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 157 usba_pipe_handle_data_t *ph, 158 uint_t *pnode, 159 uchar_t *smask, 160 uchar_t *cmask); 161 static int ehci_allocate_high_speed_bandwidth( 162 ehci_state_t *ehcip, 163 usba_pipe_handle_data_t *ph, 164 uint_t *hnode, 165 uchar_t *smask, 166 uchar_t *cmask); 167 static int ehci_allocate_classic_tt_bandwidth( 168 ehci_state_t *ehcip, 169 usba_pipe_handle_data_t *ph, 170 uint_t pnode); 171 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 172 usba_pipe_handle_data_t *ph, 173 uint_t pnode, 174 uchar_t smask, 175 uchar_t cmask); 176 static void ehci_deallocate_high_speed_bandwidth( 177 ehci_state_t *ehcip, 178 usba_pipe_handle_data_t *ph, 179 uint_t hnode, 180 uchar_t smask, 181 uchar_t cmask); 182 static void ehci_deallocate_classic_tt_bandwidth( 183 ehci_state_t *ehcip, 184 usba_pipe_handle_data_t *ph, 185 uint_t pnode); 186 static int ehci_compute_high_speed_bandwidth( 187 ehci_state_t *ehcip, 188 usb_ep_descr_t *endpoint, 189 usb_port_status_t port_status, 190 uint_t *sbandwidth, 191 uint_t *cbandwidth); 192 static int ehci_compute_classic_bandwidth( 193 usb_ep_descr_t *endpoint, 194 usb_port_status_t port_status, 195 uint_t *bandwidth); 196 int ehci_adjust_polling_interval( 197 ehci_state_t *ehcip, 198 usb_ep_descr_t *endpoint, 199 usb_port_status_t port_status); 200 static int ehci_adjust_high_speed_polling_interval( 201 ehci_state_t *ehcip, 202 usb_ep_descr_t *endpoint); 203 static uint_t ehci_lattice_height(uint_t interval); 204 static uint_t ehci_lattice_parent(uint_t node); 205 static uint_t ehci_find_periodic_node( 206 uint_t leaf, 207 int interval); 208 static uint_t ehci_leftmost_leaf(uint_t node, 209 uint_t height); 210 static uint_t ehci_pow_2(uint_t x); 211 static uint_t ehci_log_2(uint_t x); 212 static int ehci_find_bestfit_hs_mask( 213 ehci_state_t *ehcip, 214 uchar_t *smask, 215 uint_t *pnode, 216 usb_ep_descr_t *endpoint, 217 uint_t bandwidth, 218 int interval); 219 static int ehci_find_bestfit_ls_intr_mask( 220 ehci_state_t *ehcip, 221 uchar_t *smask, 222 uchar_t *cmask, 223 uint_t *pnode, 224 uint_t sbandwidth, 225 uint_t cbandwidth, 226 int interval); 227 static int ehci_find_bestfit_sitd_in_mask( 228 ehci_state_t *ehcip, 229 uchar_t *smask, 230 uchar_t *cmask, 231 uint_t *pnode, 232 uint_t sbandwidth, 233 uint_t cbandwidth, 234 int interval); 235 static int ehci_find_bestfit_sitd_out_mask( 236 ehci_state_t *ehcip, 237 uchar_t *smask, 238 uint_t *pnode, 239 uint_t sbandwidth, 240 int interval); 241 static uint_t ehci_calculate_bw_availability_mask( 242 ehci_state_t *ehcip, 243 uint_t bandwidth, 244 int leaf, 245 int leaf_count, 246 uchar_t *bw_mask); 247 static void ehci_update_bw_availability( 248 ehci_state_t *ehcip, 249 int bandwidth, 250 int leftmost_leaf, 251 int leaf_count, 252 uchar_t mask); 253 254 /* Miscellaneous functions */ 255 ehci_state_t *ehci_obtain_state( 256 dev_info_t *dip); 257 int ehci_state_is_operational( 258 ehci_state_t *ehcip); 259 int ehci_do_soft_reset( 260 ehci_state_t *ehcip); 261 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 262 ehci_pipe_private_t *pp, 263 ehci_trans_wrapper_t *tw); 264 usb_frame_number_t ehci_get_current_frame_number( 265 ehci_state_t *ehcip); 266 static void ehci_cpr_cleanup( 267 ehci_state_t *ehcip); 268 int ehci_wait_for_sof( 269 ehci_state_t *ehcip); 270 void ehci_toggle_scheduler( 271 ehci_state_t *ehcip); 272 void ehci_print_caps(ehci_state_t *ehcip); 273 void ehci_print_regs(ehci_state_t *ehcip); 274 void ehci_print_qh(ehci_state_t *ehcip, 275 ehci_qh_t *qh); 276 void ehci_print_qtd(ehci_state_t *ehcip, 277 ehci_qtd_t *qtd); 278 void ehci_create_stats(ehci_state_t *ehcip); 279 void ehci_destroy_stats(ehci_state_t *ehcip); 280 void ehci_do_intrs_stats(ehci_state_t *ehcip, 281 int val); 282 void ehci_do_byte_stats(ehci_state_t *ehcip, 283 size_t len, 284 uint8_t attr, 285 uint8_t addr); 286 287 /* 288 * check if this ehci controller can support PM 289 */ 290 int 291 ehci_hcdi_pm_support(dev_info_t *dip) 292 { 293 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 294 ddi_get_instance(dip)); 295 296 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 297 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 298 299 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 300 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 301 302 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 303 304 return (USB_SUCCESS); 305 } 306 307 return (USB_FAILURE); 308 } 309 310 311 /* 312 * Host Controller Driver (HCD) initialization functions 313 */ 314 315 /* 316 * ehci_set_dma_attributes: 317 * 318 * Set the limits in the DMA attributes structure. Most of the values used 319 * in the DMA limit structures are the default values as specified by the 320 * Writing PCI device drivers document. 321 */ 322 void 323 ehci_set_dma_attributes(ehci_state_t *ehcip) 324 { 325 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 326 "ehci_set_dma_attributes:"); 327 328 /* Initialize the DMA attributes */ 329 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 330 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 331 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 332 333 /* 32 bit addressing */ 334 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 335 336 /* Byte alignment */ 337 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 338 339 /* 340 * Since PCI specification is byte alignment, the 341 * burst size field should be set to 1 for PCI devices. 342 */ 343 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 344 345 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 346 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 347 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 348 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 349 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 350 ehcip->ehci_dma_attr.dma_attr_flags = 0; 351 } 352 353 354 /* 355 * ehci_allocate_pools: 356 * 357 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 358 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 359 * to a 16 byte boundary. 360 */ 361 int 362 ehci_allocate_pools(ehci_state_t *ehcip) 363 { 364 ddi_device_acc_attr_t dev_attr; 365 size_t real_length; 366 int result; 367 uint_t ccount; 368 int i; 369 370 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 371 "ehci_allocate_pools:"); 372 373 /* The host controller will be little endian */ 374 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 375 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 376 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 377 378 /* Byte alignment */ 379 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 380 381 /* Allocate the QTD pool DMA handle */ 382 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 383 DDI_DMA_SLEEP, 0, 384 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 385 386 goto failure; 387 } 388 389 /* Allocate the memory for the QTD pool */ 390 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 391 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 392 &dev_attr, 393 DDI_DMA_CONSISTENT, 394 DDI_DMA_SLEEP, 395 0, 396 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 397 &real_length, 398 &ehcip->ehci_qtd_pool_mem_handle)) { 399 400 goto failure; 401 } 402 403 /* Map the QTD pool into the I/O address space */ 404 result = ddi_dma_addr_bind_handle( 405 ehcip->ehci_qtd_pool_dma_handle, 406 NULL, 407 (caddr_t)ehcip->ehci_qtd_pool_addr, 408 real_length, 409 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 410 DDI_DMA_SLEEP, 411 NULL, 412 &ehcip->ehci_qtd_pool_cookie, 413 &ccount); 414 415 bzero((void *)ehcip->ehci_qtd_pool_addr, 416 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 417 418 /* Process the result */ 419 if (result == DDI_DMA_MAPPED) { 420 /* The cookie count should be 1 */ 421 if (ccount != 1) { 422 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 423 "ehci_allocate_pools: More than 1 cookie"); 424 425 goto failure; 426 } 427 } else { 428 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 429 "ehci_allocate_pools: Result = %d", result); 430 431 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 432 433 goto failure; 434 } 435 436 /* 437 * DMA addresses for QTD pools are bound 438 */ 439 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 440 441 /* Initialize the QTD pool */ 442 for (i = 0; i < ehci_qtd_pool_size; i ++) { 443 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 444 qtd_state, EHCI_QTD_FREE); 445 } 446 447 /* Allocate the QTD pool DMA handle */ 448 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 449 &ehcip->ehci_dma_attr, 450 DDI_DMA_SLEEP, 451 0, 452 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 453 454 goto failure; 455 } 456 457 /* Allocate the memory for the QH pool */ 458 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 459 ehci_qh_pool_size * sizeof (ehci_qh_t), 460 &dev_attr, 461 DDI_DMA_CONSISTENT, 462 DDI_DMA_SLEEP, 463 0, 464 (caddr_t *)&ehcip->ehci_qh_pool_addr, 465 &real_length, 466 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 467 468 goto failure; 469 } 470 471 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 472 NULL, 473 (caddr_t)ehcip->ehci_qh_pool_addr, 474 real_length, 475 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 476 DDI_DMA_SLEEP, 477 NULL, 478 &ehcip->ehci_qh_pool_cookie, 479 &ccount); 480 481 bzero((void *)ehcip->ehci_qh_pool_addr, 482 ehci_qh_pool_size * sizeof (ehci_qh_t)); 483 484 /* Process the result */ 485 if (result == DDI_DMA_MAPPED) { 486 /* The cookie count should be 1 */ 487 if (ccount != 1) { 488 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 489 "ehci_allocate_pools: More than 1 cookie"); 490 491 goto failure; 492 } 493 } else { 494 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 495 496 goto failure; 497 } 498 499 /* 500 * DMA addresses for QH pools are bound 501 */ 502 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 503 504 /* Initialize the QH pool */ 505 for (i = 0; i < ehci_qh_pool_size; i ++) { 506 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 507 } 508 509 /* Byte alignment */ 510 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 511 512 return (DDI_SUCCESS); 513 514 failure: 515 /* Byte alignment */ 516 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 517 518 return (DDI_FAILURE); 519 } 520 521 522 /* 523 * ehci_decode_ddi_dma_addr_bind_handle_result: 524 * 525 * Process the return values of ddi_dma_addr_bind_handle() 526 */ 527 void 528 ehci_decode_ddi_dma_addr_bind_handle_result( 529 ehci_state_t *ehcip, 530 int result) 531 { 532 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 533 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 534 535 switch (result) { 536 case DDI_DMA_PARTIAL_MAP: 537 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 538 "Partial transfers not allowed"); 539 break; 540 case DDI_DMA_INUSE: 541 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 542 "Handle is in use"); 543 break; 544 case DDI_DMA_NORESOURCES: 545 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 546 "No resources"); 547 break; 548 case DDI_DMA_NOMAPPING: 549 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 550 "No mapping"); 551 break; 552 case DDI_DMA_TOOBIG: 553 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 554 "Object is too big"); 555 break; 556 default: 557 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 558 "Unknown dma error"); 559 } 560 } 561 562 563 /* 564 * ehci_map_regs: 565 * 566 * The Host Controller (HC) contains a set of on-chip operational registers 567 * and which should be mapped into a non-cacheable portion of the system 568 * addressable space. 569 */ 570 int 571 ehci_map_regs(ehci_state_t *ehcip) 572 { 573 ddi_device_acc_attr_t attr; 574 uint16_t cmd_reg; 575 uint_t length; 576 577 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 578 579 /* Check to make sure we have memory access */ 580 if (pci_config_setup(ehcip->ehci_dip, 581 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 582 583 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 584 "ehci_map_regs: Config error"); 585 586 return (DDI_FAILURE); 587 } 588 589 /* Make sure Memory Access Enable is set */ 590 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 591 592 if (!(cmd_reg & PCI_COMM_MAE)) { 593 594 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 595 "ehci_map_regs: Memory base address access disabled"); 596 597 return (DDI_FAILURE); 598 } 599 600 /* The host controller will be little endian */ 601 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 602 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 603 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 604 605 /* Map in EHCI Capability registers */ 606 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 607 (caddr_t *)&ehcip->ehci_capsp, 0, 608 sizeof (ehci_caps_t), &attr, 609 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 610 611 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 612 "ehci_map_regs: Map setup error"); 613 614 return (DDI_FAILURE); 615 } 616 617 length = ddi_get8(ehcip->ehci_caps_handle, 618 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 619 620 /* Free the original mapping */ 621 ddi_regs_map_free(&ehcip->ehci_caps_handle); 622 623 /* Re-map in EHCI Capability and Operational registers */ 624 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 625 (caddr_t *)&ehcip->ehci_capsp, 0, 626 length + sizeof (ehci_regs_t), &attr, 627 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 628 629 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 630 "ehci_map_regs: Map setup error"); 631 632 return (DDI_FAILURE); 633 } 634 635 /* Get the pointer to EHCI Operational Register */ 636 ehcip->ehci_regsp = (ehci_regs_t *) 637 ((uintptr_t)ehcip->ehci_capsp + length); 638 639 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 640 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 641 ehcip->ehci_capsp, ehcip->ehci_regsp); 642 643 return (DDI_SUCCESS); 644 } 645 646 647 /* 648 * ehci_register_intrs_and_init_mutex: 649 * 650 * Register interrupts and initialize each mutex and condition variables 651 */ 652 int 653 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 654 { 655 int intr_types; 656 657 #if defined(__x86) 658 uint8_t iline; 659 #endif 660 661 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 662 "ehci_register_intrs_and_init_mutex:"); 663 664 /* 665 * There is a known MSI hardware bug with the EHCI controller 666 * of ULI1575 southbridge. Hence MSI is disabled for this chip. 667 */ 668 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 669 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) { 670 ehcip->ehci_msi_enabled = B_FALSE; 671 } else { 672 /* Set the MSI enable flag from the global EHCI MSI tunable */ 673 ehcip->ehci_msi_enabled = ehci_enable_msi; 674 } 675 676 #if defined(__x86) 677 /* 678 * Make sure that the interrupt pin is connected to the 679 * interrupt controller on x86. Interrupt line 255 means 680 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 681 * If we would return failure when interrupt line equals 255, then 682 * high speed devices will be routed to companion host controllers. 683 * However, it is not necessary to return failure here, and 684 * o/uhci codes don't check the interrupt line either. 685 * But it's good to log a message here for debug purposes. 686 */ 687 iline = pci_config_get8(ehcip->ehci_config_handle, 688 PCI_CONF_ILINE); 689 690 if (iline == 255) { 691 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 692 "ehci_register_intrs_and_init_mutex: " 693 "interrupt line value out of range (%d)", 694 iline); 695 } 696 #endif /* __x86 */ 697 698 /* Get supported interrupt types */ 699 if (ddi_intr_get_supported_types(ehcip->ehci_dip, 700 &intr_types) != DDI_SUCCESS) { 701 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 702 "ehci_register_intrs_and_init_mutex: " 703 "ddi_intr_get_supported_types failed"); 704 705 return (DDI_FAILURE); 706 } 707 708 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 709 "ehci_register_intrs_and_init_mutex: " 710 "supported interrupt types 0x%x", intr_types); 711 712 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) { 713 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI) 714 != DDI_SUCCESS) { 715 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 716 "ehci_register_intrs_and_init_mutex: MSI " 717 "registration failed, trying FIXED interrupt \n"); 718 } else { 719 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 720 "ehci_register_intrs_and_init_mutex: " 721 "Using MSI interrupt type\n"); 722 723 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI; 724 ehcip->ehci_flags |= EHCI_INTR; 725 } 726 } 727 728 if ((!(ehcip->ehci_flags & EHCI_INTR)) && 729 (intr_types & DDI_INTR_TYPE_FIXED)) { 730 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED) 731 != DDI_SUCCESS) { 732 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 733 "ehci_register_intrs_and_init_mutex: " 734 "FIXED interrupt registration failed\n"); 735 736 return (DDI_FAILURE); 737 } 738 739 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 740 "ehci_register_intrs_and_init_mutex: " 741 "Using FIXED interrupt type\n"); 742 743 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED; 744 ehcip->ehci_flags |= EHCI_INTR; 745 } 746 747 /* Create prototype for advance on async schedule */ 748 cv_init(&ehcip->ehci_async_schedule_advance_cv, 749 NULL, CV_DRIVER, NULL); 750 751 return (DDI_SUCCESS); 752 } 753 754 755 /* 756 * ehci_add_intrs: 757 * 758 * Register FIXED or MSI interrupts. 759 */ 760 static int 761 ehci_add_intrs(ehci_state_t *ehcip, 762 int intr_type) 763 { 764 int actual, avail, intr_size, count = 0; 765 int i, flag, ret; 766 767 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 768 "ehci_add_intrs: interrupt type 0x%x", intr_type); 769 770 /* Get number of interrupts */ 771 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count); 772 if ((ret != DDI_SUCCESS) || (count == 0)) { 773 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 774 "ehci_add_intrs: ddi_intr_get_nintrs() failure, " 775 "ret: %d, count: %d", ret, count); 776 777 return (DDI_FAILURE); 778 } 779 780 /* Get number of available interrupts */ 781 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail); 782 if ((ret != DDI_SUCCESS) || (avail == 0)) { 783 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 784 "ehci_add_intrs: ddi_intr_get_navail() failure, " 785 "ret: %d, count: %d", ret, count); 786 787 return (DDI_FAILURE); 788 } 789 790 if (avail < count) { 791 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 792 "ehci_add_intrs: ehci_add_intrs: nintrs () " 793 "returned %d, navail returned %d\n", count, avail); 794 } 795 796 /* Allocate an array of interrupt handles */ 797 intr_size = count * sizeof (ddi_intr_handle_t); 798 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP); 799 800 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 801 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 802 803 /* call ddi_intr_alloc() */ 804 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 805 intr_type, 0, count, &actual, flag); 806 807 if ((ret != DDI_SUCCESS) || (actual == 0)) { 808 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 809 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret); 810 811 kmem_free(ehcip->ehci_htable, intr_size); 812 813 return (DDI_FAILURE); 814 } 815 816 if (actual < count) { 817 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 818 "ehci_add_intrs: Requested: %d, Received: %d\n", 819 count, actual); 820 821 for (i = 0; i < actual; i++) 822 (void) ddi_intr_free(ehcip->ehci_htable[i]); 823 824 kmem_free(ehcip->ehci_htable, intr_size); 825 826 return (DDI_FAILURE); 827 } 828 829 ehcip->ehci_intr_cnt = actual; 830 831 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0], 832 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) { 833 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 834 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret); 835 836 for (i = 0; i < actual; i++) 837 (void) ddi_intr_free(ehcip->ehci_htable[i]); 838 839 kmem_free(ehcip->ehci_htable, intr_size); 840 841 return (DDI_FAILURE); 842 } 843 844 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 845 "ehci_add_intrs: Supported Interrupt priority 0x%x", 846 ehcip->ehci_intr_pri); 847 848 /* Test for high level mutex */ 849 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 850 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 851 "ehci_add_intrs: Hi level interrupt not supported"); 852 853 for (i = 0; i < actual; i++) 854 (void) ddi_intr_free(ehcip->ehci_htable[i]); 855 856 kmem_free(ehcip->ehci_htable, intr_size); 857 858 return (DDI_FAILURE); 859 } 860 861 /* Initialize the mutex */ 862 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 863 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 864 865 /* Call ddi_intr_add_handler() */ 866 for (i = 0; i < actual; i++) { 867 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i], 868 ehci_intr, (caddr_t)ehcip, 869 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 870 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 871 "ehci_add_intrs:ddi_intr_add_handler() " 872 "failed %d", ret); 873 874 for (i = 0; i < actual; i++) 875 (void) ddi_intr_free(ehcip->ehci_htable[i]); 876 877 mutex_destroy(&ehcip->ehci_int_mutex); 878 kmem_free(ehcip->ehci_htable, intr_size); 879 880 return (DDI_FAILURE); 881 } 882 } 883 884 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0], 885 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) { 886 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 887 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret); 888 889 for (i = 0; i < actual; i++) { 890 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 891 (void) ddi_intr_free(ehcip->ehci_htable[i]); 892 } 893 894 mutex_destroy(&ehcip->ehci_int_mutex); 895 kmem_free(ehcip->ehci_htable, intr_size); 896 897 return (DDI_FAILURE); 898 } 899 900 /* Enable all interrupts */ 901 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 902 /* Call ddi_intr_block_enable() for MSI interrupts */ 903 (void) ddi_intr_block_enable(ehcip->ehci_htable, 904 ehcip->ehci_intr_cnt); 905 } else { 906 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 907 for (i = 0; i < ehcip->ehci_intr_cnt; i++) 908 (void) ddi_intr_enable(ehcip->ehci_htable[i]); 909 } 910 911 return (DDI_SUCCESS); 912 } 913 914 915 /* 916 * ehci_init_hardware 917 * 918 * take control from BIOS, reset EHCI host controller, and check version, etc. 919 */ 920 int 921 ehci_init_hardware(ehci_state_t *ehcip) 922 { 923 int revision; 924 uint16_t cmd_reg; 925 int abort_on_BIOS_take_over_failure; 926 927 /* Take control from the BIOS */ 928 if (ehci_take_control(ehcip) != USB_SUCCESS) { 929 930 /* read .conf file properties */ 931 abort_on_BIOS_take_over_failure = 932 ddi_prop_get_int(DDI_DEV_T_ANY, 933 ehcip->ehci_dip, DDI_PROP_DONTPASS, 934 "abort-on-BIOS-take-over-failure", 0); 935 936 if (abort_on_BIOS_take_over_failure) { 937 938 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 939 "Unable to take control from BIOS."); 940 941 return (DDI_FAILURE); 942 } 943 944 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 945 "Unable to take control from BIOS. Failure is ignored."); 946 } 947 948 /* set Memory Master Enable */ 949 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 950 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 951 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 952 953 /* Reset the EHCI host controller */ 954 Set_OpReg(ehci_command, 955 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 956 957 /* Wait 10ms for reset to complete */ 958 drv_usecwait(EHCI_RESET_TIMEWAIT); 959 960 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 961 962 /* Verify the version number */ 963 revision = Get_16Cap(ehci_version); 964 965 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 966 "ehci_init_hardware: Revision 0x%x", revision); 967 968 /* 969 * EHCI driver supports EHCI host controllers compliant to 970 * 0.95 and higher revisions of EHCI specifications. 971 */ 972 if (revision < EHCI_REVISION_0_95) { 973 974 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 975 "Revision 0x%x is not supported", revision); 976 977 return (DDI_FAILURE); 978 } 979 980 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 981 982 /* Initialize the Frame list base address area */ 983 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 984 985 return (DDI_FAILURE); 986 } 987 988 /* 989 * For performance reasons, do not insert anything into the 990 * asynchronous list or activate the asynch list schedule until 991 * there is a valid QH. 992 */ 993 ehcip->ehci_head_of_async_sched_list = NULL; 994 995 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 996 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 997 /* 998 * The driver is unable to reliably stop the asynch 999 * list schedule on VIA VT6202 controllers, so we 1000 * always keep a dummy QH on the list. 1001 */ 1002 ehci_qh_t *dummy_async_qh = 1003 ehci_alloc_qh(ehcip, NULL, NULL); 1004 1005 Set_QH(dummy_async_qh->qh_link_ptr, 1006 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 1007 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 1008 1009 /* Set this QH to be the "head" of the circular list */ 1010 Set_QH(dummy_async_qh->qh_ctrl, 1011 Get_QH(dummy_async_qh->qh_ctrl) | 1012 EHCI_QH_CTRL_RECLAIM_HEAD); 1013 1014 Set_QH(dummy_async_qh->qh_next_qtd, 1015 EHCI_QH_NEXT_QTD_PTR_VALID); 1016 Set_QH(dummy_async_qh->qh_alt_next_qtd, 1017 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1018 1019 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 1020 ehcip->ehci_open_async_count++; 1021 } 1022 } 1023 1024 return (DDI_SUCCESS); 1025 } 1026 1027 1028 /* 1029 * ehci_init_workaround 1030 * 1031 * some workarounds during initializing ehci 1032 */ 1033 int 1034 ehci_init_workaround(ehci_state_t *ehcip) 1035 { 1036 /* 1037 * Acer Labs Inc. M5273 EHCI controller does not send 1038 * interrupts unless the Root hub ports are routed to the EHCI 1039 * host controller; so route the ports now, before we test for 1040 * the presence of SOFs interrupts. 1041 */ 1042 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1043 /* Route all Root hub ports to EHCI host controller */ 1044 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1045 } 1046 1047 /* 1048 * VIA chips have some issues and may not work reliably. 1049 * Revisions >= 0x80 are part of a southbridge and appear 1050 * to be reliable with the workaround. 1051 * For revisions < 0x80, if we were bound using class 1052 * complain, else proceed. This will allow the user to 1053 * bind ehci specifically to this chip and not have the 1054 * warnings 1055 */ 1056 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 1057 1058 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 1059 1060 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1061 "ehci_init_workaround: Applying VIA workarounds " 1062 "for the 6212 chip."); 1063 1064 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1065 "pciclass,0c0320") == 0) { 1066 1067 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1068 "Due to recently discovered incompatibilities"); 1069 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1070 "with this USB controller, USB2.x transfer"); 1071 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1072 "support has been disabled. This device will"); 1073 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1074 "continue to function as a USB1.x controller."); 1075 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1076 "If you are interested in enabling USB2.x"); 1077 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1078 "support please, refer to the ehci(7D) man page."); 1079 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1080 "Please also refer to www.sun.com/io for"); 1081 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1082 "Solaris Ready products and to"); 1083 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1084 "www.sun.com/bigadmin/hcl for additional"); 1085 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1086 "compatible USB products."); 1087 1088 return (DDI_FAILURE); 1089 1090 } else if (ehci_vt62x2_workaround) { 1091 1092 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1093 "Applying VIA workarounds"); 1094 } 1095 } 1096 1097 return (DDI_SUCCESS); 1098 } 1099 1100 1101 /* 1102 * ehci_init_check_status 1103 * 1104 * Check if EHCI host controller is running 1105 */ 1106 int 1107 ehci_init_check_status(ehci_state_t *ehcip) 1108 { 1109 clock_t sof_time_wait; 1110 1111 /* 1112 * Get the number of clock ticks to wait. 1113 * This is based on the maximum time it takes for a frame list rollover 1114 * and maximum time wait for SOFs to begin. 1115 */ 1116 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1117 EHCI_SOF_TIMEWAIT); 1118 1119 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1120 ehcip->ehci_flags |= EHCI_CV_INTR; 1121 1122 /* We need to add a delay to allow the chip time to start running */ 1123 (void) cv_timedwait(&ehcip->ehci_async_schedule_advance_cv, 1124 &ehcip->ehci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1125 1126 /* 1127 * Check EHCI host controller is running, otherwise return failure. 1128 */ 1129 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1130 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1131 1132 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1133 "No SOF interrupts have been received, this USB EHCI host" 1134 "controller is unusable"); 1135 1136 /* 1137 * Route all Root hub ports to Classic host 1138 * controller, in case this is an unusable ALI M5273 1139 * EHCI controller. 1140 */ 1141 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1142 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1143 } 1144 1145 return (DDI_FAILURE); 1146 } 1147 1148 return (DDI_SUCCESS); 1149 } 1150 1151 1152 /* 1153 * ehci_init_ctlr: 1154 * 1155 * Initialize the Host Controller (HC). 1156 */ 1157 int 1158 ehci_init_ctlr(ehci_state_t *ehcip, 1159 int init_type) 1160 { 1161 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 1162 1163 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1164 1165 if (ehci_init_hardware(ehcip) != DDI_SUCCESS) { 1166 1167 return (DDI_FAILURE); 1168 } 1169 } 1170 1171 /* 1172 * Check for Asynchronous schedule park capability feature. If this 1173 * feature is supported, then, program ehci command register with 1174 * appropriate values.. 1175 */ 1176 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 1177 1178 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1179 "ehci_init_ctlr: Async park mode is supported"); 1180 1181 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1182 (EHCI_CMD_ASYNC_PARK_ENABLE | 1183 EHCI_CMD_ASYNC_PARK_COUNT_3))); 1184 } 1185 1186 /* 1187 * Check for programmable periodic frame list feature. If this 1188 * feature is supported, then, program ehci command register with 1189 * 1024 frame list value. 1190 */ 1191 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 1192 1193 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1194 "ehci_init_ctlr: Variable programmable periodic " 1195 "frame list is supported"); 1196 1197 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1198 EHCI_CMD_FRAME_1024_SIZE)); 1199 } 1200 1201 /* 1202 * Currently EHCI driver doesn't support 64 bit addressing. 1203 * 1204 * If we are using 64 bit addressing capability, then, program 1205 * ehci_ctrl_segment register with 4 Gigabyte segment where all 1206 * of the interface data structures are allocated. 1207 */ 1208 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 1209 1210 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1211 "ehci_init_ctlr: EHCI driver doesn't support " 1212 "64 bit addressing"); 1213 } 1214 1215 /* 64 bit addressing is not support */ 1216 Set_OpReg(ehci_ctrl_segment, 0x00000000); 1217 1218 /* Turn on/off the schedulers */ 1219 ehci_toggle_scheduler(ehcip); 1220 1221 /* 1222 * Set the Periodic Frame List Base Address register with the 1223 * starting physical address of the Periodic Frame List. 1224 */ 1225 Set_OpReg(ehci_periodic_list_base, 1226 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 1227 EHCI_PERIODIC_LIST_BASE)); 1228 1229 /* 1230 * Set ehci_interrupt to enable all interrupts except Root 1231 * Hub Status change interrupt. 1232 */ 1233 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 1234 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 1235 EHCI_INTR_USB); 1236 1237 /* 1238 * Set the desired interrupt threshold and turn on EHCI host controller. 1239 */ 1240 Set_OpReg(ehci_command, 1241 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 1242 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 1243 1244 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 1245 1246 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1247 1248 if (ehci_init_workaround(ehcip) != DDI_SUCCESS) { 1249 1250 return (DDI_FAILURE); 1251 } 1252 1253 if (ehci_init_check_status(ehcip) != DDI_SUCCESS) { 1254 1255 return (DDI_FAILURE); 1256 } 1257 1258 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1259 "ehci_init_ctlr: SOF's have started"); 1260 } 1261 1262 /* Route all Root hub ports to EHCI host controller */ 1263 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1264 1265 /* Set host controller soft state to operational */ 1266 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1267 1268 return (DDI_SUCCESS); 1269 } 1270 1271 /* 1272 * ehci_take_control: 1273 * 1274 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1275 * x86 machines, because sparc doesn't have a BIOS. 1276 * On x86 machine, the take control process includes 1277 * o get the base address of the extended capability list 1278 * o find out the capability for handoff synchronization in the list. 1279 * o check if BIOS has owned the host controller. 1280 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1281 * o wait for a constant time and check if BIOS has relinquished control. 1282 */ 1283 /* ARGSUSED */ 1284 static int 1285 ehci_take_control(ehci_state_t *ehcip) 1286 { 1287 #if defined(__x86) 1288 uint32_t extended_cap; 1289 uint32_t extended_cap_offset; 1290 uint32_t extended_cap_id; 1291 uint_t retry; 1292 1293 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1294 "ehci_take_control:"); 1295 1296 /* 1297 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1298 * register. 1299 */ 1300 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1301 EHCI_HCC_EECP_SHIFT; 1302 1303 /* 1304 * According EHCI Spec 2.2.4, if the extended capability offset is 1305 * less than 40h then its not valid. This means we don't need to 1306 * worry about BIOS handoff. 1307 */ 1308 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1309 1310 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1311 "ehci_take_control: Hardware doesn't support legacy."); 1312 1313 goto success; 1314 } 1315 1316 /* 1317 * According EHCI Spec 2.1.7, A zero offset indicates the 1318 * end of the extended capability list. 1319 */ 1320 while (extended_cap_offset) { 1321 1322 /* Get the extended capability value. */ 1323 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1324 extended_cap_offset); 1325 1326 /* Get the capability ID */ 1327 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1328 EHCI_EX_CAP_ID_SHIFT; 1329 1330 /* Check if the card support legacy */ 1331 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1332 break; 1333 } 1334 1335 /* Get the offset of the next capability */ 1336 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1337 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1338 } 1339 1340 /* 1341 * Unable to find legacy support in hardware's extended capability list. 1342 * This means we don't need to worry about BIOS handoff. 1343 */ 1344 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1345 1346 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1347 "ehci_take_control: Hardware doesn't support legacy"); 1348 1349 goto success; 1350 } 1351 1352 /* Check if BIOS has owned it. */ 1353 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1354 1355 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1356 "ehci_take_control: BIOS does not own EHCI"); 1357 1358 goto success; 1359 } 1360 1361 /* 1362 * According EHCI Spec 5.1, The OS driver initiates an ownership 1363 * request by setting the OS Owned semaphore to a one. The OS 1364 * waits for the BIOS Owned bit to go to a zero before attempting 1365 * to use the EHCI controller. The time that OS must wait for BIOS 1366 * to respond to the request for ownership is beyond the scope of 1367 * this specification. 1368 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1369 * for BIOS to release the ownership. 1370 */ 1371 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1372 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1373 extended_cap); 1374 1375 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1376 1377 /* wait a special interval */ 1378 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1379 1380 /* Check to see if the BIOS has released the ownership */ 1381 extended_cap = pci_config_get32( 1382 ehcip->ehci_config_handle, extended_cap_offset); 1383 1384 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1385 1386 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1387 ehcip->ehci_log_hdl, 1388 "ehci_take_control: BIOS has released " 1389 "the ownership. retry = %d", retry); 1390 1391 goto success; 1392 } 1393 1394 } 1395 1396 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1397 "ehci_take_control: take control from BIOS failed."); 1398 1399 return (USB_FAILURE); 1400 1401 success: 1402 1403 #endif /* __x86 */ 1404 return (USB_SUCCESS); 1405 } 1406 1407 1408 /* 1409 * ehci_init_periodic_frame_list_table : 1410 * 1411 * Allocate the system memory and initialize Host Controller 1412 * Periodic Frame List table area. The starting of the Periodic 1413 * Frame List Table area must be 4096 byte aligned. 1414 */ 1415 static int 1416 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1417 { 1418 ddi_device_acc_attr_t dev_attr; 1419 size_t real_length; 1420 uint_t ccount; 1421 int result; 1422 1423 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1424 1425 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1426 "ehci_init_periodic_frame_lst_table:"); 1427 1428 /* The host controller will be little endian */ 1429 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1430 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1431 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1432 1433 /* Force the required 4K restrictive alignment */ 1434 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1435 1436 /* Create space for the Periodic Frame List */ 1437 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1438 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1439 1440 goto failure; 1441 } 1442 1443 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1444 sizeof (ehci_periodic_frame_list_t), 1445 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1446 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1447 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1448 1449 goto failure; 1450 } 1451 1452 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1453 "ehci_init_periodic_frame_lst_table: " 1454 "Real length %lu", real_length); 1455 1456 /* Map the whole Periodic Frame List into the I/O address space */ 1457 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1458 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1459 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1460 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1461 1462 if (result == DDI_DMA_MAPPED) { 1463 /* The cookie count should be 1 */ 1464 if (ccount != 1) { 1465 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1466 "ehci_init_periodic_frame_lst_table: " 1467 "More than 1 cookie"); 1468 1469 goto failure; 1470 } 1471 } else { 1472 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1473 1474 goto failure; 1475 } 1476 1477 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1478 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1479 (void *)ehcip->ehci_periodic_frame_list_tablep, 1480 ehcip->ehci_pflt_cookie.dmac_address); 1481 1482 /* 1483 * DMA addresses for Periodic Frame List are bound. 1484 */ 1485 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1486 1487 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1488 1489 /* Initialize the Periodic Frame List */ 1490 ehci_build_interrupt_lattice(ehcip); 1491 1492 /* Reset Byte Alignment to Default */ 1493 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1494 1495 return (DDI_SUCCESS); 1496 failure: 1497 /* Byte alignment */ 1498 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1499 1500 return (DDI_FAILURE); 1501 } 1502 1503 1504 /* 1505 * ehci_build_interrupt_lattice: 1506 * 1507 * Construct the interrupt lattice tree using static Endpoint Descriptors 1508 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1509 * lists and the Host Controller (HC) processes one interrupt QH list in 1510 * every frame. The Host Controller traverses the periodic schedule by 1511 * constructing an array offset reference from the Periodic List Base Address 1512 * register and bits 12 to 3 of Frame Index register. It fetches the element 1513 * and begins traversing the graph of linked schedule data structures. 1514 */ 1515 static void 1516 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1517 { 1518 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1519 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1520 ehci_periodic_frame_list_t *periodic_frame_list = 1521 ehcip->ehci_periodic_frame_list_tablep; 1522 ushort_t *temp, num_of_nodes; 1523 uintptr_t addr; 1524 int i, j, k; 1525 1526 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1527 "ehci_build_interrupt_lattice:"); 1528 1529 /* 1530 * Reserve the first 63 Endpoint Descriptor (QH) structures 1531 * in the pool as static endpoints & these are required for 1532 * constructing interrupt lattice tree. 1533 */ 1534 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1535 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1536 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1537 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1538 Set_QH(list_array[i].qh_alt_next_qtd, 1539 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1540 } 1541 1542 /* 1543 * Make sure that last Endpoint on the periodic frame list terminates 1544 * periodic schedule. 1545 */ 1546 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1547 1548 /* Build the interrupt lattice tree */ 1549 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1550 /* 1551 * The next pointer in the host controller endpoint 1552 * descriptor must contain an iommu address. Calculate 1553 * the offset into the cpu address and add this to the 1554 * starting iommu address. 1555 */ 1556 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1557 1558 Set_QH(list_array[2*i + 1].qh_link_ptr, 1559 addr | EHCI_QH_LINK_REF_QH); 1560 Set_QH(list_array[2*i + 2].qh_link_ptr, 1561 addr | EHCI_QH_LINK_REF_QH); 1562 } 1563 1564 /* Build the tree bottom */ 1565 temp = (unsigned short *) 1566 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1567 1568 num_of_nodes = 1; 1569 1570 /* 1571 * Initialize the values which are used for setting up head pointers 1572 * for the 32ms scheduling lists which starts from the Periodic Frame 1573 * List. 1574 */ 1575 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1576 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1577 ehci_index[j++] = temp[k]; 1578 ehci_index[j] = temp[k] + ehci_pow_2(i); 1579 } 1580 1581 num_of_nodes *= 2; 1582 for (k = 0; k < num_of_nodes; k++) 1583 temp[k] = ehci_index[k]; 1584 } 1585 1586 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1587 1588 /* 1589 * Initialize the interrupt list in the Periodic Frame List Table 1590 * so that it points to the bottom of the tree. 1591 */ 1592 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1593 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1594 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1595 1596 ASSERT(addr); 1597 1598 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1599 Set_PFLT(periodic_frame_list-> 1600 ehci_periodic_frame_list_table[ehci_index[j++]], 1601 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1602 } 1603 } 1604 } 1605 1606 1607 /* 1608 * ehci_alloc_hcdi_ops: 1609 * 1610 * The HCDI interfaces or entry points are the software interfaces used by 1611 * the Universal Serial Bus Driver (USBA) to access the services of the 1612 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1613 * about all available HCDI interfaces or entry points. 1614 */ 1615 usba_hcdi_ops_t * 1616 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1617 { 1618 usba_hcdi_ops_t *usba_hcdi_ops; 1619 1620 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1621 "ehci_alloc_hcdi_ops:"); 1622 1623 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1624 1625 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1626 1627 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1628 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1629 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1630 1631 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1632 1633 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1634 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1635 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1636 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1637 1638 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1639 ehci_hcdi_bulk_transfer_size; 1640 1641 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1642 ehci_hcdi_pipe_stop_intr_polling; 1643 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1644 ehci_hcdi_pipe_stop_isoc_polling; 1645 1646 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1647 ehci_hcdi_get_current_frame_number; 1648 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1649 ehci_hcdi_get_max_isoc_pkts; 1650 1651 usba_hcdi_ops->usba_hcdi_console_input_init = 1652 ehci_hcdi_polled_input_init; 1653 usba_hcdi_ops->usba_hcdi_console_input_enter = 1654 ehci_hcdi_polled_input_enter; 1655 usba_hcdi_ops->usba_hcdi_console_read = 1656 ehci_hcdi_polled_read; 1657 usba_hcdi_ops->usba_hcdi_console_input_exit = 1658 ehci_hcdi_polled_input_exit; 1659 usba_hcdi_ops->usba_hcdi_console_input_fini = 1660 ehci_hcdi_polled_input_fini; 1661 return (usba_hcdi_ops); 1662 } 1663 1664 1665 /* 1666 * Host Controller Driver (HCD) deinitialization functions 1667 */ 1668 1669 /* 1670 * ehci_cleanup: 1671 * 1672 * Cleanup on attach failure or detach 1673 */ 1674 int 1675 ehci_cleanup(ehci_state_t *ehcip) 1676 { 1677 ehci_trans_wrapper_t *tw; 1678 ehci_pipe_private_t *pp; 1679 ehci_qtd_t *qtd; 1680 int i, ctrl, rval; 1681 int flags = ehcip->ehci_flags; 1682 1683 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1684 1685 if (flags & EHCI_RHREG) { 1686 /* Unload the root hub driver */ 1687 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1688 1689 return (DDI_FAILURE); 1690 } 1691 } 1692 1693 if (flags & EHCI_USBAREG) { 1694 /* Unregister this HCD instance with USBA */ 1695 usba_hcdi_unregister(ehcip->ehci_dip); 1696 } 1697 1698 if (flags & EHCI_INTR) { 1699 1700 mutex_enter(&ehcip->ehci_int_mutex); 1701 1702 /* Disable all EHCI QH list processing */ 1703 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1704 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1705 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1706 1707 /* Disable all EHCI interrupts */ 1708 Set_OpReg(ehci_interrupt, 0); 1709 1710 /* wait for the next SOF */ 1711 (void) ehci_wait_for_sof(ehcip); 1712 1713 /* Route all Root hub ports to Classic host controller */ 1714 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1715 1716 /* Stop the EHCI host controller */ 1717 Set_OpReg(ehci_command, 1718 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1719 1720 /* Wait for sometime */ 1721 drv_usecwait(EHCI_TIMEWAIT); 1722 1723 mutex_exit(&ehcip->ehci_int_mutex); 1724 1725 ehci_rem_intrs(ehcip); 1726 } 1727 1728 /* Unmap the EHCI registers */ 1729 if (ehcip->ehci_caps_handle) { 1730 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1731 } 1732 1733 if (ehcip->ehci_config_handle) { 1734 pci_config_teardown(&ehcip->ehci_config_handle); 1735 } 1736 1737 /* Free all the buffers */ 1738 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1739 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1740 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1741 ctrl = Get_QTD(ehcip-> 1742 ehci_qtd_pool_addr[i].qtd_state); 1743 1744 if ((ctrl != EHCI_QTD_FREE) && 1745 (ctrl != EHCI_QTD_DUMMY) && 1746 (qtd->qtd_trans_wrapper)) { 1747 1748 mutex_enter(&ehcip->ehci_int_mutex); 1749 1750 tw = (ehci_trans_wrapper_t *) 1751 EHCI_LOOKUP_ID((uint32_t) 1752 Get_QTD(qtd->qtd_trans_wrapper)); 1753 1754 /* Obtain the pipe private structure */ 1755 pp = tw->tw_pipe_private; 1756 1757 /* Stop the the transfer timer */ 1758 ehci_stop_xfer_timer(ehcip, tw, 1759 EHCI_REMOVE_XFER_ALWAYS); 1760 1761 ehci_deallocate_tw(ehcip, pp, tw); 1762 1763 mutex_exit(&ehcip->ehci_int_mutex); 1764 } 1765 } 1766 1767 /* 1768 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1769 * the handle for QTD pools. 1770 */ 1771 if ((ehcip->ehci_dma_addr_bind_flag & 1772 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1773 1774 rval = ddi_dma_unbind_handle( 1775 ehcip->ehci_qtd_pool_dma_handle); 1776 1777 ASSERT(rval == DDI_SUCCESS); 1778 } 1779 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1780 } 1781 1782 /* Free the QTD pool */ 1783 if (ehcip->ehci_qtd_pool_dma_handle) { 1784 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1785 } 1786 1787 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1788 /* 1789 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1790 * the handle for QH pools. 1791 */ 1792 if ((ehcip->ehci_dma_addr_bind_flag & 1793 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1794 1795 rval = ddi_dma_unbind_handle( 1796 ehcip->ehci_qh_pool_dma_handle); 1797 1798 ASSERT(rval == DDI_SUCCESS); 1799 } 1800 1801 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1802 } 1803 1804 /* Free the QH pool */ 1805 if (ehcip->ehci_qh_pool_dma_handle) { 1806 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1807 } 1808 1809 /* Free the Periodic frame list table (PFLT) area */ 1810 if (ehcip->ehci_periodic_frame_list_tablep && 1811 ehcip->ehci_pflt_mem_handle) { 1812 /* 1813 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1814 * the handle for PFLT. 1815 */ 1816 if ((ehcip->ehci_dma_addr_bind_flag & 1817 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1818 1819 rval = ddi_dma_unbind_handle( 1820 ehcip->ehci_pflt_dma_handle); 1821 1822 ASSERT(rval == DDI_SUCCESS); 1823 } 1824 1825 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1826 } 1827 1828 (void) ehci_isoc_cleanup(ehcip); 1829 1830 if (ehcip->ehci_pflt_dma_handle) { 1831 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1832 } 1833 1834 if (flags & EHCI_INTR) { 1835 /* Destroy the mutex */ 1836 mutex_destroy(&ehcip->ehci_int_mutex); 1837 1838 /* Destroy the async schedule advance condition variable */ 1839 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1840 } 1841 1842 /* clean up kstat structs */ 1843 ehci_destroy_stats(ehcip); 1844 1845 /* Free ehci hcdi ops */ 1846 if (ehcip->ehci_hcdi_ops) { 1847 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1848 } 1849 1850 if (flags & EHCI_ZALLOC) { 1851 1852 usb_free_log_hdl(ehcip->ehci_log_hdl); 1853 1854 /* Remove all properties that might have been created */ 1855 ddi_prop_remove_all(ehcip->ehci_dip); 1856 1857 /* Free the soft state */ 1858 ddi_soft_state_free(ehci_statep, 1859 ddi_get_instance(ehcip->ehci_dip)); 1860 } 1861 1862 return (DDI_SUCCESS); 1863 } 1864 1865 1866 /* 1867 * ehci_rem_intrs: 1868 * 1869 * Unregister FIXED or MSI interrupts 1870 */ 1871 static void 1872 ehci_rem_intrs(ehci_state_t *ehcip) 1873 { 1874 int i; 1875 1876 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1877 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type); 1878 1879 /* Disable all interrupts */ 1880 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1881 (void) ddi_intr_block_disable(ehcip->ehci_htable, 1882 ehcip->ehci_intr_cnt); 1883 } else { 1884 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1885 (void) ddi_intr_disable(ehcip->ehci_htable[i]); 1886 } 1887 } 1888 1889 /* Call ddi_intr_remove_handler() */ 1890 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1891 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 1892 (void) ddi_intr_free(ehcip->ehci_htable[i]); 1893 } 1894 1895 kmem_free(ehcip->ehci_htable, 1896 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t)); 1897 } 1898 1899 1900 /* 1901 * ehci_cpr_suspend 1902 */ 1903 int 1904 ehci_cpr_suspend(ehci_state_t *ehcip) 1905 { 1906 int i; 1907 1908 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1909 "ehci_cpr_suspend:"); 1910 1911 /* Call into the root hub and suspend it */ 1912 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 1913 1914 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1915 "ehci_cpr_suspend: root hub fails to suspend"); 1916 1917 return (DDI_FAILURE); 1918 } 1919 1920 /* Only root hub's intr pipe should be open at this time */ 1921 mutex_enter(&ehcip->ehci_int_mutex); 1922 1923 ASSERT(ehcip->ehci_open_pipe_count == 0); 1924 1925 /* Just wait till all resources are reclaimed */ 1926 i = 0; 1927 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 1928 ehci_handle_endpoint_reclaimation(ehcip); 1929 (void) ehci_wait_for_sof(ehcip); 1930 } 1931 ASSERT(ehcip->ehci_reclaim_list == NULL); 1932 1933 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1934 "ehci_cpr_suspend: Disable HC QH list processing"); 1935 1936 /* Disable all EHCI QH list processing */ 1937 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1938 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1939 1940 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1941 "ehci_cpr_suspend: Disable HC interrupts"); 1942 1943 /* Disable all EHCI interrupts */ 1944 Set_OpReg(ehci_interrupt, 0); 1945 1946 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1947 "ehci_cpr_suspend: Wait for the next SOF"); 1948 1949 /* Wait for the next SOF */ 1950 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 1951 1952 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1953 "ehci_cpr_suspend: ehci host controller suspend failed"); 1954 1955 mutex_exit(&ehcip->ehci_int_mutex); 1956 return (DDI_FAILURE); 1957 } 1958 1959 /* 1960 * Stop the ehci host controller 1961 * if usb keyboard is not connected. 1962 */ 1963 if (ehcip->ehci_polled_kbd_count == 0) { 1964 Set_OpReg(ehci_command, 1965 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1966 } 1967 1968 /* Set host controller soft state to suspend */ 1969 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 1970 1971 mutex_exit(&ehcip->ehci_int_mutex); 1972 1973 return (DDI_SUCCESS); 1974 } 1975 1976 1977 /* 1978 * ehci_cpr_resume 1979 */ 1980 int 1981 ehci_cpr_resume(ehci_state_t *ehcip) 1982 { 1983 mutex_enter(&ehcip->ehci_int_mutex); 1984 1985 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1986 "ehci_cpr_resume: Restart the controller"); 1987 1988 /* Cleanup ehci specific information across cpr */ 1989 ehci_cpr_cleanup(ehcip); 1990 1991 /* Restart the controller */ 1992 if (ehci_init_ctlr(ehcip, EHCI_NORMAL_INITIALIZATION) != DDI_SUCCESS) { 1993 1994 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1995 "ehci_cpr_resume: ehci host controller resume failed "); 1996 1997 mutex_exit(&ehcip->ehci_int_mutex); 1998 1999 return (DDI_FAILURE); 2000 } 2001 2002 mutex_exit(&ehcip->ehci_int_mutex); 2003 2004 /* Now resume the root hub */ 2005 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 2006 2007 return (DDI_FAILURE); 2008 } 2009 2010 return (DDI_SUCCESS); 2011 } 2012 2013 2014 /* 2015 * Bandwidth Allocation functions 2016 */ 2017 2018 /* 2019 * ehci_allocate_bandwidth: 2020 * 2021 * Figure out whether or not this interval may be supported. Return the index 2022 * into the lattice if it can be supported. Return allocation failure if it 2023 * can not be supported. 2024 */ 2025 int 2026 ehci_allocate_bandwidth( 2027 ehci_state_t *ehcip, 2028 usba_pipe_handle_data_t *ph, 2029 uint_t *pnode, 2030 uchar_t *smask, 2031 uchar_t *cmask) 2032 { 2033 int error = USB_SUCCESS; 2034 2035 /* This routine is protected by the ehci_int_mutex */ 2036 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2037 2038 /* Reset the pnode to the last checked pnode */ 2039 *pnode = 0; 2040 2041 /* Allocate high speed bandwidth */ 2042 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 2043 ph, pnode, smask, cmask)) != USB_SUCCESS) { 2044 2045 return (error); 2046 } 2047 2048 /* 2049 * For low/full speed usb devices, allocate classic TT bandwidth 2050 * in additional to high speed bandwidth. 2051 */ 2052 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2053 2054 /* Allocate classic TT bandwidth */ 2055 if ((error = ehci_allocate_classic_tt_bandwidth( 2056 ehcip, ph, *pnode)) != USB_SUCCESS) { 2057 2058 /* Deallocate high speed bandwidth */ 2059 ehci_deallocate_high_speed_bandwidth( 2060 ehcip, ph, *pnode, *smask, *cmask); 2061 } 2062 } 2063 2064 return (error); 2065 } 2066 2067 2068 /* 2069 * ehci_allocate_high_speed_bandwidth: 2070 * 2071 * Allocate high speed bandwidth for the low/full/high speed interrupt and 2072 * isochronous endpoints. 2073 */ 2074 static int 2075 ehci_allocate_high_speed_bandwidth( 2076 ehci_state_t *ehcip, 2077 usba_pipe_handle_data_t *ph, 2078 uint_t *pnode, 2079 uchar_t *smask, 2080 uchar_t *cmask) 2081 { 2082 uint_t sbandwidth, cbandwidth; 2083 int interval; 2084 usb_ep_descr_t *endpoint = &ph->p_ep; 2085 usba_device_t *child_ud; 2086 usb_port_status_t port_status; 2087 int error; 2088 2089 /* This routine is protected by the ehci_int_mutex */ 2090 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2091 2092 /* Get child's usba device structure */ 2093 child_ud = ph->p_usba_device; 2094 2095 mutex_enter(&child_ud->usb_mutex); 2096 2097 /* Get the current usb device's port status */ 2098 port_status = ph->p_usba_device->usb_port_status; 2099 2100 mutex_exit(&child_ud->usb_mutex); 2101 2102 /* 2103 * Calculate the length in bytes of a transaction on this 2104 * periodic endpoint. Return failure if maximum packet is 2105 * zero. 2106 */ 2107 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2108 port_status, &sbandwidth, &cbandwidth); 2109 if (error != USB_SUCCESS) { 2110 2111 return (error); 2112 } 2113 2114 /* 2115 * Adjust polling interval to be a power of 2. 2116 * If this interval can't be supported, return 2117 * allocation failure. 2118 */ 2119 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2120 if (interval == USB_FAILURE) { 2121 2122 return (USB_FAILURE); 2123 } 2124 2125 if (port_status == USBA_HIGH_SPEED_DEV) { 2126 /* Allocate bandwidth for high speed devices, except ITD */ 2127 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 2128 endpoint, sbandwidth, interval); 2129 *cmask = 0x00; 2130 2131 } else { 2132 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2133 USB_EP_ATTR_INTR) { 2134 2135 /* Allocate bandwidth for low speed interrupt */ 2136 error = ehci_find_bestfit_ls_intr_mask(ehcip, 2137 smask, cmask, pnode, sbandwidth, cbandwidth, 2138 interval); 2139 } else { 2140 if ((endpoint->bEndpointAddress & 2141 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2142 2143 /* Allocate bandwidth for sitd in */ 2144 error = ehci_find_bestfit_sitd_in_mask(ehcip, 2145 smask, cmask, pnode, sbandwidth, cbandwidth, 2146 interval); 2147 } else { 2148 2149 /* Allocate bandwidth for sitd out */ 2150 error = ehci_find_bestfit_sitd_out_mask(ehcip, 2151 smask, pnode, sbandwidth, interval); 2152 *cmask = 0x00; 2153 } 2154 } 2155 } 2156 2157 if (error != USB_SUCCESS) { 2158 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2159 "ehci_allocate_high_speed_bandwidth: Reached maximum " 2160 "bandwidth value and cannot allocate bandwidth for a " 2161 "given high-speed periodic endpoint"); 2162 2163 return (USB_NO_BANDWIDTH); 2164 } 2165 2166 return (error); 2167 } 2168 2169 2170 /* 2171 * ehci_allocate_classic_tt_speed_bandwidth: 2172 * 2173 * Allocate classic TT bandwidth for the low/full speed interrupt and 2174 * isochronous endpoints. 2175 */ 2176 static int 2177 ehci_allocate_classic_tt_bandwidth( 2178 ehci_state_t *ehcip, 2179 usba_pipe_handle_data_t *ph, 2180 uint_t pnode) 2181 { 2182 uint_t bandwidth, min; 2183 uint_t height, leftmost, list; 2184 usb_ep_descr_t *endpoint = &ph->p_ep; 2185 usba_device_t *child_ud, *parent_ud; 2186 usb_port_status_t port_status; 2187 int i, interval; 2188 2189 /* This routine is protected by the ehci_int_mutex */ 2190 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2191 2192 /* Get child's usba device structure */ 2193 child_ud = ph->p_usba_device; 2194 2195 mutex_enter(&child_ud->usb_mutex); 2196 2197 /* Get the current usb device's port status */ 2198 port_status = child_ud->usb_port_status; 2199 2200 /* Get the parent high speed hub's usba device structure */ 2201 parent_ud = child_ud->usb_hs_hub_usba_dev; 2202 2203 mutex_exit(&child_ud->usb_mutex); 2204 2205 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2206 "ehci_allocate_classic_tt_bandwidth: " 2207 "child_ud 0x%p parent_ud 0x%p", child_ud, parent_ud); 2208 2209 /* 2210 * Calculate the length in bytes of a transaction on this 2211 * periodic endpoint. Return failure if maximum packet is 2212 * zero. 2213 */ 2214 if (ehci_compute_classic_bandwidth(endpoint, 2215 port_status, &bandwidth) != USB_SUCCESS) { 2216 2217 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2218 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2219 "with zero endpoint maximum packet size is not supported"); 2220 2221 return (USB_NOT_SUPPORTED); 2222 } 2223 2224 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2225 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2226 2227 mutex_enter(&parent_ud->usb_mutex); 2228 2229 /* 2230 * If the length in bytes plus the allocated bandwidth exceeds 2231 * the maximum, return bandwidth allocation failure. 2232 */ 2233 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2234 FS_PERIODIC_BANDWIDTH) { 2235 2236 mutex_exit(&parent_ud->usb_mutex); 2237 2238 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2239 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2240 "bandwidth value and cannot allocate bandwidth for a " 2241 "given low/full speed periodic endpoint"); 2242 2243 return (USB_NO_BANDWIDTH); 2244 } 2245 2246 mutex_exit(&parent_ud->usb_mutex); 2247 2248 /* Adjust polling interval to be a power of 2 */ 2249 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2250 2251 /* Find the height in the tree */ 2252 height = ehci_lattice_height(interval); 2253 2254 /* Find the leftmost leaf in the subtree specified by the node. */ 2255 leftmost = ehci_leftmost_leaf(pnode, height); 2256 2257 mutex_enter(&parent_ud->usb_mutex); 2258 2259 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2260 list = ehci_index[leftmost + i]; 2261 2262 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2263 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2264 2265 mutex_exit(&parent_ud->usb_mutex); 2266 2267 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2268 "ehci_allocate_classic_tt_bandwidth: Reached " 2269 "maximum bandwidth value and cannot allocate " 2270 "bandwidth for low/full periodic endpoint"); 2271 2272 return (USB_NO_BANDWIDTH); 2273 } 2274 } 2275 2276 /* 2277 * All the leaves for this node must be updated with the bandwidth. 2278 */ 2279 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2280 list = ehci_index[leftmost + i]; 2281 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2282 } 2283 2284 /* Find the leaf with the smallest allocated bandwidth */ 2285 min = parent_ud->usb_hs_hub_bandwidth[0]; 2286 2287 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2288 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2289 min = parent_ud->usb_hs_hub_bandwidth[i]; 2290 } 2291 } 2292 2293 /* Save the minimum for later use */ 2294 parent_ud->usb_hs_hub_min_bandwidth = min; 2295 2296 mutex_exit(&parent_ud->usb_mutex); 2297 2298 return (USB_SUCCESS); 2299 } 2300 2301 2302 /* 2303 * ehci_deallocate_bandwidth: 2304 * 2305 * Deallocate bandwidth for the given node in the lattice and the length 2306 * of transfer. 2307 */ 2308 void 2309 ehci_deallocate_bandwidth( 2310 ehci_state_t *ehcip, 2311 usba_pipe_handle_data_t *ph, 2312 uint_t pnode, 2313 uchar_t smask, 2314 uchar_t cmask) 2315 { 2316 /* This routine is protected by the ehci_int_mutex */ 2317 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2318 2319 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2320 2321 /* 2322 * For low/full speed usb devices, deallocate classic TT bandwidth 2323 * in additional to high speed bandwidth. 2324 */ 2325 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2326 2327 /* Deallocate classic TT bandwidth */ 2328 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2329 } 2330 } 2331 2332 2333 /* 2334 * ehci_deallocate_high_speed_bandwidth: 2335 * 2336 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2337 */ 2338 static void 2339 ehci_deallocate_high_speed_bandwidth( 2340 ehci_state_t *ehcip, 2341 usba_pipe_handle_data_t *ph, 2342 uint_t pnode, 2343 uchar_t smask, 2344 uchar_t cmask) 2345 { 2346 uint_t height, leftmost; 2347 uint_t list_count; 2348 uint_t sbandwidth, cbandwidth; 2349 int interval; 2350 usb_ep_descr_t *endpoint = &ph->p_ep; 2351 usba_device_t *child_ud; 2352 usb_port_status_t port_status; 2353 2354 /* This routine is protected by the ehci_int_mutex */ 2355 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2356 2357 /* Get child's usba device structure */ 2358 child_ud = ph->p_usba_device; 2359 2360 mutex_enter(&child_ud->usb_mutex); 2361 2362 /* Get the current usb device's port status */ 2363 port_status = ph->p_usba_device->usb_port_status; 2364 2365 mutex_exit(&child_ud->usb_mutex); 2366 2367 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2368 port_status, &sbandwidth, &cbandwidth); 2369 2370 /* Adjust polling interval to be a power of 2 */ 2371 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2372 2373 /* Find the height in the tree */ 2374 height = ehci_lattice_height(interval); 2375 2376 /* 2377 * Find the leftmost leaf in the subtree specified by the node 2378 */ 2379 leftmost = ehci_leftmost_leaf(pnode, height); 2380 2381 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2382 2383 /* Delete the bandwidth from the appropriate lists */ 2384 if (port_status == USBA_HIGH_SPEED_DEV) { 2385 2386 ehci_update_bw_availability(ehcip, -sbandwidth, 2387 leftmost, list_count, smask); 2388 } else { 2389 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2390 USB_EP_ATTR_INTR) { 2391 2392 ehci_update_bw_availability(ehcip, -sbandwidth, 2393 leftmost, list_count, smask); 2394 ehci_update_bw_availability(ehcip, -cbandwidth, 2395 leftmost, list_count, cmask); 2396 } else { 2397 if ((endpoint->bEndpointAddress & 2398 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2399 2400 ehci_update_bw_availability(ehcip, -sbandwidth, 2401 leftmost, list_count, smask); 2402 ehci_update_bw_availability(ehcip, 2403 -MAX_UFRAME_SITD_XFER, leftmost, 2404 list_count, cmask); 2405 } else { 2406 2407 ehci_update_bw_availability(ehcip, 2408 -MAX_UFRAME_SITD_XFER, leftmost, 2409 list_count, smask); 2410 } 2411 } 2412 } 2413 } 2414 2415 /* 2416 * ehci_deallocate_classic_tt_bandwidth: 2417 * 2418 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2419 */ 2420 static void 2421 ehci_deallocate_classic_tt_bandwidth( 2422 ehci_state_t *ehcip, 2423 usba_pipe_handle_data_t *ph, 2424 uint_t pnode) 2425 { 2426 uint_t bandwidth, height, leftmost, list, min; 2427 int i, interval; 2428 usb_ep_descr_t *endpoint = &ph->p_ep; 2429 usba_device_t *child_ud, *parent_ud; 2430 usb_port_status_t port_status; 2431 2432 /* This routine is protected by the ehci_int_mutex */ 2433 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2434 2435 /* Get child's usba device structure */ 2436 child_ud = ph->p_usba_device; 2437 2438 mutex_enter(&child_ud->usb_mutex); 2439 2440 /* Get the current usb device's port status */ 2441 port_status = child_ud->usb_port_status; 2442 2443 /* Get the parent high speed hub's usba device structure */ 2444 parent_ud = child_ud->usb_hs_hub_usba_dev; 2445 2446 mutex_exit(&child_ud->usb_mutex); 2447 2448 /* Obtain the bandwidth */ 2449 (void) ehci_compute_classic_bandwidth(endpoint, 2450 port_status, &bandwidth); 2451 2452 /* Adjust polling interval to be a power of 2 */ 2453 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2454 2455 /* Find the height in the tree */ 2456 height = ehci_lattice_height(interval); 2457 2458 /* Find the leftmost leaf in the subtree specified by the node */ 2459 leftmost = ehci_leftmost_leaf(pnode, height); 2460 2461 mutex_enter(&parent_ud->usb_mutex); 2462 2463 /* Delete the bandwidth from the appropriate lists */ 2464 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2465 list = ehci_index[leftmost + i]; 2466 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2467 } 2468 2469 /* Find the leaf with the smallest allocated bandwidth */ 2470 min = parent_ud->usb_hs_hub_bandwidth[0]; 2471 2472 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2473 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2474 min = parent_ud->usb_hs_hub_bandwidth[i]; 2475 } 2476 } 2477 2478 /* Save the minimum for later use */ 2479 parent_ud->usb_hs_hub_min_bandwidth = min; 2480 2481 mutex_exit(&parent_ud->usb_mutex); 2482 } 2483 2484 2485 /* 2486 * ehci_compute_high_speed_bandwidth: 2487 * 2488 * Given a periodic endpoint (interrupt or isochronous) determine the total 2489 * bandwidth for one transaction. The EHCI host controller traverses the 2490 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2491 * services an endpoint, only a single transaction attempt is made. The HC 2492 * moves to the next Endpoint Descriptor after the first transaction attempt 2493 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2494 * Transfer Descriptor is inserted into the lattice, we will only count the 2495 * number of bytes for one transaction. 2496 * 2497 * The following are the formulas used for calculating bandwidth in terms 2498 * bytes and it is for the single USB high speed transaction. The protocol 2499 * overheads will be different for each of type of USB transfer & all these 2500 * formulas & protocol overheads are derived from the 5.11.3 section of the 2501 * USB 2.0 Specification. 2502 * 2503 * High-Speed: 2504 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2505 * 2506 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2507 * 2508 * Protocol overhead + Split transaction overhead + 2509 * ((MaxPktSz * 7)/6) + Host_Delay; 2510 */ 2511 /* ARGSUSED */ 2512 static int 2513 ehci_compute_high_speed_bandwidth( 2514 ehci_state_t *ehcip, 2515 usb_ep_descr_t *endpoint, 2516 usb_port_status_t port_status, 2517 uint_t *sbandwidth, 2518 uint_t *cbandwidth) 2519 { 2520 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2521 2522 /* Return failure if endpoint maximum packet is zero */ 2523 if (maxpacketsize == 0) { 2524 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2525 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2526 "with zero endpoint maximum packet size is not supported"); 2527 2528 return (USB_NOT_SUPPORTED); 2529 } 2530 2531 /* Add bit-stuffing overhead */ 2532 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2533 2534 /* Add Host Controller specific delay to required bandwidth */ 2535 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2536 2537 /* Add xfer specific protocol overheads */ 2538 if ((endpoint->bmAttributes & 2539 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2540 /* High speed interrupt transaction */ 2541 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2542 } else { 2543 /* Isochronous transaction */ 2544 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2545 } 2546 2547 /* 2548 * For low/full speed devices, add split transaction specific 2549 * overheads. 2550 */ 2551 if (port_status != USBA_HIGH_SPEED_DEV) { 2552 /* 2553 * Add start and complete split transaction 2554 * tokens overheads. 2555 */ 2556 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2557 *sbandwidth += START_SPLIT_OVERHEAD; 2558 2559 /* Add data overhead depending on data direction */ 2560 if ((endpoint->bEndpointAddress & 2561 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2562 *cbandwidth += maxpacketsize; 2563 } else { 2564 if ((endpoint->bmAttributes & 2565 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2566 /* There is no compete splits for out */ 2567 *cbandwidth = 0; 2568 } 2569 *sbandwidth += maxpacketsize; 2570 } 2571 } else { 2572 uint_t xactions; 2573 2574 /* Get the max transactions per microframe */ 2575 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2576 USB_EP_MAX_XACTS_SHIFT) + 1; 2577 2578 /* High speed transaction */ 2579 *sbandwidth += maxpacketsize; 2580 2581 /* Calculate bandwidth per micro-frame */ 2582 *sbandwidth *= xactions; 2583 2584 *cbandwidth = 0; 2585 } 2586 2587 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2588 "ehci_allocate_high_speed_bandwidth: " 2589 "Start split bandwidth %d Complete split bandwidth %d", 2590 *sbandwidth, *cbandwidth); 2591 2592 return (USB_SUCCESS); 2593 } 2594 2595 2596 /* 2597 * ehci_compute_classic_bandwidth: 2598 * 2599 * Given a periodic endpoint (interrupt or isochronous) determine the total 2600 * bandwidth for one transaction. The EHCI host controller traverses the 2601 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2602 * services an endpoint, only a single transaction attempt is made. The HC 2603 * moves to the next Endpoint Descriptor after the first transaction attempt 2604 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2605 * Transfer Descriptor is inserted into the lattice, we will only count the 2606 * number of bytes for one transaction. 2607 * 2608 * The following are the formulas used for calculating bandwidth in terms 2609 * bytes and it is for the single USB high speed transaction. The protocol 2610 * overheads will be different for each of type of USB transfer & all these 2611 * formulas & protocol overheads are derived from the 5.11.3 section of the 2612 * USB 2.0 Specification. 2613 * 2614 * Low-Speed: 2615 * Protocol overhead + Hub LS overhead + 2616 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2617 * 2618 * Full-Speed: 2619 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2620 */ 2621 /* ARGSUSED */ 2622 static int 2623 ehci_compute_classic_bandwidth( 2624 usb_ep_descr_t *endpoint, 2625 usb_port_status_t port_status, 2626 uint_t *bandwidth) 2627 { 2628 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2629 2630 /* 2631 * If endpoint maximum packet is zero, then return immediately. 2632 */ 2633 if (maxpacketsize == 0) { 2634 2635 return (USB_NOT_SUPPORTED); 2636 } 2637 2638 /* Add TT delay to required bandwidth */ 2639 *bandwidth = TT_DELAY; 2640 2641 /* Add bit-stuffing overhead */ 2642 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2643 2644 switch (port_status) { 2645 case USBA_LOW_SPEED_DEV: 2646 /* Low speed interrupt transaction */ 2647 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2648 HUB_LOW_SPEED_PROTO_OVERHEAD + 2649 (LOW_SPEED_CLOCK * maxpacketsize)); 2650 break; 2651 case USBA_FULL_SPEED_DEV: 2652 /* Full speed transaction */ 2653 *bandwidth += maxpacketsize; 2654 2655 /* Add xfer specific protocol overheads */ 2656 if ((endpoint->bmAttributes & 2657 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2658 /* Full speed interrupt transaction */ 2659 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2660 } else { 2661 /* Isochronous and input transaction */ 2662 if ((endpoint->bEndpointAddress & 2663 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2664 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2665 } else { 2666 /* Isochronous and output transaction */ 2667 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2668 } 2669 } 2670 break; 2671 } 2672 2673 return (USB_SUCCESS); 2674 } 2675 2676 2677 /* 2678 * ehci_adjust_polling_interval: 2679 * 2680 * Adjust bandwidth according usb device speed. 2681 */ 2682 /* ARGSUSED */ 2683 int 2684 ehci_adjust_polling_interval( 2685 ehci_state_t *ehcip, 2686 usb_ep_descr_t *endpoint, 2687 usb_port_status_t port_status) 2688 { 2689 uint_t interval; 2690 int i = 0; 2691 2692 /* Get the polling interval */ 2693 interval = endpoint->bInterval; 2694 2695 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2696 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2697 2698 /* 2699 * According USB 2.0 Specifications, a high-speed endpoint's 2700 * polling intervals are specified interms of 125us or micro 2701 * frame, where as full/low endpoint's polling intervals are 2702 * specified in milliseconds. 2703 * 2704 * A high speed interrupt/isochronous endpoints can specify 2705 * desired polling interval between 1 to 16 micro-frames, 2706 * where as full/low endpoints can specify between 1 to 255 2707 * milliseconds. 2708 */ 2709 switch (port_status) { 2710 case USBA_LOW_SPEED_DEV: 2711 /* 2712 * Low speed endpoints are limited to specifying 2713 * only 8ms to 255ms in this driver. If a device 2714 * reports a polling interval that is less than 8ms, 2715 * it will use 8 ms instead. 2716 */ 2717 if (interval < LS_MIN_POLL_INTERVAL) { 2718 2719 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2720 "Low speed endpoint's poll interval of %d ms " 2721 "is below threshold. Rounding up to %d ms", 2722 interval, LS_MIN_POLL_INTERVAL); 2723 2724 interval = LS_MIN_POLL_INTERVAL; 2725 } 2726 2727 /* 2728 * Return an error if the polling interval is greater 2729 * than 255ms. 2730 */ 2731 if (interval > LS_MAX_POLL_INTERVAL) { 2732 2733 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2734 "Low speed endpoint's poll interval is " 2735 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2736 2737 return (USB_FAILURE); 2738 } 2739 break; 2740 2741 case USBA_FULL_SPEED_DEV: 2742 /* 2743 * Return an error if the polling interval is less 2744 * than 1ms and greater than 255ms. 2745 */ 2746 if ((interval < FS_MIN_POLL_INTERVAL) && 2747 (interval > FS_MAX_POLL_INTERVAL)) { 2748 2749 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2750 "Full speed endpoint's poll interval must " 2751 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2752 FS_MAX_POLL_INTERVAL); 2753 2754 return (USB_FAILURE); 2755 } 2756 break; 2757 case USBA_HIGH_SPEED_DEV: 2758 /* 2759 * Return an error if the polling interval is less 1 2760 * and greater than 16. Convert this value to 125us 2761 * units using 2^(bInterval -1). refer usb 2.0 spec 2762 * page 51 for details. 2763 */ 2764 if ((interval < HS_MIN_POLL_INTERVAL) && 2765 (interval > HS_MAX_POLL_INTERVAL)) { 2766 2767 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2768 "High speed endpoint's poll interval " 2769 "must be between %d and %d units", 2770 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2771 2772 return (USB_FAILURE); 2773 } 2774 2775 /* Adjust high speed device polling interval */ 2776 interval = 2777 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2778 2779 break; 2780 } 2781 2782 /* 2783 * If polling interval is greater than 32ms, 2784 * adjust polling interval equal to 32ms. 2785 */ 2786 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2787 interval = EHCI_NUM_INTR_QH_LISTS; 2788 } 2789 2790 /* 2791 * Find the nearest power of 2 that's less 2792 * than interval. 2793 */ 2794 while ((ehci_pow_2(i)) <= interval) { 2795 i++; 2796 } 2797 2798 return (ehci_pow_2((i - 1))); 2799 } 2800 2801 2802 /* 2803 * ehci_adjust_high_speed_polling_interval: 2804 */ 2805 /* ARGSUSED */ 2806 static int 2807 ehci_adjust_high_speed_polling_interval( 2808 ehci_state_t *ehcip, 2809 usb_ep_descr_t *endpoint) 2810 { 2811 uint_t interval; 2812 2813 /* Get the polling interval */ 2814 interval = ehci_pow_2(endpoint->bInterval - 1); 2815 2816 /* 2817 * Convert polling interval from micro seconds 2818 * to milli seconds. 2819 */ 2820 if (interval <= EHCI_MAX_UFRAMES) { 2821 interval = 1; 2822 } else { 2823 interval = interval/EHCI_MAX_UFRAMES; 2824 } 2825 2826 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2827 "ehci_adjust_high_speed_polling_interval: " 2828 "High speed adjusted interval 0x%x", interval); 2829 2830 return (interval); 2831 } 2832 2833 2834 /* 2835 * ehci_lattice_height: 2836 * 2837 * Given the requested bandwidth, find the height in the tree at which the 2838 * nodes for this bandwidth fall. The height is measured as the number of 2839 * nodes from the leaf to the level specified by bandwidth The root of the 2840 * tree is at height TREE_HEIGHT. 2841 */ 2842 static uint_t 2843 ehci_lattice_height(uint_t interval) 2844 { 2845 return (TREE_HEIGHT - (ehci_log_2(interval))); 2846 } 2847 2848 2849 /* 2850 * ehci_lattice_parent: 2851 * 2852 * Given a node in the lattice, find the index of the parent node 2853 */ 2854 static uint_t 2855 ehci_lattice_parent(uint_t node) 2856 { 2857 if ((node % 2) == 0) { 2858 2859 return ((node/2) - 1); 2860 } else { 2861 2862 return ((node + 1)/2 - 1); 2863 } 2864 } 2865 2866 2867 /* 2868 * ehci_find_periodic_node: 2869 * 2870 * Based on the "real" array leaf node and interval, get the periodic node. 2871 */ 2872 static uint_t 2873 ehci_find_periodic_node(uint_t leaf, int interval) { 2874 uint_t lattice_leaf; 2875 uint_t height = ehci_lattice_height(interval); 2876 uint_t pnode; 2877 int i; 2878 2879 /* Get the leaf number in the lattice */ 2880 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2881 2882 /* Get the node in the lattice based on the height and leaf */ 2883 pnode = lattice_leaf; 2884 for (i = 0; i < height; i++) { 2885 pnode = ehci_lattice_parent(pnode); 2886 } 2887 2888 return (pnode); 2889 } 2890 2891 2892 /* 2893 * ehci_leftmost_leaf: 2894 * 2895 * Find the leftmost leaf in the subtree specified by the node. Height refers 2896 * to number of nodes from the bottom of the tree to the node, including the 2897 * node. 2898 * 2899 * The formula for a zero based tree is: 2900 * 2^H * Node + 2^H - 1 2901 * The leaf of the tree is an array, convert the number for the array. 2902 * Subtract the size of nodes not in the array 2903 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 2904 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 2905 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 2906 * 0 2907 * 1 2 2908 * 0 1 2 3 2909 */ 2910 static uint_t 2911 ehci_leftmost_leaf( 2912 uint_t node, 2913 uint_t height) 2914 { 2915 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 2916 } 2917 2918 2919 /* 2920 * ehci_pow_2: 2921 * 2922 * Compute 2 to the power 2923 */ 2924 static uint_t 2925 ehci_pow_2(uint_t x) 2926 { 2927 if (x == 0) { 2928 2929 return (1); 2930 } else { 2931 2932 return (2 << (x - 1)); 2933 } 2934 } 2935 2936 2937 /* 2938 * ehci_log_2: 2939 * 2940 * Compute log base 2 of x 2941 */ 2942 static uint_t 2943 ehci_log_2(uint_t x) 2944 { 2945 int i = 0; 2946 2947 while (x != 1) { 2948 x = x >> 1; 2949 i++; 2950 } 2951 2952 return (i); 2953 } 2954 2955 2956 /* 2957 * ehci_find_bestfit_hs_mask: 2958 * 2959 * Find the smask and cmask in the bandwidth allocation, and update the 2960 * bandwidth allocation. 2961 */ 2962 static int 2963 ehci_find_bestfit_hs_mask( 2964 ehci_state_t *ehcip, 2965 uchar_t *smask, 2966 uint_t *pnode, 2967 usb_ep_descr_t *endpoint, 2968 uint_t bandwidth, 2969 int interval) 2970 { 2971 int i; 2972 uint_t elements, index; 2973 int array_leaf, best_array_leaf; 2974 uint_t node_bandwidth, best_node_bandwidth; 2975 uint_t leaf_count; 2976 uchar_t bw_mask; 2977 uchar_t best_smask; 2978 2979 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2980 "ehci_find_bestfit_hs_mask: "); 2981 2982 /* Get all the valid smasks */ 2983 switch (ehci_pow_2(endpoint->bInterval - 1)) { 2984 case EHCI_INTR_1US_POLL: 2985 index = EHCI_1US_MASK_INDEX; 2986 elements = EHCI_INTR_1US_POLL; 2987 break; 2988 case EHCI_INTR_2US_POLL: 2989 index = EHCI_2US_MASK_INDEX; 2990 elements = EHCI_INTR_2US_POLL; 2991 break; 2992 case EHCI_INTR_4US_POLL: 2993 index = EHCI_4US_MASK_INDEX; 2994 elements = EHCI_INTR_4US_POLL; 2995 break; 2996 case EHCI_INTR_XUS_POLL: 2997 default: 2998 index = EHCI_XUS_MASK_INDEX; 2999 elements = EHCI_INTR_XUS_POLL; 3000 break; 3001 } 3002 3003 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3004 3005 /* 3006 * Because of the way the leaves are setup, we will automatically 3007 * hit the leftmost leaf of every possible node with this interval. 3008 */ 3009 best_smask = 0x00; 3010 best_node_bandwidth = 0; 3011 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3012 /* Find the bandwidth mask */ 3013 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 3014 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 3015 3016 /* 3017 * If this node cannot support our requirements skip to the 3018 * next leaf. 3019 */ 3020 if (bw_mask == 0x00) { 3021 continue; 3022 } 3023 3024 /* 3025 * Now make sure our bandwidth requirements can be 3026 * satisfied with one of smasks in this node. 3027 */ 3028 *smask = 0x00; 3029 for (i = index; i < (index + elements); i++) { 3030 /* Check the start split mask value */ 3031 if (ehci_start_split_mask[index] & bw_mask) { 3032 *smask = ehci_start_split_mask[index]; 3033 break; 3034 } 3035 } 3036 3037 /* 3038 * If an appropriate smask is found save the information if: 3039 * o best_smask has not been found yet. 3040 * - or - 3041 * o This is the node with the least amount of bandwidth 3042 */ 3043 if ((*smask != 0x00) && 3044 ((best_smask == 0x00) || 3045 (best_node_bandwidth > node_bandwidth))) { 3046 3047 best_node_bandwidth = node_bandwidth; 3048 best_array_leaf = array_leaf; 3049 best_smask = *smask; 3050 } 3051 } 3052 3053 /* 3054 * If we find node that can handle the bandwidth populate the 3055 * appropriate variables and return success. 3056 */ 3057 if (best_smask) { 3058 *smask = best_smask; 3059 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3060 interval); 3061 ehci_update_bw_availability(ehcip, bandwidth, 3062 ehci_index[best_array_leaf], leaf_count, best_smask); 3063 3064 return (USB_SUCCESS); 3065 } 3066 3067 return (USB_FAILURE); 3068 } 3069 3070 3071 /* 3072 * ehci_find_bestfit_ls_intr_mask: 3073 * 3074 * Find the smask and cmask in the bandwidth allocation. 3075 */ 3076 static int 3077 ehci_find_bestfit_ls_intr_mask( 3078 ehci_state_t *ehcip, 3079 uchar_t *smask, 3080 uchar_t *cmask, 3081 uint_t *pnode, 3082 uint_t sbandwidth, 3083 uint_t cbandwidth, 3084 int interval) 3085 { 3086 int i; 3087 uint_t elements, index; 3088 int array_leaf, best_array_leaf; 3089 uint_t node_sbandwidth, node_cbandwidth; 3090 uint_t best_node_bandwidth; 3091 uint_t leaf_count; 3092 uchar_t bw_smask, bw_cmask; 3093 uchar_t best_smask, best_cmask; 3094 3095 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3096 "ehci_find_bestfit_ls_intr_mask: "); 3097 3098 /* For low and full speed devices */ 3099 index = EHCI_XUS_MASK_INDEX; 3100 elements = EHCI_INTR_4MS_POLL; 3101 3102 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3103 3104 /* 3105 * Because of the way the leaves are setup, we will automatically 3106 * hit the leftmost leaf of every possible node with this interval. 3107 */ 3108 best_smask = 0x00; 3109 best_node_bandwidth = 0; 3110 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3111 /* Find the bandwidth mask */ 3112 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3113 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3114 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3115 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 3116 3117 /* 3118 * If this node cannot support our requirements skip to the 3119 * next leaf. 3120 */ 3121 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3122 continue; 3123 } 3124 3125 /* 3126 * Now make sure our bandwidth requirements can be 3127 * satisfied with one of smasks in this node. 3128 */ 3129 *smask = 0x00; 3130 *cmask = 0x00; 3131 for (i = index; i < (index + elements); i++) { 3132 /* Check the start split mask value */ 3133 if ((ehci_start_split_mask[index] & bw_smask) && 3134 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 3135 *smask = ehci_start_split_mask[index]; 3136 *cmask = ehci_intr_complete_split_mask[index]; 3137 break; 3138 } 3139 } 3140 3141 /* 3142 * If an appropriate smask is found save the information if: 3143 * o best_smask has not been found yet. 3144 * - or - 3145 * o This is the node with the least amount of bandwidth 3146 */ 3147 if ((*smask != 0x00) && 3148 ((best_smask == 0x00) || 3149 (best_node_bandwidth > 3150 (node_sbandwidth + node_cbandwidth)))) { 3151 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3152 best_array_leaf = array_leaf; 3153 best_smask = *smask; 3154 best_cmask = *cmask; 3155 } 3156 } 3157 3158 /* 3159 * If we find node that can handle the bandwidth populate the 3160 * appropriate variables and return success. 3161 */ 3162 if (best_smask) { 3163 *smask = best_smask; 3164 *cmask = best_cmask; 3165 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3166 interval); 3167 ehci_update_bw_availability(ehcip, sbandwidth, 3168 ehci_index[best_array_leaf], leaf_count, best_smask); 3169 ehci_update_bw_availability(ehcip, cbandwidth, 3170 ehci_index[best_array_leaf], leaf_count, best_cmask); 3171 3172 return (USB_SUCCESS); 3173 } 3174 3175 return (USB_FAILURE); 3176 } 3177 3178 3179 /* 3180 * ehci_find_bestfit_sitd_in_mask: 3181 * 3182 * Find the smask and cmask in the bandwidth allocation. 3183 */ 3184 static int 3185 ehci_find_bestfit_sitd_in_mask( 3186 ehci_state_t *ehcip, 3187 uchar_t *smask, 3188 uchar_t *cmask, 3189 uint_t *pnode, 3190 uint_t sbandwidth, 3191 uint_t cbandwidth, 3192 int interval) 3193 { 3194 int i, uFrames, found; 3195 int array_leaf, best_array_leaf; 3196 uint_t node_sbandwidth, node_cbandwidth; 3197 uint_t best_node_bandwidth; 3198 uint_t leaf_count; 3199 uchar_t bw_smask, bw_cmask; 3200 uchar_t best_smask, best_cmask; 3201 3202 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3203 "ehci_find_bestfit_sitd_in_mask: "); 3204 3205 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3206 3207 /* 3208 * Because of the way the leaves are setup, we will automatically 3209 * hit the leftmost leaf of every possible node with this interval. 3210 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3211 */ 3212 /* 3213 * Need to add an additional 2 uFrames, if the "L"ast 3214 * complete split is before uFrame 6. See section 3215 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3216 * the "Back Ptr" which means we support on IN of 3217 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3218 */ 3219 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3220 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3221 uFrames++; 3222 } 3223 if (uFrames > 6) { 3224 3225 return (USB_FAILURE); 3226 } 3227 *smask = 0x1; 3228 *cmask = 0x00; 3229 for (i = 0; i < uFrames; i++) { 3230 *cmask = *cmask << 1; 3231 *cmask |= 0x1; 3232 } 3233 /* cmask must start 2 frames after the smask */ 3234 *cmask = *cmask << 2; 3235 3236 found = 0; 3237 best_smask = 0x00; 3238 best_node_bandwidth = 0; 3239 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3240 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3241 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3242 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3243 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3244 &bw_cmask); 3245 3246 /* 3247 * If this node cannot support our requirements skip to the 3248 * next leaf. 3249 */ 3250 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3251 continue; 3252 } 3253 3254 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3255 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3256 found = 1; 3257 break; 3258 } 3259 *smask = *smask << 1; 3260 *cmask = *cmask << 1; 3261 } 3262 3263 /* 3264 * If an appropriate smask is found save the information if: 3265 * o best_smask has not been found yet. 3266 * - or - 3267 * o This is the node with the least amount of bandwidth 3268 */ 3269 if (found && 3270 ((best_smask == 0x00) || 3271 (best_node_bandwidth > 3272 (node_sbandwidth + node_cbandwidth)))) { 3273 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3274 best_array_leaf = array_leaf; 3275 best_smask = *smask; 3276 best_cmask = *cmask; 3277 } 3278 } 3279 3280 /* 3281 * If we find node that can handle the bandwidth populate the 3282 * appropriate variables and return success. 3283 */ 3284 if (best_smask) { 3285 *smask = best_smask; 3286 *cmask = best_cmask; 3287 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3288 interval); 3289 ehci_update_bw_availability(ehcip, sbandwidth, 3290 ehci_index[best_array_leaf], leaf_count, best_smask); 3291 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3292 ehci_index[best_array_leaf], leaf_count, best_cmask); 3293 3294 return (USB_SUCCESS); 3295 } 3296 3297 return (USB_FAILURE); 3298 } 3299 3300 3301 /* 3302 * ehci_find_bestfit_sitd_out_mask: 3303 * 3304 * Find the smask in the bandwidth allocation. 3305 */ 3306 static int 3307 ehci_find_bestfit_sitd_out_mask( 3308 ehci_state_t *ehcip, 3309 uchar_t *smask, 3310 uint_t *pnode, 3311 uint_t sbandwidth, 3312 int interval) 3313 { 3314 int i, uFrames, found; 3315 int array_leaf, best_array_leaf; 3316 uint_t node_sbandwidth; 3317 uint_t best_node_bandwidth; 3318 uint_t leaf_count; 3319 uchar_t bw_smask; 3320 uchar_t best_smask; 3321 3322 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3323 "ehci_find_bestfit_sitd_out_mask: "); 3324 3325 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3326 3327 /* 3328 * Because of the way the leaves are setup, we will automatically 3329 * hit the leftmost leaf of every possible node with this interval. 3330 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3331 */ 3332 *smask = 0x00; 3333 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3334 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3335 uFrames++; 3336 } 3337 for (i = 0; i < uFrames; i++) { 3338 *smask = *smask << 1; 3339 *smask |= 0x1; 3340 } 3341 3342 found = 0; 3343 best_smask = 0x00; 3344 best_node_bandwidth = 0; 3345 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3346 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3347 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3348 &bw_smask); 3349 3350 /* 3351 * If this node cannot support our requirements skip to the 3352 * next leaf. 3353 */ 3354 if (bw_smask == 0x00) { 3355 continue; 3356 } 3357 3358 /* You cannot have a start split on the 8th uFrame */ 3359 for (i = 0; (*smask & 0x80) == 0; i++) { 3360 if (*smask & bw_smask) { 3361 found = 1; 3362 break; 3363 } 3364 *smask = *smask << 1; 3365 } 3366 3367 /* 3368 * If an appropriate smask is found save the information if: 3369 * o best_smask has not been found yet. 3370 * - or - 3371 * o This is the node with the least amount of bandwidth 3372 */ 3373 if (found && 3374 ((best_smask == 0x00) || 3375 (best_node_bandwidth > node_sbandwidth))) { 3376 best_node_bandwidth = node_sbandwidth; 3377 best_array_leaf = array_leaf; 3378 best_smask = *smask; 3379 } 3380 } 3381 3382 /* 3383 * If we find node that can handle the bandwidth populate the 3384 * appropriate variables and return success. 3385 */ 3386 if (best_smask) { 3387 *smask = best_smask; 3388 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3389 interval); 3390 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3391 ehci_index[best_array_leaf], leaf_count, best_smask); 3392 3393 return (USB_SUCCESS); 3394 } 3395 3396 return (USB_FAILURE); 3397 } 3398 3399 3400 /* 3401 * ehci_calculate_bw_availability_mask: 3402 * 3403 * Returns the "total bandwidth used" in this node. 3404 * Populates bw_mask with the uFrames that can support the bandwidth. 3405 * 3406 * If all the Frames cannot support this bandwidth, then bw_mask 3407 * will return 0x00 and the "total bandwidth used" will be invalid. 3408 */ 3409 static uint_t 3410 ehci_calculate_bw_availability_mask( 3411 ehci_state_t *ehcip, 3412 uint_t bandwidth, 3413 int leaf, 3414 int leaf_count, 3415 uchar_t *bw_mask) 3416 { 3417 int i, j; 3418 uchar_t bw_uframe; 3419 int uframe_total; 3420 ehci_frame_bandwidth_t *fbp; 3421 uint_t total_bandwidth = 0; 3422 3423 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3424 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3425 leaf, leaf_count); 3426 3427 /* Start by saying all uFrames are available */ 3428 *bw_mask = 0xFF; 3429 3430 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3431 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3432 3433 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3434 3435 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3436 /* 3437 * If the uFrame in bw_mask is available check to see if 3438 * it can support the additional bandwidth. 3439 */ 3440 bw_uframe = (*bw_mask & (0x1 << j)); 3441 uframe_total = 3442 fbp->ehci_micro_frame_bandwidth[j] + 3443 bandwidth; 3444 if ((bw_uframe) && 3445 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3446 *bw_mask = *bw_mask & ~bw_uframe; 3447 } 3448 } 3449 } 3450 3451 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3452 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3453 *bw_mask); 3454 3455 return (total_bandwidth); 3456 } 3457 3458 3459 /* 3460 * ehci_update_bw_availability: 3461 * 3462 * The leftmost leaf needs to be in terms of array position and 3463 * not the actual lattice position. 3464 */ 3465 static void 3466 ehci_update_bw_availability( 3467 ehci_state_t *ehcip, 3468 int bandwidth, 3469 int leftmost_leaf, 3470 int leaf_count, 3471 uchar_t mask) 3472 { 3473 int i, j; 3474 ehci_frame_bandwidth_t *fbp; 3475 int uFrame_bandwidth[8]; 3476 3477 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3478 "ehci_update_bw_availability: " 3479 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3480 leftmost_leaf, leaf_count, bandwidth, mask); 3481 3482 ASSERT(leftmost_leaf < 32); 3483 ASSERT(leftmost_leaf >= 0); 3484 3485 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3486 if (mask & 0x1) { 3487 uFrame_bandwidth[j] = bandwidth; 3488 } else { 3489 uFrame_bandwidth[j] = 0; 3490 } 3491 3492 mask = mask >> 1; 3493 } 3494 3495 /* Updated all the effected leafs with the bandwidth */ 3496 for (i = 0; i < leaf_count; i++) { 3497 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3498 3499 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3500 fbp->ehci_micro_frame_bandwidth[j] += 3501 uFrame_bandwidth[j]; 3502 fbp->ehci_allocated_frame_bandwidth += 3503 uFrame_bandwidth[j]; 3504 } 3505 } 3506 } 3507 3508 /* 3509 * Miscellaneous functions 3510 */ 3511 3512 /* 3513 * ehci_obtain_state: 3514 * 3515 * NOTE: This function is also called from POLLED MODE. 3516 */ 3517 ehci_state_t * 3518 ehci_obtain_state(dev_info_t *dip) 3519 { 3520 int instance = ddi_get_instance(dip); 3521 3522 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3523 3524 ASSERT(state != NULL); 3525 3526 return (state); 3527 } 3528 3529 3530 /* 3531 * ehci_state_is_operational: 3532 * 3533 * Check the Host controller state and return proper values. 3534 */ 3535 int 3536 ehci_state_is_operational(ehci_state_t *ehcip) 3537 { 3538 int val; 3539 3540 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3541 3542 switch (ehcip->ehci_hc_soft_state) { 3543 case EHCI_CTLR_INIT_STATE: 3544 case EHCI_CTLR_SUSPEND_STATE: 3545 val = USB_FAILURE; 3546 break; 3547 case EHCI_CTLR_OPERATIONAL_STATE: 3548 val = USB_SUCCESS; 3549 break; 3550 case EHCI_CTLR_ERROR_STATE: 3551 val = USB_HC_HARDWARE_ERROR; 3552 break; 3553 default: 3554 val = USB_FAILURE; 3555 break; 3556 } 3557 3558 return (val); 3559 } 3560 3561 3562 /* 3563 * ehci_do_soft_reset 3564 * 3565 * Do soft reset of ehci host controller. 3566 */ 3567 int 3568 ehci_do_soft_reset(ehci_state_t *ehcip) 3569 { 3570 usb_frame_number_t before_frame_number, after_frame_number; 3571 ehci_regs_t *ehci_save_regs; 3572 3573 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3574 3575 /* Increment host controller error count */ 3576 ehcip->ehci_hc_error++; 3577 3578 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3579 "ehci_do_soft_reset:" 3580 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3581 3582 /* 3583 * Allocate space for saving current Host Controller 3584 * registers. Don't do any recovery if allocation 3585 * fails. 3586 */ 3587 ehci_save_regs = (ehci_regs_t *) 3588 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3589 3590 if (ehci_save_regs == NULL) { 3591 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3592 "ehci_do_soft_reset: kmem_zalloc failed"); 3593 3594 return (USB_FAILURE); 3595 } 3596 3597 /* Save current ehci registers */ 3598 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3599 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3600 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3601 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3602 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3603 ehci_save_regs->ehci_periodic_list_base = 3604 Get_OpReg(ehci_periodic_list_base); 3605 3606 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3607 "ehci_do_soft_reset: Save reg = 0x%p", ehci_save_regs); 3608 3609 /* Disable all list processing and interrupts */ 3610 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3611 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3612 3613 /* Disable all EHCI interrupts */ 3614 Set_OpReg(ehci_interrupt, 0); 3615 3616 /* Wait for few milliseconds */ 3617 drv_usecwait(EHCI_SOF_TIMEWAIT); 3618 3619 /* Do light soft reset of ehci host controller */ 3620 Set_OpReg(ehci_command, 3621 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3622 3623 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3624 "ehci_do_soft_reset: Reset in progress"); 3625 3626 /* Wait for reset to complete */ 3627 drv_usecwait(EHCI_RESET_TIMEWAIT); 3628 3629 /* 3630 * Restore previous saved EHCI register value 3631 * into the current EHCI registers. 3632 */ 3633 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3634 ehci_save_regs->ehci_ctrl_segment); 3635 3636 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3637 ehci_save_regs->ehci_periodic_list_base); 3638 3639 Set_OpReg(ehci_async_list_addr, (uint32_t) 3640 ehci_save_regs->ehci_async_list_addr); 3641 3642 Set_OpReg(ehci_config_flag, (uint32_t) 3643 ehci_save_regs->ehci_config_flag); 3644 3645 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3646 ehci_toggle_scheduler(ehcip); 3647 3648 /* 3649 * Set ehci_interrupt to enable all interrupts except Root 3650 * Hub Status change and frame list rollover interrupts. 3651 */ 3652 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3653 EHCI_INTR_FRAME_LIST_ROLLOVER | 3654 EHCI_INTR_USB_ERROR | 3655 EHCI_INTR_USB); 3656 3657 /* 3658 * Deallocate the space that allocated for saving 3659 * HC registers. 3660 */ 3661 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3662 3663 /* 3664 * Set the desired interrupt threshold, frame list size (if 3665 * applicable) and turn EHCI host controller. 3666 */ 3667 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3668 ~EHCI_CMD_INTR_THRESHOLD) | 3669 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3670 3671 /* Wait 10ms for EHCI to start sending SOF */ 3672 drv_usecwait(EHCI_RESET_TIMEWAIT); 3673 3674 /* 3675 * Get the current usb frame number before waiting for 3676 * few milliseconds. 3677 */ 3678 before_frame_number = ehci_get_current_frame_number(ehcip); 3679 3680 /* Wait for few milliseconds */ 3681 drv_usecwait(EHCI_SOF_TIMEWAIT); 3682 3683 /* 3684 * Get the current usb frame number after waiting for 3685 * few milliseconds. 3686 */ 3687 after_frame_number = ehci_get_current_frame_number(ehcip); 3688 3689 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3690 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3691 "After Frame Number 0x%llx", 3692 before_frame_number, after_frame_number); 3693 3694 if ((after_frame_number <= before_frame_number) && 3695 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3696 3697 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3698 "ehci_do_soft_reset: Soft reset failed"); 3699 3700 return (USB_FAILURE); 3701 } 3702 3703 return (USB_SUCCESS); 3704 } 3705 3706 3707 /* 3708 * ehci_get_xfer_attrs: 3709 * 3710 * Get the attributes of a particular xfer. 3711 * 3712 * NOTE: This function is also called from POLLED MODE. 3713 */ 3714 usb_req_attrs_t 3715 ehci_get_xfer_attrs( 3716 ehci_state_t *ehcip, 3717 ehci_pipe_private_t *pp, 3718 ehci_trans_wrapper_t *tw) 3719 { 3720 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3721 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3722 3723 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3724 "ehci_get_xfer_attrs:"); 3725 3726 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3727 case USB_EP_ATTR_CONTROL: 3728 attrs = ((usb_ctrl_req_t *) 3729 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3730 break; 3731 case USB_EP_ATTR_BULK: 3732 attrs = ((usb_bulk_req_t *) 3733 tw->tw_curr_xfer_reqp)->bulk_attributes; 3734 break; 3735 case USB_EP_ATTR_INTR: 3736 attrs = ((usb_intr_req_t *) 3737 tw->tw_curr_xfer_reqp)->intr_attributes; 3738 break; 3739 } 3740 3741 return (attrs); 3742 } 3743 3744 3745 /* 3746 * ehci_get_current_frame_number: 3747 * 3748 * Get the current software based usb frame number. 3749 */ 3750 usb_frame_number_t 3751 ehci_get_current_frame_number(ehci_state_t *ehcip) 3752 { 3753 usb_frame_number_t usb_frame_number; 3754 usb_frame_number_t ehci_fno, micro_frame_number; 3755 3756 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3757 3758 ehci_fno = ehcip->ehci_fno; 3759 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3760 3761 /* 3762 * Calculate current software based usb frame number. 3763 * 3764 * This code accounts for the fact that frame number is 3765 * updated by the Host Controller before the ehci driver 3766 * gets an FrameListRollover interrupt that will adjust 3767 * Frame higher part. 3768 * 3769 * Refer ehci specification 1.0, section 2.3.2, page 21. 3770 */ 3771 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3772 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3773 ehci_fno) & 0x2000); 3774 3775 /* 3776 * Micro Frame number is equivalent to 125 usec. Eight 3777 * Micro Frame numbers are equivalent to one millsecond 3778 * or one usb frame number. 3779 */ 3780 usb_frame_number = micro_frame_number >> 3781 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3782 3783 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3784 "ehci_get_current_frame_number: " 3785 "Current usb uframe number = 0x%llx " 3786 "Current usb frame number = 0x%llx", 3787 micro_frame_number, usb_frame_number); 3788 3789 return (usb_frame_number); 3790 } 3791 3792 3793 /* 3794 * ehci_cpr_cleanup: 3795 * 3796 * Cleanup ehci state and other ehci specific informations across 3797 * Check Point Resume (CPR). 3798 */ 3799 static void 3800 ehci_cpr_cleanup(ehci_state_t *ehcip) 3801 { 3802 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3803 3804 /* Reset software part of usb frame number */ 3805 ehcip->ehci_fno = 0; 3806 } 3807 3808 3809 /* 3810 * ehci_wait_for_sof: 3811 * 3812 * Wait for couple of SOF interrupts 3813 */ 3814 int 3815 ehci_wait_for_sof(ehci_state_t *ehcip) 3816 { 3817 usb_frame_number_t before_frame_number, after_frame_number; 3818 int error = USB_SUCCESS; 3819 3820 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3821 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3822 3823 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3824 3825 error = ehci_state_is_operational(ehcip); 3826 3827 if (error != USB_SUCCESS) { 3828 3829 return (error); 3830 } 3831 3832 /* Get the current usb frame number before waiting for two SOFs */ 3833 before_frame_number = ehci_get_current_frame_number(ehcip); 3834 3835 mutex_exit(&ehcip->ehci_int_mutex); 3836 3837 /* Wait for few milliseconds */ 3838 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3839 3840 mutex_enter(&ehcip->ehci_int_mutex); 3841 3842 /* Get the current usb frame number after woken up */ 3843 after_frame_number = ehci_get_current_frame_number(ehcip); 3844 3845 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3846 "ehci_wait_for_sof: framenumber: before 0x%llx " 3847 "after 0x%llx", before_frame_number, after_frame_number); 3848 3849 /* Return failure, if usb frame number has not been changed */ 3850 if (after_frame_number <= before_frame_number) { 3851 3852 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3853 3854 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3855 ehcip->ehci_log_hdl, "No SOF interrupts"); 3856 3857 /* Set host controller soft state to error */ 3858 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 3859 3860 return (USB_FAILURE); 3861 } 3862 3863 /* Get new usb frame number */ 3864 after_frame_number = before_frame_number = 3865 ehci_get_current_frame_number(ehcip); 3866 } 3867 3868 ASSERT(after_frame_number > before_frame_number); 3869 3870 return (USB_SUCCESS); 3871 } 3872 3873 3874 /* 3875 * ehci_toggle_scheduler: 3876 * 3877 * Turn scheduler based on pipe open count. 3878 */ 3879 void 3880 ehci_toggle_scheduler(ehci_state_t *ehcip) { 3881 uint_t temp_reg, cmd_reg; 3882 3883 cmd_reg = Get_OpReg(ehci_command); 3884 temp_reg = cmd_reg; 3885 3886 /* 3887 * Enable/Disable asynchronous scheduler, and 3888 * turn on/off async list door bell 3889 */ 3890 if (ehcip->ehci_open_async_count) { 3891 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 3892 /* 3893 * For some reason this address might get nulled out by 3894 * the ehci chip. Set it here just in case it is null. 3895 */ 3896 Set_OpReg(ehci_async_list_addr, 3897 ehci_qh_cpu_to_iommu(ehcip, 3898 ehcip->ehci_head_of_async_sched_list)); 3899 } 3900 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 3901 } else { 3902 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 3903 } 3904 3905 if (ehcip->ehci_open_periodic_count) { 3906 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 3907 /* 3908 * For some reason this address get's nulled out by 3909 * the ehci chip. Set it here just in case it is null. 3910 */ 3911 Set_OpReg(ehci_periodic_list_base, 3912 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 3913 0xFFFFF000)); 3914 } 3915 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 3916 } else { 3917 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 3918 } 3919 3920 /* Just an optimization */ 3921 if (temp_reg != cmd_reg) { 3922 Set_OpReg(ehci_command, cmd_reg); 3923 } 3924 } 3925 3926 /* 3927 * ehci print functions 3928 */ 3929 3930 /* 3931 * ehci_print_caps: 3932 */ 3933 void 3934 ehci_print_caps(ehci_state_t *ehcip) 3935 { 3936 uint_t i; 3937 3938 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3939 "\n\tUSB 2.0 Host Controller Characteristics\n"); 3940 3941 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3942 "Caps Length: 0x%x Version: 0x%x\n", 3943 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 3944 3945 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3946 "Structural Parameters\n"); 3947 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3948 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 3949 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 3950 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3951 "No of Classic host controllers: 0x%x", 3952 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 3953 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 3954 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3955 "No of ports per Classic host controller: 0x%x", 3956 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 3957 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 3958 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3959 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 3960 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 3961 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3962 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 3963 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 3964 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3965 "No of root hub ports: 0x%x\n", 3966 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 3967 3968 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3969 "Capability Parameters\n"); 3970 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3971 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 3972 EHCI_HCC_EECP) ? "Yes" : "No"); 3973 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3974 "Isoch schedule threshold: 0x%x", 3975 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 3976 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3977 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 3978 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 3979 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3980 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 3981 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 3982 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3983 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 3984 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 3985 3986 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3987 "Classic Port Route Description"); 3988 3989 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 3990 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3991 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 3992 } 3993 } 3994 3995 3996 /* 3997 * ehci_print_regs: 3998 */ 3999 void 4000 ehci_print_regs(ehci_state_t *ehcip) 4001 { 4002 uint_t i; 4003 4004 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4005 "\n\tEHCI%d Operational Registers\n", 4006 ddi_get_instance(ehcip->ehci_dip)); 4007 4008 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4009 "Command: 0x%x Status: 0x%x", 4010 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 4011 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4012 "Interrupt: 0x%x Frame Index: 0x%x", 4013 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 4014 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4015 "Control Segment: 0x%x Periodic List Base: 0x%x", 4016 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 4017 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4018 "Async List Addr: 0x%x Config Flag: 0x%x", 4019 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 4020 4021 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4022 "Root Hub Port Status"); 4023 4024 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4025 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4026 "\tPort Status 0x%x: 0x%x ", i, 4027 Get_OpReg(ehci_rh_port_status[i])); 4028 } 4029 } 4030 4031 4032 /* 4033 * ehci_print_qh: 4034 */ 4035 void 4036 ehci_print_qh( 4037 ehci_state_t *ehcip, 4038 ehci_qh_t *qh) 4039 { 4040 uint_t i; 4041 4042 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4043 "ehci_print_qh: qh = 0x%p", (void *)qh); 4044 4045 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4046 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 4047 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4048 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 4049 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4050 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 4051 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4052 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 4053 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4054 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 4055 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4056 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 4057 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4058 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 4059 4060 for (i = 0; i < 5; i++) { 4061 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4062 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 4063 } 4064 4065 for (i = 0; i < 5; i++) { 4066 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4067 "\tqh_buf_high[%d]: 0x%x ", 4068 i, Get_QH(qh->qh_buf_high[i])); 4069 } 4070 4071 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4072 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 4073 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4074 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 4075 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4076 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 4077 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4078 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 4079 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4080 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 4081 } 4082 4083 4084 /* 4085 * ehci_print_qtd: 4086 */ 4087 void 4088 ehci_print_qtd( 4089 ehci_state_t *ehcip, 4090 ehci_qtd_t *qtd) 4091 { 4092 uint_t i; 4093 4094 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4095 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 4096 4097 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4098 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 4099 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4100 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 4101 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4102 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 4103 4104 for (i = 0; i < 5; i++) { 4105 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4106 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 4107 } 4108 4109 for (i = 0; i < 5; i++) { 4110 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4111 "\tqtd_buf_high[%d]: 0x%x ", 4112 i, Get_QTD(qtd->qtd_buf_high[i])); 4113 } 4114 4115 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4116 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 4117 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4118 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 4119 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4120 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 4121 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4122 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 4123 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4124 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 4125 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4126 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 4127 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4128 "\tqtd_xfer_offs: 0x%x ", Get_QTD(qtd->qtd_xfer_offs)); 4129 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4130 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 4131 } 4132 4133 /* 4134 * ehci kstat functions 4135 */ 4136 4137 /* 4138 * ehci_create_stats: 4139 * 4140 * Allocate and initialize the ehci kstat structures 4141 */ 4142 void 4143 ehci_create_stats(ehci_state_t *ehcip) 4144 { 4145 char kstatname[KSTAT_STRLEN]; 4146 const char *dname = ddi_driver_name(ehcip->ehci_dip); 4147 char *usbtypes[USB_N_COUNT_KSTATS] = 4148 {"ctrl", "isoch", "bulk", "intr"}; 4149 uint_t instance = ehcip->ehci_instance; 4150 ehci_intrs_stats_t *isp; 4151 int i; 4152 4153 if (EHCI_INTRS_STATS(ehcip) == NULL) { 4154 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 4155 dname, instance); 4156 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 4157 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 4158 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 4159 KSTAT_FLAG_PERSISTENT); 4160 4161 if (EHCI_INTRS_STATS(ehcip)) { 4162 isp = EHCI_INTRS_STATS_DATA(ehcip); 4163 kstat_named_init(&isp->ehci_sts_total, 4164 "Interrupts Total", KSTAT_DATA_UINT64); 4165 kstat_named_init(&isp->ehci_sts_not_claimed, 4166 "Not Claimed", KSTAT_DATA_UINT64); 4167 kstat_named_init(&isp->ehci_sts_async_sched_status, 4168 "Async schedule status", KSTAT_DATA_UINT64); 4169 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 4170 "Periodic sched status", KSTAT_DATA_UINT64); 4171 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 4172 "Empty async schedule", KSTAT_DATA_UINT64); 4173 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 4174 "Host controller Halted", KSTAT_DATA_UINT64); 4175 kstat_named_init(&isp->ehci_sts_async_advance_intr, 4176 "Intr on async advance", KSTAT_DATA_UINT64); 4177 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 4178 "Host system error", KSTAT_DATA_UINT64); 4179 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 4180 "Frame list rollover", KSTAT_DATA_UINT64); 4181 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 4182 "Port change detect", KSTAT_DATA_UINT64); 4183 kstat_named_init(&isp->ehci_sts_usb_error_intr, 4184 "USB error interrupt", KSTAT_DATA_UINT64); 4185 kstat_named_init(&isp->ehci_sts_usb_intr, 4186 "USB interrupt", KSTAT_DATA_UINT64); 4187 4188 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 4189 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 4190 kstat_install(EHCI_INTRS_STATS(ehcip)); 4191 } 4192 } 4193 4194 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 4195 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 4196 dname, instance); 4197 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 4198 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 4199 KSTAT_FLAG_PERSISTENT); 4200 4201 if (EHCI_TOTAL_STATS(ehcip)) { 4202 kstat_install(EHCI_TOTAL_STATS(ehcip)); 4203 } 4204 } 4205 4206 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4207 if (ehcip->ehci_count_stats[i] == NULL) { 4208 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4209 dname, instance, usbtypes[i]); 4210 ehcip->ehci_count_stats[i] = kstat_create("usba", 4211 instance, kstatname, "usb_byte_count", 4212 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4213 4214 if (ehcip->ehci_count_stats[i]) { 4215 kstat_install(ehcip->ehci_count_stats[i]); 4216 } 4217 } 4218 } 4219 } 4220 4221 4222 /* 4223 * ehci_destroy_stats: 4224 * 4225 * Clean up ehci kstat structures 4226 */ 4227 void 4228 ehci_destroy_stats(ehci_state_t *ehcip) 4229 { 4230 int i; 4231 4232 if (EHCI_INTRS_STATS(ehcip)) { 4233 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4234 EHCI_INTRS_STATS(ehcip) = NULL; 4235 } 4236 4237 if (EHCI_TOTAL_STATS(ehcip)) { 4238 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4239 EHCI_TOTAL_STATS(ehcip) = NULL; 4240 } 4241 4242 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4243 if (ehcip->ehci_count_stats[i]) { 4244 kstat_delete(ehcip->ehci_count_stats[i]); 4245 ehcip->ehci_count_stats[i] = NULL; 4246 } 4247 } 4248 } 4249 4250 4251 /* 4252 * ehci_do_intrs_stats: 4253 * 4254 * ehci status information 4255 */ 4256 void 4257 ehci_do_intrs_stats( 4258 ehci_state_t *ehcip, 4259 int val) 4260 { 4261 if (EHCI_INTRS_STATS(ehcip)) { 4262 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4263 switch (val) { 4264 case EHCI_STS_ASYNC_SCHED_STATUS: 4265 EHCI_INTRS_STATS_DATA(ehcip)-> 4266 ehci_sts_async_sched_status.value.ui64++; 4267 break; 4268 case EHCI_STS_PERIODIC_SCHED_STATUS: 4269 EHCI_INTRS_STATS_DATA(ehcip)-> 4270 ehci_sts_periodic_sched_status.value.ui64++; 4271 break; 4272 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4273 EHCI_INTRS_STATS_DATA(ehcip)-> 4274 ehci_sts_empty_async_schedule.value.ui64++; 4275 break; 4276 case EHCI_STS_HOST_CTRL_HALTED: 4277 EHCI_INTRS_STATS_DATA(ehcip)-> 4278 ehci_sts_host_ctrl_halted.value.ui64++; 4279 break; 4280 case EHCI_STS_ASYNC_ADVANCE_INTR: 4281 EHCI_INTRS_STATS_DATA(ehcip)-> 4282 ehci_sts_async_advance_intr.value.ui64++; 4283 break; 4284 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4285 EHCI_INTRS_STATS_DATA(ehcip)-> 4286 ehci_sts_host_system_error_intr.value.ui64++; 4287 break; 4288 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4289 EHCI_INTRS_STATS_DATA(ehcip)-> 4290 ehci_sts_frm_list_rollover_intr.value.ui64++; 4291 break; 4292 case EHCI_STS_RH_PORT_CHANGE_INTR: 4293 EHCI_INTRS_STATS_DATA(ehcip)-> 4294 ehci_sts_rh_port_change_intr.value.ui64++; 4295 break; 4296 case EHCI_STS_USB_ERROR_INTR: 4297 EHCI_INTRS_STATS_DATA(ehcip)-> 4298 ehci_sts_usb_error_intr.value.ui64++; 4299 break; 4300 case EHCI_STS_USB_INTR: 4301 EHCI_INTRS_STATS_DATA(ehcip)-> 4302 ehci_sts_usb_intr.value.ui64++; 4303 break; 4304 default: 4305 EHCI_INTRS_STATS_DATA(ehcip)-> 4306 ehci_sts_not_claimed.value.ui64++; 4307 break; 4308 } 4309 } 4310 } 4311 4312 4313 /* 4314 * ehci_do_byte_stats: 4315 * 4316 * ehci data xfer information 4317 */ 4318 void 4319 ehci_do_byte_stats( 4320 ehci_state_t *ehcip, 4321 size_t len, 4322 uint8_t attr, 4323 uint8_t addr) 4324 { 4325 uint8_t type = attr & USB_EP_ATTR_MASK; 4326 uint8_t dir = addr & USB_EP_DIR_MASK; 4327 4328 if (dir == USB_EP_DIR_IN) { 4329 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4330 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4331 switch (type) { 4332 case USB_EP_ATTR_CONTROL: 4333 EHCI_CTRL_STATS(ehcip)->reads++; 4334 EHCI_CTRL_STATS(ehcip)->nread += len; 4335 break; 4336 case USB_EP_ATTR_BULK: 4337 EHCI_BULK_STATS(ehcip)->reads++; 4338 EHCI_BULK_STATS(ehcip)->nread += len; 4339 break; 4340 case USB_EP_ATTR_INTR: 4341 EHCI_INTR_STATS(ehcip)->reads++; 4342 EHCI_INTR_STATS(ehcip)->nread += len; 4343 break; 4344 case USB_EP_ATTR_ISOCH: 4345 EHCI_ISOC_STATS(ehcip)->reads++; 4346 EHCI_ISOC_STATS(ehcip)->nread += len; 4347 break; 4348 } 4349 } else if (dir == USB_EP_DIR_OUT) { 4350 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4351 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4352 switch (type) { 4353 case USB_EP_ATTR_CONTROL: 4354 EHCI_CTRL_STATS(ehcip)->writes++; 4355 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4356 break; 4357 case USB_EP_ATTR_BULK: 4358 EHCI_BULK_STATS(ehcip)->writes++; 4359 EHCI_BULK_STATS(ehcip)->nwritten += len; 4360 break; 4361 case USB_EP_ATTR_INTR: 4362 EHCI_INTR_STATS(ehcip)->writes++; 4363 EHCI_INTR_STATS(ehcip)->nwritten += len; 4364 break; 4365 case USB_EP_ATTR_ISOCH: 4366 EHCI_ISOC_STATS(ehcip)->writes++; 4367 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4368 break; 4369 } 4370 } 4371 } 4372