1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 25 /* 26 * This file contains various support routines. 27 */ 28 29 #include <sys/scsi/adapters/pmcs/pmcs.h> 30 31 /* 32 * Local static data 33 */ 34 static int tgtmap_stable_usec = MICROSEC; /* 1 second */ 35 static int tgtmap_csync_usec = 10 * MICROSEC; /* 10 seconds */ 36 37 /* 38 * SAS Topology Configuration 39 */ 40 static void pmcs_new_tport(pmcs_hw_t *, pmcs_phy_t *); 41 static void pmcs_configure_expander(pmcs_hw_t *, pmcs_phy_t *, pmcs_iport_t *); 42 43 static void pmcs_check_expanders(pmcs_hw_t *, pmcs_phy_t *); 44 static void pmcs_check_expander(pmcs_hw_t *, pmcs_phy_t *); 45 static void pmcs_clear_expander(pmcs_hw_t *, pmcs_phy_t *, int); 46 47 static int pmcs_expander_get_nphy(pmcs_hw_t *, pmcs_phy_t *); 48 static int pmcs_expander_content_discover(pmcs_hw_t *, pmcs_phy_t *, 49 pmcs_phy_t *); 50 51 static int pmcs_smp_function_result(pmcs_hw_t *, smp_response_frame_t *); 52 static void pmcs_flush_nonio_cmds(pmcs_hw_t *pwp, pmcs_xscsi_t *tgt); 53 static boolean_t pmcs_validate_devid(pmcs_phy_t *, pmcs_phy_t *, uint32_t); 54 static void pmcs_clear_phys(pmcs_hw_t *, pmcs_phy_t *); 55 static int pmcs_configure_new_devices(pmcs_hw_t *, pmcs_phy_t *); 56 static void pmcs_begin_observations(pmcs_hw_t *); 57 static void pmcs_flush_observations(pmcs_hw_t *); 58 static boolean_t pmcs_report_observations(pmcs_hw_t *); 59 static boolean_t pmcs_report_iport_observations(pmcs_hw_t *, pmcs_iport_t *, 60 pmcs_phy_t *); 61 static pmcs_phy_t *pmcs_find_phy_needing_work(pmcs_hw_t *, pmcs_phy_t *); 62 static int pmcs_kill_devices(pmcs_hw_t *, pmcs_phy_t *); 63 static void pmcs_lock_phy_impl(pmcs_phy_t *, int); 64 static void pmcs_unlock_phy_impl(pmcs_phy_t *, int); 65 static pmcs_phy_t *pmcs_clone_phy(pmcs_phy_t *); 66 static boolean_t pmcs_configure_phy(pmcs_hw_t *, pmcs_phy_t *); 67 static void pmcs_reap_dead_phy(pmcs_phy_t *); 68 static pmcs_iport_t *pmcs_get_iport_by_ua(pmcs_hw_t *, char *); 69 static boolean_t pmcs_phy_target_match(pmcs_phy_t *); 70 static void pmcs_iport_active(pmcs_iport_t *); 71 static void pmcs_tgtmap_activate_cb(void *, char *, scsi_tgtmap_tgt_type_t, 72 void **); 73 static boolean_t pmcs_tgtmap_deactivate_cb(void *, char *, 74 scsi_tgtmap_tgt_type_t, void *, scsi_tgtmap_deact_rsn_t); 75 static void pmcs_add_dead_phys(pmcs_hw_t *, pmcs_phy_t *); 76 static void pmcs_get_fw_version(pmcs_hw_t *); 77 static int pmcs_get_time_stamp(pmcs_hw_t *, uint64_t *, hrtime_t *); 78 79 /* 80 * Often used strings 81 */ 82 const char pmcs_nowrk[] = "%s: unable to get work structure"; 83 const char pmcs_nomsg[] = "%s: unable to get Inbound Message entry"; 84 const char pmcs_timeo[] = "%s: command timed out"; 85 86 extern const ddi_dma_attr_t pmcs_dattr; 87 extern kmutex_t pmcs_trace_lock; 88 89 /* 90 * Some Initial setup steps. 91 */ 92 93 int 94 pmcs_setup(pmcs_hw_t *pwp) 95 { 96 uint32_t barval = pwp->mpibar; 97 uint32_t i, scratch, regbar, regoff, barbar, baroff; 98 uint32_t new_ioq_depth, ferr = 0; 99 100 /* 101 * Check current state. If we're not at READY state, 102 * we can't go further. 103 */ 104 scratch = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1); 105 if ((scratch & PMCS_MSGU_AAP_STATE_MASK) == PMCS_MSGU_AAP_STATE_ERROR) { 106 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 107 "%s: AAP Error State (0x%x)", 108 __func__, pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1) & 109 PMCS_MSGU_AAP_ERROR_MASK); 110 pmcs_fm_ereport(pwp, DDI_FM_DEVICE_INVAL_STATE); 111 ddi_fm_service_impact(pwp->dip, DDI_SERVICE_LOST); 112 return (-1); 113 } 114 if ((scratch & PMCS_MSGU_AAP_STATE_MASK) != PMCS_MSGU_AAP_STATE_READY) { 115 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 116 "%s: AAP unit not ready (state 0x%x)", 117 __func__, scratch & PMCS_MSGU_AAP_STATE_MASK); 118 pmcs_fm_ereport(pwp, DDI_FM_DEVICE_INVAL_STATE); 119 ddi_fm_service_impact(pwp->dip, DDI_SERVICE_LOST); 120 return (-1); 121 } 122 123 /* 124 * Read the offset from the Message Unit scratchpad 0 register. 125 * This allows us to read the MPI Configuration table. 126 * 127 * Check its signature for validity. 128 */ 129 baroff = barval; 130 barbar = barval >> PMCS_MSGU_MPI_BAR_SHIFT; 131 baroff &= PMCS_MSGU_MPI_OFFSET_MASK; 132 133 regoff = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH0); 134 regbar = regoff >> PMCS_MSGU_MPI_BAR_SHIFT; 135 regoff &= PMCS_MSGU_MPI_OFFSET_MASK; 136 137 if (regoff > baroff) { 138 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 139 "%s: bad MPI Table Length (register offset=0x%08x, " 140 "passed offset=0x%08x)", __func__, regoff, baroff); 141 return (-1); 142 } 143 if (regbar != barbar) { 144 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 145 "%s: bad MPI BAR (register BAROFF=0x%08x, " 146 "passed BAROFF=0x%08x)", __func__, regbar, barbar); 147 return (-1); 148 } 149 pwp->mpi_offset = regoff; 150 if (pmcs_rd_mpi_tbl(pwp, PMCS_MPI_AS) != PMCS_SIGNATURE) { 151 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 152 "%s: Bad MPI Configuration Table Signature 0x%x", __func__, 153 pmcs_rd_mpi_tbl(pwp, PMCS_MPI_AS)); 154 return (-1); 155 } 156 157 if (pmcs_rd_mpi_tbl(pwp, PMCS_MPI_IR) != PMCS_MPI_REVISION1) { 158 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 159 "%s: Bad MPI Configuration Revision 0x%x", __func__, 160 pmcs_rd_mpi_tbl(pwp, PMCS_MPI_IR)); 161 return (-1); 162 } 163 164 /* 165 * Generate offsets for the General System, Inbound Queue Configuration 166 * and Outbound Queue configuration tables. This way the macros to 167 * access those tables will work correctly. 168 */ 169 pwp->mpi_gst_offset = 170 pwp->mpi_offset + pmcs_rd_mpi_tbl(pwp, PMCS_MPI_GSTO); 171 pwp->mpi_iqc_offset = 172 pwp->mpi_offset + pmcs_rd_mpi_tbl(pwp, PMCS_MPI_IQCTO); 173 pwp->mpi_oqc_offset = 174 pwp->mpi_offset + pmcs_rd_mpi_tbl(pwp, PMCS_MPI_OQCTO); 175 176 pmcs_get_fw_version(pwp); 177 178 pwp->max_cmd = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_MOIO); 179 pwp->max_dev = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO0) >> 16; 180 181 pwp->max_iq = PMCS_MNIQ(pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO1)); 182 pwp->max_oq = PMCS_MNOQ(pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO1)); 183 pwp->nphy = PMCS_NPHY(pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO1)); 184 if (pwp->max_iq <= PMCS_NIQ) { 185 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 186 "%s: not enough Inbound Queues supported " 187 "(need %d, max_oq=%d)", __func__, pwp->max_iq, PMCS_NIQ); 188 return (-1); 189 } 190 if (pwp->max_oq <= PMCS_NOQ) { 191 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 192 "%s: not enough Outbound Queues supported " 193 "(need %d, max_oq=%d)", __func__, pwp->max_oq, PMCS_NOQ); 194 return (-1); 195 } 196 if (pwp->nphy == 0) { 197 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 198 "%s: zero phys reported", __func__); 199 return (-1); 200 } 201 if (PMCS_HPIQ(pmcs_rd_mpi_tbl(pwp, PMCS_MPI_INFO1))) { 202 pwp->hipri_queue = (1 << PMCS_IQ_OTHER); 203 } 204 205 206 for (i = 0; i < pwp->nphy; i++) { 207 PMCS_MPI_EVQSET(pwp, PMCS_OQ_EVENTS, i); 208 PMCS_MPI_NCQSET(pwp, PMCS_OQ_EVENTS, i); 209 } 210 211 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_INFO2, 212 (PMCS_OQ_EVENTS << GENERAL_EVENT_OQ_SHIFT) | 213 (PMCS_OQ_EVENTS << DEVICE_HANDLE_REMOVED_SHIFT)); 214 215 /* 216 * Verify that ioq_depth is valid (> 0 and not so high that it 217 * would cause us to overrun the chip with commands). 218 */ 219 if (pwp->ioq_depth == 0) { 220 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 221 "%s: I/O queue depth set to 0. Setting to %d", 222 __func__, PMCS_NQENTRY); 223 pwp->ioq_depth = PMCS_NQENTRY; 224 } 225 226 if (pwp->ioq_depth < PMCS_MIN_NQENTRY) { 227 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 228 "%s: I/O queue depth set too low (%d). Setting to %d", 229 __func__, pwp->ioq_depth, PMCS_MIN_NQENTRY); 230 pwp->ioq_depth = PMCS_MIN_NQENTRY; 231 } 232 233 if (pwp->ioq_depth > (pwp->max_cmd / (PMCS_IO_IQ_MASK + 1))) { 234 new_ioq_depth = pwp->max_cmd / (PMCS_IO_IQ_MASK + 1); 235 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 236 "%s: I/O queue depth set too high (%d). Setting to %d", 237 __func__, pwp->ioq_depth, new_ioq_depth); 238 pwp->ioq_depth = new_ioq_depth; 239 } 240 241 /* 242 * Allocate consistent memory for OQs and IQs. 243 */ 244 pwp->iqp_dma_attr = pwp->oqp_dma_attr = pmcs_dattr; 245 pwp->iqp_dma_attr.dma_attr_align = 246 pwp->oqp_dma_attr.dma_attr_align = PMCS_QENTRY_SIZE; 247 248 /* 249 * The Rev C chip has the ability to do PIO to or from consistent 250 * memory anywhere in a 64 bit address space, but the firmware is 251 * not presently set up to do so. 252 */ 253 pwp->iqp_dma_attr.dma_attr_addr_hi = 254 pwp->oqp_dma_attr.dma_attr_addr_hi = 0x000000FFFFFFFFFFull; 255 256 for (i = 0; i < PMCS_NIQ; i++) { 257 if (pmcs_dma_setup(pwp, &pwp->iqp_dma_attr, 258 &pwp->iqp_acchdls[i], 259 &pwp->iqp_handles[i], PMCS_QENTRY_SIZE * pwp->ioq_depth, 260 (caddr_t *)&pwp->iqp[i], &pwp->iqaddr[i]) == B_FALSE) { 261 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 262 "Failed to setup DMA for iqp[%d]", i); 263 return (-1); 264 } 265 bzero(pwp->iqp[i], PMCS_QENTRY_SIZE * pwp->ioq_depth); 266 } 267 268 for (i = 0; i < PMCS_NOQ; i++) { 269 if (pmcs_dma_setup(pwp, &pwp->oqp_dma_attr, 270 &pwp->oqp_acchdls[i], 271 &pwp->oqp_handles[i], PMCS_QENTRY_SIZE * pwp->ioq_depth, 272 (caddr_t *)&pwp->oqp[i], &pwp->oqaddr[i]) == B_FALSE) { 273 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 274 "Failed to setup DMA for oqp[%d]", i); 275 return (-1); 276 } 277 bzero(pwp->oqp[i], PMCS_QENTRY_SIZE * pwp->ioq_depth); 278 } 279 280 /* 281 * Install the IQ and OQ addresses (and null out the rest). 282 */ 283 for (i = 0; i < pwp->max_iq; i++) { 284 pwp->iqpi_offset[i] = pmcs_rd_iqc_tbl(pwp, PMCS_IQPIOFFX(i)); 285 if (i < PMCS_NIQ) { 286 if (i != PMCS_IQ_OTHER) { 287 pmcs_wr_iqc_tbl(pwp, PMCS_IQC_PARMX(i), 288 pwp->ioq_depth | (PMCS_QENTRY_SIZE << 16)); 289 } else { 290 pmcs_wr_iqc_tbl(pwp, PMCS_IQC_PARMX(i), 291 (1 << 30) | pwp->ioq_depth | 292 (PMCS_QENTRY_SIZE << 16)); 293 } 294 pmcs_wr_iqc_tbl(pwp, PMCS_IQBAHX(i), 295 DWORD1(pwp->iqaddr[i])); 296 pmcs_wr_iqc_tbl(pwp, PMCS_IQBALX(i), 297 DWORD0(pwp->iqaddr[i])); 298 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBAHX(i), 299 DWORD1(pwp->ciaddr+IQ_OFFSET(i))); 300 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBALX(i), 301 DWORD0(pwp->ciaddr+IQ_OFFSET(i))); 302 } else { 303 pmcs_wr_iqc_tbl(pwp, PMCS_IQC_PARMX(i), 0); 304 pmcs_wr_iqc_tbl(pwp, PMCS_IQBAHX(i), 0); 305 pmcs_wr_iqc_tbl(pwp, PMCS_IQBALX(i), 0); 306 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBAHX(i), 0); 307 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBALX(i), 0); 308 } 309 } 310 311 for (i = 0; i < pwp->max_oq; i++) { 312 pwp->oqci_offset[i] = pmcs_rd_oqc_tbl(pwp, PMCS_OQCIOFFX(i)); 313 if (i < PMCS_NOQ) { 314 pmcs_wr_oqc_tbl(pwp, PMCS_OQC_PARMX(i), pwp->ioq_depth | 315 (PMCS_QENTRY_SIZE << 16) | OQIEX); 316 pmcs_wr_oqc_tbl(pwp, PMCS_OQBAHX(i), 317 DWORD1(pwp->oqaddr[i])); 318 pmcs_wr_oqc_tbl(pwp, PMCS_OQBALX(i), 319 DWORD0(pwp->oqaddr[i])); 320 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBAHX(i), 321 DWORD1(pwp->ciaddr+OQ_OFFSET(i))); 322 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBALX(i), 323 DWORD0(pwp->ciaddr+OQ_OFFSET(i))); 324 pmcs_wr_oqc_tbl(pwp, PMCS_OQIPARM(i), 325 pwp->oqvec[i] << 24); 326 pmcs_wr_oqc_tbl(pwp, PMCS_OQDICX(i), 0); 327 } else { 328 pmcs_wr_oqc_tbl(pwp, PMCS_OQC_PARMX(i), 0); 329 pmcs_wr_oqc_tbl(pwp, PMCS_OQBAHX(i), 0); 330 pmcs_wr_oqc_tbl(pwp, PMCS_OQBALX(i), 0); 331 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBAHX(i), 0); 332 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBALX(i), 0); 333 pmcs_wr_oqc_tbl(pwp, PMCS_OQIPARM(i), 0); 334 pmcs_wr_oqc_tbl(pwp, PMCS_OQDICX(i), 0); 335 } 336 } 337 338 /* 339 * Set up logging, if defined. 340 */ 341 if (pwp->fwlog) { 342 uint64_t logdma = pwp->fwaddr; 343 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_MELBAH, DWORD1(logdma)); 344 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_MELBAL, DWORD0(logdma)); 345 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_MELBS, PMCS_FWLOG_SIZE >> 1); 346 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_MELSEV, pwp->fwlog); 347 logdma += (PMCS_FWLOG_SIZE >> 1); 348 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_IELBAH, DWORD1(logdma)); 349 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_IELBAL, DWORD0(logdma)); 350 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_IELBS, PMCS_FWLOG_SIZE >> 1); 351 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_IELSEV, pwp->fwlog); 352 } 353 354 /* 355 * Interrupt vectors, outbound queues, and odb_auto_clear 356 * 357 * MSI/MSI-X: 358 * If we got 4 interrupt vectors, we'll assign one to each outbound 359 * queue as well as the fatal interrupt, and auto clear can be set 360 * for each. 361 * 362 * If we only got 2 vectors, one will be used for I/O completions 363 * and the other for the other two vectors. In this case, auto_ 364 * clear can only be set for I/Os, which is fine. The fatal 365 * interrupt will be mapped to the PMCS_FATAL_INTERRUPT bit, which 366 * is not an interrupt vector. 367 * 368 * MSI/MSI-X/INT-X: 369 * If we only got 1 interrupt vector, auto_clear must be set to 0, 370 * and again the fatal interrupt will be mapped to the 371 * PMCS_FATAL_INTERRUPT bit (again, not an interrupt vector). 372 */ 373 374 switch (pwp->int_type) { 375 case PMCS_INT_MSIX: 376 case PMCS_INT_MSI: 377 switch (pwp->intr_cnt) { 378 case 1: 379 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, PMCS_FERRIE | 380 (PMCS_FATAL_INTERRUPT << PMCS_FERIV_SHIFT)); 381 pwp->odb_auto_clear = 0; 382 break; 383 case 2: 384 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, PMCS_FERRIE | 385 (PMCS_FATAL_INTERRUPT << PMCS_FERIV_SHIFT)); 386 pwp->odb_auto_clear = (1 << PMCS_FATAL_INTERRUPT) | 387 (1 << PMCS_MSIX_IODONE); 388 break; 389 case 4: 390 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, PMCS_FERRIE | 391 (PMCS_MSIX_FATAL << PMCS_FERIV_SHIFT)); 392 pwp->odb_auto_clear = (1 << PMCS_MSIX_FATAL) | 393 (1 << PMCS_MSIX_GENERAL) | (1 << PMCS_MSIX_IODONE) | 394 (1 << PMCS_MSIX_EVENTS); 395 break; 396 } 397 break; 398 399 case PMCS_INT_FIXED: 400 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, 401 PMCS_FERRIE | (PMCS_FATAL_INTERRUPT << PMCS_FERIV_SHIFT)); 402 pwp->odb_auto_clear = 0; 403 break; 404 } 405 406 /* 407 * If the open retry interval is non-zero, set it. 408 */ 409 if (pwp->open_retry_interval != 0) { 410 int phynum; 411 412 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 413 "%s: Setting open retry interval to %d usecs", __func__, 414 pwp->open_retry_interval); 415 for (phynum = 0; phynum < pwp->nphy; phynum ++) { 416 pmcs_wr_gsm_reg(pwp, OPEN_RETRY_INTERVAL(phynum), 417 pwp->open_retry_interval); 418 } 419 } 420 421 /* 422 * Enable Interrupt Reassertion 423 * Default Delay 1000us 424 */ 425 ferr = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_FERR); 426 if ((ferr & PMCS_MPI_IRAE) == 0) { 427 ferr &= ~(PMCS_MPI_IRAU | PMCS_MPI_IRAD_MASK); 428 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, ferr | PMCS_MPI_IRAE); 429 } 430 431 pmcs_wr_topunit(pwp, PMCS_OBDB_AUTO_CLR, pwp->odb_auto_clear); 432 pwp->mpi_table_setup = 1; 433 return (0); 434 } 435 436 /* 437 * Start the Message Passing protocol with the PMC chip. 438 */ 439 int 440 pmcs_start_mpi(pmcs_hw_t *pwp) 441 { 442 int i; 443 444 pmcs_wr_msgunit(pwp, PMCS_MSGU_IBDB, PMCS_MSGU_IBDB_MPIINI); 445 for (i = 0; i < 1000; i++) { 446 if ((pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB) & 447 PMCS_MSGU_IBDB_MPIINI) == 0) { 448 break; 449 } 450 drv_usecwait(1000); 451 } 452 if (pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB) & PMCS_MSGU_IBDB_MPIINI) { 453 return (-1); 454 } 455 drv_usecwait(500000); 456 457 /* 458 * Check to make sure we got to INIT state. 459 */ 460 if (PMCS_MPI_S(pmcs_rd_gst_tbl(pwp, PMCS_GST_BASE)) != 461 PMCS_MPI_STATE_INIT) { 462 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 463 "%s: MPI launch failed (GST 0x%x DBCLR 0x%x)", __func__, 464 pmcs_rd_gst_tbl(pwp, PMCS_GST_BASE), 465 pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB_CLEAR)); 466 return (-1); 467 } 468 return (0); 469 } 470 471 /* 472 * Stop the Message Passing protocol with the PMC chip. 473 */ 474 int 475 pmcs_stop_mpi(pmcs_hw_t *pwp) 476 { 477 int i; 478 479 for (i = 0; i < pwp->max_iq; i++) { 480 pmcs_wr_iqc_tbl(pwp, PMCS_IQC_PARMX(i), 0); 481 pmcs_wr_iqc_tbl(pwp, PMCS_IQBAHX(i), 0); 482 pmcs_wr_iqc_tbl(pwp, PMCS_IQBALX(i), 0); 483 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBAHX(i), 0); 484 pmcs_wr_iqc_tbl(pwp, PMCS_IQCIBALX(i), 0); 485 } 486 for (i = 0; i < pwp->max_oq; i++) { 487 pmcs_wr_oqc_tbl(pwp, PMCS_OQC_PARMX(i), 0); 488 pmcs_wr_oqc_tbl(pwp, PMCS_OQBAHX(i), 0); 489 pmcs_wr_oqc_tbl(pwp, PMCS_OQBALX(i), 0); 490 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBAHX(i), 0); 491 pmcs_wr_oqc_tbl(pwp, PMCS_OQPIBALX(i), 0); 492 pmcs_wr_oqc_tbl(pwp, PMCS_OQIPARM(i), 0); 493 pmcs_wr_oqc_tbl(pwp, PMCS_OQDICX(i), 0); 494 } 495 pmcs_wr_mpi_tbl(pwp, PMCS_MPI_FERR, 0); 496 pmcs_wr_msgunit(pwp, PMCS_MSGU_IBDB, PMCS_MSGU_IBDB_MPICTU); 497 for (i = 0; i < 2000; i++) { 498 if ((pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB) & 499 PMCS_MSGU_IBDB_MPICTU) == 0) { 500 break; 501 } 502 drv_usecwait(1000); 503 } 504 if (pmcs_rd_msgunit(pwp, PMCS_MSGU_IBDB) & PMCS_MSGU_IBDB_MPICTU) { 505 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 506 "%s: MPI stop failed", __func__); 507 return (-1); 508 } 509 return (0); 510 } 511 512 /* 513 * Do a sequence of ECHO messages to test for MPI functionality, 514 * all inbound and outbound queue functionality and interrupts. 515 */ 516 int 517 pmcs_echo_test(pmcs_hw_t *pwp) 518 { 519 echo_test_t fred; 520 struct pmcwork *pwrk; 521 uint32_t *msg, count; 522 int iqe = 0, iqo = 0, result, rval = 0; 523 int iterations; 524 hrtime_t echo_start, echo_end, echo_total; 525 526 ASSERT(pwp->max_cmd > 0); 527 528 /* 529 * We want iterations to be max_cmd * 3 to ensure that we run the 530 * echo test enough times to iterate through every inbound queue 531 * at least twice. 532 */ 533 iterations = pwp->max_cmd * 3; 534 535 echo_total = 0; 536 count = 0; 537 538 while (count < iterations) { 539 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, NULL); 540 if (pwrk == NULL) { 541 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, 542 pmcs_nowrk, __func__); 543 rval = -1; 544 break; 545 } 546 547 mutex_enter(&pwp->iqp_lock[iqe]); 548 msg = GET_IQ_ENTRY(pwp, iqe); 549 if (msg == NULL) { 550 mutex_exit(&pwp->iqp_lock[iqe]); 551 pmcs_pwork(pwp, pwrk); 552 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, 553 pmcs_nomsg, __func__); 554 rval = -1; 555 break; 556 } 557 558 bzero(msg, PMCS_QENTRY_SIZE); 559 560 if (iqe == PMCS_IQ_OTHER) { 561 /* This is on the high priority queue */ 562 msg[0] = LE_32(PMCS_HIPRI(pwp, iqo, PMCIN_ECHO)); 563 } else { 564 msg[0] = LE_32(PMCS_IOMB_IN_SAS(iqo, PMCIN_ECHO)); 565 } 566 msg[1] = LE_32(pwrk->htag); 567 fred.signature = 0xdeadbeef; 568 fred.count = count; 569 fred.ptr = &count; 570 (void) memcpy(&msg[2], &fred, sizeof (fred)); 571 pwrk->state = PMCS_WORK_STATE_ONCHIP; 572 573 INC_IQ_ENTRY(pwp, iqe); 574 575 echo_start = gethrtime(); 576 DTRACE_PROBE2(pmcs__echo__test__wait__start, 577 hrtime_t, echo_start, uint32_t, pwrk->htag); 578 579 if (++iqe == PMCS_NIQ) { 580 iqe = 0; 581 } 582 if (++iqo == PMCS_NOQ) { 583 iqo = 0; 584 } 585 586 WAIT_FOR(pwrk, 250, result); 587 pmcs_pwork(pwp, pwrk); 588 589 echo_end = gethrtime(); 590 DTRACE_PROBE2(pmcs__echo__test__wait__end, 591 hrtime_t, echo_end, int, result); 592 echo_total += (echo_end - echo_start); 593 594 if (result) { 595 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 596 "%s: command timed out on echo test #%d", 597 __func__, count); 598 rval = -1; 599 break; 600 } 601 } 602 603 /* 604 * The intr_threshold is adjusted by PMCS_INTR_THRESHOLD in order to 605 * remove the overhead of things like the delay in getting signaled 606 * for completion. 607 */ 608 if (echo_total != 0) { 609 pwp->io_intr_coal.intr_latency = 610 (echo_total / iterations) / 2; 611 pwp->io_intr_coal.intr_threshold = 612 PMCS_INTR_THRESHOLD(PMCS_QUANTUM_TIME_USECS * 1000 / 613 pwp->io_intr_coal.intr_latency); 614 } 615 616 return (rval); 617 } 618 619 /* 620 * Start the (real) phys 621 */ 622 int 623 pmcs_start_phy(pmcs_hw_t *pwp, int phynum, int linkmode, int speed) 624 { 625 int result; 626 uint32_t *msg; 627 struct pmcwork *pwrk; 628 pmcs_phy_t *pptr; 629 sas_identify_af_t sap; 630 631 mutex_enter(&pwp->lock); 632 pptr = pwp->root_phys + phynum; 633 if (pptr == NULL) { 634 mutex_exit(&pwp->lock); 635 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 636 "%s: cannot find port %d", __func__, phynum); 637 return (0); 638 } 639 640 pmcs_lock_phy(pptr); 641 mutex_exit(&pwp->lock); 642 643 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 644 if (pwrk == NULL) { 645 pmcs_unlock_phy(pptr); 646 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nowrk, __func__); 647 return (-1); 648 } 649 650 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 651 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 652 653 if (msg == NULL) { 654 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 655 pmcs_unlock_phy(pptr); 656 pmcs_pwork(pwp, pwrk); 657 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nomsg, __func__); 658 return (-1); 659 } 660 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_EVENTS, PMCIN_PHY_START)); 661 msg[1] = LE_32(pwrk->htag); 662 msg[2] = LE_32(linkmode | speed | phynum); 663 bzero(&sap, sizeof (sap)); 664 sap.device_type = SAS_IF_DTYPE_ENDPOINT; 665 sap.ssp_ini_port = 1; 666 667 if (pwp->separate_ports) { 668 pmcs_wwn2barray(pwp->sas_wwns[phynum], sap.sas_address); 669 } else { 670 pmcs_wwn2barray(pwp->sas_wwns[0], sap.sas_address); 671 } 672 673 ASSERT(phynum < SAS2_PHYNUM_MAX); 674 sap.phy_identifier = phynum & SAS2_PHYNUM_MASK; 675 (void) memcpy(&msg[3], &sap, sizeof (sas_identify_af_t)); 676 pwrk->state = PMCS_WORK_STATE_ONCHIP; 677 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 678 679 pptr->state.prog_min_rate = (lowbit((ulong_t)speed) - 1); 680 pptr->state.prog_max_rate = (highbit((ulong_t)speed) - 1); 681 pptr->state.hw_min_rate = PMCS_HW_MIN_LINK_RATE; 682 pptr->state.hw_max_rate = PMCS_HW_MAX_LINK_RATE; 683 684 pmcs_unlock_phy(pptr); 685 WAIT_FOR(pwrk, 1000, result); 686 pmcs_pwork(pwp, pwrk); 687 688 if (result) { 689 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, pmcs_timeo, __func__); 690 } else { 691 mutex_enter(&pwp->lock); 692 pwp->phys_started |= (1 << phynum); 693 mutex_exit(&pwp->lock); 694 } 695 696 return (0); 697 } 698 699 int 700 pmcs_start_phys(pmcs_hw_t *pwp) 701 { 702 int i, rval; 703 704 for (i = 0; i < pwp->nphy; i++) { 705 if ((pwp->phyid_block_mask & (1 << i)) == 0) { 706 if (pmcs_start_phy(pwp, i, 707 (pwp->phymode << PHY_MODE_SHIFT), 708 pwp->physpeed << PHY_LINK_SHIFT)) { 709 return (-1); 710 } 711 if (pmcs_clear_diag_counters(pwp, i)) { 712 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 713 "%s: failed to reset counters on PHY (%d)", 714 __func__, i); 715 } 716 } 717 } 718 719 rval = pmcs_get_time_stamp(pwp, &pwp->fw_timestamp, &pwp->hrtimestamp); 720 if (rval) { 721 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 722 "%s: Failed to obtain firmware timestamp", __func__); 723 } else { 724 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 725 "Firmware timestamp: 0x%" PRIx64, pwp->fw_timestamp); 726 } 727 728 return (0); 729 } 730 731 /* 732 * Called with PHY locked 733 */ 734 int 735 pmcs_reset_phy(pmcs_hw_t *pwp, pmcs_phy_t *pptr, uint8_t type) 736 { 737 uint32_t *msg; 738 uint32_t iomb[(PMCS_QENTRY_SIZE << 1) >> 2]; 739 const char *mbar; 740 uint32_t amt; 741 uint32_t pdevid; 742 uint32_t stsoff; 743 uint32_t status; 744 int result, level, phynum; 745 struct pmcwork *pwrk; 746 pmcs_iport_t *iport; 747 uint32_t htag; 748 749 ASSERT(mutex_owned(&pptr->phy_lock)); 750 751 bzero(iomb, PMCS_QENTRY_SIZE); 752 phynum = pptr->phynum; 753 level = pptr->level; 754 if (level > 0) { 755 pdevid = pptr->parent->device_id; 756 } else if ((level == 0) && (pptr->dtype == EXPANDER)) { 757 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, pptr->target, 758 "%s: Not resetting HBA PHY @ %s", __func__, pptr->path); 759 return (0); 760 } 761 762 if (!pptr->iport || !pptr->valid_device_id) { 763 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, pptr->target, 764 "%s: Can't reach PHY %s", __func__, pptr->path); 765 return (0); 766 } 767 768 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 769 770 if (pwrk == NULL) { 771 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nowrk, __func__); 772 return (ENOMEM); 773 } 774 775 pwrk->arg = iomb; 776 777 /* 778 * If level > 0, we need to issue an SMP_REQUEST with a PHY_CONTROL 779 * function to do either a link reset or hard reset. If level == 0, 780 * then we do a LOCAL_PHY_CONTROL IOMB to do link/hard reset to the 781 * root (local) PHY 782 */ 783 if (level) { 784 stsoff = 2; 785 iomb[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 786 PMCIN_SMP_REQUEST)); 787 iomb[1] = LE_32(pwrk->htag); 788 iomb[2] = LE_32(pdevid); 789 iomb[3] = LE_32(40 << SMP_REQUEST_LENGTH_SHIFT); 790 /* 791 * Send SMP PHY CONTROL/HARD or LINK RESET 792 */ 793 iomb[4] = BE_32(0x40910000); 794 iomb[5] = 0; 795 796 if (type == PMCS_PHYOP_HARD_RESET) { 797 mbar = "SMP PHY CONTROL/HARD RESET"; 798 iomb[6] = BE_32((phynum << 16) | 799 (PMCS_PHYOP_HARD_RESET << 8)); 800 } else { 801 mbar = "SMP PHY CONTROL/LINK RESET"; 802 iomb[6] = BE_32((phynum << 16) | 803 (PMCS_PHYOP_LINK_RESET << 8)); 804 } 805 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 806 "%s: sending %s to %s for phy 0x%x", 807 __func__, mbar, pptr->parent->path, pptr->phynum); 808 amt = 7; 809 } else { 810 /* 811 * Unlike most other Outbound messages, status for 812 * a local phy operation is in DWORD 3. 813 */ 814 stsoff = 3; 815 iomb[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 816 PMCIN_LOCAL_PHY_CONTROL)); 817 iomb[1] = LE_32(pwrk->htag); 818 if (type == PMCS_PHYOP_LINK_RESET) { 819 mbar = "LOCAL PHY LINK RESET"; 820 iomb[2] = LE_32((PMCS_PHYOP_LINK_RESET << 8) | phynum); 821 } else { 822 mbar = "LOCAL PHY HARD RESET"; 823 iomb[2] = LE_32((PMCS_PHYOP_HARD_RESET << 8) | phynum); 824 } 825 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 826 "%s: sending %s to %s", __func__, mbar, pptr->path); 827 amt = 3; 828 } 829 830 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 831 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 832 if (msg == NULL) { 833 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 834 pmcs_pwork(pwp, pwrk); 835 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nomsg, __func__); 836 return (ENOMEM); 837 } 838 COPY_MESSAGE(msg, iomb, amt); 839 htag = pwrk->htag; 840 841 pmcs_hold_iport(pptr->iport); 842 iport = pptr->iport; 843 pmcs_smp_acquire(iport); 844 pwrk->state = PMCS_WORK_STATE_ONCHIP; 845 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 846 pmcs_unlock_phy(pptr); 847 WAIT_FOR(pwrk, 1000, result); 848 pmcs_pwork(pwp, pwrk); 849 pmcs_lock_phy(pptr); 850 if (result) { 851 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, pmcs_timeo, __func__); 852 853 if (pmcs_abort(pwp, pptr, htag, 0, 0)) { 854 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 855 "%s: Unable to issue SMP abort for htag 0x%08x", 856 __func__, htag); 857 } else { 858 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 859 "%s: Issuing SMP ABORT for htag 0x%08x", 860 __func__, htag); 861 } 862 pmcs_smp_release(iport); 863 pmcs_rele_iport(iport); 864 return (EIO); 865 } 866 pmcs_smp_release(iport); 867 pmcs_rele_iport(iport); 868 status = LE_32(iomb[stsoff]); 869 870 if (status != PMCOUT_STATUS_OK) { 871 char buf[32]; 872 const char *es = pmcs_status_str(status); 873 if (es == NULL) { 874 (void) snprintf(buf, sizeof (buf), "Status 0x%x", 875 status); 876 es = buf; 877 } 878 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 879 "%s: %s action returned %s for %s", __func__, mbar, es, 880 pptr->path); 881 return (status); 882 } 883 884 return (0); 885 } 886 887 /* 888 * Stop the (real) phys. No PHY or softstate locks are required as this only 889 * happens during detach. 890 */ 891 void 892 pmcs_stop_phy(pmcs_hw_t *pwp, int phynum) 893 { 894 int result; 895 pmcs_phy_t *pptr; 896 uint32_t *msg; 897 struct pmcwork *pwrk; 898 899 pptr = pwp->root_phys + phynum; 900 if (pptr == NULL) { 901 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 902 "%s: unable to find port %d", __func__, phynum); 903 return; 904 } 905 906 if (pwp->phys_started & (1 << phynum)) { 907 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 908 909 if (pwrk == NULL) { 910 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, 911 pmcs_nowrk, __func__); 912 return; 913 } 914 915 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 916 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 917 918 if (msg == NULL) { 919 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 920 pmcs_pwork(pwp, pwrk); 921 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, 922 pmcs_nomsg, __func__); 923 return; 924 } 925 926 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_EVENTS, PMCIN_PHY_STOP)); 927 msg[1] = LE_32(pwrk->htag); 928 msg[2] = LE_32(phynum); 929 pwrk->state = PMCS_WORK_STATE_ONCHIP; 930 /* 931 * Make this unconfigured now. 932 */ 933 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 934 WAIT_FOR(pwrk, 1000, result); 935 pmcs_pwork(pwp, pwrk); 936 if (result) { 937 pmcs_prt(pwp, PMCS_PRT_DEBUG, 938 pptr, NULL, pmcs_timeo, __func__); 939 } 940 941 pwp->phys_started &= ~(1 << phynum); 942 } 943 944 pptr->configured = 0; 945 } 946 947 /* 948 * No locks should be required as this is only called during detach 949 */ 950 void 951 pmcs_stop_phys(pmcs_hw_t *pwp) 952 { 953 int i; 954 for (i = 0; i < pwp->nphy; i++) { 955 if ((pwp->phyid_block_mask & (1 << i)) == 0) { 956 pmcs_stop_phy(pwp, i); 957 } 958 } 959 } 960 961 /* 962 * Run SAS_DIAG_EXECUTE with cmd and cmd_desc passed. 963 * ERR_CNT_RESET: return status of cmd 964 * DIAG_REPORT_GET: return value of the counter 965 */ 966 int 967 pmcs_sas_diag_execute(pmcs_hw_t *pwp, uint32_t cmd, uint32_t cmd_desc, 968 uint8_t phynum) 969 { 970 uint32_t htag, *ptr, status, msg[PMCS_MSG_SIZE << 1]; 971 int result; 972 struct pmcwork *pwrk; 973 974 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, NULL); 975 if (pwrk == NULL) { 976 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, pmcs_nowrk, __func__); 977 return (DDI_FAILURE); 978 } 979 pwrk->arg = msg; 980 htag = pwrk->htag; 981 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_EVENTS, PMCIN_SAS_DIAG_EXECUTE)); 982 msg[1] = LE_32(htag); 983 msg[2] = LE_32((cmd << PMCS_DIAG_CMD_SHIFT) | 984 (cmd_desc << PMCS_DIAG_CMD_DESC_SHIFT) | phynum); 985 986 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 987 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 988 if (ptr == NULL) { 989 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 990 pmcs_pwork(pwp, pwrk); 991 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, pmcs_nomsg, __func__); 992 return (DDI_FAILURE); 993 } 994 COPY_MESSAGE(ptr, msg, 3); 995 pwrk->state = PMCS_WORK_STATE_ONCHIP; 996 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 997 998 WAIT_FOR(pwrk, 1000, result); 999 pmcs_pwork(pwp, pwrk); 1000 if (result) { 1001 pmcs_timed_out(pwp, htag, __func__); 1002 return (DDI_FAILURE); 1003 } 1004 1005 status = LE_32(msg[3]); 1006 1007 /* Return for counter reset */ 1008 if (cmd == PMCS_ERR_CNT_RESET) 1009 return (status); 1010 1011 /* Return for counter value */ 1012 if (status) { 1013 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1014 "%s: failed, status (0x%x)", __func__, status); 1015 return (DDI_FAILURE); 1016 } 1017 return (LE_32(msg[4])); 1018 } 1019 1020 /* Get the current value of the counter for desc on phynum and return it. */ 1021 int 1022 pmcs_get_diag_report(pmcs_hw_t *pwp, uint32_t desc, uint8_t phynum) 1023 { 1024 return (pmcs_sas_diag_execute(pwp, PMCS_DIAG_REPORT_GET, desc, phynum)); 1025 } 1026 1027 /* Clear all of the counters for phynum. Returns the status of the command. */ 1028 int 1029 pmcs_clear_diag_counters(pmcs_hw_t *pwp, uint8_t phynum) 1030 { 1031 uint32_t cmd = PMCS_ERR_CNT_RESET; 1032 uint32_t cmd_desc; 1033 1034 cmd_desc = PMCS_INVALID_DWORD_CNT; 1035 if (pmcs_sas_diag_execute(pwp, cmd, cmd_desc, phynum)) 1036 return (DDI_FAILURE); 1037 1038 cmd_desc = PMCS_DISPARITY_ERR_CNT; 1039 if (pmcs_sas_diag_execute(pwp, cmd, cmd_desc, phynum)) 1040 return (DDI_FAILURE); 1041 1042 cmd_desc = PMCS_LOST_DWORD_SYNC_CNT; 1043 if (pmcs_sas_diag_execute(pwp, cmd, cmd_desc, phynum)) 1044 return (DDI_FAILURE); 1045 1046 cmd_desc = PMCS_RESET_FAILED_CNT; 1047 if (pmcs_sas_diag_execute(pwp, cmd, cmd_desc, phynum)) 1048 return (DDI_FAILURE); 1049 1050 return (DDI_SUCCESS); 1051 } 1052 1053 /* 1054 * Get firmware timestamp 1055 */ 1056 static int 1057 pmcs_get_time_stamp(pmcs_hw_t *pwp, uint64_t *fw_ts, hrtime_t *sys_hr_ts) 1058 { 1059 uint32_t htag, *ptr, msg[PMCS_MSG_SIZE << 1]; 1060 int result; 1061 struct pmcwork *pwrk; 1062 1063 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, NULL); 1064 if (pwrk == NULL) { 1065 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, pmcs_nowrk, __func__); 1066 return (-1); 1067 } 1068 pwrk->arg = msg; 1069 htag = pwrk->htag; 1070 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_EVENTS, PMCIN_GET_TIME_STAMP)); 1071 msg[1] = LE_32(pwrk->htag); 1072 1073 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1074 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1075 if (ptr == NULL) { 1076 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1077 pmcs_pwork(pwp, pwrk); 1078 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, pmcs_nomsg, __func__); 1079 return (-1); 1080 } 1081 COPY_MESSAGE(ptr, msg, 2); 1082 pwrk->state = PMCS_WORK_STATE_ONCHIP; 1083 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1084 1085 WAIT_FOR(pwrk, 1000, result); 1086 pmcs_pwork(pwp, pwrk); 1087 if (result) { 1088 pmcs_timed_out(pwp, htag, __func__); 1089 return (-1); 1090 } 1091 1092 mutex_enter(&pmcs_trace_lock); 1093 *sys_hr_ts = gethrtime(); 1094 gethrestime(&pwp->sys_timestamp); 1095 *fw_ts = LE_32(msg[2]) | (((uint64_t)LE_32(msg[3])) << 32); 1096 mutex_exit(&pmcs_trace_lock); 1097 return (0); 1098 } 1099 1100 /* 1101 * Dump all pertinent registers 1102 */ 1103 1104 void 1105 pmcs_register_dump(pmcs_hw_t *pwp) 1106 { 1107 int i; 1108 uint32_t val; 1109 1110 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "pmcs%d: Register dump start", 1111 ddi_get_instance(pwp->dip)); 1112 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 1113 "OBDB (intr): 0x%08x (mask): 0x%08x (clear): 0x%08x", 1114 pmcs_rd_msgunit(pwp, PMCS_MSGU_OBDB), 1115 pmcs_rd_msgunit(pwp, PMCS_MSGU_OBDB_MASK), 1116 pmcs_rd_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR)); 1117 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "SCRATCH0: 0x%08x", 1118 pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH0)); 1119 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "SCRATCH1: 0x%08x", 1120 pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1)); 1121 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "SCRATCH2: 0x%08x", 1122 pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2)); 1123 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "SCRATCH3: 0x%08x", 1124 pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH3)); 1125 for (i = 0; i < PMCS_NIQ; i++) { 1126 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "IQ %d: CI %u PI %u", 1127 i, pmcs_rd_iqci(pwp, i), pmcs_rd_iqpi(pwp, i)); 1128 } 1129 for (i = 0; i < PMCS_NOQ; i++) { 1130 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "OQ %d: CI %u PI %u", 1131 i, pmcs_rd_oqci(pwp, i), pmcs_rd_oqpi(pwp, i)); 1132 } 1133 val = pmcs_rd_gst_tbl(pwp, PMCS_GST_BASE); 1134 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 1135 "GST TABLE BASE: 0x%08x (STATE=0x%x QF=%d GSTLEN=%d HMI_ERR=0x%x)", 1136 val, PMCS_MPI_S(val), PMCS_QF(val), PMCS_GSTLEN(val) * 4, 1137 PMCS_HMI_ERR(val)); 1138 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "GST TABLE IQFRZ0: 0x%08x", 1139 pmcs_rd_gst_tbl(pwp, PMCS_GST_IQFRZ0)); 1140 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "GST TABLE IQFRZ1: 0x%08x", 1141 pmcs_rd_gst_tbl(pwp, PMCS_GST_IQFRZ1)); 1142 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "GST TABLE MSGU TICK: 0x%08x", 1143 pmcs_rd_gst_tbl(pwp, PMCS_GST_MSGU_TICK)); 1144 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "GST TABLE IOP TICK: 0x%08x", 1145 pmcs_rd_gst_tbl(pwp, PMCS_GST_IOP_TICK)); 1146 for (i = 0; i < pwp->nphy; i++) { 1147 uint32_t rerrf, pinfo, started = 0, link = 0; 1148 pinfo = pmcs_rd_gst_tbl(pwp, PMCS_GST_PHY_INFO(i)); 1149 if (pinfo & 1) { 1150 started = 1; 1151 link = pinfo & 2; 1152 } 1153 rerrf = pmcs_rd_gst_tbl(pwp, PMCS_GST_RERR_INFO(i)); 1154 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 1155 "GST TABLE PHY%d STARTED=%d LINK=%d RERR=0x%08x", 1156 i, started, link, rerrf); 1157 } 1158 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "pmcs%d: Register dump end", 1159 ddi_get_instance(pwp->dip)); 1160 } 1161 1162 /* 1163 * Handle SATA Abort and other error processing 1164 */ 1165 int 1166 pmcs_abort_handler(pmcs_hw_t *pwp) 1167 { 1168 pmcs_phy_t *pptr, *pnext, *pnext_uplevel[PMCS_MAX_XPND]; 1169 pmcs_xscsi_t *tgt; 1170 int r, level = 0; 1171 1172 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "%s", __func__); 1173 1174 mutex_enter(&pwp->lock); 1175 pptr = pwp->root_phys; 1176 mutex_exit(&pwp->lock); 1177 1178 while (pptr) { 1179 /* 1180 * XXX: Need to make sure this doesn't happen 1181 * XXX: when non-NCQ commands are running. 1182 */ 1183 pmcs_lock_phy(pptr); 1184 if (pptr->need_rl_ext) { 1185 ASSERT(pptr->dtype == SATA); 1186 if (pmcs_acquire_scratch(pwp, B_FALSE)) { 1187 goto next_phy; 1188 } 1189 r = pmcs_sata_abort_ncq(pwp, pptr); 1190 pmcs_release_scratch(pwp); 1191 if (r == ENOMEM) { 1192 goto next_phy; 1193 } 1194 if (r) { 1195 r = pmcs_reset_phy(pwp, pptr, 1196 PMCS_PHYOP_LINK_RESET); 1197 if (r == ENOMEM) { 1198 goto next_phy; 1199 } 1200 /* what if other failures happened? */ 1201 pptr->abort_pending = 1; 1202 pptr->abort_sent = 0; 1203 } 1204 } 1205 if (pptr->abort_pending == 0 || pptr->abort_sent) { 1206 goto next_phy; 1207 } 1208 pptr->abort_pending = 0; 1209 if (pmcs_abort(pwp, pptr, pptr->device_id, 1, 1) == ENOMEM) { 1210 pptr->abort_pending = 1; 1211 goto next_phy; 1212 } 1213 pptr->abort_sent = 1; 1214 1215 /* 1216 * If the iport is no longer active, flush the queues 1217 */ 1218 if ((pptr->iport == NULL) || 1219 (pptr->iport->ua_state != UA_ACTIVE)) { 1220 tgt = pptr->target; 1221 if (tgt != NULL) { 1222 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, tgt, 1223 "%s: Clearing target 0x%p, inactive iport", 1224 __func__, (void *) tgt); 1225 mutex_enter(&tgt->statlock); 1226 pmcs_clear_xp(pwp, tgt); 1227 mutex_exit(&tgt->statlock); 1228 } 1229 } 1230 1231 next_phy: 1232 if (pptr->children) { 1233 pnext = pptr->children; 1234 pnext_uplevel[level++] = pptr->sibling; 1235 } else { 1236 pnext = pptr->sibling; 1237 while ((pnext == NULL) && (level > 0)) { 1238 pnext = pnext_uplevel[--level]; 1239 } 1240 } 1241 1242 pmcs_unlock_phy(pptr); 1243 pptr = pnext; 1244 } 1245 1246 return (0); 1247 } 1248 1249 /* 1250 * Register a device (get a device handle for it). 1251 * Called with PHY lock held. 1252 */ 1253 int 1254 pmcs_register_device(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 1255 { 1256 struct pmcwork *pwrk; 1257 int result = 0; 1258 uint32_t *msg; 1259 uint32_t tmp, status; 1260 uint32_t iomb[(PMCS_QENTRY_SIZE << 1) >> 2]; 1261 1262 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1263 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1264 1265 if (msg == NULL || 1266 (pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr)) == NULL) { 1267 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1268 result = ENOMEM; 1269 goto out; 1270 } 1271 1272 pwrk->arg = iomb; 1273 pwrk->dtype = pptr->dtype; 1274 1275 msg[1] = LE_32(pwrk->htag); 1276 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, PMCIN_REGISTER_DEVICE)); 1277 tmp = PMCS_DEVREG_TLR | 1278 (pptr->link_rate << PMCS_DEVREG_LINK_RATE_SHIFT); 1279 if (IS_ROOT_PHY(pptr)) { 1280 msg[2] = LE_32(pptr->portid | 1281 (pptr->phynum << PMCS_PHYID_SHIFT)); 1282 } else { 1283 msg[2] = LE_32(pptr->portid); 1284 } 1285 if (pptr->dtype == SATA) { 1286 if (IS_ROOT_PHY(pptr)) { 1287 tmp |= PMCS_DEVREG_TYPE_SATA_DIRECT; 1288 } else { 1289 tmp |= PMCS_DEVREG_TYPE_SATA; 1290 } 1291 } else { 1292 tmp |= PMCS_DEVREG_TYPE_SAS; 1293 } 1294 msg[3] = LE_32(tmp); 1295 msg[4] = LE_32(PMCS_DEVREG_IT_NEXUS_TIMEOUT); 1296 (void) memcpy(&msg[5], pptr->sas_address, 8); 1297 1298 CLEAN_MESSAGE(msg, 7); 1299 pwrk->state = PMCS_WORK_STATE_ONCHIP; 1300 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1301 1302 pmcs_unlock_phy(pptr); 1303 WAIT_FOR(pwrk, 250, result); 1304 pmcs_pwork(pwp, pwrk); 1305 pmcs_lock_phy(pptr); 1306 1307 if (result) { 1308 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, pmcs_timeo, __func__); 1309 result = ETIMEDOUT; 1310 goto out; 1311 } 1312 status = LE_32(iomb[2]); 1313 tmp = LE_32(iomb[3]); 1314 switch (status) { 1315 case PMCS_DEVREG_OK: 1316 case PMCS_DEVREG_DEVICE_ALREADY_REGISTERED: 1317 case PMCS_DEVREG_PHY_ALREADY_REGISTERED: 1318 if (pmcs_validate_devid(pwp->root_phys, pptr, tmp) == B_FALSE) { 1319 result = EEXIST; 1320 goto out; 1321 } else if (status != PMCS_DEVREG_OK) { 1322 if (tmp == 0xffffffff) { /* F/W bug */ 1323 pmcs_prt(pwp, PMCS_PRT_INFO, pptr, NULL, 1324 "%s: phy %s already has bogus devid 0x%x", 1325 __func__, pptr->path, tmp); 1326 result = EIO; 1327 goto out; 1328 } else { 1329 pmcs_prt(pwp, PMCS_PRT_INFO, pptr, NULL, 1330 "%s: phy %s already has a device id 0x%x", 1331 __func__, pptr->path, tmp); 1332 } 1333 } 1334 break; 1335 default: 1336 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 1337 "%s: status 0x%x when trying to register device %s", 1338 __func__, status, pptr->path); 1339 result = EIO; 1340 goto out; 1341 } 1342 pptr->device_id = tmp; 1343 pptr->valid_device_id = 1; 1344 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "Phy %s/" SAS_ADDR_FMT 1345 " registered with device_id 0x%x (portid %d)", pptr->path, 1346 SAS_ADDR_PRT(pptr->sas_address), tmp, pptr->portid); 1347 out: 1348 return (result); 1349 } 1350 1351 /* 1352 * Deregister a device (remove a device handle). 1353 * Called with PHY locked. 1354 */ 1355 void 1356 pmcs_deregister_device(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 1357 { 1358 struct pmcwork *pwrk; 1359 uint32_t msg[PMCS_MSG_SIZE], *ptr, status; 1360 uint32_t iomb[(PMCS_QENTRY_SIZE << 1) >> 2]; 1361 int result; 1362 1363 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 1364 if (pwrk == NULL) { 1365 return; 1366 } 1367 1368 pwrk->arg = iomb; 1369 pwrk->dtype = pptr->dtype; 1370 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1371 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1372 if (ptr == NULL) { 1373 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 1374 pmcs_pwork(pwp, pwrk); 1375 return; 1376 } 1377 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 1378 PMCIN_DEREGISTER_DEVICE_HANDLE)); 1379 msg[1] = LE_32(pwrk->htag); 1380 msg[2] = LE_32(pptr->device_id); 1381 pwrk->state = PMCS_WORK_STATE_ONCHIP; 1382 COPY_MESSAGE(ptr, msg, 3); 1383 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 1384 1385 pmcs_unlock_phy(pptr); 1386 WAIT_FOR(pwrk, 250, result); 1387 pmcs_pwork(pwp, pwrk); 1388 pmcs_lock_phy(pptr); 1389 1390 if (result) { 1391 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, pmcs_timeo, __func__); 1392 return; 1393 } 1394 status = LE_32(iomb[2]); 1395 if (status != PMCOUT_STATUS_OK) { 1396 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 1397 "%s: status 0x%x when trying to deregister device %s", 1398 __func__, status, pptr->path); 1399 } else { 1400 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 1401 "%s: device %s deregistered", __func__, pptr->path); 1402 } 1403 1404 pptr->device_id = PMCS_INVALID_DEVICE_ID; 1405 pptr->configured = 0; 1406 pptr->deregister_wait = 0; 1407 pptr->valid_device_id = 0; 1408 } 1409 1410 /* 1411 * Deregister all registered devices. 1412 */ 1413 void 1414 pmcs_deregister_devices(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 1415 { 1416 /* 1417 * Start at the maximum level and walk back to level 0. This only 1418 * gets done during detach after all threads and timers have been 1419 * destroyed. 1420 */ 1421 while (phyp) { 1422 if (phyp->children) { 1423 pmcs_deregister_devices(pwp, phyp->children); 1424 } 1425 pmcs_lock_phy(phyp); 1426 if (phyp->valid_device_id) { 1427 pmcs_deregister_device(pwp, phyp); 1428 } 1429 pmcs_unlock_phy(phyp); 1430 phyp = phyp->sibling; 1431 } 1432 } 1433 1434 /* 1435 * Perform a 'soft' reset on the PMC chip 1436 */ 1437 int 1438 pmcs_soft_reset(pmcs_hw_t *pwp, boolean_t no_restart) 1439 { 1440 uint32_t s2, sfrbits, gsm, rapchk, wapchk, wdpchk, spc, tsmode; 1441 pmcs_phy_t *pptr; 1442 char *msg = NULL; 1443 int i; 1444 1445 /* 1446 * Disable interrupts 1447 */ 1448 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_MASK, 0xffffffff); 1449 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR, 0xffffffff); 1450 1451 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, "%s", __func__); 1452 1453 if (pwp->locks_initted) { 1454 mutex_enter(&pwp->lock); 1455 } 1456 pwp->blocked = 1; 1457 1458 /* 1459 * Clear our softstate copies of the MSGU and IOP heartbeats. 1460 */ 1461 pwp->last_msgu_tick = pwp->last_iop_tick = 0; 1462 1463 /* 1464 * Step 1 1465 */ 1466 s2 = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2); 1467 if ((s2 & PMCS_MSGU_HOST_SOFT_RESET_READY) == 0) { 1468 pmcs_wr_gsm_reg(pwp, RB6_ACCESS, RB6_NMI_SIGNATURE); 1469 pmcs_wr_gsm_reg(pwp, RB6_ACCESS, RB6_NMI_SIGNATURE); 1470 for (i = 0; i < 100; i++) { 1471 s2 = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2) & 1472 PMCS_MSGU_HOST_SOFT_RESET_READY; 1473 if (s2) { 1474 break; 1475 } 1476 drv_usecwait(10000); 1477 } 1478 s2 = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2) & 1479 PMCS_MSGU_HOST_SOFT_RESET_READY; 1480 if (s2 == 0) { 1481 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1482 "%s: PMCS_MSGU_HOST_SOFT_RESET_READY never came " 1483 "ready", __func__); 1484 pmcs_register_dump(pwp); 1485 if ((pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1) & 1486 PMCS_MSGU_CPU_SOFT_RESET_READY) == 0 || 1487 (pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH2) & 1488 PMCS_MSGU_CPU_SOFT_RESET_READY) == 0) { 1489 pwp->state = STATE_DEAD; 1490 pwp->blocked = 0; 1491 if (pwp->locks_initted) { 1492 mutex_exit(&pwp->lock); 1493 } 1494 return (-1); 1495 } 1496 } 1497 } 1498 1499 /* 1500 * Step 2 1501 */ 1502 pmcs_wr_gsm_reg(pwp, NMI_EN_VPE0_IOP, 0); 1503 drv_usecwait(10); 1504 pmcs_wr_gsm_reg(pwp, NMI_EN_VPE0_AAP1, 0); 1505 drv_usecwait(10); 1506 pmcs_wr_topunit(pwp, PMCS_EVENT_INT_ENABLE, 0); 1507 drv_usecwait(10); 1508 pmcs_wr_topunit(pwp, PMCS_EVENT_INT_STAT, 1509 pmcs_rd_topunit(pwp, PMCS_EVENT_INT_STAT)); 1510 drv_usecwait(10); 1511 pmcs_wr_topunit(pwp, PMCS_ERROR_INT_ENABLE, 0); 1512 drv_usecwait(10); 1513 pmcs_wr_topunit(pwp, PMCS_ERROR_INT_STAT, 1514 pmcs_rd_topunit(pwp, PMCS_ERROR_INT_STAT)); 1515 drv_usecwait(10); 1516 1517 sfrbits = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1) & 1518 PMCS_MSGU_AAP_SFR_PROGRESS; 1519 sfrbits ^= PMCS_MSGU_AAP_SFR_PROGRESS; 1520 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "PMCS_MSGU_HOST_SCRATCH0 " 1521 "%08x -> %08x", pmcs_rd_msgunit(pwp, PMCS_MSGU_HOST_SCRATCH0), 1522 HST_SFT_RESET_SIG); 1523 pmcs_wr_msgunit(pwp, PMCS_MSGU_HOST_SCRATCH0, HST_SFT_RESET_SIG); 1524 1525 /* 1526 * Step 3 1527 */ 1528 gsm = pmcs_rd_gsm_reg(pwp, 0, GSM_CFG_AND_RESET); 1529 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "GSM %08x -> %08x", gsm, 1530 gsm & ~PMCS_SOFT_RESET_BITS); 1531 pmcs_wr_gsm_reg(pwp, GSM_CFG_AND_RESET, gsm & ~PMCS_SOFT_RESET_BITS); 1532 1533 /* 1534 * Step 4 1535 */ 1536 rapchk = pmcs_rd_gsm_reg(pwp, 0, READ_ADR_PARITY_CHK_EN); 1537 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "READ_ADR_PARITY_CHK_EN " 1538 "%08x -> %08x", rapchk, 0); 1539 pmcs_wr_gsm_reg(pwp, READ_ADR_PARITY_CHK_EN, 0); 1540 wapchk = pmcs_rd_gsm_reg(pwp, 0, WRITE_ADR_PARITY_CHK_EN); 1541 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "WRITE_ADR_PARITY_CHK_EN " 1542 "%08x -> %08x", wapchk, 0); 1543 pmcs_wr_gsm_reg(pwp, WRITE_ADR_PARITY_CHK_EN, 0); 1544 wdpchk = pmcs_rd_gsm_reg(pwp, 0, WRITE_DATA_PARITY_CHK_EN); 1545 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "WRITE_DATA_PARITY_CHK_EN " 1546 "%08x -> %08x", wdpchk, 0); 1547 pmcs_wr_gsm_reg(pwp, WRITE_DATA_PARITY_CHK_EN, 0); 1548 1549 /* 1550 * Step 5 1551 */ 1552 drv_usecwait(100); 1553 1554 /* 1555 * Step 5.5 (Temporary workaround for 1.07.xx Beta) 1556 */ 1557 tsmode = pmcs_rd_gsm_reg(pwp, 0, PMCS_GPIO_TRISTATE_MODE_ADDR); 1558 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "GPIO TSMODE %08x -> %08x", 1559 tsmode, tsmode & ~(PMCS_GPIO_TSMODE_BIT0|PMCS_GPIO_TSMODE_BIT1)); 1560 pmcs_wr_gsm_reg(pwp, PMCS_GPIO_TRISTATE_MODE_ADDR, 1561 tsmode & ~(PMCS_GPIO_TSMODE_BIT0|PMCS_GPIO_TSMODE_BIT1)); 1562 drv_usecwait(10); 1563 1564 /* 1565 * Step 6 1566 */ 1567 spc = pmcs_rd_topunit(pwp, PMCS_SPC_RESET); 1568 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "SPC_RESET %08x -> %08x", 1569 spc, spc & ~(PCS_IOP_SS_RSTB|PCS_AAP1_SS_RSTB)); 1570 pmcs_wr_topunit(pwp, PMCS_SPC_RESET, 1571 spc & ~(PCS_IOP_SS_RSTB|PCS_AAP1_SS_RSTB)); 1572 drv_usecwait(10); 1573 1574 /* 1575 * Step 7 1576 */ 1577 spc = pmcs_rd_topunit(pwp, PMCS_SPC_RESET); 1578 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "SPC_RESET %08x -> %08x", 1579 spc, spc & ~(BDMA_CORE_RSTB|OSSP_RSTB)); 1580 pmcs_wr_topunit(pwp, PMCS_SPC_RESET, spc & ~(BDMA_CORE_RSTB|OSSP_RSTB)); 1581 1582 /* 1583 * Step 8 1584 */ 1585 drv_usecwait(100); 1586 1587 /* 1588 * Step 9 1589 */ 1590 spc = pmcs_rd_topunit(pwp, PMCS_SPC_RESET); 1591 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "SPC_RESET %08x -> %08x", 1592 spc, spc | (BDMA_CORE_RSTB|OSSP_RSTB)); 1593 pmcs_wr_topunit(pwp, PMCS_SPC_RESET, spc | (BDMA_CORE_RSTB|OSSP_RSTB)); 1594 1595 /* 1596 * Step 10 1597 */ 1598 drv_usecwait(100); 1599 1600 /* 1601 * Step 11 1602 */ 1603 gsm = pmcs_rd_gsm_reg(pwp, 0, GSM_CFG_AND_RESET); 1604 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "GSM %08x -> %08x", gsm, 1605 gsm | PMCS_SOFT_RESET_BITS); 1606 pmcs_wr_gsm_reg(pwp, GSM_CFG_AND_RESET, gsm | PMCS_SOFT_RESET_BITS); 1607 drv_usecwait(10); 1608 1609 /* 1610 * Step 12 1611 */ 1612 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "READ_ADR_PARITY_CHK_EN " 1613 "%08x -> %08x", pmcs_rd_gsm_reg(pwp, 0, READ_ADR_PARITY_CHK_EN), 1614 rapchk); 1615 pmcs_wr_gsm_reg(pwp, READ_ADR_PARITY_CHK_EN, rapchk); 1616 drv_usecwait(10); 1617 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "WRITE_ADR_PARITY_CHK_EN " 1618 "%08x -> %08x", pmcs_rd_gsm_reg(pwp, 0, WRITE_ADR_PARITY_CHK_EN), 1619 wapchk); 1620 pmcs_wr_gsm_reg(pwp, WRITE_ADR_PARITY_CHK_EN, wapchk); 1621 drv_usecwait(10); 1622 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "WRITE_DATA_PARITY_CHK_EN " 1623 "%08x -> %08x", pmcs_rd_gsm_reg(pwp, 0, WRITE_DATA_PARITY_CHK_EN), 1624 wapchk); 1625 pmcs_wr_gsm_reg(pwp, WRITE_DATA_PARITY_CHK_EN, wdpchk); 1626 drv_usecwait(10); 1627 1628 /* 1629 * Step 13 1630 */ 1631 spc = pmcs_rd_topunit(pwp, PMCS_SPC_RESET); 1632 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, "SPC_RESET %08x -> %08x", 1633 spc, spc | (PCS_IOP_SS_RSTB|PCS_AAP1_SS_RSTB)); 1634 pmcs_wr_topunit(pwp, PMCS_SPC_RESET, 1635 spc | (PCS_IOP_SS_RSTB|PCS_AAP1_SS_RSTB)); 1636 1637 /* 1638 * Step 14 1639 */ 1640 drv_usecwait(100); 1641 1642 /* 1643 * Step 15 1644 */ 1645 for (spc = 0, i = 0; i < 1000; i++) { 1646 drv_usecwait(1000); 1647 spc = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1); 1648 if ((spc & PMCS_MSGU_AAP_SFR_PROGRESS) == sfrbits) { 1649 break; 1650 } 1651 } 1652 1653 if ((spc & PMCS_MSGU_AAP_SFR_PROGRESS) != sfrbits) { 1654 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1655 "SFR didn't toggle (sfr 0x%x)", spc); 1656 pwp->state = STATE_DEAD; 1657 pwp->blocked = 0; 1658 if (pwp->locks_initted) { 1659 mutex_exit(&pwp->lock); 1660 } 1661 return (-1); 1662 } 1663 1664 /* 1665 * Step 16 1666 */ 1667 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_MASK, 0xffffffff); 1668 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR, 0xffffffff); 1669 1670 /* 1671 * Wait for up to 5 seconds for AAP state to come either ready or error. 1672 */ 1673 for (i = 0; i < 50; i++) { 1674 spc = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1) & 1675 PMCS_MSGU_AAP_STATE_MASK; 1676 if (spc == PMCS_MSGU_AAP_STATE_ERROR || 1677 spc == PMCS_MSGU_AAP_STATE_READY) { 1678 break; 1679 } 1680 drv_usecwait(100000); 1681 } 1682 spc = pmcs_rd_msgunit(pwp, PMCS_MSGU_SCRATCH1); 1683 if ((spc & PMCS_MSGU_AAP_STATE_MASK) != PMCS_MSGU_AAP_STATE_READY) { 1684 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1685 "soft reset failed (state 0x%x)", spc); 1686 pwp->state = STATE_DEAD; 1687 pwp->blocked = 0; 1688 if (pwp->locks_initted) { 1689 mutex_exit(&pwp->lock); 1690 } 1691 return (-1); 1692 } 1693 1694 /* Clear the firmware log */ 1695 if (pwp->fwlogp) { 1696 bzero(pwp->fwlogp, PMCS_FWLOG_SIZE); 1697 } 1698 1699 /* Reset our queue indices and entries */ 1700 bzero(pwp->shadow_iqpi, sizeof (pwp->shadow_iqpi)); 1701 bzero(pwp->last_iqci, sizeof (pwp->last_iqci)); 1702 bzero(pwp->last_htag, sizeof (pwp->last_htag)); 1703 for (i = 0; i < PMCS_NIQ; i++) { 1704 if (pwp->iqp[i]) { 1705 bzero(pwp->iqp[i], PMCS_QENTRY_SIZE * pwp->ioq_depth); 1706 pmcs_wr_iqpi(pwp, i, 0); 1707 pmcs_wr_iqci(pwp, i, 0); 1708 } 1709 } 1710 for (i = 0; i < PMCS_NOQ; i++) { 1711 if (pwp->oqp[i]) { 1712 bzero(pwp->oqp[i], PMCS_QENTRY_SIZE * pwp->ioq_depth); 1713 pmcs_wr_oqpi(pwp, i, 0); 1714 pmcs_wr_oqci(pwp, i, 0); 1715 } 1716 1717 } 1718 1719 if (pwp->state == STATE_DEAD || pwp->state == STATE_UNPROBING || 1720 pwp->state == STATE_PROBING || pwp->locks_initted == 0) { 1721 pwp->blocked = 0; 1722 if (pwp->locks_initted) { 1723 mutex_exit(&pwp->lock); 1724 } 1725 return (0); 1726 } 1727 1728 /* 1729 * Return at this point if we dont need to startup. 1730 */ 1731 if (no_restart) { 1732 return (0); 1733 } 1734 1735 ASSERT(pwp->locks_initted != 0); 1736 1737 /* 1738 * Flush the target queues and clear each target's PHY 1739 */ 1740 if (pwp->targets) { 1741 for (i = 0; i < pwp->max_dev; i++) { 1742 pmcs_xscsi_t *xp = pwp->targets[i]; 1743 1744 if (xp == NULL) { 1745 continue; 1746 } 1747 1748 mutex_enter(&xp->statlock); 1749 pmcs_flush_target_queues(pwp, xp, PMCS_TGT_ALL_QUEUES); 1750 xp->phy = NULL; 1751 mutex_exit(&xp->statlock); 1752 } 1753 } 1754 1755 /* 1756 * Zero out the ports list, free non root phys, clear root phys 1757 */ 1758 bzero(pwp->ports, sizeof (pwp->ports)); 1759 pmcs_free_all_phys(pwp, pwp->root_phys); 1760 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 1761 pmcs_lock_phy(pptr); 1762 pmcs_clear_phy(pwp, pptr); 1763 pptr->target = NULL; 1764 pmcs_unlock_phy(pptr); 1765 } 1766 1767 /* 1768 * Restore Interrupt Mask 1769 */ 1770 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_MASK, pwp->intr_mask); 1771 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR, 0xffffffff); 1772 1773 pwp->mpi_table_setup = 0; 1774 mutex_exit(&pwp->lock); 1775 1776 /* 1777 * Set up MPI again. 1778 */ 1779 if (pmcs_setup(pwp)) { 1780 msg = "unable to setup MPI tables again"; 1781 goto fail_restart; 1782 } 1783 pmcs_report_fwversion(pwp); 1784 1785 /* 1786 * Restart MPI 1787 */ 1788 if (pmcs_start_mpi(pwp)) { 1789 msg = "unable to restart MPI again"; 1790 goto fail_restart; 1791 } 1792 1793 mutex_enter(&pwp->lock); 1794 SCHEDULE_WORK(pwp, PMCS_WORK_RUN_QUEUES); 1795 mutex_exit(&pwp->lock); 1796 1797 /* 1798 * Run any completions 1799 */ 1800 PMCS_CQ_RUN(pwp); 1801 1802 /* 1803 * Delay 1804 */ 1805 drv_usecwait(1000000); 1806 return (0); 1807 1808 fail_restart: 1809 mutex_enter(&pwp->lock); 1810 pwp->state = STATE_DEAD; 1811 mutex_exit(&pwp->lock); 1812 pmcs_prt(pwp, PMCS_PRT_ERR, NULL, NULL, 1813 "%s: Failed: %s", __func__, msg); 1814 return (-1); 1815 } 1816 1817 1818 /* 1819 * Perform a 'hot' reset, which will soft reset the chip and 1820 * restore the state back to pre-reset context. Called with pwp 1821 * lock held. 1822 */ 1823 int 1824 pmcs_hot_reset(pmcs_hw_t *pwp) 1825 { 1826 pmcs_iport_t *iport; 1827 1828 ASSERT(mutex_owned(&pwp->lock)); 1829 pwp->state = STATE_IN_RESET; 1830 1831 /* 1832 * For any iports on this HBA, report empty target sets and 1833 * then tear them down. 1834 */ 1835 rw_enter(&pwp->iports_lock, RW_READER); 1836 for (iport = list_head(&pwp->iports); iport != NULL; 1837 iport = list_next(&pwp->iports, iport)) { 1838 mutex_enter(&iport->lock); 1839 (void) scsi_hba_tgtmap_set_begin(iport->iss_tgtmap); 1840 (void) scsi_hba_tgtmap_set_end(iport->iss_tgtmap, 0); 1841 pmcs_iport_teardown_phys(iport); 1842 mutex_exit(&iport->lock); 1843 } 1844 rw_exit(&pwp->iports_lock); 1845 1846 /* Grab a register dump, in the event that reset fails */ 1847 pmcs_register_dump_int(pwp); 1848 mutex_exit(&pwp->lock); 1849 1850 /* Ensure discovery is not running before we proceed */ 1851 mutex_enter(&pwp->config_lock); 1852 while (pwp->configuring) { 1853 cv_wait(&pwp->config_cv, &pwp->config_lock); 1854 } 1855 mutex_exit(&pwp->config_lock); 1856 1857 /* Issue soft reset and clean up related softstate */ 1858 if (pmcs_soft_reset(pwp, B_FALSE)) { 1859 /* 1860 * Disable interrupts, in case we got far enough along to 1861 * enable them, then fire off ereport and service impact. 1862 */ 1863 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1864 "%s: failed soft reset", __func__); 1865 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_MASK, 0xffffffff); 1866 pmcs_wr_msgunit(pwp, PMCS_MSGU_OBDB_CLEAR, 0xffffffff); 1867 pmcs_fm_ereport(pwp, DDI_FM_DEVICE_NO_RESPONSE); 1868 ddi_fm_service_impact(pwp->dip, DDI_SERVICE_LOST); 1869 mutex_enter(&pwp->lock); 1870 pwp->state = STATE_DEAD; 1871 return (DDI_FAILURE); 1872 } 1873 1874 mutex_enter(&pwp->lock); 1875 pwp->state = STATE_RUNNING; 1876 mutex_exit(&pwp->lock); 1877 1878 /* 1879 * Finally, restart the phys, which will bring the iports back 1880 * up and eventually result in discovery running. 1881 */ 1882 if (pmcs_start_phys(pwp)) { 1883 /* We should be up and running now, so retry */ 1884 if (pmcs_start_phys(pwp)) { 1885 /* Apparently unable to restart PHYs, fail */ 1886 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 1887 "%s: failed to restart PHYs after soft reset", 1888 __func__); 1889 mutex_enter(&pwp->lock); 1890 return (DDI_FAILURE); 1891 } 1892 } 1893 1894 mutex_enter(&pwp->lock); 1895 return (DDI_SUCCESS); 1896 } 1897 1898 /* 1899 * Reset a device or a logical unit. 1900 */ 1901 int 1902 pmcs_reset_dev(pmcs_hw_t *pwp, pmcs_phy_t *pptr, uint64_t lun) 1903 { 1904 int rval = 0; 1905 1906 if (pptr == NULL) { 1907 return (ENXIO); 1908 } 1909 1910 pmcs_lock_phy(pptr); 1911 if (pptr->dtype == SAS) { 1912 /* 1913 * Some devices do not support SAS_I_T_NEXUS_RESET as 1914 * it is not a mandatory (in SAM4) task management 1915 * function, while LOGIC_UNIT_RESET is mandatory. 1916 * 1917 * The problem here is that we need to iterate over 1918 * all known LUNs to emulate the semantics of 1919 * "RESET_TARGET". 1920 * 1921 * XXX: FIX ME 1922 */ 1923 if (lun == (uint64_t)-1) { 1924 lun = 0; 1925 } 1926 rval = pmcs_ssp_tmf(pwp, pptr, SAS_LOGICAL_UNIT_RESET, 0, lun, 1927 NULL); 1928 } else if (pptr->dtype == SATA) { 1929 if (lun != 0ull) { 1930 pmcs_unlock_phy(pptr); 1931 return (EINVAL); 1932 } 1933 rval = pmcs_reset_phy(pwp, pptr, PMCS_PHYOP_LINK_RESET); 1934 } else { 1935 pmcs_unlock_phy(pptr); 1936 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 1937 "%s: cannot reset a SMP device yet (%s)", 1938 __func__, pptr->path); 1939 return (EINVAL); 1940 } 1941 1942 /* 1943 * Now harvest any commands killed by this action 1944 * by issuing an ABORT for all commands on this device. 1945 * 1946 * We do this even if the the tmf or reset fails (in case there 1947 * are any dead commands around to be harvested *anyway*). 1948 * We don't have to await for the abort to complete. 1949 */ 1950 if (pmcs_abort(pwp, pptr, 0, 1, 0)) { 1951 pptr->abort_pending = 1; 1952 SCHEDULE_WORK(pwp, PMCS_WORK_ABORT_HANDLE); 1953 } 1954 1955 pmcs_unlock_phy(pptr); 1956 return (rval); 1957 } 1958 1959 /* 1960 * Called with PHY locked. 1961 */ 1962 static int 1963 pmcs_get_device_handle(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 1964 { 1965 if (pptr->valid_device_id == 0) { 1966 int result = pmcs_register_device(pwp, pptr); 1967 1968 /* 1969 * If we changed while registering, punt 1970 */ 1971 if (pptr->changed) { 1972 RESTART_DISCOVERY(pwp); 1973 return (-1); 1974 } 1975 1976 /* 1977 * If we had a failure to register, check against errors. 1978 * An ENOMEM error means we just retry (temp resource shortage). 1979 */ 1980 if (result == ENOMEM) { 1981 PHY_CHANGED(pwp, pptr); 1982 RESTART_DISCOVERY(pwp); 1983 return (-1); 1984 } 1985 1986 /* 1987 * An ETIMEDOUT error means we retry (if our counter isn't 1988 * exhausted) 1989 */ 1990 if (result == ETIMEDOUT) { 1991 if (ddi_get_lbolt() < pptr->config_stop) { 1992 PHY_CHANGED(pwp, pptr); 1993 RESTART_DISCOVERY(pwp); 1994 } else { 1995 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 1996 "%s: Retries exhausted for %s, killing", 1997 __func__, pptr->path); 1998 pptr->config_stop = 0; 1999 pmcs_kill_changed(pwp, pptr, 0); 2000 } 2001 return (-1); 2002 } 2003 /* 2004 * Other errors or no valid device id is fatal, but don't 2005 * preclude a future action. 2006 */ 2007 if (result || pptr->valid_device_id == 0) { 2008 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 2009 "%s: %s could not be registered", __func__, 2010 pptr->path); 2011 return (-1); 2012 } 2013 } 2014 return (0); 2015 } 2016 2017 int 2018 pmcs_iport_tgtmap_create(pmcs_iport_t *iport) 2019 { 2020 ASSERT(iport); 2021 if (iport == NULL) 2022 return (B_FALSE); 2023 2024 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s", __func__); 2025 2026 /* create target map */ 2027 if (scsi_hba_tgtmap_create(iport->dip, SCSI_TM_FULLSET, 2028 tgtmap_csync_usec, tgtmap_stable_usec, (void *)iport, 2029 pmcs_tgtmap_activate_cb, pmcs_tgtmap_deactivate_cb, 2030 &iport->iss_tgtmap) != DDI_SUCCESS) { 2031 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG, NULL, NULL, 2032 "%s: failed to create tgtmap", __func__); 2033 return (B_FALSE); 2034 } 2035 return (B_TRUE); 2036 } 2037 2038 int 2039 pmcs_iport_tgtmap_destroy(pmcs_iport_t *iport) 2040 { 2041 ASSERT(iport && iport->iss_tgtmap); 2042 if ((iport == NULL) || (iport->iss_tgtmap == NULL)) 2043 return (B_FALSE); 2044 2045 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s", __func__); 2046 2047 /* destroy target map */ 2048 scsi_hba_tgtmap_destroy(iport->iss_tgtmap); 2049 return (B_TRUE); 2050 } 2051 2052 /* 2053 * Remove all phys from an iport's phymap and empty it's phylist. 2054 * Called when a port has been reset by the host (see pmcs_intr.c) 2055 * or prior to issuing a soft reset if we detect a stall on the chip 2056 * (see pmcs_attach.c). 2057 */ 2058 void 2059 pmcs_iport_teardown_phys(pmcs_iport_t *iport) 2060 { 2061 pmcs_hw_t *pwp; 2062 sas_phymap_phys_t *phys; 2063 int phynum; 2064 2065 ASSERT(iport); 2066 ASSERT(mutex_owned(&iport->lock)); 2067 pwp = iport->pwp; 2068 ASSERT(pwp); 2069 2070 /* 2071 * Remove all phys from the iport handle's phy list, unset its 2072 * primary phy and update its state. 2073 */ 2074 pmcs_remove_phy_from_iport(iport, NULL); 2075 iport->pptr = NULL; 2076 iport->ua_state = UA_PEND_DEACTIVATE; 2077 2078 /* Remove all phys from the phymap */ 2079 phys = sas_phymap_ua2phys(pwp->hss_phymap, iport->ua); 2080 if (phys) { 2081 while ((phynum = sas_phymap_phys_next(phys)) != -1) { 2082 (void) sas_phymap_phy_rem(pwp->hss_phymap, phynum); 2083 } 2084 sas_phymap_phys_free(phys); 2085 } 2086 } 2087 2088 /* 2089 * Query the phymap and populate the iport handle passed in. 2090 * Called with iport lock held. 2091 */ 2092 int 2093 pmcs_iport_configure_phys(pmcs_iport_t *iport) 2094 { 2095 pmcs_hw_t *pwp; 2096 pmcs_phy_t *pptr; 2097 sas_phymap_phys_t *phys; 2098 int phynum; 2099 int inst; 2100 2101 ASSERT(iport); 2102 ASSERT(mutex_owned(&iport->lock)); 2103 pwp = iport->pwp; 2104 ASSERT(pwp); 2105 inst = ddi_get_instance(iport->dip); 2106 2107 mutex_enter(&pwp->lock); 2108 ASSERT(pwp->root_phys != NULL); 2109 2110 /* 2111 * Query the phymap regarding the phys in this iport and populate 2112 * the iport's phys list. Hereafter this list is maintained via 2113 * port up and down events in pmcs_intr.c 2114 */ 2115 ASSERT(list_is_empty(&iport->phys)); 2116 phys = sas_phymap_ua2phys(pwp->hss_phymap, iport->ua); 2117 ASSERT(phys != NULL); 2118 while ((phynum = sas_phymap_phys_next(phys)) != -1) { 2119 /* Grab the phy pointer from root_phys */ 2120 pptr = pwp->root_phys + phynum; 2121 ASSERT(pptr); 2122 pmcs_lock_phy(pptr); 2123 ASSERT(pptr->phynum == phynum); 2124 2125 /* 2126 * Set a back pointer in the phy to this iport. 2127 */ 2128 pptr->iport = iport; 2129 2130 /* 2131 * If this phy is the primary, set a pointer to it on our 2132 * iport handle, and set our portid from it. 2133 */ 2134 if (!pptr->subsidiary) { 2135 iport->pptr = pptr; 2136 iport->portid = pptr->portid; 2137 } 2138 2139 /* 2140 * Finally, insert the phy into our list 2141 */ 2142 pmcs_unlock_phy(pptr); 2143 pmcs_add_phy_to_iport(iport, pptr); 2144 2145 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "%s: found " 2146 "phy %d [0x%p] on iport%d, refcnt(%d)", __func__, phynum, 2147 (void *)pptr, inst, iport->refcnt); 2148 } 2149 mutex_exit(&pwp->lock); 2150 sas_phymap_phys_free(phys); 2151 RESTART_DISCOVERY(pwp); 2152 return (DDI_SUCCESS); 2153 } 2154 2155 /* 2156 * Return the iport that ua is associated with, or NULL. If an iport is 2157 * returned, it will be held and the caller must release the hold. 2158 */ 2159 static pmcs_iport_t * 2160 pmcs_get_iport_by_ua(pmcs_hw_t *pwp, char *ua) 2161 { 2162 pmcs_iport_t *iport = NULL; 2163 2164 rw_enter(&pwp->iports_lock, RW_READER); 2165 for (iport = list_head(&pwp->iports); 2166 iport != NULL; 2167 iport = list_next(&pwp->iports, iport)) { 2168 mutex_enter(&iport->lock); 2169 if (strcmp(iport->ua, ua) == 0) { 2170 mutex_exit(&iport->lock); 2171 pmcs_hold_iport(iport); 2172 break; 2173 } 2174 mutex_exit(&iport->lock); 2175 } 2176 rw_exit(&pwp->iports_lock); 2177 2178 return (iport); 2179 } 2180 2181 /* 2182 * Return the iport that pptr is associated with, or NULL. 2183 * If an iport is returned, there is a hold that the caller must release. 2184 */ 2185 pmcs_iport_t * 2186 pmcs_get_iport_by_wwn(pmcs_hw_t *pwp, uint64_t wwn) 2187 { 2188 pmcs_iport_t *iport = NULL; 2189 char *ua; 2190 2191 ua = sas_phymap_lookup_ua(pwp->hss_phymap, pwp->sas_wwns[0], wwn); 2192 if (ua) { 2193 iport = pmcs_get_iport_by_ua(pwp, ua); 2194 if (iport) { 2195 mutex_enter(&iport->lock); 2196 pmcs_iport_active(iport); 2197 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "%s: " 2198 "found iport [0x%p] on ua (%s), refcnt (%d)", 2199 __func__, (void *)iport, ua, iport->refcnt); 2200 mutex_exit(&iport->lock); 2201 } 2202 } 2203 2204 return (iport); 2205 } 2206 2207 /* 2208 * Promote the next phy on this port to primary, and return it. 2209 * Called when the primary PHY on a port is going down, but the port 2210 * remains up (see pmcs_intr.c). 2211 */ 2212 pmcs_phy_t * 2213 pmcs_promote_next_phy(pmcs_phy_t *prev_primary) 2214 { 2215 pmcs_hw_t *pwp; 2216 pmcs_iport_t *iport; 2217 pmcs_phy_t *pptr, *child; 2218 int portid; 2219 2220 pmcs_lock_phy(prev_primary); 2221 portid = prev_primary->portid; 2222 iport = prev_primary->iport; 2223 pwp = prev_primary->pwp; 2224 2225 /* Use the first available phy in this port */ 2226 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 2227 if ((pptr->portid == portid) && (pptr != prev_primary)) { 2228 mutex_enter(&pptr->phy_lock); 2229 break; 2230 } 2231 } 2232 2233 if (pptr == NULL) { 2234 pmcs_unlock_phy(prev_primary); 2235 return (NULL); 2236 } 2237 2238 if (iport) { 2239 mutex_enter(&iport->lock); 2240 iport->pptr = pptr; 2241 mutex_exit(&iport->lock); 2242 } 2243 2244 /* Update the phy handle with the data from the previous primary */ 2245 pptr->children = prev_primary->children; 2246 child = pptr->children; 2247 while (child) { 2248 child->parent = pptr; 2249 child = child->sibling; 2250 } 2251 pptr->ncphy = prev_primary->ncphy; 2252 pptr->width = prev_primary->width; 2253 pptr->dtype = prev_primary->dtype; 2254 pptr->pend_dtype = prev_primary->pend_dtype; 2255 pptr->tolerates_sas2 = prev_primary->tolerates_sas2; 2256 pptr->atdt = prev_primary->atdt; 2257 pptr->portid = prev_primary->portid; 2258 pptr->link_rate = prev_primary->link_rate; 2259 pptr->configured = prev_primary->configured; 2260 pptr->iport = prev_primary->iport; 2261 pptr->target = prev_primary->target; 2262 if (pptr->target) { 2263 pptr->target->phy = pptr; 2264 } 2265 2266 /* Update the phy mask properties for the affected PHYs */ 2267 /* Clear the current values... */ 2268 pmcs_update_phy_pm_props(pptr, pptr->att_port_pm_tmp, 2269 pptr->tgt_port_pm_tmp, B_FALSE); 2270 /* ...replace with the values from prev_primary... */ 2271 pmcs_update_phy_pm_props(pptr, prev_primary->att_port_pm_tmp, 2272 prev_primary->tgt_port_pm_tmp, B_TRUE); 2273 /* ...then clear prev_primary's PHY values from the new primary */ 2274 pmcs_update_phy_pm_props(pptr, prev_primary->att_port_pm, 2275 prev_primary->tgt_port_pm, B_FALSE); 2276 /* Clear the prev_primary's values */ 2277 pmcs_update_phy_pm_props(prev_primary, prev_primary->att_port_pm_tmp, 2278 prev_primary->tgt_port_pm_tmp, B_FALSE); 2279 2280 pptr->subsidiary = 0; 2281 2282 prev_primary->subsidiary = 1; 2283 prev_primary->children = NULL; 2284 prev_primary->target = NULL; 2285 pptr->device_id = prev_primary->device_id; 2286 pptr->valid_device_id = prev_primary->valid_device_id; 2287 pmcs_unlock_phy(prev_primary); 2288 2289 /* 2290 * We call pmcs_unlock_phy() on pptr because it now contains the 2291 * list of children. 2292 */ 2293 pmcs_unlock_phy(pptr); 2294 2295 return (pptr); 2296 } 2297 2298 void 2299 pmcs_hold_iport(pmcs_iport_t *iport) 2300 { 2301 /* 2302 * Grab a reference to this iport. 2303 */ 2304 ASSERT(iport); 2305 mutex_enter(&iport->refcnt_lock); 2306 iport->refcnt++; 2307 mutex_exit(&iport->refcnt_lock); 2308 2309 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG2, NULL, NULL, "%s: iport " 2310 "[0x%p] refcnt (%d)", __func__, (void *)iport, iport->refcnt); 2311 } 2312 2313 void 2314 pmcs_rele_iport(pmcs_iport_t *iport) 2315 { 2316 /* 2317 * Release a refcnt on this iport. If this is the last reference, 2318 * signal the potential waiter in pmcs_iport_unattach(). 2319 */ 2320 ASSERT(iport->refcnt > 0); 2321 mutex_enter(&iport->refcnt_lock); 2322 iport->refcnt--; 2323 mutex_exit(&iport->refcnt_lock); 2324 if (iport->refcnt == 0) { 2325 cv_signal(&iport->refcnt_cv); 2326 } 2327 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG2, NULL, NULL, "%s: iport " 2328 "[0x%p] refcnt (%d)", __func__, (void *)iport, iport->refcnt); 2329 } 2330 2331 void 2332 pmcs_phymap_activate(void *arg, char *ua, void **privp) 2333 { 2334 _NOTE(ARGUNUSED(privp)); 2335 pmcs_hw_t *pwp = arg; 2336 pmcs_iport_t *iport = NULL; 2337 2338 mutex_enter(&pwp->lock); 2339 if ((pwp->state == STATE_UNPROBING) || (pwp->state == STATE_DEAD) || 2340 (pwp->state == STATE_IN_RESET)) { 2341 mutex_exit(&pwp->lock); 2342 return; 2343 } 2344 pwp->phymap_active++; 2345 mutex_exit(&pwp->lock); 2346 2347 if (scsi_hba_iportmap_iport_add(pwp->hss_iportmap, ua, NULL) != 2348 DDI_SUCCESS) { 2349 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s: failed to " 2350 "add iport handle on unit address [%s]", __func__, ua); 2351 } else { 2352 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s: " 2353 "phymap_active count (%d), added iport handle on unit " 2354 "address [%s]", __func__, pwp->phymap_active, ua); 2355 } 2356 2357 /* Set the HBA softstate as our private data for this unit address */ 2358 *privp = (void *)pwp; 2359 2360 /* 2361 * We are waiting on attach for this iport node, unless it is still 2362 * attached. This can happen if a consumer has an outstanding open 2363 * on our iport node, but the port is down. If this is the case, we 2364 * need to configure our iport here for reuse. 2365 */ 2366 iport = pmcs_get_iport_by_ua(pwp, ua); 2367 if (iport) { 2368 mutex_enter(&iport->lock); 2369 if (pmcs_iport_configure_phys(iport) != DDI_SUCCESS) { 2370 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "%s: " 2371 "failed to configure phys on iport [0x%p] at " 2372 "unit address (%s)", __func__, (void *)iport, ua); 2373 } 2374 pmcs_iport_active(iport); 2375 pmcs_smhba_add_iport_prop(iport, DATA_TYPE_INT32, PMCS_NUM_PHYS, 2376 &iport->nphy); 2377 mutex_exit(&iport->lock); 2378 pmcs_rele_iport(iport); 2379 } 2380 2381 } 2382 2383 void 2384 pmcs_phymap_deactivate(void *arg, char *ua, void *privp) 2385 { 2386 _NOTE(ARGUNUSED(privp)); 2387 pmcs_hw_t *pwp = arg; 2388 pmcs_iport_t *iport; 2389 2390 mutex_enter(&pwp->lock); 2391 pwp->phymap_active--; 2392 mutex_exit(&pwp->lock); 2393 2394 if (scsi_hba_iportmap_iport_remove(pwp->hss_iportmap, ua) != 2395 DDI_SUCCESS) { 2396 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s: failed to " 2397 "remove iport handle on unit address [%s]", __func__, ua); 2398 } else { 2399 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, "%s: " 2400 "phymap_active count (%d), removed iport handle on unit " 2401 "address [%s]", __func__, pwp->phymap_active, ua); 2402 } 2403 2404 iport = pmcs_get_iport_by_ua(pwp, ua); 2405 2406 if (iport == NULL) { 2407 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "%s: failed " 2408 "lookup of iport handle on unit addr (%s)", __func__, ua); 2409 return; 2410 } 2411 2412 mutex_enter(&iport->lock); 2413 iport->ua_state = UA_INACTIVE; 2414 iport->portid = PMCS_IPORT_INVALID_PORT_ID; 2415 pmcs_remove_phy_from_iport(iport, NULL); 2416 mutex_exit(&iport->lock); 2417 pmcs_rele_iport(iport); 2418 } 2419 2420 /* 2421 * Top-level discovery function 2422 */ 2423 void 2424 pmcs_discover(pmcs_hw_t *pwp) 2425 { 2426 pmcs_phy_t *pptr; 2427 pmcs_phy_t *root_phy; 2428 2429 DTRACE_PROBE2(pmcs__discover__entry, ulong_t, pwp->work_flags, 2430 boolean_t, pwp->config_changed); 2431 2432 mutex_enter(&pwp->lock); 2433 2434 if (pwp->state != STATE_RUNNING) { 2435 mutex_exit(&pwp->lock); 2436 return; 2437 } 2438 2439 /* Ensure we have at least one phymap active */ 2440 if (pwp->phymap_active == 0) { 2441 mutex_exit(&pwp->lock); 2442 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2443 "%s: phymap inactive, exiting", __func__); 2444 return; 2445 } 2446 2447 mutex_exit(&pwp->lock); 2448 2449 /* 2450 * If no iports have attached, but we have PHYs that are up, we 2451 * are waiting for iport attach to complete. Restart discovery. 2452 */ 2453 rw_enter(&pwp->iports_lock, RW_READER); 2454 if (!pwp->iports_attached) { 2455 rw_exit(&pwp->iports_lock); 2456 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2457 "%s: no iports attached, retry discovery", __func__); 2458 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 2459 return; 2460 } 2461 rw_exit(&pwp->iports_lock); 2462 2463 mutex_enter(&pwp->config_lock); 2464 if (pwp->configuring) { 2465 mutex_exit(&pwp->config_lock); 2466 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2467 "%s: configuration already in progress", __func__); 2468 return; 2469 } 2470 2471 if (pmcs_acquire_scratch(pwp, B_FALSE)) { 2472 mutex_exit(&pwp->config_lock); 2473 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2474 "%s: cannot allocate scratch", __func__); 2475 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 2476 return; 2477 } 2478 2479 pwp->configuring = 1; 2480 pwp->config_changed = B_FALSE; 2481 mutex_exit(&pwp->config_lock); 2482 2483 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "Discovery begin"); 2484 2485 /* 2486 * First, tell SCSA that we're beginning set operations. 2487 */ 2488 pmcs_begin_observations(pwp); 2489 2490 /* 2491 * The order of the following traversals is important. 2492 * 2493 * The first one checks for changed expanders. 2494 * 2495 * The second one aborts commands for dead devices and deregisters them. 2496 * 2497 * The third one clears the contents of dead expanders from the tree 2498 * 2499 * The fourth one clears now dead devices in expanders that remain. 2500 */ 2501 2502 /* 2503 * 1. Check expanders marked changed (but not dead) to see if they still 2504 * have the same number of phys and the same SAS address. Mark them, 2505 * their subsidiary phys (if wide) and their descendents dead if 2506 * anything has changed. Check the devices they contain to see if 2507 * *they* have changed. If they've changed from type NOTHING we leave 2508 * them marked changed to be configured later (picking up a new SAS 2509 * address and link rate if possible). Otherwise, any change in type, 2510 * SAS address or removal of target role will cause us to mark them 2511 * (and their descendents) as dead (and cause any pending commands 2512 * and associated devices to be removed). 2513 * 2514 * NOTE: We don't want to bail on discovery if the config has 2515 * changed until *after* we run pmcs_kill_devices. 2516 */ 2517 root_phy = pwp->root_phys; 2518 pmcs_check_expanders(pwp, root_phy); 2519 2520 /* 2521 * 2. Descend the tree looking for dead devices and kill them 2522 * by aborting all active commands and then deregistering them. 2523 */ 2524 if (pmcs_kill_devices(pwp, root_phy)) { 2525 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2526 "%s: pmcs_kill_devices failed!", __func__); 2527 } 2528 2529 /* 2530 * 3. Check for dead expanders and remove their children from the tree. 2531 * By the time we get here, the devices and commands for them have 2532 * already been terminated and removed. 2533 * 2534 * We do this independent of the configuration count changing so we can 2535 * free any dead device PHYs that were discovered while checking 2536 * expanders. We ignore any subsidiary phys as pmcs_clear_expander 2537 * will take care of those. 2538 * 2539 * NOTE: pmcs_clear_expander requires softstate lock 2540 */ 2541 mutex_enter(&pwp->lock); 2542 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 2543 /* 2544 * Call pmcs_clear_expander for every root PHY. It will 2545 * recurse and determine which (if any) expanders actually 2546 * need to be cleared. 2547 */ 2548 pmcs_lock_phy(pptr); 2549 pmcs_clear_expander(pwp, pptr, 0); 2550 pmcs_unlock_phy(pptr); 2551 } 2552 mutex_exit(&pwp->lock); 2553 2554 /* 2555 * 4. Check for dead devices and nullify them. By the time we get here, 2556 * the devices and commands for them have already been terminated 2557 * and removed. This is different from step 2 in that this just nulls 2558 * phys that are part of expanders that are still here but used to 2559 * be something but are no longer something (e.g., after a pulled 2560 * disk drive). Note that dead expanders had their contained phys 2561 * removed from the tree- here, the expanders themselves are 2562 * nullified (unless they were removed by being contained in another 2563 * expander phy). 2564 */ 2565 pmcs_clear_phys(pwp, root_phy); 2566 2567 /* 2568 * 5. Now check for and configure new devices. 2569 */ 2570 if (pmcs_configure_new_devices(pwp, root_phy)) { 2571 goto restart; 2572 } 2573 2574 out: 2575 DTRACE_PROBE2(pmcs__discover__exit, ulong_t, pwp->work_flags, 2576 boolean_t, pwp->config_changed); 2577 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, "Discovery end"); 2578 2579 mutex_enter(&pwp->config_lock); 2580 2581 if (pwp->config_changed == B_FALSE) { 2582 /* 2583 * Observation is stable, report what we currently see to 2584 * the tgtmaps for delta processing. Start by setting 2585 * BEGIN on all tgtmaps. 2586 */ 2587 mutex_exit(&pwp->config_lock); 2588 if (pmcs_report_observations(pwp) == B_FALSE) { 2589 goto restart; 2590 } 2591 mutex_enter(&pwp->config_lock); 2592 } else { 2593 /* 2594 * If config_changed is TRUE, we need to reschedule 2595 * discovery now. 2596 */ 2597 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2598 "%s: Config has changed, will re-run discovery", __func__); 2599 SCHEDULE_WORK(pwp, PMCS_WORK_DISCOVER); 2600 } 2601 2602 pmcs_release_scratch(pwp); 2603 if (!pwp->quiesced) { 2604 pwp->blocked = 0; 2605 } 2606 pwp->configuring = 0; 2607 cv_signal(&pwp->config_cv); 2608 mutex_exit(&pwp->config_lock); 2609 2610 #ifdef DEBUG 2611 pptr = pmcs_find_phy_needing_work(pwp, pwp->root_phys); 2612 if (pptr != NULL) { 2613 if (!WORK_IS_SCHEDULED(pwp, PMCS_WORK_DISCOVER)) { 2614 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 2615 "PHY %s dead=%d changed=%d configured=%d " 2616 "but no work scheduled", pptr->path, pptr->dead, 2617 pptr->changed, pptr->configured); 2618 } 2619 pmcs_unlock_phy(pptr); 2620 } 2621 #endif 2622 2623 return; 2624 2625 restart: 2626 /* Clean up and restart discovery */ 2627 pmcs_release_scratch(pwp); 2628 pmcs_flush_observations(pwp); 2629 mutex_enter(&pwp->config_lock); 2630 pwp->configuring = 0; 2631 cv_signal(&pwp->config_cv); 2632 RESTART_DISCOVERY_LOCKED(pwp); 2633 mutex_exit(&pwp->config_lock); 2634 } 2635 2636 /* 2637 * Return any PHY that needs to have scheduled work done. The PHY is returned 2638 * locked. 2639 */ 2640 static pmcs_phy_t * 2641 pmcs_find_phy_needing_work(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 2642 { 2643 pmcs_phy_t *cphyp, *pnext; 2644 2645 while (pptr) { 2646 pmcs_lock_phy(pptr); 2647 2648 if (pptr->changed || (pptr->dead && pptr->valid_device_id)) { 2649 return (pptr); 2650 } 2651 2652 pnext = pptr->sibling; 2653 2654 if (pptr->children) { 2655 cphyp = pptr->children; 2656 pmcs_unlock_phy(pptr); 2657 cphyp = pmcs_find_phy_needing_work(pwp, cphyp); 2658 if (cphyp) { 2659 return (cphyp); 2660 } 2661 } else { 2662 pmcs_unlock_phy(pptr); 2663 } 2664 2665 pptr = pnext; 2666 } 2667 2668 return (NULL); 2669 } 2670 2671 /* 2672 * We may (or may not) report observations to SCSA. This is prefaced by 2673 * issuing a set_begin for each iport target map. 2674 */ 2675 static void 2676 pmcs_begin_observations(pmcs_hw_t *pwp) 2677 { 2678 pmcs_iport_t *iport; 2679 scsi_hba_tgtmap_t *tgtmap; 2680 2681 rw_enter(&pwp->iports_lock, RW_READER); 2682 for (iport = list_head(&pwp->iports); iport != NULL; 2683 iport = list_next(&pwp->iports, iport)) { 2684 /* 2685 * Unless we have at least one phy up, skip this iport. 2686 * Note we don't need to lock the iport for report_skip 2687 * since it is only used here. We are doing the skip so that 2688 * the phymap and iportmap stabilization times are honored - 2689 * giving us the ability to recover port operation within the 2690 * stabilization time without unconfiguring targets using the 2691 * port. 2692 */ 2693 if (!sas_phymap_uahasphys(pwp->hss_phymap, iport->ua)) { 2694 iport->report_skip = 1; 2695 continue; /* skip set_begin */ 2696 } 2697 iport->report_skip = 0; 2698 2699 tgtmap = iport->iss_tgtmap; 2700 ASSERT(tgtmap); 2701 if (scsi_hba_tgtmap_set_begin(tgtmap) != DDI_SUCCESS) { 2702 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2703 "%s: cannot set_begin tgtmap ", __func__); 2704 rw_exit(&pwp->iports_lock); 2705 return; 2706 } 2707 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2708 "%s: set begin on tgtmap [0x%p]", __func__, (void *)tgtmap); 2709 } 2710 rw_exit(&pwp->iports_lock); 2711 } 2712 2713 /* 2714 * Tell SCSA to flush the observations we've already sent (if any), as they 2715 * are no longer valid. 2716 */ 2717 static void 2718 pmcs_flush_observations(pmcs_hw_t *pwp) 2719 { 2720 pmcs_iport_t *iport; 2721 scsi_hba_tgtmap_t *tgtmap; 2722 2723 rw_enter(&pwp->iports_lock, RW_READER); 2724 for (iport = list_head(&pwp->iports); iport != NULL; 2725 iport = list_next(&pwp->iports, iport)) { 2726 /* 2727 * Skip this iport if it has no PHYs up. 2728 */ 2729 if (!sas_phymap_uahasphys(pwp->hss_phymap, iport->ua)) { 2730 continue; 2731 } 2732 2733 tgtmap = iport->iss_tgtmap; 2734 ASSERT(tgtmap); 2735 if (scsi_hba_tgtmap_set_flush(tgtmap) != DDI_SUCCESS) { 2736 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2737 "%s: Failed set_flush on tgtmap 0x%p", __func__, 2738 (void *)tgtmap); 2739 } else { 2740 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2741 "%s: set flush on tgtmap 0x%p", __func__, 2742 (void *)tgtmap); 2743 } 2744 } 2745 rw_exit(&pwp->iports_lock); 2746 } 2747 2748 /* 2749 * Report current observations to SCSA. 2750 */ 2751 static boolean_t 2752 pmcs_report_observations(pmcs_hw_t *pwp) 2753 { 2754 pmcs_iport_t *iport; 2755 scsi_hba_tgtmap_t *tgtmap; 2756 char *ap; 2757 pmcs_phy_t *pptr; 2758 uint64_t wwn; 2759 2760 /* 2761 * Observation is stable, report what we currently see to the tgtmaps 2762 * for delta processing. 2763 */ 2764 pptr = pwp->root_phys; 2765 2766 while (pptr) { 2767 pmcs_lock_phy(pptr); 2768 2769 /* 2770 * Skip PHYs that have nothing attached or are dead. 2771 */ 2772 if ((pptr->dtype == NOTHING) || pptr->dead) { 2773 pmcs_unlock_phy(pptr); 2774 pptr = pptr->sibling; 2775 continue; 2776 } 2777 2778 if (pptr->changed) { 2779 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 2780 "%s: oops, PHY %s changed; restart discovery", 2781 __func__, pptr->path); 2782 pmcs_unlock_phy(pptr); 2783 return (B_FALSE); 2784 } 2785 2786 /* 2787 * Get the iport for this root PHY, then call the helper 2788 * to report observations for this iport's targets 2789 */ 2790 wwn = pmcs_barray2wwn(pptr->sas_address); 2791 pmcs_unlock_phy(pptr); 2792 iport = pmcs_get_iport_by_wwn(pwp, wwn); 2793 if (iport == NULL) { 2794 /* No iport for this tgt */ 2795 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 2796 "%s: no iport for this target", __func__); 2797 pptr = pptr->sibling; 2798 continue; 2799 } 2800 2801 pmcs_lock_phy(pptr); 2802 if (!iport->report_skip) { 2803 if (pmcs_report_iport_observations( 2804 pwp, iport, pptr) == B_FALSE) { 2805 pmcs_rele_iport(iport); 2806 pmcs_unlock_phy(pptr); 2807 return (B_FALSE); 2808 } 2809 } 2810 pmcs_rele_iport(iport); 2811 pmcs_unlock_phy(pptr); 2812 pptr = pptr->sibling; 2813 } 2814 2815 /* 2816 * The observation is complete, end sets. Note we will skip any 2817 * iports that are active, but have no PHYs in them (i.e. awaiting 2818 * unconfigure). Set to restart discovery if we find this. 2819 */ 2820 rw_enter(&pwp->iports_lock, RW_READER); 2821 for (iport = list_head(&pwp->iports); 2822 iport != NULL; 2823 iport = list_next(&pwp->iports, iport)) { 2824 2825 if (iport->report_skip) 2826 continue; /* skip set_end */ 2827 2828 tgtmap = iport->iss_tgtmap; 2829 ASSERT(tgtmap); 2830 if (scsi_hba_tgtmap_set_end(tgtmap, 0) != DDI_SUCCESS) { 2831 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2832 "%s: cannot set_end tgtmap ", __func__); 2833 rw_exit(&pwp->iports_lock); 2834 return (B_FALSE); 2835 } 2836 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2837 "%s: set end on tgtmap [0x%p]", __func__, (void *)tgtmap); 2838 } 2839 2840 /* 2841 * Now that discovery is complete, set up the necessary 2842 * DDI properties on each iport node. 2843 */ 2844 for (iport = list_head(&pwp->iports); iport != NULL; 2845 iport = list_next(&pwp->iports, iport)) { 2846 /* Set up the 'attached-port' property on the iport */ 2847 ap = kmem_zalloc(PMCS_MAX_UA_SIZE, KM_SLEEP); 2848 mutex_enter(&iport->lock); 2849 pptr = iport->pptr; 2850 mutex_exit(&iport->lock); 2851 if (pptr == NULL) { 2852 /* 2853 * This iport is down, but has not been 2854 * removed from our list (unconfigured). 2855 * Set our value to '0'. 2856 */ 2857 (void) snprintf(ap, 1, "%s", "0"); 2858 } else { 2859 /* Otherwise, set it to remote phy's wwn */ 2860 pmcs_lock_phy(pptr); 2861 wwn = pmcs_barray2wwn(pptr->sas_address); 2862 (void) scsi_wwn_to_wwnstr(wwn, 1, ap); 2863 pmcs_unlock_phy(pptr); 2864 } 2865 if (ndi_prop_update_string(DDI_DEV_T_NONE, iport->dip, 2866 SCSI_ADDR_PROP_ATTACHED_PORT, ap) != DDI_SUCCESS) { 2867 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "%s: Failed " 2868 "to set prop ("SCSI_ADDR_PROP_ATTACHED_PORT")", 2869 __func__); 2870 } 2871 kmem_free(ap, PMCS_MAX_UA_SIZE); 2872 } 2873 rw_exit(&pwp->iports_lock); 2874 2875 return (B_TRUE); 2876 } 2877 2878 /* 2879 * Report observations into a particular iport's target map 2880 * 2881 * Called with phyp (and all descendents) locked 2882 */ 2883 static boolean_t 2884 pmcs_report_iport_observations(pmcs_hw_t *pwp, pmcs_iport_t *iport, 2885 pmcs_phy_t *phyp) 2886 { 2887 pmcs_phy_t *lphyp; 2888 scsi_hba_tgtmap_t *tgtmap; 2889 scsi_tgtmap_tgt_type_t tgt_type; 2890 char *ua; 2891 uint64_t wwn; 2892 2893 tgtmap = iport->iss_tgtmap; 2894 ASSERT(tgtmap); 2895 2896 lphyp = phyp; 2897 while (lphyp) { 2898 switch (lphyp->dtype) { 2899 default: /* Skip unknown PHYs. */ 2900 /* for non-root phys, skip to sibling */ 2901 goto next_phy; 2902 2903 case SATA: 2904 case SAS: 2905 tgt_type = SCSI_TGT_SCSI_DEVICE; 2906 break; 2907 2908 case EXPANDER: 2909 tgt_type = SCSI_TGT_SMP_DEVICE; 2910 break; 2911 } 2912 2913 if (lphyp->dead || !lphyp->configured) { 2914 goto next_phy; 2915 } 2916 2917 /* 2918 * Validate the PHY's SAS address 2919 */ 2920 if (((lphyp->sas_address[0] & 0xf0) >> 4) != NAA_IEEE_REG) { 2921 pmcs_prt(pwp, PMCS_PRT_ERR, lphyp, NULL, 2922 "PHY 0x%p (%s) has invalid SAS address; " 2923 "will not enumerate", (void *)lphyp, lphyp->path); 2924 goto next_phy; 2925 } 2926 2927 wwn = pmcs_barray2wwn(lphyp->sas_address); 2928 ua = scsi_wwn_to_wwnstr(wwn, 1, NULL); 2929 2930 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, lphyp, NULL, 2931 "iport_observation: adding %s on tgtmap [0x%p] phy [0x%p]", 2932 ua, (void *)tgtmap, (void*)lphyp); 2933 2934 if (scsi_hba_tgtmap_set_add(tgtmap, tgt_type, ua, NULL) != 2935 DDI_SUCCESS) { 2936 pmcs_prt(pwp, PMCS_PRT_DEBUG_MAP, NULL, NULL, 2937 "%s: failed to add address %s", __func__, ua); 2938 scsi_free_wwnstr(ua); 2939 return (B_FALSE); 2940 } 2941 scsi_free_wwnstr(ua); 2942 2943 if (lphyp->children) { 2944 if (pmcs_report_iport_observations(pwp, iport, 2945 lphyp->children) == B_FALSE) { 2946 return (B_FALSE); 2947 } 2948 } 2949 2950 /* for non-root phys, report siblings too */ 2951 next_phy: 2952 if (IS_ROOT_PHY(lphyp)) { 2953 lphyp = NULL; 2954 } else { 2955 lphyp = lphyp->sibling; 2956 } 2957 } 2958 2959 return (B_TRUE); 2960 } 2961 2962 /* 2963 * Check for and configure new devices. 2964 * 2965 * If the changed device is a SATA device, add a SATA device. 2966 * 2967 * If the changed device is a SAS device, add a SAS device. 2968 * 2969 * If the changed device is an EXPANDER device, do a REPORT 2970 * GENERAL SMP command to find out the number of contained phys. 2971 * 2972 * For each number of contained phys, allocate a phy, do a 2973 * DISCOVERY SMP command to find out what kind of device it 2974 * is and add it to the linked list of phys on the *next* level. 2975 * 2976 * NOTE: pptr passed in by the caller will be a root PHY 2977 */ 2978 static int 2979 pmcs_configure_new_devices(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 2980 { 2981 int rval = 0; 2982 pmcs_iport_t *iport; 2983 pmcs_phy_t *pnext, *orig_pptr = pptr, *root_phy, *pchild; 2984 uint64_t wwn; 2985 2986 /* 2987 * First, walk through each PHY at this level 2988 */ 2989 while (pptr) { 2990 pmcs_lock_phy(pptr); 2991 pnext = pptr->sibling; 2992 2993 /* 2994 * Set the new dtype if it has changed 2995 */ 2996 if ((pptr->pend_dtype != NEW) && 2997 (pptr->pend_dtype != pptr->dtype)) { 2998 pptr->dtype = pptr->pend_dtype; 2999 } 3000 3001 if (pptr->changed == 0 || pptr->dead || pptr->configured) { 3002 goto next_phy; 3003 } 3004 3005 /* Confirm that this iport is configured */ 3006 root_phy = pmcs_get_root_phy(pptr); 3007 wwn = pmcs_barray2wwn(root_phy->sas_address); 3008 pmcs_unlock_phy(pptr); 3009 iport = pmcs_get_iport_by_wwn(pwp, wwn); 3010 if (iport == NULL) { 3011 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, NULL, 3012 "%s: iport not yet configured, " 3013 "retry discovery", __func__); 3014 pnext = NULL; 3015 rval = -1; 3016 pmcs_lock_phy(pptr); 3017 goto next_phy; 3018 } 3019 3020 pmcs_lock_phy(pptr); 3021 switch (pptr->dtype) { 3022 case NOTHING: 3023 pptr->changed = 0; 3024 break; 3025 case SATA: 3026 case SAS: 3027 pptr->iport = iport; 3028 pmcs_new_tport(pwp, pptr); 3029 break; 3030 case EXPANDER: 3031 pmcs_configure_expander(pwp, pptr, iport); 3032 break; 3033 } 3034 pmcs_rele_iport(iport); 3035 3036 mutex_enter(&pwp->config_lock); 3037 if (pwp->config_changed) { 3038 mutex_exit(&pwp->config_lock); 3039 pnext = NULL; 3040 goto next_phy; 3041 } 3042 mutex_exit(&pwp->config_lock); 3043 3044 next_phy: 3045 pmcs_unlock_phy(pptr); 3046 pptr = pnext; 3047 } 3048 3049 if (rval != 0) { 3050 return (rval); 3051 } 3052 3053 /* 3054 * Now walk through each PHY again, recalling ourselves if they 3055 * have children 3056 */ 3057 pptr = orig_pptr; 3058 while (pptr) { 3059 pmcs_lock_phy(pptr); 3060 pnext = pptr->sibling; 3061 pchild = pptr->children; 3062 pmcs_unlock_phy(pptr); 3063 3064 if (pchild) { 3065 rval = pmcs_configure_new_devices(pwp, pchild); 3066 if (rval != 0) { 3067 break; 3068 } 3069 } 3070 3071 pptr = pnext; 3072 } 3073 3074 return (rval); 3075 } 3076 3077 /* 3078 * Set all phys and descendent phys as changed if changed == B_TRUE, otherwise 3079 * mark them all as not changed. 3080 * 3081 * Called with parent PHY locked. 3082 */ 3083 void 3084 pmcs_set_changed(pmcs_hw_t *pwp, pmcs_phy_t *parent, boolean_t changed, 3085 int level) 3086 { 3087 pmcs_phy_t *pptr; 3088 3089 if (level == 0) { 3090 if (changed) { 3091 PHY_CHANGED(pwp, parent); 3092 } else { 3093 parent->changed = 0; 3094 } 3095 if (parent->dtype == EXPANDER && parent->level) { 3096 parent->width = 1; 3097 } 3098 if (parent->children) { 3099 pmcs_set_changed(pwp, parent->children, changed, 3100 level + 1); 3101 } 3102 } else { 3103 pptr = parent; 3104 while (pptr) { 3105 if (changed) { 3106 PHY_CHANGED(pwp, pptr); 3107 } else { 3108 pptr->changed = 0; 3109 } 3110 if (pptr->dtype == EXPANDER && pptr->level) { 3111 pptr->width = 1; 3112 } 3113 if (pptr->children) { 3114 pmcs_set_changed(pwp, pptr->children, changed, 3115 level + 1); 3116 } 3117 pptr = pptr->sibling; 3118 } 3119 } 3120 } 3121 3122 /* 3123 * Take the passed phy mark it and its descendants as dead. 3124 * Fire up reconfiguration to abort commands and bury it. 3125 * 3126 * Called with the parent PHY locked. 3127 */ 3128 void 3129 pmcs_kill_changed(pmcs_hw_t *pwp, pmcs_phy_t *parent, int level) 3130 { 3131 pmcs_phy_t *pptr = parent; 3132 3133 while (pptr) { 3134 pptr->link_rate = 0; 3135 pptr->abort_sent = 0; 3136 pptr->abort_pending = 1; 3137 SCHEDULE_WORK(pwp, PMCS_WORK_ABORT_HANDLE); 3138 pptr->need_rl_ext = 0; 3139 3140 if (pptr->dead == 0) { 3141 PHY_CHANGED(pwp, pptr); 3142 RESTART_DISCOVERY(pwp); 3143 } 3144 3145 pptr->dead = 1; 3146 3147 if (pptr->children) { 3148 pmcs_kill_changed(pwp, pptr->children, level + 1); 3149 } 3150 3151 /* 3152 * Only kill siblings at level > 0 3153 */ 3154 if (level == 0) { 3155 return; 3156 } 3157 3158 pptr = pptr->sibling; 3159 } 3160 } 3161 3162 /* 3163 * Go through every PHY and clear any that are dead (unless they're expanders) 3164 */ 3165 static void 3166 pmcs_clear_phys(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3167 { 3168 pmcs_phy_t *pnext, *phyp; 3169 3170 phyp = pptr; 3171 while (phyp) { 3172 if (IS_ROOT_PHY(phyp)) { 3173 pmcs_lock_phy(phyp); 3174 } 3175 3176 if ((phyp->dtype != EXPANDER) && phyp->dead) { 3177 pmcs_clear_phy(pwp, phyp); 3178 } 3179 3180 if (phyp->children) { 3181 pmcs_clear_phys(pwp, phyp->children); 3182 } 3183 3184 pnext = phyp->sibling; 3185 3186 if (IS_ROOT_PHY(phyp)) { 3187 pmcs_unlock_phy(phyp); 3188 } 3189 3190 phyp = pnext; 3191 } 3192 } 3193 3194 /* 3195 * Clear volatile parts of a phy. Called with PHY locked. 3196 */ 3197 void 3198 pmcs_clear_phy(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3199 { 3200 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "%s: %s", 3201 __func__, pptr->path); 3202 ASSERT(mutex_owned(&pptr->phy_lock)); 3203 /* keep sibling */ 3204 /* keep children */ 3205 /* keep parent */ 3206 pptr->device_id = PMCS_INVALID_DEVICE_ID; 3207 /* keep hw_event_ack */ 3208 pptr->ncphy = 0; 3209 /* keep phynum */ 3210 pptr->width = 0; 3211 pptr->ds_recovery_retries = 0; 3212 pptr->ds_prev_good_recoveries = 0; 3213 pptr->last_good_recovery = 0; 3214 pptr->prev_recovery = 0; 3215 3216 /* keep dtype */ 3217 pptr->config_stop = 0; 3218 pptr->spinup_hold = 0; 3219 pptr->atdt = 0; 3220 /* keep portid */ 3221 pptr->link_rate = 0; 3222 pptr->valid_device_id = 0; 3223 pptr->abort_sent = 0; 3224 pptr->abort_pending = 0; 3225 pptr->need_rl_ext = 0; 3226 pptr->subsidiary = 0; 3227 pptr->configured = 0; 3228 pptr->deregister_wait = 0; 3229 pptr->reenumerate = 0; 3230 /* Only mark dead if it's not a root PHY and its dtype isn't NOTHING */ 3231 /* XXX: What about directly attached disks? */ 3232 if (!IS_ROOT_PHY(pptr) && (pptr->dtype != NOTHING)) 3233 pptr->dead = 1; 3234 pptr->changed = 0; 3235 /* keep SAS address */ 3236 /* keep path */ 3237 /* keep ref_count */ 3238 /* Don't clear iport on root PHYs - they are handled in pmcs_intr.c */ 3239 if (!IS_ROOT_PHY(pptr)) { 3240 pptr->last_iport = pptr->iport; 3241 pptr->iport = NULL; 3242 } 3243 /* keep target */ 3244 } 3245 3246 /* 3247 * Allocate softstate for this target if there isn't already one. If there 3248 * is, just redo our internal configuration. If it is actually "new", we'll 3249 * soon get a tran_tgt_init for it. 3250 * 3251 * Called with PHY locked. 3252 */ 3253 static void 3254 pmcs_new_tport(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3255 { 3256 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "%s: phy 0x%p @ %s", 3257 __func__, (void *)pptr, pptr->path); 3258 3259 if (pmcs_configure_phy(pwp, pptr) == B_FALSE) { 3260 /* 3261 * If the config failed, mark the PHY as changed. 3262 */ 3263 PHY_CHANGED(pwp, pptr); 3264 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3265 "%s: pmcs_configure_phy failed for phy 0x%p", __func__, 3266 (void *)pptr); 3267 return; 3268 } 3269 3270 /* Mark PHY as no longer changed */ 3271 pptr->changed = 0; 3272 3273 /* 3274 * If the PHY has no target pointer: 3275 * 3276 * If it's a root PHY, see if another PHY in the iport holds the 3277 * target pointer (primary PHY changed). If so, move it over. 3278 * 3279 * If it's not a root PHY, see if there's a PHY on the dead_phys 3280 * list that matches. 3281 */ 3282 if (pptr->target == NULL) { 3283 if (IS_ROOT_PHY(pptr)) { 3284 pmcs_phy_t *rphy = pwp->root_phys; 3285 3286 while (rphy) { 3287 if (rphy == pptr) { 3288 rphy = rphy->sibling; 3289 continue; 3290 } 3291 3292 mutex_enter(&rphy->phy_lock); 3293 if ((rphy->iport == pptr->iport) && 3294 (rphy->target != NULL)) { 3295 mutex_enter(&rphy->target->statlock); 3296 pptr->target = rphy->target; 3297 rphy->target = NULL; 3298 pptr->target->phy = pptr; 3299 /* The target is now on pptr */ 3300 mutex_exit(&pptr->target->statlock); 3301 mutex_exit(&rphy->phy_lock); 3302 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, 3303 pptr, pptr->target, 3304 "%s: Moved target from %s to %s", 3305 __func__, rphy->path, pptr->path); 3306 break; 3307 } 3308 mutex_exit(&rphy->phy_lock); 3309 3310 rphy = rphy->sibling; 3311 } 3312 } else { 3313 pmcs_reap_dead_phy(pptr); 3314 } 3315 } 3316 3317 /* 3318 * Only assign the device if there is a target for this PHY with a 3319 * matching SAS address. If an iport is disconnected from one piece 3320 * of storage and connected to another within the iport stabilization 3321 * time, we can get the PHY/target mismatch situation. 3322 * 3323 * Otherwise, it'll get done in tran_tgt_init. 3324 */ 3325 if (pptr->target) { 3326 mutex_enter(&pptr->target->statlock); 3327 if (pmcs_phy_target_match(pptr) == B_FALSE) { 3328 mutex_exit(&pptr->target->statlock); 3329 if (!IS_ROOT_PHY(pptr)) { 3330 pmcs_dec_phy_ref_count(pptr); 3331 } 3332 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 3333 "%s: Not assigning existing tgt %p for PHY %p " 3334 "(WWN mismatch)", __func__, (void *)pptr->target, 3335 (void *)pptr); 3336 pptr->target = NULL; 3337 return; 3338 } 3339 3340 if (!pmcs_assign_device(pwp, pptr->target)) { 3341 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, pptr->target, 3342 "%s: pmcs_assign_device failed for target 0x%p", 3343 __func__, (void *)pptr->target); 3344 } 3345 mutex_exit(&pptr->target->statlock); 3346 } 3347 } 3348 3349 /* 3350 * Called with PHY lock held. 3351 */ 3352 static boolean_t 3353 pmcs_configure_phy(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3354 { 3355 char *dtype; 3356 3357 ASSERT(mutex_owned(&pptr->phy_lock)); 3358 3359 /* 3360 * Mark this device as no longer changed. 3361 */ 3362 pptr->changed = 0; 3363 3364 /* 3365 * If we don't have a device handle, get one. 3366 */ 3367 if (pmcs_get_device_handle(pwp, pptr)) { 3368 return (B_FALSE); 3369 } 3370 3371 pptr->configured = 1; 3372 3373 switch (pptr->dtype) { 3374 case SAS: 3375 dtype = "SAS"; 3376 break; 3377 case SATA: 3378 dtype = "SATA"; 3379 break; 3380 case EXPANDER: 3381 dtype = "SMP"; 3382 break; 3383 default: 3384 dtype = "???"; 3385 } 3386 3387 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "config_dev: %s " 3388 "dev %s " SAS_ADDR_FMT " dev id 0x%x lr 0x%x", dtype, pptr->path, 3389 SAS_ADDR_PRT(pptr->sas_address), pptr->device_id, pptr->link_rate); 3390 3391 return (B_TRUE); 3392 } 3393 3394 /* 3395 * Called with PHY locked 3396 */ 3397 static void 3398 pmcs_configure_expander(pmcs_hw_t *pwp, pmcs_phy_t *pptr, pmcs_iport_t *iport) 3399 { 3400 pmcs_phy_t *ctmp, *clist = NULL, *cnext; 3401 int result, i, nphy = 0; 3402 boolean_t root_phy = B_FALSE; 3403 3404 ASSERT(iport); 3405 3406 /* 3407 * Step 1- clear our "changed" bit. If we need to retry/restart due 3408 * to resource shortages, we'll set it again. While we're doing 3409 * configuration, other events may set it again as well. If the PHY 3410 * is a root PHY and is currently marked as having changed, reset the 3411 * config_stop timer as well. 3412 */ 3413 if (IS_ROOT_PHY(pptr) && pptr->changed) { 3414 pptr->config_stop = ddi_get_lbolt() + 3415 drv_usectohz(PMCS_MAX_CONFIG_TIME); 3416 } 3417 pptr->changed = 0; 3418 3419 /* 3420 * Step 2- make sure we don't overflow 3421 */ 3422 if (pptr->level == PMCS_MAX_XPND-1) { 3423 pmcs_prt(pwp, PMCS_PRT_WARN, pptr, NULL, 3424 "%s: SAS expansion tree too deep", __func__); 3425 return; 3426 } 3427 3428 /* 3429 * Step 3- Check if this expander is part of a wide phy that has 3430 * already been configured. 3431 * 3432 * This is known by checking this level for another EXPANDER device 3433 * with the same SAS address and isn't already marked as a subsidiary 3434 * phy and a parent whose SAS address is the same as our SAS address 3435 * (if there are parents). 3436 */ 3437 if (!IS_ROOT_PHY(pptr)) { 3438 /* 3439 * No need to lock the parent here because we're in discovery 3440 * and the only time a PHY's children pointer can change is 3441 * in discovery; either in pmcs_clear_expander (which has 3442 * already been called) or here, down below. Plus, trying to 3443 * grab the parent's lock here can cause deadlock. 3444 */ 3445 ctmp = pptr->parent->children; 3446 } else { 3447 ctmp = pwp->root_phys; 3448 root_phy = B_TRUE; 3449 } 3450 3451 while (ctmp) { 3452 /* 3453 * If we've checked all PHYs up to pptr, we stop. Otherwise, 3454 * we'll be checking for a primary PHY with a higher PHY 3455 * number than pptr, which will never happen. The primary 3456 * PHY on non-root expanders will ALWAYS be the lowest 3457 * numbered PHY. 3458 */ 3459 if (ctmp == pptr) { 3460 break; 3461 } 3462 3463 /* 3464 * If pptr and ctmp are root PHYs, just grab the mutex on 3465 * ctmp. No need to lock the entire tree. If they are not 3466 * root PHYs, there is no need to lock since a non-root PHY's 3467 * SAS address and other characteristics can only change in 3468 * discovery anyway. 3469 */ 3470 if (root_phy) { 3471 mutex_enter(&ctmp->phy_lock); 3472 } 3473 3474 if (ctmp->dtype == EXPANDER && ctmp->width && 3475 memcmp(ctmp->sas_address, pptr->sas_address, 8) == 0) { 3476 int widephy = 0; 3477 /* 3478 * If these phys are not root PHYs, compare their SAS 3479 * addresses too. 3480 */ 3481 if (!root_phy) { 3482 if (memcmp(ctmp->parent->sas_address, 3483 pptr->parent->sas_address, 8) == 0) { 3484 widephy = 1; 3485 } 3486 } else { 3487 widephy = 1; 3488 } 3489 if (widephy) { 3490 ctmp->width++; 3491 pptr->subsidiary = 1; 3492 3493 /* 3494 * Update the primary PHY's attached-port-pm 3495 * and target-port-pm information with the info 3496 * from this subsidiary 3497 */ 3498 pmcs_update_phy_pm_props(ctmp, 3499 pptr->att_port_pm_tmp, 3500 pptr->tgt_port_pm_tmp, B_TRUE); 3501 3502 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3503 "%s: PHY %s part of wide PHY %s " 3504 "(now %d wide)", __func__, pptr->path, 3505 ctmp->path, ctmp->width); 3506 if (root_phy) { 3507 mutex_exit(&ctmp->phy_lock); 3508 } 3509 return; 3510 } 3511 } 3512 3513 cnext = ctmp->sibling; 3514 if (root_phy) { 3515 mutex_exit(&ctmp->phy_lock); 3516 } 3517 ctmp = cnext; 3518 } 3519 3520 /* 3521 * Step 4- If we don't have a device handle, get one. Since this 3522 * is the primary PHY, make sure subsidiary is cleared. 3523 */ 3524 pptr->subsidiary = 0; 3525 pptr->iport = iport; 3526 if (pmcs_get_device_handle(pwp, pptr)) { 3527 goto out; 3528 } 3529 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, "Config expander %s " 3530 SAS_ADDR_FMT " dev id 0x%x lr 0x%x", pptr->path, 3531 SAS_ADDR_PRT(pptr->sas_address), pptr->device_id, pptr->link_rate); 3532 3533 /* 3534 * Step 5- figure out how many phys are in this expander. 3535 */ 3536 nphy = pmcs_expander_get_nphy(pwp, pptr); 3537 if (nphy <= 0) { 3538 if (nphy == 0 && ddi_get_lbolt() < pptr->config_stop) { 3539 PHY_CHANGED(pwp, pptr); 3540 RESTART_DISCOVERY(pwp); 3541 } else { 3542 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3543 "%s: Retries exhausted for %s, killing", __func__, 3544 pptr->path); 3545 pptr->config_stop = 0; 3546 pmcs_kill_changed(pwp, pptr, 0); 3547 } 3548 goto out; 3549 } 3550 3551 /* 3552 * Step 6- Allocate a list of phys for this expander and figure out 3553 * what each one is. 3554 */ 3555 for (i = 0; i < nphy; i++) { 3556 ctmp = kmem_cache_alloc(pwp->phy_cache, KM_SLEEP); 3557 bzero(ctmp, sizeof (pmcs_phy_t)); 3558 ctmp->device_id = PMCS_INVALID_DEVICE_ID; 3559 ctmp->sibling = clist; 3560 ctmp->pend_dtype = NEW; /* Init pending dtype */ 3561 ctmp->config_stop = ddi_get_lbolt() + 3562 drv_usectohz(PMCS_MAX_CONFIG_TIME); 3563 clist = ctmp; 3564 } 3565 3566 mutex_enter(&pwp->config_lock); 3567 if (pwp->config_changed) { 3568 RESTART_DISCOVERY_LOCKED(pwp); 3569 mutex_exit(&pwp->config_lock); 3570 /* 3571 * Clean up the newly allocated PHYs and return 3572 */ 3573 while (clist) { 3574 ctmp = clist->sibling; 3575 clist->target_addr = NULL; 3576 kmem_cache_free(pwp->phy_cache, clist); 3577 clist = ctmp; 3578 } 3579 return; 3580 } 3581 mutex_exit(&pwp->config_lock); 3582 3583 /* 3584 * Step 7- Now fill in the rest of the static portions of the phy. 3585 */ 3586 for (i = 0, ctmp = clist; ctmp; ctmp = ctmp->sibling, i++) { 3587 ctmp->parent = pptr; 3588 ctmp->pwp = pwp; 3589 ctmp->level = pptr->level+1; 3590 ctmp->portid = pptr->portid; 3591 if (ctmp->tolerates_sas2) { 3592 ASSERT(i < SAS2_PHYNUM_MAX); 3593 ctmp->phynum = i & SAS2_PHYNUM_MASK; 3594 } else { 3595 ASSERT(i < SAS_PHYNUM_MAX); 3596 ctmp->phynum = i & SAS_PHYNUM_MASK; 3597 } 3598 pmcs_phy_name(pwp, ctmp, ctmp->path, sizeof (ctmp->path)); 3599 pmcs_lock_phy(ctmp); 3600 } 3601 3602 /* 3603 * Step 8- Discover things about each phy in the expander. 3604 */ 3605 for (i = 0, ctmp = clist; ctmp; ctmp = ctmp->sibling, i++) { 3606 result = pmcs_expander_content_discover(pwp, pptr, ctmp); 3607 if (result <= 0) { 3608 if (ddi_get_lbolt() < pptr->config_stop) { 3609 PHY_CHANGED(pwp, pptr); 3610 RESTART_DISCOVERY(pwp); 3611 } else { 3612 pptr->config_stop = 0; 3613 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3614 "%s: Retries exhausted for %s, killing", 3615 __func__, pptr->path); 3616 pmcs_kill_changed(pwp, pptr, 0); 3617 } 3618 goto out; 3619 } 3620 3621 /* Set pend_dtype to dtype for 1st time initialization */ 3622 ctmp->pend_dtype = ctmp->dtype; 3623 } 3624 3625 /* 3626 * Step 9: Install the new list on the next level. There should 3627 * typically be no children pointer on this PHY. There is one known 3628 * case where this can happen, though. If a root PHY goes down and 3629 * comes back up before discovery can run, we will fail to remove the 3630 * children from that PHY since it will no longer be marked dead. 3631 * However, in this case, all children should also be marked dead. If 3632 * we see that, take those children and put them on the dead_phys list. 3633 */ 3634 if (pptr->children != NULL) { 3635 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 3636 "%s: Expander @ %s still has children: Clean up", 3637 __func__, pptr->path); 3638 pmcs_add_dead_phys(pwp, pptr->children); 3639 } 3640 3641 /* 3642 * Set the new children pointer for this expander 3643 */ 3644 pptr->children = clist; 3645 clist = NULL; 3646 pptr->ncphy = nphy; 3647 pptr->configured = 1; 3648 3649 /* 3650 * We only set width if we're greater than level 0. 3651 */ 3652 if (pptr->level) { 3653 pptr->width = 1; 3654 } 3655 3656 /* 3657 * Now tell the rest of the world about us, as an SMP node. 3658 */ 3659 pptr->iport = iport; 3660 pmcs_new_tport(pwp, pptr); 3661 3662 out: 3663 while (clist) { 3664 ctmp = clist->sibling; 3665 pmcs_unlock_phy(clist); 3666 clist->target_addr = NULL; 3667 kmem_cache_free(pwp->phy_cache, clist); 3668 clist = ctmp; 3669 } 3670 } 3671 3672 /* 3673 * 2. Check expanders marked changed (but not dead) to see if they still have 3674 * the same number of phys and the same SAS address. Mark them, their subsidiary 3675 * phys (if wide) and their descendents dead if anything has changed. Check the 3676 * the devices they contain to see if *they* have changed. If they've changed 3677 * from type NOTHING we leave them marked changed to be configured later 3678 * (picking up a new SAS address and link rate if possible). Otherwise, any 3679 * change in type, SAS address or removal of target role will cause us to 3680 * mark them (and their descendents) as dead and cause any pending commands 3681 * and associated devices to be removed. 3682 * 3683 * Called with PHY (pptr) locked. 3684 */ 3685 3686 static void 3687 pmcs_check_expander(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 3688 { 3689 int nphy, result; 3690 pmcs_phy_t *ctmp, *local, *local_list = NULL, *local_tail = NULL; 3691 boolean_t kill_changed, changed; 3692 3693 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3694 "%s: check %s", __func__, pptr->path); 3695 3696 /* 3697 * Step 1: Mark phy as not changed. We will mark it changed if we need 3698 * to retry. 3699 */ 3700 pptr->changed = 0; 3701 3702 /* 3703 * Reset the config_stop time. Although we're not actually configuring 3704 * anything here, we do want some indication of when to give up trying 3705 * if we can't communicate with the expander. 3706 */ 3707 pptr->config_stop = ddi_get_lbolt() + 3708 drv_usectohz(PMCS_MAX_CONFIG_TIME); 3709 3710 /* 3711 * Step 2: Figure out how many phys are in this expander. If 3712 * pmcs_expander_get_nphy returns 0 we ran out of resources, 3713 * so reschedule and try later. If it returns another error, 3714 * just return. 3715 */ 3716 nphy = pmcs_expander_get_nphy(pwp, pptr); 3717 if (nphy <= 0) { 3718 if ((nphy == 0) && (ddi_get_lbolt() < pptr->config_stop)) { 3719 PHY_CHANGED(pwp, pptr); 3720 RESTART_DISCOVERY(pwp); 3721 } else { 3722 pptr->config_stop = 0; 3723 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3724 "%s: Retries exhausted for %s, killing", __func__, 3725 pptr->path); 3726 pmcs_kill_changed(pwp, pptr, 0); 3727 } 3728 return; 3729 } 3730 3731 /* 3732 * Step 3: If the number of phys don't agree, kill the old sub-tree. 3733 */ 3734 if (nphy != pptr->ncphy) { 3735 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3736 "%s: number of contained phys for %s changed from %d to %d", 3737 __func__, pptr->path, pptr->ncphy, nphy); 3738 /* 3739 * Force a rescan of this expander after dead contents 3740 * are cleared and removed. 3741 */ 3742 pmcs_kill_changed(pwp, pptr, 0); 3743 return; 3744 } 3745 3746 /* 3747 * Step 4: if we're at the bottom of the stack, we're done 3748 * (we can't have any levels below us) 3749 */ 3750 if (pptr->level == PMCS_MAX_XPND-1) { 3751 return; 3752 } 3753 3754 /* 3755 * Step 5: Discover things about each phy in this expander. We do 3756 * this by walking the current list of contained phys and doing a 3757 * content discovery for it to a local phy. 3758 */ 3759 ctmp = pptr->children; 3760 ASSERT(ctmp); 3761 if (ctmp == NULL) { 3762 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3763 "%s: No children attached to expander @ %s?", __func__, 3764 pptr->path); 3765 return; 3766 } 3767 3768 while (ctmp) { 3769 /* 3770 * Allocate a local PHY to contain the proposed new contents 3771 * and link it to the rest of the local PHYs so that they 3772 * can all be freed later. 3773 */ 3774 local = pmcs_clone_phy(ctmp); 3775 3776 if (local_list == NULL) { 3777 local_list = local; 3778 local_tail = local; 3779 } else { 3780 local_tail->sibling = local; 3781 local_tail = local; 3782 } 3783 3784 /* 3785 * Need to lock the local PHY since pmcs_expander_content_ 3786 * discovery may call pmcs_clear_phy on it, which expects 3787 * the PHY to be locked. 3788 */ 3789 pmcs_lock_phy(local); 3790 result = pmcs_expander_content_discover(pwp, pptr, local); 3791 pmcs_unlock_phy(local); 3792 if (result <= 0) { 3793 if (ddi_get_lbolt() < pptr->config_stop) { 3794 PHY_CHANGED(pwp, pptr); 3795 RESTART_DISCOVERY(pwp); 3796 } else { 3797 pptr->config_stop = 0; 3798 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 3799 "%s: Retries exhausted for %s, killing", 3800 __func__, pptr->path); 3801 pmcs_kill_changed(pwp, pptr, 0); 3802 } 3803 3804 /* 3805 * Release all the local PHYs that we allocated. 3806 */ 3807 pmcs_free_phys(pwp, local_list); 3808 return; 3809 } 3810 3811 ctmp = ctmp->sibling; 3812 } 3813 3814 /* 3815 * Step 6: Compare the local PHY's contents to our current PHY. If 3816 * there are changes, take the appropriate action. 3817 * This is done in two steps (step 5 above, and 6 here) so that if we 3818 * have to bail during this process (e.g. pmcs_expander_content_discover 3819 * fails), we haven't actually changed the state of any of the real 3820 * PHYs. Next time we come through here, we'll be starting over from 3821 * scratch. This keeps us from marking a changed PHY as no longer 3822 * changed, but then having to bail only to come back next time and 3823 * think that the PHY hadn't changed. If this were to happen, we 3824 * would fail to properly configure the device behind this PHY. 3825 */ 3826 local = local_list; 3827 ctmp = pptr->children; 3828 3829 while (ctmp) { 3830 changed = B_FALSE; 3831 kill_changed = B_FALSE; 3832 3833 /* 3834 * We set local to local_list prior to this loop so that we 3835 * can simply walk the local_list while we walk this list. The 3836 * two lists should be completely in sync. 3837 * 3838 * Clear the changed flag here. 3839 */ 3840 ctmp->changed = 0; 3841 3842 if (ctmp->dtype != local->dtype) { 3843 if (ctmp->dtype != NOTHING) { 3844 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 3845 "%s: %s type changed from %s to %s " 3846 "(killing)", __func__, ctmp->path, 3847 PHY_TYPE(ctmp), PHY_TYPE(local)); 3848 /* 3849 * Force a rescan of this expander after dead 3850 * contents are cleared and removed. 3851 */ 3852 changed = B_TRUE; 3853 kill_changed = B_TRUE; 3854 } else { 3855 changed = B_TRUE; 3856 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 3857 "%s: %s type changed from NOTHING to %s", 3858 __func__, ctmp->path, PHY_TYPE(local)); 3859 /* 3860 * Since this PHY was nothing and is now 3861 * something, reset the config_stop timer. 3862 */ 3863 ctmp->config_stop = ddi_get_lbolt() + 3864 drv_usectohz(PMCS_MAX_CONFIG_TIME); 3865 } 3866 3867 } else if (ctmp->atdt != local->atdt) { 3868 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, "%s: " 3869 "%s attached device type changed from %d to %d " 3870 "(killing)", __func__, ctmp->path, ctmp->atdt, 3871 local->atdt); 3872 /* 3873 * Force a rescan of this expander after dead 3874 * contents are cleared and removed. 3875 */ 3876 changed = B_TRUE; 3877 3878 if (local->atdt == 0) { 3879 kill_changed = B_TRUE; 3880 } 3881 } else if (ctmp->link_rate != local->link_rate) { 3882 pmcs_prt(pwp, PMCS_PRT_INFO, ctmp, NULL, "%s: %s " 3883 "changed speed from %s to %s", __func__, ctmp->path, 3884 pmcs_get_rate(ctmp->link_rate), 3885 pmcs_get_rate(local->link_rate)); 3886 /* If the speed changed from invalid, force rescan */ 3887 if (!PMCS_VALID_LINK_RATE(ctmp->link_rate)) { 3888 changed = B_TRUE; 3889 RESTART_DISCOVERY(pwp); 3890 } else { 3891 /* Just update to the new link rate */ 3892 ctmp->link_rate = local->link_rate; 3893 } 3894 3895 if (!PMCS_VALID_LINK_RATE(local->link_rate)) { 3896 kill_changed = B_TRUE; 3897 } 3898 } else if (memcmp(ctmp->sas_address, local->sas_address, 3899 sizeof (ctmp->sas_address)) != 0) { 3900 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 3901 "%s: SAS Addr for %s changed from " SAS_ADDR_FMT 3902 "to " SAS_ADDR_FMT " (kill old tree)", __func__, 3903 ctmp->path, SAS_ADDR_PRT(ctmp->sas_address), 3904 SAS_ADDR_PRT(local->sas_address)); 3905 /* 3906 * Force a rescan of this expander after dead 3907 * contents are cleared and removed. 3908 */ 3909 changed = B_TRUE; 3910 } else { 3911 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 3912 "%s: %s looks the same (type %s)", 3913 __func__, ctmp->path, PHY_TYPE(ctmp)); 3914 /* 3915 * If EXPANDER, still mark it changed so we 3916 * re-evaluate its contents. If it's not an expander, 3917 * but it hasn't been configured, also mark it as 3918 * changed so that it will undergo configuration. 3919 */ 3920 if (ctmp->dtype == EXPANDER) { 3921 changed = B_TRUE; 3922 } else if ((ctmp->dtype != NOTHING) && 3923 !ctmp->configured) { 3924 ctmp->changed = 1; 3925 } else { 3926 /* It simply hasn't changed */ 3927 ctmp->changed = 0; 3928 } 3929 } 3930 3931 /* 3932 * If the PHY changed, call pmcs_kill_changed if indicated, 3933 * update its contents to reflect its current state and mark it 3934 * as changed. 3935 */ 3936 if (changed) { 3937 /* 3938 * pmcs_kill_changed will mark the PHY as changed, so 3939 * only do PHY_CHANGED if we did not do kill_changed. 3940 */ 3941 if (kill_changed) { 3942 pmcs_kill_changed(pwp, ctmp, 0); 3943 } else { 3944 /* 3945 * If we're not killing the device, it's not 3946 * dead. Mark the PHY as changed. 3947 */ 3948 PHY_CHANGED(pwp, ctmp); 3949 3950 if (ctmp->dead) { 3951 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, 3952 ctmp, NULL, "%s: Unmarking PHY %s " 3953 "dead, restarting discovery", 3954 __func__, ctmp->path); 3955 ctmp->dead = 0; 3956 RESTART_DISCOVERY(pwp); 3957 } 3958 } 3959 3960 /* 3961 * If the dtype of this PHY is now NOTHING, mark it as 3962 * unconfigured. Set pend_dtype to what the new dtype 3963 * is. It'll get updated at the end of the discovery 3964 * process. 3965 */ 3966 if (local->dtype == NOTHING) { 3967 bzero(ctmp->sas_address, 3968 sizeof (local->sas_address)); 3969 ctmp->atdt = 0; 3970 ctmp->link_rate = 0; 3971 ctmp->pend_dtype = NOTHING; 3972 ctmp->configured = 0; 3973 } else { 3974 (void) memcpy(ctmp->sas_address, 3975 local->sas_address, 3976 sizeof (local->sas_address)); 3977 ctmp->atdt = local->atdt; 3978 ctmp->link_rate = local->link_rate; 3979 ctmp->pend_dtype = local->dtype; 3980 ctmp->att_port_pm_tmp = local->att_port_pm_tmp; 3981 ctmp->tgt_port_pm_tmp = local->tgt_port_pm_tmp; 3982 } 3983 } 3984 3985 local = local->sibling; 3986 ctmp = ctmp->sibling; 3987 } 3988 3989 /* 3990 * If we got to here, that means we were able to see all the PHYs 3991 * and we can now update all of the real PHYs with the information 3992 * we got on the local PHYs. Once that's done, free all the local 3993 * PHYs. 3994 */ 3995 3996 pmcs_free_phys(pwp, local_list); 3997 } 3998 3999 /* 4000 * Top level routine to check expanders. We call pmcs_check_expander for 4001 * each expander. Since we're not doing any configuration right now, it 4002 * doesn't matter if this is breadth-first. 4003 */ 4004 static void 4005 pmcs_check_expanders(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 4006 { 4007 pmcs_phy_t *phyp, *pnext, *pchild; 4008 4009 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4010 "%s: %s", __func__, pptr->path); 4011 4012 /* 4013 * Check each expander at this level 4014 */ 4015 phyp = pptr; 4016 while (phyp) { 4017 pmcs_lock_phy(phyp); 4018 4019 if ((phyp->dtype == EXPANDER) && phyp->changed && 4020 !phyp->dead && !phyp->subsidiary && 4021 phyp->configured) { 4022 pmcs_check_expander(pwp, phyp); 4023 } 4024 4025 pnext = phyp->sibling; 4026 pmcs_unlock_phy(phyp); 4027 phyp = pnext; 4028 } 4029 4030 /* 4031 * Now check the children 4032 */ 4033 phyp = pptr; 4034 while (phyp) { 4035 pmcs_lock_phy(phyp); 4036 pnext = phyp->sibling; 4037 pchild = phyp->children; 4038 pmcs_unlock_phy(phyp); 4039 4040 if (pchild) { 4041 pmcs_check_expanders(pwp, pchild); 4042 } 4043 4044 phyp = pnext; 4045 } 4046 } 4047 4048 /* 4049 * Called with softstate and PHY locked 4050 */ 4051 static void 4052 pmcs_clear_expander(pmcs_hw_t *pwp, pmcs_phy_t *pptr, int level) 4053 { 4054 pmcs_phy_t *ctmp; 4055 4056 ASSERT(mutex_owned(&pwp->lock)); 4057 ASSERT(mutex_owned(&pptr->phy_lock)); 4058 ASSERT(pptr->level < PMCS_MAX_XPND - 1); 4059 4060 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4061 "%s: checking %s", __func__, pptr->path); 4062 4063 ctmp = pptr->children; 4064 while (ctmp) { 4065 /* 4066 * If the expander is dead, mark its children dead 4067 */ 4068 if (pptr->dead) { 4069 ctmp->dead = 1; 4070 } 4071 if (ctmp->dtype == EXPANDER) { 4072 pmcs_clear_expander(pwp, ctmp, level + 1); 4073 } 4074 ctmp = ctmp->sibling; 4075 } 4076 4077 /* 4078 * If this expander is not dead, we're done here. 4079 */ 4080 if (!pptr->dead) { 4081 return; 4082 } 4083 4084 /* 4085 * Now snip out the list of children below us and release them 4086 */ 4087 if (pptr->children) { 4088 pmcs_add_dead_phys(pwp, pptr->children); 4089 } 4090 4091 pptr->children = NULL; 4092 4093 /* 4094 * Clear subsidiary phys as well. Getting the parent's PHY lock 4095 * is only necessary if level == 0 since otherwise the parent is 4096 * already locked. 4097 */ 4098 if (!IS_ROOT_PHY(pptr)) { 4099 if (level == 0) { 4100 mutex_enter(&pptr->parent->phy_lock); 4101 } 4102 ctmp = pptr->parent->children; 4103 if (level == 0) { 4104 mutex_exit(&pptr->parent->phy_lock); 4105 } 4106 } else { 4107 ctmp = pwp->root_phys; 4108 } 4109 4110 while (ctmp) { 4111 if (ctmp == pptr) { 4112 ctmp = ctmp->sibling; 4113 continue; 4114 } 4115 /* 4116 * We only need to lock subsidiary PHYs on the level 0 4117 * expander. Any children of that expander, subsidiaries or 4118 * not, will already be locked. 4119 */ 4120 if (level == 0) { 4121 pmcs_lock_phy(ctmp); 4122 } 4123 if (ctmp->dtype != EXPANDER || ctmp->subsidiary == 0 || 4124 memcmp(ctmp->sas_address, pptr->sas_address, 4125 sizeof (ctmp->sas_address)) != 0) { 4126 if (level == 0) { 4127 pmcs_unlock_phy(ctmp); 4128 } 4129 ctmp = ctmp->sibling; 4130 continue; 4131 } 4132 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 4133 "%s: subsidiary %s", __func__, ctmp->path); 4134 pmcs_clear_phy(pwp, ctmp); 4135 if (level == 0) { 4136 pmcs_unlock_phy(ctmp); 4137 } 4138 ctmp = ctmp->sibling; 4139 } 4140 4141 pmcs_clear_phy(pwp, pptr); 4142 } 4143 4144 /* 4145 * Called with PHY locked and with scratch acquired. We return 0 if 4146 * we fail to allocate resources or notice that the configuration 4147 * count changed while we were running the command. We return 4148 * less than zero if we had an I/O error or received an unsupported 4149 * configuration. Otherwise we return the number of phys in the 4150 * expander. 4151 */ 4152 #define DFM(m, y) if (m == NULL) m = y 4153 static int 4154 pmcs_expander_get_nphy(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 4155 { 4156 struct pmcwork *pwrk; 4157 pmcs_iport_t *iport; 4158 char buf[64]; 4159 const uint_t rdoff = 0x100; /* returned data offset */ 4160 smp_response_frame_t *srf; 4161 smp_report_general_resp_t *srgr; 4162 uint32_t msg[PMCS_MSG_SIZE], *ptr, htag, status, ival; 4163 int result = 0; 4164 4165 ival = 0x40001100; 4166 4167 again: 4168 if (!pptr->iport || !pptr->valid_device_id) { 4169 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, pptr->target, 4170 "%s: Can't reach PHY %s", __func__, pptr->path); 4171 goto out; 4172 } 4173 4174 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 4175 if (pwrk == NULL) { 4176 goto out; 4177 } 4178 (void) memset(pwp->scratch, 0x77, PMCS_SCRATCH_SIZE); 4179 pwrk->arg = pwp->scratch; 4180 pwrk->dtype = pptr->dtype; 4181 pwrk->xp = pptr->target; 4182 pwrk->htag |= PMCS_TAG_NONIO_CMD; 4183 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4184 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4185 if (ptr == NULL) { 4186 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4187 pmcs_prt(pwp, PMCS_PRT_DEBUG2, pptr, NULL, 4188 "%s: GET_IQ_ENTRY failed", __func__); 4189 pmcs_pwork(pwp, pwrk); 4190 goto out; 4191 } 4192 4193 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, PMCIN_SMP_REQUEST)); 4194 msg[1] = LE_32(pwrk->htag); 4195 msg[2] = LE_32(pptr->device_id); 4196 msg[3] = LE_32((4 << SMP_REQUEST_LENGTH_SHIFT) | SMP_INDIRECT_RESPONSE); 4197 /* 4198 * Send SMP REPORT GENERAL (of either SAS1.1 or SAS2 flavors). 4199 */ 4200 msg[4] = BE_32(ival); 4201 msg[5] = 0; 4202 msg[6] = 0; 4203 msg[7] = 0; 4204 msg[8] = 0; 4205 msg[9] = 0; 4206 msg[10] = 0; 4207 msg[11] = 0; 4208 msg[12] = LE_32(DWORD0(pwp->scratch_dma+rdoff)); 4209 msg[13] = LE_32(DWORD1(pwp->scratch_dma+rdoff)); 4210 msg[14] = LE_32(PMCS_SCRATCH_SIZE - rdoff); 4211 msg[15] = 0; 4212 4213 COPY_MESSAGE(ptr, msg, PMCS_MSG_SIZE); 4214 4215 pmcs_hold_iport(pptr->iport); 4216 iport = pptr->iport; 4217 pmcs_smp_acquire(iport); 4218 pwrk->state = PMCS_WORK_STATE_ONCHIP; 4219 htag = pwrk->htag; 4220 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4221 pmcs_unlock_phy(pptr); 4222 WAIT_FOR(pwrk, 1000, result); 4223 pmcs_pwork(pwp, pwrk); 4224 pmcs_lock_phy(pptr); 4225 if (result) { 4226 pmcs_timed_out(pwp, htag, __func__); 4227 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4228 "%s: Issuing SMP ABORT for htag 0x%08x", __func__, htag); 4229 if (pmcs_abort(pwp, pptr, htag, 0, 1)) { 4230 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4231 "%s: SMP ABORT failed for cmd (htag 0x%08x)", 4232 __func__, htag); 4233 } 4234 pmcs_smp_release(iport); 4235 pmcs_rele_iport(iport); 4236 result = 0; 4237 goto out; 4238 } 4239 pmcs_smp_release(iport); 4240 pmcs_rele_iport(iport); 4241 4242 mutex_enter(&pwp->config_lock); 4243 if (pwp->config_changed) { 4244 RESTART_DISCOVERY_LOCKED(pwp); 4245 mutex_exit(&pwp->config_lock); 4246 result = 0; 4247 goto out; 4248 } 4249 mutex_exit(&pwp->config_lock); 4250 4251 ptr = (void *)pwp->scratch; 4252 status = LE_32(ptr[2]); 4253 if (status == PMCOUT_STATUS_UNDERFLOW || 4254 status == PMCOUT_STATUS_OVERFLOW) { 4255 pmcs_prt(pwp, PMCS_PRT_DEBUG_UNDERFLOW, pptr, NULL, 4256 "%s: over/underflow", __func__); 4257 status = PMCOUT_STATUS_OK; 4258 } 4259 srf = (smp_response_frame_t *)&((uint32_t *)pwp->scratch)[rdoff >> 2]; 4260 srgr = (smp_report_general_resp_t *) 4261 &((uint32_t *)pwp->scratch)[(rdoff >> 2)+1]; 4262 4263 if (status != PMCOUT_STATUS_OK) { 4264 char *nag = NULL; 4265 (void) snprintf(buf, sizeof (buf), 4266 "%s: SMP op failed (0x%x)", __func__, status); 4267 switch (status) { 4268 case PMCOUT_STATUS_IO_PORT_IN_RESET: 4269 DFM(nag, "I/O Port In Reset"); 4270 /* FALLTHROUGH */ 4271 case PMCOUT_STATUS_ERROR_HW_TIMEOUT: 4272 DFM(nag, "Hardware Timeout"); 4273 /* FALLTHROUGH */ 4274 case PMCOUT_STATUS_ERROR_INTERNAL_SMP_RESOURCE: 4275 DFM(nag, "Internal SMP Resource Failure"); 4276 /* FALLTHROUGH */ 4277 case PMCOUT_STATUS_XFER_ERR_PHY_NOT_READY: 4278 DFM(nag, "PHY Not Ready"); 4279 /* FALLTHROUGH */ 4280 case PMCOUT_STATUS_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 4281 DFM(nag, "Connection Rate Not Supported"); 4282 /* FALLTHROUGH */ 4283 case PMCOUT_STATUS_IO_XFER_OPEN_RETRY_TIMEOUT: 4284 DFM(nag, "Open Retry Timeout"); 4285 /* FALLTHROUGH */ 4286 case PMCOUT_STATUS_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 4287 DFM(nag, "HW Resource Busy"); 4288 /* FALLTHROUGH */ 4289 case PMCOUT_STATUS_SMP_RESP_CONNECTION_ERROR: 4290 DFM(nag, "Response Connection Error"); 4291 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4292 "%s: expander %s SMP operation failed (%s)", 4293 __func__, pptr->path, nag); 4294 break; 4295 4296 /* 4297 * For the IO_DS_NON_OPERATIONAL case, we need to kick off 4298 * device state recovery and return 0 so that the caller 4299 * doesn't assume this expander is dead for good. 4300 */ 4301 case PMCOUT_STATUS_IO_DS_NON_OPERATIONAL: { 4302 pmcs_xscsi_t *xp = pptr->target; 4303 4304 pmcs_prt(pwp, PMCS_PRT_DEBUG_DEV_STATE, pptr, xp, 4305 "%s: expander %s device state non-operational", 4306 __func__, pptr->path); 4307 4308 if (xp == NULL) { 4309 /* 4310 * Kick off recovery right now. 4311 */ 4312 SCHEDULE_WORK(pwp, PMCS_WORK_DS_ERR_RECOVERY); 4313 (void) ddi_taskq_dispatch(pwp->tq, pmcs_worker, 4314 pwp, DDI_NOSLEEP); 4315 } else { 4316 mutex_enter(&xp->statlock); 4317 pmcs_start_dev_state_recovery(xp, pptr); 4318 mutex_exit(&xp->statlock); 4319 } 4320 4321 break; 4322 } 4323 4324 default: 4325 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, buf, ptr); 4326 result = -EIO; 4327 break; 4328 } 4329 } else if (srf->srf_frame_type != SMP_FRAME_TYPE_RESPONSE) { 4330 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4331 "%s: bad response frame type 0x%x", 4332 __func__, srf->srf_frame_type); 4333 result = -EINVAL; 4334 } else if (srf->srf_function != SMP_FUNC_REPORT_GENERAL) { 4335 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4336 "%s: bad response function 0x%x", 4337 __func__, srf->srf_function); 4338 result = -EINVAL; 4339 } else if (srf->srf_result != 0) { 4340 /* 4341 * Check to see if we have a value of 3 for failure and 4342 * whether we were using a SAS2.0 allocation length value 4343 * and retry without it. 4344 */ 4345 if (srf->srf_result == 3 && (ival & 0xff00)) { 4346 ival &= ~0xff00; 4347 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4348 "%s: err 0x%x with SAS2 request- retry with SAS1", 4349 __func__, srf->srf_result); 4350 goto again; 4351 } 4352 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4353 "%s: bad response 0x%x", __func__, srf->srf_result); 4354 result = -EINVAL; 4355 } else if (srgr->srgr_configuring) { 4356 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4357 "%s: expander at phy %s is still configuring", 4358 __func__, pptr->path); 4359 result = 0; 4360 } else { 4361 result = srgr->srgr_number_of_phys; 4362 if (ival & 0xff00) { 4363 pptr->tolerates_sas2 = 1; 4364 } 4365 /* 4366 * Save off the REPORT_GENERAL response 4367 */ 4368 bcopy(srgr, &pptr->rg_resp, sizeof (smp_report_general_resp_t)); 4369 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4370 "%s has %d phys and %s SAS2", pptr->path, result, 4371 pptr->tolerates_sas2? "tolerates" : "does not tolerate"); 4372 } 4373 out: 4374 return (result); 4375 } 4376 4377 /* 4378 * Called with expander locked (and thus, pptr) as well as all PHYs up to 4379 * the root, and scratch acquired. Return 0 if we fail to allocate resources 4380 * or notice that the configuration changed while we were running the command. 4381 * 4382 * We return less than zero if we had an I/O error or received an 4383 * unsupported configuration. 4384 */ 4385 static int 4386 pmcs_expander_content_discover(pmcs_hw_t *pwp, pmcs_phy_t *expander, 4387 pmcs_phy_t *pptr) 4388 { 4389 struct pmcwork *pwrk; 4390 pmcs_iport_t *iport; 4391 char buf[64]; 4392 uint8_t sas_address[8]; 4393 uint8_t att_sas_address[8]; 4394 smp_response_frame_t *srf; 4395 smp_discover_resp_t *sdr; 4396 const uint_t rdoff = 0x100; /* returned data offset */ 4397 uint8_t *roff; 4398 uint32_t status, *ptr, msg[PMCS_MSG_SIZE], htag; 4399 int result = 0; 4400 uint8_t ini_support; 4401 uint8_t tgt_support; 4402 4403 if (!expander->iport || !expander->valid_device_id) { 4404 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, expander, expander->target, 4405 "%s: Can't reach PHY %s", __func__, expander->path); 4406 goto out; 4407 } 4408 4409 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, expander); 4410 if (pwrk == NULL) { 4411 goto out; 4412 } 4413 (void) memset(pwp->scratch, 0x77, PMCS_SCRATCH_SIZE); 4414 pwrk->arg = pwp->scratch; 4415 pwrk->dtype = expander->dtype; 4416 pwrk->xp = expander->target; 4417 pwrk->htag |= PMCS_TAG_NONIO_CMD; 4418 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, PMCIN_SMP_REQUEST)); 4419 msg[1] = LE_32(pwrk->htag); 4420 msg[2] = LE_32(expander->device_id); 4421 msg[3] = LE_32((12 << SMP_REQUEST_LENGTH_SHIFT) | 4422 SMP_INDIRECT_RESPONSE); 4423 /* 4424 * Send SMP DISCOVER (of either SAS1.1 or SAS2 flavors). 4425 */ 4426 if (expander->tolerates_sas2) { 4427 msg[4] = BE_32(0x40101B00); 4428 } else { 4429 msg[4] = BE_32(0x40100000); 4430 } 4431 msg[5] = 0; 4432 msg[6] = BE_32((pptr->phynum << 16)); 4433 msg[7] = 0; 4434 msg[8] = 0; 4435 msg[9] = 0; 4436 msg[10] = 0; 4437 msg[11] = 0; 4438 msg[12] = LE_32(DWORD0(pwp->scratch_dma+rdoff)); 4439 msg[13] = LE_32(DWORD1(pwp->scratch_dma+rdoff)); 4440 msg[14] = LE_32(PMCS_SCRATCH_SIZE - rdoff); 4441 msg[15] = 0; 4442 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4443 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4444 if (ptr == NULL) { 4445 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4446 goto out; 4447 } 4448 4449 COPY_MESSAGE(ptr, msg, PMCS_MSG_SIZE); 4450 4451 pmcs_hold_iport(expander->iport); 4452 iport = expander->iport; 4453 pmcs_smp_acquire(iport); 4454 pwrk->state = PMCS_WORK_STATE_ONCHIP; 4455 htag = pwrk->htag; 4456 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4457 pmcs_unlock_phy(expander); 4458 WAIT_FOR(pwrk, 1000, result); 4459 pmcs_pwork(pwp, pwrk); 4460 pmcs_lock_phy(expander); 4461 if (result) { 4462 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4463 "%s: Issuing SMP ABORT for htag 0x%08x", __func__, htag); 4464 if (pmcs_abort(pwp, pptr, htag, 0, 1)) { 4465 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4466 "%s: SMP ABORT failed for cmd (htag 0x%08x)", 4467 __func__, htag); 4468 } 4469 pmcs_smp_release(iport); 4470 pmcs_rele_iport(iport); 4471 result = -ETIMEDOUT; 4472 goto out; 4473 } 4474 pmcs_smp_release(iport); 4475 pmcs_rele_iport(iport); 4476 4477 mutex_enter(&pwp->config_lock); 4478 if (pwp->config_changed) { 4479 RESTART_DISCOVERY_LOCKED(pwp); 4480 mutex_exit(&pwp->config_lock); 4481 result = 0; 4482 goto out; 4483 } 4484 4485 mutex_exit(&pwp->config_lock); 4486 ptr = (void *)pwp->scratch; 4487 /* 4488 * Point roff to the DMA offset for returned data 4489 */ 4490 roff = pwp->scratch; 4491 roff += rdoff; 4492 srf = (smp_response_frame_t *)roff; 4493 sdr = (smp_discover_resp_t *)(roff+4); 4494 status = LE_32(ptr[2]); 4495 if (status == PMCOUT_STATUS_UNDERFLOW || 4496 status == PMCOUT_STATUS_OVERFLOW) { 4497 pmcs_prt(pwp, PMCS_PRT_DEBUG_UNDERFLOW, pptr, NULL, 4498 "%s: over/underflow", __func__); 4499 status = PMCOUT_STATUS_OK; 4500 } 4501 if (status != PMCOUT_STATUS_OK) { 4502 char *nag = NULL; 4503 (void) snprintf(buf, sizeof (buf), 4504 "%s: SMP op failed (0x%x)", __func__, status); 4505 switch (status) { 4506 case PMCOUT_STATUS_ERROR_HW_TIMEOUT: 4507 DFM(nag, "Hardware Timeout"); 4508 /* FALLTHROUGH */ 4509 case PMCOUT_STATUS_ERROR_INTERNAL_SMP_RESOURCE: 4510 DFM(nag, "Internal SMP Resource Failure"); 4511 /* FALLTHROUGH */ 4512 case PMCOUT_STATUS_XFER_ERR_PHY_NOT_READY: 4513 DFM(nag, "PHY Not Ready"); 4514 /* FALLTHROUGH */ 4515 case PMCOUT_STATUS_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 4516 DFM(nag, "Connection Rate Not Supported"); 4517 /* FALLTHROUGH */ 4518 case PMCOUT_STATUS_IO_XFER_OPEN_RETRY_TIMEOUT: 4519 DFM(nag, "Open Retry Timeout"); 4520 /* FALLTHROUGH */ 4521 case PMCOUT_STATUS_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 4522 DFM(nag, "HW Resource Busy"); 4523 /* FALLTHROUGH */ 4524 case PMCOUT_STATUS_SMP_RESP_CONNECTION_ERROR: 4525 DFM(nag, "Response Connection Error"); 4526 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4527 "%s: expander %s SMP operation failed (%s)", 4528 __func__, pptr->path, nag); 4529 break; 4530 default: 4531 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, buf, ptr); 4532 result = -EIO; 4533 break; 4534 } 4535 goto out; 4536 } else if (srf->srf_frame_type != SMP_FRAME_TYPE_RESPONSE) { 4537 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4538 "%s: bad response frame type 0x%x", 4539 __func__, srf->srf_frame_type); 4540 result = -EINVAL; 4541 goto out; 4542 } else if (srf->srf_function != SMP_FUNC_DISCOVER) { 4543 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4544 "%s: bad response function 0x%x", 4545 __func__, srf->srf_function); 4546 result = -EINVAL; 4547 goto out; 4548 } else if (srf->srf_result != SMP_RES_FUNCTION_ACCEPTED) { 4549 result = pmcs_smp_function_result(pwp, srf); 4550 /* Need not fail if PHY is Vacant */ 4551 if (result != SMP_RES_PHY_VACANT) { 4552 result = -EINVAL; 4553 goto out; 4554 } 4555 } 4556 4557 /* 4558 * Save off the DISCOVER response 4559 */ 4560 bcopy(sdr, &pptr->disc_resp, sizeof (smp_discover_resp_t)); 4561 4562 ini_support = (sdr->sdr_attached_sata_host | 4563 (sdr->sdr_attached_smp_initiator << 1) | 4564 (sdr->sdr_attached_stp_initiator << 2) | 4565 (sdr->sdr_attached_ssp_initiator << 3)); 4566 4567 tgt_support = (sdr->sdr_attached_sata_device | 4568 (sdr->sdr_attached_smp_target << 1) | 4569 (sdr->sdr_attached_stp_target << 2) | 4570 (sdr->sdr_attached_ssp_target << 3)); 4571 4572 pmcs_wwn2barray(BE_64(sdr->sdr_sas_addr), sas_address); 4573 pmcs_wwn2barray(BE_64(sdr->sdr_attached_sas_addr), att_sas_address); 4574 4575 pptr->virtual = sdr->sdr_virtual_phy; 4576 4577 /* 4578 * Set the routing attribute regardless of the PHY type. 4579 */ 4580 pptr->routing_attr = sdr->sdr_routing_attr; 4581 4582 switch (sdr->sdr_attached_device_type) { 4583 case SAS_IF_DTYPE_ENDPOINT: 4584 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4585 "exp_content: %s atdt=0x%x lr=%x is=%x ts=%x SAS=" 4586 SAS_ADDR_FMT " attSAS=" SAS_ADDR_FMT " atPHY=%x", 4587 pptr->path, 4588 sdr->sdr_attached_device_type, 4589 sdr->sdr_negotiated_logical_link_rate, 4590 ini_support, 4591 tgt_support, 4592 SAS_ADDR_PRT(sas_address), 4593 SAS_ADDR_PRT(att_sas_address), 4594 sdr->sdr_attached_phy_identifier); 4595 4596 if (sdr->sdr_attached_sata_device || 4597 sdr->sdr_attached_stp_target) { 4598 pptr->dtype = SATA; 4599 } else if (sdr->sdr_attached_ssp_target) { 4600 pptr->dtype = SAS; 4601 } else if (tgt_support || ini_support) { 4602 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4603 "%s: %s has tgt support=%x init support=(%x)", 4604 __func__, pptr->path, tgt_support, ini_support); 4605 } 4606 4607 switch (pptr->routing_attr) { 4608 case SMP_ROUTING_SUBTRACTIVE: 4609 case SMP_ROUTING_TABLE: 4610 case SMP_ROUTING_DIRECT: 4611 pptr->routing_method = SMP_ROUTING_DIRECT; 4612 break; 4613 default: 4614 pptr->routing_method = 0xff; /* Invalid method */ 4615 break; 4616 } 4617 pmcs_update_phy_pm_props(pptr, (1ULL << pptr->phynum), 4618 (1ULL << sdr->sdr_attached_phy_identifier), B_TRUE); 4619 break; 4620 case SAS_IF_DTYPE_EDGE: 4621 case SAS_IF_DTYPE_FANOUT: 4622 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4623 "exp_content: %s atdt=0x%x lr=%x is=%x ts=%x SAS=" 4624 SAS_ADDR_FMT " attSAS=" SAS_ADDR_FMT " atPHY=%x", 4625 pptr->path, 4626 sdr->sdr_attached_device_type, 4627 sdr->sdr_negotiated_logical_link_rate, 4628 ini_support, 4629 tgt_support, 4630 SAS_ADDR_PRT(sas_address), 4631 SAS_ADDR_PRT(att_sas_address), 4632 sdr->sdr_attached_phy_identifier); 4633 if (sdr->sdr_attached_smp_target) { 4634 /* 4635 * Avoid configuring phys that just point back 4636 * at a parent phy 4637 */ 4638 if (expander->parent && 4639 memcmp(expander->parent->sas_address, 4640 att_sas_address, 4641 sizeof (expander->parent->sas_address)) == 0) { 4642 pmcs_prt(pwp, PMCS_PRT_DEBUG3, pptr, NULL, 4643 "%s: skipping port back to parent " 4644 "expander (%s)", __func__, pptr->path); 4645 pptr->dtype = NOTHING; 4646 break; 4647 } 4648 pptr->dtype = EXPANDER; 4649 4650 } else if (tgt_support || ini_support) { 4651 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4652 "%s has tgt support=%x init support=(%x)", 4653 pptr->path, tgt_support, ini_support); 4654 pptr->dtype = EXPANDER; 4655 } 4656 if (pptr->routing_attr == SMP_ROUTING_DIRECT) { 4657 pptr->routing_method = 0xff; /* Invalid method */ 4658 } else { 4659 pptr->routing_method = pptr->routing_attr; 4660 } 4661 pmcs_update_phy_pm_props(pptr, (1ULL << pptr->phynum), 4662 (1ULL << sdr->sdr_attached_phy_identifier), B_TRUE); 4663 break; 4664 default: 4665 pptr->dtype = NOTHING; 4666 break; 4667 } 4668 if (pptr->dtype != NOTHING) { 4669 pmcs_phy_t *ctmp; 4670 4671 /* 4672 * If the attached device is a SATA device and the expander 4673 * is (possibly) a SAS2 compliant expander, check for whether 4674 * there is a NAA=5 WWN field starting at this offset and 4675 * use that for the SAS Address for this device. 4676 */ 4677 if (expander->tolerates_sas2 && pptr->dtype == SATA && 4678 (roff[SAS_ATTACHED_NAME_OFFSET] >> 8) == NAA_IEEE_REG) { 4679 (void) memcpy(pptr->sas_address, 4680 &roff[SAS_ATTACHED_NAME_OFFSET], 8); 4681 } else { 4682 (void) memcpy(pptr->sas_address, att_sas_address, 8); 4683 } 4684 pptr->atdt = (sdr->sdr_attached_device_type); 4685 /* 4686 * Now run up from the expander's parent up to the top to 4687 * make sure we only use the least common link_rate. 4688 */ 4689 for (ctmp = expander->parent; ctmp; ctmp = ctmp->parent) { 4690 if (ctmp->link_rate < 4691 sdr->sdr_negotiated_logical_link_rate) { 4692 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, pptr, NULL, 4693 "%s: derating link rate from %x to %x due " 4694 "to %s being slower", pptr->path, 4695 sdr->sdr_negotiated_logical_link_rate, 4696 ctmp->link_rate, 4697 ctmp->path); 4698 sdr->sdr_negotiated_logical_link_rate = 4699 ctmp->link_rate; 4700 } 4701 } 4702 pptr->link_rate = sdr->sdr_negotiated_logical_link_rate; 4703 pptr->state.prog_min_rate = sdr->sdr_prog_min_phys_link_rate; 4704 pptr->state.hw_min_rate = sdr->sdr_hw_min_phys_link_rate; 4705 pptr->state.prog_max_rate = sdr->sdr_prog_max_phys_link_rate; 4706 pptr->state.hw_max_rate = sdr->sdr_hw_max_phys_link_rate; 4707 PHY_CHANGED(pwp, pptr); 4708 } else { 4709 pmcs_clear_phy(pwp, pptr); 4710 } 4711 result = 1; 4712 out: 4713 return (result); 4714 } 4715 4716 /* 4717 * Get a work structure and assign it a tag with type and serial number 4718 * If a structure is returned, it is returned locked. 4719 */ 4720 pmcwork_t * 4721 pmcs_gwork(pmcs_hw_t *pwp, uint32_t tag_type, pmcs_phy_t *phyp) 4722 { 4723 pmcwork_t *p; 4724 uint16_t snum; 4725 uint32_t off; 4726 4727 mutex_enter(&pwp->wfree_lock); 4728 p = STAILQ_FIRST(&pwp->wf); 4729 if (p == NULL) { 4730 /* 4731 * If we couldn't get a work structure, it's time to bite 4732 * the bullet, grab the pfree_lock and copy over all the 4733 * work structures from the pending free list to the actual 4734 * free list (assuming it's not also empty). 4735 */ 4736 mutex_enter(&pwp->pfree_lock); 4737 if (STAILQ_FIRST(&pwp->pf) == NULL) { 4738 mutex_exit(&pwp->pfree_lock); 4739 mutex_exit(&pwp->wfree_lock); 4740 return (NULL); 4741 } 4742 pwp->wf.stqh_first = pwp->pf.stqh_first; 4743 pwp->wf.stqh_last = pwp->pf.stqh_last; 4744 STAILQ_INIT(&pwp->pf); 4745 mutex_exit(&pwp->pfree_lock); 4746 4747 p = STAILQ_FIRST(&pwp->wf); 4748 ASSERT(p != NULL); 4749 } 4750 STAILQ_REMOVE(&pwp->wf, p, pmcwork, next); 4751 snum = pwp->wserno++; 4752 mutex_exit(&pwp->wfree_lock); 4753 4754 off = p - pwp->work; 4755 4756 mutex_enter(&p->lock); 4757 ASSERT(p->state == PMCS_WORK_STATE_NIL); 4758 ASSERT(p->htag == PMCS_TAG_FREE); 4759 p->htag = (tag_type << PMCS_TAG_TYPE_SHIFT) & PMCS_TAG_TYPE_MASK; 4760 p->htag |= ((snum << PMCS_TAG_SERNO_SHIFT) & PMCS_TAG_SERNO_MASK); 4761 p->htag |= ((off << PMCS_TAG_INDEX_SHIFT) & PMCS_TAG_INDEX_MASK); 4762 p->start = gethrtime(); 4763 p->state = PMCS_WORK_STATE_READY; 4764 p->ssp_event = 0; 4765 p->dead = 0; 4766 p->timer = 0; 4767 4768 if (phyp) { 4769 p->phy = phyp; 4770 pmcs_inc_phy_ref_count(phyp); 4771 } 4772 4773 return (p); 4774 } 4775 4776 /* 4777 * Called with pwrk lock held. Returned with lock released. 4778 */ 4779 void 4780 pmcs_pwork(pmcs_hw_t *pwp, pmcwork_t *p) 4781 { 4782 ASSERT(p != NULL); 4783 ASSERT(mutex_owned(&p->lock)); 4784 4785 p->last_ptr = p->ptr; 4786 p->last_arg = p->arg; 4787 p->last_phy = p->phy; 4788 p->last_xp = p->xp; 4789 p->last_htag = p->htag; 4790 p->last_state = p->state; 4791 p->finish = gethrtime(); 4792 4793 if (p->phy) { 4794 pmcs_dec_phy_ref_count(p->phy); 4795 } 4796 4797 p->state = PMCS_WORK_STATE_NIL; 4798 p->htag = PMCS_TAG_FREE; 4799 p->xp = NULL; 4800 p->ptr = NULL; 4801 p->arg = NULL; 4802 p->phy = NULL; 4803 p->abt_htag = 0; 4804 p->timer = 0; 4805 p->onwire = 0; 4806 mutex_exit(&p->lock); 4807 4808 if (mutex_tryenter(&pwp->wfree_lock) == 0) { 4809 mutex_enter(&pwp->pfree_lock); 4810 STAILQ_INSERT_TAIL(&pwp->pf, p, next); 4811 mutex_exit(&pwp->pfree_lock); 4812 } else { 4813 STAILQ_INSERT_TAIL(&pwp->wf, p, next); 4814 mutex_exit(&pwp->wfree_lock); 4815 } 4816 } 4817 4818 /* 4819 * Find a work structure based upon a tag and make sure that the tag 4820 * serial number matches the work structure we've found. 4821 * If a structure is found, its lock is held upon return. 4822 * If lock_phy is B_TRUE, then lock the phy also when returning the work struct 4823 */ 4824 pmcwork_t * 4825 pmcs_tag2wp(pmcs_hw_t *pwp, uint32_t htag, boolean_t lock_phy) 4826 { 4827 pmcwork_t *p; 4828 pmcs_phy_t *phyp; 4829 uint32_t idx = PMCS_TAG_INDEX(htag); 4830 4831 p = &pwp->work[idx]; 4832 4833 mutex_enter(&p->lock); 4834 if (p->htag == htag) { 4835 if (lock_phy) { 4836 phyp = p->phy; 4837 if (phyp != NULL) { 4838 /* phy lock should be held before work lock */ 4839 mutex_exit(&p->lock); 4840 mutex_enter(&phyp->phy_lock); 4841 mutex_enter(&p->lock); 4842 } 4843 /* 4844 * Check htag again, in case the work got completed 4845 * while we dropped the work lock and got the phy lock 4846 */ 4847 if (p->htag != htag) { 4848 if (phyp != NULL) { 4849 mutex_exit(&p->lock); 4850 mutex_exit(&phyp->phy_lock); 4851 } 4852 pmcs_prt(pwp, PMCS_PRT_DEBUG, phyp, NULL, "%s: " 4853 "HTAG (0x%x) found, but work (0x%p) " 4854 "is already complete", __func__, htag, 4855 (void *)p); 4856 return (NULL); 4857 } 4858 } 4859 return (p); 4860 } 4861 mutex_exit(&p->lock); 4862 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, 4863 "INDEX 0x%x HTAG 0x%x got p->htag 0x%x", idx, htag, p->htag); 4864 return (NULL); 4865 } 4866 4867 /* 4868 * Issue an abort for a command or for all commands. 4869 * 4870 * Since this can be called from interrupt context, 4871 * we don't wait for completion if wait is not set. 4872 * 4873 * Called with PHY lock held. 4874 */ 4875 int 4876 pmcs_abort(pmcs_hw_t *pwp, pmcs_phy_t *pptr, uint32_t tag, int all_cmds, 4877 int wait) 4878 { 4879 pmcwork_t *pwrk; 4880 pmcs_xscsi_t *tgt; 4881 uint32_t msg[PMCS_MSG_SIZE], *ptr; 4882 int result, abt_type; 4883 uint32_t abt_htag, status; 4884 4885 if (pptr->abort_all_start) { 4886 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, "%s: ABORT_ALL for " 4887 "(%s) already in progress.", __func__, pptr->path); 4888 return (EBUSY); 4889 } 4890 4891 switch (pptr->dtype) { 4892 case SAS: 4893 abt_type = PMCIN_SSP_ABORT; 4894 break; 4895 case SATA: 4896 abt_type = PMCIN_SATA_ABORT; 4897 break; 4898 case EXPANDER: 4899 abt_type = PMCIN_SMP_ABORT; 4900 break; 4901 default: 4902 return (0); 4903 } 4904 4905 pwrk = pmcs_gwork(pwp, wait ? PMCS_TAG_TYPE_WAIT : PMCS_TAG_TYPE_NONE, 4906 pptr); 4907 4908 if (pwrk == NULL) { 4909 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nowrk, __func__); 4910 return (ENOMEM); 4911 } 4912 4913 pwrk->dtype = pptr->dtype; 4914 pwrk->xp = pptr->target; 4915 pwrk->htag |= PMCS_TAG_NONIO_CMD; 4916 if (wait) { 4917 pwrk->arg = msg; 4918 } 4919 if (pptr->valid_device_id == 0) { 4920 pmcs_pwork(pwp, pwrk); 4921 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4922 "%s: Invalid DeviceID", __func__); 4923 return (ENODEV); 4924 } 4925 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, abt_type)); 4926 msg[1] = LE_32(pwrk->htag); 4927 msg[2] = LE_32(pptr->device_id); 4928 if (all_cmds) { 4929 msg[3] = 0; 4930 msg[4] = LE_32(1); 4931 pwrk->ptr = NULL; 4932 pwrk->abt_htag = PMCS_ABT_HTAG_ALL; 4933 pptr->abort_all_start = gethrtime(); 4934 } else { 4935 msg[3] = LE_32(tag); 4936 msg[4] = 0; 4937 pwrk->abt_htag = tag; 4938 } 4939 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4940 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4941 if (ptr == NULL) { 4942 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 4943 pmcs_pwork(pwp, pwrk); 4944 pptr->abort_all_start = 0; 4945 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nomsg, __func__); 4946 return (ENOMEM); 4947 } 4948 4949 COPY_MESSAGE(ptr, msg, 5); 4950 if (all_cmds) { 4951 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4952 "%s: aborting all commands for %s device %s. (htag=0x%x)", 4953 __func__, pmcs_get_typename(pptr->dtype), pptr->path, 4954 msg[1]); 4955 } else { 4956 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 4957 "%s: aborting tag 0x%x for %s device %s. (htag=0x%x)", 4958 __func__, tag, pmcs_get_typename(pptr->dtype), pptr->path, 4959 msg[1]); 4960 } 4961 pwrk->state = PMCS_WORK_STATE_ONCHIP; 4962 4963 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 4964 if (!wait) { 4965 mutex_exit(&pwrk->lock); 4966 return (0); 4967 } 4968 4969 abt_htag = pwrk->htag; 4970 pmcs_unlock_phy(pptr); 4971 WAIT_FOR(pwrk, 1000, result); 4972 pmcs_pwork(pwp, pwrk); 4973 pmcs_lock_phy(pptr); 4974 tgt = pptr->target; 4975 4976 if (all_cmds) { 4977 pptr->abort_all_start = 0; 4978 cv_signal(&pptr->abort_all_cv); 4979 } 4980 4981 if (result) { 4982 if (all_cmds) { 4983 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 4984 "%s: Abort all request timed out", __func__); 4985 } else { 4986 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 4987 "%s: Abort (htag 0x%08x) request timed out", 4988 __func__, abt_htag); 4989 } 4990 if (tgt != NULL) { 4991 mutex_enter(&tgt->statlock); 4992 if ((tgt->dev_state != PMCS_DEVICE_STATE_IN_RECOVERY) && 4993 (tgt->dev_state != 4994 PMCS_DEVICE_STATE_NON_OPERATIONAL)) { 4995 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 4996 "%s: Trying DS error recovery for tgt 0x%p", 4997 __func__, (void *)tgt); 4998 (void) pmcs_send_err_recovery_cmd(pwp, 4999 PMCS_DEVICE_STATE_IN_RECOVERY, pptr, tgt); 5000 } 5001 mutex_exit(&tgt->statlock); 5002 } 5003 return (ETIMEDOUT); 5004 } 5005 5006 status = LE_32(msg[2]); 5007 if (status != PMCOUT_STATUS_OK) { 5008 /* 5009 * The only non-success status are IO_NOT_VALID & 5010 * IO_ABORT_IN_PROGRESS. 5011 * In case of IO_ABORT_IN_PROGRESS, the other ABORT cmd's 5012 * status is of concern and this duplicate cmd status can 5013 * be ignored. 5014 * If IO_NOT_VALID, that's not an error per-se. 5015 * For abort of single I/O complete the command anyway. 5016 * If, however, we were aborting all, that is a problem 5017 * as IO_NOT_VALID really means that the IO or device is 5018 * not there. So, discovery process will take of the cleanup. 5019 */ 5020 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 5021 "%s: abort result 0x%x", __func__, LE_32(msg[2])); 5022 if (all_cmds) { 5023 PHY_CHANGED(pwp, pptr); 5024 RESTART_DISCOVERY(pwp); 5025 } else { 5026 return (EINVAL); 5027 } 5028 5029 return (0); 5030 } 5031 5032 if (tgt != NULL) { 5033 mutex_enter(&tgt->statlock); 5034 if (tgt->dev_state == PMCS_DEVICE_STATE_IN_RECOVERY) { 5035 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 5036 "%s: Restoring OPERATIONAL dev_state for tgt 0x%p", 5037 __func__, (void *)tgt); 5038 (void) pmcs_send_err_recovery_cmd(pwp, 5039 PMCS_DEVICE_STATE_OPERATIONAL, pptr, tgt); 5040 } 5041 mutex_exit(&tgt->statlock); 5042 } 5043 5044 return (0); 5045 } 5046 5047 /* 5048 * Issue a task management function to an SSP device. 5049 * 5050 * Called with PHY lock held. 5051 * statlock CANNOT be held upon entry. 5052 */ 5053 int 5054 pmcs_ssp_tmf(pmcs_hw_t *pwp, pmcs_phy_t *pptr, uint8_t tmf, uint32_t tag, 5055 uint64_t lun, uint32_t *response) 5056 { 5057 int result, ds; 5058 uint8_t local[PMCS_QENTRY_SIZE << 1], *xd; 5059 sas_ssp_rsp_iu_t *rptr = (void *)local; 5060 static const uint8_t ssp_rsp_evec[] = { 5061 0x58, 0x61, 0x56, 0x72, 0x00 5062 }; 5063 uint32_t msg[PMCS_MSG_SIZE], *ptr, status; 5064 struct pmcwork *pwrk; 5065 pmcs_xscsi_t *xp; 5066 5067 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 5068 if (pwrk == NULL) { 5069 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nowrk, __func__); 5070 return (ENOMEM); 5071 } 5072 /* 5073 * NB: We use the PMCS_OQ_GENERAL outbound queue 5074 * NB: so as to not get entangled in normal I/O 5075 * NB: processing. 5076 */ 5077 pwrk->htag |= PMCS_TAG_NONIO_CMD; 5078 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 5079 PMCIN_SSP_INI_TM_START)); 5080 msg[1] = LE_32(pwrk->htag); 5081 msg[2] = LE_32(pptr->device_id); 5082 if (tmf == SAS_ABORT_TASK || tmf == SAS_QUERY_TASK) { 5083 msg[3] = LE_32(tag); 5084 } else { 5085 msg[3] = 0; 5086 } 5087 msg[4] = LE_32(tmf); 5088 msg[5] = BE_32((uint32_t)lun); 5089 msg[6] = BE_32((uint32_t)(lun >> 32)); 5090 msg[7] = LE_32(PMCIN_MESSAGE_REPORT); 5091 5092 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5093 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5094 if (ptr == NULL) { 5095 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5096 pmcs_pwork(pwp, pwrk); 5097 pmcs_prt(pwp, PMCS_PRT_ERR, pptr, NULL, pmcs_nomsg, __func__); 5098 return (ENOMEM); 5099 } 5100 COPY_MESSAGE(ptr, msg, 7); 5101 pwrk->arg = msg; 5102 pwrk->dtype = pptr->dtype; 5103 xp = pptr->target; 5104 pwrk->xp = xp; 5105 5106 if (xp != NULL) { 5107 mutex_enter(&xp->statlock); 5108 if (xp->dev_state == PMCS_DEVICE_STATE_NON_OPERATIONAL) { 5109 mutex_exit(&xp->statlock); 5110 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5111 pmcs_pwork(pwp, pwrk); 5112 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, "%s: Not " 5113 "sending '%s' because DS is '%s'", __func__, 5114 pmcs_tmf2str(tmf), pmcs_status_str 5115 (PMCOUT_STATUS_IO_DS_NON_OPERATIONAL)); 5116 return (EIO); 5117 } 5118 mutex_exit(&xp->statlock); 5119 } 5120 5121 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5122 "%s: sending '%s' to %s (lun %llu) tag 0x%x", __func__, 5123 pmcs_tmf2str(tmf), pptr->path, (unsigned long long) lun, tag); 5124 pwrk->state = PMCS_WORK_STATE_ONCHIP; 5125 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5126 5127 pmcs_unlock_phy(pptr); 5128 /* 5129 * This is a command sent to the target device, so it can take 5130 * significant amount of time to complete when path & device is busy. 5131 * Set a timeout to 20 seconds 5132 */ 5133 WAIT_FOR(pwrk, 20000, result); 5134 pmcs_pwork(pwp, pwrk); 5135 pmcs_lock_phy(pptr); 5136 xp = pptr->target; 5137 5138 if (result) { 5139 if (xp == NULL) { 5140 return (ETIMEDOUT); 5141 } 5142 5143 mutex_enter(&xp->statlock); 5144 pmcs_start_dev_state_recovery(xp, pptr); 5145 mutex_exit(&xp->statlock); 5146 return (ETIMEDOUT); 5147 } 5148 5149 status = LE_32(msg[2]); 5150 if (status != PMCOUT_STATUS_OK) { 5151 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5152 "%s: status %s for TMF %s action to %s, lun %llu", 5153 __func__, pmcs_status_str(status), pmcs_tmf2str(tmf), 5154 pptr->path, (unsigned long long) lun); 5155 if ((status == PMCOUT_STATUS_IO_DS_NON_OPERATIONAL) || 5156 (status == PMCOUT_STATUS_OPEN_CNX_ERROR_BREAK) || 5157 (status == PMCOUT_STATUS_OPEN_CNX_ERROR_IT_NEXUS_LOSS)) { 5158 ds = PMCS_DEVICE_STATE_NON_OPERATIONAL; 5159 } else if (status == PMCOUT_STATUS_IO_DS_IN_RECOVERY) { 5160 /* 5161 * If the status is IN_RECOVERY, it's an indication 5162 * that it's now time for us to request to have the 5163 * device state set to OPERATIONAL since we're the ones 5164 * that requested recovery to begin with. 5165 */ 5166 ds = PMCS_DEVICE_STATE_OPERATIONAL; 5167 } else { 5168 ds = PMCS_DEVICE_STATE_IN_RECOVERY; 5169 } 5170 if (xp != NULL) { 5171 mutex_enter(&xp->statlock); 5172 if (xp->dev_state != ds) { 5173 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5174 "%s: Sending err recovery cmd" 5175 " for tgt 0x%p (status = %s)", 5176 __func__, (void *)xp, 5177 pmcs_status_str(status)); 5178 (void) pmcs_send_err_recovery_cmd(pwp, ds, 5179 pptr, xp); 5180 } 5181 mutex_exit(&xp->statlock); 5182 } 5183 return (EIO); 5184 } else { 5185 ds = PMCS_DEVICE_STATE_OPERATIONAL; 5186 if (xp != NULL) { 5187 mutex_enter(&xp->statlock); 5188 if (xp->dev_state != ds) { 5189 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5190 "%s: Sending err recovery cmd" 5191 " for tgt 0x%p (status = %s)", 5192 __func__, (void *)xp, 5193 pmcs_status_str(status)); 5194 (void) pmcs_send_err_recovery_cmd(pwp, ds, 5195 pptr, xp); 5196 } 5197 mutex_exit(&xp->statlock); 5198 } 5199 } 5200 if (LE_32(msg[3]) == 0) { 5201 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5202 "TMF completed with no response"); 5203 return (EIO); 5204 } 5205 pmcs_endian_transform(pwp, local, &msg[5], ssp_rsp_evec); 5206 xd = (uint8_t *)(&msg[5]); 5207 xd += SAS_RSP_HDR_SIZE; 5208 if (rptr->datapres != SAS_RSP_DATAPRES_RESPONSE_DATA) { 5209 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5210 "%s: TMF response not RESPONSE DATA (0x%x)", 5211 __func__, rptr->datapres); 5212 return (EIO); 5213 } 5214 if (rptr->response_data_length != 4) { 5215 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, 5216 "Bad SAS RESPONSE DATA LENGTH", msg); 5217 return (EIO); 5218 } 5219 (void) memcpy(&status, xd, sizeof (uint32_t)); 5220 status = BE_32(status); 5221 if (response != NULL) 5222 *response = status; 5223 /* 5224 * The status is actually in the low-order byte. The upper three 5225 * bytes contain additional information for the TMFs that support them. 5226 * However, at this time we do not issue any of those. In the other 5227 * cases, the upper three bytes are supposed to be 0, but it appears 5228 * they aren't always. Just mask them off. 5229 */ 5230 switch (status & 0xff) { 5231 case SAS_RSP_TMF_COMPLETE: 5232 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5233 "%s: TMF complete", __func__); 5234 result = 0; 5235 break; 5236 case SAS_RSP_TMF_SUCCEEDED: 5237 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5238 "%s: TMF succeeded", __func__); 5239 result = 0; 5240 break; 5241 case SAS_RSP_INVALID_FRAME: 5242 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5243 "%s: TMF returned INVALID FRAME", __func__); 5244 result = EIO; 5245 break; 5246 case SAS_RSP_TMF_NOT_SUPPORTED: 5247 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5248 "%s: TMF returned TMF NOT SUPPORTED", __func__); 5249 result = EIO; 5250 break; 5251 case SAS_RSP_TMF_FAILED: 5252 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5253 "%s: TMF returned TMF FAILED", __func__); 5254 result = EIO; 5255 break; 5256 case SAS_RSP_TMF_INCORRECT_LUN: 5257 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5258 "%s: TMF returned INCORRECT LUN", __func__); 5259 result = EIO; 5260 break; 5261 case SAS_RSP_OVERLAPPED_OIPTTA: 5262 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5263 "%s: TMF returned OVERLAPPED INITIATOR PORT TRANSFER TAG " 5264 "ATTEMPTED", __func__); 5265 result = EIO; 5266 break; 5267 default: 5268 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, xp, 5269 "%s: TMF returned unknown code 0x%x", __func__, status); 5270 result = EIO; 5271 break; 5272 } 5273 return (result); 5274 } 5275 5276 /* 5277 * Called with PHY lock held and scratch acquired 5278 */ 5279 int 5280 pmcs_sata_abort_ncq(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 5281 { 5282 const char *utag_fail_fmt = "%s: untagged NCQ command failure"; 5283 const char *tag_fail_fmt = "%s: NCQ command failure (tag 0x%x)"; 5284 uint32_t msg[PMCS_QENTRY_SIZE], *ptr, result, status; 5285 uint8_t *fp = pwp->scratch, ds; 5286 fis_t fis; 5287 pmcwork_t *pwrk; 5288 pmcs_xscsi_t *tgt; 5289 5290 pwrk = pmcs_gwork(pwp, PMCS_TAG_TYPE_WAIT, pptr); 5291 if (pwrk == NULL) { 5292 return (ENOMEM); 5293 } 5294 pwrk->htag |= PMCS_TAG_NONIO_CMD; 5295 msg[0] = LE_32(PMCS_IOMB_IN_SAS(PMCS_OQ_IODONE, 5296 PMCIN_SATA_HOST_IO_START)); 5297 msg[1] = LE_32(pwrk->htag); 5298 msg[2] = LE_32(pptr->device_id); 5299 msg[3] = LE_32(512); 5300 msg[4] = LE_32(SATA_PROTOCOL_PIO | PMCIN_DATADIR_2_INI); 5301 msg[5] = LE_32((READ_LOG_EXT << 16) | (C_BIT << 8) | FIS_REG_H2DEV); 5302 msg[6] = LE_32(0x10); 5303 msg[8] = LE_32(1); 5304 msg[9] = 0; 5305 msg[10] = 0; 5306 msg[11] = 0; 5307 msg[12] = LE_32(DWORD0(pwp->scratch_dma)); 5308 msg[13] = LE_32(DWORD1(pwp->scratch_dma)); 5309 msg[14] = LE_32(512); 5310 msg[15] = 0; 5311 5312 pwrk->arg = msg; 5313 pwrk->dtype = pptr->dtype; 5314 pwrk->xp = pptr->target; 5315 5316 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5317 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5318 if (ptr == NULL) { 5319 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5320 pmcs_pwork(pwp, pwrk); 5321 return (ENOMEM); 5322 } 5323 COPY_MESSAGE(ptr, msg, PMCS_QENTRY_SIZE); 5324 pwrk->state = PMCS_WORK_STATE_ONCHIP; 5325 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5326 5327 pmcs_unlock_phy(pptr); 5328 WAIT_FOR(pwrk, 250, result); 5329 pmcs_pwork(pwp, pwrk); 5330 pmcs_lock_phy(pptr); 5331 5332 tgt = pptr->target; 5333 if (result) { 5334 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, pmcs_timeo, __func__); 5335 return (EIO); 5336 } 5337 status = LE_32(msg[2]); 5338 if (status != PMCOUT_STATUS_OK || LE_32(msg[3])) { 5339 if (tgt == NULL) { 5340 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 5341 "%s: cannot find target for phy 0x%p for " 5342 "dev state recovery", __func__, (void *)pptr); 5343 return (EIO); 5344 } 5345 5346 mutex_enter(&tgt->statlock); 5347 5348 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, "READ LOG EXT", msg); 5349 if ((status == PMCOUT_STATUS_IO_DS_NON_OPERATIONAL) || 5350 (status == PMCOUT_STATUS_OPEN_CNX_ERROR_BREAK) || 5351 (status == PMCOUT_STATUS_OPEN_CNX_ERROR_IT_NEXUS_LOSS)) { 5352 ds = PMCS_DEVICE_STATE_NON_OPERATIONAL; 5353 } else { 5354 ds = PMCS_DEVICE_STATE_IN_RECOVERY; 5355 } 5356 if (tgt->dev_state != ds) { 5357 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, "%s: Trying " 5358 "SATA DS Recovery for tgt(0x%p) for status(%s)", 5359 __func__, (void *)tgt, pmcs_status_str(status)); 5360 (void) pmcs_send_err_recovery_cmd(pwp, ds, pptr, tgt); 5361 } 5362 5363 mutex_exit(&tgt->statlock); 5364 return (EIO); 5365 } 5366 fis[0] = (fp[4] << 24) | (fp[3] << 16) | (fp[2] << 8) | FIS_REG_D2H; 5367 fis[1] = (fp[8] << 24) | (fp[7] << 16) | (fp[6] << 8) | fp[5]; 5368 fis[2] = (fp[12] << 24) | (fp[11] << 16) | (fp[10] << 8) | fp[9]; 5369 fis[3] = (fp[16] << 24) | (fp[15] << 16) | (fp[14] << 8) | fp[13]; 5370 fis[4] = 0; 5371 if (fp[0] & 0x80) { 5372 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 5373 utag_fail_fmt, __func__); 5374 } else { 5375 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, tgt, 5376 tag_fail_fmt, __func__, fp[0] & 0x1f); 5377 } 5378 pmcs_fis_dump(pwp, fis); 5379 pptr->need_rl_ext = 0; 5380 return (0); 5381 } 5382 5383 /* 5384 * Transform a structure from CPU to Device endian format, or 5385 * vice versa, based upon a transformation vector. 5386 * 5387 * A transformation vector is an array of bytes, each byte 5388 * of which is defined thusly: 5389 * 5390 * bit 7: from CPU to desired endian, otherwise from desired endian 5391 * to CPU format 5392 * bit 6: Big Endian, else Little Endian 5393 * bits 5-4: 5394 * 00 Undefined 5395 * 01 One Byte quantities 5396 * 02 Two Byte quantities 5397 * 03 Four Byte quantities 5398 * 5399 * bits 3-0: 5400 * 00 Undefined 5401 * Number of quantities to transform 5402 * 5403 * The vector is terminated by a 0 value. 5404 */ 5405 5406 void 5407 pmcs_endian_transform(pmcs_hw_t *pwp, void *orig_out, void *orig_in, 5408 const uint8_t *xfvec) 5409 { 5410 uint8_t c, *out = orig_out, *in = orig_in; 5411 5412 if (xfvec == NULL) { 5413 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 5414 "%s: null xfvec", __func__); 5415 return; 5416 } 5417 if (out == NULL) { 5418 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 5419 "%s: null out", __func__); 5420 return; 5421 } 5422 if (in == NULL) { 5423 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 5424 "%s: null in", __func__); 5425 return; 5426 } 5427 while ((c = *xfvec++) != 0) { 5428 int nbyt = (c & 0xf); 5429 int size = (c >> 4) & 0x3; 5430 int bige = (c >> 4) & 0x4; 5431 5432 switch (size) { 5433 case 1: 5434 { 5435 while (nbyt-- > 0) { 5436 *out++ = *in++; 5437 } 5438 break; 5439 } 5440 case 2: 5441 { 5442 uint16_t tmp; 5443 while (nbyt-- > 0) { 5444 (void) memcpy(&tmp, in, sizeof (uint16_t)); 5445 if (bige) { 5446 tmp = BE_16(tmp); 5447 } else { 5448 tmp = LE_16(tmp); 5449 } 5450 (void) memcpy(out, &tmp, sizeof (uint16_t)); 5451 out += sizeof (uint16_t); 5452 in += sizeof (uint16_t); 5453 } 5454 break; 5455 } 5456 case 3: 5457 { 5458 uint32_t tmp; 5459 while (nbyt-- > 0) { 5460 (void) memcpy(&tmp, in, sizeof (uint32_t)); 5461 if (bige) { 5462 tmp = BE_32(tmp); 5463 } else { 5464 tmp = LE_32(tmp); 5465 } 5466 (void) memcpy(out, &tmp, sizeof (uint32_t)); 5467 out += sizeof (uint32_t); 5468 in += sizeof (uint32_t); 5469 } 5470 break; 5471 } 5472 default: 5473 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 5474 "%s: bad size", __func__); 5475 return; 5476 } 5477 } 5478 } 5479 5480 const char * 5481 pmcs_get_rate(unsigned int linkrt) 5482 { 5483 const char *rate; 5484 switch (linkrt) { 5485 case SAS_LINK_RATE_1_5GBIT: 5486 rate = "1.5"; 5487 break; 5488 case SAS_LINK_RATE_3GBIT: 5489 rate = "3.0"; 5490 break; 5491 case SAS_LINK_RATE_6GBIT: 5492 rate = "6.0"; 5493 break; 5494 default: 5495 rate = "???"; 5496 break; 5497 } 5498 return (rate); 5499 } 5500 5501 const char * 5502 pmcs_get_typename(pmcs_dtype_t type) 5503 { 5504 switch (type) { 5505 case NOTHING: 5506 return ("NIL"); 5507 case SATA: 5508 return ("SATA"); 5509 case SAS: 5510 return ("SSP"); 5511 case EXPANDER: 5512 return ("EXPANDER"); 5513 } 5514 return ("????"); 5515 } 5516 5517 const char * 5518 pmcs_tmf2str(int tmf) 5519 { 5520 switch (tmf) { 5521 case SAS_ABORT_TASK: 5522 return ("Abort Task"); 5523 case SAS_ABORT_TASK_SET: 5524 return ("Abort Task Set"); 5525 case SAS_CLEAR_TASK_SET: 5526 return ("Clear Task Set"); 5527 case SAS_LOGICAL_UNIT_RESET: 5528 return ("Logical Unit Reset"); 5529 case SAS_I_T_NEXUS_RESET: 5530 return ("I_T Nexus Reset"); 5531 case SAS_CLEAR_ACA: 5532 return ("Clear ACA"); 5533 case SAS_QUERY_TASK: 5534 return ("Query Task"); 5535 case SAS_QUERY_TASK_SET: 5536 return ("Query Task Set"); 5537 case SAS_QUERY_UNIT_ATTENTION: 5538 return ("Query Unit Attention"); 5539 default: 5540 return ("Unknown"); 5541 } 5542 } 5543 5544 const char * 5545 pmcs_status_str(uint32_t status) 5546 { 5547 switch (status) { 5548 case PMCOUT_STATUS_OK: 5549 return ("OK"); 5550 case PMCOUT_STATUS_ABORTED: 5551 return ("ABORTED"); 5552 case PMCOUT_STATUS_OVERFLOW: 5553 return ("OVERFLOW"); 5554 case PMCOUT_STATUS_UNDERFLOW: 5555 return ("UNDERFLOW"); 5556 case PMCOUT_STATUS_FAILED: 5557 return ("FAILED"); 5558 case PMCOUT_STATUS_ABORT_RESET: 5559 return ("ABORT_RESET"); 5560 case PMCOUT_STATUS_IO_NOT_VALID: 5561 return ("IO_NOT_VALID"); 5562 case PMCOUT_STATUS_NO_DEVICE: 5563 return ("NO_DEVICE"); 5564 case PMCOUT_STATUS_ILLEGAL_PARAMETER: 5565 return ("ILLEGAL_PARAMETER"); 5566 case PMCOUT_STATUS_LINK_FAILURE: 5567 return ("LINK_FAILURE"); 5568 case PMCOUT_STATUS_PROG_ERROR: 5569 return ("PROG_ERROR"); 5570 case PMCOUT_STATUS_EDC_IN_ERROR: 5571 return ("EDC_IN_ERROR"); 5572 case PMCOUT_STATUS_EDC_OUT_ERROR: 5573 return ("EDC_OUT_ERROR"); 5574 case PMCOUT_STATUS_ERROR_HW_TIMEOUT: 5575 return ("ERROR_HW_TIMEOUT"); 5576 case PMCOUT_STATUS_XFER_ERR_BREAK: 5577 return ("XFER_ERR_BREAK"); 5578 case PMCOUT_STATUS_XFER_ERR_PHY_NOT_READY: 5579 return ("XFER_ERR_PHY_NOT_READY"); 5580 case PMCOUT_STATUS_OPEN_CNX_PROTOCOL_NOT_SUPPORTED: 5581 return ("OPEN_CNX_PROTOCOL_NOT_SUPPORTED"); 5582 case PMCOUT_STATUS_OPEN_CNX_ERROR_ZONE_VIOLATION: 5583 return ("OPEN_CNX_ERROR_ZONE_VIOLATION"); 5584 case PMCOUT_STATUS_OPEN_CNX_ERROR_BREAK: 5585 return ("OPEN_CNX_ERROR_BREAK"); 5586 case PMCOUT_STATUS_OPEN_CNX_ERROR_IT_NEXUS_LOSS: 5587 return ("OPEN_CNX_ERROR_IT_NEXUS_LOSS"); 5588 case PMCOUT_STATUS_OPENCNX_ERROR_BAD_DESTINATION: 5589 return ("OPENCNX_ERROR_BAD_DESTINATION"); 5590 case PMCOUT_STATUS_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 5591 return ("OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED"); 5592 case PMCOUT_STATUS_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 5593 return ("OPEN_CNX_ERROR_STP_RESOURCES_BUSY"); 5594 case PMCOUT_STATUS_OPEN_CNX_ERROR_WRONG_DESTINATION: 5595 return ("OPEN_CNX_ERROR_WRONG_DESTINATION"); 5596 case PMCOUT_STATUS_OPEN_CNX_ERROR_UNKNOWN_ERROR: 5597 return ("OPEN_CNX_ERROR_UNKNOWN_ERROR"); 5598 case PMCOUT_STATUS_IO_XFER_ERROR_NAK_RECEIVED: 5599 return ("IO_XFER_ERROR_NAK_RECEIVED"); 5600 case PMCOUT_STATUS_XFER_ERROR_ACK_NAK_TIMEOUT: 5601 return ("XFER_ERROR_ACK_NAK_TIMEOUT"); 5602 case PMCOUT_STATUS_XFER_ERROR_PEER_ABORTED: 5603 return ("XFER_ERROR_PEER_ABORTED"); 5604 case PMCOUT_STATUS_XFER_ERROR_RX_FRAME: 5605 return ("XFER_ERROR_RX_FRAME"); 5606 case PMCOUT_STATUS_IO_XFER_ERROR_DMA: 5607 return ("IO_XFER_ERROR_DMA"); 5608 case PMCOUT_STATUS_XFER_ERROR_CREDIT_TIMEOUT: 5609 return ("XFER_ERROR_CREDIT_TIMEOUT"); 5610 case PMCOUT_STATUS_XFER_ERROR_SATA_LINK_TIMEOUT: 5611 return ("XFER_ERROR_SATA_LINK_TIMEOUT"); 5612 case PMCOUT_STATUS_XFER_ERROR_SATA: 5613 return ("XFER_ERROR_SATA"); 5614 case PMCOUT_STATUS_XFER_ERROR_REJECTED_NCQ_MODE: 5615 return ("XFER_ERROR_REJECTED_NCQ_MODE"); 5616 case PMCOUT_STATUS_XFER_ERROR_ABORTED_DUE_TO_SRST: 5617 return ("XFER_ERROR_ABORTED_DUE_TO_SRST"); 5618 case PMCOUT_STATUS_XFER_ERROR_ABORTED_NCQ_MODE: 5619 return ("XFER_ERROR_ABORTED_NCQ_MODE"); 5620 case PMCOUT_STATUS_IO_XFER_OPEN_RETRY_TIMEOUT: 5621 return ("IO_XFER_OPEN_RETRY_TIMEOUT"); 5622 case PMCOUT_STATUS_SMP_RESP_CONNECTION_ERROR: 5623 return ("SMP_RESP_CONNECTION_ERROR"); 5624 case PMCOUT_STATUS_XFER_ERROR_UNEXPECTED_PHASE: 5625 return ("XFER_ERROR_UNEXPECTED_PHASE"); 5626 case PMCOUT_STATUS_XFER_ERROR_RDY_OVERRUN: 5627 return ("XFER_ERROR_RDY_OVERRUN"); 5628 case PMCOUT_STATUS_XFER_ERROR_RDY_NOT_EXPECTED: 5629 return ("XFER_ERROR_RDY_NOT_EXPECTED"); 5630 case PMCOUT_STATUS_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT: 5631 return ("XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT"); 5632 case PMCOUT_STATUS_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NACK: 5633 return ("XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NACK"); 5634 case PMCOUT_STATUS_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK: 5635 return ("XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK"); 5636 case PMCOUT_STATUS_XFER_ERROR_OFFSET_MISMATCH: 5637 return ("XFER_ERROR_OFFSET_MISMATCH"); 5638 case PMCOUT_STATUS_XFER_ERROR_ZERO_DATA_LEN: 5639 return ("XFER_ERROR_ZERO_DATA_LEN"); 5640 case PMCOUT_STATUS_XFER_CMD_FRAME_ISSUED: 5641 return ("XFER_CMD_FRAME_ISSUED"); 5642 case PMCOUT_STATUS_ERROR_INTERNAL_SMP_RESOURCE: 5643 return ("ERROR_INTERNAL_SMP_RESOURCE"); 5644 case PMCOUT_STATUS_IO_PORT_IN_RESET: 5645 return ("IO_PORT_IN_RESET"); 5646 case PMCOUT_STATUS_IO_DS_NON_OPERATIONAL: 5647 return ("DEVICE STATE NON-OPERATIONAL"); 5648 case PMCOUT_STATUS_IO_DS_IN_RECOVERY: 5649 return ("DEVICE STATE IN RECOVERY"); 5650 case PMCOUT_STATUS_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 5651 return ("OPEN CNX ERR HW RESOURCE BUSY"); 5652 default: 5653 return (NULL); 5654 } 5655 } 5656 5657 uint64_t 5658 pmcs_barray2wwn(uint8_t ba[8]) 5659 { 5660 uint64_t result = 0; 5661 int i; 5662 5663 for (i = 0; i < 8; i++) { 5664 result <<= 8; 5665 result |= ba[i]; 5666 } 5667 return (result); 5668 } 5669 5670 void 5671 pmcs_wwn2barray(uint64_t wwn, uint8_t ba[8]) 5672 { 5673 int i; 5674 for (i = 0; i < 8; i++) { 5675 ba[7 - i] = wwn & 0xff; 5676 wwn >>= 8; 5677 } 5678 } 5679 5680 void 5681 pmcs_report_fwversion(pmcs_hw_t *pwp) 5682 { 5683 const char *fwsupport; 5684 switch (PMCS_FW_TYPE(pwp)) { 5685 case PMCS_FW_TYPE_RELEASED: 5686 fwsupport = "Released"; 5687 break; 5688 case PMCS_FW_TYPE_DEVELOPMENT: 5689 fwsupport = "Development"; 5690 break; 5691 case PMCS_FW_TYPE_ALPHA: 5692 fwsupport = "Alpha"; 5693 break; 5694 case PMCS_FW_TYPE_BETA: 5695 fwsupport = "Beta"; 5696 break; 5697 default: 5698 fwsupport = "Special"; 5699 break; 5700 } 5701 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 5702 "Chip Revision: %c; F/W Revision %x.%x.%x %s (ILA rev %08x)", 5703 'A' + pwp->chiprev, PMCS_FW_MAJOR(pwp), PMCS_FW_MINOR(pwp), 5704 PMCS_FW_MICRO(pwp), fwsupport, pwp->ila_ver); 5705 } 5706 5707 void 5708 pmcs_phy_name(pmcs_hw_t *pwp, pmcs_phy_t *pptr, char *obuf, size_t olen) 5709 { 5710 if (pptr->parent) { 5711 pmcs_phy_name(pwp, pptr->parent, obuf, olen); 5712 (void) snprintf(obuf, olen, "%s.%02x", obuf, pptr->phynum); 5713 } else { 5714 (void) snprintf(obuf, olen, "pp%02x", pptr->phynum); 5715 } 5716 } 5717 5718 /* 5719 * This function is called as a sanity check to ensure that a newly registered 5720 * PHY doesn't have a device_id that exists with another registered PHY. 5721 */ 5722 static boolean_t 5723 pmcs_validate_devid(pmcs_phy_t *parent, pmcs_phy_t *phyp, uint32_t device_id) 5724 { 5725 pmcs_phy_t *pptr, *pchild; 5726 boolean_t rval; 5727 5728 pptr = parent; 5729 5730 while (pptr) { 5731 if (pptr->valid_device_id && (pptr != phyp) && 5732 (pptr->device_id == device_id)) { 5733 /* 5734 * This can still be OK if both of these PHYs actually 5735 * represent the same device (e.g. expander). It could 5736 * be a case of a new "primary" PHY. If the SAS address 5737 * is the same and they have the same parent, we'll 5738 * accept this if the PHY to be registered is the 5739 * primary. 5740 */ 5741 if ((phyp->parent == pptr->parent) && 5742 (memcmp(phyp->sas_address, 5743 pptr->sas_address, 8) == 0) && (phyp->width > 1)) { 5744 /* 5745 * Move children over to the new primary and 5746 * update both PHYs 5747 */ 5748 pmcs_lock_phy(pptr); 5749 phyp->children = pptr->children; 5750 pchild = phyp->children; 5751 while (pchild) { 5752 pchild->parent = phyp; 5753 pchild = pchild->sibling; 5754 } 5755 phyp->subsidiary = 0; 5756 phyp->ncphy = pptr->ncphy; 5757 /* 5758 * device_id, valid_device_id, and configured 5759 * will be set by the caller 5760 */ 5761 pptr->children = NULL; 5762 pptr->subsidiary = 1; 5763 pptr->ncphy = 0; 5764 pmcs_unlock_phy(pptr); 5765 pmcs_prt(pptr->pwp, PMCS_PRT_DEBUG, pptr, NULL, 5766 "%s: Moving device_id %d from PHY %s to %s", 5767 __func__, device_id, pptr->path, 5768 phyp->path); 5769 return (B_TRUE); 5770 } 5771 pmcs_prt(pptr->pwp, PMCS_PRT_DEBUG, pptr, NULL, 5772 "%s: phy %s already exists as %s with " 5773 "device id 0x%x", __func__, phyp->path, 5774 pptr->path, device_id); 5775 return (B_FALSE); 5776 } 5777 5778 if (pptr->children) { 5779 rval = pmcs_validate_devid(pptr->children, phyp, 5780 device_id); 5781 if (rval == B_FALSE) { 5782 return (rval); 5783 } 5784 } 5785 5786 pptr = pptr->sibling; 5787 } 5788 5789 /* This PHY and device_id are valid */ 5790 return (B_TRUE); 5791 } 5792 5793 /* 5794 * If the PHY is found, it is returned locked 5795 */ 5796 static pmcs_phy_t * 5797 pmcs_find_phy_by_wwn_impl(pmcs_phy_t *phyp, uint8_t *wwn) 5798 { 5799 pmcs_phy_t *matched_phy, *cphyp, *nphyp; 5800 5801 ASSERT(!mutex_owned(&phyp->phy_lock)); 5802 5803 while (phyp) { 5804 pmcs_lock_phy(phyp); 5805 5806 if (phyp->valid_device_id) { 5807 if (memcmp(phyp->sas_address, wwn, 8) == 0) { 5808 return (phyp); 5809 } 5810 } 5811 5812 if (phyp->children) { 5813 cphyp = phyp->children; 5814 pmcs_unlock_phy(phyp); 5815 matched_phy = pmcs_find_phy_by_wwn_impl(cphyp, wwn); 5816 if (matched_phy) { 5817 ASSERT(mutex_owned(&matched_phy->phy_lock)); 5818 return (matched_phy); 5819 } 5820 pmcs_lock_phy(phyp); 5821 } 5822 5823 /* 5824 * Only iterate through non-root PHYs 5825 */ 5826 if (IS_ROOT_PHY(phyp)) { 5827 pmcs_unlock_phy(phyp); 5828 phyp = NULL; 5829 } else { 5830 nphyp = phyp->sibling; 5831 pmcs_unlock_phy(phyp); 5832 phyp = nphyp; 5833 } 5834 } 5835 5836 return (NULL); 5837 } 5838 5839 pmcs_phy_t * 5840 pmcs_find_phy_by_wwn(pmcs_hw_t *pwp, uint64_t wwn) 5841 { 5842 uint8_t ebstr[8]; 5843 pmcs_phy_t *pptr, *matched_phy; 5844 5845 pmcs_wwn2barray(wwn, ebstr); 5846 5847 pptr = pwp->root_phys; 5848 while (pptr) { 5849 matched_phy = pmcs_find_phy_by_wwn_impl(pptr, ebstr); 5850 if (matched_phy) { 5851 ASSERT(mutex_owned(&matched_phy->phy_lock)); 5852 return (matched_phy); 5853 } 5854 5855 pptr = pptr->sibling; 5856 } 5857 5858 return (NULL); 5859 } 5860 5861 5862 /* 5863 * pmcs_find_phy_by_sas_address 5864 * 5865 * Find a PHY that both matches "sas_addr" and is on "iport". 5866 * If a matching PHY is found, it is returned locked. 5867 */ 5868 pmcs_phy_t * 5869 pmcs_find_phy_by_sas_address(pmcs_hw_t *pwp, pmcs_iport_t *iport, 5870 pmcs_phy_t *root, char *sas_addr) 5871 { 5872 int ua_form = 1; 5873 uint64_t wwn; 5874 char addr[PMCS_MAX_UA_SIZE]; 5875 pmcs_phy_t *pptr, *pnext, *pchild; 5876 5877 if (root == NULL) { 5878 pptr = pwp->root_phys; 5879 } else { 5880 pptr = root; 5881 } 5882 5883 while (pptr) { 5884 pmcs_lock_phy(pptr); 5885 /* 5886 * If the PHY is dead or does not have a valid device ID, 5887 * skip it. 5888 */ 5889 if ((pptr->dead) || (!pptr->valid_device_id)) { 5890 goto next_phy; 5891 } 5892 5893 if (pptr->iport != iport) { 5894 goto next_phy; 5895 } 5896 5897 wwn = pmcs_barray2wwn(pptr->sas_address); 5898 (void *) scsi_wwn_to_wwnstr(wwn, ua_form, addr); 5899 if (strncmp(addr, sas_addr, strlen(addr)) == 0) { 5900 return (pptr); 5901 } 5902 5903 if (pptr->children) { 5904 pchild = pptr->children; 5905 pmcs_unlock_phy(pptr); 5906 pnext = pmcs_find_phy_by_sas_address(pwp, iport, pchild, 5907 sas_addr); 5908 if (pnext) { 5909 return (pnext); 5910 } 5911 pmcs_lock_phy(pptr); 5912 } 5913 5914 next_phy: 5915 pnext = pptr->sibling; 5916 pmcs_unlock_phy(pptr); 5917 pptr = pnext; 5918 } 5919 5920 return (NULL); 5921 } 5922 5923 void 5924 pmcs_fis_dump(pmcs_hw_t *pwp, fis_t fis) 5925 { 5926 switch (fis[0] & 0xff) { 5927 case FIS_REG_H2DEV: 5928 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 5929 "FIS REGISTER HOST TO DEVICE: " 5930 "OP=0x%02x Feature=0x%04x Count=0x%04x Device=0x%02x " 5931 "LBA=%llu", BYTE2(fis[0]), BYTE3(fis[2]) << 8 | 5932 BYTE3(fis[0]), WORD0(fis[3]), BYTE3(fis[1]), 5933 (unsigned long long) 5934 (((uint64_t)fis[2] & 0x00ffffff) << 24 | 5935 ((uint64_t)fis[1] & 0x00ffffff))); 5936 break; 5937 case FIS_REG_D2H: 5938 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 5939 "FIS REGISTER DEVICE TO HOST: Status=0x%02x " 5940 "Error=0x%02x Dev=0x%02x Count=0x%04x LBA=%llu", 5941 BYTE2(fis[0]), BYTE3(fis[0]), BYTE3(fis[1]), WORD0(fis[3]), 5942 (unsigned long long)(((uint64_t)fis[2] & 0x00ffffff) << 24 | 5943 ((uint64_t)fis[1] & 0x00ffffff))); 5944 break; 5945 default: 5946 pmcs_prt(pwp, PMCS_PRT_INFO, NULL, NULL, 5947 "FIS: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", 5948 fis[0], fis[1], fis[2], fis[3], fis[4]); 5949 break; 5950 } 5951 } 5952 5953 void 5954 pmcs_print_entry(pmcs_hw_t *pwp, int level, char *msg, void *arg) 5955 { 5956 uint32_t *mb = arg; 5957 size_t i; 5958 5959 pmcs_prt(pwp, level, NULL, NULL, msg); 5960 for (i = 0; i < (PMCS_QENTRY_SIZE / sizeof (uint32_t)); i += 4) { 5961 pmcs_prt(pwp, level, NULL, NULL, 5962 "Offset %2lu: 0x%08x 0x%08x 0x%08x 0x%08x", 5963 i * sizeof (uint32_t), LE_32(mb[i]), 5964 LE_32(mb[i+1]), LE_32(mb[i+2]), LE_32(mb[i+3])); 5965 } 5966 } 5967 5968 /* 5969 * If phyp == NULL we're being called from the worker thread, in which 5970 * case we need to check all the PHYs. In this case, the softstate lock 5971 * will be held. 5972 * If phyp is non-NULL, just issue the spinup release for the specified PHY 5973 * (which will already be locked). 5974 */ 5975 void 5976 pmcs_spinup_release(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 5977 { 5978 uint32_t *msg; 5979 struct pmcwork *pwrk; 5980 pmcs_phy_t *tphyp; 5981 5982 if (phyp != NULL) { 5983 ASSERT(mutex_owned(&phyp->phy_lock)); 5984 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, phyp, NULL, 5985 "%s: Issuing spinup release only for PHY %s", __func__, 5986 phyp->path); 5987 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5988 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 5989 if (msg == NULL || (pwrk = 5990 pmcs_gwork(pwp, PMCS_TAG_TYPE_NONE, NULL)) == NULL) { 5991 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 5992 SCHEDULE_WORK(pwp, PMCS_WORK_SPINUP_RELEASE); 5993 return; 5994 } 5995 5996 phyp->spinup_hold = 0; 5997 bzero(msg, PMCS_QENTRY_SIZE); 5998 pwrk->htag |= PMCS_TAG_NONIO_CMD; 5999 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 6000 PMCIN_LOCAL_PHY_CONTROL)); 6001 msg[1] = LE_32(pwrk->htag); 6002 msg[2] = LE_32((0x10 << 8) | phyp->phynum); 6003 6004 pwrk->dtype = phyp->dtype; 6005 pwrk->state = PMCS_WORK_STATE_ONCHIP; 6006 pwrk->xp = phyp->target; 6007 mutex_exit(&pwrk->lock); 6008 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 6009 return; 6010 } 6011 6012 ASSERT(mutex_owned(&pwp->lock)); 6013 6014 tphyp = pwp->root_phys; 6015 while (tphyp) { 6016 pmcs_lock_phy(tphyp); 6017 if (tphyp->spinup_hold == 0) { 6018 pmcs_unlock_phy(tphyp); 6019 tphyp = tphyp->sibling; 6020 continue; 6021 } 6022 6023 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, tphyp, NULL, 6024 "%s: Issuing spinup release for PHY %s", __func__, 6025 tphyp->path); 6026 6027 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 6028 msg = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 6029 if (msg == NULL || (pwrk = 6030 pmcs_gwork(pwp, PMCS_TAG_TYPE_NONE, NULL)) == NULL) { 6031 pmcs_unlock_phy(tphyp); 6032 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 6033 SCHEDULE_WORK(pwp, PMCS_WORK_SPINUP_RELEASE); 6034 break; 6035 } 6036 6037 tphyp->spinup_hold = 0; 6038 bzero(msg, PMCS_QENTRY_SIZE); 6039 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 6040 PMCIN_LOCAL_PHY_CONTROL)); 6041 msg[1] = LE_32(pwrk->htag); 6042 msg[2] = LE_32((0x10 << 8) | tphyp->phynum); 6043 6044 pwrk->dtype = tphyp->dtype; 6045 pwrk->state = PMCS_WORK_STATE_ONCHIP; 6046 pwrk->xp = tphyp->target; 6047 mutex_exit(&pwrk->lock); 6048 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 6049 pmcs_unlock_phy(tphyp); 6050 6051 tphyp = tphyp->sibling; 6052 } 6053 } 6054 6055 /* 6056 * Abort commands on dead PHYs and deregister them as well as removing 6057 * the associated targets. 6058 */ 6059 static int 6060 pmcs_kill_devices(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 6061 { 6062 pmcs_phy_t *pnext, *pchild; 6063 boolean_t remove_device; 6064 int rval = 0; 6065 6066 while (phyp) { 6067 pmcs_lock_phy(phyp); 6068 pchild = phyp->children; 6069 pnext = phyp->sibling; 6070 pmcs_unlock_phy(phyp); 6071 6072 if (pchild) { 6073 rval = pmcs_kill_devices(pwp, pchild); 6074 if (rval) { 6075 return (rval); 6076 } 6077 } 6078 6079 mutex_enter(&pwp->lock); 6080 pmcs_lock_phy(phyp); 6081 if (phyp->dead && phyp->valid_device_id) { 6082 remove_device = B_TRUE; 6083 } else { 6084 remove_device = B_FALSE; 6085 } 6086 6087 if (remove_device) { 6088 pmcs_remove_device(pwp, phyp); 6089 mutex_exit(&pwp->lock); 6090 6091 rval = pmcs_kill_device(pwp, phyp); 6092 if (rval) { 6093 pmcs_unlock_phy(phyp); 6094 return (rval); 6095 } 6096 } else { 6097 mutex_exit(&pwp->lock); 6098 } 6099 6100 pmcs_unlock_phy(phyp); 6101 phyp = pnext; 6102 } 6103 6104 return (rval); 6105 } 6106 6107 /* 6108 * Called with PHY locked 6109 */ 6110 int 6111 pmcs_kill_device(pmcs_hw_t *pwp, pmcs_phy_t *pptr) 6112 { 6113 int rval; 6114 6115 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, "kill %s device @ %s", 6116 pmcs_get_typename(pptr->dtype), pptr->path); 6117 6118 /* 6119 * There may be an outstanding ABORT_ALL running, which we wouldn't 6120 * know just by checking abort_pending. We can, however, check 6121 * abort_all_start. If it's non-zero, there is one, and we'll just 6122 * sit here and wait for it to complete. If we don't, we'll remove 6123 * the device while there are still commands pending. 6124 */ 6125 if (pptr->abort_all_start) { 6126 while (pptr->abort_all_start) { 6127 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 6128 "%s: Waiting for outstanding ABORT_ALL on PHY 0x%p", 6129 __func__, (void *)pptr); 6130 cv_wait(&pptr->abort_all_cv, &pptr->phy_lock); 6131 } 6132 } else if (pptr->abort_pending) { 6133 rval = pmcs_abort(pwp, pptr, pptr->device_id, 1, 1); 6134 if (rval) { 6135 pmcs_prt(pwp, PMCS_PRT_DEBUG, pptr, NULL, 6136 "%s: ABORT_ALL returned non-zero status (%d) for " 6137 "PHY 0x%p", __func__, rval, (void *)pptr); 6138 return (rval); 6139 } 6140 pptr->abort_pending = 0; 6141 } 6142 6143 if (pptr->valid_device_id) { 6144 pmcs_deregister_device(pwp, pptr); 6145 } 6146 6147 PHY_CHANGED(pwp, pptr); 6148 RESTART_DISCOVERY(pwp); 6149 pptr->valid_device_id = 0; 6150 return (0); 6151 } 6152 6153 /* 6154 * Acknowledge the SAS h/w events that need acknowledgement. 6155 * This is only needed for first level PHYs. 6156 */ 6157 void 6158 pmcs_ack_events(pmcs_hw_t *pwp) 6159 { 6160 uint32_t msg[PMCS_MSG_SIZE], *ptr; 6161 struct pmcwork *pwrk; 6162 pmcs_phy_t *pptr; 6163 6164 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 6165 pmcs_lock_phy(pptr); 6166 if (pptr->hw_event_ack == 0) { 6167 pmcs_unlock_phy(pptr); 6168 continue; 6169 } 6170 mutex_enter(&pwp->iqp_lock[PMCS_IQ_OTHER]); 6171 ptr = GET_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 6172 6173 if ((ptr == NULL) || (pwrk = 6174 pmcs_gwork(pwp, PMCS_TAG_TYPE_NONE, NULL)) == NULL) { 6175 mutex_exit(&pwp->iqp_lock[PMCS_IQ_OTHER]); 6176 pmcs_unlock_phy(pptr); 6177 SCHEDULE_WORK(pwp, PMCS_WORK_SAS_HW_ACK); 6178 break; 6179 } 6180 6181 msg[0] = LE_32(PMCS_HIPRI(pwp, PMCS_OQ_GENERAL, 6182 PMCIN_SAS_HW_EVENT_ACK)); 6183 msg[1] = LE_32(pwrk->htag); 6184 msg[2] = LE_32(pptr->hw_event_ack); 6185 6186 mutex_exit(&pwrk->lock); 6187 pwrk->dtype = pptr->dtype; 6188 pptr->hw_event_ack = 0; 6189 COPY_MESSAGE(ptr, msg, 3); 6190 INC_IQ_ENTRY(pwp, PMCS_IQ_OTHER); 6191 pmcs_unlock_phy(pptr); 6192 } 6193 } 6194 6195 /* 6196 * Load DMA 6197 */ 6198 int 6199 pmcs_dma_load(pmcs_hw_t *pwp, pmcs_cmd_t *sp, uint32_t *msg) 6200 { 6201 ddi_dma_cookie_t *sg; 6202 pmcs_dmachunk_t *tc; 6203 pmcs_dmasgl_t *sgl, *prior; 6204 int seg, tsc; 6205 uint64_t sgl_addr; 6206 6207 /* 6208 * If we have no data segments, we're done. 6209 */ 6210 if (CMD2PKT(sp)->pkt_numcookies == 0) { 6211 return (0); 6212 } 6213 6214 /* 6215 * Get the S/G list pointer. 6216 */ 6217 sg = CMD2PKT(sp)->pkt_cookies; 6218 6219 /* 6220 * If we only have one dma segment, we can directly address that 6221 * data within the Inbound message itself. 6222 */ 6223 if (CMD2PKT(sp)->pkt_numcookies == 1) { 6224 msg[12] = LE_32(DWORD0(sg->dmac_laddress)); 6225 msg[13] = LE_32(DWORD1(sg->dmac_laddress)); 6226 msg[14] = LE_32(sg->dmac_size); 6227 msg[15] = 0; 6228 return (0); 6229 } 6230 6231 /* 6232 * Otherwise, we'll need one or more external S/G list chunks. 6233 * Get the first one and its dma address into the Inbound message. 6234 */ 6235 mutex_enter(&pwp->dma_lock); 6236 tc = pwp->dma_freelist; 6237 if (tc == NULL) { 6238 SCHEDULE_WORK(pwp, PMCS_WORK_ADD_DMA_CHUNKS); 6239 mutex_exit(&pwp->dma_lock); 6240 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, 6241 "%s: out of SG lists", __func__); 6242 return (-1); 6243 } 6244 pwp->dma_freelist = tc->nxt; 6245 mutex_exit(&pwp->dma_lock); 6246 6247 tc->nxt = NULL; 6248 sp->cmd_clist = tc; 6249 sgl = tc->chunks; 6250 (void) memset(tc->chunks, 0, PMCS_SGL_CHUNKSZ); 6251 sgl_addr = tc->addr; 6252 msg[12] = LE_32(DWORD0(sgl_addr)); 6253 msg[13] = LE_32(DWORD1(sgl_addr)); 6254 msg[14] = 0; 6255 msg[15] = LE_32(PMCS_DMASGL_EXTENSION); 6256 6257 prior = sgl; 6258 tsc = 0; 6259 6260 for (seg = 0; seg < CMD2PKT(sp)->pkt_numcookies; seg++) { 6261 /* 6262 * If the current segment count for this chunk is one less than 6263 * the number s/g lists per chunk and we have more than one seg 6264 * to go, we need another chunk. Get it, and make sure that the 6265 * tail end of the the previous chunk points the new chunk 6266 * (if remembering an offset can be called 'pointing to'). 6267 * 6268 * Note that we can store the offset into our command area that 6269 * represents the new chunk in the length field of the part 6270 * that points the PMC chip at the next chunk- the PMC chip 6271 * ignores this field when the EXTENSION bit is set. 6272 * 6273 * This is required for dma unloads later. 6274 */ 6275 if (tsc == (PMCS_SGL_NCHUNKS - 1) && 6276 seg < (CMD2PKT(sp)->pkt_numcookies - 1)) { 6277 mutex_enter(&pwp->dma_lock); 6278 tc = pwp->dma_freelist; 6279 if (tc == NULL) { 6280 SCHEDULE_WORK(pwp, PMCS_WORK_ADD_DMA_CHUNKS); 6281 mutex_exit(&pwp->dma_lock); 6282 pmcs_dma_unload(pwp, sp); 6283 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, 6284 "%s: out of SG lists", __func__); 6285 return (-1); 6286 } 6287 pwp->dma_freelist = tc->nxt; 6288 tc->nxt = sp->cmd_clist; 6289 mutex_exit(&pwp->dma_lock); 6290 6291 sp->cmd_clist = tc; 6292 (void) memset(tc->chunks, 0, PMCS_SGL_CHUNKSZ); 6293 sgl = tc->chunks; 6294 sgl_addr = tc->addr; 6295 prior[PMCS_SGL_NCHUNKS-1].sglal = 6296 LE_32(DWORD0(sgl_addr)); 6297 prior[PMCS_SGL_NCHUNKS-1].sglah = 6298 LE_32(DWORD1(sgl_addr)); 6299 prior[PMCS_SGL_NCHUNKS-1].sglen = 0; 6300 prior[PMCS_SGL_NCHUNKS-1].flags = 6301 LE_32(PMCS_DMASGL_EXTENSION); 6302 prior = sgl; 6303 tsc = 0; 6304 } 6305 sgl[tsc].sglal = LE_32(DWORD0(sg->dmac_laddress)); 6306 sgl[tsc].sglah = LE_32(DWORD1(sg->dmac_laddress)); 6307 sgl[tsc].sglen = LE_32(sg->dmac_size); 6308 sgl[tsc++].flags = 0; 6309 sg++; 6310 } 6311 return (0); 6312 } 6313 6314 /* 6315 * Unload DMA 6316 */ 6317 void 6318 pmcs_dma_unload(pmcs_hw_t *pwp, pmcs_cmd_t *sp) 6319 { 6320 pmcs_dmachunk_t *cp; 6321 6322 mutex_enter(&pwp->dma_lock); 6323 while ((cp = sp->cmd_clist) != NULL) { 6324 sp->cmd_clist = cp->nxt; 6325 cp->nxt = pwp->dma_freelist; 6326 pwp->dma_freelist = cp; 6327 } 6328 mutex_exit(&pwp->dma_lock); 6329 } 6330 6331 /* 6332 * Take a chunk of consistent memory that has just been allocated and inserted 6333 * into the cip indices and prepare it for DMA chunk usage and add it to the 6334 * freelist. 6335 * 6336 * Called with dma_lock locked (except during attach when it's unnecessary) 6337 */ 6338 void 6339 pmcs_idma_chunks(pmcs_hw_t *pwp, pmcs_dmachunk_t *dcp, 6340 pmcs_chunk_t *pchunk, unsigned long lim) 6341 { 6342 unsigned long off, n; 6343 pmcs_dmachunk_t *np = dcp; 6344 pmcs_chunk_t *tmp_chunk; 6345 6346 if (pwp->dma_chunklist == NULL) { 6347 pwp->dma_chunklist = pchunk; 6348 } else { 6349 tmp_chunk = pwp->dma_chunklist; 6350 while (tmp_chunk->next) { 6351 tmp_chunk = tmp_chunk->next; 6352 } 6353 tmp_chunk->next = pchunk; 6354 } 6355 6356 /* 6357 * Install offsets into chunk lists. 6358 */ 6359 for (n = 0, off = 0; off < lim; off += PMCS_SGL_CHUNKSZ, n++) { 6360 np->chunks = (void *)&pchunk->addrp[off]; 6361 np->addr = pchunk->dma_addr + off; 6362 np->acc_handle = pchunk->acc_handle; 6363 np->dma_handle = pchunk->dma_handle; 6364 if ((off + PMCS_SGL_CHUNKSZ) < lim) { 6365 np = np->nxt; 6366 } 6367 } 6368 np->nxt = pwp->dma_freelist; 6369 pwp->dma_freelist = dcp; 6370 pmcs_prt(pwp, PMCS_PRT_DEBUG2, NULL, NULL, 6371 "added %lu DMA chunks ", n); 6372 } 6373 6374 /* 6375 * Change the value of the interrupt coalescing timer. This is done currently 6376 * only for I/O completions. If we're using the "auto clear" feature, it can 6377 * be turned back on when interrupt coalescing is turned off and must be 6378 * turned off when the coalescing timer is on. 6379 * NOTE: PMCS_MSIX_GENERAL and PMCS_OQ_IODONE are the same value. As long 6380 * as that's true, we don't need to distinguish between them. 6381 */ 6382 6383 void 6384 pmcs_set_intr_coal_timer(pmcs_hw_t *pwp, pmcs_coal_timer_adj_t adj) 6385 { 6386 if (adj == DECREASE_TIMER) { 6387 /* If the timer is already off, nothing to do. */ 6388 if (pwp->io_intr_coal.timer_on == B_FALSE) { 6389 return; 6390 } 6391 6392 pwp->io_intr_coal.intr_coal_timer -= PMCS_COAL_TIMER_GRAN; 6393 6394 if (pwp->io_intr_coal.intr_coal_timer == 0) { 6395 /* Disable the timer */ 6396 pmcs_wr_topunit(pwp, PMCS_INT_COALESCING_CONTROL, 0); 6397 6398 if (pwp->odb_auto_clear & (1 << PMCS_MSIX_IODONE)) { 6399 pmcs_wr_topunit(pwp, PMCS_OBDB_AUTO_CLR, 6400 pwp->odb_auto_clear); 6401 } 6402 6403 pwp->io_intr_coal.timer_on = B_FALSE; 6404 pwp->io_intr_coal.max_io_completions = B_FALSE; 6405 pwp->io_intr_coal.num_intrs = 0; 6406 pwp->io_intr_coal.int_cleared = B_FALSE; 6407 pwp->io_intr_coal.num_io_completions = 0; 6408 6409 DTRACE_PROBE1(pmcs__intr__coalesce__timer__off, 6410 pmcs_io_intr_coal_t *, &pwp->io_intr_coal); 6411 } else { 6412 pmcs_wr_topunit(pwp, PMCS_INT_COALESCING_TIMER, 6413 pwp->io_intr_coal.intr_coal_timer); 6414 } 6415 } else { 6416 /* 6417 * If the timer isn't on yet, do the setup for it now. 6418 */ 6419 if (pwp->io_intr_coal.timer_on == B_FALSE) { 6420 /* If auto clear is being used, turn it off. */ 6421 if (pwp->odb_auto_clear & (1 << PMCS_MSIX_IODONE)) { 6422 pmcs_wr_topunit(pwp, PMCS_OBDB_AUTO_CLR, 6423 (pwp->odb_auto_clear & 6424 ~(1 << PMCS_MSIX_IODONE))); 6425 } 6426 6427 pmcs_wr_topunit(pwp, PMCS_INT_COALESCING_CONTROL, 6428 (1 << PMCS_MSIX_IODONE)); 6429 pwp->io_intr_coal.timer_on = B_TRUE; 6430 pwp->io_intr_coal.intr_coal_timer = 6431 PMCS_COAL_TIMER_GRAN; 6432 6433 DTRACE_PROBE1(pmcs__intr__coalesce__timer__on, 6434 pmcs_io_intr_coal_t *, &pwp->io_intr_coal); 6435 } else { 6436 pwp->io_intr_coal.intr_coal_timer += 6437 PMCS_COAL_TIMER_GRAN; 6438 } 6439 6440 if (pwp->io_intr_coal.intr_coal_timer > PMCS_MAX_COAL_TIMER) { 6441 pwp->io_intr_coal.intr_coal_timer = PMCS_MAX_COAL_TIMER; 6442 } 6443 6444 pmcs_wr_topunit(pwp, PMCS_INT_COALESCING_TIMER, 6445 pwp->io_intr_coal.intr_coal_timer); 6446 } 6447 6448 /* 6449 * Adjust the interrupt threshold based on the current timer value 6450 */ 6451 pwp->io_intr_coal.intr_threshold = 6452 PMCS_INTR_THRESHOLD(PMCS_QUANTUM_TIME_USECS * 1000 / 6453 (pwp->io_intr_coal.intr_latency + 6454 (pwp->io_intr_coal.intr_coal_timer * 1000))); 6455 } 6456 6457 /* 6458 * Register Access functions 6459 */ 6460 uint32_t 6461 pmcs_rd_iqci(pmcs_hw_t *pwp, uint32_t qnum) 6462 { 6463 uint32_t iqci; 6464 6465 if (ddi_dma_sync(pwp->cip_handles, 0, 0, DDI_DMA_SYNC_FORKERNEL) != 6466 DDI_SUCCESS) { 6467 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6468 "%s: ddi_dma_sync failed?", __func__); 6469 } 6470 6471 iqci = LE_32( 6472 ((uint32_t *)((void *)pwp->cip))[IQ_OFFSET(qnum) >> 2]); 6473 6474 return (iqci); 6475 } 6476 6477 uint32_t 6478 pmcs_rd_oqpi(pmcs_hw_t *pwp, uint32_t qnum) 6479 { 6480 uint32_t oqpi; 6481 6482 if (ddi_dma_sync(pwp->cip_handles, 0, 0, DDI_DMA_SYNC_FORKERNEL) != 6483 DDI_SUCCESS) { 6484 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6485 "%s: ddi_dma_sync failed?", __func__); 6486 } 6487 6488 oqpi = LE_32( 6489 ((uint32_t *)((void *)pwp->cip))[OQ_OFFSET(qnum) >> 2]); 6490 6491 return (oqpi); 6492 } 6493 6494 uint32_t 6495 pmcs_rd_gsm_reg(pmcs_hw_t *pwp, uint8_t hi, uint32_t off) 6496 { 6497 uint32_t rv, newaxil, oldaxil, oldaxih; 6498 6499 newaxil = off & ~GSM_BASE_MASK; 6500 off &= GSM_BASE_MASK; 6501 mutex_enter(&pwp->axil_lock); 6502 oldaxil = ddi_get32(pwp->top_acc_handle, 6503 &pwp->top_regs[PMCS_AXI_TRANS >> 2]); 6504 ddi_put32(pwp->top_acc_handle, 6505 &pwp->top_regs[PMCS_AXI_TRANS >> 2], newaxil); 6506 drv_usecwait(10); 6507 if (ddi_get32(pwp->top_acc_handle, 6508 &pwp->top_regs[PMCS_AXI_TRANS >> 2]) != newaxil) { 6509 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6510 "AXIL register update failed"); 6511 } 6512 if (hi) { 6513 oldaxih = ddi_get32(pwp->top_acc_handle, 6514 &pwp->top_regs[PMCS_AXI_TRANS_UPPER >> 2]); 6515 ddi_put32(pwp->top_acc_handle, 6516 &pwp->top_regs[PMCS_AXI_TRANS_UPPER >> 2], hi); 6517 drv_usecwait(10); 6518 if (ddi_get32(pwp->top_acc_handle, 6519 &pwp->top_regs[PMCS_AXI_TRANS_UPPER >> 2]) != hi) { 6520 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6521 "AXIH register update failed"); 6522 } 6523 } 6524 rv = ddi_get32(pwp->gsm_acc_handle, &pwp->gsm_regs[off >> 2]); 6525 if (hi) { 6526 ddi_put32(pwp->top_acc_handle, 6527 &pwp->top_regs[PMCS_AXI_TRANS_UPPER >> 2], oldaxih); 6528 drv_usecwait(10); 6529 if (ddi_get32(pwp->top_acc_handle, 6530 &pwp->top_regs[PMCS_AXI_TRANS_UPPER >> 2]) != oldaxih) { 6531 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6532 "AXIH register restore failed"); 6533 } 6534 } 6535 ddi_put32(pwp->top_acc_handle, 6536 &pwp->top_regs[PMCS_AXI_TRANS >> 2], oldaxil); 6537 drv_usecwait(10); 6538 if (ddi_get32(pwp->top_acc_handle, 6539 &pwp->top_regs[PMCS_AXI_TRANS >> 2]) != oldaxil) { 6540 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6541 "AXIL register restore failed"); 6542 } 6543 mutex_exit(&pwp->axil_lock); 6544 return (rv); 6545 } 6546 6547 void 6548 pmcs_wr_gsm_reg(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6549 { 6550 uint32_t newaxil, oldaxil; 6551 6552 newaxil = off & ~GSM_BASE_MASK; 6553 off &= GSM_BASE_MASK; 6554 mutex_enter(&pwp->axil_lock); 6555 oldaxil = ddi_get32(pwp->top_acc_handle, 6556 &pwp->top_regs[PMCS_AXI_TRANS >> 2]); 6557 ddi_put32(pwp->top_acc_handle, 6558 &pwp->top_regs[PMCS_AXI_TRANS >> 2], newaxil); 6559 drv_usecwait(10); 6560 if (ddi_get32(pwp->top_acc_handle, 6561 &pwp->top_regs[PMCS_AXI_TRANS >> 2]) != newaxil) { 6562 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6563 "AXIL register update failed"); 6564 } 6565 ddi_put32(pwp->gsm_acc_handle, &pwp->gsm_regs[off >> 2], val); 6566 ddi_put32(pwp->top_acc_handle, 6567 &pwp->top_regs[PMCS_AXI_TRANS >> 2], oldaxil); 6568 drv_usecwait(10); 6569 if (ddi_get32(pwp->top_acc_handle, 6570 &pwp->top_regs[PMCS_AXI_TRANS >> 2]) != oldaxil) { 6571 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6572 "AXIL register restore failed"); 6573 } 6574 mutex_exit(&pwp->axil_lock); 6575 } 6576 6577 uint32_t 6578 pmcs_rd_topunit(pmcs_hw_t *pwp, uint32_t off) 6579 { 6580 switch (off) { 6581 case PMCS_SPC_RESET: 6582 case PMCS_SPC_BOOT_STRAP: 6583 case PMCS_SPC_DEVICE_ID: 6584 case PMCS_DEVICE_REVISION: 6585 off = pmcs_rd_gsm_reg(pwp, 0, off); 6586 break; 6587 default: 6588 off = ddi_get32(pwp->top_acc_handle, 6589 &pwp->top_regs[off >> 2]); 6590 break; 6591 } 6592 return (off); 6593 } 6594 6595 void 6596 pmcs_wr_topunit(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6597 { 6598 switch (off) { 6599 case PMCS_SPC_RESET: 6600 case PMCS_DEVICE_REVISION: 6601 pmcs_wr_gsm_reg(pwp, off, val); 6602 break; 6603 default: 6604 ddi_put32(pwp->top_acc_handle, &pwp->top_regs[off >> 2], val); 6605 break; 6606 } 6607 } 6608 6609 uint32_t 6610 pmcs_rd_msgunit(pmcs_hw_t *pwp, uint32_t off) 6611 { 6612 return (ddi_get32(pwp->msg_acc_handle, &pwp->msg_regs[off >> 2])); 6613 } 6614 6615 uint32_t 6616 pmcs_rd_mpi_tbl(pmcs_hw_t *pwp, uint32_t off) 6617 { 6618 return (ddi_get32(pwp->mpi_acc_handle, 6619 &pwp->mpi_regs[(pwp->mpi_offset + off) >> 2])); 6620 } 6621 6622 uint32_t 6623 pmcs_rd_gst_tbl(pmcs_hw_t *pwp, uint32_t off) 6624 { 6625 return (ddi_get32(pwp->mpi_acc_handle, 6626 &pwp->mpi_regs[(pwp->mpi_gst_offset + off) >> 2])); 6627 } 6628 6629 uint32_t 6630 pmcs_rd_iqc_tbl(pmcs_hw_t *pwp, uint32_t off) 6631 { 6632 return (ddi_get32(pwp->mpi_acc_handle, 6633 &pwp->mpi_regs[(pwp->mpi_iqc_offset + off) >> 2])); 6634 } 6635 6636 uint32_t 6637 pmcs_rd_oqc_tbl(pmcs_hw_t *pwp, uint32_t off) 6638 { 6639 return (ddi_get32(pwp->mpi_acc_handle, 6640 &pwp->mpi_regs[(pwp->mpi_oqc_offset + off) >> 2])); 6641 } 6642 6643 uint32_t 6644 pmcs_rd_iqpi(pmcs_hw_t *pwp, uint32_t qnum) 6645 { 6646 return (ddi_get32(pwp->mpi_acc_handle, 6647 &pwp->mpi_regs[pwp->iqpi_offset[qnum] >> 2])); 6648 } 6649 6650 uint32_t 6651 pmcs_rd_oqci(pmcs_hw_t *pwp, uint32_t qnum) 6652 { 6653 return (ddi_get32(pwp->mpi_acc_handle, 6654 &pwp->mpi_regs[pwp->oqci_offset[qnum] >> 2])); 6655 } 6656 6657 void 6658 pmcs_wr_msgunit(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6659 { 6660 ddi_put32(pwp->msg_acc_handle, &pwp->msg_regs[off >> 2], val); 6661 } 6662 6663 void 6664 pmcs_wr_mpi_tbl(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6665 { 6666 ddi_put32(pwp->mpi_acc_handle, 6667 &pwp->mpi_regs[(pwp->mpi_offset + off) >> 2], (val)); 6668 } 6669 6670 void 6671 pmcs_wr_gst_tbl(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6672 { 6673 ddi_put32(pwp->mpi_acc_handle, 6674 &pwp->mpi_regs[(pwp->mpi_gst_offset + off) >> 2], val); 6675 } 6676 6677 void 6678 pmcs_wr_iqc_tbl(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6679 { 6680 ddi_put32(pwp->mpi_acc_handle, 6681 &pwp->mpi_regs[(pwp->mpi_iqc_offset + off) >> 2], val); 6682 } 6683 6684 void 6685 pmcs_wr_oqc_tbl(pmcs_hw_t *pwp, uint32_t off, uint32_t val) 6686 { 6687 ddi_put32(pwp->mpi_acc_handle, 6688 &pwp->mpi_regs[(pwp->mpi_oqc_offset + off) >> 2], val); 6689 } 6690 6691 void 6692 pmcs_wr_iqci(pmcs_hw_t *pwp, uint32_t qnum, uint32_t val) 6693 { 6694 ((uint32_t *)((void *)pwp->cip))[IQ_OFFSET(qnum) >> 2] = val; 6695 if (ddi_dma_sync(pwp->cip_handles, 0, 0, DDI_DMA_SYNC_FORDEV) != 6696 DDI_SUCCESS) { 6697 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6698 "%s: ddi_dma_sync failed?", __func__); 6699 } 6700 } 6701 6702 void 6703 pmcs_wr_iqpi(pmcs_hw_t *pwp, uint32_t qnum, uint32_t val) 6704 { 6705 ddi_put32(pwp->mpi_acc_handle, 6706 &pwp->mpi_regs[pwp->iqpi_offset[qnum] >> 2], val); 6707 } 6708 6709 void 6710 pmcs_wr_oqci(pmcs_hw_t *pwp, uint32_t qnum, uint32_t val) 6711 { 6712 ddi_put32(pwp->mpi_acc_handle, 6713 &pwp->mpi_regs[pwp->oqci_offset[qnum] >> 2], val); 6714 } 6715 6716 void 6717 pmcs_wr_oqpi(pmcs_hw_t *pwp, uint32_t qnum, uint32_t val) 6718 { 6719 ((uint32_t *)((void *)pwp->cip))[OQ_OFFSET(qnum) >> 2] = val; 6720 if (ddi_dma_sync(pwp->cip_handles, 0, 0, DDI_DMA_SYNC_FORDEV) != 6721 DDI_SUCCESS) { 6722 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6723 "%s: ddi_dma_sync failed?", __func__); 6724 } 6725 } 6726 6727 /* 6728 * Check the status value of an outbound IOMB and report anything bad 6729 */ 6730 6731 void 6732 pmcs_check_iomb_status(pmcs_hw_t *pwp, uint32_t *iomb) 6733 { 6734 uint16_t opcode; 6735 int offset; 6736 6737 if (iomb == NULL) { 6738 return; 6739 } 6740 6741 opcode = LE_32(iomb[0]) & 0xfff; 6742 6743 switch (opcode) { 6744 /* 6745 * The following have no status field, so ignore them 6746 */ 6747 case PMCOUT_ECHO: 6748 case PMCOUT_SAS_HW_EVENT: 6749 case PMCOUT_GET_DEVICE_HANDLE: 6750 case PMCOUT_SATA_EVENT: 6751 case PMCOUT_SSP_EVENT: 6752 case PMCOUT_DEVICE_HANDLE_ARRIVED: 6753 case PMCOUT_GPIO: 6754 case PMCOUT_GPIO_EVENT: 6755 case PMCOUT_GET_TIME_STAMP: 6756 case PMCOUT_SKIP_ENTRIES: 6757 case PMCOUT_GET_NVMD_DATA: /* Actually lower 16 bits of word 3 */ 6758 case PMCOUT_SET_NVMD_DATA: /* but ignore - we don't use these */ 6759 case PMCOUT_DEVICE_HANDLE_REMOVED: 6760 case PMCOUT_SSP_REQUEST_RECEIVED: 6761 return; 6762 6763 case PMCOUT_GENERAL_EVENT: 6764 offset = 1; 6765 break; 6766 6767 case PMCOUT_SSP_COMPLETION: 6768 case PMCOUT_SMP_COMPLETION: 6769 case PMCOUT_DEVICE_REGISTRATION: 6770 case PMCOUT_DEREGISTER_DEVICE_HANDLE: 6771 case PMCOUT_SATA_COMPLETION: 6772 case PMCOUT_DEVICE_INFO: 6773 case PMCOUT_FW_FLASH_UPDATE: 6774 case PMCOUT_SSP_ABORT: 6775 case PMCOUT_SATA_ABORT: 6776 case PMCOUT_SAS_DIAG_MODE_START_END: 6777 case PMCOUT_SAS_HW_EVENT_ACK_ACK: 6778 case PMCOUT_SMP_ABORT: 6779 case PMCOUT_SET_DEVICE_STATE: 6780 case PMCOUT_GET_DEVICE_STATE: 6781 case PMCOUT_SET_DEVICE_INFO: 6782 offset = 2; 6783 break; 6784 6785 case PMCOUT_LOCAL_PHY_CONTROL: 6786 case PMCOUT_SAS_DIAG_EXECUTE: 6787 case PMCOUT_PORT_CONTROL: 6788 offset = 3; 6789 break; 6790 6791 case PMCOUT_GET_INFO: 6792 case PMCOUT_GET_VPD: 6793 case PMCOUT_SAS_ASSISTED_DISCOVERY_EVENT: 6794 case PMCOUT_SATA_ASSISTED_DISCOVERY_EVENT: 6795 case PMCOUT_SET_VPD: 6796 case PMCOUT_TWI: 6797 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, 6798 "Got response for deprecated opcode", iomb); 6799 return; 6800 6801 default: 6802 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, 6803 "Got response for unknown opcode", iomb); 6804 return; 6805 } 6806 6807 if (LE_32(iomb[offset]) != PMCOUT_STATUS_OK) { 6808 pmcs_print_entry(pwp, PMCS_PRT_DEBUG, 6809 "bad status on TAG_TYPE_NONE command", iomb); 6810 } 6811 } 6812 6813 /* 6814 * Called with statlock held 6815 */ 6816 void 6817 pmcs_clear_xp(pmcs_hw_t *pwp, pmcs_xscsi_t *xp) 6818 { 6819 _NOTE(ARGUNUSED(pwp)); 6820 6821 ASSERT(mutex_owned(&xp->statlock)); 6822 6823 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, xp, "%s: Device 0x%p is gone.", 6824 __func__, (void *)xp); 6825 6826 xp->special_running = 0; 6827 xp->recovering = 0; 6828 xp->recover_wait = 0; 6829 xp->draining = 0; 6830 xp->new = 0; 6831 xp->assigned = 0; 6832 xp->dev_state = 0; 6833 xp->tagmap = 0; 6834 xp->dev_gone = 1; 6835 xp->event_recovery = 0; 6836 xp->dtype = NOTHING; 6837 xp->wq_recovery_tail = NULL; 6838 /* Don't clear xp->phy */ 6839 /* Don't clear xp->actv_cnt */ 6840 /* Don't clear xp->actv_pkts */ 6841 6842 /* 6843 * Flush all target queues 6844 */ 6845 pmcs_flush_target_queues(pwp, xp, PMCS_TGT_ALL_QUEUES); 6846 } 6847 6848 static int 6849 pmcs_smp_function_result(pmcs_hw_t *pwp, smp_response_frame_t *srf) 6850 { 6851 int result = srf->srf_result; 6852 6853 switch (result) { 6854 case SMP_RES_UNKNOWN_FUNCTION: 6855 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6856 "%s: SMP DISCOVER Response " 6857 "Function Result: Unknown SMP Function(0x%x)", 6858 __func__, result); 6859 break; 6860 case SMP_RES_FUNCTION_FAILED: 6861 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6862 "%s: SMP DISCOVER Response " 6863 "Function Result: SMP Function Failed(0x%x)", 6864 __func__, result); 6865 break; 6866 case SMP_RES_INVALID_REQUEST_FRAME_LENGTH: 6867 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6868 "%s: SMP DISCOVER Response " 6869 "Function Result: Invalid Request Frame Length(0x%x)", 6870 __func__, result); 6871 break; 6872 case SMP_RES_INCOMPLETE_DESCRIPTOR_LIST: 6873 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6874 "%s: SMP DISCOVER Response " 6875 "Function Result: Incomplete Descriptor List(0x%x)", 6876 __func__, result); 6877 break; 6878 case SMP_RES_PHY_DOES_NOT_EXIST: 6879 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6880 "%s: SMP DISCOVER Response " 6881 "Function Result: PHY does not exist(0x%x)", 6882 __func__, result); 6883 break; 6884 case SMP_RES_PHY_VACANT: 6885 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6886 "%s: SMP DISCOVER Response " 6887 "Function Result: PHY Vacant(0x%x)", 6888 __func__, result); 6889 break; 6890 default: 6891 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6892 "%s: SMP DISCOVER Response " 6893 "Function Result: (0x%x)", 6894 __func__, result); 6895 break; 6896 } 6897 6898 return (result); 6899 } 6900 6901 /* 6902 * Do all the repetitive stuff necessary to setup for DMA 6903 * 6904 * pwp: Used for dip 6905 * dma_attr: ddi_dma_attr_t to use for the mapping 6906 * acch: ddi_acc_handle_t to use for the mapping 6907 * dmah: ddi_dma_handle_t to use 6908 * length: Amount of memory for mapping 6909 * kvap: Pointer filled in with kernel virtual address on successful return 6910 * dma_addr: Pointer filled in with DMA address on successful return 6911 */ 6912 boolean_t 6913 pmcs_dma_setup(pmcs_hw_t *pwp, ddi_dma_attr_t *dma_attr, ddi_acc_handle_t *acch, 6914 ddi_dma_handle_t *dmah, size_t length, caddr_t *kvap, uint64_t *dma_addr) 6915 { 6916 dev_info_t *dip = pwp->dip; 6917 ddi_dma_cookie_t cookie; 6918 size_t real_length; 6919 uint_t ddma_flag = DDI_DMA_CONSISTENT; 6920 uint_t ddabh_flag = DDI_DMA_CONSISTENT | DDI_DMA_RDWR; 6921 uint_t cookie_cnt; 6922 ddi_device_acc_attr_t mattr = { 6923 DDI_DEVICE_ATTR_V0, 6924 DDI_NEVERSWAP_ACC, 6925 DDI_STRICTORDER_ACC, 6926 DDI_DEFAULT_ACC 6927 }; 6928 6929 *acch = NULL; 6930 *dmah = NULL; 6931 6932 if (ddi_dma_alloc_handle(dip, dma_attr, DDI_DMA_SLEEP, NULL, dmah) != 6933 DDI_SUCCESS) { 6934 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6935 "Failed to allocate DMA handle"); 6936 return (B_FALSE); 6937 } 6938 6939 if (ddi_dma_mem_alloc(*dmah, length, &mattr, ddma_flag, DDI_DMA_SLEEP, 6940 NULL, kvap, &real_length, acch) != DDI_SUCCESS) { 6941 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 6942 "Failed to allocate DMA mem"); 6943 ddi_dma_free_handle(dmah); 6944 *dmah = NULL; 6945 return (B_FALSE); 6946 } 6947 6948 if (ddi_dma_addr_bind_handle(*dmah, NULL, *kvap, real_length, 6949 ddabh_flag, DDI_DMA_SLEEP, NULL, &cookie, &cookie_cnt) 6950 != DDI_DMA_MAPPED) { 6951 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "Failed to bind DMA"); 6952 ddi_dma_free_handle(dmah); 6953 ddi_dma_mem_free(acch); 6954 *dmah = NULL; 6955 *acch = NULL; 6956 return (B_FALSE); 6957 } 6958 6959 if (cookie_cnt != 1) { 6960 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "Multiple cookies"); 6961 if (ddi_dma_unbind_handle(*dmah) != DDI_SUCCESS) { 6962 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, "Condition " 6963 "failed at %s():%d", __func__, __LINE__); 6964 } 6965 ddi_dma_free_handle(dmah); 6966 ddi_dma_mem_free(acch); 6967 *dmah = NULL; 6968 *acch = NULL; 6969 return (B_FALSE); 6970 } 6971 6972 *dma_addr = cookie.dmac_laddress; 6973 6974 return (B_TRUE); 6975 } 6976 6977 /* 6978 * Flush requested queues for a particular target. Called with statlock held 6979 */ 6980 void 6981 pmcs_flush_target_queues(pmcs_hw_t *pwp, pmcs_xscsi_t *tgt, uint8_t queues) 6982 { 6983 pmcs_cmd_t *sp, *sp_next; 6984 pmcwork_t *pwrk; 6985 6986 ASSERT(pwp != NULL); 6987 ASSERT(tgt != NULL); 6988 6989 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, tgt, 6990 "%s: Flushing queues (%d) for target 0x%p", __func__, 6991 queues, (void *)tgt); 6992 6993 /* 6994 * Commands on the wait queue (or the special queue below) don't have 6995 * work structures associated with them. 6996 */ 6997 if (queues & PMCS_TGT_WAIT_QUEUE) { 6998 mutex_enter(&tgt->wqlock); 6999 while ((sp = STAILQ_FIRST(&tgt->wq)) != NULL) { 7000 STAILQ_REMOVE(&tgt->wq, sp, pmcs_cmd, cmd_next); 7001 pmcs_prt(pwp, PMCS_PRT_DEBUG1, NULL, tgt, 7002 "%s: Removing cmd 0x%p from wq for target 0x%p", 7003 __func__, (void *)sp, (void *)tgt); 7004 CMD2PKT(sp)->pkt_reason = CMD_DEV_GONE; 7005 CMD2PKT(sp)->pkt_state = STATE_GOT_BUS; 7006 mutex_exit(&tgt->wqlock); 7007 pmcs_dma_unload(pwp, sp); 7008 mutex_enter(&pwp->cq_lock); 7009 STAILQ_INSERT_TAIL(&pwp->cq, sp, cmd_next); 7010 PMCS_CQ_RUN_LOCKED(pwp); 7011 mutex_exit(&pwp->cq_lock); 7012 mutex_enter(&tgt->wqlock); 7013 } 7014 mutex_exit(&tgt->wqlock); 7015 } 7016 7017 /* 7018 * Commands on the active queue will have work structures associated 7019 * with them. 7020 */ 7021 if (queues & PMCS_TGT_ACTIVE_QUEUE) { 7022 mutex_exit(&tgt->statlock); 7023 mutex_enter(&tgt->aqlock); 7024 sp = STAILQ_FIRST(&tgt->aq); 7025 while (sp) { 7026 sp_next = STAILQ_NEXT(sp, cmd_next); 7027 pwrk = pmcs_tag2wp(pwp, sp->cmd_tag, B_FALSE); 7028 7029 /* 7030 * If we don't find a work structure, it's because 7031 * the command is already complete. If so, move on 7032 * to the next one. 7033 */ 7034 if (pwrk == NULL) { 7035 pmcs_prt(pwp, PMCS_PRT_DEBUG1, tgt->phy, tgt, 7036 "%s: Not removing cmd 0x%p (htag 0x%x) " 7037 "from aq", __func__, (void *)sp, 7038 sp->cmd_tag); 7039 sp = sp_next; 7040 continue; 7041 } 7042 7043 STAILQ_REMOVE(&tgt->aq, sp, pmcs_cmd, cmd_next); 7044 pmcs_prt(pwp, PMCS_PRT_DEBUG1, tgt->phy, tgt, 7045 "%s: Removing cmd 0x%p (htag 0x%x) from aq for " 7046 "target 0x%p", __func__, (void *)sp, sp->cmd_tag, 7047 (void *)tgt); 7048 mutex_exit(&tgt->aqlock); 7049 7050 /* 7051 * Mark the work structure as dead and complete it 7052 */ 7053 pwrk->dead = 1; 7054 CMD2PKT(sp)->pkt_reason = CMD_DEV_GONE; 7055 CMD2PKT(sp)->pkt_state = STATE_GOT_BUS; 7056 pmcs_complete_work_impl(pwp, pwrk, NULL, 0); 7057 pmcs_dma_unload(pwp, sp); 7058 mutex_enter(&pwp->cq_lock); 7059 STAILQ_INSERT_TAIL(&pwp->cq, sp, cmd_next); 7060 mutex_exit(&pwp->cq_lock); 7061 mutex_enter(&tgt->aqlock); 7062 sp = sp_next; 7063 } 7064 mutex_exit(&tgt->aqlock); 7065 mutex_enter(&tgt->statlock); 7066 } 7067 7068 if (queues & PMCS_TGT_SPECIAL_QUEUE) { 7069 while ((sp = STAILQ_FIRST(&tgt->sq)) != NULL) { 7070 STAILQ_REMOVE(&tgt->sq, sp, pmcs_cmd, cmd_next); 7071 pmcs_prt(pwp, PMCS_PRT_DEBUG1, tgt->phy, tgt, 7072 "%s: Removing cmd 0x%p from sq for target 0x%p", 7073 __func__, (void *)sp, (void *)tgt); 7074 CMD2PKT(sp)->pkt_reason = CMD_DEV_GONE; 7075 CMD2PKT(sp)->pkt_state = STATE_GOT_BUS; 7076 pmcs_dma_unload(pwp, sp); 7077 mutex_enter(&pwp->cq_lock); 7078 STAILQ_INSERT_TAIL(&pwp->cq, sp, cmd_next); 7079 mutex_exit(&pwp->cq_lock); 7080 } 7081 } 7082 7083 if (queues == PMCS_TGT_ALL_QUEUES) { 7084 mutex_exit(&tgt->statlock); 7085 pmcs_flush_nonio_cmds(pwp, tgt); 7086 mutex_enter(&tgt->statlock); 7087 } 7088 } 7089 7090 /* 7091 * Flush non-IO commands for this target. This cleans up the off-queue 7092 * work with no pmcs_cmd_t associated. 7093 */ 7094 static void 7095 pmcs_flush_nonio_cmds(pmcs_hw_t *pwp, pmcs_xscsi_t *tgt) 7096 { 7097 int i; 7098 pmcwork_t *p; 7099 7100 for (i = 0; i < pwp->max_cmd; i++) { 7101 p = &pwp->work[i]; 7102 mutex_enter(&p->lock); 7103 if (p->xp != tgt) { 7104 mutex_exit(&p->lock); 7105 continue; 7106 } 7107 if (p->htag & PMCS_TAG_NONIO_CMD) { 7108 if (!PMCS_COMMAND_ACTIVE(p) || PMCS_COMMAND_DONE(p)) { 7109 mutex_exit(&p->lock); 7110 continue; 7111 } 7112 pmcs_prt(pwp, PMCS_PRT_DEBUG, p->phy, p->xp, 7113 "%s: Completing non-io cmd with HTAG 0x%x", 7114 __func__, p->htag); 7115 pmcs_complete_work_impl(pwp, p, NULL, 0); 7116 } else { 7117 mutex_exit(&p->lock); 7118 } 7119 } 7120 } 7121 7122 void 7123 pmcs_complete_work_impl(pmcs_hw_t *pwp, pmcwork_t *pwrk, uint32_t *iomb, 7124 size_t amt) 7125 { 7126 pmcs_phy_t *pptr = NULL; 7127 7128 switch (PMCS_TAG_TYPE(pwrk->htag)) { 7129 case PMCS_TAG_TYPE_CBACK: 7130 { 7131 pmcs_cb_t callback = (pmcs_cb_t)pwrk->ptr; 7132 (*callback)(pwp, pwrk, iomb); 7133 break; 7134 } 7135 case PMCS_TAG_TYPE_WAIT: 7136 if (pwrk->arg && iomb && amt) { 7137 (void) memcpy(pwrk->arg, iomb, amt); 7138 } 7139 cv_signal(&pwrk->sleep_cv); 7140 mutex_exit(&pwrk->lock); 7141 break; 7142 case PMCS_TAG_TYPE_NONE: 7143 #ifdef DEBUG 7144 pmcs_check_iomb_status(pwp, iomb); 7145 #endif 7146 pptr = pwrk->phy; 7147 pmcs_pwork(pwp, pwrk); 7148 7149 /* If this was an abort all, clean up if needed */ 7150 if ((pwrk->abt_htag == PMCS_ABT_HTAG_ALL) && (pptr != NULL)) { 7151 mutex_enter(&pptr->phy_lock); 7152 if (pptr->abort_all_start) { 7153 pptr->abort_all_start = 0; 7154 cv_signal(&pptr->abort_all_cv); 7155 } 7156 mutex_exit(&pptr->phy_lock); 7157 } 7158 break; 7159 default: 7160 /* 7161 * We will leak a structure here if we don't know 7162 * what happened 7163 */ 7164 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 7165 "%s: Unknown PMCS_TAG_TYPE (%x)", 7166 __func__, PMCS_TAG_TYPE(pwrk->htag)); 7167 break; 7168 } 7169 } 7170 7171 /* 7172 * Determine if iport still has targets. During detach(9E), if SCSA is 7173 * successfull in its guarantee of tran_tgt_free(9E) before detach(9E), 7174 * this should always return B_FALSE. 7175 */ 7176 boolean_t 7177 pmcs_iport_has_targets(pmcs_hw_t *pwp, pmcs_iport_t *iport) 7178 { 7179 pmcs_xscsi_t *xp; 7180 int i; 7181 7182 mutex_enter(&pwp->lock); 7183 7184 if (!pwp->targets || !pwp->max_dev) { 7185 mutex_exit(&pwp->lock); 7186 return (B_FALSE); 7187 } 7188 7189 for (i = 0; i < pwp->max_dev; i++) { 7190 xp = pwp->targets[i]; 7191 if ((xp == NULL) || (xp->phy == NULL) || 7192 (xp->phy->iport != iport)) { 7193 continue; 7194 } 7195 7196 mutex_exit(&pwp->lock); 7197 return (B_TRUE); 7198 } 7199 7200 mutex_exit(&pwp->lock); 7201 return (B_FALSE); 7202 } 7203 7204 /* 7205 * Called with softstate lock held 7206 */ 7207 void 7208 pmcs_destroy_target(pmcs_xscsi_t *target) 7209 { 7210 pmcs_hw_t *pwp = target->pwp; 7211 pmcs_iport_t *iport; 7212 7213 ASSERT(pwp); 7214 ASSERT(mutex_owned(&pwp->lock)); 7215 7216 if (!target->ua) { 7217 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, target, 7218 "%s: target %p iport address is null", 7219 __func__, (void *)target); 7220 } 7221 7222 iport = pmcs_get_iport_by_ua(pwp, target->ua); 7223 if (iport == NULL) { 7224 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, target, 7225 "%s: no iport associated with tgt(0x%p)", 7226 __func__, (void *)target); 7227 return; 7228 } 7229 7230 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, NULL, target, 7231 "%s: free target %p", __func__, (void *)target); 7232 if (target->ua) { 7233 strfree(target->ua); 7234 } 7235 7236 mutex_destroy(&target->wqlock); 7237 mutex_destroy(&target->aqlock); 7238 mutex_destroy(&target->statlock); 7239 cv_destroy(&target->reset_cv); 7240 cv_destroy(&target->abort_cv); 7241 ddi_soft_state_bystr_fini(&target->lun_sstate); 7242 ddi_soft_state_bystr_free(iport->tgt_sstate, target->unit_address); 7243 pmcs_rele_iport(iport); 7244 } 7245 7246 /* 7247 * pmcs_lock_phy_impl 7248 * 7249 * This function is what does the actual work for pmcs_lock_phy. It will 7250 * lock all PHYs from phyp down in a top-down fashion. 7251 * 7252 * Locking notes: 7253 * 1. level starts from 0 for the PHY ("parent") that's passed in. It is 7254 * not a reflection of the actual level of the PHY in the SAS topology. 7255 * 2. If parent is an expander, then parent is locked along with all its 7256 * descendents. 7257 * 3. Expander subsidiary PHYs at level 0 are not locked. It is the 7258 * responsibility of the caller to individually lock expander subsidiary PHYs 7259 * at level 0 if necessary. 7260 * 4. Siblings at level 0 are not traversed due to the possibility that we're 7261 * locking a PHY on the dead list. The siblings could be pointing to invalid 7262 * PHYs. We don't lock siblings at level 0 anyway. 7263 */ 7264 static void 7265 pmcs_lock_phy_impl(pmcs_phy_t *phyp, int level) 7266 { 7267 pmcs_phy_t *tphyp; 7268 7269 ASSERT((phyp->dtype == SAS) || (phyp->dtype == SATA) || 7270 (phyp->dtype == EXPANDER) || (phyp->dtype == NOTHING)); 7271 7272 /* 7273 * Start walking the PHYs. 7274 */ 7275 tphyp = phyp; 7276 while (tphyp) { 7277 /* 7278 * If we're at the top level, only lock ourselves. For anything 7279 * at level > 0, traverse children while locking everything. 7280 */ 7281 if ((level > 0) || (tphyp == phyp)) { 7282 pmcs_prt(tphyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, tphyp, 7283 NULL, "%s: PHY 0x%p parent 0x%p path %s lvl %d", 7284 __func__, (void *)tphyp, (void *)tphyp->parent, 7285 tphyp->path, level); 7286 mutex_enter(&tphyp->phy_lock); 7287 7288 if (tphyp->children) { 7289 pmcs_lock_phy_impl(tphyp->children, level + 1); 7290 } 7291 } 7292 7293 if (level == 0) { 7294 return; 7295 } 7296 7297 tphyp = tphyp->sibling; 7298 } 7299 } 7300 7301 /* 7302 * pmcs_lock_phy 7303 * 7304 * This function is responsible for locking a PHY and all its descendents 7305 */ 7306 void 7307 pmcs_lock_phy(pmcs_phy_t *phyp) 7308 { 7309 #ifdef DEBUG 7310 char *callername = NULL; 7311 ulong_t off; 7312 7313 ASSERT(phyp != NULL); 7314 7315 callername = modgetsymname((uintptr_t)caller(), &off); 7316 7317 if (callername == NULL) { 7318 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7319 "%s: PHY 0x%p path %s caller: unknown", __func__, 7320 (void *)phyp, phyp->path); 7321 } else { 7322 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7323 "%s: PHY 0x%p path %s caller: %s+%lx", __func__, 7324 (void *)phyp, phyp->path, callername, off); 7325 } 7326 #else 7327 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7328 "%s: PHY 0x%p path %s", __func__, (void *)phyp, phyp->path); 7329 #endif 7330 pmcs_lock_phy_impl(phyp, 0); 7331 } 7332 7333 /* 7334 * pmcs_unlock_phy_impl 7335 * 7336 * Unlock all PHYs from phyp down in a bottom-up fashion. 7337 */ 7338 static void 7339 pmcs_unlock_phy_impl(pmcs_phy_t *phyp, int level) 7340 { 7341 pmcs_phy_t *phy_next; 7342 7343 ASSERT((phyp->dtype == SAS) || (phyp->dtype == SATA) || 7344 (phyp->dtype == EXPANDER) || (phyp->dtype == NOTHING)); 7345 7346 /* 7347 * Recurse down to the bottom PHYs 7348 */ 7349 if (level == 0) { 7350 if (phyp->children) { 7351 pmcs_unlock_phy_impl(phyp->children, level + 1); 7352 } 7353 } else { 7354 phy_next = phyp; 7355 while (phy_next) { 7356 if (phy_next->children) { 7357 pmcs_unlock_phy_impl(phy_next->children, 7358 level + 1); 7359 } 7360 phy_next = phy_next->sibling; 7361 } 7362 } 7363 7364 /* 7365 * Iterate through PHYs unlocking all at level > 0 as well the top PHY 7366 */ 7367 phy_next = phyp; 7368 while (phy_next) { 7369 if ((level > 0) || (phy_next == phyp)) { 7370 pmcs_prt(phy_next->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, 7371 phy_next, NULL, 7372 "%s: PHY 0x%p parent 0x%p path %s lvl %d", 7373 __func__, (void *)phy_next, 7374 (void *)phy_next->parent, phy_next->path, level); 7375 mutex_exit(&phy_next->phy_lock); 7376 } 7377 7378 if (level == 0) { 7379 return; 7380 } 7381 7382 phy_next = phy_next->sibling; 7383 } 7384 } 7385 7386 /* 7387 * pmcs_unlock_phy 7388 * 7389 * Unlock a PHY and all its descendents 7390 */ 7391 void 7392 pmcs_unlock_phy(pmcs_phy_t *phyp) 7393 { 7394 #ifdef DEBUG 7395 char *callername = NULL; 7396 ulong_t off; 7397 7398 ASSERT(phyp != NULL); 7399 7400 callername = modgetsymname((uintptr_t)caller(), &off); 7401 7402 if (callername == NULL) { 7403 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7404 "%s: PHY 0x%p path %s caller: unknown", __func__, 7405 (void *)phyp, phyp->path); 7406 } else { 7407 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7408 "%s: PHY 0x%p path %s caller: %s+%lx", __func__, 7409 (void *)phyp, phyp->path, callername, off); 7410 } 7411 #else 7412 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG_PHY_LOCKING, phyp, NULL, 7413 "%s: PHY 0x%p path %s", __func__, (void *)phyp, phyp->path); 7414 #endif 7415 pmcs_unlock_phy_impl(phyp, 0); 7416 } 7417 7418 /* 7419 * pmcs_get_root_phy 7420 * 7421 * For a given phy pointer return its root phy. 7422 * This function must only be called during discovery in order to ensure that 7423 * the chain of PHYs from phyp up to the root PHY doesn't change. 7424 */ 7425 pmcs_phy_t * 7426 pmcs_get_root_phy(pmcs_phy_t *phyp) 7427 { 7428 ASSERT(phyp); 7429 7430 while (phyp) { 7431 if (IS_ROOT_PHY(phyp)) { 7432 break; 7433 } 7434 phyp = phyp->parent; 7435 } 7436 7437 return (phyp); 7438 } 7439 7440 /* 7441 * pmcs_free_dma_chunklist 7442 * 7443 * Free DMA S/G chunk list 7444 */ 7445 void 7446 pmcs_free_dma_chunklist(pmcs_hw_t *pwp) 7447 { 7448 pmcs_chunk_t *pchunk; 7449 7450 while (pwp->dma_chunklist) { 7451 pchunk = pwp->dma_chunklist; 7452 pwp->dma_chunklist = pwp->dma_chunklist->next; 7453 if (pchunk->dma_handle) { 7454 if (ddi_dma_unbind_handle(pchunk->dma_handle) != 7455 DDI_SUCCESS) { 7456 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 7457 "Condition failed at %s():%d", 7458 __func__, __LINE__); 7459 } 7460 ddi_dma_free_handle(&pchunk->dma_handle); 7461 ddi_dma_mem_free(&pchunk->acc_handle); 7462 } 7463 kmem_free(pchunk, sizeof (pmcs_chunk_t)); 7464 } 7465 } 7466 7467 /*ARGSUSED2*/ 7468 int 7469 pmcs_phy_constructor(void *buf, void *arg, int kmflags) 7470 { 7471 pmcs_hw_t *pwp = (pmcs_hw_t *)arg; 7472 pmcs_phy_t *phyp = (pmcs_phy_t *)buf; 7473 7474 mutex_init(&phyp->phy_lock, NULL, MUTEX_DRIVER, 7475 DDI_INTR_PRI(pwp->intr_pri)); 7476 cv_init(&phyp->abort_all_cv, NULL, CV_DRIVER, NULL); 7477 return (0); 7478 } 7479 7480 /*ARGSUSED1*/ 7481 void 7482 pmcs_phy_destructor(void *buf, void *arg) 7483 { 7484 pmcs_phy_t *phyp = (pmcs_phy_t *)buf; 7485 7486 cv_destroy(&phyp->abort_all_cv); 7487 mutex_destroy(&phyp->phy_lock); 7488 } 7489 7490 /* 7491 * Free all PHYs from the kmem_cache starting at phyp as well as everything 7492 * on the dead_phys list. 7493 * 7494 * NOTE: This function does not free root PHYs as they are not allocated 7495 * from the kmem_cache. 7496 * 7497 * No PHY locks are acquired as this should only be called during DDI_DETACH 7498 * or soft reset (while pmcs interrupts are disabled). 7499 */ 7500 void 7501 pmcs_free_all_phys(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 7502 { 7503 pmcs_phy_t *tphyp, *nphyp, *cphyp; 7504 7505 if (phyp == NULL) { 7506 return; 7507 } 7508 7509 for (tphyp = phyp; tphyp; tphyp = nphyp) { 7510 nphyp = tphyp->sibling; 7511 cphyp = tphyp->children; 7512 7513 if (cphyp) { 7514 tphyp->children = NULL; 7515 pmcs_free_all_phys(pwp, cphyp); 7516 } 7517 7518 if (!IS_ROOT_PHY(tphyp)) { 7519 tphyp->target_addr = NULL; 7520 kmem_cache_free(pwp->phy_cache, tphyp); 7521 } 7522 } 7523 7524 mutex_enter(&pwp->dead_phylist_lock); 7525 for (tphyp = pwp->dead_phys; tphyp; tphyp = nphyp) { 7526 nphyp = tphyp->dead_next; 7527 tphyp->target_addr = NULL; 7528 kmem_cache_free(pwp->phy_cache, tphyp); 7529 } 7530 pwp->dead_phys = NULL; 7531 mutex_exit(&pwp->dead_phylist_lock); 7532 } 7533 7534 /* 7535 * Free a list of PHYs linked together by the sibling pointer back to the 7536 * kmem cache from whence they came. This function does not recurse, so the 7537 * caller must ensure there are no children. 7538 */ 7539 void 7540 pmcs_free_phys(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 7541 { 7542 pmcs_phy_t *next_phy; 7543 7544 while (phyp) { 7545 next_phy = phyp->sibling; 7546 ASSERT(!mutex_owned(&phyp->phy_lock)); 7547 phyp->target_addr = NULL; 7548 kmem_cache_free(pwp->phy_cache, phyp); 7549 phyp = next_phy; 7550 } 7551 } 7552 7553 /* 7554 * Make a copy of an existing PHY structure. This is used primarily in 7555 * discovery to compare the contents of an existing PHY with what gets 7556 * reported back by an expander. 7557 * 7558 * This function must not be called from any context where sleeping is 7559 * not possible. 7560 * 7561 * The new PHY is returned unlocked. 7562 */ 7563 static pmcs_phy_t * 7564 pmcs_clone_phy(pmcs_phy_t *orig_phy) 7565 { 7566 pmcs_phy_t *local; 7567 7568 local = kmem_cache_alloc(orig_phy->pwp->phy_cache, KM_SLEEP); 7569 7570 /* 7571 * Go ahead and just copy everything... 7572 */ 7573 *local = *orig_phy; 7574 local->target_addr = &orig_phy->target; 7575 7576 /* 7577 * But the following must be set appropriately for this copy 7578 */ 7579 local->sibling = NULL; 7580 local->children = NULL; 7581 local->target = NULL; 7582 mutex_init(&local->phy_lock, NULL, MUTEX_DRIVER, 7583 DDI_INTR_PRI(orig_phy->pwp->intr_pri)); 7584 7585 return (local); 7586 } 7587 7588 int 7589 pmcs_check_acc_handle(ddi_acc_handle_t handle) 7590 { 7591 ddi_fm_error_t de; 7592 7593 if (handle == NULL) { 7594 return (DDI_FAILURE); 7595 } 7596 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0); 7597 return (de.fme_status); 7598 } 7599 7600 int 7601 pmcs_check_dma_handle(ddi_dma_handle_t handle) 7602 { 7603 ddi_fm_error_t de; 7604 7605 if (handle == NULL) { 7606 return (DDI_FAILURE); 7607 } 7608 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0); 7609 return (de.fme_status); 7610 } 7611 7612 7613 void 7614 pmcs_fm_ereport(pmcs_hw_t *pwp, char *detail) 7615 { 7616 uint64_t ena; 7617 char buf[FM_MAX_CLASS]; 7618 7619 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 7620 ena = fm_ena_generate(0, FM_ENA_FMT1); 7621 if (DDI_FM_EREPORT_CAP(pwp->fm_capabilities)) { 7622 ddi_fm_ereport_post(pwp->dip, buf, ena, DDI_NOSLEEP, 7623 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 7624 } 7625 } 7626 7627 int 7628 pmcs_check_acc_dma_handle(pmcs_hw_t *pwp) 7629 { 7630 pmcs_chunk_t *pchunk; 7631 int i; 7632 7633 /* check all acc & dma handles allocated in attach */ 7634 if ((pmcs_check_acc_handle(pwp->pci_acc_handle) != DDI_SUCCESS) || 7635 (pmcs_check_acc_handle(pwp->msg_acc_handle) != DDI_SUCCESS) || 7636 (pmcs_check_acc_handle(pwp->top_acc_handle) != DDI_SUCCESS) || 7637 (pmcs_check_acc_handle(pwp->mpi_acc_handle) != DDI_SUCCESS) || 7638 (pmcs_check_acc_handle(pwp->gsm_acc_handle) != DDI_SUCCESS)) { 7639 goto check_failed; 7640 } 7641 7642 for (i = 0; i < PMCS_NIQ; i++) { 7643 if ((pmcs_check_dma_handle( 7644 pwp->iqp_handles[i]) != DDI_SUCCESS) || 7645 (pmcs_check_acc_handle( 7646 pwp->iqp_acchdls[i]) != DDI_SUCCESS)) { 7647 goto check_failed; 7648 } 7649 } 7650 7651 for (i = 0; i < PMCS_NOQ; i++) { 7652 if ((pmcs_check_dma_handle( 7653 pwp->oqp_handles[i]) != DDI_SUCCESS) || 7654 (pmcs_check_acc_handle( 7655 pwp->oqp_acchdls[i]) != DDI_SUCCESS)) { 7656 goto check_failed; 7657 } 7658 } 7659 7660 if ((pmcs_check_dma_handle(pwp->cip_handles) != DDI_SUCCESS) || 7661 (pmcs_check_acc_handle(pwp->cip_acchdls) != DDI_SUCCESS)) { 7662 goto check_failed; 7663 } 7664 7665 if (pwp->fwlog && 7666 ((pmcs_check_dma_handle(pwp->fwlog_hndl) != DDI_SUCCESS) || 7667 (pmcs_check_acc_handle(pwp->fwlog_acchdl) != DDI_SUCCESS))) { 7668 goto check_failed; 7669 } 7670 7671 if (pwp->regdump_hndl && pwp->regdump_acchdl && 7672 ((pmcs_check_dma_handle(pwp->regdump_hndl) != DDI_SUCCESS) || 7673 (pmcs_check_acc_handle(pwp->regdump_acchdl) 7674 != DDI_SUCCESS))) { 7675 goto check_failed; 7676 } 7677 7678 7679 pchunk = pwp->dma_chunklist; 7680 while (pchunk) { 7681 if ((pmcs_check_acc_handle(pchunk->acc_handle) 7682 != DDI_SUCCESS) || 7683 (pmcs_check_dma_handle(pchunk->dma_handle) 7684 != DDI_SUCCESS)) { 7685 goto check_failed; 7686 } 7687 pchunk = pchunk->next; 7688 } 7689 7690 return (0); 7691 7692 check_failed: 7693 7694 return (1); 7695 } 7696 7697 /* 7698 * pmcs_handle_dead_phys 7699 * 7700 * If the PHY has no outstanding work associated with it, remove it from 7701 * the dead PHY list and free it. 7702 * 7703 * If pwp->ds_err_recovering or pwp->configuring is set, don't run. 7704 * This keeps routines that need to submit work to the chip from having to 7705 * hold PHY locks to ensure that PHYs don't disappear while they do their work. 7706 */ 7707 void 7708 pmcs_handle_dead_phys(pmcs_hw_t *pwp) 7709 { 7710 pmcs_phy_t *phyp, *nphyp, *pphyp; 7711 7712 mutex_enter(&pwp->lock); 7713 mutex_enter(&pwp->config_lock); 7714 7715 if (pwp->configuring | pwp->ds_err_recovering) { 7716 mutex_exit(&pwp->config_lock); 7717 mutex_exit(&pwp->lock); 7718 return; 7719 } 7720 7721 /* 7722 * Check every PHY in the dead PHY list 7723 */ 7724 mutex_enter(&pwp->dead_phylist_lock); 7725 phyp = pwp->dead_phys; 7726 pphyp = NULL; /* Set previous PHY to NULL */ 7727 7728 while (phyp != NULL) { 7729 pmcs_lock_phy(phyp); 7730 ASSERT(phyp->dead); 7731 7732 nphyp = phyp->dead_next; 7733 7734 /* 7735 * Check for outstanding work 7736 */ 7737 if (phyp->ref_count > 0) { 7738 pmcs_unlock_phy(phyp); 7739 pphyp = phyp; /* This PHY becomes "previous" */ 7740 } else if (phyp->target) { 7741 pmcs_unlock_phy(phyp); 7742 pmcs_prt(pwp, PMCS_PRT_DEBUG1, phyp, phyp->target, 7743 "%s: Not freeing PHY 0x%p: target 0x%p is not free", 7744 __func__, (void *)phyp, (void *)phyp->target); 7745 pphyp = phyp; 7746 } else { 7747 /* 7748 * No outstanding work or target references. Remove it 7749 * from the list and free it 7750 */ 7751 pmcs_prt(pwp, PMCS_PRT_DEBUG, phyp, phyp->target, 7752 "%s: Freeing inactive dead PHY 0x%p @ %s " 7753 "target = 0x%p", __func__, (void *)phyp, 7754 phyp->path, (void *)phyp->target); 7755 /* 7756 * If pphyp is NULL, then phyp was the head of the list, 7757 * so just reset the head to nphyp. Otherwise, the 7758 * previous PHY will now point to nphyp (the next PHY) 7759 */ 7760 if (pphyp == NULL) { 7761 pwp->dead_phys = nphyp; 7762 } else { 7763 pphyp->dead_next = nphyp; 7764 } 7765 /* 7766 * If the target still points to this PHY, remove 7767 * that linkage now. 7768 */ 7769 if (phyp->target) { 7770 mutex_enter(&phyp->target->statlock); 7771 if (phyp->target->phy == phyp) { 7772 phyp->target->phy = NULL; 7773 } 7774 mutex_exit(&phyp->target->statlock); 7775 } 7776 pmcs_unlock_phy(phyp); 7777 phyp->target_addr = NULL; 7778 kmem_cache_free(pwp->phy_cache, phyp); 7779 } 7780 7781 phyp = nphyp; 7782 } 7783 7784 mutex_exit(&pwp->dead_phylist_lock); 7785 mutex_exit(&pwp->config_lock); 7786 mutex_exit(&pwp->lock); 7787 } 7788 7789 void 7790 pmcs_inc_phy_ref_count(pmcs_phy_t *phyp) 7791 { 7792 atomic_inc_32(&phyp->ref_count); 7793 } 7794 7795 void 7796 pmcs_dec_phy_ref_count(pmcs_phy_t *phyp) 7797 { 7798 ASSERT(phyp->ref_count != 0); 7799 atomic_dec_32(&phyp->ref_count); 7800 } 7801 7802 /* 7803 * pmcs_reap_dead_phy 7804 * 7805 * This function is called from pmcs_new_tport when we have a PHY 7806 * without a target pointer. It's possible in that case that this PHY 7807 * may have a "brother" on the dead_phys list. That is, it may be the same as 7808 * this one but with a different root PHY number (e.g. pp05 vs. pp04). If 7809 * that's the case, update the dead PHY and this new PHY. If that's not the 7810 * case, we should get a tran_tgt_init on this after it's reported to SCSA. 7811 * 7812 * Called with PHY locked. 7813 */ 7814 static void 7815 pmcs_reap_dead_phy(pmcs_phy_t *phyp) 7816 { 7817 pmcs_hw_t *pwp = phyp->pwp; 7818 pmcs_phy_t *ctmp; 7819 pmcs_iport_t *iport_cmp; 7820 7821 ASSERT(mutex_owned(&phyp->phy_lock)); 7822 7823 /* 7824 * Check the dead PHYs list 7825 */ 7826 mutex_enter(&pwp->dead_phylist_lock); 7827 ctmp = pwp->dead_phys; 7828 while (ctmp) { 7829 /* 7830 * If the iport is NULL, compare against last_iport. 7831 */ 7832 if (ctmp->iport) { 7833 iport_cmp = ctmp->iport; 7834 } else { 7835 iport_cmp = ctmp->last_iport; 7836 } 7837 7838 if ((iport_cmp != phyp->iport) || 7839 (memcmp((void *)&ctmp->sas_address[0], 7840 (void *)&phyp->sas_address[0], 8))) { 7841 ctmp = ctmp->dead_next; 7842 continue; 7843 } 7844 7845 /* 7846 * Same SAS address on same iport. Now check to see if 7847 * the PHY path is the same with the possible exception 7848 * of the root PHY number. 7849 * The "5" is the string length of "pp00." 7850 */ 7851 if ((strnlen(phyp->path, 5) >= 5) && 7852 (strnlen(ctmp->path, 5) >= 5)) { 7853 if (memcmp((void *)&phyp->path[5], 7854 (void *)&ctmp->path[5], 7855 strnlen(phyp->path, 32) - 5) == 0) { 7856 break; 7857 } 7858 } 7859 7860 ctmp = ctmp->dead_next; 7861 } 7862 mutex_exit(&pwp->dead_phylist_lock); 7863 7864 /* 7865 * Found a match. Remove the target linkage and drop the 7866 * ref count on the old PHY. Then, increment the ref count 7867 * on the new PHY to compensate. 7868 */ 7869 if (ctmp) { 7870 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, ctmp, NULL, 7871 "%s: Found match in dead PHY list (0x%p) for new PHY %s", 7872 __func__, (void *)ctmp, phyp->path); 7873 /* 7874 * If there is a pointer to the target in the dead PHY, move 7875 * all reference counts to the new PHY. 7876 */ 7877 if (ctmp->target) { 7878 mutex_enter(&ctmp->target->statlock); 7879 phyp->target = ctmp->target; 7880 7881 while (ctmp->ref_count != 0) { 7882 pmcs_inc_phy_ref_count(phyp); 7883 pmcs_dec_phy_ref_count(ctmp); 7884 } 7885 /* 7886 * Update the target's linkage as well 7887 */ 7888 phyp->target->phy = phyp; 7889 phyp->target->dtype = phyp->dtype; 7890 ctmp->target = NULL; 7891 mutex_exit(&phyp->target->statlock); 7892 } 7893 } 7894 } 7895 7896 /* 7897 * Called with iport lock held 7898 */ 7899 void 7900 pmcs_add_phy_to_iport(pmcs_iport_t *iport, pmcs_phy_t *phyp) 7901 { 7902 ASSERT(mutex_owned(&iport->lock)); 7903 ASSERT(phyp); 7904 ASSERT(!list_link_active(&phyp->list_node)); 7905 7906 iport->nphy++; 7907 list_insert_tail(&iport->phys, phyp); 7908 pmcs_smhba_add_iport_prop(iport, DATA_TYPE_INT32, PMCS_NUM_PHYS, 7909 &iport->nphy); 7910 mutex_enter(&phyp->phy_lock); 7911 pmcs_create_one_phy_stats(iport, phyp); 7912 mutex_exit(&phyp->phy_lock); 7913 pmcs_hold_iport(iport); 7914 } 7915 7916 /* 7917 * Called with the iport lock held 7918 */ 7919 void 7920 pmcs_remove_phy_from_iport(pmcs_iport_t *iport, pmcs_phy_t *phyp) 7921 { 7922 pmcs_phy_t *pptr, *next_pptr; 7923 7924 ASSERT(mutex_owned(&iport->lock)); 7925 7926 /* 7927 * If phyp is NULL, remove all PHYs from the iport 7928 */ 7929 if (phyp == NULL) { 7930 for (pptr = list_head(&iport->phys); pptr != NULL; 7931 pptr = next_pptr) { 7932 next_pptr = list_next(&iport->phys, pptr); 7933 mutex_enter(&pptr->phy_lock); 7934 if (pptr->phy_stats != NULL) { 7935 kstat_delete(pptr->phy_stats); 7936 pptr->phy_stats = NULL; 7937 } 7938 pptr->iport = NULL; 7939 pmcs_update_phy_pm_props(pptr, pptr->att_port_pm_tmp, 7940 pptr->tgt_port_pm_tmp, B_FALSE); 7941 mutex_exit(&pptr->phy_lock); 7942 pmcs_rele_iport(iport); 7943 list_remove(&iport->phys, pptr); 7944 pmcs_smhba_add_iport_prop(iport, DATA_TYPE_INT32, 7945 PMCS_NUM_PHYS, &iport->nphy); 7946 } 7947 iport->nphy = 0; 7948 return; 7949 } 7950 7951 ASSERT(phyp); 7952 ASSERT(iport->nphy > 0); 7953 ASSERT(list_link_active(&phyp->list_node)); 7954 iport->nphy--; 7955 list_remove(&iport->phys, phyp); 7956 pmcs_update_phy_pm_props(phyp, phyp->att_port_pm_tmp, 7957 phyp->tgt_port_pm_tmp, B_FALSE); 7958 pmcs_smhba_add_iport_prop(iport, DATA_TYPE_INT32, PMCS_NUM_PHYS, 7959 &iport->nphy); 7960 pmcs_rele_iport(iport); 7961 } 7962 7963 /* 7964 * This function checks to see if the target pointed to by phyp is still 7965 * correct. This is done by comparing the target's unit address with the 7966 * SAS address in phyp. 7967 * 7968 * Called with PHY locked and target statlock held 7969 */ 7970 static boolean_t 7971 pmcs_phy_target_match(pmcs_phy_t *phyp) 7972 { 7973 uint64_t wwn; 7974 char unit_address[PMCS_MAX_UA_SIZE]; 7975 boolean_t rval = B_FALSE; 7976 7977 ASSERT(phyp); 7978 ASSERT(phyp->target); 7979 ASSERT(mutex_owned(&phyp->phy_lock)); 7980 ASSERT(mutex_owned(&phyp->target->statlock)); 7981 7982 wwn = pmcs_barray2wwn(phyp->sas_address); 7983 (void) scsi_wwn_to_wwnstr(wwn, 1, unit_address); 7984 7985 if (memcmp((void *)unit_address, (void *)phyp->target->unit_address, 7986 strnlen(phyp->target->unit_address, PMCS_MAX_UA_SIZE)) == 0) { 7987 rval = B_TRUE; 7988 } 7989 7990 return (rval); 7991 } 7992 /* 7993 * Commands used to serialize SMP requests. 7994 * 7995 * The SPC only allows 2 SMP commands per SMP target: 1 cmd pending and 1 cmd 7996 * queued for the same SMP target. If a third SMP cmd is sent to the SPC for an 7997 * SMP target that already has a SMP cmd pending and one queued, then the 7998 * SPC responds with the ERROR_INTERNAL_SMP_RESOURCE response. 7999 * 8000 * Additionally, the SPC has an 8 entry deep cmd queue and the number of SMP 8001 * cmds that can be queued is controlled by the PORT_CONTROL IOMB. The 8002 * SPC default is 1 SMP command/port (iport). These 2 queued SMP cmds would 8003 * have to be for different SMP targets. The INTERNAL_SMP_RESOURCE error will 8004 * also be returned if a 2nd SMP cmd is sent to the controller when there is 8005 * already 1 SMP cmd queued for that port or if a 3rd SMP cmd is sent to the 8006 * queue if there are already 2 queued SMP cmds. 8007 */ 8008 void 8009 pmcs_smp_acquire(pmcs_iport_t *iport) 8010 { 8011 if (iport == NULL) { 8012 return; 8013 } 8014 8015 mutex_enter(&iport->smp_lock); 8016 while (iport->smp_active) { 8017 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_IPORT, NULL, NULL, 8018 "%s: SMP is active on thread 0x%p, waiting", __func__, 8019 (void *)iport->smp_active_thread); 8020 cv_wait(&iport->smp_cv, &iport->smp_lock); 8021 } 8022 iport->smp_active = B_TRUE; 8023 iport->smp_active_thread = curthread; 8024 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG3, NULL, NULL, 8025 "%s: SMP acquired by thread 0x%p", __func__, 8026 (void *)iport->smp_active_thread); 8027 mutex_exit(&iport->smp_lock); 8028 } 8029 8030 void 8031 pmcs_smp_release(pmcs_iport_t *iport) 8032 { 8033 if (iport == NULL) { 8034 return; 8035 } 8036 8037 mutex_enter(&iport->smp_lock); 8038 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG3, NULL, NULL, 8039 "%s: SMP released by thread 0x%p", __func__, (void *)curthread); 8040 iport->smp_active = B_FALSE; 8041 iport->smp_active_thread = NULL; 8042 cv_signal(&iport->smp_cv); 8043 mutex_exit(&iport->smp_lock); 8044 } 8045 8046 /* 8047 * Update a PHY's attached-port-pm and target-port-pm properties 8048 * 8049 * phyp: PHY whose properties are to be updated 8050 * 8051 * att_bv: Bit value of the attached-port-pm property to be updated in the 8052 * 64-bit holding area for the PHY. 8053 * 8054 * tgt_bv: Bit value of the target-port-pm property to update in the 64-bit 8055 * holding area for the PHY. 8056 * 8057 * prop_add_val: If TRUE, we're adding bits into the property value. 8058 * Otherwise, we're taking them out. Either way, the properties for this 8059 * PHY will be updated. 8060 */ 8061 void 8062 pmcs_update_phy_pm_props(pmcs_phy_t *phyp, uint64_t att_bv, uint64_t tgt_bv, 8063 boolean_t prop_add_val) 8064 { 8065 pmcs_xscsi_t *tgt; 8066 8067 if (prop_add_val) { 8068 /* 8069 * If the values are currently 0, then we're setting the 8070 * phymask for just this PHY as well. 8071 */ 8072 if (phyp->att_port_pm_tmp == 0) { 8073 phyp->att_port_pm = att_bv; 8074 phyp->tgt_port_pm = tgt_bv; 8075 } 8076 phyp->att_port_pm_tmp |= att_bv; 8077 phyp->tgt_port_pm_tmp |= tgt_bv; 8078 (void) snprintf(phyp->att_port_pm_str, PMCS_PM_MAX_NAMELEN, 8079 "%"PRIx64, phyp->att_port_pm_tmp); 8080 (void) snprintf(phyp->tgt_port_pm_str, PMCS_PM_MAX_NAMELEN, 8081 "%"PRIx64, phyp->tgt_port_pm_tmp); 8082 } else { 8083 phyp->att_port_pm_tmp &= ~att_bv; 8084 phyp->tgt_port_pm_tmp &= ~tgt_bv; 8085 if (phyp->att_port_pm_tmp) { 8086 (void) snprintf(phyp->att_port_pm_str, 8087 PMCS_PM_MAX_NAMELEN, "%"PRIx64, 8088 phyp->att_port_pm_tmp); 8089 } else { 8090 phyp->att_port_pm_str[0] = '\0'; 8091 phyp->att_port_pm = 0; 8092 } 8093 if (phyp->tgt_port_pm_tmp) { 8094 (void) snprintf(phyp->tgt_port_pm_str, 8095 PMCS_PM_MAX_NAMELEN, "%"PRIx64, 8096 phyp->tgt_port_pm_tmp); 8097 } else { 8098 phyp->tgt_port_pm_str[0] = '\0'; 8099 phyp->tgt_port_pm = 0; 8100 } 8101 } 8102 8103 if ((phyp->target_addr) && (*phyp->target_addr != NULL)) { 8104 tgt = *phyp->target_addr; 8105 } else if (phyp->target != NULL) { 8106 tgt = phyp->target; 8107 } else { 8108 return; 8109 } 8110 8111 mutex_enter(&tgt->statlock); 8112 if (!list_is_empty(&tgt->lun_list)) { 8113 pmcs_lun_t *lunp; 8114 8115 lunp = list_head(&tgt->lun_list); 8116 while (lunp) { 8117 (void) scsi_device_prop_update_string(lunp->sd, 8118 SCSI_DEVICE_PROP_PATH, 8119 SCSI_ADDR_PROP_ATTACHED_PORT_PM, 8120 phyp->att_port_pm_str); 8121 (void) scsi_device_prop_update_string(lunp->sd, 8122 SCSI_DEVICE_PROP_PATH, 8123 SCSI_ADDR_PROP_TARGET_PORT_PM, 8124 phyp->tgt_port_pm_str); 8125 lunp = list_next(&tgt->lun_list, lunp); 8126 } 8127 } else if (tgt->smpd) { 8128 (void) smp_device_prop_update_string(tgt->smpd, 8129 SCSI_ADDR_PROP_ATTACHED_PORT_PM, 8130 phyp->att_port_pm_str); 8131 (void) smp_device_prop_update_string(tgt->smpd, 8132 SCSI_ADDR_PROP_TARGET_PORT_PM, 8133 phyp->tgt_port_pm_str); 8134 } 8135 mutex_exit(&tgt->statlock); 8136 } 8137 8138 /* ARGSUSED */ 8139 void 8140 pmcs_deregister_device_work(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 8141 { 8142 pmcs_phy_t *pptr; 8143 8144 for (pptr = pwp->root_phys; pptr; pptr = pptr->sibling) { 8145 pmcs_lock_phy(pptr); 8146 if (pptr->deregister_wait) { 8147 pmcs_deregister_device(pwp, pptr); 8148 } 8149 pmcs_unlock_phy(pptr); 8150 } 8151 } 8152 8153 /* 8154 * pmcs_iport_active 8155 * 8156 * Mark this iport as active. Called with the iport lock held. 8157 */ 8158 static void 8159 pmcs_iport_active(pmcs_iport_t *iport) 8160 { 8161 ASSERT(mutex_owned(&iport->lock)); 8162 8163 iport->ua_state = UA_ACTIVE; 8164 iport->smp_active = B_FALSE; 8165 iport->smp_active_thread = NULL; 8166 } 8167 8168 /* ARGSUSED */ 8169 static void 8170 pmcs_tgtmap_activate_cb(void *tgtmap_priv, char *tgt_addr, 8171 scsi_tgtmap_tgt_type_t tgt_type, void **tgt_privp) 8172 { 8173 pmcs_iport_t *iport = (pmcs_iport_t *)tgtmap_priv; 8174 pmcs_hw_t *pwp = iport->pwp; 8175 pmcs_xscsi_t *target; 8176 8177 /* 8178 * Look up the target. If there is one, and it doesn't have a PHY 8179 * pointer, re-establish that linkage here. 8180 */ 8181 mutex_enter(&pwp->lock); 8182 target = pmcs_get_target(iport, tgt_addr, B_FALSE); 8183 mutex_exit(&pwp->lock); 8184 8185 /* 8186 * If we got a target, it will now have a PHY pointer and the PHY 8187 * will point to the target. The PHY will be locked, so we'll need 8188 * to unlock it. 8189 */ 8190 if (target != NULL) { 8191 pmcs_unlock_phy(target->phy); 8192 } 8193 8194 /* 8195 * Update config_restart_time so we don't try to restart discovery 8196 * while enumeration is still in progress. 8197 */ 8198 mutex_enter(&pwp->config_lock); 8199 pwp->config_restart_time = ddi_get_lbolt() + 8200 drv_usectohz(PMCS_REDISCOVERY_DELAY); 8201 mutex_exit(&pwp->config_lock); 8202 } 8203 8204 /* ARGSUSED */ 8205 static boolean_t 8206 pmcs_tgtmap_deactivate_cb(void *tgtmap_priv, char *tgt_addr, 8207 scsi_tgtmap_tgt_type_t tgt_type, void *tgt_priv, 8208 scsi_tgtmap_deact_rsn_t tgt_deact_rsn) 8209 { 8210 pmcs_iport_t *iport = (pmcs_iport_t *)tgtmap_priv; 8211 pmcs_phy_t *phyp; 8212 boolean_t rediscover = B_FALSE; 8213 8214 ASSERT(iport); 8215 8216 phyp = pmcs_find_phy_by_sas_address(iport->pwp, iport, NULL, tgt_addr); 8217 if (phyp == NULL) { 8218 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_IPORT, NULL, NULL, 8219 "%s: Couldn't find PHY at %s", __func__, tgt_addr); 8220 return (rediscover); 8221 } 8222 /* phyp is locked */ 8223 8224 if (!phyp->reenumerate && phyp->configured) { 8225 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_CONFIG, phyp, phyp->target, 8226 "%s: PHY @ %s is configured... re-enumerate", __func__, 8227 tgt_addr); 8228 phyp->reenumerate = 1; 8229 } 8230 8231 /* 8232 * Check to see if reenumerate is set, and if so, if we've reached our 8233 * maximum number of retries. 8234 */ 8235 if (phyp->reenumerate) { 8236 if (phyp->enum_attempts == PMCS_MAX_REENUMERATE) { 8237 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_CONFIG, phyp, 8238 phyp->target, 8239 "%s: No more enumeration attempts for %s", __func__, 8240 tgt_addr); 8241 } else { 8242 pmcs_prt(iport->pwp, PMCS_PRT_DEBUG_CONFIG, phyp, 8243 phyp->target, "%s: Re-attempt enumeration for %s", 8244 __func__, tgt_addr); 8245 ++phyp->enum_attempts; 8246 rediscover = B_TRUE; 8247 } 8248 8249 phyp->reenumerate = 0; 8250 } 8251 8252 pmcs_unlock_phy(phyp); 8253 8254 mutex_enter(&iport->pwp->config_lock); 8255 iport->pwp->config_restart_time = ddi_get_lbolt() + 8256 drv_usectohz(PMCS_REDISCOVERY_DELAY); 8257 if (rediscover) { 8258 iport->pwp->config_restart = B_TRUE; 8259 } else if (iport->pwp->config_restart == B_TRUE) { 8260 /* 8261 * If we aren't asking for rediscovery because of this PHY, 8262 * check to see if we're already asking for it on behalf of 8263 * some other PHY. If so, we'll want to return TRUE, so reset 8264 * "rediscover" here. 8265 */ 8266 rediscover = B_TRUE; 8267 } 8268 8269 mutex_exit(&iport->pwp->config_lock); 8270 8271 return (rediscover); 8272 } 8273 8274 void 8275 pmcs_status_disposition(pmcs_phy_t *phyp, uint32_t status) 8276 { 8277 ASSERT(phyp); 8278 ASSERT(!mutex_owned(&phyp->phy_lock)); 8279 8280 if (phyp == NULL) { 8281 return; 8282 } 8283 8284 pmcs_lock_phy(phyp); 8285 8286 /* 8287 * XXX: Do we need to call this function from an SSP_EVENT? 8288 */ 8289 8290 switch (status) { 8291 case PMCOUT_STATUS_NO_DEVICE: 8292 case PMCOUT_STATUS_ERROR_HW_TIMEOUT: 8293 case PMCOUT_STATUS_XFER_ERR_BREAK: 8294 case PMCOUT_STATUS_XFER_ERR_PHY_NOT_READY: 8295 case PMCOUT_STATUS_OPEN_CNX_PROTOCOL_NOT_SUPPORTED: 8296 case PMCOUT_STATUS_OPEN_CNX_ERROR_ZONE_VIOLATION: 8297 case PMCOUT_STATUS_OPEN_CNX_ERROR_BREAK: 8298 case PMCOUT_STATUS_OPENCNX_ERROR_BAD_DESTINATION: 8299 case PMCOUT_STATUS_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED: 8300 case PMCOUT_STATUS_OPEN_CNX_ERROR_STP_RESOURCES_BUSY: 8301 case PMCOUT_STATUS_OPEN_CNX_ERROR_WRONG_DESTINATION: 8302 case PMCOUT_STATUS_OPEN_CNX_ERROR_UNKNOWN_ERROR: 8303 case PMCOUT_STATUS_IO_XFER_ERROR_NAK_RECEIVED: 8304 case PMCOUT_STATUS_XFER_ERROR_RX_FRAME: 8305 case PMCOUT_STATUS_IO_XFER_OPEN_RETRY_TIMEOUT: 8306 case PMCOUT_STATUS_ERROR_INTERNAL_SMP_RESOURCE: 8307 case PMCOUT_STATUS_IO_PORT_IN_RESET: 8308 case PMCOUT_STATUS_IO_DS_NON_OPERATIONAL: 8309 case PMCOUT_STATUS_IO_DS_IN_RECOVERY: 8310 case PMCOUT_STATUS_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY: 8311 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG, phyp, phyp->target, 8312 "%s: status = 0x%x for " SAS_ADDR_FMT ", reenumerate", 8313 __func__, status, SAS_ADDR_PRT(phyp->sas_address)); 8314 phyp->reenumerate = 1; 8315 break; 8316 8317 default: 8318 pmcs_prt(phyp->pwp, PMCS_PRT_DEBUG, phyp, phyp->target, 8319 "%s: status = 0x%x for " SAS_ADDR_FMT ", no reenumeration", 8320 __func__, status, SAS_ADDR_PRT(phyp->sas_address)); 8321 break; 8322 } 8323 8324 pmcs_unlock_phy(phyp); 8325 } 8326 8327 /* 8328 * Add the list of PHYs pointed to by phyp to the dead_phys_list 8329 * 8330 * Called with all PHYs in the list locked 8331 */ 8332 static void 8333 pmcs_add_dead_phys(pmcs_hw_t *pwp, pmcs_phy_t *phyp) 8334 { 8335 mutex_enter(&pwp->dead_phylist_lock); 8336 while (phyp) { 8337 pmcs_phy_t *nxt = phyp->sibling; 8338 ASSERT(phyp->dead); 8339 pmcs_prt(pwp, PMCS_PRT_DEBUG_CONFIG, phyp, NULL, 8340 "%s: dead PHY 0x%p (%s) (ref_count %d)", __func__, 8341 (void *)phyp, phyp->path, phyp->ref_count); 8342 /* 8343 * Put this PHY on the dead PHY list for the watchdog to 8344 * clean up after any outstanding work has completed. 8345 */ 8346 phyp->dead_next = pwp->dead_phys; 8347 pwp->dead_phys = phyp; 8348 pmcs_unlock_phy(phyp); 8349 phyp = nxt; 8350 } 8351 mutex_exit(&pwp->dead_phylist_lock); 8352 } 8353 8354 static void 8355 pmcs_get_fw_version(pmcs_hw_t *pwp) 8356 { 8357 uint32_t ila_len, ver_hi, ver_lo; 8358 uint8_t ila_ver_string[9], img_flag; 8359 char uc, *ucp = &uc; 8360 unsigned long ila_ver; 8361 uint64_t ver_hilo; 8362 8363 /* Firmware version is easy. */ 8364 pwp->fw = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_FW); 8365 8366 /* 8367 * Get the image size (2nd to last dword) 8368 * NOTE: The GSM registers are mapped little-endian, but the data 8369 * on the flash is actually big-endian, so we need to swap these values 8370 * regardless of which platform we're on. 8371 */ 8372 ila_len = BSWAP_32(pmcs_rd_gsm_reg(pwp, GSM_FLASH_BASE_UPPER, 8373 GSM_FLASH_BASE + GSM_SM_BLKSZ - (2 << 2))); 8374 if (ila_len > 65535) { 8375 pmcs_prt(pwp, PMCS_PRT_DEBUG, NULL, NULL, 8376 "%s: Invalid ILA image size (0x%x)?", __func__, ila_len); 8377 return; 8378 } 8379 8380 /* 8381 * The numeric version is at ila_len - PMCS_ILA_VER_OFFSET 8382 */ 8383 ver_hi = BSWAP_32(pmcs_rd_gsm_reg(pwp, GSM_FLASH_BASE_UPPER, 8384 GSM_FLASH_BASE + ila_len - PMCS_ILA_VER_OFFSET)); 8385 ver_lo = BSWAP_32(pmcs_rd_gsm_reg(pwp, GSM_FLASH_BASE_UPPER, 8386 GSM_FLASH_BASE + ila_len - PMCS_ILA_VER_OFFSET + 4)); 8387 ver_hilo = BE_64(((uint64_t)ver_hi << 32) | ver_lo); 8388 bcopy((const void *)&ver_hilo, &ila_ver_string[0], 8); 8389 ila_ver_string[8] = '\0'; 8390 8391 (void) ddi_strtoul((const char *)ila_ver_string, &ucp, 16, &ila_ver); 8392 pwp->ila_ver = (int)(ila_ver & 0xffffffff); 8393 8394 img_flag = (BSWAP_32(pmcs_rd_gsm_reg(pwp, GSM_FLASH_BASE_UPPER, 8395 GSM_FLASH_IMG_FLAGS)) & 0xff000000) >> 24; 8396 if (img_flag & PMCS_IMG_FLAG_A) { 8397 pwp->fw_active_img = 1; 8398 } else { 8399 pwp->fw_active_img = 0; 8400 } 8401 } 8402