1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2016 Nexenta Systems, Inc. All rights reserved. 25 * Copyright 2019 Joyent, Inc. 26 * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved. 27 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved. 28 * Copyright 2023 Oxide Computer Company 29 */ 30 31 /* 32 * Copyright (c) 2000 to 2010, LSI Corporation. 33 * All rights reserved. 34 * 35 * Redistribution and use in source and binary forms of all code within 36 * this file that is exclusively owned by LSI, with or without 37 * modification, is permitted provided that, in addition to the CDDL 1.0 38 * License requirements, the following conditions are met: 39 * 40 * Neither the name of the author nor the names of its contributors may be 41 * used to endorse or promote products derived from this software without 42 * specific prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 45 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 46 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 47 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 48 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 50 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 51 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 52 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 53 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 54 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 55 * DAMAGE. 56 */ 57 58 /* 59 * mptsas - This is a driver based on LSI Logic's MPT2.0/2.5 interface. 60 * 61 */ 62 63 #if defined(lint) || defined(DEBUG) 64 #define MPTSAS_DEBUG 65 #endif 66 67 /* 68 * standard header files. 69 */ 70 #include <sys/note.h> 71 #include <sys/scsi/scsi.h> 72 #include <sys/pci.h> 73 #include <sys/file.h> 74 #include <sys/policy.h> 75 #include <sys/model.h> 76 #include <sys/refhash.h> 77 #include <sys/sysevent.h> 78 #include <sys/sysevent/eventdefs.h> 79 #include <sys/sysevent/dr.h> 80 #include <sys/sata/sata_defs.h> 81 #include <sys/sata/sata_hba.h> 82 #include <sys/scsi/generic/sas.h> 83 #include <sys/scsi/impl/scsi_sas.h> 84 85 #pragma pack(1) 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h> 87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h> 88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h> 90 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h> 91 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h> 92 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 93 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h> 94 #pragma pack() 95 96 /* 97 * private header files. 98 * 99 */ 100 #include <sys/scsi/impl/scsi_reset_notify.h> 101 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h> 102 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 103 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h> 104 #include <sys/raidioctl.h> 105 106 #include <sys/fs/dv_node.h> /* devfs_clean */ 107 108 /* 109 * FMA header files 110 */ 111 #include <sys/ddifm.h> 112 #include <sys/fm/protocol.h> 113 #include <sys/fm/util.h> 114 #include <sys/fm/io/ddi.h> 115 116 /* 117 * autoconfiguration data and routines. 118 */ 119 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 120 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 121 static int mptsas_power(dev_info_t *dip, int component, int level); 122 123 /* 124 * cb_ops function 125 */ 126 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 127 cred_t *credp, int *rval); 128 #ifdef __sparc 129 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd); 130 #else /* __sparc */ 131 static int mptsas_quiesce(dev_info_t *devi); 132 #endif /* __sparc */ 133 134 /* 135 * ddi_ufm_ops 136 */ 137 static int mptsas_ufm_fill_image(ddi_ufm_handle_t *ufmh, void *arg, 138 uint_t imgno, ddi_ufm_image_t *img); 139 static int mptsas_ufm_fill_slot(ddi_ufm_handle_t *ufmh, void *arg, 140 uint_t imgno, uint_t slotno, ddi_ufm_slot_t *slot); 141 static int mptsas_ufm_getcaps(ddi_ufm_handle_t *ufmh, void *arg, 142 ddi_ufm_cap_t *caps); 143 144 /* 145 * Resource initialization for hardware 146 */ 147 static void mptsas_setup_cmd_reg(mptsas_t *mpt); 148 static void mptsas_disable_bus_master(mptsas_t *mpt); 149 static void mptsas_hba_fini(mptsas_t *mpt); 150 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp); 151 static int mptsas_hba_setup(mptsas_t *mpt); 152 static void mptsas_hba_teardown(mptsas_t *mpt); 153 static int mptsas_config_space_init(mptsas_t *mpt); 154 static void mptsas_config_space_fini(mptsas_t *mpt); 155 static void mptsas_iport_register(mptsas_t *mpt); 156 static int mptsas_smp_setup(mptsas_t *mpt); 157 static void mptsas_smp_teardown(mptsas_t *mpt); 158 static int mptsas_enc_setup(mptsas_t *mpt); 159 static void mptsas_enc_teardown(mptsas_t *mpt); 160 static int mptsas_cache_create(mptsas_t *mpt); 161 static void mptsas_cache_destroy(mptsas_t *mpt); 162 static int mptsas_alloc_request_frames(mptsas_t *mpt); 163 static int mptsas_alloc_sense_bufs(mptsas_t *mpt); 164 static int mptsas_alloc_reply_frames(mptsas_t *mpt); 165 static int mptsas_alloc_free_queue(mptsas_t *mpt); 166 static int mptsas_alloc_post_queue(mptsas_t *mpt); 167 static void mptsas_alloc_reply_args(mptsas_t *mpt); 168 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 169 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 170 static int mptsas_init_chip(mptsas_t *mpt, int first_time); 171 static void mptsas_update_hashtab(mptsas_t *mpt); 172 173 /* 174 * SCSA function prototypes 175 */ 176 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt); 177 static int mptsas_scsi_reset(struct scsi_address *ap, int level); 178 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt); 179 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly); 180 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, 181 int tgtonly); 182 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt); 183 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap, 184 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 185 int tgtlen, int flags, int (*callback)(), caddr_t arg); 186 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt); 187 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap, 188 struct scsi_pkt *pkt); 189 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 190 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 191 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 192 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 193 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 194 void (*callback)(caddr_t), caddr_t arg); 195 static int mptsas_get_name(struct scsi_device *sd, char *name, int len); 196 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len); 197 static int mptsas_scsi_quiesce(dev_info_t *dip); 198 static int mptsas_scsi_unquiesce(dev_info_t *dip); 199 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags, 200 ddi_bus_config_op_t op, void *arg, dev_info_t **childp); 201 202 /* 203 * SMP functions 204 */ 205 static int mptsas_smp_start(struct smp_pkt *smp_pkt); 206 207 /* 208 * internal function prototypes. 209 */ 210 static void mptsas_list_add(mptsas_t *mpt); 211 static void mptsas_list_del(mptsas_t *mpt); 212 213 static int mptsas_quiesce_bus(mptsas_t *mpt); 214 static int mptsas_unquiesce_bus(mptsas_t *mpt); 215 216 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size); 217 static void mptsas_free_handshake_msg(mptsas_t *mpt); 218 219 static void mptsas_ncmds_checkdrain(void *arg); 220 221 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd); 222 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 223 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 224 static void mptsas_accept_tx_waitq(mptsas_t *mpt); 225 226 static int mptsas_do_detach(dev_info_t *dev); 227 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl); 228 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, 229 struct scsi_pkt *pkt); 230 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp); 231 232 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd); 233 static void mptsas_handle_event(void *args); 234 static int mptsas_handle_event_sync(void *args); 235 static void mptsas_handle_dr(void *args); 236 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 237 dev_info_t *pdip); 238 239 static void mptsas_restart_cmd(void *); 240 241 static void mptsas_flush_hba(mptsas_t *mpt); 242 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, 243 uint8_t tasktype); 244 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, 245 uchar_t reason, uint_t stat); 246 247 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2); 248 static void mptsas_process_intr(mptsas_t *mpt, 249 pMpi2ReplyDescriptorsUnion_t reply_desc_union); 250 static void mptsas_handle_scsi_io_success(mptsas_t *mpt, 251 pMpi2ReplyDescriptorsUnion_t reply_desc); 252 static void mptsas_handle_address_reply(mptsas_t *mpt, 253 pMpi2ReplyDescriptorsUnion_t reply_desc); 254 static int mptsas_wait_intr(mptsas_t *mpt, int polltime); 255 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, 256 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl); 257 258 static void mptsas_watch(void *arg); 259 static void mptsas_watchsubr(mptsas_t *mpt); 260 static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt); 261 262 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd); 263 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 264 uint8_t *data, uint32_t request_size, uint32_t reply_size, 265 uint32_t data_size, uint32_t direction, uint8_t *dataout, 266 uint32_t dataout_size, short timeout, int mode); 267 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl); 268 269 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, 270 uint32_t unique_id); 271 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd); 272 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt, 273 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code); 274 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt, 275 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 276 uint32_t diag_type); 277 static int mptsas_diag_register(mptsas_t *mpt, 278 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code); 279 static int mptsas_diag_unregister(mptsas_t *mpt, 280 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code); 281 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 282 uint32_t *return_code); 283 static int mptsas_diag_read_buffer(mptsas_t *mpt, 284 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 285 uint32_t *return_code, int ioctl_mode); 286 static int mptsas_diag_release(mptsas_t *mpt, 287 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code); 288 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, 289 uint8_t *diag_action, uint32_t length, uint32_t *return_code, 290 int ioctl_mode); 291 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data, 292 int mode); 293 294 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 295 int cmdlen, int tgtlen, int statuslen, int kf); 296 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd); 297 298 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags); 299 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg); 300 301 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg, 302 int kmflags); 303 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg); 304 305 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 306 mptsas_cmd_t *cmd); 307 static void mptsas_check_task_mgt(mptsas_t *mpt, 308 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd); 309 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 310 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 311 int *resid); 312 313 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag); 314 static void mptsas_free_active_slots(mptsas_t *mpt); 315 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 316 317 static void mptsas_restart_hba(mptsas_t *mpt); 318 static void mptsas_restart_waitq(mptsas_t *mpt); 319 320 static void mptsas_deliver_doneq_thread(mptsas_t *mpt); 321 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 322 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t); 323 324 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t); 325 static void mptsas_doneq_empty(mptsas_t *mpt); 326 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg); 327 328 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt); 329 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 330 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt); 331 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 332 333 334 static void mptsas_start_watch_reset_delay(); 335 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt); 336 static void mptsas_watch_reset_delay(void *arg); 337 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt); 338 339 /* 340 * helper functions 341 */ 342 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 343 344 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name); 345 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy); 346 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, 347 int lun); 348 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr, 349 int lun); 350 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy); 351 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn); 352 353 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, 354 int *lun); 355 static int mptsas_parse_smp_name(char *name, uint64_t *wwn); 356 357 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, 358 mptsas_phymask_t phymask, uint8_t phy); 359 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, 360 mptsas_phymask_t phymask, uint64_t wwid); 361 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, 362 mptsas_phymask_t phymask, uint64_t wwid); 363 364 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, 365 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd); 366 367 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 368 uint16_t *handle, mptsas_target_t **pptgt); 369 static void mptsas_update_phymask(mptsas_t *mpt); 370 371 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_enclosure_t *mep, 372 uint16_t idx); 373 static int mptsas_send_sep(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx, 374 uint32_t *status, uint8_t cmd); 375 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev, 376 mptsas_phymask_t *phymask); 377 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, 378 mptsas_phymask_t phymask); 379 380 381 /* 382 * Enumeration / DR functions 383 */ 384 static void mptsas_config_all(dev_info_t *pdip); 385 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 386 dev_info_t **lundip); 387 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 388 dev_info_t **lundip); 389 390 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt); 391 static int mptsas_offline_target(dev_info_t *pdip, char *name); 392 393 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target, 394 dev_info_t **dip); 395 396 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt); 397 static int mptsas_probe_lun(dev_info_t *pdip, int lun, 398 dev_info_t **dip, mptsas_target_t *ptgt); 399 400 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 401 dev_info_t **dip, mptsas_target_t *ptgt, int lun); 402 403 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 404 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun); 405 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 406 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, 407 int lun); 408 409 static void mptsas_offline_missed_luns(dev_info_t *pdip, 410 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt); 411 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 412 mdi_pathinfo_t *rpip, uint_t flags); 413 414 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, 415 dev_info_t **smp_dip); 416 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 417 uint_t flags); 418 419 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, 420 int mode, int *rval); 421 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, 422 int mode, int *rval); 423 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, 424 int mode, int *rval); 425 static void mptsas_record_event(void *args); 426 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, 427 int mode); 428 429 mptsas_target_t *mptsas_tgt_alloc(refhash_t *, uint16_t, uint64_t, 430 uint32_t, mptsas_phymask_t, uint8_t); 431 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *); 432 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 433 dev_info_t **smp_dip); 434 435 /* 436 * Power management functions 437 */ 438 static int mptsas_get_pci_cap(mptsas_t *mpt); 439 static int mptsas_init_pm(mptsas_t *mpt); 440 441 /* 442 * MPT MSI tunable: 443 * 444 * By default MSI is enabled on all supported platforms. 445 */ 446 boolean_t mptsas_enable_msi = B_TRUE; 447 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE; 448 449 /* 450 * Global switch for use of MPI2.5 FAST PATH. 451 * We don't really know what FAST PATH actually does, so if it is suspected 452 * to cause problems it can be turned off by setting this variable to B_FALSE. 453 */ 454 boolean_t mptsas_use_fastpath = B_TRUE; 455 456 static int mptsas_register_intrs(mptsas_t *); 457 static void mptsas_unregister_intrs(mptsas_t *); 458 static int mptsas_add_intrs(mptsas_t *, int); 459 static void mptsas_rem_intrs(mptsas_t *); 460 461 /* 462 * FMA Prototypes 463 */ 464 static void mptsas_fm_init(mptsas_t *mpt); 465 static void mptsas_fm_fini(mptsas_t *mpt); 466 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *); 467 468 extern pri_t minclsyspri, maxclsyspri; 469 470 /* 471 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is 472 * under this device that the paths to a physical device are created when 473 * MPxIO is used. 474 */ 475 extern dev_info_t *scsi_vhci_dip; 476 477 /* 478 * Tunable timeout value for Inquiry VPD page 0x83 479 * By default the value is 30 seconds. 480 */ 481 int mptsas_inq83_retry_timeout = 30; 482 483 /* 484 * This is used to allocate memory for message frame storage, not for 485 * data I/O DMA. All message frames must be stored in the first 4G of 486 * physical memory. 487 */ 488 ddi_dma_attr_t mptsas_dma_attrs = { 489 DMA_ATTR_V0, /* attribute layout version */ 490 0x0ull, /* address low - should be 0 (longlong) */ 491 0xffffffffull, /* address high - 32-bit max range */ 492 0x00ffffffull, /* count max - max DMA object size */ 493 4, /* allocation alignment requirements */ 494 0x78, /* burstsizes - binary encoded values */ 495 1, /* minxfer - gran. of DMA engine */ 496 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 497 0xffffffffull, /* max segment size (DMA boundary) */ 498 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 499 512, /* granularity - device transfer size */ 500 0 /* flags, set to 0 */ 501 }; 502 503 /* 504 * This is used for data I/O DMA memory allocation. (full 64-bit DMA 505 * physical addresses are supported.) 506 */ 507 ddi_dma_attr_t mptsas_dma_attrs64 = { 508 DMA_ATTR_V0, /* attribute layout version */ 509 0x0ull, /* address low - should be 0 (longlong) */ 510 0xffffffffffffffffull, /* address high - 64-bit max */ 511 0x00ffffffull, /* count max - max DMA object size */ 512 4, /* allocation alignment requirements */ 513 0x78, /* burstsizes - binary encoded values */ 514 1, /* minxfer - gran. of DMA engine */ 515 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 516 0xffffffffull, /* max segment size (DMA boundary) */ 517 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 518 512, /* granularity - device transfer size */ 519 0 /* flags, set to 0 */ 520 }; 521 522 ddi_device_acc_attr_t mptsas_dev_attr = { 523 DDI_DEVICE_ATTR_V1, 524 DDI_STRUCTURE_LE_ACC, 525 DDI_STRICTORDER_ACC, 526 DDI_DEFAULT_ACC 527 }; 528 529 static struct cb_ops mptsas_cb_ops = { 530 scsi_hba_open, /* open */ 531 scsi_hba_close, /* close */ 532 nodev, /* strategy */ 533 nodev, /* print */ 534 nodev, /* dump */ 535 nodev, /* read */ 536 nodev, /* write */ 537 mptsas_ioctl, /* ioctl */ 538 nodev, /* devmap */ 539 nodev, /* mmap */ 540 nodev, /* segmap */ 541 nochpoll, /* chpoll */ 542 ddi_prop_op, /* cb_prop_op */ 543 NULL, /* streamtab */ 544 D_MP, /* cb_flag */ 545 CB_REV, /* rev */ 546 nodev, /* aread */ 547 nodev /* awrite */ 548 }; 549 550 static struct dev_ops mptsas_ops = { 551 DEVO_REV, /* devo_rev, */ 552 0, /* refcnt */ 553 ddi_no_info, /* info */ 554 nulldev, /* identify */ 555 nulldev, /* probe */ 556 mptsas_attach, /* attach */ 557 mptsas_detach, /* detach */ 558 #ifdef __sparc 559 mptsas_reset, 560 #else 561 nodev, /* reset */ 562 #endif /* __sparc */ 563 &mptsas_cb_ops, /* driver operations */ 564 NULL, /* bus operations */ 565 mptsas_power, /* power management */ 566 #ifdef __sparc 567 ddi_quiesce_not_needed 568 #else 569 mptsas_quiesce /* quiesce */ 570 #endif /* __sparc */ 571 }; 572 573 static ddi_ufm_ops_t mptsas_ufm_ops = { 574 NULL, 575 mptsas_ufm_fill_image, 576 mptsas_ufm_fill_slot, 577 mptsas_ufm_getcaps 578 }; 579 580 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24" 581 582 static struct modldrv modldrv = { 583 &mod_driverops, /* Type of module. This one is a driver */ 584 MPTSAS_MOD_STRING, /* Name of the module. */ 585 &mptsas_ops, /* driver ops */ 586 }; 587 588 static struct modlinkage modlinkage = { 589 MODREV_1, &modldrv, NULL 590 }; 591 #define TARGET_PROP "target" 592 #define LUN_PROP "lun" 593 #define LUN64_PROP "lun64" 594 #define SAS_PROP "sas-mpt" 595 #define MDI_GUID "wwn" 596 #define NDI_GUID "guid" 597 #define MPTSAS_DEV_GONE "mptsas_dev_gone" 598 599 /* 600 * Local static data 601 */ 602 #if defined(MPTSAS_DEBUG) 603 /* 604 * Flags to indicate which debug messages are to be printed and which go to the 605 * debug log ring buffer. Default is to not print anything, and to log 606 * everything except the watchsubr() output which normally happens every second. 607 */ 608 uint32_t mptsas_debugprt_flags = 0x0; 609 uint32_t mptsas_debuglog_flags = ~(1U << 30); 610 #endif /* defined(MPTSAS_DEBUG) */ 611 uint32_t mptsas_debug_resets = 0; 612 613 static kmutex_t mptsas_global_mutex; 614 static void *mptsas_state; /* soft state ptr */ 615 static krwlock_t mptsas_global_rwlock; 616 617 static kmutex_t mptsas_log_mutex; 618 static char mptsas_log_buf[256]; 619 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf)) 620 621 static mptsas_t *mptsas_head, *mptsas_tail; 622 static clock_t mptsas_scsi_watchdog_tick; 623 static clock_t mptsas_tick; 624 static timeout_id_t mptsas_reset_watch; 625 static timeout_id_t mptsas_timeout_id; 626 static int mptsas_timeouts_enabled = 0; 627 628 /* 629 * Default length for extended auto request sense buffers. 630 * All sense buffers need to be under the same alloc because there 631 * is only one common top 32bits (of 64bits) address register. 632 * Most requests only require 32 bytes, but some request >256. 633 * We use rmalloc()/rmfree() on this additional memory to manage the 634 * "extended" requests. 635 */ 636 int mptsas_extreq_sense_bufsize = 256*64; 637 638 /* 639 * We believe that all software resrictions of having to run with DMA 640 * attributes to limit allocation to the first 4G are removed. 641 * However, this flag remains to enable quick switchback should suspicious 642 * problems emerge. 643 * Note that scsi_alloc_consistent_buf() does still adhere to allocating 644 * 32 bit addressable memory, but we can cope if that is changed now. 645 */ 646 int mptsas_use_64bit_msgaddr = 1; 647 648 /* 649 * warlock directives 650 */ 651 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \ 652 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status)) 653 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt)) 654 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address)) 655 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private)) 656 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private)) 657 658 /* 659 * SM - HBA statics 660 */ 661 char *mptsas_driver_rev = MPTSAS_MOD_STRING; 662 663 #ifdef MPTSAS_DEBUG 664 void debug_enter(char *); 665 #endif 666 667 /* 668 * Notes: 669 * - scsi_hba_init(9F) initializes SCSI HBA modules 670 * - must call scsi_hba_fini(9F) if modload() fails 671 */ 672 int 673 _init(void) 674 { 675 int status; 676 /* CONSTCOND */ 677 ASSERT(NO_COMPETING_THREADS); 678 679 NDBG0(("_init")); 680 681 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE, 682 MPTSAS_INITIAL_SOFT_SPACE); 683 if (status != 0) { 684 return (status); 685 } 686 687 if ((status = scsi_hba_init(&modlinkage)) != 0) { 688 ddi_soft_state_fini(&mptsas_state); 689 return (status); 690 } 691 692 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL); 693 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL); 694 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL); 695 696 if ((status = mod_install(&modlinkage)) != 0) { 697 mutex_destroy(&mptsas_log_mutex); 698 rw_destroy(&mptsas_global_rwlock); 699 mutex_destroy(&mptsas_global_mutex); 700 ddi_soft_state_fini(&mptsas_state); 701 scsi_hba_fini(&modlinkage); 702 } 703 704 return (status); 705 } 706 707 /* 708 * Notes: 709 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules 710 */ 711 int 712 _fini(void) 713 { 714 int status; 715 /* CONSTCOND */ 716 ASSERT(NO_COMPETING_THREADS); 717 718 NDBG0(("_fini")); 719 720 if ((status = mod_remove(&modlinkage)) == 0) { 721 ddi_soft_state_fini(&mptsas_state); 722 scsi_hba_fini(&modlinkage); 723 mutex_destroy(&mptsas_global_mutex); 724 rw_destroy(&mptsas_global_rwlock); 725 mutex_destroy(&mptsas_log_mutex); 726 } 727 return (status); 728 } 729 730 /* 731 * The loadable-module _info(9E) entry point 732 */ 733 int 734 _info(struct modinfo *modinfop) 735 { 736 /* CONSTCOND */ 737 ASSERT(NO_COMPETING_THREADS); 738 NDBG0(("mptsas _info")); 739 740 return (mod_info(&modlinkage, modinfop)); 741 } 742 743 static int 744 mptsas_target_eval_devhdl(const void *op, void *arg) 745 { 746 uint16_t dh = *(uint16_t *)arg; 747 const mptsas_target_t *tp = op; 748 749 return ((int)tp->m_devhdl - (int)dh); 750 } 751 752 static int 753 mptsas_target_eval_nowwn(const void *op, void *arg) 754 { 755 uint8_t phy = *(uint8_t *)arg; 756 const mptsas_target_t *tp = op; 757 758 if (tp->m_addr.mta_wwn != 0) 759 return (-1); 760 761 return ((int)tp->m_phynum - (int)phy); 762 } 763 764 static int 765 mptsas_smp_eval_devhdl(const void *op, void *arg) 766 { 767 uint16_t dh = *(uint16_t *)arg; 768 const mptsas_smp_t *sp = op; 769 770 return ((int)sp->m_devhdl - (int)dh); 771 } 772 773 static uint64_t 774 mptsas_target_addr_hash(const void *tp) 775 { 776 const mptsas_target_addr_t *tap = tp; 777 778 return ((tap->mta_wwn & 0xffffffffffffULL) | 779 ((uint64_t)tap->mta_phymask << 48)); 780 } 781 782 static int 783 mptsas_target_addr_cmp(const void *a, const void *b) 784 { 785 const mptsas_target_addr_t *aap = a; 786 const mptsas_target_addr_t *bap = b; 787 788 if (aap->mta_wwn < bap->mta_wwn) 789 return (-1); 790 if (aap->mta_wwn > bap->mta_wwn) 791 return (1); 792 return ((int)bap->mta_phymask - (int)aap->mta_phymask); 793 } 794 795 static uint64_t 796 mptsas_tmp_target_hash(const void *tp) 797 { 798 return ((uint64_t)(uintptr_t)tp); 799 } 800 801 static int 802 mptsas_tmp_target_cmp(const void *a, const void *b) 803 { 804 if (a > b) 805 return (1); 806 if (b < a) 807 return (-1); 808 809 return (0); 810 } 811 812 static void 813 mptsas_target_free(void *op) 814 { 815 kmem_free(op, sizeof (mptsas_target_t)); 816 } 817 818 static void 819 mptsas_smp_free(void *op) 820 { 821 kmem_free(op, sizeof (mptsas_smp_t)); 822 } 823 824 static void 825 mptsas_destroy_hashes(mptsas_t *mpt) 826 { 827 mptsas_target_t *tp; 828 mptsas_smp_t *sp; 829 830 for (tp = refhash_first(mpt->m_targets); tp != NULL; 831 tp = refhash_next(mpt->m_targets, tp)) { 832 refhash_remove(mpt->m_targets, tp); 833 } 834 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 835 sp = refhash_next(mpt->m_smp_targets, sp)) { 836 refhash_remove(mpt->m_smp_targets, sp); 837 } 838 refhash_destroy(mpt->m_tmp_targets); 839 refhash_destroy(mpt->m_targets); 840 refhash_destroy(mpt->m_smp_targets); 841 mpt->m_targets = NULL; 842 mpt->m_smp_targets = NULL; 843 } 844 845 static int 846 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 847 { 848 dev_info_t *pdip; 849 mptsas_t *mpt; 850 scsi_hba_tran_t *hba_tran; 851 char *iport = NULL; 852 char phymask[MPTSAS_MAX_PHYS]; 853 mptsas_phymask_t phy_mask = 0; 854 int dynamic_port = 0; 855 uint32_t page_address; 856 char initiator_wwnstr[MPTSAS_WWN_STRLEN]; 857 int rval = DDI_FAILURE; 858 int i = 0; 859 uint8_t numphys = 0; 860 uint8_t phy_id; 861 uint8_t phy_port = 0; 862 uint16_t attached_devhdl = 0; 863 uint32_t dev_info; 864 uint64_t attached_sas_wwn; 865 uint16_t dev_hdl; 866 uint16_t pdev_hdl; 867 uint16_t bay_num, enclosure, io_flags; 868 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 869 870 /* CONSTCOND */ 871 ASSERT(NO_COMPETING_THREADS); 872 873 switch (cmd) { 874 case DDI_ATTACH: 875 break; 876 877 case DDI_RESUME: 878 /* 879 * If this a scsi-iport node, nothing to do here. 880 */ 881 return (DDI_SUCCESS); 882 883 default: 884 return (DDI_FAILURE); 885 } 886 887 pdip = ddi_get_parent(dip); 888 889 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) == 890 NULL) { 891 cmn_err(CE_WARN, "Failed attach iport because fail to " 892 "get tran vector for the HBA node"); 893 return (DDI_FAILURE); 894 } 895 896 mpt = TRAN2MPT(hba_tran); 897 ASSERT(mpt != NULL); 898 if (mpt == NULL) 899 return (DDI_FAILURE); 900 901 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == 902 NULL) { 903 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to " 904 "get tran vector for the iport node"); 905 return (DDI_FAILURE); 906 } 907 908 /* 909 * Overwrite parent's tran_hba_private to iport's tran vector 910 */ 911 hba_tran->tran_hba_private = mpt; 912 913 ddi_report_dev(dip); 914 915 /* 916 * Get SAS address for initiator port according dev_handle 917 */ 918 iport = ddi_get_name_addr(dip); 919 if (iport && strncmp(iport, "v0", 2) == 0) { 920 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 921 MPTSAS_VIRTUAL_PORT, 1) != 922 DDI_PROP_SUCCESS) { 923 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 924 MPTSAS_VIRTUAL_PORT); 925 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 926 "prop update failed"); 927 return (DDI_FAILURE); 928 } 929 return (DDI_SUCCESS); 930 } 931 932 mutex_enter(&mpt->m_mutex); 933 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 934 bzero(phymask, sizeof (phymask)); 935 (void) sprintf(phymask, 936 "%x", mpt->m_phy_info[i].phy_mask); 937 if (strcmp(phymask, iport) == 0) { 938 break; 939 } 940 } 941 942 if (i == MPTSAS_MAX_PHYS) { 943 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port" 944 "seems not exist", iport); 945 mutex_exit(&mpt->m_mutex); 946 return (DDI_FAILURE); 947 } 948 949 phy_mask = mpt->m_phy_info[i].phy_mask; 950 951 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION) 952 dynamic_port = 1; 953 else 954 dynamic_port = 0; 955 956 /* 957 * Update PHY info for smhba 958 */ 959 if (mptsas_smhba_phy_init(mpt)) { 960 mutex_exit(&mpt->m_mutex); 961 mptsas_log(mpt, CE_WARN, "mptsas phy update " 962 "failed"); 963 return (DDI_FAILURE); 964 } 965 966 mutex_exit(&mpt->m_mutex); 967 968 numphys = 0; 969 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 970 if ((phy_mask >> i) & 0x01) { 971 numphys++; 972 } 973 } 974 975 bzero(initiator_wwnstr, sizeof (initiator_wwnstr)); 976 (void) sprintf(initiator_wwnstr, "w%016"PRIx64, 977 mpt->un.m_base_wwid); 978 979 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 980 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) != 981 DDI_PROP_SUCCESS) { 982 (void) ddi_prop_remove(DDI_DEV_T_NONE, 983 dip, SCSI_ADDR_PROP_INITIATOR_PORT); 984 mptsas_log(mpt, CE_WARN, "mptsas Initiator port " 985 "prop update failed"); 986 return (DDI_FAILURE); 987 } 988 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 989 MPTSAS_NUM_PHYS, numphys) != 990 DDI_PROP_SUCCESS) { 991 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS); 992 return (DDI_FAILURE); 993 } 994 995 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 996 "phymask", phy_mask) != 997 DDI_PROP_SUCCESS) { 998 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask"); 999 mptsas_log(mpt, CE_WARN, "mptsas phy mask " 1000 "prop update failed"); 1001 return (DDI_FAILURE); 1002 } 1003 1004 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 1005 "dynamic-port", dynamic_port) != 1006 DDI_PROP_SUCCESS) { 1007 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port"); 1008 mptsas_log(mpt, CE_WARN, "mptsas dynamic port " 1009 "prop update failed"); 1010 return (DDI_FAILURE); 1011 } 1012 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 1013 MPTSAS_VIRTUAL_PORT, 0) != 1014 DDI_PROP_SUCCESS) { 1015 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 1016 MPTSAS_VIRTUAL_PORT); 1017 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 1018 "prop update failed"); 1019 return (DDI_FAILURE); 1020 } 1021 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask, 1022 &attached_devhdl); 1023 1024 mutex_enter(&mpt->m_mutex); 1025 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 1026 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl; 1027 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 1028 &attached_sas_wwn, &dev_info, &phy_port, &phy_id, 1029 &pdev_hdl, &bay_num, &enclosure, &io_flags); 1030 if (rval != DDI_SUCCESS) { 1031 mptsas_log(mpt, CE_WARN, 1032 "Failed to get device page0 for handle:%d", 1033 attached_devhdl); 1034 mutex_exit(&mpt->m_mutex); 1035 return (DDI_FAILURE); 1036 } 1037 1038 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1039 bzero(phymask, sizeof (phymask)); 1040 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask); 1041 if (strcmp(phymask, iport) == 0) { 1042 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0], 1043 "%x", 1044 mpt->m_phy_info[i].phy_mask); 1045 } 1046 } 1047 mutex_exit(&mpt->m_mutex); 1048 1049 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 1050 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 1051 attached_sas_wwn); 1052 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 1053 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 1054 DDI_PROP_SUCCESS) { 1055 (void) ddi_prop_remove(DDI_DEV_T_NONE, 1056 dip, SCSI_ADDR_PROP_ATTACHED_PORT); 1057 return (DDI_FAILURE); 1058 } 1059 1060 /* Create kstats for each phy on this iport */ 1061 1062 mptsas_create_phy_stats(mpt, iport, dip); 1063 1064 /* 1065 * register sas hba iport with mdi (MPxIO/vhci) 1066 */ 1067 if (mdi_phci_register(MDI_HCI_CLASS_SCSI, 1068 dip, 0) == MDI_SUCCESS) { 1069 mpt->m_mpxio_enable = TRUE; 1070 } 1071 return (DDI_SUCCESS); 1072 } 1073 1074 /* 1075 * Notes: 1076 * Set up all device state and allocate data structures, 1077 * mutexes, condition variables, etc. for device operation. 1078 * Add interrupts needed. 1079 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE. 1080 */ 1081 static int 1082 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 1083 { 1084 mptsas_t *mpt = NULL; 1085 int instance, i, j; 1086 int doneq_thread_num; 1087 char intr_added = 0; 1088 char map_setup = 0; 1089 char config_setup = 0; 1090 char hba_attach_setup = 0; 1091 char smp_attach_setup = 0; 1092 char enc_attach_setup = 0; 1093 char mutex_init_done = 0; 1094 char event_taskq_create = 0; 1095 char dr_taskq_create = 0; 1096 char doneq_thread_create = 0; 1097 char added_watchdog = 0; 1098 scsi_hba_tran_t *hba_tran; 1099 uint_t mem_bar = MEM_SPACE; 1100 int rval = DDI_FAILURE; 1101 1102 /* CONSTCOND */ 1103 ASSERT(NO_COMPETING_THREADS); 1104 1105 if (scsi_hba_iport_unit_address(dip)) { 1106 return (mptsas_iport_attach(dip, cmd)); 1107 } 1108 1109 switch (cmd) { 1110 case DDI_ATTACH: 1111 break; 1112 1113 case DDI_RESUME: 1114 if ((hba_tran = ddi_get_driver_private(dip)) == NULL) 1115 return (DDI_FAILURE); 1116 1117 mpt = TRAN2MPT(hba_tran); 1118 1119 if (!mpt) { 1120 return (DDI_FAILURE); 1121 } 1122 1123 /* 1124 * Reset hardware and softc to "no outstanding commands" 1125 * Note that a check condition can result on first command 1126 * to a target. 1127 */ 1128 mutex_enter(&mpt->m_mutex); 1129 1130 /* 1131 * raise power. 1132 */ 1133 if (mpt->m_options & MPTSAS_OPT_PM) { 1134 mutex_exit(&mpt->m_mutex); 1135 (void) pm_busy_component(dip, 0); 1136 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0); 1137 if (rval == DDI_SUCCESS) { 1138 mutex_enter(&mpt->m_mutex); 1139 } else { 1140 /* 1141 * The pm_raise_power() call above failed, 1142 * and that can only occur if we were unable 1143 * to reset the hardware. This is probably 1144 * due to unhealty hardware, and because 1145 * important filesystems(such as the root 1146 * filesystem) could be on the attached disks, 1147 * it would not be a good idea to continue, 1148 * as we won't be entirely certain we are 1149 * writing correct data. So we panic() here 1150 * to not only prevent possible data corruption, 1151 * but to give developers or end users a hope 1152 * of identifying and correcting any problems. 1153 */ 1154 fm_panic("mptsas could not reset hardware " 1155 "during resume"); 1156 } 1157 } 1158 1159 mpt->m_suspended = 0; 1160 1161 /* 1162 * Reinitialize ioc 1163 */ 1164 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1165 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 1166 mutex_exit(&mpt->m_mutex); 1167 if (mpt->m_options & MPTSAS_OPT_PM) { 1168 (void) pm_idle_component(dip, 0); 1169 } 1170 fm_panic("mptsas init chip fail during resume"); 1171 } 1172 /* 1173 * mptsas_update_driver_data needs interrupts so enable them 1174 * first. 1175 */ 1176 MPTSAS_ENABLE_INTR(mpt); 1177 mptsas_update_driver_data(mpt); 1178 1179 /* start requests, if possible */ 1180 mptsas_restart_hba(mpt); 1181 1182 mutex_exit(&mpt->m_mutex); 1183 1184 /* 1185 * Restart watch thread 1186 */ 1187 mutex_enter(&mptsas_global_mutex); 1188 if (mptsas_timeout_id == 0) { 1189 mptsas_timeout_id = timeout(mptsas_watch, NULL, 1190 mptsas_tick); 1191 mptsas_timeouts_enabled = 1; 1192 } 1193 mutex_exit(&mptsas_global_mutex); 1194 1195 /* report idle status to pm framework */ 1196 if (mpt->m_options & MPTSAS_OPT_PM) { 1197 (void) pm_idle_component(dip, 0); 1198 } 1199 1200 return (DDI_SUCCESS); 1201 1202 default: 1203 return (DDI_FAILURE); 1204 1205 } 1206 1207 instance = ddi_get_instance(dip); 1208 1209 /* 1210 * Allocate softc information. 1211 */ 1212 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) { 1213 mptsas_log(NULL, CE_WARN, 1214 "mptsas%d: cannot allocate soft state", instance); 1215 goto fail; 1216 } 1217 1218 mpt = ddi_get_soft_state(mptsas_state, instance); 1219 1220 if (mpt == NULL) { 1221 mptsas_log(NULL, CE_WARN, 1222 "mptsas%d: cannot get soft state", instance); 1223 goto fail; 1224 } 1225 1226 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */ 1227 scsi_size_clean(dip); 1228 1229 mpt->m_dip = dip; 1230 mpt->m_instance = instance; 1231 1232 /* Make a per-instance copy of the structures */ 1233 mpt->m_io_dma_attr = mptsas_dma_attrs64; 1234 if (mptsas_use_64bit_msgaddr) { 1235 mpt->m_msg_dma_attr = mptsas_dma_attrs64; 1236 } else { 1237 mpt->m_msg_dma_attr = mptsas_dma_attrs; 1238 } 1239 mpt->m_reg_acc_attr = mptsas_dev_attr; 1240 mpt->m_dev_acc_attr = mptsas_dev_attr; 1241 1242 /* 1243 * Size of individual request sense buffer 1244 */ 1245 mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE; 1246 1247 /* 1248 * Initialize FMA 1249 */ 1250 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip, 1251 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 1252 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 1253 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 1254 1255 mptsas_fm_init(mpt); 1256 1257 /* 1258 * Initialize us with the UFM subsystem 1259 */ 1260 if (ddi_ufm_init(dip, DDI_UFM_CURRENT_VERSION, &mptsas_ufm_ops, 1261 &mpt->m_ufmh, mpt) != 0) { 1262 mptsas_log(mpt, CE_WARN, "failed to initialize UFM subsystem"); 1263 goto fail; 1264 } 1265 1266 if (mptsas_alloc_handshake_msg(mpt, 1267 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) { 1268 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg."); 1269 goto fail; 1270 } 1271 1272 /* 1273 * Setup configuration space 1274 */ 1275 if (mptsas_config_space_init(mpt) == FALSE) { 1276 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed"); 1277 goto fail; 1278 } 1279 config_setup++; 1280 1281 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg, 1282 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) { 1283 mptsas_log(mpt, CE_WARN, "map setup failed"); 1284 goto fail; 1285 } 1286 map_setup++; 1287 1288 /* 1289 * A taskq is created for dealing with the event handler 1290 */ 1291 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq", 1292 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1293 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed"); 1294 goto fail; 1295 } 1296 event_taskq_create++; 1297 1298 /* 1299 * A taskq is created for dealing with dr events 1300 */ 1301 if ((mpt->m_dr_taskq = ddi_taskq_create(dip, 1302 "mptsas_dr_taskq", 1303 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1304 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery " 1305 "failed"); 1306 goto fail; 1307 } 1308 dr_taskq_create++; 1309 1310 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1311 0, "mptsas_doneq_thread_threshold_prop", 10); 1312 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1313 0, "mptsas_doneq_length_threshold_prop", 8); 1314 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1315 0, "mptsas_doneq_thread_n_prop", 8); 1316 1317 if (mpt->m_doneq_thread_n) { 1318 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL); 1319 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL); 1320 1321 mutex_enter(&mpt->m_doneq_mutex); 1322 mpt->m_doneq_thread_id = 1323 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t) 1324 * mpt->m_doneq_thread_n, KM_SLEEP); 1325 1326 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1327 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL, 1328 CV_DRIVER, NULL); 1329 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL, 1330 MUTEX_DRIVER, NULL); 1331 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1332 mpt->m_doneq_thread_id[j].flag |= 1333 MPTSAS_DONEQ_THREAD_ACTIVE; 1334 mpt->m_doneq_thread_id[j].arg.mpt = mpt; 1335 mpt->m_doneq_thread_id[j].arg.t = j; 1336 mpt->m_doneq_thread_id[j].threadp = 1337 thread_create(NULL, 0, mptsas_doneq_thread, 1338 &mpt->m_doneq_thread_id[j].arg, 1339 0, &p0, TS_RUN, minclsyspri); 1340 mpt->m_doneq_thread_id[j].donetail = 1341 &mpt->m_doneq_thread_id[j].doneq; 1342 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1343 } 1344 mutex_exit(&mpt->m_doneq_mutex); 1345 doneq_thread_create++; 1346 } 1347 1348 /* 1349 * Disable hardware interrupt since we're not ready to 1350 * handle it yet. 1351 */ 1352 MPTSAS_DISABLE_INTR(mpt); 1353 if (mptsas_register_intrs(mpt) == FALSE) 1354 goto fail; 1355 intr_added++; 1356 1357 /* Initialize mutex used in interrupt handler */ 1358 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, 1359 DDI_INTR_PRI(mpt->m_intr_pri)); 1360 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL); 1361 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER, 1362 DDI_INTR_PRI(mpt->m_intr_pri)); 1363 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1364 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex, 1365 NULL, MUTEX_DRIVER, 1366 DDI_INTR_PRI(mpt->m_intr_pri)); 1367 } 1368 1369 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL); 1370 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL); 1371 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL); 1372 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL); 1373 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL); 1374 cv_init(&mpt->m_extreq_sense_refcount_cv, NULL, CV_DRIVER, NULL); 1375 mutex_init_done++; 1376 1377 mutex_enter(&mpt->m_mutex); 1378 /* 1379 * Initialize power management component 1380 */ 1381 if (mpt->m_options & MPTSAS_OPT_PM) { 1382 if (mptsas_init_pm(mpt)) { 1383 mutex_exit(&mpt->m_mutex); 1384 mptsas_log(mpt, CE_WARN, "mptsas pm initialization " 1385 "failed"); 1386 goto fail; 1387 } 1388 } 1389 1390 /* 1391 * Initialize chip using Message Unit Reset, if allowed 1392 */ 1393 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1394 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) { 1395 mutex_exit(&mpt->m_mutex); 1396 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed"); 1397 goto fail; 1398 } 1399 1400 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT, 1401 mptsas_target_addr_hash, mptsas_target_addr_cmp, 1402 mptsas_target_free, sizeof (mptsas_target_t), 1403 offsetof(mptsas_target_t, m_link), 1404 offsetof(mptsas_target_t, m_addr), KM_SLEEP); 1405 1406 /* 1407 * The refhash for temporary targets uses the address of the target 1408 * struct itself as tag, so the tag offset is 0. See the implementation 1409 * of mptsas_tmp_target_hash() and mptsas_tmp_target_cmp(). 1410 */ 1411 mpt->m_tmp_targets = refhash_create(MPTSAS_TMP_TARGET_BUCKET_COUNT, 1412 mptsas_tmp_target_hash, mptsas_tmp_target_cmp, 1413 mptsas_target_free, sizeof (mptsas_target_t), 1414 offsetof(mptsas_target_t, m_link), 0, KM_SLEEP); 1415 1416 /* 1417 * Fill in the phy_info structure and get the base WWID 1418 */ 1419 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) { 1420 mptsas_log(mpt, CE_WARN, 1421 "mptsas_get_manufacture_page5 failed!"); 1422 goto fail; 1423 } 1424 1425 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) { 1426 mptsas_log(mpt, CE_WARN, 1427 "mptsas_get_sas_io_unit_page_hndshk failed!"); 1428 goto fail; 1429 } 1430 1431 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) { 1432 mptsas_log(mpt, CE_WARN, 1433 "mptsas_get_manufacture_page0 failed!"); 1434 goto fail; 1435 } 1436 1437 mutex_exit(&mpt->m_mutex); 1438 1439 /* 1440 * Register the iport for multiple port HBA 1441 */ 1442 mptsas_iport_register(mpt); 1443 1444 /* 1445 * initialize SCSI HBA transport structure 1446 */ 1447 if (mptsas_hba_setup(mpt) == FALSE) 1448 goto fail; 1449 hba_attach_setup++; 1450 1451 if (mptsas_smp_setup(mpt) == FALSE) 1452 goto fail; 1453 smp_attach_setup++; 1454 1455 if (mptsas_enc_setup(mpt) == FALSE) 1456 goto fail; 1457 enc_attach_setup++; 1458 1459 if (mptsas_cache_create(mpt) == FALSE) 1460 goto fail; 1461 1462 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 1463 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY); 1464 if (mpt->m_scsi_reset_delay == 0) { 1465 mptsas_log(mpt, CE_NOTE, 1466 "scsi_reset_delay of 0 is not recommended," 1467 " resetting to SCSI_DEFAULT_RESET_DELAY\n"); 1468 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY; 1469 } 1470 1471 /* 1472 * Initialize the wait and done FIFO queue 1473 */ 1474 mpt->m_donetail = &mpt->m_doneq; 1475 mpt->m_waitqtail = &mpt->m_waitq; 1476 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 1477 mpt->m_tx_draining = 0; 1478 1479 /* 1480 * ioc cmd queue initialize 1481 */ 1482 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq; 1483 mpt->m_dev_handle = 0xFFFF; 1484 1485 MPTSAS_ENABLE_INTR(mpt); 1486 1487 /* 1488 * enable event notification 1489 */ 1490 mutex_enter(&mpt->m_mutex); 1491 if (mptsas_ioc_enable_event_notification(mpt)) { 1492 mutex_exit(&mpt->m_mutex); 1493 goto fail; 1494 } 1495 mutex_exit(&mpt->m_mutex); 1496 1497 /* 1498 * used for mptsas_watch 1499 */ 1500 mptsas_list_add(mpt); 1501 1502 mutex_enter(&mptsas_global_mutex); 1503 if (mptsas_timeouts_enabled == 0) { 1504 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY, 1505 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK); 1506 1507 mptsas_tick = mptsas_scsi_watchdog_tick * 1508 drv_usectohz((clock_t)1000000); 1509 1510 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 1511 mptsas_timeouts_enabled = 1; 1512 } 1513 mutex_exit(&mptsas_global_mutex); 1514 added_watchdog++; 1515 1516 /* 1517 * Initialize PHY info for smhba. 1518 * This requires watchdog to be enabled otherwise if interrupts 1519 * don't work the system will hang. 1520 */ 1521 if (mptsas_smhba_setup(mpt)) { 1522 mptsas_log(mpt, CE_WARN, "mptsas phy initialization " 1523 "failed"); 1524 goto fail; 1525 } 1526 1527 /* Check all dma handles allocated in attach */ 1528 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) 1529 != DDI_SUCCESS) || 1530 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) 1531 != DDI_SUCCESS) || 1532 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) 1533 != DDI_SUCCESS) || 1534 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) 1535 != DDI_SUCCESS) || 1536 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) 1537 != DDI_SUCCESS) || 1538 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) 1539 != DDI_SUCCESS)) { 1540 goto fail; 1541 } 1542 1543 /* Check all acc handles allocated in attach */ 1544 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 1545 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) 1546 != DDI_SUCCESS) || 1547 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) 1548 != DDI_SUCCESS) || 1549 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) 1550 != DDI_SUCCESS) || 1551 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) 1552 != DDI_SUCCESS) || 1553 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) 1554 != DDI_SUCCESS) || 1555 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) 1556 != DDI_SUCCESS) || 1557 (mptsas_check_acc_handle(mpt->m_config_handle) 1558 != DDI_SUCCESS)) { 1559 goto fail; 1560 } 1561 1562 /* 1563 * After this point, we are not going to fail the attach. 1564 */ 1565 1566 /* Let the UFM susbsystem know we're ready to receive callbacks */ 1567 ddi_ufm_update(mpt->m_ufmh); 1568 1569 /* Print message of HBA present */ 1570 ddi_report_dev(dip); 1571 1572 /* report idle status to pm framework */ 1573 if (mpt->m_options & MPTSAS_OPT_PM) { 1574 (void) pm_idle_component(dip, 0); 1575 } 1576 1577 return (DDI_SUCCESS); 1578 1579 fail: 1580 mptsas_log(mpt, CE_WARN, "attach failed"); 1581 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 1582 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 1583 if (mpt) { 1584 /* deallocate in reverse order */ 1585 if (added_watchdog) { 1586 mptsas_list_del(mpt); 1587 mutex_enter(&mptsas_global_mutex); 1588 1589 if (mptsas_timeout_id && (mptsas_head == NULL)) { 1590 timeout_id_t tid = mptsas_timeout_id; 1591 mptsas_timeouts_enabled = 0; 1592 mptsas_timeout_id = 0; 1593 mutex_exit(&mptsas_global_mutex); 1594 (void) untimeout(tid); 1595 mutex_enter(&mptsas_global_mutex); 1596 } 1597 mutex_exit(&mptsas_global_mutex); 1598 } 1599 1600 mptsas_cache_destroy(mpt); 1601 1602 if (smp_attach_setup) { 1603 mptsas_smp_teardown(mpt); 1604 } 1605 if (enc_attach_setup) { 1606 mptsas_enc_teardown(mpt); 1607 } 1608 if (hba_attach_setup) { 1609 mptsas_hba_teardown(mpt); 1610 } 1611 1612 if (mpt->m_tmp_targets) 1613 refhash_destroy(mpt->m_tmp_targets); 1614 if (mpt->m_targets) 1615 refhash_destroy(mpt->m_targets); 1616 if (mpt->m_smp_targets) 1617 refhash_destroy(mpt->m_smp_targets); 1618 1619 if (mpt->m_active) { 1620 mptsas_free_active_slots(mpt); 1621 } 1622 if (intr_added) { 1623 mptsas_unregister_intrs(mpt); 1624 } 1625 1626 if (doneq_thread_create) { 1627 mutex_enter(&mpt->m_doneq_mutex); 1628 doneq_thread_num = mpt->m_doneq_thread_n; 1629 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1630 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1631 mpt->m_doneq_thread_id[j].flag &= 1632 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1633 cv_signal(&mpt->m_doneq_thread_id[j].cv); 1634 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1635 } 1636 while (mpt->m_doneq_thread_n) { 1637 cv_wait(&mpt->m_doneq_thread_cv, 1638 &mpt->m_doneq_mutex); 1639 } 1640 for (j = 0; j < doneq_thread_num; j++) { 1641 cv_destroy(&mpt->m_doneq_thread_id[j].cv); 1642 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex); 1643 } 1644 kmem_free(mpt->m_doneq_thread_id, 1645 sizeof (mptsas_doneq_thread_list_t) 1646 * doneq_thread_num); 1647 mutex_exit(&mpt->m_doneq_mutex); 1648 cv_destroy(&mpt->m_doneq_thread_cv); 1649 mutex_destroy(&mpt->m_doneq_mutex); 1650 } 1651 if (event_taskq_create) { 1652 ddi_taskq_destroy(mpt->m_event_taskq); 1653 } 1654 if (dr_taskq_create) { 1655 ddi_taskq_destroy(mpt->m_dr_taskq); 1656 } 1657 if (mutex_init_done) { 1658 mutex_destroy(&mpt->m_tx_waitq_mutex); 1659 mutex_destroy(&mpt->m_passthru_mutex); 1660 mutex_destroy(&mpt->m_mutex); 1661 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1662 mutex_destroy( 1663 &mpt->m_phy_info[i].smhba_info.phy_mutex); 1664 } 1665 cv_destroy(&mpt->m_cv); 1666 cv_destroy(&mpt->m_passthru_cv); 1667 cv_destroy(&mpt->m_fw_cv); 1668 cv_destroy(&mpt->m_config_cv); 1669 cv_destroy(&mpt->m_fw_diag_cv); 1670 cv_destroy(&mpt->m_extreq_sense_refcount_cv); 1671 } 1672 1673 if (map_setup) { 1674 mptsas_cfg_fini(mpt); 1675 } 1676 if (config_setup) { 1677 mptsas_config_space_fini(mpt); 1678 } 1679 mptsas_free_handshake_msg(mpt); 1680 mptsas_hba_fini(mpt); 1681 1682 mptsas_fm_fini(mpt); 1683 ddi_soft_state_free(mptsas_state, instance); 1684 ddi_prop_remove_all(dip); 1685 } 1686 return (DDI_FAILURE); 1687 } 1688 1689 static int 1690 mptsas_suspend(dev_info_t *devi) 1691 { 1692 mptsas_t *mpt, *g; 1693 scsi_hba_tran_t *tran; 1694 1695 if (scsi_hba_iport_unit_address(devi)) { 1696 return (DDI_SUCCESS); 1697 } 1698 1699 if ((tran = ddi_get_driver_private(devi)) == NULL) 1700 return (DDI_SUCCESS); 1701 1702 mpt = TRAN2MPT(tran); 1703 if (!mpt) { 1704 return (DDI_SUCCESS); 1705 } 1706 1707 mutex_enter(&mpt->m_mutex); 1708 1709 if (mpt->m_suspended++) { 1710 mutex_exit(&mpt->m_mutex); 1711 return (DDI_SUCCESS); 1712 } 1713 1714 /* 1715 * Cancel timeout threads for this mpt 1716 */ 1717 if (mpt->m_quiesce_timeid) { 1718 timeout_id_t tid = mpt->m_quiesce_timeid; 1719 mpt->m_quiesce_timeid = 0; 1720 mutex_exit(&mpt->m_mutex); 1721 (void) untimeout(tid); 1722 mutex_enter(&mpt->m_mutex); 1723 } 1724 1725 if (mpt->m_restart_cmd_timeid) { 1726 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1727 mpt->m_restart_cmd_timeid = 0; 1728 mutex_exit(&mpt->m_mutex); 1729 (void) untimeout(tid); 1730 mutex_enter(&mpt->m_mutex); 1731 } 1732 1733 mutex_exit(&mpt->m_mutex); 1734 1735 (void) pm_idle_component(mpt->m_dip, 0); 1736 1737 /* 1738 * Cancel watch threads if all mpts suspended 1739 */ 1740 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1741 for (g = mptsas_head; g != NULL; g = g->m_next) { 1742 if (!g->m_suspended) 1743 break; 1744 } 1745 rw_exit(&mptsas_global_rwlock); 1746 1747 mutex_enter(&mptsas_global_mutex); 1748 if (g == NULL) { 1749 timeout_id_t tid; 1750 1751 mptsas_timeouts_enabled = 0; 1752 if (mptsas_timeout_id) { 1753 tid = mptsas_timeout_id; 1754 mptsas_timeout_id = 0; 1755 mutex_exit(&mptsas_global_mutex); 1756 (void) untimeout(tid); 1757 mutex_enter(&mptsas_global_mutex); 1758 } 1759 if (mptsas_reset_watch) { 1760 tid = mptsas_reset_watch; 1761 mptsas_reset_watch = 0; 1762 mutex_exit(&mptsas_global_mutex); 1763 (void) untimeout(tid); 1764 mutex_enter(&mptsas_global_mutex); 1765 } 1766 } 1767 mutex_exit(&mptsas_global_mutex); 1768 1769 mutex_enter(&mpt->m_mutex); 1770 1771 /* 1772 * If this mpt is not in full power(PM_LEVEL_D0), just return. 1773 */ 1774 if ((mpt->m_options & MPTSAS_OPT_PM) && 1775 (mpt->m_power_level != PM_LEVEL_D0)) { 1776 mutex_exit(&mpt->m_mutex); 1777 return (DDI_SUCCESS); 1778 } 1779 1780 /* Disable HBA interrupts in hardware */ 1781 MPTSAS_DISABLE_INTR(mpt); 1782 /* 1783 * Send RAID action system shutdown to sync IR 1784 */ 1785 mptsas_raid_action_system_shutdown(mpt); 1786 1787 mutex_exit(&mpt->m_mutex); 1788 1789 /* drain the taskq */ 1790 ddi_taskq_wait(mpt->m_event_taskq); 1791 ddi_taskq_wait(mpt->m_dr_taskq); 1792 1793 return (DDI_SUCCESS); 1794 } 1795 1796 #ifdef __sparc 1797 /*ARGSUSED*/ 1798 static int 1799 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd) 1800 { 1801 mptsas_t *mpt; 1802 scsi_hba_tran_t *tran; 1803 1804 /* 1805 * If this call is for iport, just return. 1806 */ 1807 if (scsi_hba_iport_unit_address(devi)) 1808 return (DDI_SUCCESS); 1809 1810 if ((tran = ddi_get_driver_private(devi)) == NULL) 1811 return (DDI_SUCCESS); 1812 1813 if ((mpt = TRAN2MPT(tran)) == NULL) 1814 return (DDI_SUCCESS); 1815 1816 /* 1817 * Send RAID action system shutdown to sync IR. Disable HBA 1818 * interrupts in hardware first. 1819 */ 1820 MPTSAS_DISABLE_INTR(mpt); 1821 mptsas_raid_action_system_shutdown(mpt); 1822 1823 return (DDI_SUCCESS); 1824 } 1825 #else /* __sparc */ 1826 /* 1827 * quiesce(9E) entry point. 1828 * 1829 * This function is called when the system is single-threaded at high 1830 * PIL with preemption disabled. Therefore, this function must not be 1831 * blocked. 1832 * 1833 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 1834 * DDI_FAILURE indicates an error condition and should almost never happen. 1835 */ 1836 static int 1837 mptsas_quiesce(dev_info_t *devi) 1838 { 1839 mptsas_t *mpt; 1840 scsi_hba_tran_t *tran; 1841 1842 /* 1843 * If this call is for iport, just return. 1844 */ 1845 if (scsi_hba_iport_unit_address(devi)) 1846 return (DDI_SUCCESS); 1847 1848 if ((tran = ddi_get_driver_private(devi)) == NULL) 1849 return (DDI_SUCCESS); 1850 1851 if ((mpt = TRAN2MPT(tran)) == NULL) 1852 return (DDI_SUCCESS); 1853 1854 /* Disable HBA interrupts in hardware */ 1855 MPTSAS_DISABLE_INTR(mpt); 1856 /* Send RAID action system shutdonw to sync IR */ 1857 mptsas_raid_action_system_shutdown(mpt); 1858 1859 return (DDI_SUCCESS); 1860 } 1861 #endif /* __sparc */ 1862 1863 /* 1864 * detach(9E). Remove all device allocations and system resources; 1865 * disable device interrupts. 1866 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem. 1867 */ 1868 static int 1869 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 1870 { 1871 /* CONSTCOND */ 1872 ASSERT(NO_COMPETING_THREADS); 1873 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd)); 1874 1875 switch (cmd) { 1876 case DDI_DETACH: 1877 return (mptsas_do_detach(devi)); 1878 1879 case DDI_SUSPEND: 1880 return (mptsas_suspend(devi)); 1881 1882 default: 1883 return (DDI_FAILURE); 1884 } 1885 /* NOTREACHED */ 1886 } 1887 1888 static int 1889 mptsas_do_detach(dev_info_t *dip) 1890 { 1891 mptsas_t *mpt; 1892 scsi_hba_tran_t *tran; 1893 mdi_pathinfo_t *pip = NULL; 1894 int i; 1895 int doneq_thread_num = 0; 1896 1897 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip)); 1898 1899 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL) 1900 return (DDI_FAILURE); 1901 1902 mpt = TRAN2MPT(tran); 1903 if (!mpt) { 1904 return (DDI_FAILURE); 1905 } 1906 1907 ddi_ufm_fini(mpt->m_ufmh); 1908 1909 /* 1910 * Still have pathinfo child, should not detach mpt driver 1911 */ 1912 if (scsi_hba_iport_unit_address(dip)) { 1913 if (mpt->m_mpxio_enable) { 1914 /* 1915 * MPxIO enabled for the iport 1916 */ 1917 ndi_devi_enter(scsi_vhci_dip); 1918 ndi_devi_enter(dip); 1919 while ((pip = mdi_get_next_client_path(dip, NULL)) != 1920 NULL) { 1921 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) { 1922 continue; 1923 } 1924 ndi_devi_exit(dip); 1925 ndi_devi_exit(scsi_vhci_dip); 1926 NDBG12(("detach failed because of " 1927 "outstanding path info")); 1928 return (DDI_FAILURE); 1929 } 1930 ndi_devi_exit(dip); 1931 ndi_devi_exit(scsi_vhci_dip); 1932 (void) mdi_phci_unregister(dip, 0); 1933 } 1934 1935 ddi_prop_remove_all(dip); 1936 1937 return (DDI_SUCCESS); 1938 } 1939 1940 /* Make sure power level is D0 before accessing registers */ 1941 if (mpt->m_options & MPTSAS_OPT_PM) { 1942 (void) pm_busy_component(dip, 0); 1943 if (mpt->m_power_level != PM_LEVEL_D0) { 1944 if (pm_raise_power(dip, 0, PM_LEVEL_D0) != 1945 DDI_SUCCESS) { 1946 mptsas_log(mpt, CE_WARN, 1947 "mptsas%d: Raise power request failed.", 1948 mpt->m_instance); 1949 (void) pm_idle_component(dip, 0); 1950 return (DDI_FAILURE); 1951 } 1952 } 1953 } 1954 1955 /* 1956 * Send RAID action system shutdown to sync IR. After action, send a 1957 * Message Unit Reset. Since after that DMA resource will be freed, 1958 * set ioc to READY state will avoid HBA initiated DMA operation. 1959 */ 1960 mutex_enter(&mpt->m_mutex); 1961 MPTSAS_DISABLE_INTR(mpt); 1962 mptsas_raid_action_system_shutdown(mpt); 1963 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1964 (void) mptsas_ioc_reset(mpt, FALSE); 1965 mutex_exit(&mpt->m_mutex); 1966 mptsas_rem_intrs(mpt); 1967 ddi_taskq_destroy(mpt->m_event_taskq); 1968 ddi_taskq_destroy(mpt->m_dr_taskq); 1969 1970 if (mpt->m_doneq_thread_n) { 1971 mutex_enter(&mpt->m_doneq_mutex); 1972 doneq_thread_num = mpt->m_doneq_thread_n; 1973 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 1974 mutex_enter(&mpt->m_doneq_thread_id[i].mutex); 1975 mpt->m_doneq_thread_id[i].flag &= 1976 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1977 cv_signal(&mpt->m_doneq_thread_id[i].cv); 1978 mutex_exit(&mpt->m_doneq_thread_id[i].mutex); 1979 } 1980 while (mpt->m_doneq_thread_n) { 1981 cv_wait(&mpt->m_doneq_thread_cv, 1982 &mpt->m_doneq_mutex); 1983 } 1984 for (i = 0; i < doneq_thread_num; i++) { 1985 cv_destroy(&mpt->m_doneq_thread_id[i].cv); 1986 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex); 1987 } 1988 kmem_free(mpt->m_doneq_thread_id, 1989 sizeof (mptsas_doneq_thread_list_t) 1990 * doneq_thread_num); 1991 mutex_exit(&mpt->m_doneq_mutex); 1992 cv_destroy(&mpt->m_doneq_thread_cv); 1993 mutex_destroy(&mpt->m_doneq_mutex); 1994 } 1995 1996 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf); 1997 1998 mptsas_list_del(mpt); 1999 2000 /* 2001 * Cancel timeout threads for this mpt 2002 */ 2003 mutex_enter(&mpt->m_mutex); 2004 if (mpt->m_quiesce_timeid) { 2005 timeout_id_t tid = mpt->m_quiesce_timeid; 2006 mpt->m_quiesce_timeid = 0; 2007 mutex_exit(&mpt->m_mutex); 2008 (void) untimeout(tid); 2009 mutex_enter(&mpt->m_mutex); 2010 } 2011 2012 if (mpt->m_restart_cmd_timeid) { 2013 timeout_id_t tid = mpt->m_restart_cmd_timeid; 2014 mpt->m_restart_cmd_timeid = 0; 2015 mutex_exit(&mpt->m_mutex); 2016 (void) untimeout(tid); 2017 mutex_enter(&mpt->m_mutex); 2018 } 2019 2020 mutex_exit(&mpt->m_mutex); 2021 2022 /* 2023 * last mpt? ... if active, CANCEL watch threads. 2024 */ 2025 mutex_enter(&mptsas_global_mutex); 2026 if (mptsas_head == NULL) { 2027 timeout_id_t tid; 2028 /* 2029 * Clear mptsas_timeouts_enable so that the watch thread 2030 * gets restarted on DDI_ATTACH 2031 */ 2032 mptsas_timeouts_enabled = 0; 2033 if (mptsas_timeout_id) { 2034 tid = mptsas_timeout_id; 2035 mptsas_timeout_id = 0; 2036 mutex_exit(&mptsas_global_mutex); 2037 (void) untimeout(tid); 2038 mutex_enter(&mptsas_global_mutex); 2039 } 2040 if (mptsas_reset_watch) { 2041 tid = mptsas_reset_watch; 2042 mptsas_reset_watch = 0; 2043 mutex_exit(&mptsas_global_mutex); 2044 (void) untimeout(tid); 2045 mutex_enter(&mptsas_global_mutex); 2046 } 2047 } 2048 mutex_exit(&mptsas_global_mutex); 2049 2050 /* 2051 * Delete Phy stats 2052 */ 2053 mptsas_destroy_phy_stats(mpt); 2054 2055 mptsas_destroy_hashes(mpt); 2056 2057 /* 2058 * Delete nt_active. 2059 */ 2060 mutex_enter(&mpt->m_mutex); 2061 mptsas_free_active_slots(mpt); 2062 mutex_exit(&mpt->m_mutex); 2063 2064 /* deallocate everything that was allocated in mptsas_attach */ 2065 mptsas_cache_destroy(mpt); 2066 2067 mptsas_hba_fini(mpt); 2068 mptsas_cfg_fini(mpt); 2069 2070 /* Lower the power informing PM Framework */ 2071 if (mpt->m_options & MPTSAS_OPT_PM) { 2072 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS) 2073 mptsas_log(mpt, CE_WARN, 2074 "!mptsas%d: Lower power request failed " 2075 "during detach, ignoring.", 2076 mpt->m_instance); 2077 } 2078 2079 mutex_destroy(&mpt->m_tx_waitq_mutex); 2080 mutex_destroy(&mpt->m_passthru_mutex); 2081 mutex_destroy(&mpt->m_mutex); 2082 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 2083 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex); 2084 } 2085 cv_destroy(&mpt->m_cv); 2086 cv_destroy(&mpt->m_passthru_cv); 2087 cv_destroy(&mpt->m_fw_cv); 2088 cv_destroy(&mpt->m_config_cv); 2089 cv_destroy(&mpt->m_fw_diag_cv); 2090 cv_destroy(&mpt->m_extreq_sense_refcount_cv); 2091 2092 mptsas_smp_teardown(mpt); 2093 mptsas_enc_teardown(mpt); 2094 mptsas_hba_teardown(mpt); 2095 2096 mptsas_config_space_fini(mpt); 2097 2098 mptsas_free_handshake_msg(mpt); 2099 2100 mptsas_fm_fini(mpt); 2101 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip)); 2102 ddi_prop_remove_all(dip); 2103 2104 return (DDI_SUCCESS); 2105 } 2106 2107 static void 2108 mptsas_list_add(mptsas_t *mpt) 2109 { 2110 rw_enter(&mptsas_global_rwlock, RW_WRITER); 2111 2112 if (mptsas_head == NULL) { 2113 mptsas_head = mpt; 2114 } else { 2115 mptsas_tail->m_next = mpt; 2116 } 2117 mptsas_tail = mpt; 2118 rw_exit(&mptsas_global_rwlock); 2119 } 2120 2121 static void 2122 mptsas_list_del(mptsas_t *mpt) 2123 { 2124 mptsas_t *m; 2125 /* 2126 * Remove device instance from the global linked list 2127 */ 2128 rw_enter(&mptsas_global_rwlock, RW_WRITER); 2129 if (mptsas_head == mpt) { 2130 m = mptsas_head = mpt->m_next; 2131 } else { 2132 for (m = mptsas_head; m != NULL; m = m->m_next) { 2133 if (m->m_next == mpt) { 2134 m->m_next = mpt->m_next; 2135 break; 2136 } 2137 } 2138 if (m == NULL) { 2139 mptsas_log(mpt, CE_PANIC, "Not in softc list!"); 2140 } 2141 } 2142 2143 if (mptsas_tail == mpt) { 2144 mptsas_tail = m; 2145 } 2146 rw_exit(&mptsas_global_rwlock); 2147 } 2148 2149 static int 2150 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size) 2151 { 2152 ddi_dma_attr_t task_dma_attrs; 2153 2154 mpt->m_hshk_dma_size = 0; 2155 task_dma_attrs = mpt->m_msg_dma_attr; 2156 task_dma_attrs.dma_attr_sgllen = 1; 2157 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size); 2158 2159 /* allocate Task Management ddi_dma resources */ 2160 if (mptsas_dma_addr_create(mpt, task_dma_attrs, 2161 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp, 2162 alloc_size, NULL) == FALSE) { 2163 return (DDI_FAILURE); 2164 } 2165 mpt->m_hshk_dma_size = alloc_size; 2166 2167 return (DDI_SUCCESS); 2168 } 2169 2170 static void 2171 mptsas_free_handshake_msg(mptsas_t *mpt) 2172 { 2173 if (mpt->m_hshk_dma_size == 0) 2174 return; 2175 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl); 2176 mpt->m_hshk_dma_size = 0; 2177 } 2178 2179 static int 2180 mptsas_hba_setup(mptsas_t *mpt) 2181 { 2182 scsi_hba_tran_t *hba_tran; 2183 int tran_flags; 2184 2185 /* Allocate a transport structure */ 2186 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip, 2187 SCSI_HBA_CANSLEEP); 2188 ASSERT(mpt->m_tran != NULL); 2189 2190 hba_tran->tran_hba_private = mpt; 2191 hba_tran->tran_tgt_private = NULL; 2192 2193 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init; 2194 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free; 2195 2196 hba_tran->tran_start = mptsas_scsi_start; 2197 hba_tran->tran_reset = mptsas_scsi_reset; 2198 hba_tran->tran_abort = mptsas_scsi_abort; 2199 hba_tran->tran_getcap = mptsas_scsi_getcap; 2200 hba_tran->tran_setcap = mptsas_scsi_setcap; 2201 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt; 2202 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt; 2203 2204 hba_tran->tran_dmafree = mptsas_scsi_dmafree; 2205 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt; 2206 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify; 2207 2208 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr; 2209 hba_tran->tran_get_name = mptsas_get_name; 2210 2211 hba_tran->tran_quiesce = mptsas_scsi_quiesce; 2212 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce; 2213 hba_tran->tran_bus_reset = NULL; 2214 2215 hba_tran->tran_add_eventcall = NULL; 2216 hba_tran->tran_get_eventcookie = NULL; 2217 hba_tran->tran_post_event = NULL; 2218 hba_tran->tran_remove_eventcall = NULL; 2219 2220 hba_tran->tran_bus_config = mptsas_bus_config; 2221 2222 hba_tran->tran_interconnect_type = INTERCONNECT_SAS; 2223 2224 /* 2225 * All children of the HBA are iports. We need tran was cloned. 2226 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be 2227 * inherited to iport's tran vector. 2228 */ 2229 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE); 2230 2231 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr, 2232 hba_tran, tran_flags) != DDI_SUCCESS) { 2233 mptsas_log(mpt, CE_WARN, "hba attach setup failed"); 2234 scsi_hba_tran_free(hba_tran); 2235 mpt->m_tran = NULL; 2236 return (FALSE); 2237 } 2238 return (TRUE); 2239 } 2240 2241 static void 2242 mptsas_hba_teardown(mptsas_t *mpt) 2243 { 2244 (void) scsi_hba_detach(mpt->m_dip); 2245 if (mpt->m_tran != NULL) { 2246 scsi_hba_tran_free(mpt->m_tran); 2247 mpt->m_tran = NULL; 2248 } 2249 } 2250 2251 static void 2252 mptsas_iport_register(mptsas_t *mpt) 2253 { 2254 int i, j; 2255 mptsas_phymask_t mask = 0x0; 2256 /* 2257 * initial value of mask is 0 2258 */ 2259 mutex_enter(&mpt->m_mutex); 2260 for (i = 0; i < mpt->m_num_phys; i++) { 2261 mptsas_phymask_t phy_mask = 0x0; 2262 char phy_mask_name[MPTSAS_MAX_PHYS]; 2263 uint8_t current_port; 2264 2265 if (mpt->m_phy_info[i].attached_devhdl == 0) 2266 continue; 2267 2268 bzero(phy_mask_name, sizeof (phy_mask_name)); 2269 2270 current_port = mpt->m_phy_info[i].port_num; 2271 2272 if ((mask & (1 << i)) != 0) 2273 continue; 2274 2275 for (j = 0; j < mpt->m_num_phys; j++) { 2276 if (mpt->m_phy_info[j].attached_devhdl && 2277 (mpt->m_phy_info[j].port_num == current_port)) { 2278 phy_mask |= (1 << j); 2279 } 2280 } 2281 mask = mask | phy_mask; 2282 2283 for (j = 0; j < mpt->m_num_phys; j++) { 2284 if ((phy_mask >> j) & 0x01) { 2285 mpt->m_phy_info[j].phy_mask = phy_mask; 2286 } 2287 } 2288 2289 (void) sprintf(phy_mask_name, "%x", phy_mask); 2290 2291 mutex_exit(&mpt->m_mutex); 2292 /* 2293 * register a iport 2294 */ 2295 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 2296 mutex_enter(&mpt->m_mutex); 2297 } 2298 mutex_exit(&mpt->m_mutex); 2299 /* 2300 * register a virtual port for RAID volume always 2301 */ 2302 (void) scsi_hba_iport_register(mpt->m_dip, "v0"); 2303 2304 } 2305 2306 static int 2307 mptsas_smp_setup(mptsas_t *mpt) 2308 { 2309 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip); 2310 ASSERT(mpt->m_smptran != NULL); 2311 mpt->m_smptran->smp_tran_hba_private = mpt; 2312 mpt->m_smptran->smp_tran_start = mptsas_smp_start; 2313 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) { 2314 mptsas_log(mpt, CE_WARN, "smp attach setup failed"); 2315 smp_hba_tran_free(mpt->m_smptran); 2316 mpt->m_smptran = NULL; 2317 return (FALSE); 2318 } 2319 /* 2320 * Initialize smp hash table 2321 */ 2322 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT, 2323 mptsas_target_addr_hash, mptsas_target_addr_cmp, 2324 mptsas_smp_free, sizeof (mptsas_smp_t), 2325 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr), 2326 KM_SLEEP); 2327 mpt->m_smp_devhdl = 0xFFFF; 2328 2329 return (TRUE); 2330 } 2331 2332 static void 2333 mptsas_smp_teardown(mptsas_t *mpt) 2334 { 2335 (void) smp_hba_detach(mpt->m_dip); 2336 if (mpt->m_smptran != NULL) { 2337 smp_hba_tran_free(mpt->m_smptran); 2338 mpt->m_smptran = NULL; 2339 } 2340 mpt->m_smp_devhdl = 0; 2341 } 2342 2343 static int 2344 mptsas_enc_setup(mptsas_t *mpt) 2345 { 2346 list_create(&mpt->m_enclosures, sizeof (mptsas_enclosure_t), 2347 offsetof(mptsas_enclosure_t, me_link)); 2348 return (TRUE); 2349 } 2350 2351 static void 2352 mptsas_enc_free(mptsas_enclosure_t *mep) 2353 { 2354 if (mep == NULL) 2355 return; 2356 if (mep->me_slotleds != NULL) { 2357 VERIFY3U(mep->me_nslots, >, 0); 2358 kmem_free(mep->me_slotleds, sizeof (uint8_t) * mep->me_nslots); 2359 } 2360 kmem_free(mep, sizeof (mptsas_enclosure_t)); 2361 } 2362 2363 static void 2364 mptsas_enc_teardown(mptsas_t *mpt) 2365 { 2366 mptsas_enclosure_t *mep; 2367 2368 while ((mep = list_remove_head(&mpt->m_enclosures)) != NULL) { 2369 mptsas_enc_free(mep); 2370 } 2371 list_destroy(&mpt->m_enclosures); 2372 } 2373 2374 static mptsas_enclosure_t * 2375 mptsas_enc_lookup(mptsas_t *mpt, uint16_t hdl) 2376 { 2377 mptsas_enclosure_t *mep; 2378 2379 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 2380 2381 for (mep = list_head(&mpt->m_enclosures); mep != NULL; 2382 mep = list_next(&mpt->m_enclosures, mep)) { 2383 if (hdl == mep->me_enchdl) { 2384 return (mep); 2385 } 2386 } 2387 2388 return (NULL); 2389 } 2390 2391 static int 2392 mptsas_cache_create(mptsas_t *mpt) 2393 { 2394 int instance = mpt->m_instance; 2395 char buf[64]; 2396 2397 /* 2398 * create kmem cache for packets 2399 */ 2400 (void) sprintf(buf, "mptsas%d_cache", instance); 2401 mpt->m_kmem_cache = kmem_cache_create(buf, 2402 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8, 2403 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor, 2404 NULL, (void *)mpt, NULL, 0); 2405 2406 if (mpt->m_kmem_cache == NULL) { 2407 mptsas_log(mpt, CE_WARN, "creating kmem cache failed"); 2408 return (FALSE); 2409 } 2410 2411 /* 2412 * create kmem cache for extra SGL frames if SGL cannot 2413 * be accomodated into main request frame. 2414 */ 2415 (void) sprintf(buf, "mptsas%d_cache_frames", instance); 2416 mpt->m_cache_frames = kmem_cache_create(buf, 2417 sizeof (mptsas_cache_frames_t), 8, 2418 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor, 2419 NULL, (void *)mpt, NULL, 0); 2420 2421 if (mpt->m_cache_frames == NULL) { 2422 mptsas_log(mpt, CE_WARN, "creating cache for frames failed"); 2423 return (FALSE); 2424 } 2425 2426 return (TRUE); 2427 } 2428 2429 static void 2430 mptsas_cache_destroy(mptsas_t *mpt) 2431 { 2432 /* deallocate in reverse order */ 2433 if (mpt->m_cache_frames) { 2434 kmem_cache_destroy(mpt->m_cache_frames); 2435 mpt->m_cache_frames = NULL; 2436 } 2437 if (mpt->m_kmem_cache) { 2438 kmem_cache_destroy(mpt->m_kmem_cache); 2439 mpt->m_kmem_cache = NULL; 2440 } 2441 } 2442 2443 static int 2444 mptsas_power(dev_info_t *dip, int component, int level) 2445 { 2446 #ifndef __lock_lint 2447 _NOTE(ARGUNUSED(component)) 2448 #endif 2449 mptsas_t *mpt; 2450 int rval = DDI_SUCCESS; 2451 int polls = 0; 2452 uint32_t ioc_status; 2453 2454 if (scsi_hba_iport_unit_address(dip) != 0) 2455 return (DDI_SUCCESS); 2456 2457 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip)); 2458 if (mpt == NULL) { 2459 return (DDI_FAILURE); 2460 } 2461 2462 mutex_enter(&mpt->m_mutex); 2463 2464 /* 2465 * If the device is busy, don't lower its power level 2466 */ 2467 if (mpt->m_busy && (mpt->m_power_level > level)) { 2468 mutex_exit(&mpt->m_mutex); 2469 return (DDI_FAILURE); 2470 } 2471 switch (level) { 2472 case PM_LEVEL_D0: 2473 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance)); 2474 MPTSAS_POWER_ON(mpt); 2475 /* 2476 * Wait up to 30 seconds for IOC to come out of reset. 2477 */ 2478 while (((ioc_status = ddi_get32(mpt->m_datap, 2479 &mpt->m_reg->Doorbell)) & 2480 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 2481 if (polls++ > 3000) { 2482 break; 2483 } 2484 delay(drv_usectohz(10000)); 2485 } 2486 /* 2487 * If IOC is not in operational state, try to hard reset it. 2488 */ 2489 if ((ioc_status & MPI2_IOC_STATE_MASK) != 2490 MPI2_IOC_STATE_OPERATIONAL) { 2491 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 2492 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 2493 mptsas_log(mpt, CE_WARN, 2494 "mptsas_power: hard reset failed"); 2495 mutex_exit(&mpt->m_mutex); 2496 return (DDI_FAILURE); 2497 } 2498 } 2499 mpt->m_power_level = PM_LEVEL_D0; 2500 break; 2501 case PM_LEVEL_D3: 2502 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance)); 2503 MPTSAS_POWER_OFF(mpt); 2504 break; 2505 default: 2506 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.", 2507 mpt->m_instance, level); 2508 rval = DDI_FAILURE; 2509 break; 2510 } 2511 mutex_exit(&mpt->m_mutex); 2512 return (rval); 2513 } 2514 2515 /* 2516 * Initialize configuration space and figure out which 2517 * chip and revison of the chip the mpt driver is using. 2518 */ 2519 static int 2520 mptsas_config_space_init(mptsas_t *mpt) 2521 { 2522 NDBG0(("mptsas_config_space_init")); 2523 2524 if (mpt->m_config_handle != NULL) 2525 return (TRUE); 2526 2527 if (pci_config_setup(mpt->m_dip, 2528 &mpt->m_config_handle) != DDI_SUCCESS) { 2529 mptsas_log(mpt, CE_WARN, "cannot map configuration space."); 2530 return (FALSE); 2531 } 2532 2533 /* 2534 * This is a workaround for a XMITS ASIC bug which does not 2535 * drive the CBE upper bits. 2536 */ 2537 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) & 2538 PCI_STAT_PERROR) { 2539 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT, 2540 PCI_STAT_PERROR); 2541 } 2542 2543 mptsas_setup_cmd_reg(mpt); 2544 2545 /* 2546 * Get the chip device id: 2547 */ 2548 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID); 2549 2550 /* 2551 * Save the revision. 2552 */ 2553 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID); 2554 2555 /* 2556 * Save the SubSystem Vendor and Device IDs 2557 */ 2558 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID); 2559 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID); 2560 2561 /* 2562 * Set the latency timer to 0x40 as specified by the upa -> pci 2563 * bridge chip design team. This may be done by the sparc pci 2564 * bus nexus driver, but the driver should make sure the latency 2565 * timer is correct for performance reasons. 2566 */ 2567 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER, 2568 MPTSAS_LATENCY_TIMER); 2569 2570 (void) mptsas_get_pci_cap(mpt); 2571 return (TRUE); 2572 } 2573 2574 static void 2575 mptsas_config_space_fini(mptsas_t *mpt) 2576 { 2577 if (mpt->m_config_handle != NULL) { 2578 mptsas_disable_bus_master(mpt); 2579 pci_config_teardown(&mpt->m_config_handle); 2580 mpt->m_config_handle = NULL; 2581 } 2582 } 2583 2584 static void 2585 mptsas_setup_cmd_reg(mptsas_t *mpt) 2586 { 2587 ushort_t cmdreg; 2588 2589 /* 2590 * Set the command register to the needed values. 2591 */ 2592 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2593 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE | 2594 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE); 2595 cmdreg &= ~PCI_COMM_IO; 2596 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2597 } 2598 2599 static void 2600 mptsas_disable_bus_master(mptsas_t *mpt) 2601 { 2602 ushort_t cmdreg; 2603 2604 /* 2605 * Clear the master enable bit in the PCI command register. 2606 * This prevents any bus mastering activity like DMA. 2607 */ 2608 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2609 cmdreg &= ~PCI_COMM_ME; 2610 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2611 } 2612 2613 int 2614 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep) 2615 { 2616 ddi_dma_attr_t attrs; 2617 2618 attrs = mpt->m_io_dma_attr; 2619 attrs.dma_attr_sgllen = 1; 2620 2621 ASSERT(dma_statep != NULL); 2622 2623 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle, 2624 &dma_statep->accessp, &dma_statep->memp, dma_statep->size, 2625 &dma_statep->cookie) == FALSE) { 2626 return (DDI_FAILURE); 2627 } 2628 2629 return (DDI_SUCCESS); 2630 } 2631 2632 void 2633 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep) 2634 { 2635 ASSERT(dma_statep != NULL); 2636 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp); 2637 dma_statep->size = 0; 2638 } 2639 2640 int 2641 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()) 2642 { 2643 ddi_dma_attr_t attrs; 2644 ddi_dma_handle_t dma_handle; 2645 caddr_t memp; 2646 ddi_acc_handle_t accessp; 2647 int rval; 2648 2649 ASSERT(mutex_owned(&mpt->m_mutex)); 2650 2651 attrs = mpt->m_msg_dma_attr; 2652 attrs.dma_attr_sgllen = 1; 2653 attrs.dma_attr_granular = size; 2654 2655 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle, 2656 &accessp, &memp, size, NULL) == FALSE) { 2657 return (DDI_FAILURE); 2658 } 2659 2660 rval = (*callback) (mpt, memp, var, accessp); 2661 2662 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) || 2663 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) { 2664 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 2665 rval = DDI_FAILURE; 2666 } 2667 2668 mptsas_dma_addr_destroy(&dma_handle, &accessp); 2669 return (rval); 2670 2671 } 2672 2673 static int 2674 mptsas_alloc_request_frames(mptsas_t *mpt) 2675 { 2676 ddi_dma_attr_t frame_dma_attrs; 2677 caddr_t memp; 2678 ddi_dma_cookie_t cookie; 2679 size_t mem_size; 2680 2681 /* 2682 * re-alloc when it has already alloced 2683 */ 2684 if (mpt->m_dma_req_frame_hdl) 2685 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2686 &mpt->m_acc_req_frame_hdl); 2687 2688 /* 2689 * The size of the request frame pool is: 2690 * Number of Request Frames * Request Frame Size 2691 */ 2692 mem_size = mpt->m_max_requests * mpt->m_req_frame_size; 2693 2694 /* 2695 * set the DMA attributes. System Request Message Frames must be 2696 * aligned on a 16-byte boundry. 2697 */ 2698 frame_dma_attrs = mpt->m_msg_dma_attr; 2699 frame_dma_attrs.dma_attr_align = 16; 2700 frame_dma_attrs.dma_attr_sgllen = 1; 2701 2702 /* 2703 * allocate the request frame pool. 2704 */ 2705 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2706 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp, 2707 mem_size, &cookie) == FALSE) { 2708 return (DDI_FAILURE); 2709 } 2710 2711 /* 2712 * Store the request frame memory address. This chip uses this 2713 * address to dma to and from the driver's frame. The second 2714 * address is the address mpt uses to fill in the frame. 2715 */ 2716 mpt->m_req_frame_dma_addr = cookie.dmac_laddress; 2717 mpt->m_req_frame = memp; 2718 2719 /* 2720 * Clear the request frame pool. 2721 */ 2722 bzero(mpt->m_req_frame, mem_size); 2723 2724 return (DDI_SUCCESS); 2725 } 2726 2727 static int 2728 mptsas_alloc_sense_bufs(mptsas_t *mpt) 2729 { 2730 ddi_dma_attr_t sense_dma_attrs; 2731 caddr_t memp; 2732 ddi_dma_cookie_t cookie; 2733 size_t mem_size; 2734 int num_extrqsense_bufs; 2735 2736 ASSERT(mpt->m_extreq_sense_refcount == 0); 2737 2738 /* 2739 * re-alloc when it has already alloced 2740 */ 2741 if (mpt->m_dma_req_sense_hdl) { 2742 rmfreemap(mpt->m_erqsense_map); 2743 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl, 2744 &mpt->m_acc_req_sense_hdl); 2745 } 2746 2747 /* 2748 * The size of the request sense pool is: 2749 * (Number of Request Frames - 2 ) * Request Sense Size + 2750 * extra memory for extended sense requests. 2751 */ 2752 mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) + 2753 mptsas_extreq_sense_bufsize; 2754 2755 /* 2756 * set the DMA attributes. ARQ buffers 2757 * aligned on a 16-byte boundry. 2758 */ 2759 sense_dma_attrs = mpt->m_msg_dma_attr; 2760 sense_dma_attrs.dma_attr_align = 16; 2761 sense_dma_attrs.dma_attr_sgllen = 1; 2762 2763 /* 2764 * allocate the request sense buffer pool. 2765 */ 2766 if (mptsas_dma_addr_create(mpt, sense_dma_attrs, 2767 &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp, 2768 mem_size, &cookie) == FALSE) { 2769 return (DDI_FAILURE); 2770 } 2771 2772 /* 2773 * Store the request sense base memory address. This chip uses this 2774 * address to dma the request sense data. The second 2775 * address is the address mpt uses to access the data. 2776 * The third is the base for the extended rqsense buffers. 2777 */ 2778 mpt->m_req_sense_dma_addr = cookie.dmac_laddress; 2779 mpt->m_req_sense = memp; 2780 memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size; 2781 mpt->m_extreq_sense = memp; 2782 2783 /* 2784 * The extra memory is divided up into multiples of the base 2785 * buffer size in order to allocate via rmalloc(). 2786 * Note that the rmallocmap cannot start at zero! 2787 */ 2788 num_extrqsense_bufs = mptsas_extreq_sense_bufsize / 2789 mpt->m_req_sense_size; 2790 mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs); 2791 rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1); 2792 2793 /* 2794 * Clear the pool. 2795 */ 2796 bzero(mpt->m_req_sense, mem_size); 2797 2798 return (DDI_SUCCESS); 2799 } 2800 2801 static int 2802 mptsas_alloc_reply_frames(mptsas_t *mpt) 2803 { 2804 ddi_dma_attr_t frame_dma_attrs; 2805 caddr_t memp; 2806 ddi_dma_cookie_t cookie; 2807 size_t mem_size; 2808 2809 /* 2810 * re-alloc when it has already alloced 2811 */ 2812 if (mpt->m_dma_reply_frame_hdl) { 2813 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2814 &mpt->m_acc_reply_frame_hdl); 2815 } 2816 2817 /* 2818 * The size of the reply frame pool is: 2819 * Number of Reply Frames * Reply Frame Size 2820 */ 2821 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size; 2822 2823 /* 2824 * set the DMA attributes. System Reply Message Frames must be 2825 * aligned on a 4-byte boundry. This is the default. 2826 */ 2827 frame_dma_attrs = mpt->m_msg_dma_attr; 2828 frame_dma_attrs.dma_attr_sgllen = 1; 2829 2830 /* 2831 * allocate the reply frame pool 2832 */ 2833 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2834 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp, 2835 mem_size, &cookie) == FALSE) { 2836 return (DDI_FAILURE); 2837 } 2838 2839 /* 2840 * Store the reply frame memory address. This chip uses this 2841 * address to dma to and from the driver's frame. The second 2842 * address is the address mpt uses to process the frame. 2843 */ 2844 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress; 2845 mpt->m_reply_frame = memp; 2846 2847 /* 2848 * Clear the reply frame pool. 2849 */ 2850 bzero(mpt->m_reply_frame, mem_size); 2851 2852 return (DDI_SUCCESS); 2853 } 2854 2855 static int 2856 mptsas_alloc_free_queue(mptsas_t *mpt) 2857 { 2858 ddi_dma_attr_t frame_dma_attrs; 2859 caddr_t memp; 2860 ddi_dma_cookie_t cookie; 2861 size_t mem_size; 2862 2863 /* 2864 * re-alloc when it has already alloced 2865 */ 2866 if (mpt->m_dma_free_queue_hdl) { 2867 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2868 &mpt->m_acc_free_queue_hdl); 2869 } 2870 2871 /* 2872 * The reply free queue size is: 2873 * Reply Free Queue Depth * 4 2874 * The "4" is the size of one 32 bit address (low part of 64-bit 2875 * address) 2876 */ 2877 mem_size = mpt->m_free_queue_depth * 4; 2878 2879 /* 2880 * set the DMA attributes The Reply Free Queue must be aligned on a 2881 * 16-byte boundry. 2882 */ 2883 frame_dma_attrs = mpt->m_msg_dma_attr; 2884 frame_dma_attrs.dma_attr_align = 16; 2885 frame_dma_attrs.dma_attr_sgllen = 1; 2886 2887 /* 2888 * allocate the reply free queue 2889 */ 2890 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2891 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp, 2892 mem_size, &cookie) == FALSE) { 2893 return (DDI_FAILURE); 2894 } 2895 2896 /* 2897 * Store the reply free queue memory address. This chip uses this 2898 * address to read from the reply free queue. The second address 2899 * is the address mpt uses to manage the queue. 2900 */ 2901 mpt->m_free_queue_dma_addr = cookie.dmac_laddress; 2902 mpt->m_free_queue = memp; 2903 2904 /* 2905 * Clear the reply free queue memory. 2906 */ 2907 bzero(mpt->m_free_queue, mem_size); 2908 2909 return (DDI_SUCCESS); 2910 } 2911 2912 static int 2913 mptsas_alloc_post_queue(mptsas_t *mpt) 2914 { 2915 ddi_dma_attr_t frame_dma_attrs; 2916 caddr_t memp; 2917 ddi_dma_cookie_t cookie; 2918 size_t mem_size; 2919 2920 /* 2921 * re-alloc when it has already alloced 2922 */ 2923 if (mpt->m_dma_post_queue_hdl) { 2924 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2925 &mpt->m_acc_post_queue_hdl); 2926 } 2927 2928 /* 2929 * The reply descriptor post queue size is: 2930 * Reply Descriptor Post Queue Depth * 8 2931 * The "8" is the size of each descriptor (8 bytes or 64 bits). 2932 */ 2933 mem_size = mpt->m_post_queue_depth * 8; 2934 2935 /* 2936 * set the DMA attributes. The Reply Descriptor Post Queue must be 2937 * aligned on a 16-byte boundry. 2938 */ 2939 frame_dma_attrs = mpt->m_msg_dma_attr; 2940 frame_dma_attrs.dma_attr_align = 16; 2941 frame_dma_attrs.dma_attr_sgllen = 1; 2942 2943 /* 2944 * allocate the reply post queue 2945 */ 2946 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2947 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp, 2948 mem_size, &cookie) == FALSE) { 2949 return (DDI_FAILURE); 2950 } 2951 2952 /* 2953 * Store the reply descriptor post queue memory address. This chip 2954 * uses this address to write to the reply descriptor post queue. The 2955 * second address is the address mpt uses to manage the queue. 2956 */ 2957 mpt->m_post_queue_dma_addr = cookie.dmac_laddress; 2958 mpt->m_post_queue = memp; 2959 2960 /* 2961 * Clear the reply post queue memory. 2962 */ 2963 bzero(mpt->m_post_queue, mem_size); 2964 2965 return (DDI_SUCCESS); 2966 } 2967 2968 static void 2969 mptsas_alloc_reply_args(mptsas_t *mpt) 2970 { 2971 if (mpt->m_replyh_args == NULL) { 2972 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) * 2973 mpt->m_max_replies, KM_SLEEP); 2974 } 2975 } 2976 2977 static int 2978 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2979 { 2980 mptsas_cache_frames_t *frames = NULL; 2981 if (cmd->cmd_extra_frames == NULL) { 2982 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP); 2983 if (frames == NULL) { 2984 return (DDI_FAILURE); 2985 } 2986 cmd->cmd_extra_frames = frames; 2987 } 2988 return (DDI_SUCCESS); 2989 } 2990 2991 static void 2992 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2993 { 2994 if (cmd->cmd_extra_frames) { 2995 kmem_cache_free(mpt->m_cache_frames, 2996 (void *)cmd->cmd_extra_frames); 2997 cmd->cmd_extra_frames = NULL; 2998 } 2999 } 3000 3001 static void 3002 mptsas_cfg_fini(mptsas_t *mpt) 3003 { 3004 NDBG0(("mptsas_cfg_fini")); 3005 ddi_regs_map_free(&mpt->m_datap); 3006 } 3007 3008 static void 3009 mptsas_hba_fini(mptsas_t *mpt) 3010 { 3011 NDBG0(("mptsas_hba_fini")); 3012 3013 /* 3014 * Free up any allocated memory 3015 */ 3016 if (mpt->m_dma_req_frame_hdl) { 3017 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 3018 &mpt->m_acc_req_frame_hdl); 3019 } 3020 3021 if (mpt->m_dma_req_sense_hdl) { 3022 rmfreemap(mpt->m_erqsense_map); 3023 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl, 3024 &mpt->m_acc_req_sense_hdl); 3025 } 3026 3027 if (mpt->m_dma_reply_frame_hdl) { 3028 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 3029 &mpt->m_acc_reply_frame_hdl); 3030 } 3031 3032 if (mpt->m_dma_free_queue_hdl) { 3033 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 3034 &mpt->m_acc_free_queue_hdl); 3035 } 3036 3037 if (mpt->m_dma_post_queue_hdl) { 3038 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 3039 &mpt->m_acc_post_queue_hdl); 3040 } 3041 3042 if (mpt->m_replyh_args != NULL) { 3043 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 3044 * mpt->m_max_replies); 3045 } 3046 } 3047 3048 static int 3049 mptsas_name_child(dev_info_t *lun_dip, char *name, int len) 3050 { 3051 int lun = 0; 3052 char *sas_wwn = NULL; 3053 int phynum = -1; 3054 int reallen = 0; 3055 3056 /* Get the target num */ 3057 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS, 3058 LUN_PROP, 0); 3059 3060 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, 3061 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) { 3062 /* 3063 * Stick in the address of form "pPHY,LUN" 3064 */ 3065 reallen = snprintf(name, len, "p%x,%x", phynum, lun); 3066 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip, 3067 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn) 3068 == DDI_PROP_SUCCESS) { 3069 /* 3070 * Stick in the address of the form "wWWN,LUN" 3071 */ 3072 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun); 3073 ddi_prop_free(sas_wwn); 3074 } else { 3075 return (DDI_FAILURE); 3076 } 3077 3078 ASSERT(reallen < len); 3079 if (reallen >= len) { 3080 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter " 3081 "length too small, it needs to be %d bytes", reallen + 1); 3082 } 3083 return (DDI_SUCCESS); 3084 } 3085 3086 /* 3087 * tran_tgt_init(9E) - target device instance initialization 3088 */ 3089 static int 3090 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 3091 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 3092 { 3093 #ifndef __lock_lint 3094 _NOTE(ARGUNUSED(hba_tran)) 3095 #endif 3096 3097 /* 3098 * At this point, the scsi_device structure already exists 3099 * and has been initialized. 3100 * 3101 * Use this function to allocate target-private data structures, 3102 * if needed by this HBA. Add revised flow-control and queue 3103 * properties for child here, if desired and if you can tell they 3104 * support tagged queueing by now. 3105 */ 3106 mptsas_t *mpt; 3107 int lun = sd->sd_address.a_lun; 3108 mdi_pathinfo_t *pip = NULL; 3109 mptsas_tgt_private_t *tgt_private = NULL; 3110 mptsas_target_t *ptgt = NULL; 3111 char *psas_wwn = NULL; 3112 mptsas_phymask_t phymask = 0; 3113 uint64_t sas_wwn = 0; 3114 mptsas_target_addr_t addr; 3115 mpt = SDEV2MPT(sd); 3116 3117 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0); 3118 3119 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d", 3120 (void *)hba_dip, (void *)tgt_dip, lun)); 3121 3122 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 3123 (void) ndi_merge_node(tgt_dip, mptsas_name_child); 3124 ddi_set_name_addr(tgt_dip, NULL); 3125 return (DDI_FAILURE); 3126 } 3127 /* 3128 * phymask is 0 means the virtual port for RAID 3129 */ 3130 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0, 3131 "phymask", 0); 3132 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 3133 if ((pip = (void *)(sd->sd_private)) == NULL) { 3134 /* 3135 * Very bad news if this occurs. Somehow scsi_vhci has 3136 * lost the pathinfo node for this target. 3137 */ 3138 return (DDI_NOT_WELL_FORMED); 3139 } 3140 3141 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) != 3142 DDI_PROP_SUCCESS) { 3143 mptsas_log(mpt, CE_WARN, "Get lun property failed\n"); 3144 return (DDI_FAILURE); 3145 } 3146 3147 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT, 3148 &psas_wwn) == MDI_SUCCESS) { 3149 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 3150 sas_wwn = 0; 3151 } 3152 (void) mdi_prop_free(psas_wwn); 3153 } 3154 } else { 3155 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip, 3156 DDI_PROP_DONTPASS, LUN_PROP, 0); 3157 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip, 3158 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) == 3159 DDI_PROP_SUCCESS) { 3160 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 3161 sas_wwn = 0; 3162 } 3163 ddi_prop_free(psas_wwn); 3164 } else { 3165 sas_wwn = 0; 3166 } 3167 } 3168 3169 ASSERT((sas_wwn != 0) || (phymask != 0)); 3170 addr.mta_wwn = sas_wwn; 3171 addr.mta_phymask = phymask; 3172 mutex_enter(&mpt->m_mutex); 3173 ptgt = refhash_lookup(mpt->m_targets, &addr); 3174 mutex_exit(&mpt->m_mutex); 3175 if (ptgt == NULL) { 3176 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or " 3177 "gone already! phymask:%x, saswwn %"PRIx64, phymask, 3178 sas_wwn); 3179 return (DDI_FAILURE); 3180 } 3181 if (hba_tran->tran_tgt_private == NULL) { 3182 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t), 3183 KM_SLEEP); 3184 tgt_private->t_lun = lun; 3185 tgt_private->t_private = ptgt; 3186 hba_tran->tran_tgt_private = tgt_private; 3187 } 3188 3189 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 3190 return (DDI_SUCCESS); 3191 } 3192 mutex_enter(&mpt->m_mutex); 3193 3194 if (ptgt->m_deviceinfo & 3195 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 3196 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 3197 uchar_t *inq89 = NULL; 3198 int inq89_len = 0x238; 3199 int reallen = 0; 3200 int rval = 0; 3201 struct sata_id *sid = NULL; 3202 char model[SATA_ID_MODEL_LEN + 1]; 3203 char fw[SATA_ID_FW_LEN + 1]; 3204 char *vid, *pid; 3205 3206 mutex_exit(&mpt->m_mutex); 3207 /* 3208 * According SCSI/ATA Translation -2 (SAT-2) revision 01a 3209 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY 3210 * DEVICE data or ATA IDENTIFY PACKET DEVICE data. 3211 */ 3212 inq89 = kmem_zalloc(inq89_len, KM_SLEEP); 3213 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89, 3214 inq89, inq89_len, &reallen, 1); 3215 3216 if (rval != 0) { 3217 if (inq89 != NULL) { 3218 kmem_free(inq89, inq89_len); 3219 } 3220 3221 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 3222 "0x89 for SATA target:%x failed!", ptgt->m_devhdl); 3223 return (DDI_SUCCESS); 3224 } 3225 sid = (void *)(&inq89[60]); 3226 3227 swab(sid->ai_model, model, SATA_ID_MODEL_LEN); 3228 swab(sid->ai_fw, fw, SATA_ID_FW_LEN); 3229 3230 model[SATA_ID_MODEL_LEN] = 0; 3231 fw[SATA_ID_FW_LEN] = 0; 3232 3233 sata_split_model(model, &vid, &pid); 3234 3235 /* 3236 * override SCSA "inquiry-*" properties 3237 */ 3238 if (vid) 3239 (void) scsi_device_prop_update_inqstring(sd, 3240 INQUIRY_VENDOR_ID, vid, strlen(vid)); 3241 if (pid) 3242 (void) scsi_device_prop_update_inqstring(sd, 3243 INQUIRY_PRODUCT_ID, pid, strlen(pid)); 3244 (void) scsi_device_prop_update_inqstring(sd, 3245 INQUIRY_REVISION_ID, fw, strlen(fw)); 3246 3247 if (inq89 != NULL) { 3248 kmem_free(inq89, inq89_len); 3249 } 3250 } else { 3251 mutex_exit(&mpt->m_mutex); 3252 } 3253 3254 return (DDI_SUCCESS); 3255 } 3256 /* 3257 * tran_tgt_free(9E) - target device instance deallocation 3258 */ 3259 static void 3260 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 3261 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 3262 { 3263 #ifndef __lock_lint 3264 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd)) 3265 #endif 3266 3267 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private; 3268 3269 if (tgt_private != NULL) { 3270 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 3271 hba_tran->tran_tgt_private = NULL; 3272 } 3273 } 3274 3275 /* 3276 * scsi_pkt handling 3277 * 3278 * Visible to the external world via the transport structure. 3279 */ 3280 3281 /* 3282 * Notes: 3283 * - transport the command to the addressed SCSI target/lun device 3284 * - normal operation is to schedule the command to be transported, 3285 * and return TRAN_ACCEPT if this is successful. 3286 * - if NO_INTR, tran_start must poll device for command completion 3287 */ 3288 static int 3289 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt) 3290 { 3291 #ifndef __lock_lint 3292 _NOTE(ARGUNUSED(ap)) 3293 #endif 3294 mptsas_t *mpt = PKT2MPT(pkt); 3295 mptsas_cmd_t *cmd = PKT2CMD(pkt); 3296 int rval; 3297 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3298 3299 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt)); 3300 ASSERT(ptgt); 3301 if (ptgt == NULL) 3302 return (TRAN_FATAL_ERROR); 3303 3304 /* 3305 * prepare the pkt before taking mutex. 3306 */ 3307 rval = mptsas_prepare_pkt(cmd); 3308 if (rval != TRAN_ACCEPT) { 3309 return (rval); 3310 } 3311 3312 /* 3313 * Send the command to target/lun, however your HBA requires it. 3314 * If busy, return TRAN_BUSY; if there's some other formatting error 3315 * in the packet, return TRAN_BADPKT; otherwise, fall through to the 3316 * return of TRAN_ACCEPT. 3317 * 3318 * Remember that access to shared resources, including the mptsas_t 3319 * data structure and the HBA hardware registers, must be protected 3320 * with mutexes, here and everywhere. 3321 * 3322 * Also remember that at interrupt time, you'll get an argument 3323 * to the interrupt handler which is a pointer to your mptsas_t 3324 * structure; you'll have to remember which commands are outstanding 3325 * and which scsi_pkt is the currently-running command so the 3326 * interrupt handler can refer to the pkt to set completion 3327 * status, call the target driver back through pkt_comp, etc. 3328 * 3329 * If the instance lock is held by other thread, don't spin to wait 3330 * for it. Instead, queue the cmd and next time when the instance lock 3331 * is not held, accept all the queued cmd. A extra tx_waitq is 3332 * introduced to protect the queue. 3333 * 3334 * The polled cmd will not be queud and accepted as usual. 3335 * 3336 * Under the tx_waitq mutex, record whether a thread is draining 3337 * the tx_waitq. An IO requesting thread that finds the instance 3338 * mutex contended appends to the tx_waitq and while holding the 3339 * tx_wait mutex, if the draining flag is not set, sets it and then 3340 * proceeds to spin for the instance mutex. This scheme ensures that 3341 * the last cmd in a burst be processed. 3342 * 3343 * we enable this feature only when the helper threads are enabled, 3344 * at which we think the loads are heavy. 3345 * 3346 * per instance mutex m_tx_waitq_mutex is introduced to protect the 3347 * m_tx_waitqtail, m_tx_waitq, m_tx_draining. 3348 */ 3349 3350 if (mpt->m_doneq_thread_n) { 3351 if (mutex_tryenter(&mpt->m_mutex) != 0) { 3352 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3353 mutex_exit(&mpt->m_mutex); 3354 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3355 mutex_enter(&mpt->m_mutex); 3356 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3357 mutex_exit(&mpt->m_mutex); 3358 } else { 3359 mutex_enter(&mpt->m_tx_waitq_mutex); 3360 /* 3361 * ptgt->m_dr_flag is protected by m_mutex or 3362 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex 3363 * is acquired. 3364 */ 3365 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3366 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3367 /* 3368 * The command should be allowed to 3369 * retry by returning TRAN_BUSY to 3370 * to stall the I/O's which come from 3371 * scsi_vhci since the device/path is 3372 * in unstable state now. 3373 */ 3374 mutex_exit(&mpt->m_tx_waitq_mutex); 3375 return (TRAN_BUSY); 3376 } else { 3377 /* 3378 * The device is offline, just fail the 3379 * command by returning 3380 * TRAN_FATAL_ERROR. 3381 */ 3382 mutex_exit(&mpt->m_tx_waitq_mutex); 3383 return (TRAN_FATAL_ERROR); 3384 } 3385 } 3386 if (mpt->m_tx_draining) { 3387 cmd->cmd_flags |= CFLAG_TXQ; 3388 *mpt->m_tx_waitqtail = cmd; 3389 mpt->m_tx_waitqtail = &cmd->cmd_linkp; 3390 mutex_exit(&mpt->m_tx_waitq_mutex); 3391 } else { /* drain the queue */ 3392 mpt->m_tx_draining = 1; 3393 mutex_exit(&mpt->m_tx_waitq_mutex); 3394 mutex_enter(&mpt->m_mutex); 3395 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3396 mutex_exit(&mpt->m_mutex); 3397 } 3398 } 3399 } else { 3400 mutex_enter(&mpt->m_mutex); 3401 /* 3402 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3403 * in this case, m_mutex is acquired. 3404 */ 3405 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3406 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3407 /* 3408 * commands should be allowed to retry by 3409 * returning TRAN_BUSY to stall the I/O's 3410 * which come from scsi_vhci since the device/ 3411 * path is in unstable state now. 3412 */ 3413 mutex_exit(&mpt->m_mutex); 3414 return (TRAN_BUSY); 3415 } else { 3416 /* 3417 * The device is offline, just fail the 3418 * command by returning TRAN_FATAL_ERROR. 3419 */ 3420 mutex_exit(&mpt->m_mutex); 3421 return (TRAN_FATAL_ERROR); 3422 } 3423 } 3424 rval = mptsas_accept_pkt(mpt, cmd); 3425 mutex_exit(&mpt->m_mutex); 3426 } 3427 3428 return (rval); 3429 } 3430 3431 /* 3432 * Accept all the queued cmds(if any) before accept the current one. 3433 */ 3434 static int 3435 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3436 { 3437 int rval; 3438 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3439 3440 ASSERT(mutex_owned(&mpt->m_mutex)); 3441 /* 3442 * The call to mptsas_accept_tx_waitq() must always be performed 3443 * because that is where mpt->m_tx_draining is cleared. 3444 */ 3445 mutex_enter(&mpt->m_tx_waitq_mutex); 3446 mptsas_accept_tx_waitq(mpt); 3447 mutex_exit(&mpt->m_tx_waitq_mutex); 3448 /* 3449 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3450 * in this case, m_mutex is acquired. 3451 */ 3452 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3453 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3454 /* 3455 * The command should be allowed to retry by returning 3456 * TRAN_BUSY to stall the I/O's which come from 3457 * scsi_vhci since the device/path is in unstable state 3458 * now. 3459 */ 3460 return (TRAN_BUSY); 3461 } else { 3462 /* 3463 * The device is offline, just fail the command by 3464 * return TRAN_FATAL_ERROR. 3465 */ 3466 return (TRAN_FATAL_ERROR); 3467 } 3468 } 3469 rval = mptsas_accept_pkt(mpt, cmd); 3470 3471 return (rval); 3472 } 3473 3474 static int 3475 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3476 { 3477 int rval = TRAN_ACCEPT; 3478 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3479 3480 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd)); 3481 3482 ASSERT(mutex_owned(&mpt->m_mutex)); 3483 3484 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) { 3485 rval = mptsas_prepare_pkt(cmd); 3486 if (rval != TRAN_ACCEPT) { 3487 cmd->cmd_flags &= ~CFLAG_TRANFLAG; 3488 return (rval); 3489 } 3490 } 3491 3492 /* 3493 * reset the throttle if we were draining 3494 */ 3495 if ((ptgt->m_t_ncmds == 0) && 3496 (ptgt->m_t_throttle == DRAIN_THROTTLE)) { 3497 NDBG23(("reset throttle")); 3498 ASSERT(ptgt->m_reset_delay == 0); 3499 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 3500 } 3501 3502 /* 3503 * If HBA is being reset, the DevHandles are being re-initialized, 3504 * which means that they could be invalid even if the target is still 3505 * attached. Check if being reset and if DevHandle is being 3506 * re-initialized. If this is the case, return BUSY so the I/O can be 3507 * retried later. 3508 */ 3509 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) { 3510 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 3511 if (cmd->cmd_flags & CFLAG_TXQ) { 3512 mptsas_doneq_add(mpt, cmd); 3513 mptsas_doneq_empty(mpt); 3514 return (rval); 3515 } else { 3516 return (TRAN_BUSY); 3517 } 3518 } 3519 3520 /* 3521 * If device handle has already been invalidated, just 3522 * fail the command. In theory, command from scsi_vhci 3523 * client is impossible send down command with invalid 3524 * devhdl since devhdl is set after path offline, target 3525 * driver is not suppose to select a offlined path. 3526 */ 3527 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) { 3528 NDBG3(("rejecting command, it might because invalid devhdl " 3529 "request.")); 3530 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED); 3531 if (cmd->cmd_flags & CFLAG_TXQ) { 3532 mptsas_doneq_add(mpt, cmd); 3533 mptsas_doneq_empty(mpt); 3534 return (rval); 3535 } else { 3536 return (TRAN_FATAL_ERROR); 3537 } 3538 } 3539 /* 3540 * The first case is the normal case. mpt gets a command from the 3541 * target driver and starts it. 3542 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 3543 * commands is m_max_requests - 2. 3544 */ 3545 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 3546 (ptgt->m_t_throttle > HOLD_THROTTLE) && 3547 (ptgt->m_t_ncmds < ptgt->m_t_throttle) && 3548 (ptgt->m_reset_delay == 0) && 3549 (ptgt->m_t_nwait == 0) && 3550 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) { 3551 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 3552 (void) mptsas_start_cmd(mpt, cmd); 3553 } else { 3554 mptsas_waitq_add(mpt, cmd); 3555 } 3556 } else { 3557 /* 3558 * Add this pkt to the work queue 3559 */ 3560 mptsas_waitq_add(mpt, cmd); 3561 3562 if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3563 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME); 3564 3565 /* 3566 * Only flush the doneq if this is not a TM 3567 * cmd. For TM cmds the flushing of the 3568 * doneq will be done in those routines. 3569 */ 3570 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 3571 mptsas_doneq_empty(mpt); 3572 } 3573 } 3574 } 3575 return (rval); 3576 } 3577 3578 int 3579 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 3580 { 3581 mptsas_slots_t *slots = mpt->m_active; 3582 uint_t slot, start_rotor; 3583 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3584 3585 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 3586 3587 /* 3588 * Account for reserved TM request slot and reserved SMID of 0. 3589 */ 3590 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2)); 3591 3592 /* 3593 * Find the next available slot, beginning at m_rotor. If no slot is 3594 * available, we'll return FALSE to indicate that. This mechanism 3595 * considers only the normal slots, not the reserved slot 0 nor the 3596 * task management slot m_n_normal + 1. The rotor is left to point to 3597 * the normal slot after the one we select, unless we select the last 3598 * normal slot in which case it returns to slot 1. 3599 */ 3600 start_rotor = slots->m_rotor; 3601 do { 3602 slot = slots->m_rotor++; 3603 if (slots->m_rotor > slots->m_n_normal) 3604 slots->m_rotor = 1; 3605 3606 if (slots->m_rotor == start_rotor) 3607 break; 3608 } while (slots->m_slot[slot] != NULL); 3609 3610 if (slots->m_slot[slot] != NULL) 3611 return (FALSE); 3612 3613 ASSERT(slot != 0 && slot <= slots->m_n_normal); 3614 3615 cmd->cmd_slot = slot; 3616 slots->m_slot[slot] = cmd; 3617 mpt->m_ncmds++; 3618 3619 /* 3620 * only increment per target ncmds if this is not a 3621 * command that has no target associated with it (i.e. a 3622 * event acknoledgment) 3623 */ 3624 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 3625 /* 3626 * Expiration time is set in mptsas_start_cmd 3627 */ 3628 ptgt->m_t_ncmds++; 3629 cmd->cmd_active_expiration = 0; 3630 } else { 3631 /* 3632 * Initialize expiration time for passthrough commands, 3633 */ 3634 cmd->cmd_active_expiration = gethrtime() + 3635 (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC; 3636 } 3637 return (TRUE); 3638 } 3639 3640 /* 3641 * prepare the pkt: 3642 * the pkt may have been resubmitted or just reused so 3643 * initialize some fields and do some checks. 3644 */ 3645 static int 3646 mptsas_prepare_pkt(mptsas_cmd_t *cmd) 3647 { 3648 struct scsi_pkt *pkt = CMD2PKT(cmd); 3649 3650 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd)); 3651 3652 /* 3653 * Reinitialize some fields that need it; the packet may 3654 * have been resubmitted 3655 */ 3656 pkt->pkt_reason = CMD_CMPLT; 3657 pkt->pkt_state = 0; 3658 pkt->pkt_statistics = 0; 3659 pkt->pkt_resid = 0; 3660 cmd->cmd_age = 0; 3661 cmd->cmd_pkt_flags = pkt->pkt_flags; 3662 3663 /* 3664 * zero status byte. 3665 */ 3666 *(pkt->pkt_scbp) = 0; 3667 3668 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3669 pkt->pkt_resid = cmd->cmd_dmacount; 3670 3671 /* 3672 * consistent packets need to be sync'ed first 3673 * (only for data going out) 3674 */ 3675 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 3676 (cmd->cmd_flags & CFLAG_DMASEND)) { 3677 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 3678 DDI_DMA_SYNC_FORDEV); 3679 } 3680 } 3681 3682 cmd->cmd_flags = 3683 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) | 3684 CFLAG_PREPARED | CFLAG_IN_TRANSPORT; 3685 3686 return (TRAN_ACCEPT); 3687 } 3688 3689 /* 3690 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command 3691 * 3692 * One of three possibilities: 3693 * - allocate scsi_pkt 3694 * - allocate scsi_pkt and DMA resources 3695 * - allocate DMA resources to an already-allocated pkt 3696 */ 3697 static struct scsi_pkt * 3698 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt, 3699 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags, 3700 int (*callback)(), caddr_t arg) 3701 { 3702 mptsas_cmd_t *cmd, *new_cmd; 3703 mptsas_t *mpt = ADDR2MPT(ap); 3704 uint_t oldcookiec; 3705 mptsas_target_t *ptgt = NULL; 3706 int rval; 3707 mptsas_tgt_private_t *tgt_private; 3708 int kf; 3709 3710 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP; 3711 3712 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 3713 tran_tgt_private; 3714 ASSERT(tgt_private != NULL); 3715 if (tgt_private == NULL) { 3716 return (NULL); 3717 } 3718 ptgt = tgt_private->t_private; 3719 ASSERT(ptgt != NULL); 3720 if (ptgt == NULL) 3721 return (NULL); 3722 ap->a_target = ptgt->m_devhdl; 3723 ap->a_lun = tgt_private->t_lun; 3724 3725 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC); 3726 #ifdef MPTSAS_TEST_EXTRN_ALLOC 3727 statuslen *= 100; tgtlen *= 4; 3728 #endif 3729 NDBG3(("mptsas_scsi_init_pkt:\n" 3730 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x", 3731 ap->a_target, (void *)pkt, (void *)bp, 3732 cmdlen, statuslen, tgtlen, flags)); 3733 3734 /* 3735 * Allocate the new packet. 3736 */ 3737 if (pkt == NULL) { 3738 ddi_dma_handle_t save_dma_handle; 3739 3740 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf); 3741 if (cmd == NULL) 3742 return (NULL); 3743 3744 save_dma_handle = cmd->cmd_dmahandle; 3745 bzero(cmd, sizeof (*cmd) + scsi_pkt_size()); 3746 cmd->cmd_dmahandle = save_dma_handle; 3747 3748 pkt = (void *)((uchar_t *)cmd + 3749 sizeof (struct mptsas_cmd)); 3750 pkt->pkt_ha_private = (opaque_t)cmd; 3751 pkt->pkt_address = *ap; 3752 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private; 3753 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 3754 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb; 3755 cmd->cmd_pkt = (struct scsi_pkt *)pkt; 3756 cmd->cmd_cdblen = (uchar_t)cmdlen; 3757 cmd->cmd_scblen = statuslen; 3758 cmd->cmd_rqslen = SENSE_LENGTH; 3759 cmd->cmd_tgt_addr = ptgt; 3760 3761 if ((cmdlen > sizeof (cmd->cmd_cdb)) || 3762 (tgtlen > PKT_PRIV_LEN) || 3763 (statuslen > EXTCMDS_STATUS_SIZE)) { 3764 int failure; 3765 3766 /* 3767 * We are going to allocate external packet space which 3768 * might include the sense data buffer for DMA so we 3769 * need to increase the reference counter here. In a 3770 * case the HBA is in reset we just simply free the 3771 * allocated packet and bail out. 3772 */ 3773 mutex_enter(&mpt->m_mutex); 3774 if (mpt->m_in_reset) { 3775 mutex_exit(&mpt->m_mutex); 3776 3777 cmd->cmd_flags = CFLAG_FREE; 3778 kmem_cache_free(mpt->m_kmem_cache, cmd); 3779 return (NULL); 3780 } 3781 mpt->m_extreq_sense_refcount++; 3782 ASSERT(mpt->m_extreq_sense_refcount > 0); 3783 mutex_exit(&mpt->m_mutex); 3784 3785 /* 3786 * if extern alloc fails, all will be 3787 * deallocated, including cmd 3788 */ 3789 failure = mptsas_pkt_alloc_extern(mpt, cmd, 3790 cmdlen, tgtlen, statuslen, kf); 3791 3792 if (failure != 0 || cmd->cmd_extrqslen == 0) { 3793 /* 3794 * If the external packet space allocation 3795 * failed, or we didn't allocate the sense 3796 * data buffer for DMA we need to decrease the 3797 * reference counter. 3798 */ 3799 mutex_enter(&mpt->m_mutex); 3800 ASSERT(mpt->m_extreq_sense_refcount > 0); 3801 mpt->m_extreq_sense_refcount--; 3802 if (mpt->m_extreq_sense_refcount == 0) 3803 cv_broadcast( 3804 &mpt->m_extreq_sense_refcount_cv); 3805 mutex_exit(&mpt->m_mutex); 3806 3807 if (failure != 0) { 3808 /* 3809 * if extern allocation fails, it will 3810 * deallocate the new pkt as well 3811 */ 3812 return (NULL); 3813 } 3814 } 3815 } 3816 new_cmd = cmd; 3817 3818 } else { 3819 cmd = PKT2CMD(pkt); 3820 new_cmd = NULL; 3821 } 3822 3823 3824 /* grab cmd->cmd_cookiec here as oldcookiec */ 3825 3826 oldcookiec = cmd->cmd_cookiec; 3827 3828 /* 3829 * If the dma was broken up into PARTIAL transfers cmd_nwin will be 3830 * greater than 0 and we'll need to grab the next dma window 3831 */ 3832 /* 3833 * SLM-not doing extra command frame right now; may add later 3834 */ 3835 3836 if (cmd->cmd_nwin > 0) { 3837 3838 /* 3839 * Make sure we havn't gone past the the total number 3840 * of windows 3841 */ 3842 if (++cmd->cmd_winindex >= cmd->cmd_nwin) { 3843 return (NULL); 3844 } 3845 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex, 3846 &cmd->cmd_dma_offset, &cmd->cmd_dma_len, 3847 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) { 3848 return (NULL); 3849 } 3850 goto get_dma_cookies; 3851 } 3852 3853 3854 if (flags & PKT_XARQ) { 3855 cmd->cmd_flags |= CFLAG_XARQ; 3856 } 3857 3858 /* 3859 * DMA resource allocation. This version assumes your 3860 * HBA has some sort of bus-mastering or onboard DMA capability, with a 3861 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the 3862 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget. 3863 */ 3864 if (bp && (bp->b_bcount != 0) && 3865 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) { 3866 3867 int cnt, dma_flags; 3868 mptti_t *dmap; /* ptr to the S/G list */ 3869 3870 /* 3871 * Set up DMA memory and position to the next DMA segment. 3872 */ 3873 ASSERT(cmd->cmd_dmahandle != NULL); 3874 3875 if (bp->b_flags & B_READ) { 3876 dma_flags = DDI_DMA_READ; 3877 cmd->cmd_flags &= ~CFLAG_DMASEND; 3878 } else { 3879 dma_flags = DDI_DMA_WRITE; 3880 cmd->cmd_flags |= CFLAG_DMASEND; 3881 } 3882 if (flags & PKT_CONSISTENT) { 3883 cmd->cmd_flags |= CFLAG_CMDIOPB; 3884 dma_flags |= DDI_DMA_CONSISTENT; 3885 } 3886 3887 if (flags & PKT_DMA_PARTIAL) { 3888 dma_flags |= DDI_DMA_PARTIAL; 3889 } 3890 3891 /* 3892 * workaround for byte hole issue on psycho and 3893 * schizo pre 2.1 3894 */ 3895 if ((bp->b_flags & B_READ) && ((bp->b_flags & 3896 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) && 3897 ((uintptr_t)bp->b_un.b_addr & 0x7)) { 3898 dma_flags |= DDI_DMA_CONSISTENT; 3899 } 3900 3901 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp, 3902 dma_flags, callback, arg, 3903 &cmd->cmd_cookie, &cmd->cmd_cookiec); 3904 if (rval == DDI_DMA_PARTIAL_MAP) { 3905 (void) ddi_dma_numwin(cmd->cmd_dmahandle, 3906 &cmd->cmd_nwin); 3907 cmd->cmd_winindex = 0; 3908 (void) ddi_dma_getwin(cmd->cmd_dmahandle, 3909 cmd->cmd_winindex, &cmd->cmd_dma_offset, 3910 &cmd->cmd_dma_len, &cmd->cmd_cookie, 3911 &cmd->cmd_cookiec); 3912 } else if (rval && (rval != DDI_DMA_MAPPED)) { 3913 switch (rval) { 3914 case DDI_DMA_NORESOURCES: 3915 bioerror(bp, 0); 3916 break; 3917 case DDI_DMA_BADATTR: 3918 case DDI_DMA_NOMAPPING: 3919 bioerror(bp, EFAULT); 3920 break; 3921 case DDI_DMA_TOOBIG: 3922 default: 3923 bioerror(bp, EINVAL); 3924 break; 3925 } 3926 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3927 if (new_cmd) { 3928 mptsas_scsi_destroy_pkt(ap, pkt); 3929 } 3930 return ((struct scsi_pkt *)NULL); 3931 } 3932 3933 get_dma_cookies: 3934 cmd->cmd_flags |= CFLAG_DMAVALID; 3935 ASSERT(cmd->cmd_cookiec > 0); 3936 3937 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) { 3938 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n", 3939 cmd->cmd_cookiec); 3940 bioerror(bp, EINVAL); 3941 if (new_cmd) { 3942 mptsas_scsi_destroy_pkt(ap, pkt); 3943 } 3944 return ((struct scsi_pkt *)NULL); 3945 } 3946 3947 /* 3948 * Allocate extra SGL buffer if needed. 3949 */ 3950 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) && 3951 (cmd->cmd_extra_frames == NULL)) { 3952 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) == 3953 DDI_FAILURE) { 3954 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc " 3955 "failed"); 3956 bioerror(bp, ENOMEM); 3957 if (new_cmd) { 3958 mptsas_scsi_destroy_pkt(ap, pkt); 3959 } 3960 return ((struct scsi_pkt *)NULL); 3961 } 3962 } 3963 3964 /* 3965 * Always use scatter-gather transfer 3966 * Use the loop below to store physical addresses of 3967 * DMA segments, from the DMA cookies, into your HBA's 3968 * scatter-gather list. 3969 * We need to ensure we have enough kmem alloc'd 3970 * for the sg entries since we are no longer using an 3971 * array inside mptsas_cmd_t. 3972 * 3973 * We check cmd->cmd_cookiec against oldcookiec so 3974 * the scatter-gather list is correctly allocated 3975 */ 3976 3977 if (oldcookiec != cmd->cmd_cookiec) { 3978 if (cmd->cmd_sg != (mptti_t *)NULL) { 3979 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * 3980 oldcookiec); 3981 cmd->cmd_sg = NULL; 3982 } 3983 } 3984 3985 if (cmd->cmd_sg == (mptti_t *)NULL) { 3986 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3987 cmd->cmd_cookiec), kf); 3988 3989 if (cmd->cmd_sg == (mptti_t *)NULL) { 3990 mptsas_log(mpt, CE_WARN, 3991 "unable to kmem_alloc enough memory " 3992 "for scatter/gather list"); 3993 /* 3994 * if we have an ENOMEM condition we need to behave 3995 * the same way as the rest of this routine 3996 */ 3997 3998 bioerror(bp, ENOMEM); 3999 if (new_cmd) { 4000 mptsas_scsi_destroy_pkt(ap, pkt); 4001 } 4002 return ((struct scsi_pkt *)NULL); 4003 } 4004 } 4005 4006 dmap = cmd->cmd_sg; 4007 4008 ASSERT(cmd->cmd_cookie.dmac_size != 0); 4009 4010 /* 4011 * store the first segment into the S/G list 4012 */ 4013 dmap->count = cmd->cmd_cookie.dmac_size; 4014 dmap->addr.address64.Low = (uint32_t) 4015 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 4016 dmap->addr.address64.High = (uint32_t) 4017 (cmd->cmd_cookie.dmac_laddress >> 32); 4018 4019 /* 4020 * dmacount counts the size of the dma for this window 4021 * (if partial dma is being used). totaldmacount 4022 * keeps track of the total amount of dma we have 4023 * transferred for all the windows (needed to calculate 4024 * the resid value below). 4025 */ 4026 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size; 4027 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 4028 4029 /* 4030 * We already stored the first DMA scatter gather segment, 4031 * start at 1 if we need to store more. 4032 */ 4033 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) { 4034 /* 4035 * Get next DMA cookie 4036 */ 4037 ddi_dma_nextcookie(cmd->cmd_dmahandle, 4038 &cmd->cmd_cookie); 4039 dmap++; 4040 4041 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size; 4042 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 4043 4044 /* 4045 * store the segment parms into the S/G list 4046 */ 4047 dmap->count = cmd->cmd_cookie.dmac_size; 4048 dmap->addr.address64.Low = (uint32_t) 4049 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 4050 dmap->addr.address64.High = (uint32_t) 4051 (cmd->cmd_cookie.dmac_laddress >> 32); 4052 } 4053 4054 /* 4055 * If this was partially allocated we set the resid 4056 * the amount of data NOT transferred in this window 4057 * If there is only one window, the resid will be 0 4058 */ 4059 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount); 4060 NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.", 4061 cmd->cmd_dmacount)); 4062 } 4063 return (pkt); 4064 } 4065 4066 /* 4067 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation 4068 * 4069 * Notes: 4070 * - also frees DMA resources if allocated 4071 * - implicit DMA synchonization 4072 */ 4073 static void 4074 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4075 { 4076 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4077 mptsas_t *mpt = ADDR2MPT(ap); 4078 4079 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p", 4080 ap->a_target, (void *)pkt)); 4081 4082 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4083 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4084 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4085 } 4086 4087 if (cmd->cmd_sg) { 4088 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec); 4089 cmd->cmd_sg = NULL; 4090 } 4091 4092 mptsas_free_extra_sgl_frame(mpt, cmd); 4093 4094 if ((cmd->cmd_flags & 4095 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN | 4096 CFLAG_SCBEXTERN)) == 0) { 4097 cmd->cmd_flags = CFLAG_FREE; 4098 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4099 } else { 4100 boolean_t extrqslen = cmd->cmd_extrqslen != 0; 4101 4102 mptsas_pkt_destroy_extern(mpt, cmd); 4103 4104 /* 4105 * If the packet had the sense data buffer for DMA allocated we 4106 * need to decrease the reference counter. 4107 */ 4108 if (extrqslen) { 4109 mutex_enter(&mpt->m_mutex); 4110 ASSERT(mpt->m_extreq_sense_refcount > 0); 4111 mpt->m_extreq_sense_refcount--; 4112 if (mpt->m_extreq_sense_refcount == 0) 4113 cv_broadcast(&mpt->m_extreq_sense_refcount_cv); 4114 mutex_exit(&mpt->m_mutex); 4115 } 4116 } 4117 } 4118 4119 /* 4120 * kmem cache constructor and destructor: 4121 * When constructing, we bzero the cmd and allocate the dma handle 4122 * When destructing, just free the dma handle 4123 */ 4124 static int 4125 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags) 4126 { 4127 mptsas_cmd_t *cmd = buf; 4128 mptsas_t *mpt = cdrarg; 4129 int (*callback)(caddr_t); 4130 4131 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 4132 4133 NDBG4(("mptsas_kmem_cache_constructor")); 4134 4135 /* 4136 * allocate a dma handle 4137 */ 4138 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback, 4139 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) { 4140 cmd->cmd_dmahandle = NULL; 4141 return (-1); 4142 } 4143 return (0); 4144 } 4145 4146 static void 4147 mptsas_kmem_cache_destructor(void *buf, void *cdrarg) 4148 { 4149 #ifndef __lock_lint 4150 _NOTE(ARGUNUSED(cdrarg)) 4151 #endif 4152 mptsas_cmd_t *cmd = buf; 4153 4154 NDBG4(("mptsas_kmem_cache_destructor")); 4155 4156 if (cmd->cmd_dmahandle) { 4157 ddi_dma_free_handle(&cmd->cmd_dmahandle); 4158 cmd->cmd_dmahandle = NULL; 4159 } 4160 } 4161 4162 static int 4163 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags) 4164 { 4165 mptsas_cache_frames_t *p = buf; 4166 mptsas_t *mpt = cdrarg; 4167 ddi_dma_attr_t frame_dma_attr; 4168 size_t mem_size, alloc_len; 4169 ddi_dma_cookie_t cookie; 4170 uint_t ncookie; 4171 int (*callback)(caddr_t) = (kmflags == KM_SLEEP) 4172 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 4173 4174 frame_dma_attr = mpt->m_msg_dma_attr; 4175 frame_dma_attr.dma_attr_align = 0x10; 4176 frame_dma_attr.dma_attr_sgllen = 1; 4177 4178 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL, 4179 &p->m_dma_hdl) != DDI_SUCCESS) { 4180 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for" 4181 " extra SGL."); 4182 return (DDI_FAILURE); 4183 } 4184 4185 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size; 4186 4187 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr, 4188 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr, 4189 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) { 4190 ddi_dma_free_handle(&p->m_dma_hdl); 4191 p->m_dma_hdl = NULL; 4192 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for" 4193 " extra SGL."); 4194 return (DDI_FAILURE); 4195 } 4196 4197 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr, 4198 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL, 4199 &cookie, &ncookie) != DDI_DMA_MAPPED) { 4200 (void) ddi_dma_mem_free(&p->m_acc_hdl); 4201 ddi_dma_free_handle(&p->m_dma_hdl); 4202 p->m_dma_hdl = NULL; 4203 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for" 4204 " extra SGL"); 4205 return (DDI_FAILURE); 4206 } 4207 4208 /* 4209 * Store the SGL memory address. This chip uses this 4210 * address to dma to and from the driver. The second 4211 * address is the address mpt uses to fill in the SGL. 4212 */ 4213 p->m_phys_addr = cookie.dmac_laddress; 4214 4215 return (DDI_SUCCESS); 4216 } 4217 4218 static void 4219 mptsas_cache_frames_destructor(void *buf, void *cdrarg) 4220 { 4221 #ifndef __lock_lint 4222 _NOTE(ARGUNUSED(cdrarg)) 4223 #endif 4224 mptsas_cache_frames_t *p = buf; 4225 if (p->m_dma_hdl != NULL) { 4226 (void) ddi_dma_unbind_handle(p->m_dma_hdl); 4227 (void) ddi_dma_mem_free(&p->m_acc_hdl); 4228 ddi_dma_free_handle(&p->m_dma_hdl); 4229 p->m_phys_addr = 0; 4230 p->m_frames_addr = NULL; 4231 p->m_dma_hdl = NULL; 4232 p->m_acc_hdl = NULL; 4233 } 4234 4235 } 4236 4237 /* 4238 * Figure out if we need to use a different method for the request 4239 * sense buffer and allocate from the map if necessary. 4240 */ 4241 static boolean_t 4242 mptsas_cmdarqsize(mptsas_t *mpt, mptsas_cmd_t *cmd, size_t senselength, int kf) 4243 { 4244 if (senselength > mpt->m_req_sense_size) { 4245 unsigned long i; 4246 4247 /* Sense length is limited to an 8 bit value in MPI Spec. */ 4248 if (senselength > 255) 4249 senselength = 255; 4250 cmd->cmd_extrqschunks = (senselength + 4251 (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size; 4252 i = (kf == KM_SLEEP ? rmalloc_wait : rmalloc) 4253 (mpt->m_erqsense_map, cmd->cmd_extrqschunks); 4254 4255 if (i == 0) 4256 return (B_FALSE); 4257 4258 cmd->cmd_extrqslen = (uint16_t)senselength; 4259 cmd->cmd_extrqsidx = i - 1; 4260 cmd->cmd_arq_buf = mpt->m_extreq_sense + 4261 (cmd->cmd_extrqsidx * mpt->m_req_sense_size); 4262 } else { 4263 cmd->cmd_rqslen = (uchar_t)senselength; 4264 } 4265 4266 return (B_TRUE); 4267 } 4268 4269 /* 4270 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd) 4271 * for non-standard length cdb, pkt_private, status areas 4272 * if allocation fails, then deallocate all external space and the pkt 4273 */ 4274 /* ARGSUSED */ 4275 static int 4276 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 4277 int cmdlen, int tgtlen, int statuslen, int kf) 4278 { 4279 caddr_t cdbp, scbp, tgt; 4280 4281 NDBG3(("mptsas_pkt_alloc_extern: " 4282 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x", 4283 (void *)cmd, cmdlen, tgtlen, statuslen, kf)); 4284 4285 tgt = cdbp = scbp = NULL; 4286 cmd->cmd_scblen = statuslen; 4287 cmd->cmd_privlen = (uchar_t)tgtlen; 4288 4289 if (cmdlen > sizeof (cmd->cmd_cdb)) { 4290 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) { 4291 goto fail; 4292 } 4293 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp; 4294 cmd->cmd_flags |= CFLAG_CDBEXTERN; 4295 } 4296 if (tgtlen > PKT_PRIV_LEN) { 4297 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) { 4298 goto fail; 4299 } 4300 cmd->cmd_flags |= CFLAG_PRIVEXTERN; 4301 cmd->cmd_pkt->pkt_private = tgt; 4302 } 4303 if (statuslen > EXTCMDS_STATUS_SIZE) { 4304 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) { 4305 goto fail; 4306 } 4307 cmd->cmd_flags |= CFLAG_SCBEXTERN; 4308 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp; 4309 4310 /* allocate sense data buf for DMA */ 4311 if (mptsas_cmdarqsize(mpt, cmd, statuslen - 4312 MPTSAS_GET_ITEM_OFF(struct scsi_arq_status, sts_sensedata), 4313 kf) == B_FALSE) 4314 goto fail; 4315 } 4316 return (0); 4317 fail: 4318 mptsas_pkt_destroy_extern(mpt, cmd); 4319 return (1); 4320 } 4321 4322 /* 4323 * deallocate external pkt space and deallocate the pkt 4324 */ 4325 static void 4326 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd) 4327 { 4328 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd)); 4329 4330 if (cmd->cmd_flags & CFLAG_FREE) { 4331 mptsas_log(mpt, CE_PANIC, 4332 "mptsas_pkt_destroy_extern: freeing free packet"); 4333 _NOTE(NOT_REACHED) 4334 /* NOTREACHED */ 4335 } 4336 if (cmd->cmd_extrqslen != 0) { 4337 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks, 4338 cmd->cmd_extrqsidx + 1); 4339 } 4340 if (cmd->cmd_flags & CFLAG_CDBEXTERN) { 4341 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen); 4342 } 4343 if (cmd->cmd_flags & CFLAG_SCBEXTERN) { 4344 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen); 4345 } 4346 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) { 4347 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen); 4348 } 4349 cmd->cmd_flags = CFLAG_FREE; 4350 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4351 } 4352 4353 /* 4354 * tran_sync_pkt(9E) - explicit DMA synchronization 4355 */ 4356 /*ARGSUSED*/ 4357 static void 4358 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4359 { 4360 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4361 4362 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p", 4363 ap->a_target, (void *)pkt)); 4364 4365 if (cmd->cmd_dmahandle) { 4366 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4367 (cmd->cmd_flags & CFLAG_DMASEND) ? 4368 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 4369 } 4370 } 4371 4372 /* 4373 * tran_dmafree(9E) - deallocate DMA resources allocated for command 4374 */ 4375 /*ARGSUSED*/ 4376 static void 4377 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 4378 { 4379 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4380 mptsas_t *mpt = ADDR2MPT(ap); 4381 4382 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p", 4383 ap->a_target, (void *)pkt)); 4384 4385 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4386 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4387 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4388 } 4389 4390 mptsas_free_extra_sgl_frame(mpt, cmd); 4391 } 4392 4393 static void 4394 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd) 4395 { 4396 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 4397 (!(cmd->cmd_flags & CFLAG_DMASEND))) { 4398 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4399 DDI_DMA_SYNC_FORCPU); 4400 } 4401 (*pkt->pkt_comp)(pkt); 4402 } 4403 4404 static void 4405 mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame, 4406 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint32_t end_flags) 4407 { 4408 pMpi2SGESimple64_t sge; 4409 mptti_t *dmap; 4410 uint32_t flags; 4411 4412 dmap = cmd->cmd_sg; 4413 4414 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4415 while (cookiec--) { 4416 ddi_put32(acc_hdl, 4417 &sge->Address.Low, dmap->addr.address64.Low); 4418 ddi_put32(acc_hdl, 4419 &sge->Address.High, dmap->addr.address64.High); 4420 ddi_put32(acc_hdl, &sge->FlagsLength, 4421 dmap->count); 4422 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4423 flags |= ((uint32_t) 4424 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4425 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4426 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4427 MPI2_SGE_FLAGS_SHIFT); 4428 4429 /* 4430 * If this is the last cookie, we set the flags 4431 * to indicate so 4432 */ 4433 if (cookiec == 0) { 4434 flags |= end_flags; 4435 } 4436 if (cmd->cmd_flags & CFLAG_DMASEND) { 4437 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC << 4438 MPI2_SGE_FLAGS_SHIFT); 4439 } else { 4440 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST << 4441 MPI2_SGE_FLAGS_SHIFT); 4442 } 4443 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4444 dmap++; 4445 sge++; 4446 } 4447 } 4448 4449 static void 4450 mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd, 4451 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4452 { 4453 pMpi2SGESimple64_t sge; 4454 pMpi2SGEChain64_t sgechain; 4455 uint64_t nframe_phys_addr; 4456 uint_t cookiec; 4457 mptti_t *dmap; 4458 uint32_t flags; 4459 4460 /* 4461 * Save the number of entries in the DMA 4462 * Scatter/Gather list 4463 */ 4464 cookiec = cmd->cmd_cookiec; 4465 4466 /* 4467 * Hereby we start to deal with multiple frames. 4468 * The process is as follows: 4469 * 1. Determine how many frames are needed for SGL element 4470 * storage; Note that all frames are stored in contiguous 4471 * memory space and in 64-bit DMA mode each element is 4472 * 3 double-words (12 bytes) long. 4473 * 2. Fill up the main frame. We need to do this separately 4474 * since it contains the SCSI IO request header and needs 4475 * dedicated processing. Note that the last 4 double-words 4476 * of the SCSI IO header is for SGL element storage 4477 * (MPI2_SGE_IO_UNION). 4478 * 3. Fill the chain element in the main frame, so the DMA 4479 * engine can use the following frames. 4480 * 4. Enter a loop to fill the remaining frames. Note that the 4481 * last frame contains no chain element. The remaining 4482 * frames go into the mpt SGL buffer allocated on the fly, 4483 * not immediately following the main message frame, as in 4484 * Gen1. 4485 * Some restrictions: 4486 * 1. For 64-bit DMA, the simple element and chain element 4487 * are both of 3 double-words (12 bytes) in size, even 4488 * though all frames are stored in the first 4G of mem 4489 * range and the higher 32-bits of the address are always 0. 4490 * 2. On some controllers (like the 1064/1068), a frame can 4491 * hold SGL elements with the last 1 or 2 double-words 4492 * (4 or 8 bytes) un-used. On these controllers, we should 4493 * recognize that there's not enough room for another SGL 4494 * element and move the sge pointer to the next frame. 4495 */ 4496 int i, j, k, l, frames, sgemax; 4497 int temp; 4498 uint8_t chainflags; 4499 uint16_t chainlength; 4500 mptsas_cache_frames_t *p; 4501 4502 /* 4503 * Sgemax is the number of SGE's that will fit 4504 * each extra frame and frames is total 4505 * number of frames we'll need. 1 sge entry per 4506 * frame is reseverd for the chain element thus the -1 below. 4507 */ 4508 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) 4509 - 1); 4510 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4511 4512 /* 4513 * A little check to see if we need to round up the number 4514 * of frames we need 4515 */ 4516 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4517 sgemax) > 1) { 4518 frames = (temp + 1); 4519 } else { 4520 frames = temp; 4521 } 4522 dmap = cmd->cmd_sg; 4523 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4524 4525 /* 4526 * First fill in the main frame 4527 */ 4528 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1; 4529 mptsas_sge_mainframe(cmd, frame, acc_hdl, j, 4530 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) << 4531 MPI2_SGE_FLAGS_SHIFT)); 4532 dmap += j; 4533 sge += j; 4534 j++; 4535 4536 /* 4537 * Fill in the chain element in the main frame. 4538 * About calculation on ChainOffset: 4539 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4540 * in the end reserved for SGL element storage 4541 * (MPI2_SGE_IO_UNION); we should count it in our 4542 * calculation. See its definition in the header file. 4543 * 2. Constant j is the counter of the current SGL element 4544 * that will be processed, and (j - 1) is the number of 4545 * SGL elements that have been processed (stored in the 4546 * main frame). 4547 * 3. ChainOffset value should be in units of double-words (4 4548 * bytes) so the last value should be divided by 4. 4549 */ 4550 ddi_put8(acc_hdl, &frame->ChainOffset, 4551 (sizeof (MPI2_SCSI_IO_REQUEST) - 4552 sizeof (MPI2_SGE_IO_UNION) + 4553 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4554 sgechain = (pMpi2SGEChain64_t)sge; 4555 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4556 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4557 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4558 ddi_put8(acc_hdl, &sgechain->Flags, chainflags); 4559 4560 /* 4561 * The size of the next frame is the accurate size of space 4562 * (in bytes) used to store the SGL elements. j is the counter 4563 * of SGL elements. (j - 1) is the number of SGL elements that 4564 * have been processed (stored in frames). 4565 */ 4566 if (frames >= 2) { 4567 ASSERT(mpt->m_req_frame_size >= sizeof (MPI2_SGE_SIMPLE64)); 4568 chainlength = mpt->m_req_frame_size / 4569 sizeof (MPI2_SGE_SIMPLE64) * 4570 sizeof (MPI2_SGE_SIMPLE64); 4571 } else { 4572 chainlength = ((cookiec - (j - 1)) * 4573 sizeof (MPI2_SGE_SIMPLE64)); 4574 } 4575 4576 p = cmd->cmd_extra_frames; 4577 4578 ddi_put16(acc_hdl, &sgechain->Length, chainlength); 4579 ddi_put32(acc_hdl, &sgechain->Address.Low, p->m_phys_addr); 4580 ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr >> 32); 4581 4582 /* 4583 * If there are more than 2 frames left we have to 4584 * fill in the next chain offset to the location of 4585 * the chain element in the next frame. 4586 * sgemax is the number of simple elements in an extra 4587 * frame. Note that the value NextChainOffset should be 4588 * in double-words (4 bytes). 4589 */ 4590 if (frames >= 2) { 4591 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 4592 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4593 } else { 4594 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0); 4595 } 4596 4597 /* 4598 * Jump to next frame; 4599 * Starting here, chain buffers go into the per command SGL. 4600 * This buffer is allocated when chain buffers are needed. 4601 */ 4602 sge = (pMpi2SGESimple64_t)p->m_frames_addr; 4603 i = cookiec; 4604 4605 /* 4606 * Start filling in frames with SGE's. If we 4607 * reach the end of frame and still have SGE's 4608 * to fill we need to add a chain element and 4609 * use another frame. j will be our counter 4610 * for what cookie we are at and i will be 4611 * the total cookiec. k is the current frame 4612 */ 4613 for (k = 1; k <= frames; k++) { 4614 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4615 4616 /* 4617 * If we have reached the end of frame 4618 * and we have more SGE's to fill in 4619 * we have to fill the final entry 4620 * with a chain element and then 4621 * continue to the next frame 4622 */ 4623 if ((l == (sgemax + 1)) && (k != frames)) { 4624 sgechain = (pMpi2SGEChain64_t)sge; 4625 j--; 4626 chainflags = ( 4627 MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4628 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4629 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4630 ddi_put8(p->m_acc_hdl, 4631 &sgechain->Flags, chainflags); 4632 /* 4633 * k is the frame counter and (k + 1) 4634 * is the number of the next frame. 4635 * Note that frames are in contiguous 4636 * memory space. 4637 */ 4638 nframe_phys_addr = p->m_phys_addr + 4639 (mpt->m_req_frame_size * k); 4640 ddi_put32(p->m_acc_hdl, 4641 &sgechain->Address.Low, 4642 nframe_phys_addr); 4643 ddi_put32(p->m_acc_hdl, 4644 &sgechain->Address.High, 4645 nframe_phys_addr >> 32); 4646 4647 /* 4648 * If there are more than 2 frames left 4649 * we have to next chain offset to 4650 * the location of the chain element 4651 * in the next frame and fill in the 4652 * length of the next chain 4653 */ 4654 if ((frames - k) >= 2) { 4655 ddi_put8(p->m_acc_hdl, 4656 &sgechain->NextChainOffset, 4657 (sgemax * 4658 sizeof (MPI2_SGE_SIMPLE64)) 4659 >> 2); 4660 ddi_put16(p->m_acc_hdl, 4661 &sgechain->Length, 4662 mpt->m_req_frame_size / 4663 sizeof (MPI2_SGE_SIMPLE64) * 4664 sizeof (MPI2_SGE_SIMPLE64)); 4665 } else { 4666 /* 4667 * This is the last frame. Set 4668 * the NextChainOffset to 0 and 4669 * Length is the total size of 4670 * all remaining simple elements 4671 */ 4672 ddi_put8(p->m_acc_hdl, 4673 &sgechain->NextChainOffset, 4674 0); 4675 ddi_put16(p->m_acc_hdl, 4676 &sgechain->Length, 4677 (cookiec - j) * 4678 sizeof (MPI2_SGE_SIMPLE64)); 4679 } 4680 4681 /* Jump to the next frame */ 4682 sge = (pMpi2SGESimple64_t) 4683 ((char *)p->m_frames_addr + 4684 (int)mpt->m_req_frame_size * k); 4685 4686 continue; 4687 } 4688 4689 ddi_put32(p->m_acc_hdl, 4690 &sge->Address.Low, 4691 dmap->addr.address64.Low); 4692 ddi_put32(p->m_acc_hdl, 4693 &sge->Address.High, 4694 dmap->addr.address64.High); 4695 ddi_put32(p->m_acc_hdl, 4696 &sge->FlagsLength, dmap->count); 4697 flags = ddi_get32(p->m_acc_hdl, 4698 &sge->FlagsLength); 4699 flags |= ((uint32_t)( 4700 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4701 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4702 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4703 MPI2_SGE_FLAGS_SHIFT); 4704 4705 /* 4706 * If we are at the end of the frame and 4707 * there is another frame to fill in 4708 * we set the last simple element as last 4709 * element 4710 */ 4711 if ((l == sgemax) && (k != frames)) { 4712 flags |= ((uint32_t) 4713 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4714 MPI2_SGE_FLAGS_SHIFT); 4715 } 4716 4717 /* 4718 * If this is the final cookie we 4719 * indicate it by setting the flags 4720 */ 4721 if (j == i) { 4722 flags |= ((uint32_t) 4723 (MPI2_SGE_FLAGS_LAST_ELEMENT | 4724 MPI2_SGE_FLAGS_END_OF_BUFFER | 4725 MPI2_SGE_FLAGS_END_OF_LIST) << 4726 MPI2_SGE_FLAGS_SHIFT); 4727 } 4728 if (cmd->cmd_flags & CFLAG_DMASEND) { 4729 flags |= 4730 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4731 MPI2_SGE_FLAGS_SHIFT); 4732 } else { 4733 flags |= 4734 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4735 MPI2_SGE_FLAGS_SHIFT); 4736 } 4737 ddi_put32(p->m_acc_hdl, 4738 &sge->FlagsLength, flags); 4739 dmap++; 4740 sge++; 4741 } 4742 } 4743 4744 /* 4745 * Sync DMA with the chain buffers that were just created 4746 */ 4747 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 4748 } 4749 4750 static void 4751 mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame, 4752 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint8_t end_flag) 4753 { 4754 pMpi2IeeeSgeSimple64_t ieeesge; 4755 mptti_t *dmap; 4756 uint8_t flags; 4757 4758 dmap = cmd->cmd_sg; 4759 4760 NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec, 4761 cmd->cmd_flags & CFLAG_DMASEND?"Out":"In")); 4762 4763 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL); 4764 while (cookiec--) { 4765 ddi_put32(acc_hdl, 4766 &ieeesge->Address.Low, dmap->addr.address64.Low); 4767 ddi_put32(acc_hdl, 4768 &ieeesge->Address.High, dmap->addr.address64.High); 4769 ddi_put32(acc_hdl, &ieeesge->Length, 4770 dmap->count); 4771 NDBG1(("mptsas_ieee_sge_mainframe: len=%d", dmap->count)); 4772 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 4773 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 4774 4775 /* 4776 * If this is the last cookie, we set the flags 4777 * to indicate so 4778 */ 4779 if (cookiec == 0) { 4780 flags |= end_flag; 4781 } 4782 4783 ddi_put8(acc_hdl, &ieeesge->Flags, flags); 4784 dmap++; 4785 ieeesge++; 4786 } 4787 } 4788 4789 static void 4790 mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd, 4791 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4792 { 4793 pMpi2IeeeSgeSimple64_t ieeesge; 4794 pMpi25IeeeSgeChain64_t ieeesgechain; 4795 uint64_t nframe_phys_addr; 4796 uint_t cookiec; 4797 mptti_t *dmap; 4798 uint8_t flags; 4799 4800 /* 4801 * Save the number of entries in the DMA 4802 * Scatter/Gather list 4803 */ 4804 cookiec = cmd->cmd_cookiec; 4805 4806 NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec)); 4807 4808 /* 4809 * Hereby we start to deal with multiple frames. 4810 * The process is as follows: 4811 * 1. Determine how many frames are needed for SGL element 4812 * storage; Note that all frames are stored in contiguous 4813 * memory space and in 64-bit DMA mode each element is 4814 * 4 double-words (16 bytes) long. 4815 * 2. Fill up the main frame. We need to do this separately 4816 * since it contains the SCSI IO request header and needs 4817 * dedicated processing. Note that the last 4 double-words 4818 * of the SCSI IO header is for SGL element storage 4819 * (MPI2_SGE_IO_UNION). 4820 * 3. Fill the chain element in the main frame, so the DMA 4821 * engine can use the following frames. 4822 * 4. Enter a loop to fill the remaining frames. Note that the 4823 * last frame contains no chain element. The remaining 4824 * frames go into the mpt SGL buffer allocated on the fly, 4825 * not immediately following the main message frame, as in 4826 * Gen1. 4827 * Restrictions: 4828 * For 64-bit DMA, the simple element and chain element 4829 * are both of 4 double-words (16 bytes) in size, even 4830 * though all frames are stored in the first 4G of mem 4831 * range and the higher 32-bits of the address are always 0. 4832 */ 4833 int i, j, k, l, frames, sgemax; 4834 int temp; 4835 uint8_t chainflags; 4836 uint32_t chainlength; 4837 mptsas_cache_frames_t *p; 4838 4839 /* 4840 * Sgemax is the number of SGE's that will fit 4841 * each extra frame and frames is total 4842 * number of frames we'll need. 1 sge entry per 4843 * frame is reseverd for the chain element thus the -1 below. 4844 */ 4845 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64)) 4846 - 1); 4847 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4848 4849 /* 4850 * A little check to see if we need to round up the number 4851 * of frames we need 4852 */ 4853 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4854 sgemax) > 1) { 4855 frames = (temp + 1); 4856 } else { 4857 frames = temp; 4858 } 4859 NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames)); 4860 dmap = cmd->cmd_sg; 4861 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL); 4862 4863 /* 4864 * First fill in the main frame 4865 */ 4866 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1; 4867 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0); 4868 dmap += j; 4869 ieeesge += j; 4870 j++; 4871 4872 /* 4873 * Fill in the chain element in the main frame. 4874 * About calculation on ChainOffset: 4875 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4876 * in the end reserved for SGL element storage 4877 * (MPI2_SGE_IO_UNION); we should count it in our 4878 * calculation. See its definition in the header file. 4879 * 2. Constant j is the counter of the current SGL element 4880 * that will be processed, and (j - 1) is the number of 4881 * SGL elements that have been processed (stored in the 4882 * main frame). 4883 * 3. ChainOffset value should be in units of quad-words (16 4884 * bytes) so the last value should be divided by 16. 4885 */ 4886 ddi_put8(acc_hdl, &frame->ChainOffset, 4887 (sizeof (MPI2_SCSI_IO_REQUEST) - 4888 sizeof (MPI2_SGE_IO_UNION) + 4889 (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4); 4890 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge; 4891 chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 4892 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 4893 ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags); 4894 4895 /* 4896 * The size of the next frame is the accurate size of space 4897 * (in bytes) used to store the SGL elements. j is the counter 4898 * of SGL elements. (j - 1) is the number of SGL elements that 4899 * have been processed (stored in frames). 4900 */ 4901 if (frames >= 2) { 4902 ASSERT(mpt->m_req_frame_size >= 4903 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4904 chainlength = mpt->m_req_frame_size / 4905 sizeof (MPI2_IEEE_SGE_SIMPLE64) * 4906 sizeof (MPI2_IEEE_SGE_SIMPLE64); 4907 } else { 4908 chainlength = ((cookiec - (j - 1)) * 4909 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4910 } 4911 4912 p = cmd->cmd_extra_frames; 4913 4914 ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength); 4915 ddi_put32(acc_hdl, &ieeesgechain->Address.Low, p->m_phys_addr); 4916 ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr >> 32); 4917 4918 /* 4919 * If there are more than 2 frames left we have to 4920 * fill in the next chain offset to the location of 4921 * the chain element in the next frame. 4922 * sgemax is the number of simple elements in an extra 4923 * frame. Note that the value NextChainOffset should be 4924 * in double-words (4 bytes). 4925 */ 4926 if (frames >= 2) { 4927 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 4928 (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4); 4929 } else { 4930 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0); 4931 } 4932 4933 /* 4934 * Jump to next frame; 4935 * Starting here, chain buffers go into the per command SGL. 4936 * This buffer is allocated when chain buffers are needed. 4937 */ 4938 ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr; 4939 i = cookiec; 4940 4941 /* 4942 * Start filling in frames with SGE's. If we 4943 * reach the end of frame and still have SGE's 4944 * to fill we need to add a chain element and 4945 * use another frame. j will be our counter 4946 * for what cookie we are at and i will be 4947 * the total cookiec. k is the current frame 4948 */ 4949 for (k = 1; k <= frames; k++) { 4950 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4951 4952 /* 4953 * If we have reached the end of frame 4954 * and we have more SGE's to fill in 4955 * we have to fill the final entry 4956 * with a chain element and then 4957 * continue to the next frame 4958 */ 4959 if ((l == (sgemax + 1)) && (k != frames)) { 4960 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge; 4961 j--; 4962 chainflags = 4963 MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 4964 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 4965 ddi_put8(p->m_acc_hdl, 4966 &ieeesgechain->Flags, chainflags); 4967 /* 4968 * k is the frame counter and (k + 1) 4969 * is the number of the next frame. 4970 * Note that frames are in contiguous 4971 * memory space. 4972 */ 4973 nframe_phys_addr = p->m_phys_addr + 4974 (mpt->m_req_frame_size * k); 4975 ddi_put32(p->m_acc_hdl, 4976 &ieeesgechain->Address.Low, 4977 nframe_phys_addr); 4978 ddi_put32(p->m_acc_hdl, 4979 &ieeesgechain->Address.High, 4980 nframe_phys_addr >> 32); 4981 4982 /* 4983 * If there are more than 2 frames left 4984 * we have to next chain offset to 4985 * the location of the chain element 4986 * in the next frame and fill in the 4987 * length of the next chain 4988 */ 4989 if ((frames - k) >= 2) { 4990 ddi_put8(p->m_acc_hdl, 4991 &ieeesgechain->NextChainOffset, 4992 (sgemax * 4993 sizeof (MPI2_IEEE_SGE_SIMPLE64)) 4994 >> 4); 4995 ASSERT(mpt->m_req_frame_size >= 4996 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4997 ddi_put32(p->m_acc_hdl, 4998 &ieeesgechain->Length, 4999 mpt->m_req_frame_size / 5000 sizeof (MPI2_IEEE_SGE_SIMPLE64) * 5001 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 5002 } else { 5003 /* 5004 * This is the last frame. Set 5005 * the NextChainOffset to 0 and 5006 * Length is the total size of 5007 * all remaining simple elements 5008 */ 5009 ddi_put8(p->m_acc_hdl, 5010 &ieeesgechain->NextChainOffset, 5011 0); 5012 ddi_put32(p->m_acc_hdl, 5013 &ieeesgechain->Length, 5014 (cookiec - j) * 5015 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 5016 } 5017 5018 /* Jump to the next frame */ 5019 ieeesge = (pMpi2IeeeSgeSimple64_t) 5020 ((char *)p->m_frames_addr + 5021 (int)mpt->m_req_frame_size * k); 5022 5023 continue; 5024 } 5025 5026 ddi_put32(p->m_acc_hdl, 5027 &ieeesge->Address.Low, 5028 dmap->addr.address64.Low); 5029 ddi_put32(p->m_acc_hdl, 5030 &ieeesge->Address.High, 5031 dmap->addr.address64.High); 5032 ddi_put32(p->m_acc_hdl, 5033 &ieeesge->Length, dmap->count); 5034 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 5035 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 5036 5037 /* 5038 * If we are at the end of the frame and 5039 * there is another frame to fill in 5040 * do we need to do anything? 5041 * if ((l == sgemax) && (k != frames)) { 5042 * } 5043 */ 5044 5045 /* 5046 * If this is the final cookie set end of list. 5047 */ 5048 if (j == i) { 5049 flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 5050 } 5051 5052 ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags); 5053 dmap++; 5054 ieeesge++; 5055 } 5056 } 5057 5058 /* 5059 * Sync DMA with the chain buffers that were just created 5060 */ 5061 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 5062 } 5063 5064 static void 5065 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control, 5066 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 5067 { 5068 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID); 5069 5070 NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec)); 5071 5072 /* 5073 * Set read/write bit in control. 5074 */ 5075 if (cmd->cmd_flags & CFLAG_DMASEND) { 5076 *control |= MPI2_SCSIIO_CONTROL_WRITE; 5077 } else { 5078 *control |= MPI2_SCSIIO_CONTROL_READ; 5079 } 5080 5081 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount); 5082 5083 /* 5084 * We have 4 cases here. First where we can fit all the 5085 * SG elements into the main frame, and the case 5086 * where we can't. The SG element is also different when using 5087 * MPI2.5 interface. 5088 * If we have more cookies than we can attach to a frame 5089 * we will need to use a chain element to point 5090 * a location of memory where the rest of the S/G 5091 * elements reside. 5092 */ 5093 if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) { 5094 if (mpt->m_MPI25) { 5095 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, 5096 cmd->cmd_cookiec, 5097 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 5098 } else { 5099 mptsas_sge_mainframe(cmd, frame, acc_hdl, 5100 cmd->cmd_cookiec, 5101 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT 5102 | MPI2_SGE_FLAGS_END_OF_BUFFER 5103 | MPI2_SGE_FLAGS_END_OF_LIST) << 5104 MPI2_SGE_FLAGS_SHIFT)); 5105 } 5106 } else { 5107 if (mpt->m_MPI25) { 5108 mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl); 5109 } else { 5110 mptsas_sge_chain(mpt, cmd, frame, acc_hdl); 5111 } 5112 } 5113 } 5114 5115 /* 5116 * Interrupt handling 5117 * Utility routine. Poll for status of a command sent to HBA 5118 * without interrupts (a FLAG_NOINTR command). 5119 */ 5120 int 5121 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime) 5122 { 5123 int rval = TRUE; 5124 5125 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd)); 5126 5127 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 5128 mptsas_restart_hba(mpt); 5129 } 5130 5131 /* 5132 * Wait, using drv_usecwait(), long enough for the command to 5133 * reasonably return from the target if the target isn't 5134 * "dead". A polled command may well be sent from scsi_poll, and 5135 * there are retries built in to scsi_poll if the transport 5136 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second 5137 * and retries the transport up to scsi_poll_busycnt times 5138 * (currently 60) if 5139 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or 5140 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY 5141 * 5142 * limit the waiting to avoid a hang in the event that the 5143 * cmd never gets started but we are still receiving interrupts 5144 */ 5145 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) { 5146 if (mptsas_wait_intr(mpt, polltime) == FALSE) { 5147 NDBG5(("mptsas_poll: command incomplete")); 5148 rval = FALSE; 5149 break; 5150 } 5151 } 5152 5153 if (rval == FALSE) { 5154 5155 /* 5156 * this isn't supposed to happen, the hba must be wedged 5157 * Mark this cmd as a timeout. 5158 */ 5159 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT, 5160 (STAT_TIMEOUT|STAT_ABORTED)); 5161 5162 if (poll_cmd->cmd_queued == FALSE) { 5163 5164 NDBG5(("mptsas_poll: not on waitq")); 5165 5166 poll_cmd->cmd_pkt->pkt_state |= 5167 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD); 5168 } else { 5169 5170 /* find and remove it from the waitq */ 5171 NDBG5(("mptsas_poll: delete from waitq")); 5172 mptsas_waitq_delete(mpt, poll_cmd); 5173 } 5174 5175 } 5176 mptsas_fma_check(mpt, poll_cmd); 5177 NDBG5(("mptsas_poll: done")); 5178 return (rval); 5179 } 5180 5181 /* 5182 * Used for polling cmds and TM function 5183 */ 5184 static int 5185 mptsas_wait_intr(mptsas_t *mpt, int polltime) 5186 { 5187 int cnt; 5188 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5189 uint32_t int_mask; 5190 5191 NDBG5(("mptsas_wait_intr")); 5192 5193 mpt->m_polled_intr = 1; 5194 5195 /* 5196 * Get the current interrupt mask and disable interrupts. When 5197 * re-enabling ints, set mask to saved value. 5198 */ 5199 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask); 5200 MPTSAS_DISABLE_INTR(mpt); 5201 5202 /* 5203 * Keep polling for at least (polltime * 1000) seconds 5204 */ 5205 for (cnt = 0; cnt < polltime; cnt++) { 5206 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5207 DDI_DMA_SYNC_FORCPU); 5208 5209 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5210 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5211 5212 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5213 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5214 ddi_get32(mpt->m_acc_post_queue_hdl, 5215 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5216 drv_usecwait(1000); 5217 continue; 5218 } 5219 5220 /* 5221 * The reply is valid, process it according to its 5222 * type. 5223 */ 5224 mptsas_process_intr(mpt, reply_desc_union); 5225 5226 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5227 mpt->m_post_index = 0; 5228 } 5229 5230 /* 5231 * Update the global reply index 5232 */ 5233 ddi_put32(mpt->m_datap, 5234 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5235 mpt->m_polled_intr = 0; 5236 5237 /* 5238 * Re-enable interrupts and quit. 5239 */ 5240 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, 5241 int_mask); 5242 return (TRUE); 5243 5244 } 5245 5246 /* 5247 * Clear polling flag, re-enable interrupts and quit. 5248 */ 5249 mpt->m_polled_intr = 0; 5250 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask); 5251 return (FALSE); 5252 } 5253 5254 static void 5255 mptsas_handle_scsi_io_success(mptsas_t *mpt, 5256 pMpi2ReplyDescriptorsUnion_t reply_desc) 5257 { 5258 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success; 5259 uint16_t SMID; 5260 mptsas_slots_t *slots = mpt->m_active; 5261 mptsas_cmd_t *cmd = NULL; 5262 struct scsi_pkt *pkt; 5263 5264 ASSERT(mutex_owned(&mpt->m_mutex)); 5265 5266 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc; 5267 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID); 5268 5269 /* 5270 * This is a success reply so just complete the IO. First, do a sanity 5271 * check on the SMID. The final slot is used for TM requests, which 5272 * would not come into this reply handler. 5273 */ 5274 if ((SMID == 0) || (SMID > slots->m_n_normal)) { 5275 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 5276 SMID); 5277 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5278 return; 5279 } 5280 5281 cmd = slots->m_slot[SMID]; 5282 5283 /* 5284 * print warning and return if the slot is empty 5285 */ 5286 if (cmd == NULL) { 5287 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 5288 "in slot %d", SMID); 5289 return; 5290 } 5291 5292 pkt = CMD2PKT(cmd); 5293 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 5294 STATE_GOT_STATUS); 5295 if (cmd->cmd_flags & CFLAG_DMAVALID) { 5296 pkt->pkt_state |= STATE_XFERRED_DATA; 5297 } 5298 pkt->pkt_resid = 0; 5299 5300 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 5301 cmd->cmd_flags |= CFLAG_FINISHED; 5302 cv_broadcast(&mpt->m_passthru_cv); 5303 return; 5304 } else { 5305 mptsas_remove_cmd(mpt, cmd); 5306 } 5307 5308 if (cmd->cmd_flags & CFLAG_RETRY) { 5309 /* 5310 * The target returned QFULL or busy, do not add tihs 5311 * pkt to the doneq since the hba will retry 5312 * this cmd. 5313 * 5314 * The pkt has already been resubmitted in 5315 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5316 * Remove this cmd_flag here. 5317 */ 5318 cmd->cmd_flags &= ~CFLAG_RETRY; 5319 } else { 5320 mptsas_doneq_add(mpt, cmd); 5321 } 5322 } 5323 5324 static void 5325 mptsas_handle_address_reply(mptsas_t *mpt, 5326 pMpi2ReplyDescriptorsUnion_t reply_desc) 5327 { 5328 pMpi2AddressReplyDescriptor_t address_reply; 5329 pMPI2DefaultReply_t reply; 5330 mptsas_fw_diagnostic_buffer_t *pBuffer; 5331 uint32_t reply_addr, reply_frame_dma_baseaddr; 5332 uint16_t SMID, iocstatus; 5333 mptsas_slots_t *slots = mpt->m_active; 5334 mptsas_cmd_t *cmd = NULL; 5335 uint8_t function, buffer_type; 5336 m_replyh_arg_t *args; 5337 int reply_frame_no; 5338 5339 ASSERT(mutex_owned(&mpt->m_mutex)); 5340 5341 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc; 5342 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl, 5343 &address_reply->ReplyFrameAddress); 5344 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID); 5345 5346 /* 5347 * If reply frame is not in the proper range we should ignore this 5348 * message and exit the interrupt handler. 5349 */ 5350 reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xffffffffu; 5351 if ((reply_addr < reply_frame_dma_baseaddr) || 5352 (reply_addr >= (reply_frame_dma_baseaddr + 5353 (mpt->m_reply_frame_size * mpt->m_max_replies))) || 5354 ((reply_addr - reply_frame_dma_baseaddr) % 5355 mpt->m_reply_frame_size != 0)) { 5356 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame " 5357 "address 0x%x\n", reply_addr); 5358 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5359 return; 5360 } 5361 5362 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 5363 DDI_DMA_SYNC_FORCPU); 5364 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr - 5365 reply_frame_dma_baseaddr)); 5366 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function); 5367 5368 NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x", 5369 function, reply_addr)); 5370 5371 /* 5372 * don't get slot information and command for events since these values 5373 * don't exist 5374 */ 5375 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) && 5376 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) { 5377 /* 5378 * This could be a TM reply, which use the last allocated SMID, 5379 * so allow for that. 5380 */ 5381 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) { 5382 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of " 5383 "%d\n", SMID); 5384 ddi_fm_service_impact(mpt->m_dip, 5385 DDI_SERVICE_UNAFFECTED); 5386 return; 5387 } 5388 5389 cmd = slots->m_slot[SMID]; 5390 5391 /* 5392 * print warning and return if the slot is empty 5393 */ 5394 if (cmd == NULL) { 5395 mptsas_log(mpt, CE_WARN, "?NULL command for address " 5396 "reply in slot %d", SMID); 5397 return; 5398 } 5399 if ((cmd->cmd_flags & 5400 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) { 5401 cmd->cmd_rfm = reply_addr; 5402 cmd->cmd_flags |= CFLAG_FINISHED; 5403 cv_broadcast(&mpt->m_passthru_cv); 5404 cv_broadcast(&mpt->m_config_cv); 5405 cv_broadcast(&mpt->m_fw_diag_cv); 5406 return; 5407 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) { 5408 mptsas_remove_cmd(mpt, cmd); 5409 } 5410 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID)); 5411 } 5412 /* 5413 * Depending on the function, we need to handle 5414 * the reply frame (and cmd) differently. 5415 */ 5416 switch (function) { 5417 case MPI2_FUNCTION_SCSI_IO_REQUEST: 5418 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd); 5419 break; 5420 case MPI2_FUNCTION_SCSI_TASK_MGMT: 5421 cmd->cmd_rfm = reply_addr; 5422 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply, 5423 cmd); 5424 break; 5425 case MPI2_FUNCTION_FW_DOWNLOAD: 5426 cmd->cmd_flags |= CFLAG_FINISHED; 5427 cv_signal(&mpt->m_fw_cv); 5428 break; 5429 case MPI2_FUNCTION_EVENT_NOTIFICATION: 5430 reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) / 5431 mpt->m_reply_frame_size; 5432 args = &mpt->m_replyh_args[reply_frame_no]; 5433 args->mpt = (void *)mpt; 5434 args->rfm = reply_addr; 5435 5436 /* 5437 * Record the event if its type is enabled in 5438 * this mpt instance by ioctl. 5439 */ 5440 mptsas_record_event(args); 5441 5442 /* 5443 * Handle time critical events 5444 * NOT_RESPONDING/ADDED only now 5445 */ 5446 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) { 5447 /* 5448 * Would not return main process, 5449 * just let taskq resolve ack action 5450 * and ack would be sent in taskq thread 5451 */ 5452 NDBG20(("send mptsas_handle_event_sync success")); 5453 } 5454 5455 if (mpt->m_in_reset) { 5456 NDBG20(("dropping event received during reset")); 5457 return; 5458 } 5459 5460 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event, 5461 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5462 mptsas_log(mpt, CE_WARN, "No memory available" 5463 "for dispatch taskq"); 5464 /* 5465 * Return the reply frame to the free queue. 5466 */ 5467 ddi_put32(mpt->m_acc_free_queue_hdl, 5468 &((uint32_t *)(void *) 5469 mpt->m_free_queue)[mpt->m_free_index], reply_addr); 5470 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5471 DDI_DMA_SYNC_FORDEV); 5472 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5473 mpt->m_free_index = 0; 5474 } 5475 5476 ddi_put32(mpt->m_datap, 5477 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index); 5478 } 5479 return; 5480 case MPI2_FUNCTION_DIAG_BUFFER_POST: 5481 /* 5482 * If SMID is 0, this implies that the reply is due to a 5483 * release function with a status that the buffer has been 5484 * released. Set the buffer flags accordingly. 5485 */ 5486 if (SMID == 0) { 5487 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 5488 &reply->IOCStatus); 5489 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl, 5490 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType)); 5491 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) { 5492 pBuffer = 5493 &mpt->m_fw_diag_buffer_list[buffer_type]; 5494 pBuffer->valid_data = TRUE; 5495 pBuffer->owned_by_firmware = FALSE; 5496 pBuffer->immediate = FALSE; 5497 } 5498 } else { 5499 /* 5500 * Normal handling of diag post reply with SMID. 5501 */ 5502 cmd = slots->m_slot[SMID]; 5503 5504 /* 5505 * print warning and return if the slot is empty 5506 */ 5507 if (cmd == NULL) { 5508 mptsas_log(mpt, CE_WARN, "?NULL command for " 5509 "address reply in slot %d", SMID); 5510 return; 5511 } 5512 cmd->cmd_rfm = reply_addr; 5513 cmd->cmd_flags |= CFLAG_FINISHED; 5514 cv_broadcast(&mpt->m_fw_diag_cv); 5515 } 5516 return; 5517 default: 5518 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function); 5519 break; 5520 } 5521 5522 /* 5523 * Return the reply frame to the free queue. 5524 */ 5525 ddi_put32(mpt->m_acc_free_queue_hdl, 5526 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 5527 reply_addr); 5528 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5529 DDI_DMA_SYNC_FORDEV); 5530 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5531 mpt->m_free_index = 0; 5532 } 5533 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 5534 mpt->m_free_index); 5535 5536 if (cmd->cmd_flags & CFLAG_FW_CMD) 5537 return; 5538 5539 if (cmd->cmd_flags & CFLAG_RETRY) { 5540 /* 5541 * The target returned QFULL or busy, do not add this 5542 * pkt to the doneq since the hba will retry 5543 * this cmd. 5544 * 5545 * The pkt has already been resubmitted in 5546 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5547 * Remove this cmd_flag here. 5548 */ 5549 cmd->cmd_flags &= ~CFLAG_RETRY; 5550 } else { 5551 mptsas_doneq_add(mpt, cmd); 5552 } 5553 } 5554 5555 #ifdef MPTSAS_DEBUG 5556 static uint8_t mptsas_last_sense[256]; 5557 #endif 5558 5559 static void 5560 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 5561 mptsas_cmd_t *cmd) 5562 { 5563 uint8_t scsi_status, scsi_state; 5564 uint16_t ioc_status, cmd_rqs_len; 5565 uint32_t xferred, sensecount, responsedata, loginfo = 0; 5566 struct scsi_pkt *pkt; 5567 struct scsi_arq_status *arqstat; 5568 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5569 uint8_t *sensedata = NULL; 5570 uint64_t sas_wwn; 5571 uint8_t phy; 5572 char wwn_str[MPTSAS_WWN_STRLEN]; 5573 5574 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus); 5575 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5576 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState); 5577 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount); 5578 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount); 5579 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl, 5580 &reply->ResponseInfo); 5581 5582 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 5583 sas_wwn = ptgt->m_addr.mta_wwn; 5584 phy = ptgt->m_phynum; 5585 if (sas_wwn == 0) { 5586 (void) sprintf(wwn_str, "p%x", phy); 5587 } else { 5588 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 5589 } 5590 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 5591 &reply->IOCLogInfo); 5592 mptsas_log(mpt, CE_NOTE, 5593 "?Log info 0x%x received for target %d %s.\n" 5594 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5595 loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status, 5596 scsi_state); 5597 } 5598 5599 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5600 scsi_status, ioc_status, scsi_state)); 5601 5602 pkt = CMD2PKT(cmd); 5603 *(pkt->pkt_scbp) = scsi_status; 5604 5605 if (loginfo == 0x31170000) { 5606 /* 5607 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY 5608 * 0x31170000 comes, that means the device missing delay 5609 * is in progressing, the command need retry later. 5610 */ 5611 *(pkt->pkt_scbp) = STATUS_BUSY; 5612 return; 5613 } 5614 5615 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) && 5616 ((ioc_status & MPI2_IOCSTATUS_MASK) == 5617 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) { 5618 pkt->pkt_reason = CMD_INCOMPLETE; 5619 pkt->pkt_state |= STATE_GOT_BUS; 5620 if (ptgt->m_reset_delay == 0) { 5621 mptsas_set_throttle(mpt, ptgt, 5622 DRAIN_THROTTLE); 5623 } 5624 return; 5625 } 5626 5627 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) { 5628 responsedata &= 0x000000FF; 5629 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) { 5630 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n"); 5631 pkt->pkt_reason = CMD_TLR_OFF; 5632 return; 5633 } 5634 } 5635 5636 5637 switch (scsi_status) { 5638 case MPI2_SCSI_STATUS_CHECK_CONDITION: 5639 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5640 arqstat = (void*)(pkt->pkt_scbp); 5641 arqstat->sts_rqpkt_status = *((struct scsi_status *) 5642 (pkt->pkt_scbp)); 5643 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 5644 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE); 5645 if (cmd->cmd_flags & CFLAG_XARQ) { 5646 pkt->pkt_state |= STATE_XARQ_DONE; 5647 } 5648 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5649 pkt->pkt_state |= STATE_XFERRED_DATA; 5650 } 5651 arqstat->sts_rqpkt_reason = pkt->pkt_reason; 5652 arqstat->sts_rqpkt_state = pkt->pkt_state; 5653 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA; 5654 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics; 5655 sensedata = (uint8_t *)&arqstat->sts_sensedata; 5656 cmd_rqs_len = cmd->cmd_extrqslen ? 5657 cmd->cmd_extrqslen : cmd->cmd_rqslen; 5658 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 5659 DDI_DMA_SYNC_FORKERNEL); 5660 #ifdef MPTSAS_DEBUG 5661 bcopy(cmd->cmd_arq_buf, mptsas_last_sense, 5662 ((cmd_rqs_len >= sizeof (mptsas_last_sense)) ? 5663 sizeof (mptsas_last_sense):cmd_rqs_len)); 5664 #endif 5665 bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata, 5666 ((cmd_rqs_len >= sensecount) ? sensecount : 5667 cmd_rqs_len)); 5668 arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount); 5669 cmd->cmd_flags |= CFLAG_CMDARQ; 5670 /* 5671 * Set proper status for pkt if autosense was valid 5672 */ 5673 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { 5674 struct scsi_status zero_status = { 0 }; 5675 arqstat->sts_rqpkt_status = zero_status; 5676 } 5677 5678 /* 5679 * ASC=0x47 is parity error 5680 * ASC=0x48 is initiator detected error received 5681 */ 5682 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) && 5683 ((scsi_sense_asc(sensedata) == 0x47) || 5684 (scsi_sense_asc(sensedata) == 0x48))) { 5685 mptsas_log(mpt, CE_NOTE, "Aborted_command!"); 5686 } 5687 5688 /* 5689 * ASC/ASCQ=0x3F/0x0E means report_luns data changed 5690 * ASC/ASCQ=0x25/0x00 means invalid lun 5691 */ 5692 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) && 5693 (scsi_sense_asc(sensedata) == 0x3F) && 5694 (scsi_sense_ascq(sensedata) == 0x0E)) || 5695 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) && 5696 (scsi_sense_asc(sensedata) == 0x25) && 5697 (scsi_sense_ascq(sensedata) == 0x00))) { 5698 mptsas_topo_change_list_t *topo_node = NULL; 5699 5700 topo_node = kmem_zalloc( 5701 sizeof (mptsas_topo_change_list_t), 5702 KM_NOSLEEP); 5703 if (topo_node == NULL) { 5704 mptsas_log(mpt, CE_NOTE, "No memory" 5705 "resource for handle SAS dynamic" 5706 "reconfigure.\n"); 5707 break; 5708 } 5709 topo_node->mpt = mpt; 5710 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET; 5711 topo_node->un.phymask = ptgt->m_addr.mta_phymask; 5712 topo_node->devhdl = ptgt->m_devhdl; 5713 topo_node->object = (void *)ptgt; 5714 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED; 5715 5716 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 5717 mptsas_handle_dr, 5718 (void *)topo_node, 5719 DDI_NOSLEEP)) != DDI_SUCCESS) { 5720 kmem_free(topo_node, 5721 sizeof (mptsas_topo_change_list_t)); 5722 mptsas_log(mpt, CE_NOTE, "mptsas start taskq" 5723 "for handle SAS dynamic reconfigure" 5724 "failed. \n"); 5725 } 5726 } 5727 break; 5728 case MPI2_SCSI_STATUS_GOOD: 5729 switch (ioc_status & MPI2_IOCSTATUS_MASK) { 5730 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 5731 pkt->pkt_reason = CMD_DEV_GONE; 5732 pkt->pkt_state |= STATE_GOT_BUS; 5733 if (ptgt->m_reset_delay == 0) { 5734 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5735 } 5736 NDBG31(("lost disk for target%d, command:%x", 5737 Tgt(cmd), pkt->pkt_cdbp[0])); 5738 break; 5739 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 5740 NDBG31(("data overrun: xferred=%d", xferred)); 5741 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5742 pkt->pkt_reason = CMD_DATA_OVR; 5743 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5744 | STATE_SENT_CMD | STATE_GOT_STATUS 5745 | STATE_XFERRED_DATA); 5746 pkt->pkt_resid = 0; 5747 break; 5748 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 5749 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 5750 NDBG31(("data underrun: xferred=%d", xferred)); 5751 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5752 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5753 | STATE_SENT_CMD | STATE_GOT_STATUS); 5754 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5755 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5756 pkt->pkt_state |= STATE_XFERRED_DATA; 5757 } 5758 break; 5759 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 5760 if (cmd->cmd_active_expiration <= gethrtime()) { 5761 /* 5762 * When timeout requested, propagate 5763 * proper reason and statistics to 5764 * target drivers. 5765 */ 5766 mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT, 5767 STAT_BUS_RESET | STAT_TIMEOUT); 5768 } else { 5769 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 5770 STAT_BUS_RESET); 5771 } 5772 break; 5773 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 5774 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 5775 mptsas_set_pkt_reason(mpt, 5776 cmd, CMD_RESET, STAT_DEV_RESET); 5777 break; 5778 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 5779 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 5780 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET); 5781 mptsas_set_pkt_reason(mpt, 5782 cmd, CMD_TERMINATED, STAT_TERMINATED); 5783 break; 5784 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 5785 case MPI2_IOCSTATUS_BUSY: 5786 /* 5787 * set throttles to drain 5788 */ 5789 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 5790 ptgt = refhash_next(mpt->m_targets, ptgt)) { 5791 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5792 } 5793 5794 /* 5795 * retry command 5796 */ 5797 cmd->cmd_flags |= CFLAG_RETRY; 5798 cmd->cmd_pkt_flags |= FLAG_HEAD; 5799 5800 (void) mptsas_accept_pkt(mpt, cmd); 5801 break; 5802 default: 5803 mptsas_log(mpt, CE_WARN, 5804 "unknown ioc_status = %x\n", ioc_status); 5805 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer " 5806 "count = %x, scsi_status = %x", scsi_state, 5807 xferred, scsi_status); 5808 break; 5809 } 5810 break; 5811 case MPI2_SCSI_STATUS_TASK_SET_FULL: 5812 mptsas_handle_qfull(mpt, cmd); 5813 break; 5814 case MPI2_SCSI_STATUS_BUSY: 5815 NDBG31(("scsi_status busy received")); 5816 break; 5817 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT: 5818 NDBG31(("scsi_status reservation conflict received")); 5819 break; 5820 default: 5821 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n", 5822 scsi_status, ioc_status); 5823 mptsas_log(mpt, CE_WARN, 5824 "mptsas_process_intr: invalid scsi status\n"); 5825 break; 5826 } 5827 } 5828 5829 static void 5830 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply, 5831 mptsas_cmd_t *cmd) 5832 { 5833 uint8_t task_type; 5834 uint16_t ioc_status; 5835 uint32_t log_info; 5836 uint16_t dev_handle; 5837 struct scsi_pkt *pkt = CMD2PKT(cmd); 5838 5839 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType); 5840 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5841 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo); 5842 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle); 5843 5844 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5845 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x " 5846 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n", 5847 task_type, ioc_status, log_info, dev_handle); 5848 pkt->pkt_reason = CMD_INCOMPLETE; 5849 return; 5850 } 5851 5852 switch (task_type) { 5853 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 5854 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 5855 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 5856 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA: 5857 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET: 5858 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION: 5859 break; 5860 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 5861 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 5862 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 5863 /* 5864 * Check for invalid DevHandle of 0 in case application 5865 * sends bad command. DevHandle of 0 could cause problems. 5866 */ 5867 if (dev_handle == 0) { 5868 mptsas_log(mpt, CE_WARN, "!Can't flush target with" 5869 " DevHandle of 0."); 5870 } else { 5871 mptsas_flush_target(mpt, dev_handle, Lun(cmd), 5872 task_type); 5873 } 5874 break; 5875 default: 5876 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 5877 task_type); 5878 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status); 5879 break; 5880 } 5881 } 5882 5883 static void 5884 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg) 5885 { 5886 mptsas_t *mpt = arg->mpt; 5887 uint64_t t = arg->t; 5888 mptsas_cmd_t *cmd; 5889 struct scsi_pkt *pkt; 5890 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 5891 5892 mutex_enter(&item->mutex); 5893 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) { 5894 if (!item->doneq) { 5895 cv_wait(&item->cv, &item->mutex); 5896 } 5897 pkt = NULL; 5898 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) { 5899 cmd->cmd_flags |= CFLAG_COMPLETED; 5900 pkt = CMD2PKT(cmd); 5901 } 5902 mutex_exit(&item->mutex); 5903 if (pkt) { 5904 mptsas_pkt_comp(pkt, cmd); 5905 } 5906 mutex_enter(&item->mutex); 5907 } 5908 mutex_exit(&item->mutex); 5909 mutex_enter(&mpt->m_doneq_mutex); 5910 mpt->m_doneq_thread_n--; 5911 cv_broadcast(&mpt->m_doneq_thread_cv); 5912 mutex_exit(&mpt->m_doneq_mutex); 5913 } 5914 5915 5916 /* 5917 * mpt interrupt handler. 5918 */ 5919 static uint_t 5920 mptsas_intr(caddr_t arg1, caddr_t arg2) 5921 { 5922 mptsas_t *mpt = (void *)arg1; 5923 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5924 uchar_t did_reply = FALSE; 5925 5926 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2)); 5927 5928 mutex_enter(&mpt->m_mutex); 5929 5930 /* 5931 * If interrupts are shared by two channels then check whether this 5932 * interrupt is genuinely for this channel by making sure first the 5933 * chip is in high power state. 5934 */ 5935 if ((mpt->m_options & MPTSAS_OPT_PM) && 5936 (mpt->m_power_level != PM_LEVEL_D0)) { 5937 mutex_exit(&mpt->m_mutex); 5938 return (DDI_INTR_UNCLAIMED); 5939 } 5940 5941 /* 5942 * If polling, interrupt was triggered by some shared interrupt because 5943 * IOC interrupts are disabled during polling, so polling routine will 5944 * handle any replies. Considering this, if polling is happening, 5945 * return with interrupt unclaimed. 5946 */ 5947 if (mpt->m_polled_intr) { 5948 mutex_exit(&mpt->m_mutex); 5949 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt"); 5950 return (DDI_INTR_UNCLAIMED); 5951 } 5952 5953 /* 5954 * Read the istat register. 5955 */ 5956 if ((INTPENDING(mpt)) != 0) { 5957 /* 5958 * read fifo until empty. 5959 */ 5960 #ifndef __lock_lint 5961 _NOTE(CONSTCOND) 5962 #endif 5963 while (TRUE) { 5964 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5965 DDI_DMA_SYNC_FORCPU); 5966 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5967 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5968 5969 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5970 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5971 ddi_get32(mpt->m_acc_post_queue_hdl, 5972 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5973 break; 5974 } 5975 5976 /* 5977 * The reply is valid, process it according to its 5978 * type. Also, set a flag for updating the reply index 5979 * after they've all been processed. 5980 */ 5981 did_reply = TRUE; 5982 5983 mptsas_process_intr(mpt, reply_desc_union); 5984 5985 /* 5986 * Increment post index and roll over if needed. 5987 */ 5988 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5989 mpt->m_post_index = 0; 5990 } 5991 } 5992 5993 /* 5994 * Update the global reply index if at least one reply was 5995 * processed. 5996 */ 5997 if (did_reply) { 5998 ddi_put32(mpt->m_datap, 5999 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 6000 } 6001 } else { 6002 mutex_exit(&mpt->m_mutex); 6003 return (DDI_INTR_UNCLAIMED); 6004 } 6005 NDBG1(("mptsas_intr complete")); 6006 6007 /* 6008 * If no helper threads are created, process the doneq in ISR. If 6009 * helpers are created, use the doneq length as a metric to measure the 6010 * load on the interrupt CPU. If it is long enough, which indicates the 6011 * load is heavy, then we deliver the IO completions to the helpers. 6012 * This measurement has some limitations, although it is simple and 6013 * straightforward and works well for most of the cases at present. 6014 */ 6015 if (!mpt->m_doneq_thread_n || 6016 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) { 6017 mptsas_doneq_empty(mpt); 6018 } else { 6019 mptsas_deliver_doneq_thread(mpt); 6020 } 6021 6022 /* 6023 * If there are queued cmd, start them now. 6024 */ 6025 if (mpt->m_waitq != NULL) { 6026 mptsas_restart_waitq(mpt); 6027 } 6028 6029 mutex_exit(&mpt->m_mutex); 6030 return (DDI_INTR_CLAIMED); 6031 } 6032 6033 static void 6034 mptsas_process_intr(mptsas_t *mpt, 6035 pMpi2ReplyDescriptorsUnion_t reply_desc_union) 6036 { 6037 uint8_t reply_type; 6038 6039 ASSERT(mutex_owned(&mpt->m_mutex)); 6040 6041 /* 6042 * The reply is valid, process it according to its 6043 * type. Also, set a flag for updated the reply index 6044 * after they've all been processed. 6045 */ 6046 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 6047 &reply_desc_union->Default.ReplyFlags); 6048 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 6049 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS || 6050 reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) { 6051 mptsas_handle_scsi_io_success(mpt, reply_desc_union); 6052 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 6053 mptsas_handle_address_reply(mpt, reply_desc_union); 6054 } else { 6055 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type); 6056 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 6057 } 6058 6059 /* 6060 * Clear the reply descriptor for re-use and increment 6061 * index. 6062 */ 6063 ddi_put64(mpt->m_acc_post_queue_hdl, 6064 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index], 6065 0xFFFFFFFFFFFFFFFF); 6066 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 6067 DDI_DMA_SYNC_FORDEV); 6068 } 6069 6070 /* 6071 * handle qfull condition 6072 */ 6073 static void 6074 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd) 6075 { 6076 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 6077 6078 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) || 6079 (ptgt->m_qfull_retries == 0)) { 6080 /* 6081 * We have exhausted the retries on QFULL, or, 6082 * the target driver has indicated that it 6083 * wants to handle QFULL itself by setting 6084 * qfull-retries capability to 0. In either case 6085 * we want the target driver's QFULL handling 6086 * to kick in. We do this by having pkt_reason 6087 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL. 6088 */ 6089 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 6090 } else { 6091 if (ptgt->m_reset_delay == 0) { 6092 ptgt->m_t_throttle = 6093 max((ptgt->m_t_ncmds - 2), 0); 6094 } 6095 6096 cmd->cmd_pkt_flags |= FLAG_HEAD; 6097 cmd->cmd_flags &= ~(CFLAG_TRANFLAG); 6098 cmd->cmd_flags |= CFLAG_RETRY; 6099 6100 (void) mptsas_accept_pkt(mpt, cmd); 6101 6102 /* 6103 * when target gives queue full status with no commands 6104 * outstanding (m_t_ncmds == 0), throttle is set to 0 6105 * (HOLD_THROTTLE), and the queue full handling start 6106 * (see psarc/1994/313); if there are commands outstanding, 6107 * throttle is set to (m_t_ncmds - 2) 6108 */ 6109 if (ptgt->m_t_throttle == HOLD_THROTTLE) { 6110 /* 6111 * By setting throttle to QFULL_THROTTLE, we 6112 * avoid submitting new commands and in 6113 * mptsas_restart_cmd find out slots which need 6114 * their throttles to be cleared. 6115 */ 6116 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE); 6117 if (mpt->m_restart_cmd_timeid == 0) { 6118 mpt->m_restart_cmd_timeid = 6119 timeout(mptsas_restart_cmd, mpt, 6120 ptgt->m_qfull_retry_interval); 6121 } 6122 } 6123 } 6124 } 6125 6126 mptsas_phymask_t 6127 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport) 6128 { 6129 mptsas_phymask_t phy_mask = 0; 6130 uint8_t i = 0; 6131 6132 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance)); 6133 6134 ASSERT(mutex_owned(&mpt->m_mutex)); 6135 6136 /* 6137 * If physport is 0xFF, this is a RAID volume. Use phymask of 0. 6138 */ 6139 if (physport == 0xFF) { 6140 return (0); 6141 } 6142 6143 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 6144 if (mpt->m_phy_info[i].attached_devhdl && 6145 (mpt->m_phy_info[i].phy_mask != 0) && 6146 (mpt->m_phy_info[i].port_num == physport)) { 6147 phy_mask = mpt->m_phy_info[i].phy_mask; 6148 break; 6149 } 6150 } 6151 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ", 6152 mpt->m_instance, physport, phy_mask)); 6153 return (phy_mask); 6154 } 6155 6156 /* 6157 * mpt free device handle after device gone, by use of passthrough 6158 */ 6159 static int 6160 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl) 6161 { 6162 Mpi2SasIoUnitControlRequest_t req; 6163 Mpi2SasIoUnitControlReply_t rep; 6164 int ret; 6165 6166 ASSERT(mutex_owned(&mpt->m_mutex)); 6167 6168 /* 6169 * Need to compose a SAS IO Unit Control request message 6170 * and call mptsas_do_passthru() function 6171 */ 6172 bzero(&req, sizeof (req)); 6173 bzero(&rep, sizeof (rep)); 6174 6175 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; 6176 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE; 6177 req.DevHandle = LE_16(devhdl); 6178 6179 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 6180 sizeof (req), sizeof (rep), 0, MPTSAS_PASS_THRU_DIRECTION_NONE, 6181 NULL, 0, 60, FKIOCTL); 6182 if (ret != 0) { 6183 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 6184 "Control error %d", ret); 6185 return (DDI_FAILURE); 6186 } 6187 6188 /* do passthrough success, check the ioc status */ 6189 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 6190 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 6191 "Control IOCStatus %d", LE_16(rep.IOCStatus)); 6192 return (DDI_FAILURE); 6193 } 6194 6195 return (DDI_SUCCESS); 6196 } 6197 6198 /* 6199 * We have a SATA target that has changed, which means the "bridge-port" 6200 * property must be updated to reflect the SAS WWN of the new attachment point. 6201 * This may change if a SATA device changes which bay, and therefore phy, it is 6202 * plugged into. This SATA device may be a multipath virtual device or may be a 6203 * physical device. We have to handle both cases. 6204 */ 6205 static boolean_t 6206 mptsas_update_sata_bridge(mptsas_t *mpt, dev_info_t *parent, 6207 mptsas_target_t *ptgt) 6208 { 6209 int rval; 6210 uint16_t dev_hdl; 6211 uint16_t pdev_hdl; 6212 uint64_t dev_sas_wwn; 6213 uint8_t physport; 6214 uint8_t phy_id; 6215 uint32_t page_address; 6216 uint16_t bay_num, enclosure, io_flags; 6217 uint32_t dev_info; 6218 char uabuf[SCSI_WWN_BUFLEN]; 6219 dev_info_t *dip; 6220 mdi_pathinfo_t *pip; 6221 6222 mutex_enter(&mpt->m_mutex); 6223 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 6224 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)ptgt->m_devhdl; 6225 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 6226 &dev_sas_wwn, &dev_info, &physport, &phy_id, &pdev_hdl, &bay_num, 6227 &enclosure, &io_flags); 6228 mutex_exit(&mpt->m_mutex); 6229 if (rval != DDI_SUCCESS) { 6230 mptsas_log(mpt, CE_WARN, "unable to get SAS page 0 for " 6231 "handle %d", page_address); 6232 return (B_FALSE); 6233 } 6234 6235 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) { 6236 mptsas_log(mpt, CE_WARN, 6237 "mptsas unable to format SATA bridge WWN"); 6238 return (B_FALSE); 6239 } 6240 6241 if (mpt->m_mpxio_enable == TRUE && (pip = mptsas_find_path_addr(parent, 6242 ptgt->m_addr.mta_wwn, 0)) != NULL) { 6243 if (mdi_prop_update_string(pip, SCSI_ADDR_PROP_BRIDGE_PORT, 6244 uabuf) != DDI_SUCCESS) { 6245 mptsas_log(mpt, CE_WARN, 6246 "mptsas unable to create SCSI bridge port " 6247 "property for SATA device"); 6248 return (B_FALSE); 6249 } 6250 return (B_TRUE); 6251 } 6252 6253 if ((dip = mptsas_find_child_addr(parent, ptgt->m_addr.mta_wwn, 6254 0)) != NULL) { 6255 if (ndi_prop_update_string(DDI_DEV_T_NONE, dip, 6256 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != DDI_PROP_SUCCESS) { 6257 mptsas_log(mpt, CE_WARN, 6258 "mptsas unable to create SCSI bridge port " 6259 "property for SATA device"); 6260 return (B_FALSE); 6261 } 6262 return (B_TRUE); 6263 } 6264 6265 mptsas_log(mpt, CE_WARN, "mptsas failed to find dev_info_t or " 6266 "mdi_pathinfo_t for target with WWN %016" PRIx64, 6267 ptgt->m_addr.mta_wwn); 6268 6269 return (B_FALSE); 6270 } 6271 6272 static void 6273 mptsas_update_phymask(mptsas_t *mpt) 6274 { 6275 mptsas_phymask_t mask = 0, phy_mask; 6276 char *phy_mask_name; 6277 uint8_t current_port; 6278 int i, j; 6279 6280 NDBG20(("mptsas%d update phymask ", mpt->m_instance)); 6281 6282 ASSERT(mutex_owned(&mpt->m_mutex)); 6283 6284 (void) mptsas_get_sas_io_unit_page(mpt); 6285 6286 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6287 6288 for (i = 0; i < mpt->m_num_phys; i++) { 6289 phy_mask = 0x00; 6290 6291 if (mpt->m_phy_info[i].attached_devhdl == 0) 6292 continue; 6293 6294 bzero(phy_mask_name, sizeof (phy_mask_name)); 6295 6296 current_port = mpt->m_phy_info[i].port_num; 6297 6298 if ((mask & (1 << i)) != 0) 6299 continue; 6300 6301 for (j = 0; j < mpt->m_num_phys; j++) { 6302 if (mpt->m_phy_info[j].attached_devhdl && 6303 (mpt->m_phy_info[j].port_num == current_port)) { 6304 phy_mask |= (1 << j); 6305 } 6306 } 6307 mask = mask | phy_mask; 6308 6309 for (j = 0; j < mpt->m_num_phys; j++) { 6310 if ((phy_mask >> j) & 0x01) { 6311 mpt->m_phy_info[j].phy_mask = phy_mask; 6312 } 6313 } 6314 6315 (void) sprintf(phy_mask_name, "%x", phy_mask); 6316 6317 mutex_exit(&mpt->m_mutex); 6318 /* 6319 * register a iport, if the port has already been existed 6320 * SCSA will do nothing and just return. 6321 */ 6322 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 6323 mutex_enter(&mpt->m_mutex); 6324 } 6325 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6326 NDBG20(("mptsas%d update phymask return", mpt->m_instance)); 6327 } 6328 6329 /* 6330 * mptsas_handle_dr is a task handler for DR, the DR action includes: 6331 * 1. Directly attched Device Added/Removed. 6332 * 2. Expander Device Added/Removed. 6333 * 3. Indirectly Attached Device Added/Expander. 6334 * 4. LUNs of a existing device status change. 6335 * 5. RAID volume created/deleted. 6336 * 6. Member of RAID volume is released because of RAID deletion. 6337 * 7. Physical disks are removed because of RAID creation. 6338 */ 6339 static void 6340 mptsas_handle_dr(void *args) 6341 { 6342 mptsas_topo_change_list_t *topo_node = NULL; 6343 mptsas_topo_change_list_t *save_node = NULL; 6344 mptsas_t *mpt; 6345 dev_info_t *parent = NULL; 6346 mptsas_phymask_t phymask = 0; 6347 char *phy_mask_name; 6348 uint8_t flags = 0, physport = 0xff; 6349 uint8_t port_update = 0; 6350 uint_t event; 6351 6352 topo_node = (mptsas_topo_change_list_t *)args; 6353 6354 mpt = topo_node->mpt; 6355 event = topo_node->event; 6356 flags = topo_node->flags; 6357 6358 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6359 6360 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance)); 6361 6362 switch (event) { 6363 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6364 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6365 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) || 6366 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6367 /* 6368 * Direct attached or expander attached device added 6369 * into system or a Phys Disk that is being unhidden. 6370 */ 6371 port_update = 1; 6372 } 6373 break; 6374 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6375 /* 6376 * New expander added into system, it must be the head 6377 * of topo_change_list_t 6378 */ 6379 port_update = 1; 6380 break; 6381 default: 6382 port_update = 0; 6383 break; 6384 } 6385 /* 6386 * All cases port_update == 1 may cause initiator port form change 6387 */ 6388 mutex_enter(&mpt->m_mutex); 6389 if (mpt->m_port_chng && port_update) { 6390 /* 6391 * mpt->m_port_chng flag indicates some PHYs of initiator 6392 * port have changed to online. So when expander added or 6393 * directly attached device online event come, we force to 6394 * update port information by issueing SAS IO Unit Page and 6395 * update PHYMASKs. 6396 */ 6397 (void) mptsas_update_phymask(mpt); 6398 mpt->m_port_chng = 0; 6399 6400 } 6401 mutex_exit(&mpt->m_mutex); 6402 while (topo_node) { 6403 phymask = 0; 6404 if (parent == NULL) { 6405 physport = topo_node->un.physport; 6406 event = topo_node->event; 6407 flags = topo_node->flags; 6408 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET | 6409 MPTSAS_DR_EVENT_OFFLINE_SMP)) { 6410 /* 6411 * For all offline events, phymask is known 6412 */ 6413 phymask = topo_node->un.phymask; 6414 goto find_parent; 6415 } 6416 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6417 goto handle_topo_change; 6418 } 6419 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) { 6420 phymask = topo_node->un.phymask; 6421 goto find_parent; 6422 } 6423 6424 if ((flags == 6425 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) && 6426 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) { 6427 /* 6428 * There is no any field in IR_CONFIG_CHANGE 6429 * event indicate physport/phynum, let's get 6430 * parent after SAS Device Page0 request. 6431 */ 6432 goto handle_topo_change; 6433 } 6434 6435 mutex_enter(&mpt->m_mutex); 6436 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6437 /* 6438 * If the direct attached device added or a 6439 * phys disk is being unhidden, argument 6440 * physport actually is PHY#, so we have to get 6441 * phymask according PHY#. 6442 */ 6443 physport = mpt->m_phy_info[physport].port_num; 6444 } 6445 6446 /* 6447 * Translate physport to phymask so that we can search 6448 * parent dip. 6449 */ 6450 phymask = mptsas_physport_to_phymask(mpt, 6451 physport); 6452 mutex_exit(&mpt->m_mutex); 6453 6454 find_parent: 6455 bzero(phy_mask_name, MPTSAS_MAX_PHYS); 6456 /* 6457 * For RAID topology change node, write the iport name 6458 * as v0. 6459 */ 6460 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6461 (void) sprintf(phy_mask_name, "v0"); 6462 } else { 6463 /* 6464 * phymask can bo 0 if the drive has been 6465 * pulled by the time an add event is 6466 * processed. If phymask is 0, just skip this 6467 * event and continue. 6468 */ 6469 if (phymask == 0) { 6470 mutex_enter(&mpt->m_mutex); 6471 save_node = topo_node; 6472 topo_node = topo_node->next; 6473 ASSERT(save_node); 6474 kmem_free(save_node, 6475 sizeof (mptsas_topo_change_list_t)); 6476 mutex_exit(&mpt->m_mutex); 6477 6478 parent = NULL; 6479 continue; 6480 } 6481 (void) sprintf(phy_mask_name, "%x", phymask); 6482 } 6483 parent = scsi_hba_iport_find(mpt->m_dip, 6484 phy_mask_name); 6485 if (parent == NULL) { 6486 mptsas_log(mpt, CE_WARN, "Failed to find an " 6487 "iport, should not happen!"); 6488 goto out; 6489 } 6490 6491 } 6492 ASSERT(parent); 6493 handle_topo_change: 6494 6495 mutex_enter(&mpt->m_mutex); 6496 /* 6497 * If HBA is being reset, don't perform operations depending 6498 * on the IOC. We must free the topo list, however. 6499 */ 6500 if (!mpt->m_in_reset) { 6501 mptsas_handle_topo_change(topo_node, parent); 6502 } else { 6503 NDBG20(("skipping topo change received during reset")); 6504 } 6505 save_node = topo_node; 6506 topo_node = topo_node->next; 6507 ASSERT(save_node); 6508 kmem_free(save_node, sizeof (mptsas_topo_change_list_t)); 6509 mutex_exit(&mpt->m_mutex); 6510 6511 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6512 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) || 6513 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) { 6514 /* 6515 * If direct attached device associated, make sure 6516 * reset the parent before start the next one. But 6517 * all devices associated with expander shares the 6518 * parent. Also, reset parent if this is for RAID. 6519 */ 6520 parent = NULL; 6521 } 6522 } 6523 out: 6524 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6525 } 6526 6527 static void 6528 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 6529 dev_info_t *parent) 6530 { 6531 mptsas_target_t *ptgt = NULL; 6532 mptsas_smp_t *psmp = NULL; 6533 mptsas_t *mpt = (void *)topo_node->mpt; 6534 uint16_t devhdl; 6535 uint16_t attached_devhdl; 6536 uint64_t sas_wwn = 0; 6537 int rval = 0; 6538 uint32_t page_address; 6539 uint8_t phy, flags; 6540 char *addr = NULL; 6541 dev_info_t *lundip; 6542 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 6543 6544 NDBG20(("mptsas%d handle_topo_change enter, devhdl 0x%x," 6545 "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl, 6546 topo_node->event, topo_node->flags)); 6547 6548 ASSERT(mutex_owned(&mpt->m_mutex)); 6549 6550 switch (topo_node->event) { 6551 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6552 { 6553 char *phy_mask_name; 6554 mptsas_phymask_t phymask = 0; 6555 6556 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6557 /* 6558 * Get latest RAID info. 6559 */ 6560 (void) mptsas_get_raid_info(mpt); 6561 ptgt = refhash_linear_search(mpt->m_targets, 6562 mptsas_target_eval_devhdl, &topo_node->devhdl); 6563 if (ptgt == NULL) 6564 break; 6565 } else { 6566 ptgt = (void *)topo_node->object; 6567 } 6568 6569 if (ptgt == NULL) { 6570 /* 6571 * If a Phys Disk was deleted, RAID info needs to be 6572 * updated to reflect the new topology. 6573 */ 6574 (void) mptsas_get_raid_info(mpt); 6575 6576 /* 6577 * Get sas device page 0 by DevHandle to make sure if 6578 * SSP/SATA end device exist. 6579 */ 6580 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 6581 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 6582 topo_node->devhdl; 6583 6584 rval = mptsas_get_target_device_info(mpt, page_address, 6585 &devhdl, &ptgt); 6586 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) { 6587 mptsas_log(mpt, CE_NOTE, 6588 "mptsas_handle_topo_change: target %d is " 6589 "not a SAS/SATA device. \n", 6590 topo_node->devhdl); 6591 } else if (rval == DEV_INFO_FAIL_ALLOC) { 6592 mptsas_log(mpt, CE_NOTE, 6593 "mptsas_handle_topo_change: could not " 6594 "allocate memory. \n"); 6595 } else if (rval == DEV_INFO_FAIL_GUID) { 6596 mptsas_log(mpt, CE_NOTE, 6597 "mptsas_handle_topo_change: could not " 6598 "get SATA GUID for target %d. \n", 6599 topo_node->devhdl); 6600 } 6601 /* 6602 * If rval is DEV_INFO_PHYS_DISK or indicates failure 6603 * then there is nothing else to do, just leave. 6604 */ 6605 if (rval != DEV_INFO_SUCCESS) { 6606 return; 6607 } 6608 } 6609 6610 ASSERT(ptgt->m_devhdl == topo_node->devhdl); 6611 6612 mutex_exit(&mpt->m_mutex); 6613 flags = topo_node->flags; 6614 6615 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) { 6616 phymask = ptgt->m_addr.mta_phymask; 6617 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6618 (void) sprintf(phy_mask_name, "%x", phymask); 6619 parent = scsi_hba_iport_find(mpt->m_dip, 6620 phy_mask_name); 6621 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6622 if (parent == NULL) { 6623 mptsas_log(mpt, CE_WARN, "Failed to find a " 6624 "iport for PD, should not happen!"); 6625 mutex_enter(&mpt->m_mutex); 6626 break; 6627 } 6628 } 6629 6630 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6631 ndi_devi_enter(parent); 6632 (void) mptsas_config_raid(parent, topo_node->devhdl, 6633 &lundip); 6634 ndi_devi_exit(parent); 6635 } else { 6636 /* 6637 * hold nexus for bus configure 6638 */ 6639 ndi_devi_enter(scsi_vhci_dip); 6640 ndi_devi_enter(parent); 6641 rval = mptsas_config_target(parent, ptgt); 6642 /* 6643 * release nexus for bus configure 6644 */ 6645 ndi_devi_exit(parent); 6646 ndi_devi_exit(scsi_vhci_dip); 6647 6648 /* 6649 * If this is a SATA device, make sure that the 6650 * bridge-port (the SAS WWN that the SATA device is 6651 * plugged into) is updated. This may change if a SATA 6652 * device changes which bay, and therefore phy, it is 6653 * plugged into. 6654 */ 6655 if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) { 6656 if (!mptsas_update_sata_bridge(mpt, parent, 6657 ptgt)) { 6658 mutex_enter(&mpt->m_mutex); 6659 return; 6660 } 6661 } 6662 6663 /* 6664 * Add parent's props for SMHBA support 6665 */ 6666 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6667 bzero(attached_wwnstr, 6668 sizeof (attached_wwnstr)); 6669 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 6670 ptgt->m_addr.mta_wwn); 6671 if (ddi_prop_update_string(DDI_DEV_T_NONE, 6672 parent, 6673 SCSI_ADDR_PROP_ATTACHED_PORT, 6674 attached_wwnstr) 6675 != DDI_PROP_SUCCESS) { 6676 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6677 parent, 6678 SCSI_ADDR_PROP_ATTACHED_PORT); 6679 mptsas_log(mpt, CE_WARN, "Failed to" 6680 "attached-port props"); 6681 mutex_enter(&mpt->m_mutex); 6682 return; 6683 } 6684 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6685 MPTSAS_NUM_PHYS, 1) != 6686 DDI_PROP_SUCCESS) { 6687 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6688 parent, MPTSAS_NUM_PHYS); 6689 mptsas_log(mpt, CE_WARN, "Failed to" 6690 " create num-phys props"); 6691 mutex_enter(&mpt->m_mutex); 6692 return; 6693 } 6694 6695 /* 6696 * Update PHY info for smhba 6697 */ 6698 mutex_enter(&mpt->m_mutex); 6699 if (mptsas_smhba_phy_init(mpt)) { 6700 mptsas_log(mpt, CE_WARN, "mptsas phy" 6701 " update failed"); 6702 return; 6703 } 6704 mutex_exit(&mpt->m_mutex); 6705 6706 /* 6707 * topo_node->un.physport is really the PHY# 6708 * for direct attached devices 6709 */ 6710 mptsas_smhba_set_one_phy_props(mpt, parent, 6711 topo_node->un.physport, &attached_devhdl); 6712 6713 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6714 MPTSAS_VIRTUAL_PORT, 0) != 6715 DDI_PROP_SUCCESS) { 6716 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6717 parent, MPTSAS_VIRTUAL_PORT); 6718 mptsas_log(mpt, CE_WARN, 6719 "mptsas virtual-port" 6720 "port prop update failed"); 6721 mutex_enter(&mpt->m_mutex); 6722 return; 6723 } 6724 } 6725 } 6726 mutex_enter(&mpt->m_mutex); 6727 6728 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, " 6729 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl, 6730 ptgt->m_addr.mta_phymask)); 6731 break; 6732 } 6733 case MPTSAS_DR_EVENT_OFFLINE_TARGET: 6734 { 6735 devhdl = topo_node->devhdl; 6736 ptgt = refhash_linear_search(mpt->m_targets, 6737 mptsas_target_eval_devhdl, &devhdl); 6738 if (ptgt == NULL) 6739 break; 6740 6741 sas_wwn = ptgt->m_addr.mta_wwn; 6742 phy = ptgt->m_phynum; 6743 6744 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 6745 6746 if (sas_wwn) { 6747 (void) sprintf(addr, "w%016"PRIx64, sas_wwn); 6748 } else { 6749 (void) sprintf(addr, "p%x", phy); 6750 } 6751 ASSERT(ptgt->m_devhdl == devhdl); 6752 6753 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) || 6754 (topo_node->flags == 6755 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6756 /* 6757 * Get latest RAID info if RAID volume status changes 6758 * or Phys Disk status changes 6759 */ 6760 (void) mptsas_get_raid_info(mpt); 6761 } 6762 /* 6763 * Abort all outstanding command on the device 6764 */ 6765 rval = mptsas_do_scsi_reset(mpt, devhdl); 6766 if (rval) { 6767 NDBG20(("mptsas%d handle_topo_change to reset target " 6768 "before offline devhdl:%x, phymask:%x, rval:%x", 6769 mpt->m_instance, ptgt->m_devhdl, 6770 ptgt->m_addr.mta_phymask, rval)); 6771 } 6772 6773 mutex_exit(&mpt->m_mutex); 6774 6775 ndi_devi_enter(scsi_vhci_dip); 6776 ndi_devi_enter(parent); 6777 rval = mptsas_offline_target(parent, addr); 6778 ndi_devi_exit(parent); 6779 ndi_devi_exit(scsi_vhci_dip); 6780 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, " 6781 "phymask:%x, rval:%x", mpt->m_instance, 6782 ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval)); 6783 6784 kmem_free(addr, SCSI_MAXNAMELEN); 6785 6786 /* 6787 * Clear parent's props for SMHBA support 6788 */ 6789 flags = topo_node->flags; 6790 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6791 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6792 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6793 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6794 DDI_PROP_SUCCESS) { 6795 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6796 SCSI_ADDR_PROP_ATTACHED_PORT); 6797 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6798 "prop update failed"); 6799 mutex_enter(&mpt->m_mutex); 6800 break; 6801 } 6802 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6803 MPTSAS_NUM_PHYS, 0) != 6804 DDI_PROP_SUCCESS) { 6805 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6806 MPTSAS_NUM_PHYS); 6807 mptsas_log(mpt, CE_WARN, "mptsas num phys " 6808 "prop update failed"); 6809 mutex_enter(&mpt->m_mutex); 6810 break; 6811 } 6812 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6813 MPTSAS_VIRTUAL_PORT, 1) != 6814 DDI_PROP_SUCCESS) { 6815 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6816 MPTSAS_VIRTUAL_PORT); 6817 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6818 "prop update failed"); 6819 mutex_enter(&mpt->m_mutex); 6820 break; 6821 } 6822 } 6823 6824 mutex_enter(&mpt->m_mutex); 6825 if (rval == DDI_SUCCESS) { 6826 refhash_remove(mpt->m_targets, ptgt); 6827 ptgt = NULL; 6828 } else { 6829 /* 6830 * clean DR_INTRANSITION flag to allow I/O down to 6831 * PHCI driver since failover finished. 6832 * Invalidate the devhdl 6833 */ 6834 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL; 6835 ptgt->m_tgt_unconfigured = 0; 6836 mutex_enter(&mpt->m_tx_waitq_mutex); 6837 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE; 6838 mutex_exit(&mpt->m_tx_waitq_mutex); 6839 } 6840 6841 /* 6842 * Send SAS IO Unit Control to free the dev handle 6843 */ 6844 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6845 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) { 6846 rval = mptsas_free_devhdl(mpt, devhdl); 6847 6848 NDBG20(("mptsas%d handle_topo_change to remove " 6849 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6850 rval)); 6851 } 6852 6853 break; 6854 } 6855 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE: 6856 { 6857 devhdl = topo_node->devhdl; 6858 /* 6859 * If this is the remove handle event, do a reset first. 6860 */ 6861 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6862 rval = mptsas_do_scsi_reset(mpt, devhdl); 6863 if (rval) { 6864 NDBG20(("mpt%d reset target before remove " 6865 "devhdl:%x, rval:%x", mpt->m_instance, 6866 devhdl, rval)); 6867 } 6868 } 6869 6870 /* 6871 * Send SAS IO Unit Control to free the dev handle 6872 */ 6873 rval = mptsas_free_devhdl(mpt, devhdl); 6874 NDBG20(("mptsas%d handle_topo_change to remove " 6875 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6876 rval)); 6877 break; 6878 } 6879 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6880 { 6881 mptsas_smp_t smp; 6882 dev_info_t *smpdip; 6883 6884 devhdl = topo_node->devhdl; 6885 6886 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 6887 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl; 6888 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp); 6889 if (rval != DDI_SUCCESS) { 6890 mptsas_log(mpt, CE_WARN, "failed to online smp, " 6891 "handle %x", devhdl); 6892 return; 6893 } 6894 6895 psmp = mptsas_smp_alloc(mpt, &smp); 6896 if (psmp == NULL) { 6897 return; 6898 } 6899 6900 mutex_exit(&mpt->m_mutex); 6901 ndi_devi_enter(parent); 6902 (void) mptsas_online_smp(parent, psmp, &smpdip); 6903 ndi_devi_exit(parent); 6904 6905 mutex_enter(&mpt->m_mutex); 6906 break; 6907 } 6908 case MPTSAS_DR_EVENT_OFFLINE_SMP: 6909 { 6910 devhdl = topo_node->devhdl; 6911 uint32_t dev_info; 6912 6913 psmp = refhash_linear_search(mpt->m_smp_targets, 6914 mptsas_smp_eval_devhdl, &devhdl); 6915 if (psmp == NULL) 6916 break; 6917 /* 6918 * The mptsas_smp_t data is released only if the dip is offlined 6919 * successfully. 6920 */ 6921 mutex_exit(&mpt->m_mutex); 6922 6923 ndi_devi_enter(parent); 6924 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE); 6925 ndi_devi_exit(parent); 6926 6927 dev_info = psmp->m_deviceinfo; 6928 if ((dev_info & DEVINFO_DIRECT_ATTACHED) == 6929 DEVINFO_DIRECT_ATTACHED) { 6930 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6931 MPTSAS_VIRTUAL_PORT, 1) != 6932 DDI_PROP_SUCCESS) { 6933 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6934 MPTSAS_VIRTUAL_PORT); 6935 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6936 "prop update failed"); 6937 mutex_enter(&mpt->m_mutex); 6938 return; 6939 } 6940 /* 6941 * Check whether the smp connected to the iport, 6942 */ 6943 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6944 MPTSAS_NUM_PHYS, 0) != 6945 DDI_PROP_SUCCESS) { 6946 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6947 MPTSAS_NUM_PHYS); 6948 mptsas_log(mpt, CE_WARN, "mptsas num phys" 6949 "prop update failed"); 6950 mutex_enter(&mpt->m_mutex); 6951 return; 6952 } 6953 /* 6954 * Clear parent's attached-port props 6955 */ 6956 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6957 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6958 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6959 DDI_PROP_SUCCESS) { 6960 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6961 SCSI_ADDR_PROP_ATTACHED_PORT); 6962 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6963 "prop update failed"); 6964 mutex_enter(&mpt->m_mutex); 6965 return; 6966 } 6967 } 6968 6969 mutex_enter(&mpt->m_mutex); 6970 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, " 6971 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval)); 6972 if (rval == DDI_SUCCESS) { 6973 refhash_remove(mpt->m_smp_targets, psmp); 6974 } else { 6975 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL; 6976 } 6977 6978 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6979 6980 break; 6981 } 6982 default: 6983 return; 6984 } 6985 } 6986 6987 /* 6988 * Record the event if its type is enabled in mpt instance by ioctl. 6989 */ 6990 static void 6991 mptsas_record_event(void *args) 6992 { 6993 m_replyh_arg_t *replyh_arg; 6994 pMpi2EventNotificationReply_t eventreply; 6995 uint32_t event, rfm; 6996 mptsas_t *mpt; 6997 int i, j; 6998 uint16_t event_data_len; 6999 boolean_t sendAEN = FALSE; 7000 7001 replyh_arg = (m_replyh_arg_t *)args; 7002 rfm = replyh_arg->rfm; 7003 mpt = replyh_arg->mpt; 7004 7005 eventreply = (pMpi2EventNotificationReply_t) 7006 (mpt->m_reply_frame + (rfm - 7007 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 7008 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7009 7010 7011 /* 7012 * Generate a system event to let anyone who cares know that a 7013 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the 7014 * event mask is set to. 7015 */ 7016 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) { 7017 sendAEN = TRUE; 7018 } 7019 7020 /* 7021 * Record the event only if it is not masked. Determine which dword 7022 * and bit of event mask to test. 7023 */ 7024 i = (uint8_t)(event / 32); 7025 j = (uint8_t)(event % 32); 7026 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) { 7027 i = mpt->m_event_index; 7028 mpt->m_events[i].Type = event; 7029 mpt->m_events[i].Number = ++mpt->m_event_number; 7030 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4); 7031 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl, 7032 &eventreply->EventDataLength); 7033 7034 if (event_data_len > 0) { 7035 /* 7036 * Limit data to size in m_event entry 7037 */ 7038 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) { 7039 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH; 7040 } 7041 for (j = 0; j < event_data_len; j++) { 7042 mpt->m_events[i].Data[j] = 7043 ddi_get32(mpt->m_acc_reply_frame_hdl, 7044 &(eventreply->EventData[j])); 7045 } 7046 7047 /* 7048 * check for index wrap-around 7049 */ 7050 if (++i == MPTSAS_EVENT_QUEUE_SIZE) { 7051 i = 0; 7052 } 7053 mpt->m_event_index = (uint8_t)i; 7054 7055 /* 7056 * Set flag to send the event. 7057 */ 7058 sendAEN = TRUE; 7059 } 7060 } 7061 7062 /* 7063 * Generate a system event if flag is set to let anyone who cares know 7064 * that an event has occurred. 7065 */ 7066 if (sendAEN) { 7067 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS", 7068 "SAS", NULL, NULL, DDI_NOSLEEP); 7069 } 7070 } 7071 7072 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS 7073 /* 7074 * handle sync events from ioc in interrupt 7075 * return value: 7076 * DDI_SUCCESS: The event is handled by this func 7077 * DDI_FAILURE: Event is not handled 7078 */ 7079 static int 7080 mptsas_handle_event_sync(void *args) 7081 { 7082 m_replyh_arg_t *replyh_arg; 7083 pMpi2EventNotificationReply_t eventreply; 7084 uint32_t event, rfm; 7085 mptsas_t *mpt; 7086 uint_t iocstatus; 7087 7088 replyh_arg = (m_replyh_arg_t *)args; 7089 rfm = replyh_arg->rfm; 7090 mpt = replyh_arg->mpt; 7091 7092 ASSERT(mutex_owned(&mpt->m_mutex)); 7093 7094 eventreply = (pMpi2EventNotificationReply_t) 7095 (mpt->m_reply_frame + (rfm - 7096 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 7097 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7098 7099 if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 7100 &eventreply->IOCStatus)) != 0) { 7101 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 7102 mptsas_log(mpt, CE_WARN, 7103 "!mptsas_handle_event_sync: event 0x%x, " 7104 "IOCStatus=0x%x, " 7105 "IOCLogInfo=0x%x", event, iocstatus, 7106 ddi_get32(mpt->m_acc_reply_frame_hdl, 7107 &eventreply->IOCLogInfo)); 7108 } else { 7109 mptsas_log(mpt, CE_WARN, 7110 "mptsas_handle_event_sync: event 0x%x, " 7111 "IOCStatus=0x%x, " 7112 "(IOCLogInfo=0x%x)", event, iocstatus, 7113 ddi_get32(mpt->m_acc_reply_frame_hdl, 7114 &eventreply->IOCLogInfo)); 7115 } 7116 } 7117 7118 /* 7119 * figure out what kind of event we got and handle accordingly 7120 */ 7121 switch (event) { 7122 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 7123 { 7124 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list; 7125 uint8_t num_entries, expstatus, phy; 7126 uint8_t phystatus, physport, state, i; 7127 uint8_t start_phy_num, link_rate; 7128 uint16_t dev_handle, reason_code; 7129 uint16_t enc_handle, expd_handle; 7130 char string[80], curr[80], prev[80]; 7131 mptsas_topo_change_list_t *topo_head = NULL; 7132 mptsas_topo_change_list_t *topo_tail = NULL; 7133 mptsas_topo_change_list_t *topo_node = NULL; 7134 mptsas_target_t *ptgt; 7135 mptsas_smp_t *psmp; 7136 uint8_t flags = 0, exp_flag; 7137 smhba_info_t *pSmhba = NULL; 7138 7139 NDBG20(("mptsas_handle_event_sync: SAS topology change")); 7140 7141 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t) 7142 eventreply->EventData; 7143 7144 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7145 &sas_topo_change_list->EnclosureHandle); 7146 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7147 &sas_topo_change_list->ExpanderDevHandle); 7148 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 7149 &sas_topo_change_list->NumEntries); 7150 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 7151 &sas_topo_change_list->StartPhyNum); 7152 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 7153 &sas_topo_change_list->ExpStatus); 7154 physport = ddi_get8(mpt->m_acc_reply_frame_hdl, 7155 &sas_topo_change_list->PhysicalPort); 7156 7157 string[0] = 0; 7158 if (expd_handle) { 7159 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED; 7160 switch (expstatus) { 7161 case MPI2_EVENT_SAS_TOPO_ES_ADDED: 7162 (void) sprintf(string, " added"); 7163 /* 7164 * New expander device added 7165 */ 7166 mpt->m_port_chng = 1; 7167 topo_node = kmem_zalloc( 7168 sizeof (mptsas_topo_change_list_t), 7169 KM_SLEEP); 7170 topo_node->mpt = mpt; 7171 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP; 7172 topo_node->un.physport = physport; 7173 topo_node->devhdl = expd_handle; 7174 topo_node->flags = flags; 7175 topo_node->object = NULL; 7176 if (topo_head == NULL) { 7177 topo_head = topo_tail = topo_node; 7178 } else { 7179 topo_tail->next = topo_node; 7180 topo_tail = topo_node; 7181 } 7182 break; 7183 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING: 7184 (void) sprintf(string, " not responding, " 7185 "removed"); 7186 psmp = refhash_linear_search(mpt->m_smp_targets, 7187 mptsas_smp_eval_devhdl, &expd_handle); 7188 if (psmp == NULL) 7189 break; 7190 7191 topo_node = kmem_zalloc( 7192 sizeof (mptsas_topo_change_list_t), 7193 KM_SLEEP); 7194 topo_node->mpt = mpt; 7195 topo_node->un.phymask = 7196 psmp->m_addr.mta_phymask; 7197 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP; 7198 topo_node->devhdl = expd_handle; 7199 topo_node->flags = flags; 7200 topo_node->object = NULL; 7201 if (topo_head == NULL) { 7202 topo_head = topo_tail = topo_node; 7203 } else { 7204 topo_tail->next = topo_node; 7205 topo_tail = topo_node; 7206 } 7207 break; 7208 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING: 7209 break; 7210 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING: 7211 (void) sprintf(string, " not responding, " 7212 "delaying removal"); 7213 break; 7214 default: 7215 break; 7216 } 7217 } else { 7218 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE; 7219 } 7220 7221 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n", 7222 enc_handle, expd_handle, string)); 7223 for (i = 0; i < num_entries; i++) { 7224 phy = i + start_phy_num; 7225 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 7226 &sas_topo_change_list->PHY[i].PhyStatus); 7227 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7228 &sas_topo_change_list->PHY[i].AttachedDevHandle); 7229 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK; 7230 /* 7231 * Filter out processing of Phy Vacant Status unless 7232 * the reason code is "Not Responding". Process all 7233 * other combinations of Phy Status and Reason Codes. 7234 */ 7235 if ((phystatus & 7236 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) && 7237 (reason_code != 7238 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) { 7239 continue; 7240 } 7241 curr[0] = 0; 7242 prev[0] = 0; 7243 string[0] = 0; 7244 switch (reason_code) { 7245 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED: 7246 { 7247 NDBG20(("mptsas%d phy %d physical_port %d " 7248 "dev_handle %d added", mpt->m_instance, phy, 7249 physport, dev_handle)); 7250 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 7251 &sas_topo_change_list->PHY[i].LinkRate); 7252 state = (link_rate & 7253 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 7254 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 7255 switch (state) { 7256 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7257 (void) sprintf(curr, "is disabled"); 7258 break; 7259 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7260 (void) sprintf(curr, "is offline, " 7261 "failed speed negotiation"); 7262 break; 7263 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7264 (void) sprintf(curr, "SATA OOB " 7265 "complete"); 7266 break; 7267 case SMP_RESET_IN_PROGRESS: 7268 (void) sprintf(curr, "SMP reset in " 7269 "progress"); 7270 break; 7271 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7272 (void) sprintf(curr, "is online at " 7273 "1.5 Gbps"); 7274 break; 7275 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7276 (void) sprintf(curr, "is online at 3.0 " 7277 "Gbps"); 7278 break; 7279 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7280 (void) sprintf(curr, "is online at 6.0 " 7281 "Gbps"); 7282 break; 7283 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7284 (void) sprintf(curr, 7285 "is online at 12.0 Gbps"); 7286 break; 7287 default: 7288 (void) sprintf(curr, "state is " 7289 "unknown"); 7290 break; 7291 } 7292 /* 7293 * New target device added into the system. 7294 * Set association flag according to if an 7295 * expander is used or not. 7296 */ 7297 exp_flag = 7298 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 7299 if (flags == 7300 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 7301 flags = exp_flag; 7302 } 7303 topo_node = kmem_zalloc( 7304 sizeof (mptsas_topo_change_list_t), 7305 KM_SLEEP); 7306 topo_node->mpt = mpt; 7307 topo_node->event = 7308 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7309 if (expd_handle == 0) { 7310 /* 7311 * Per MPI 2, if expander dev handle 7312 * is 0, it's a directly attached 7313 * device. So driver use PHY to decide 7314 * which iport is associated 7315 */ 7316 physport = phy; 7317 mpt->m_port_chng = 1; 7318 } 7319 topo_node->un.physport = physport; 7320 topo_node->devhdl = dev_handle; 7321 topo_node->flags = flags; 7322 topo_node->object = NULL; 7323 if (topo_head == NULL) { 7324 topo_head = topo_tail = topo_node; 7325 } else { 7326 topo_tail->next = topo_node; 7327 topo_tail = topo_node; 7328 } 7329 break; 7330 } 7331 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING: 7332 { 7333 NDBG20(("mptsas%d phy %d physical_port %d " 7334 "dev_handle %d removed", mpt->m_instance, 7335 phy, physport, dev_handle)); 7336 /* 7337 * Set association flag according to if an 7338 * expander is used or not. 7339 */ 7340 exp_flag = 7341 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 7342 if (flags == 7343 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 7344 flags = exp_flag; 7345 } 7346 /* 7347 * Target device is removed from the system 7348 * Before the device is really offline from 7349 * from system. 7350 */ 7351 ptgt = refhash_linear_search(mpt->m_targets, 7352 mptsas_target_eval_devhdl, &dev_handle); 7353 /* 7354 * If ptgt is NULL here, it means that the 7355 * DevHandle is not in the hash table. This is 7356 * reasonable sometimes. For example, if a 7357 * disk was pulled, then added, then pulled 7358 * again, the disk will not have been put into 7359 * the hash table because the add event will 7360 * have an invalid phymask. BUT, this does not 7361 * mean that the DevHandle is invalid. The 7362 * controller will still have a valid DevHandle 7363 * that must be removed. To do this, use the 7364 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event. 7365 */ 7366 if (ptgt == NULL) { 7367 topo_node = kmem_zalloc( 7368 sizeof (mptsas_topo_change_list_t), 7369 KM_SLEEP); 7370 topo_node->mpt = mpt; 7371 topo_node->un.phymask = 0; 7372 topo_node->event = 7373 MPTSAS_TOPO_FLAG_REMOVE_HANDLE; 7374 topo_node->devhdl = dev_handle; 7375 topo_node->flags = flags; 7376 topo_node->object = NULL; 7377 if (topo_head == NULL) { 7378 topo_head = topo_tail = 7379 topo_node; 7380 } else { 7381 topo_tail->next = topo_node; 7382 topo_tail = topo_node; 7383 } 7384 break; 7385 } 7386 7387 /* 7388 * Update DR flag immediately avoid I/O failure 7389 * before failover finish. Pay attention to the 7390 * mutex protect, we need grab m_tx_waitq_mutex 7391 * during set m_dr_flag because we won't add 7392 * the following command into waitq, instead, 7393 * we need return TRAN_BUSY in the tran_start 7394 * context. 7395 */ 7396 mutex_enter(&mpt->m_tx_waitq_mutex); 7397 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7398 mutex_exit(&mpt->m_tx_waitq_mutex); 7399 7400 topo_node = kmem_zalloc( 7401 sizeof (mptsas_topo_change_list_t), 7402 KM_SLEEP); 7403 topo_node->mpt = mpt; 7404 topo_node->un.phymask = 7405 ptgt->m_addr.mta_phymask; 7406 topo_node->event = 7407 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7408 topo_node->devhdl = dev_handle; 7409 topo_node->flags = flags; 7410 topo_node->object = NULL; 7411 if (topo_head == NULL) { 7412 topo_head = topo_tail = topo_node; 7413 } else { 7414 topo_tail->next = topo_node; 7415 topo_tail = topo_node; 7416 } 7417 break; 7418 } 7419 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED: 7420 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 7421 &sas_topo_change_list->PHY[i].LinkRate); 7422 state = (link_rate & 7423 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 7424 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 7425 pSmhba = &mpt->m_phy_info[i].smhba_info; 7426 pSmhba->negotiated_link_rate = state; 7427 switch (state) { 7428 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7429 (void) sprintf(curr, "is disabled"); 7430 mptsas_smhba_log_sysevent(mpt, 7431 ESC_SAS_PHY_EVENT, 7432 SAS_PHY_REMOVE, 7433 &mpt->m_phy_info[i].smhba_info); 7434 mpt->m_phy_info[i].smhba_info. 7435 negotiated_link_rate 7436 = 0x1; 7437 break; 7438 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7439 (void) sprintf(curr, "is offline, " 7440 "failed speed negotiation"); 7441 mptsas_smhba_log_sysevent(mpt, 7442 ESC_SAS_PHY_EVENT, 7443 SAS_PHY_OFFLINE, 7444 &mpt->m_phy_info[i].smhba_info); 7445 break; 7446 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7447 (void) sprintf(curr, "SATA OOB " 7448 "complete"); 7449 break; 7450 case SMP_RESET_IN_PROGRESS: 7451 (void) sprintf(curr, "SMP reset in " 7452 "progress"); 7453 break; 7454 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7455 (void) sprintf(curr, "is online at " 7456 "1.5 Gbps"); 7457 if ((expd_handle == 0) && 7458 (enc_handle == 1)) { 7459 mpt->m_port_chng = 1; 7460 } 7461 mptsas_smhba_log_sysevent(mpt, 7462 ESC_SAS_PHY_EVENT, 7463 SAS_PHY_ONLINE, 7464 &mpt->m_phy_info[i].smhba_info); 7465 break; 7466 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7467 (void) sprintf(curr, "is online at 3.0 " 7468 "Gbps"); 7469 if ((expd_handle == 0) && 7470 (enc_handle == 1)) { 7471 mpt->m_port_chng = 1; 7472 } 7473 mptsas_smhba_log_sysevent(mpt, 7474 ESC_SAS_PHY_EVENT, 7475 SAS_PHY_ONLINE, 7476 &mpt->m_phy_info[i].smhba_info); 7477 break; 7478 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7479 (void) sprintf(curr, "is online at " 7480 "6.0 Gbps"); 7481 if ((expd_handle == 0) && 7482 (enc_handle == 1)) { 7483 mpt->m_port_chng = 1; 7484 } 7485 mptsas_smhba_log_sysevent(mpt, 7486 ESC_SAS_PHY_EVENT, 7487 SAS_PHY_ONLINE, 7488 &mpt->m_phy_info[i].smhba_info); 7489 break; 7490 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7491 (void) sprintf(curr, "is online at " 7492 "12.0 Gbps"); 7493 if ((expd_handle == 0) && 7494 (enc_handle == 1)) { 7495 mpt->m_port_chng = 1; 7496 } 7497 mptsas_smhba_log_sysevent(mpt, 7498 ESC_SAS_PHY_EVENT, 7499 SAS_PHY_ONLINE, 7500 &mpt->m_phy_info[i].smhba_info); 7501 break; 7502 default: 7503 (void) sprintf(curr, "state is " 7504 "unknown"); 7505 break; 7506 } 7507 7508 state = (link_rate & 7509 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >> 7510 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT; 7511 switch (state) { 7512 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7513 (void) sprintf(prev, ", was disabled"); 7514 break; 7515 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7516 (void) sprintf(prev, ", was offline, " 7517 "failed speed negotiation"); 7518 break; 7519 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7520 (void) sprintf(prev, ", was SATA OOB " 7521 "complete"); 7522 break; 7523 case SMP_RESET_IN_PROGRESS: 7524 (void) sprintf(prev, ", was SMP reset " 7525 "in progress"); 7526 break; 7527 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7528 (void) sprintf(prev, ", was online at " 7529 "1.5 Gbps"); 7530 break; 7531 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7532 (void) sprintf(prev, ", was online at " 7533 "3.0 Gbps"); 7534 break; 7535 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7536 (void) sprintf(prev, ", was online at " 7537 "6.0 Gbps"); 7538 break; 7539 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7540 (void) sprintf(prev, ", was online at " 7541 "12.0 Gbps"); 7542 break; 7543 default: 7544 break; 7545 } 7546 (void) sprintf(&string[strlen(string)], "link " 7547 "changed, "); 7548 break; 7549 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE: 7550 continue; 7551 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING: 7552 (void) sprintf(&string[strlen(string)], 7553 "target not responding, delaying " 7554 "removal"); 7555 break; 7556 } 7557 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n", 7558 mpt->m_instance, phy, dev_handle, string, curr, 7559 prev)); 7560 } 7561 if (topo_head != NULL) { 7562 /* 7563 * Launch DR taskq to handle topology change 7564 */ 7565 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7566 mptsas_handle_dr, (void *)topo_head, 7567 DDI_NOSLEEP)) != DDI_SUCCESS) { 7568 while (topo_head != NULL) { 7569 topo_node = topo_head; 7570 topo_head = topo_head->next; 7571 kmem_free(topo_node, 7572 sizeof (mptsas_topo_change_list_t)); 7573 } 7574 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7575 "for handle SAS DR event failed. \n"); 7576 } 7577 } 7578 break; 7579 } 7580 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7581 { 7582 Mpi2EventDataIrConfigChangeList_t *irChangeList; 7583 mptsas_topo_change_list_t *topo_head = NULL; 7584 mptsas_topo_change_list_t *topo_tail = NULL; 7585 mptsas_topo_change_list_t *topo_node = NULL; 7586 mptsas_target_t *ptgt; 7587 uint8_t num_entries, i, reason; 7588 uint16_t volhandle, diskhandle; 7589 7590 irChangeList = (pMpi2EventDataIrConfigChangeList_t) 7591 eventreply->EventData; 7592 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 7593 &irChangeList->NumElements); 7594 7595 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received", 7596 mpt->m_instance)); 7597 7598 for (i = 0; i < num_entries; i++) { 7599 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 7600 &irChangeList->ConfigElement[i].ReasonCode); 7601 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7602 &irChangeList->ConfigElement[i].VolDevHandle); 7603 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7604 &irChangeList->ConfigElement[i].PhysDiskDevHandle); 7605 7606 switch (reason) { 7607 case MPI2_EVENT_IR_CHANGE_RC_ADDED: 7608 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED: 7609 { 7610 NDBG20(("mptsas %d volume added\n", 7611 mpt->m_instance)); 7612 7613 topo_node = kmem_zalloc( 7614 sizeof (mptsas_topo_change_list_t), 7615 KM_SLEEP); 7616 7617 topo_node->mpt = mpt; 7618 topo_node->event = 7619 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7620 topo_node->un.physport = 0xff; 7621 topo_node->devhdl = volhandle; 7622 topo_node->flags = 7623 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7624 topo_node->object = NULL; 7625 if (topo_head == NULL) { 7626 topo_head = topo_tail = topo_node; 7627 } else { 7628 topo_tail->next = topo_node; 7629 topo_tail = topo_node; 7630 } 7631 break; 7632 } 7633 case MPI2_EVENT_IR_CHANGE_RC_REMOVED: 7634 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED: 7635 { 7636 NDBG20(("mptsas %d volume deleted\n", 7637 mpt->m_instance)); 7638 ptgt = refhash_linear_search(mpt->m_targets, 7639 mptsas_target_eval_devhdl, &volhandle); 7640 if (ptgt == NULL) 7641 break; 7642 7643 /* 7644 * Clear any flags related to volume 7645 */ 7646 (void) mptsas_delete_volume(mpt, volhandle); 7647 7648 /* 7649 * Update DR flag immediately avoid I/O failure 7650 */ 7651 mutex_enter(&mpt->m_tx_waitq_mutex); 7652 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7653 mutex_exit(&mpt->m_tx_waitq_mutex); 7654 7655 topo_node = kmem_zalloc( 7656 sizeof (mptsas_topo_change_list_t), 7657 KM_SLEEP); 7658 topo_node->mpt = mpt; 7659 topo_node->un.phymask = 7660 ptgt->m_addr.mta_phymask; 7661 topo_node->event = 7662 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7663 topo_node->devhdl = volhandle; 7664 topo_node->flags = 7665 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7666 topo_node->object = (void *)ptgt; 7667 if (topo_head == NULL) { 7668 topo_head = topo_tail = topo_node; 7669 } else { 7670 topo_tail->next = topo_node; 7671 topo_tail = topo_node; 7672 } 7673 break; 7674 } 7675 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED: 7676 case MPI2_EVENT_IR_CHANGE_RC_HIDE: 7677 { 7678 ptgt = refhash_linear_search(mpt->m_targets, 7679 mptsas_target_eval_devhdl, &diskhandle); 7680 if (ptgt == NULL) 7681 break; 7682 7683 /* 7684 * Update DR flag immediately avoid I/O failure 7685 */ 7686 mutex_enter(&mpt->m_tx_waitq_mutex); 7687 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7688 mutex_exit(&mpt->m_tx_waitq_mutex); 7689 7690 topo_node = kmem_zalloc( 7691 sizeof (mptsas_topo_change_list_t), 7692 KM_SLEEP); 7693 topo_node->mpt = mpt; 7694 topo_node->un.phymask = 7695 ptgt->m_addr.mta_phymask; 7696 topo_node->event = 7697 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7698 topo_node->devhdl = diskhandle; 7699 topo_node->flags = 7700 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7701 topo_node->object = (void *)ptgt; 7702 if (topo_head == NULL) { 7703 topo_head = topo_tail = topo_node; 7704 } else { 7705 topo_tail->next = topo_node; 7706 topo_tail = topo_node; 7707 } 7708 break; 7709 } 7710 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE: 7711 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED: 7712 { 7713 /* 7714 * The physical drive is released by a IR 7715 * volume. But we cannot get the the physport 7716 * or phynum from the event data, so we only 7717 * can get the physport/phynum after SAS 7718 * Device Page0 request for the devhdl. 7719 */ 7720 topo_node = kmem_zalloc( 7721 sizeof (mptsas_topo_change_list_t), 7722 KM_SLEEP); 7723 topo_node->mpt = mpt; 7724 topo_node->un.phymask = 0; 7725 topo_node->event = 7726 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7727 topo_node->devhdl = diskhandle; 7728 topo_node->flags = 7729 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7730 topo_node->object = NULL; 7731 mpt->m_port_chng = 1; 7732 if (topo_head == NULL) { 7733 topo_head = topo_tail = topo_node; 7734 } else { 7735 topo_tail->next = topo_node; 7736 topo_tail = topo_node; 7737 } 7738 break; 7739 } 7740 default: 7741 break; 7742 } 7743 } 7744 7745 if (topo_head != NULL) { 7746 /* 7747 * Launch DR taskq to handle topology change 7748 */ 7749 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7750 mptsas_handle_dr, (void *)topo_head, 7751 DDI_NOSLEEP)) != DDI_SUCCESS) { 7752 while (topo_head != NULL) { 7753 topo_node = topo_head; 7754 topo_head = topo_head->next; 7755 kmem_free(topo_node, 7756 sizeof (mptsas_topo_change_list_t)); 7757 } 7758 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7759 "for handle SAS DR event failed. \n"); 7760 } 7761 } 7762 break; 7763 } 7764 default: 7765 return (DDI_FAILURE); 7766 } 7767 7768 return (DDI_SUCCESS); 7769 } 7770 7771 /* 7772 * handle events from ioc 7773 */ 7774 static void 7775 mptsas_handle_event(void *args) 7776 { 7777 m_replyh_arg_t *replyh_arg; 7778 pMpi2EventNotificationReply_t eventreply; 7779 uint32_t event, iocloginfo, rfm; 7780 uint32_t status; 7781 uint8_t port; 7782 mptsas_t *mpt; 7783 uint_t iocstatus; 7784 7785 replyh_arg = (m_replyh_arg_t *)args; 7786 rfm = replyh_arg->rfm; 7787 mpt = replyh_arg->mpt; 7788 7789 mutex_enter(&mpt->m_mutex); 7790 /* 7791 * If HBA is being reset, drop incoming event. 7792 */ 7793 if (mpt->m_in_reset) { 7794 NDBG20(("dropping event received prior to reset")); 7795 mutex_exit(&mpt->m_mutex); 7796 return; 7797 } 7798 7799 eventreply = (pMpi2EventNotificationReply_t) 7800 (mpt->m_reply_frame + (rfm - 7801 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 7802 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7803 7804 if ((iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 7805 &eventreply->IOCStatus)) != 0) { 7806 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 7807 mptsas_log(mpt, CE_WARN, 7808 "!mptsas_handle_event: IOCStatus=0x%x, " 7809 "IOCLogInfo=0x%x", iocstatus, 7810 ddi_get32(mpt->m_acc_reply_frame_hdl, 7811 &eventreply->IOCLogInfo)); 7812 } else { 7813 mptsas_log(mpt, CE_WARN, 7814 "mptsas_handle_event: IOCStatus=0x%x, " 7815 "IOCLogInfo=0x%x", iocstatus, 7816 ddi_get32(mpt->m_acc_reply_frame_hdl, 7817 &eventreply->IOCLogInfo)); 7818 } 7819 } 7820 7821 /* 7822 * figure out what kind of event we got and handle accordingly 7823 */ 7824 switch (event) { 7825 case MPI2_EVENT_LOG_ENTRY_ADDED: 7826 break; 7827 case MPI2_EVENT_LOG_DATA: 7828 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7829 &eventreply->IOCLogInfo); 7830 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance, 7831 iocloginfo)); 7832 break; 7833 case MPI2_EVENT_STATE_CHANGE: 7834 NDBG20(("mptsas%d state change.", mpt->m_instance)); 7835 break; 7836 case MPI2_EVENT_HARD_RESET_RECEIVED: 7837 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7838 break; 7839 case MPI2_EVENT_SAS_DISCOVERY: 7840 { 7841 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery; 7842 char string[80]; 7843 uint8_t rc; 7844 7845 sasdiscovery = 7846 (pMpi2EventDataSasDiscovery_t)eventreply->EventData; 7847 7848 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7849 &sasdiscovery->ReasonCode); 7850 port = ddi_get8(mpt->m_acc_reply_frame_hdl, 7851 &sasdiscovery->PhysicalPort); 7852 status = ddi_get32(mpt->m_acc_reply_frame_hdl, 7853 &sasdiscovery->DiscoveryStatus); 7854 7855 string[0] = 0; 7856 switch (rc) { 7857 case MPI2_EVENT_SAS_DISC_RC_STARTED: 7858 (void) sprintf(string, "STARTING"); 7859 break; 7860 case MPI2_EVENT_SAS_DISC_RC_COMPLETED: 7861 (void) sprintf(string, "COMPLETED"); 7862 break; 7863 default: 7864 (void) sprintf(string, "UNKNOWN"); 7865 break; 7866 } 7867 7868 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string, 7869 port, status)); 7870 7871 break; 7872 } 7873 case MPI2_EVENT_EVENT_CHANGE: 7874 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7875 break; 7876 case MPI2_EVENT_TASK_SET_FULL: 7877 { 7878 pMpi2EventDataTaskSetFull_t taskfull; 7879 7880 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData; 7881 7882 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n", 7883 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 7884 &taskfull->CurrentDepth))); 7885 break; 7886 } 7887 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 7888 { 7889 /* 7890 * SAS TOPOLOGY CHANGE LIST Event has already been handled 7891 * in mptsas_handle_event_sync() of interrupt context 7892 */ 7893 break; 7894 } 7895 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 7896 { 7897 pMpi2EventDataSasEnclDevStatusChange_t encstatus; 7898 uint8_t rc; 7899 uint16_t enchdl; 7900 char string[80]; 7901 mptsas_enclosure_t *mep; 7902 7903 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t) 7904 eventreply->EventData; 7905 7906 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7907 &encstatus->ReasonCode); 7908 enchdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7909 &encstatus->EnclosureHandle); 7910 7911 switch (rc) { 7912 case MPI2_EVENT_SAS_ENCL_RC_ADDED: 7913 (void) sprintf(string, "added"); 7914 break; 7915 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING: 7916 mep = mptsas_enc_lookup(mpt, enchdl); 7917 if (mep != NULL) { 7918 list_remove(&mpt->m_enclosures, mep); 7919 mptsas_enc_free(mep); 7920 mep = NULL; 7921 } 7922 (void) sprintf(string, ", not responding"); 7923 break; 7924 default: 7925 break; 7926 } 7927 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure " 7928 "%x%s\n", mpt->m_instance, 7929 ddi_get16(mpt->m_acc_reply_frame_hdl, 7930 &encstatus->EnclosureHandle), string)); 7931 7932 /* 7933 * No matter what has happened, update all of our device state 7934 * for enclosures, by retriggering an evaluation. 7935 */ 7936 mpt->m_done_traverse_enc = 0; 7937 mptsas_update_hashtab(mpt); 7938 break; 7939 } 7940 7941 /* 7942 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by 7943 * mptsas_handle_event_sync,in here just send ack message. 7944 */ 7945 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 7946 { 7947 pMpi2EventDataSasDeviceStatusChange_t statuschange; 7948 uint8_t rc; 7949 uint16_t devhdl; 7950 uint64_t wwn = 0; 7951 uint32_t wwn_lo, wwn_hi; 7952 7953 statuschange = (pMpi2EventDataSasDeviceStatusChange_t) 7954 eventreply->EventData; 7955 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7956 &statuschange->ReasonCode); 7957 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7958 (uint32_t *)(void *)&statuschange->SASAddress); 7959 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl, 7960 (uint32_t *)(void *)&statuschange->SASAddress + 1); 7961 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo; 7962 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7963 &statuschange->DevHandle); 7964 7965 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64, 7966 wwn)); 7967 7968 switch (rc) { 7969 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7970 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x", 7971 ddi_get8(mpt->m_acc_reply_frame_hdl, 7972 &statuschange->ASC), 7973 ddi_get8(mpt->m_acc_reply_frame_hdl, 7974 &statuschange->ASCQ))); 7975 break; 7976 7977 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7978 NDBG20(("Device not supported")); 7979 break; 7980 7981 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7982 NDBG20(("IOC internally generated the Target Reset " 7983 "for devhdl:%x", devhdl)); 7984 break; 7985 7986 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET: 7987 NDBG20(("IOC's internally generated Target Reset " 7988 "completed for devhdl:%x", devhdl)); 7989 break; 7990 7991 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7992 NDBG20(("IOC internally generated Abort Task")); 7993 break; 7994 7995 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL: 7996 NDBG20(("IOC's internally generated Abort Task " 7997 "completed")); 7998 break; 7999 8000 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 8001 NDBG20(("IOC internally generated Abort Task Set")); 8002 break; 8003 8004 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 8005 NDBG20(("IOC internally generated Clear Task Set")); 8006 break; 8007 8008 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 8009 NDBG20(("IOC internally generated Query Task")); 8010 break; 8011 8012 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION: 8013 NDBG20(("Device sent an Asynchronous Notification")); 8014 break; 8015 8016 default: 8017 break; 8018 } 8019 break; 8020 } 8021 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 8022 { 8023 /* 8024 * IR TOPOLOGY CHANGE LIST Event has already been handled 8025 * in mpt_handle_event_sync() of interrupt context 8026 */ 8027 break; 8028 } 8029 case MPI2_EVENT_IR_OPERATION_STATUS: 8030 { 8031 Mpi2EventDataIrOperationStatus_t *irOpStatus; 8032 char reason_str[80]; 8033 uint8_t rc, percent; 8034 uint16_t handle; 8035 8036 irOpStatus = (pMpi2EventDataIrOperationStatus_t) 8037 eventreply->EventData; 8038 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 8039 &irOpStatus->RAIDOperation); 8040 percent = ddi_get8(mpt->m_acc_reply_frame_hdl, 8041 &irOpStatus->PercentComplete); 8042 handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8043 &irOpStatus->VolDevHandle); 8044 8045 switch (rc) { 8046 case MPI2_EVENT_IR_RAIDOP_RESYNC: 8047 (void) sprintf(reason_str, "resync"); 8048 break; 8049 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION: 8050 (void) sprintf(reason_str, "online capacity " 8051 "expansion"); 8052 break; 8053 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK: 8054 (void) sprintf(reason_str, "consistency check"); 8055 break; 8056 default: 8057 (void) sprintf(reason_str, "unknown reason %x", 8058 rc); 8059 } 8060 8061 NDBG20(("mptsas%d raid operational status: (%s)" 8062 "\thandle(0x%04x), percent complete(%d)\n", 8063 mpt->m_instance, reason_str, handle, percent)); 8064 break; 8065 } 8066 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 8067 { 8068 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast; 8069 uint8_t phy_num; 8070 uint8_t primitive; 8071 8072 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t) 8073 eventreply->EventData; 8074 8075 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 8076 &sas_broadcast->PhyNum); 8077 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl, 8078 &sas_broadcast->Primitive); 8079 8080 switch (primitive) { 8081 case MPI2_EVENT_PRIMITIVE_CHANGE: 8082 mptsas_smhba_log_sysevent(mpt, 8083 ESC_SAS_HBA_PORT_BROADCAST, 8084 SAS_PORT_BROADCAST_CHANGE, 8085 &mpt->m_phy_info[phy_num].smhba_info); 8086 break; 8087 case MPI2_EVENT_PRIMITIVE_SES: 8088 mptsas_smhba_log_sysevent(mpt, 8089 ESC_SAS_HBA_PORT_BROADCAST, 8090 SAS_PORT_BROADCAST_SES, 8091 &mpt->m_phy_info[phy_num].smhba_info); 8092 break; 8093 case MPI2_EVENT_PRIMITIVE_EXPANDER: 8094 mptsas_smhba_log_sysevent(mpt, 8095 ESC_SAS_HBA_PORT_BROADCAST, 8096 SAS_PORT_BROADCAST_D01_4, 8097 &mpt->m_phy_info[phy_num].smhba_info); 8098 break; 8099 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT: 8100 mptsas_smhba_log_sysevent(mpt, 8101 ESC_SAS_HBA_PORT_BROADCAST, 8102 SAS_PORT_BROADCAST_D04_7, 8103 &mpt->m_phy_info[phy_num].smhba_info); 8104 break; 8105 case MPI2_EVENT_PRIMITIVE_RESERVED3: 8106 mptsas_smhba_log_sysevent(mpt, 8107 ESC_SAS_HBA_PORT_BROADCAST, 8108 SAS_PORT_BROADCAST_D16_7, 8109 &mpt->m_phy_info[phy_num].smhba_info); 8110 break; 8111 case MPI2_EVENT_PRIMITIVE_RESERVED4: 8112 mptsas_smhba_log_sysevent(mpt, 8113 ESC_SAS_HBA_PORT_BROADCAST, 8114 SAS_PORT_BROADCAST_D29_7, 8115 &mpt->m_phy_info[phy_num].smhba_info); 8116 break; 8117 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED: 8118 mptsas_smhba_log_sysevent(mpt, 8119 ESC_SAS_HBA_PORT_BROADCAST, 8120 SAS_PORT_BROADCAST_D24_0, 8121 &mpt->m_phy_info[phy_num].smhba_info); 8122 break; 8123 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED: 8124 mptsas_smhba_log_sysevent(mpt, 8125 ESC_SAS_HBA_PORT_BROADCAST, 8126 SAS_PORT_BROADCAST_D27_4, 8127 &mpt->m_phy_info[phy_num].smhba_info); 8128 break; 8129 default: 8130 NDBG16(("mptsas%d: unknown BROADCAST PRIMITIVE" 8131 " %x received", 8132 mpt->m_instance, primitive)); 8133 break; 8134 } 8135 NDBG16(("mptsas%d sas broadcast primitive: " 8136 "\tprimitive(0x%04x), phy(%d) complete\n", 8137 mpt->m_instance, primitive, phy_num)); 8138 break; 8139 } 8140 case MPI2_EVENT_IR_VOLUME: 8141 { 8142 Mpi2EventDataIrVolume_t *irVolume; 8143 uint16_t devhandle; 8144 uint32_t state; 8145 int config, vol; 8146 uint8_t found = FALSE; 8147 8148 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData; 8149 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 8150 &irVolume->NewValue); 8151 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8152 &irVolume->VolDevHandle); 8153 8154 NDBG20(("EVENT_IR_VOLUME event is received")); 8155 8156 /* 8157 * Get latest RAID info and then find the DevHandle for this 8158 * event in the configuration. If the DevHandle is not found 8159 * just exit the event. 8160 */ 8161 (void) mptsas_get_raid_info(mpt); 8162 for (config = 0; (config < mpt->m_num_raid_configs) && 8163 (!found); config++) { 8164 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 8165 if (mpt->m_raidconfig[config].m_raidvol[vol]. 8166 m_raidhandle == devhandle) { 8167 found = TRUE; 8168 break; 8169 } 8170 } 8171 } 8172 if (!found) { 8173 break; 8174 } 8175 8176 switch (irVolume->ReasonCode) { 8177 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED: 8178 { 8179 uint32_t i; 8180 mpt->m_raidconfig[config].m_raidvol[vol].m_settings = 8181 state; 8182 8183 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING; 8184 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed" 8185 ", auto-config of hot-swap drives is %s" 8186 ", write caching is %s" 8187 ", hot-spare pool mask is %02x\n", 8188 vol, state & 8189 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE 8190 ? "disabled" : "enabled", 8191 i == MPI2_RAIDVOL0_SETTING_UNCHANGED 8192 ? "controlled by member disks" : 8193 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING 8194 ? "disabled" : 8195 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING 8196 ? "enabled" : 8197 "incorrectly set", 8198 (state >> 16) & 0xff); 8199 break; 8200 } 8201 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED: 8202 { 8203 mpt->m_raidconfig[config].m_raidvol[vol].m_state = 8204 (uint8_t)state; 8205 8206 mptsas_log(mpt, CE_NOTE, 8207 "Volume %d is now %s\n", vol, 8208 state == MPI2_RAID_VOL_STATE_OPTIMAL 8209 ? "optimal" : 8210 state == MPI2_RAID_VOL_STATE_DEGRADED 8211 ? "degraded" : 8212 state == MPI2_RAID_VOL_STATE_ONLINE 8213 ? "online" : 8214 state == MPI2_RAID_VOL_STATE_INITIALIZING 8215 ? "initializing" : 8216 state == MPI2_RAID_VOL_STATE_FAILED 8217 ? "failed" : 8218 state == MPI2_RAID_VOL_STATE_MISSING 8219 ? "missing" : 8220 "state unknown"); 8221 break; 8222 } 8223 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED: 8224 { 8225 mpt->m_raidconfig[config].m_raidvol[vol]. 8226 m_statusflags = state; 8227 8228 mptsas_log(mpt, CE_NOTE, 8229 " Volume %d is now %s%s%s%s%s%s%s%s%s\n", 8230 vol, 8231 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED 8232 ? ", enabled" : ", disabled", 8233 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED 8234 ? ", quiesced" : "", 8235 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE 8236 ? ", inactive" : ", active", 8237 state & 8238 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL 8239 ? ", bad block table is full" : "", 8240 state & 8241 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 8242 ? ", resync in progress" : "", 8243 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT 8244 ? ", background initialization in progress" : "", 8245 state & 8246 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION 8247 ? ", capacity expansion in progress" : "", 8248 state & 8249 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK 8250 ? ", consistency check in progress" : "", 8251 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB 8252 ? ", data scrub in progress" : ""); 8253 break; 8254 } 8255 default: 8256 break; 8257 } 8258 break; 8259 } 8260 case MPI2_EVENT_IR_PHYSICAL_DISK: 8261 { 8262 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk; 8263 uint16_t devhandle, enchandle, slot; 8264 uint32_t status, state; 8265 uint8_t physdisknum, reason; 8266 8267 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *) 8268 eventreply->EventData; 8269 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl, 8270 &irPhysDisk->PhysDiskNum); 8271 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8272 &irPhysDisk->PhysDiskDevHandle); 8273 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8274 &irPhysDisk->EnclosureHandle); 8275 slot = ddi_get16(mpt->m_acc_reply_frame_hdl, 8276 &irPhysDisk->Slot); 8277 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 8278 &irPhysDisk->NewValue); 8279 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 8280 &irPhysDisk->ReasonCode); 8281 8282 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received")); 8283 8284 switch (reason) { 8285 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED: 8286 mptsas_log(mpt, CE_NOTE, 8287 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8288 "for enclosure with handle 0x%x is now in hot " 8289 "spare pool %d", 8290 physdisknum, devhandle, slot, enchandle, 8291 (state >> 16) & 0xff); 8292 break; 8293 8294 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED: 8295 status = state; 8296 mptsas_log(mpt, CE_NOTE, 8297 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8298 "for enclosure with handle 0x%x is now " 8299 "%s%s%s%s%s\n", physdisknum, devhandle, slot, 8300 enchandle, 8301 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME 8302 ? ", inactive" : ", active", 8303 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 8304 ? ", out of sync" : "", 8305 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED 8306 ? ", quiesced" : "", 8307 status & 8308 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED 8309 ? ", write cache enabled" : "", 8310 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET 8311 ? ", capacity expansion target" : ""); 8312 break; 8313 8314 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED: 8315 mptsas_log(mpt, CE_NOTE, 8316 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8317 "for enclosure with handle 0x%x is now %s\n", 8318 physdisknum, devhandle, slot, enchandle, 8319 state == MPI2_RAID_PD_STATE_OPTIMAL 8320 ? "optimal" : 8321 state == MPI2_RAID_PD_STATE_REBUILDING 8322 ? "rebuilding" : 8323 state == MPI2_RAID_PD_STATE_DEGRADED 8324 ? "degraded" : 8325 state == MPI2_RAID_PD_STATE_HOT_SPARE 8326 ? "a hot spare" : 8327 state == MPI2_RAID_PD_STATE_ONLINE 8328 ? "online" : 8329 state == MPI2_RAID_PD_STATE_OFFLINE 8330 ? "offline" : 8331 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE 8332 ? "not compatible" : 8333 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED 8334 ? "not configured" : 8335 "state unknown"); 8336 break; 8337 } 8338 break; 8339 } 8340 case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION: 8341 { 8342 pMpi26EventDataActiveCableExcept_t actcable; 8343 uint32_t power; 8344 uint8_t reason, id; 8345 8346 actcable = (pMpi26EventDataActiveCableExcept_t) 8347 eventreply->EventData; 8348 power = ddi_get32(mpt->m_acc_reply_frame_hdl, 8349 &actcable->ActiveCablePowerRequirement); 8350 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 8351 &actcable->ReasonCode); 8352 id = ddi_get8(mpt->m_acc_reply_frame_hdl, 8353 &actcable->ReceptacleID); 8354 8355 /* 8356 * It'd be nice if this weren't just logging to the system but 8357 * were telling FMA about the active cable problem and FMA was 8358 * aware of the cable topology and state. 8359 */ 8360 switch (reason) { 8361 case MPI26_EVENT_ACTIVE_CABLE_PRESENT: 8362 /* Don't log anything if it's fine */ 8363 break; 8364 case MPI26_EVENT_ACTIVE_CABLE_INSUFFICIENT_POWER: 8365 mptsas_log(mpt, CE_WARN, "An active cable (id %u) does " 8366 "not have sufficient power to be enabled. " 8367 "Devices connected to this cable will not be " 8368 "visible to the system.", id); 8369 if (power == UINT32_MAX) { 8370 mptsas_log(mpt, CE_CONT, "The cable's power " 8371 "requirements are unknown.\n"); 8372 } else { 8373 mptsas_log(mpt, CE_CONT, "The cable requires " 8374 "%u mW of power to function.\n", power); 8375 } 8376 break; 8377 case MPI26_EVENT_ACTIVE_CABLE_DEGRADED: 8378 mptsas_log(mpt, CE_WARN, "An active cable (id %u) is " 8379 "degraded and not running at its full speed. " 8380 "Some devices might not appear.", id); 8381 break; 8382 default: 8383 break; 8384 } 8385 break; 8386 } 8387 case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE: 8388 case MPI2_EVENT_PCIE_ENUMERATION: 8389 case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 8390 case MPI2_EVENT_PCIE_LINK_COUNTER: 8391 mptsas_log(mpt, CE_NOTE, "Unhandled mpt_sas PCIe device " 8392 "event received (0x%x)", event); 8393 break; 8394 default: 8395 NDBG20(("mptsas%d: unknown event %x received", 8396 mpt->m_instance, event)); 8397 break; 8398 } 8399 8400 /* 8401 * Return the reply frame to the free queue. 8402 */ 8403 ddi_put32(mpt->m_acc_free_queue_hdl, 8404 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm); 8405 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 8406 DDI_DMA_SYNC_FORDEV); 8407 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 8408 mpt->m_free_index = 0; 8409 } 8410 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 8411 mpt->m_free_index); 8412 mutex_exit(&mpt->m_mutex); 8413 } 8414 8415 /* 8416 * invoked from timeout() to restart qfull cmds with throttle == 0 8417 */ 8418 static void 8419 mptsas_restart_cmd(void *arg) 8420 { 8421 mptsas_t *mpt = arg; 8422 mptsas_target_t *ptgt = NULL; 8423 8424 mutex_enter(&mpt->m_mutex); 8425 8426 mpt->m_restart_cmd_timeid = 0; 8427 8428 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 8429 ptgt = refhash_next(mpt->m_targets, ptgt)) { 8430 if (ptgt->m_reset_delay == 0) { 8431 if (ptgt->m_t_throttle == QFULL_THROTTLE) { 8432 mptsas_set_throttle(mpt, ptgt, 8433 MAX_THROTTLE); 8434 } 8435 } 8436 } 8437 mptsas_restart_hba(mpt); 8438 mutex_exit(&mpt->m_mutex); 8439 } 8440 8441 void 8442 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 8443 { 8444 int slot; 8445 mptsas_slots_t *slots = mpt->m_active; 8446 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8447 8448 ASSERT(cmd != NULL); 8449 ASSERT(cmd->cmd_queued == FALSE); 8450 8451 /* 8452 * Task Management cmds are removed in their own routines. Also, 8453 * we don't want to modify timeout based on TM cmds. 8454 */ 8455 if (cmd->cmd_flags & CFLAG_TM_CMD) { 8456 return; 8457 } 8458 8459 slot = cmd->cmd_slot; 8460 8461 /* 8462 * remove the cmd. 8463 */ 8464 if (cmd == slots->m_slot[slot]) { 8465 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags " 8466 "0x%x", (void *)cmd, cmd->cmd_flags)); 8467 slots->m_slot[slot] = NULL; 8468 mpt->m_ncmds--; 8469 8470 /* 8471 * only decrement per target ncmds if command 8472 * has a target associated with it. 8473 */ 8474 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 8475 ptgt->m_t_ncmds--; 8476 /* 8477 * reset throttle if we just ran an untagged command 8478 * to a tagged target 8479 */ 8480 if ((ptgt->m_t_ncmds == 0) && 8481 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) { 8482 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8483 } 8484 8485 /* 8486 * Remove this command from the active queue. 8487 */ 8488 if (cmd->cmd_active_expiration != 0) { 8489 TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd, 8490 cmd_active_link); 8491 cmd->cmd_active_expiration = 0; 8492 } 8493 } 8494 } 8495 8496 /* 8497 * This is all we need to do for ioc commands. 8498 */ 8499 if (cmd->cmd_flags & CFLAG_CMDIOC) { 8500 mptsas_return_to_pool(mpt, cmd); 8501 return; 8502 } 8503 8504 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]); 8505 } 8506 8507 /* 8508 * accept all cmds on the tx_waitq if any and then 8509 * start a fresh request from the top of the device queue. 8510 * 8511 * since there are always cmds queued on the tx_waitq, and rare cmds on 8512 * the instance waitq, so this function should not be invoked in the ISR, 8513 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the 8514 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU. 8515 */ 8516 static void 8517 mptsas_restart_hba(mptsas_t *mpt) 8518 { 8519 ASSERT(mutex_owned(&mpt->m_mutex)); 8520 8521 mutex_enter(&mpt->m_tx_waitq_mutex); 8522 if (mpt->m_tx_waitq) { 8523 mptsas_accept_tx_waitq(mpt); 8524 } 8525 mutex_exit(&mpt->m_tx_waitq_mutex); 8526 mptsas_restart_waitq(mpt); 8527 } 8528 8529 /* 8530 * start a fresh request from the top of the device queue 8531 */ 8532 static void 8533 mptsas_restart_waitq(mptsas_t *mpt) 8534 { 8535 mptsas_cmd_t *cmd, *next_cmd; 8536 mptsas_target_t *ptgt = NULL; 8537 8538 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt)); 8539 8540 ASSERT(mutex_owned(&mpt->m_mutex)); 8541 8542 /* 8543 * If there is a reset delay, don't start any cmds. Otherwise, start 8544 * as many cmds as possible. 8545 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 8546 * commands is m_max_requests - 2. 8547 */ 8548 cmd = mpt->m_waitq; 8549 8550 while (cmd != NULL) { 8551 next_cmd = cmd->cmd_linkp; 8552 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 8553 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8554 /* 8555 * passthru command get slot need 8556 * set CFLAG_PREPARED. 8557 */ 8558 cmd->cmd_flags |= CFLAG_PREPARED; 8559 mptsas_waitq_delete(mpt, cmd); 8560 mptsas_start_passthru(mpt, cmd); 8561 } 8562 cmd = next_cmd; 8563 continue; 8564 } 8565 if (cmd->cmd_flags & CFLAG_CONFIG) { 8566 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8567 /* 8568 * Send the config page request and delete it 8569 * from the waitq. 8570 */ 8571 cmd->cmd_flags |= CFLAG_PREPARED; 8572 mptsas_waitq_delete(mpt, cmd); 8573 mptsas_start_config_page_access(mpt, cmd); 8574 } 8575 cmd = next_cmd; 8576 continue; 8577 } 8578 if (cmd->cmd_flags & CFLAG_FW_DIAG) { 8579 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8580 /* 8581 * Send the FW Diag request and delete if from 8582 * the waitq. 8583 */ 8584 cmd->cmd_flags |= CFLAG_PREPARED; 8585 mptsas_waitq_delete(mpt, cmd); 8586 mptsas_start_diag(mpt, cmd); 8587 } 8588 cmd = next_cmd; 8589 continue; 8590 } 8591 8592 ptgt = cmd->cmd_tgt_addr; 8593 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) && 8594 (ptgt->m_t_ncmds == 0)) { 8595 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8596 } 8597 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 8598 (ptgt && (ptgt->m_reset_delay == 0)) && 8599 (ptgt && (ptgt->m_t_ncmds < 8600 ptgt->m_t_throttle))) { 8601 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8602 mptsas_waitq_delete(mpt, cmd); 8603 (void) mptsas_start_cmd(mpt, cmd); 8604 } 8605 } 8606 cmd = next_cmd; 8607 } 8608 } 8609 /* 8610 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait). 8611 * Accept all those queued cmds before new cmd is accept so that the 8612 * cmds are sent in order. 8613 */ 8614 static void 8615 mptsas_accept_tx_waitq(mptsas_t *mpt) 8616 { 8617 mptsas_cmd_t *cmd; 8618 8619 ASSERT(mutex_owned(&mpt->m_mutex)); 8620 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex)); 8621 8622 /* 8623 * A Bus Reset could occur at any time and flush the tx_waitq, 8624 * so we cannot count on the tx_waitq to contain even one cmd. 8625 * And when the m_tx_waitq_mutex is released and run 8626 * mptsas_accept_pkt(), the tx_waitq may be flushed. 8627 */ 8628 cmd = mpt->m_tx_waitq; 8629 for (;;) { 8630 if ((cmd = mpt->m_tx_waitq) == NULL) { 8631 mpt->m_tx_draining = 0; 8632 break; 8633 } 8634 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) { 8635 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 8636 } 8637 cmd->cmd_linkp = NULL; 8638 mutex_exit(&mpt->m_tx_waitq_mutex); 8639 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT) 8640 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed " 8641 "to accept cmd on queue\n"); 8642 mutex_enter(&mpt->m_tx_waitq_mutex); 8643 } 8644 } 8645 8646 8647 /* 8648 * mpt tag type lookup 8649 */ 8650 static char mptsas_tag_lookup[] = 8651 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG}; 8652 8653 static int 8654 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 8655 { 8656 struct scsi_pkt *pkt = CMD2PKT(cmd); 8657 uint32_t control = 0; 8658 caddr_t mem, arsbuf; 8659 pMpi2SCSIIORequest_t io_request; 8660 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 8661 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 8662 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8663 uint16_t SMID, io_flags = 0; 8664 uint8_t ars_size; 8665 uint64_t request_desc; 8666 uint32_t ars_dmaaddrlow; 8667 mptsas_cmd_t *c; 8668 8669 NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd, 8670 cmd->cmd_flags)); 8671 8672 /* 8673 * Set SMID and increment index. Rollover to 1 instead of 0 if index 8674 * is at the max. 0 is an invalid SMID, so we call the first index 1. 8675 */ 8676 SMID = cmd->cmd_slot; 8677 8678 /* 8679 * It is possible for back to back device reset to 8680 * happen before the reset delay has expired. That's 8681 * ok, just let the device reset go out on the bus. 8682 */ 8683 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8684 ASSERT(ptgt->m_reset_delay == 0); 8685 } 8686 8687 /* 8688 * if a non-tagged cmd is submitted to an active tagged target 8689 * then drain before submitting this cmd; SCSI-2 allows RQSENSE 8690 * to be untagged 8691 */ 8692 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) && 8693 (ptgt->m_t_ncmds > 1) && 8694 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) && 8695 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) { 8696 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8697 NDBG23(("target=%d, untagged cmd, start draining\n", 8698 ptgt->m_devhdl)); 8699 8700 if (ptgt->m_reset_delay == 0) { 8701 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 8702 } 8703 8704 mptsas_remove_cmd(mpt, cmd); 8705 cmd->cmd_pkt_flags |= FLAG_HEAD; 8706 mptsas_waitq_add(mpt, cmd); 8707 } 8708 return (DDI_FAILURE); 8709 } 8710 8711 /* 8712 * Set correct tag bits. 8713 */ 8714 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) { 8715 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags & 8716 FLAG_TAGMASK) >> 12)]) { 8717 case MSG_SIMPLE_QTAG: 8718 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8719 break; 8720 case MSG_HEAD_QTAG: 8721 control |= MPI2_SCSIIO_CONTROL_HEADOFQ; 8722 break; 8723 case MSG_ORDERED_QTAG: 8724 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ; 8725 break; 8726 default: 8727 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n"); 8728 break; 8729 } 8730 } else { 8731 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) { 8732 ptgt->m_t_throttle = 1; 8733 } 8734 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8735 } 8736 8737 if (cmd->cmd_pkt_flags & FLAG_TLR) { 8738 control |= MPI2_SCSIIO_CONTROL_TLR_ON; 8739 } 8740 8741 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 8742 io_request = (pMpi2SCSIIORequest_t)mem; 8743 if (cmd->cmd_extrqslen != 0) { 8744 /* 8745 * Mapping of the buffer was done in mptsas_pkt_alloc_extern(). 8746 * Calculate the DMA address with the same offset. 8747 */ 8748 arsbuf = cmd->cmd_arq_buf; 8749 ars_size = cmd->cmd_extrqslen; 8750 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 8751 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) & 8752 0xffffffffu; 8753 } else { 8754 arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1)); 8755 cmd->cmd_arq_buf = arsbuf; 8756 ars_size = mpt->m_req_sense_size; 8757 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 8758 (mpt->m_req_sense_size * (SMID-1))) & 8759 0xffffffffu; 8760 } 8761 bzero(io_request, sizeof (Mpi2SCSIIORequest_t)); 8762 bzero(arsbuf, ars_size); 8763 8764 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof 8765 (MPI2_SCSI_IO_REQUEST, SGL) / 4); 8766 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0, 8767 MPI2_FUNCTION_SCSI_IO_REQUEST); 8768 8769 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp, 8770 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR); 8771 8772 io_flags = cmd->cmd_cdblen; 8773 if (mptsas_use_fastpath && 8774 ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) { 8775 io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH; 8776 request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 8777 } else { 8778 request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 8779 } 8780 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags); 8781 /* 8782 * setup the Scatter/Gather DMA list for this request 8783 */ 8784 if (cmd->cmd_cookiec > 0) { 8785 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl); 8786 } else { 8787 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength, 8788 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT | 8789 MPI2_SGE_FLAGS_END_OF_BUFFER | 8790 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 8791 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT); 8792 } 8793 8794 /* 8795 * save ARQ information 8796 */ 8797 ddi_put8(acc_hdl, &io_request->SenseBufferLength, ars_size); 8798 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow); 8799 8800 ddi_put32(acc_hdl, &io_request->Control, control); 8801 8802 NDBG31(("starting message=%d(0x%p), with cmd=0x%p", 8803 SMID, (void *)io_request, (void *)cmd)); 8804 8805 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 8806 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 8807 DDI_DMA_SYNC_FORDEV); 8808 8809 /* 8810 * Build request descriptor and write it to the request desc post reg. 8811 */ 8812 request_desc |= (SMID << 16); 8813 request_desc |= (uint64_t)ptgt->m_devhdl << 48; 8814 MPTSAS_START_CMD(mpt, request_desc); 8815 8816 /* 8817 * Start timeout. 8818 */ 8819 cmd->cmd_active_expiration = 8820 gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC; 8821 #ifdef MPTSAS_TEST 8822 /* 8823 * Force timeouts to happen immediately. 8824 */ 8825 if (mptsas_test_timeouts) 8826 cmd->cmd_active_expiration = gethrtime(); 8827 #endif 8828 c = TAILQ_FIRST(&ptgt->m_active_cmdq); 8829 if (c == NULL || 8830 c->cmd_active_expiration < cmd->cmd_active_expiration) { 8831 /* 8832 * Common case is that this is the last pending expiration 8833 * (or queue is empty). Insert at head of the queue. 8834 */ 8835 TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link); 8836 } else { 8837 /* 8838 * Queue is not empty and first element expires later than 8839 * this command. Search for element expiring sooner. 8840 */ 8841 while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) { 8842 if (c->cmd_active_expiration < 8843 cmd->cmd_active_expiration) { 8844 TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link); 8845 break; 8846 } 8847 } 8848 if (c == NULL) { 8849 /* 8850 * No element found expiring sooner, append to 8851 * non-empty queue. 8852 */ 8853 TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd, 8854 cmd_active_link); 8855 } 8856 } 8857 8858 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 8859 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 8860 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8861 return (DDI_FAILURE); 8862 } 8863 return (DDI_SUCCESS); 8864 } 8865 8866 /* 8867 * Select a helper thread to handle current doneq 8868 */ 8869 static void 8870 mptsas_deliver_doneq_thread(mptsas_t *mpt) 8871 { 8872 uint64_t t, i; 8873 uint32_t min = 0xffffffff; 8874 mptsas_doneq_thread_list_t *item; 8875 8876 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 8877 item = &mpt->m_doneq_thread_id[i]; 8878 /* 8879 * If the completed command on help thread[i] less than 8880 * doneq_thread_threshold, then pick the thread[i]. Otherwise 8881 * pick a thread which has least completed command. 8882 */ 8883 8884 mutex_enter(&item->mutex); 8885 if (item->len < mpt->m_doneq_thread_threshold) { 8886 t = i; 8887 mutex_exit(&item->mutex); 8888 break; 8889 } 8890 if (item->len < min) { 8891 min = item->len; 8892 t = i; 8893 } 8894 mutex_exit(&item->mutex); 8895 } 8896 mutex_enter(&mpt->m_doneq_thread_id[t].mutex); 8897 mptsas_doneq_mv(mpt, t); 8898 cv_signal(&mpt->m_doneq_thread_id[t].cv); 8899 mutex_exit(&mpt->m_doneq_thread_id[t].mutex); 8900 } 8901 8902 /* 8903 * move the current global doneq to the doneq of thead[t] 8904 */ 8905 static void 8906 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t) 8907 { 8908 mptsas_cmd_t *cmd; 8909 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8910 8911 ASSERT(mutex_owned(&item->mutex)); 8912 while ((cmd = mpt->m_doneq) != NULL) { 8913 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) { 8914 mpt->m_donetail = &mpt->m_doneq; 8915 } 8916 cmd->cmd_linkp = NULL; 8917 *item->donetail = cmd; 8918 item->donetail = &cmd->cmd_linkp; 8919 mpt->m_doneq_len--; 8920 item->len++; 8921 } 8922 } 8923 8924 void 8925 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd) 8926 { 8927 struct scsi_pkt *pkt = CMD2PKT(cmd); 8928 8929 /* Check all acc and dma handles */ 8930 if ((mptsas_check_acc_handle(mpt->m_datap) != 8931 DDI_SUCCESS) || 8932 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 8933 DDI_SUCCESS) || 8934 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) != 8935 DDI_SUCCESS) || 8936 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 8937 DDI_SUCCESS) || 8938 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 8939 DDI_SUCCESS) || 8940 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 8941 DDI_SUCCESS) || 8942 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 8943 DDI_SUCCESS) || 8944 (mptsas_check_acc_handle(mpt->m_config_handle) != 8945 DDI_SUCCESS)) { 8946 ddi_fm_service_impact(mpt->m_dip, 8947 DDI_SERVICE_UNAFFECTED); 8948 ddi_fm_acc_err_clear(mpt->m_config_handle, 8949 DDI_FME_VER0); 8950 pkt->pkt_reason = CMD_TRAN_ERR; 8951 pkt->pkt_statistics = 0; 8952 } 8953 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 8954 DDI_SUCCESS) || 8955 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) != 8956 DDI_SUCCESS) || 8957 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 8958 DDI_SUCCESS) || 8959 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 8960 DDI_SUCCESS) || 8961 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 8962 DDI_SUCCESS) || 8963 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 8964 DDI_SUCCESS)) { 8965 ddi_fm_service_impact(mpt->m_dip, 8966 DDI_SERVICE_UNAFFECTED); 8967 pkt->pkt_reason = CMD_TRAN_ERR; 8968 pkt->pkt_statistics = 0; 8969 } 8970 if (cmd->cmd_dmahandle && 8971 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) { 8972 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8973 pkt->pkt_reason = CMD_TRAN_ERR; 8974 pkt->pkt_statistics = 0; 8975 } 8976 if ((cmd->cmd_extra_frames && 8977 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) != 8978 DDI_SUCCESS) || 8979 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) != 8980 DDI_SUCCESS)))) { 8981 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8982 pkt->pkt_reason = CMD_TRAN_ERR; 8983 pkt->pkt_statistics = 0; 8984 } 8985 } 8986 8987 /* 8988 * These routines manipulate the queue of commands that 8989 * are waiting for their completion routines to be called. 8990 * The queue is usually in FIFO order but on an MP system 8991 * it's possible for the completion routines to get out 8992 * of order. If that's a problem you need to add a global 8993 * mutex around the code that calls the completion routine 8994 * in the interrupt handler. 8995 */ 8996 static void 8997 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 8998 { 8999 struct scsi_pkt *pkt = CMD2PKT(cmd); 9000 9001 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd)); 9002 9003 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0); 9004 cmd->cmd_linkp = NULL; 9005 cmd->cmd_flags |= CFLAG_FINISHED; 9006 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT; 9007 9008 mptsas_fma_check(mpt, cmd); 9009 9010 /* 9011 * only add scsi pkts that have completion routines to 9012 * the doneq. no intr cmds do not have callbacks. 9013 */ 9014 if (pkt && (pkt->pkt_comp)) { 9015 *mpt->m_donetail = cmd; 9016 mpt->m_donetail = &cmd->cmd_linkp; 9017 mpt->m_doneq_len++; 9018 } 9019 } 9020 9021 static mptsas_cmd_t * 9022 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t) 9023 { 9024 mptsas_cmd_t *cmd; 9025 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 9026 9027 /* pop one off the done queue */ 9028 if ((cmd = item->doneq) != NULL) { 9029 /* if the queue is now empty fix the tail pointer */ 9030 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd)); 9031 if ((item->doneq = cmd->cmd_linkp) == NULL) { 9032 item->donetail = &item->doneq; 9033 } 9034 cmd->cmd_linkp = NULL; 9035 item->len--; 9036 } 9037 return (cmd); 9038 } 9039 9040 static void 9041 mptsas_doneq_empty(mptsas_t *mpt) 9042 { 9043 if (mpt->m_doneq && !mpt->m_in_callback) { 9044 mptsas_cmd_t *cmd, *next; 9045 struct scsi_pkt *pkt; 9046 9047 mpt->m_in_callback = 1; 9048 cmd = mpt->m_doneq; 9049 mpt->m_doneq = NULL; 9050 mpt->m_donetail = &mpt->m_doneq; 9051 mpt->m_doneq_len = 0; 9052 9053 mutex_exit(&mpt->m_mutex); 9054 /* 9055 * run the completion routines of all the 9056 * completed commands 9057 */ 9058 while (cmd != NULL) { 9059 next = cmd->cmd_linkp; 9060 cmd->cmd_linkp = NULL; 9061 /* run this command's completion routine */ 9062 cmd->cmd_flags |= CFLAG_COMPLETED; 9063 pkt = CMD2PKT(cmd); 9064 mptsas_pkt_comp(pkt, cmd); 9065 cmd = next; 9066 } 9067 mutex_enter(&mpt->m_mutex); 9068 mpt->m_in_callback = 0; 9069 } 9070 } 9071 9072 /* 9073 * These routines manipulate the target's queue of pending requests 9074 */ 9075 void 9076 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 9077 { 9078 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd)); 9079 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 9080 cmd->cmd_queued = TRUE; 9081 if (ptgt) 9082 ptgt->m_t_nwait++; 9083 if (cmd->cmd_pkt_flags & FLAG_HEAD) { 9084 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) { 9085 mpt->m_waitqtail = &cmd->cmd_linkp; 9086 } 9087 mpt->m_waitq = cmd; 9088 } else { 9089 cmd->cmd_linkp = NULL; 9090 *(mpt->m_waitqtail) = cmd; 9091 mpt->m_waitqtail = &cmd->cmd_linkp; 9092 } 9093 } 9094 9095 static mptsas_cmd_t * 9096 mptsas_waitq_rm(mptsas_t *mpt) 9097 { 9098 mptsas_cmd_t *cmd; 9099 mptsas_target_t *ptgt; 9100 NDBG7(("mptsas_waitq_rm")); 9101 9102 MPTSAS_WAITQ_RM(mpt, cmd); 9103 9104 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd)); 9105 if (cmd) { 9106 ptgt = cmd->cmd_tgt_addr; 9107 if (ptgt) { 9108 ptgt->m_t_nwait--; 9109 ASSERT(ptgt->m_t_nwait >= 0); 9110 } 9111 } 9112 return (cmd); 9113 } 9114 9115 /* 9116 * remove specified cmd from the middle of the wait queue. 9117 */ 9118 static void 9119 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 9120 { 9121 mptsas_cmd_t *prevp = mpt->m_waitq; 9122 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 9123 9124 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 9125 (void *)mpt, (void *)cmd)); 9126 if (ptgt) { 9127 ptgt->m_t_nwait--; 9128 ASSERT(ptgt->m_t_nwait >= 0); 9129 } 9130 9131 if (prevp == cmd) { 9132 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL) 9133 mpt->m_waitqtail = &mpt->m_waitq; 9134 9135 cmd->cmd_linkp = NULL; 9136 cmd->cmd_queued = FALSE; 9137 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 9138 (void *)mpt, (void *)cmd)); 9139 return; 9140 } 9141 9142 while (prevp != NULL) { 9143 if (prevp->cmd_linkp == cmd) { 9144 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 9145 mpt->m_waitqtail = &prevp->cmd_linkp; 9146 9147 cmd->cmd_linkp = NULL; 9148 cmd->cmd_queued = FALSE; 9149 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 9150 (void *)mpt, (void *)cmd)); 9151 return; 9152 } 9153 prevp = prevp->cmd_linkp; 9154 } 9155 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch"); 9156 } 9157 9158 static mptsas_cmd_t * 9159 mptsas_tx_waitq_rm(mptsas_t *mpt) 9160 { 9161 mptsas_cmd_t *cmd; 9162 NDBG7(("mptsas_tx_waitq_rm")); 9163 9164 MPTSAS_TX_WAITQ_RM(mpt, cmd); 9165 9166 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd)); 9167 9168 return (cmd); 9169 } 9170 9171 /* 9172 * remove specified cmd from the middle of the tx_waitq. 9173 */ 9174 static void 9175 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 9176 { 9177 mptsas_cmd_t *prevp = mpt->m_tx_waitq; 9178 9179 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9180 (void *)mpt, (void *)cmd)); 9181 9182 if (prevp == cmd) { 9183 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) 9184 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 9185 9186 cmd->cmd_linkp = NULL; 9187 cmd->cmd_queued = FALSE; 9188 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9189 (void *)mpt, (void *)cmd)); 9190 return; 9191 } 9192 9193 while (prevp != NULL) { 9194 if (prevp->cmd_linkp == cmd) { 9195 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 9196 mpt->m_tx_waitqtail = &prevp->cmd_linkp; 9197 9198 cmd->cmd_linkp = NULL; 9199 cmd->cmd_queued = FALSE; 9200 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9201 (void *)mpt, (void *)cmd)); 9202 return; 9203 } 9204 prevp = prevp->cmd_linkp; 9205 } 9206 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch"); 9207 } 9208 9209 /* 9210 * device and bus reset handling 9211 * 9212 * Notes: 9213 * - RESET_ALL: reset the controller 9214 * - RESET_TARGET: reset the target specified in scsi_address 9215 */ 9216 static int 9217 mptsas_scsi_reset(struct scsi_address *ap, int level) 9218 { 9219 mptsas_t *mpt = ADDR2MPT(ap); 9220 int rval; 9221 mptsas_tgt_private_t *tgt_private; 9222 mptsas_target_t *ptgt = NULL; 9223 9224 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private; 9225 ptgt = tgt_private->t_private; 9226 if (ptgt == NULL) { 9227 return (FALSE); 9228 } 9229 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl, 9230 level)); 9231 9232 mutex_enter(&mpt->m_mutex); 9233 /* 9234 * if we are not in panic set up a reset delay for this target 9235 */ 9236 if (!ddi_in_panic()) { 9237 mptsas_setup_bus_reset_delay(mpt); 9238 } else { 9239 drv_usecwait(mpt->m_scsi_reset_delay * 1000); 9240 } 9241 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl); 9242 mutex_exit(&mpt->m_mutex); 9243 9244 /* 9245 * The transport layer expect to only see TRUE and 9246 * FALSE. Therefore, we will adjust the return value 9247 * if mptsas_do_scsi_reset returns FAILED. 9248 */ 9249 if (rval == FAILED) 9250 rval = FALSE; 9251 return (rval); 9252 } 9253 9254 static int 9255 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl) 9256 { 9257 int rval = FALSE; 9258 uint8_t config, disk; 9259 9260 ASSERT(mutex_owned(&mpt->m_mutex)); 9261 9262 if (mptsas_debug_resets) { 9263 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d", 9264 devhdl); 9265 } 9266 9267 /* 9268 * Issue a Target Reset message to the target specified but not to a 9269 * disk making up a raid volume. Just look through the RAID config 9270 * Phys Disk list of DevHandles. If the target's DevHandle is in this 9271 * list, then don't reset this target. 9272 */ 9273 for (config = 0; config < mpt->m_num_raid_configs; config++) { 9274 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 9275 if (devhdl == mpt->m_raidconfig[config]. 9276 m_physdisk_devhdl[disk]) { 9277 return (TRUE); 9278 } 9279 } 9280 } 9281 9282 rval = mptsas_ioc_task_management(mpt, 9283 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0); 9284 9285 mptsas_doneq_empty(mpt); 9286 return (rval); 9287 } 9288 9289 static int 9290 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 9291 void (*callback)(caddr_t), caddr_t arg) 9292 { 9293 mptsas_t *mpt = ADDR2MPT(ap); 9294 9295 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target)); 9296 9297 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg, 9298 &mpt->m_mutex, &mpt->m_reset_notify_listf)); 9299 } 9300 9301 static int 9302 mptsas_get_name(struct scsi_device *sd, char *name, int len) 9303 { 9304 dev_info_t *lun_dip = NULL; 9305 9306 ASSERT(sd != NULL); 9307 ASSERT(name != NULL); 9308 lun_dip = sd->sd_dev; 9309 ASSERT(lun_dip != NULL); 9310 9311 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) { 9312 return (1); 9313 } else { 9314 return (0); 9315 } 9316 } 9317 9318 static int 9319 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len) 9320 { 9321 return (mptsas_get_name(sd, name, len)); 9322 } 9323 9324 void 9325 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what) 9326 { 9327 9328 NDBG25(("mptsas_set_throttle: throttle=%x", what)); 9329 9330 /* 9331 * if the bus is draining/quiesced, no changes to the throttles 9332 * are allowed. Not allowing change of throttles during draining 9333 * limits error recovery but will reduce draining time 9334 * 9335 * all throttles should have been set to HOLD_THROTTLE 9336 */ 9337 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) { 9338 return; 9339 } 9340 9341 if (what == HOLD_THROTTLE) { 9342 ptgt->m_t_throttle = HOLD_THROTTLE; 9343 } else if (ptgt->m_reset_delay == 0) { 9344 ptgt->m_t_throttle = what; 9345 } 9346 } 9347 9348 /* 9349 * Clean up from a device reset. 9350 * For the case of target reset, this function clears the waitq of all 9351 * commands for a particular target. For the case of abort task set, this 9352 * function clears the waitq of all commonds for a particular target/lun. 9353 */ 9354 static void 9355 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype) 9356 { 9357 mptsas_slots_t *slots = mpt->m_active; 9358 mptsas_cmd_t *cmd, *next_cmd; 9359 int slot; 9360 uchar_t reason; 9361 uint_t stat; 9362 hrtime_t timestamp; 9363 9364 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun)); 9365 9366 timestamp = gethrtime(); 9367 9368 /* 9369 * Make sure the I/O Controller has flushed all cmds 9370 * that are associated with this target for a target reset 9371 * and target/lun for abort task set. 9372 * Account for TM requests, which use the last SMID. 9373 */ 9374 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 9375 if ((cmd = slots->m_slot[slot]) == NULL) 9376 continue; 9377 reason = CMD_RESET; 9378 stat = STAT_DEV_RESET; 9379 switch (tasktype) { 9380 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9381 if (Tgt(cmd) == target) { 9382 if (cmd->cmd_active_expiration <= timestamp) { 9383 /* 9384 * When timeout requested, propagate 9385 * proper reason and statistics to 9386 * target drivers. 9387 */ 9388 reason = CMD_TIMEOUT; 9389 stat |= STAT_TIMEOUT; 9390 } 9391 NDBG25(("mptsas_flush_target discovered non-" 9392 "NULL cmd in slot %d, tasktype 0x%x", slot, 9393 tasktype)); 9394 mptsas_dump_cmd(mpt, cmd); 9395 mptsas_remove_cmd(mpt, cmd); 9396 mptsas_set_pkt_reason(mpt, cmd, reason, stat); 9397 mptsas_doneq_add(mpt, cmd); 9398 } 9399 break; 9400 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9401 reason = CMD_ABORTED; 9402 stat = STAT_ABORTED; 9403 /*FALLTHROUGH*/ 9404 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9405 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9406 9407 NDBG25(("mptsas_flush_target discovered non-" 9408 "NULL cmd in slot %d, tasktype 0x%x", slot, 9409 tasktype)); 9410 mptsas_dump_cmd(mpt, cmd); 9411 mptsas_remove_cmd(mpt, cmd); 9412 mptsas_set_pkt_reason(mpt, cmd, reason, 9413 stat); 9414 mptsas_doneq_add(mpt, cmd); 9415 } 9416 break; 9417 default: 9418 break; 9419 } 9420 } 9421 9422 /* 9423 * Flush the waitq and tx_waitq of this target's cmds 9424 */ 9425 cmd = mpt->m_waitq; 9426 9427 reason = CMD_RESET; 9428 stat = STAT_DEV_RESET; 9429 9430 switch (tasktype) { 9431 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9432 while (cmd != NULL) { 9433 next_cmd = cmd->cmd_linkp; 9434 if (Tgt(cmd) == target) { 9435 mptsas_waitq_delete(mpt, cmd); 9436 mptsas_set_pkt_reason(mpt, cmd, 9437 reason, stat); 9438 mptsas_doneq_add(mpt, cmd); 9439 } 9440 cmd = next_cmd; 9441 } 9442 mutex_enter(&mpt->m_tx_waitq_mutex); 9443 cmd = mpt->m_tx_waitq; 9444 while (cmd != NULL) { 9445 next_cmd = cmd->cmd_linkp; 9446 if (Tgt(cmd) == target) { 9447 mptsas_tx_waitq_delete(mpt, cmd); 9448 mutex_exit(&mpt->m_tx_waitq_mutex); 9449 mptsas_set_pkt_reason(mpt, cmd, 9450 reason, stat); 9451 mptsas_doneq_add(mpt, cmd); 9452 mutex_enter(&mpt->m_tx_waitq_mutex); 9453 } 9454 cmd = next_cmd; 9455 } 9456 mutex_exit(&mpt->m_tx_waitq_mutex); 9457 break; 9458 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9459 reason = CMD_ABORTED; 9460 stat = STAT_ABORTED; 9461 /*FALLTHROUGH*/ 9462 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9463 while (cmd != NULL) { 9464 next_cmd = cmd->cmd_linkp; 9465 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9466 mptsas_waitq_delete(mpt, cmd); 9467 mptsas_set_pkt_reason(mpt, cmd, 9468 reason, stat); 9469 mptsas_doneq_add(mpt, cmd); 9470 } 9471 cmd = next_cmd; 9472 } 9473 mutex_enter(&mpt->m_tx_waitq_mutex); 9474 cmd = mpt->m_tx_waitq; 9475 while (cmd != NULL) { 9476 next_cmd = cmd->cmd_linkp; 9477 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9478 mptsas_tx_waitq_delete(mpt, cmd); 9479 mutex_exit(&mpt->m_tx_waitq_mutex); 9480 mptsas_set_pkt_reason(mpt, cmd, 9481 reason, stat); 9482 mptsas_doneq_add(mpt, cmd); 9483 mutex_enter(&mpt->m_tx_waitq_mutex); 9484 } 9485 cmd = next_cmd; 9486 } 9487 mutex_exit(&mpt->m_tx_waitq_mutex); 9488 break; 9489 default: 9490 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 9491 tasktype); 9492 break; 9493 } 9494 } 9495 9496 /* 9497 * Clean up hba state, abort all outstanding command and commands in waitq 9498 * reset timeout of all targets. 9499 */ 9500 static void 9501 mptsas_flush_hba(mptsas_t *mpt) 9502 { 9503 mptsas_slots_t *slots = mpt->m_active; 9504 mptsas_cmd_t *cmd; 9505 int slot; 9506 9507 NDBG25(("mptsas_flush_hba")); 9508 9509 /* 9510 * The I/O Controller should have already sent back 9511 * all commands via the scsi I/O reply frame. Make 9512 * sure all commands have been flushed. 9513 * Account for TM request, which use the last SMID. 9514 */ 9515 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 9516 if ((cmd = slots->m_slot[slot]) == NULL) 9517 continue; 9518 9519 if (cmd->cmd_flags & CFLAG_CMDIOC) { 9520 /* 9521 * Need to make sure to tell everyone that might be 9522 * waiting on this command that it's going to fail. If 9523 * we get here, this command will never timeout because 9524 * the active command table is going to be re-allocated, 9525 * so there will be nothing to check against a time out. 9526 * Instead, mark the command as failed due to reset. 9527 */ 9528 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 9529 STAT_BUS_RESET); 9530 if ((cmd->cmd_flags & 9531 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) { 9532 cmd->cmd_flags |= CFLAG_FINISHED; 9533 cv_broadcast(&mpt->m_passthru_cv); 9534 cv_broadcast(&mpt->m_config_cv); 9535 cv_broadcast(&mpt->m_fw_diag_cv); 9536 } 9537 continue; 9538 } 9539 9540 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d", 9541 slot)); 9542 mptsas_dump_cmd(mpt, cmd); 9543 9544 mptsas_remove_cmd(mpt, cmd); 9545 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9546 mptsas_doneq_add(mpt, cmd); 9547 } 9548 9549 /* 9550 * Flush the waitq. 9551 */ 9552 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) { 9553 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9554 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 9555 (cmd->cmd_flags & CFLAG_CONFIG) || 9556 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 9557 cmd->cmd_flags |= CFLAG_FINISHED; 9558 cv_broadcast(&mpt->m_passthru_cv); 9559 cv_broadcast(&mpt->m_config_cv); 9560 cv_broadcast(&mpt->m_fw_diag_cv); 9561 } else { 9562 mptsas_doneq_add(mpt, cmd); 9563 } 9564 } 9565 9566 /* 9567 * Flush the tx_waitq 9568 */ 9569 mutex_enter(&mpt->m_tx_waitq_mutex); 9570 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) { 9571 mutex_exit(&mpt->m_tx_waitq_mutex); 9572 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9573 mptsas_doneq_add(mpt, cmd); 9574 mutex_enter(&mpt->m_tx_waitq_mutex); 9575 } 9576 mutex_exit(&mpt->m_tx_waitq_mutex); 9577 9578 /* 9579 * Drain the taskqs prior to reallocating resources. The thread 9580 * passing through here could be launched from either (dr) 9581 * or (event) taskqs so only wait on the 'other' queue since 9582 * waiting on 'this' queue is a deadlock condition. 9583 */ 9584 mutex_exit(&mpt->m_mutex); 9585 if (!taskq_member((taskq_t *)mpt->m_event_taskq, curthread)) 9586 ddi_taskq_wait(mpt->m_event_taskq); 9587 if (!taskq_member((taskq_t *)mpt->m_dr_taskq, curthread)) 9588 ddi_taskq_wait(mpt->m_dr_taskq); 9589 9590 mutex_enter(&mpt->m_mutex); 9591 } 9592 9593 /* 9594 * set pkt_reason and OR in pkt_statistics flag 9595 */ 9596 static void 9597 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason, 9598 uint_t stat) 9599 { 9600 #ifndef __lock_lint 9601 _NOTE(ARGUNUSED(mpt)) 9602 #endif 9603 9604 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x", 9605 (void *)cmd, reason, stat)); 9606 9607 if (cmd) { 9608 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) { 9609 cmd->cmd_pkt->pkt_reason = reason; 9610 } 9611 cmd->cmd_pkt->pkt_statistics |= stat; 9612 } 9613 } 9614 9615 static void 9616 mptsas_start_watch_reset_delay() 9617 { 9618 NDBG22(("mptsas_start_watch_reset_delay")); 9619 9620 mutex_enter(&mptsas_global_mutex); 9621 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) { 9622 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL, 9623 drv_usectohz((clock_t) 9624 MPTSAS_WATCH_RESET_DELAY_TICK * 1000)); 9625 ASSERT(mptsas_reset_watch != NULL); 9626 } 9627 mutex_exit(&mptsas_global_mutex); 9628 } 9629 9630 static void 9631 mptsas_setup_bus_reset_delay(mptsas_t *mpt) 9632 { 9633 mptsas_target_t *ptgt = NULL; 9634 9635 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 9636 9637 NDBG22(("mptsas_setup_bus_reset_delay")); 9638 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9639 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9640 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 9641 ptgt->m_reset_delay = mpt->m_scsi_reset_delay; 9642 } 9643 9644 mptsas_start_watch_reset_delay(); 9645 } 9646 9647 /* 9648 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every 9649 * mpt instance for active reset delays 9650 */ 9651 static void 9652 mptsas_watch_reset_delay(void *arg) 9653 { 9654 #ifndef __lock_lint 9655 _NOTE(ARGUNUSED(arg)) 9656 #endif 9657 9658 mptsas_t *mpt; 9659 int not_done = 0; 9660 9661 NDBG22(("mptsas_watch_reset_delay")); 9662 9663 mutex_enter(&mptsas_global_mutex); 9664 mptsas_reset_watch = 0; 9665 mutex_exit(&mptsas_global_mutex); 9666 rw_enter(&mptsas_global_rwlock, RW_READER); 9667 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) { 9668 if (mpt->m_tran == 0) { 9669 continue; 9670 } 9671 mutex_enter(&mpt->m_mutex); 9672 not_done += mptsas_watch_reset_delay_subr(mpt); 9673 mutex_exit(&mpt->m_mutex); 9674 } 9675 rw_exit(&mptsas_global_rwlock); 9676 9677 if (not_done) { 9678 mptsas_start_watch_reset_delay(); 9679 } 9680 } 9681 9682 static int 9683 mptsas_watch_reset_delay_subr(mptsas_t *mpt) 9684 { 9685 int done = 0; 9686 int restart = 0; 9687 mptsas_target_t *ptgt = NULL; 9688 9689 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt)); 9690 9691 ASSERT(mutex_owned(&mpt->m_mutex)); 9692 9693 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9694 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9695 if (ptgt->m_reset_delay != 0) { 9696 ptgt->m_reset_delay -= 9697 MPTSAS_WATCH_RESET_DELAY_TICK; 9698 if (ptgt->m_reset_delay <= 0) { 9699 ptgt->m_reset_delay = 0; 9700 mptsas_set_throttle(mpt, ptgt, 9701 MAX_THROTTLE); 9702 restart++; 9703 } else { 9704 done = -1; 9705 } 9706 } 9707 } 9708 9709 if (restart > 0) { 9710 mptsas_restart_hba(mpt); 9711 } 9712 return (done); 9713 } 9714 9715 #ifdef MPTSAS_TEST 9716 static void 9717 mptsas_test_reset(mptsas_t *mpt, int target) 9718 { 9719 mptsas_target_t *ptgt = NULL; 9720 9721 if (mptsas_rtest == target) { 9722 if (mptsas_do_scsi_reset(mpt, target) == TRUE) { 9723 mptsas_rtest = -1; 9724 } 9725 if (mptsas_rtest == -1) { 9726 NDBG22(("mptsas_test_reset success")); 9727 } 9728 } 9729 } 9730 #endif 9731 9732 /* 9733 * abort handling: 9734 * 9735 * Notes: 9736 * - if pkt is not NULL, abort just that command 9737 * - if pkt is NULL, abort all outstanding commands for target 9738 */ 9739 static int 9740 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 9741 { 9742 mptsas_t *mpt = ADDR2MPT(ap); 9743 int rval; 9744 mptsas_tgt_private_t *tgt_private; 9745 int target, lun; 9746 9747 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 9748 tran_tgt_private; 9749 ASSERT(tgt_private != NULL); 9750 target = tgt_private->t_private->m_devhdl; 9751 lun = tgt_private->t_lun; 9752 9753 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun)); 9754 9755 mutex_enter(&mpt->m_mutex); 9756 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt); 9757 mutex_exit(&mpt->m_mutex); 9758 return (rval); 9759 } 9760 9761 static int 9762 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt) 9763 { 9764 mptsas_cmd_t *sp = NULL; 9765 mptsas_slots_t *slots = mpt->m_active; 9766 int rval = FALSE; 9767 9768 ASSERT(mutex_owned(&mpt->m_mutex)); 9769 9770 /* 9771 * Abort the command pkt on the target/lun in ap. If pkt is 9772 * NULL, abort all outstanding commands on that target/lun. 9773 * If you can abort them, return 1, else return 0. 9774 * Each packet that's aborted should be sent back to the target 9775 * driver through the callback routine, with pkt_reason set to 9776 * CMD_ABORTED. 9777 * 9778 * abort cmd pkt on HBA hardware; clean out of outstanding 9779 * command lists, etc. 9780 */ 9781 if (pkt != NULL) { 9782 /* abort the specified packet */ 9783 sp = PKT2CMD(pkt); 9784 9785 if (sp->cmd_queued) { 9786 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted", 9787 (void *)sp)); 9788 mptsas_waitq_delete(mpt, sp); 9789 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED, 9790 STAT_ABORTED); 9791 mptsas_doneq_add(mpt, sp); 9792 rval = TRUE; 9793 goto done; 9794 } 9795 9796 /* 9797 * Have mpt firmware abort this command 9798 */ 9799 9800 if (slots->m_slot[sp->cmd_slot] != NULL) { 9801 rval = mptsas_ioc_task_management(mpt, 9802 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target, 9803 lun, NULL, 0, 0); 9804 9805 /* 9806 * The transport layer expects only TRUE and FALSE. 9807 * Therefore, if mptsas_ioc_task_management returns 9808 * FAILED we will return FALSE. 9809 */ 9810 if (rval == FAILED) 9811 rval = FALSE; 9812 goto done; 9813 } 9814 } 9815 9816 /* 9817 * If pkt is NULL then abort task set 9818 */ 9819 rval = mptsas_ioc_task_management(mpt, 9820 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0); 9821 9822 /* 9823 * The transport layer expects only TRUE and FALSE. 9824 * Therefore, if mptsas_ioc_task_management returns 9825 * FAILED we will return FALSE. 9826 */ 9827 if (rval == FAILED) 9828 rval = FALSE; 9829 9830 #ifdef MPTSAS_TEST 9831 if (rval && mptsas_test_stop) { 9832 debug_enter("mptsas_do_scsi_abort"); 9833 } 9834 #endif 9835 9836 done: 9837 mptsas_doneq_empty(mpt); 9838 return (rval); 9839 } 9840 9841 /* 9842 * capability handling: 9843 * (*tran_getcap). Get the capability named, and return its value. 9844 */ 9845 static int 9846 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly) 9847 { 9848 mptsas_t *mpt = ADDR2MPT(ap); 9849 int ckey; 9850 int rval = FALSE; 9851 9852 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x", 9853 ap->a_target, cap, tgtonly)); 9854 9855 mutex_enter(&mpt->m_mutex); 9856 9857 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9858 mutex_exit(&mpt->m_mutex); 9859 return (UNDEFINED); 9860 } 9861 9862 switch (ckey) { 9863 case SCSI_CAP_DMA_MAX: 9864 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer; 9865 break; 9866 case SCSI_CAP_ARQ: 9867 rval = TRUE; 9868 break; 9869 case SCSI_CAP_MSG_OUT: 9870 case SCSI_CAP_PARITY: 9871 case SCSI_CAP_UNTAGGED_QING: 9872 rval = TRUE; 9873 break; 9874 case SCSI_CAP_TAGGED_QING: 9875 rval = TRUE; 9876 break; 9877 case SCSI_CAP_RESET_NOTIFICATION: 9878 rval = TRUE; 9879 break; 9880 case SCSI_CAP_LINKED_CMDS: 9881 rval = FALSE; 9882 break; 9883 case SCSI_CAP_QFULL_RETRIES: 9884 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran-> 9885 tran_tgt_private))->t_private->m_qfull_retries; 9886 break; 9887 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9888 rval = drv_hztousec(((mptsas_tgt_private_t *) 9889 (ap->a_hba_tran->tran_tgt_private))-> 9890 t_private->m_qfull_retry_interval) / 1000; 9891 break; 9892 case SCSI_CAP_CDB_LEN: 9893 rval = CDB_GROUP4; 9894 break; 9895 case SCSI_CAP_INTERCONNECT_TYPE: 9896 rval = INTERCONNECT_SAS; 9897 break; 9898 case SCSI_CAP_TRAN_LAYER_RETRIES: 9899 if (mpt->m_ioc_capabilities & 9900 MPI2_IOCFACTS_CAPABILITY_TLR) 9901 rval = TRUE; 9902 else 9903 rval = FALSE; 9904 break; 9905 default: 9906 rval = UNDEFINED; 9907 break; 9908 } 9909 9910 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval)); 9911 9912 mutex_exit(&mpt->m_mutex); 9913 return (rval); 9914 } 9915 9916 /* 9917 * (*tran_setcap). Set the capability named to the value given. 9918 */ 9919 static int 9920 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly) 9921 { 9922 mptsas_t *mpt = ADDR2MPT(ap); 9923 int ckey; 9924 int rval = FALSE; 9925 9926 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x", 9927 ap->a_target, cap, value, tgtonly)); 9928 9929 if (!tgtonly) { 9930 return (rval); 9931 } 9932 9933 mutex_enter(&mpt->m_mutex); 9934 9935 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9936 mutex_exit(&mpt->m_mutex); 9937 return (UNDEFINED); 9938 } 9939 9940 switch (ckey) { 9941 case SCSI_CAP_DMA_MAX: 9942 case SCSI_CAP_MSG_OUT: 9943 case SCSI_CAP_PARITY: 9944 case SCSI_CAP_INITIATOR_ID: 9945 case SCSI_CAP_LINKED_CMDS: 9946 case SCSI_CAP_UNTAGGED_QING: 9947 case SCSI_CAP_RESET_NOTIFICATION: 9948 /* 9949 * None of these are settable via 9950 * the capability interface. 9951 */ 9952 break; 9953 case SCSI_CAP_ARQ: 9954 /* 9955 * We cannot turn off arq so return false if asked to 9956 */ 9957 if (value) { 9958 rval = TRUE; 9959 } else { 9960 rval = FALSE; 9961 } 9962 break; 9963 case SCSI_CAP_TAGGED_QING: 9964 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *) 9965 (ap->a_hba_tran->tran_tgt_private))->t_private, 9966 MAX_THROTTLE); 9967 rval = TRUE; 9968 break; 9969 case SCSI_CAP_QFULL_RETRIES: 9970 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9971 t_private->m_qfull_retries = (uchar_t)value; 9972 rval = TRUE; 9973 break; 9974 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9975 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9976 t_private->m_qfull_retry_interval = 9977 drv_usectohz(value * 1000); 9978 rval = TRUE; 9979 break; 9980 default: 9981 rval = UNDEFINED; 9982 break; 9983 } 9984 mutex_exit(&mpt->m_mutex); 9985 return (rval); 9986 } 9987 9988 /* 9989 * Utility routine for mptsas_ifsetcap/ifgetcap 9990 */ 9991 /*ARGSUSED*/ 9992 static int 9993 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp) 9994 { 9995 NDBG24(("mptsas_scsi_capchk: cap=%s", cap)); 9996 9997 if (!cap) 9998 return (FALSE); 9999 10000 *cidxp = scsi_hba_lookup_capstr(cap); 10001 return (TRUE); 10002 } 10003 10004 static int 10005 mptsas_alloc_active_slots(mptsas_t *mpt, int flag) 10006 { 10007 mptsas_slots_t *old_active = mpt->m_active; 10008 mptsas_slots_t *new_active; 10009 size_t size; 10010 10011 /* 10012 * if there are active commands, then we cannot 10013 * change size of active slots array. 10014 */ 10015 ASSERT(mpt->m_ncmds == 0); 10016 10017 size = MPTSAS_SLOTS_SIZE(mpt); 10018 new_active = kmem_zalloc(size, flag); 10019 if (new_active == NULL) { 10020 NDBG1(("new active alloc failed")); 10021 return (-1); 10022 } 10023 /* 10024 * Since SMID 0 is reserved and the TM slot is reserved, the 10025 * number of slots that can be used at any one time is 10026 * m_max_requests - 2. 10027 */ 10028 new_active->m_n_normal = (mpt->m_max_requests - 2); 10029 new_active->m_size = size; 10030 new_active->m_rotor = 1; 10031 if (old_active) 10032 mptsas_free_active_slots(mpt); 10033 mpt->m_active = new_active; 10034 10035 return (0); 10036 } 10037 10038 static void 10039 mptsas_free_active_slots(mptsas_t *mpt) 10040 { 10041 mptsas_slots_t *active = mpt->m_active; 10042 size_t size; 10043 10044 if (active == NULL) 10045 return; 10046 size = active->m_size; 10047 kmem_free(active, size); 10048 mpt->m_active = NULL; 10049 } 10050 10051 /* 10052 * Error logging, printing, and debug print routines. 10053 */ 10054 static char *mptsas_label = "mpt_sas"; 10055 10056 /*PRINTFLIKE3*/ 10057 void 10058 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...) 10059 { 10060 dev_info_t *dev; 10061 va_list ap; 10062 10063 if (mpt) { 10064 dev = mpt->m_dip; 10065 } else { 10066 dev = 0; 10067 } 10068 10069 mutex_enter(&mptsas_log_mutex); 10070 10071 va_start(ap, fmt); 10072 (void) vsprintf(mptsas_log_buf, fmt, ap); 10073 va_end(ap); 10074 10075 if (level == CE_CONT) { 10076 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf); 10077 } else { 10078 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf); 10079 } 10080 10081 mutex_exit(&mptsas_log_mutex); 10082 } 10083 10084 #ifdef MPTSAS_DEBUG 10085 /* 10086 * Use a circular buffer to log messages to private memory. 10087 * Increment idx atomically to minimize risk to miss lines. 10088 * It's fast and does not hold up the proceedings too much. 10089 */ 10090 static const size_t mptsas_dbglog_linecnt = MPTSAS_DBGLOG_LINECNT; 10091 static const size_t mptsas_dbglog_linelen = MPTSAS_DBGLOG_LINELEN; 10092 static char mptsas_dbglog_bufs[MPTSAS_DBGLOG_LINECNT][MPTSAS_DBGLOG_LINELEN]; 10093 static uint32_t mptsas_dbglog_idx = 0; 10094 10095 /*PRINTFLIKE1*/ 10096 void 10097 mptsas_debug_log(char *fmt, ...) 10098 { 10099 va_list ap; 10100 uint32_t idx; 10101 10102 idx = atomic_inc_32_nv(&mptsas_dbglog_idx) & 10103 (mptsas_dbglog_linecnt - 1); 10104 10105 va_start(ap, fmt); 10106 (void) vsnprintf(mptsas_dbglog_bufs[idx], 10107 mptsas_dbglog_linelen, fmt, ap); 10108 va_end(ap); 10109 } 10110 10111 /*PRINTFLIKE1*/ 10112 void 10113 mptsas_printf(char *fmt, ...) 10114 { 10115 dev_info_t *dev = 0; 10116 va_list ap; 10117 10118 mutex_enter(&mptsas_log_mutex); 10119 10120 va_start(ap, fmt); 10121 (void) vsprintf(mptsas_log_buf, fmt, ap); 10122 va_end(ap); 10123 10124 #ifdef PROM_PRINTF 10125 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf); 10126 #else 10127 scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf); 10128 #endif 10129 mutex_exit(&mptsas_log_mutex); 10130 } 10131 #endif 10132 10133 /* 10134 * timeout handling 10135 */ 10136 static void 10137 mptsas_watch(void *arg) 10138 { 10139 #ifndef __lock_lint 10140 _NOTE(ARGUNUSED(arg)) 10141 #endif 10142 10143 mptsas_t *mpt; 10144 uint32_t doorbell; 10145 10146 NDBG30(("mptsas_watch")); 10147 10148 rw_enter(&mptsas_global_rwlock, RW_READER); 10149 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) { 10150 10151 mutex_enter(&mpt->m_mutex); 10152 10153 /* Skip device if not powered on */ 10154 if (mpt->m_options & MPTSAS_OPT_PM) { 10155 if (mpt->m_power_level == PM_LEVEL_D0) { 10156 (void) pm_busy_component(mpt->m_dip, 0); 10157 mpt->m_busy = 1; 10158 } else { 10159 mutex_exit(&mpt->m_mutex); 10160 continue; 10161 } 10162 } 10163 10164 /* 10165 * Check if controller is in a FAULT state. If so, reset it. 10166 */ 10167 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell); 10168 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 10169 doorbell &= MPI2_DOORBELL_DATA_MASK; 10170 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, " 10171 "code: %04x", doorbell); 10172 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 10173 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 10174 mptsas_log(mpt, CE_WARN, "Reset failed" 10175 "after fault was detected"); 10176 } 10177 } 10178 10179 /* 10180 * For now, always call mptsas_watchsubr. 10181 */ 10182 mptsas_watchsubr(mpt); 10183 10184 if (mpt->m_options & MPTSAS_OPT_PM) { 10185 mpt->m_busy = 0; 10186 (void) pm_idle_component(mpt->m_dip, 0); 10187 } 10188 10189 mutex_exit(&mpt->m_mutex); 10190 } 10191 rw_exit(&mptsas_global_rwlock); 10192 10193 mutex_enter(&mptsas_global_mutex); 10194 if (mptsas_timeouts_enabled) 10195 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 10196 mutex_exit(&mptsas_global_mutex); 10197 } 10198 10199 static void 10200 mptsas_watchsubr_tgt(mptsas_t *mpt, mptsas_target_t *ptgt, hrtime_t timestamp) 10201 { 10202 mptsas_cmd_t *cmd; 10203 10204 /* 10205 * If we were draining due to a qfull condition, 10206 * go back to full throttle. 10207 */ 10208 if ((ptgt->m_t_throttle < MAX_THROTTLE) && 10209 (ptgt->m_t_throttle > HOLD_THROTTLE) && 10210 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) { 10211 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10212 mptsas_restart_hba(mpt); 10213 } 10214 10215 cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq); 10216 if (cmd == NULL) 10217 return; 10218 10219 if (cmd->cmd_active_expiration <= timestamp) { 10220 /* 10221 * Earliest command timeout expired. Drain throttle. 10222 */ 10223 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 10224 10225 /* 10226 * Check for remaining commands. 10227 */ 10228 cmd = TAILQ_FIRST(&ptgt->m_active_cmdq); 10229 if (cmd->cmd_active_expiration > timestamp) { 10230 /* 10231 * Wait for remaining commands to complete or 10232 * time out. 10233 */ 10234 NDBG23(("command timed out, pending drain")); 10235 return; 10236 } 10237 10238 /* 10239 * All command timeouts expired. 10240 */ 10241 mptsas_log(mpt, CE_NOTE, "Timeout of %d seconds " 10242 "expired with %d commands on target %d lun %d.", 10243 cmd->cmd_pkt->pkt_time, ptgt->m_t_ncmds, 10244 ptgt->m_devhdl, Lun(cmd)); 10245 10246 mptsas_cmd_timeout(mpt, ptgt); 10247 } else if (cmd->cmd_active_expiration <= 10248 timestamp + (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) { 10249 NDBG23(("pending timeout")); 10250 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 10251 } 10252 } 10253 10254 static void 10255 mptsas_watchsubr(mptsas_t *mpt) 10256 { 10257 int i; 10258 mptsas_cmd_t *cmd; 10259 mptsas_target_t *ptgt = NULL; 10260 hrtime_t timestamp = gethrtime(); 10261 10262 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 10263 10264 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt)); 10265 10266 #ifdef MPTSAS_TEST 10267 if (mptsas_enable_untagged) { 10268 mptsas_test_untagged++; 10269 } 10270 #endif 10271 10272 /* 10273 * Check for commands stuck in active slot 10274 * Account for TM requests, which use the last SMID. 10275 */ 10276 for (i = 0; i <= mpt->m_active->m_n_normal; i++) { 10277 if ((cmd = mpt->m_active->m_slot[i]) != NULL) { 10278 if (cmd->cmd_active_expiration <= timestamp) { 10279 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 10280 /* 10281 * There seems to be a command stuck 10282 * in the active slot. Drain throttle. 10283 */ 10284 mptsas_set_throttle(mpt, 10285 cmd->cmd_tgt_addr, 10286 DRAIN_THROTTLE); 10287 } else if (cmd->cmd_flags & 10288 (CFLAG_PASSTHRU | CFLAG_CONFIG | 10289 CFLAG_FW_DIAG)) { 10290 /* 10291 * passthrough command timeout 10292 */ 10293 cmd->cmd_flags |= (CFLAG_FINISHED | 10294 CFLAG_TIMEOUT); 10295 cv_broadcast(&mpt->m_passthru_cv); 10296 cv_broadcast(&mpt->m_config_cv); 10297 cv_broadcast(&mpt->m_fw_diag_cv); 10298 } 10299 } 10300 } 10301 } 10302 10303 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10304 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10305 mptsas_watchsubr_tgt(mpt, ptgt, timestamp); 10306 } 10307 10308 for (ptgt = refhash_first(mpt->m_tmp_targets); ptgt != NULL; 10309 ptgt = refhash_next(mpt->m_tmp_targets, ptgt)) { 10310 mptsas_watchsubr_tgt(mpt, ptgt, timestamp); 10311 } 10312 } 10313 10314 /* 10315 * timeout recovery 10316 */ 10317 static void 10318 mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt) 10319 { 10320 uint16_t devhdl; 10321 uint64_t sas_wwn; 10322 uint8_t phy; 10323 char wwn_str[MPTSAS_WWN_STRLEN]; 10324 10325 devhdl = ptgt->m_devhdl; 10326 sas_wwn = ptgt->m_addr.mta_wwn; 10327 phy = ptgt->m_phynum; 10328 if (sas_wwn == 0) { 10329 (void) sprintf(wwn_str, "p%x", phy); 10330 } else { 10331 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 10332 } 10333 10334 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl)); 10335 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for " 10336 "target %d %s, enclosure %u", devhdl, wwn_str, 10337 ptgt->m_enclosure); 10338 10339 /* 10340 * Abort all outstanding commands on the device. 10341 */ 10342 NDBG29(("mptsas_cmd_timeout: device reset")); 10343 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) { 10344 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout " 10345 "recovery failed!", devhdl); 10346 } 10347 } 10348 10349 /* 10350 * Device / Hotplug control 10351 */ 10352 static int 10353 mptsas_scsi_quiesce(dev_info_t *dip) 10354 { 10355 mptsas_t *mpt; 10356 scsi_hba_tran_t *tran; 10357 10358 tran = ddi_get_driver_private(dip); 10359 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10360 return (-1); 10361 10362 return (mptsas_quiesce_bus(mpt)); 10363 } 10364 10365 static int 10366 mptsas_scsi_unquiesce(dev_info_t *dip) 10367 { 10368 mptsas_t *mpt; 10369 scsi_hba_tran_t *tran; 10370 10371 tran = ddi_get_driver_private(dip); 10372 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10373 return (-1); 10374 10375 return (mptsas_unquiesce_bus(mpt)); 10376 } 10377 10378 static int 10379 mptsas_quiesce_bus(mptsas_t *mpt) 10380 { 10381 mptsas_target_t *ptgt = NULL; 10382 10383 NDBG28(("mptsas_quiesce_bus")); 10384 mutex_enter(&mpt->m_mutex); 10385 10386 /* Set all the throttles to zero */ 10387 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10388 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10389 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10390 } 10391 10392 /* If there are any outstanding commands in the queue */ 10393 if (mpt->m_ncmds) { 10394 mpt->m_softstate |= MPTSAS_SS_DRAINING; 10395 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10396 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000))); 10397 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) { 10398 /* 10399 * Quiesce has been interrupted 10400 */ 10401 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10402 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10403 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10404 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10405 } 10406 mptsas_restart_hba(mpt); 10407 if (mpt->m_quiesce_timeid != 0) { 10408 timeout_id_t tid = mpt->m_quiesce_timeid; 10409 mpt->m_quiesce_timeid = 0; 10410 mutex_exit(&mpt->m_mutex); 10411 (void) untimeout(tid); 10412 return (-1); 10413 } 10414 mutex_exit(&mpt->m_mutex); 10415 return (-1); 10416 } else { 10417 /* Bus has been quiesced */ 10418 ASSERT(mpt->m_quiesce_timeid == 0); 10419 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10420 mpt->m_softstate |= MPTSAS_SS_QUIESCED; 10421 mutex_exit(&mpt->m_mutex); 10422 return (0); 10423 } 10424 } 10425 /* Bus was not busy - QUIESCED */ 10426 mutex_exit(&mpt->m_mutex); 10427 10428 return (0); 10429 } 10430 10431 static int 10432 mptsas_unquiesce_bus(mptsas_t *mpt) 10433 { 10434 mptsas_target_t *ptgt = NULL; 10435 10436 NDBG28(("mptsas_unquiesce_bus")); 10437 mutex_enter(&mpt->m_mutex); 10438 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED; 10439 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10440 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10441 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10442 } 10443 mptsas_restart_hba(mpt); 10444 mutex_exit(&mpt->m_mutex); 10445 return (0); 10446 } 10447 10448 static void 10449 mptsas_ncmds_checkdrain(void *arg) 10450 { 10451 mptsas_t *mpt = arg; 10452 mptsas_target_t *ptgt = NULL; 10453 10454 mutex_enter(&mpt->m_mutex); 10455 if (mpt->m_softstate & MPTSAS_SS_DRAINING) { 10456 mpt->m_quiesce_timeid = 0; 10457 if (mpt->m_ncmds == 0) { 10458 /* Command queue has been drained */ 10459 cv_signal(&mpt->m_cv); 10460 } else { 10461 /* 10462 * The throttle may have been reset because 10463 * of a SCSI bus reset 10464 */ 10465 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10466 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10467 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10468 } 10469 10470 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10471 mpt, (MPTSAS_QUIESCE_TIMEOUT * 10472 drv_usectohz(1000000))); 10473 } 10474 } 10475 mutex_exit(&mpt->m_mutex); 10476 } 10477 10478 /*ARGSUSED*/ 10479 static void 10480 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 10481 { 10482 int i; 10483 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp; 10484 char buf[128]; 10485 10486 buf[0] = '\0'; 10487 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd, 10488 Tgt(cmd), Lun(cmd))); 10489 (void) sprintf(&buf[0], "\tcdb=["); 10490 for (i = 0; i < (int)cmd->cmd_cdblen; i++) { 10491 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++); 10492 } 10493 (void) sprintf(&buf[strlen(buf)], " ]"); 10494 NDBG25(("?%s\n", buf)); 10495 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n", 10496 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics, 10497 cmd->cmd_pkt->pkt_state)); 10498 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ? 10499 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags)); 10500 } 10501 10502 static void 10503 mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt, 10504 pMpi2SGESimple64_t sgep) 10505 { 10506 uint32_t sge_flags; 10507 uint32_t data_size, dataout_size; 10508 ddi_dma_cookie_t data_cookie; 10509 ddi_dma_cookie_t dataout_cookie; 10510 10511 data_size = pt->data_size; 10512 dataout_size = pt->dataout_size; 10513 data_cookie = pt->data_cookie; 10514 dataout_cookie = pt->dataout_cookie; 10515 10516 if (dataout_size) { 10517 sge_flags = dataout_size | 10518 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10519 MPI2_SGE_FLAGS_END_OF_BUFFER | 10520 MPI2_SGE_FLAGS_HOST_TO_IOC | 10521 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10522 MPI2_SGE_FLAGS_SHIFT); 10523 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags); 10524 ddi_put32(acc_hdl, &sgep->Address.Low, 10525 (uint32_t)(dataout_cookie.dmac_laddress & 10526 0xffffffffull)); 10527 ddi_put32(acc_hdl, &sgep->Address.High, 10528 (uint32_t)(dataout_cookie.dmac_laddress 10529 >> 32)); 10530 sgep++; 10531 } 10532 sge_flags = data_size; 10533 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10534 MPI2_SGE_FLAGS_LAST_ELEMENT | 10535 MPI2_SGE_FLAGS_END_OF_BUFFER | 10536 MPI2_SGE_FLAGS_END_OF_LIST | 10537 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10538 MPI2_SGE_FLAGS_SHIFT); 10539 if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 10540 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 10541 MPI2_SGE_FLAGS_SHIFT); 10542 } else { 10543 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 10544 MPI2_SGE_FLAGS_SHIFT); 10545 } 10546 ddi_put32(acc_hdl, &sgep->FlagsLength, 10547 sge_flags); 10548 ddi_put32(acc_hdl, &sgep->Address.Low, 10549 (uint32_t)(data_cookie.dmac_laddress & 10550 0xffffffffull)); 10551 ddi_put32(acc_hdl, &sgep->Address.High, 10552 (uint32_t)(data_cookie.dmac_laddress >> 32)); 10553 } 10554 10555 static void 10556 mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt, 10557 pMpi2IeeeSgeSimple64_t ieeesgep) 10558 { 10559 uint8_t sge_flags; 10560 uint32_t data_size, dataout_size; 10561 ddi_dma_cookie_t data_cookie; 10562 ddi_dma_cookie_t dataout_cookie; 10563 10564 data_size = pt->data_size; 10565 dataout_size = pt->dataout_size; 10566 data_cookie = pt->data_cookie; 10567 dataout_cookie = pt->dataout_cookie; 10568 10569 sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 10570 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 10571 if (dataout_size) { 10572 ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size); 10573 ddi_put32(acc_hdl, &ieeesgep->Address.Low, 10574 (uint32_t)(dataout_cookie.dmac_laddress & 10575 0xffffffffull)); 10576 ddi_put32(acc_hdl, &ieeesgep->Address.High, 10577 (uint32_t)(dataout_cookie.dmac_laddress >> 32)); 10578 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags); 10579 ieeesgep++; 10580 } 10581 sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 10582 ddi_put32(acc_hdl, &ieeesgep->Length, data_size); 10583 ddi_put32(acc_hdl, &ieeesgep->Address.Low, 10584 (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull)); 10585 ddi_put32(acc_hdl, &ieeesgep->Address.High, 10586 (uint32_t)(data_cookie.dmac_laddress >> 32)); 10587 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags); 10588 } 10589 10590 static void 10591 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd) 10592 { 10593 caddr_t memp; 10594 pMPI2RequestHeader_t request_hdrp; 10595 struct scsi_pkt *pkt = cmd->cmd_pkt; 10596 mptsas_pt_request_t *pt = pkt->pkt_ha_private; 10597 uint32_t request_size; 10598 uint32_t i; 10599 uint64_t request_desc = 0; 10600 uint8_t desc_type; 10601 uint16_t SMID; 10602 uint8_t *request, function; 10603 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 10604 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 10605 10606 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 10607 10608 request = pt->request; 10609 request_size = pt->request_size; 10610 10611 SMID = cmd->cmd_slot; 10612 10613 /* 10614 * Store the passthrough message in memory location 10615 * corresponding to our slot number 10616 */ 10617 memp = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 10618 request_hdrp = (pMPI2RequestHeader_t)memp; 10619 bzero(memp, mpt->m_req_frame_size); 10620 10621 for (i = 0; i < request_size; i++) { 10622 bcopy(request + i, memp + i, 1); 10623 } 10624 10625 NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, " 10626 "size=%d, in %d, out %d, SMID %d", request_hdrp->Function, 10627 request_hdrp->MsgFlags, request_size, 10628 pt->data_size, pt->dataout_size, SMID)); 10629 10630 /* 10631 * Add an SGE, even if the length is zero. 10632 */ 10633 if (mpt->m_MPI25 && pt->simple == 0) { 10634 mptsas_passthru_ieee_sge(acc_hdl, pt, 10635 (pMpi2IeeeSgeSimple64_t) 10636 ((uint8_t *)request_hdrp + pt->sgl_offset)); 10637 } else { 10638 mptsas_passthru_sge(acc_hdl, pt, 10639 (pMpi2SGESimple64_t) 10640 ((uint8_t *)request_hdrp + pt->sgl_offset)); 10641 } 10642 10643 function = request_hdrp->Function; 10644 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 10645 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 10646 pMpi2SCSIIORequest_t scsi_io_req; 10647 caddr_t arsbuf; 10648 uint8_t ars_size; 10649 uint32_t ars_dmaaddrlow; 10650 10651 NDBG15(("mptsas_start_passthru: Is SCSI IO Req")); 10652 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp; 10653 10654 if (cmd->cmd_extrqslen != 0) { 10655 /* 10656 * Mapping of the buffer was done in 10657 * mptsas_do_passthru(). 10658 * Calculate the DMA address with the same offset. 10659 */ 10660 arsbuf = cmd->cmd_arq_buf; 10661 ars_size = cmd->cmd_extrqslen; 10662 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 10663 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) & 10664 0xffffffffu; 10665 } else { 10666 arsbuf = mpt->m_req_sense + 10667 (mpt->m_req_sense_size * (SMID-1)); 10668 cmd->cmd_arq_buf = arsbuf; 10669 ars_size = mpt->m_req_sense_size; 10670 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 10671 (mpt->m_req_sense_size * (SMID-1))) & 10672 0xffffffffu; 10673 } 10674 bzero(arsbuf, ars_size); 10675 10676 ddi_put8(acc_hdl, &scsi_io_req->SenseBufferLength, ars_size); 10677 ddi_put32(acc_hdl, &scsi_io_req->SenseBufferLowAddress, 10678 ars_dmaaddrlow); 10679 10680 /* 10681 * Put SGE for data and data_out buffer at the end of 10682 * scsi_io_request message header.(64 bytes in total) 10683 * Set SGLOffset0 value 10684 */ 10685 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0, 10686 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4); 10687 10688 /* 10689 * Setup descriptor info. RAID passthrough must use the 10690 * default request descriptor which is already set, so if this 10691 * is a SCSI IO request, change the descriptor to SCSI IO. 10692 */ 10693 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 10694 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 10695 request_desc = ((uint64_t)ddi_get16(acc_hdl, 10696 &scsi_io_req->DevHandle) << 48); 10697 } 10698 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 10699 DDI_DMA_SYNC_FORDEV); 10700 } 10701 10702 /* 10703 * We must wait till the message has been completed before 10704 * beginning the next message so we wait for this one to 10705 * finish. 10706 */ 10707 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 10708 request_desc |= (SMID << 16) + desc_type; 10709 cmd->cmd_rfm = 0; 10710 MPTSAS_START_CMD(mpt, request_desc); 10711 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 10712 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 10713 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 10714 } 10715 } 10716 10717 typedef void (mptsas_pre_f)(mptsas_t *, mptsas_pt_request_t *); 10718 static mptsas_pre_f mpi_pre_ioc_facts; 10719 static mptsas_pre_f mpi_pre_port_facts; 10720 static mptsas_pre_f mpi_pre_fw_download; 10721 static mptsas_pre_f mpi_pre_fw_25_download; 10722 static mptsas_pre_f mpi_pre_fw_upload; 10723 static mptsas_pre_f mpi_pre_fw_25_upload; 10724 static mptsas_pre_f mpi_pre_sata_passthrough; 10725 static mptsas_pre_f mpi_pre_smp_passthrough; 10726 static mptsas_pre_f mpi_pre_config; 10727 static mptsas_pre_f mpi_pre_sas_io_unit_control; 10728 static mptsas_pre_f mpi_pre_scsi_io_req; 10729 10730 /* 10731 * Prepare the pt for a SAS2 FW_DOWNLOAD request. 10732 */ 10733 static void 10734 mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt) 10735 { 10736 pMpi2FWDownloadTCSGE_t tcsge; 10737 pMpi2FWDownloadRequest req; 10738 10739 /* 10740 * If SAS3, call separate function. 10741 */ 10742 if (mpt->m_MPI25) { 10743 mpi_pre_fw_25_download(mpt, pt); 10744 return; 10745 } 10746 10747 /* 10748 * User requests should come in with the Transaction 10749 * context element where the SGL will go. Putting the 10750 * SGL after that seems to work, but don't really know 10751 * why. Other drivers tend to create an extra SGL and 10752 * refer to the TCE through that. 10753 */ 10754 req = (pMpi2FWDownloadRequest)pt->request; 10755 tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL; 10756 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10757 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10758 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!"); 10759 } 10760 10761 pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) + 10762 sizeof (*tcsge); 10763 if (pt->request_size != pt->sgl_offset) { 10764 NDBG15(("mpi_pre_fw_download(): Incorrect req size, " 10765 "0x%x, should be 0x%x, dataoutsz 0x%x", 10766 (int)pt->request_size, (int)pt->sgl_offset, 10767 (int)pt->dataout_size)); 10768 } 10769 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) { 10770 NDBG15(("mpi_pre_fw_download(): Incorrect rep size, " 10771 "0x%x, should be 0x%x", pt->data_size, 10772 (int)sizeof (MPI2_FW_DOWNLOAD_REPLY))); 10773 } 10774 } 10775 10776 /* 10777 * Prepare the pt for a SAS3 FW_DOWNLOAD request. 10778 */ 10779 static void 10780 mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt) 10781 { 10782 pMpi2FWDownloadTCSGE_t tcsge; 10783 pMpi2FWDownloadRequest req2; 10784 pMpi25FWDownloadRequest req25; 10785 10786 /* 10787 * User requests should come in with the Transaction 10788 * context element where the SGL will go. The new firmware 10789 * Doesn't use TCE and has space in the main request for 10790 * this information. So move to the right place. 10791 */ 10792 req2 = (pMpi2FWDownloadRequest)pt->request; 10793 req25 = (pMpi25FWDownloadRequest)pt->request; 10794 tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL; 10795 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10796 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10797 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!"); 10798 } 10799 req25->ImageOffset = tcsge->ImageOffset; 10800 req25->ImageSize = tcsge->ImageSize; 10801 10802 pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL); 10803 if (pt->request_size != pt->sgl_offset) { 10804 NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, " 10805 "0x%x, should be 0x%x, dataoutsz 0x%x", 10806 pt->request_size, pt->sgl_offset, 10807 pt->dataout_size)); 10808 } 10809 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) { 10810 NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, " 10811 "0x%x, should be 0x%x", pt->data_size, 10812 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10813 } 10814 } 10815 10816 /* 10817 * Prepare the pt for a SAS2 FW_UPLOAD request. 10818 */ 10819 static void 10820 mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) 10821 { 10822 pMpi2FWUploadTCSGE_t tcsge; 10823 pMpi2FWUploadRequest_t req; 10824 10825 /* 10826 * If SAS3, call separate function. 10827 */ 10828 if (mpt->m_MPI25) { 10829 mpi_pre_fw_25_upload(mpt, pt); 10830 return; 10831 } 10832 10833 /* 10834 * User requests should come in with the Transaction 10835 * context element where the SGL will go. Putting the 10836 * SGL after that seems to work, but don't really know 10837 * why. Other drivers tend to create an extra SGL and 10838 * refer to the TCE through that. 10839 */ 10840 req = (pMpi2FWUploadRequest_t)pt->request; 10841 tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL; 10842 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10843 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10844 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!"); 10845 } 10846 10847 pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) + 10848 sizeof (*tcsge); 10849 if (pt->request_size != pt->sgl_offset) { 10850 NDBG15(("mpi_pre_fw_upload(): Incorrect req size, " 10851 "0x%x, should be 0x%x, dataoutsz 0x%x", 10852 pt->request_size, pt->sgl_offset, 10853 pt->dataout_size)); 10854 } 10855 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) { 10856 NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, " 10857 "0x%x, should be 0x%x", pt->data_size, 10858 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10859 } 10860 } 10861 10862 /* 10863 * Prepare the pt a SAS3 FW_UPLOAD request. 10864 */ 10865 static void 10866 mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) 10867 { 10868 pMpi2FWUploadTCSGE_t tcsge; 10869 pMpi2FWUploadRequest_t req2; 10870 pMpi25FWUploadRequest_t req25; 10871 10872 /* 10873 * User requests should come in with the Transaction 10874 * context element where the SGL will go. The new firmware 10875 * Doesn't use TCE and has space in the main request for 10876 * this information. So move to the right place. 10877 */ 10878 req2 = (pMpi2FWUploadRequest_t)pt->request; 10879 req25 = (pMpi25FWUploadRequest_t)pt->request; 10880 tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL; 10881 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10882 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10883 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!"); 10884 } 10885 req25->ImageOffset = tcsge->ImageOffset; 10886 req25->ImageSize = tcsge->ImageSize; 10887 10888 pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL); 10889 if (pt->request_size != pt->sgl_offset) { 10890 NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, " 10891 "0x%x, should be 0x%x, dataoutsz 0x%x", 10892 pt->request_size, pt->sgl_offset, 10893 pt->dataout_size)); 10894 } 10895 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) { 10896 NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, " 10897 "0x%x, should be 0x%x", pt->data_size, 10898 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10899 } 10900 } 10901 10902 /* 10903 * Prepare the pt for an IOC_FACTS request. 10904 */ 10905 static void 10906 mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) 10907 { 10908 #ifndef __lock_lint 10909 _NOTE(ARGUNUSED(mpt)) 10910 #endif 10911 if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST)) { 10912 NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, " 10913 "0x%x, should be 0x%x, dataoutsz 0x%x", 10914 pt->request_size, 10915 (int)sizeof (MPI2_IOC_FACTS_REQUEST), 10916 pt->dataout_size)); 10917 } 10918 if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY)) { 10919 NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, " 10920 "0x%x, should be 0x%x", pt->data_size, 10921 (int)sizeof (MPI2_IOC_FACTS_REPLY))); 10922 } 10923 pt->sgl_offset = (uint16_t)pt->request_size; 10924 } 10925 10926 /* 10927 * Prepare the pt for a PORT_FACTS request. 10928 */ 10929 static void 10930 mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) 10931 { 10932 #ifndef __lock_lint 10933 _NOTE(ARGUNUSED(mpt)) 10934 #endif 10935 if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST)) { 10936 NDBG15(("mpi_pre_port_facts(): Incorrect req size, " 10937 "0x%x, should be 0x%x, dataoutsz 0x%x", 10938 pt->request_size, 10939 (int)sizeof (MPI2_PORT_FACTS_REQUEST), 10940 pt->dataout_size)); 10941 } 10942 if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY)) { 10943 NDBG15(("mpi_pre_port_facts(): Incorrect rep size, " 10944 "0x%x, should be 0x%x", pt->data_size, 10945 (int)sizeof (MPI2_PORT_FACTS_REPLY))); 10946 } 10947 pt->sgl_offset = (uint16_t)pt->request_size; 10948 } 10949 10950 /* 10951 * Prepare pt for a SATA_PASSTHROUGH request. 10952 */ 10953 static void 10954 mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) 10955 { 10956 #ifndef __lock_lint 10957 _NOTE(ARGUNUSED(mpt)) 10958 #endif 10959 pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL); 10960 if (pt->request_size != pt->sgl_offset) { 10961 NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, " 10962 "0x%x, should be 0x%x, dataoutsz 0x%x", 10963 pt->request_size, pt->sgl_offset, 10964 pt->dataout_size)); 10965 } 10966 if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY)) { 10967 NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, " 10968 "0x%x, should be 0x%x", pt->data_size, 10969 (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY))); 10970 } 10971 } 10972 10973 static void 10974 mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) 10975 { 10976 #ifndef __lock_lint 10977 _NOTE(ARGUNUSED(mpt)) 10978 #endif 10979 pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL); 10980 if (pt->request_size != pt->sgl_offset) { 10981 NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, " 10982 "0x%x, should be 0x%x, dataoutsz 0x%x", 10983 pt->request_size, pt->sgl_offset, 10984 pt->dataout_size)); 10985 } 10986 if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY)) { 10987 NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, " 10988 "0x%x, should be 0x%x", pt->data_size, 10989 (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY))); 10990 } 10991 } 10992 10993 /* 10994 * Prepare pt for a CONFIG request. 10995 */ 10996 static void 10997 mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt) 10998 { 10999 #ifndef __lock_lint 11000 _NOTE(ARGUNUSED(mpt)) 11001 #endif 11002 pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE); 11003 if (pt->request_size != pt->sgl_offset) { 11004 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " 11005 "should be 0x%x, dataoutsz 0x%x", pt->request_size, 11006 pt->sgl_offset, pt->dataout_size)); 11007 } 11008 if (pt->data_size != sizeof (MPI2_CONFIG_REPLY)) { 11009 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " 11010 "should be 0x%x", pt->data_size, 11011 (int)sizeof (MPI2_CONFIG_REPLY))); 11012 } 11013 pt->simple = 1; 11014 } 11015 11016 /* 11017 * Prepare pt for a SCSI_IO_REQ request. 11018 */ 11019 static void 11020 mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt) 11021 { 11022 #ifndef __lock_lint 11023 _NOTE(ARGUNUSED(mpt)) 11024 #endif 11025 pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL); 11026 if (pt->request_size != pt->sgl_offset) { 11027 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " 11028 "should be 0x%x, dataoutsz 0x%x", pt->request_size, 11029 pt->sgl_offset, 11030 pt->dataout_size)); 11031 } 11032 if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY)) { 11033 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " 11034 "should be 0x%x", pt->data_size, 11035 (int)sizeof (MPI2_SCSI_IO_REPLY))); 11036 } 11037 } 11038 11039 /* 11040 * Prepare the mptsas_cmd for a SAS_IO_UNIT_CONTROL request. 11041 */ 11042 static void 11043 mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt) 11044 { 11045 #ifndef __lock_lint 11046 _NOTE(ARGUNUSED(mpt)) 11047 #endif 11048 pt->sgl_offset = (uint16_t)pt->request_size; 11049 } 11050 11051 /* 11052 * A set of functions to prepare an mptsas_cmd for the various 11053 * supported requests. 11054 */ 11055 static struct mptsas_func { 11056 U8 Function; 11057 char *Name; 11058 mptsas_pre_f *f_pre; 11059 } mptsas_func_list[] = { 11060 { MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS", mpi_pre_ioc_facts }, 11061 { MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS", mpi_pre_port_facts }, 11062 { MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD", mpi_pre_fw_download }, 11063 { MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD", mpi_pre_fw_upload }, 11064 { MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH", 11065 mpi_pre_sata_passthrough }, 11066 { MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH", 11067 mpi_pre_smp_passthrough}, 11068 { MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST", 11069 mpi_pre_scsi_io_req}, 11070 { MPI2_FUNCTION_CONFIG, "CONFIG", mpi_pre_config}, 11071 { MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL", 11072 mpi_pre_sas_io_unit_control }, 11073 { 0xFF, NULL, NULL } /* list end */ 11074 }; 11075 11076 static void 11077 mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt) 11078 { 11079 pMPI2RequestHeader_t hdr; 11080 struct mptsas_func *f; 11081 11082 hdr = (pMPI2RequestHeader_t)pt->request; 11083 11084 for (f = mptsas_func_list; f->f_pre != NULL; f++) { 11085 if (hdr->Function == f->Function) { 11086 f->f_pre(mpt, pt); 11087 NDBG15(("mptsas_prep_sgl_offset: Function %s," 11088 " sgl_offset 0x%x", f->Name, 11089 pt->sgl_offset)); 11090 return; 11091 } 11092 } 11093 NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x," 11094 " returning req_size 0x%x for sgl_offset", 11095 hdr->Function, pt->request_size)); 11096 pt->sgl_offset = (uint16_t)pt->request_size; 11097 } 11098 11099 11100 static int 11101 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 11102 uint8_t *data, uint32_t request_size, uint32_t reply_size, 11103 uint32_t data_size, uint32_t direction, uint8_t *dataout, 11104 uint32_t dataout_size, short timeout, int mode) 11105 { 11106 mptsas_pt_request_t pt; 11107 mptsas_dma_alloc_state_t data_dma_state; 11108 mptsas_dma_alloc_state_t dataout_dma_state; 11109 caddr_t memp; 11110 mptsas_cmd_t *cmd = NULL; 11111 struct scsi_pkt *pkt; 11112 uint32_t reply_len = 0, sense_len = 0; 11113 pMPI2RequestHeader_t request_hdrp; 11114 pMPI2RequestHeader_t request_msg; 11115 pMPI2DefaultReply_t reply_msg; 11116 Mpi2SCSIIOReply_t rep_msg; 11117 int rvalue; 11118 int i, status = 0, pt_flags = 0, rv = 0; 11119 uint8_t function; 11120 11121 ASSERT(mutex_owned(&mpt->m_mutex)); 11122 11123 reply_msg = (pMPI2DefaultReply_t)(&rep_msg); 11124 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY)); 11125 request_msg = kmem_zalloc(request_size, KM_SLEEP); 11126 11127 mutex_exit(&mpt->m_mutex); 11128 /* 11129 * copy in the request buffer since it could be used by 11130 * another thread when the pt request into waitq 11131 */ 11132 if (ddi_copyin(request, request_msg, request_size, mode)) { 11133 mutex_enter(&mpt->m_mutex); 11134 status = EFAULT; 11135 mptsas_log(mpt, CE_WARN, "failed to copy request data"); 11136 goto out; 11137 } 11138 NDBG27(("mptsas_do_passthru: mode 0x%x, size 0x%x, Func 0x%x", 11139 mode, request_size, request_msg->Function)); 11140 mutex_enter(&mpt->m_mutex); 11141 11142 function = request_msg->Function; 11143 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) { 11144 pMpi2SCSITaskManagementRequest_t task; 11145 task = (pMpi2SCSITaskManagementRequest_t)request_msg; 11146 mptsas_setup_bus_reset_delay(mpt); 11147 rv = mptsas_ioc_task_management(mpt, task->TaskType, 11148 task->DevHandle, (int)task->LUN[1], reply, reply_size, 11149 mode); 11150 11151 if (rv != TRUE) { 11152 status = EIO; 11153 mptsas_log(mpt, CE_WARN, "task management failed"); 11154 } 11155 goto out; 11156 } 11157 11158 if (data_size != 0) { 11159 data_dma_state.size = data_size; 11160 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) { 11161 status = ENOMEM; 11162 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 11163 "resource"); 11164 goto out; 11165 } 11166 pt_flags |= MPTSAS_DATA_ALLOCATED; 11167 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 11168 mutex_exit(&mpt->m_mutex); 11169 for (i = 0; i < data_size; i++) { 11170 if (ddi_copyin(data + i, (uint8_t *) 11171 data_dma_state.memp + i, 1, mode)) { 11172 mutex_enter(&mpt->m_mutex); 11173 status = EFAULT; 11174 mptsas_log(mpt, CE_WARN, "failed to " 11175 "copy read data"); 11176 goto out; 11177 } 11178 } 11179 mutex_enter(&mpt->m_mutex); 11180 } 11181 } else { 11182 bzero(&data_dma_state, sizeof (data_dma_state)); 11183 } 11184 11185 if (dataout_size != 0) { 11186 dataout_dma_state.size = dataout_size; 11187 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) { 11188 status = ENOMEM; 11189 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 11190 "resource"); 11191 goto out; 11192 } 11193 pt_flags |= MPTSAS_DATAOUT_ALLOCATED; 11194 mutex_exit(&mpt->m_mutex); 11195 for (i = 0; i < dataout_size; i++) { 11196 if (ddi_copyin(dataout + i, (uint8_t *) 11197 dataout_dma_state.memp + i, 1, mode)) { 11198 mutex_enter(&mpt->m_mutex); 11199 mptsas_log(mpt, CE_WARN, "failed to copy out" 11200 " data"); 11201 status = EFAULT; 11202 goto out; 11203 } 11204 } 11205 mutex_enter(&mpt->m_mutex); 11206 } else { 11207 bzero(&dataout_dma_state, sizeof (dataout_dma_state)); 11208 } 11209 11210 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11211 status = EAGAIN; 11212 mptsas_log(mpt, CE_NOTE, "event ack command pool is full"); 11213 goto out; 11214 } 11215 pt_flags |= MPTSAS_REQUEST_POOL_CMD; 11216 11217 bzero((caddr_t)cmd, sizeof (*cmd)); 11218 bzero((caddr_t)pkt, scsi_pkt_size()); 11219 bzero((caddr_t)&pt, sizeof (pt)); 11220 11221 cmd->ioc_cmd_slot = (uint32_t)(rvalue); 11222 11223 pt.request = (uint8_t *)request_msg; 11224 pt.direction = direction; 11225 pt.simple = 0; 11226 pt.request_size = request_size; 11227 pt.data_size = data_size; 11228 pt.dataout_size = dataout_size; 11229 pt.data_cookie = data_dma_state.cookie; 11230 pt.dataout_cookie = dataout_dma_state.cookie; 11231 mptsas_prep_sgl_offset(mpt, &pt); 11232 11233 /* 11234 * Form a blank cmd/pkt to store the acknowledgement message 11235 */ 11236 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0]; 11237 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 11238 pkt->pkt_ha_private = (opaque_t)&pt; 11239 pkt->pkt_flags = FLAG_HEAD; 11240 pkt->pkt_time = timeout; 11241 cmd->cmd_pkt = pkt; 11242 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU; 11243 11244 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 11245 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 11246 uint8_t com, cdb_group_id; 11247 boolean_t ret; 11248 11249 pkt->pkt_cdbp = ((pMpi2SCSIIORequest_t)request_msg)->CDB.CDB32; 11250 com = pkt->pkt_cdbp[0]; 11251 cdb_group_id = CDB_GROUPID(com); 11252 switch (cdb_group_id) { 11253 case CDB_GROUPID_0: cmd->cmd_cdblen = CDB_GROUP0; break; 11254 case CDB_GROUPID_1: cmd->cmd_cdblen = CDB_GROUP1; break; 11255 case CDB_GROUPID_2: cmd->cmd_cdblen = CDB_GROUP2; break; 11256 case CDB_GROUPID_4: cmd->cmd_cdblen = CDB_GROUP4; break; 11257 case CDB_GROUPID_5: cmd->cmd_cdblen = CDB_GROUP5; break; 11258 default: 11259 NDBG27(("mptsas_do_passthru: SCSI_IO, reserved " 11260 "CDBGROUP 0x%x requested!", cdb_group_id)); 11261 break; 11262 } 11263 11264 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 11265 sense_len = reply_size - reply_len; 11266 ret = mptsas_cmdarqsize(mpt, cmd, sense_len, KM_SLEEP); 11267 VERIFY(ret == B_TRUE); 11268 } else { 11269 reply_len = reply_size; 11270 sense_len = 0; 11271 } 11272 11273 NDBG27(("mptsas_do_passthru: %s, dsz 0x%x, dosz 0x%x, replen 0x%x, " 11274 "snslen 0x%x", 11275 (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE)?"Write":"Read", 11276 data_size, dataout_size, reply_len, sense_len)); 11277 11278 /* 11279 * Save the command in a slot 11280 */ 11281 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11282 /* 11283 * Once passthru command get slot, set cmd_flags 11284 * CFLAG_PREPARED. 11285 */ 11286 cmd->cmd_flags |= CFLAG_PREPARED; 11287 mptsas_start_passthru(mpt, cmd); 11288 } else { 11289 mptsas_waitq_add(mpt, cmd); 11290 } 11291 11292 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11293 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex); 11294 } 11295 11296 NDBG27(("mptsas_do_passthru: Cmd complete, flags 0x%x, rfm 0x%x " 11297 "pktreason 0x%x", cmd->cmd_flags, cmd->cmd_rfm, 11298 pkt->pkt_reason)); 11299 11300 if (cmd->cmd_flags & CFLAG_PREPARED) { 11301 memp = mpt->m_req_frame + (mpt->m_req_frame_size * 11302 cmd->cmd_slot); 11303 request_hdrp = (pMPI2RequestHeader_t)memp; 11304 } 11305 11306 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11307 status = ETIMEDOUT; 11308 mptsas_log(mpt, CE_WARN, "passthrough command timeout"); 11309 pt_flags |= MPTSAS_CMD_TIMEOUT; 11310 goto out; 11311 } 11312 11313 if (cmd->cmd_rfm) { 11314 /* 11315 * cmd_rfm is zero means the command reply is a CONTEXT 11316 * reply and no PCI Write to post the free reply SMFA 11317 * because no reply message frame is used. 11318 * cmd_rfm is non-zero means the reply is a ADDRESS 11319 * reply and reply message frame is used. 11320 */ 11321 pt_flags |= MPTSAS_ADDRESS_REPLY; 11322 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11323 DDI_DMA_SYNC_FORCPU); 11324 reply_msg = (pMPI2DefaultReply_t) 11325 (mpt->m_reply_frame + (cmd->cmd_rfm - 11326 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11327 } 11328 11329 mptsas_fma_check(mpt, cmd); 11330 if (pkt->pkt_reason == CMD_TRAN_ERR) { 11331 status = EAGAIN; 11332 mptsas_log(mpt, CE_WARN, "passthru fma error"); 11333 goto out; 11334 } 11335 if (pkt->pkt_reason == CMD_RESET) { 11336 status = EAGAIN; 11337 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru"); 11338 goto out; 11339 } 11340 11341 if (pkt->pkt_reason == CMD_INCOMPLETE) { 11342 status = EIO; 11343 mptsas_log(mpt, CE_WARN, "passthrough command incomplete"); 11344 goto out; 11345 } 11346 11347 mutex_exit(&mpt->m_mutex); 11348 if (cmd->cmd_flags & CFLAG_PREPARED) { 11349 function = request_hdrp->Function; 11350 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 11351 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 11352 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 11353 sense_len = cmd->cmd_extrqslen ? 11354 min(sense_len, cmd->cmd_extrqslen) : 11355 min(sense_len, cmd->cmd_rqslen); 11356 } else { 11357 reply_len = reply_size; 11358 sense_len = 0; 11359 } 11360 11361 for (i = 0; i < reply_len; i++) { 11362 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1, 11363 mode)) { 11364 mutex_enter(&mpt->m_mutex); 11365 status = EFAULT; 11366 mptsas_log(mpt, CE_WARN, "failed to copy out " 11367 "reply data"); 11368 goto out; 11369 } 11370 } 11371 for (i = 0; i < sense_len; i++) { 11372 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i, 11373 reply + reply_len + i, 1, mode)) { 11374 mutex_enter(&mpt->m_mutex); 11375 status = EFAULT; 11376 mptsas_log(mpt, CE_WARN, "failed to copy out " 11377 "sense data"); 11378 goto out; 11379 } 11380 } 11381 } 11382 11383 if (data_size) { 11384 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) { 11385 (void) ddi_dma_sync(data_dma_state.handle, 0, 0, 11386 DDI_DMA_SYNC_FORCPU); 11387 for (i = 0; i < data_size; i++) { 11388 if (ddi_copyout((uint8_t *)( 11389 data_dma_state.memp + i), data + i, 1, 11390 mode)) { 11391 mutex_enter(&mpt->m_mutex); 11392 status = EFAULT; 11393 mptsas_log(mpt, CE_WARN, "failed to " 11394 "copy out the reply data"); 11395 goto out; 11396 } 11397 } 11398 } 11399 } 11400 mutex_enter(&mpt->m_mutex); 11401 out: 11402 /* 11403 * Put the reply frame back on the free queue, increment the free 11404 * index, and write the new index to the free index register. But only 11405 * if this reply is an ADDRESS reply. 11406 */ 11407 if (pt_flags & MPTSAS_ADDRESS_REPLY) { 11408 ddi_put32(mpt->m_acc_free_queue_hdl, 11409 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11410 cmd->cmd_rfm); 11411 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11412 DDI_DMA_SYNC_FORDEV); 11413 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11414 mpt->m_free_index = 0; 11415 } 11416 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11417 mpt->m_free_index); 11418 } 11419 if (cmd) { 11420 if (cmd->cmd_extrqslen != 0) { 11421 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks, 11422 cmd->cmd_extrqsidx + 1); 11423 } 11424 if (cmd->cmd_flags & CFLAG_PREPARED) { 11425 mptsas_remove_cmd(mpt, cmd); 11426 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11427 } 11428 } 11429 if (pt_flags & MPTSAS_REQUEST_POOL_CMD) 11430 mptsas_return_to_pool(mpt, cmd); 11431 if (pt_flags & MPTSAS_DATA_ALLOCATED) { 11432 if (mptsas_check_dma_handle(data_dma_state.handle) != 11433 DDI_SUCCESS) { 11434 ddi_fm_service_impact(mpt->m_dip, 11435 DDI_SERVICE_UNAFFECTED); 11436 status = EFAULT; 11437 } 11438 mptsas_dma_free(&data_dma_state); 11439 } 11440 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) { 11441 if (mptsas_check_dma_handle(dataout_dma_state.handle) != 11442 DDI_SUCCESS) { 11443 ddi_fm_service_impact(mpt->m_dip, 11444 DDI_SERVICE_UNAFFECTED); 11445 status = EFAULT; 11446 } 11447 mptsas_dma_free(&dataout_dma_state); 11448 } 11449 if (pt_flags & MPTSAS_CMD_TIMEOUT) { 11450 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 11451 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed"); 11452 } 11453 } 11454 if (request_msg) 11455 kmem_free(request_msg, request_size); 11456 NDBG27(("mptsas_do_passthru: Done status 0x%x", status)); 11457 11458 return (status); 11459 } 11460 11461 static int 11462 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode) 11463 { 11464 /* 11465 * If timeout is 0, set timeout to default of 60 seconds. 11466 */ 11467 if (data->Timeout == 0) { 11468 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT; 11469 } 11470 11471 if (((data->DataSize == 0) && 11472 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) || 11473 ((data->DataSize != 0) && 11474 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) || 11475 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) || 11476 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) && 11477 (data->DataOutSize != 0))))) { 11478 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) { 11479 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ; 11480 } else { 11481 data->DataOutSize = 0; 11482 } 11483 /* 11484 * Send passthru request messages 11485 */ 11486 return (mptsas_do_passthru(mpt, 11487 (uint8_t *)((uintptr_t)data->PtrRequest), 11488 (uint8_t *)((uintptr_t)data->PtrReply), 11489 (uint8_t *)((uintptr_t)data->PtrData), 11490 data->RequestSize, data->ReplySize, 11491 data->DataSize, data->DataDirection, 11492 (uint8_t *)((uintptr_t)data->PtrDataOut), 11493 data->DataOutSize, data->Timeout, mode)); 11494 } else { 11495 return (EINVAL); 11496 } 11497 } 11498 11499 static uint8_t 11500 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id) 11501 { 11502 uint8_t index; 11503 11504 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) { 11505 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) { 11506 return (index); 11507 } 11508 } 11509 11510 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND); 11511 } 11512 11513 static void 11514 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd) 11515 { 11516 pMpi2DiagBufferPostRequest_t pDiag_post_msg; 11517 pMpi2DiagReleaseRequest_t pDiag_release_msg; 11518 struct scsi_pkt *pkt = cmd->cmd_pkt; 11519 mptsas_diag_request_t *diag = pkt->pkt_ha_private; 11520 uint32_t i; 11521 uint64_t request_desc; 11522 11523 ASSERT(mutex_owned(&mpt->m_mutex)); 11524 11525 /* 11526 * Form the diag message depending on the post or release function. 11527 */ 11528 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) { 11529 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t) 11530 (mpt->m_req_frame + (mpt->m_req_frame_size * 11531 cmd->cmd_slot)); 11532 bzero(pDiag_post_msg, mpt->m_req_frame_size); 11533 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function, 11534 diag->function); 11535 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType, 11536 diag->pBuffer->buffer_type); 11537 ddi_put8(mpt->m_acc_req_frame_hdl, 11538 &pDiag_post_msg->ExtendedType, 11539 diag->pBuffer->extended_type); 11540 ddi_put32(mpt->m_acc_req_frame_hdl, 11541 &pDiag_post_msg->BufferLength, 11542 diag->pBuffer->buffer_data.size); 11543 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4); 11544 i++) { 11545 ddi_put32(mpt->m_acc_req_frame_hdl, 11546 &pDiag_post_msg->ProductSpecific[i], 11547 diag->pBuffer->product_specific[i]); 11548 } 11549 ddi_put32(mpt->m_acc_req_frame_hdl, 11550 &pDiag_post_msg->BufferAddress.Low, 11551 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 11552 & 0xffffffffull)); 11553 ddi_put32(mpt->m_acc_req_frame_hdl, 11554 &pDiag_post_msg->BufferAddress.High, 11555 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 11556 >> 32)); 11557 } else { 11558 pDiag_release_msg = (pMpi2DiagReleaseRequest_t) 11559 (mpt->m_req_frame + (mpt->m_req_frame_size * 11560 cmd->cmd_slot)); 11561 bzero(pDiag_release_msg, mpt->m_req_frame_size); 11562 ddi_put8(mpt->m_acc_req_frame_hdl, 11563 &pDiag_release_msg->Function, diag->function); 11564 ddi_put8(mpt->m_acc_req_frame_hdl, 11565 &pDiag_release_msg->BufferType, 11566 diag->pBuffer->buffer_type); 11567 } 11568 11569 /* 11570 * Send the message 11571 */ 11572 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0, 11573 DDI_DMA_SYNC_FORDEV); 11574 request_desc = (cmd->cmd_slot << 16) + 11575 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 11576 cmd->cmd_rfm = 0; 11577 MPTSAS_START_CMD(mpt, request_desc); 11578 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 11579 DDI_SUCCESS) || 11580 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 11581 DDI_SUCCESS)) { 11582 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11583 } 11584 } 11585 11586 static int 11587 mptsas_post_fw_diag_buffer(mptsas_t *mpt, 11588 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code) 11589 { 11590 mptsas_diag_request_t diag; 11591 int status, slot_num, post_flags = 0; 11592 mptsas_cmd_t *cmd = NULL; 11593 struct scsi_pkt *pkt; 11594 pMpi2DiagBufferPostReply_t reply; 11595 uint16_t iocstatus; 11596 uint32_t iocloginfo, transfer_length; 11597 11598 /* 11599 * If buffer is not enabled, just leave. 11600 */ 11601 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED; 11602 if (!pBuffer->enabled) { 11603 status = DDI_FAILURE; 11604 goto out; 11605 } 11606 11607 /* 11608 * Clear some flags initially. 11609 */ 11610 pBuffer->force_release = FALSE; 11611 pBuffer->valid_data = FALSE; 11612 pBuffer->owned_by_firmware = FALSE; 11613 11614 /* 11615 * Get a cmd buffer from the cmd buffer pool 11616 */ 11617 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11618 status = DDI_FAILURE; 11619 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag"); 11620 goto out; 11621 } 11622 post_flags |= MPTSAS_REQUEST_POOL_CMD; 11623 11624 bzero((caddr_t)cmd, sizeof (*cmd)); 11625 bzero((caddr_t)pkt, scsi_pkt_size()); 11626 11627 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 11628 11629 diag.pBuffer = pBuffer; 11630 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST; 11631 11632 /* 11633 * Form a blank cmd/pkt to store the acknowledgement message 11634 */ 11635 pkt->pkt_ha_private = (opaque_t)&diag; 11636 pkt->pkt_flags = FLAG_HEAD; 11637 pkt->pkt_time = 60; 11638 cmd->cmd_pkt = pkt; 11639 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 11640 11641 /* 11642 * Save the command in a slot 11643 */ 11644 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11645 /* 11646 * Once passthru command get slot, set cmd_flags 11647 * CFLAG_PREPARED. 11648 */ 11649 cmd->cmd_flags |= CFLAG_PREPARED; 11650 mptsas_start_diag(mpt, cmd); 11651 } else { 11652 mptsas_waitq_add(mpt, cmd); 11653 } 11654 11655 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11656 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 11657 } 11658 11659 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11660 status = DDI_FAILURE; 11661 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout"); 11662 goto out; 11663 } 11664 11665 /* 11666 * cmd_rfm points to the reply message if a reply was given. Check the 11667 * IOCStatus to make sure everything went OK with the FW diag request 11668 * and set buffer flags. 11669 */ 11670 if (cmd->cmd_rfm) { 11671 post_flags |= MPTSAS_ADDRESS_REPLY; 11672 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11673 DDI_DMA_SYNC_FORCPU); 11674 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame + 11675 (cmd->cmd_rfm - 11676 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11677 11678 /* 11679 * Get the reply message data 11680 */ 11681 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 11682 &reply->IOCStatus); 11683 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 11684 &reply->IOCLogInfo); 11685 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl, 11686 &reply->TransferLength); 11687 11688 /* 11689 * If post failed quit. 11690 */ 11691 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) { 11692 status = DDI_FAILURE; 11693 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, " 11694 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus, 11695 iocloginfo, transfer_length)); 11696 goto out; 11697 } 11698 11699 /* 11700 * Post was successful. 11701 */ 11702 pBuffer->valid_data = TRUE; 11703 pBuffer->owned_by_firmware = TRUE; 11704 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11705 status = DDI_SUCCESS; 11706 } 11707 11708 out: 11709 /* 11710 * Put the reply frame back on the free queue, increment the free 11711 * index, and write the new index to the free index register. But only 11712 * if this reply is an ADDRESS reply. 11713 */ 11714 if (post_flags & MPTSAS_ADDRESS_REPLY) { 11715 ddi_put32(mpt->m_acc_free_queue_hdl, 11716 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11717 cmd->cmd_rfm); 11718 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11719 DDI_DMA_SYNC_FORDEV); 11720 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11721 mpt->m_free_index = 0; 11722 } 11723 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11724 mpt->m_free_index); 11725 } 11726 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 11727 mptsas_remove_cmd(mpt, cmd); 11728 post_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11729 } 11730 if (post_flags & MPTSAS_REQUEST_POOL_CMD) { 11731 mptsas_return_to_pool(mpt, cmd); 11732 } 11733 11734 return (status); 11735 } 11736 11737 static int 11738 mptsas_release_fw_diag_buffer(mptsas_t *mpt, 11739 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 11740 uint32_t diag_type) 11741 { 11742 mptsas_diag_request_t diag; 11743 int status, slot_num, rel_flags = 0; 11744 mptsas_cmd_t *cmd = NULL; 11745 struct scsi_pkt *pkt; 11746 pMpi2DiagReleaseReply_t reply; 11747 uint16_t iocstatus; 11748 uint32_t iocloginfo; 11749 11750 /* 11751 * If buffer is not enabled, just leave. 11752 */ 11753 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED; 11754 if (!pBuffer->enabled) { 11755 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported " 11756 "by the IOC"); 11757 status = DDI_FAILURE; 11758 goto out; 11759 } 11760 11761 /* 11762 * Clear some flags initially. 11763 */ 11764 pBuffer->force_release = FALSE; 11765 pBuffer->valid_data = FALSE; 11766 pBuffer->owned_by_firmware = FALSE; 11767 11768 /* 11769 * Get a cmd buffer from the cmd buffer pool 11770 */ 11771 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11772 status = DDI_FAILURE; 11773 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW " 11774 "Diag"); 11775 goto out; 11776 } 11777 rel_flags |= MPTSAS_REQUEST_POOL_CMD; 11778 11779 bzero((caddr_t)cmd, sizeof (*cmd)); 11780 bzero((caddr_t)pkt, scsi_pkt_size()); 11781 11782 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 11783 11784 diag.pBuffer = pBuffer; 11785 diag.function = MPI2_FUNCTION_DIAG_RELEASE; 11786 11787 /* 11788 * Form a blank cmd/pkt to store the acknowledgement message 11789 */ 11790 pkt->pkt_ha_private = (opaque_t)&diag; 11791 pkt->pkt_flags = FLAG_HEAD; 11792 pkt->pkt_time = 60; 11793 cmd->cmd_pkt = pkt; 11794 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 11795 11796 /* 11797 * Save the command in a slot 11798 */ 11799 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11800 /* 11801 * Once passthru command get slot, set cmd_flags 11802 * CFLAG_PREPARED. 11803 */ 11804 cmd->cmd_flags |= CFLAG_PREPARED; 11805 mptsas_start_diag(mpt, cmd); 11806 } else { 11807 mptsas_waitq_add(mpt, cmd); 11808 } 11809 11810 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11811 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 11812 } 11813 11814 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11815 status = DDI_FAILURE; 11816 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout"); 11817 goto out; 11818 } 11819 11820 /* 11821 * cmd_rfm points to the reply message if a reply was given. Check the 11822 * IOCStatus to make sure everything went OK with the FW diag request 11823 * and set buffer flags. 11824 */ 11825 if (cmd->cmd_rfm) { 11826 rel_flags |= MPTSAS_ADDRESS_REPLY; 11827 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11828 DDI_DMA_SYNC_FORCPU); 11829 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame + 11830 (cmd->cmd_rfm - 11831 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11832 11833 /* 11834 * Get the reply message data 11835 */ 11836 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 11837 &reply->IOCStatus); 11838 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 11839 &reply->IOCLogInfo); 11840 11841 /* 11842 * If release failed quit. 11843 */ 11844 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) || 11845 pBuffer->owned_by_firmware) { 11846 status = DDI_FAILURE; 11847 NDBG13(("release FW Diag Buffer failed: " 11848 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, 11849 iocloginfo)); 11850 goto out; 11851 } 11852 11853 /* 11854 * Release was successful. 11855 */ 11856 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11857 status = DDI_SUCCESS; 11858 11859 /* 11860 * If this was for an UNREGISTER diag type command, clear the 11861 * unique ID. 11862 */ 11863 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) { 11864 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 11865 } 11866 } 11867 11868 out: 11869 /* 11870 * Put the reply frame back on the free queue, increment the free 11871 * index, and write the new index to the free index register. But only 11872 * if this reply is an ADDRESS reply. 11873 */ 11874 if (rel_flags & MPTSAS_ADDRESS_REPLY) { 11875 ddi_put32(mpt->m_acc_free_queue_hdl, 11876 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11877 cmd->cmd_rfm); 11878 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11879 DDI_DMA_SYNC_FORDEV); 11880 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11881 mpt->m_free_index = 0; 11882 } 11883 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11884 mpt->m_free_index); 11885 } 11886 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 11887 mptsas_remove_cmd(mpt, cmd); 11888 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11889 } 11890 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) { 11891 mptsas_return_to_pool(mpt, cmd); 11892 } 11893 11894 return (status); 11895 } 11896 11897 static int 11898 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register, 11899 uint32_t *return_code) 11900 { 11901 mptsas_fw_diagnostic_buffer_t *pBuffer; 11902 uint8_t extended_type, buffer_type, i; 11903 uint32_t buffer_size; 11904 uint32_t unique_id; 11905 int status; 11906 11907 ASSERT(mutex_owned(&mpt->m_mutex)); 11908 11909 extended_type = diag_register->ExtendedType; 11910 buffer_type = diag_register->BufferType; 11911 buffer_size = diag_register->RequestedBufferSize; 11912 unique_id = diag_register->UniqueId; 11913 11914 /* 11915 * Check for valid buffer type 11916 */ 11917 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) { 11918 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11919 return (DDI_FAILURE); 11920 } 11921 11922 /* 11923 * Get the current buffer and look up the unique ID. The unique ID 11924 * should not be found. If it is, the ID is already in use. 11925 */ 11926 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11927 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type]; 11928 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11929 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11930 return (DDI_FAILURE); 11931 } 11932 11933 /* 11934 * The buffer's unique ID should not be registered yet, and the given 11935 * unique ID cannot be 0. 11936 */ 11937 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) || 11938 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11939 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11940 return (DDI_FAILURE); 11941 } 11942 11943 /* 11944 * If this buffer is already posted as immediate, just change owner. 11945 */ 11946 if (pBuffer->immediate && pBuffer->owned_by_firmware && 11947 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11948 pBuffer->immediate = FALSE; 11949 pBuffer->unique_id = unique_id; 11950 return (DDI_SUCCESS); 11951 } 11952 11953 /* 11954 * Post a new buffer after checking if it's enabled. The DMA buffer 11955 * that is allocated will be contiguous (sgl_len = 1). 11956 */ 11957 if (!pBuffer->enabled) { 11958 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11959 return (DDI_FAILURE); 11960 } 11961 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t)); 11962 pBuffer->buffer_data.size = buffer_size; 11963 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) { 11964 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for " 11965 "diag buffer: size = %d bytes", buffer_size); 11966 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11967 return (DDI_FAILURE); 11968 } 11969 11970 /* 11971 * Copy the given info to the diag buffer and post the buffer. 11972 */ 11973 pBuffer->buffer_type = buffer_type; 11974 pBuffer->immediate = FALSE; 11975 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) { 11976 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4); 11977 i++) { 11978 pBuffer->product_specific[i] = 11979 diag_register->ProductSpecific[i]; 11980 } 11981 } 11982 pBuffer->extended_type = extended_type; 11983 pBuffer->unique_id = unique_id; 11984 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code); 11985 11986 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 11987 DDI_SUCCESS) { 11988 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in " 11989 "mptsas_diag_register."); 11990 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11991 status = DDI_FAILURE; 11992 } 11993 11994 /* 11995 * In case there was a failure, free the DMA buffer. 11996 */ 11997 if (status == DDI_FAILURE) { 11998 mptsas_dma_free(&pBuffer->buffer_data); 11999 } 12000 12001 return (status); 12002 } 12003 12004 static int 12005 mptsas_diag_unregister(mptsas_t *mpt, 12006 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code) 12007 { 12008 mptsas_fw_diagnostic_buffer_t *pBuffer; 12009 uint8_t i; 12010 uint32_t unique_id; 12011 int status; 12012 12013 ASSERT(mutex_owned(&mpt->m_mutex)); 12014 12015 unique_id = diag_unregister->UniqueId; 12016 12017 /* 12018 * Get the current buffer and look up the unique ID. The unique ID 12019 * should be there. 12020 */ 12021 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12022 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12023 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12024 return (DDI_FAILURE); 12025 } 12026 12027 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12028 12029 /* 12030 * Try to release the buffer from FW before freeing it. If release 12031 * fails, don't free the DMA buffer in case FW tries to access it 12032 * later. If buffer is not owned by firmware, can't release it. 12033 */ 12034 if (!pBuffer->owned_by_firmware) { 12035 status = DDI_SUCCESS; 12036 } else { 12037 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, 12038 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER); 12039 } 12040 12041 /* 12042 * At this point, return the current status no matter what happens with 12043 * the DMA buffer. 12044 */ 12045 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 12046 if (status == DDI_SUCCESS) { 12047 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 12048 DDI_SUCCESS) { 12049 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed " 12050 "in mptsas_diag_unregister."); 12051 ddi_fm_service_impact(mpt->m_dip, 12052 DDI_SERVICE_UNAFFECTED); 12053 } 12054 mptsas_dma_free(&pBuffer->buffer_data); 12055 } 12056 12057 return (status); 12058 } 12059 12060 static int 12061 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 12062 uint32_t *return_code) 12063 { 12064 mptsas_fw_diagnostic_buffer_t *pBuffer; 12065 uint8_t i; 12066 uint32_t unique_id; 12067 12068 ASSERT(mutex_owned(&mpt->m_mutex)); 12069 12070 unique_id = diag_query->UniqueId; 12071 12072 /* 12073 * If ID is valid, query on ID. 12074 * If ID is invalid, query on buffer type. 12075 */ 12076 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) { 12077 i = diag_query->BufferType; 12078 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) { 12079 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12080 return (DDI_FAILURE); 12081 } 12082 } else { 12083 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12084 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12085 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12086 return (DDI_FAILURE); 12087 } 12088 } 12089 12090 /* 12091 * Fill query structure with the diag buffer info. 12092 */ 12093 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12094 diag_query->BufferType = pBuffer->buffer_type; 12095 diag_query->ExtendedType = pBuffer->extended_type; 12096 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) { 12097 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4); 12098 i++) { 12099 diag_query->ProductSpecific[i] = 12100 pBuffer->product_specific[i]; 12101 } 12102 } 12103 diag_query->TotalBufferSize = pBuffer->buffer_data.size; 12104 diag_query->DriverAddedBufferSize = 0; 12105 diag_query->UniqueId = pBuffer->unique_id; 12106 diag_query->ApplicationFlags = 0; 12107 diag_query->DiagnosticFlags = 0; 12108 12109 /* 12110 * Set/Clear application flags 12111 */ 12112 if (pBuffer->immediate) { 12113 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED; 12114 } else { 12115 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED; 12116 } 12117 if (pBuffer->valid_data || pBuffer->owned_by_firmware) { 12118 diag_query->ApplicationFlags |= 12119 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 12120 } else { 12121 diag_query->ApplicationFlags &= 12122 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 12123 } 12124 if (pBuffer->owned_by_firmware) { 12125 diag_query->ApplicationFlags |= 12126 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 12127 } else { 12128 diag_query->ApplicationFlags &= 12129 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 12130 } 12131 12132 return (DDI_SUCCESS); 12133 } 12134 12135 static int 12136 mptsas_diag_read_buffer(mptsas_t *mpt, 12137 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 12138 uint32_t *return_code, int ioctl_mode) 12139 { 12140 mptsas_fw_diagnostic_buffer_t *pBuffer; 12141 uint8_t i, *pData; 12142 uint32_t unique_id, byte; 12143 int status; 12144 12145 ASSERT(mutex_owned(&mpt->m_mutex)); 12146 12147 unique_id = diag_read_buffer->UniqueId; 12148 12149 /* 12150 * Get the current buffer and look up the unique ID. The unique ID 12151 * should be there. 12152 */ 12153 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12154 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12155 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12156 return (DDI_FAILURE); 12157 } 12158 12159 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12160 12161 /* 12162 * Make sure requested read is within limits 12163 */ 12164 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead > 12165 pBuffer->buffer_data.size) { 12166 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12167 return (DDI_FAILURE); 12168 } 12169 12170 /* 12171 * Copy the requested data from DMA to the diag_read_buffer. The DMA 12172 * buffer that was allocated is one contiguous buffer. 12173 */ 12174 pData = (uint8_t *)(pBuffer->buffer_data.memp + 12175 diag_read_buffer->StartingOffset); 12176 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0, 12177 DDI_DMA_SYNC_FORCPU); 12178 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) { 12179 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode) 12180 != 0) { 12181 return (DDI_FAILURE); 12182 } 12183 } 12184 diag_read_buffer->Status = 0; 12185 12186 /* 12187 * Set or clear the Force Release flag. 12188 */ 12189 if (pBuffer->force_release) { 12190 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 12191 } else { 12192 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 12193 } 12194 12195 /* 12196 * If buffer is to be reregistered, make sure it's not already owned by 12197 * firmware first. 12198 */ 12199 status = DDI_SUCCESS; 12200 if (!pBuffer->owned_by_firmware) { 12201 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) { 12202 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, 12203 return_code); 12204 } 12205 } 12206 12207 return (status); 12208 } 12209 12210 static int 12211 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release, 12212 uint32_t *return_code) 12213 { 12214 mptsas_fw_diagnostic_buffer_t *pBuffer; 12215 uint8_t i; 12216 uint32_t unique_id; 12217 int status; 12218 12219 ASSERT(mutex_owned(&mpt->m_mutex)); 12220 12221 unique_id = diag_release->UniqueId; 12222 12223 /* 12224 * Get the current buffer and look up the unique ID. The unique ID 12225 * should be there. 12226 */ 12227 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12228 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12229 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12230 return (DDI_FAILURE); 12231 } 12232 12233 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12234 12235 /* 12236 * If buffer is not owned by firmware, it's already been released. 12237 */ 12238 if (!pBuffer->owned_by_firmware) { 12239 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED; 12240 return (DDI_FAILURE); 12241 } 12242 12243 /* 12244 * Release the buffer. 12245 */ 12246 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code, 12247 MPTSAS_FW_DIAG_TYPE_RELEASE); 12248 return (status); 12249 } 12250 12251 static int 12252 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action, 12253 uint32_t length, uint32_t *return_code, int ioctl_mode) 12254 { 12255 mptsas_fw_diag_register_t diag_register; 12256 mptsas_fw_diag_unregister_t diag_unregister; 12257 mptsas_fw_diag_query_t diag_query; 12258 mptsas_diag_read_buffer_t diag_read_buffer; 12259 mptsas_fw_diag_release_t diag_release; 12260 int status = DDI_SUCCESS; 12261 uint32_t original_return_code, read_buf_len; 12262 12263 ASSERT(mutex_owned(&mpt->m_mutex)); 12264 12265 original_return_code = *return_code; 12266 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 12267 12268 switch (action) { 12269 case MPTSAS_FW_DIAG_TYPE_REGISTER: 12270 if (!length) { 12271 *return_code = 12272 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12273 status = DDI_FAILURE; 12274 break; 12275 } 12276 if (ddi_copyin(diag_action, &diag_register, 12277 sizeof (diag_register), ioctl_mode) != 0) { 12278 return (DDI_FAILURE); 12279 } 12280 status = mptsas_diag_register(mpt, &diag_register, 12281 return_code); 12282 break; 12283 12284 case MPTSAS_FW_DIAG_TYPE_UNREGISTER: 12285 if (length < sizeof (diag_unregister)) { 12286 *return_code = 12287 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12288 status = DDI_FAILURE; 12289 break; 12290 } 12291 if (ddi_copyin(diag_action, &diag_unregister, 12292 sizeof (diag_unregister), ioctl_mode) != 0) { 12293 return (DDI_FAILURE); 12294 } 12295 status = mptsas_diag_unregister(mpt, &diag_unregister, 12296 return_code); 12297 break; 12298 12299 case MPTSAS_FW_DIAG_TYPE_QUERY: 12300 if (length < sizeof (diag_query)) { 12301 *return_code = 12302 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12303 status = DDI_FAILURE; 12304 break; 12305 } 12306 if (ddi_copyin(diag_action, &diag_query, 12307 sizeof (diag_query), ioctl_mode) != 0) { 12308 return (DDI_FAILURE); 12309 } 12310 status = mptsas_diag_query(mpt, &diag_query, 12311 return_code); 12312 if (status == DDI_SUCCESS) { 12313 if (ddi_copyout(&diag_query, diag_action, 12314 sizeof (diag_query), ioctl_mode) != 0) { 12315 return (DDI_FAILURE); 12316 } 12317 } 12318 break; 12319 12320 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER: 12321 if (ddi_copyin(diag_action, &diag_read_buffer, 12322 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) { 12323 return (DDI_FAILURE); 12324 } 12325 read_buf_len = sizeof (diag_read_buffer) - 12326 sizeof (diag_read_buffer.DataBuffer) + 12327 diag_read_buffer.BytesToRead; 12328 if (length < read_buf_len) { 12329 *return_code = 12330 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12331 status = DDI_FAILURE; 12332 break; 12333 } 12334 status = mptsas_diag_read_buffer(mpt, 12335 &diag_read_buffer, diag_action + 12336 sizeof (diag_read_buffer) - 4, return_code, 12337 ioctl_mode); 12338 if (status == DDI_SUCCESS) { 12339 if (ddi_copyout(&diag_read_buffer, diag_action, 12340 sizeof (diag_read_buffer) - 4, ioctl_mode) 12341 != 0) { 12342 return (DDI_FAILURE); 12343 } 12344 } 12345 break; 12346 12347 case MPTSAS_FW_DIAG_TYPE_RELEASE: 12348 if (length < sizeof (diag_release)) { 12349 *return_code = 12350 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12351 status = DDI_FAILURE; 12352 break; 12353 } 12354 if (ddi_copyin(diag_action, &diag_release, 12355 sizeof (diag_release), ioctl_mode) != 0) { 12356 return (DDI_FAILURE); 12357 } 12358 status = mptsas_diag_release(mpt, &diag_release, 12359 return_code); 12360 break; 12361 12362 default: 12363 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12364 status = DDI_FAILURE; 12365 break; 12366 } 12367 12368 if ((status == DDI_FAILURE) && 12369 (original_return_code == MPTSAS_FW_DIAG_NEW) && 12370 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) { 12371 status = DDI_SUCCESS; 12372 } 12373 12374 return (status); 12375 } 12376 12377 static int 12378 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode) 12379 { 12380 int status; 12381 mptsas_diag_action_t driver_data; 12382 12383 ASSERT(mutex_owned(&mpt->m_mutex)); 12384 12385 /* 12386 * Copy the user data to a driver data buffer. 12387 */ 12388 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t), 12389 mode) == 0) { 12390 /* 12391 * Send diag action request if Action is valid 12392 */ 12393 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER || 12394 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER || 12395 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY || 12396 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER || 12397 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) { 12398 status = mptsas_do_diag_action(mpt, driver_data.Action, 12399 (void *)(uintptr_t)driver_data.PtrDiagAction, 12400 driver_data.Length, &driver_data.ReturnCode, 12401 mode); 12402 if (status == DDI_SUCCESS) { 12403 if (ddi_copyout(&driver_data.ReturnCode, 12404 &user_data->ReturnCode, 12405 sizeof (user_data->ReturnCode), mode) 12406 != 0) { 12407 status = EFAULT; 12408 } else { 12409 status = 0; 12410 } 12411 } else { 12412 status = EIO; 12413 } 12414 } else { 12415 status = EINVAL; 12416 } 12417 } else { 12418 status = EFAULT; 12419 } 12420 12421 return (status); 12422 } 12423 12424 /* 12425 * This routine handles the "event query" ioctl. 12426 */ 12427 static int 12428 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode, 12429 int *rval) 12430 { 12431 int status; 12432 mptsas_event_query_t driverdata; 12433 uint8_t i; 12434 12435 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE; 12436 12437 mutex_enter(&mpt->m_mutex); 12438 for (i = 0; i < 4; i++) { 12439 driverdata.Types[i] = mpt->m_event_mask[i]; 12440 } 12441 mutex_exit(&mpt->m_mutex); 12442 12443 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) { 12444 status = EFAULT; 12445 } else { 12446 *rval = MPTIOCTL_STATUS_GOOD; 12447 status = 0; 12448 } 12449 12450 return (status); 12451 } 12452 12453 /* 12454 * This routine handles the "event enable" ioctl. 12455 */ 12456 static int 12457 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode, 12458 int *rval) 12459 { 12460 int status; 12461 mptsas_event_enable_t driverdata; 12462 uint8_t i; 12463 12464 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 12465 mutex_enter(&mpt->m_mutex); 12466 for (i = 0; i < 4; i++) { 12467 mpt->m_event_mask[i] = driverdata.Types[i]; 12468 } 12469 mutex_exit(&mpt->m_mutex); 12470 12471 *rval = MPTIOCTL_STATUS_GOOD; 12472 status = 0; 12473 } else { 12474 status = EFAULT; 12475 } 12476 return (status); 12477 } 12478 12479 /* 12480 * This routine handles the "event report" ioctl. 12481 */ 12482 static int 12483 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode, 12484 int *rval) 12485 { 12486 int status; 12487 mptsas_event_report_t driverdata; 12488 12489 mutex_enter(&mpt->m_mutex); 12490 12491 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size), 12492 mode) == 0) { 12493 if (driverdata.Size >= sizeof (mpt->m_events)) { 12494 if (ddi_copyout(mpt->m_events, data->Events, 12495 sizeof (mpt->m_events), mode) != 0) { 12496 status = EFAULT; 12497 } else { 12498 if (driverdata.Size > sizeof (mpt->m_events)) { 12499 driverdata.Size = 12500 sizeof (mpt->m_events); 12501 if (ddi_copyout(&driverdata.Size, 12502 &data->Size, 12503 sizeof (driverdata.Size), 12504 mode) != 0) { 12505 status = EFAULT; 12506 } else { 12507 *rval = MPTIOCTL_STATUS_GOOD; 12508 status = 0; 12509 } 12510 } else { 12511 *rval = MPTIOCTL_STATUS_GOOD; 12512 status = 0; 12513 } 12514 } 12515 } else { 12516 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 12517 status = 0; 12518 } 12519 } else { 12520 status = EFAULT; 12521 } 12522 12523 mutex_exit(&mpt->m_mutex); 12524 return (status); 12525 } 12526 12527 static void 12528 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 12529 { 12530 int *reg_data; 12531 uint_t reglen; 12532 12533 /* 12534 * Lookup the 'reg' property and extract the other data 12535 */ 12536 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 12537 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 12538 DDI_PROP_SUCCESS) { 12539 /* 12540 * Extract the PCI data from the 'reg' property first DWORD. 12541 * The entry looks like the following: 12542 * First DWORD: 12543 * Bits 0 - 7 8-bit Register number 12544 * Bits 8 - 10 3-bit Function number 12545 * Bits 11 - 15 5-bit Device number 12546 * Bits 16 - 23 8-bit Bus number 12547 * Bits 24 - 25 2-bit Address Space type identifier 12548 * 12549 */ 12550 adapter_data->PciInformation.u.bits.BusNumber = 12551 (reg_data[0] & 0x00FF0000) >> 16; 12552 adapter_data->PciInformation.u.bits.DeviceNumber = 12553 (reg_data[0] & 0x0000F800) >> 11; 12554 adapter_data->PciInformation.u.bits.FunctionNumber = 12555 (reg_data[0] & 0x00000700) >> 8; 12556 ddi_prop_free((void *)reg_data); 12557 } else { 12558 /* 12559 * If we can't determine the PCI data then we fill in FF's for 12560 * the data to indicate this. 12561 */ 12562 adapter_data->PCIDeviceHwId = 0xFFFFFFFF; 12563 adapter_data->MpiPortNumber = 0xFFFFFFFF; 12564 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF; 12565 } 12566 12567 /* 12568 * Saved in the mpt->m_fwversion 12569 */ 12570 adapter_data->MpiFirmwareVersion = mpt->m_fwversion; 12571 } 12572 12573 static void 12574 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 12575 { 12576 char *driver_verstr = MPTSAS_MOD_STRING; 12577 12578 mptsas_lookup_pci_data(mpt, adapter_data); 12579 adapter_data->AdapterType = mpt->m_MPI25 ? 12580 MPTIOCTL_ADAPTER_TYPE_SAS3 : 12581 MPTIOCTL_ADAPTER_TYPE_SAS2; 12582 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid; 12583 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid; 12584 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid; 12585 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid; 12586 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr); 12587 adapter_data->BiosVersion = 0; 12588 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion); 12589 } 12590 12591 static void 12592 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info) 12593 { 12594 int *reg_data, i; 12595 uint_t reglen; 12596 12597 /* 12598 * Lookup the 'reg' property and extract the other data 12599 */ 12600 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 12601 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 12602 DDI_PROP_SUCCESS) { 12603 /* 12604 * Extract the PCI data from the 'reg' property first DWORD. 12605 * The entry looks like the following: 12606 * First DWORD: 12607 * Bits 8 - 10 3-bit Function number 12608 * Bits 11 - 15 5-bit Device number 12609 * Bits 16 - 23 8-bit Bus number 12610 */ 12611 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16; 12612 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11; 12613 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8; 12614 ddi_prop_free((void *)reg_data); 12615 } else { 12616 /* 12617 * If we can't determine the PCI info then we fill in FF's for 12618 * the data to indicate this. 12619 */ 12620 pci_info->BusNumber = 0xFFFFFFFF; 12621 pci_info->DeviceNumber = 0xFF; 12622 pci_info->FunctionNumber = 0xFF; 12623 } 12624 12625 /* 12626 * Now get the interrupt vector and the pci header. The vector can 12627 * only be 0 right now. The header is the first 256 bytes of config 12628 * space. 12629 */ 12630 pci_info->InterruptVector = 0; 12631 for (i = 0; i < sizeof (pci_info->PciHeader); i++) { 12632 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle, 12633 i); 12634 } 12635 } 12636 12637 static int 12638 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode) 12639 { 12640 int status = 0; 12641 mptsas_reg_access_t driverdata; 12642 12643 mutex_enter(&mpt->m_mutex); 12644 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 12645 switch (driverdata.Command) { 12646 /* 12647 * IO access is not supported. 12648 */ 12649 case REG_IO_READ: 12650 case REG_IO_WRITE: 12651 mptsas_log(mpt, CE_WARN, "IO access is not " 12652 "supported. Use memory access."); 12653 status = EINVAL; 12654 break; 12655 12656 case REG_MEM_READ: 12657 driverdata.RegData = ddi_get32(mpt->m_datap, 12658 (uint32_t *)(void *)mpt->m_reg + 12659 driverdata.RegOffset); 12660 if (ddi_copyout(&driverdata.RegData, 12661 &data->RegData, 12662 sizeof (driverdata.RegData), mode) != 0) { 12663 mptsas_log(mpt, CE_WARN, "Register " 12664 "Read Failed"); 12665 status = EFAULT; 12666 } 12667 break; 12668 12669 case REG_MEM_WRITE: 12670 ddi_put32(mpt->m_datap, 12671 (uint32_t *)(void *)mpt->m_reg + 12672 driverdata.RegOffset, 12673 driverdata.RegData); 12674 break; 12675 12676 default: 12677 status = EINVAL; 12678 break; 12679 } 12680 } else { 12681 status = EFAULT; 12682 } 12683 12684 mutex_exit(&mpt->m_mutex); 12685 return (status); 12686 } 12687 12688 static int 12689 led_control(mptsas_t *mpt, intptr_t data, int mode) 12690 { 12691 int ret = 0; 12692 mptsas_led_control_t lc; 12693 mptsas_enclosure_t *mep; 12694 uint16_t slotidx; 12695 12696 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) { 12697 return (EFAULT); 12698 } 12699 12700 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET && 12701 lc.Command != MPTSAS_LEDCTL_FLAG_GET) || 12702 lc.Led < MPTSAS_LEDCTL_LED_MIN || 12703 lc.Led > MPTSAS_LEDCTL_LED_MAX || 12704 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 && 12705 lc.LedStatus != 1)) { 12706 return (EINVAL); 12707 } 12708 12709 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) || 12710 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0)) 12711 return (EACCES); 12712 12713 /* Locate the required enclosure */ 12714 mutex_enter(&mpt->m_mutex); 12715 mep = mptsas_enc_lookup(mpt, lc.Enclosure); 12716 if (mep == NULL) { 12717 mutex_exit(&mpt->m_mutex); 12718 return (ENOENT); 12719 } 12720 12721 if (lc.Slot < mep->me_fslot) { 12722 mutex_exit(&mpt->m_mutex); 12723 return (ENOENT); 12724 } 12725 12726 /* 12727 * Slots on the enclosure are maintained in array where me_fslot is 12728 * entry zero. We normalize the requested slot. 12729 */ 12730 slotidx = lc.Slot - mep->me_fslot; 12731 if (slotidx >= mep->me_nslots) { 12732 mutex_exit(&mpt->m_mutex); 12733 return (ENOENT); 12734 } 12735 12736 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) { 12737 /* Update our internal LED state. */ 12738 mep->me_slotleds[slotidx] &= ~(1 << (lc.Led - 1)); 12739 mep->me_slotleds[slotidx] |= lc.LedStatus << (lc.Led - 1); 12740 12741 /* Flush it to the controller. */ 12742 ret = mptsas_flush_led_status(mpt, mep, slotidx); 12743 mutex_exit(&mpt->m_mutex); 12744 return (ret); 12745 } 12746 12747 /* Return our internal LED state. */ 12748 lc.LedStatus = (mep->me_slotleds[slotidx] >> (lc.Led - 1)) & 1; 12749 mutex_exit(&mpt->m_mutex); 12750 12751 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) { 12752 return (EFAULT); 12753 } 12754 12755 return (0); 12756 } 12757 12758 static int 12759 get_disk_info(mptsas_t *mpt, intptr_t data, int mode) 12760 { 12761 uint16_t i = 0; 12762 uint16_t count = 0; 12763 int ret = 0; 12764 mptsas_target_t *ptgt; 12765 mptsas_disk_info_t *di; 12766 STRUCT_DECL(mptsas_get_disk_info, gdi); 12767 12768 if ((mode & FREAD) == 0) 12769 return (EACCES); 12770 12771 STRUCT_INIT(gdi, get_udatamodel()); 12772 12773 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi), 12774 mode) != 0) { 12775 return (EFAULT); 12776 } 12777 12778 /* Find out how many targets there are. */ 12779 mutex_enter(&mpt->m_mutex); 12780 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12781 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12782 count++; 12783 } 12784 mutex_exit(&mpt->m_mutex); 12785 12786 /* 12787 * If we haven't been asked to copy out information on each target, 12788 * then just return the count. 12789 */ 12790 STRUCT_FSET(gdi, DiskCount, count); 12791 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL) 12792 goto copy_out; 12793 12794 /* 12795 * If we haven't been given a large enough buffer to copy out into, 12796 * let the caller know. 12797 */ 12798 if (STRUCT_FGET(gdi, DiskInfoArraySize) < 12799 count * sizeof (mptsas_disk_info_t)) { 12800 ret = ENOSPC; 12801 goto copy_out; 12802 } 12803 12804 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP); 12805 12806 mutex_enter(&mpt->m_mutex); 12807 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12808 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12809 if (i >= count) { 12810 /* 12811 * The number of targets changed while we weren't 12812 * looking, so give up. 12813 */ 12814 refhash_rele(mpt->m_targets, ptgt); 12815 mutex_exit(&mpt->m_mutex); 12816 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 12817 return (EAGAIN); 12818 } 12819 di[i].Instance = mpt->m_instance; 12820 di[i].Enclosure = ptgt->m_enclosure; 12821 di[i].Slot = ptgt->m_slot_num; 12822 di[i].SasAddress = ptgt->m_addr.mta_wwn; 12823 i++; 12824 } 12825 mutex_exit(&mpt->m_mutex); 12826 STRUCT_FSET(gdi, DiskCount, i); 12827 12828 /* Copy out the disk information to the caller. */ 12829 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray), 12830 i * sizeof (mptsas_disk_info_t), mode) != 0) { 12831 ret = EFAULT; 12832 } 12833 12834 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 12835 12836 copy_out: 12837 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi), 12838 mode) != 0) { 12839 ret = EFAULT; 12840 } 12841 12842 return (ret); 12843 } 12844 12845 static int 12846 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp, 12847 int *rval) 12848 { 12849 int status = 0; 12850 mptsas_t *mpt; 12851 mptsas_update_flash_t flashdata; 12852 mptsas_pass_thru_t passthru_data; 12853 mptsas_adapter_data_t adapter_data; 12854 mptsas_pci_info_t pci_info; 12855 int copylen; 12856 12857 int iport_flag = 0; 12858 dev_info_t *dip = NULL; 12859 mptsas_phymask_t phymask = 0; 12860 struct devctl_iocdata *dcp = NULL; 12861 char *addr = NULL; 12862 mptsas_target_t *ptgt = NULL; 12863 12864 *rval = MPTIOCTL_STATUS_GOOD; 12865 if (secpolicy_sys_config(credp, B_FALSE) != 0) { 12866 return (EPERM); 12867 } 12868 12869 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev))); 12870 if (mpt == NULL) { 12871 /* 12872 * Called from iport node, get the states 12873 */ 12874 iport_flag = 1; 12875 dip = mptsas_get_dip_from_dev(dev, &phymask); 12876 if (dip == NULL) { 12877 return (ENXIO); 12878 } 12879 mpt = DIP2MPT(dip); 12880 } 12881 /* Make sure power level is D0 before accessing registers */ 12882 mutex_enter(&mpt->m_mutex); 12883 if (mpt->m_options & MPTSAS_OPT_PM) { 12884 (void) pm_busy_component(mpt->m_dip, 0); 12885 if (mpt->m_power_level != PM_LEVEL_D0) { 12886 mutex_exit(&mpt->m_mutex); 12887 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) != 12888 DDI_SUCCESS) { 12889 mptsas_log(mpt, CE_WARN, 12890 "mptsas%d: mptsas_ioctl: Raise power " 12891 "request failed.", mpt->m_instance); 12892 (void) pm_idle_component(mpt->m_dip, 0); 12893 return (ENXIO); 12894 } 12895 } else { 12896 mutex_exit(&mpt->m_mutex); 12897 } 12898 } else { 12899 mutex_exit(&mpt->m_mutex); 12900 } 12901 12902 if (iport_flag) { 12903 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval); 12904 if (status != 0) { 12905 goto out; 12906 } 12907 /* 12908 * The following code control the OK2RM LED, it doesn't affect 12909 * the ioctl return status. 12910 */ 12911 if ((cmd == DEVCTL_DEVICE_ONLINE) || 12912 (cmd == DEVCTL_DEVICE_OFFLINE)) { 12913 if (ndi_dc_allochdl((void *)data, &dcp) != 12914 NDI_SUCCESS) { 12915 goto out; 12916 } 12917 addr = ndi_dc_getaddr(dcp); 12918 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask); 12919 if (ptgt == NULL) { 12920 NDBG14(("mptsas_ioctl led control: tgt %s not " 12921 "found", addr)); 12922 ndi_dc_freehdl(dcp); 12923 goto out; 12924 } 12925 ndi_dc_freehdl(dcp); 12926 } 12927 goto out; 12928 } 12929 switch (cmd) { 12930 case MPTIOCTL_GET_DISK_INFO: 12931 status = get_disk_info(mpt, data, mode); 12932 break; 12933 case MPTIOCTL_LED_CONTROL: 12934 status = led_control(mpt, data, mode); 12935 break; 12936 case MPTIOCTL_UPDATE_FLASH: 12937 if (ddi_copyin((void *)data, &flashdata, 12938 sizeof (struct mptsas_update_flash), mode)) { 12939 status = EFAULT; 12940 break; 12941 } 12942 12943 mutex_enter(&mpt->m_mutex); 12944 if (mptsas_update_flash(mpt, 12945 (caddr_t)(long)flashdata.PtrBuffer, 12946 flashdata.ImageSize, flashdata.ImageType, mode)) { 12947 status = EFAULT; 12948 } 12949 12950 /* 12951 * Reset the chip to start using the new 12952 * firmware. Reset if failed also. 12953 */ 12954 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 12955 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 12956 status = EFAULT; 12957 } 12958 mutex_exit(&mpt->m_mutex); 12959 break; 12960 case MPTIOCTL_PASS_THRU: 12961 /* 12962 * The user has requested to pass through a command to 12963 * be executed by the MPT firmware. Call our routine 12964 * which does this. Only allow one passthru IOCTL at 12965 * one time. Other threads will block on 12966 * m_passthru_mutex, which is of adaptive variant. 12967 */ 12968 if (ddi_copyin((void *)data, &passthru_data, 12969 sizeof (mptsas_pass_thru_t), mode)) { 12970 status = EFAULT; 12971 break; 12972 } 12973 mutex_enter(&mpt->m_passthru_mutex); 12974 mutex_enter(&mpt->m_mutex); 12975 status = mptsas_pass_thru(mpt, &passthru_data, mode); 12976 mutex_exit(&mpt->m_mutex); 12977 mutex_exit(&mpt->m_passthru_mutex); 12978 12979 break; 12980 case MPTIOCTL_GET_ADAPTER_DATA: 12981 /* 12982 * The user has requested to read adapter data. Call 12983 * our routine which does this. 12984 */ 12985 bzero(&adapter_data, sizeof (mptsas_adapter_data_t)); 12986 if (ddi_copyin((void *)data, (void *)&adapter_data, 12987 sizeof (mptsas_adapter_data_t), mode)) { 12988 status = EFAULT; 12989 break; 12990 } 12991 if (adapter_data.StructureLength >= 12992 sizeof (mptsas_adapter_data_t)) { 12993 adapter_data.StructureLength = (uint32_t) 12994 sizeof (mptsas_adapter_data_t); 12995 copylen = sizeof (mptsas_adapter_data_t); 12996 mutex_enter(&mpt->m_mutex); 12997 mptsas_read_adapter_data(mpt, &adapter_data); 12998 mutex_exit(&mpt->m_mutex); 12999 } else { 13000 adapter_data.StructureLength = (uint32_t) 13001 sizeof (mptsas_adapter_data_t); 13002 copylen = sizeof (adapter_data.StructureLength); 13003 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 13004 } 13005 if (ddi_copyout((void *)(&adapter_data), (void *)data, 13006 copylen, mode) != 0) { 13007 status = EFAULT; 13008 } 13009 break; 13010 case MPTIOCTL_GET_PCI_INFO: 13011 /* 13012 * The user has requested to read pci info. Call 13013 * our routine which does this. 13014 */ 13015 bzero(&pci_info, sizeof (mptsas_pci_info_t)); 13016 mutex_enter(&mpt->m_mutex); 13017 mptsas_read_pci_info(mpt, &pci_info); 13018 mutex_exit(&mpt->m_mutex); 13019 if (ddi_copyout((void *)(&pci_info), (void *)data, 13020 sizeof (mptsas_pci_info_t), mode) != 0) { 13021 status = EFAULT; 13022 } 13023 break; 13024 case MPTIOCTL_RESET_ADAPTER: 13025 mutex_enter(&mpt->m_mutex); 13026 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 13027 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 13028 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL " 13029 "failed"); 13030 status = EFAULT; 13031 } 13032 mutex_exit(&mpt->m_mutex); 13033 break; 13034 case MPTIOCTL_DIAG_ACTION: 13035 /* 13036 * The user has done a diag buffer action. Call our 13037 * routine which does this. Only allow one diag action 13038 * at one time. 13039 */ 13040 mutex_enter(&mpt->m_mutex); 13041 if (mpt->m_diag_action_in_progress) { 13042 mutex_exit(&mpt->m_mutex); 13043 return (EBUSY); 13044 } 13045 mpt->m_diag_action_in_progress = 1; 13046 status = mptsas_diag_action(mpt, 13047 (mptsas_diag_action_t *)data, mode); 13048 mpt->m_diag_action_in_progress = 0; 13049 mutex_exit(&mpt->m_mutex); 13050 break; 13051 case MPTIOCTL_EVENT_QUERY: 13052 /* 13053 * The user has done an event query. Call our routine 13054 * which does this. 13055 */ 13056 status = mptsas_event_query(mpt, 13057 (mptsas_event_query_t *)data, mode, rval); 13058 break; 13059 case MPTIOCTL_EVENT_ENABLE: 13060 /* 13061 * The user has done an event enable. Call our routine 13062 * which does this. 13063 */ 13064 status = mptsas_event_enable(mpt, 13065 (mptsas_event_enable_t *)data, mode, rval); 13066 break; 13067 case MPTIOCTL_EVENT_REPORT: 13068 /* 13069 * The user has done an event report. Call our routine 13070 * which does this. 13071 */ 13072 status = mptsas_event_report(mpt, 13073 (mptsas_event_report_t *)data, mode, rval); 13074 break; 13075 case MPTIOCTL_REG_ACCESS: 13076 /* 13077 * The user has requested register access. Call our 13078 * routine which does this. 13079 */ 13080 status = mptsas_reg_access(mpt, 13081 (mptsas_reg_access_t *)data, mode); 13082 break; 13083 default: 13084 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, 13085 rval); 13086 break; 13087 } 13088 13089 out: 13090 return (status); 13091 } 13092 13093 int 13094 mptsas_restart_ioc(mptsas_t *mpt) 13095 { 13096 int rval = DDI_SUCCESS; 13097 mptsas_target_t *ptgt = NULL; 13098 13099 ASSERT(mutex_owned(&mpt->m_mutex)); 13100 13101 /* 13102 * Set a flag telling I/O path that we're processing a reset. This is 13103 * needed because after the reset is complete, the hash table still 13104 * needs to be rebuilt. If I/Os are started before the hash table is 13105 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked 13106 * so that they can be retried. 13107 */ 13108 mpt->m_in_reset = TRUE; 13109 13110 /* 13111 * Wait until all the allocated sense data buffers for DMA are freed. 13112 */ 13113 while (mpt->m_extreq_sense_refcount > 0) 13114 cv_wait(&mpt->m_extreq_sense_refcount_cv, &mpt->m_mutex); 13115 13116 /* 13117 * Set all throttles to HOLD 13118 */ 13119 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 13120 ptgt = refhash_next(mpt->m_targets, ptgt)) { 13121 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 13122 } 13123 13124 /* 13125 * Disable interrupts 13126 */ 13127 MPTSAS_DISABLE_INTR(mpt); 13128 13129 /* 13130 * Abort all commands: outstanding commands, commands in waitq and 13131 * tx_waitq. 13132 */ 13133 mptsas_flush_hba(mpt); 13134 13135 /* 13136 * Reinitialize the chip. 13137 */ 13138 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 13139 rval = DDI_FAILURE; 13140 } 13141 13142 /* 13143 * Enable interrupts again 13144 */ 13145 MPTSAS_ENABLE_INTR(mpt); 13146 13147 /* 13148 * If mptsas_init_chip was successful, update the driver data. 13149 */ 13150 if (rval == DDI_SUCCESS) { 13151 mptsas_update_driver_data(mpt); 13152 } 13153 13154 /* 13155 * Reset the throttles 13156 */ 13157 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 13158 ptgt = refhash_next(mpt->m_targets, ptgt)) { 13159 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 13160 } 13161 13162 mptsas_doneq_empty(mpt); 13163 mptsas_restart_hba(mpt); 13164 13165 if (rval != DDI_SUCCESS) { 13166 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 13167 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 13168 } 13169 13170 /* 13171 * Clear the reset flag so that I/Os can continue. 13172 */ 13173 mpt->m_in_reset = FALSE; 13174 13175 return (rval); 13176 } 13177 13178 static int 13179 mptsas_init_chip(mptsas_t *mpt, int first_time) 13180 { 13181 ddi_dma_cookie_t cookie; 13182 uint32_t i; 13183 int rval; 13184 13185 /* 13186 * Check to see if the firmware image is valid 13187 */ 13188 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) & 13189 MPI2_DIAG_FLASH_BAD_SIG) { 13190 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!"); 13191 goto fail; 13192 } 13193 13194 /* 13195 * Reset the chip 13196 */ 13197 rval = mptsas_ioc_reset(mpt, first_time); 13198 if (rval == MPTSAS_RESET_FAIL) { 13199 mptsas_log(mpt, CE_WARN, "hard reset failed!"); 13200 goto fail; 13201 } 13202 13203 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) { 13204 goto mur; 13205 } 13206 /* 13207 * Setup configuration space 13208 */ 13209 if (mptsas_config_space_init(mpt) == FALSE) { 13210 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init " 13211 "failed!"); 13212 goto fail; 13213 } 13214 13215 /* 13216 * IOC facts can change after a diag reset so all buffers that are 13217 * based on these numbers must be de-allocated and re-allocated. Get 13218 * new IOC facts each time chip is initialized. 13219 */ 13220 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) { 13221 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed"); 13222 goto fail; 13223 } 13224 13225 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) { 13226 goto fail; 13227 } 13228 /* 13229 * Allocate request message frames, reply free queue, reply descriptor 13230 * post queue, and reply message frames using latest IOC facts. 13231 */ 13232 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) { 13233 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed"); 13234 goto fail; 13235 } 13236 if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) { 13237 mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed"); 13238 goto fail; 13239 } 13240 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) { 13241 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!"); 13242 goto fail; 13243 } 13244 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) { 13245 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!"); 13246 goto fail; 13247 } 13248 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) { 13249 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!"); 13250 goto fail; 13251 } 13252 13253 mur: 13254 /* 13255 * Re-Initialize ioc to operational state 13256 */ 13257 if (mptsas_ioc_init(mpt) == DDI_FAILURE) { 13258 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed"); 13259 goto fail; 13260 } 13261 13262 mptsas_alloc_reply_args(mpt); 13263 13264 /* 13265 * Initialize reply post index. Reply free index is initialized after 13266 * the next loop. 13267 */ 13268 mpt->m_post_index = 0; 13269 13270 /* 13271 * Initialize the Reply Free Queue with the physical addresses of our 13272 * reply frames. 13273 */ 13274 cookie.dmac_address = mpt->m_reply_frame_dma_addr & 0xffffffffu; 13275 for (i = 0; i < mpt->m_max_replies; i++) { 13276 ddi_put32(mpt->m_acc_free_queue_hdl, 13277 &((uint32_t *)(void *)mpt->m_free_queue)[i], 13278 cookie.dmac_address); 13279 cookie.dmac_address += mpt->m_reply_frame_size; 13280 } 13281 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 13282 DDI_DMA_SYNC_FORDEV); 13283 13284 /* 13285 * Initialize the reply free index to one past the last frame on the 13286 * queue. This will signify that the queue is empty to start with. 13287 */ 13288 mpt->m_free_index = i; 13289 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i); 13290 13291 /* 13292 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's. 13293 */ 13294 for (i = 0; i < mpt->m_post_queue_depth; i++) { 13295 ddi_put64(mpt->m_acc_post_queue_hdl, 13296 &((uint64_t *)(void *)mpt->m_post_queue)[i], 13297 0xFFFFFFFFFFFFFFFF); 13298 } 13299 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 13300 DDI_DMA_SYNC_FORDEV); 13301 13302 /* 13303 * Enable ports 13304 */ 13305 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) { 13306 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed"); 13307 goto fail; 13308 } 13309 13310 /* 13311 * enable events 13312 */ 13313 if (mptsas_ioc_enable_event_notification(mpt)) { 13314 mptsas_log(mpt, CE_WARN, 13315 "mptsas_ioc_enable_event_notification failed"); 13316 goto fail; 13317 } 13318 13319 /* 13320 * We need checks in attach and these. 13321 * chip_init is called in mult. places 13322 */ 13323 13324 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 13325 DDI_SUCCESS) || 13326 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) != 13327 DDI_SUCCESS) || 13328 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 13329 DDI_SUCCESS) || 13330 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 13331 DDI_SUCCESS) || 13332 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 13333 DDI_SUCCESS) || 13334 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 13335 DDI_SUCCESS)) { 13336 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 13337 goto fail; 13338 } 13339 13340 /* Check all acc handles */ 13341 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 13342 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 13343 DDI_SUCCESS) || 13344 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) != 13345 DDI_SUCCESS) || 13346 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 13347 DDI_SUCCESS) || 13348 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 13349 DDI_SUCCESS) || 13350 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 13351 DDI_SUCCESS) || 13352 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 13353 DDI_SUCCESS) || 13354 (mptsas_check_acc_handle(mpt->m_config_handle) != 13355 DDI_SUCCESS)) { 13356 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 13357 goto fail; 13358 } 13359 13360 return (DDI_SUCCESS); 13361 13362 fail: 13363 return (DDI_FAILURE); 13364 } 13365 13366 static int 13367 mptsas_get_pci_cap(mptsas_t *mpt) 13368 { 13369 ushort_t caps_ptr, cap, cap_count; 13370 13371 if (mpt->m_config_handle == NULL) 13372 return (FALSE); 13373 /* 13374 * Check if capabilities list is supported and if so, 13375 * get initial capabilities pointer and clear bits 0,1. 13376 */ 13377 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) 13378 & PCI_STAT_CAP) { 13379 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 13380 PCI_CONF_CAP_PTR), 4); 13381 } else { 13382 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 13383 } 13384 13385 /* 13386 * Walk capabilities if supported. 13387 */ 13388 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 13389 13390 /* 13391 * Check that we haven't exceeded the maximum number of 13392 * capabilities and that the pointer is in a valid range. 13393 */ 13394 if (++cap_count > 48) { 13395 mptsas_log(mpt, CE_WARN, 13396 "too many device capabilities.\n"); 13397 break; 13398 } 13399 if (caps_ptr < 64) { 13400 mptsas_log(mpt, CE_WARN, 13401 "capabilities pointer 0x%x out of range.\n", 13402 caps_ptr); 13403 break; 13404 } 13405 13406 /* 13407 * Get next capability and check that it is valid. 13408 * For now, we only support power management. 13409 */ 13410 cap = pci_config_get8(mpt->m_config_handle, caps_ptr); 13411 switch (cap) { 13412 case PCI_CAP_ID_PM: 13413 mptsas_log(mpt, CE_NOTE, 13414 "?mptsas%d supports power management.\n", 13415 mpt->m_instance); 13416 mpt->m_options |= MPTSAS_OPT_PM; 13417 13418 /* Save PMCSR offset */ 13419 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR; 13420 break; 13421 /* 13422 * The following capabilities are valid. Any others 13423 * will cause a message to be logged. 13424 */ 13425 case PCI_CAP_ID_VPD: 13426 case PCI_CAP_ID_MSI: 13427 case PCI_CAP_ID_PCIX: 13428 case PCI_CAP_ID_PCI_E: 13429 case PCI_CAP_ID_MSI_X: 13430 break; 13431 default: 13432 mptsas_log(mpt, CE_NOTE, 13433 "?mptsas%d unrecognized capability " 13434 "0x%x.\n", mpt->m_instance, cap); 13435 break; 13436 } 13437 13438 /* 13439 * Get next capabilities pointer and clear bits 0,1. 13440 */ 13441 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 13442 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 13443 } 13444 return (TRUE); 13445 } 13446 13447 static int 13448 mptsas_init_pm(mptsas_t *mpt) 13449 { 13450 char pmc_name[16]; 13451 char *pmc[] = { 13452 NULL, 13453 "0=Off (PCI D3 State)", 13454 "3=On (PCI D0 State)", 13455 NULL 13456 }; 13457 uint16_t pmcsr_stat; 13458 13459 if (mptsas_get_pci_cap(mpt) == FALSE) { 13460 return (DDI_FAILURE); 13461 } 13462 /* 13463 * If PCI's capability does not support PM, then don't need 13464 * to registe the pm-components 13465 */ 13466 if (!(mpt->m_options & MPTSAS_OPT_PM)) 13467 return (DDI_SUCCESS); 13468 /* 13469 * If power management is supported by this chip, create 13470 * pm-components property for the power management framework 13471 */ 13472 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance); 13473 pmc[0] = pmc_name; 13474 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip, 13475 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 13476 mpt->m_options &= ~MPTSAS_OPT_PM; 13477 mptsas_log(mpt, CE_WARN, 13478 "mptsas%d: pm-component property creation failed.", 13479 mpt->m_instance); 13480 return (DDI_FAILURE); 13481 } 13482 13483 /* 13484 * Power on device. 13485 */ 13486 (void) pm_busy_component(mpt->m_dip, 0); 13487 pmcsr_stat = pci_config_get16(mpt->m_config_handle, 13488 mpt->m_pmcsr_offset); 13489 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) { 13490 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device", 13491 mpt->m_instance); 13492 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, 13493 PCI_PMCSR_D0); 13494 } 13495 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 13496 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed"); 13497 return (DDI_FAILURE); 13498 } 13499 mpt->m_power_level = PM_LEVEL_D0; 13500 /* 13501 * Set pm idle delay. 13502 */ 13503 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 13504 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT); 13505 13506 return (DDI_SUCCESS); 13507 } 13508 13509 static int 13510 mptsas_register_intrs(mptsas_t *mpt) 13511 { 13512 dev_info_t *dip; 13513 int intr_types; 13514 13515 dip = mpt->m_dip; 13516 13517 /* Get supported interrupt types */ 13518 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 13519 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types " 13520 "failed\n"); 13521 return (FALSE); 13522 } 13523 13524 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types)); 13525 13526 /* 13527 * Try MSI, but fall back to FIXED 13528 */ 13529 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) { 13530 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) { 13531 NDBG0(("Using MSI interrupt type")); 13532 mpt->m_intr_type = DDI_INTR_TYPE_MSI; 13533 return (TRUE); 13534 } 13535 } 13536 if (intr_types & DDI_INTR_TYPE_FIXED) { 13537 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) { 13538 NDBG0(("Using FIXED interrupt type")); 13539 mpt->m_intr_type = DDI_INTR_TYPE_FIXED; 13540 return (TRUE); 13541 } else { 13542 NDBG0(("FIXED interrupt registration failed")); 13543 return (FALSE); 13544 } 13545 } 13546 13547 return (FALSE); 13548 } 13549 13550 static void 13551 mptsas_unregister_intrs(mptsas_t *mpt) 13552 { 13553 mptsas_rem_intrs(mpt); 13554 } 13555 13556 /* 13557 * mptsas_add_intrs: 13558 * 13559 * Register FIXED or MSI interrupts. 13560 */ 13561 static int 13562 mptsas_add_intrs(mptsas_t *mpt, int intr_type) 13563 { 13564 dev_info_t *dip = mpt->m_dip; 13565 int avail, actual, count = 0; 13566 int i, flag, ret; 13567 13568 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type)); 13569 13570 /* Get number of interrupts */ 13571 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 13572 if ((ret != DDI_SUCCESS) || (count <= 0)) { 13573 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, " 13574 "ret %d count %d\n", ret, count); 13575 13576 return (DDI_FAILURE); 13577 } 13578 13579 /* Get number of available interrupts */ 13580 ret = ddi_intr_get_navail(dip, intr_type, &avail); 13581 if ((ret != DDI_SUCCESS) || (avail == 0)) { 13582 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, " 13583 "ret %d avail %d\n", ret, avail); 13584 13585 return (DDI_FAILURE); 13586 } 13587 13588 if (avail < count) { 13589 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, " 13590 "navail() returned %d", count, avail); 13591 } 13592 13593 /* Mpt only have one interrupt routine */ 13594 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 13595 count = 1; 13596 } 13597 13598 /* Allocate an array of interrupt handles */ 13599 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t); 13600 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP); 13601 13602 flag = DDI_INTR_ALLOC_NORMAL; 13603 13604 /* call ddi_intr_alloc() */ 13605 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0, 13606 count, &actual, flag); 13607 13608 if ((ret != DDI_SUCCESS) || (actual == 0)) { 13609 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n", 13610 ret); 13611 kmem_free(mpt->m_htable, mpt->m_intr_size); 13612 return (DDI_FAILURE); 13613 } 13614 13615 /* use interrupt count returned or abort? */ 13616 if (actual < count) { 13617 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n", 13618 count, actual); 13619 } 13620 13621 mpt->m_intr_cnt = actual; 13622 13623 /* 13624 * Get priority for first msi, assume remaining are all the same 13625 */ 13626 if ((ret = ddi_intr_get_pri(mpt->m_htable[0], 13627 &mpt->m_intr_pri)) != DDI_SUCCESS) { 13628 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret); 13629 13630 /* Free already allocated intr */ 13631 for (i = 0; i < actual; i++) { 13632 (void) ddi_intr_free(mpt->m_htable[i]); 13633 } 13634 13635 kmem_free(mpt->m_htable, mpt->m_intr_size); 13636 return (DDI_FAILURE); 13637 } 13638 13639 /* Test for high level mutex */ 13640 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) { 13641 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: " 13642 "Hi level interrupt not supported\n"); 13643 13644 /* Free already allocated intr */ 13645 for (i = 0; i < actual; i++) { 13646 (void) ddi_intr_free(mpt->m_htable[i]); 13647 } 13648 13649 kmem_free(mpt->m_htable, mpt->m_intr_size); 13650 return (DDI_FAILURE); 13651 } 13652 13653 /* Call ddi_intr_add_handler() */ 13654 for (i = 0; i < actual; i++) { 13655 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr, 13656 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 13657 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() " 13658 "failed %d\n", ret); 13659 13660 /* Free already allocated intr */ 13661 for (i = 0; i < actual; i++) { 13662 (void) ddi_intr_free(mpt->m_htable[i]); 13663 } 13664 13665 kmem_free(mpt->m_htable, mpt->m_intr_size); 13666 return (DDI_FAILURE); 13667 } 13668 } 13669 13670 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap)) 13671 != DDI_SUCCESS) { 13672 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret); 13673 13674 /* Free already allocated intr */ 13675 for (i = 0; i < actual; i++) { 13676 (void) ddi_intr_free(mpt->m_htable[i]); 13677 } 13678 13679 kmem_free(mpt->m_htable, mpt->m_intr_size); 13680 return (DDI_FAILURE); 13681 } 13682 13683 /* 13684 * Enable interrupts 13685 */ 13686 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 13687 /* Call ddi_intr_block_enable() for MSI interrupts */ 13688 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt); 13689 } else { 13690 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 13691 for (i = 0; i < mpt->m_intr_cnt; i++) { 13692 (void) ddi_intr_enable(mpt->m_htable[i]); 13693 } 13694 } 13695 return (DDI_SUCCESS); 13696 } 13697 13698 /* 13699 * mptsas_rem_intrs: 13700 * 13701 * Unregister FIXED or MSI interrupts 13702 */ 13703 static void 13704 mptsas_rem_intrs(mptsas_t *mpt) 13705 { 13706 int i; 13707 13708 NDBG6(("mptsas_rem_intrs")); 13709 13710 /* Disable all interrupts */ 13711 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 13712 /* Call ddi_intr_block_disable() */ 13713 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt); 13714 } else { 13715 for (i = 0; i < mpt->m_intr_cnt; i++) { 13716 (void) ddi_intr_disable(mpt->m_htable[i]); 13717 } 13718 } 13719 13720 /* Call ddi_intr_remove_handler() */ 13721 for (i = 0; i < mpt->m_intr_cnt; i++) { 13722 (void) ddi_intr_remove_handler(mpt->m_htable[i]); 13723 (void) ddi_intr_free(mpt->m_htable[i]); 13724 } 13725 13726 kmem_free(mpt->m_htable, mpt->m_intr_size); 13727 } 13728 13729 /* 13730 * The IO fault service error handling callback function 13731 */ 13732 /*ARGSUSED*/ 13733 static int 13734 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 13735 { 13736 /* 13737 * as the driver can always deal with an error in any dma or 13738 * access handle, we can just return the fme_status value. 13739 */ 13740 pci_ereport_post(dip, err, NULL); 13741 return (err->fme_status); 13742 } 13743 13744 /* 13745 * mptsas_fm_init - initialize fma capabilities and register with IO 13746 * fault services. 13747 */ 13748 static void 13749 mptsas_fm_init(mptsas_t *mpt) 13750 { 13751 /* 13752 * Need to change iblock to priority for new MSI intr 13753 */ 13754 ddi_iblock_cookie_t fm_ibc; 13755 13756 /* Only register with IO Fault Services if we have some capability */ 13757 if (mpt->m_fm_capabilities) { 13758 /* Adjust access and dma attributes for FMA */ 13759 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 13760 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 13761 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 13762 13763 /* 13764 * Register capabilities with IO Fault Services. 13765 * mpt->m_fm_capabilities will be updated to indicate 13766 * capabilities actually supported (not requested.) 13767 */ 13768 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc); 13769 13770 /* 13771 * Initialize pci ereport capabilities if ereport 13772 * capable (should always be.) 13773 */ 13774 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 13775 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13776 pci_ereport_setup(mpt->m_dip); 13777 } 13778 13779 /* 13780 * Register error callback if error callback capable. 13781 */ 13782 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13783 ddi_fm_handler_register(mpt->m_dip, 13784 mptsas_fm_error_cb, (void *) mpt); 13785 } 13786 } 13787 } 13788 13789 /* 13790 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO 13791 * fault services. 13792 * 13793 */ 13794 static void 13795 mptsas_fm_fini(mptsas_t *mpt) 13796 { 13797 /* Only unregister FMA capabilities if registered */ 13798 if (mpt->m_fm_capabilities) { 13799 13800 /* 13801 * Un-register error callback if error callback capable. 13802 */ 13803 13804 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13805 ddi_fm_handler_unregister(mpt->m_dip); 13806 } 13807 13808 /* 13809 * Release any resources allocated by pci_ereport_setup() 13810 */ 13811 13812 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 13813 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13814 pci_ereport_teardown(mpt->m_dip); 13815 } 13816 13817 /* Unregister from IO Fault Services */ 13818 ddi_fm_fini(mpt->m_dip); 13819 13820 /* Adjust access and dma attributes for FMA */ 13821 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 13822 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 13823 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 13824 13825 } 13826 } 13827 13828 int 13829 mptsas_check_acc_handle(ddi_acc_handle_t handle) 13830 { 13831 ddi_fm_error_t de; 13832 13833 if (handle == NULL) 13834 return (DDI_FAILURE); 13835 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0); 13836 return (de.fme_status); 13837 } 13838 13839 int 13840 mptsas_check_dma_handle(ddi_dma_handle_t handle) 13841 { 13842 ddi_fm_error_t de; 13843 13844 if (handle == NULL) 13845 return (DDI_FAILURE); 13846 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0); 13847 return (de.fme_status); 13848 } 13849 13850 void 13851 mptsas_fm_ereport(mptsas_t *mpt, char *detail) 13852 { 13853 uint64_t ena; 13854 char buf[FM_MAX_CLASS]; 13855 13856 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 13857 ena = fm_ena_generate(0, FM_ENA_FMT1); 13858 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) { 13859 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP, 13860 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 13861 } 13862 } 13863 13864 static int 13865 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 13866 uint16_t *dev_handle, mptsas_target_t **pptgt) 13867 { 13868 int rval; 13869 uint32_t dev_info; 13870 uint64_t sas_wwn; 13871 mptsas_phymask_t phymask; 13872 uint8_t physport, phynum, config, disk; 13873 uint64_t devicename; 13874 uint16_t pdev_hdl; 13875 mptsas_target_t *tmp_tgt = NULL; 13876 uint16_t bay_num, enclosure, io_flags; 13877 13878 ASSERT(*pptgt == NULL); 13879 13880 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle, 13881 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl, 13882 &bay_num, &enclosure, &io_flags); 13883 if (rval != DDI_SUCCESS) { 13884 rval = DEV_INFO_FAIL_PAGE0; 13885 return (rval); 13886 } 13887 13888 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET | 13889 MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13890 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == 0) { 13891 rval = DEV_INFO_WRONG_DEVICE_TYPE; 13892 return (rval); 13893 } 13894 13895 /* 13896 * Check if the dev handle is for a Phys Disk. If so, set return value 13897 * and exit. Don't add Phys Disks to hash. 13898 */ 13899 for (config = 0; config < mpt->m_num_raid_configs; config++) { 13900 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 13901 if (*dev_handle == mpt->m_raidconfig[config]. 13902 m_physdisk_devhdl[disk]) { 13903 rval = DEV_INFO_PHYS_DISK; 13904 return (rval); 13905 } 13906 } 13907 } 13908 13909 /* 13910 * Get SATA Device Name from SAS device page0 for 13911 * sata device, if device name doesn't exist, set mta_wwn to 13912 * 0 for direct attached SATA. For the device behind the expander 13913 * we still can use STP address assigned by expander. 13914 */ 13915 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13916 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 13917 /* alloc a temporary target to send the cmd to */ 13918 tmp_tgt = mptsas_tgt_alloc(mpt->m_tmp_targets, *dev_handle, 13919 0, dev_info, 0, 0); 13920 mutex_exit(&mpt->m_mutex); 13921 13922 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0); 13923 13924 if (devicename == -1) { 13925 mutex_enter(&mpt->m_mutex); 13926 refhash_remove(mpt->m_tmp_targets, tmp_tgt); 13927 rval = DEV_INFO_FAIL_GUID; 13928 return (rval); 13929 } 13930 13931 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) { 13932 sas_wwn = devicename; 13933 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) { 13934 sas_wwn = 0; 13935 } 13936 13937 mutex_enter(&mpt->m_mutex); 13938 refhash_remove(mpt->m_tmp_targets, tmp_tgt); 13939 } 13940 13941 phymask = mptsas_physport_to_phymask(mpt, physport); 13942 *pptgt = mptsas_tgt_alloc(mpt->m_targets, *dev_handle, sas_wwn, 13943 dev_info, phymask, phynum); 13944 if (*pptgt == NULL) { 13945 mptsas_log(mpt, CE_WARN, "Failed to allocated target" 13946 "structure!"); 13947 rval = DEV_INFO_FAIL_ALLOC; 13948 return (rval); 13949 } 13950 (*pptgt)->m_io_flags = io_flags; 13951 (*pptgt)->m_enclosure = enclosure; 13952 (*pptgt)->m_slot_num = bay_num; 13953 return (DEV_INFO_SUCCESS); 13954 } 13955 13956 uint64_t 13957 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun) 13958 { 13959 uint64_t sata_guid = 0, *pwwn = NULL; 13960 int target = ptgt->m_devhdl; 13961 uchar_t *inq83 = NULL; 13962 int inq83_len = 0xFF; 13963 uchar_t *dblk = NULL; 13964 int inq83_retry = 3; 13965 int rval = DDI_FAILURE; 13966 13967 inq83 = kmem_zalloc(inq83_len, KM_SLEEP); 13968 13969 inq83_retry: 13970 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 13971 inq83_len, NULL, 1); 13972 if (rval != DDI_SUCCESS) { 13973 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 13974 "0x83 for target:%x, lun:%x failed!", target, lun); 13975 sata_guid = -1; 13976 goto out; 13977 } 13978 /* According to SAT2, the first descriptor is logic unit name */ 13979 dblk = &inq83[4]; 13980 if ((dblk[1] & 0x30) != 0) { 13981 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated."); 13982 goto out; 13983 } 13984 pwwn = (uint64_t *)(void *)(&dblk[4]); 13985 if ((dblk[4] & 0xf0) == 0x50) { 13986 sata_guid = BE_64(*pwwn); 13987 goto out; 13988 } else if (dblk[4] == 'A') { 13989 NDBG20(("SATA drive has no NAA format GUID.")); 13990 goto out; 13991 } else { 13992 /* The data is not ready, wait and retry */ 13993 inq83_retry--; 13994 if (inq83_retry <= 0) { 13995 goto out; 13996 } 13997 NDBG20(("The GUID is not ready, retry...")); 13998 delay(1 * drv_usectohz(1000000)); 13999 goto inq83_retry; 14000 } 14001 out: 14002 kmem_free(inq83, inq83_len); 14003 return (sata_guid); 14004 } 14005 14006 static int 14007 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page, 14008 unsigned char *buf, int len, int *reallen, uchar_t evpd) 14009 { 14010 uchar_t cdb[CDB_GROUP0]; 14011 struct scsi_address ap; 14012 struct buf *data_bp = NULL; 14013 int resid = 0; 14014 int ret = DDI_FAILURE; 14015 14016 ASSERT(len <= 0xffff); 14017 14018 ap.a_target = MPTSAS_INVALID_DEVHDL; 14019 ap.a_lun = (uchar_t)(lun); 14020 ap.a_hba_tran = mpt->m_tran; 14021 14022 data_bp = scsi_alloc_consistent_buf(&ap, 14023 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL); 14024 if (data_bp == NULL) { 14025 return (ret); 14026 } 14027 bzero(cdb, CDB_GROUP0); 14028 cdb[0] = SCMD_INQUIRY; 14029 cdb[1] = evpd; 14030 cdb[2] = page; 14031 cdb[3] = (len & 0xff00) >> 8; 14032 cdb[4] = (len & 0x00ff); 14033 cdb[5] = 0; 14034 14035 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp, 14036 &resid); 14037 if (ret == DDI_SUCCESS) { 14038 if (reallen) { 14039 *reallen = len - resid; 14040 } 14041 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len); 14042 } 14043 if (data_bp) { 14044 scsi_free_consistent_buf(data_bp); 14045 } 14046 return (ret); 14047 } 14048 14049 static int 14050 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 14051 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 14052 int *resid) 14053 { 14054 struct scsi_pkt *pktp = NULL; 14055 scsi_hba_tran_t *tran_clone = NULL; 14056 mptsas_tgt_private_t *tgt_private = NULL; 14057 int ret = DDI_FAILURE; 14058 14059 /* 14060 * scsi_hba_tran_t->tran_tgt_private is used to pass the address 14061 * information to scsi_init_pkt, allocate a scsi_hba_tran structure 14062 * to simulate the cmds from sd 14063 */ 14064 tran_clone = kmem_alloc( 14065 sizeof (scsi_hba_tran_t), KM_SLEEP); 14066 if (tran_clone == NULL) { 14067 goto out; 14068 } 14069 bcopy((caddr_t)mpt->m_tran, 14070 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t)); 14071 tgt_private = kmem_alloc( 14072 sizeof (mptsas_tgt_private_t), KM_SLEEP); 14073 if (tgt_private == NULL) { 14074 goto out; 14075 } 14076 tgt_private->t_lun = ap->a_lun; 14077 tgt_private->t_private = ptgt; 14078 tran_clone->tran_tgt_private = tgt_private; 14079 ap->a_hba_tran = tran_clone; 14080 14081 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL, 14082 data_bp, cdblen, sizeof (struct scsi_arq_status), 14083 0, PKT_CONSISTENT, NULL, NULL); 14084 if (pktp == NULL) { 14085 goto out; 14086 } 14087 bcopy(cdb, pktp->pkt_cdbp, cdblen); 14088 pktp->pkt_flags = FLAG_NOPARITY; 14089 if (scsi_poll(pktp) < 0) { 14090 goto out; 14091 } 14092 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) { 14093 goto out; 14094 } 14095 if (resid != NULL) { 14096 *resid = pktp->pkt_resid; 14097 } 14098 14099 ret = DDI_SUCCESS; 14100 out: 14101 if (pktp) { 14102 scsi_destroy_pkt(pktp); 14103 } 14104 if (tran_clone) { 14105 kmem_free(tran_clone, sizeof (scsi_hba_tran_t)); 14106 } 14107 if (tgt_private) { 14108 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 14109 } 14110 return (ret); 14111 } 14112 static int 14113 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun) 14114 { 14115 char *cp = NULL; 14116 char *ptr = NULL; 14117 size_t s = 0; 14118 char *wwid_str = NULL; 14119 char *lun_str = NULL; 14120 long lunnum; 14121 long phyid = -1; 14122 int rc = DDI_FAILURE; 14123 14124 ptr = name; 14125 ASSERT(ptr[0] == 'w' || ptr[0] == 'p'); 14126 ptr++; 14127 if ((cp = strchr(ptr, ',')) == NULL) { 14128 return (DDI_FAILURE); 14129 } 14130 14131 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14132 s = (uintptr_t)cp - (uintptr_t)ptr; 14133 14134 bcopy(ptr, wwid_str, s); 14135 wwid_str[s] = '\0'; 14136 14137 ptr = ++cp; 14138 14139 if ((cp = strchr(ptr, '\0')) == NULL) { 14140 goto out; 14141 } 14142 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14143 s = (uintptr_t)cp - (uintptr_t)ptr; 14144 14145 bcopy(ptr, lun_str, s); 14146 lun_str[s] = '\0'; 14147 14148 if (name[0] == 'p') { 14149 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid); 14150 } else { 14151 rc = scsi_wwnstr_to_wwn(wwid_str, wwid); 14152 } 14153 if (rc != DDI_SUCCESS) 14154 goto out; 14155 14156 if (phyid != -1) { 14157 ASSERT(phyid < MPTSAS_MAX_PHYS); 14158 *phy = (uint8_t)phyid; 14159 } 14160 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum); 14161 if (rc != 0) 14162 goto out; 14163 14164 *lun = (int)lunnum; 14165 rc = DDI_SUCCESS; 14166 out: 14167 if (wwid_str) 14168 kmem_free(wwid_str, SCSI_MAXNAMELEN); 14169 if (lun_str) 14170 kmem_free(lun_str, SCSI_MAXNAMELEN); 14171 14172 return (rc); 14173 } 14174 14175 /* 14176 * mptsas_parse_smp_name() is to parse sas wwn string 14177 * which format is "wWWN" 14178 */ 14179 static int 14180 mptsas_parse_smp_name(char *name, uint64_t *wwn) 14181 { 14182 char *ptr = name; 14183 14184 if (*ptr != 'w') { 14185 return (DDI_FAILURE); 14186 } 14187 14188 ptr++; 14189 if (scsi_wwnstr_to_wwn(ptr, wwn)) { 14190 return (DDI_FAILURE); 14191 } 14192 return (DDI_SUCCESS); 14193 } 14194 14195 static int 14196 mptsas_bus_config(dev_info_t *pdip, uint_t flag, 14197 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 14198 { 14199 int ret = NDI_FAILURE; 14200 mptsas_t *mpt; 14201 char *ptr = NULL; 14202 char *devnm = NULL; 14203 uint64_t wwid = 0; 14204 uint8_t phy = 0xFF; 14205 int lun = 0; 14206 uint_t mflags = flag; 14207 int bconfig = TRUE; 14208 14209 if (scsi_hba_iport_unit_address(pdip) == 0) { 14210 return (DDI_FAILURE); 14211 } 14212 14213 mpt = DIP2MPT(pdip); 14214 if (!mpt) { 14215 return (DDI_FAILURE); 14216 } 14217 /* 14218 * Hold the nexus across the bus_config 14219 */ 14220 ndi_devi_enter(scsi_vhci_dip); 14221 ndi_devi_enter(pdip); 14222 switch (op) { 14223 case BUS_CONFIG_ONE: 14224 /* parse wwid/target name out of name given */ 14225 if ((ptr = strchr((char *)arg, '@')) == NULL) { 14226 ret = NDI_FAILURE; 14227 break; 14228 } 14229 ptr++; 14230 if (strncmp((char *)arg, "smp", 3) == 0) { 14231 /* 14232 * This is a SMP target device 14233 */ 14234 ret = mptsas_parse_smp_name(ptr, &wwid); 14235 if (ret != DDI_SUCCESS) { 14236 ret = NDI_FAILURE; 14237 break; 14238 } 14239 ret = mptsas_config_smp(pdip, wwid, childp); 14240 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) { 14241 /* 14242 * OBP could pass down a non-canonical form 14243 * bootpath without LUN part when LUN is 0. 14244 * So driver need adjust the string. 14245 */ 14246 if (strchr(ptr, ',') == NULL) { 14247 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14248 (void) sprintf(devnm, "%s,0", (char *)arg); 14249 ptr = strchr(devnm, '@'); 14250 ptr++; 14251 } 14252 14253 /* 14254 * The device path is wWWID format and the device 14255 * is not SMP target device. 14256 */ 14257 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun); 14258 if (ret != DDI_SUCCESS) { 14259 ret = NDI_FAILURE; 14260 break; 14261 } 14262 *childp = NULL; 14263 if (ptr[0] == 'w') { 14264 ret = mptsas_config_one_addr(pdip, wwid, 14265 lun, childp); 14266 } else if (ptr[0] == 'p') { 14267 ret = mptsas_config_one_phy(pdip, phy, lun, 14268 childp); 14269 } 14270 14271 /* 14272 * If this is CD/DVD device in OBP path, the 14273 * ndi_busop_bus_config can be skipped as config one 14274 * operation is done above. 14275 */ 14276 if ((ret == NDI_SUCCESS) && (*childp != NULL) && 14277 (strcmp(ddi_node_name(*childp), "cdrom") == 0) && 14278 (strncmp((char *)arg, "disk", 4) == 0)) { 14279 bconfig = FALSE; 14280 ndi_hold_devi(*childp); 14281 } 14282 } else { 14283 ret = NDI_FAILURE; 14284 break; 14285 } 14286 14287 /* 14288 * DDI group instructed us to use this flag. 14289 */ 14290 mflags |= NDI_MDI_FALLBACK; 14291 break; 14292 case BUS_CONFIG_DRIVER: 14293 case BUS_CONFIG_ALL: 14294 mptsas_config_all(pdip); 14295 ret = NDI_SUCCESS; 14296 break; 14297 default: 14298 ret = NDI_FAILURE; 14299 break; 14300 } 14301 14302 if ((ret == NDI_SUCCESS) && bconfig) { 14303 ret = ndi_busop_bus_config(pdip, mflags, op, 14304 (devnm == NULL) ? arg : devnm, childp, 0); 14305 } 14306 14307 ndi_devi_exit(pdip); 14308 ndi_devi_exit(scsi_vhci_dip); 14309 if (devnm != NULL) 14310 kmem_free(devnm, SCSI_MAXNAMELEN); 14311 return (ret); 14312 } 14313 14314 static int 14315 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip, 14316 mptsas_target_t *ptgt) 14317 { 14318 int rval = DDI_FAILURE; 14319 struct scsi_inquiry *sd_inq = NULL; 14320 mptsas_t *mpt = DIP2MPT(pdip); 14321 14322 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 14323 14324 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq, 14325 SUN_INQSIZE, 0, (uchar_t)0); 14326 14327 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 14328 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun); 14329 } else { 14330 rval = DDI_FAILURE; 14331 } 14332 14333 kmem_free(sd_inq, SUN_INQSIZE); 14334 return (rval); 14335 } 14336 14337 static int 14338 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 14339 dev_info_t **lundip) 14340 { 14341 int rval; 14342 mptsas_t *mpt = DIP2MPT(pdip); 14343 int phymask; 14344 mptsas_target_t *ptgt = NULL; 14345 14346 /* 14347 * Get the physical port associated to the iport 14348 */ 14349 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14350 "phymask", 0); 14351 14352 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr); 14353 if (ptgt == NULL) { 14354 /* 14355 * didn't match any device by searching 14356 */ 14357 return (DDI_FAILURE); 14358 } 14359 /* 14360 * If the LUN already exists and the status is online, 14361 * we just return the pointer to dev_info_t directly. 14362 * For the mdi_pathinfo node, we'll handle it in 14363 * mptsas_create_virt_lun() 14364 * TODO should be also in mptsas_handle_dr 14365 */ 14366 14367 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun); 14368 if (*lundip != NULL) { 14369 /* 14370 * TODO Another senario is, we hotplug the same disk 14371 * on the same slot, the devhdl changed, is this 14372 * possible? 14373 * tgt_private->t_private != ptgt 14374 */ 14375 if (sasaddr != ptgt->m_addr.mta_wwn) { 14376 /* 14377 * The device has changed although the devhdl is the 14378 * same (Enclosure mapping mode, change drive on the 14379 * same slot) 14380 */ 14381 return (DDI_FAILURE); 14382 } 14383 return (DDI_SUCCESS); 14384 } 14385 14386 if (phymask == 0) { 14387 /* 14388 * Configure IR volume 14389 */ 14390 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip); 14391 return (rval); 14392 } 14393 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 14394 14395 return (rval); 14396 } 14397 14398 static int 14399 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 14400 dev_info_t **lundip) 14401 { 14402 int rval; 14403 mptsas_t *mpt = DIP2MPT(pdip); 14404 mptsas_phymask_t phymask; 14405 mptsas_target_t *ptgt = NULL; 14406 14407 /* 14408 * Get the physical port associated to the iport 14409 */ 14410 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14411 "phymask", 0); 14412 14413 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy); 14414 if (ptgt == NULL) { 14415 /* 14416 * didn't match any device by searching 14417 */ 14418 return (DDI_FAILURE); 14419 } 14420 14421 /* 14422 * If the LUN already exists and the status is online, 14423 * we just return the pointer to dev_info_t directly. 14424 * For the mdi_pathinfo node, we'll handle it in 14425 * mptsas_create_virt_lun(). 14426 */ 14427 14428 *lundip = mptsas_find_child_phy(pdip, phy); 14429 if (*lundip != NULL) { 14430 return (DDI_SUCCESS); 14431 } 14432 14433 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 14434 14435 return (rval); 14436 } 14437 14438 static int 14439 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num, 14440 uint8_t *lun_addr_type) 14441 { 14442 uint32_t lun_idx = 0; 14443 14444 ASSERT(lun_num != NULL); 14445 ASSERT(lun_addr_type != NULL); 14446 14447 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 14448 /* determine report luns addressing type */ 14449 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) { 14450 /* 14451 * Vendors in the field have been found to be concatenating 14452 * bus/target/lun to equal the complete lun value instead 14453 * of switching to flat space addressing 14454 */ 14455 /* 00b - peripheral device addressing method */ 14456 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL: 14457 /* FALLTHRU */ 14458 /* 10b - logical unit addressing method */ 14459 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT: 14460 /* FALLTHRU */ 14461 /* 01b - flat space addressing method */ 14462 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE: 14463 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */ 14464 *lun_addr_type = (buf[lun_idx] & 14465 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6; 14466 *lun_num = (buf[lun_idx] & 0x3F) << 8; 14467 *lun_num |= buf[lun_idx + 1]; 14468 return (DDI_SUCCESS); 14469 default: 14470 return (DDI_FAILURE); 14471 } 14472 } 14473 14474 static int 14475 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt) 14476 { 14477 struct buf *repluns_bp = NULL; 14478 struct scsi_address ap; 14479 uchar_t cdb[CDB_GROUP5]; 14480 int ret = DDI_FAILURE; 14481 int retry = 0; 14482 int lun_list_len = 0; 14483 uint16_t lun_num = 0; 14484 uint8_t lun_addr_type = 0; 14485 uint32_t lun_cnt = 0; 14486 uint32_t lun_total = 0; 14487 dev_info_t *cdip = NULL; 14488 uint16_t *saved_repluns = NULL; 14489 char *buffer = NULL; 14490 int buf_len = 128; 14491 mptsas_t *mpt = DIP2MPT(pdip); 14492 uint64_t sas_wwn = 0; 14493 uint8_t phy = 0xFF; 14494 uint32_t dev_info = 0; 14495 14496 mutex_enter(&mpt->m_mutex); 14497 sas_wwn = ptgt->m_addr.mta_wwn; 14498 phy = ptgt->m_phynum; 14499 dev_info = ptgt->m_deviceinfo; 14500 mutex_exit(&mpt->m_mutex); 14501 14502 if (sas_wwn == 0) { 14503 /* 14504 * It's a SATA without Device Name 14505 * So don't try multi-LUNs 14506 */ 14507 if (mptsas_find_child_phy(pdip, phy)) { 14508 return (DDI_SUCCESS); 14509 } else { 14510 /* 14511 * need configure and create node 14512 */ 14513 return (DDI_FAILURE); 14514 } 14515 } 14516 14517 /* 14518 * WWN (SAS address or Device Name exist) 14519 */ 14520 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 14521 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 14522 /* 14523 * SATA device with Device Name 14524 * So don't try multi-LUNs 14525 */ 14526 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) { 14527 return (DDI_SUCCESS); 14528 } else { 14529 return (DDI_FAILURE); 14530 } 14531 } 14532 14533 do { 14534 ap.a_target = MPTSAS_INVALID_DEVHDL; 14535 ap.a_lun = 0; 14536 ap.a_hba_tran = mpt->m_tran; 14537 repluns_bp = scsi_alloc_consistent_buf(&ap, 14538 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL); 14539 if (repluns_bp == NULL) { 14540 retry++; 14541 continue; 14542 } 14543 bzero(cdb, CDB_GROUP5); 14544 cdb[0] = SCMD_REPORT_LUNS; 14545 cdb[6] = (buf_len & 0xff000000) >> 24; 14546 cdb[7] = (buf_len & 0x00ff0000) >> 16; 14547 cdb[8] = (buf_len & 0x0000ff00) >> 8; 14548 cdb[9] = (buf_len & 0x000000ff); 14549 14550 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5, 14551 repluns_bp, NULL); 14552 if (ret != DDI_SUCCESS) { 14553 scsi_free_consistent_buf(repluns_bp); 14554 retry++; 14555 continue; 14556 } 14557 lun_list_len = BE_32(*(int *)((void *)( 14558 repluns_bp->b_un.b_addr))); 14559 if (buf_len >= lun_list_len + 8) { 14560 ret = DDI_SUCCESS; 14561 break; 14562 } 14563 scsi_free_consistent_buf(repluns_bp); 14564 buf_len = lun_list_len + 8; 14565 14566 } while (retry < 3); 14567 14568 if (ret != DDI_SUCCESS) 14569 return (ret); 14570 buffer = (char *)repluns_bp->b_un.b_addr; 14571 /* 14572 * find out the number of luns returned by the SCSI ReportLun call 14573 * and allocate buffer space 14574 */ 14575 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 14576 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP); 14577 if (saved_repluns == NULL) { 14578 scsi_free_consistent_buf(repluns_bp); 14579 return (DDI_FAILURE); 14580 } 14581 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) { 14582 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer), 14583 &lun_num, &lun_addr_type) != DDI_SUCCESS) { 14584 continue; 14585 } 14586 saved_repluns[lun_cnt] = lun_num; 14587 if ((cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) != 14588 NULL) { 14589 ret = DDI_SUCCESS; 14590 } else { 14591 ret = mptsas_probe_lun(pdip, lun_num, &cdip, 14592 ptgt); 14593 } 14594 if ((ret == DDI_SUCCESS) && (cdip != NULL)) { 14595 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip, 14596 MPTSAS_DEV_GONE); 14597 } 14598 } 14599 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt); 14600 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total); 14601 scsi_free_consistent_buf(repluns_bp); 14602 return (DDI_SUCCESS); 14603 } 14604 14605 static int 14606 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip) 14607 { 14608 int rval = DDI_FAILURE; 14609 struct scsi_inquiry *sd_inq = NULL; 14610 mptsas_t *mpt = DIP2MPT(pdip); 14611 mptsas_target_t *ptgt = NULL; 14612 14613 mutex_enter(&mpt->m_mutex); 14614 ptgt = refhash_linear_search(mpt->m_targets, 14615 mptsas_target_eval_devhdl, &target); 14616 mutex_exit(&mpt->m_mutex); 14617 if (ptgt == NULL) { 14618 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x " 14619 "not found.", target); 14620 return (rval); 14621 } 14622 14623 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 14624 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq, 14625 SUN_INQSIZE, 0, (uchar_t)0); 14626 14627 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 14628 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt, 14629 0); 14630 } else { 14631 rval = DDI_FAILURE; 14632 } 14633 14634 kmem_free(sd_inq, SUN_INQSIZE); 14635 return (rval); 14636 } 14637 14638 /* 14639 * configure all RAID volumes for virtual iport 14640 */ 14641 static void 14642 mptsas_config_all_viport(dev_info_t *pdip) 14643 { 14644 mptsas_t *mpt = DIP2MPT(pdip); 14645 int config, vol; 14646 int target; 14647 dev_info_t *lundip = NULL; 14648 14649 /* 14650 * Get latest RAID info and search for any Volume DevHandles. If any 14651 * are found, configure the volume. 14652 */ 14653 mutex_enter(&mpt->m_mutex); 14654 for (config = 0; config < mpt->m_num_raid_configs; config++) { 14655 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 14656 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid 14657 == 1) { 14658 target = mpt->m_raidconfig[config]. 14659 m_raidvol[vol].m_raidhandle; 14660 mutex_exit(&mpt->m_mutex); 14661 (void) mptsas_config_raid(pdip, target, 14662 &lundip); 14663 mutex_enter(&mpt->m_mutex); 14664 } 14665 } 14666 } 14667 mutex_exit(&mpt->m_mutex); 14668 } 14669 14670 static void 14671 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns, 14672 int lun_cnt, mptsas_target_t *ptgt) 14673 { 14674 dev_info_t *child = NULL, *savechild = NULL; 14675 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 14676 uint64_t sas_wwn, wwid; 14677 uint8_t phy; 14678 int lun; 14679 int i; 14680 int find; 14681 char *addr; 14682 char *nodename; 14683 mptsas_t *mpt = DIP2MPT(pdip); 14684 14685 mutex_enter(&mpt->m_mutex); 14686 wwid = ptgt->m_addr.mta_wwn; 14687 mutex_exit(&mpt->m_mutex); 14688 14689 child = ddi_get_child(pdip); 14690 while (child) { 14691 find = 0; 14692 savechild = child; 14693 child = ddi_get_next_sibling(child); 14694 14695 nodename = ddi_node_name(savechild); 14696 if (strcmp(nodename, "smp") == 0) { 14697 continue; 14698 } 14699 14700 addr = ddi_get_name_addr(savechild); 14701 if (addr == NULL) { 14702 continue; 14703 } 14704 14705 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) != 14706 DDI_SUCCESS) { 14707 continue; 14708 } 14709 14710 if (wwid == sas_wwn) { 14711 for (i = 0; i < lun_cnt; i++) { 14712 if (repluns[i] == lun) { 14713 find = 1; 14714 break; 14715 } 14716 } 14717 } else { 14718 continue; 14719 } 14720 if (find == 0) { 14721 /* 14722 * The lun has not been there already 14723 */ 14724 (void) mptsas_offline_lun(pdip, savechild, NULL, 14725 NDI_DEVI_REMOVE); 14726 } 14727 } 14728 14729 pip = mdi_get_next_client_path(pdip, NULL); 14730 while (pip) { 14731 find = 0; 14732 savepip = pip; 14733 addr = MDI_PI(pip)->pi_addr; 14734 14735 pip = mdi_get_next_client_path(pdip, pip); 14736 14737 if (addr == NULL) { 14738 continue; 14739 } 14740 14741 if (mptsas_parse_address(addr, &sas_wwn, &phy, 14742 &lun) != DDI_SUCCESS) { 14743 continue; 14744 } 14745 14746 if (sas_wwn == wwid) { 14747 for (i = 0; i < lun_cnt; i++) { 14748 if (repluns[i] == lun) { 14749 find = 1; 14750 break; 14751 } 14752 } 14753 } else { 14754 continue; 14755 } 14756 14757 if (find == 0) { 14758 /* 14759 * The lun has not been there already 14760 */ 14761 (void) mptsas_offline_lun(pdip, NULL, savepip, 14762 NDI_DEVI_REMOVE); 14763 } 14764 } 14765 } 14766 14767 /* 14768 * If this enclosure doesn't exist in the enclosure list, add it. If it does, 14769 * update it. 14770 */ 14771 static void 14772 mptsas_enclosure_update(mptsas_t *mpt, mptsas_enclosure_t *mep) 14773 { 14774 mptsas_enclosure_t *m; 14775 14776 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 14777 m = mptsas_enc_lookup(mpt, mep->me_enchdl); 14778 if (m != NULL) { 14779 uint8_t *ledp; 14780 m->me_flags = mep->me_flags; 14781 14782 14783 /* 14784 * If the number of slots and the first slot entry in the 14785 * enclosure has not changed, then we don't need to do anything 14786 * here. Otherwise, we need to allocate a new array for the LED 14787 * status of the slot. 14788 */ 14789 if (m->me_fslot == mep->me_fslot && 14790 m->me_nslots == mep->me_nslots) 14791 return; 14792 14793 /* 14794 * If the number of slots or the first slot has changed, it's 14795 * not clear that we're really in a place that we can continue 14796 * to honor the existing flags. 14797 */ 14798 if (mep->me_nslots > 0) { 14799 ledp = kmem_zalloc(sizeof (uint8_t) * mep->me_nslots, 14800 KM_SLEEP); 14801 } else { 14802 ledp = NULL; 14803 } 14804 14805 if (m->me_slotleds != NULL) { 14806 kmem_free(m->me_slotleds, sizeof (uint8_t) * 14807 m->me_nslots); 14808 } 14809 m->me_slotleds = ledp; 14810 m->me_fslot = mep->me_fslot; 14811 m->me_nslots = mep->me_nslots; 14812 return; 14813 } 14814 14815 m = kmem_zalloc(sizeof (*m), KM_SLEEP); 14816 m->me_enchdl = mep->me_enchdl; 14817 m->me_flags = mep->me_flags; 14818 m->me_nslots = mep->me_nslots; 14819 m->me_fslot = mep->me_fslot; 14820 if (m->me_nslots > 0) { 14821 m->me_slotleds = kmem_zalloc(sizeof (uint8_t) * mep->me_nslots, 14822 KM_SLEEP); 14823 /* 14824 * It may make sense to optionally flush all of the slots and/or 14825 * read the slot status flag here to synchronize between 14826 * ourselves and the card. So far, that hasn't been needed 14827 * annecdotally when enumerating something new. If we do, we 14828 * should kick that off in a taskq potentially. 14829 */ 14830 } 14831 list_insert_tail(&mpt->m_enclosures, m); 14832 } 14833 14834 static void 14835 mptsas_update_hashtab(struct mptsas *mpt) 14836 { 14837 uint32_t page_address; 14838 int rval = 0; 14839 uint16_t dev_handle; 14840 mptsas_target_t *ptgt = NULL; 14841 mptsas_smp_t smp_node; 14842 14843 /* 14844 * Get latest RAID info. 14845 */ 14846 (void) mptsas_get_raid_info(mpt); 14847 14848 dev_handle = mpt->m_smp_devhdl; 14849 while (mpt->m_done_traverse_smp == 0) { 14850 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 14851 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle; 14852 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node) 14853 != DDI_SUCCESS) { 14854 break; 14855 } 14856 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl; 14857 (void) mptsas_smp_alloc(mpt, &smp_node); 14858 } 14859 14860 /* 14861 * Loop over enclosures so we can understand what's there. 14862 */ 14863 dev_handle = MPTSAS_INVALID_DEVHDL; 14864 while (mpt->m_done_traverse_enc == 0) { 14865 mptsas_enclosure_t me; 14866 14867 page_address = (MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE & 14868 MPI2_SAS_ENCLOS_PGAD_FORM_MASK) | (uint32_t)dev_handle; 14869 14870 if (mptsas_get_enclosure_page0(mpt, page_address, &me) != 14871 DDI_SUCCESS) { 14872 break; 14873 } 14874 dev_handle = me.me_enchdl; 14875 mptsas_enclosure_update(mpt, &me); 14876 } 14877 14878 /* 14879 * Config target devices 14880 */ 14881 dev_handle = mpt->m_dev_handle; 14882 14883 /* 14884 * Loop to get sas device page 0 by GetNextHandle till the 14885 * the last handle. If the sas device is a SATA/SSP target, 14886 * we try to config it. 14887 */ 14888 while (mpt->m_done_traverse_dev == 0) { 14889 ptgt = NULL; 14890 page_address = 14891 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 14892 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14893 (uint32_t)dev_handle; 14894 rval = mptsas_get_target_device_info(mpt, page_address, 14895 &dev_handle, &ptgt); 14896 if ((rval == DEV_INFO_FAIL_PAGE0) || 14897 (rval == DEV_INFO_FAIL_ALLOC)) { 14898 break; 14899 } 14900 if (rval == DEV_INFO_FAIL_GUID) { 14901 continue; 14902 } 14903 14904 mpt->m_dev_handle = dev_handle; 14905 } 14906 14907 } 14908 14909 void 14910 mptsas_update_driver_data(struct mptsas *mpt) 14911 { 14912 mptsas_target_t *tp; 14913 mptsas_smp_t *sp; 14914 14915 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 14916 14917 /* 14918 * TODO after hard reset, update the driver data structures 14919 * 1. update port/phymask mapping table mpt->m_phy_info 14920 * 2. invalid all the entries in hash table 14921 * m_devhdl = 0xffff and m_deviceinfo = 0 14922 * 3. call sas_device_page/expander_page to update hash table 14923 */ 14924 mptsas_update_phymask(mpt); 14925 14926 /* 14927 * Remove all the devhdls for existing entries but leave their 14928 * addresses alone. In update_hashtab() below, we'll find all 14929 * targets that are still present and reassociate them with 14930 * their potentially new devhdls. Leaving the targets around in 14931 * this fashion allows them to be used on the tx waitq even 14932 * while IOC reset is occurring. 14933 */ 14934 for (tp = refhash_first(mpt->m_targets); tp != NULL; 14935 tp = refhash_next(mpt->m_targets, tp)) { 14936 tp->m_devhdl = MPTSAS_INVALID_DEVHDL; 14937 tp->m_deviceinfo = 0; 14938 tp->m_dr_flag = MPTSAS_DR_INACTIVE; 14939 } 14940 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 14941 sp = refhash_next(mpt->m_smp_targets, sp)) { 14942 sp->m_devhdl = MPTSAS_INVALID_DEVHDL; 14943 sp->m_deviceinfo = 0; 14944 } 14945 mpt->m_done_traverse_dev = 0; 14946 mpt->m_done_traverse_smp = 0; 14947 mpt->m_done_traverse_enc = 0; 14948 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL; 14949 mptsas_update_hashtab(mpt); 14950 } 14951 14952 static void 14953 mptsas_config_all(dev_info_t *pdip) 14954 { 14955 dev_info_t *smpdip = NULL; 14956 mptsas_t *mpt = DIP2MPT(pdip); 14957 int phymask = 0; 14958 mptsas_phymask_t phy_mask; 14959 mptsas_target_t *ptgt = NULL; 14960 mptsas_smp_t *psmp; 14961 14962 /* 14963 * Get the phymask associated to the iport 14964 */ 14965 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14966 "phymask", 0); 14967 14968 /* 14969 * Enumerate RAID volumes here (phymask == 0). 14970 */ 14971 if (phymask == 0) { 14972 mptsas_config_all_viport(pdip); 14973 return; 14974 } 14975 14976 mutex_enter(&mpt->m_mutex); 14977 14978 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp || 14979 !mpt->m_done_traverse_enc) { 14980 mptsas_update_hashtab(mpt); 14981 } 14982 14983 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL; 14984 psmp = refhash_next(mpt->m_smp_targets, psmp)) { 14985 phy_mask = psmp->m_addr.mta_phymask; 14986 if (phy_mask == phymask) { 14987 smpdip = NULL; 14988 mutex_exit(&mpt->m_mutex); 14989 (void) mptsas_online_smp(pdip, psmp, &smpdip); 14990 mutex_enter(&mpt->m_mutex); 14991 } 14992 } 14993 14994 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 14995 ptgt = refhash_next(mpt->m_targets, ptgt)) { 14996 phy_mask = ptgt->m_addr.mta_phymask; 14997 if (phy_mask == phymask) { 14998 mutex_exit(&mpt->m_mutex); 14999 (void) mptsas_config_target(pdip, ptgt); 15000 mutex_enter(&mpt->m_mutex); 15001 } 15002 } 15003 mutex_exit(&mpt->m_mutex); 15004 } 15005 15006 static int 15007 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt) 15008 { 15009 int rval = DDI_FAILURE; 15010 dev_info_t *tdip; 15011 15012 rval = mptsas_config_luns(pdip, ptgt); 15013 if (rval != DDI_SUCCESS) { 15014 /* 15015 * The return value means the SCMD_REPORT_LUNS 15016 * did not execute successfully. The target maybe 15017 * doesn't support such command. 15018 */ 15019 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt); 15020 } 15021 return (rval); 15022 } 15023 15024 /* 15025 * Return fail if not all the childs/paths are freed. 15026 * if there is any path under the HBA, the return value will be always fail 15027 * because we didn't call mdi_pi_free for path 15028 */ 15029 static int 15030 mptsas_offline_target(dev_info_t *pdip, char *name) 15031 { 15032 dev_info_t *child = NULL, *prechild = NULL; 15033 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 15034 int tmp_rval, rval = DDI_SUCCESS; 15035 char *addr, *cp; 15036 size_t s; 15037 mptsas_t *mpt = DIP2MPT(pdip); 15038 15039 child = ddi_get_child(pdip); 15040 while (child) { 15041 addr = ddi_get_name_addr(child); 15042 prechild = child; 15043 child = ddi_get_next_sibling(child); 15044 15045 if (addr == NULL) { 15046 continue; 15047 } 15048 if ((cp = strchr(addr, ',')) == NULL) { 15049 continue; 15050 } 15051 15052 s = (uintptr_t)cp - (uintptr_t)addr; 15053 15054 if (strncmp(addr, name, s) != 0) { 15055 continue; 15056 } 15057 15058 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL, 15059 NDI_DEVI_REMOVE); 15060 if (tmp_rval != DDI_SUCCESS) { 15061 rval = DDI_FAILURE; 15062 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 15063 prechild, MPTSAS_DEV_GONE) != 15064 DDI_PROP_SUCCESS) { 15065 mptsas_log(mpt, CE_WARN, "mptsas driver " 15066 "unable to create property for " 15067 "SAS %s (MPTSAS_DEV_GONE)", addr); 15068 } 15069 } 15070 } 15071 15072 pip = mdi_get_next_client_path(pdip, NULL); 15073 while (pip) { 15074 addr = MDI_PI(pip)->pi_addr; 15075 savepip = pip; 15076 pip = mdi_get_next_client_path(pdip, pip); 15077 if (addr == NULL) { 15078 continue; 15079 } 15080 15081 if ((cp = strchr(addr, ',')) == NULL) { 15082 continue; 15083 } 15084 15085 s = (uintptr_t)cp - (uintptr_t)addr; 15086 15087 if (strncmp(addr, name, s) != 0) { 15088 continue; 15089 } 15090 15091 (void) mptsas_offline_lun(pdip, NULL, savepip, 15092 NDI_DEVI_REMOVE); 15093 /* 15094 * driver will not invoke mdi_pi_free, so path will not 15095 * be freed forever, return DDI_FAILURE. 15096 */ 15097 rval = DDI_FAILURE; 15098 } 15099 return (rval); 15100 } 15101 15102 static int 15103 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 15104 mdi_pathinfo_t *rpip, uint_t flags) 15105 { 15106 int rval = DDI_FAILURE; 15107 char *devname; 15108 dev_info_t *cdip, *parent; 15109 15110 if (rpip != NULL) { 15111 parent = scsi_vhci_dip; 15112 cdip = mdi_pi_get_client(rpip); 15113 } else if (rdip != NULL) { 15114 parent = pdip; 15115 cdip = rdip; 15116 } else { 15117 return (DDI_FAILURE); 15118 } 15119 15120 /* 15121 * Make sure node is attached otherwise 15122 * it won't have related cache nodes to 15123 * clean up. i_ddi_devi_attached is 15124 * similiar to i_ddi_node_state(cdip) >= 15125 * DS_ATTACHED. 15126 */ 15127 if (i_ddi_devi_attached(cdip)) { 15128 15129 /* Get full devname */ 15130 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 15131 (void) ddi_deviname(cdip, devname); 15132 /* Clean cache */ 15133 (void) devfs_clean(parent, devname + 1, 15134 DV_CLEAN_FORCE); 15135 kmem_free(devname, MAXNAMELEN + 1); 15136 } 15137 if (rpip != NULL) { 15138 if (MDI_PI_IS_OFFLINE(rpip)) { 15139 rval = DDI_SUCCESS; 15140 } else { 15141 rval = mdi_pi_offline(rpip, 0); 15142 } 15143 } else { 15144 rval = ndi_devi_offline(cdip, flags); 15145 } 15146 15147 return (rval); 15148 } 15149 15150 static dev_info_t * 15151 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn) 15152 { 15153 dev_info_t *child = NULL; 15154 char *smp_wwn = NULL; 15155 15156 child = ddi_get_child(parent); 15157 while (child) { 15158 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child, 15159 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn) 15160 != DDI_SUCCESS) { 15161 child = ddi_get_next_sibling(child); 15162 continue; 15163 } 15164 15165 if (strcmp(smp_wwn, str_wwn) == 0) { 15166 ddi_prop_free(smp_wwn); 15167 break; 15168 } 15169 child = ddi_get_next_sibling(child); 15170 ddi_prop_free(smp_wwn); 15171 } 15172 return (child); 15173 } 15174 15175 static int 15176 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags) 15177 { 15178 int rval = DDI_FAILURE; 15179 char *devname; 15180 char wwn_str[MPTSAS_WWN_STRLEN]; 15181 dev_info_t *cdip; 15182 15183 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 15184 15185 cdip = mptsas_find_smp_child(pdip, wwn_str); 15186 15187 if (cdip == NULL) 15188 return (DDI_SUCCESS); 15189 15190 /* 15191 * Make sure node is attached otherwise 15192 * it won't have related cache nodes to 15193 * clean up. i_ddi_devi_attached is 15194 * similiar to i_ddi_node_state(cdip) >= 15195 * DS_ATTACHED. 15196 */ 15197 if (i_ddi_devi_attached(cdip)) { 15198 15199 /* Get full devname */ 15200 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 15201 (void) ddi_deviname(cdip, devname); 15202 /* Clean cache */ 15203 (void) devfs_clean(pdip, devname + 1, 15204 DV_CLEAN_FORCE); 15205 kmem_free(devname, MAXNAMELEN + 1); 15206 } 15207 15208 rval = ndi_devi_offline(cdip, flags); 15209 15210 return (rval); 15211 } 15212 15213 static dev_info_t * 15214 mptsas_find_child(dev_info_t *pdip, char *name) 15215 { 15216 dev_info_t *child = NULL; 15217 char *rname = NULL; 15218 int rval = DDI_FAILURE; 15219 15220 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15221 15222 child = ddi_get_child(pdip); 15223 while (child) { 15224 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN); 15225 if (rval != DDI_SUCCESS) { 15226 child = ddi_get_next_sibling(child); 15227 bzero(rname, SCSI_MAXNAMELEN); 15228 continue; 15229 } 15230 15231 if (strcmp(rname, name) == 0) { 15232 break; 15233 } 15234 child = ddi_get_next_sibling(child); 15235 bzero(rname, SCSI_MAXNAMELEN); 15236 } 15237 15238 kmem_free(rname, SCSI_MAXNAMELEN); 15239 15240 return (child); 15241 } 15242 15243 15244 static dev_info_t * 15245 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun) 15246 { 15247 dev_info_t *child = NULL; 15248 char *name = NULL; 15249 char *addr = NULL; 15250 15251 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15252 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15253 (void) sprintf(name, "%016"PRIx64, sasaddr); 15254 (void) sprintf(addr, "w%s,%x", name, lun); 15255 child = mptsas_find_child(pdip, addr); 15256 kmem_free(name, SCSI_MAXNAMELEN); 15257 kmem_free(addr, SCSI_MAXNAMELEN); 15258 return (child); 15259 } 15260 15261 static dev_info_t * 15262 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy) 15263 { 15264 dev_info_t *child; 15265 char *addr; 15266 15267 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15268 (void) sprintf(addr, "p%x,0", phy); 15269 child = mptsas_find_child(pdip, addr); 15270 kmem_free(addr, SCSI_MAXNAMELEN); 15271 return (child); 15272 } 15273 15274 static mdi_pathinfo_t * 15275 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy) 15276 { 15277 mdi_pathinfo_t *path; 15278 char *addr = NULL; 15279 15280 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15281 (void) sprintf(addr, "p%x,0", phy); 15282 path = mdi_pi_find(pdip, NULL, addr); 15283 kmem_free(addr, SCSI_MAXNAMELEN); 15284 return (path); 15285 } 15286 15287 static mdi_pathinfo_t * 15288 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun) 15289 { 15290 mdi_pathinfo_t *path; 15291 char *name = NULL; 15292 char *addr = NULL; 15293 15294 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15295 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15296 (void) sprintf(name, "%016"PRIx64, sasaddr); 15297 (void) sprintf(addr, "w%s,%x", name, lun); 15298 path = mdi_pi_find(parent, NULL, addr); 15299 kmem_free(name, SCSI_MAXNAMELEN); 15300 kmem_free(addr, SCSI_MAXNAMELEN); 15301 15302 return (path); 15303 } 15304 15305 static int 15306 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 15307 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 15308 { 15309 int i = 0; 15310 uchar_t *inq83 = NULL; 15311 int inq83_len1 = 0xFF; 15312 int inq83_len = 0; 15313 int rval = DDI_FAILURE; 15314 ddi_devid_t devid; 15315 char *guid = NULL; 15316 int target = ptgt->m_devhdl; 15317 mdi_pathinfo_t *pip = NULL; 15318 mptsas_t *mpt = DIP2MPT(pdip); 15319 15320 /* 15321 * For DVD/CD ROM and tape devices and optical 15322 * devices, we won't try to enumerate them under 15323 * scsi_vhci, so no need to try page83 15324 */ 15325 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT || 15326 sd_inq->inq_dtype == DTYPE_OPTICAL || 15327 sd_inq->inq_dtype == DTYPE_ESI)) 15328 goto create_lun; 15329 15330 /* 15331 * The LCA returns good SCSI status, but corrupt page 83 data the first 15332 * time it is queried. The solution is to keep trying to request page83 15333 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in 15334 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver 15335 * give up to get VPD page at this stage and fail the enumeration. 15336 */ 15337 15338 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP); 15339 15340 for (i = 0; i < mptsas_inq83_retry_timeout; i++) { 15341 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 15342 inq83_len1, &inq83_len, 1); 15343 if (rval != 0) { 15344 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 15345 "0x83 for target:%x, lun:%x failed!", target, lun); 15346 if (mptsas_physical_bind_failed_page_83 != B_FALSE) 15347 goto create_lun; 15348 goto out; 15349 } 15350 /* 15351 * create DEVID from inquiry data 15352 */ 15353 if ((rval = ddi_devid_scsi_encode( 15354 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq, 15355 sizeof (struct scsi_inquiry), NULL, 0, inq83, 15356 (size_t)inq83_len, &devid)) == DDI_SUCCESS) { 15357 /* 15358 * extract GUID from DEVID 15359 */ 15360 guid = ddi_devid_to_guid(devid); 15361 15362 /* 15363 * Do not enable MPXIO if the strlen(guid) is greater 15364 * than MPTSAS_MAX_GUID_LEN, this constrain would be 15365 * handled by framework later. 15366 */ 15367 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) { 15368 ddi_devid_free_guid(guid); 15369 guid = NULL; 15370 if (mpt->m_mpxio_enable == TRUE) { 15371 mptsas_log(mpt, CE_NOTE, "!Target:%x, " 15372 "lun:%x doesn't have a valid GUID, " 15373 "multipathing for this drive is " 15374 "not enabled", target, lun); 15375 } 15376 } 15377 15378 /* 15379 * devid no longer needed 15380 */ 15381 ddi_devid_free(devid); 15382 break; 15383 } else if (rval == DDI_NOT_WELL_FORMED) { 15384 /* 15385 * return value of ddi_devid_scsi_encode equal to 15386 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth 15387 * to retry inquiry page 0x83 and get GUID. 15388 */ 15389 NDBG20(("Not well formed devid, retry...")); 15390 delay(1 * drv_usectohz(1000000)); 15391 continue; 15392 } else { 15393 mptsas_log(mpt, CE_WARN, "!Encode devid failed for " 15394 "path target:%x, lun:%x", target, lun); 15395 rval = DDI_FAILURE; 15396 goto create_lun; 15397 } 15398 } 15399 15400 if (i == mptsas_inq83_retry_timeout) { 15401 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout " 15402 "for path target:%x, lun:%x", target, lun); 15403 } 15404 15405 rval = DDI_FAILURE; 15406 15407 create_lun: 15408 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) { 15409 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip, 15410 ptgt, lun); 15411 } 15412 if (rval != DDI_SUCCESS) { 15413 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip, 15414 ptgt, lun); 15415 15416 } 15417 out: 15418 if (guid != NULL) { 15419 /* 15420 * guid no longer needed 15421 */ 15422 ddi_devid_free_guid(guid); 15423 } 15424 if (inq83 != NULL) 15425 kmem_free(inq83, inq83_len1); 15426 return (rval); 15427 } 15428 15429 static int 15430 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid, 15431 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun) 15432 { 15433 int target; 15434 char *nodename = NULL; 15435 char **compatible = NULL; 15436 int ncompatible = 0; 15437 int mdi_rtn = MDI_FAILURE; 15438 int rval = DDI_FAILURE; 15439 char *old_guid = NULL; 15440 mptsas_t *mpt = DIP2MPT(pdip); 15441 char *lun_addr = NULL; 15442 char *wwn_str = NULL; 15443 char *attached_wwn_str = NULL; 15444 char *component = NULL; 15445 uint8_t phy = 0xFF; 15446 uint64_t sas_wwn; 15447 int64_t lun64 = 0; 15448 uint32_t devinfo; 15449 uint16_t dev_hdl; 15450 uint16_t pdev_hdl; 15451 uint64_t dev_sas_wwn; 15452 uint64_t pdev_sas_wwn; 15453 uint32_t pdev_info; 15454 uint8_t physport; 15455 uint8_t phy_id; 15456 uint32_t page_address; 15457 uint16_t bay_num, enclosure, io_flags; 15458 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 15459 uint32_t dev_info; 15460 15461 mutex_enter(&mpt->m_mutex); 15462 target = ptgt->m_devhdl; 15463 sas_wwn = ptgt->m_addr.mta_wwn; 15464 devinfo = ptgt->m_deviceinfo; 15465 phy = ptgt->m_phynum; 15466 mutex_exit(&mpt->m_mutex); 15467 15468 if (sas_wwn) { 15469 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun); 15470 } else { 15471 *pip = mptsas_find_path_phy(pdip, phy); 15472 } 15473 15474 if (*pip != NULL) { 15475 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 15476 ASSERT(*lun_dip != NULL); 15477 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip, 15478 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM), 15479 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) { 15480 if (strncmp(guid, old_guid, strlen(guid)) == 0) { 15481 /* 15482 * Same path back online again. 15483 */ 15484 (void) ddi_prop_free(old_guid); 15485 if ((!MDI_PI_IS_ONLINE(*pip)) && 15486 (!MDI_PI_IS_STANDBY(*pip)) && 15487 (ptgt->m_tgt_unconfigured == 0)) { 15488 rval = mdi_pi_online(*pip, 0); 15489 } else { 15490 rval = DDI_SUCCESS; 15491 } 15492 if (rval != DDI_SUCCESS) { 15493 mptsas_log(mpt, CE_WARN, "path:target: " 15494 "%x, lun:%x online failed!", target, 15495 lun); 15496 *pip = NULL; 15497 *lun_dip = NULL; 15498 } 15499 return (rval); 15500 } else { 15501 /* 15502 * The GUID of the LUN has changed which maybe 15503 * because customer mapped another volume to the 15504 * same LUN. 15505 */ 15506 mptsas_log(mpt, CE_WARN, "The GUID of the " 15507 "target:%x, lun:%x was changed, maybe " 15508 "because someone mapped another volume " 15509 "to the same LUN", target, lun); 15510 (void) ddi_prop_free(old_guid); 15511 if (!MDI_PI_IS_OFFLINE(*pip)) { 15512 rval = mdi_pi_offline(*pip, 0); 15513 if (rval != MDI_SUCCESS) { 15514 mptsas_log(mpt, CE_WARN, "path:" 15515 "target:%x, lun:%x offline " 15516 "failed!", target, lun); 15517 *pip = NULL; 15518 *lun_dip = NULL; 15519 return (DDI_FAILURE); 15520 } 15521 } 15522 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) { 15523 mptsas_log(mpt, CE_WARN, "path:target:" 15524 "%x, lun:%x free failed!", target, 15525 lun); 15526 *pip = NULL; 15527 *lun_dip = NULL; 15528 return (DDI_FAILURE); 15529 } 15530 } 15531 } else { 15532 mptsas_log(mpt, CE_WARN, "Can't get client-guid " 15533 "property for path:target:%x, lun:%x", target, lun); 15534 *pip = NULL; 15535 *lun_dip = NULL; 15536 return (DDI_FAILURE); 15537 } 15538 } 15539 scsi_hba_nodename_compatible_get(inq, NULL, 15540 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible); 15541 15542 /* 15543 * if nodename can't be determined then print a message and skip it 15544 */ 15545 if (nodename == NULL) { 15546 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible " 15547 "driver for target%d lun %d dtype:0x%02x", target, lun, 15548 inq->inq_dtype); 15549 return (DDI_FAILURE); 15550 } 15551 15552 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 15553 /* The property is needed by MPAPI */ 15554 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 15555 15556 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15557 if (guid) { 15558 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun); 15559 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15560 } else { 15561 (void) sprintf(lun_addr, "p%x,%x", phy, lun); 15562 (void) sprintf(wwn_str, "p%x", phy); 15563 } 15564 15565 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename, 15566 guid, lun_addr, compatible, ncompatible, 15567 0, pip); 15568 if (mdi_rtn == MDI_SUCCESS) { 15569 15570 if (mdi_prop_update_string(*pip, MDI_GUID, 15571 guid) != DDI_SUCCESS) { 15572 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15573 "create prop for target %d lun %d (MDI_GUID)", 15574 target, lun); 15575 mdi_rtn = MDI_FAILURE; 15576 goto virt_create_done; 15577 } 15578 15579 if (mdi_prop_update_int(*pip, LUN_PROP, 15580 lun) != DDI_SUCCESS) { 15581 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15582 "create prop for target %d lun %d (LUN_PROP)", 15583 target, lun); 15584 mdi_rtn = MDI_FAILURE; 15585 goto virt_create_done; 15586 } 15587 lun64 = (int64_t)lun; 15588 if (mdi_prop_update_int64(*pip, LUN64_PROP, 15589 lun64) != DDI_SUCCESS) { 15590 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15591 "create prop for target %d (LUN64_PROP)", 15592 target); 15593 mdi_rtn = MDI_FAILURE; 15594 goto virt_create_done; 15595 } 15596 if (mdi_prop_update_string_array(*pip, "compatible", 15597 compatible, ncompatible) != 15598 DDI_PROP_SUCCESS) { 15599 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15600 "create prop for target %d lun %d (COMPATIBLE)", 15601 target, lun); 15602 mdi_rtn = MDI_FAILURE; 15603 goto virt_create_done; 15604 } 15605 if (sas_wwn && (mdi_prop_update_string(*pip, 15606 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) { 15607 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15608 "create prop for target %d lun %d " 15609 "(target-port)", target, lun); 15610 mdi_rtn = MDI_FAILURE; 15611 goto virt_create_done; 15612 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip, 15613 "sata-phy", phy) != DDI_PROP_SUCCESS)) { 15614 /* 15615 * Direct attached SATA device without DeviceName 15616 */ 15617 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15618 "create prop for SAS target %d lun %d " 15619 "(sata-phy)", target, lun); 15620 mdi_rtn = MDI_FAILURE; 15621 goto virt_create_done; 15622 } 15623 mutex_enter(&mpt->m_mutex); 15624 15625 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15626 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15627 (uint32_t)ptgt->m_devhdl; 15628 rval = mptsas_get_sas_device_page0(mpt, page_address, 15629 &dev_hdl, &dev_sas_wwn, &dev_info, &physport, 15630 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15631 if (rval != DDI_SUCCESS) { 15632 mutex_exit(&mpt->m_mutex); 15633 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 15634 "parent device for handle %d", page_address); 15635 mdi_rtn = MDI_FAILURE; 15636 goto virt_create_done; 15637 } 15638 15639 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15640 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 15641 rval = mptsas_get_sas_device_page0(mpt, page_address, 15642 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 15643 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15644 if (rval != DDI_SUCCESS) { 15645 mutex_exit(&mpt->m_mutex); 15646 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 15647 "device info for handle %d", page_address); 15648 mdi_rtn = MDI_FAILURE; 15649 goto virt_create_done; 15650 } 15651 15652 mutex_exit(&mpt->m_mutex); 15653 15654 /* 15655 * If this device direct attached to the controller 15656 * set the attached-port to the base wwid 15657 */ 15658 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15659 != DEVINFO_DIRECT_ATTACHED) { 15660 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15661 pdev_sas_wwn); 15662 } else { 15663 /* 15664 * Update the iport's attached-port to guid 15665 */ 15666 if (sas_wwn == 0) { 15667 (void) sprintf(wwn_str, "p%x", phy); 15668 } else { 15669 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15670 } 15671 if (ddi_prop_update_string(DDI_DEV_T_NONE, 15672 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15673 DDI_PROP_SUCCESS) { 15674 mptsas_log(mpt, CE_WARN, 15675 "mptsas unable to create " 15676 "property for iport target-port" 15677 " %s (sas_wwn)", 15678 wwn_str); 15679 mdi_rtn = MDI_FAILURE; 15680 goto virt_create_done; 15681 } 15682 15683 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15684 mpt->un.m_base_wwid); 15685 } 15686 15687 if (IS_SATA_DEVICE(ptgt->m_deviceinfo)) { 15688 char uabuf[SCSI_WWN_BUFLEN]; 15689 15690 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) { 15691 mptsas_log(mpt, CE_WARN, 15692 "mptsas unable to format SATA bridge WWN"); 15693 mdi_rtn = MDI_FAILURE; 15694 goto virt_create_done; 15695 } 15696 15697 if (mdi_prop_update_string(*pip, 15698 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != 15699 DDI_SUCCESS) { 15700 mptsas_log(mpt, CE_WARN, 15701 "mptsas unable to create SCSI bridge port " 15702 "property for SATA device"); 15703 mdi_rtn = MDI_FAILURE; 15704 goto virt_create_done; 15705 } 15706 } 15707 15708 if (mdi_prop_update_string(*pip, 15709 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 15710 DDI_PROP_SUCCESS) { 15711 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15712 "property for iport attached-port %s (sas_wwn)", 15713 attached_wwn_str); 15714 mdi_rtn = MDI_FAILURE; 15715 goto virt_create_done; 15716 } 15717 15718 15719 if (inq->inq_dtype == 0) { 15720 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 15721 /* 15722 * set obp path for pathinfo 15723 */ 15724 (void) snprintf(component, MAXPATHLEN, 15725 "disk@%s", lun_addr); 15726 15727 if (mdi_pi_pathname_obp_set(*pip, component) != 15728 DDI_SUCCESS) { 15729 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 15730 "unable to set obp-path for object %s", 15731 component); 15732 mdi_rtn = MDI_FAILURE; 15733 goto virt_create_done; 15734 } 15735 } 15736 15737 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 15738 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 15739 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 15740 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip, 15741 "pm-capable", 1)) != 15742 DDI_PROP_SUCCESS) { 15743 mptsas_log(mpt, CE_WARN, "mptsas driver" 15744 "failed to create pm-capable " 15745 "property, target %d", target); 15746 mdi_rtn = MDI_FAILURE; 15747 goto virt_create_done; 15748 } 15749 } 15750 /* 15751 * Create the phy-num property 15752 */ 15753 if (mdi_prop_update_int(*pip, "phy-num", 15754 ptgt->m_phynum) != DDI_SUCCESS) { 15755 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15756 "create phy-num property for target %d lun %d", 15757 target, lun); 15758 mdi_rtn = MDI_FAILURE; 15759 goto virt_create_done; 15760 } 15761 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr)); 15762 mdi_rtn = mdi_pi_online(*pip, 0); 15763 if (mdi_rtn == MDI_NOT_SUPPORTED) { 15764 mdi_rtn = MDI_FAILURE; 15765 } 15766 virt_create_done: 15767 if (*pip && mdi_rtn != MDI_SUCCESS) { 15768 (void) mdi_pi_free(*pip, 0); 15769 *pip = NULL; 15770 *lun_dip = NULL; 15771 } 15772 } 15773 15774 scsi_hba_nodename_compatible_free(nodename, compatible); 15775 if (lun_addr != NULL) { 15776 kmem_free(lun_addr, SCSI_MAXNAMELEN); 15777 } 15778 if (wwn_str != NULL) { 15779 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 15780 } 15781 if (component != NULL) { 15782 kmem_free(component, MAXPATHLEN); 15783 } 15784 15785 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 15786 } 15787 15788 static int 15789 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq, 15790 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 15791 { 15792 int target; 15793 int rval; 15794 int ndi_rtn = NDI_FAILURE; 15795 uint64_t be_sas_wwn; 15796 char *nodename = NULL; 15797 char **compatible = NULL; 15798 int ncompatible = 0; 15799 int instance = 0; 15800 mptsas_t *mpt = DIP2MPT(pdip); 15801 char *wwn_str = NULL; 15802 char *component = NULL; 15803 char *attached_wwn_str = NULL; 15804 uint8_t phy = 0xFF; 15805 uint64_t sas_wwn; 15806 uint32_t devinfo; 15807 uint16_t dev_hdl; 15808 uint16_t pdev_hdl; 15809 uint64_t pdev_sas_wwn; 15810 uint64_t dev_sas_wwn; 15811 uint32_t pdev_info; 15812 uint8_t physport; 15813 uint8_t phy_id; 15814 uint32_t page_address; 15815 uint16_t bay_num, enclosure, io_flags; 15816 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 15817 uint32_t dev_info; 15818 int64_t lun64 = 0; 15819 15820 mutex_enter(&mpt->m_mutex); 15821 target = ptgt->m_devhdl; 15822 sas_wwn = ptgt->m_addr.mta_wwn; 15823 devinfo = ptgt->m_deviceinfo; 15824 phy = ptgt->m_phynum; 15825 mutex_exit(&mpt->m_mutex); 15826 15827 /* 15828 * generate compatible property with binding-set "mpt" 15829 */ 15830 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL, 15831 &nodename, &compatible, &ncompatible); 15832 15833 /* 15834 * if nodename can't be determined then print a message and skip it 15835 */ 15836 if (nodename == NULL) { 15837 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver " 15838 "for target %d lun %d", target, lun); 15839 return (DDI_FAILURE); 15840 } 15841 15842 ndi_rtn = ndi_devi_alloc(pdip, nodename, 15843 DEVI_SID_NODEID, lun_dip); 15844 15845 /* 15846 * if lun alloc success, set props 15847 */ 15848 if (ndi_rtn == NDI_SUCCESS) { 15849 15850 if (ndi_prop_update_int(DDI_DEV_T_NONE, 15851 *lun_dip, LUN_PROP, lun) != 15852 DDI_PROP_SUCCESS) { 15853 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15854 "property for target %d lun %d (LUN_PROP)", 15855 target, lun); 15856 ndi_rtn = NDI_FAILURE; 15857 goto phys_create_done; 15858 } 15859 15860 lun64 = (int64_t)lun; 15861 if (ndi_prop_update_int64(DDI_DEV_T_NONE, 15862 *lun_dip, LUN64_PROP, lun64) != 15863 DDI_PROP_SUCCESS) { 15864 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15865 "property for target %d lun64 %d (LUN64_PROP)", 15866 target, lun); 15867 ndi_rtn = NDI_FAILURE; 15868 goto phys_create_done; 15869 } 15870 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, 15871 *lun_dip, "compatible", compatible, ncompatible) 15872 != DDI_PROP_SUCCESS) { 15873 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15874 "property for target %d lun %d (COMPATIBLE)", 15875 target, lun); 15876 ndi_rtn = NDI_FAILURE; 15877 goto phys_create_done; 15878 } 15879 15880 /* 15881 * We need the SAS WWN for non-multipath devices, so 15882 * we'll use the same property as that multipathing 15883 * devices need to present for MPAPI. If we don't have 15884 * a WWN (e.g. parallel SCSI), don't create the prop. 15885 */ 15886 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 15887 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15888 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE, 15889 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) 15890 != DDI_PROP_SUCCESS) { 15891 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15892 "create property for SAS target %d lun %d " 15893 "(target-port)", target, lun); 15894 ndi_rtn = NDI_FAILURE; 15895 goto phys_create_done; 15896 } 15897 15898 be_sas_wwn = BE_64(sas_wwn); 15899 if (sas_wwn && ndi_prop_update_byte_array( 15900 DDI_DEV_T_NONE, *lun_dip, "port-wwn", 15901 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) { 15902 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15903 "create property for SAS target %d lun %d " 15904 "(port-wwn)", target, lun); 15905 ndi_rtn = NDI_FAILURE; 15906 goto phys_create_done; 15907 } else if ((sas_wwn == 0) && (ndi_prop_update_int( 15908 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) != 15909 DDI_PROP_SUCCESS)) { 15910 /* 15911 * Direct attached SATA device without DeviceName 15912 */ 15913 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15914 "create property for SAS target %d lun %d " 15915 "(sata-phy)", target, lun); 15916 ndi_rtn = NDI_FAILURE; 15917 goto phys_create_done; 15918 } 15919 15920 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 15921 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) { 15922 mptsas_log(mpt, CE_WARN, "mptsas unable to" 15923 "create property for SAS target %d lun %d" 15924 " (SAS_PROP)", target, lun); 15925 ndi_rtn = NDI_FAILURE; 15926 goto phys_create_done; 15927 } 15928 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE, 15929 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) { 15930 mptsas_log(mpt, CE_WARN, "mptsas unable " 15931 "to create guid property for target %d " 15932 "lun %d", target, lun); 15933 ndi_rtn = NDI_FAILURE; 15934 goto phys_create_done; 15935 } 15936 15937 /* 15938 * The following code is to set properties for SM-HBA support, 15939 * it doesn't apply to RAID volumes 15940 */ 15941 if (ptgt->m_addr.mta_phymask == 0) 15942 goto phys_raid_lun; 15943 15944 mutex_enter(&mpt->m_mutex); 15945 15946 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15947 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15948 (uint32_t)ptgt->m_devhdl; 15949 rval = mptsas_get_sas_device_page0(mpt, page_address, 15950 &dev_hdl, &dev_sas_wwn, &dev_info, 15951 &physport, &phy_id, &pdev_hdl, 15952 &bay_num, &enclosure, &io_flags); 15953 if (rval != DDI_SUCCESS) { 15954 mutex_exit(&mpt->m_mutex); 15955 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 15956 "parent device for handle %d.", page_address); 15957 ndi_rtn = NDI_FAILURE; 15958 goto phys_create_done; 15959 } 15960 15961 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15962 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 15963 rval = mptsas_get_sas_device_page0(mpt, page_address, 15964 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 15965 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15966 if (rval != DDI_SUCCESS) { 15967 mutex_exit(&mpt->m_mutex); 15968 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15969 "device for handle %d.", page_address); 15970 ndi_rtn = NDI_FAILURE; 15971 goto phys_create_done; 15972 } 15973 15974 mutex_exit(&mpt->m_mutex); 15975 15976 /* 15977 * If this device direct attached to the controller 15978 * set the attached-port to the base wwid 15979 */ 15980 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15981 != DEVINFO_DIRECT_ATTACHED) { 15982 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15983 pdev_sas_wwn); 15984 } else { 15985 /* 15986 * Update the iport's attached-port to guid 15987 */ 15988 if (sas_wwn == 0) { 15989 (void) sprintf(wwn_str, "p%x", phy); 15990 } else { 15991 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15992 } 15993 if (ddi_prop_update_string(DDI_DEV_T_NONE, 15994 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15995 DDI_PROP_SUCCESS) { 15996 mptsas_log(mpt, CE_WARN, 15997 "mptsas unable to create " 15998 "property for iport target-port" 15999 " %s (sas_wwn)", 16000 wwn_str); 16001 ndi_rtn = NDI_FAILURE; 16002 goto phys_create_done; 16003 } 16004 16005 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 16006 mpt->un.m_base_wwid); 16007 } 16008 16009 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16010 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 16011 DDI_PROP_SUCCESS) { 16012 mptsas_log(mpt, CE_WARN, 16013 "mptsas unable to create " 16014 "property for iport attached-port %s (sas_wwn)", 16015 attached_wwn_str); 16016 ndi_rtn = NDI_FAILURE; 16017 goto phys_create_done; 16018 } 16019 16020 if (IS_SATA_DEVICE(dev_info)) { 16021 char uabuf[SCSI_WWN_BUFLEN]; 16022 16023 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16024 *lun_dip, MPTSAS_VARIANT, "sata") != 16025 DDI_PROP_SUCCESS) { 16026 mptsas_log(mpt, CE_WARN, 16027 "mptsas unable to create " 16028 "property for device variant "); 16029 ndi_rtn = NDI_FAILURE; 16030 goto phys_create_done; 16031 } 16032 16033 if (scsi_wwn_to_wwnstr(dev_sas_wwn, 1, uabuf) == NULL) { 16034 mptsas_log(mpt, CE_WARN, 16035 "mptsas unable to format SATA bridge WWN"); 16036 ndi_rtn = NDI_FAILURE; 16037 goto phys_create_done; 16038 } 16039 16040 if (ndi_prop_update_string(DDI_DEV_T_NONE, *lun_dip, 16041 SCSI_ADDR_PROP_BRIDGE_PORT, uabuf) != 16042 DDI_PROP_SUCCESS) { 16043 mptsas_log(mpt, CE_WARN, 16044 "mptsas unable to create SCSI bridge port " 16045 "property for SATA device"); 16046 ndi_rtn = NDI_FAILURE; 16047 goto phys_create_done; 16048 } 16049 } 16050 16051 if (IS_ATAPI_DEVICE(dev_info)) { 16052 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16053 *lun_dip, MPTSAS_VARIANT, "atapi") != 16054 DDI_PROP_SUCCESS) { 16055 mptsas_log(mpt, CE_WARN, 16056 "mptsas unable to create " 16057 "property for device variant "); 16058 ndi_rtn = NDI_FAILURE; 16059 goto phys_create_done; 16060 } 16061 } 16062 16063 phys_raid_lun: 16064 /* 16065 * if this is a SAS controller, and the target is a SATA 16066 * drive, set the 'pm-capable' property for sd and if on 16067 * an OPL platform, also check if this is an ATAPI 16068 * device. 16069 */ 16070 instance = ddi_get_instance(mpt->m_dip); 16071 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 16072 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 16073 NDBG2(("mptsas%d: creating pm-capable property, " 16074 "target %d", instance, target)); 16075 16076 if ((ndi_prop_update_int(DDI_DEV_T_NONE, 16077 *lun_dip, "pm-capable", 1)) != 16078 DDI_PROP_SUCCESS) { 16079 mptsas_log(mpt, CE_WARN, "mptsas " 16080 "failed to create pm-capable " 16081 "property, target %d", target); 16082 ndi_rtn = NDI_FAILURE; 16083 goto phys_create_done; 16084 } 16085 16086 } 16087 16088 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) { 16089 /* 16090 * add 'obp-path' properties for devinfo 16091 */ 16092 bzero(wwn_str, sizeof (wwn_str)); 16093 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 16094 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 16095 if (guid) { 16096 (void) snprintf(component, MAXPATHLEN, 16097 "disk@w%s,%x", wwn_str, lun); 16098 } else { 16099 (void) snprintf(component, MAXPATHLEN, 16100 "disk@p%x,%x", phy, lun); 16101 } 16102 if (ddi_pathname_obp_set(*lun_dip, component) 16103 != DDI_SUCCESS) { 16104 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 16105 "unable to set obp-path for SAS " 16106 "object %s", component); 16107 ndi_rtn = NDI_FAILURE; 16108 goto phys_create_done; 16109 } 16110 } 16111 /* 16112 * Create the phy-num property for non-raid disk 16113 */ 16114 if (ptgt->m_addr.mta_phymask != 0) { 16115 if (ndi_prop_update_int(DDI_DEV_T_NONE, 16116 *lun_dip, "phy-num", ptgt->m_phynum) != 16117 DDI_PROP_SUCCESS) { 16118 mptsas_log(mpt, CE_WARN, "mptsas driver " 16119 "failed to create phy-num property for " 16120 "target %d", target); 16121 ndi_rtn = NDI_FAILURE; 16122 goto phys_create_done; 16123 } 16124 } 16125 phys_create_done: 16126 /* 16127 * If props were setup ok, online the lun 16128 */ 16129 if (ndi_rtn == NDI_SUCCESS) { 16130 /* 16131 * Try to online the new node 16132 */ 16133 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH); 16134 } 16135 16136 /* 16137 * If success set rtn flag, else unwire alloc'd lun 16138 */ 16139 if (ndi_rtn != NDI_SUCCESS) { 16140 NDBG12(("mptsas driver unable to online " 16141 "target %d lun %d", target, lun)); 16142 ndi_prop_remove_all(*lun_dip); 16143 (void) ndi_devi_free(*lun_dip); 16144 *lun_dip = NULL; 16145 } 16146 } 16147 16148 scsi_hba_nodename_compatible_free(nodename, compatible); 16149 16150 if (wwn_str != NULL) { 16151 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 16152 } 16153 if (component != NULL) { 16154 kmem_free(component, MAXPATHLEN); 16155 } 16156 16157 16158 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 16159 } 16160 16161 static int 16162 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn) 16163 { 16164 mptsas_t *mpt = DIP2MPT(pdip); 16165 struct smp_device smp_sd; 16166 16167 /* XXX An HBA driver should not be allocating an smp_device. */ 16168 bzero(&smp_sd, sizeof (struct smp_device)); 16169 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran; 16170 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE); 16171 16172 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS) 16173 return (NDI_FAILURE); 16174 return (NDI_SUCCESS); 16175 } 16176 16177 static int 16178 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip) 16179 { 16180 mptsas_t *mpt = DIP2MPT(pdip); 16181 mptsas_smp_t *psmp = NULL; 16182 int rval; 16183 int phymask; 16184 16185 /* 16186 * Get the physical port associated to the iport 16187 * PHYMASK TODO 16188 */ 16189 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 16190 "phymask", 0); 16191 /* 16192 * Find the smp node in hash table with specified sas address and 16193 * physical port 16194 */ 16195 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn); 16196 if (psmp == NULL) { 16197 return (DDI_FAILURE); 16198 } 16199 16200 rval = mptsas_online_smp(pdip, psmp, smp_dip); 16201 16202 return (rval); 16203 } 16204 16205 static int 16206 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 16207 dev_info_t **smp_dip) 16208 { 16209 char wwn_str[MPTSAS_WWN_STRLEN]; 16210 char attached_wwn_str[MPTSAS_WWN_STRLEN]; 16211 int ndi_rtn = NDI_FAILURE; 16212 int rval = 0; 16213 mptsas_smp_t dev_info; 16214 uint32_t page_address; 16215 mptsas_t *mpt = DIP2MPT(pdip); 16216 uint16_t dev_hdl; 16217 uint64_t sas_wwn; 16218 uint64_t smp_sas_wwn; 16219 uint8_t physport; 16220 uint8_t phy_id; 16221 uint16_t pdev_hdl; 16222 uint8_t numphys = 0; 16223 uint16_t i = 0; 16224 char phymask[MPTSAS_MAX_PHYS]; 16225 char *iport = NULL; 16226 mptsas_phymask_t phy_mask = 0; 16227 uint16_t attached_devhdl; 16228 uint16_t bay_num, enclosure, io_flags; 16229 16230 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 16231 16232 /* 16233 * Probe smp device, prevent the node of removed device from being 16234 * configured succesfully 16235 */ 16236 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) { 16237 return (DDI_FAILURE); 16238 } 16239 16240 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) { 16241 return (DDI_SUCCESS); 16242 } 16243 16244 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip); 16245 16246 /* 16247 * if lun alloc success, set props 16248 */ 16249 if (ndi_rtn == NDI_SUCCESS) { 16250 /* 16251 * Set the flavor of the child to be SMP flavored 16252 */ 16253 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP); 16254 16255 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16256 *smp_dip, SMP_WWN, wwn_str) != 16257 DDI_PROP_SUCCESS) { 16258 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16259 "property for smp device %s (sas_wwn)", 16260 wwn_str); 16261 ndi_rtn = NDI_FAILURE; 16262 goto smp_create_done; 16263 } 16264 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn); 16265 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16266 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != 16267 DDI_PROP_SUCCESS) { 16268 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16269 "property for iport target-port %s (sas_wwn)", 16270 wwn_str); 16271 ndi_rtn = NDI_FAILURE; 16272 goto smp_create_done; 16273 } 16274 16275 mutex_enter(&mpt->m_mutex); 16276 16277 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 16278 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl; 16279 rval = mptsas_get_sas_expander_page0(mpt, page_address, 16280 &dev_info); 16281 if (rval != DDI_SUCCESS) { 16282 mutex_exit(&mpt->m_mutex); 16283 mptsas_log(mpt, CE_WARN, 16284 "mptsas unable to get expander " 16285 "parent device info for %x", page_address); 16286 ndi_rtn = NDI_FAILURE; 16287 goto smp_create_done; 16288 } 16289 16290 smp_node->m_pdevhdl = dev_info.m_pdevhdl; 16291 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 16292 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 16293 (uint32_t)dev_info.m_pdevhdl; 16294 rval = mptsas_get_sas_device_page0(mpt, page_address, 16295 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport, 16296 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 16297 if (rval != DDI_SUCCESS) { 16298 mutex_exit(&mpt->m_mutex); 16299 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 16300 "device info for %x", page_address); 16301 ndi_rtn = NDI_FAILURE; 16302 goto smp_create_done; 16303 } 16304 16305 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 16306 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 16307 (uint32_t)dev_info.m_devhdl; 16308 rval = mptsas_get_sas_device_page0(mpt, page_address, 16309 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo, 16310 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure, 16311 &io_flags); 16312 if (rval != DDI_SUCCESS) { 16313 mutex_exit(&mpt->m_mutex); 16314 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 16315 "device info for %x", page_address); 16316 ndi_rtn = NDI_FAILURE; 16317 goto smp_create_done; 16318 } 16319 mutex_exit(&mpt->m_mutex); 16320 16321 /* 16322 * If this smp direct attached to the controller 16323 * set the attached-port to the base wwid 16324 */ 16325 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 16326 != DEVINFO_DIRECT_ATTACHED) { 16327 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 16328 sas_wwn); 16329 } else { 16330 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 16331 mpt->un.m_base_wwid); 16332 } 16333 16334 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16335 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) != 16336 DDI_PROP_SUCCESS) { 16337 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16338 "property for smp attached-port %s (sas_wwn)", 16339 attached_wwn_str); 16340 ndi_rtn = NDI_FAILURE; 16341 goto smp_create_done; 16342 } 16343 16344 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 16345 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) { 16346 mptsas_log(mpt, CE_WARN, "mptsas unable to " 16347 "create property for SMP %s (SMP_PROP) ", 16348 wwn_str); 16349 ndi_rtn = NDI_FAILURE; 16350 goto smp_create_done; 16351 } 16352 16353 /* 16354 * check the smp to see whether it direct 16355 * attached to the controller 16356 */ 16357 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 16358 != DEVINFO_DIRECT_ATTACHED) { 16359 goto smp_create_done; 16360 } 16361 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 16362 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1); 16363 if (numphys > 0) { 16364 goto smp_create_done; 16365 } 16366 /* 16367 * this iport is an old iport, we need to 16368 * reconfig the props for it. 16369 */ 16370 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 16371 MPTSAS_VIRTUAL_PORT, 0) != 16372 DDI_PROP_SUCCESS) { 16373 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16374 MPTSAS_VIRTUAL_PORT); 16375 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 16376 "prop update failed"); 16377 goto smp_create_done; 16378 } 16379 16380 mutex_enter(&mpt->m_mutex); 16381 numphys = 0; 16382 iport = ddi_get_name_addr(pdip); 16383 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16384 bzero(phymask, sizeof (phymask)); 16385 (void) sprintf(phymask, 16386 "%x", mpt->m_phy_info[i].phy_mask); 16387 if (strcmp(phymask, iport) == 0) { 16388 phy_mask = mpt->m_phy_info[i].phy_mask; 16389 break; 16390 } 16391 } 16392 16393 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16394 if ((phy_mask >> i) & 0x01) { 16395 numphys++; 16396 } 16397 } 16398 /* 16399 * Update PHY info for smhba 16400 */ 16401 if (mptsas_smhba_phy_init(mpt)) { 16402 mutex_exit(&mpt->m_mutex); 16403 mptsas_log(mpt, CE_WARN, "mptsas phy update " 16404 "failed"); 16405 goto smp_create_done; 16406 } 16407 mutex_exit(&mpt->m_mutex); 16408 16409 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask, 16410 &attached_devhdl); 16411 16412 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 16413 MPTSAS_NUM_PHYS, numphys) != 16414 DDI_PROP_SUCCESS) { 16415 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16416 MPTSAS_NUM_PHYS); 16417 mptsas_log(mpt, CE_WARN, "mptsas update " 16418 "num phys props failed"); 16419 goto smp_create_done; 16420 } 16421 /* 16422 * Add parent's props for SMHBA support 16423 */ 16424 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip, 16425 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 16426 DDI_PROP_SUCCESS) { 16427 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16428 SCSI_ADDR_PROP_ATTACHED_PORT); 16429 mptsas_log(mpt, CE_WARN, "mptsas update iport" 16430 "attached-port failed"); 16431 goto smp_create_done; 16432 } 16433 16434 smp_create_done: 16435 /* 16436 * If props were setup ok, online the lun 16437 */ 16438 if (ndi_rtn == NDI_SUCCESS) { 16439 /* 16440 * Try to online the new node 16441 */ 16442 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH); 16443 } 16444 16445 /* 16446 * If success set rtn flag, else unwire alloc'd lun 16447 */ 16448 if (ndi_rtn != NDI_SUCCESS) { 16449 NDBG12(("mptsas unable to online " 16450 "SMP target %s", wwn_str)); 16451 ndi_prop_remove_all(*smp_dip); 16452 (void) ndi_devi_free(*smp_dip); 16453 } 16454 } 16455 16456 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 16457 } 16458 16459 /* smp transport routine */ 16460 static int mptsas_smp_start(struct smp_pkt *smp_pkt) 16461 { 16462 uint64_t wwn; 16463 Mpi2SmpPassthroughRequest_t req; 16464 Mpi2SmpPassthroughReply_t rep; 16465 uint32_t direction = 0; 16466 mptsas_t *mpt; 16467 int ret; 16468 uint64_t tmp64; 16469 16470 mpt = (mptsas_t *)smp_pkt->smp_pkt_address-> 16471 smp_a_hba_tran->smp_tran_hba_private; 16472 16473 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE); 16474 /* 16475 * Need to compose a SMP request message 16476 * and call mptsas_do_passthru() function 16477 */ 16478 bzero(&req, sizeof (req)); 16479 bzero(&rep, sizeof (rep)); 16480 req.PassthroughFlags = 0; 16481 req.PhysicalPort = 0xff; 16482 req.ChainOffset = 0; 16483 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH; 16484 16485 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) { 16486 smp_pkt->smp_pkt_reason = ERANGE; 16487 return (DDI_FAILURE); 16488 } 16489 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4)); 16490 16491 req.MsgFlags = 0; 16492 tmp64 = LE_64(wwn); 16493 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE); 16494 if (smp_pkt->smp_pkt_rspsize > 0) { 16495 direction |= MPTSAS_PASS_THRU_DIRECTION_READ; 16496 } 16497 if (smp_pkt->smp_pkt_reqsize > 0) { 16498 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE; 16499 } 16500 16501 mutex_enter(&mpt->m_mutex); 16502 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, 16503 (uint8_t *)smp_pkt->smp_pkt_rsp, 16504 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep), 16505 smp_pkt->smp_pkt_rspsize - 4, direction, 16506 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4, 16507 smp_pkt->smp_pkt_timeout, FKIOCTL); 16508 mutex_exit(&mpt->m_mutex); 16509 if (ret != 0) { 16510 cmn_err(CE_WARN, "smp_start do passthru error %d", ret); 16511 smp_pkt->smp_pkt_reason = (uchar_t)(ret); 16512 return (DDI_FAILURE); 16513 } 16514 /* do passthrough success, check the smp status */ 16515 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 16516 switch (LE_16(rep.IOCStatus)) { 16517 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 16518 smp_pkt->smp_pkt_reason = ENODEV; 16519 break; 16520 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 16521 smp_pkt->smp_pkt_reason = EOVERFLOW; 16522 break; 16523 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 16524 smp_pkt->smp_pkt_reason = EIO; 16525 break; 16526 default: 16527 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc" 16528 "status:%x", LE_16(rep.IOCStatus)); 16529 smp_pkt->smp_pkt_reason = EIO; 16530 break; 16531 } 16532 return (DDI_FAILURE); 16533 } 16534 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) { 16535 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x", 16536 rep.SASStatus); 16537 smp_pkt->smp_pkt_reason = EIO; 16538 return (DDI_FAILURE); 16539 } 16540 16541 return (DDI_SUCCESS); 16542 } 16543 16544 /* 16545 * If we didn't get a match, we need to get sas page0 for each device, and 16546 * untill we get a match. If failed, return NULL 16547 */ 16548 static mptsas_target_t * 16549 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy) 16550 { 16551 int i, j = 0; 16552 int rval = 0; 16553 uint16_t cur_handle; 16554 uint32_t page_address; 16555 mptsas_target_t *ptgt = NULL; 16556 16557 /* 16558 * PHY named device must be direct attached and attaches to 16559 * narrow port, if the iport is not parent of the device which 16560 * we are looking for. 16561 */ 16562 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16563 if ((1 << i) & phymask) 16564 j++; 16565 } 16566 16567 if (j > 1) 16568 return (NULL); 16569 16570 /* 16571 * Must be a narrow port and single device attached to the narrow port 16572 * So the physical port num of device which is equal to the iport's 16573 * port num is the device what we are looking for. 16574 */ 16575 16576 if (mpt->m_phy_info[phy].phy_mask != phymask) 16577 return (NULL); 16578 16579 mutex_enter(&mpt->m_mutex); 16580 16581 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn, 16582 &phy); 16583 if (ptgt != NULL) { 16584 mutex_exit(&mpt->m_mutex); 16585 return (ptgt); 16586 } 16587 16588 if (mpt->m_done_traverse_dev) { 16589 mutex_exit(&mpt->m_mutex); 16590 return (NULL); 16591 } 16592 16593 /* If didn't get a match, come here */ 16594 cur_handle = mpt->m_dev_handle; 16595 for (; ; ) { 16596 ptgt = NULL; 16597 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 16598 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle; 16599 rval = mptsas_get_target_device_info(mpt, page_address, 16600 &cur_handle, &ptgt); 16601 if ((rval == DEV_INFO_FAIL_PAGE0) || 16602 (rval == DEV_INFO_FAIL_ALLOC)) { 16603 break; 16604 } 16605 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 16606 (rval == DEV_INFO_PHYS_DISK) || 16607 (rval == DEV_INFO_FAIL_GUID)) { 16608 continue; 16609 } 16610 mpt->m_dev_handle = cur_handle; 16611 16612 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) { 16613 break; 16614 } 16615 } 16616 16617 mutex_exit(&mpt->m_mutex); 16618 return (ptgt); 16619 } 16620 16621 /* 16622 * The ptgt->m_addr.mta_wwn contains the wwid for each disk. 16623 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid 16624 * If we didn't get a match, we need to get sas page0 for each device, and 16625 * untill we get a match 16626 * If failed, return NULL 16627 */ 16628 static mptsas_target_t * 16629 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 16630 { 16631 int rval = 0; 16632 uint16_t cur_handle; 16633 uint32_t page_address; 16634 mptsas_target_t *tmp_tgt = NULL; 16635 mptsas_target_addr_t addr; 16636 16637 addr.mta_wwn = wwid; 16638 addr.mta_phymask = phymask; 16639 mutex_enter(&mpt->m_mutex); 16640 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 16641 if (tmp_tgt != NULL) { 16642 mutex_exit(&mpt->m_mutex); 16643 return (tmp_tgt); 16644 } 16645 16646 if (phymask == 0) { 16647 /* 16648 * It's IR volume 16649 */ 16650 rval = mptsas_get_raid_info(mpt); 16651 if (rval) { 16652 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 16653 } 16654 mutex_exit(&mpt->m_mutex); 16655 return (tmp_tgt); 16656 } 16657 16658 if (mpt->m_done_traverse_dev) { 16659 mutex_exit(&mpt->m_mutex); 16660 return (NULL); 16661 } 16662 16663 /* If didn't get a match, come here */ 16664 cur_handle = mpt->m_dev_handle; 16665 for (;;) { 16666 tmp_tgt = NULL; 16667 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 16668 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle; 16669 rval = mptsas_get_target_device_info(mpt, page_address, 16670 &cur_handle, &tmp_tgt); 16671 if ((rval == DEV_INFO_FAIL_PAGE0) || 16672 (rval == DEV_INFO_FAIL_ALLOC)) { 16673 tmp_tgt = NULL; 16674 break; 16675 } 16676 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 16677 (rval == DEV_INFO_PHYS_DISK) || 16678 (rval == DEV_INFO_FAIL_GUID)) { 16679 continue; 16680 } 16681 mpt->m_dev_handle = cur_handle; 16682 if ((tmp_tgt->m_addr.mta_wwn) && 16683 (tmp_tgt->m_addr.mta_wwn == wwid) && 16684 (tmp_tgt->m_addr.mta_phymask == phymask)) { 16685 break; 16686 } 16687 } 16688 16689 mutex_exit(&mpt->m_mutex); 16690 return (tmp_tgt); 16691 } 16692 16693 static mptsas_smp_t * 16694 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 16695 { 16696 int rval = 0; 16697 uint16_t cur_handle; 16698 uint32_t page_address; 16699 mptsas_smp_t smp_node, *psmp = NULL; 16700 mptsas_target_addr_t addr; 16701 16702 addr.mta_wwn = wwid; 16703 addr.mta_phymask = phymask; 16704 mutex_enter(&mpt->m_mutex); 16705 psmp = refhash_lookup(mpt->m_smp_targets, &addr); 16706 if (psmp != NULL) { 16707 mutex_exit(&mpt->m_mutex); 16708 return (psmp); 16709 } 16710 16711 if (mpt->m_done_traverse_smp) { 16712 mutex_exit(&mpt->m_mutex); 16713 return (NULL); 16714 } 16715 16716 /* If didn't get a match, come here */ 16717 cur_handle = mpt->m_smp_devhdl; 16718 for (;;) { 16719 psmp = NULL; 16720 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 16721 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle; 16722 rval = mptsas_get_sas_expander_page0(mpt, page_address, 16723 &smp_node); 16724 if (rval != DDI_SUCCESS) { 16725 break; 16726 } 16727 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl; 16728 psmp = mptsas_smp_alloc(mpt, &smp_node); 16729 ASSERT(psmp); 16730 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) && 16731 (psmp->m_addr.mta_phymask == phymask)) { 16732 break; 16733 } 16734 } 16735 16736 mutex_exit(&mpt->m_mutex); 16737 return (psmp); 16738 } 16739 16740 mptsas_target_t * 16741 mptsas_tgt_alloc(refhash_t *refhash, uint16_t devhdl, uint64_t wwid, 16742 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum) 16743 { 16744 mptsas_target_t *tmp_tgt = NULL; 16745 mptsas_target_addr_t addr; 16746 16747 addr.mta_wwn = wwid; 16748 addr.mta_phymask = phymask; 16749 tmp_tgt = refhash_lookup(refhash, &addr); 16750 if (tmp_tgt != NULL) { 16751 NDBG20(("Hash item already exist")); 16752 tmp_tgt->m_deviceinfo = devinfo; 16753 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */ 16754 return (tmp_tgt); 16755 } 16756 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP); 16757 if (tmp_tgt == NULL) { 16758 cmn_err(CE_WARN, "Fatal, allocated tgt failed"); 16759 return (NULL); 16760 } 16761 tmp_tgt->m_devhdl = devhdl; 16762 tmp_tgt->m_addr.mta_wwn = wwid; 16763 tmp_tgt->m_deviceinfo = devinfo; 16764 tmp_tgt->m_addr.mta_phymask = phymask; 16765 tmp_tgt->m_phynum = phynum; 16766 /* Initialized the tgt structure */ 16767 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 16768 tmp_tgt->m_qfull_retry_interval = 16769 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 16770 tmp_tgt->m_t_throttle = MAX_THROTTLE; 16771 TAILQ_INIT(&tmp_tgt->m_active_cmdq); 16772 16773 refhash_insert(refhash, tmp_tgt); 16774 16775 return (tmp_tgt); 16776 } 16777 16778 static void 16779 mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst) 16780 { 16781 dst->m_devhdl = src->m_devhdl; 16782 dst->m_deviceinfo = src->m_deviceinfo; 16783 dst->m_pdevhdl = src->m_pdevhdl; 16784 dst->m_pdevinfo = src->m_pdevinfo; 16785 } 16786 16787 static mptsas_smp_t * 16788 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data) 16789 { 16790 mptsas_target_addr_t addr; 16791 mptsas_smp_t *ret_data; 16792 16793 addr.mta_wwn = data->m_addr.mta_wwn; 16794 addr.mta_phymask = data->m_addr.mta_phymask; 16795 ret_data = refhash_lookup(mpt->m_smp_targets, &addr); 16796 /* 16797 * If there's already a matching SMP target, update its fields 16798 * in place. Since the address is not changing, it's safe to do 16799 * this. We cannot just bcopy() here because the structure we've 16800 * been given has invalid hash links. 16801 */ 16802 if (ret_data != NULL) { 16803 mptsas_smp_target_copy(data, ret_data); 16804 return (ret_data); 16805 } 16806 16807 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP); 16808 bcopy(data, ret_data, sizeof (mptsas_smp_t)); 16809 refhash_insert(mpt->m_smp_targets, ret_data); 16810 return (ret_data); 16811 } 16812 16813 /* 16814 * Functions for SGPIO LED support 16815 */ 16816 static dev_info_t * 16817 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask) 16818 { 16819 dev_info_t *dip; 16820 int prop; 16821 dip = e_ddi_hold_devi_by_dev(dev, 0); 16822 if (dip == NULL) 16823 return (dip); 16824 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 16825 "phymask", 0); 16826 *phymask = (mptsas_phymask_t)prop; 16827 ddi_release_devi(dip); 16828 return (dip); 16829 } 16830 static mptsas_target_t * 16831 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask) 16832 { 16833 uint8_t phynum; 16834 uint64_t wwn; 16835 int lun; 16836 mptsas_target_t *ptgt = NULL; 16837 16838 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) { 16839 return (NULL); 16840 } 16841 if (addr[0] == 'w') { 16842 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn); 16843 } else { 16844 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum); 16845 } 16846 return (ptgt); 16847 } 16848 16849 static int 16850 mptsas_flush_led_status(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx) 16851 { 16852 uint32_t slotstatus = 0; 16853 16854 ASSERT3U(idx, <, mep->me_nslots); 16855 16856 /* Build an MPI2 Slot Status based on our view of the world */ 16857 if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1))) 16858 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST; 16859 if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1))) 16860 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT; 16861 if (mep->me_slotleds[idx] & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1))) 16862 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE; 16863 16864 /* Write it to the controller */ 16865 NDBG14(("mptsas_ioctl: set LED status %x for slot %x", 16866 slotstatus, idx + mep->me_fslot)); 16867 return (mptsas_send_sep(mpt, mep, idx, &slotstatus, 16868 MPI2_SEP_REQ_ACTION_WRITE_STATUS)); 16869 } 16870 16871 /* 16872 * send sep request, use enclosure/slot addressing 16873 */ 16874 static int 16875 mptsas_send_sep(mptsas_t *mpt, mptsas_enclosure_t *mep, uint16_t idx, 16876 uint32_t *status, uint8_t act) 16877 { 16878 Mpi2SepRequest_t req; 16879 Mpi2SepReply_t rep; 16880 int ret; 16881 uint16_t enctype; 16882 uint16_t slot; 16883 16884 ASSERT(mutex_owned(&mpt->m_mutex)); 16885 16886 /* 16887 * Look through the enclosures and make sure that this enclosure is 16888 * something that is directly attached device. If we didn't find an 16889 * enclosure for this device, don't send the ioctl. 16890 */ 16891 enctype = mep->me_flags & MPI2_SAS_ENCLS0_FLAGS_MNG_MASK; 16892 if (enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES && 16893 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO && 16894 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO) { 16895 return (ENOTTY); 16896 } 16897 slot = idx + mep->me_fslot; 16898 16899 bzero(&req, sizeof (req)); 16900 bzero(&rep, sizeof (rep)); 16901 16902 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR; 16903 req.Action = act; 16904 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS; 16905 req.EnclosureHandle = LE_16(mep->me_enchdl); 16906 req.Slot = LE_16(slot); 16907 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16908 req.SlotStatus = LE_32(*status); 16909 } 16910 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 16911 sizeof (req), sizeof (rep), 0, MPTSAS_PASS_THRU_DIRECTION_NONE, 16912 NULL, 0, 60, FKIOCTL); 16913 if (ret != 0) { 16914 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP " 16915 "Processor Request message error %d", ret); 16916 return (ret); 16917 } 16918 /* do passthrough success, check the ioc status */ 16919 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 16920 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc " 16921 "status:%x loginfo %x", act, LE_16(rep.IOCStatus), 16922 LE_32(rep.IOCLogInfo)); 16923 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) { 16924 case MPI2_IOCSTATUS_INVALID_FUNCTION: 16925 case MPI2_IOCSTATUS_INVALID_VPID: 16926 case MPI2_IOCSTATUS_INVALID_FIELD: 16927 case MPI2_IOCSTATUS_INVALID_STATE: 16928 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 16929 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 16930 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 16931 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 16932 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 16933 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 16934 return (EINVAL); 16935 case MPI2_IOCSTATUS_BUSY: 16936 return (EBUSY); 16937 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 16938 return (EAGAIN); 16939 case MPI2_IOCSTATUS_INVALID_SGL: 16940 case MPI2_IOCSTATUS_INTERNAL_ERROR: 16941 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 16942 default: 16943 return (EIO); 16944 } 16945 } 16946 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16947 *status = LE_32(rep.SlotStatus); 16948 } 16949 16950 return (0); 16951 } 16952 16953 int 16954 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 16955 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 16956 uint32_t alloc_size, ddi_dma_cookie_t *cookiep) 16957 { 16958 ddi_dma_cookie_t new_cookie; 16959 size_t alloc_len; 16960 uint_t ncookie; 16961 16962 if (cookiep == NULL) 16963 cookiep = &new_cookie; 16964 16965 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP, 16966 NULL, dma_hdp) != DDI_SUCCESS) { 16967 return (FALSE); 16968 } 16969 16970 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr, 16971 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len, 16972 acc_hdp) != DDI_SUCCESS) { 16973 ddi_dma_free_handle(dma_hdp); 16974 *dma_hdp = NULL; 16975 return (FALSE); 16976 } 16977 16978 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len, 16979 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL, 16980 cookiep, &ncookie) != DDI_DMA_MAPPED) { 16981 (void) ddi_dma_mem_free(acc_hdp); 16982 ddi_dma_free_handle(dma_hdp); 16983 *dma_hdp = NULL; 16984 return (FALSE); 16985 } 16986 16987 return (TRUE); 16988 } 16989 16990 void 16991 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp) 16992 { 16993 if (*dma_hdp == NULL) 16994 return; 16995 16996 (void) ddi_dma_unbind_handle(*dma_hdp); 16997 (void) ddi_dma_mem_free(acc_hdp); 16998 ddi_dma_free_handle(dma_hdp); 16999 *dma_hdp = NULL; 17000 } 17001 17002 /* 17003 * DDI UFM Callbacks 17004 */ 17005 static int 17006 mptsas_ufm_fill_image(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno, 17007 ddi_ufm_image_t *img) 17008 { 17009 if (imgno != 0) 17010 return (EINVAL); 17011 17012 ddi_ufm_image_set_desc(img, "IOC Firmware"); 17013 ddi_ufm_image_set_nslots(img, 1); 17014 17015 return (0); 17016 } 17017 17018 static int 17019 mptsas_ufm_fill_slot(ddi_ufm_handle_t *ufmh, void *arg, uint_t imgno, 17020 uint_t slotno, ddi_ufm_slot_t *slot) 17021 { 17022 mptsas_t *mpt = (mptsas_t *)arg; 17023 char *buf; 17024 17025 if (imgno != 0 || slotno != 0 || 17026 ddi_prop_lookup_string(DDI_DEV_T_ANY, mpt->m_dip, 17027 DDI_PROP_DONTPASS, "firmware-version", &buf) != DDI_PROP_SUCCESS) 17028 return (EINVAL); 17029 17030 ddi_ufm_slot_set_attrs(slot, DDI_UFM_ATTR_ACTIVE); 17031 ddi_ufm_slot_set_version(slot, buf); 17032 17033 ddi_prop_free(buf); 17034 17035 return (0); 17036 } 17037 17038 static int 17039 mptsas_ufm_getcaps(ddi_ufm_handle_t *ufmh, void *arg, ddi_ufm_cap_t *caps) 17040 { 17041 *caps = DDI_UFM_CAP_REPORT; 17042 17043 return (0); 17044 } 17045