1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2000 to 2010, LSI Corporation. 28 * All rights reserved. 29 * 30 * Redistribution and use in source and binary forms of all code within 31 * this file that is exclusively owned by LSI, with or without 32 * modification, is permitted provided that, in addition to the CDDL 1.0 33 * License requirements, the following conditions are met: 34 * 35 * Neither the name of the author nor the names of its contributors may be 36 * used to endorse or promote products derived from this software without 37 * specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 40 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 41 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 42 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 43 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 44 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 45 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 46 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 47 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 49 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 50 * DAMAGE. 51 */ 52 53 /* 54 * mptsas - This is a driver based on LSI Logic's MPT2.0 interface. 55 * 56 */ 57 58 #if defined(lint) || defined(DEBUG) 59 #define MPTSAS_DEBUG 60 #endif 61 62 /* 63 * standard header files. 64 */ 65 #include <sys/note.h> 66 #include <sys/scsi/scsi.h> 67 #include <sys/pci.h> 68 #include <sys/file.h> 69 #include <sys/cpuvar.h> 70 #include <sys/policy.h> 71 #include <sys/sysevent.h> 72 #include <sys/sysevent/eventdefs.h> 73 #include <sys/sysevent/dr.h> 74 #include <sys/sata/sata_defs.h> 75 #include <sys/scsi/generic/sas.h> 76 #include <sys/scsi/impl/scsi_sas.h> 77 78 #pragma pack(1) 79 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h> 80 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h> 81 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 82 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h> 83 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h> 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h> 85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h> 87 #pragma pack() 88 89 /* 90 * private header files. 91 * 92 */ 93 #include <sys/scsi/impl/scsi_reset_notify.h> 94 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h> 95 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 96 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h> 97 98 #include <sys/raidioctl.h> 99 100 #include <sys/fs/dv_node.h> /* devfs_clean */ 101 102 /* 103 * FMA header files 104 */ 105 #include <sys/ddifm.h> 106 #include <sys/fm/protocol.h> 107 #include <sys/fm/util.h> 108 #include <sys/fm/io/ddi.h> 109 110 /* 111 * For anyone who would modify the code in mptsas_driver, it must be awared 112 * that from snv_145 where CR6910752(mpt_sas driver performance can be 113 * improved) is integrated, the per_instance mutex m_mutex is not hold 114 * in the key IO code path, including mptsas_scsi_start(), mptsas_intr() 115 * and all of the recursive functions called in them, so don't 116 * make it for granted that all operations are sync/exclude correctly. Before 117 * doing any modification in key code path, and even other code path such as 118 * DR, watchsubr, ioctl, passthrough etc, make sure the elements modified have 119 * no releationship to elements shown in the fastpath 120 * (function mptsas_handle_io_fastpath()) in ISR and its recursive functions. 121 * otherwise, you have to use the new introduced mutex to protect them. 122 * As to how to do correctly, refer to the comments in mptsas_intr(). 123 */ 124 125 /* 126 * autoconfiguration data and routines. 127 */ 128 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 129 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 130 static int mptsas_power(dev_info_t *dip, int component, int level); 131 132 /* 133 * cb_ops function 134 */ 135 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 136 cred_t *credp, int *rval); 137 #ifdef __sparc 138 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd); 139 #else /* __sparc */ 140 static int mptsas_quiesce(dev_info_t *devi); 141 #endif /* __sparc */ 142 143 /* 144 * Resource initilaization for hardware 145 */ 146 static void mptsas_setup_cmd_reg(mptsas_t *mpt); 147 static void mptsas_disable_bus_master(mptsas_t *mpt); 148 static void mptsas_hba_fini(mptsas_t *mpt); 149 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp); 150 static int mptsas_hba_setup(mptsas_t *mpt); 151 static void mptsas_hba_teardown(mptsas_t *mpt); 152 static int mptsas_config_space_init(mptsas_t *mpt); 153 static void mptsas_config_space_fini(mptsas_t *mpt); 154 static void mptsas_iport_register(mptsas_t *mpt); 155 static int mptsas_smp_setup(mptsas_t *mpt); 156 static void mptsas_smp_teardown(mptsas_t *mpt); 157 static int mptsas_cache_create(mptsas_t *mpt); 158 static void mptsas_cache_destroy(mptsas_t *mpt); 159 static int mptsas_alloc_request_frames(mptsas_t *mpt); 160 static int mptsas_alloc_reply_frames(mptsas_t *mpt); 161 static int mptsas_alloc_free_queue(mptsas_t *mpt); 162 static int mptsas_alloc_post_queue(mptsas_t *mpt); 163 static void mptsas_alloc_reply_args(mptsas_t *mpt); 164 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 165 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 166 static int mptsas_init_chip(mptsas_t *mpt, int first_time); 167 168 /* 169 * SCSA function prototypes 170 */ 171 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt); 172 static int mptsas_scsi_reset(struct scsi_address *ap, int level); 173 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt); 174 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly); 175 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, 176 int tgtonly); 177 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt); 178 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap, 179 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 180 int tgtlen, int flags, int (*callback)(), caddr_t arg); 181 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt); 182 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap, 183 struct scsi_pkt *pkt); 184 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 185 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 186 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 187 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 188 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 189 void (*callback)(caddr_t), caddr_t arg); 190 static int mptsas_get_name(struct scsi_device *sd, char *name, int len); 191 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len); 192 static int mptsas_scsi_quiesce(dev_info_t *dip); 193 static int mptsas_scsi_unquiesce(dev_info_t *dip); 194 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags, 195 ddi_bus_config_op_t op, void *arg, dev_info_t **childp); 196 197 /* 198 * SMP functions 199 */ 200 static int mptsas_smp_start(struct smp_pkt *smp_pkt); 201 202 /* 203 * internal function prototypes. 204 */ 205 static void mptsas_list_add(mptsas_t *mpt); 206 static void mptsas_list_del(mptsas_t *mpt); 207 208 static int mptsas_quiesce_bus(mptsas_t *mpt); 209 static int mptsas_unquiesce_bus(mptsas_t *mpt); 210 211 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size); 212 static void mptsas_free_handshake_msg(mptsas_t *mpt); 213 214 static void mptsas_ncmds_checkdrain(void *arg); 215 216 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd); 217 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 218 219 static int mptsas_do_detach(dev_info_t *dev); 220 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl); 221 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, 222 struct scsi_pkt *pkt); 223 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp); 224 225 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd); 226 static void mptsas_handle_event(void *args); 227 static int mptsas_handle_event_sync(void *args); 228 static void mptsas_handle_dr(void *args); 229 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 230 dev_info_t *pdip); 231 232 static void mptsas_restart_cmd(void *); 233 234 static void mptsas_flush_hba(mptsas_t *mpt); 235 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, 236 uint8_t tasktype); 237 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, 238 uchar_t reason, uint_t stat); 239 240 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2); 241 static void mptsas_process_intr(mptsas_t *mpt, 242 pMpi2ReplyDescriptorsUnion_t reply_desc_union); 243 static int mptsas_handle_io_fastpath(mptsas_t *mpt, uint16_t SMID); 244 static void mptsas_handle_scsi_io_success(mptsas_t *mpt, 245 pMpi2ReplyDescriptorsUnion_t reply_desc); 246 static void mptsas_handle_address_reply(mptsas_t *mpt, 247 pMpi2ReplyDescriptorsUnion_t reply_desc); 248 static int mptsas_wait_intr(mptsas_t *mpt, int polltime); 249 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, 250 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl); 251 252 static void mptsas_watch(void *arg); 253 static void mptsas_watchsubr(mptsas_t *mpt); 254 static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl); 255 256 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd); 257 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 258 uint8_t *data, uint32_t request_size, uint32_t reply_size, 259 uint32_t data_size, uint32_t direction, uint8_t *dataout, 260 uint32_t dataout_size, short timeout, int mode); 261 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl); 262 263 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, 264 uint32_t unique_id); 265 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd); 266 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt, 267 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code); 268 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt, 269 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 270 uint32_t diag_type); 271 static int mptsas_diag_register(mptsas_t *mpt, 272 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code); 273 static int mptsas_diag_unregister(mptsas_t *mpt, 274 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code); 275 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 276 uint32_t *return_code); 277 static int mptsas_diag_read_buffer(mptsas_t *mpt, 278 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 279 uint32_t *return_code, int ioctl_mode); 280 static int mptsas_diag_release(mptsas_t *mpt, 281 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code); 282 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, 283 uint8_t *diag_action, uint32_t length, uint32_t *return_code, 284 int ioctl_mode); 285 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data, 286 int mode); 287 288 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 289 int cmdlen, int tgtlen, int statuslen, int kf); 290 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd); 291 292 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags); 293 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg); 294 295 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg, 296 int kmflags); 297 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg); 298 299 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 300 mptsas_cmd_t *cmd); 301 static void mptsas_check_task_mgt(mptsas_t *mpt, 302 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd); 303 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 304 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 305 int *resid); 306 307 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag); 308 static void mptsas_free_active_slots(mptsas_t *mpt); 309 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 310 static int mptsas_start_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd); 311 312 static void mptsas_restart_hba(mptsas_t *mpt); 313 314 static void mptsas_deliver_doneq_thread(mptsas_t *mpt); 315 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 316 static inline void mptsas_doneq_add0(mptsas_t *mpt, mptsas_cmd_t *cmd); 317 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t); 318 319 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t); 320 static void mptsas_doneq_empty(mptsas_t *mpt); 321 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg); 322 323 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt); 324 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 325 326 static void mptsas_start_watch_reset_delay(); 327 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt); 328 static void mptsas_watch_reset_delay(void *arg); 329 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt); 330 331 static int mptsas_outstanding_cmds_n(mptsas_t *mpt); 332 /* 333 * helper functions 334 */ 335 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 336 337 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name); 338 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy); 339 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, 340 int lun); 341 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr, 342 int lun); 343 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy); 344 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn); 345 346 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, 347 int *lun); 348 static int mptsas_parse_smp_name(char *name, uint64_t *wwn); 349 350 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, int phymask, 351 uint8_t phy); 352 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask, 353 uint64_t wwid); 354 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask, 355 uint64_t wwid); 356 357 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, 358 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd); 359 360 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 361 uint16_t *handle, mptsas_target_t **pptgt); 362 static void mptsas_update_phymask(mptsas_t *mpt); 363 static inline void mptsas_remove_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd); 364 365 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt, 366 uint32_t *status, uint8_t cmd); 367 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev, 368 mptsas_phymask_t *phymask); 369 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, 370 mptsas_phymask_t phymask); 371 static int mptsas_set_led_status(mptsas_t *mpt, mptsas_target_t *ptgt, 372 uint32_t slotstatus); 373 374 375 /* 376 * Enumeration / DR functions 377 */ 378 static void mptsas_config_all(dev_info_t *pdip); 379 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 380 dev_info_t **lundip); 381 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 382 dev_info_t **lundip); 383 384 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt); 385 static int mptsas_offline_target(dev_info_t *pdip, char *name); 386 387 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target, 388 dev_info_t **dip); 389 390 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt); 391 static int mptsas_probe_lun(dev_info_t *pdip, int lun, 392 dev_info_t **dip, mptsas_target_t *ptgt); 393 394 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 395 dev_info_t **dip, mptsas_target_t *ptgt, int lun); 396 397 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 398 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun); 399 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 400 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, 401 int lun); 402 403 static void mptsas_offline_missed_luns(dev_info_t *pdip, 404 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt); 405 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 406 mdi_pathinfo_t *rpip, uint_t flags); 407 408 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, 409 dev_info_t **smp_dip); 410 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 411 uint_t flags); 412 413 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, 414 int mode, int *rval); 415 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, 416 int mode, int *rval); 417 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, 418 int mode, int *rval); 419 static void mptsas_record_event(void *args); 420 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, 421 int mode); 422 423 static void mptsas_hash_init(mptsas_hash_table_t *hashtab); 424 static void mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen); 425 static void mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data); 426 static void * mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1, 427 mptsas_phymask_t key2); 428 static void * mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1, 429 mptsas_phymask_t key2); 430 static void * mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos); 431 432 mptsas_target_t *mptsas_tgt_alloc(mptsas_hash_table_t *, uint16_t, uint64_t, 433 uint32_t, mptsas_phymask_t, uint8_t, mptsas_t *); 434 static mptsas_smp_t *mptsas_smp_alloc(mptsas_hash_table_t *hashtab, 435 mptsas_smp_t *data); 436 static void mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid, 437 mptsas_phymask_t phymask); 438 static void mptsas_tgt_free(mptsas_hash_table_t *, uint64_t, mptsas_phymask_t); 439 static void * mptsas_search_by_devhdl(mptsas_hash_table_t *, uint16_t); 440 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 441 dev_info_t **smp_dip); 442 443 /* 444 * Power management functions 445 */ 446 static int mptsas_get_pci_cap(mptsas_t *mpt); 447 static int mptsas_init_pm(mptsas_t *mpt); 448 449 /* 450 * MPT MSI tunable: 451 * 452 * By default MSI is enabled on all supported platforms. 453 */ 454 boolean_t mptsas_enable_msi = B_TRUE; 455 456 static int mptsas_register_intrs(mptsas_t *); 457 static void mptsas_unregister_intrs(mptsas_t *); 458 static int mptsas_add_intrs(mptsas_t *, int); 459 static void mptsas_rem_intrs(mptsas_t *); 460 461 /* 462 * FMA Prototypes 463 */ 464 static void mptsas_fm_init(mptsas_t *mpt); 465 static void mptsas_fm_fini(mptsas_t *mpt); 466 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *); 467 468 extern pri_t minclsyspri, maxclsyspri; 469 470 /* 471 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is 472 * under this device that the paths to a physical device are created when 473 * MPxIO is used. 474 */ 475 extern dev_info_t *scsi_vhci_dip; 476 477 /* 478 * Tunable timeout value for Inquiry VPD page 0x83 479 * By default the value is 30 seconds. 480 */ 481 int mptsas_inq83_retry_timeout = 30; 482 483 /* 484 * This is used to allocate memory for message frame storage, not for 485 * data I/O DMA. All message frames must be stored in the first 4G of 486 * physical memory. 487 */ 488 ddi_dma_attr_t mptsas_dma_attrs = { 489 DMA_ATTR_V0, /* attribute layout version */ 490 0x0ull, /* address low - should be 0 (longlong) */ 491 0xffffffffull, /* address high - 32-bit max range */ 492 0x00ffffffull, /* count max - max DMA object size */ 493 4, /* allocation alignment requirements */ 494 0x78, /* burstsizes - binary encoded values */ 495 1, /* minxfer - gran. of DMA engine */ 496 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 497 0xffffffffull, /* max segment size (DMA boundary) */ 498 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 499 512, /* granularity - device transfer size */ 500 0 /* flags, set to 0 */ 501 }; 502 503 /* 504 * This is used for data I/O DMA memory allocation. (full 64-bit DMA 505 * physical addresses are supported.) 506 */ 507 ddi_dma_attr_t mptsas_dma_attrs64 = { 508 DMA_ATTR_V0, /* attribute layout version */ 509 0x0ull, /* address low - should be 0 (longlong) */ 510 0xffffffffffffffffull, /* address high - 64-bit max */ 511 0x00ffffffull, /* count max - max DMA object size */ 512 4, /* allocation alignment requirements */ 513 0x78, /* burstsizes - binary encoded values */ 514 1, /* minxfer - gran. of DMA engine */ 515 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 516 0xffffffffull, /* max segment size (DMA boundary) */ 517 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 518 512, /* granularity - device transfer size */ 519 DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */ 520 }; 521 522 ddi_device_acc_attr_t mptsas_dev_attr = { 523 DDI_DEVICE_ATTR_V1, 524 DDI_STRUCTURE_LE_ACC, 525 DDI_STRICTORDER_ACC, 526 DDI_DEFAULT_ACC 527 }; 528 529 static struct cb_ops mptsas_cb_ops = { 530 scsi_hba_open, /* open */ 531 scsi_hba_close, /* close */ 532 nodev, /* strategy */ 533 nodev, /* print */ 534 nodev, /* dump */ 535 nodev, /* read */ 536 nodev, /* write */ 537 mptsas_ioctl, /* ioctl */ 538 nodev, /* devmap */ 539 nodev, /* mmap */ 540 nodev, /* segmap */ 541 nochpoll, /* chpoll */ 542 ddi_prop_op, /* cb_prop_op */ 543 NULL, /* streamtab */ 544 D_MP, /* cb_flag */ 545 CB_REV, /* rev */ 546 nodev, /* aread */ 547 nodev /* awrite */ 548 }; 549 550 static struct dev_ops mptsas_ops = { 551 DEVO_REV, /* devo_rev, */ 552 0, /* refcnt */ 553 ddi_no_info, /* info */ 554 nulldev, /* identify */ 555 nulldev, /* probe */ 556 mptsas_attach, /* attach */ 557 mptsas_detach, /* detach */ 558 #ifdef __sparc 559 mptsas_reset, 560 #else 561 nodev, /* reset */ 562 #endif /* __sparc */ 563 &mptsas_cb_ops, /* driver operations */ 564 NULL, /* bus operations */ 565 mptsas_power, /* power management */ 566 #ifdef __sparc 567 ddi_quiesce_not_needed 568 #else 569 mptsas_quiesce /* quiesce */ 570 #endif /* __sparc */ 571 }; 572 573 574 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24" 575 576 static struct modldrv modldrv = { 577 &mod_driverops, /* Type of module. This one is a driver */ 578 MPTSAS_MOD_STRING, /* Name of the module. */ 579 &mptsas_ops, /* driver ops */ 580 }; 581 582 static struct modlinkage modlinkage = { 583 MODREV_1, &modldrv, NULL 584 }; 585 #define TARGET_PROP "target" 586 #define LUN_PROP "lun" 587 #define LUN64_PROP "lun64" 588 #define SAS_PROP "sas-mpt" 589 #define MDI_GUID "wwn" 590 #define NDI_GUID "guid" 591 #define MPTSAS_DEV_GONE "mptsas_dev_gone" 592 593 /* 594 * Local static data 595 */ 596 #if defined(MPTSAS_DEBUG) 597 uint32_t mptsas_debug_flags = 0; 598 #endif /* defined(MPTSAS_DEBUG) */ 599 uint32_t mptsas_debug_resets = 0; 600 601 static kmutex_t mptsas_global_mutex; 602 static void *mptsas_state; /* soft state ptr */ 603 static krwlock_t mptsas_global_rwlock; 604 605 static kmutex_t mptsas_log_mutex; 606 static char mptsas_log_buf[256]; 607 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf)) 608 609 static mptsas_t *mptsas_head, *mptsas_tail; 610 static clock_t mptsas_scsi_watchdog_tick; 611 static clock_t mptsas_tick; 612 static timeout_id_t mptsas_reset_watch; 613 static timeout_id_t mptsas_timeout_id; 614 static int mptsas_timeouts_enabled = 0; 615 /* 616 * warlock directives 617 */ 618 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \ 619 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status)) 620 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt)) 621 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address)) 622 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private)) 623 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private)) 624 625 /* 626 * SM - HBA statics 627 */ 628 char *mptsas_driver_rev = MPTSAS_MOD_STRING; 629 630 #ifdef MPTSAS_DEBUG 631 void debug_enter(char *); 632 #endif 633 634 /* 635 * Notes: 636 * - scsi_hba_init(9F) initializes SCSI HBA modules 637 * - must call scsi_hba_fini(9F) if modload() fails 638 */ 639 int 640 _init(void) 641 { 642 int status; 643 /* CONSTCOND */ 644 ASSERT(NO_COMPETING_THREADS); 645 646 NDBG0(("_init")); 647 648 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE, 649 MPTSAS_INITIAL_SOFT_SPACE); 650 if (status != 0) { 651 return (status); 652 } 653 654 if ((status = scsi_hba_init(&modlinkage)) != 0) { 655 ddi_soft_state_fini(&mptsas_state); 656 return (status); 657 } 658 659 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL); 660 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL); 661 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL); 662 663 if ((status = mod_install(&modlinkage)) != 0) { 664 mutex_destroy(&mptsas_log_mutex); 665 rw_destroy(&mptsas_global_rwlock); 666 mutex_destroy(&mptsas_global_mutex); 667 ddi_soft_state_fini(&mptsas_state); 668 scsi_hba_fini(&modlinkage); 669 } 670 671 return (status); 672 } 673 674 /* 675 * Notes: 676 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules 677 */ 678 int 679 _fini(void) 680 { 681 int status; 682 /* CONSTCOND */ 683 ASSERT(NO_COMPETING_THREADS); 684 685 NDBG0(("_fini")); 686 687 if ((status = mod_remove(&modlinkage)) == 0) { 688 ddi_soft_state_fini(&mptsas_state); 689 scsi_hba_fini(&modlinkage); 690 mutex_destroy(&mptsas_global_mutex); 691 rw_destroy(&mptsas_global_rwlock); 692 mutex_destroy(&mptsas_log_mutex); 693 } 694 return (status); 695 } 696 697 /* 698 * The loadable-module _info(9E) entry point 699 */ 700 int 701 _info(struct modinfo *modinfop) 702 { 703 /* CONSTCOND */ 704 ASSERT(NO_COMPETING_THREADS); 705 NDBG0(("mptsas _info")); 706 707 return (mod_info(&modlinkage, modinfop)); 708 } 709 710 711 static int 712 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 713 { 714 dev_info_t *pdip; 715 mptsas_t *mpt; 716 scsi_hba_tran_t *hba_tran; 717 char *iport = NULL; 718 char phymask[MPTSAS_MAX_PHYS]; 719 mptsas_phymask_t phy_mask = 0; 720 int dynamic_port = 0; 721 uint32_t page_address; 722 char initiator_wwnstr[MPTSAS_WWN_STRLEN]; 723 int rval = DDI_FAILURE; 724 int i = 0; 725 uint8_t numphys = 0; 726 uint8_t phy_id; 727 uint8_t phy_port = 0; 728 uint16_t attached_devhdl = 0; 729 uint32_t dev_info; 730 uint64_t attached_sas_wwn; 731 uint16_t dev_hdl; 732 uint16_t pdev_hdl; 733 uint16_t bay_num, enclosure; 734 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 735 736 /* CONSTCOND */ 737 ASSERT(NO_COMPETING_THREADS); 738 739 switch (cmd) { 740 case DDI_ATTACH: 741 break; 742 743 case DDI_RESUME: 744 /* 745 * If this a scsi-iport node, nothing to do here. 746 */ 747 return (DDI_SUCCESS); 748 749 default: 750 return (DDI_FAILURE); 751 } 752 753 pdip = ddi_get_parent(dip); 754 755 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) == 756 NULL) { 757 cmn_err(CE_WARN, "Failed attach iport because fail to " 758 "get tran vector for the HBA node"); 759 return (DDI_FAILURE); 760 } 761 762 mpt = TRAN2MPT(hba_tran); 763 ASSERT(mpt != NULL); 764 if (mpt == NULL) 765 return (DDI_FAILURE); 766 767 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == 768 NULL) { 769 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to " 770 "get tran vector for the iport node"); 771 return (DDI_FAILURE); 772 } 773 774 /* 775 * Overwrite parent's tran_hba_private to iport's tran vector 776 */ 777 hba_tran->tran_hba_private = mpt; 778 779 ddi_report_dev(dip); 780 781 /* 782 * Get SAS address for initiator port according dev_handle 783 */ 784 iport = ddi_get_name_addr(dip); 785 if (iport && strncmp(iport, "v0", 2) == 0) { 786 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 787 MPTSAS_VIRTUAL_PORT, 1) != 788 DDI_PROP_SUCCESS) { 789 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 790 MPTSAS_VIRTUAL_PORT); 791 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 792 "prop update failed"); 793 return (DDI_FAILURE); 794 } 795 return (DDI_SUCCESS); 796 } 797 798 mutex_enter(&mpt->m_mutex); 799 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 800 bzero(phymask, sizeof (phymask)); 801 (void) sprintf(phymask, 802 "%x", mpt->m_phy_info[i].phy_mask); 803 if (strcmp(phymask, iport) == 0) { 804 break; 805 } 806 } 807 808 if (i == MPTSAS_MAX_PHYS) { 809 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port" 810 "seems not exist", iport); 811 mutex_exit(&mpt->m_mutex); 812 return (DDI_FAILURE); 813 } 814 815 phy_mask = mpt->m_phy_info[i].phy_mask; 816 817 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION) 818 dynamic_port = 1; 819 else 820 dynamic_port = 0; 821 822 /* 823 * Update PHY info for smhba 824 */ 825 if (mptsas_smhba_phy_init(mpt)) { 826 mutex_exit(&mpt->m_mutex); 827 mptsas_log(mpt, CE_WARN, "mptsas phy update " 828 "failed"); 829 return (DDI_FAILURE); 830 } 831 832 mutex_exit(&mpt->m_mutex); 833 834 numphys = 0; 835 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 836 if ((phy_mask >> i) & 0x01) { 837 numphys++; 838 } 839 } 840 841 bzero(initiator_wwnstr, sizeof (initiator_wwnstr)); 842 (void) sprintf(initiator_wwnstr, "w%016"PRIx64, 843 mpt->un.m_base_wwid); 844 845 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 846 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) != 847 DDI_PROP_SUCCESS) { 848 (void) ddi_prop_remove(DDI_DEV_T_NONE, 849 dip, SCSI_ADDR_PROP_INITIATOR_PORT); 850 mptsas_log(mpt, CE_WARN, "mptsas Initiator port " 851 "prop update failed"); 852 return (DDI_FAILURE); 853 } 854 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 855 MPTSAS_NUM_PHYS, numphys) != 856 DDI_PROP_SUCCESS) { 857 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS); 858 return (DDI_FAILURE); 859 } 860 861 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 862 "phymask", phy_mask) != 863 DDI_PROP_SUCCESS) { 864 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask"); 865 mptsas_log(mpt, CE_WARN, "mptsas phy mask " 866 "prop update failed"); 867 return (DDI_FAILURE); 868 } 869 870 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 871 "dynamic-port", dynamic_port) != 872 DDI_PROP_SUCCESS) { 873 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port"); 874 mptsas_log(mpt, CE_WARN, "mptsas dynamic port " 875 "prop update failed"); 876 return (DDI_FAILURE); 877 } 878 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 879 MPTSAS_VIRTUAL_PORT, 0) != 880 DDI_PROP_SUCCESS) { 881 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 882 MPTSAS_VIRTUAL_PORT); 883 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 884 "prop update failed"); 885 return (DDI_FAILURE); 886 } 887 mptsas_smhba_set_phy_props(mpt, 888 iport, dip, numphys, &attached_devhdl); 889 890 mutex_enter(&mpt->m_mutex); 891 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 892 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl; 893 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 894 &attached_sas_wwn, &dev_info, &phy_port, &phy_id, 895 &pdev_hdl, &bay_num, &enclosure); 896 if (rval != DDI_SUCCESS) { 897 mptsas_log(mpt, CE_WARN, 898 "Failed to get device page0 for handle:%d", 899 attached_devhdl); 900 mutex_exit(&mpt->m_mutex); 901 return (DDI_FAILURE); 902 } 903 904 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 905 bzero(phymask, sizeof (phymask)); 906 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask); 907 if (strcmp(phymask, iport) == 0) { 908 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0], 909 "%x", 910 mpt->m_phy_info[i].phy_mask); 911 } 912 } 913 mutex_exit(&mpt->m_mutex); 914 915 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 916 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 917 attached_sas_wwn); 918 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 919 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 920 DDI_PROP_SUCCESS) { 921 (void) ddi_prop_remove(DDI_DEV_T_NONE, 922 dip, SCSI_ADDR_PROP_ATTACHED_PORT); 923 return (DDI_FAILURE); 924 } 925 926 /* Create kstats for each phy on this iport */ 927 928 mptsas_create_phy_stats(mpt, iport, dip); 929 930 /* 931 * register sas hba iport with mdi (MPxIO/vhci) 932 */ 933 if (mdi_phci_register(MDI_HCI_CLASS_SCSI, 934 dip, 0) == MDI_SUCCESS) { 935 mpt->m_mpxio_enable = TRUE; 936 } 937 return (DDI_SUCCESS); 938 } 939 940 /* 941 * Notes: 942 * Set up all device state and allocate data structures, 943 * mutexes, condition variables, etc. for device operation. 944 * Add interrupts needed. 945 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE. 946 */ 947 static int 948 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 949 { 950 mptsas_t *mpt = NULL; 951 int instance, i, j; 952 int doneq_thread_num; 953 char intr_added = 0; 954 char map_setup = 0; 955 char config_setup = 0; 956 char hba_attach_setup = 0; 957 char smp_attach_setup = 0; 958 char mutex_init_done = 0; 959 char event_taskq_create = 0; 960 char dr_taskq_create = 0; 961 char doneq_thread_create = 0; 962 scsi_hba_tran_t *hba_tran; 963 uint_t mem_bar = MEM_SPACE; 964 int rval = DDI_FAILURE; 965 966 /* CONSTCOND */ 967 ASSERT(NO_COMPETING_THREADS); 968 969 if (scsi_hba_iport_unit_address(dip)) { 970 return (mptsas_iport_attach(dip, cmd)); 971 } 972 973 switch (cmd) { 974 case DDI_ATTACH: 975 break; 976 977 case DDI_RESUME: 978 if ((hba_tran = ddi_get_driver_private(dip)) == NULL) 979 return (DDI_FAILURE); 980 981 mpt = TRAN2MPT(hba_tran); 982 983 if (!mpt) { 984 return (DDI_FAILURE); 985 } 986 987 /* 988 * Reset hardware and softc to "no outstanding commands" 989 * Note that a check condition can result on first command 990 * to a target. 991 */ 992 mutex_enter(&mpt->m_mutex); 993 994 /* 995 * raise power. 996 */ 997 if (mpt->m_options & MPTSAS_OPT_PM) { 998 mutex_exit(&mpt->m_mutex); 999 (void) pm_busy_component(dip, 0); 1000 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0); 1001 if (rval == DDI_SUCCESS) { 1002 mutex_enter(&mpt->m_mutex); 1003 } else { 1004 /* 1005 * The pm_raise_power() call above failed, 1006 * and that can only occur if we were unable 1007 * to reset the hardware. This is probably 1008 * due to unhealty hardware, and because 1009 * important filesystems(such as the root 1010 * filesystem) could be on the attached disks, 1011 * it would not be a good idea to continue, 1012 * as we won't be entirely certain we are 1013 * writing correct data. So we panic() here 1014 * to not only prevent possible data corruption, 1015 * but to give developers or end users a hope 1016 * of identifying and correcting any problems. 1017 */ 1018 fm_panic("mptsas could not reset hardware " 1019 "during resume"); 1020 } 1021 } 1022 1023 mpt->m_suspended = 0; 1024 1025 /* 1026 * Reinitialize ioc 1027 */ 1028 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1029 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 1030 mutex_exit(&mpt->m_mutex); 1031 if (mpt->m_options & MPTSAS_OPT_PM) { 1032 (void) pm_idle_component(dip, 0); 1033 } 1034 fm_panic("mptsas init chip fail during resume"); 1035 } 1036 /* 1037 * mptsas_update_driver_data needs interrupts so enable them 1038 * first. 1039 */ 1040 MPTSAS_ENABLE_INTR(mpt); 1041 mptsas_update_driver_data(mpt); 1042 1043 /* start requests, if possible */ 1044 mptsas_restart_hba(mpt); 1045 1046 mutex_exit(&mpt->m_mutex); 1047 1048 /* 1049 * Restart watch thread 1050 */ 1051 mutex_enter(&mptsas_global_mutex); 1052 if (mptsas_timeout_id == 0) { 1053 mptsas_timeout_id = timeout(mptsas_watch, NULL, 1054 mptsas_tick); 1055 mptsas_timeouts_enabled = 1; 1056 } 1057 mutex_exit(&mptsas_global_mutex); 1058 1059 /* report idle status to pm framework */ 1060 if (mpt->m_options & MPTSAS_OPT_PM) { 1061 (void) pm_idle_component(dip, 0); 1062 } 1063 1064 return (DDI_SUCCESS); 1065 1066 default: 1067 return (DDI_FAILURE); 1068 1069 } 1070 1071 instance = ddi_get_instance(dip); 1072 1073 /* 1074 * Allocate softc information. 1075 */ 1076 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) { 1077 mptsas_log(NULL, CE_WARN, 1078 "mptsas%d: cannot allocate soft state", instance); 1079 goto fail; 1080 } 1081 1082 mpt = ddi_get_soft_state(mptsas_state, instance); 1083 1084 if (mpt == NULL) { 1085 mptsas_log(NULL, CE_WARN, 1086 "mptsas%d: cannot get soft state", instance); 1087 goto fail; 1088 } 1089 1090 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */ 1091 scsi_size_clean(dip); 1092 1093 mpt->m_dip = dip; 1094 mpt->m_instance = instance; 1095 1096 /* Make a per-instance copy of the structures */ 1097 mpt->m_io_dma_attr = mptsas_dma_attrs64; 1098 mpt->m_msg_dma_attr = mptsas_dma_attrs; 1099 mpt->m_reg_acc_attr = mptsas_dev_attr; 1100 mpt->m_dev_acc_attr = mptsas_dev_attr; 1101 1102 /* 1103 * Initialize FMA 1104 */ 1105 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip, 1106 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 1107 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 1108 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 1109 1110 mptsas_fm_init(mpt); 1111 1112 if (mptsas_alloc_handshake_msg(mpt, 1113 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) { 1114 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg."); 1115 goto fail; 1116 } 1117 1118 /* 1119 * Setup configuration space 1120 */ 1121 if (mptsas_config_space_init(mpt) == FALSE) { 1122 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed"); 1123 goto fail; 1124 } 1125 config_setup++; 1126 1127 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg, 1128 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) { 1129 mptsas_log(mpt, CE_WARN, "map setup failed"); 1130 goto fail; 1131 } 1132 map_setup++; 1133 1134 /* 1135 * A taskq is created for dealing with the event handler 1136 */ 1137 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq", 1138 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1139 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed"); 1140 goto fail; 1141 } 1142 event_taskq_create++; 1143 1144 /* 1145 * A taskq is created for dealing with dr events 1146 */ 1147 if ((mpt->m_dr_taskq = ddi_taskq_create(dip, 1148 "mptsas_dr_taskq", 1149 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1150 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery " 1151 "failed"); 1152 goto fail; 1153 } 1154 dr_taskq_create++; 1155 1156 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1157 0, "mptsas_doneq_thread_threshold_prop", 10); 1158 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1159 0, "mptsas_doneq_length_threshold_prop", 8); 1160 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1161 0, "mptsas_doneq_thread_n_prop", 8); 1162 1163 if (mpt->m_doneq_thread_n) { 1164 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL); 1165 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL); 1166 1167 mutex_enter(&mpt->m_doneq_mutex); 1168 mpt->m_doneq_thread_id = 1169 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t) 1170 * mpt->m_doneq_thread_n, KM_SLEEP); 1171 1172 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1173 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL, 1174 CV_DRIVER, NULL); 1175 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL, 1176 MUTEX_DRIVER, NULL); 1177 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1178 mpt->m_doneq_thread_id[j].flag |= 1179 MPTSAS_DONEQ_THREAD_ACTIVE; 1180 mpt->m_doneq_thread_id[j].arg.mpt = mpt; 1181 mpt->m_doneq_thread_id[j].arg.t = j; 1182 mpt->m_doneq_thread_id[j].threadp = 1183 thread_create(NULL, 0, mptsas_doneq_thread, 1184 &mpt->m_doneq_thread_id[j].arg, 1185 0, &p0, TS_RUN, minclsyspri); 1186 mpt->m_doneq_thread_id[j].donetail = 1187 &mpt->m_doneq_thread_id[j].doneq; 1188 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1189 } 1190 mutex_exit(&mpt->m_doneq_mutex); 1191 doneq_thread_create++; 1192 } 1193 1194 /* Initialize mutex used in interrupt handler */ 1195 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, 1196 DDI_INTR_PRI(mpt->m_intr_pri)); 1197 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL); 1198 mutex_init(&mpt->m_intr_mutex, NULL, MUTEX_DRIVER, 1199 DDI_INTR_PRI(mpt->m_intr_pri)); 1200 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1201 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex, 1202 NULL, MUTEX_DRIVER, 1203 DDI_INTR_PRI(mpt->m_intr_pri)); 1204 } 1205 1206 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL); 1207 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL); 1208 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL); 1209 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL); 1210 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL); 1211 mutex_init_done++; 1212 1213 /* 1214 * Disable hardware interrupt since we're not ready to 1215 * handle it yet. 1216 */ 1217 MPTSAS_DISABLE_INTR(mpt); 1218 if (mptsas_register_intrs(mpt) == FALSE) 1219 goto fail; 1220 intr_added++; 1221 1222 mutex_enter(&mpt->m_mutex); 1223 /* 1224 * Initialize power management component 1225 */ 1226 if (mpt->m_options & MPTSAS_OPT_PM) { 1227 if (mptsas_init_pm(mpt)) { 1228 mutex_exit(&mpt->m_mutex); 1229 mptsas_log(mpt, CE_WARN, "mptsas pm initialization " 1230 "failed"); 1231 goto fail; 1232 } 1233 } 1234 1235 /* 1236 * Initialize chip using Message Unit Reset, if allowed 1237 */ 1238 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1239 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) { 1240 mutex_exit(&mpt->m_mutex); 1241 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed"); 1242 goto fail; 1243 } 1244 1245 /* 1246 * Fill in the phy_info structure and get the base WWID 1247 */ 1248 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) { 1249 mptsas_log(mpt, CE_WARN, 1250 "mptsas_get_manufacture_page5 failed!"); 1251 goto fail; 1252 } 1253 1254 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) { 1255 mptsas_log(mpt, CE_WARN, 1256 "mptsas_get_sas_io_unit_page_hndshk failed!"); 1257 goto fail; 1258 } 1259 1260 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) { 1261 mptsas_log(mpt, CE_WARN, 1262 "mptsas_get_manufacture_page0 failed!"); 1263 goto fail; 1264 } 1265 1266 mutex_exit(&mpt->m_mutex); 1267 1268 /* 1269 * Register the iport for multiple port HBA 1270 */ 1271 mptsas_iport_register(mpt); 1272 1273 /* 1274 * initialize SCSI HBA transport structure 1275 */ 1276 if (mptsas_hba_setup(mpt) == FALSE) 1277 goto fail; 1278 hba_attach_setup++; 1279 1280 if (mptsas_smp_setup(mpt) == FALSE) 1281 goto fail; 1282 smp_attach_setup++; 1283 1284 if (mptsas_cache_create(mpt) == FALSE) 1285 goto fail; 1286 1287 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 1288 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY); 1289 if (mpt->m_scsi_reset_delay == 0) { 1290 mptsas_log(mpt, CE_NOTE, 1291 "scsi_reset_delay of 0 is not recommended," 1292 " resetting to SCSI_DEFAULT_RESET_DELAY\n"); 1293 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY; 1294 } 1295 1296 /* 1297 * Initialize the wait and done FIFO queue 1298 */ 1299 mpt->m_donetail = &mpt->m_doneq; 1300 mpt->m_waitqtail = &mpt->m_waitq; 1301 1302 /* 1303 * ioc cmd queue initialize 1304 */ 1305 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq; 1306 mpt->m_dev_handle = 0xFFFF; 1307 1308 MPTSAS_ENABLE_INTR(mpt); 1309 1310 /* 1311 * enable event notification 1312 */ 1313 mutex_enter(&mpt->m_mutex); 1314 if (mptsas_ioc_enable_event_notification(mpt)) { 1315 mutex_exit(&mpt->m_mutex); 1316 goto fail; 1317 } 1318 mutex_exit(&mpt->m_mutex); 1319 1320 /* 1321 * Initialize PHY info for smhba 1322 */ 1323 if (mptsas_smhba_setup(mpt)) { 1324 mptsas_log(mpt, CE_WARN, "mptsas phy initialization " 1325 "failed"); 1326 goto fail; 1327 } 1328 1329 /* Check all dma handles allocated in attach */ 1330 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) 1331 != DDI_SUCCESS) || 1332 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) 1333 != DDI_SUCCESS) || 1334 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) 1335 != DDI_SUCCESS) || 1336 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) 1337 != DDI_SUCCESS) || 1338 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) 1339 != DDI_SUCCESS)) { 1340 goto fail; 1341 } 1342 1343 /* Check all acc handles allocated in attach */ 1344 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 1345 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) 1346 != DDI_SUCCESS) || 1347 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) 1348 != DDI_SUCCESS) || 1349 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) 1350 != DDI_SUCCESS) || 1351 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) 1352 != DDI_SUCCESS) || 1353 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) 1354 != DDI_SUCCESS) || 1355 (mptsas_check_acc_handle(mpt->m_config_handle) 1356 != DDI_SUCCESS)) { 1357 goto fail; 1358 } 1359 1360 /* 1361 * After this point, we are not going to fail the attach. 1362 */ 1363 /* 1364 * used for mptsas_watch 1365 */ 1366 mptsas_list_add(mpt); 1367 1368 mutex_enter(&mptsas_global_mutex); 1369 if (mptsas_timeouts_enabled == 0) { 1370 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY, 1371 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK); 1372 1373 mptsas_tick = mptsas_scsi_watchdog_tick * 1374 drv_usectohz((clock_t)1000000); 1375 1376 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 1377 mptsas_timeouts_enabled = 1; 1378 } 1379 mutex_exit(&mptsas_global_mutex); 1380 1381 /* Print message of HBA present */ 1382 ddi_report_dev(dip); 1383 1384 /* report idle status to pm framework */ 1385 if (mpt->m_options & MPTSAS_OPT_PM) { 1386 (void) pm_idle_component(dip, 0); 1387 } 1388 1389 return (DDI_SUCCESS); 1390 1391 fail: 1392 mptsas_log(mpt, CE_WARN, "attach failed"); 1393 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 1394 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 1395 if (mpt) { 1396 mutex_enter(&mptsas_global_mutex); 1397 1398 if (mptsas_timeout_id && (mptsas_head == NULL)) { 1399 timeout_id_t tid = mptsas_timeout_id; 1400 mptsas_timeouts_enabled = 0; 1401 mptsas_timeout_id = 0; 1402 mutex_exit(&mptsas_global_mutex); 1403 (void) untimeout(tid); 1404 mutex_enter(&mptsas_global_mutex); 1405 } 1406 mutex_exit(&mptsas_global_mutex); 1407 /* deallocate in reverse order */ 1408 mptsas_cache_destroy(mpt); 1409 1410 if (smp_attach_setup) { 1411 mptsas_smp_teardown(mpt); 1412 } 1413 if (hba_attach_setup) { 1414 mptsas_hba_teardown(mpt); 1415 } 1416 1417 if (mpt->m_active) { 1418 mptsas_hash_uninit(&mpt->m_active->m_smptbl, 1419 sizeof (mptsas_smp_t)); 1420 mptsas_hash_uninit(&mpt->m_active->m_tgttbl, 1421 sizeof (mptsas_target_t)); 1422 mptsas_free_active_slots(mpt); 1423 } 1424 if (intr_added) { 1425 mptsas_unregister_intrs(mpt); 1426 } 1427 1428 if (doneq_thread_create) { 1429 mutex_enter(&mpt->m_doneq_mutex); 1430 doneq_thread_num = mpt->m_doneq_thread_n; 1431 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1432 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1433 mpt->m_doneq_thread_id[j].flag &= 1434 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1435 cv_signal(&mpt->m_doneq_thread_id[j].cv); 1436 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1437 } 1438 while (mpt->m_doneq_thread_n) { 1439 cv_wait(&mpt->m_doneq_thread_cv, 1440 &mpt->m_doneq_mutex); 1441 } 1442 for (j = 0; j < doneq_thread_num; j++) { 1443 cv_destroy(&mpt->m_doneq_thread_id[j].cv); 1444 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex); 1445 } 1446 kmem_free(mpt->m_doneq_thread_id, 1447 sizeof (mptsas_doneq_thread_list_t) 1448 * doneq_thread_num); 1449 mutex_exit(&mpt->m_doneq_mutex); 1450 cv_destroy(&mpt->m_doneq_thread_cv); 1451 mutex_destroy(&mpt->m_doneq_mutex); 1452 } 1453 if (event_taskq_create) { 1454 ddi_taskq_destroy(mpt->m_event_taskq); 1455 } 1456 if (dr_taskq_create) { 1457 ddi_taskq_destroy(mpt->m_dr_taskq); 1458 } 1459 if (mutex_init_done) { 1460 mutex_destroy(&mpt->m_intr_mutex); 1461 mutex_destroy(&mpt->m_passthru_mutex); 1462 mutex_destroy(&mpt->m_mutex); 1463 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1464 mutex_destroy( 1465 &mpt->m_phy_info[i].smhba_info.phy_mutex); 1466 } 1467 cv_destroy(&mpt->m_cv); 1468 cv_destroy(&mpt->m_passthru_cv); 1469 cv_destroy(&mpt->m_fw_cv); 1470 cv_destroy(&mpt->m_config_cv); 1471 cv_destroy(&mpt->m_fw_diag_cv); 1472 } 1473 1474 if (map_setup) { 1475 mptsas_cfg_fini(mpt); 1476 } 1477 if (config_setup) { 1478 mptsas_config_space_fini(mpt); 1479 } 1480 mptsas_free_handshake_msg(mpt); 1481 mptsas_hba_fini(mpt); 1482 1483 mptsas_fm_fini(mpt); 1484 ddi_soft_state_free(mptsas_state, instance); 1485 ddi_prop_remove_all(dip); 1486 } 1487 return (DDI_FAILURE); 1488 } 1489 1490 static int 1491 mptsas_suspend(dev_info_t *devi) 1492 { 1493 mptsas_t *mpt, *g; 1494 scsi_hba_tran_t *tran; 1495 1496 if (scsi_hba_iport_unit_address(devi)) { 1497 return (DDI_SUCCESS); 1498 } 1499 1500 if ((tran = ddi_get_driver_private(devi)) == NULL) 1501 return (DDI_SUCCESS); 1502 1503 mpt = TRAN2MPT(tran); 1504 if (!mpt) { 1505 return (DDI_SUCCESS); 1506 } 1507 1508 mutex_enter(&mpt->m_mutex); 1509 1510 if (mpt->m_suspended++) { 1511 mutex_exit(&mpt->m_mutex); 1512 return (DDI_SUCCESS); 1513 } 1514 1515 /* 1516 * Cancel timeout threads for this mpt 1517 */ 1518 if (mpt->m_quiesce_timeid) { 1519 timeout_id_t tid = mpt->m_quiesce_timeid; 1520 mpt->m_quiesce_timeid = 0; 1521 mutex_exit(&mpt->m_mutex); 1522 (void) untimeout(tid); 1523 mutex_enter(&mpt->m_mutex); 1524 } 1525 1526 if (mpt->m_restart_cmd_timeid) { 1527 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1528 mpt->m_restart_cmd_timeid = 0; 1529 mutex_exit(&mpt->m_mutex); 1530 (void) untimeout(tid); 1531 mutex_enter(&mpt->m_mutex); 1532 } 1533 1534 mutex_exit(&mpt->m_mutex); 1535 1536 (void) pm_idle_component(mpt->m_dip, 0); 1537 1538 /* 1539 * Cancel watch threads if all mpts suspended 1540 */ 1541 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1542 for (g = mptsas_head; g != NULL; g = g->m_next) { 1543 if (!g->m_suspended) 1544 break; 1545 } 1546 rw_exit(&mptsas_global_rwlock); 1547 1548 mutex_enter(&mptsas_global_mutex); 1549 if (g == NULL) { 1550 timeout_id_t tid; 1551 1552 mptsas_timeouts_enabled = 0; 1553 if (mptsas_timeout_id) { 1554 tid = mptsas_timeout_id; 1555 mptsas_timeout_id = 0; 1556 mutex_exit(&mptsas_global_mutex); 1557 (void) untimeout(tid); 1558 mutex_enter(&mptsas_global_mutex); 1559 } 1560 if (mptsas_reset_watch) { 1561 tid = mptsas_reset_watch; 1562 mptsas_reset_watch = 0; 1563 mutex_exit(&mptsas_global_mutex); 1564 (void) untimeout(tid); 1565 mutex_enter(&mptsas_global_mutex); 1566 } 1567 } 1568 mutex_exit(&mptsas_global_mutex); 1569 1570 mutex_enter(&mpt->m_mutex); 1571 1572 /* 1573 * If this mpt is not in full power(PM_LEVEL_D0), just return. 1574 */ 1575 if ((mpt->m_options & MPTSAS_OPT_PM) && 1576 (mpt->m_power_level != PM_LEVEL_D0)) { 1577 mutex_exit(&mpt->m_mutex); 1578 return (DDI_SUCCESS); 1579 } 1580 1581 /* Disable HBA interrupts in hardware */ 1582 MPTSAS_DISABLE_INTR(mpt); 1583 /* 1584 * Send RAID action system shutdown to sync IR 1585 */ 1586 mptsas_raid_action_system_shutdown(mpt); 1587 1588 mutex_exit(&mpt->m_mutex); 1589 1590 /* drain the taskq */ 1591 ddi_taskq_wait(mpt->m_event_taskq); 1592 ddi_taskq_wait(mpt->m_dr_taskq); 1593 1594 return (DDI_SUCCESS); 1595 } 1596 1597 #ifdef __sparc 1598 /*ARGSUSED*/ 1599 static int 1600 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd) 1601 { 1602 mptsas_t *mpt; 1603 scsi_hba_tran_t *tran; 1604 1605 /* 1606 * If this call is for iport, just return. 1607 */ 1608 if (scsi_hba_iport_unit_address(devi)) 1609 return (DDI_SUCCESS); 1610 1611 if ((tran = ddi_get_driver_private(devi)) == NULL) 1612 return (DDI_SUCCESS); 1613 1614 if ((mpt = TRAN2MPT(tran)) == NULL) 1615 return (DDI_SUCCESS); 1616 1617 /* 1618 * Send RAID action system shutdown to sync IR. Disable HBA 1619 * interrupts in hardware first. 1620 */ 1621 MPTSAS_DISABLE_INTR(mpt); 1622 mptsas_raid_action_system_shutdown(mpt); 1623 1624 return (DDI_SUCCESS); 1625 } 1626 #else /* __sparc */ 1627 /* 1628 * quiesce(9E) entry point. 1629 * 1630 * This function is called when the system is single-threaded at high 1631 * PIL with preemption disabled. Therefore, this function must not be 1632 * blocked. 1633 * 1634 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 1635 * DDI_FAILURE indicates an error condition and should almost never happen. 1636 */ 1637 static int 1638 mptsas_quiesce(dev_info_t *devi) 1639 { 1640 mptsas_t *mpt; 1641 scsi_hba_tran_t *tran; 1642 1643 /* 1644 * If this call is for iport, just return. 1645 */ 1646 if (scsi_hba_iport_unit_address(devi)) 1647 return (DDI_SUCCESS); 1648 1649 if ((tran = ddi_get_driver_private(devi)) == NULL) 1650 return (DDI_SUCCESS); 1651 1652 if ((mpt = TRAN2MPT(tran)) == NULL) 1653 return (DDI_SUCCESS); 1654 1655 /* Disable HBA interrupts in hardware */ 1656 MPTSAS_DISABLE_INTR(mpt); 1657 /* Send RAID action system shutdonw to sync IR */ 1658 mptsas_raid_action_system_shutdown(mpt); 1659 1660 return (DDI_SUCCESS); 1661 } 1662 #endif /* __sparc */ 1663 1664 /* 1665 * detach(9E). Remove all device allocations and system resources; 1666 * disable device interrupts. 1667 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem. 1668 */ 1669 static int 1670 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 1671 { 1672 /* CONSTCOND */ 1673 ASSERT(NO_COMPETING_THREADS); 1674 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd)); 1675 1676 switch (cmd) { 1677 case DDI_DETACH: 1678 return (mptsas_do_detach(devi)); 1679 1680 case DDI_SUSPEND: 1681 return (mptsas_suspend(devi)); 1682 1683 default: 1684 return (DDI_FAILURE); 1685 } 1686 /* NOTREACHED */ 1687 } 1688 1689 static int 1690 mptsas_do_detach(dev_info_t *dip) 1691 { 1692 mptsas_t *mpt; 1693 scsi_hba_tran_t *tran; 1694 int circ = 0; 1695 int circ1 = 0; 1696 mdi_pathinfo_t *pip = NULL; 1697 int i; 1698 int doneq_thread_num = 0; 1699 1700 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip)); 1701 1702 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL) 1703 return (DDI_FAILURE); 1704 1705 mpt = TRAN2MPT(tran); 1706 if (!mpt) { 1707 return (DDI_FAILURE); 1708 } 1709 /* 1710 * Still have pathinfo child, should not detach mpt driver 1711 */ 1712 if (scsi_hba_iport_unit_address(dip)) { 1713 if (mpt->m_mpxio_enable) { 1714 /* 1715 * MPxIO enabled for the iport 1716 */ 1717 ndi_devi_enter(scsi_vhci_dip, &circ1); 1718 ndi_devi_enter(dip, &circ); 1719 while (pip = mdi_get_next_client_path(dip, NULL)) { 1720 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) { 1721 continue; 1722 } 1723 ndi_devi_exit(dip, circ); 1724 ndi_devi_exit(scsi_vhci_dip, circ1); 1725 NDBG12(("detach failed because of " 1726 "outstanding path info")); 1727 return (DDI_FAILURE); 1728 } 1729 ndi_devi_exit(dip, circ); 1730 ndi_devi_exit(scsi_vhci_dip, circ1); 1731 (void) mdi_phci_unregister(dip, 0); 1732 } 1733 1734 ddi_prop_remove_all(dip); 1735 1736 return (DDI_SUCCESS); 1737 } 1738 1739 /* Make sure power level is D0 before accessing registers */ 1740 if (mpt->m_options & MPTSAS_OPT_PM) { 1741 (void) pm_busy_component(dip, 0); 1742 if (mpt->m_power_level != PM_LEVEL_D0) { 1743 if (pm_raise_power(dip, 0, PM_LEVEL_D0) != 1744 DDI_SUCCESS) { 1745 mptsas_log(mpt, CE_WARN, 1746 "mptsas%d: Raise power request failed.", 1747 mpt->m_instance); 1748 (void) pm_idle_component(dip, 0); 1749 return (DDI_FAILURE); 1750 } 1751 } 1752 } 1753 1754 /* 1755 * Send RAID action system shutdown to sync IR. After action, send a 1756 * Message Unit Reset. Since after that DMA resource will be freed, 1757 * set ioc to READY state will avoid HBA initiated DMA operation. 1758 */ 1759 mutex_enter(&mpt->m_mutex); 1760 MPTSAS_DISABLE_INTR(mpt); 1761 mptsas_raid_action_system_shutdown(mpt); 1762 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1763 (void) mptsas_ioc_reset(mpt); 1764 mutex_exit(&mpt->m_mutex); 1765 mptsas_rem_intrs(mpt); 1766 ddi_taskq_destroy(mpt->m_event_taskq); 1767 ddi_taskq_destroy(mpt->m_dr_taskq); 1768 1769 if (mpt->m_doneq_thread_n) { 1770 mutex_enter(&mpt->m_doneq_mutex); 1771 doneq_thread_num = mpt->m_doneq_thread_n; 1772 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 1773 mutex_enter(&mpt->m_doneq_thread_id[i].mutex); 1774 mpt->m_doneq_thread_id[i].flag &= 1775 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1776 cv_signal(&mpt->m_doneq_thread_id[i].cv); 1777 mutex_exit(&mpt->m_doneq_thread_id[i].mutex); 1778 } 1779 while (mpt->m_doneq_thread_n) { 1780 cv_wait(&mpt->m_doneq_thread_cv, 1781 &mpt->m_doneq_mutex); 1782 } 1783 for (i = 0; i < doneq_thread_num; i++) { 1784 cv_destroy(&mpt->m_doneq_thread_id[i].cv); 1785 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex); 1786 } 1787 kmem_free(mpt->m_doneq_thread_id, 1788 sizeof (mptsas_doneq_thread_list_t) 1789 * doneq_thread_num); 1790 mutex_exit(&mpt->m_doneq_mutex); 1791 cv_destroy(&mpt->m_doneq_thread_cv); 1792 mutex_destroy(&mpt->m_doneq_mutex); 1793 } 1794 1795 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf); 1796 1797 mptsas_list_del(mpt); 1798 1799 /* 1800 * Cancel timeout threads for this mpt 1801 */ 1802 mutex_enter(&mpt->m_mutex); 1803 if (mpt->m_quiesce_timeid) { 1804 timeout_id_t tid = mpt->m_quiesce_timeid; 1805 mpt->m_quiesce_timeid = 0; 1806 mutex_exit(&mpt->m_mutex); 1807 (void) untimeout(tid); 1808 mutex_enter(&mpt->m_mutex); 1809 } 1810 1811 if (mpt->m_restart_cmd_timeid) { 1812 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1813 mpt->m_restart_cmd_timeid = 0; 1814 mutex_exit(&mpt->m_mutex); 1815 (void) untimeout(tid); 1816 mutex_enter(&mpt->m_mutex); 1817 } 1818 1819 mutex_exit(&mpt->m_mutex); 1820 1821 /* 1822 * last mpt? ... if active, CANCEL watch threads. 1823 */ 1824 mutex_enter(&mptsas_global_mutex); 1825 if (mptsas_head == NULL) { 1826 timeout_id_t tid; 1827 /* 1828 * Clear mptsas_timeouts_enable so that the watch thread 1829 * gets restarted on DDI_ATTACH 1830 */ 1831 mptsas_timeouts_enabled = 0; 1832 if (mptsas_timeout_id) { 1833 tid = mptsas_timeout_id; 1834 mptsas_timeout_id = 0; 1835 mutex_exit(&mptsas_global_mutex); 1836 (void) untimeout(tid); 1837 mutex_enter(&mptsas_global_mutex); 1838 } 1839 if (mptsas_reset_watch) { 1840 tid = mptsas_reset_watch; 1841 mptsas_reset_watch = 0; 1842 mutex_exit(&mptsas_global_mutex); 1843 (void) untimeout(tid); 1844 mutex_enter(&mptsas_global_mutex); 1845 } 1846 } 1847 mutex_exit(&mptsas_global_mutex); 1848 1849 /* 1850 * Delete Phy stats 1851 */ 1852 mptsas_destroy_phy_stats(mpt); 1853 1854 /* 1855 * Delete nt_active. 1856 */ 1857 mutex_enter(&mpt->m_mutex); 1858 mptsas_hash_uninit(&mpt->m_active->m_tgttbl, sizeof (mptsas_target_t)); 1859 mptsas_hash_uninit(&mpt->m_active->m_smptbl, sizeof (mptsas_smp_t)); 1860 mptsas_free_active_slots(mpt); 1861 mutex_exit(&mpt->m_mutex); 1862 1863 /* deallocate everything that was allocated in mptsas_attach */ 1864 mptsas_cache_destroy(mpt); 1865 1866 mptsas_hba_fini(mpt); 1867 mptsas_cfg_fini(mpt); 1868 1869 /* Lower the power informing PM Framework */ 1870 if (mpt->m_options & MPTSAS_OPT_PM) { 1871 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS) 1872 mptsas_log(mpt, CE_WARN, 1873 "!mptsas%d: Lower power request failed " 1874 "during detach, ignoring.", 1875 mpt->m_instance); 1876 } 1877 1878 mutex_destroy(&mpt->m_intr_mutex); 1879 mutex_destroy(&mpt->m_passthru_mutex); 1880 mutex_destroy(&mpt->m_mutex); 1881 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1882 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex); 1883 } 1884 cv_destroy(&mpt->m_cv); 1885 cv_destroy(&mpt->m_passthru_cv); 1886 cv_destroy(&mpt->m_fw_cv); 1887 cv_destroy(&mpt->m_config_cv); 1888 cv_destroy(&mpt->m_fw_diag_cv); 1889 1890 1891 mptsas_smp_teardown(mpt); 1892 mptsas_hba_teardown(mpt); 1893 1894 mptsas_config_space_fini(mpt); 1895 1896 mptsas_free_handshake_msg(mpt); 1897 1898 mptsas_fm_fini(mpt); 1899 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip)); 1900 ddi_prop_remove_all(dip); 1901 1902 return (DDI_SUCCESS); 1903 } 1904 1905 static void 1906 mptsas_list_add(mptsas_t *mpt) 1907 { 1908 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1909 1910 if (mptsas_head == NULL) { 1911 mptsas_head = mpt; 1912 } else { 1913 mptsas_tail->m_next = mpt; 1914 } 1915 mptsas_tail = mpt; 1916 rw_exit(&mptsas_global_rwlock); 1917 } 1918 1919 static void 1920 mptsas_list_del(mptsas_t *mpt) 1921 { 1922 mptsas_t *m; 1923 /* 1924 * Remove device instance from the global linked list 1925 */ 1926 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1927 if (mptsas_head == mpt) { 1928 m = mptsas_head = mpt->m_next; 1929 } else { 1930 for (m = mptsas_head; m != NULL; m = m->m_next) { 1931 if (m->m_next == mpt) { 1932 m->m_next = mpt->m_next; 1933 break; 1934 } 1935 } 1936 if (m == NULL) { 1937 mptsas_log(mpt, CE_PANIC, "Not in softc list!"); 1938 } 1939 } 1940 1941 if (mptsas_tail == mpt) { 1942 mptsas_tail = m; 1943 } 1944 rw_exit(&mptsas_global_rwlock); 1945 } 1946 1947 static int 1948 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size) 1949 { 1950 ddi_dma_attr_t task_dma_attrs; 1951 1952 task_dma_attrs = mpt->m_msg_dma_attr; 1953 task_dma_attrs.dma_attr_sgllen = 1; 1954 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size); 1955 1956 /* allocate Task Management ddi_dma resources */ 1957 if (mptsas_dma_addr_create(mpt, task_dma_attrs, 1958 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp, 1959 alloc_size, NULL) == FALSE) { 1960 return (DDI_FAILURE); 1961 } 1962 mpt->m_hshk_dma_size = alloc_size; 1963 1964 return (DDI_SUCCESS); 1965 } 1966 1967 static void 1968 mptsas_free_handshake_msg(mptsas_t *mpt) 1969 { 1970 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl); 1971 mpt->m_hshk_dma_size = 0; 1972 } 1973 1974 static int 1975 mptsas_hba_setup(mptsas_t *mpt) 1976 { 1977 scsi_hba_tran_t *hba_tran; 1978 int tran_flags; 1979 1980 /* Allocate a transport structure */ 1981 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip, 1982 SCSI_HBA_CANSLEEP); 1983 ASSERT(mpt->m_tran != NULL); 1984 1985 hba_tran->tran_hba_private = mpt; 1986 hba_tran->tran_tgt_private = NULL; 1987 1988 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init; 1989 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free; 1990 1991 hba_tran->tran_start = mptsas_scsi_start; 1992 hba_tran->tran_reset = mptsas_scsi_reset; 1993 hba_tran->tran_abort = mptsas_scsi_abort; 1994 hba_tran->tran_getcap = mptsas_scsi_getcap; 1995 hba_tran->tran_setcap = mptsas_scsi_setcap; 1996 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt; 1997 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt; 1998 1999 hba_tran->tran_dmafree = mptsas_scsi_dmafree; 2000 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt; 2001 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify; 2002 2003 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr; 2004 hba_tran->tran_get_name = mptsas_get_name; 2005 2006 hba_tran->tran_quiesce = mptsas_scsi_quiesce; 2007 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce; 2008 hba_tran->tran_bus_reset = NULL; 2009 2010 hba_tran->tran_add_eventcall = NULL; 2011 hba_tran->tran_get_eventcookie = NULL; 2012 hba_tran->tran_post_event = NULL; 2013 hba_tran->tran_remove_eventcall = NULL; 2014 2015 hba_tran->tran_bus_config = mptsas_bus_config; 2016 2017 hba_tran->tran_interconnect_type = INTERCONNECT_SAS; 2018 2019 /* 2020 * All children of the HBA are iports. We need tran was cloned. 2021 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be 2022 * inherited to iport's tran vector. 2023 */ 2024 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE); 2025 2026 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr, 2027 hba_tran, tran_flags) != DDI_SUCCESS) { 2028 mptsas_log(mpt, CE_WARN, "hba attach setup failed"); 2029 scsi_hba_tran_free(hba_tran); 2030 mpt->m_tran = NULL; 2031 return (FALSE); 2032 } 2033 return (TRUE); 2034 } 2035 2036 static void 2037 mptsas_hba_teardown(mptsas_t *mpt) 2038 { 2039 (void) scsi_hba_detach(mpt->m_dip); 2040 if (mpt->m_tran != NULL) { 2041 scsi_hba_tran_free(mpt->m_tran); 2042 mpt->m_tran = NULL; 2043 } 2044 } 2045 2046 static void 2047 mptsas_iport_register(mptsas_t *mpt) 2048 { 2049 int i, j; 2050 mptsas_phymask_t mask = 0x0; 2051 /* 2052 * initial value of mask is 0 2053 */ 2054 mutex_enter(&mpt->m_mutex); 2055 for (i = 0; i < mpt->m_num_phys; i++) { 2056 mptsas_phymask_t phy_mask = 0x0; 2057 char phy_mask_name[MPTSAS_MAX_PHYS]; 2058 uint8_t current_port; 2059 2060 if (mpt->m_phy_info[i].attached_devhdl == 0) 2061 continue; 2062 2063 bzero(phy_mask_name, sizeof (phy_mask_name)); 2064 2065 current_port = mpt->m_phy_info[i].port_num; 2066 2067 if ((mask & (1 << i)) != 0) 2068 continue; 2069 2070 for (j = 0; j < mpt->m_num_phys; j++) { 2071 if (mpt->m_phy_info[j].attached_devhdl && 2072 (mpt->m_phy_info[j].port_num == current_port)) { 2073 phy_mask |= (1 << j); 2074 } 2075 } 2076 mask = mask | phy_mask; 2077 2078 for (j = 0; j < mpt->m_num_phys; j++) { 2079 if ((phy_mask >> j) & 0x01) { 2080 mpt->m_phy_info[j].phy_mask = phy_mask; 2081 } 2082 } 2083 2084 (void) sprintf(phy_mask_name, "%x", phy_mask); 2085 2086 mutex_exit(&mpt->m_mutex); 2087 /* 2088 * register a iport 2089 */ 2090 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 2091 mutex_enter(&mpt->m_mutex); 2092 } 2093 mutex_exit(&mpt->m_mutex); 2094 /* 2095 * register a virtual port for RAID volume always 2096 */ 2097 (void) scsi_hba_iport_register(mpt->m_dip, "v0"); 2098 2099 } 2100 2101 static int 2102 mptsas_smp_setup(mptsas_t *mpt) 2103 { 2104 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip); 2105 ASSERT(mpt->m_smptran != NULL); 2106 mpt->m_smptran->smp_tran_hba_private = mpt; 2107 mpt->m_smptran->smp_tran_start = mptsas_smp_start; 2108 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) { 2109 mptsas_log(mpt, CE_WARN, "smp attach setup failed"); 2110 smp_hba_tran_free(mpt->m_smptran); 2111 mpt->m_smptran = NULL; 2112 return (FALSE); 2113 } 2114 /* 2115 * Initialize smp hash table 2116 */ 2117 mptsas_hash_init(&mpt->m_active->m_smptbl); 2118 mpt->m_smp_devhdl = 0xFFFF; 2119 2120 return (TRUE); 2121 } 2122 2123 static void 2124 mptsas_smp_teardown(mptsas_t *mpt) 2125 { 2126 (void) smp_hba_detach(mpt->m_dip); 2127 if (mpt->m_smptran != NULL) { 2128 smp_hba_tran_free(mpt->m_smptran); 2129 mpt->m_smptran = NULL; 2130 } 2131 mpt->m_smp_devhdl = 0; 2132 } 2133 2134 static int 2135 mptsas_cache_create(mptsas_t *mpt) 2136 { 2137 int instance = mpt->m_instance; 2138 char buf[64]; 2139 2140 /* 2141 * create kmem cache for packets 2142 */ 2143 (void) sprintf(buf, "mptsas%d_cache", instance); 2144 mpt->m_kmem_cache = kmem_cache_create(buf, 2145 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8, 2146 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor, 2147 NULL, (void *)mpt, NULL, 0); 2148 2149 if (mpt->m_kmem_cache == NULL) { 2150 mptsas_log(mpt, CE_WARN, "creating kmem cache failed"); 2151 return (FALSE); 2152 } 2153 2154 /* 2155 * create kmem cache for extra SGL frames if SGL cannot 2156 * be accomodated into main request frame. 2157 */ 2158 (void) sprintf(buf, "mptsas%d_cache_frames", instance); 2159 mpt->m_cache_frames = kmem_cache_create(buf, 2160 sizeof (mptsas_cache_frames_t), 8, 2161 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor, 2162 NULL, (void *)mpt, NULL, 0); 2163 2164 if (mpt->m_cache_frames == NULL) { 2165 mptsas_log(mpt, CE_WARN, "creating cache for frames failed"); 2166 return (FALSE); 2167 } 2168 2169 return (TRUE); 2170 } 2171 2172 static void 2173 mptsas_cache_destroy(mptsas_t *mpt) 2174 { 2175 /* deallocate in reverse order */ 2176 if (mpt->m_cache_frames) { 2177 kmem_cache_destroy(mpt->m_cache_frames); 2178 mpt->m_cache_frames = NULL; 2179 } 2180 if (mpt->m_kmem_cache) { 2181 kmem_cache_destroy(mpt->m_kmem_cache); 2182 mpt->m_kmem_cache = NULL; 2183 } 2184 } 2185 2186 static int 2187 mptsas_power(dev_info_t *dip, int component, int level) 2188 { 2189 #ifndef __lock_lint 2190 _NOTE(ARGUNUSED(component)) 2191 #endif 2192 mptsas_t *mpt; 2193 int rval = DDI_SUCCESS; 2194 int polls = 0; 2195 uint32_t ioc_status; 2196 2197 if (scsi_hba_iport_unit_address(dip) != 0) 2198 return (DDI_SUCCESS); 2199 2200 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip)); 2201 if (mpt == NULL) { 2202 return (DDI_FAILURE); 2203 } 2204 2205 mutex_enter(&mpt->m_mutex); 2206 2207 /* 2208 * If the device is busy, don't lower its power level 2209 */ 2210 if (mpt->m_busy && (mpt->m_power_level > level)) { 2211 mutex_exit(&mpt->m_mutex); 2212 return (DDI_FAILURE); 2213 } 2214 switch (level) { 2215 case PM_LEVEL_D0: 2216 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance)); 2217 MPTSAS_POWER_ON(mpt); 2218 /* 2219 * Wait up to 30 seconds for IOC to come out of reset. 2220 */ 2221 while (((ioc_status = ddi_get32(mpt->m_datap, 2222 &mpt->m_reg->Doorbell)) & 2223 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 2224 if (polls++ > 3000) { 2225 break; 2226 } 2227 delay(drv_usectohz(10000)); 2228 } 2229 /* 2230 * If IOC is not in operational state, try to hard reset it. 2231 */ 2232 if ((ioc_status & MPI2_IOC_STATE_MASK) != 2233 MPI2_IOC_STATE_OPERATIONAL) { 2234 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 2235 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 2236 mptsas_log(mpt, CE_WARN, 2237 "mptsas_power: hard reset failed"); 2238 mutex_exit(&mpt->m_mutex); 2239 return (DDI_FAILURE); 2240 } 2241 } 2242 mutex_enter(&mpt->m_intr_mutex); 2243 mpt->m_power_level = PM_LEVEL_D0; 2244 mutex_exit(&mpt->m_intr_mutex); 2245 break; 2246 case PM_LEVEL_D3: 2247 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance)); 2248 MPTSAS_POWER_OFF(mpt); 2249 break; 2250 default: 2251 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.", 2252 mpt->m_instance, level); 2253 rval = DDI_FAILURE; 2254 break; 2255 } 2256 mutex_exit(&mpt->m_mutex); 2257 return (rval); 2258 } 2259 2260 /* 2261 * Initialize configuration space and figure out which 2262 * chip and revison of the chip the mpt driver is using. 2263 */ 2264 static int 2265 mptsas_config_space_init(mptsas_t *mpt) 2266 { 2267 NDBG0(("mptsas_config_space_init")); 2268 2269 if (mpt->m_config_handle != NULL) 2270 return (TRUE); 2271 2272 if (pci_config_setup(mpt->m_dip, 2273 &mpt->m_config_handle) != DDI_SUCCESS) { 2274 mptsas_log(mpt, CE_WARN, "cannot map configuration space."); 2275 return (FALSE); 2276 } 2277 2278 /* 2279 * This is a workaround for a XMITS ASIC bug which does not 2280 * drive the CBE upper bits. 2281 */ 2282 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) & 2283 PCI_STAT_PERROR) { 2284 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT, 2285 PCI_STAT_PERROR); 2286 } 2287 2288 mptsas_setup_cmd_reg(mpt); 2289 2290 /* 2291 * Get the chip device id: 2292 */ 2293 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID); 2294 2295 /* 2296 * Save the revision. 2297 */ 2298 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID); 2299 2300 /* 2301 * Save the SubSystem Vendor and Device IDs 2302 */ 2303 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID); 2304 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID); 2305 2306 /* 2307 * Set the latency timer to 0x40 as specified by the upa -> pci 2308 * bridge chip design team. This may be done by the sparc pci 2309 * bus nexus driver, but the driver should make sure the latency 2310 * timer is correct for performance reasons. 2311 */ 2312 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER, 2313 MPTSAS_LATENCY_TIMER); 2314 2315 (void) mptsas_get_pci_cap(mpt); 2316 return (TRUE); 2317 } 2318 2319 static void 2320 mptsas_config_space_fini(mptsas_t *mpt) 2321 { 2322 if (mpt->m_config_handle != NULL) { 2323 mptsas_disable_bus_master(mpt); 2324 pci_config_teardown(&mpt->m_config_handle); 2325 mpt->m_config_handle = NULL; 2326 } 2327 } 2328 2329 static void 2330 mptsas_setup_cmd_reg(mptsas_t *mpt) 2331 { 2332 ushort_t cmdreg; 2333 2334 /* 2335 * Set the command register to the needed values. 2336 */ 2337 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2338 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE | 2339 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE); 2340 cmdreg &= ~PCI_COMM_IO; 2341 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2342 } 2343 2344 static void 2345 mptsas_disable_bus_master(mptsas_t *mpt) 2346 { 2347 ushort_t cmdreg; 2348 2349 /* 2350 * Clear the master enable bit in the PCI command register. 2351 * This prevents any bus mastering activity like DMA. 2352 */ 2353 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2354 cmdreg &= ~PCI_COMM_ME; 2355 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2356 } 2357 2358 int 2359 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep) 2360 { 2361 ddi_dma_attr_t attrs; 2362 2363 attrs = mpt->m_io_dma_attr; 2364 attrs.dma_attr_sgllen = 1; 2365 2366 ASSERT(dma_statep != NULL); 2367 2368 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle, 2369 &dma_statep->accessp, &dma_statep->memp, dma_statep->size, 2370 &dma_statep->cookie) == FALSE) { 2371 return (DDI_FAILURE); 2372 } 2373 2374 return (DDI_SUCCESS); 2375 } 2376 2377 void 2378 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep) 2379 { 2380 ASSERT(dma_statep != NULL); 2381 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp); 2382 dma_statep->size = 0; 2383 } 2384 2385 int 2386 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()) 2387 { 2388 ddi_dma_attr_t attrs; 2389 ddi_dma_handle_t dma_handle; 2390 caddr_t memp; 2391 ddi_acc_handle_t accessp; 2392 int rval; 2393 2394 ASSERT(mutex_owned(&mpt->m_mutex)); 2395 2396 attrs = mpt->m_msg_dma_attr; 2397 attrs.dma_attr_sgllen = 1; 2398 attrs.dma_attr_granular = size; 2399 2400 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle, 2401 &accessp, &memp, size, NULL) == FALSE) { 2402 return (DDI_FAILURE); 2403 } 2404 2405 rval = (*callback) (mpt, memp, var, accessp); 2406 2407 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) || 2408 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) { 2409 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 2410 rval = DDI_FAILURE; 2411 } 2412 2413 mptsas_dma_addr_destroy(&dma_handle, &accessp); 2414 return (rval); 2415 2416 } 2417 2418 static int 2419 mptsas_alloc_request_frames(mptsas_t *mpt) 2420 { 2421 ddi_dma_attr_t frame_dma_attrs; 2422 caddr_t memp; 2423 ddi_dma_cookie_t cookie; 2424 size_t mem_size; 2425 2426 /* 2427 * re-alloc when it has already alloced 2428 */ 2429 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2430 &mpt->m_acc_req_frame_hdl); 2431 2432 /* 2433 * The size of the request frame pool is: 2434 * Number of Request Frames * Request Frame Size 2435 */ 2436 mem_size = mpt->m_max_requests * mpt->m_req_frame_size; 2437 2438 /* 2439 * set the DMA attributes. System Request Message Frames must be 2440 * aligned on a 16-byte boundry. 2441 */ 2442 frame_dma_attrs = mpt->m_msg_dma_attr; 2443 frame_dma_attrs.dma_attr_align = 16; 2444 frame_dma_attrs.dma_attr_sgllen = 1; 2445 2446 /* 2447 * allocate the request frame pool. 2448 */ 2449 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2450 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp, 2451 mem_size, &cookie) == FALSE) { 2452 return (DDI_FAILURE); 2453 } 2454 2455 /* 2456 * Store the request frame memory address. This chip uses this 2457 * address to dma to and from the driver's frame. The second 2458 * address is the address mpt uses to fill in the frame. 2459 */ 2460 mpt->m_req_frame_dma_addr = cookie.dmac_laddress; 2461 mpt->m_req_frame = memp; 2462 2463 /* 2464 * Clear the request frame pool. 2465 */ 2466 bzero(mpt->m_req_frame, mem_size); 2467 2468 return (DDI_SUCCESS); 2469 } 2470 2471 static int 2472 mptsas_alloc_reply_frames(mptsas_t *mpt) 2473 { 2474 ddi_dma_attr_t frame_dma_attrs; 2475 caddr_t memp; 2476 ddi_dma_cookie_t cookie; 2477 size_t mem_size; 2478 2479 /* 2480 * re-alloc when it has already alloced 2481 */ 2482 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2483 &mpt->m_acc_reply_frame_hdl); 2484 2485 /* 2486 * The size of the reply frame pool is: 2487 * Number of Reply Frames * Reply Frame Size 2488 */ 2489 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size; 2490 2491 /* 2492 * set the DMA attributes. System Reply Message Frames must be 2493 * aligned on a 4-byte boundry. This is the default. 2494 */ 2495 frame_dma_attrs = mpt->m_msg_dma_attr; 2496 frame_dma_attrs.dma_attr_sgllen = 1; 2497 2498 /* 2499 * allocate the reply frame pool 2500 */ 2501 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2502 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp, 2503 mem_size, &cookie) == FALSE) { 2504 return (DDI_FAILURE); 2505 } 2506 2507 /* 2508 * Store the reply frame memory address. This chip uses this 2509 * address to dma to and from the driver's frame. The second 2510 * address is the address mpt uses to process the frame. 2511 */ 2512 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress; 2513 mpt->m_reply_frame = memp; 2514 2515 /* 2516 * Clear the reply frame pool. 2517 */ 2518 bzero(mpt->m_reply_frame, mem_size); 2519 2520 return (DDI_SUCCESS); 2521 } 2522 2523 static int 2524 mptsas_alloc_free_queue(mptsas_t *mpt) 2525 { 2526 ddi_dma_attr_t frame_dma_attrs; 2527 caddr_t memp; 2528 ddi_dma_cookie_t cookie; 2529 size_t mem_size; 2530 2531 /* 2532 * re-alloc when it has already alloced 2533 */ 2534 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2535 &mpt->m_acc_free_queue_hdl); 2536 2537 /* 2538 * The reply free queue size is: 2539 * Reply Free Queue Depth * 4 2540 * The "4" is the size of one 32 bit address (low part of 64-bit 2541 * address) 2542 */ 2543 mem_size = mpt->m_free_queue_depth * 4; 2544 2545 /* 2546 * set the DMA attributes The Reply Free Queue must be aligned on a 2547 * 16-byte boundry. 2548 */ 2549 frame_dma_attrs = mpt->m_msg_dma_attr; 2550 frame_dma_attrs.dma_attr_align = 16; 2551 frame_dma_attrs.dma_attr_sgllen = 1; 2552 2553 /* 2554 * allocate the reply free queue 2555 */ 2556 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2557 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp, 2558 mem_size, &cookie) == FALSE) { 2559 return (DDI_FAILURE); 2560 } 2561 2562 /* 2563 * Store the reply free queue memory address. This chip uses this 2564 * address to read from the reply free queue. The second address 2565 * is the address mpt uses to manage the queue. 2566 */ 2567 mpt->m_free_queue_dma_addr = cookie.dmac_laddress; 2568 mpt->m_free_queue = memp; 2569 2570 /* 2571 * Clear the reply free queue memory. 2572 */ 2573 bzero(mpt->m_free_queue, mem_size); 2574 2575 return (DDI_SUCCESS); 2576 } 2577 2578 static int 2579 mptsas_alloc_post_queue(mptsas_t *mpt) 2580 { 2581 ddi_dma_attr_t frame_dma_attrs; 2582 caddr_t memp; 2583 ddi_dma_cookie_t cookie; 2584 size_t mem_size; 2585 2586 /* 2587 * re-alloc when it has already alloced 2588 */ 2589 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2590 &mpt->m_acc_post_queue_hdl); 2591 2592 /* 2593 * The reply descriptor post queue size is: 2594 * Reply Descriptor Post Queue Depth * 8 2595 * The "8" is the size of each descriptor (8 bytes or 64 bits). 2596 */ 2597 mem_size = mpt->m_post_queue_depth * 8; 2598 2599 /* 2600 * set the DMA attributes. The Reply Descriptor Post Queue must be 2601 * aligned on a 16-byte boundry. 2602 */ 2603 frame_dma_attrs = mpt->m_msg_dma_attr; 2604 frame_dma_attrs.dma_attr_align = 16; 2605 frame_dma_attrs.dma_attr_sgllen = 1; 2606 2607 /* 2608 * allocate the reply post queue 2609 */ 2610 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2611 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp, 2612 mem_size, &cookie) == FALSE) { 2613 return (DDI_FAILURE); 2614 } 2615 2616 /* 2617 * Store the reply descriptor post queue memory address. This chip 2618 * uses this address to write to the reply descriptor post queue. The 2619 * second address is the address mpt uses to manage the queue. 2620 */ 2621 mpt->m_post_queue_dma_addr = cookie.dmac_laddress; 2622 mpt->m_post_queue = memp; 2623 2624 /* 2625 * Clear the reply post queue memory. 2626 */ 2627 bzero(mpt->m_post_queue, mem_size); 2628 2629 return (DDI_SUCCESS); 2630 } 2631 2632 static void 2633 mptsas_alloc_reply_args(mptsas_t *mpt) 2634 { 2635 if (mpt->m_replyh_args != NULL) { 2636 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 2637 * mpt->m_max_replies); 2638 mpt->m_replyh_args = NULL; 2639 } 2640 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) * 2641 mpt->m_max_replies, KM_SLEEP); 2642 } 2643 2644 static int 2645 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2646 { 2647 mptsas_cache_frames_t *frames = NULL; 2648 if (cmd->cmd_extra_frames == NULL) { 2649 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP); 2650 if (frames == NULL) { 2651 return (DDI_FAILURE); 2652 } 2653 cmd->cmd_extra_frames = frames; 2654 } 2655 return (DDI_SUCCESS); 2656 } 2657 2658 static void 2659 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2660 { 2661 if (cmd->cmd_extra_frames) { 2662 kmem_cache_free(mpt->m_cache_frames, 2663 (void *)cmd->cmd_extra_frames); 2664 cmd->cmd_extra_frames = NULL; 2665 } 2666 } 2667 2668 static void 2669 mptsas_cfg_fini(mptsas_t *mpt) 2670 { 2671 NDBG0(("mptsas_cfg_fini")); 2672 ddi_regs_map_free(&mpt->m_datap); 2673 } 2674 2675 static void 2676 mptsas_hba_fini(mptsas_t *mpt) 2677 { 2678 NDBG0(("mptsas_hba_fini")); 2679 2680 /* 2681 * Free up any allocated memory 2682 */ 2683 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2684 &mpt->m_acc_req_frame_hdl); 2685 2686 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2687 &mpt->m_acc_reply_frame_hdl); 2688 2689 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2690 &mpt->m_acc_free_queue_hdl); 2691 2692 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2693 &mpt->m_acc_post_queue_hdl); 2694 2695 if (mpt->m_replyh_args != NULL) { 2696 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 2697 * mpt->m_max_replies); 2698 } 2699 } 2700 2701 static int 2702 mptsas_name_child(dev_info_t *lun_dip, char *name, int len) 2703 { 2704 int lun = 0; 2705 char *sas_wwn = NULL; 2706 int phynum = -1; 2707 int reallen = 0; 2708 2709 /* Get the target num */ 2710 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS, 2711 LUN_PROP, 0); 2712 2713 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, 2714 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) { 2715 /* 2716 * Stick in the address of form "pPHY,LUN" 2717 */ 2718 reallen = snprintf(name, len, "p%x,%x", phynum, lun); 2719 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip, 2720 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn) 2721 == DDI_PROP_SUCCESS) { 2722 /* 2723 * Stick in the address of the form "wWWN,LUN" 2724 */ 2725 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun); 2726 ddi_prop_free(sas_wwn); 2727 } else { 2728 return (DDI_FAILURE); 2729 } 2730 2731 ASSERT(reallen < len); 2732 if (reallen >= len) { 2733 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter " 2734 "length too small, it needs to be %d bytes", reallen + 1); 2735 } 2736 return (DDI_SUCCESS); 2737 } 2738 2739 /* 2740 * tran_tgt_init(9E) - target device instance initialization 2741 */ 2742 static int 2743 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 2744 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 2745 { 2746 #ifndef __lock_lint 2747 _NOTE(ARGUNUSED(hba_tran)) 2748 #endif 2749 2750 /* 2751 * At this point, the scsi_device structure already exists 2752 * and has been initialized. 2753 * 2754 * Use this function to allocate target-private data structures, 2755 * if needed by this HBA. Add revised flow-control and queue 2756 * properties for child here, if desired and if you can tell they 2757 * support tagged queueing by now. 2758 */ 2759 mptsas_t *mpt; 2760 int lun = sd->sd_address.a_lun; 2761 mdi_pathinfo_t *pip = NULL; 2762 mptsas_tgt_private_t *tgt_private = NULL; 2763 mptsas_target_t *ptgt = NULL; 2764 char *psas_wwn = NULL; 2765 int phymask = 0; 2766 uint64_t sas_wwn = 0; 2767 mpt = SDEV2MPT(sd); 2768 2769 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0); 2770 2771 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d", 2772 (void *)hba_dip, (void *)tgt_dip, lun)); 2773 2774 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 2775 (void) ndi_merge_node(tgt_dip, mptsas_name_child); 2776 ddi_set_name_addr(tgt_dip, NULL); 2777 return (DDI_FAILURE); 2778 } 2779 /* 2780 * phymask is 0 means the virtual port for RAID 2781 */ 2782 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0, 2783 "phymask", 0); 2784 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 2785 if ((pip = (void *)(sd->sd_private)) == NULL) { 2786 /* 2787 * Very bad news if this occurs. Somehow scsi_vhci has 2788 * lost the pathinfo node for this target. 2789 */ 2790 return (DDI_NOT_WELL_FORMED); 2791 } 2792 2793 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) != 2794 DDI_PROP_SUCCESS) { 2795 mptsas_log(mpt, CE_WARN, "Get lun property failed\n"); 2796 return (DDI_FAILURE); 2797 } 2798 2799 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT, 2800 &psas_wwn) == MDI_SUCCESS) { 2801 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 2802 sas_wwn = 0; 2803 } 2804 (void) mdi_prop_free(psas_wwn); 2805 } 2806 } else { 2807 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip, 2808 DDI_PROP_DONTPASS, LUN_PROP, 0); 2809 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip, 2810 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) == 2811 DDI_PROP_SUCCESS) { 2812 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 2813 sas_wwn = 0; 2814 } 2815 ddi_prop_free(psas_wwn); 2816 } else { 2817 sas_wwn = 0; 2818 } 2819 } 2820 ASSERT((sas_wwn != 0) || (phymask != 0)); 2821 mutex_enter(&mpt->m_mutex); 2822 ptgt = mptsas_hash_search(&mpt->m_active->m_tgttbl, sas_wwn, phymask); 2823 mutex_exit(&mpt->m_mutex); 2824 if (ptgt == NULL) { 2825 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or " 2826 "gone already! phymask:%x, saswwn %"PRIx64, phymask, 2827 sas_wwn); 2828 return (DDI_FAILURE); 2829 } 2830 if (hba_tran->tran_tgt_private == NULL) { 2831 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t), 2832 KM_SLEEP); 2833 tgt_private->t_lun = lun; 2834 tgt_private->t_private = ptgt; 2835 hba_tran->tran_tgt_private = tgt_private; 2836 } 2837 2838 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 2839 return (DDI_SUCCESS); 2840 } 2841 mutex_enter(&mpt->m_mutex); 2842 2843 if (ptgt->m_deviceinfo & 2844 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 2845 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 2846 uchar_t *inq89 = NULL; 2847 int inq89_len = 0x238; 2848 int reallen = 0; 2849 int rval = 0; 2850 struct sata_id *sid = NULL; 2851 char model[SATA_ID_MODEL_LEN + 1]; 2852 char fw[SATA_ID_FW_LEN + 1]; 2853 char *vid, *pid; 2854 int i; 2855 2856 mutex_exit(&mpt->m_mutex); 2857 /* 2858 * According SCSI/ATA Translation -2 (SAT-2) revision 01a 2859 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY 2860 * DEVICE data or ATA IDENTIFY PACKET DEVICE data. 2861 */ 2862 inq89 = kmem_zalloc(inq89_len, KM_SLEEP); 2863 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89, 2864 inq89, inq89_len, &reallen, 1); 2865 2866 if (rval != 0) { 2867 if (inq89 != NULL) { 2868 kmem_free(inq89, inq89_len); 2869 } 2870 2871 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 2872 "0x89 for SATA target:%x failed!", ptgt->m_devhdl); 2873 return (DDI_SUCCESS); 2874 } 2875 sid = (void *)(&inq89[60]); 2876 2877 swab(sid->ai_model, model, SATA_ID_MODEL_LEN); 2878 swab(sid->ai_fw, fw, SATA_ID_FW_LEN); 2879 2880 model[SATA_ID_MODEL_LEN] = 0; 2881 fw[SATA_ID_FW_LEN] = 0; 2882 2883 /* 2884 * split model into into vid/pid 2885 */ 2886 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++) 2887 if ((*pid == ' ') || (*pid == '\t')) 2888 break; 2889 if (i < SATA_ID_MODEL_LEN) { 2890 vid = model; 2891 /* 2892 * terminate vid, establish pid 2893 */ 2894 *pid++ = 0; 2895 } else { 2896 /* 2897 * vid will stay "ATA ", the rule is same 2898 * as sata framework implementation. 2899 */ 2900 vid = NULL; 2901 /* 2902 * model is all pid 2903 */ 2904 pid = model; 2905 } 2906 2907 /* 2908 * override SCSA "inquiry-*" properties 2909 */ 2910 if (vid) 2911 (void) scsi_device_prop_update_inqstring(sd, 2912 INQUIRY_VENDOR_ID, vid, strlen(vid)); 2913 if (pid) 2914 (void) scsi_device_prop_update_inqstring(sd, 2915 INQUIRY_PRODUCT_ID, pid, strlen(pid)); 2916 (void) scsi_device_prop_update_inqstring(sd, 2917 INQUIRY_REVISION_ID, fw, strlen(fw)); 2918 2919 if (inq89 != NULL) { 2920 kmem_free(inq89, inq89_len); 2921 } 2922 } else { 2923 mutex_exit(&mpt->m_mutex); 2924 } 2925 2926 return (DDI_SUCCESS); 2927 } 2928 /* 2929 * tran_tgt_free(9E) - target device instance deallocation 2930 */ 2931 static void 2932 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 2933 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 2934 { 2935 #ifndef __lock_lint 2936 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd)) 2937 #endif 2938 2939 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private; 2940 2941 if (tgt_private != NULL) { 2942 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 2943 hba_tran->tran_tgt_private = NULL; 2944 } 2945 } 2946 2947 /* 2948 * scsi_pkt handling 2949 * 2950 * Visible to the external world via the transport structure. 2951 */ 2952 2953 /* 2954 * Notes: 2955 * - transport the command to the addressed SCSI target/lun device 2956 * - normal operation is to schedule the command to be transported, 2957 * and return TRAN_ACCEPT if this is successful. 2958 * - if NO_INTR, tran_start must poll device for command completion 2959 */ 2960 static int 2961 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt) 2962 { 2963 #ifndef __lock_lint 2964 _NOTE(ARGUNUSED(ap)) 2965 #endif 2966 mptsas_t *mpt = PKT2MPT(pkt); 2967 mptsas_cmd_t *cmd = PKT2CMD(pkt); 2968 int rval; 2969 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 2970 2971 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt)); 2972 ASSERT(ptgt); 2973 if (ptgt == NULL) 2974 return (TRAN_FATAL_ERROR); 2975 2976 /* 2977 * prepare the pkt before taking mutex. 2978 */ 2979 rval = mptsas_prepare_pkt(cmd); 2980 if (rval != TRAN_ACCEPT) { 2981 return (rval); 2982 } 2983 2984 /* 2985 * Send the command to target/lun, however your HBA requires it. 2986 * If busy, return TRAN_BUSY; if there's some other formatting error 2987 * in the packet, return TRAN_BADPKT; otherwise, fall through to the 2988 * return of TRAN_ACCEPT. 2989 * 2990 * Remember that access to shared resources, including the mptsas_t 2991 * data structure and the HBA hardware registers, must be protected 2992 * with mutexes, here and everywhere. 2993 * 2994 * Also remember that at interrupt time, you'll get an argument 2995 * to the interrupt handler which is a pointer to your mptsas_t 2996 * structure; you'll have to remember which commands are outstanding 2997 * and which scsi_pkt is the currently-running command so the 2998 * interrupt handler can refer to the pkt to set completion 2999 * status, call the target driver back through pkt_comp, etc. 3000 */ 3001 3002 mutex_enter(&ptgt->m_tgt_intr_mutex); 3003 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3004 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3005 /* 3006 * commands should be allowed to retry by 3007 * returning TRAN_BUSY to stall the I/O's 3008 * which come from scsi_vhci since the device/ 3009 * path is in unstable state now. 3010 */ 3011 mutex_exit(&ptgt->m_tgt_intr_mutex); 3012 return (TRAN_BUSY); 3013 } else { 3014 /* 3015 * The device is offline, just fail the 3016 * command by returning TRAN_FATAL_ERROR. 3017 */ 3018 mutex_exit(&ptgt->m_tgt_intr_mutex); 3019 return (TRAN_FATAL_ERROR); 3020 } 3021 } 3022 mutex_exit(&ptgt->m_tgt_intr_mutex); 3023 rval = mptsas_accept_pkt(mpt, cmd); 3024 3025 return (rval); 3026 } 3027 3028 static int 3029 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3030 { 3031 int rval = TRAN_ACCEPT; 3032 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3033 3034 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd)); 3035 3036 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) { 3037 rval = mptsas_prepare_pkt(cmd); 3038 if (rval != TRAN_ACCEPT) { 3039 cmd->cmd_flags &= ~CFLAG_TRANFLAG; 3040 return (rval); 3041 } 3042 } 3043 3044 /* 3045 * reset the throttle if we were draining 3046 */ 3047 mutex_enter(&ptgt->m_tgt_intr_mutex); 3048 if ((ptgt->m_t_ncmds == 0) && 3049 (ptgt->m_t_throttle == DRAIN_THROTTLE)) { 3050 NDBG23(("reset throttle")); 3051 ASSERT(ptgt->m_reset_delay == 0); 3052 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 3053 } 3054 3055 /* 3056 * If device handle has already been invalidated, just 3057 * fail the command. In theory, command from scsi_vhci 3058 * client is impossible send down command with invalid 3059 * devhdl since devhdl is set after path offline, target 3060 * driver is not suppose to select a offlined path. 3061 */ 3062 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) { 3063 NDBG20(("rejecting command, it might because invalid devhdl " 3064 "request.")); 3065 mutex_exit(&ptgt->m_tgt_intr_mutex); 3066 mutex_enter(&mpt->m_mutex); 3067 /* 3068 * If HBA is being reset, the DevHandles are being 3069 * re-initialized, which means that they could be invalid 3070 * even if the target is still attached. Check if being reset 3071 * and if DevHandle is being re-initialized. If this is the 3072 * case, return BUSY so the I/O can be retried later. 3073 */ 3074 if (mpt->m_in_reset) { 3075 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 3076 STAT_BUS_RESET); 3077 if (cmd->cmd_flags & CFLAG_TXQ) { 3078 mptsas_doneq_add(mpt, cmd); 3079 mptsas_doneq_empty(mpt); 3080 mutex_exit(&mpt->m_mutex); 3081 return (rval); 3082 } else { 3083 mutex_exit(&mpt->m_mutex); 3084 return (TRAN_BUSY); 3085 } 3086 } 3087 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED); 3088 if (cmd->cmd_flags & CFLAG_TXQ) { 3089 mptsas_doneq_add(mpt, cmd); 3090 mptsas_doneq_empty(mpt); 3091 mutex_exit(&mpt->m_mutex); 3092 return (rval); 3093 } else { 3094 mutex_exit(&mpt->m_mutex); 3095 return (TRAN_FATAL_ERROR); 3096 } 3097 } 3098 mutex_exit(&ptgt->m_tgt_intr_mutex); 3099 /* 3100 * The first case is the normal case. mpt gets a command from the 3101 * target driver and starts it. 3102 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 3103 * commands is m_max_requests - 2. 3104 */ 3105 mutex_enter(&ptgt->m_tgt_intr_mutex); 3106 if ((ptgt->m_t_throttle > HOLD_THROTTLE) && 3107 (ptgt->m_t_ncmds < ptgt->m_t_throttle) && 3108 (ptgt->m_reset_delay == 0) && 3109 (ptgt->m_t_nwait == 0) && 3110 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) { 3111 mutex_exit(&ptgt->m_tgt_intr_mutex); 3112 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 3113 (void) mptsas_start_cmd0(mpt, cmd); 3114 } else { 3115 mutex_enter(&mpt->m_mutex); 3116 mptsas_waitq_add(mpt, cmd); 3117 mutex_exit(&mpt->m_mutex); 3118 } 3119 } else { 3120 /* 3121 * Add this pkt to the work queue 3122 */ 3123 mutex_exit(&ptgt->m_tgt_intr_mutex); 3124 mutex_enter(&mpt->m_mutex); 3125 mptsas_waitq_add(mpt, cmd); 3126 3127 if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3128 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME); 3129 3130 /* 3131 * Only flush the doneq if this is not a TM 3132 * cmd. For TM cmds the flushing of the 3133 * doneq will be done in those routines. 3134 */ 3135 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 3136 mptsas_doneq_empty(mpt); 3137 } 3138 } 3139 mutex_exit(&mpt->m_mutex); 3140 } 3141 return (rval); 3142 } 3143 3144 int 3145 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 3146 { 3147 mptsas_slots_t *slots; 3148 int slot; 3149 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3150 mptsas_slot_free_e_t *pe; 3151 int qn, qn_first; 3152 3153 slots = mpt->m_active; 3154 3155 /* 3156 * Account for reserved TM request slot and reserved SMID of 0. 3157 */ 3158 ASSERT(slots->m_n_slots == (mpt->m_max_requests - 2)); 3159 3160 qn = qn_first = CPU->cpu_seqid & (mpt->m_slot_freeq_pair_n - 1); 3161 3162 qpair_retry: 3163 ASSERT(qn < mpt->m_slot_freeq_pair_n); 3164 mutex_enter(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_mutex); 3165 pe = list_head(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq. 3166 s.m_fq_list); 3167 if (!pe) { /* switch the allocq and releq */ 3168 mutex_enter(&mpt->m_slot_freeq_pairp[qn].m_slot_releq. 3169 s.m_fq_mutex); 3170 if (mpt->m_slot_freeq_pairp[qn].m_slot_releq.s.m_fq_n) { 3171 mpt->m_slot_freeq_pairp[qn]. 3172 m_slot_allocq.s.m_fq_n = 3173 mpt->m_slot_freeq_pairp[qn]. 3174 m_slot_releq.s.m_fq_n; 3175 mpt->m_slot_freeq_pairp[qn]. 3176 m_slot_allocq.s.m_fq_list.list_head.list_next = 3177 mpt->m_slot_freeq_pairp[qn]. 3178 m_slot_releq.s.m_fq_list.list_head.list_next; 3179 mpt->m_slot_freeq_pairp[qn]. 3180 m_slot_allocq.s.m_fq_list.list_head.list_prev = 3181 mpt->m_slot_freeq_pairp[qn]. 3182 m_slot_releq.s.m_fq_list.list_head.list_prev; 3183 mpt->m_slot_freeq_pairp[qn]. 3184 m_slot_releq.s.m_fq_list.list_head.list_prev-> 3185 list_next = 3186 &mpt->m_slot_freeq_pairp[qn]. 3187 m_slot_allocq.s.m_fq_list.list_head; 3188 mpt->m_slot_freeq_pairp[qn]. 3189 m_slot_releq.s.m_fq_list.list_head.list_next-> 3190 list_prev = 3191 &mpt->m_slot_freeq_pairp[qn]. 3192 m_slot_allocq.s.m_fq_list.list_head; 3193 3194 mpt->m_slot_freeq_pairp[qn]. 3195 m_slot_releq.s.m_fq_list.list_head.list_next = 3196 mpt->m_slot_freeq_pairp[qn]. 3197 m_slot_releq.s.m_fq_list.list_head.list_prev = 3198 &mpt->m_slot_freeq_pairp[qn]. 3199 m_slot_releq.s.m_fq_list.list_head; 3200 mpt->m_slot_freeq_pairp[qn]. 3201 m_slot_releq.s.m_fq_n = 0; 3202 } else { 3203 mutex_exit(&mpt->m_slot_freeq_pairp[qn]. 3204 m_slot_releq.s.m_fq_mutex); 3205 mutex_exit(&mpt->m_slot_freeq_pairp[qn]. 3206 m_slot_allocq.s.m_fq_mutex); 3207 qn = (qn + 1) & (mpt->m_slot_freeq_pair_n - 1); 3208 if (qn == qn_first) 3209 return (FALSE); 3210 else 3211 goto qpair_retry; 3212 } 3213 mutex_exit(&mpt->m_slot_freeq_pairp[qn]. 3214 m_slot_releq.s.m_fq_mutex); 3215 pe = list_head(&mpt->m_slot_freeq_pairp[qn]. 3216 m_slot_allocq.s.m_fq_list); 3217 ASSERT(pe); 3218 } 3219 list_remove(&mpt->m_slot_freeq_pairp[qn]. 3220 m_slot_allocq.s.m_fq_list, pe); 3221 slot = pe->slot; 3222 /* 3223 * Make sure SMID is not using reserved value of 0 3224 * and the TM request slot. 3225 */ 3226 ASSERT((slot > 0) && (slot <= slots->m_n_slots) && 3227 mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n > 0); 3228 cmd->cmd_slot = slot; 3229 mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n--; 3230 ASSERT(mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_n >= 0); 3231 3232 mutex_exit(&mpt->m_slot_freeq_pairp[qn].m_slot_allocq.s.m_fq_mutex); 3233 /* 3234 * only increment per target ncmds if this is not a 3235 * command that has no target associated with it (i.e. a 3236 * event acknoledgment) 3237 */ 3238 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 3239 mutex_enter(&ptgt->m_tgt_intr_mutex); 3240 ptgt->m_t_ncmds++; 3241 mutex_exit(&ptgt->m_tgt_intr_mutex); 3242 } 3243 cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time; 3244 3245 /* 3246 * If initial timout is less than or equal to one tick, bump 3247 * the timeout by a tick so that command doesn't timeout before 3248 * its allotted time. 3249 */ 3250 if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) { 3251 cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick; 3252 } 3253 return (TRUE); 3254 } 3255 3256 /* 3257 * prepare the pkt: 3258 * the pkt may have been resubmitted or just reused so 3259 * initialize some fields and do some checks. 3260 */ 3261 static int 3262 mptsas_prepare_pkt(mptsas_cmd_t *cmd) 3263 { 3264 struct scsi_pkt *pkt = CMD2PKT(cmd); 3265 3266 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd)); 3267 3268 /* 3269 * Reinitialize some fields that need it; the packet may 3270 * have been resubmitted 3271 */ 3272 pkt->pkt_reason = CMD_CMPLT; 3273 pkt->pkt_state = 0; 3274 pkt->pkt_statistics = 0; 3275 pkt->pkt_resid = 0; 3276 cmd->cmd_age = 0; 3277 cmd->cmd_pkt_flags = pkt->pkt_flags; 3278 3279 /* 3280 * zero status byte. 3281 */ 3282 *(pkt->pkt_scbp) = 0; 3283 3284 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3285 pkt->pkt_resid = cmd->cmd_dmacount; 3286 3287 /* 3288 * consistent packets need to be sync'ed first 3289 * (only for data going out) 3290 */ 3291 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 3292 (cmd->cmd_flags & CFLAG_DMASEND)) { 3293 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 3294 DDI_DMA_SYNC_FORDEV); 3295 } 3296 } 3297 3298 cmd->cmd_flags = 3299 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) | 3300 CFLAG_PREPARED | CFLAG_IN_TRANSPORT; 3301 3302 return (TRAN_ACCEPT); 3303 } 3304 3305 /* 3306 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command 3307 * 3308 * One of three possibilities: 3309 * - allocate scsi_pkt 3310 * - allocate scsi_pkt and DMA resources 3311 * - allocate DMA resources to an already-allocated pkt 3312 */ 3313 static struct scsi_pkt * 3314 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt, 3315 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags, 3316 int (*callback)(), caddr_t arg) 3317 { 3318 mptsas_cmd_t *cmd, *new_cmd; 3319 mptsas_t *mpt = ADDR2MPT(ap); 3320 int failure = 1; 3321 #ifndef __sparc 3322 uint_t oldcookiec; 3323 #endif /* __sparc */ 3324 mptsas_target_t *ptgt = NULL; 3325 int rval; 3326 mptsas_tgt_private_t *tgt_private; 3327 int kf; 3328 3329 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP; 3330 3331 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 3332 tran_tgt_private; 3333 ASSERT(tgt_private != NULL); 3334 if (tgt_private == NULL) { 3335 return (NULL); 3336 } 3337 ptgt = tgt_private->t_private; 3338 ASSERT(ptgt != NULL); 3339 if (ptgt == NULL) 3340 return (NULL); 3341 ap->a_target = ptgt->m_devhdl; 3342 ap->a_lun = tgt_private->t_lun; 3343 3344 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC); 3345 #ifdef MPTSAS_TEST_EXTRN_ALLOC 3346 statuslen *= 100; tgtlen *= 4; 3347 #endif 3348 NDBG3(("mptsas_scsi_init_pkt:\n" 3349 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x", 3350 ap->a_target, (void *)pkt, (void *)bp, 3351 cmdlen, statuslen, tgtlen, flags)); 3352 3353 /* 3354 * Allocate the new packet. 3355 */ 3356 if (pkt == NULL) { 3357 ddi_dma_handle_t save_dma_handle; 3358 ddi_dma_handle_t save_arq_dma_handle; 3359 struct buf *save_arq_bp; 3360 ddi_dma_cookie_t save_arqcookie; 3361 #ifdef __sparc 3362 mptti_t *save_sg; 3363 #endif /* __sparc */ 3364 3365 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf); 3366 3367 if (cmd) { 3368 save_dma_handle = cmd->cmd_dmahandle; 3369 save_arq_dma_handle = cmd->cmd_arqhandle; 3370 save_arq_bp = cmd->cmd_arq_buf; 3371 save_arqcookie = cmd->cmd_arqcookie; 3372 #ifdef __sparc 3373 save_sg = cmd->cmd_sg; 3374 #endif /* __sparc */ 3375 bzero(cmd, sizeof (*cmd) + scsi_pkt_size()); 3376 cmd->cmd_dmahandle = save_dma_handle; 3377 cmd->cmd_arqhandle = save_arq_dma_handle; 3378 cmd->cmd_arq_buf = save_arq_bp; 3379 cmd->cmd_arqcookie = save_arqcookie; 3380 #ifdef __sparc 3381 cmd->cmd_sg = save_sg; 3382 #endif /* __sparc */ 3383 pkt = (void *)((uchar_t *)cmd + 3384 sizeof (struct mptsas_cmd)); 3385 pkt->pkt_ha_private = (opaque_t)cmd; 3386 pkt->pkt_address = *ap; 3387 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private; 3388 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 3389 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb; 3390 cmd->cmd_pkt = (struct scsi_pkt *)pkt; 3391 cmd->cmd_cdblen = (uchar_t)cmdlen; 3392 cmd->cmd_scblen = statuslen; 3393 cmd->cmd_rqslen = SENSE_LENGTH; 3394 cmd->cmd_tgt_addr = ptgt; 3395 failure = 0; 3396 } 3397 3398 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) || 3399 (tgtlen > PKT_PRIV_LEN) || 3400 (statuslen > EXTCMDS_STATUS_SIZE)) { 3401 if (failure == 0) { 3402 /* 3403 * if extern alloc fails, all will be 3404 * deallocated, including cmd 3405 */ 3406 failure = mptsas_pkt_alloc_extern(mpt, cmd, 3407 cmdlen, tgtlen, statuslen, kf); 3408 } 3409 if (failure) { 3410 /* 3411 * if extern allocation fails, it will 3412 * deallocate the new pkt as well 3413 */ 3414 return (NULL); 3415 } 3416 } 3417 new_cmd = cmd; 3418 3419 } else { 3420 cmd = PKT2CMD(pkt); 3421 new_cmd = NULL; 3422 } 3423 3424 3425 #ifndef __sparc 3426 /* grab cmd->cmd_cookiec here as oldcookiec */ 3427 3428 oldcookiec = cmd->cmd_cookiec; 3429 #endif /* __sparc */ 3430 3431 /* 3432 * If the dma was broken up into PARTIAL transfers cmd_nwin will be 3433 * greater than 0 and we'll need to grab the next dma window 3434 */ 3435 /* 3436 * SLM-not doing extra command frame right now; may add later 3437 */ 3438 3439 if (cmd->cmd_nwin > 0) { 3440 3441 /* 3442 * Make sure we havn't gone past the the total number 3443 * of windows 3444 */ 3445 if (++cmd->cmd_winindex >= cmd->cmd_nwin) { 3446 return (NULL); 3447 } 3448 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex, 3449 &cmd->cmd_dma_offset, &cmd->cmd_dma_len, 3450 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) { 3451 return (NULL); 3452 } 3453 goto get_dma_cookies; 3454 } 3455 3456 3457 if (flags & PKT_XARQ) { 3458 cmd->cmd_flags |= CFLAG_XARQ; 3459 } 3460 3461 /* 3462 * DMA resource allocation. This version assumes your 3463 * HBA has some sort of bus-mastering or onboard DMA capability, with a 3464 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the 3465 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget. 3466 */ 3467 if (bp && (bp->b_bcount != 0) && 3468 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) { 3469 3470 int cnt, dma_flags; 3471 mptti_t *dmap; /* ptr to the S/G list */ 3472 3473 /* 3474 * Set up DMA memory and position to the next DMA segment. 3475 */ 3476 ASSERT(cmd->cmd_dmahandle != NULL); 3477 3478 if (bp->b_flags & B_READ) { 3479 dma_flags = DDI_DMA_READ; 3480 cmd->cmd_flags &= ~CFLAG_DMASEND; 3481 } else { 3482 dma_flags = DDI_DMA_WRITE; 3483 cmd->cmd_flags |= CFLAG_DMASEND; 3484 } 3485 if (flags & PKT_CONSISTENT) { 3486 cmd->cmd_flags |= CFLAG_CMDIOPB; 3487 dma_flags |= DDI_DMA_CONSISTENT; 3488 } 3489 3490 if (flags & PKT_DMA_PARTIAL) { 3491 dma_flags |= DDI_DMA_PARTIAL; 3492 } 3493 3494 /* 3495 * workaround for byte hole issue on psycho and 3496 * schizo pre 2.1 3497 */ 3498 if ((bp->b_flags & B_READ) && ((bp->b_flags & 3499 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) && 3500 ((uintptr_t)bp->b_un.b_addr & 0x7)) { 3501 dma_flags |= DDI_DMA_CONSISTENT; 3502 } 3503 3504 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp, 3505 dma_flags, callback, arg, 3506 &cmd->cmd_cookie, &cmd->cmd_cookiec); 3507 if (rval == DDI_DMA_PARTIAL_MAP) { 3508 (void) ddi_dma_numwin(cmd->cmd_dmahandle, 3509 &cmd->cmd_nwin); 3510 cmd->cmd_winindex = 0; 3511 (void) ddi_dma_getwin(cmd->cmd_dmahandle, 3512 cmd->cmd_winindex, &cmd->cmd_dma_offset, 3513 &cmd->cmd_dma_len, &cmd->cmd_cookie, 3514 &cmd->cmd_cookiec); 3515 } else if (rval && (rval != DDI_DMA_MAPPED)) { 3516 switch (rval) { 3517 case DDI_DMA_NORESOURCES: 3518 bioerror(bp, 0); 3519 break; 3520 case DDI_DMA_BADATTR: 3521 case DDI_DMA_NOMAPPING: 3522 bioerror(bp, EFAULT); 3523 break; 3524 case DDI_DMA_TOOBIG: 3525 default: 3526 bioerror(bp, EINVAL); 3527 break; 3528 } 3529 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3530 if (new_cmd) { 3531 mptsas_scsi_destroy_pkt(ap, pkt); 3532 } 3533 return ((struct scsi_pkt *)NULL); 3534 } 3535 3536 get_dma_cookies: 3537 cmd->cmd_flags |= CFLAG_DMAVALID; 3538 ASSERT(cmd->cmd_cookiec > 0); 3539 3540 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) { 3541 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n", 3542 cmd->cmd_cookiec); 3543 bioerror(bp, EINVAL); 3544 if (new_cmd) { 3545 mptsas_scsi_destroy_pkt(ap, pkt); 3546 } 3547 return ((struct scsi_pkt *)NULL); 3548 } 3549 3550 /* 3551 * Allocate extra SGL buffer if needed. 3552 */ 3553 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) && 3554 (cmd->cmd_extra_frames == NULL)) { 3555 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) == 3556 DDI_FAILURE) { 3557 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc " 3558 "failed"); 3559 bioerror(bp, ENOMEM); 3560 if (new_cmd) { 3561 mptsas_scsi_destroy_pkt(ap, pkt); 3562 } 3563 return ((struct scsi_pkt *)NULL); 3564 } 3565 } 3566 3567 /* 3568 * Always use scatter-gather transfer 3569 * Use the loop below to store physical addresses of 3570 * DMA segments, from the DMA cookies, into your HBA's 3571 * scatter-gather list. 3572 * We need to ensure we have enough kmem alloc'd 3573 * for the sg entries since we are no longer using an 3574 * array inside mptsas_cmd_t. 3575 * 3576 * We check cmd->cmd_cookiec against oldcookiec so 3577 * the scatter-gather list is correctly allocated 3578 */ 3579 #ifndef __sparc 3580 if (oldcookiec != cmd->cmd_cookiec) { 3581 if (cmd->cmd_sg != (mptti_t *)NULL) { 3582 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * 3583 oldcookiec); 3584 cmd->cmd_sg = NULL; 3585 } 3586 } 3587 3588 if (cmd->cmd_sg == (mptti_t *)NULL) { 3589 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3590 cmd->cmd_cookiec), kf); 3591 3592 if (cmd->cmd_sg == (mptti_t *)NULL) { 3593 mptsas_log(mpt, CE_WARN, 3594 "unable to kmem_alloc enough memory " 3595 "for scatter/gather list"); 3596 /* 3597 * if we have an ENOMEM condition we need to behave 3598 * the same way as the rest of this routine 3599 */ 3600 3601 bioerror(bp, ENOMEM); 3602 if (new_cmd) { 3603 mptsas_scsi_destroy_pkt(ap, pkt); 3604 } 3605 return ((struct scsi_pkt *)NULL); 3606 } 3607 } 3608 #endif /* __sparc */ 3609 dmap = cmd->cmd_sg; 3610 3611 ASSERT(cmd->cmd_cookie.dmac_size != 0); 3612 3613 /* 3614 * store the first segment into the S/G list 3615 */ 3616 dmap->count = cmd->cmd_cookie.dmac_size; 3617 dmap->addr.address64.Low = (uint32_t) 3618 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3619 dmap->addr.address64.High = (uint32_t) 3620 (cmd->cmd_cookie.dmac_laddress >> 32); 3621 3622 /* 3623 * dmacount counts the size of the dma for this window 3624 * (if partial dma is being used). totaldmacount 3625 * keeps track of the total amount of dma we have 3626 * transferred for all the windows (needed to calculate 3627 * the resid value below). 3628 */ 3629 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size; 3630 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3631 3632 /* 3633 * We already stored the first DMA scatter gather segment, 3634 * start at 1 if we need to store more. 3635 */ 3636 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) { 3637 /* 3638 * Get next DMA cookie 3639 */ 3640 ddi_dma_nextcookie(cmd->cmd_dmahandle, 3641 &cmd->cmd_cookie); 3642 dmap++; 3643 3644 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size; 3645 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3646 3647 /* 3648 * store the segment parms into the S/G list 3649 */ 3650 dmap->count = cmd->cmd_cookie.dmac_size; 3651 dmap->addr.address64.Low = (uint32_t) 3652 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3653 dmap->addr.address64.High = (uint32_t) 3654 (cmd->cmd_cookie.dmac_laddress >> 32); 3655 } 3656 3657 /* 3658 * If this was partially allocated we set the resid 3659 * the amount of data NOT transferred in this window 3660 * If there is only one window, the resid will be 0 3661 */ 3662 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount); 3663 NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount)); 3664 } 3665 return (pkt); 3666 } 3667 3668 /* 3669 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation 3670 * 3671 * Notes: 3672 * - also frees DMA resources if allocated 3673 * - implicit DMA synchonization 3674 */ 3675 static void 3676 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 3677 { 3678 mptsas_cmd_t *cmd = PKT2CMD(pkt); 3679 mptsas_t *mpt = ADDR2MPT(ap); 3680 3681 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p", 3682 ap->a_target, (void *)pkt)); 3683 3684 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3685 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 3686 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3687 } 3688 #ifndef __sparc 3689 if (cmd->cmd_sg) { 3690 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec); 3691 cmd->cmd_sg = NULL; 3692 } 3693 #endif /* __sparc */ 3694 mptsas_free_extra_sgl_frame(mpt, cmd); 3695 3696 if ((cmd->cmd_flags & 3697 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN | 3698 CFLAG_SCBEXTERN)) == 0) { 3699 cmd->cmd_flags = CFLAG_FREE; 3700 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 3701 } else { 3702 mptsas_pkt_destroy_extern(mpt, cmd); 3703 } 3704 } 3705 3706 /* 3707 * kmem cache constructor and destructor: 3708 * When constructing, we bzero the cmd and allocate the dma handle 3709 * When destructing, just free the dma handle 3710 */ 3711 static int 3712 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags) 3713 { 3714 mptsas_cmd_t *cmd = buf; 3715 mptsas_t *mpt = cdrarg; 3716 struct scsi_address ap; 3717 uint_t cookiec; 3718 ddi_dma_attr_t arq_dma_attr; 3719 int (*callback)(caddr_t); 3720 3721 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 3722 3723 NDBG4(("mptsas_kmem_cache_constructor")); 3724 3725 ap.a_hba_tran = mpt->m_tran; 3726 ap.a_target = 0; 3727 ap.a_lun = 0; 3728 3729 /* 3730 * allocate a dma handle 3731 */ 3732 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback, 3733 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) { 3734 cmd->cmd_dmahandle = NULL; 3735 return (-1); 3736 } 3737 3738 cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL, 3739 SENSE_LENGTH, B_READ, callback, NULL); 3740 if (cmd->cmd_arq_buf == NULL) { 3741 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3742 cmd->cmd_dmahandle = NULL; 3743 return (-1); 3744 } 3745 3746 /* 3747 * allocate a arq handle 3748 */ 3749 arq_dma_attr = mpt->m_msg_dma_attr; 3750 arq_dma_attr.dma_attr_sgllen = 1; 3751 if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback, 3752 NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) { 3753 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3754 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3755 cmd->cmd_dmahandle = NULL; 3756 cmd->cmd_arqhandle = NULL; 3757 return (-1); 3758 } 3759 3760 if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle, 3761 cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT), 3762 callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) { 3763 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3764 ddi_dma_free_handle(&cmd->cmd_arqhandle); 3765 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3766 cmd->cmd_dmahandle = NULL; 3767 cmd->cmd_arqhandle = NULL; 3768 cmd->cmd_arq_buf = NULL; 3769 return (-1); 3770 } 3771 /* 3772 * In sparc, the sgl length in most of the cases would be 1, so we 3773 * pre-allocate it in cache. On x86, the max number would be 256, 3774 * pre-allocate a maximum would waste a lot of memory especially 3775 * when many cmds are put onto waitq. 3776 */ 3777 #ifdef __sparc 3778 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3779 MPTSAS_MAX_CMD_SEGS), KM_SLEEP); 3780 #endif /* __sparc */ 3781 3782 return (0); 3783 } 3784 3785 static void 3786 mptsas_kmem_cache_destructor(void *buf, void *cdrarg) 3787 { 3788 #ifndef __lock_lint 3789 _NOTE(ARGUNUSED(cdrarg)) 3790 #endif 3791 mptsas_cmd_t *cmd = buf; 3792 3793 NDBG4(("mptsas_kmem_cache_destructor")); 3794 3795 if (cmd->cmd_arqhandle) { 3796 (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle); 3797 ddi_dma_free_handle(&cmd->cmd_arqhandle); 3798 cmd->cmd_arqhandle = NULL; 3799 } 3800 if (cmd->cmd_arq_buf) { 3801 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3802 cmd->cmd_arq_buf = NULL; 3803 } 3804 if (cmd->cmd_dmahandle) { 3805 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3806 cmd->cmd_dmahandle = NULL; 3807 } 3808 #ifdef __sparc 3809 if (cmd->cmd_sg) { 3810 kmem_free(cmd->cmd_sg, sizeof (mptti_t)* MPTSAS_MAX_CMD_SEGS); 3811 cmd->cmd_sg = NULL; 3812 } 3813 #endif /* __sparc */ 3814 } 3815 3816 static int 3817 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags) 3818 { 3819 mptsas_cache_frames_t *p = buf; 3820 mptsas_t *mpt = cdrarg; 3821 ddi_dma_attr_t frame_dma_attr; 3822 size_t mem_size, alloc_len; 3823 ddi_dma_cookie_t cookie; 3824 uint_t ncookie; 3825 int (*callback)(caddr_t) = (kmflags == KM_SLEEP) 3826 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 3827 3828 frame_dma_attr = mpt->m_msg_dma_attr; 3829 frame_dma_attr.dma_attr_align = 0x10; 3830 frame_dma_attr.dma_attr_sgllen = 1; 3831 3832 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL, 3833 &p->m_dma_hdl) != DDI_SUCCESS) { 3834 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for" 3835 " extra SGL."); 3836 return (DDI_FAILURE); 3837 } 3838 3839 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size; 3840 3841 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr, 3842 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr, 3843 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) { 3844 ddi_dma_free_handle(&p->m_dma_hdl); 3845 p->m_dma_hdl = NULL; 3846 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for" 3847 " extra SGL."); 3848 return (DDI_FAILURE); 3849 } 3850 3851 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr, 3852 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL, 3853 &cookie, &ncookie) != DDI_DMA_MAPPED) { 3854 (void) ddi_dma_mem_free(&p->m_acc_hdl); 3855 ddi_dma_free_handle(&p->m_dma_hdl); 3856 p->m_dma_hdl = NULL; 3857 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for" 3858 " extra SGL"); 3859 return (DDI_FAILURE); 3860 } 3861 3862 /* 3863 * Store the SGL memory address. This chip uses this 3864 * address to dma to and from the driver. The second 3865 * address is the address mpt uses to fill in the SGL. 3866 */ 3867 p->m_phys_addr = cookie.dmac_address; 3868 3869 return (DDI_SUCCESS); 3870 } 3871 3872 static void 3873 mptsas_cache_frames_destructor(void *buf, void *cdrarg) 3874 { 3875 #ifndef __lock_lint 3876 _NOTE(ARGUNUSED(cdrarg)) 3877 #endif 3878 mptsas_cache_frames_t *p = buf; 3879 if (p->m_dma_hdl != NULL) { 3880 (void) ddi_dma_unbind_handle(p->m_dma_hdl); 3881 (void) ddi_dma_mem_free(&p->m_acc_hdl); 3882 ddi_dma_free_handle(&p->m_dma_hdl); 3883 p->m_phys_addr = NULL; 3884 p->m_frames_addr = NULL; 3885 p->m_dma_hdl = NULL; 3886 p->m_acc_hdl = NULL; 3887 } 3888 3889 } 3890 3891 /* 3892 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd) 3893 * for non-standard length cdb, pkt_private, status areas 3894 * if allocation fails, then deallocate all external space and the pkt 3895 */ 3896 /* ARGSUSED */ 3897 static int 3898 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 3899 int cmdlen, int tgtlen, int statuslen, int kf) 3900 { 3901 caddr_t cdbp, scbp, tgt; 3902 int (*callback)(caddr_t) = (kf == KM_SLEEP) ? 3903 DDI_DMA_SLEEP : DDI_DMA_DONTWAIT; 3904 struct scsi_address ap; 3905 size_t senselength; 3906 ddi_dma_attr_t ext_arq_dma_attr; 3907 uint_t cookiec; 3908 3909 NDBG3(("mptsas_pkt_alloc_extern: " 3910 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x", 3911 (void *)cmd, cmdlen, tgtlen, statuslen, kf)); 3912 3913 tgt = cdbp = scbp = NULL; 3914 cmd->cmd_scblen = statuslen; 3915 cmd->cmd_privlen = (uchar_t)tgtlen; 3916 3917 if (cmdlen > sizeof (cmd->cmd_cdb)) { 3918 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) { 3919 goto fail; 3920 } 3921 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp; 3922 cmd->cmd_flags |= CFLAG_CDBEXTERN; 3923 } 3924 if (tgtlen > PKT_PRIV_LEN) { 3925 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) { 3926 goto fail; 3927 } 3928 cmd->cmd_flags |= CFLAG_PRIVEXTERN; 3929 cmd->cmd_pkt->pkt_private = tgt; 3930 } 3931 if (statuslen > EXTCMDS_STATUS_SIZE) { 3932 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) { 3933 goto fail; 3934 } 3935 cmd->cmd_flags |= CFLAG_SCBEXTERN; 3936 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp; 3937 3938 /* allocate sense data buf for DMA */ 3939 3940 senselength = statuslen - MPTSAS_GET_ITEM_OFF( 3941 struct scsi_arq_status, sts_sensedata); 3942 cmd->cmd_rqslen = (uchar_t)senselength; 3943 3944 ap.a_hba_tran = mpt->m_tran; 3945 ap.a_target = 0; 3946 ap.a_lun = 0; 3947 3948 cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap, 3949 (struct buf *)NULL, senselength, B_READ, 3950 callback, NULL); 3951 3952 if (cmd->cmd_ext_arq_buf == NULL) { 3953 goto fail; 3954 } 3955 /* 3956 * allocate a extern arq handle and bind the buf 3957 */ 3958 ext_arq_dma_attr = mpt->m_msg_dma_attr; 3959 ext_arq_dma_attr.dma_attr_sgllen = 1; 3960 if ((ddi_dma_alloc_handle(mpt->m_dip, 3961 &ext_arq_dma_attr, callback, 3962 NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) { 3963 goto fail; 3964 } 3965 3966 if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle, 3967 cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT), 3968 callback, NULL, &cmd->cmd_ext_arqcookie, 3969 &cookiec) 3970 != DDI_SUCCESS) { 3971 goto fail; 3972 } 3973 cmd->cmd_flags |= CFLAG_EXTARQBUFVALID; 3974 } 3975 return (0); 3976 fail: 3977 mptsas_pkt_destroy_extern(mpt, cmd); 3978 return (1); 3979 } 3980 3981 /* 3982 * deallocate external pkt space and deallocate the pkt 3983 */ 3984 static void 3985 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd) 3986 { 3987 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd)); 3988 3989 if (cmd->cmd_flags & CFLAG_FREE) { 3990 mptsas_log(mpt, CE_PANIC, 3991 "mptsas_pkt_destroy_extern: freeing free packet"); 3992 _NOTE(NOT_REACHED) 3993 /* NOTREACHED */ 3994 } 3995 if (cmd->cmd_flags & CFLAG_CDBEXTERN) { 3996 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen); 3997 } 3998 if (cmd->cmd_flags & CFLAG_SCBEXTERN) { 3999 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen); 4000 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) { 4001 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle); 4002 } 4003 if (cmd->cmd_ext_arqhandle) { 4004 ddi_dma_free_handle(&cmd->cmd_ext_arqhandle); 4005 cmd->cmd_ext_arqhandle = NULL; 4006 } 4007 if (cmd->cmd_ext_arq_buf) 4008 scsi_free_consistent_buf(cmd->cmd_ext_arq_buf); 4009 } 4010 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) { 4011 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen); 4012 } 4013 cmd->cmd_flags = CFLAG_FREE; 4014 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4015 } 4016 4017 /* 4018 * tran_sync_pkt(9E) - explicit DMA synchronization 4019 */ 4020 /*ARGSUSED*/ 4021 static void 4022 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4023 { 4024 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4025 4026 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p", 4027 ap->a_target, (void *)pkt)); 4028 4029 if (cmd->cmd_dmahandle) { 4030 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4031 (cmd->cmd_flags & CFLAG_DMASEND) ? 4032 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 4033 } 4034 } 4035 4036 /* 4037 * tran_dmafree(9E) - deallocate DMA resources allocated for command 4038 */ 4039 /*ARGSUSED*/ 4040 static void 4041 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 4042 { 4043 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4044 mptsas_t *mpt = ADDR2MPT(ap); 4045 4046 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p", 4047 ap->a_target, (void *)pkt)); 4048 4049 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4050 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4051 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4052 } 4053 4054 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) { 4055 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle); 4056 cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID; 4057 } 4058 4059 mptsas_free_extra_sgl_frame(mpt, cmd); 4060 } 4061 4062 static void 4063 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd) 4064 { 4065 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 4066 (!(cmd->cmd_flags & CFLAG_DMASEND))) { 4067 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4068 DDI_DMA_SYNC_FORCPU); 4069 } 4070 (*pkt->pkt_comp)(pkt); 4071 } 4072 4073 static void 4074 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control, 4075 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4076 { 4077 uint_t cookiec; 4078 mptti_t *dmap; 4079 uint32_t flags; 4080 pMpi2SGESimple64_t sge; 4081 pMpi2SGEChain64_t sgechain; 4082 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID); 4083 4084 /* 4085 * Save the number of entries in the DMA 4086 * Scatter/Gather list 4087 */ 4088 cookiec = cmd->cmd_cookiec; 4089 4090 NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec)); 4091 4092 /* 4093 * Set read/write bit in control. 4094 */ 4095 if (cmd->cmd_flags & CFLAG_DMASEND) { 4096 *control |= MPI2_SCSIIO_CONTROL_WRITE; 4097 } else { 4098 *control |= MPI2_SCSIIO_CONTROL_READ; 4099 } 4100 4101 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount); 4102 4103 /* 4104 * We have 2 cases here. First where we can fit all the 4105 * SG elements into the main frame, and the case 4106 * where we can't. 4107 * If we have more cookies than we can attach to a frame 4108 * we will need to use a chain element to point 4109 * a location of memory where the rest of the S/G 4110 * elements reside. 4111 */ 4112 if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) { 4113 dmap = cmd->cmd_sg; 4114 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4115 while (cookiec--) { 4116 ddi_put32(acc_hdl, 4117 &sge->Address.Low, dmap->addr.address64.Low); 4118 ddi_put32(acc_hdl, 4119 &sge->Address.High, dmap->addr.address64.High); 4120 ddi_put32(acc_hdl, &sge->FlagsLength, 4121 dmap->count); 4122 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4123 flags |= ((uint32_t) 4124 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4125 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4126 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4127 MPI2_SGE_FLAGS_SHIFT); 4128 4129 /* 4130 * If this is the last cookie, we set the flags 4131 * to indicate so 4132 */ 4133 if (cookiec == 0) { 4134 flags |= 4135 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT 4136 | MPI2_SGE_FLAGS_END_OF_BUFFER 4137 | MPI2_SGE_FLAGS_END_OF_LIST) << 4138 MPI2_SGE_FLAGS_SHIFT); 4139 } 4140 if (cmd->cmd_flags & CFLAG_DMASEND) { 4141 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC << 4142 MPI2_SGE_FLAGS_SHIFT); 4143 } else { 4144 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST << 4145 MPI2_SGE_FLAGS_SHIFT); 4146 } 4147 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4148 dmap++; 4149 sge++; 4150 } 4151 } else { 4152 /* 4153 * Hereby we start to deal with multiple frames. 4154 * The process is as follows: 4155 * 1. Determine how many frames are needed for SGL element 4156 * storage; Note that all frames are stored in contiguous 4157 * memory space and in 64-bit DMA mode each element is 4158 * 3 double-words (12 bytes) long. 4159 * 2. Fill up the main frame. We need to do this separately 4160 * since it contains the SCSI IO request header and needs 4161 * dedicated processing. Note that the last 4 double-words 4162 * of the SCSI IO header is for SGL element storage 4163 * (MPI2_SGE_IO_UNION). 4164 * 3. Fill the chain element in the main frame, so the DMA 4165 * engine can use the following frames. 4166 * 4. Enter a loop to fill the remaining frames. Note that the 4167 * last frame contains no chain element. The remaining 4168 * frames go into the mpt SGL buffer allocated on the fly, 4169 * not immediately following the main message frame, as in 4170 * Gen1. 4171 * Some restrictions: 4172 * 1. For 64-bit DMA, the simple element and chain element 4173 * are both of 3 double-words (12 bytes) in size, even 4174 * though all frames are stored in the first 4G of mem 4175 * range and the higher 32-bits of the address are always 0. 4176 * 2. On some controllers (like the 1064/1068), a frame can 4177 * hold SGL elements with the last 1 or 2 double-words 4178 * (4 or 8 bytes) un-used. On these controllers, we should 4179 * recognize that there's not enough room for another SGL 4180 * element and move the sge pointer to the next frame. 4181 */ 4182 int i, j, k, l, frames, sgemax; 4183 int temp; 4184 uint8_t chainflags; 4185 uint16_t chainlength; 4186 mptsas_cache_frames_t *p; 4187 4188 /* 4189 * Sgemax is the number of SGE's that will fit 4190 * each extra frame and frames is total 4191 * number of frames we'll need. 1 sge entry per 4192 * frame is reseverd for the chain element thus the -1 below. 4193 */ 4194 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) 4195 - 1); 4196 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4197 4198 /* 4199 * A little check to see if we need to round up the number 4200 * of frames we need 4201 */ 4202 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4203 sgemax) > 1) { 4204 frames = (temp + 1); 4205 } else { 4206 frames = temp; 4207 } 4208 dmap = cmd->cmd_sg; 4209 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4210 4211 /* 4212 * First fill in the main frame 4213 */ 4214 for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) { 4215 ddi_put32(acc_hdl, &sge->Address.Low, 4216 dmap->addr.address64.Low); 4217 ddi_put32(acc_hdl, &sge->Address.High, 4218 dmap->addr.address64.High); 4219 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count); 4220 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4221 flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4222 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4223 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4224 MPI2_SGE_FLAGS_SHIFT); 4225 4226 /* 4227 * If this is the last SGE of this frame 4228 * we set the end of list flag 4229 */ 4230 if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) { 4231 flags |= ((uint32_t) 4232 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4233 MPI2_SGE_FLAGS_SHIFT); 4234 } 4235 if (cmd->cmd_flags & CFLAG_DMASEND) { 4236 flags |= 4237 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4238 MPI2_SGE_FLAGS_SHIFT); 4239 } else { 4240 flags |= 4241 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4242 MPI2_SGE_FLAGS_SHIFT); 4243 } 4244 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4245 dmap++; 4246 sge++; 4247 } 4248 4249 /* 4250 * Fill in the chain element in the main frame. 4251 * About calculation on ChainOffset: 4252 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4253 * in the end reserved for SGL element storage 4254 * (MPI2_SGE_IO_UNION); we should count it in our 4255 * calculation. See its definition in the header file. 4256 * 2. Constant j is the counter of the current SGL element 4257 * that will be processed, and (j - 1) is the number of 4258 * SGL elements that have been processed (stored in the 4259 * main frame). 4260 * 3. ChainOffset value should be in units of double-words (4 4261 * bytes) so the last value should be divided by 4. 4262 */ 4263 ddi_put8(acc_hdl, &frame->ChainOffset, 4264 (sizeof (MPI2_SCSI_IO_REQUEST) - 4265 sizeof (MPI2_SGE_IO_UNION) + 4266 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4267 sgechain = (pMpi2SGEChain64_t)sge; 4268 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4269 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4270 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4271 ddi_put8(acc_hdl, &sgechain->Flags, chainflags); 4272 4273 /* 4274 * The size of the next frame is the accurate size of space 4275 * (in bytes) used to store the SGL elements. j is the counter 4276 * of SGL elements. (j - 1) is the number of SGL elements that 4277 * have been processed (stored in frames). 4278 */ 4279 if (frames >= 2) { 4280 chainlength = mpt->m_req_frame_size / 4281 sizeof (MPI2_SGE_SIMPLE64) * 4282 sizeof (MPI2_SGE_SIMPLE64); 4283 } else { 4284 chainlength = ((cookiec - (j - 1)) * 4285 sizeof (MPI2_SGE_SIMPLE64)); 4286 } 4287 4288 p = cmd->cmd_extra_frames; 4289 4290 ddi_put16(acc_hdl, &sgechain->Length, chainlength); 4291 ddi_put32(acc_hdl, &sgechain->Address.Low, 4292 p->m_phys_addr); 4293 /* SGL is allocated in the first 4G mem range */ 4294 ddi_put32(acc_hdl, &sgechain->Address.High, 0); 4295 4296 /* 4297 * If there are more than 2 frames left we have to 4298 * fill in the next chain offset to the location of 4299 * the chain element in the next frame. 4300 * sgemax is the number of simple elements in an extra 4301 * frame. Note that the value NextChainOffset should be 4302 * in double-words (4 bytes). 4303 */ 4304 if (frames >= 2) { 4305 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 4306 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4307 } else { 4308 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0); 4309 } 4310 4311 /* 4312 * Jump to next frame; 4313 * Starting here, chain buffers go into the per command SGL. 4314 * This buffer is allocated when chain buffers are needed. 4315 */ 4316 sge = (pMpi2SGESimple64_t)p->m_frames_addr; 4317 i = cookiec; 4318 4319 /* 4320 * Start filling in frames with SGE's. If we 4321 * reach the end of frame and still have SGE's 4322 * to fill we need to add a chain element and 4323 * use another frame. j will be our counter 4324 * for what cookie we are at and i will be 4325 * the total cookiec. k is the current frame 4326 */ 4327 for (k = 1; k <= frames; k++) { 4328 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4329 4330 /* 4331 * If we have reached the end of frame 4332 * and we have more SGE's to fill in 4333 * we have to fill the final entry 4334 * with a chain element and then 4335 * continue to the next frame 4336 */ 4337 if ((l == (sgemax + 1)) && (k != frames)) { 4338 sgechain = (pMpi2SGEChain64_t)sge; 4339 j--; 4340 chainflags = ( 4341 MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4342 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4343 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4344 ddi_put8(p->m_acc_hdl, 4345 &sgechain->Flags, chainflags); 4346 /* 4347 * k is the frame counter and (k + 1) 4348 * is the number of the next frame. 4349 * Note that frames are in contiguous 4350 * memory space. 4351 */ 4352 ddi_put32(p->m_acc_hdl, 4353 &sgechain->Address.Low, 4354 (p->m_phys_addr + 4355 (mpt->m_req_frame_size * k))); 4356 ddi_put32(p->m_acc_hdl, 4357 &sgechain->Address.High, 0); 4358 4359 /* 4360 * If there are more than 2 frames left 4361 * we have to next chain offset to 4362 * the location of the chain element 4363 * in the next frame and fill in the 4364 * length of the next chain 4365 */ 4366 if ((frames - k) >= 2) { 4367 ddi_put8(p->m_acc_hdl, 4368 &sgechain->NextChainOffset, 4369 (sgemax * 4370 sizeof (MPI2_SGE_SIMPLE64)) 4371 >> 2); 4372 ddi_put16(p->m_acc_hdl, 4373 &sgechain->Length, 4374 mpt->m_req_frame_size / 4375 sizeof (MPI2_SGE_SIMPLE64) * 4376 sizeof (MPI2_SGE_SIMPLE64)); 4377 } else { 4378 /* 4379 * This is the last frame. Set 4380 * the NextChainOffset to 0 and 4381 * Length is the total size of 4382 * all remaining simple elements 4383 */ 4384 ddi_put8(p->m_acc_hdl, 4385 &sgechain->NextChainOffset, 4386 0); 4387 ddi_put16(p->m_acc_hdl, 4388 &sgechain->Length, 4389 (cookiec - j) * 4390 sizeof (MPI2_SGE_SIMPLE64)); 4391 } 4392 4393 /* Jump to the next frame */ 4394 sge = (pMpi2SGESimple64_t) 4395 ((char *)p->m_frames_addr + 4396 (int)mpt->m_req_frame_size * k); 4397 4398 continue; 4399 } 4400 4401 ddi_put32(p->m_acc_hdl, 4402 &sge->Address.Low, 4403 dmap->addr.address64.Low); 4404 ddi_put32(p->m_acc_hdl, 4405 &sge->Address.High, 4406 dmap->addr.address64.High); 4407 ddi_put32(p->m_acc_hdl, 4408 &sge->FlagsLength, dmap->count); 4409 flags = ddi_get32(p->m_acc_hdl, 4410 &sge->FlagsLength); 4411 flags |= ((uint32_t)( 4412 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4413 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4414 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4415 MPI2_SGE_FLAGS_SHIFT); 4416 4417 /* 4418 * If we are at the end of the frame and 4419 * there is another frame to fill in 4420 * we set the last simple element as last 4421 * element 4422 */ 4423 if ((l == sgemax) && (k != frames)) { 4424 flags |= ((uint32_t) 4425 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4426 MPI2_SGE_FLAGS_SHIFT); 4427 } 4428 4429 /* 4430 * If this is the final cookie we 4431 * indicate it by setting the flags 4432 */ 4433 if (j == i) { 4434 flags |= ((uint32_t) 4435 (MPI2_SGE_FLAGS_LAST_ELEMENT | 4436 MPI2_SGE_FLAGS_END_OF_BUFFER | 4437 MPI2_SGE_FLAGS_END_OF_LIST) << 4438 MPI2_SGE_FLAGS_SHIFT); 4439 } 4440 if (cmd->cmd_flags & CFLAG_DMASEND) { 4441 flags |= 4442 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4443 MPI2_SGE_FLAGS_SHIFT); 4444 } else { 4445 flags |= 4446 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4447 MPI2_SGE_FLAGS_SHIFT); 4448 } 4449 ddi_put32(p->m_acc_hdl, 4450 &sge->FlagsLength, flags); 4451 dmap++; 4452 sge++; 4453 } 4454 } 4455 4456 /* 4457 * Sync DMA with the chain buffers that were just created 4458 */ 4459 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 4460 } 4461 } 4462 4463 /* 4464 * Interrupt handling 4465 * Utility routine. Poll for status of a command sent to HBA 4466 * without interrupts (a FLAG_NOINTR command). 4467 */ 4468 int 4469 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime) 4470 { 4471 int rval = TRUE; 4472 4473 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd)); 4474 4475 /* 4476 * In order to avoid using m_mutex in ISR(a new separate mutex 4477 * m_intr_mutex is introduced) and keep the same lock logic, 4478 * the m_intr_mutex should be used to protect the getting and 4479 * setting of the ReplyDescriptorIndex. 4480 * 4481 * Since the m_intr_mutex would be released during processing the poll 4482 * cmd, so we should set the poll flag earlier here to make sure the 4483 * polled cmd be handled in this thread/context. A side effect is other 4484 * cmds during the period between the flag set and reset are also 4485 * handled in this thread and not the ISR. Since the poll cmd is not 4486 * so common, so the performance degradation in this case is not a big 4487 * issue. 4488 */ 4489 mutex_enter(&mpt->m_intr_mutex); 4490 mpt->m_polled_intr = 1; 4491 mutex_exit(&mpt->m_intr_mutex); 4492 4493 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 4494 mptsas_restart_hba(mpt); 4495 } 4496 4497 /* 4498 * Wait, using drv_usecwait(), long enough for the command to 4499 * reasonably return from the target if the target isn't 4500 * "dead". A polled command may well be sent from scsi_poll, and 4501 * there are retries built in to scsi_poll if the transport 4502 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second 4503 * and retries the transport up to scsi_poll_busycnt times 4504 * (currently 60) if 4505 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or 4506 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY 4507 * 4508 * limit the waiting to avoid a hang in the event that the 4509 * cmd never gets started but we are still receiving interrupts 4510 */ 4511 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) { 4512 if (mptsas_wait_intr(mpt, polltime) == FALSE) { 4513 NDBG5(("mptsas_poll: command incomplete")); 4514 rval = FALSE; 4515 break; 4516 } 4517 } 4518 4519 mutex_enter(&mpt->m_intr_mutex); 4520 mpt->m_polled_intr = 0; 4521 mutex_exit(&mpt->m_intr_mutex); 4522 4523 if (rval == FALSE) { 4524 4525 /* 4526 * this isn't supposed to happen, the hba must be wedged 4527 * Mark this cmd as a timeout. 4528 */ 4529 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT, 4530 (STAT_TIMEOUT|STAT_ABORTED)); 4531 4532 if (poll_cmd->cmd_queued == FALSE) { 4533 4534 NDBG5(("mptsas_poll: not on waitq")); 4535 4536 poll_cmd->cmd_pkt->pkt_state |= 4537 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD); 4538 } else { 4539 4540 /* find and remove it from the waitq */ 4541 NDBG5(("mptsas_poll: delete from waitq")); 4542 mptsas_waitq_delete(mpt, poll_cmd); 4543 } 4544 4545 } 4546 mptsas_fma_check(mpt, poll_cmd); 4547 NDBG5(("mptsas_poll: done")); 4548 return (rval); 4549 } 4550 4551 /* 4552 * Used for polling cmds and TM function 4553 */ 4554 static int 4555 mptsas_wait_intr(mptsas_t *mpt, int polltime) 4556 { 4557 int cnt; 4558 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 4559 Mpi2ReplyDescriptorsUnion_t reply_desc_union_v; 4560 uint32_t int_mask; 4561 uint8_t reply_type; 4562 4563 NDBG5(("mptsas_wait_intr")); 4564 4565 4566 /* 4567 * Get the current interrupt mask and disable interrupts. When 4568 * re-enabling ints, set mask to saved value. 4569 */ 4570 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask); 4571 MPTSAS_DISABLE_INTR(mpt); 4572 4573 /* 4574 * Keep polling for at least (polltime * 1000) seconds 4575 */ 4576 for (cnt = 0; cnt < polltime; cnt++) { 4577 mutex_enter(&mpt->m_intr_mutex); 4578 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 4579 DDI_DMA_SYNC_FORCPU); 4580 4581 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 4582 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 4583 4584 if (ddi_get32(mpt->m_acc_post_queue_hdl, 4585 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 4586 ddi_get32(mpt->m_acc_post_queue_hdl, 4587 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 4588 mutex_exit(&mpt->m_intr_mutex); 4589 drv_usecwait(1000); 4590 continue; 4591 } 4592 4593 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 4594 &reply_desc_union->Default.ReplyFlags); 4595 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 4596 reply_desc_union_v.Default.ReplyFlags = reply_type; 4597 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 4598 reply_desc_union_v.SCSIIOSuccess.SMID = 4599 ddi_get16(mpt->m_acc_post_queue_hdl, 4600 &reply_desc_union->SCSIIOSuccess.SMID); 4601 } else if (reply_type == 4602 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 4603 reply_desc_union_v.AddressReply.ReplyFrameAddress = 4604 ddi_get32(mpt->m_acc_post_queue_hdl, 4605 &reply_desc_union->AddressReply.ReplyFrameAddress); 4606 reply_desc_union_v.AddressReply.SMID = 4607 ddi_get16(mpt->m_acc_post_queue_hdl, 4608 &reply_desc_union->AddressReply.SMID); 4609 } 4610 /* 4611 * Clear the reply descriptor for re-use and increment 4612 * index. 4613 */ 4614 ddi_put64(mpt->m_acc_post_queue_hdl, 4615 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index], 4616 0xFFFFFFFFFFFFFFFF); 4617 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 4618 DDI_DMA_SYNC_FORDEV); 4619 4620 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 4621 mpt->m_post_index = 0; 4622 } 4623 4624 /* 4625 * Update the global reply index 4626 */ 4627 ddi_put32(mpt->m_datap, 4628 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 4629 mutex_exit(&mpt->m_intr_mutex); 4630 4631 /* 4632 * The reply is valid, process it according to its 4633 * type. 4634 */ 4635 mptsas_process_intr(mpt, &reply_desc_union_v); 4636 4637 4638 /* 4639 * Re-enable interrupts and quit. 4640 */ 4641 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, 4642 int_mask); 4643 return (TRUE); 4644 4645 } 4646 4647 /* 4648 * Clear polling flag, re-enable interrupts and quit. 4649 */ 4650 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask); 4651 return (FALSE); 4652 } 4653 4654 /* 4655 * For fastpath, the m_intr_mutex should be held from the begining to the end, 4656 * so we only treat those cmds that need not release m_intr_mutex(even just for 4657 * a moment) as candidate for fast processing. otherwise, we don't handle them 4658 * and just return, then in ISR, those cmds would be handled later with m_mutex 4659 * held and m_intr_mutex not held. 4660 */ 4661 static int 4662 mptsas_handle_io_fastpath(mptsas_t *mpt, 4663 uint16_t SMID) 4664 { 4665 mptsas_slots_t *slots = mpt->m_active; 4666 mptsas_cmd_t *cmd = NULL; 4667 struct scsi_pkt *pkt; 4668 4669 /* 4670 * This is a success reply so just complete the IO. First, do a sanity 4671 * check on the SMID. The final slot is used for TM requests, which 4672 * would not come into this reply handler. 4673 */ 4674 if ((SMID == 0) || (SMID > slots->m_n_slots)) { 4675 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 4676 SMID); 4677 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4678 return (TRUE); 4679 } 4680 4681 cmd = slots->m_slot[SMID]; 4682 4683 /* 4684 * print warning and return if the slot is empty 4685 */ 4686 if (cmd == NULL) { 4687 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 4688 "in slot %d", SMID); 4689 return (TRUE); 4690 } 4691 4692 pkt = CMD2PKT(cmd); 4693 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 4694 STATE_GOT_STATUS); 4695 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4696 pkt->pkt_state |= STATE_XFERRED_DATA; 4697 } 4698 pkt->pkt_resid = 0; 4699 4700 /* 4701 * If the cmd is a IOC, or a passthrough, then we don't process it in 4702 * fastpath, and later it would be handled by mptsas_process_intr() 4703 * with m_mutex protected. 4704 */ 4705 if (cmd->cmd_flags & (CFLAG_PASSTHRU | CFLAG_CMDIOC)) { 4706 return (FALSE); 4707 } else { 4708 mptsas_remove_cmd0(mpt, cmd); 4709 } 4710 4711 if (cmd->cmd_flags & CFLAG_RETRY) { 4712 /* 4713 * The target returned QFULL or busy, do not add tihs 4714 * pkt to the doneq since the hba will retry 4715 * this cmd. 4716 * 4717 * The pkt has already been resubmitted in 4718 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 4719 * Remove this cmd_flag here. 4720 */ 4721 cmd->cmd_flags &= ~CFLAG_RETRY; 4722 } else { 4723 mptsas_doneq_add0(mpt, cmd); 4724 } 4725 4726 /* 4727 * In fastpath, the cmd should only be a context reply, so just check 4728 * the post queue of the reply descriptor and the dmahandle of the cmd 4729 * is enough. No sense data in this case and no need to check the dma 4730 * handle where sense data dma info is saved, the dma handle of the 4731 * reply frame, and the dma handle of the reply free queue. 4732 * For the dma handle of the request queue. Check fma here since we 4733 * are sure the request must have already been sent/DMAed correctly. 4734 * otherwise checking in mptsas_scsi_start() is not correct since 4735 * at that time the dma may not start. 4736 */ 4737 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 4738 DDI_SUCCESS) || 4739 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 4740 DDI_SUCCESS)) { 4741 ddi_fm_service_impact(mpt->m_dip, 4742 DDI_SERVICE_UNAFFECTED); 4743 pkt->pkt_reason = CMD_TRAN_ERR; 4744 pkt->pkt_statistics = 0; 4745 } 4746 if (cmd->cmd_dmahandle && 4747 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) { 4748 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4749 pkt->pkt_reason = CMD_TRAN_ERR; 4750 pkt->pkt_statistics = 0; 4751 } 4752 if ((cmd->cmd_extra_frames && 4753 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) != 4754 DDI_SUCCESS) || 4755 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) != 4756 DDI_SUCCESS)))) { 4757 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4758 pkt->pkt_reason = CMD_TRAN_ERR; 4759 pkt->pkt_statistics = 0; 4760 } 4761 4762 return (TRUE); 4763 } 4764 4765 static void 4766 mptsas_handle_scsi_io_success(mptsas_t *mpt, 4767 pMpi2ReplyDescriptorsUnion_t reply_desc) 4768 { 4769 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success; 4770 uint16_t SMID; 4771 mptsas_slots_t *slots = mpt->m_active; 4772 mptsas_cmd_t *cmd = NULL; 4773 struct scsi_pkt *pkt; 4774 4775 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc; 4776 SMID = scsi_io_success->SMID; 4777 4778 /* 4779 * This is a success reply so just complete the IO. First, do a sanity 4780 * check on the SMID. The final slot is used for TM requests, which 4781 * would not come into this reply handler. 4782 */ 4783 if ((SMID == 0) || (SMID > slots->m_n_slots)) { 4784 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 4785 SMID); 4786 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4787 return; 4788 } 4789 4790 cmd = slots->m_slot[SMID]; 4791 4792 /* 4793 * print warning and return if the slot is empty 4794 */ 4795 if (cmd == NULL) { 4796 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 4797 "in slot %d", SMID); 4798 return; 4799 } 4800 4801 pkt = CMD2PKT(cmd); 4802 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 4803 STATE_GOT_STATUS); 4804 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4805 pkt->pkt_state |= STATE_XFERRED_DATA; 4806 } 4807 pkt->pkt_resid = 0; 4808 4809 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 4810 cmd->cmd_flags |= CFLAG_FINISHED; 4811 cv_broadcast(&mpt->m_passthru_cv); 4812 return; 4813 } else { 4814 mptsas_remove_cmd(mpt, cmd); 4815 } 4816 4817 if (cmd->cmd_flags & CFLAG_RETRY) { 4818 /* 4819 * The target returned QFULL or busy, do not add tihs 4820 * pkt to the doneq since the hba will retry 4821 * this cmd. 4822 * 4823 * The pkt has already been resubmitted in 4824 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 4825 * Remove this cmd_flag here. 4826 */ 4827 cmd->cmd_flags &= ~CFLAG_RETRY; 4828 } else { 4829 mptsas_doneq_add(mpt, cmd); 4830 } 4831 } 4832 4833 static void 4834 mptsas_handle_address_reply(mptsas_t *mpt, 4835 pMpi2ReplyDescriptorsUnion_t reply_desc) 4836 { 4837 pMpi2AddressReplyDescriptor_t address_reply; 4838 pMPI2DefaultReply_t reply; 4839 mptsas_fw_diagnostic_buffer_t *pBuffer; 4840 uint32_t reply_addr; 4841 uint16_t SMID, iocstatus; 4842 mptsas_slots_t *slots = mpt->m_active; 4843 mptsas_cmd_t *cmd = NULL; 4844 uint8_t function, buffer_type; 4845 m_replyh_arg_t *args; 4846 int reply_frame_no; 4847 4848 ASSERT(mutex_owned(&mpt->m_mutex)); 4849 4850 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc; 4851 4852 reply_addr = address_reply->ReplyFrameAddress; 4853 SMID = address_reply->SMID; 4854 /* 4855 * If reply frame is not in the proper range we should ignore this 4856 * message and exit the interrupt handler. 4857 */ 4858 if ((reply_addr < mpt->m_reply_frame_dma_addr) || 4859 (reply_addr >= (mpt->m_reply_frame_dma_addr + 4860 (mpt->m_reply_frame_size * mpt->m_max_replies))) || 4861 ((reply_addr - mpt->m_reply_frame_dma_addr) % 4862 mpt->m_reply_frame_size != 0)) { 4863 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame " 4864 "address 0x%x\n", reply_addr); 4865 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4866 return; 4867 } 4868 4869 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 4870 DDI_DMA_SYNC_FORCPU); 4871 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr - 4872 mpt->m_reply_frame_dma_addr)); 4873 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function); 4874 4875 /* 4876 * don't get slot information and command for events since these values 4877 * don't exist 4878 */ 4879 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) && 4880 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) { 4881 /* 4882 * This could be a TM reply, which use the last allocated SMID, 4883 * so allow for that. 4884 */ 4885 if ((SMID == 0) || (SMID > (slots->m_n_slots + 1))) { 4886 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of " 4887 "%d\n", SMID); 4888 ddi_fm_service_impact(mpt->m_dip, 4889 DDI_SERVICE_UNAFFECTED); 4890 return; 4891 } 4892 4893 cmd = slots->m_slot[SMID]; 4894 4895 /* 4896 * print warning and return if the slot is empty 4897 */ 4898 if (cmd == NULL) { 4899 mptsas_log(mpt, CE_WARN, "?NULL command for address " 4900 "reply in slot %d", SMID); 4901 return; 4902 } 4903 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 4904 (cmd->cmd_flags & CFLAG_CONFIG) || 4905 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 4906 cmd->cmd_rfm = reply_addr; 4907 cmd->cmd_flags |= CFLAG_FINISHED; 4908 cv_broadcast(&mpt->m_passthru_cv); 4909 cv_broadcast(&mpt->m_config_cv); 4910 cv_broadcast(&mpt->m_fw_diag_cv); 4911 return; 4912 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) { 4913 mptsas_remove_cmd(mpt, cmd); 4914 } 4915 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID)); 4916 } 4917 /* 4918 * Depending on the function, we need to handle 4919 * the reply frame (and cmd) differently. 4920 */ 4921 switch (function) { 4922 case MPI2_FUNCTION_SCSI_IO_REQUEST: 4923 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd); 4924 break; 4925 case MPI2_FUNCTION_SCSI_TASK_MGMT: 4926 cmd->cmd_rfm = reply_addr; 4927 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply, 4928 cmd); 4929 break; 4930 case MPI2_FUNCTION_FW_DOWNLOAD: 4931 cmd->cmd_flags |= CFLAG_FINISHED; 4932 cv_signal(&mpt->m_fw_cv); 4933 break; 4934 case MPI2_FUNCTION_EVENT_NOTIFICATION: 4935 reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) / 4936 mpt->m_reply_frame_size; 4937 args = &mpt->m_replyh_args[reply_frame_no]; 4938 args->mpt = (void *)mpt; 4939 args->rfm = reply_addr; 4940 4941 /* 4942 * Record the event if its type is enabled in 4943 * this mpt instance by ioctl. 4944 */ 4945 mptsas_record_event(args); 4946 4947 /* 4948 * Handle time critical events 4949 * NOT_RESPONDING/ADDED only now 4950 */ 4951 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) { 4952 /* 4953 * Would not return main process, 4954 * just let taskq resolve ack action 4955 * and ack would be sent in taskq thread 4956 */ 4957 NDBG20(("send mptsas_handle_event_sync success")); 4958 } 4959 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event, 4960 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 4961 mptsas_log(mpt, CE_WARN, "No memory available" 4962 "for dispatch taskq"); 4963 /* 4964 * Return the reply frame to the free queue. 4965 */ 4966 ddi_put32(mpt->m_acc_free_queue_hdl, 4967 &((uint32_t *)(void *) 4968 mpt->m_free_queue)[mpt->m_free_index], reply_addr); 4969 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 4970 DDI_DMA_SYNC_FORDEV); 4971 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 4972 mpt->m_free_index = 0; 4973 } 4974 4975 ddi_put32(mpt->m_datap, 4976 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index); 4977 } 4978 return; 4979 case MPI2_FUNCTION_DIAG_BUFFER_POST: 4980 /* 4981 * If SMID is 0, this implies that the reply is due to a 4982 * release function with a status that the buffer has been 4983 * released. Set the buffer flags accordingly. 4984 */ 4985 if (SMID == 0) { 4986 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 4987 &reply->IOCStatus); 4988 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl, 4989 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType)); 4990 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) { 4991 pBuffer = 4992 &mpt->m_fw_diag_buffer_list[buffer_type]; 4993 pBuffer->valid_data = TRUE; 4994 pBuffer->owned_by_firmware = FALSE; 4995 pBuffer->immediate = FALSE; 4996 } 4997 } else { 4998 /* 4999 * Normal handling of diag post reply with SMID. 5000 */ 5001 cmd = slots->m_slot[SMID]; 5002 5003 /* 5004 * print warning and return if the slot is empty 5005 */ 5006 if (cmd == NULL) { 5007 mptsas_log(mpt, CE_WARN, "?NULL command for " 5008 "address reply in slot %d", SMID); 5009 return; 5010 } 5011 cmd->cmd_rfm = reply_addr; 5012 cmd->cmd_flags |= CFLAG_FINISHED; 5013 cv_broadcast(&mpt->m_fw_diag_cv); 5014 } 5015 return; 5016 default: 5017 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function); 5018 break; 5019 } 5020 5021 /* 5022 * Return the reply frame to the free queue. 5023 */ 5024 ddi_put32(mpt->m_acc_free_queue_hdl, 5025 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 5026 reply_addr); 5027 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5028 DDI_DMA_SYNC_FORDEV); 5029 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5030 mpt->m_free_index = 0; 5031 } 5032 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 5033 mpt->m_free_index); 5034 5035 if (cmd->cmd_flags & CFLAG_FW_CMD) 5036 return; 5037 5038 if (cmd->cmd_flags & CFLAG_RETRY) { 5039 /* 5040 * The target returned QFULL or busy, do not add tihs 5041 * pkt to the doneq since the hba will retry 5042 * this cmd. 5043 * 5044 * The pkt has already been resubmitted in 5045 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5046 * Remove this cmd_flag here. 5047 */ 5048 cmd->cmd_flags &= ~CFLAG_RETRY; 5049 } else { 5050 mptsas_doneq_add(mpt, cmd); 5051 } 5052 } 5053 5054 static void 5055 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 5056 mptsas_cmd_t *cmd) 5057 { 5058 uint8_t scsi_status, scsi_state; 5059 uint16_t ioc_status; 5060 uint32_t xferred, sensecount, responsedata, loginfo = 0; 5061 struct scsi_pkt *pkt; 5062 struct scsi_arq_status *arqstat; 5063 struct buf *bp; 5064 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5065 uint8_t *sensedata = NULL; 5066 5067 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) == 5068 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) { 5069 bp = cmd->cmd_ext_arq_buf; 5070 } else { 5071 bp = cmd->cmd_arq_buf; 5072 } 5073 5074 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus); 5075 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5076 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState); 5077 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount); 5078 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount); 5079 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl, 5080 &reply->ResponseInfo); 5081 5082 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 5083 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 5084 &reply->IOCLogInfo); 5085 mptsas_log(mpt, CE_NOTE, 5086 "?Log info 0x%x received for target %d.\n" 5087 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5088 loginfo, Tgt(cmd), scsi_status, ioc_status, 5089 scsi_state); 5090 } 5091 5092 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5093 scsi_status, ioc_status, scsi_state)); 5094 5095 pkt = CMD2PKT(cmd); 5096 *(pkt->pkt_scbp) = scsi_status; 5097 5098 if (loginfo == 0x31170000) { 5099 /* 5100 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY 5101 * 0x31170000 comes, that means the device missing delay 5102 * is in progressing, the command need retry later. 5103 */ 5104 *(pkt->pkt_scbp) = STATUS_BUSY; 5105 return; 5106 } 5107 5108 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) && 5109 ((ioc_status & MPI2_IOCSTATUS_MASK) == 5110 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) { 5111 pkt->pkt_reason = CMD_INCOMPLETE; 5112 pkt->pkt_state |= STATE_GOT_BUS; 5113 mutex_enter(&ptgt->m_tgt_intr_mutex); 5114 if (ptgt->m_reset_delay == 0) { 5115 mptsas_set_throttle(mpt, ptgt, 5116 DRAIN_THROTTLE); 5117 } 5118 mutex_exit(&ptgt->m_tgt_intr_mutex); 5119 return; 5120 } 5121 5122 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) { 5123 responsedata &= 0x000000FF; 5124 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) { 5125 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n"); 5126 pkt->pkt_reason = CMD_TLR_OFF; 5127 return; 5128 } 5129 } 5130 5131 5132 switch (scsi_status) { 5133 case MPI2_SCSI_STATUS_CHECK_CONDITION: 5134 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5135 arqstat = (void*)(pkt->pkt_scbp); 5136 arqstat->sts_rqpkt_status = *((struct scsi_status *) 5137 (pkt->pkt_scbp)); 5138 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 5139 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE); 5140 if (cmd->cmd_flags & CFLAG_XARQ) { 5141 pkt->pkt_state |= STATE_XARQ_DONE; 5142 } 5143 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5144 pkt->pkt_state |= STATE_XFERRED_DATA; 5145 } 5146 arqstat->sts_rqpkt_reason = pkt->pkt_reason; 5147 arqstat->sts_rqpkt_state = pkt->pkt_state; 5148 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA; 5149 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics; 5150 sensedata = (uint8_t *)&arqstat->sts_sensedata; 5151 5152 bcopy((uchar_t *)bp->b_un.b_addr, sensedata, 5153 ((cmd->cmd_rqslen >= sensecount) ? sensecount : 5154 cmd->cmd_rqslen)); 5155 arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount); 5156 cmd->cmd_flags |= CFLAG_CMDARQ; 5157 /* 5158 * Set proper status for pkt if autosense was valid 5159 */ 5160 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { 5161 struct scsi_status zero_status = { 0 }; 5162 arqstat->sts_rqpkt_status = zero_status; 5163 } 5164 5165 /* 5166 * ASC=0x47 is parity error 5167 * ASC=0x48 is initiator detected error received 5168 */ 5169 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) && 5170 ((scsi_sense_asc(sensedata) == 0x47) || 5171 (scsi_sense_asc(sensedata) == 0x48))) { 5172 mptsas_log(mpt, CE_NOTE, "Aborted_command!"); 5173 } 5174 5175 /* 5176 * ASC/ASCQ=0x3F/0x0E means report_luns data changed 5177 * ASC/ASCQ=0x25/0x00 means invalid lun 5178 */ 5179 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) && 5180 (scsi_sense_asc(sensedata) == 0x3F) && 5181 (scsi_sense_ascq(sensedata) == 0x0E)) || 5182 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) && 5183 (scsi_sense_asc(sensedata) == 0x25) && 5184 (scsi_sense_ascq(sensedata) == 0x00))) { 5185 mptsas_topo_change_list_t *topo_node = NULL; 5186 5187 topo_node = kmem_zalloc( 5188 sizeof (mptsas_topo_change_list_t), 5189 KM_NOSLEEP); 5190 if (topo_node == NULL) { 5191 mptsas_log(mpt, CE_NOTE, "No memory" 5192 "resource for handle SAS dynamic" 5193 "reconfigure.\n"); 5194 break; 5195 } 5196 topo_node->mpt = mpt; 5197 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET; 5198 topo_node->un.phymask = ptgt->m_phymask; 5199 topo_node->devhdl = ptgt->m_devhdl; 5200 topo_node->object = (void *)ptgt; 5201 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED; 5202 5203 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 5204 mptsas_handle_dr, 5205 (void *)topo_node, 5206 DDI_NOSLEEP)) != DDI_SUCCESS) { 5207 mptsas_log(mpt, CE_NOTE, "mptsas start taskq" 5208 "for handle SAS dynamic reconfigure" 5209 "failed. \n"); 5210 } 5211 } 5212 break; 5213 case MPI2_SCSI_STATUS_GOOD: 5214 switch (ioc_status & MPI2_IOCSTATUS_MASK) { 5215 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 5216 pkt->pkt_reason = CMD_DEV_GONE; 5217 pkt->pkt_state |= STATE_GOT_BUS; 5218 mutex_enter(&ptgt->m_tgt_intr_mutex); 5219 if (ptgt->m_reset_delay == 0) { 5220 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5221 } 5222 mutex_exit(&ptgt->m_tgt_intr_mutex); 5223 NDBG31(("lost disk for target%d, command:%x", 5224 Tgt(cmd), pkt->pkt_cdbp[0])); 5225 break; 5226 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 5227 NDBG31(("data overrun: xferred=%d", xferred)); 5228 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5229 pkt->pkt_reason = CMD_DATA_OVR; 5230 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5231 | STATE_SENT_CMD | STATE_GOT_STATUS 5232 | STATE_XFERRED_DATA); 5233 pkt->pkt_resid = 0; 5234 break; 5235 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 5236 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 5237 NDBG31(("data underrun: xferred=%d", xferred)); 5238 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5239 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5240 | STATE_SENT_CMD | STATE_GOT_STATUS); 5241 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5242 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5243 pkt->pkt_state |= STATE_XFERRED_DATA; 5244 } 5245 break; 5246 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 5247 mptsas_set_pkt_reason(mpt, 5248 cmd, CMD_RESET, STAT_BUS_RESET); 5249 break; 5250 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 5251 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 5252 mptsas_set_pkt_reason(mpt, 5253 cmd, CMD_RESET, STAT_DEV_RESET); 5254 break; 5255 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 5256 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 5257 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET); 5258 mptsas_set_pkt_reason(mpt, 5259 cmd, CMD_TERMINATED, STAT_TERMINATED); 5260 break; 5261 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 5262 case MPI2_IOCSTATUS_BUSY: 5263 /* 5264 * set throttles to drain 5265 */ 5266 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 5267 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST); 5268 while (ptgt != NULL) { 5269 mutex_enter(&ptgt->m_tgt_intr_mutex); 5270 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5271 mutex_exit(&ptgt->m_tgt_intr_mutex); 5272 5273 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 5274 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 5275 } 5276 5277 /* 5278 * retry command 5279 */ 5280 cmd->cmd_flags |= CFLAG_RETRY; 5281 cmd->cmd_pkt_flags |= FLAG_HEAD; 5282 5283 mutex_exit(&mpt->m_mutex); 5284 (void) mptsas_accept_pkt(mpt, cmd); 5285 mutex_enter(&mpt->m_mutex); 5286 break; 5287 default: 5288 mptsas_log(mpt, CE_WARN, 5289 "unknown ioc_status = %x\n", ioc_status); 5290 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer " 5291 "count = %x, scsi_status = %x", scsi_state, 5292 xferred, scsi_status); 5293 break; 5294 } 5295 break; 5296 case MPI2_SCSI_STATUS_TASK_SET_FULL: 5297 mptsas_handle_qfull(mpt, cmd); 5298 break; 5299 case MPI2_SCSI_STATUS_BUSY: 5300 NDBG31(("scsi_status busy received")); 5301 break; 5302 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT: 5303 NDBG31(("scsi_status reservation conflict received")); 5304 break; 5305 default: 5306 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n", 5307 scsi_status, ioc_status); 5308 mptsas_log(mpt, CE_WARN, 5309 "mptsas_process_intr: invalid scsi status\n"); 5310 break; 5311 } 5312 } 5313 5314 static void 5315 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply, 5316 mptsas_cmd_t *cmd) 5317 { 5318 uint8_t task_type; 5319 uint16_t ioc_status; 5320 uint32_t log_info; 5321 uint16_t dev_handle; 5322 struct scsi_pkt *pkt = CMD2PKT(cmd); 5323 5324 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType); 5325 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5326 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo); 5327 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle); 5328 5329 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5330 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x " 5331 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n", 5332 task_type, ioc_status, log_info, dev_handle); 5333 pkt->pkt_reason = CMD_INCOMPLETE; 5334 return; 5335 } 5336 5337 switch (task_type) { 5338 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 5339 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 5340 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 5341 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA: 5342 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET: 5343 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION: 5344 break; 5345 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 5346 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 5347 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 5348 /* 5349 * Check for invalid DevHandle of 0 in case application 5350 * sends bad command. DevHandle of 0 could cause problems. 5351 */ 5352 if (dev_handle == 0) { 5353 mptsas_log(mpt, CE_WARN, "!Can't flush target with" 5354 " DevHandle of 0."); 5355 } else { 5356 mptsas_flush_target(mpt, dev_handle, Lun(cmd), 5357 task_type); 5358 } 5359 break; 5360 default: 5361 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 5362 task_type); 5363 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status); 5364 break; 5365 } 5366 } 5367 5368 static void 5369 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg) 5370 { 5371 mptsas_t *mpt = arg->mpt; 5372 uint64_t t = arg->t; 5373 mptsas_cmd_t *cmd; 5374 struct scsi_pkt *pkt; 5375 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 5376 5377 mutex_enter(&item->mutex); 5378 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) { 5379 if (!item->doneq) { 5380 cv_wait(&item->cv, &item->mutex); 5381 } 5382 pkt = NULL; 5383 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) { 5384 cmd->cmd_flags |= CFLAG_COMPLETED; 5385 pkt = CMD2PKT(cmd); 5386 } 5387 mutex_exit(&item->mutex); 5388 if (pkt) { 5389 mptsas_pkt_comp(pkt, cmd); 5390 } 5391 mutex_enter(&item->mutex); 5392 } 5393 mutex_exit(&item->mutex); 5394 mutex_enter(&mpt->m_doneq_mutex); 5395 mpt->m_doneq_thread_n--; 5396 cv_broadcast(&mpt->m_doneq_thread_cv); 5397 mutex_exit(&mpt->m_doneq_mutex); 5398 } 5399 5400 /* 5401 * mpt interrupt handler. 5402 */ 5403 static uint_t 5404 mptsas_intr(caddr_t arg1, caddr_t arg2) 5405 { 5406 mptsas_t *mpt = (void *)arg1; 5407 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5408 uchar_t did_reply = FALSE; 5409 int i = 0, j; 5410 uint8_t reply_type; 5411 uint16_t SMID; 5412 5413 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2)); 5414 5415 /* 5416 * 1. 5417 * To avoid using m_mutex in the ISR(ISR referes not only mptsas_intr, 5418 * but all of the recursive called functions in it. the same below), 5419 * separate mutexs are introduced to protect the elements shown in ISR. 5420 * 3 type of mutex are involved here: 5421 * a)per instance mutex m_intr_mutex. 5422 * b)per target mutex m_tgt_intr_mutex. 5423 * c)mutex that protect the free slot. 5424 * 5425 * a)per instance mutex m_intr_mutex: 5426 * used to protect m_options, m_power, m_waitq, etc that would be 5427 * checked/modified in ISR; protect the getting and setting the reply 5428 * descriptor index; protect the m_slots[]; 5429 * 5430 * b)per target mutex m_tgt_intr_mutex: 5431 * used to protect per target element which has relationship to ISR. 5432 * contention for the new per target mutex is just as high as it in 5433 * sd(7d) driver. 5434 * 5435 * c)mutexs that protect the free slots: 5436 * those mutexs are introduced to minimize the mutex contentions 5437 * between the IO request threads where free slots are allocated 5438 * for sending cmds and ISR where slots holding outstanding cmds 5439 * are returned to the free pool. 5440 * the idea is like this: 5441 * 1) Partition all of the free slot into NCPU groups. For example, 5442 * In system where we have 15 slots, and 4 CPU, then slot s1,s5,s9,s13 5443 * are marked belonging to CPU1, s2,s6,s10,s14 to CPU2, s3,s7,s11,s15 5444 * to CPU3, and s4,s8,s12 to CPU4. 5445 * 2) In each of the group, an alloc/release queue pair is created, 5446 * and both the allocq and the releaseq have a dedicated mutex. 5447 * 3) When init, all of the slots in a CPU group are inserted into the 5448 * allocq of its CPU's pair. 5449 * 4) When doing IO, 5450 * mptsas_scsi_start() 5451 * { 5452 * cpuid = the cpu NO of the cpu where this thread is running on 5453 * retry: 5454 * mutex_enter(&allocq[cpuid]); 5455 * if (get free slot = success) { 5456 * remove the slot from the allocq 5457 * mutex_exit(&allocq[cpuid]); 5458 * return(success); 5459 * } else { // exchange allocq and releaseq and try again 5460 * mutex_enter(&releq[cpuid]); 5461 * exchange the allocq and releaseq of this pair; 5462 * mutex_exit(&releq[cpuid]); 5463 * if (try to get free slot again = success) { 5464 * remove the slot from the allocq 5465 * mutex_exit(&allocq[cpuid]); 5466 * return(success); 5467 * } else { 5468 * MOD(cpuid)++; 5469 * goto retry; 5470 * if (all CPU groups tried) 5471 * mutex_exit(&allocq[cpuid]); 5472 * return(failure); 5473 * } 5474 * } 5475 * } 5476 * ISR() 5477 * { 5478 * cpuid = the CPU group id where the slot sending the 5479 * cmd belongs; 5480 * mutex_enter(&releq[cpuid]); 5481 * remove the slot from the releaseq 5482 * mutex_exit(&releq[cpuid]); 5483 * } 5484 * This way, only when the queue pair doing exchange have mutex 5485 * contentions. 5486 * 5487 * For mutex m_intr_mutex and m_tgt_intr_mutex, there are 2 scenarios: 5488 * 5489 * a)If the elements are only checked but not modified in the ISR, then 5490 * only the places where those elements are modifed(outside of ISR) 5491 * need to be protected by the new introduced mutex. 5492 * For example, data A is only read/checked in ISR, then we need do 5493 * like this: 5494 * In ISR: 5495 * { 5496 * mutex_enter(&new_mutex); 5497 * read(A); 5498 * mutex_exit(&new_mutex); 5499 * //the new_mutex here is either the m_tgt_intr_mutex or 5500 * //the m_intr_mutex. 5501 * } 5502 * In non-ISR 5503 * { 5504 * mutex_enter(&m_mutex); //the stock driver already did this 5505 * mutex_enter(&new_mutex); 5506 * write(A); 5507 * mutex_exit(&new_mutex); 5508 * mutex_exit(&m_mutex); //the stock driver already did this 5509 * 5510 * read(A); 5511 * // read(A) in non-ISR is not required to be protected by new 5512 * // mutex since 'A' has already been protected by m_mutex 5513 * // outside of the ISR 5514 * } 5515 * 5516 * Those fields in mptsas_target_t/ptgt which are only read in ISR 5517 * fall into this catergory. So they, together with the fields which 5518 * are never read in ISR, are not necessary to be protected by 5519 * m_tgt_intr_mutex, don't bother. 5520 * checking of m_waitq also falls into this catergory. so all of the 5521 * place outside of ISR where the m_waitq is modified, such as in 5522 * mptsas_waitq_add(), mptsas_waitq_delete(), mptsas_waitq_rm(), 5523 * m_intr_mutex should be used. 5524 * 5525 * b)If the elements are modified in the ISR, then each place where 5526 * those elements are referred(outside of ISR) need to be protected 5527 * by the new introduced mutex. Of course, if those elements only 5528 * appear in the non-key code path, that is, they don't affect 5529 * performance, then the m_mutex can still be used as before. 5530 * For example, data B is modified in key code path in ISR, and data C 5531 * is modified in non-key code path in ISR, then we can do like this: 5532 * In ISR: 5533 * { 5534 * mutex_enter(&new_mutex); 5535 * wirte(B); 5536 * mutex_exit(&new_mutex); 5537 * if (seldom happen) { 5538 * mutex_enter(&m_mutex); 5539 * write(C); 5540 * mutex_exit(&m_mutex); 5541 * } 5542 * //the new_mutex here is either the m_tgt_intr_mutex or 5543 * //the m_intr_mutex. 5544 * } 5545 * In non-ISR 5546 * { 5547 * mutex_enter(&new_mutex); 5548 * write(B); 5549 * mutex_exit(&new_mutex); 5550 * 5551 * mutex_enter(&new_mutex); 5552 * read(B); 5553 * mutex_exit(&new_mutex); 5554 * // both write(B) and read(B) in non-ISR is required to be 5555 * // protected by new mutex outside of the ISR 5556 * 5557 * mutex_enter(&m_mutex); //the stock driver already did this 5558 * read(C); 5559 * write(C); 5560 * mutex_exit(&m_mutex); //the stock driver already did this 5561 * // both write(C) and read(C) in non-ISR have been already 5562 * // been protected by m_mutex outside of the ISR 5563 * } 5564 * 5565 * For example, ptgt->m_t_ncmds fall into 'B' of this catergory, and 5566 * elements shown in address reply, restart_hba, passthrough, IOC 5567 * fall into 'C' of this catergory. 5568 * 5569 * In any case where mutexs are nested, make sure in the following 5570 * order: 5571 * m_mutex -> m_intr_mutex -> m_tgt_intr_mutex 5572 * m_intr_mutex -> m_tgt_intr_mutex 5573 * m_mutex -> m_intr_mutex 5574 * m_mutex -> m_tgt_intr_mutex 5575 * 5576 * 2. 5577 * Make sure at any time, getting the ReplyDescriptor by m_post_index 5578 * and setting m_post_index to the ReplyDescriptorIndex register are 5579 * atomic. Since m_mutex is not used for this purpose in ISR, the new 5580 * mutex m_intr_mutex must play this role. So mptsas_poll(), where this 5581 * kind of getting/setting is also performed, must use m_intr_mutex. 5582 * Note, since context reply in ISR/process_intr is the only code path 5583 * which affect performance, a fast path is introduced to only handle 5584 * the read/write IO having context reply. For other IOs such as 5585 * passthrough and IOC with context reply and all address reply, we 5586 * use the as-is process_intr() to handle them. In order to keep the 5587 * same semantics in process_intr(), make sure any new mutex is not held 5588 * before enterring it. 5589 */ 5590 5591 mutex_enter(&mpt->m_intr_mutex); 5592 5593 /* 5594 * If interrupts are shared by two channels then check whether this 5595 * interrupt is genuinely for this channel by making sure first the 5596 * chip is in high power state. 5597 */ 5598 if ((mpt->m_options & MPTSAS_OPT_PM) && 5599 (mpt->m_power_level != PM_LEVEL_D0)) { 5600 mutex_exit(&mpt->m_intr_mutex); 5601 return (DDI_INTR_UNCLAIMED); 5602 } 5603 5604 /* 5605 * If polling, interrupt was triggered by some shared interrupt because 5606 * IOC interrupts are disabled during polling, so polling routine will 5607 * handle any replies. Considering this, if polling is happening, 5608 * return with interrupt unclaimed. 5609 */ 5610 if (mpt->m_polled_intr) { 5611 mutex_exit(&mpt->m_intr_mutex); 5612 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt"); 5613 return (DDI_INTR_UNCLAIMED); 5614 } 5615 5616 /* 5617 * Read the istat register. 5618 */ 5619 if ((INTPENDING(mpt)) != 0) { 5620 /* 5621 * read fifo until empty. 5622 */ 5623 #ifndef __lock_lint 5624 _NOTE(CONSTCOND) 5625 #endif 5626 while (TRUE) { 5627 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5628 DDI_DMA_SYNC_FORCPU); 5629 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5630 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5631 5632 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5633 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5634 ddi_get32(mpt->m_acc_post_queue_hdl, 5635 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5636 break; 5637 } 5638 5639 /* 5640 * The reply is valid, process it according to its 5641 * type. Also, set a flag for updating the reply index 5642 * after they've all been processed. 5643 */ 5644 did_reply = TRUE; 5645 5646 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 5647 &reply_desc_union->Default.ReplyFlags); 5648 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 5649 mpt->m_reply[i].Default.ReplyFlags = reply_type; 5650 if (reply_type == 5651 MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 5652 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, 5653 &reply_desc_union->SCSIIOSuccess.SMID); 5654 if (mptsas_handle_io_fastpath(mpt, SMID) != 5655 TRUE) { 5656 mpt->m_reply[i].SCSIIOSuccess.SMID = 5657 SMID; 5658 i++; 5659 } 5660 } else if (reply_type == 5661 MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 5662 mpt->m_reply[i].AddressReply.ReplyFrameAddress = 5663 ddi_get32(mpt->m_acc_post_queue_hdl, 5664 &reply_desc_union->AddressReply. 5665 ReplyFrameAddress); 5666 mpt->m_reply[i].AddressReply.SMID = 5667 ddi_get16(mpt->m_acc_post_queue_hdl, 5668 &reply_desc_union->AddressReply.SMID); 5669 i++; 5670 } 5671 /* 5672 * Clear the reply descriptor for re-use and increment 5673 * index. 5674 */ 5675 ddi_put64(mpt->m_acc_post_queue_hdl, 5676 &((uint64_t *)(void *)mpt->m_post_queue) 5677 [mpt->m_post_index], 0xFFFFFFFFFFFFFFFF); 5678 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5679 DDI_DMA_SYNC_FORDEV); 5680 5681 /* 5682 * Increment post index and roll over if needed. 5683 */ 5684 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5685 mpt->m_post_index = 0; 5686 } 5687 if (i >= MPI_ADDRESS_COALSCE_MAX) 5688 break; 5689 } 5690 5691 /* 5692 * Update the global reply index if at least one reply was 5693 * processed. 5694 */ 5695 if (did_reply) { 5696 ddi_put32(mpt->m_datap, 5697 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5698 5699 /* 5700 * For fma, only check the PIO is required and enough 5701 * here. Those cases where fastpath is not hit, the 5702 * mptsas_fma_check() check all of the types of 5703 * fma. That is not necessary and sometimes not 5704 * correct. fma check should only be done after 5705 * the PIO and/or dma is performed. 5706 */ 5707 if ((mptsas_check_acc_handle(mpt->m_datap) != 5708 DDI_SUCCESS)) { 5709 ddi_fm_service_impact(mpt->m_dip, 5710 DDI_SERVICE_UNAFFECTED); 5711 } 5712 5713 } 5714 } else { 5715 mutex_exit(&mpt->m_intr_mutex); 5716 return (DDI_INTR_UNCLAIMED); 5717 } 5718 NDBG1(("mptsas_intr complete")); 5719 mutex_exit(&mpt->m_intr_mutex); 5720 5721 /* 5722 * Since most of the cmds(read and write IO with success return.) 5723 * have already been processed in fast path in which the m_mutex 5724 * is not held, handling here the address reply and other context reply 5725 * such as passthrough and IOC cmd with m_mutex held should be a big 5726 * issue for performance. 5727 * If holding m_mutex to process these cmds was still an obvious issue, 5728 * we can process them in a taskq. 5729 */ 5730 for (j = 0; j < i; j++) { 5731 mutex_enter(&mpt->m_mutex); 5732 mptsas_process_intr(mpt, &mpt->m_reply[j]); 5733 mutex_exit(&mpt->m_mutex); 5734 } 5735 5736 /* 5737 * If no helper threads are created, process the doneq in ISR. If 5738 * helpers are created, use the doneq length as a metric to measure the 5739 * load on the interrupt CPU. If it is long enough, which indicates the 5740 * load is heavy, then we deliver the IO completions to the helpers. 5741 * This measurement has some limitations, although it is simple and 5742 * straightforward and works well for most of the cases at present. 5743 */ 5744 if (!mpt->m_doneq_thread_n) { 5745 mptsas_doneq_empty(mpt); 5746 } else { 5747 int helper = 1; 5748 mutex_enter(&mpt->m_intr_mutex); 5749 if (mpt->m_doneq_len <= mpt->m_doneq_length_threshold) 5750 helper = 0; 5751 mutex_exit(&mpt->m_intr_mutex); 5752 if (helper) { 5753 mptsas_deliver_doneq_thread(mpt); 5754 } else { 5755 mptsas_doneq_empty(mpt); 5756 } 5757 } 5758 5759 /* 5760 * If there are queued cmd, start them now. 5761 */ 5762 mutex_enter(&mpt->m_intr_mutex); 5763 if (mpt->m_waitq != NULL) { 5764 mutex_exit(&mpt->m_intr_mutex); 5765 mutex_enter(&mpt->m_mutex); 5766 mptsas_restart_hba(mpt); 5767 mutex_exit(&mpt->m_mutex); 5768 return (DDI_INTR_CLAIMED); 5769 } 5770 mutex_exit(&mpt->m_intr_mutex); 5771 return (DDI_INTR_CLAIMED); 5772 } 5773 5774 /* 5775 * In ISR, the successfully completed read and write IO are processed in a 5776 * fast path. This function is only used to handle non-fastpath IO, including 5777 * all of the address reply, and the context reply for IOC cmd, passthrough, 5778 * etc. 5779 * This function is also used to process polled cmd. 5780 */ 5781 static void 5782 mptsas_process_intr(mptsas_t *mpt, 5783 pMpi2ReplyDescriptorsUnion_t reply_desc_union) 5784 { 5785 uint8_t reply_type; 5786 5787 /* 5788 * The reply is valid, process it according to its 5789 * type. Also, set a flag for updated the reply index 5790 * after they've all been processed. 5791 */ 5792 reply_type = reply_desc_union->Default.ReplyFlags; 5793 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 5794 mptsas_handle_scsi_io_success(mpt, reply_desc_union); 5795 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 5796 mptsas_handle_address_reply(mpt, reply_desc_union); 5797 } else { 5798 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type); 5799 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5800 } 5801 } 5802 5803 /* 5804 * handle qfull condition 5805 */ 5806 static void 5807 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd) 5808 { 5809 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5810 5811 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) || 5812 (ptgt->m_qfull_retries == 0)) { 5813 /* 5814 * We have exhausted the retries on QFULL, or, 5815 * the target driver has indicated that it 5816 * wants to handle QFULL itself by setting 5817 * qfull-retries capability to 0. In either case 5818 * we want the target driver's QFULL handling 5819 * to kick in. We do this by having pkt_reason 5820 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL. 5821 */ 5822 mutex_enter(&ptgt->m_tgt_intr_mutex); 5823 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5824 mutex_exit(&ptgt->m_tgt_intr_mutex); 5825 } else { 5826 mutex_enter(&ptgt->m_tgt_intr_mutex); 5827 if (ptgt->m_reset_delay == 0) { 5828 ptgt->m_t_throttle = 5829 max((ptgt->m_t_ncmds - 2), 0); 5830 } 5831 mutex_exit(&ptgt->m_tgt_intr_mutex); 5832 5833 cmd->cmd_pkt_flags |= FLAG_HEAD; 5834 cmd->cmd_flags &= ~(CFLAG_TRANFLAG); 5835 cmd->cmd_flags |= CFLAG_RETRY; 5836 5837 mutex_exit(&mpt->m_mutex); 5838 (void) mptsas_accept_pkt(mpt, cmd); 5839 mutex_enter(&mpt->m_mutex); 5840 5841 /* 5842 * when target gives queue full status with no commands 5843 * outstanding (m_t_ncmds == 0), throttle is set to 0 5844 * (HOLD_THROTTLE), and the queue full handling start 5845 * (see psarc/1994/313); if there are commands outstanding, 5846 * throttle is set to (m_t_ncmds - 2) 5847 */ 5848 mutex_enter(&ptgt->m_tgt_intr_mutex); 5849 if (ptgt->m_t_throttle == HOLD_THROTTLE) { 5850 /* 5851 * By setting throttle to QFULL_THROTTLE, we 5852 * avoid submitting new commands and in 5853 * mptsas_restart_cmd find out slots which need 5854 * their throttles to be cleared. 5855 */ 5856 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE); 5857 if (mpt->m_restart_cmd_timeid == 0) { 5858 mpt->m_restart_cmd_timeid = 5859 timeout(mptsas_restart_cmd, mpt, 5860 ptgt->m_qfull_retry_interval); 5861 } 5862 } 5863 mutex_exit(&ptgt->m_tgt_intr_mutex); 5864 } 5865 } 5866 5867 mptsas_phymask_t 5868 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport) 5869 { 5870 mptsas_phymask_t phy_mask = 0; 5871 uint8_t i = 0; 5872 5873 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance)); 5874 5875 ASSERT(mutex_owned(&mpt->m_mutex)); 5876 5877 /* 5878 * If physport is 0xFF, this is a RAID volume. Use phymask of 0. 5879 */ 5880 if (physport == 0xFF) { 5881 return (0); 5882 } 5883 5884 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 5885 if (mpt->m_phy_info[i].attached_devhdl && 5886 (mpt->m_phy_info[i].phy_mask != 0) && 5887 (mpt->m_phy_info[i].port_num == physport)) { 5888 phy_mask = mpt->m_phy_info[i].phy_mask; 5889 break; 5890 } 5891 } 5892 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ", 5893 mpt->m_instance, physport, phy_mask)); 5894 return (phy_mask); 5895 } 5896 5897 /* 5898 * mpt free device handle after device gone, by use of passthrough 5899 */ 5900 static int 5901 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl) 5902 { 5903 Mpi2SasIoUnitControlRequest_t req; 5904 Mpi2SasIoUnitControlReply_t rep; 5905 int ret; 5906 5907 ASSERT(mutex_owned(&mpt->m_mutex)); 5908 5909 /* 5910 * Need to compose a SAS IO Unit Control request message 5911 * and call mptsas_do_passthru() function 5912 */ 5913 bzero(&req, sizeof (req)); 5914 bzero(&rep, sizeof (rep)); 5915 5916 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; 5917 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE; 5918 req.DevHandle = LE_16(devhdl); 5919 5920 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 5921 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 5922 if (ret != 0) { 5923 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 5924 "Control error %d", ret); 5925 return (DDI_FAILURE); 5926 } 5927 5928 /* do passthrough success, check the ioc status */ 5929 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 5930 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 5931 "Control IOCStatus %d", LE_16(rep.IOCStatus)); 5932 return (DDI_FAILURE); 5933 } 5934 5935 return (DDI_SUCCESS); 5936 } 5937 5938 static void 5939 mptsas_update_phymask(mptsas_t *mpt) 5940 { 5941 mptsas_phymask_t mask = 0, phy_mask; 5942 char *phy_mask_name; 5943 uint8_t current_port; 5944 int i, j; 5945 5946 NDBG20(("mptsas%d update phymask ", mpt->m_instance)); 5947 5948 ASSERT(mutex_owned(&mpt->m_mutex)); 5949 5950 (void) mptsas_get_sas_io_unit_page(mpt); 5951 5952 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 5953 5954 for (i = 0; i < mpt->m_num_phys; i++) { 5955 phy_mask = 0x00; 5956 5957 if (mpt->m_phy_info[i].attached_devhdl == 0) 5958 continue; 5959 5960 bzero(phy_mask_name, sizeof (phy_mask_name)); 5961 5962 current_port = mpt->m_phy_info[i].port_num; 5963 5964 if ((mask & (1 << i)) != 0) 5965 continue; 5966 5967 for (j = 0; j < mpt->m_num_phys; j++) { 5968 if (mpt->m_phy_info[j].attached_devhdl && 5969 (mpt->m_phy_info[j].port_num == current_port)) { 5970 phy_mask |= (1 << j); 5971 } 5972 } 5973 mask = mask | phy_mask; 5974 5975 for (j = 0; j < mpt->m_num_phys; j++) { 5976 if ((phy_mask >> j) & 0x01) { 5977 mpt->m_phy_info[j].phy_mask = phy_mask; 5978 } 5979 } 5980 5981 (void) sprintf(phy_mask_name, "%x", phy_mask); 5982 5983 mutex_exit(&mpt->m_mutex); 5984 /* 5985 * register a iport, if the port has already been existed 5986 * SCSA will do nothing and just return. 5987 */ 5988 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 5989 mutex_enter(&mpt->m_mutex); 5990 } 5991 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 5992 NDBG20(("mptsas%d update phymask return", mpt->m_instance)); 5993 } 5994 5995 /* 5996 * mptsas_handle_dr is a task handler for DR, the DR action includes: 5997 * 1. Directly attched Device Added/Removed. 5998 * 2. Expander Device Added/Removed. 5999 * 3. Indirectly Attached Device Added/Expander. 6000 * 4. LUNs of a existing device status change. 6001 * 5. RAID volume created/deleted. 6002 * 6. Member of RAID volume is released because of RAID deletion. 6003 * 7. Physical disks are removed because of RAID creation. 6004 */ 6005 static void 6006 mptsas_handle_dr(void *args) { 6007 mptsas_topo_change_list_t *topo_node = NULL; 6008 mptsas_topo_change_list_t *save_node = NULL; 6009 mptsas_t *mpt; 6010 dev_info_t *parent = NULL; 6011 mptsas_phymask_t phymask = 0; 6012 char *phy_mask_name; 6013 uint8_t flags = 0, physport = 0xff; 6014 uint8_t port_update = 0; 6015 uint_t event; 6016 6017 topo_node = (mptsas_topo_change_list_t *)args; 6018 6019 mpt = topo_node->mpt; 6020 event = topo_node->event; 6021 flags = topo_node->flags; 6022 6023 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6024 6025 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance)); 6026 6027 switch (event) { 6028 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6029 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6030 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) || 6031 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6032 /* 6033 * Direct attached or expander attached device added 6034 * into system or a Phys Disk that is being unhidden. 6035 */ 6036 port_update = 1; 6037 } 6038 break; 6039 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6040 /* 6041 * New expander added into system, it must be the head 6042 * of topo_change_list_t 6043 */ 6044 port_update = 1; 6045 break; 6046 default: 6047 port_update = 0; 6048 break; 6049 } 6050 /* 6051 * All cases port_update == 1 may cause initiator port form change 6052 */ 6053 mutex_enter(&mpt->m_mutex); 6054 if (mpt->m_port_chng && port_update) { 6055 /* 6056 * mpt->m_port_chng flag indicates some PHYs of initiator 6057 * port have changed to online. So when expander added or 6058 * directly attached device online event come, we force to 6059 * update port information by issueing SAS IO Unit Page and 6060 * update PHYMASKs. 6061 */ 6062 (void) mptsas_update_phymask(mpt); 6063 mpt->m_port_chng = 0; 6064 6065 } 6066 mutex_exit(&mpt->m_mutex); 6067 while (topo_node) { 6068 phymask = 0; 6069 if (parent == NULL) { 6070 physport = topo_node->un.physport; 6071 event = topo_node->event; 6072 flags = topo_node->flags; 6073 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET | 6074 MPTSAS_DR_EVENT_OFFLINE_SMP)) { 6075 /* 6076 * For all offline events, phymask is known 6077 */ 6078 phymask = topo_node->un.phymask; 6079 goto find_parent; 6080 } 6081 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6082 goto handle_topo_change; 6083 } 6084 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) { 6085 phymask = topo_node->un.phymask; 6086 goto find_parent; 6087 } 6088 6089 if ((flags == 6090 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) && 6091 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) { 6092 /* 6093 * There is no any field in IR_CONFIG_CHANGE 6094 * event indicate physport/phynum, let's get 6095 * parent after SAS Device Page0 request. 6096 */ 6097 goto handle_topo_change; 6098 } 6099 6100 mutex_enter(&mpt->m_mutex); 6101 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6102 /* 6103 * If the direct attached device added or a 6104 * phys disk is being unhidden, argument 6105 * physport actually is PHY#, so we have to get 6106 * phymask according PHY#. 6107 */ 6108 physport = mpt->m_phy_info[physport].port_num; 6109 } 6110 6111 /* 6112 * Translate physport to phymask so that we can search 6113 * parent dip. 6114 */ 6115 phymask = mptsas_physport_to_phymask(mpt, 6116 physport); 6117 mutex_exit(&mpt->m_mutex); 6118 6119 find_parent: 6120 bzero(phy_mask_name, MPTSAS_MAX_PHYS); 6121 /* 6122 * For RAID topology change node, write the iport name 6123 * as v0. 6124 */ 6125 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6126 (void) sprintf(phy_mask_name, "v0"); 6127 } else { 6128 /* 6129 * phymask can bo 0 if the drive has been 6130 * pulled by the time an add event is 6131 * processed. If phymask is 0, just skip this 6132 * event and continue. 6133 */ 6134 if (phymask == 0) { 6135 mutex_enter(&mpt->m_mutex); 6136 save_node = topo_node; 6137 topo_node = topo_node->next; 6138 ASSERT(save_node); 6139 kmem_free(save_node, 6140 sizeof (mptsas_topo_change_list_t)); 6141 mutex_exit(&mpt->m_mutex); 6142 6143 parent = NULL; 6144 continue; 6145 } 6146 (void) sprintf(phy_mask_name, "%x", phymask); 6147 } 6148 parent = scsi_hba_iport_find(mpt->m_dip, 6149 phy_mask_name); 6150 if (parent == NULL) { 6151 mptsas_log(mpt, CE_WARN, "Failed to find an " 6152 "iport, should not happen!"); 6153 goto out; 6154 } 6155 6156 } 6157 ASSERT(parent); 6158 handle_topo_change: 6159 6160 mutex_enter(&mpt->m_mutex); 6161 6162 mptsas_handle_topo_change(topo_node, parent); 6163 save_node = topo_node; 6164 topo_node = topo_node->next; 6165 ASSERT(save_node); 6166 kmem_free(save_node, sizeof (mptsas_topo_change_list_t)); 6167 mutex_exit(&mpt->m_mutex); 6168 6169 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6170 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) || 6171 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) { 6172 /* 6173 * If direct attached device associated, make sure 6174 * reset the parent before start the next one. But 6175 * all devices associated with expander shares the 6176 * parent. Also, reset parent if this is for RAID. 6177 */ 6178 parent = NULL; 6179 } 6180 } 6181 out: 6182 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6183 } 6184 6185 static void 6186 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 6187 dev_info_t *parent) 6188 { 6189 mptsas_target_t *ptgt = NULL; 6190 mptsas_smp_t *psmp = NULL; 6191 mptsas_t *mpt = (void *)topo_node->mpt; 6192 uint16_t devhdl; 6193 uint16_t attached_devhdl; 6194 uint64_t sas_wwn = 0; 6195 int rval = 0; 6196 uint32_t page_address; 6197 uint8_t phy, flags; 6198 char *addr = NULL; 6199 dev_info_t *lundip; 6200 int circ = 0, circ1 = 0; 6201 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 6202 6203 NDBG20(("mptsas%d handle_topo_change enter", mpt->m_instance)); 6204 6205 ASSERT(mutex_owned(&mpt->m_mutex)); 6206 6207 switch (topo_node->event) { 6208 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6209 { 6210 char *phy_mask_name; 6211 mptsas_phymask_t phymask = 0; 6212 6213 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6214 /* 6215 * Get latest RAID info. 6216 */ 6217 (void) mptsas_get_raid_info(mpt); 6218 ptgt = mptsas_search_by_devhdl( 6219 &mpt->m_active->m_tgttbl, topo_node->devhdl); 6220 if (ptgt == NULL) 6221 break; 6222 } else { 6223 ptgt = (void *)topo_node->object; 6224 } 6225 6226 if (ptgt == NULL) { 6227 /* 6228 * If a Phys Disk was deleted, RAID info needs to be 6229 * updated to reflect the new topology. 6230 */ 6231 (void) mptsas_get_raid_info(mpt); 6232 6233 /* 6234 * Get sas device page 0 by DevHandle to make sure if 6235 * SSP/SATA end device exist. 6236 */ 6237 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 6238 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 6239 topo_node->devhdl; 6240 6241 rval = mptsas_get_target_device_info(mpt, page_address, 6242 &devhdl, &ptgt); 6243 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) { 6244 mptsas_log(mpt, CE_NOTE, 6245 "mptsas_handle_topo_change: target %d is " 6246 "not a SAS/SATA device. \n", 6247 topo_node->devhdl); 6248 } else if (rval == DEV_INFO_FAIL_ALLOC) { 6249 mptsas_log(mpt, CE_NOTE, 6250 "mptsas_handle_topo_change: could not " 6251 "allocate memory. \n"); 6252 } 6253 /* 6254 * If rval is DEV_INFO_PHYS_DISK than there is nothing 6255 * else to do, just leave. 6256 */ 6257 if (rval != DEV_INFO_SUCCESS) { 6258 return; 6259 } 6260 } 6261 6262 ASSERT(ptgt->m_devhdl == topo_node->devhdl); 6263 6264 mutex_exit(&mpt->m_mutex); 6265 flags = topo_node->flags; 6266 6267 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) { 6268 phymask = ptgt->m_phymask; 6269 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6270 (void) sprintf(phy_mask_name, "%x", phymask); 6271 parent = scsi_hba_iport_find(mpt->m_dip, 6272 phy_mask_name); 6273 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6274 if (parent == NULL) { 6275 mptsas_log(mpt, CE_WARN, "Failed to find a " 6276 "iport for PD, should not happen!"); 6277 mutex_enter(&mpt->m_mutex); 6278 break; 6279 } 6280 } 6281 6282 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6283 ndi_devi_enter(parent, &circ1); 6284 (void) mptsas_config_raid(parent, topo_node->devhdl, 6285 &lundip); 6286 ndi_devi_exit(parent, circ1); 6287 } else { 6288 /* 6289 * hold nexus for bus configure 6290 */ 6291 ndi_devi_enter(scsi_vhci_dip, &circ); 6292 ndi_devi_enter(parent, &circ1); 6293 rval = mptsas_config_target(parent, ptgt); 6294 /* 6295 * release nexus for bus configure 6296 */ 6297 ndi_devi_exit(parent, circ1); 6298 ndi_devi_exit(scsi_vhci_dip, circ); 6299 6300 /* 6301 * Add parent's props for SMHBA support 6302 */ 6303 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6304 bzero(attached_wwnstr, 6305 sizeof (attached_wwnstr)); 6306 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 6307 ptgt->m_sas_wwn); 6308 if (ddi_prop_update_string(DDI_DEV_T_NONE, 6309 parent, 6310 SCSI_ADDR_PROP_ATTACHED_PORT, 6311 attached_wwnstr) 6312 != DDI_PROP_SUCCESS) { 6313 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6314 parent, 6315 SCSI_ADDR_PROP_ATTACHED_PORT); 6316 mptsas_log(mpt, CE_WARN, "Failed to" 6317 "attached-port props"); 6318 return; 6319 } 6320 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6321 MPTSAS_NUM_PHYS, 1) != 6322 DDI_PROP_SUCCESS) { 6323 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6324 parent, MPTSAS_NUM_PHYS); 6325 mptsas_log(mpt, CE_WARN, "Failed to" 6326 " create num-phys props"); 6327 return; 6328 } 6329 6330 /* 6331 * Update PHY info for smhba 6332 */ 6333 mutex_enter(&mpt->m_mutex); 6334 if (mptsas_smhba_phy_init(mpt)) { 6335 mutex_exit(&mpt->m_mutex); 6336 mptsas_log(mpt, CE_WARN, "mptsas phy" 6337 " update failed"); 6338 return; 6339 } 6340 mutex_exit(&mpt->m_mutex); 6341 mptsas_smhba_set_phy_props(mpt, 6342 ddi_get_name_addr(parent), parent, 6343 1, &attached_devhdl); 6344 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6345 MPTSAS_VIRTUAL_PORT, 0) != 6346 DDI_PROP_SUCCESS) { 6347 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6348 parent, MPTSAS_VIRTUAL_PORT); 6349 mptsas_log(mpt, CE_WARN, 6350 "mptsas virtual-port" 6351 "port prop update failed"); 6352 return; 6353 } 6354 } 6355 } 6356 mutex_enter(&mpt->m_mutex); 6357 6358 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, " 6359 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl, 6360 ptgt->m_phymask)); 6361 break; 6362 } 6363 case MPTSAS_DR_EVENT_OFFLINE_TARGET: 6364 { 6365 mptsas_hash_table_t *tgttbl = &mpt->m_active->m_tgttbl; 6366 devhdl = topo_node->devhdl; 6367 ptgt = mptsas_search_by_devhdl(tgttbl, devhdl); 6368 if (ptgt == NULL) 6369 break; 6370 6371 sas_wwn = ptgt->m_sas_wwn; 6372 phy = ptgt->m_phynum; 6373 6374 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 6375 6376 if (sas_wwn) { 6377 (void) sprintf(addr, "w%016"PRIx64, sas_wwn); 6378 } else { 6379 (void) sprintf(addr, "p%x", phy); 6380 } 6381 ASSERT(ptgt->m_devhdl == devhdl); 6382 6383 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) || 6384 (topo_node->flags == 6385 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6386 /* 6387 * Get latest RAID info if RAID volume status changes 6388 * or Phys Disk status changes 6389 */ 6390 (void) mptsas_get_raid_info(mpt); 6391 } 6392 /* 6393 * Abort all outstanding command on the device 6394 */ 6395 rval = mptsas_do_scsi_reset(mpt, devhdl); 6396 if (rval) { 6397 NDBG20(("mptsas%d handle_topo_change to reset target " 6398 "before offline devhdl:%x, phymask:%x, rval:%x", 6399 mpt->m_instance, ptgt->m_devhdl, ptgt->m_phymask, 6400 rval)); 6401 } 6402 6403 mutex_exit(&mpt->m_mutex); 6404 6405 ndi_devi_enter(scsi_vhci_dip, &circ); 6406 ndi_devi_enter(parent, &circ1); 6407 rval = mptsas_offline_target(parent, addr); 6408 ndi_devi_exit(parent, circ1); 6409 ndi_devi_exit(scsi_vhci_dip, circ); 6410 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, " 6411 "phymask:%x, rval:%x", mpt->m_instance, 6412 ptgt->m_devhdl, ptgt->m_phymask, rval)); 6413 6414 kmem_free(addr, SCSI_MAXNAMELEN); 6415 6416 /* 6417 * Clear parent's props for SMHBA support 6418 */ 6419 flags = topo_node->flags; 6420 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6421 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6422 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6423 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6424 DDI_PROP_SUCCESS) { 6425 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6426 SCSI_ADDR_PROP_ATTACHED_PORT); 6427 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6428 "prop update failed"); 6429 break; 6430 } 6431 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6432 MPTSAS_NUM_PHYS, 0) != 6433 DDI_PROP_SUCCESS) { 6434 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6435 MPTSAS_NUM_PHYS); 6436 mptsas_log(mpt, CE_WARN, "mptsas num phys " 6437 "prop update failed"); 6438 break; 6439 } 6440 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6441 MPTSAS_VIRTUAL_PORT, 1) != 6442 DDI_PROP_SUCCESS) { 6443 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6444 MPTSAS_VIRTUAL_PORT); 6445 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6446 "prop update failed"); 6447 break; 6448 } 6449 } 6450 6451 mutex_enter(&mpt->m_mutex); 6452 if (rval == DDI_SUCCESS) { 6453 mptsas_tgt_free(&mpt->m_active->m_tgttbl, 6454 ptgt->m_sas_wwn, ptgt->m_phymask); 6455 ptgt = NULL; 6456 } else { 6457 /* 6458 * clean DR_INTRANSITION flag to allow I/O down to 6459 * PHCI driver since failover finished. 6460 * Invalidate the devhdl 6461 */ 6462 mutex_enter(&ptgt->m_tgt_intr_mutex); 6463 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL; 6464 ptgt->m_tgt_unconfigured = 0; 6465 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE; 6466 mutex_exit(&ptgt->m_tgt_intr_mutex); 6467 } 6468 6469 /* 6470 * Send SAS IO Unit Control to free the dev handle 6471 */ 6472 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6473 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) { 6474 rval = mptsas_free_devhdl(mpt, devhdl); 6475 6476 NDBG20(("mptsas%d handle_topo_change to remove " 6477 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6478 rval)); 6479 } 6480 6481 break; 6482 } 6483 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE: 6484 { 6485 devhdl = topo_node->devhdl; 6486 /* 6487 * If this is the remove handle event, do a reset first. 6488 */ 6489 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6490 rval = mptsas_do_scsi_reset(mpt, devhdl); 6491 if (rval) { 6492 NDBG20(("mpt%d reset target before remove " 6493 "devhdl:%x, rval:%x", mpt->m_instance, 6494 devhdl, rval)); 6495 } 6496 } 6497 6498 /* 6499 * Send SAS IO Unit Control to free the dev handle 6500 */ 6501 rval = mptsas_free_devhdl(mpt, devhdl); 6502 NDBG20(("mptsas%d handle_topo_change to remove " 6503 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6504 rval)); 6505 break; 6506 } 6507 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6508 { 6509 mptsas_smp_t smp; 6510 dev_info_t *smpdip; 6511 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl; 6512 6513 devhdl = topo_node->devhdl; 6514 6515 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 6516 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl; 6517 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp); 6518 if (rval != DDI_SUCCESS) { 6519 mptsas_log(mpt, CE_WARN, "failed to online smp, " 6520 "handle %x", devhdl); 6521 return; 6522 } 6523 6524 psmp = mptsas_smp_alloc(smptbl, &smp); 6525 if (psmp == NULL) { 6526 return; 6527 } 6528 6529 mutex_exit(&mpt->m_mutex); 6530 ndi_devi_enter(parent, &circ1); 6531 (void) mptsas_online_smp(parent, psmp, &smpdip); 6532 ndi_devi_exit(parent, circ1); 6533 6534 mutex_enter(&mpt->m_mutex); 6535 break; 6536 } 6537 case MPTSAS_DR_EVENT_OFFLINE_SMP: 6538 { 6539 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl; 6540 devhdl = topo_node->devhdl; 6541 uint32_t dev_info; 6542 6543 psmp = mptsas_search_by_devhdl(smptbl, devhdl); 6544 if (psmp == NULL) 6545 break; 6546 /* 6547 * The mptsas_smp_t data is released only if the dip is offlined 6548 * successfully. 6549 */ 6550 mutex_exit(&mpt->m_mutex); 6551 6552 ndi_devi_enter(parent, &circ1); 6553 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE); 6554 ndi_devi_exit(parent, circ1); 6555 6556 dev_info = psmp->m_deviceinfo; 6557 if ((dev_info & DEVINFO_DIRECT_ATTACHED) == 6558 DEVINFO_DIRECT_ATTACHED) { 6559 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6560 MPTSAS_VIRTUAL_PORT, 1) != 6561 DDI_PROP_SUCCESS) { 6562 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6563 MPTSAS_VIRTUAL_PORT); 6564 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6565 "prop update failed"); 6566 return; 6567 } 6568 /* 6569 * Check whether the smp connected to the iport, 6570 */ 6571 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6572 MPTSAS_NUM_PHYS, 0) != 6573 DDI_PROP_SUCCESS) { 6574 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6575 MPTSAS_NUM_PHYS); 6576 mptsas_log(mpt, CE_WARN, "mptsas num phys" 6577 "prop update failed"); 6578 return; 6579 } 6580 /* 6581 * Clear parent's attached-port props 6582 */ 6583 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6584 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6585 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6586 DDI_PROP_SUCCESS) { 6587 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6588 SCSI_ADDR_PROP_ATTACHED_PORT); 6589 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6590 "prop update failed"); 6591 return; 6592 } 6593 } 6594 6595 mutex_enter(&mpt->m_mutex); 6596 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, " 6597 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval)); 6598 if (rval == DDI_SUCCESS) { 6599 mptsas_smp_free(smptbl, psmp->m_sasaddr, 6600 psmp->m_phymask); 6601 } else { 6602 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL; 6603 } 6604 6605 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6606 6607 break; 6608 } 6609 default: 6610 return; 6611 } 6612 } 6613 6614 /* 6615 * Record the event if its type is enabled in mpt instance by ioctl. 6616 */ 6617 static void 6618 mptsas_record_event(void *args) 6619 { 6620 m_replyh_arg_t *replyh_arg; 6621 pMpi2EventNotificationReply_t eventreply; 6622 uint32_t event, rfm; 6623 mptsas_t *mpt; 6624 int i, j; 6625 uint16_t event_data_len; 6626 boolean_t sendAEN = FALSE; 6627 6628 replyh_arg = (m_replyh_arg_t *)args; 6629 rfm = replyh_arg->rfm; 6630 mpt = replyh_arg->mpt; 6631 6632 eventreply = (pMpi2EventNotificationReply_t) 6633 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr)); 6634 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6635 6636 6637 /* 6638 * Generate a system event to let anyone who cares know that a 6639 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the 6640 * event mask is set to. 6641 */ 6642 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) { 6643 sendAEN = TRUE; 6644 } 6645 6646 /* 6647 * Record the event only if it is not masked. Determine which dword 6648 * and bit of event mask to test. 6649 */ 6650 i = (uint8_t)(event / 32); 6651 j = (uint8_t)(event % 32); 6652 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) { 6653 i = mpt->m_event_index; 6654 mpt->m_events[i].Type = event; 6655 mpt->m_events[i].Number = ++mpt->m_event_number; 6656 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4); 6657 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl, 6658 &eventreply->EventDataLength); 6659 6660 if (event_data_len > 0) { 6661 /* 6662 * Limit data to size in m_event entry 6663 */ 6664 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) { 6665 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH; 6666 } 6667 for (j = 0; j < event_data_len; j++) { 6668 mpt->m_events[i].Data[j] = 6669 ddi_get32(mpt->m_acc_reply_frame_hdl, 6670 &(eventreply->EventData[j])); 6671 } 6672 6673 /* 6674 * check for index wrap-around 6675 */ 6676 if (++i == MPTSAS_EVENT_QUEUE_SIZE) { 6677 i = 0; 6678 } 6679 mpt->m_event_index = (uint8_t)i; 6680 6681 /* 6682 * Set flag to send the event. 6683 */ 6684 sendAEN = TRUE; 6685 } 6686 } 6687 6688 /* 6689 * Generate a system event if flag is set to let anyone who cares know 6690 * that an event has occurred. 6691 */ 6692 if (sendAEN) { 6693 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS", 6694 "SAS", NULL, NULL, DDI_NOSLEEP); 6695 } 6696 } 6697 6698 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS 6699 /* 6700 * handle sync events from ioc in interrupt 6701 * return value: 6702 * DDI_SUCCESS: The event is handled by this func 6703 * DDI_FAILURE: Event is not handled 6704 */ 6705 static int 6706 mptsas_handle_event_sync(void *args) 6707 { 6708 m_replyh_arg_t *replyh_arg; 6709 pMpi2EventNotificationReply_t eventreply; 6710 uint32_t event, rfm; 6711 mptsas_t *mpt; 6712 uint_t iocstatus; 6713 6714 replyh_arg = (m_replyh_arg_t *)args; 6715 rfm = replyh_arg->rfm; 6716 mpt = replyh_arg->mpt; 6717 6718 ASSERT(mutex_owned(&mpt->m_mutex)); 6719 6720 eventreply = (pMpi2EventNotificationReply_t) 6721 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr)); 6722 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6723 6724 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 6725 &eventreply->IOCStatus)) { 6726 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 6727 mptsas_log(mpt, CE_WARN, 6728 "!mptsas_handle_event_sync: IOCStatus=0x%x, " 6729 "IOCLogInfo=0x%x", iocstatus, 6730 ddi_get32(mpt->m_acc_reply_frame_hdl, 6731 &eventreply->IOCLogInfo)); 6732 } else { 6733 mptsas_log(mpt, CE_WARN, 6734 "mptsas_handle_event_sync: IOCStatus=0x%x, " 6735 "IOCLogInfo=0x%x", iocstatus, 6736 ddi_get32(mpt->m_acc_reply_frame_hdl, 6737 &eventreply->IOCLogInfo)); 6738 } 6739 } 6740 6741 /* 6742 * figure out what kind of event we got and handle accordingly 6743 */ 6744 switch (event) { 6745 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 6746 { 6747 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list; 6748 uint8_t num_entries, expstatus, phy; 6749 uint8_t phystatus, physport, state, i; 6750 uint8_t start_phy_num, link_rate; 6751 uint16_t dev_handle, reason_code; 6752 uint16_t enc_handle, expd_handle; 6753 char string[80], curr[80], prev[80]; 6754 mptsas_topo_change_list_t *topo_head = NULL; 6755 mptsas_topo_change_list_t *topo_tail = NULL; 6756 mptsas_topo_change_list_t *topo_node = NULL; 6757 mptsas_target_t *ptgt; 6758 mptsas_smp_t *psmp; 6759 mptsas_hash_table_t *tgttbl, *smptbl; 6760 uint8_t flags = 0, exp_flag; 6761 smhba_info_t *pSmhba = NULL; 6762 6763 NDBG20(("mptsas_handle_event_sync: SAS topology change")); 6764 6765 tgttbl = &mpt->m_active->m_tgttbl; 6766 smptbl = &mpt->m_active->m_smptbl; 6767 6768 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t) 6769 eventreply->EventData; 6770 6771 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6772 &sas_topo_change_list->EnclosureHandle); 6773 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6774 &sas_topo_change_list->ExpanderDevHandle); 6775 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 6776 &sas_topo_change_list->NumEntries); 6777 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 6778 &sas_topo_change_list->StartPhyNum); 6779 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 6780 &sas_topo_change_list->ExpStatus); 6781 physport = ddi_get8(mpt->m_acc_reply_frame_hdl, 6782 &sas_topo_change_list->PhysicalPort); 6783 6784 string[0] = 0; 6785 if (expd_handle) { 6786 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED; 6787 switch (expstatus) { 6788 case MPI2_EVENT_SAS_TOPO_ES_ADDED: 6789 (void) sprintf(string, " added"); 6790 /* 6791 * New expander device added 6792 */ 6793 mpt->m_port_chng = 1; 6794 topo_node = kmem_zalloc( 6795 sizeof (mptsas_topo_change_list_t), 6796 KM_SLEEP); 6797 topo_node->mpt = mpt; 6798 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP; 6799 topo_node->un.physport = physport; 6800 topo_node->devhdl = expd_handle; 6801 topo_node->flags = flags; 6802 topo_node->object = NULL; 6803 if (topo_head == NULL) { 6804 topo_head = topo_tail = topo_node; 6805 } else { 6806 topo_tail->next = topo_node; 6807 topo_tail = topo_node; 6808 } 6809 break; 6810 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING: 6811 (void) sprintf(string, " not responding, " 6812 "removed"); 6813 psmp = mptsas_search_by_devhdl(smptbl, 6814 expd_handle); 6815 if (psmp == NULL) 6816 break; 6817 6818 topo_node = kmem_zalloc( 6819 sizeof (mptsas_topo_change_list_t), 6820 KM_SLEEP); 6821 topo_node->mpt = mpt; 6822 topo_node->un.phymask = psmp->m_phymask; 6823 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP; 6824 topo_node->devhdl = expd_handle; 6825 topo_node->flags = flags; 6826 topo_node->object = NULL; 6827 if (topo_head == NULL) { 6828 topo_head = topo_tail = topo_node; 6829 } else { 6830 topo_tail->next = topo_node; 6831 topo_tail = topo_node; 6832 } 6833 break; 6834 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING: 6835 break; 6836 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING: 6837 (void) sprintf(string, " not responding, " 6838 "delaying removal"); 6839 break; 6840 default: 6841 break; 6842 } 6843 } else { 6844 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE; 6845 } 6846 6847 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n", 6848 enc_handle, expd_handle, string)); 6849 for (i = 0; i < num_entries; i++) { 6850 phy = i + start_phy_num; 6851 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 6852 &sas_topo_change_list->PHY[i].PhyStatus); 6853 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6854 &sas_topo_change_list->PHY[i].AttachedDevHandle); 6855 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK; 6856 /* 6857 * Filter out processing of Phy Vacant Status unless 6858 * the reason code is "Not Responding". Process all 6859 * other combinations of Phy Status and Reason Codes. 6860 */ 6861 if ((phystatus & 6862 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) && 6863 (reason_code != 6864 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) { 6865 continue; 6866 } 6867 curr[0] = 0; 6868 prev[0] = 0; 6869 string[0] = 0; 6870 switch (reason_code) { 6871 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED: 6872 { 6873 NDBG20(("mptsas%d phy %d physical_port %d " 6874 "dev_handle %d added", mpt->m_instance, phy, 6875 physport, dev_handle)); 6876 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 6877 &sas_topo_change_list->PHY[i].LinkRate); 6878 state = (link_rate & 6879 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 6880 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 6881 switch (state) { 6882 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 6883 (void) sprintf(curr, "is disabled"); 6884 break; 6885 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 6886 (void) sprintf(curr, "is offline, " 6887 "failed speed negotiation"); 6888 break; 6889 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 6890 (void) sprintf(curr, "SATA OOB " 6891 "complete"); 6892 break; 6893 case SMP_RESET_IN_PROGRESS: 6894 (void) sprintf(curr, "SMP reset in " 6895 "progress"); 6896 break; 6897 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 6898 (void) sprintf(curr, "is online at " 6899 "1.5 Gbps"); 6900 break; 6901 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 6902 (void) sprintf(curr, "is online at 3.0 " 6903 "Gbps"); 6904 break; 6905 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 6906 (void) sprintf(curr, "is online at 6.0 " 6907 "Gbps"); 6908 break; 6909 default: 6910 (void) sprintf(curr, "state is " 6911 "unknown"); 6912 break; 6913 } 6914 /* 6915 * New target device added into the system. 6916 * Set association flag according to if an 6917 * expander is used or not. 6918 */ 6919 exp_flag = 6920 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 6921 if (flags == 6922 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 6923 flags = exp_flag; 6924 } 6925 topo_node = kmem_zalloc( 6926 sizeof (mptsas_topo_change_list_t), 6927 KM_SLEEP); 6928 topo_node->mpt = mpt; 6929 topo_node->event = 6930 MPTSAS_DR_EVENT_RECONFIG_TARGET; 6931 if (expd_handle == 0) { 6932 /* 6933 * Per MPI 2, if expander dev handle 6934 * is 0, it's a directly attached 6935 * device. So driver use PHY to decide 6936 * which iport is associated 6937 */ 6938 physport = phy; 6939 mpt->m_port_chng = 1; 6940 } 6941 topo_node->un.physport = physport; 6942 topo_node->devhdl = dev_handle; 6943 topo_node->flags = flags; 6944 topo_node->object = NULL; 6945 if (topo_head == NULL) { 6946 topo_head = topo_tail = topo_node; 6947 } else { 6948 topo_tail->next = topo_node; 6949 topo_tail = topo_node; 6950 } 6951 break; 6952 } 6953 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING: 6954 { 6955 NDBG20(("mptsas%d phy %d physical_port %d " 6956 "dev_handle %d removed", mpt->m_instance, 6957 phy, physport, dev_handle)); 6958 /* 6959 * Set association flag according to if an 6960 * expander is used or not. 6961 */ 6962 exp_flag = 6963 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 6964 if (flags == 6965 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 6966 flags = exp_flag; 6967 } 6968 /* 6969 * Target device is removed from the system 6970 * Before the device is really offline from 6971 * from system. 6972 */ 6973 ptgt = mptsas_search_by_devhdl(tgttbl, 6974 dev_handle); 6975 /* 6976 * If ptgt is NULL here, it means that the 6977 * DevHandle is not in the hash table. This is 6978 * reasonable sometimes. For example, if a 6979 * disk was pulled, then added, then pulled 6980 * again, the disk will not have been put into 6981 * the hash table because the add event will 6982 * have an invalid phymask. BUT, this does not 6983 * mean that the DevHandle is invalid. The 6984 * controller will still have a valid DevHandle 6985 * that must be removed. To do this, use the 6986 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event. 6987 */ 6988 if (ptgt == NULL) { 6989 topo_node = kmem_zalloc( 6990 sizeof (mptsas_topo_change_list_t), 6991 KM_SLEEP); 6992 topo_node->mpt = mpt; 6993 topo_node->un.phymask = 0; 6994 topo_node->event = 6995 MPTSAS_TOPO_FLAG_REMOVE_HANDLE; 6996 topo_node->devhdl = dev_handle; 6997 topo_node->flags = flags; 6998 topo_node->object = NULL; 6999 if (topo_head == NULL) { 7000 topo_head = topo_tail = 7001 topo_node; 7002 } else { 7003 topo_tail->next = topo_node; 7004 topo_tail = topo_node; 7005 } 7006 break; 7007 } 7008 7009 /* 7010 * Update DR flag immediately avoid I/O failure 7011 * before failover finish. Pay attention to the 7012 * mutex protect, we need grab the per target 7013 * mutex during set m_dr_flag because the 7014 * m_mutex would not be held all the time in 7015 * mptsas_scsi_start(). 7016 */ 7017 mutex_enter(&ptgt->m_tgt_intr_mutex); 7018 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7019 mutex_exit(&ptgt->m_tgt_intr_mutex); 7020 7021 topo_node = kmem_zalloc( 7022 sizeof (mptsas_topo_change_list_t), 7023 KM_SLEEP); 7024 topo_node->mpt = mpt; 7025 topo_node->un.phymask = ptgt->m_phymask; 7026 topo_node->event = 7027 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7028 topo_node->devhdl = dev_handle; 7029 topo_node->flags = flags; 7030 topo_node->object = NULL; 7031 if (topo_head == NULL) { 7032 topo_head = topo_tail = topo_node; 7033 } else { 7034 topo_tail->next = topo_node; 7035 topo_tail = topo_node; 7036 } 7037 break; 7038 } 7039 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED: 7040 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 7041 &sas_topo_change_list->PHY[i].LinkRate); 7042 state = (link_rate & 7043 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 7044 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 7045 pSmhba = &mpt->m_phy_info[i].smhba_info; 7046 pSmhba->negotiated_link_rate = state; 7047 switch (state) { 7048 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7049 (void) sprintf(curr, "is disabled"); 7050 mptsas_smhba_log_sysevent(mpt, 7051 ESC_SAS_PHY_EVENT, 7052 SAS_PHY_REMOVE, 7053 &mpt->m_phy_info[i].smhba_info); 7054 mpt->m_phy_info[i].smhba_info. 7055 negotiated_link_rate 7056 = 0x1; 7057 break; 7058 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7059 (void) sprintf(curr, "is offline, " 7060 "failed speed negotiation"); 7061 mptsas_smhba_log_sysevent(mpt, 7062 ESC_SAS_PHY_EVENT, 7063 SAS_PHY_OFFLINE, 7064 &mpt->m_phy_info[i].smhba_info); 7065 break; 7066 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7067 (void) sprintf(curr, "SATA OOB " 7068 "complete"); 7069 break; 7070 case SMP_RESET_IN_PROGRESS: 7071 (void) sprintf(curr, "SMP reset in " 7072 "progress"); 7073 break; 7074 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7075 (void) sprintf(curr, "is online at " 7076 "1.5 Gbps"); 7077 if ((expd_handle == 0) && 7078 (enc_handle == 1)) { 7079 mpt->m_port_chng = 1; 7080 } 7081 mptsas_smhba_log_sysevent(mpt, 7082 ESC_SAS_PHY_EVENT, 7083 SAS_PHY_ONLINE, 7084 &mpt->m_phy_info[i].smhba_info); 7085 break; 7086 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7087 (void) sprintf(curr, "is online at 3.0 " 7088 "Gbps"); 7089 if ((expd_handle == 0) && 7090 (enc_handle == 1)) { 7091 mpt->m_port_chng = 1; 7092 } 7093 mptsas_smhba_log_sysevent(mpt, 7094 ESC_SAS_PHY_EVENT, 7095 SAS_PHY_ONLINE, 7096 &mpt->m_phy_info[i].smhba_info); 7097 break; 7098 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7099 (void) sprintf(curr, "is online at " 7100 "6.0 Gbps"); 7101 if ((expd_handle == 0) && 7102 (enc_handle == 1)) { 7103 mpt->m_port_chng = 1; 7104 } 7105 mptsas_smhba_log_sysevent(mpt, 7106 ESC_SAS_PHY_EVENT, 7107 SAS_PHY_ONLINE, 7108 &mpt->m_phy_info[i].smhba_info); 7109 break; 7110 default: 7111 (void) sprintf(curr, "state is " 7112 "unknown"); 7113 break; 7114 } 7115 7116 state = (link_rate & 7117 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >> 7118 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT; 7119 switch (state) { 7120 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7121 (void) sprintf(prev, ", was disabled"); 7122 break; 7123 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7124 (void) sprintf(prev, ", was offline, " 7125 "failed speed negotiation"); 7126 break; 7127 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7128 (void) sprintf(prev, ", was SATA OOB " 7129 "complete"); 7130 break; 7131 case SMP_RESET_IN_PROGRESS: 7132 (void) sprintf(prev, ", was SMP reset " 7133 "in progress"); 7134 break; 7135 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7136 (void) sprintf(prev, ", was online at " 7137 "1.5 Gbps"); 7138 break; 7139 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7140 (void) sprintf(prev, ", was online at " 7141 "3.0 Gbps"); 7142 break; 7143 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7144 (void) sprintf(prev, ", was online at " 7145 "6.0 Gbps"); 7146 break; 7147 default: 7148 break; 7149 } 7150 (void) sprintf(&string[strlen(string)], "link " 7151 "changed, "); 7152 break; 7153 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE: 7154 continue; 7155 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING: 7156 (void) sprintf(&string[strlen(string)], 7157 "target not responding, delaying " 7158 "removal"); 7159 break; 7160 } 7161 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n", 7162 mpt->m_instance, phy, dev_handle, string, curr, 7163 prev)); 7164 } 7165 if (topo_head != NULL) { 7166 /* 7167 * Launch DR taskq to handle topology change 7168 */ 7169 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7170 mptsas_handle_dr, (void *)topo_head, 7171 DDI_NOSLEEP)) != DDI_SUCCESS) { 7172 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7173 "for handle SAS DR event failed. \n"); 7174 } 7175 } 7176 break; 7177 } 7178 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7179 { 7180 Mpi2EventDataIrConfigChangeList_t *irChangeList; 7181 mptsas_topo_change_list_t *topo_head = NULL; 7182 mptsas_topo_change_list_t *topo_tail = NULL; 7183 mptsas_topo_change_list_t *topo_node = NULL; 7184 mptsas_target_t *ptgt; 7185 mptsas_hash_table_t *tgttbl; 7186 uint8_t num_entries, i, reason; 7187 uint16_t volhandle, diskhandle; 7188 7189 irChangeList = (pMpi2EventDataIrConfigChangeList_t) 7190 eventreply->EventData; 7191 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 7192 &irChangeList->NumElements); 7193 7194 tgttbl = &mpt->m_active->m_tgttbl; 7195 7196 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received", 7197 mpt->m_instance)); 7198 7199 for (i = 0; i < num_entries; i++) { 7200 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 7201 &irChangeList->ConfigElement[i].ReasonCode); 7202 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7203 &irChangeList->ConfigElement[i].VolDevHandle); 7204 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7205 &irChangeList->ConfigElement[i].PhysDiskDevHandle); 7206 7207 switch (reason) { 7208 case MPI2_EVENT_IR_CHANGE_RC_ADDED: 7209 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED: 7210 { 7211 NDBG20(("mptsas %d volume added\n", 7212 mpt->m_instance)); 7213 7214 topo_node = kmem_zalloc( 7215 sizeof (mptsas_topo_change_list_t), 7216 KM_SLEEP); 7217 7218 topo_node->mpt = mpt; 7219 topo_node->event = 7220 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7221 topo_node->un.physport = 0xff; 7222 topo_node->devhdl = volhandle; 7223 topo_node->flags = 7224 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7225 topo_node->object = NULL; 7226 if (topo_head == NULL) { 7227 topo_head = topo_tail = topo_node; 7228 } else { 7229 topo_tail->next = topo_node; 7230 topo_tail = topo_node; 7231 } 7232 break; 7233 } 7234 case MPI2_EVENT_IR_CHANGE_RC_REMOVED: 7235 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED: 7236 { 7237 NDBG20(("mptsas %d volume deleted\n", 7238 mpt->m_instance)); 7239 ptgt = mptsas_search_by_devhdl(tgttbl, 7240 volhandle); 7241 if (ptgt == NULL) 7242 break; 7243 7244 /* 7245 * Clear any flags related to volume 7246 */ 7247 (void) mptsas_delete_volume(mpt, volhandle); 7248 7249 /* 7250 * Update DR flag immediately avoid I/O failure 7251 */ 7252 mutex_enter(&ptgt->m_tgt_intr_mutex); 7253 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7254 mutex_exit(&ptgt->m_tgt_intr_mutex); 7255 7256 topo_node = kmem_zalloc( 7257 sizeof (mptsas_topo_change_list_t), 7258 KM_SLEEP); 7259 topo_node->mpt = mpt; 7260 topo_node->un.phymask = ptgt->m_phymask; 7261 topo_node->event = 7262 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7263 topo_node->devhdl = volhandle; 7264 topo_node->flags = 7265 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7266 topo_node->object = (void *)ptgt; 7267 if (topo_head == NULL) { 7268 topo_head = topo_tail = topo_node; 7269 } else { 7270 topo_tail->next = topo_node; 7271 topo_tail = topo_node; 7272 } 7273 break; 7274 } 7275 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED: 7276 case MPI2_EVENT_IR_CHANGE_RC_HIDE: 7277 { 7278 ptgt = mptsas_search_by_devhdl(tgttbl, 7279 diskhandle); 7280 if (ptgt == NULL) 7281 break; 7282 7283 /* 7284 * Update DR flag immediately avoid I/O failure 7285 */ 7286 mutex_enter(&ptgt->m_tgt_intr_mutex); 7287 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7288 mutex_exit(&ptgt->m_tgt_intr_mutex); 7289 7290 topo_node = kmem_zalloc( 7291 sizeof (mptsas_topo_change_list_t), 7292 KM_SLEEP); 7293 topo_node->mpt = mpt; 7294 topo_node->un.phymask = ptgt->m_phymask; 7295 topo_node->event = 7296 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7297 topo_node->devhdl = diskhandle; 7298 topo_node->flags = 7299 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7300 topo_node->object = (void *)ptgt; 7301 if (topo_head == NULL) { 7302 topo_head = topo_tail = topo_node; 7303 } else { 7304 topo_tail->next = topo_node; 7305 topo_tail = topo_node; 7306 } 7307 break; 7308 } 7309 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE: 7310 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED: 7311 { 7312 /* 7313 * The physical drive is released by a IR 7314 * volume. But we cannot get the the physport 7315 * or phynum from the event data, so we only 7316 * can get the physport/phynum after SAS 7317 * Device Page0 request for the devhdl. 7318 */ 7319 topo_node = kmem_zalloc( 7320 sizeof (mptsas_topo_change_list_t), 7321 KM_SLEEP); 7322 topo_node->mpt = mpt; 7323 topo_node->un.phymask = 0; 7324 topo_node->event = 7325 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7326 topo_node->devhdl = diskhandle; 7327 topo_node->flags = 7328 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7329 topo_node->object = NULL; 7330 mpt->m_port_chng = 1; 7331 if (topo_head == NULL) { 7332 topo_head = topo_tail = topo_node; 7333 } else { 7334 topo_tail->next = topo_node; 7335 topo_tail = topo_node; 7336 } 7337 break; 7338 } 7339 default: 7340 break; 7341 } 7342 } 7343 7344 if (topo_head != NULL) { 7345 /* 7346 * Launch DR taskq to handle topology change 7347 */ 7348 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7349 mptsas_handle_dr, (void *)topo_head, 7350 DDI_NOSLEEP)) != DDI_SUCCESS) { 7351 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7352 "for handle SAS DR event failed. \n"); 7353 } 7354 } 7355 break; 7356 } 7357 default: 7358 return (DDI_FAILURE); 7359 } 7360 7361 return (DDI_SUCCESS); 7362 } 7363 7364 /* 7365 * handle events from ioc 7366 */ 7367 static void 7368 mptsas_handle_event(void *args) 7369 { 7370 m_replyh_arg_t *replyh_arg; 7371 pMpi2EventNotificationReply_t eventreply; 7372 uint32_t event, iocloginfo, rfm; 7373 uint32_t status; 7374 uint8_t port; 7375 mptsas_t *mpt; 7376 uint_t iocstatus; 7377 7378 replyh_arg = (m_replyh_arg_t *)args; 7379 rfm = replyh_arg->rfm; 7380 mpt = replyh_arg->mpt; 7381 7382 mutex_enter(&mpt->m_mutex); 7383 7384 eventreply = (pMpi2EventNotificationReply_t) 7385 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr)); 7386 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7387 7388 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 7389 &eventreply->IOCStatus)) { 7390 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 7391 mptsas_log(mpt, CE_WARN, 7392 "!mptsas_handle_event: IOCStatus=0x%x, " 7393 "IOCLogInfo=0x%x", iocstatus, 7394 ddi_get32(mpt->m_acc_reply_frame_hdl, 7395 &eventreply->IOCLogInfo)); 7396 } else { 7397 mptsas_log(mpt, CE_WARN, 7398 "mptsas_handle_event: IOCStatus=0x%x, " 7399 "IOCLogInfo=0x%x", iocstatus, 7400 ddi_get32(mpt->m_acc_reply_frame_hdl, 7401 &eventreply->IOCLogInfo)); 7402 } 7403 } 7404 7405 /* 7406 * figure out what kind of event we got and handle accordingly 7407 */ 7408 switch (event) { 7409 case MPI2_EVENT_LOG_ENTRY_ADDED: 7410 break; 7411 case MPI2_EVENT_LOG_DATA: 7412 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7413 &eventreply->IOCLogInfo); 7414 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance, 7415 iocloginfo)); 7416 break; 7417 case MPI2_EVENT_STATE_CHANGE: 7418 NDBG20(("mptsas%d state change.", mpt->m_instance)); 7419 break; 7420 case MPI2_EVENT_HARD_RESET_RECEIVED: 7421 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7422 break; 7423 case MPI2_EVENT_SAS_DISCOVERY: 7424 { 7425 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery; 7426 char string[80]; 7427 uint8_t rc; 7428 7429 sasdiscovery = 7430 (pMpi2EventDataSasDiscovery_t)eventreply->EventData; 7431 7432 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7433 &sasdiscovery->ReasonCode); 7434 port = ddi_get8(mpt->m_acc_reply_frame_hdl, 7435 &sasdiscovery->PhysicalPort); 7436 status = ddi_get32(mpt->m_acc_reply_frame_hdl, 7437 &sasdiscovery->DiscoveryStatus); 7438 7439 string[0] = 0; 7440 switch (rc) { 7441 case MPI2_EVENT_SAS_DISC_RC_STARTED: 7442 (void) sprintf(string, "STARTING"); 7443 break; 7444 case MPI2_EVENT_SAS_DISC_RC_COMPLETED: 7445 (void) sprintf(string, "COMPLETED"); 7446 break; 7447 default: 7448 (void) sprintf(string, "UNKNOWN"); 7449 break; 7450 } 7451 7452 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string, 7453 port, status)); 7454 7455 break; 7456 } 7457 case MPI2_EVENT_EVENT_CHANGE: 7458 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7459 break; 7460 case MPI2_EVENT_TASK_SET_FULL: 7461 { 7462 pMpi2EventDataTaskSetFull_t taskfull; 7463 7464 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData; 7465 7466 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n", 7467 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 7468 &taskfull->CurrentDepth))); 7469 break; 7470 } 7471 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 7472 { 7473 /* 7474 * SAS TOPOLOGY CHANGE LIST Event has already been handled 7475 * in mptsas_handle_event_sync() of interrupt context 7476 */ 7477 break; 7478 } 7479 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 7480 { 7481 pMpi2EventDataSasEnclDevStatusChange_t encstatus; 7482 uint8_t rc; 7483 char string[80]; 7484 7485 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t) 7486 eventreply->EventData; 7487 7488 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7489 &encstatus->ReasonCode); 7490 switch (rc) { 7491 case MPI2_EVENT_SAS_ENCL_RC_ADDED: 7492 (void) sprintf(string, "added"); 7493 break; 7494 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING: 7495 (void) sprintf(string, ", not responding"); 7496 break; 7497 default: 7498 break; 7499 } 7500 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure %x%s\n", 7501 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 7502 &encstatus->EnclosureHandle), string)); 7503 break; 7504 } 7505 7506 /* 7507 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by 7508 * mptsas_handle_event_sync,in here just send ack message. 7509 */ 7510 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 7511 { 7512 pMpi2EventDataSasDeviceStatusChange_t statuschange; 7513 uint8_t rc; 7514 uint16_t devhdl; 7515 uint64_t wwn = 0; 7516 uint32_t wwn_lo, wwn_hi; 7517 7518 statuschange = (pMpi2EventDataSasDeviceStatusChange_t) 7519 eventreply->EventData; 7520 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7521 &statuschange->ReasonCode); 7522 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7523 (uint32_t *)(void *)&statuschange->SASAddress); 7524 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl, 7525 (uint32_t *)(void *)&statuschange->SASAddress + 1); 7526 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo; 7527 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7528 &statuschange->DevHandle); 7529 7530 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64, 7531 wwn)); 7532 7533 switch (rc) { 7534 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7535 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x", 7536 ddi_get8(mpt->m_acc_reply_frame_hdl, 7537 &statuschange->ASC), 7538 ddi_get8(mpt->m_acc_reply_frame_hdl, 7539 &statuschange->ASCQ))); 7540 break; 7541 7542 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7543 NDBG20(("Device not supported")); 7544 break; 7545 7546 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7547 NDBG20(("IOC internally generated the Target Reset " 7548 "for devhdl:%x", devhdl)); 7549 break; 7550 7551 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET: 7552 NDBG20(("IOC's internally generated Target Reset " 7553 "completed for devhdl:%x", devhdl)); 7554 break; 7555 7556 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7557 NDBG20(("IOC internally generated Abort Task")); 7558 break; 7559 7560 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL: 7561 NDBG20(("IOC's internally generated Abort Task " 7562 "completed")); 7563 break; 7564 7565 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 7566 NDBG20(("IOC internally generated Abort Task Set")); 7567 break; 7568 7569 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 7570 NDBG20(("IOC internally generated Clear Task Set")); 7571 break; 7572 7573 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 7574 NDBG20(("IOC internally generated Query Task")); 7575 break; 7576 7577 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION: 7578 NDBG20(("Device sent an Asynchronous Notification")); 7579 break; 7580 7581 default: 7582 break; 7583 } 7584 break; 7585 } 7586 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7587 { 7588 /* 7589 * IR TOPOLOGY CHANGE LIST Event has already been handled 7590 * in mpt_handle_event_sync() of interrupt context 7591 */ 7592 break; 7593 } 7594 case MPI2_EVENT_IR_OPERATION_STATUS: 7595 { 7596 Mpi2EventDataIrOperationStatus_t *irOpStatus; 7597 char reason_str[80]; 7598 uint8_t rc, percent; 7599 uint16_t handle; 7600 7601 irOpStatus = (pMpi2EventDataIrOperationStatus_t) 7602 eventreply->EventData; 7603 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7604 &irOpStatus->RAIDOperation); 7605 percent = ddi_get8(mpt->m_acc_reply_frame_hdl, 7606 &irOpStatus->PercentComplete); 7607 handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7608 &irOpStatus->VolDevHandle); 7609 7610 switch (rc) { 7611 case MPI2_EVENT_IR_RAIDOP_RESYNC: 7612 (void) sprintf(reason_str, "resync"); 7613 break; 7614 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION: 7615 (void) sprintf(reason_str, "online capacity " 7616 "expansion"); 7617 break; 7618 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK: 7619 (void) sprintf(reason_str, "consistency check"); 7620 break; 7621 default: 7622 (void) sprintf(reason_str, "unknown reason %x", 7623 rc); 7624 } 7625 7626 NDBG20(("mptsas%d raid operational status: (%s)" 7627 "\thandle(0x%04x), percent complete(%d)\n", 7628 mpt->m_instance, reason_str, handle, percent)); 7629 break; 7630 } 7631 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 7632 { 7633 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast; 7634 uint8_t phy_num; 7635 uint8_t primitive; 7636 7637 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t) 7638 eventreply->EventData; 7639 7640 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 7641 &sas_broadcast->PhyNum); 7642 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl, 7643 &sas_broadcast->Primitive); 7644 7645 switch (primitive) { 7646 case MPI2_EVENT_PRIMITIVE_CHANGE: 7647 mptsas_smhba_log_sysevent(mpt, 7648 ESC_SAS_HBA_PORT_BROADCAST, 7649 SAS_PORT_BROADCAST_CHANGE, 7650 &mpt->m_phy_info[phy_num].smhba_info); 7651 break; 7652 case MPI2_EVENT_PRIMITIVE_SES: 7653 mptsas_smhba_log_sysevent(mpt, 7654 ESC_SAS_HBA_PORT_BROADCAST, 7655 SAS_PORT_BROADCAST_SES, 7656 &mpt->m_phy_info[phy_num].smhba_info); 7657 break; 7658 case MPI2_EVENT_PRIMITIVE_EXPANDER: 7659 mptsas_smhba_log_sysevent(mpt, 7660 ESC_SAS_HBA_PORT_BROADCAST, 7661 SAS_PORT_BROADCAST_D01_4, 7662 &mpt->m_phy_info[phy_num].smhba_info); 7663 break; 7664 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT: 7665 mptsas_smhba_log_sysevent(mpt, 7666 ESC_SAS_HBA_PORT_BROADCAST, 7667 SAS_PORT_BROADCAST_D04_7, 7668 &mpt->m_phy_info[phy_num].smhba_info); 7669 break; 7670 case MPI2_EVENT_PRIMITIVE_RESERVED3: 7671 mptsas_smhba_log_sysevent(mpt, 7672 ESC_SAS_HBA_PORT_BROADCAST, 7673 SAS_PORT_BROADCAST_D16_7, 7674 &mpt->m_phy_info[phy_num].smhba_info); 7675 break; 7676 case MPI2_EVENT_PRIMITIVE_RESERVED4: 7677 mptsas_smhba_log_sysevent(mpt, 7678 ESC_SAS_HBA_PORT_BROADCAST, 7679 SAS_PORT_BROADCAST_D29_7, 7680 &mpt->m_phy_info[phy_num].smhba_info); 7681 break; 7682 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED: 7683 mptsas_smhba_log_sysevent(mpt, 7684 ESC_SAS_HBA_PORT_BROADCAST, 7685 SAS_PORT_BROADCAST_D24_0, 7686 &mpt->m_phy_info[phy_num].smhba_info); 7687 break; 7688 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED: 7689 mptsas_smhba_log_sysevent(mpt, 7690 ESC_SAS_HBA_PORT_BROADCAST, 7691 SAS_PORT_BROADCAST_D27_4, 7692 &mpt->m_phy_info[phy_num].smhba_info); 7693 break; 7694 default: 7695 NDBG20(("mptsas%d: unknown BROADCAST PRIMITIVE" 7696 " %x received", 7697 mpt->m_instance, primitive)); 7698 break; 7699 } 7700 NDBG20(("mptsas%d sas broadcast primitive: " 7701 "\tprimitive(0x%04x), phy(%d) complete\n", 7702 mpt->m_instance, primitive, phy_num)); 7703 break; 7704 } 7705 case MPI2_EVENT_IR_VOLUME: 7706 { 7707 Mpi2EventDataIrVolume_t *irVolume; 7708 uint16_t devhandle; 7709 uint32_t state; 7710 int config, vol; 7711 mptsas_slots_t *slots = mpt->m_active; 7712 uint8_t found = FALSE; 7713 7714 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData; 7715 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 7716 &irVolume->NewValue); 7717 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7718 &irVolume->VolDevHandle); 7719 7720 NDBG20(("EVENT_IR_VOLUME event is received")); 7721 7722 /* 7723 * Get latest RAID info and then find the DevHandle for this 7724 * event in the configuration. If the DevHandle is not found 7725 * just exit the event. 7726 */ 7727 (void) mptsas_get_raid_info(mpt); 7728 for (config = 0; (config < slots->m_num_raid_configs) && 7729 (!found); config++) { 7730 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 7731 if (slots->m_raidconfig[config].m_raidvol[vol]. 7732 m_raidhandle == devhandle) { 7733 found = TRUE; 7734 break; 7735 } 7736 } 7737 } 7738 if (!found) { 7739 break; 7740 } 7741 7742 switch (irVolume->ReasonCode) { 7743 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED: 7744 { 7745 uint32_t i; 7746 slots->m_raidconfig[config].m_raidvol[vol].m_settings = 7747 state; 7748 7749 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING; 7750 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed" 7751 ", auto-config of hot-swap drives is %s" 7752 ", write caching is %s" 7753 ", hot-spare pool mask is %02x\n", 7754 vol, state & 7755 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE 7756 ? "disabled" : "enabled", 7757 i == MPI2_RAIDVOL0_SETTING_UNCHANGED 7758 ? "controlled by member disks" : 7759 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING 7760 ? "disabled" : 7761 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING 7762 ? "enabled" : 7763 "incorrectly set", 7764 (state >> 16) & 0xff); 7765 break; 7766 } 7767 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED: 7768 { 7769 slots->m_raidconfig[config].m_raidvol[vol].m_state = 7770 (uint8_t)state; 7771 7772 mptsas_log(mpt, CE_NOTE, 7773 "Volume %d is now %s\n", vol, 7774 state == MPI2_RAID_VOL_STATE_OPTIMAL 7775 ? "optimal" : 7776 state == MPI2_RAID_VOL_STATE_DEGRADED 7777 ? "degraded" : 7778 state == MPI2_RAID_VOL_STATE_ONLINE 7779 ? "online" : 7780 state == MPI2_RAID_VOL_STATE_INITIALIZING 7781 ? "initializing" : 7782 state == MPI2_RAID_VOL_STATE_FAILED 7783 ? "failed" : 7784 state == MPI2_RAID_VOL_STATE_MISSING 7785 ? "missing" : 7786 "state unknown"); 7787 break; 7788 } 7789 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED: 7790 { 7791 slots->m_raidconfig[config].m_raidvol[vol]. 7792 m_statusflags = state; 7793 7794 mptsas_log(mpt, CE_NOTE, 7795 " Volume %d is now %s%s%s%s%s%s%s%s%s\n", 7796 vol, 7797 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED 7798 ? ", enabled" : ", disabled", 7799 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED 7800 ? ", quiesced" : "", 7801 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE 7802 ? ", inactive" : ", active", 7803 state & 7804 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL 7805 ? ", bad block table is full" : "", 7806 state & 7807 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 7808 ? ", resync in progress" : "", 7809 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT 7810 ? ", background initialization in progress" : "", 7811 state & 7812 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION 7813 ? ", capacity expansion in progress" : "", 7814 state & 7815 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK 7816 ? ", consistency check in progress" : "", 7817 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB 7818 ? ", data scrub in progress" : ""); 7819 break; 7820 } 7821 default: 7822 break; 7823 } 7824 break; 7825 } 7826 case MPI2_EVENT_IR_PHYSICAL_DISK: 7827 { 7828 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk; 7829 uint16_t devhandle, enchandle, slot; 7830 uint32_t status, state; 7831 uint8_t physdisknum, reason; 7832 7833 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *) 7834 eventreply->EventData; 7835 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl, 7836 &irPhysDisk->PhysDiskNum); 7837 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7838 &irPhysDisk->PhysDiskDevHandle); 7839 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7840 &irPhysDisk->EnclosureHandle); 7841 slot = ddi_get16(mpt->m_acc_reply_frame_hdl, 7842 &irPhysDisk->Slot); 7843 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 7844 &irPhysDisk->NewValue); 7845 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 7846 &irPhysDisk->ReasonCode); 7847 7848 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received")); 7849 7850 switch (reason) { 7851 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED: 7852 mptsas_log(mpt, CE_NOTE, 7853 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 7854 "for enclosure with handle 0x%x is now in hot " 7855 "spare pool %d", 7856 physdisknum, devhandle, slot, enchandle, 7857 (state >> 16) & 0xff); 7858 break; 7859 7860 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED: 7861 status = state; 7862 mptsas_log(mpt, CE_NOTE, 7863 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 7864 "for enclosure with handle 0x%x is now " 7865 "%s%s%s%s%s\n", physdisknum, devhandle, slot, 7866 enchandle, 7867 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME 7868 ? ", inactive" : ", active", 7869 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 7870 ? ", out of sync" : "", 7871 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED 7872 ? ", quiesced" : "", 7873 status & 7874 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED 7875 ? ", write cache enabled" : "", 7876 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET 7877 ? ", capacity expansion target" : ""); 7878 break; 7879 7880 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED: 7881 mptsas_log(mpt, CE_NOTE, 7882 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 7883 "for enclosure with handle 0x%x is now %s\n", 7884 physdisknum, devhandle, slot, enchandle, 7885 state == MPI2_RAID_PD_STATE_OPTIMAL 7886 ? "optimal" : 7887 state == MPI2_RAID_PD_STATE_REBUILDING 7888 ? "rebuilding" : 7889 state == MPI2_RAID_PD_STATE_DEGRADED 7890 ? "degraded" : 7891 state == MPI2_RAID_PD_STATE_HOT_SPARE 7892 ? "a hot spare" : 7893 state == MPI2_RAID_PD_STATE_ONLINE 7894 ? "online" : 7895 state == MPI2_RAID_PD_STATE_OFFLINE 7896 ? "offline" : 7897 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE 7898 ? "not compatible" : 7899 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED 7900 ? "not configured" : 7901 "state unknown"); 7902 break; 7903 } 7904 break; 7905 } 7906 default: 7907 NDBG20(("mptsas%d: unknown event %x received", 7908 mpt->m_instance, event)); 7909 break; 7910 } 7911 7912 /* 7913 * Return the reply frame to the free queue. 7914 */ 7915 ddi_put32(mpt->m_acc_free_queue_hdl, 7916 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm); 7917 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 7918 DDI_DMA_SYNC_FORDEV); 7919 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 7920 mpt->m_free_index = 0; 7921 } 7922 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 7923 mpt->m_free_index); 7924 mutex_exit(&mpt->m_mutex); 7925 } 7926 7927 /* 7928 * invoked from timeout() to restart qfull cmds with throttle == 0 7929 */ 7930 static void 7931 mptsas_restart_cmd(void *arg) 7932 { 7933 mptsas_t *mpt = arg; 7934 mptsas_target_t *ptgt = NULL; 7935 7936 mutex_enter(&mpt->m_mutex); 7937 7938 mpt->m_restart_cmd_timeid = 0; 7939 7940 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 7941 MPTSAS_HASH_FIRST); 7942 while (ptgt != NULL) { 7943 mutex_enter(&ptgt->m_tgt_intr_mutex); 7944 if (ptgt->m_reset_delay == 0) { 7945 if (ptgt->m_t_throttle == QFULL_THROTTLE) { 7946 mptsas_set_throttle(mpt, ptgt, 7947 MAX_THROTTLE); 7948 } 7949 } 7950 mutex_exit(&ptgt->m_tgt_intr_mutex); 7951 7952 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 7953 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 7954 } 7955 mptsas_restart_hba(mpt); 7956 mutex_exit(&mpt->m_mutex); 7957 } 7958 7959 /* 7960 * mptsas_remove_cmd0 is similar to mptsas_remove_cmd except that it is called 7961 * where m_intr_mutex has already been held. 7962 */ 7963 void 7964 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 7965 { 7966 ASSERT(mutex_owned(&mpt->m_mutex)); 7967 7968 /* 7969 * With new fine-grained lock mechanism, the outstanding cmd is only 7970 * linked to m_active before the dma is triggerred(MPTSAS_START_CMD) 7971 * to send it. that is, mptsas_save_cmd() doesn't link the outstanding 7972 * cmd now. So when mptsas_remove_cmd is called, a mptsas_save_cmd must 7973 * have been called, but the cmd may have not been linked. 7974 * For mptsas_remove_cmd0, the cmd must have been linked. 7975 * In order to keep the same semantic, we link the cmd to the 7976 * outstanding cmd list. 7977 */ 7978 mpt->m_active->m_slot[cmd->cmd_slot] = cmd; 7979 7980 mutex_enter(&mpt->m_intr_mutex); 7981 mptsas_remove_cmd0(mpt, cmd); 7982 mutex_exit(&mpt->m_intr_mutex); 7983 } 7984 7985 static inline void 7986 mptsas_remove_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd) 7987 { 7988 int slot; 7989 mptsas_slots_t *slots = mpt->m_active; 7990 int t; 7991 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 7992 mptsas_slot_free_e_t *pe; 7993 7994 ASSERT(cmd != NULL); 7995 ASSERT(cmd->cmd_queued == FALSE); 7996 7997 /* 7998 * Task Management cmds are removed in their own routines. Also, 7999 * we don't want to modify timeout based on TM cmds. 8000 */ 8001 if (cmd->cmd_flags & CFLAG_TM_CMD) { 8002 return; 8003 } 8004 8005 t = Tgt(cmd); 8006 slot = cmd->cmd_slot; 8007 pe = mpt->m_slot_free_ae + slot - 1; 8008 ASSERT(cmd == slots->m_slot[slot]); 8009 ASSERT((slot > 0) && slot < (mpt->m_max_requests - 1)); 8010 8011 /* 8012 * remove the cmd. 8013 */ 8014 mutex_enter(&mpt->m_slot_freeq_pairp[pe->cpuid]. 8015 m_slot_releq.s.m_fq_mutex); 8016 NDBG31(("mptsas_remove_cmd0: removing cmd=0x%p", (void *)cmd)); 8017 slots->m_slot[slot] = NULL; 8018 ASSERT(pe->slot == slot); 8019 list_insert_tail(&mpt->m_slot_freeq_pairp[pe->cpuid]. 8020 m_slot_releq.s.m_fq_list, pe); 8021 mpt->m_slot_freeq_pairp[pe->cpuid].m_slot_releq.s.m_fq_n++; 8022 ASSERT(mpt->m_slot_freeq_pairp[pe->cpuid]. 8023 m_slot_releq.s.m_fq_n <= mpt->m_max_requests - 2); 8024 mutex_exit(&mpt->m_slot_freeq_pairp[pe->cpuid]. 8025 m_slot_releq.s.m_fq_mutex); 8026 8027 /* 8028 * only decrement per target ncmds if command 8029 * has a target associated with it. 8030 */ 8031 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 8032 mutex_enter(&ptgt->m_tgt_intr_mutex); 8033 ptgt->m_t_ncmds--; 8034 /* 8035 * reset throttle if we just ran an untagged command 8036 * to a tagged target 8037 */ 8038 if ((ptgt->m_t_ncmds == 0) && 8039 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) { 8040 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8041 } 8042 mutex_exit(&ptgt->m_tgt_intr_mutex); 8043 } 8044 8045 /* 8046 * This is all we need to do for ioc commands. 8047 * The ioc cmds would never be handled in fastpath in ISR, so we make 8048 * sure the mptsas_return_to_pool() would always be called with 8049 * m_mutex protected. 8050 */ 8051 if (cmd->cmd_flags & CFLAG_CMDIOC) { 8052 ASSERT(mutex_owned(&mpt->m_mutex)); 8053 mptsas_return_to_pool(mpt, cmd); 8054 return; 8055 } 8056 8057 /* 8058 * Figure out what to set tag Q timeout for... 8059 * 8060 * Optimize: If we have duplicate's of same timeout 8061 * we're using, then we'll use it again until we run 8062 * out of duplicates. This should be the normal case 8063 * for block and raw I/O. 8064 * If no duplicates, we have to scan through tag que and 8065 * find the longest timeout value and use it. This is 8066 * going to take a while... 8067 * Add 1 to m_n_slots to account for TM request. 8068 */ 8069 mutex_enter(&ptgt->m_tgt_intr_mutex); 8070 if (cmd->cmd_pkt->pkt_time == ptgt->m_timebase) { 8071 if (--(ptgt->m_dups) == 0) { 8072 if (ptgt->m_t_ncmds) { 8073 mptsas_cmd_t *ssp; 8074 uint_t n = 0; 8075 ushort_t nslots = (slots->m_n_slots + 1); 8076 ushort_t i; 8077 /* 8078 * This crude check assumes we don't do 8079 * this too often which seems reasonable 8080 * for block and raw I/O. 8081 */ 8082 for (i = 0; i < nslots; i++) { 8083 ssp = slots->m_slot[i]; 8084 if (ssp && (Tgt(ssp) == t) && 8085 (ssp->cmd_pkt->pkt_time > n)) { 8086 n = ssp->cmd_pkt->pkt_time; 8087 ptgt->m_dups = 1; 8088 } else if (ssp && (Tgt(ssp) == t) && 8089 (ssp->cmd_pkt->pkt_time == n)) { 8090 ptgt->m_dups++; 8091 } 8092 } 8093 ptgt->m_timebase = n; 8094 } else { 8095 ptgt->m_dups = 0; 8096 ptgt->m_timebase = 0; 8097 } 8098 } 8099 } 8100 ptgt->m_timeout = ptgt->m_timebase; 8101 8102 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]); 8103 mutex_exit(&ptgt->m_tgt_intr_mutex); 8104 } 8105 8106 /* 8107 * start a fresh request from the top of the device queue. 8108 */ 8109 static void 8110 mptsas_restart_hba(mptsas_t *mpt) 8111 { 8112 mptsas_cmd_t *cmd, *next_cmd; 8113 mptsas_target_t *ptgt = NULL; 8114 8115 NDBG1(("mptsas_restart_hba: mpt=0x%p", (void *)mpt)); 8116 8117 ASSERT(mutex_owned(&mpt->m_mutex)); 8118 8119 /* 8120 * If there is a reset delay, don't start any cmds. Otherwise, start 8121 * as many cmds as possible. 8122 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 8123 * commands is m_max_requests - 2. 8124 */ 8125 cmd = mpt->m_waitq; 8126 8127 while (cmd != NULL) { 8128 next_cmd = cmd->cmd_linkp; 8129 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 8130 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8131 /* 8132 * passthru command get slot need 8133 * set CFLAG_PREPARED. 8134 */ 8135 cmd->cmd_flags |= CFLAG_PREPARED; 8136 mptsas_waitq_delete(mpt, cmd); 8137 mptsas_start_passthru(mpt, cmd); 8138 } 8139 cmd = next_cmd; 8140 continue; 8141 } 8142 if (cmd->cmd_flags & CFLAG_CONFIG) { 8143 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8144 /* 8145 * Send the config page request and delete it 8146 * from the waitq. 8147 */ 8148 cmd->cmd_flags |= CFLAG_PREPARED; 8149 mptsas_waitq_delete(mpt, cmd); 8150 mptsas_start_config_page_access(mpt, cmd); 8151 } 8152 cmd = next_cmd; 8153 continue; 8154 } 8155 if (cmd->cmd_flags & CFLAG_FW_DIAG) { 8156 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8157 /* 8158 * Send the FW Diag request and delete if from 8159 * the waitq. 8160 */ 8161 cmd->cmd_flags |= CFLAG_PREPARED; 8162 mptsas_waitq_delete(mpt, cmd); 8163 mptsas_start_diag(mpt, cmd); 8164 } 8165 cmd = next_cmd; 8166 continue; 8167 } 8168 8169 ptgt = cmd->cmd_tgt_addr; 8170 if (ptgt) { 8171 mutex_enter(&mpt->m_intr_mutex); 8172 mutex_enter(&ptgt->m_tgt_intr_mutex); 8173 if ((ptgt->m_t_throttle == DRAIN_THROTTLE) && 8174 (ptgt->m_t_ncmds == 0)) { 8175 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8176 } 8177 if ((ptgt->m_reset_delay == 0) && 8178 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) { 8179 mutex_exit(&ptgt->m_tgt_intr_mutex); 8180 mutex_exit(&mpt->m_intr_mutex); 8181 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8182 mptsas_waitq_delete(mpt, cmd); 8183 (void) mptsas_start_cmd(mpt, cmd); 8184 } 8185 goto out; 8186 } 8187 mutex_exit(&ptgt->m_tgt_intr_mutex); 8188 mutex_exit(&mpt->m_intr_mutex); 8189 } 8190 out: 8191 cmd = next_cmd; 8192 } 8193 } 8194 8195 /* 8196 * mpt tag type lookup 8197 */ 8198 static char mptsas_tag_lookup[] = 8199 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG}; 8200 8201 /* 8202 * mptsas_start_cmd0 is similar to mptsas_start_cmd, except that, it is called 8203 * without ANY mutex protected, while, mptsas_start_cmd is called with m_mutex 8204 * protected. 8205 * 8206 * the relevant field in ptgt should be protected by m_tgt_intr_mutex in both 8207 * functions. 8208 * 8209 * before the cmds are linked on the slot for monitor as outstanding cmds, they 8210 * are accessed as slab objects, so slab framework ensures the exclusive access, 8211 * and no other mutex is requireed. Linking for monitor and the trigger of dma 8212 * must be done exclusively. 8213 */ 8214 static int 8215 mptsas_start_cmd0(mptsas_t *mpt, mptsas_cmd_t *cmd) 8216 { 8217 struct scsi_pkt *pkt = CMD2PKT(cmd); 8218 uint32_t control = 0; 8219 int n; 8220 caddr_t mem; 8221 pMpi2SCSIIORequest_t io_request; 8222 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 8223 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 8224 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8225 uint16_t SMID, io_flags = 0; 8226 uint32_t request_desc_low, request_desc_high; 8227 8228 NDBG1(("mptsas_start_cmd0: cmd=0x%p", (void *)cmd)); 8229 8230 /* 8231 * Set SMID and increment index. Rollover to 1 instead of 0 if index 8232 * is at the max. 0 is an invalid SMID, so we call the first index 1. 8233 */ 8234 SMID = cmd->cmd_slot; 8235 8236 /* 8237 * It is possible for back to back device reset to 8238 * happen before the reset delay has expired. That's 8239 * ok, just let the device reset go out on the bus. 8240 */ 8241 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8242 ASSERT(ptgt->m_reset_delay == 0); 8243 } 8244 8245 /* 8246 * if a non-tagged cmd is submitted to an active tagged target 8247 * then drain before submitting this cmd; SCSI-2 allows RQSENSE 8248 * to be untagged 8249 */ 8250 mutex_enter(&ptgt->m_tgt_intr_mutex); 8251 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) && 8252 (ptgt->m_t_ncmds > 1) && 8253 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) && 8254 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) { 8255 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8256 NDBG23(("target=%d, untagged cmd, start draining\n", 8257 ptgt->m_devhdl)); 8258 8259 if (ptgt->m_reset_delay == 0) { 8260 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 8261 } 8262 mutex_exit(&ptgt->m_tgt_intr_mutex); 8263 8264 mutex_enter(&mpt->m_mutex); 8265 mptsas_remove_cmd(mpt, cmd); 8266 cmd->cmd_pkt_flags |= FLAG_HEAD; 8267 mptsas_waitq_add(mpt, cmd); 8268 mutex_exit(&mpt->m_mutex); 8269 return (DDI_FAILURE); 8270 } 8271 mutex_exit(&ptgt->m_tgt_intr_mutex); 8272 return (DDI_FAILURE); 8273 } 8274 mutex_exit(&ptgt->m_tgt_intr_mutex); 8275 8276 /* 8277 * Set correct tag bits. 8278 */ 8279 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) { 8280 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags & 8281 FLAG_TAGMASK) >> 12)]) { 8282 case MSG_SIMPLE_QTAG: 8283 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8284 break; 8285 case MSG_HEAD_QTAG: 8286 control |= MPI2_SCSIIO_CONTROL_HEADOFQ; 8287 break; 8288 case MSG_ORDERED_QTAG: 8289 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ; 8290 break; 8291 default: 8292 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n"); 8293 break; 8294 } 8295 } else { 8296 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) { 8297 ptgt->m_t_throttle = 1; 8298 } 8299 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8300 } 8301 8302 if (cmd->cmd_pkt_flags & FLAG_TLR) { 8303 control |= MPI2_SCSIIO_CONTROL_TLR_ON; 8304 } 8305 8306 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 8307 io_request = (pMpi2SCSIIORequest_t)mem; 8308 8309 bzero(io_request, sizeof (Mpi2SCSIIORequest_t)); 8310 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof 8311 (MPI2_SCSI_IO_REQUEST, SGL) / 4); 8312 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0, 8313 MPI2_FUNCTION_SCSI_IO_REQUEST); 8314 8315 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp, 8316 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR); 8317 8318 io_flags = cmd->cmd_cdblen; 8319 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags); 8320 /* 8321 * setup the Scatter/Gather DMA list for this request 8322 */ 8323 if (cmd->cmd_cookiec > 0) { 8324 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl); 8325 } else { 8326 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength, 8327 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT | 8328 MPI2_SGE_FLAGS_END_OF_BUFFER | 8329 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 8330 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT); 8331 } 8332 8333 /* 8334 * save ARQ information 8335 */ 8336 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen); 8337 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) == 8338 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) { 8339 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, 8340 cmd->cmd_ext_arqcookie.dmac_address); 8341 } else { 8342 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, 8343 cmd->cmd_arqcookie.dmac_address); 8344 } 8345 8346 ddi_put32(acc_hdl, &io_request->Control, control); 8347 8348 NDBG31(("starting message=0x%p, with cmd=0x%p", 8349 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd)); 8350 8351 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 8352 8353 /* 8354 * Build request descriptor and write it to the request desc post reg. 8355 */ 8356 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 8357 request_desc_high = ptgt->m_devhdl << 16; 8358 8359 mutex_enter(&mpt->m_mutex); 8360 mpt->m_active->m_slot[cmd->cmd_slot] = cmd; 8361 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high); 8362 mutex_exit(&mpt->m_mutex); 8363 8364 /* 8365 * Start timeout. 8366 */ 8367 mutex_enter(&ptgt->m_tgt_intr_mutex); 8368 #ifdef MPTSAS_TEST 8369 /* 8370 * Temporarily set timebase = 0; needed for 8371 * timeout torture test. 8372 */ 8373 if (mptsas_test_timeouts) { 8374 ptgt->m_timebase = 0; 8375 } 8376 #endif 8377 n = pkt->pkt_time - ptgt->m_timebase; 8378 8379 if (n == 0) { 8380 (ptgt->m_dups)++; 8381 ptgt->m_timeout = ptgt->m_timebase; 8382 } else if (n > 0) { 8383 ptgt->m_timeout = 8384 ptgt->m_timebase = pkt->pkt_time; 8385 ptgt->m_dups = 1; 8386 } else if (n < 0) { 8387 ptgt->m_timeout = ptgt->m_timebase; 8388 } 8389 #ifdef MPTSAS_TEST 8390 /* 8391 * Set back to a number higher than 8392 * mptsas_scsi_watchdog_tick 8393 * so timeouts will happen in mptsas_watchsubr 8394 */ 8395 if (mptsas_test_timeouts) { 8396 ptgt->m_timebase = 60; 8397 } 8398 #endif 8399 mutex_exit(&ptgt->m_tgt_intr_mutex); 8400 8401 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 8402 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 8403 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8404 return (DDI_FAILURE); 8405 } 8406 return (DDI_SUCCESS); 8407 } 8408 8409 static int 8410 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 8411 { 8412 struct scsi_pkt *pkt = CMD2PKT(cmd); 8413 uint32_t control = 0; 8414 int n; 8415 caddr_t mem; 8416 pMpi2SCSIIORequest_t io_request; 8417 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 8418 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 8419 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8420 uint16_t SMID, io_flags = 0; 8421 uint32_t request_desc_low, request_desc_high; 8422 8423 NDBG1(("mptsas_start_cmd: cmd=0x%p", (void *)cmd)); 8424 8425 /* 8426 * Set SMID and increment index. Rollover to 1 instead of 0 if index 8427 * is at the max. 0 is an invalid SMID, so we call the first index 1. 8428 */ 8429 SMID = cmd->cmd_slot; 8430 8431 /* 8432 * It is possible for back to back device reset to 8433 * happen before the reset delay has expired. That's 8434 * ok, just let the device reset go out on the bus. 8435 */ 8436 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8437 ASSERT(ptgt->m_reset_delay == 0); 8438 } 8439 8440 /* 8441 * if a non-tagged cmd is submitted to an active tagged target 8442 * then drain before submitting this cmd; SCSI-2 allows RQSENSE 8443 * to be untagged 8444 */ 8445 mutex_enter(&ptgt->m_tgt_intr_mutex); 8446 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) && 8447 (ptgt->m_t_ncmds > 1) && 8448 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) && 8449 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) { 8450 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8451 NDBG23(("target=%d, untagged cmd, start draining\n", 8452 ptgt->m_devhdl)); 8453 8454 if (ptgt->m_reset_delay == 0) { 8455 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 8456 } 8457 mutex_exit(&ptgt->m_tgt_intr_mutex); 8458 8459 mptsas_remove_cmd(mpt, cmd); 8460 cmd->cmd_pkt_flags |= FLAG_HEAD; 8461 mptsas_waitq_add(mpt, cmd); 8462 return (DDI_FAILURE); 8463 } 8464 mutex_exit(&ptgt->m_tgt_intr_mutex); 8465 return (DDI_FAILURE); 8466 } 8467 mutex_exit(&ptgt->m_tgt_intr_mutex); 8468 8469 /* 8470 * Set correct tag bits. 8471 */ 8472 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) { 8473 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags & 8474 FLAG_TAGMASK) >> 12)]) { 8475 case MSG_SIMPLE_QTAG: 8476 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8477 break; 8478 case MSG_HEAD_QTAG: 8479 control |= MPI2_SCSIIO_CONTROL_HEADOFQ; 8480 break; 8481 case MSG_ORDERED_QTAG: 8482 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ; 8483 break; 8484 default: 8485 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n"); 8486 break; 8487 } 8488 } else { 8489 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) { 8490 ptgt->m_t_throttle = 1; 8491 } 8492 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8493 } 8494 8495 if (cmd->cmd_pkt_flags & FLAG_TLR) { 8496 control |= MPI2_SCSIIO_CONTROL_TLR_ON; 8497 } 8498 8499 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 8500 io_request = (pMpi2SCSIIORequest_t)mem; 8501 8502 bzero(io_request, sizeof (Mpi2SCSIIORequest_t)); 8503 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof 8504 (MPI2_SCSI_IO_REQUEST, SGL) / 4); 8505 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0, 8506 MPI2_FUNCTION_SCSI_IO_REQUEST); 8507 8508 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp, 8509 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR); 8510 8511 io_flags = cmd->cmd_cdblen; 8512 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags); 8513 /* 8514 * setup the Scatter/Gather DMA list for this request 8515 */ 8516 if (cmd->cmd_cookiec > 0) { 8517 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl); 8518 } else { 8519 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength, 8520 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT | 8521 MPI2_SGE_FLAGS_END_OF_BUFFER | 8522 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 8523 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT); 8524 } 8525 8526 /* 8527 * save ARQ information 8528 */ 8529 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen); 8530 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) == 8531 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) { 8532 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, 8533 cmd->cmd_ext_arqcookie.dmac_address); 8534 } else { 8535 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, 8536 cmd->cmd_arqcookie.dmac_address); 8537 } 8538 8539 ddi_put32(acc_hdl, &io_request->Control, control); 8540 8541 NDBG31(("starting message=0x%p, with cmd=0x%p", 8542 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd)); 8543 8544 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 8545 8546 /* 8547 * Build request descriptor and write it to the request desc post reg. 8548 */ 8549 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 8550 request_desc_high = ptgt->m_devhdl << 16; 8551 8552 mpt->m_active->m_slot[cmd->cmd_slot] = cmd; 8553 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high); 8554 8555 /* 8556 * Start timeout. 8557 */ 8558 mutex_enter(&ptgt->m_tgt_intr_mutex); 8559 #ifdef MPTSAS_TEST 8560 /* 8561 * Temporarily set timebase = 0; needed for 8562 * timeout torture test. 8563 */ 8564 if (mptsas_test_timeouts) { 8565 ptgt->m_timebase = 0; 8566 } 8567 #endif 8568 n = pkt->pkt_time - ptgt->m_timebase; 8569 8570 if (n == 0) { 8571 (ptgt->m_dups)++; 8572 ptgt->m_timeout = ptgt->m_timebase; 8573 } else if (n > 0) { 8574 ptgt->m_timeout = 8575 ptgt->m_timebase = pkt->pkt_time; 8576 ptgt->m_dups = 1; 8577 } else if (n < 0) { 8578 ptgt->m_timeout = ptgt->m_timebase; 8579 } 8580 #ifdef MPTSAS_TEST 8581 /* 8582 * Set back to a number higher than 8583 * mptsas_scsi_watchdog_tick 8584 * so timeouts will happen in mptsas_watchsubr 8585 */ 8586 if (mptsas_test_timeouts) { 8587 ptgt->m_timebase = 60; 8588 } 8589 #endif 8590 mutex_exit(&ptgt->m_tgt_intr_mutex); 8591 8592 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 8593 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 8594 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8595 return (DDI_FAILURE); 8596 } 8597 return (DDI_SUCCESS); 8598 } 8599 8600 /* 8601 * Select a helper thread to handle current doneq 8602 */ 8603 static void 8604 mptsas_deliver_doneq_thread(mptsas_t *mpt) 8605 { 8606 uint64_t t, i; 8607 uint32_t min = 0xffffffff; 8608 mptsas_doneq_thread_list_t *item; 8609 8610 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 8611 item = &mpt->m_doneq_thread_id[i]; 8612 /* 8613 * If the completed command on help thread[i] less than 8614 * doneq_thread_threshold, then pick the thread[i]. Otherwise 8615 * pick a thread which has least completed command. 8616 */ 8617 8618 mutex_enter(&item->mutex); 8619 if (item->len < mpt->m_doneq_thread_threshold) { 8620 t = i; 8621 mutex_exit(&item->mutex); 8622 break; 8623 } 8624 if (item->len < min) { 8625 min = item->len; 8626 t = i; 8627 } 8628 mutex_exit(&item->mutex); 8629 } 8630 mutex_enter(&mpt->m_doneq_thread_id[t].mutex); 8631 mptsas_doneq_mv(mpt, t); 8632 cv_signal(&mpt->m_doneq_thread_id[t].cv); 8633 mutex_exit(&mpt->m_doneq_thread_id[t].mutex); 8634 } 8635 8636 /* 8637 * move the current global doneq to the doneq of thread[t] 8638 */ 8639 static void 8640 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t) 8641 { 8642 mptsas_cmd_t *cmd; 8643 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8644 8645 ASSERT(mutex_owned(&item->mutex)); 8646 mutex_enter(&mpt->m_intr_mutex); 8647 while ((cmd = mpt->m_doneq) != NULL) { 8648 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) { 8649 mpt->m_donetail = &mpt->m_doneq; 8650 } 8651 cmd->cmd_linkp = NULL; 8652 *item->donetail = cmd; 8653 item->donetail = &cmd->cmd_linkp; 8654 mpt->m_doneq_len--; 8655 item->len++; 8656 } 8657 mutex_exit(&mpt->m_intr_mutex); 8658 } 8659 8660 void 8661 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd) 8662 { 8663 struct scsi_pkt *pkt = CMD2PKT(cmd); 8664 8665 /* Check all acc and dma handles */ 8666 if ((mptsas_check_acc_handle(mpt->m_datap) != 8667 DDI_SUCCESS) || 8668 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 8669 DDI_SUCCESS) || 8670 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 8671 DDI_SUCCESS) || 8672 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 8673 DDI_SUCCESS) || 8674 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 8675 DDI_SUCCESS) || 8676 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 8677 DDI_SUCCESS) || 8678 (mptsas_check_acc_handle(mpt->m_config_handle) != 8679 DDI_SUCCESS)) { 8680 ddi_fm_service_impact(mpt->m_dip, 8681 DDI_SERVICE_UNAFFECTED); 8682 ddi_fm_acc_err_clear(mpt->m_config_handle, 8683 DDI_FME_VER0); 8684 pkt->pkt_reason = CMD_TRAN_ERR; 8685 pkt->pkt_statistics = 0; 8686 } 8687 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 8688 DDI_SUCCESS) || 8689 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 8690 DDI_SUCCESS) || 8691 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 8692 DDI_SUCCESS) || 8693 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 8694 DDI_SUCCESS) || 8695 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 8696 DDI_SUCCESS)) { 8697 ddi_fm_service_impact(mpt->m_dip, 8698 DDI_SERVICE_UNAFFECTED); 8699 pkt->pkt_reason = CMD_TRAN_ERR; 8700 pkt->pkt_statistics = 0; 8701 } 8702 if (cmd->cmd_dmahandle && 8703 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) { 8704 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8705 pkt->pkt_reason = CMD_TRAN_ERR; 8706 pkt->pkt_statistics = 0; 8707 } 8708 if ((cmd->cmd_extra_frames && 8709 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) != 8710 DDI_SUCCESS) || 8711 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) != 8712 DDI_SUCCESS)))) { 8713 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8714 pkt->pkt_reason = CMD_TRAN_ERR; 8715 pkt->pkt_statistics = 0; 8716 } 8717 if (cmd->cmd_arqhandle && 8718 (mptsas_check_dma_handle(cmd->cmd_arqhandle) != DDI_SUCCESS)) { 8719 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8720 pkt->pkt_reason = CMD_TRAN_ERR; 8721 pkt->pkt_statistics = 0; 8722 } 8723 if (cmd->cmd_ext_arqhandle && 8724 (mptsas_check_dma_handle(cmd->cmd_ext_arqhandle) != DDI_SUCCESS)) { 8725 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8726 pkt->pkt_reason = CMD_TRAN_ERR; 8727 pkt->pkt_statistics = 0; 8728 } 8729 } 8730 8731 /* 8732 * mptsas_doneq_add0 is similar to mptsas_doneq_add except that it is called 8733 * where m_intr_mutex has already been held. 8734 */ 8735 static inline void 8736 mptsas_doneq_add0(mptsas_t *mpt, mptsas_cmd_t *cmd) 8737 { 8738 struct scsi_pkt *pkt = CMD2PKT(cmd); 8739 8740 NDBG31(("mptsas_doneq_add0: cmd=0x%p", (void *)cmd)); 8741 8742 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0); 8743 cmd->cmd_linkp = NULL; 8744 cmd->cmd_flags |= CFLAG_FINISHED; 8745 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT; 8746 8747 /* 8748 * only add scsi pkts that have completion routines to 8749 * the doneq. no intr cmds do not have callbacks. 8750 */ 8751 if (pkt && (pkt->pkt_comp)) { 8752 *mpt->m_donetail = cmd; 8753 mpt->m_donetail = &cmd->cmd_linkp; 8754 mpt->m_doneq_len++; 8755 } 8756 } 8757 8758 /* 8759 * These routines manipulate the queue of commands that 8760 * are waiting for their completion routines to be called. 8761 * The queue is usually in FIFO order but on an MP system 8762 * it's possible for the completion routines to get out 8763 * of order. If that's a problem you need to add a global 8764 * mutex around the code that calls the completion routine 8765 * in the interrupt handler. 8766 */ 8767 static void 8768 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 8769 { 8770 ASSERT(mutex_owned(&mpt->m_mutex)); 8771 8772 mptsas_fma_check(mpt, cmd); 8773 8774 mutex_enter(&mpt->m_intr_mutex); 8775 mptsas_doneq_add0(mpt, cmd); 8776 mutex_exit(&mpt->m_intr_mutex); 8777 } 8778 8779 static mptsas_cmd_t * 8780 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t) 8781 { 8782 mptsas_cmd_t *cmd; 8783 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8784 8785 /* pop one off the done queue */ 8786 if ((cmd = item->doneq) != NULL) { 8787 /* if the queue is now empty fix the tail pointer */ 8788 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd)); 8789 if ((item->doneq = cmd->cmd_linkp) == NULL) { 8790 item->donetail = &item->doneq; 8791 } 8792 cmd->cmd_linkp = NULL; 8793 item->len--; 8794 } 8795 return (cmd); 8796 } 8797 8798 static void 8799 mptsas_doneq_empty(mptsas_t *mpt) 8800 { 8801 mutex_enter(&mpt->m_intr_mutex); 8802 if (mpt->m_doneq && !mpt->m_in_callback) { 8803 mptsas_cmd_t *cmd, *next; 8804 struct scsi_pkt *pkt; 8805 8806 mpt->m_in_callback = 1; 8807 cmd = mpt->m_doneq; 8808 mpt->m_doneq = NULL; 8809 mpt->m_donetail = &mpt->m_doneq; 8810 mpt->m_doneq_len = 0; 8811 8812 mutex_exit(&mpt->m_intr_mutex); 8813 8814 /* 8815 * ONLY in ISR, is it called without m_mutex held, otherwise, 8816 * it is always called with m_mutex held. 8817 */ 8818 if ((curthread->t_flag & T_INTR_THREAD) == 0) 8819 mutex_exit(&mpt->m_mutex); 8820 /* 8821 * run the completion routines of all the 8822 * completed commands 8823 */ 8824 while (cmd != NULL) { 8825 next = cmd->cmd_linkp; 8826 cmd->cmd_linkp = NULL; 8827 /* run this command's completion routine */ 8828 cmd->cmd_flags |= CFLAG_COMPLETED; 8829 pkt = CMD2PKT(cmd); 8830 mptsas_pkt_comp(pkt, cmd); 8831 cmd = next; 8832 } 8833 if ((curthread->t_flag & T_INTR_THREAD) == 0) 8834 mutex_enter(&mpt->m_mutex); 8835 mpt->m_in_callback = 0; 8836 return; 8837 } 8838 mutex_exit(&mpt->m_intr_mutex); 8839 } 8840 8841 /* 8842 * These routines manipulate the target's queue of pending requests 8843 */ 8844 void 8845 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 8846 { 8847 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd)); 8848 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8849 cmd->cmd_queued = TRUE; 8850 if (ptgt) 8851 ptgt->m_t_nwait++; 8852 if (cmd->cmd_pkt_flags & FLAG_HEAD) { 8853 mutex_enter(&mpt->m_intr_mutex); 8854 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) { 8855 mpt->m_waitqtail = &cmd->cmd_linkp; 8856 } 8857 mpt->m_waitq = cmd; 8858 mutex_exit(&mpt->m_intr_mutex); 8859 } else { 8860 cmd->cmd_linkp = NULL; 8861 *(mpt->m_waitqtail) = cmd; 8862 mpt->m_waitqtail = &cmd->cmd_linkp; 8863 } 8864 } 8865 8866 static mptsas_cmd_t * 8867 mptsas_waitq_rm(mptsas_t *mpt) 8868 { 8869 mptsas_cmd_t *cmd; 8870 mptsas_target_t *ptgt; 8871 NDBG7(("mptsas_waitq_rm")); 8872 8873 mutex_enter(&mpt->m_intr_mutex); 8874 MPTSAS_WAITQ_RM(mpt, cmd); 8875 mutex_exit(&mpt->m_intr_mutex); 8876 8877 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd)); 8878 if (cmd) { 8879 ptgt = cmd->cmd_tgt_addr; 8880 if (ptgt) { 8881 ptgt->m_t_nwait--; 8882 ASSERT(ptgt->m_t_nwait >= 0); 8883 } 8884 } 8885 return (cmd); 8886 } 8887 8888 /* 8889 * remove specified cmd from the middle of the wait queue. 8890 */ 8891 static void 8892 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 8893 { 8894 mptsas_cmd_t *prevp = mpt->m_waitq; 8895 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8896 8897 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8898 (void *)mpt, (void *)cmd)); 8899 if (ptgt) { 8900 ptgt->m_t_nwait--; 8901 ASSERT(ptgt->m_t_nwait >= 0); 8902 } 8903 8904 if (prevp == cmd) { 8905 mutex_enter(&mpt->m_intr_mutex); 8906 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL) 8907 mpt->m_waitqtail = &mpt->m_waitq; 8908 mutex_exit(&mpt->m_intr_mutex); 8909 8910 cmd->cmd_linkp = NULL; 8911 cmd->cmd_queued = FALSE; 8912 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8913 (void *)mpt, (void *)cmd)); 8914 return; 8915 } 8916 8917 while (prevp != NULL) { 8918 if (prevp->cmd_linkp == cmd) { 8919 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 8920 mpt->m_waitqtail = &prevp->cmd_linkp; 8921 8922 cmd->cmd_linkp = NULL; 8923 cmd->cmd_queued = FALSE; 8924 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8925 (void *)mpt, (void *)cmd)); 8926 return; 8927 } 8928 prevp = prevp->cmd_linkp; 8929 } 8930 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch"); 8931 } 8932 8933 /* 8934 * device and bus reset handling 8935 * 8936 * Notes: 8937 * - RESET_ALL: reset the controller 8938 * - RESET_TARGET: reset the target specified in scsi_address 8939 */ 8940 static int 8941 mptsas_scsi_reset(struct scsi_address *ap, int level) 8942 { 8943 mptsas_t *mpt = ADDR2MPT(ap); 8944 int rval; 8945 mptsas_tgt_private_t *tgt_private; 8946 mptsas_target_t *ptgt = NULL; 8947 8948 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private; 8949 ptgt = tgt_private->t_private; 8950 if (ptgt == NULL) { 8951 return (FALSE); 8952 } 8953 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl, 8954 level)); 8955 8956 mutex_enter(&mpt->m_mutex); 8957 /* 8958 * if we are not in panic set up a reset delay for this target 8959 */ 8960 if (!ddi_in_panic()) { 8961 mptsas_setup_bus_reset_delay(mpt); 8962 } else { 8963 drv_usecwait(mpt->m_scsi_reset_delay * 1000); 8964 } 8965 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl); 8966 mutex_exit(&mpt->m_mutex); 8967 8968 /* 8969 * The transport layer expect to only see TRUE and 8970 * FALSE. Therefore, we will adjust the return value 8971 * if mptsas_do_scsi_reset returns FAILED. 8972 */ 8973 if (rval == FAILED) 8974 rval = FALSE; 8975 return (rval); 8976 } 8977 8978 static int 8979 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl) 8980 { 8981 int rval = FALSE; 8982 uint8_t config, disk; 8983 mptsas_slots_t *slots = mpt->m_active; 8984 8985 ASSERT(mutex_owned(&mpt->m_mutex)); 8986 8987 if (mptsas_debug_resets) { 8988 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d", 8989 devhdl); 8990 } 8991 8992 /* 8993 * Issue a Target Reset message to the target specified but not to a 8994 * disk making up a raid volume. Just look through the RAID config 8995 * Phys Disk list of DevHandles. If the target's DevHandle is in this 8996 * list, then don't reset this target. 8997 */ 8998 for (config = 0; config < slots->m_num_raid_configs; config++) { 8999 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 9000 if (devhdl == slots->m_raidconfig[config]. 9001 m_physdisk_devhdl[disk]) { 9002 return (TRUE); 9003 } 9004 } 9005 } 9006 9007 rval = mptsas_ioc_task_management(mpt, 9008 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0); 9009 9010 mptsas_doneq_empty(mpt); 9011 return (rval); 9012 } 9013 9014 static int 9015 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 9016 void (*callback)(caddr_t), caddr_t arg) 9017 { 9018 mptsas_t *mpt = ADDR2MPT(ap); 9019 9020 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target)); 9021 9022 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg, 9023 &mpt->m_mutex, &mpt->m_reset_notify_listf)); 9024 } 9025 9026 static int 9027 mptsas_get_name(struct scsi_device *sd, char *name, int len) 9028 { 9029 dev_info_t *lun_dip = NULL; 9030 9031 ASSERT(sd != NULL); 9032 ASSERT(name != NULL); 9033 lun_dip = sd->sd_dev; 9034 ASSERT(lun_dip != NULL); 9035 9036 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) { 9037 return (1); 9038 } else { 9039 return (0); 9040 } 9041 } 9042 9043 static int 9044 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len) 9045 { 9046 return (mptsas_get_name(sd, name, len)); 9047 } 9048 9049 void 9050 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what) 9051 { 9052 9053 NDBG25(("mptsas_set_throttle: throttle=%x", what)); 9054 9055 /* 9056 * if the bus is draining/quiesced, no changes to the throttles 9057 * are allowed. Not allowing change of throttles during draining 9058 * limits error recovery but will reduce draining time 9059 * 9060 * all throttles should have been set to HOLD_THROTTLE 9061 */ 9062 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) { 9063 return; 9064 } 9065 9066 if (what == HOLD_THROTTLE) { 9067 ptgt->m_t_throttle = HOLD_THROTTLE; 9068 } else if (ptgt->m_reset_delay == 0) { 9069 ptgt->m_t_throttle = what; 9070 } 9071 } 9072 9073 /* 9074 * Clean up from a device reset. 9075 * For the case of target reset, this function clears the waitq of all 9076 * commands for a particular target. For the case of abort task set, this 9077 * function clears the waitq of all commonds for a particular target/lun. 9078 */ 9079 static void 9080 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype) 9081 { 9082 mptsas_slots_t *slots = mpt->m_active; 9083 mptsas_cmd_t *cmd, *next_cmd; 9084 int slot; 9085 uchar_t reason; 9086 uint_t stat; 9087 9088 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun)); 9089 9090 /* 9091 * Make sure the I/O Controller has flushed all cmds 9092 * that are associated with this target for a target reset 9093 * and target/lun for abort task set. 9094 * Account for TM requests, which use the last SMID. 9095 */ 9096 mutex_enter(&mpt->m_intr_mutex); 9097 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) { 9098 if ((cmd = slots->m_slot[slot]) == NULL) { 9099 continue; 9100 } 9101 reason = CMD_RESET; 9102 stat = STAT_DEV_RESET; 9103 switch (tasktype) { 9104 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9105 if (Tgt(cmd) == target) { 9106 NDBG25(("mptsas_flush_target discovered non-" 9107 "NULL cmd in slot %d, tasktype 0x%x", slot, 9108 tasktype)); 9109 mptsas_dump_cmd(mpt, cmd); 9110 mptsas_remove_cmd0(mpt, cmd); 9111 mptsas_set_pkt_reason(mpt, cmd, reason, stat); 9112 mptsas_doneq_add0(mpt, cmd); 9113 } 9114 break; 9115 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9116 reason = CMD_ABORTED; 9117 stat = STAT_ABORTED; 9118 /*FALLTHROUGH*/ 9119 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9120 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9121 9122 NDBG25(("mptsas_flush_target discovered non-" 9123 "NULL cmd in slot %d, tasktype 0x%x", slot, 9124 tasktype)); 9125 mptsas_dump_cmd(mpt, cmd); 9126 mptsas_remove_cmd0(mpt, cmd); 9127 mptsas_set_pkt_reason(mpt, cmd, reason, 9128 stat); 9129 mptsas_doneq_add0(mpt, cmd); 9130 } 9131 break; 9132 default: 9133 break; 9134 } 9135 } 9136 mutex_exit(&mpt->m_intr_mutex); 9137 9138 /* 9139 * Flush the waitq of this target's cmds 9140 */ 9141 cmd = mpt->m_waitq; 9142 9143 reason = CMD_RESET; 9144 stat = STAT_DEV_RESET; 9145 9146 switch (tasktype) { 9147 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9148 while (cmd != NULL) { 9149 next_cmd = cmd->cmd_linkp; 9150 if (Tgt(cmd) == target) { 9151 mptsas_waitq_delete(mpt, cmd); 9152 mptsas_set_pkt_reason(mpt, cmd, 9153 reason, stat); 9154 mptsas_doneq_add(mpt, cmd); 9155 } 9156 cmd = next_cmd; 9157 } 9158 break; 9159 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9160 reason = CMD_ABORTED; 9161 stat = STAT_ABORTED; 9162 /*FALLTHROUGH*/ 9163 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9164 while (cmd != NULL) { 9165 next_cmd = cmd->cmd_linkp; 9166 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9167 mptsas_waitq_delete(mpt, cmd); 9168 mptsas_set_pkt_reason(mpt, cmd, 9169 reason, stat); 9170 mptsas_doneq_add(mpt, cmd); 9171 } 9172 cmd = next_cmd; 9173 } 9174 break; 9175 default: 9176 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 9177 tasktype); 9178 break; 9179 } 9180 } 9181 9182 /* 9183 * Clean up hba state, abort all outstanding command and commands in waitq 9184 * reset timeout of all targets. 9185 */ 9186 static void 9187 mptsas_flush_hba(mptsas_t *mpt) 9188 { 9189 mptsas_slots_t *slots = mpt->m_active; 9190 mptsas_cmd_t *cmd; 9191 int slot; 9192 9193 NDBG25(("mptsas_flush_hba")); 9194 9195 /* 9196 * The I/O Controller should have already sent back 9197 * all commands via the scsi I/O reply frame. Make 9198 * sure all commands have been flushed. 9199 * Account for TM request, which use the last SMID. 9200 */ 9201 mutex_enter(&mpt->m_intr_mutex); 9202 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) { 9203 if ((cmd = slots->m_slot[slot]) == NULL) { 9204 continue; 9205 } 9206 9207 if (cmd->cmd_flags & CFLAG_CMDIOC) { 9208 /* 9209 * Need to make sure to tell everyone that might be 9210 * waiting on this command that it's going to fail. If 9211 * we get here, this command will never timeout because 9212 * the active command table is going to be re-allocated, 9213 * so there will be nothing to check against a time out. 9214 * Instead, mark the command as failed due to reset. 9215 */ 9216 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 9217 STAT_BUS_RESET); 9218 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 9219 (cmd->cmd_flags & CFLAG_CONFIG) || 9220 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 9221 cmd->cmd_flags |= CFLAG_FINISHED; 9222 cv_broadcast(&mpt->m_passthru_cv); 9223 cv_broadcast(&mpt->m_config_cv); 9224 cv_broadcast(&mpt->m_fw_diag_cv); 9225 } 9226 continue; 9227 } 9228 9229 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d", 9230 slot)); 9231 mptsas_dump_cmd(mpt, cmd); 9232 9233 mptsas_remove_cmd0(mpt, cmd); 9234 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9235 mptsas_doneq_add0(mpt, cmd); 9236 } 9237 mutex_exit(&mpt->m_intr_mutex); 9238 9239 /* 9240 * Flush the waitq. 9241 */ 9242 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) { 9243 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9244 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 9245 (cmd->cmd_flags & CFLAG_CONFIG) || 9246 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 9247 cmd->cmd_flags |= CFLAG_FINISHED; 9248 cv_broadcast(&mpt->m_passthru_cv); 9249 cv_broadcast(&mpt->m_config_cv); 9250 cv_broadcast(&mpt->m_fw_diag_cv); 9251 } else { 9252 mptsas_doneq_add(mpt, cmd); 9253 } 9254 } 9255 } 9256 9257 /* 9258 * set pkt_reason and OR in pkt_statistics flag 9259 */ 9260 static void 9261 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason, 9262 uint_t stat) 9263 { 9264 #ifndef __lock_lint 9265 _NOTE(ARGUNUSED(mpt)) 9266 #endif 9267 9268 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x", 9269 (void *)cmd, reason, stat)); 9270 9271 if (cmd) { 9272 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) { 9273 cmd->cmd_pkt->pkt_reason = reason; 9274 } 9275 cmd->cmd_pkt->pkt_statistics |= stat; 9276 } 9277 } 9278 9279 static void 9280 mptsas_start_watch_reset_delay() 9281 { 9282 NDBG22(("mptsas_start_watch_reset_delay")); 9283 9284 mutex_enter(&mptsas_global_mutex); 9285 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) { 9286 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL, 9287 drv_usectohz((clock_t) 9288 MPTSAS_WATCH_RESET_DELAY_TICK * 1000)); 9289 ASSERT(mptsas_reset_watch != NULL); 9290 } 9291 mutex_exit(&mptsas_global_mutex); 9292 } 9293 9294 static void 9295 mptsas_setup_bus_reset_delay(mptsas_t *mpt) 9296 { 9297 mptsas_target_t *ptgt = NULL; 9298 9299 NDBG22(("mptsas_setup_bus_reset_delay")); 9300 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 9301 MPTSAS_HASH_FIRST); 9302 while (ptgt != NULL) { 9303 mutex_enter(&ptgt->m_tgt_intr_mutex); 9304 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 9305 ptgt->m_reset_delay = mpt->m_scsi_reset_delay; 9306 mutex_exit(&ptgt->m_tgt_intr_mutex); 9307 9308 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9309 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 9310 } 9311 9312 mptsas_start_watch_reset_delay(); 9313 } 9314 9315 /* 9316 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every 9317 * mpt instance for active reset delays 9318 */ 9319 static void 9320 mptsas_watch_reset_delay(void *arg) 9321 { 9322 #ifndef __lock_lint 9323 _NOTE(ARGUNUSED(arg)) 9324 #endif 9325 9326 mptsas_t *mpt; 9327 int not_done = 0; 9328 9329 NDBG22(("mptsas_watch_reset_delay")); 9330 9331 mutex_enter(&mptsas_global_mutex); 9332 mptsas_reset_watch = 0; 9333 mutex_exit(&mptsas_global_mutex); 9334 rw_enter(&mptsas_global_rwlock, RW_READER); 9335 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) { 9336 if (mpt->m_tran == 0) { 9337 continue; 9338 } 9339 mutex_enter(&mpt->m_mutex); 9340 not_done += mptsas_watch_reset_delay_subr(mpt); 9341 mutex_exit(&mpt->m_mutex); 9342 } 9343 rw_exit(&mptsas_global_rwlock); 9344 9345 if (not_done) { 9346 mptsas_start_watch_reset_delay(); 9347 } 9348 } 9349 9350 static int 9351 mptsas_watch_reset_delay_subr(mptsas_t *mpt) 9352 { 9353 int done = 0; 9354 int restart = 0; 9355 mptsas_target_t *ptgt = NULL; 9356 9357 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt)); 9358 9359 ASSERT(mutex_owned(&mpt->m_mutex)); 9360 9361 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 9362 MPTSAS_HASH_FIRST); 9363 while (ptgt != NULL) { 9364 mutex_enter(&ptgt->m_tgt_intr_mutex); 9365 if (ptgt->m_reset_delay != 0) { 9366 ptgt->m_reset_delay -= 9367 MPTSAS_WATCH_RESET_DELAY_TICK; 9368 if (ptgt->m_reset_delay <= 0) { 9369 ptgt->m_reset_delay = 0; 9370 mptsas_set_throttle(mpt, ptgt, 9371 MAX_THROTTLE); 9372 restart++; 9373 } else { 9374 done = -1; 9375 } 9376 } 9377 mutex_exit(&ptgt->m_tgt_intr_mutex); 9378 9379 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9380 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 9381 } 9382 9383 if (restart > 0) { 9384 mptsas_restart_hba(mpt); 9385 } 9386 return (done); 9387 } 9388 9389 #ifdef MPTSAS_TEST 9390 static void 9391 mptsas_test_reset(mptsas_t *mpt, int target) 9392 { 9393 mptsas_target_t *ptgt = NULL; 9394 9395 if (mptsas_rtest == target) { 9396 if (mptsas_do_scsi_reset(mpt, target) == TRUE) { 9397 mptsas_rtest = -1; 9398 } 9399 if (mptsas_rtest == -1) { 9400 NDBG22(("mptsas_test_reset success")); 9401 } 9402 } 9403 } 9404 #endif 9405 9406 /* 9407 * abort handling: 9408 * 9409 * Notes: 9410 * - if pkt is not NULL, abort just that command 9411 * - if pkt is NULL, abort all outstanding commands for target 9412 */ 9413 static int 9414 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 9415 { 9416 mptsas_t *mpt = ADDR2MPT(ap); 9417 int rval; 9418 mptsas_tgt_private_t *tgt_private; 9419 int target, lun; 9420 9421 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 9422 tran_tgt_private; 9423 ASSERT(tgt_private != NULL); 9424 target = tgt_private->t_private->m_devhdl; 9425 lun = tgt_private->t_lun; 9426 9427 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun)); 9428 9429 mutex_enter(&mpt->m_mutex); 9430 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt); 9431 mutex_exit(&mpt->m_mutex); 9432 return (rval); 9433 } 9434 9435 static int 9436 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt) 9437 { 9438 mptsas_cmd_t *sp = NULL; 9439 mptsas_slots_t *slots = mpt->m_active; 9440 int rval = FALSE; 9441 9442 ASSERT(mutex_owned(&mpt->m_mutex)); 9443 9444 /* 9445 * Abort the command pkt on the target/lun in ap. If pkt is 9446 * NULL, abort all outstanding commands on that target/lun. 9447 * If you can abort them, return 1, else return 0. 9448 * Each packet that's aborted should be sent back to the target 9449 * driver through the callback routine, with pkt_reason set to 9450 * CMD_ABORTED. 9451 * 9452 * abort cmd pkt on HBA hardware; clean out of outstanding 9453 * command lists, etc. 9454 */ 9455 if (pkt != NULL) { 9456 /* abort the specified packet */ 9457 sp = PKT2CMD(pkt); 9458 9459 if (sp->cmd_queued) { 9460 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted", 9461 (void *)sp)); 9462 mptsas_waitq_delete(mpt, sp); 9463 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED, 9464 STAT_ABORTED); 9465 mptsas_doneq_add(mpt, sp); 9466 rval = TRUE; 9467 goto done; 9468 } 9469 9470 /* 9471 * Have mpt firmware abort this command 9472 */ 9473 mutex_enter(&mpt->m_intr_mutex); 9474 if (slots->m_slot[sp->cmd_slot] != NULL) { 9475 mutex_exit(&mpt->m_intr_mutex); 9476 rval = mptsas_ioc_task_management(mpt, 9477 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target, 9478 lun, NULL, 0, 0); 9479 9480 /* 9481 * The transport layer expects only TRUE and FALSE. 9482 * Therefore, if mptsas_ioc_task_management returns 9483 * FAILED we will return FALSE. 9484 */ 9485 if (rval == FAILED) 9486 rval = FALSE; 9487 goto done; 9488 } 9489 mutex_exit(&mpt->m_intr_mutex); 9490 } 9491 9492 /* 9493 * If pkt is NULL then abort task set 9494 */ 9495 rval = mptsas_ioc_task_management(mpt, 9496 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0); 9497 9498 /* 9499 * The transport layer expects only TRUE and FALSE. 9500 * Therefore, if mptsas_ioc_task_management returns 9501 * FAILED we will return FALSE. 9502 */ 9503 if (rval == FAILED) 9504 rval = FALSE; 9505 9506 #ifdef MPTSAS_TEST 9507 if (rval && mptsas_test_stop) { 9508 debug_enter("mptsas_do_scsi_abort"); 9509 } 9510 #endif 9511 9512 done: 9513 mptsas_doneq_empty(mpt); 9514 return (rval); 9515 } 9516 9517 /* 9518 * capability handling: 9519 * (*tran_getcap). Get the capability named, and return its value. 9520 */ 9521 static int 9522 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly) 9523 { 9524 mptsas_t *mpt = ADDR2MPT(ap); 9525 int ckey; 9526 int rval = FALSE; 9527 9528 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x", 9529 ap->a_target, cap, tgtonly)); 9530 9531 mutex_enter(&mpt->m_mutex); 9532 9533 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9534 mutex_exit(&mpt->m_mutex); 9535 return (UNDEFINED); 9536 } 9537 9538 switch (ckey) { 9539 case SCSI_CAP_DMA_MAX: 9540 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer; 9541 break; 9542 case SCSI_CAP_ARQ: 9543 rval = TRUE; 9544 break; 9545 case SCSI_CAP_MSG_OUT: 9546 case SCSI_CAP_PARITY: 9547 case SCSI_CAP_UNTAGGED_QING: 9548 rval = TRUE; 9549 break; 9550 case SCSI_CAP_TAGGED_QING: 9551 rval = TRUE; 9552 break; 9553 case SCSI_CAP_RESET_NOTIFICATION: 9554 rval = TRUE; 9555 break; 9556 case SCSI_CAP_LINKED_CMDS: 9557 rval = FALSE; 9558 break; 9559 case SCSI_CAP_QFULL_RETRIES: 9560 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran-> 9561 tran_tgt_private))->t_private->m_qfull_retries; 9562 break; 9563 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9564 rval = drv_hztousec(((mptsas_tgt_private_t *) 9565 (ap->a_hba_tran->tran_tgt_private))-> 9566 t_private->m_qfull_retry_interval) / 1000; 9567 break; 9568 case SCSI_CAP_CDB_LEN: 9569 rval = CDB_GROUP4; 9570 break; 9571 case SCSI_CAP_INTERCONNECT_TYPE: 9572 rval = INTERCONNECT_SAS; 9573 break; 9574 case SCSI_CAP_TRAN_LAYER_RETRIES: 9575 if (mpt->m_ioc_capabilities & 9576 MPI2_IOCFACTS_CAPABILITY_TLR) 9577 rval = TRUE; 9578 else 9579 rval = FALSE; 9580 break; 9581 default: 9582 rval = UNDEFINED; 9583 break; 9584 } 9585 9586 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval)); 9587 9588 mutex_exit(&mpt->m_mutex); 9589 return (rval); 9590 } 9591 9592 /* 9593 * (*tran_setcap). Set the capability named to the value given. 9594 */ 9595 static int 9596 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly) 9597 { 9598 mptsas_t *mpt = ADDR2MPT(ap); 9599 int ckey; 9600 int rval = FALSE; 9601 mptsas_target_t *ptgt; 9602 9603 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x", 9604 ap->a_target, cap, value, tgtonly)); 9605 9606 if (!tgtonly) { 9607 return (rval); 9608 } 9609 9610 mutex_enter(&mpt->m_mutex); 9611 9612 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9613 mutex_exit(&mpt->m_mutex); 9614 return (UNDEFINED); 9615 } 9616 9617 switch (ckey) { 9618 case SCSI_CAP_DMA_MAX: 9619 case SCSI_CAP_MSG_OUT: 9620 case SCSI_CAP_PARITY: 9621 case SCSI_CAP_INITIATOR_ID: 9622 case SCSI_CAP_LINKED_CMDS: 9623 case SCSI_CAP_UNTAGGED_QING: 9624 case SCSI_CAP_RESET_NOTIFICATION: 9625 /* 9626 * None of these are settable via 9627 * the capability interface. 9628 */ 9629 break; 9630 case SCSI_CAP_ARQ: 9631 /* 9632 * We cannot turn off arq so return false if asked to 9633 */ 9634 if (value) { 9635 rval = TRUE; 9636 } else { 9637 rval = FALSE; 9638 } 9639 break; 9640 case SCSI_CAP_TAGGED_QING: 9641 ptgt = ((mptsas_tgt_private_t *) 9642 (ap->a_hba_tran->tran_tgt_private))->t_private; 9643 mutex_enter(&ptgt->m_tgt_intr_mutex); 9644 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 9645 mutex_exit(&ptgt->m_tgt_intr_mutex); 9646 rval = TRUE; 9647 break; 9648 case SCSI_CAP_QFULL_RETRIES: 9649 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9650 t_private->m_qfull_retries = (uchar_t)value; 9651 rval = TRUE; 9652 break; 9653 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9654 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9655 t_private->m_qfull_retry_interval = 9656 drv_usectohz(value * 1000); 9657 rval = TRUE; 9658 break; 9659 default: 9660 rval = UNDEFINED; 9661 break; 9662 } 9663 mutex_exit(&mpt->m_mutex); 9664 return (rval); 9665 } 9666 9667 /* 9668 * Utility routine for mptsas_ifsetcap/ifgetcap 9669 */ 9670 /*ARGSUSED*/ 9671 static int 9672 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp) 9673 { 9674 NDBG24(("mptsas_scsi_capchk: cap=%s", cap)); 9675 9676 if (!cap) 9677 return (FALSE); 9678 9679 *cidxp = scsi_hba_lookup_capstr(cap); 9680 return (TRUE); 9681 } 9682 9683 static int 9684 mptsas_alloc_active_slots(mptsas_t *mpt, int flag) 9685 { 9686 mptsas_slots_t *old_active = mpt->m_active; 9687 mptsas_slots_t *new_active; 9688 size_t size; 9689 int rval = -1, nslot, i; 9690 mptsas_slot_free_e_t *pe; 9691 9692 if (mptsas_outstanding_cmds_n(mpt)) { 9693 NDBG9(("cannot change size of active slots array")); 9694 return (rval); 9695 } 9696 9697 size = MPTSAS_SLOTS_SIZE(mpt); 9698 new_active = kmem_zalloc(size, flag); 9699 if (new_active == NULL) { 9700 NDBG1(("new active alloc failed")); 9701 return (rval); 9702 } 9703 /* 9704 * Since SMID 0 is reserved and the TM slot is reserved, the 9705 * number of slots that can be used at any one time is 9706 * m_max_requests - 2. 9707 */ 9708 new_active->m_n_slots = nslot = (mpt->m_max_requests - 2); 9709 new_active->m_size = size; 9710 new_active->m_tags = 1; 9711 9712 if (old_active) { 9713 new_active->m_tgttbl = old_active->m_tgttbl; 9714 new_active->m_smptbl = old_active->m_smptbl; 9715 new_active->m_num_raid_configs = 9716 old_active->m_num_raid_configs; 9717 for (i = 0; i < new_active->m_num_raid_configs; i++) { 9718 new_active->m_raidconfig[i] = 9719 old_active->m_raidconfig[i]; 9720 } 9721 mptsas_free_active_slots(mpt); 9722 } 9723 9724 if (max_ncpus & (max_ncpus - 1)) { 9725 mpt->m_slot_freeq_pair_n = (1 << highbit(max_ncpus)); 9726 } else { 9727 mpt->m_slot_freeq_pair_n = max_ncpus; 9728 } 9729 mpt->m_slot_freeq_pairp = kmem_zalloc( 9730 mpt->m_slot_freeq_pair_n * 9731 sizeof (mptsas_slot_freeq_pair_t), KM_SLEEP); 9732 for (i = 0; i < mpt->m_slot_freeq_pair_n; i++) { 9733 list_create(&mpt->m_slot_freeq_pairp[i]. 9734 m_slot_allocq.s.m_fq_list, 9735 sizeof (mptsas_slot_free_e_t), 9736 offsetof(mptsas_slot_free_e_t, node)); 9737 list_create(&mpt->m_slot_freeq_pairp[i]. 9738 m_slot_releq.s.m_fq_list, 9739 sizeof (mptsas_slot_free_e_t), 9740 offsetof(mptsas_slot_free_e_t, node)); 9741 mpt->m_slot_freeq_pairp[i].m_slot_allocq.s.m_fq_n = 0; 9742 mpt->m_slot_freeq_pairp[i].m_slot_releq.s.m_fq_n = 0; 9743 mutex_init(&mpt->m_slot_freeq_pairp[i]. 9744 m_slot_allocq.s.m_fq_mutex, NULL, MUTEX_DRIVER, 9745 DDI_INTR_PRI(mpt->m_intr_pri)); 9746 mutex_init(&mpt->m_slot_freeq_pairp[i]. 9747 m_slot_releq.s.m_fq_mutex, NULL, MUTEX_DRIVER, 9748 DDI_INTR_PRI(mpt->m_intr_pri)); 9749 } 9750 pe = mpt->m_slot_free_ae = kmem_zalloc(nslot * 9751 sizeof (mptsas_slot_free_e_t), KM_SLEEP); 9752 /* 9753 * An array of Mpi2ReplyDescriptorsUnion_t is defined here. 9754 * We are trying to eliminate the m_mutex in the context 9755 * reply code path in the ISR. Since the read of the 9756 * ReplyDescriptor and update/write of the ReplyIndex must 9757 * be atomic (since the poll thread may also update them at 9758 * the same time) so we first read out of the ReplyDescriptor 9759 * into this array and update the ReplyIndex register with a 9760 * separate mutex m_intr_mutex protected, and then release the 9761 * mutex and process all of them. the length of the array is 9762 * defined as max as 128(128*64=8k), which is 9763 * assumed as the maxmium depth of the interrupt coalese. 9764 */ 9765 mpt->m_reply = kmem_zalloc(MPI_ADDRESS_COALSCE_MAX * 9766 sizeof (Mpi2ReplyDescriptorsUnion_t), KM_SLEEP); 9767 for (i = 0; i < nslot; i++, pe++) { 9768 pe->slot = i + 1; /* SMID 0 is reserved */ 9769 pe->cpuid = i % mpt->m_slot_freeq_pair_n; 9770 list_insert_tail(&mpt->m_slot_freeq_pairp 9771 [i % mpt->m_slot_freeq_pair_n] 9772 .m_slot_allocq.s.m_fq_list, pe); 9773 mpt->m_slot_freeq_pairp[i % mpt->m_slot_freeq_pair_n] 9774 .m_slot_allocq.s.m_fq_n++; 9775 mpt->m_slot_freeq_pairp[i % mpt->m_slot_freeq_pair_n] 9776 .m_slot_allocq.s.m_fq_n_init++; 9777 } 9778 9779 mpt->m_active = new_active; 9780 rval = 0; 9781 9782 return (rval); 9783 } 9784 9785 static void 9786 mptsas_free_active_slots(mptsas_t *mpt) 9787 { 9788 mptsas_slots_t *active = mpt->m_active; 9789 size_t size; 9790 mptsas_slot_free_e_t *pe; 9791 int i; 9792 9793 if (active == NULL) 9794 return; 9795 9796 if (mpt->m_slot_freeq_pairp) { 9797 for (i = 0; i < mpt->m_slot_freeq_pair_n; i++) { 9798 while ((pe = list_head(&mpt->m_slot_freeq_pairp 9799 [i].m_slot_allocq.s.m_fq_list)) != NULL) { 9800 list_remove(&mpt->m_slot_freeq_pairp[i] 9801 .m_slot_allocq.s.m_fq_list, pe); 9802 } 9803 list_destroy(&mpt->m_slot_freeq_pairp 9804 [i].m_slot_allocq.s.m_fq_list); 9805 while ((pe = list_head(&mpt->m_slot_freeq_pairp 9806 [i].m_slot_releq.s.m_fq_list)) != NULL) { 9807 list_remove(&mpt->m_slot_freeq_pairp[i] 9808 .m_slot_releq.s.m_fq_list, pe); 9809 } 9810 list_destroy(&mpt->m_slot_freeq_pairp 9811 [i].m_slot_releq.s.m_fq_list); 9812 mutex_destroy(&mpt->m_slot_freeq_pairp 9813 [i].m_slot_allocq.s.m_fq_mutex); 9814 mutex_destroy(&mpt->m_slot_freeq_pairp 9815 [i].m_slot_releq.s.m_fq_mutex); 9816 } 9817 kmem_free(mpt->m_slot_freeq_pairp, mpt->m_slot_freeq_pair_n * 9818 sizeof (mptsas_slot_freeq_pair_t)); 9819 } 9820 if (mpt->m_slot_free_ae) 9821 kmem_free(mpt->m_slot_free_ae, mpt->m_active->m_n_slots * 9822 sizeof (mptsas_slot_free_e_t)); 9823 9824 if (mpt->m_reply) 9825 kmem_free(mpt->m_reply, MPI_ADDRESS_COALSCE_MAX * 9826 sizeof (Mpi2ReplyDescriptorsUnion_t)); 9827 9828 size = active->m_size; 9829 kmem_free(active, size); 9830 mpt->m_active = NULL; 9831 } 9832 9833 /* 9834 * Error logging, printing, and debug print routines. 9835 */ 9836 static char *mptsas_label = "mpt_sas"; 9837 9838 /*PRINTFLIKE3*/ 9839 void 9840 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...) 9841 { 9842 dev_info_t *dev; 9843 va_list ap; 9844 9845 if (mpt) { 9846 dev = mpt->m_dip; 9847 } else { 9848 dev = 0; 9849 } 9850 9851 mutex_enter(&mptsas_log_mutex); 9852 9853 va_start(ap, fmt); 9854 (void) vsprintf(mptsas_log_buf, fmt, ap); 9855 va_end(ap); 9856 9857 if (level == CE_CONT) { 9858 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf); 9859 } else { 9860 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf); 9861 } 9862 9863 mutex_exit(&mptsas_log_mutex); 9864 } 9865 9866 #ifdef MPTSAS_DEBUG 9867 /*PRINTFLIKE1*/ 9868 void 9869 mptsas_printf(char *fmt, ...) 9870 { 9871 dev_info_t *dev = 0; 9872 va_list ap; 9873 9874 mutex_enter(&mptsas_log_mutex); 9875 9876 va_start(ap, fmt); 9877 (void) vsprintf(mptsas_log_buf, fmt, ap); 9878 va_end(ap); 9879 9880 #ifdef PROM_PRINTF 9881 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf); 9882 #else 9883 scsi_log(dev, mptsas_label, SCSI_DEBUG, "%s\n", mptsas_log_buf); 9884 #endif 9885 mutex_exit(&mptsas_log_mutex); 9886 } 9887 #endif 9888 9889 /* 9890 * timeout handling 9891 */ 9892 static void 9893 mptsas_watch(void *arg) 9894 { 9895 #ifndef __lock_lint 9896 _NOTE(ARGUNUSED(arg)) 9897 #endif 9898 9899 mptsas_t *mpt; 9900 uint32_t doorbell; 9901 9902 NDBG30(("mptsas_watch")); 9903 9904 rw_enter(&mptsas_global_rwlock, RW_READER); 9905 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) { 9906 9907 mutex_enter(&mpt->m_mutex); 9908 9909 /* Skip device if not powered on */ 9910 if (mpt->m_options & MPTSAS_OPT_PM) { 9911 if (mpt->m_power_level == PM_LEVEL_D0) { 9912 (void) pm_busy_component(mpt->m_dip, 0); 9913 mpt->m_busy = 1; 9914 } else { 9915 mutex_exit(&mpt->m_mutex); 9916 continue; 9917 } 9918 } 9919 9920 /* 9921 * Check if controller is in a FAULT state. If so, reset it. 9922 */ 9923 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell); 9924 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 9925 doorbell &= MPI2_DOORBELL_DATA_MASK; 9926 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, " 9927 "code: %04x", doorbell); 9928 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 9929 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 9930 mptsas_log(mpt, CE_WARN, "Reset failed" 9931 "after fault was detected"); 9932 } 9933 } 9934 9935 /* 9936 * For now, always call mptsas_watchsubr. 9937 */ 9938 mptsas_watchsubr(mpt); 9939 9940 if (mpt->m_options & MPTSAS_OPT_PM) { 9941 mpt->m_busy = 0; 9942 (void) pm_idle_component(mpt->m_dip, 0); 9943 } 9944 9945 mutex_exit(&mpt->m_mutex); 9946 } 9947 rw_exit(&mptsas_global_rwlock); 9948 9949 mutex_enter(&mptsas_global_mutex); 9950 if (mptsas_timeouts_enabled) 9951 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 9952 mutex_exit(&mptsas_global_mutex); 9953 } 9954 9955 static void 9956 mptsas_watchsubr(mptsas_t *mpt) 9957 { 9958 int i; 9959 mptsas_cmd_t *cmd; 9960 mptsas_target_t *ptgt = NULL; 9961 9962 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt)); 9963 9964 #ifdef MPTSAS_TEST 9965 if (mptsas_enable_untagged) { 9966 mptsas_test_untagged++; 9967 } 9968 #endif 9969 9970 /* 9971 * Check for commands stuck in active slot 9972 * Account for TM requests, which use the last SMID. 9973 */ 9974 mutex_enter(&mpt->m_intr_mutex); 9975 for (i = 0; i <= mpt->m_active->m_n_slots; i++) { 9976 if ((cmd = mpt->m_active->m_slot[i]) != NULL) { 9977 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 9978 cmd->cmd_active_timeout -= 9979 mptsas_scsi_watchdog_tick; 9980 if (cmd->cmd_active_timeout <= 0) { 9981 /* 9982 * There seems to be a command stuck 9983 * in the active slot. Drain throttle. 9984 */ 9985 ptgt = cmd->cmd_tgt_addr; 9986 mutex_enter(&ptgt->m_tgt_intr_mutex); 9987 mptsas_set_throttle(mpt, ptgt, 9988 DRAIN_THROTTLE); 9989 mutex_exit(&ptgt->m_tgt_intr_mutex); 9990 } 9991 } 9992 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 9993 (cmd->cmd_flags & CFLAG_CONFIG) || 9994 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 9995 cmd->cmd_active_timeout -= 9996 mptsas_scsi_watchdog_tick; 9997 if (cmd->cmd_active_timeout <= 0) { 9998 /* 9999 * passthrough command timeout 10000 */ 10001 cmd->cmd_flags |= (CFLAG_FINISHED | 10002 CFLAG_TIMEOUT); 10003 cv_broadcast(&mpt->m_passthru_cv); 10004 cv_broadcast(&mpt->m_config_cv); 10005 cv_broadcast(&mpt->m_fw_diag_cv); 10006 } 10007 } 10008 } 10009 } 10010 mutex_exit(&mpt->m_intr_mutex); 10011 10012 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 10013 MPTSAS_HASH_FIRST); 10014 while (ptgt != NULL) { 10015 /* 10016 * In order to avoid using m_mutex in the key code path in ISR, 10017 * separate mutexs are introduced to protect those elements 10018 * shown in ISR. 10019 */ 10020 mutex_enter(&ptgt->m_tgt_intr_mutex); 10021 10022 /* 10023 * If we were draining due to a qfull condition, 10024 * go back to full throttle. 10025 */ 10026 if ((ptgt->m_t_throttle < MAX_THROTTLE) && 10027 (ptgt->m_t_throttle > HOLD_THROTTLE) && 10028 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) { 10029 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10030 mptsas_restart_hba(mpt); 10031 } 10032 10033 if ((ptgt->m_t_ncmds > 0) && 10034 (ptgt->m_timebase)) { 10035 10036 if (ptgt->m_timebase <= 10037 mptsas_scsi_watchdog_tick) { 10038 ptgt->m_timebase += 10039 mptsas_scsi_watchdog_tick; 10040 mutex_exit(&ptgt->m_tgt_intr_mutex); 10041 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 10042 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 10043 continue; 10044 } 10045 10046 ptgt->m_timeout -= mptsas_scsi_watchdog_tick; 10047 10048 if (ptgt->m_timeout < 0) { 10049 mutex_exit(&ptgt->m_tgt_intr_mutex); 10050 mptsas_cmd_timeout(mpt, ptgt->m_devhdl); 10051 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 10052 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 10053 continue; 10054 } 10055 10056 if ((ptgt->m_timeout) <= 10057 mptsas_scsi_watchdog_tick) { 10058 NDBG23(("pending timeout")); 10059 mptsas_set_throttle(mpt, ptgt, 10060 DRAIN_THROTTLE); 10061 } 10062 } 10063 mutex_exit(&ptgt->m_tgt_intr_mutex); 10064 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 10065 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 10066 } 10067 } 10068 10069 /* 10070 * timeout recovery 10071 */ 10072 static void 10073 mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl) 10074 { 10075 10076 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl)); 10077 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for " 10078 "Target %d", devhdl); 10079 10080 /* 10081 * If the current target is not the target passed in, 10082 * try to reset that target. 10083 */ 10084 NDBG29(("mptsas_cmd_timeout: device reset")); 10085 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) { 10086 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout " 10087 "recovery failed!", devhdl); 10088 } 10089 } 10090 10091 /* 10092 * Device / Hotplug control 10093 */ 10094 static int 10095 mptsas_scsi_quiesce(dev_info_t *dip) 10096 { 10097 mptsas_t *mpt; 10098 scsi_hba_tran_t *tran; 10099 10100 tran = ddi_get_driver_private(dip); 10101 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10102 return (-1); 10103 10104 return (mptsas_quiesce_bus(mpt)); 10105 } 10106 10107 static int 10108 mptsas_scsi_unquiesce(dev_info_t *dip) 10109 { 10110 mptsas_t *mpt; 10111 scsi_hba_tran_t *tran; 10112 10113 tran = ddi_get_driver_private(dip); 10114 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10115 return (-1); 10116 10117 return (mptsas_unquiesce_bus(mpt)); 10118 } 10119 10120 static int 10121 mptsas_quiesce_bus(mptsas_t *mpt) 10122 { 10123 mptsas_target_t *ptgt = NULL; 10124 10125 NDBG28(("mptsas_quiesce_bus")); 10126 mutex_enter(&mpt->m_mutex); 10127 10128 /* Set all the throttles to zero */ 10129 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 10130 MPTSAS_HASH_FIRST); 10131 while (ptgt != NULL) { 10132 mutex_enter(&ptgt->m_tgt_intr_mutex); 10133 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10134 mutex_exit(&ptgt->m_tgt_intr_mutex); 10135 10136 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 10137 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 10138 } 10139 10140 /* If there are any outstanding commands in the queue */ 10141 mutex_enter(&mpt->m_intr_mutex); 10142 if (mptsas_outstanding_cmds_n(mpt)) { 10143 mutex_exit(&mpt->m_intr_mutex); 10144 mpt->m_softstate |= MPTSAS_SS_DRAINING; 10145 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10146 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000))); 10147 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) { 10148 /* 10149 * Quiesce has been interrupted 10150 */ 10151 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10152 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 10153 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST); 10154 while (ptgt != NULL) { 10155 mutex_enter(&ptgt->m_tgt_intr_mutex); 10156 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10157 mutex_exit(&ptgt->m_tgt_intr_mutex); 10158 10159 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 10160 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 10161 } 10162 mptsas_restart_hba(mpt); 10163 if (mpt->m_quiesce_timeid != 0) { 10164 timeout_id_t tid = mpt->m_quiesce_timeid; 10165 mpt->m_quiesce_timeid = 0; 10166 mutex_exit(&mpt->m_mutex); 10167 (void) untimeout(tid); 10168 return (-1); 10169 } 10170 mutex_exit(&mpt->m_mutex); 10171 return (-1); 10172 } else { 10173 /* Bus has been quiesced */ 10174 ASSERT(mpt->m_quiesce_timeid == 0); 10175 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10176 mpt->m_softstate |= MPTSAS_SS_QUIESCED; 10177 mutex_exit(&mpt->m_mutex); 10178 return (0); 10179 } 10180 } 10181 mutex_exit(&mpt->m_intr_mutex); 10182 /* Bus was not busy - QUIESCED */ 10183 mutex_exit(&mpt->m_mutex); 10184 10185 return (0); 10186 } 10187 10188 static int 10189 mptsas_unquiesce_bus(mptsas_t *mpt) 10190 { 10191 mptsas_target_t *ptgt = NULL; 10192 10193 NDBG28(("mptsas_unquiesce_bus")); 10194 mutex_enter(&mpt->m_mutex); 10195 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED; 10196 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 10197 MPTSAS_HASH_FIRST); 10198 while (ptgt != NULL) { 10199 mutex_enter(&ptgt->m_tgt_intr_mutex); 10200 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10201 mutex_exit(&ptgt->m_tgt_intr_mutex); 10202 10203 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 10204 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 10205 } 10206 mptsas_restart_hba(mpt); 10207 mutex_exit(&mpt->m_mutex); 10208 return (0); 10209 } 10210 10211 static void 10212 mptsas_ncmds_checkdrain(void *arg) 10213 { 10214 mptsas_t *mpt = arg; 10215 mptsas_target_t *ptgt = NULL; 10216 10217 mutex_enter(&mpt->m_mutex); 10218 if (mpt->m_softstate & MPTSAS_SS_DRAINING) { 10219 mpt->m_quiesce_timeid = 0; 10220 mutex_enter(&mpt->m_intr_mutex); 10221 if (mptsas_outstanding_cmds_n(mpt)) { 10222 mutex_exit(&mpt->m_intr_mutex); 10223 /* 10224 * The throttle may have been reset because 10225 * of a SCSI bus reset 10226 */ 10227 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 10228 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST); 10229 while (ptgt != NULL) { 10230 mutex_enter(&ptgt->m_tgt_intr_mutex); 10231 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10232 mutex_exit(&ptgt->m_tgt_intr_mutex); 10233 10234 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 10235 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 10236 } 10237 10238 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10239 mpt, (MPTSAS_QUIESCE_TIMEOUT * 10240 drv_usectohz(1000000))); 10241 } else { 10242 mutex_exit(&mpt->m_intr_mutex); 10243 /* Command queue has been drained */ 10244 cv_signal(&mpt->m_cv); 10245 } 10246 } 10247 mutex_exit(&mpt->m_mutex); 10248 } 10249 10250 /*ARGSUSED*/ 10251 static void 10252 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 10253 { 10254 int i; 10255 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp; 10256 char buf[128]; 10257 10258 buf[0] = '\0'; 10259 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd, 10260 Tgt(cmd), Lun(cmd))); 10261 (void) sprintf(&buf[0], "\tcdb=["); 10262 for (i = 0; i < (int)cmd->cmd_cdblen; i++) { 10263 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++); 10264 } 10265 (void) sprintf(&buf[strlen(buf)], " ]"); 10266 NDBG25(("?%s\n", buf)); 10267 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n", 10268 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics, 10269 cmd->cmd_pkt->pkt_state)); 10270 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ? 10271 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags)); 10272 } 10273 10274 static void 10275 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd) 10276 { 10277 caddr_t memp; 10278 pMPI2RequestHeader_t request_hdrp; 10279 struct scsi_pkt *pkt = cmd->cmd_pkt; 10280 mptsas_pt_request_t *pt = pkt->pkt_ha_private; 10281 uint32_t request_size, data_size, dataout_size; 10282 uint32_t direction; 10283 ddi_dma_cookie_t data_cookie; 10284 ddi_dma_cookie_t dataout_cookie; 10285 uint32_t request_desc_low, request_desc_high = 0; 10286 uint32_t i, sense_bufp; 10287 uint8_t desc_type; 10288 uint8_t *request, function; 10289 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 10290 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 10291 10292 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 10293 10294 request = pt->request; 10295 direction = pt->direction; 10296 request_size = pt->request_size; 10297 data_size = pt->data_size; 10298 dataout_size = pt->dataout_size; 10299 data_cookie = pt->data_cookie; 10300 dataout_cookie = pt->dataout_cookie; 10301 10302 /* 10303 * Store the passthrough message in memory location 10304 * corresponding to our slot number 10305 */ 10306 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot); 10307 request_hdrp = (pMPI2RequestHeader_t)memp; 10308 bzero(memp, mpt->m_req_frame_size); 10309 10310 for (i = 0; i < request_size; i++) { 10311 bcopy(request + i, memp + i, 1); 10312 } 10313 10314 if (data_size || dataout_size) { 10315 pMpi2SGESimple64_t sgep; 10316 uint32_t sge_flags; 10317 10318 sgep = (pMpi2SGESimple64_t)((uint8_t *)request_hdrp + 10319 request_size); 10320 if (dataout_size) { 10321 10322 sge_flags = dataout_size | 10323 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10324 MPI2_SGE_FLAGS_END_OF_BUFFER | 10325 MPI2_SGE_FLAGS_HOST_TO_IOC | 10326 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10327 MPI2_SGE_FLAGS_SHIFT); 10328 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags); 10329 ddi_put32(acc_hdl, &sgep->Address.Low, 10330 (uint32_t)(dataout_cookie.dmac_laddress & 10331 0xffffffffull)); 10332 ddi_put32(acc_hdl, &sgep->Address.High, 10333 (uint32_t)(dataout_cookie.dmac_laddress 10334 >> 32)); 10335 sgep++; 10336 } 10337 sge_flags = data_size; 10338 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10339 MPI2_SGE_FLAGS_LAST_ELEMENT | 10340 MPI2_SGE_FLAGS_END_OF_BUFFER | 10341 MPI2_SGE_FLAGS_END_OF_LIST | 10342 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10343 MPI2_SGE_FLAGS_SHIFT); 10344 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 10345 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 10346 MPI2_SGE_FLAGS_SHIFT); 10347 } else { 10348 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 10349 MPI2_SGE_FLAGS_SHIFT); 10350 } 10351 ddi_put32(acc_hdl, &sgep->FlagsLength, 10352 sge_flags); 10353 ddi_put32(acc_hdl, &sgep->Address.Low, 10354 (uint32_t)(data_cookie.dmac_laddress & 10355 0xffffffffull)); 10356 ddi_put32(acc_hdl, &sgep->Address.High, 10357 (uint32_t)(data_cookie.dmac_laddress >> 32)); 10358 } 10359 10360 function = request_hdrp->Function; 10361 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 10362 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 10363 pMpi2SCSIIORequest_t scsi_io_req; 10364 10365 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp; 10366 /* 10367 * Put SGE for data and data_out buffer at the end of 10368 * scsi_io_request message header.(64 bytes in total) 10369 * Following above SGEs, the residual space will be 10370 * used by sense data. 10371 */ 10372 ddi_put8(acc_hdl, 10373 &scsi_io_req->SenseBufferLength, 10374 (uint8_t)(request_size - 64)); 10375 10376 sense_bufp = mpt->m_req_frame_dma_addr + 10377 (mpt->m_req_frame_size * cmd->cmd_slot); 10378 sense_bufp += 64; 10379 ddi_put32(acc_hdl, 10380 &scsi_io_req->SenseBufferLowAddress, sense_bufp); 10381 10382 /* 10383 * Set SGLOffset0 value 10384 */ 10385 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0, 10386 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4); 10387 10388 /* 10389 * Setup descriptor info. RAID passthrough must use the 10390 * default request descriptor which is already set, so if this 10391 * is a SCSI IO request, change the descriptor to SCSI IO. 10392 */ 10393 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 10394 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 10395 request_desc_high = (ddi_get16(acc_hdl, 10396 &scsi_io_req->DevHandle) << 16); 10397 } 10398 } 10399 10400 /* 10401 * We must wait till the message has been completed before 10402 * beginning the next message so we wait for this one to 10403 * finish. 10404 */ 10405 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 10406 request_desc_low = (cmd->cmd_slot << 16) + desc_type; 10407 cmd->cmd_rfm = NULL; 10408 mpt->m_active->m_slot[cmd->cmd_slot] = cmd; 10409 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high); 10410 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 10411 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 10412 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 10413 } 10414 } 10415 10416 10417 10418 static int 10419 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 10420 uint8_t *data, uint32_t request_size, uint32_t reply_size, 10421 uint32_t data_size, uint32_t direction, uint8_t *dataout, 10422 uint32_t dataout_size, short timeout, int mode) 10423 { 10424 mptsas_pt_request_t pt; 10425 mptsas_dma_alloc_state_t data_dma_state; 10426 mptsas_dma_alloc_state_t dataout_dma_state; 10427 caddr_t memp; 10428 mptsas_cmd_t *cmd = NULL; 10429 struct scsi_pkt *pkt; 10430 uint32_t reply_len = 0, sense_len = 0; 10431 pMPI2RequestHeader_t request_hdrp; 10432 pMPI2RequestHeader_t request_msg; 10433 pMPI2DefaultReply_t reply_msg; 10434 Mpi2SCSIIOReply_t rep_msg; 10435 int i, status = 0, pt_flags = 0, rv = 0; 10436 int rvalue; 10437 uint8_t function; 10438 10439 ASSERT(mutex_owned(&mpt->m_mutex)); 10440 10441 reply_msg = (pMPI2DefaultReply_t)(&rep_msg); 10442 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY)); 10443 request_msg = kmem_zalloc(request_size, KM_SLEEP); 10444 10445 mutex_exit(&mpt->m_mutex); 10446 /* 10447 * copy in the request buffer since it could be used by 10448 * another thread when the pt request into waitq 10449 */ 10450 if (ddi_copyin(request, request_msg, request_size, mode)) { 10451 mutex_enter(&mpt->m_mutex); 10452 status = EFAULT; 10453 mptsas_log(mpt, CE_WARN, "failed to copy request data"); 10454 goto out; 10455 } 10456 mutex_enter(&mpt->m_mutex); 10457 10458 function = request_msg->Function; 10459 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) { 10460 pMpi2SCSITaskManagementRequest_t task; 10461 task = (pMpi2SCSITaskManagementRequest_t)request_msg; 10462 mptsas_setup_bus_reset_delay(mpt); 10463 rv = mptsas_ioc_task_management(mpt, task->TaskType, 10464 task->DevHandle, (int)task->LUN[1], reply, reply_size, 10465 mode); 10466 10467 if (rv != TRUE) { 10468 status = EIO; 10469 mptsas_log(mpt, CE_WARN, "task management failed"); 10470 } 10471 goto out; 10472 } 10473 10474 if (data_size != 0) { 10475 data_dma_state.size = data_size; 10476 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) { 10477 status = ENOMEM; 10478 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 10479 "resource"); 10480 goto out; 10481 } 10482 pt_flags |= MPTSAS_DATA_ALLOCATED; 10483 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 10484 mutex_exit(&mpt->m_mutex); 10485 for (i = 0; i < data_size; i++) { 10486 if (ddi_copyin(data + i, (uint8_t *) 10487 data_dma_state.memp + i, 1, mode)) { 10488 mutex_enter(&mpt->m_mutex); 10489 status = EFAULT; 10490 mptsas_log(mpt, CE_WARN, "failed to " 10491 "copy read data"); 10492 goto out; 10493 } 10494 } 10495 mutex_enter(&mpt->m_mutex); 10496 } 10497 } 10498 10499 if (dataout_size != 0) { 10500 dataout_dma_state.size = dataout_size; 10501 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) { 10502 status = ENOMEM; 10503 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 10504 "resource"); 10505 goto out; 10506 } 10507 pt_flags |= MPTSAS_DATAOUT_ALLOCATED; 10508 mutex_exit(&mpt->m_mutex); 10509 for (i = 0; i < dataout_size; i++) { 10510 if (ddi_copyin(dataout + i, (uint8_t *) 10511 dataout_dma_state.memp + i, 1, mode)) { 10512 mutex_enter(&mpt->m_mutex); 10513 mptsas_log(mpt, CE_WARN, "failed to copy out" 10514 " data"); 10515 status = EFAULT; 10516 goto out; 10517 } 10518 } 10519 mutex_enter(&mpt->m_mutex); 10520 } 10521 10522 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 10523 status = EAGAIN; 10524 mptsas_log(mpt, CE_NOTE, "event ack command pool is full"); 10525 goto out; 10526 } 10527 pt_flags |= MPTSAS_REQUEST_POOL_CMD; 10528 10529 bzero((caddr_t)cmd, sizeof (*cmd)); 10530 bzero((caddr_t)pkt, scsi_pkt_size()); 10531 bzero((caddr_t)&pt, sizeof (pt)); 10532 10533 cmd->ioc_cmd_slot = (uint32_t)(rvalue); 10534 10535 pt.request = (uint8_t *)request_msg; 10536 pt.direction = direction; 10537 pt.request_size = request_size; 10538 pt.data_size = data_size; 10539 pt.dataout_size = dataout_size; 10540 pt.data_cookie = data_dma_state.cookie; 10541 pt.dataout_cookie = dataout_dma_state.cookie; 10542 10543 /* 10544 * Form a blank cmd/pkt to store the acknowledgement message 10545 */ 10546 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0]; 10547 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 10548 pkt->pkt_ha_private = (opaque_t)&pt; 10549 pkt->pkt_flags = FLAG_HEAD; 10550 pkt->pkt_time = timeout; 10551 cmd->cmd_pkt = pkt; 10552 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU; 10553 10554 /* 10555 * Save the command in a slot 10556 */ 10557 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 10558 /* 10559 * Once passthru command get slot, set cmd_flags 10560 * CFLAG_PREPARED. 10561 */ 10562 cmd->cmd_flags |= CFLAG_PREPARED; 10563 mptsas_start_passthru(mpt, cmd); 10564 } else { 10565 mptsas_waitq_add(mpt, cmd); 10566 } 10567 10568 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 10569 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex); 10570 } 10571 10572 if (cmd->cmd_flags & CFLAG_PREPARED) { 10573 memp = mpt->m_req_frame + (mpt->m_req_frame_size * 10574 cmd->cmd_slot); 10575 request_hdrp = (pMPI2RequestHeader_t)memp; 10576 } 10577 10578 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 10579 status = ETIMEDOUT; 10580 mptsas_log(mpt, CE_WARN, "passthrough command timeout"); 10581 pt_flags |= MPTSAS_CMD_TIMEOUT; 10582 goto out; 10583 } 10584 10585 if (cmd->cmd_rfm) { 10586 /* 10587 * cmd_rfm is zero means the command reply is a CONTEXT 10588 * reply and no PCI Write to post the free reply SMFA 10589 * because no reply message frame is used. 10590 * cmd_rfm is non-zero means the reply is a ADDRESS 10591 * reply and reply message frame is used. 10592 */ 10593 pt_flags |= MPTSAS_ADDRESS_REPLY; 10594 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 10595 DDI_DMA_SYNC_FORCPU); 10596 reply_msg = (pMPI2DefaultReply_t) 10597 (mpt->m_reply_frame + (cmd->cmd_rfm - 10598 mpt->m_reply_frame_dma_addr)); 10599 } 10600 10601 mptsas_fma_check(mpt, cmd); 10602 if (pkt->pkt_reason == CMD_TRAN_ERR) { 10603 status = EAGAIN; 10604 mptsas_log(mpt, CE_WARN, "passthru fma error"); 10605 goto out; 10606 } 10607 if (pkt->pkt_reason == CMD_RESET) { 10608 status = EAGAIN; 10609 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru"); 10610 goto out; 10611 } 10612 10613 if (pkt->pkt_reason == CMD_INCOMPLETE) { 10614 status = EIO; 10615 mptsas_log(mpt, CE_WARN, "passthrough command incomplete"); 10616 goto out; 10617 } 10618 10619 mutex_exit(&mpt->m_mutex); 10620 if (cmd->cmd_flags & CFLAG_PREPARED) { 10621 function = request_hdrp->Function; 10622 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 10623 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 10624 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 10625 sense_len = reply_size - reply_len; 10626 } else { 10627 reply_len = reply_size; 10628 sense_len = 0; 10629 } 10630 10631 for (i = 0; i < reply_len; i++) { 10632 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1, 10633 mode)) { 10634 mutex_enter(&mpt->m_mutex); 10635 status = EFAULT; 10636 mptsas_log(mpt, CE_WARN, "failed to copy out " 10637 "reply data"); 10638 goto out; 10639 } 10640 } 10641 for (i = 0; i < sense_len; i++) { 10642 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i, 10643 reply + reply_len + i, 1, mode)) { 10644 mutex_enter(&mpt->m_mutex); 10645 status = EFAULT; 10646 mptsas_log(mpt, CE_WARN, "failed to copy out " 10647 "sense data"); 10648 goto out; 10649 } 10650 } 10651 } 10652 10653 if (data_size) { 10654 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) { 10655 (void) ddi_dma_sync(data_dma_state.handle, 0, 0, 10656 DDI_DMA_SYNC_FORCPU); 10657 for (i = 0; i < data_size; i++) { 10658 if (ddi_copyout((uint8_t *)( 10659 data_dma_state.memp + i), data + i, 1, 10660 mode)) { 10661 mutex_enter(&mpt->m_mutex); 10662 status = EFAULT; 10663 mptsas_log(mpt, CE_WARN, "failed to " 10664 "copy out the reply data"); 10665 goto out; 10666 } 10667 } 10668 } 10669 } 10670 mutex_enter(&mpt->m_mutex); 10671 out: 10672 /* 10673 * Put the reply frame back on the free queue, increment the free 10674 * index, and write the new index to the free index register. But only 10675 * if this reply is an ADDRESS reply. 10676 */ 10677 if (pt_flags & MPTSAS_ADDRESS_REPLY) { 10678 ddi_put32(mpt->m_acc_free_queue_hdl, 10679 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 10680 cmd->cmd_rfm); 10681 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 10682 DDI_DMA_SYNC_FORDEV); 10683 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 10684 mpt->m_free_index = 0; 10685 } 10686 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 10687 mpt->m_free_index); 10688 } 10689 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 10690 mptsas_remove_cmd(mpt, cmd); 10691 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD); 10692 } 10693 if (pt_flags & MPTSAS_REQUEST_POOL_CMD) 10694 mptsas_return_to_pool(mpt, cmd); 10695 if (pt_flags & MPTSAS_DATA_ALLOCATED) { 10696 if (mptsas_check_dma_handle(data_dma_state.handle) != 10697 DDI_SUCCESS) { 10698 ddi_fm_service_impact(mpt->m_dip, 10699 DDI_SERVICE_UNAFFECTED); 10700 status = EFAULT; 10701 } 10702 mptsas_dma_free(&data_dma_state); 10703 } 10704 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) { 10705 if (mptsas_check_dma_handle(dataout_dma_state.handle) != 10706 DDI_SUCCESS) { 10707 ddi_fm_service_impact(mpt->m_dip, 10708 DDI_SERVICE_UNAFFECTED); 10709 status = EFAULT; 10710 } 10711 mptsas_dma_free(&dataout_dma_state); 10712 } 10713 if (pt_flags & MPTSAS_CMD_TIMEOUT) { 10714 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 10715 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed"); 10716 } 10717 } 10718 if (request_msg) 10719 kmem_free(request_msg, request_size); 10720 10721 return (status); 10722 } 10723 10724 static int 10725 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode) 10726 { 10727 /* 10728 * If timeout is 0, set timeout to default of 60 seconds. 10729 */ 10730 if (data->Timeout == 0) { 10731 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT; 10732 } 10733 10734 if (((data->DataSize == 0) && 10735 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) || 10736 ((data->DataSize != 0) && 10737 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) || 10738 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) || 10739 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) && 10740 (data->DataOutSize != 0))))) { 10741 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) { 10742 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ; 10743 } else { 10744 data->DataOutSize = 0; 10745 } 10746 /* 10747 * Send passthru request messages 10748 */ 10749 return (mptsas_do_passthru(mpt, 10750 (uint8_t *)((uintptr_t)data->PtrRequest), 10751 (uint8_t *)((uintptr_t)data->PtrReply), 10752 (uint8_t *)((uintptr_t)data->PtrData), 10753 data->RequestSize, data->ReplySize, 10754 data->DataSize, data->DataDirection, 10755 (uint8_t *)((uintptr_t)data->PtrDataOut), 10756 data->DataOutSize, data->Timeout, mode)); 10757 } else { 10758 return (EINVAL); 10759 } 10760 } 10761 10762 static uint8_t 10763 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id) 10764 { 10765 uint8_t index; 10766 10767 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) { 10768 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) { 10769 return (index); 10770 } 10771 } 10772 10773 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND); 10774 } 10775 10776 static void 10777 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd) 10778 { 10779 pMpi2DiagBufferPostRequest_t pDiag_post_msg; 10780 pMpi2DiagReleaseRequest_t pDiag_release_msg; 10781 struct scsi_pkt *pkt = cmd->cmd_pkt; 10782 mptsas_diag_request_t *diag = pkt->pkt_ha_private; 10783 uint32_t request_desc_low, i; 10784 10785 ASSERT(mutex_owned(&mpt->m_mutex)); 10786 10787 /* 10788 * Form the diag message depending on the post or release function. 10789 */ 10790 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) { 10791 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t) 10792 (mpt->m_req_frame + (mpt->m_req_frame_size * 10793 cmd->cmd_slot)); 10794 bzero(pDiag_post_msg, mpt->m_req_frame_size); 10795 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function, 10796 diag->function); 10797 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType, 10798 diag->pBuffer->buffer_type); 10799 ddi_put8(mpt->m_acc_req_frame_hdl, 10800 &pDiag_post_msg->ExtendedType, 10801 diag->pBuffer->extended_type); 10802 ddi_put32(mpt->m_acc_req_frame_hdl, 10803 &pDiag_post_msg->BufferLength, 10804 diag->pBuffer->buffer_data.size); 10805 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4); 10806 i++) { 10807 ddi_put32(mpt->m_acc_req_frame_hdl, 10808 &pDiag_post_msg->ProductSpecific[i], 10809 diag->pBuffer->product_specific[i]); 10810 } 10811 ddi_put32(mpt->m_acc_req_frame_hdl, 10812 &pDiag_post_msg->BufferAddress.Low, 10813 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 10814 & 0xffffffffull)); 10815 ddi_put32(mpt->m_acc_req_frame_hdl, 10816 &pDiag_post_msg->BufferAddress.High, 10817 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 10818 >> 32)); 10819 } else { 10820 pDiag_release_msg = (pMpi2DiagReleaseRequest_t) 10821 (mpt->m_req_frame + (mpt->m_req_frame_size * 10822 cmd->cmd_slot)); 10823 bzero(pDiag_release_msg, mpt->m_req_frame_size); 10824 ddi_put8(mpt->m_acc_req_frame_hdl, 10825 &pDiag_release_msg->Function, diag->function); 10826 ddi_put8(mpt->m_acc_req_frame_hdl, 10827 &pDiag_release_msg->BufferType, 10828 diag->pBuffer->buffer_type); 10829 } 10830 10831 /* 10832 * Send the message 10833 */ 10834 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0, 10835 DDI_DMA_SYNC_FORDEV); 10836 request_desc_low = (cmd->cmd_slot << 16) + 10837 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 10838 cmd->cmd_rfm = NULL; 10839 mpt->m_active->m_slot[cmd->cmd_slot] = cmd; 10840 MPTSAS_START_CMD(mpt, request_desc_low, 0); 10841 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 10842 DDI_SUCCESS) || 10843 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 10844 DDI_SUCCESS)) { 10845 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 10846 } 10847 } 10848 10849 static int 10850 mptsas_post_fw_diag_buffer(mptsas_t *mpt, 10851 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code) 10852 { 10853 mptsas_diag_request_t diag; 10854 int status, slot_num, post_flags = 0; 10855 mptsas_cmd_t *cmd = NULL; 10856 struct scsi_pkt *pkt; 10857 pMpi2DiagBufferPostReply_t reply; 10858 uint16_t iocstatus; 10859 uint32_t iocloginfo, transfer_length; 10860 10861 /* 10862 * If buffer is not enabled, just leave. 10863 */ 10864 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED; 10865 if (!pBuffer->enabled) { 10866 status = DDI_FAILURE; 10867 goto out; 10868 } 10869 10870 /* 10871 * Clear some flags initially. 10872 */ 10873 pBuffer->force_release = FALSE; 10874 pBuffer->valid_data = FALSE; 10875 pBuffer->owned_by_firmware = FALSE; 10876 10877 /* 10878 * Get a cmd buffer from the cmd buffer pool 10879 */ 10880 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 10881 status = DDI_FAILURE; 10882 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag"); 10883 goto out; 10884 } 10885 post_flags |= MPTSAS_REQUEST_POOL_CMD; 10886 10887 bzero((caddr_t)cmd, sizeof (*cmd)); 10888 bzero((caddr_t)pkt, scsi_pkt_size()); 10889 10890 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 10891 10892 diag.pBuffer = pBuffer; 10893 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST; 10894 10895 /* 10896 * Form a blank cmd/pkt to store the acknowledgement message 10897 */ 10898 pkt->pkt_ha_private = (opaque_t)&diag; 10899 pkt->pkt_flags = FLAG_HEAD; 10900 pkt->pkt_time = 60; 10901 cmd->cmd_pkt = pkt; 10902 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 10903 10904 /* 10905 * Save the command in a slot 10906 */ 10907 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 10908 /* 10909 * Once passthru command get slot, set cmd_flags 10910 * CFLAG_PREPARED. 10911 */ 10912 cmd->cmd_flags |= CFLAG_PREPARED; 10913 mptsas_start_diag(mpt, cmd); 10914 } else { 10915 mptsas_waitq_add(mpt, cmd); 10916 } 10917 10918 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 10919 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 10920 } 10921 10922 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 10923 status = DDI_FAILURE; 10924 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout"); 10925 goto out; 10926 } 10927 10928 /* 10929 * cmd_rfm points to the reply message if a reply was given. Check the 10930 * IOCStatus to make sure everything went OK with the FW diag request 10931 * and set buffer flags. 10932 */ 10933 if (cmd->cmd_rfm) { 10934 post_flags |= MPTSAS_ADDRESS_REPLY; 10935 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 10936 DDI_DMA_SYNC_FORCPU); 10937 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame + 10938 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr)); 10939 10940 /* 10941 * Get the reply message data 10942 */ 10943 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 10944 &reply->IOCStatus); 10945 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 10946 &reply->IOCLogInfo); 10947 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl, 10948 &reply->TransferLength); 10949 10950 /* 10951 * If post failed quit. 10952 */ 10953 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) { 10954 status = DDI_FAILURE; 10955 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, " 10956 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus, 10957 iocloginfo, transfer_length)); 10958 goto out; 10959 } 10960 10961 /* 10962 * Post was successful. 10963 */ 10964 pBuffer->valid_data = TRUE; 10965 pBuffer->owned_by_firmware = TRUE; 10966 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 10967 status = DDI_SUCCESS; 10968 } 10969 10970 out: 10971 /* 10972 * Put the reply frame back on the free queue, increment the free 10973 * index, and write the new index to the free index register. But only 10974 * if this reply is an ADDRESS reply. 10975 */ 10976 if (post_flags & MPTSAS_ADDRESS_REPLY) { 10977 ddi_put32(mpt->m_acc_free_queue_hdl, 10978 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 10979 cmd->cmd_rfm); 10980 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 10981 DDI_DMA_SYNC_FORDEV); 10982 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 10983 mpt->m_free_index = 0; 10984 } 10985 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 10986 mpt->m_free_index); 10987 } 10988 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 10989 mptsas_remove_cmd(mpt, cmd); 10990 post_flags &= (~MPTSAS_REQUEST_POOL_CMD); 10991 } 10992 if (post_flags & MPTSAS_REQUEST_POOL_CMD) { 10993 mptsas_return_to_pool(mpt, cmd); 10994 } 10995 10996 return (status); 10997 } 10998 10999 static int 11000 mptsas_release_fw_diag_buffer(mptsas_t *mpt, 11001 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 11002 uint32_t diag_type) 11003 { 11004 mptsas_diag_request_t diag; 11005 int status, slot_num, rel_flags = 0; 11006 mptsas_cmd_t *cmd = NULL; 11007 struct scsi_pkt *pkt; 11008 pMpi2DiagReleaseReply_t reply; 11009 uint16_t iocstatus; 11010 uint32_t iocloginfo; 11011 11012 /* 11013 * If buffer is not enabled, just leave. 11014 */ 11015 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED; 11016 if (!pBuffer->enabled) { 11017 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported " 11018 "by the IOC"); 11019 status = DDI_FAILURE; 11020 goto out; 11021 } 11022 11023 /* 11024 * Clear some flags initially. 11025 */ 11026 pBuffer->force_release = FALSE; 11027 pBuffer->valid_data = FALSE; 11028 pBuffer->owned_by_firmware = FALSE; 11029 11030 /* 11031 * Get a cmd buffer from the cmd buffer pool 11032 */ 11033 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11034 status = DDI_FAILURE; 11035 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW " 11036 "Diag"); 11037 goto out; 11038 } 11039 rel_flags |= MPTSAS_REQUEST_POOL_CMD; 11040 11041 bzero((caddr_t)cmd, sizeof (*cmd)); 11042 bzero((caddr_t)pkt, scsi_pkt_size()); 11043 11044 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 11045 11046 diag.pBuffer = pBuffer; 11047 diag.function = MPI2_FUNCTION_DIAG_RELEASE; 11048 11049 /* 11050 * Form a blank cmd/pkt to store the acknowledgement message 11051 */ 11052 pkt->pkt_ha_private = (opaque_t)&diag; 11053 pkt->pkt_flags = FLAG_HEAD; 11054 pkt->pkt_time = 60; 11055 cmd->cmd_pkt = pkt; 11056 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 11057 11058 /* 11059 * Save the command in a slot 11060 */ 11061 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11062 /* 11063 * Once passthru command get slot, set cmd_flags 11064 * CFLAG_PREPARED. 11065 */ 11066 cmd->cmd_flags |= CFLAG_PREPARED; 11067 mptsas_start_diag(mpt, cmd); 11068 } else { 11069 mptsas_waitq_add(mpt, cmd); 11070 } 11071 11072 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11073 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 11074 } 11075 11076 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11077 status = DDI_FAILURE; 11078 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout"); 11079 goto out; 11080 } 11081 11082 /* 11083 * cmd_rfm points to the reply message if a reply was given. Check the 11084 * IOCStatus to make sure everything went OK with the FW diag request 11085 * and set buffer flags. 11086 */ 11087 if (cmd->cmd_rfm) { 11088 rel_flags |= MPTSAS_ADDRESS_REPLY; 11089 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11090 DDI_DMA_SYNC_FORCPU); 11091 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame + 11092 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr)); 11093 11094 /* 11095 * Get the reply message data 11096 */ 11097 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 11098 &reply->IOCStatus); 11099 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 11100 &reply->IOCLogInfo); 11101 11102 /* 11103 * If release failed quit. 11104 */ 11105 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) || 11106 pBuffer->owned_by_firmware) { 11107 status = DDI_FAILURE; 11108 NDBG13(("release FW Diag Buffer failed: " 11109 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, 11110 iocloginfo)); 11111 goto out; 11112 } 11113 11114 /* 11115 * Release was successful. 11116 */ 11117 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11118 status = DDI_SUCCESS; 11119 11120 /* 11121 * If this was for an UNREGISTER diag type command, clear the 11122 * unique ID. 11123 */ 11124 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) { 11125 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 11126 } 11127 } 11128 11129 out: 11130 /* 11131 * Put the reply frame back on the free queue, increment the free 11132 * index, and write the new index to the free index register. But only 11133 * if this reply is an ADDRESS reply. 11134 */ 11135 if (rel_flags & MPTSAS_ADDRESS_REPLY) { 11136 ddi_put32(mpt->m_acc_free_queue_hdl, 11137 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11138 cmd->cmd_rfm); 11139 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11140 DDI_DMA_SYNC_FORDEV); 11141 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11142 mpt->m_free_index = 0; 11143 } 11144 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11145 mpt->m_free_index); 11146 } 11147 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 11148 mptsas_remove_cmd(mpt, cmd); 11149 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11150 } 11151 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) { 11152 mptsas_return_to_pool(mpt, cmd); 11153 } 11154 11155 return (status); 11156 } 11157 11158 static int 11159 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register, 11160 uint32_t *return_code) 11161 { 11162 mptsas_fw_diagnostic_buffer_t *pBuffer; 11163 uint8_t extended_type, buffer_type, i; 11164 uint32_t buffer_size; 11165 uint32_t unique_id; 11166 int status; 11167 11168 ASSERT(mutex_owned(&mpt->m_mutex)); 11169 11170 extended_type = diag_register->ExtendedType; 11171 buffer_type = diag_register->BufferType; 11172 buffer_size = diag_register->RequestedBufferSize; 11173 unique_id = diag_register->UniqueId; 11174 11175 /* 11176 * Check for valid buffer type 11177 */ 11178 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) { 11179 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11180 return (DDI_FAILURE); 11181 } 11182 11183 /* 11184 * Get the current buffer and look up the unique ID. The unique ID 11185 * should not be found. If it is, the ID is already in use. 11186 */ 11187 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11188 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type]; 11189 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11190 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11191 return (DDI_FAILURE); 11192 } 11193 11194 /* 11195 * The buffer's unique ID should not be registered yet, and the given 11196 * unique ID cannot be 0. 11197 */ 11198 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) || 11199 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11200 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11201 return (DDI_FAILURE); 11202 } 11203 11204 /* 11205 * If this buffer is already posted as immediate, just change owner. 11206 */ 11207 if (pBuffer->immediate && pBuffer->owned_by_firmware && 11208 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11209 pBuffer->immediate = FALSE; 11210 pBuffer->unique_id = unique_id; 11211 return (DDI_SUCCESS); 11212 } 11213 11214 /* 11215 * Post a new buffer after checking if it's enabled. The DMA buffer 11216 * that is allocated will be contiguous (sgl_len = 1). 11217 */ 11218 if (!pBuffer->enabled) { 11219 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11220 return (DDI_FAILURE); 11221 } 11222 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t)); 11223 pBuffer->buffer_data.size = buffer_size; 11224 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) { 11225 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for " 11226 "diag buffer: size = %d bytes", buffer_size); 11227 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11228 return (DDI_FAILURE); 11229 } 11230 11231 /* 11232 * Copy the given info to the diag buffer and post the buffer. 11233 */ 11234 pBuffer->buffer_type = buffer_type; 11235 pBuffer->immediate = FALSE; 11236 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) { 11237 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4); 11238 i++) { 11239 pBuffer->product_specific[i] = 11240 diag_register->ProductSpecific[i]; 11241 } 11242 } 11243 pBuffer->extended_type = extended_type; 11244 pBuffer->unique_id = unique_id; 11245 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code); 11246 11247 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 11248 DDI_SUCCESS) { 11249 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in " 11250 "mptsas_diag_register."); 11251 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11252 status = DDI_FAILURE; 11253 } 11254 11255 /* 11256 * In case there was a failure, free the DMA buffer. 11257 */ 11258 if (status == DDI_FAILURE) { 11259 mptsas_dma_free(&pBuffer->buffer_data); 11260 } 11261 11262 return (status); 11263 } 11264 11265 static int 11266 mptsas_diag_unregister(mptsas_t *mpt, 11267 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code) 11268 { 11269 mptsas_fw_diagnostic_buffer_t *pBuffer; 11270 uint8_t i; 11271 uint32_t unique_id; 11272 int status; 11273 11274 ASSERT(mutex_owned(&mpt->m_mutex)); 11275 11276 unique_id = diag_unregister->UniqueId; 11277 11278 /* 11279 * Get the current buffer and look up the unique ID. The unique ID 11280 * should be there. 11281 */ 11282 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11283 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11284 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11285 return (DDI_FAILURE); 11286 } 11287 11288 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 11289 11290 /* 11291 * Try to release the buffer from FW before freeing it. If release 11292 * fails, don't free the DMA buffer in case FW tries to access it 11293 * later. If buffer is not owned by firmware, can't release it. 11294 */ 11295 if (!pBuffer->owned_by_firmware) { 11296 status = DDI_SUCCESS; 11297 } else { 11298 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, 11299 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER); 11300 } 11301 11302 /* 11303 * At this point, return the current status no matter what happens with 11304 * the DMA buffer. 11305 */ 11306 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 11307 if (status == DDI_SUCCESS) { 11308 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 11309 DDI_SUCCESS) { 11310 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed " 11311 "in mptsas_diag_unregister."); 11312 ddi_fm_service_impact(mpt->m_dip, 11313 DDI_SERVICE_UNAFFECTED); 11314 } 11315 mptsas_dma_free(&pBuffer->buffer_data); 11316 } 11317 11318 return (status); 11319 } 11320 11321 static int 11322 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 11323 uint32_t *return_code) 11324 { 11325 mptsas_fw_diagnostic_buffer_t *pBuffer; 11326 uint8_t i; 11327 uint32_t unique_id; 11328 11329 ASSERT(mutex_owned(&mpt->m_mutex)); 11330 11331 unique_id = diag_query->UniqueId; 11332 11333 /* 11334 * If ID is valid, query on ID. 11335 * If ID is invalid, query on buffer type. 11336 */ 11337 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) { 11338 i = diag_query->BufferType; 11339 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) { 11340 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11341 return (DDI_FAILURE); 11342 } 11343 } else { 11344 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11345 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11346 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11347 return (DDI_FAILURE); 11348 } 11349 } 11350 11351 /* 11352 * Fill query structure with the diag buffer info. 11353 */ 11354 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 11355 diag_query->BufferType = pBuffer->buffer_type; 11356 diag_query->ExtendedType = pBuffer->extended_type; 11357 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) { 11358 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4); 11359 i++) { 11360 diag_query->ProductSpecific[i] = 11361 pBuffer->product_specific[i]; 11362 } 11363 } 11364 diag_query->TotalBufferSize = pBuffer->buffer_data.size; 11365 diag_query->DriverAddedBufferSize = 0; 11366 diag_query->UniqueId = pBuffer->unique_id; 11367 diag_query->ApplicationFlags = 0; 11368 diag_query->DiagnosticFlags = 0; 11369 11370 /* 11371 * Set/Clear application flags 11372 */ 11373 if (pBuffer->immediate) { 11374 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED; 11375 } else { 11376 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED; 11377 } 11378 if (pBuffer->valid_data || pBuffer->owned_by_firmware) { 11379 diag_query->ApplicationFlags |= 11380 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 11381 } else { 11382 diag_query->ApplicationFlags &= 11383 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 11384 } 11385 if (pBuffer->owned_by_firmware) { 11386 diag_query->ApplicationFlags |= 11387 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 11388 } else { 11389 diag_query->ApplicationFlags &= 11390 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 11391 } 11392 11393 return (DDI_SUCCESS); 11394 } 11395 11396 static int 11397 mptsas_diag_read_buffer(mptsas_t *mpt, 11398 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 11399 uint32_t *return_code, int ioctl_mode) 11400 { 11401 mptsas_fw_diagnostic_buffer_t *pBuffer; 11402 uint8_t i, *pData; 11403 uint32_t unique_id, byte; 11404 int status; 11405 11406 ASSERT(mutex_owned(&mpt->m_mutex)); 11407 11408 unique_id = diag_read_buffer->UniqueId; 11409 11410 /* 11411 * Get the current buffer and look up the unique ID. The unique ID 11412 * should be there. 11413 */ 11414 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11415 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11416 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11417 return (DDI_FAILURE); 11418 } 11419 11420 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 11421 11422 /* 11423 * Make sure requested read is within limits 11424 */ 11425 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead > 11426 pBuffer->buffer_data.size) { 11427 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11428 return (DDI_FAILURE); 11429 } 11430 11431 /* 11432 * Copy the requested data from DMA to the diag_read_buffer. The DMA 11433 * buffer that was allocated is one contiguous buffer. 11434 */ 11435 pData = (uint8_t *)(pBuffer->buffer_data.memp + 11436 diag_read_buffer->StartingOffset); 11437 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0, 11438 DDI_DMA_SYNC_FORCPU); 11439 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) { 11440 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode) 11441 != 0) { 11442 return (DDI_FAILURE); 11443 } 11444 } 11445 diag_read_buffer->Status = 0; 11446 11447 /* 11448 * Set or clear the Force Release flag. 11449 */ 11450 if (pBuffer->force_release) { 11451 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 11452 } else { 11453 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 11454 } 11455 11456 /* 11457 * If buffer is to be reregistered, make sure it's not already owned by 11458 * firmware first. 11459 */ 11460 status = DDI_SUCCESS; 11461 if (!pBuffer->owned_by_firmware) { 11462 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) { 11463 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, 11464 return_code); 11465 } 11466 } 11467 11468 return (status); 11469 } 11470 11471 static int 11472 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release, 11473 uint32_t *return_code) 11474 { 11475 mptsas_fw_diagnostic_buffer_t *pBuffer; 11476 uint8_t i; 11477 uint32_t unique_id; 11478 int status; 11479 11480 ASSERT(mutex_owned(&mpt->m_mutex)); 11481 11482 unique_id = diag_release->UniqueId; 11483 11484 /* 11485 * Get the current buffer and look up the unique ID. The unique ID 11486 * should be there. 11487 */ 11488 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11489 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11490 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11491 return (DDI_FAILURE); 11492 } 11493 11494 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 11495 11496 /* 11497 * If buffer is not owned by firmware, it's already been released. 11498 */ 11499 if (!pBuffer->owned_by_firmware) { 11500 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED; 11501 return (DDI_FAILURE); 11502 } 11503 11504 /* 11505 * Release the buffer. 11506 */ 11507 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code, 11508 MPTSAS_FW_DIAG_TYPE_RELEASE); 11509 return (status); 11510 } 11511 11512 static int 11513 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action, 11514 uint32_t length, uint32_t *return_code, int ioctl_mode) 11515 { 11516 mptsas_fw_diag_register_t diag_register; 11517 mptsas_fw_diag_unregister_t diag_unregister; 11518 mptsas_fw_diag_query_t diag_query; 11519 mptsas_diag_read_buffer_t diag_read_buffer; 11520 mptsas_fw_diag_release_t diag_release; 11521 int status = DDI_SUCCESS; 11522 uint32_t original_return_code, read_buf_len; 11523 11524 ASSERT(mutex_owned(&mpt->m_mutex)); 11525 11526 original_return_code = *return_code; 11527 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11528 11529 switch (action) { 11530 case MPTSAS_FW_DIAG_TYPE_REGISTER: 11531 if (!length) { 11532 *return_code = 11533 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11534 status = DDI_FAILURE; 11535 break; 11536 } 11537 if (ddi_copyin(diag_action, &diag_register, 11538 sizeof (diag_register), ioctl_mode) != 0) { 11539 return (DDI_FAILURE); 11540 } 11541 status = mptsas_diag_register(mpt, &diag_register, 11542 return_code); 11543 break; 11544 11545 case MPTSAS_FW_DIAG_TYPE_UNREGISTER: 11546 if (length < sizeof (diag_unregister)) { 11547 *return_code = 11548 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11549 status = DDI_FAILURE; 11550 break; 11551 } 11552 if (ddi_copyin(diag_action, &diag_unregister, 11553 sizeof (diag_unregister), ioctl_mode) != 0) { 11554 return (DDI_FAILURE); 11555 } 11556 status = mptsas_diag_unregister(mpt, &diag_unregister, 11557 return_code); 11558 break; 11559 11560 case MPTSAS_FW_DIAG_TYPE_QUERY: 11561 if (length < sizeof (diag_query)) { 11562 *return_code = 11563 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11564 status = DDI_FAILURE; 11565 break; 11566 } 11567 if (ddi_copyin(diag_action, &diag_query, 11568 sizeof (diag_query), ioctl_mode) != 0) { 11569 return (DDI_FAILURE); 11570 } 11571 status = mptsas_diag_query(mpt, &diag_query, 11572 return_code); 11573 if (status == DDI_SUCCESS) { 11574 if (ddi_copyout(&diag_query, diag_action, 11575 sizeof (diag_query), ioctl_mode) != 0) { 11576 return (DDI_FAILURE); 11577 } 11578 } 11579 break; 11580 11581 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER: 11582 if (ddi_copyin(diag_action, &diag_read_buffer, 11583 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) { 11584 return (DDI_FAILURE); 11585 } 11586 read_buf_len = sizeof (diag_read_buffer) - 11587 sizeof (diag_read_buffer.DataBuffer) + 11588 diag_read_buffer.BytesToRead; 11589 if (length < read_buf_len) { 11590 *return_code = 11591 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11592 status = DDI_FAILURE; 11593 break; 11594 } 11595 status = mptsas_diag_read_buffer(mpt, 11596 &diag_read_buffer, diag_action + 11597 sizeof (diag_read_buffer) - 4, return_code, 11598 ioctl_mode); 11599 if (status == DDI_SUCCESS) { 11600 if (ddi_copyout(&diag_read_buffer, diag_action, 11601 sizeof (diag_read_buffer) - 4, ioctl_mode) 11602 != 0) { 11603 return (DDI_FAILURE); 11604 } 11605 } 11606 break; 11607 11608 case MPTSAS_FW_DIAG_TYPE_RELEASE: 11609 if (length < sizeof (diag_release)) { 11610 *return_code = 11611 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11612 status = DDI_FAILURE; 11613 break; 11614 } 11615 if (ddi_copyin(diag_action, &diag_release, 11616 sizeof (diag_release), ioctl_mode) != 0) { 11617 return (DDI_FAILURE); 11618 } 11619 status = mptsas_diag_release(mpt, &diag_release, 11620 return_code); 11621 break; 11622 11623 default: 11624 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11625 status = DDI_FAILURE; 11626 break; 11627 } 11628 11629 if ((status == DDI_FAILURE) && 11630 (original_return_code == MPTSAS_FW_DIAG_NEW) && 11631 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) { 11632 status = DDI_SUCCESS; 11633 } 11634 11635 return (status); 11636 } 11637 11638 static int 11639 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode) 11640 { 11641 int status; 11642 mptsas_diag_action_t driver_data; 11643 11644 ASSERT(mutex_owned(&mpt->m_mutex)); 11645 11646 /* 11647 * Copy the user data to a driver data buffer. 11648 */ 11649 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t), 11650 mode) == 0) { 11651 /* 11652 * Send diag action request if Action is valid 11653 */ 11654 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER || 11655 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER || 11656 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY || 11657 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER || 11658 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) { 11659 status = mptsas_do_diag_action(mpt, driver_data.Action, 11660 (void *)(uintptr_t)driver_data.PtrDiagAction, 11661 driver_data.Length, &driver_data.ReturnCode, 11662 mode); 11663 if (status == DDI_SUCCESS) { 11664 if (ddi_copyout(&driver_data.ReturnCode, 11665 &user_data->ReturnCode, 11666 sizeof (user_data->ReturnCode), mode) 11667 != 0) { 11668 status = EFAULT; 11669 } else { 11670 status = 0; 11671 } 11672 } else { 11673 status = EIO; 11674 } 11675 } else { 11676 status = EINVAL; 11677 } 11678 } else { 11679 status = EFAULT; 11680 } 11681 11682 return (status); 11683 } 11684 11685 /* 11686 * This routine handles the "event query" ioctl. 11687 */ 11688 static int 11689 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode, 11690 int *rval) 11691 { 11692 int status; 11693 mptsas_event_query_t driverdata; 11694 uint8_t i; 11695 11696 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE; 11697 11698 mutex_enter(&mpt->m_mutex); 11699 for (i = 0; i < 4; i++) { 11700 driverdata.Types[i] = mpt->m_event_mask[i]; 11701 } 11702 mutex_exit(&mpt->m_mutex); 11703 11704 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) { 11705 status = EFAULT; 11706 } else { 11707 *rval = MPTIOCTL_STATUS_GOOD; 11708 status = 0; 11709 } 11710 11711 return (status); 11712 } 11713 11714 /* 11715 * This routine handles the "event enable" ioctl. 11716 */ 11717 static int 11718 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode, 11719 int *rval) 11720 { 11721 int status; 11722 mptsas_event_enable_t driverdata; 11723 uint8_t i; 11724 11725 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 11726 mutex_enter(&mpt->m_mutex); 11727 for (i = 0; i < 4; i++) { 11728 mpt->m_event_mask[i] = driverdata.Types[i]; 11729 } 11730 mutex_exit(&mpt->m_mutex); 11731 11732 *rval = MPTIOCTL_STATUS_GOOD; 11733 status = 0; 11734 } else { 11735 status = EFAULT; 11736 } 11737 return (status); 11738 } 11739 11740 /* 11741 * This routine handles the "event report" ioctl. 11742 */ 11743 static int 11744 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode, 11745 int *rval) 11746 { 11747 int status; 11748 mptsas_event_report_t driverdata; 11749 11750 mutex_enter(&mpt->m_mutex); 11751 11752 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size), 11753 mode) == 0) { 11754 if (driverdata.Size >= sizeof (mpt->m_events)) { 11755 if (ddi_copyout(mpt->m_events, data->Events, 11756 sizeof (mpt->m_events), mode) != 0) { 11757 status = EFAULT; 11758 } else { 11759 if (driverdata.Size > sizeof (mpt->m_events)) { 11760 driverdata.Size = 11761 sizeof (mpt->m_events); 11762 if (ddi_copyout(&driverdata.Size, 11763 &data->Size, 11764 sizeof (driverdata.Size), 11765 mode) != 0) { 11766 status = EFAULT; 11767 } else { 11768 *rval = MPTIOCTL_STATUS_GOOD; 11769 status = 0; 11770 } 11771 } else { 11772 *rval = MPTIOCTL_STATUS_GOOD; 11773 status = 0; 11774 } 11775 } 11776 } else { 11777 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 11778 status = 0; 11779 } 11780 } else { 11781 status = EFAULT; 11782 } 11783 11784 mutex_exit(&mpt->m_mutex); 11785 return (status); 11786 } 11787 11788 static void 11789 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 11790 { 11791 int *reg_data; 11792 uint_t reglen; 11793 11794 /* 11795 * Lookup the 'reg' property and extract the other data 11796 */ 11797 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 11798 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 11799 DDI_PROP_SUCCESS) { 11800 /* 11801 * Extract the PCI data from the 'reg' property first DWORD. 11802 * The entry looks like the following: 11803 * First DWORD: 11804 * Bits 0 - 7 8-bit Register number 11805 * Bits 8 - 10 3-bit Function number 11806 * Bits 11 - 15 5-bit Device number 11807 * Bits 16 - 23 8-bit Bus number 11808 * Bits 24 - 25 2-bit Address Space type identifier 11809 * 11810 */ 11811 adapter_data->PciInformation.u.bits.BusNumber = 11812 (reg_data[0] & 0x00FF0000) >> 16; 11813 adapter_data->PciInformation.u.bits.DeviceNumber = 11814 (reg_data[0] & 0x0000F800) >> 11; 11815 adapter_data->PciInformation.u.bits.FunctionNumber = 11816 (reg_data[0] & 0x00000700) >> 8; 11817 ddi_prop_free((void *)reg_data); 11818 } else { 11819 /* 11820 * If we can't determine the PCI data then we fill in FF's for 11821 * the data to indicate this. 11822 */ 11823 adapter_data->PCIDeviceHwId = 0xFFFFFFFF; 11824 adapter_data->MpiPortNumber = 0xFFFFFFFF; 11825 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF; 11826 } 11827 11828 /* 11829 * Saved in the mpt->m_fwversion 11830 */ 11831 adapter_data->MpiFirmwareVersion = mpt->m_fwversion; 11832 } 11833 11834 static void 11835 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 11836 { 11837 char *driver_verstr = MPTSAS_MOD_STRING; 11838 11839 mptsas_lookup_pci_data(mpt, adapter_data); 11840 adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS2; 11841 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid; 11842 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid; 11843 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid; 11844 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid; 11845 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr); 11846 adapter_data->BiosVersion = 0; 11847 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion); 11848 } 11849 11850 static void 11851 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info) 11852 { 11853 int *reg_data, i; 11854 uint_t reglen; 11855 11856 /* 11857 * Lookup the 'reg' property and extract the other data 11858 */ 11859 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 11860 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 11861 DDI_PROP_SUCCESS) { 11862 /* 11863 * Extract the PCI data from the 'reg' property first DWORD. 11864 * The entry looks like the following: 11865 * First DWORD: 11866 * Bits 8 - 10 3-bit Function number 11867 * Bits 11 - 15 5-bit Device number 11868 * Bits 16 - 23 8-bit Bus number 11869 */ 11870 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16; 11871 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11; 11872 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8; 11873 ddi_prop_free((void *)reg_data); 11874 } else { 11875 /* 11876 * If we can't determine the PCI info then we fill in FF's for 11877 * the data to indicate this. 11878 */ 11879 pci_info->BusNumber = 0xFFFFFFFF; 11880 pci_info->DeviceNumber = 0xFF; 11881 pci_info->FunctionNumber = 0xFF; 11882 } 11883 11884 /* 11885 * Now get the interrupt vector and the pci header. The vector can 11886 * only be 0 right now. The header is the first 256 bytes of config 11887 * space. 11888 */ 11889 pci_info->InterruptVector = 0; 11890 for (i = 0; i < sizeof (pci_info->PciHeader); i++) { 11891 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle, 11892 i); 11893 } 11894 } 11895 11896 static int 11897 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode) 11898 { 11899 int status = 0; 11900 mptsas_reg_access_t driverdata; 11901 11902 mutex_enter(&mpt->m_mutex); 11903 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 11904 switch (driverdata.Command) { 11905 /* 11906 * IO access is not supported. 11907 */ 11908 case REG_IO_READ: 11909 case REG_IO_WRITE: 11910 mptsas_log(mpt, CE_WARN, "IO access is not " 11911 "supported. Use memory access."); 11912 status = EINVAL; 11913 break; 11914 11915 case REG_MEM_READ: 11916 driverdata.RegData = ddi_get32(mpt->m_datap, 11917 (uint32_t *)(void *)mpt->m_reg + 11918 driverdata.RegOffset); 11919 if (ddi_copyout(&driverdata.RegData, 11920 &data->RegData, 11921 sizeof (driverdata.RegData), mode) != 0) { 11922 mptsas_log(mpt, CE_WARN, "Register " 11923 "Read Failed"); 11924 status = EFAULT; 11925 } 11926 break; 11927 11928 case REG_MEM_WRITE: 11929 ddi_put32(mpt->m_datap, 11930 (uint32_t *)(void *)mpt->m_reg + 11931 driverdata.RegOffset, 11932 driverdata.RegData); 11933 break; 11934 11935 default: 11936 status = EINVAL; 11937 break; 11938 } 11939 } else { 11940 status = EFAULT; 11941 } 11942 11943 mutex_exit(&mpt->m_mutex); 11944 return (status); 11945 } 11946 11947 static int 11948 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp, 11949 int *rval) 11950 { 11951 int status = 0; 11952 mptsas_t *mpt; 11953 mptsas_update_flash_t flashdata; 11954 mptsas_pass_thru_t passthru_data; 11955 mptsas_adapter_data_t adapter_data; 11956 mptsas_pci_info_t pci_info; 11957 int copylen; 11958 11959 int iport_flag = 0; 11960 dev_info_t *dip = NULL; 11961 mptsas_phymask_t phymask = 0; 11962 struct devctl_iocdata *dcp = NULL; 11963 uint32_t slotstatus = 0; 11964 char *addr = NULL; 11965 mptsas_target_t *ptgt = NULL; 11966 11967 *rval = MPTIOCTL_STATUS_GOOD; 11968 if (secpolicy_sys_config(credp, B_FALSE) != 0) { 11969 return (EPERM); 11970 } 11971 11972 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev))); 11973 if (mpt == NULL) { 11974 /* 11975 * Called from iport node, get the states 11976 */ 11977 iport_flag = 1; 11978 dip = mptsas_get_dip_from_dev(dev, &phymask); 11979 if (dip == NULL) { 11980 return (ENXIO); 11981 } 11982 mpt = DIP2MPT(dip); 11983 } 11984 /* Make sure power level is D0 before accessing registers */ 11985 mutex_enter(&mpt->m_mutex); 11986 if (mpt->m_options & MPTSAS_OPT_PM) { 11987 (void) pm_busy_component(mpt->m_dip, 0); 11988 if (mpt->m_power_level != PM_LEVEL_D0) { 11989 mutex_exit(&mpt->m_mutex); 11990 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) != 11991 DDI_SUCCESS) { 11992 mptsas_log(mpt, CE_WARN, 11993 "mptsas%d: mptsas_ioctl: Raise power " 11994 "request failed.", mpt->m_instance); 11995 (void) pm_idle_component(mpt->m_dip, 0); 11996 return (ENXIO); 11997 } 11998 } else { 11999 mutex_exit(&mpt->m_mutex); 12000 } 12001 } else { 12002 mutex_exit(&mpt->m_mutex); 12003 } 12004 12005 if (iport_flag) { 12006 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval); 12007 if (status != 0) { 12008 goto out; 12009 } 12010 /* 12011 * The following code control the OK2RM LED, it doesn't affect 12012 * the ioctl return status. 12013 */ 12014 if ((cmd == DEVCTL_DEVICE_ONLINE) || 12015 (cmd == DEVCTL_DEVICE_OFFLINE)) { 12016 if (ndi_dc_allochdl((void *)data, &dcp) != 12017 NDI_SUCCESS) { 12018 goto out; 12019 } 12020 addr = ndi_dc_getaddr(dcp); 12021 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask); 12022 if (ptgt == NULL) { 12023 NDBG14(("mptsas_ioctl led control: tgt %s not " 12024 "found", addr)); 12025 ndi_dc_freehdl(dcp); 12026 goto out; 12027 } 12028 mutex_enter(&mpt->m_mutex); 12029 if (cmd == DEVCTL_DEVICE_ONLINE) { 12030 ptgt->m_tgt_unconfigured = 0; 12031 } else if (cmd == DEVCTL_DEVICE_OFFLINE) { 12032 ptgt->m_tgt_unconfigured = 1; 12033 } 12034 slotstatus = 0; 12035 #ifdef MPTSAS_GET_LED 12036 /* 12037 * The get led status can't get a valid/reasonable 12038 * state, so ignore the get led status, and write the 12039 * required value directly 12040 */ 12041 if (mptsas_get_led_status(mpt, ptgt, &slotstatus) != 12042 DDI_SUCCESS) { 12043 NDBG14(("mptsas_ioctl: get LED for tgt %s " 12044 "failed %x", addr, slotstatus)); 12045 slotstatus = 0; 12046 } 12047 NDBG14(("mptsas_ioctl: LED status %x for %s", 12048 slotstatus, addr)); 12049 #endif 12050 if (cmd == DEVCTL_DEVICE_OFFLINE) { 12051 slotstatus |= 12052 MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE; 12053 } else { 12054 slotstatus &= 12055 ~MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE; 12056 } 12057 if (mptsas_set_led_status(mpt, ptgt, slotstatus) != 12058 DDI_SUCCESS) { 12059 NDBG14(("mptsas_ioctl: set LED for tgt %s " 12060 "failed %x", addr, slotstatus)); 12061 } 12062 mutex_exit(&mpt->m_mutex); 12063 ndi_dc_freehdl(dcp); 12064 } 12065 goto out; 12066 } 12067 switch (cmd) { 12068 case MPTIOCTL_UPDATE_FLASH: 12069 if (ddi_copyin((void *)data, &flashdata, 12070 sizeof (struct mptsas_update_flash), mode)) { 12071 status = EFAULT; 12072 break; 12073 } 12074 12075 mutex_enter(&mpt->m_mutex); 12076 if (mptsas_update_flash(mpt, 12077 (caddr_t)(long)flashdata.PtrBuffer, 12078 flashdata.ImageSize, flashdata.ImageType, mode)) { 12079 status = EFAULT; 12080 } 12081 12082 /* 12083 * Reset the chip to start using the new 12084 * firmware. Reset if failed also. 12085 */ 12086 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 12087 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 12088 status = EFAULT; 12089 } 12090 mutex_exit(&mpt->m_mutex); 12091 break; 12092 case MPTIOCTL_PASS_THRU: 12093 /* 12094 * The user has requested to pass through a command to 12095 * be executed by the MPT firmware. Call our routine 12096 * which does this. Only allow one passthru IOCTL at 12097 * one time. Other threads will block on 12098 * m_passthru_mutex, which is of adaptive variant. 12099 */ 12100 if (ddi_copyin((void *)data, &passthru_data, 12101 sizeof (mptsas_pass_thru_t), mode)) { 12102 status = EFAULT; 12103 break; 12104 } 12105 mutex_enter(&mpt->m_passthru_mutex); 12106 mutex_enter(&mpt->m_mutex); 12107 status = mptsas_pass_thru(mpt, &passthru_data, mode); 12108 mutex_exit(&mpt->m_mutex); 12109 mutex_exit(&mpt->m_passthru_mutex); 12110 12111 break; 12112 case MPTIOCTL_GET_ADAPTER_DATA: 12113 /* 12114 * The user has requested to read adapter data. Call 12115 * our routine which does this. 12116 */ 12117 bzero(&adapter_data, sizeof (mptsas_adapter_data_t)); 12118 if (ddi_copyin((void *)data, (void *)&adapter_data, 12119 sizeof (mptsas_adapter_data_t), mode)) { 12120 status = EFAULT; 12121 break; 12122 } 12123 if (adapter_data.StructureLength >= 12124 sizeof (mptsas_adapter_data_t)) { 12125 adapter_data.StructureLength = (uint32_t) 12126 sizeof (mptsas_adapter_data_t); 12127 copylen = sizeof (mptsas_adapter_data_t); 12128 mutex_enter(&mpt->m_mutex); 12129 mptsas_read_adapter_data(mpt, &adapter_data); 12130 mutex_exit(&mpt->m_mutex); 12131 } else { 12132 adapter_data.StructureLength = (uint32_t) 12133 sizeof (mptsas_adapter_data_t); 12134 copylen = sizeof (adapter_data.StructureLength); 12135 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 12136 } 12137 if (ddi_copyout((void *)(&adapter_data), (void *)data, 12138 copylen, mode) != 0) { 12139 status = EFAULT; 12140 } 12141 break; 12142 case MPTIOCTL_GET_PCI_INFO: 12143 /* 12144 * The user has requested to read pci info. Call 12145 * our routine which does this. 12146 */ 12147 bzero(&pci_info, sizeof (mptsas_pci_info_t)); 12148 mutex_enter(&mpt->m_mutex); 12149 mptsas_read_pci_info(mpt, &pci_info); 12150 mutex_exit(&mpt->m_mutex); 12151 if (ddi_copyout((void *)(&pci_info), (void *)data, 12152 sizeof (mptsas_pci_info_t), mode) != 0) { 12153 status = EFAULT; 12154 } 12155 break; 12156 case MPTIOCTL_RESET_ADAPTER: 12157 mutex_enter(&mpt->m_mutex); 12158 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 12159 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 12160 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL " 12161 "failed"); 12162 status = EFAULT; 12163 } 12164 mutex_exit(&mpt->m_mutex); 12165 break; 12166 case MPTIOCTL_DIAG_ACTION: 12167 /* 12168 * The user has done a diag buffer action. Call our 12169 * routine which does this. Only allow one diag action 12170 * at one time. 12171 */ 12172 mutex_enter(&mpt->m_mutex); 12173 if (mpt->m_diag_action_in_progress) { 12174 mutex_exit(&mpt->m_mutex); 12175 return (EBUSY); 12176 } 12177 mpt->m_diag_action_in_progress = 1; 12178 status = mptsas_diag_action(mpt, 12179 (mptsas_diag_action_t *)data, mode); 12180 mpt->m_diag_action_in_progress = 0; 12181 mutex_exit(&mpt->m_mutex); 12182 break; 12183 case MPTIOCTL_EVENT_QUERY: 12184 /* 12185 * The user has done an event query. Call our routine 12186 * which does this. 12187 */ 12188 status = mptsas_event_query(mpt, 12189 (mptsas_event_query_t *)data, mode, rval); 12190 break; 12191 case MPTIOCTL_EVENT_ENABLE: 12192 /* 12193 * The user has done an event enable. Call our routine 12194 * which does this. 12195 */ 12196 status = mptsas_event_enable(mpt, 12197 (mptsas_event_enable_t *)data, mode, rval); 12198 break; 12199 case MPTIOCTL_EVENT_REPORT: 12200 /* 12201 * The user has done an event report. Call our routine 12202 * which does this. 12203 */ 12204 status = mptsas_event_report(mpt, 12205 (mptsas_event_report_t *)data, mode, rval); 12206 break; 12207 case MPTIOCTL_REG_ACCESS: 12208 /* 12209 * The user has requested register access. Call our 12210 * routine which does this. 12211 */ 12212 status = mptsas_reg_access(mpt, 12213 (mptsas_reg_access_t *)data, mode); 12214 break; 12215 default: 12216 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, 12217 rval); 12218 break; 12219 } 12220 12221 out: 12222 if (mpt->m_options & MPTSAS_OPT_PM) 12223 (void) pm_idle_component(mpt->m_dip, 0); 12224 return (status); 12225 } 12226 12227 int 12228 mptsas_restart_ioc(mptsas_t *mpt) 12229 { 12230 int rval = DDI_SUCCESS; 12231 mptsas_target_t *ptgt = NULL; 12232 12233 ASSERT(mutex_owned(&mpt->m_mutex)); 12234 12235 /* 12236 * Set a flag telling I/O path that we're processing a reset. This is 12237 * needed because after the reset is complete, the hash table still 12238 * needs to be rebuilt. If I/Os are started before the hash table is 12239 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked 12240 * so that they can be retried. 12241 */ 12242 mpt->m_in_reset = TRUE; 12243 12244 /* 12245 * Set all throttles to HOLD 12246 */ 12247 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 12248 MPTSAS_HASH_FIRST); 12249 while (ptgt != NULL) { 12250 mutex_enter(&ptgt->m_tgt_intr_mutex); 12251 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 12252 mutex_exit(&ptgt->m_tgt_intr_mutex); 12253 12254 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 12255 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 12256 } 12257 12258 /* 12259 * Disable interrupts 12260 */ 12261 MPTSAS_DISABLE_INTR(mpt); 12262 12263 /* 12264 * Abort all commands: outstanding commands, commands in waitq 12265 */ 12266 mptsas_flush_hba(mpt); 12267 12268 /* 12269 * Reinitialize the chip. 12270 */ 12271 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 12272 rval = DDI_FAILURE; 12273 } 12274 12275 /* 12276 * Enable interrupts again 12277 */ 12278 MPTSAS_ENABLE_INTR(mpt); 12279 12280 /* 12281 * If mptsas_init_chip was successful, update the driver data. 12282 */ 12283 if (rval == DDI_SUCCESS) { 12284 mptsas_update_driver_data(mpt); 12285 } 12286 12287 /* 12288 * Reset the throttles 12289 */ 12290 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 12291 MPTSAS_HASH_FIRST); 12292 while (ptgt != NULL) { 12293 mutex_enter(&ptgt->m_tgt_intr_mutex); 12294 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 12295 mutex_exit(&ptgt->m_tgt_intr_mutex); 12296 12297 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 12298 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 12299 } 12300 12301 mptsas_doneq_empty(mpt); 12302 mptsas_restart_hba(mpt); 12303 12304 if (rval != DDI_SUCCESS) { 12305 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 12306 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 12307 } 12308 12309 /* 12310 * Clear the reset flag so that I/Os can continue. 12311 */ 12312 mpt->m_in_reset = FALSE; 12313 12314 return (rval); 12315 } 12316 12317 static int 12318 mptsas_init_chip(mptsas_t *mpt, int first_time) 12319 { 12320 ddi_dma_cookie_t cookie; 12321 uint32_t i; 12322 int rval; 12323 12324 /* 12325 * Check to see if the firmware image is valid 12326 */ 12327 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) & 12328 MPI2_DIAG_FLASH_BAD_SIG) { 12329 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!"); 12330 goto fail; 12331 } 12332 12333 /* 12334 * Reset the chip 12335 */ 12336 rval = mptsas_ioc_reset(mpt); 12337 if (rval == MPTSAS_RESET_FAIL) { 12338 mptsas_log(mpt, CE_WARN, "hard reset failed!"); 12339 goto fail; 12340 } 12341 12342 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) { 12343 goto mur; 12344 } 12345 /* 12346 * Setup configuration space 12347 */ 12348 if (mptsas_config_space_init(mpt) == FALSE) { 12349 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init " 12350 "failed!"); 12351 goto fail; 12352 } 12353 12354 /* 12355 * IOC facts can change after a diag reset so all buffers that are 12356 * based on these numbers must be de-allocated and re-allocated. Get 12357 * new IOC facts each time chip is initialized. 12358 */ 12359 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) { 12360 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed"); 12361 goto fail; 12362 } 12363 12364 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) { 12365 goto fail; 12366 } 12367 /* 12368 * Allocate request message frames, reply free queue, reply descriptor 12369 * post queue, and reply message frames using latest IOC facts. 12370 */ 12371 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) { 12372 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed"); 12373 goto fail; 12374 } 12375 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) { 12376 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!"); 12377 goto fail; 12378 } 12379 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) { 12380 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!"); 12381 goto fail; 12382 } 12383 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) { 12384 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!"); 12385 goto fail; 12386 } 12387 12388 mur: 12389 /* 12390 * Re-Initialize ioc to operational state 12391 */ 12392 if (mptsas_ioc_init(mpt) == DDI_FAILURE) { 12393 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed"); 12394 goto fail; 12395 } 12396 12397 mptsas_alloc_reply_args(mpt); 12398 12399 /* 12400 * Initialize reply post index. Reply free index is initialized after 12401 * the next loop. 12402 */ 12403 mpt->m_post_index = 0; 12404 12405 /* 12406 * Initialize the Reply Free Queue with the physical addresses of our 12407 * reply frames. 12408 */ 12409 cookie.dmac_address = mpt->m_reply_frame_dma_addr; 12410 for (i = 0; i < mpt->m_max_replies; i++) { 12411 ddi_put32(mpt->m_acc_free_queue_hdl, 12412 &((uint32_t *)(void *)mpt->m_free_queue)[i], 12413 cookie.dmac_address); 12414 cookie.dmac_address += mpt->m_reply_frame_size; 12415 } 12416 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 12417 DDI_DMA_SYNC_FORDEV); 12418 12419 /* 12420 * Initialize the reply free index to one past the last frame on the 12421 * queue. This will signify that the queue is empty to start with. 12422 */ 12423 mpt->m_free_index = i; 12424 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i); 12425 12426 /* 12427 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's. 12428 */ 12429 for (i = 0; i < mpt->m_post_queue_depth; i++) { 12430 ddi_put64(mpt->m_acc_post_queue_hdl, 12431 &((uint64_t *)(void *)mpt->m_post_queue)[i], 12432 0xFFFFFFFFFFFFFFFF); 12433 } 12434 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 12435 DDI_DMA_SYNC_FORDEV); 12436 12437 /* 12438 * Enable ports 12439 */ 12440 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) { 12441 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed"); 12442 goto fail; 12443 } 12444 12445 /* 12446 * enable events 12447 */ 12448 if (mptsas_ioc_enable_event_notification(mpt)) { 12449 goto fail; 12450 } 12451 12452 /* 12453 * We need checks in attach and these. 12454 * chip_init is called in mult. places 12455 */ 12456 12457 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 12458 DDI_SUCCESS) || 12459 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 12460 DDI_SUCCESS) || 12461 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 12462 DDI_SUCCESS) || 12463 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 12464 DDI_SUCCESS) || 12465 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 12466 DDI_SUCCESS)) { 12467 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 12468 goto fail; 12469 } 12470 12471 /* Check all acc handles */ 12472 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 12473 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 12474 DDI_SUCCESS) || 12475 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 12476 DDI_SUCCESS) || 12477 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 12478 DDI_SUCCESS) || 12479 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 12480 DDI_SUCCESS) || 12481 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 12482 DDI_SUCCESS) || 12483 (mptsas_check_acc_handle(mpt->m_config_handle) != 12484 DDI_SUCCESS)) { 12485 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 12486 goto fail; 12487 } 12488 12489 return (DDI_SUCCESS); 12490 12491 fail: 12492 return (DDI_FAILURE); 12493 } 12494 12495 static int 12496 mptsas_get_pci_cap(mptsas_t *mpt) 12497 { 12498 ushort_t caps_ptr, cap, cap_count; 12499 12500 if (mpt->m_config_handle == NULL) 12501 return (FALSE); 12502 /* 12503 * Check if capabilities list is supported and if so, 12504 * get initial capabilities pointer and clear bits 0,1. 12505 */ 12506 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) 12507 & PCI_STAT_CAP) { 12508 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 12509 PCI_CONF_CAP_PTR), 4); 12510 } else { 12511 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 12512 } 12513 12514 /* 12515 * Walk capabilities if supported. 12516 */ 12517 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 12518 12519 /* 12520 * Check that we haven't exceeded the maximum number of 12521 * capabilities and that the pointer is in a valid range. 12522 */ 12523 if (++cap_count > 48) { 12524 mptsas_log(mpt, CE_WARN, 12525 "too many device capabilities.\n"); 12526 break; 12527 } 12528 if (caps_ptr < 64) { 12529 mptsas_log(mpt, CE_WARN, 12530 "capabilities pointer 0x%x out of range.\n", 12531 caps_ptr); 12532 break; 12533 } 12534 12535 /* 12536 * Get next capability and check that it is valid. 12537 * For now, we only support power management. 12538 */ 12539 cap = pci_config_get8(mpt->m_config_handle, caps_ptr); 12540 switch (cap) { 12541 case PCI_CAP_ID_PM: 12542 mptsas_log(mpt, CE_NOTE, 12543 "?mptsas%d supports power management.\n", 12544 mpt->m_instance); 12545 mpt->m_options |= MPTSAS_OPT_PM; 12546 12547 /* Save PMCSR offset */ 12548 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR; 12549 break; 12550 /* 12551 * The following capabilities are valid. Any others 12552 * will cause a message to be logged. 12553 */ 12554 case PCI_CAP_ID_VPD: 12555 case PCI_CAP_ID_MSI: 12556 case PCI_CAP_ID_PCIX: 12557 case PCI_CAP_ID_PCI_E: 12558 case PCI_CAP_ID_MSI_X: 12559 break; 12560 default: 12561 mptsas_log(mpt, CE_NOTE, 12562 "?mptsas%d unrecognized capability " 12563 "0x%x.\n", mpt->m_instance, cap); 12564 break; 12565 } 12566 12567 /* 12568 * Get next capabilities pointer and clear bits 0,1. 12569 */ 12570 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 12571 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 12572 } 12573 return (TRUE); 12574 } 12575 12576 static int 12577 mptsas_init_pm(mptsas_t *mpt) 12578 { 12579 char pmc_name[16]; 12580 char *pmc[] = { 12581 NULL, 12582 "0=Off (PCI D3 State)", 12583 "3=On (PCI D0 State)", 12584 NULL 12585 }; 12586 uint16_t pmcsr_stat; 12587 12588 if (mptsas_get_pci_cap(mpt) == FALSE) { 12589 return (DDI_FAILURE); 12590 } 12591 /* 12592 * If PCI's capability does not support PM, then don't need 12593 * to registe the pm-components 12594 */ 12595 if (!(mpt->m_options & MPTSAS_OPT_PM)) 12596 return (DDI_SUCCESS); 12597 /* 12598 * If power management is supported by this chip, create 12599 * pm-components property for the power management framework 12600 */ 12601 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance); 12602 pmc[0] = pmc_name; 12603 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip, 12604 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 12605 mutex_enter(&mpt->m_intr_mutex); 12606 mpt->m_options &= ~MPTSAS_OPT_PM; 12607 mutex_exit(&mpt->m_intr_mutex); 12608 mptsas_log(mpt, CE_WARN, 12609 "mptsas%d: pm-component property creation failed.", 12610 mpt->m_instance); 12611 return (DDI_FAILURE); 12612 } 12613 12614 /* 12615 * Power on device. 12616 */ 12617 (void) pm_busy_component(mpt->m_dip, 0); 12618 pmcsr_stat = pci_config_get16(mpt->m_config_handle, 12619 mpt->m_pmcsr_offset); 12620 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) { 12621 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device", 12622 mpt->m_instance); 12623 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, 12624 PCI_PMCSR_D0); 12625 } 12626 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 12627 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed"); 12628 return (DDI_FAILURE); 12629 } 12630 mutex_enter(&mpt->m_intr_mutex); 12631 mpt->m_power_level = PM_LEVEL_D0; 12632 mutex_exit(&mpt->m_intr_mutex); 12633 /* 12634 * Set pm idle delay. 12635 */ 12636 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 12637 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT); 12638 12639 return (DDI_SUCCESS); 12640 } 12641 12642 static int 12643 mptsas_register_intrs(mptsas_t *mpt) 12644 { 12645 dev_info_t *dip; 12646 int intr_types; 12647 12648 dip = mpt->m_dip; 12649 12650 /* Get supported interrupt types */ 12651 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 12652 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types " 12653 "failed\n"); 12654 return (FALSE); 12655 } 12656 12657 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types)); 12658 12659 /* 12660 * Try MSI, but fall back to FIXED 12661 */ 12662 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) { 12663 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) { 12664 NDBG0(("Using MSI interrupt type")); 12665 mpt->m_intr_type = DDI_INTR_TYPE_MSI; 12666 return (TRUE); 12667 } 12668 } 12669 if (intr_types & DDI_INTR_TYPE_FIXED) { 12670 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) { 12671 NDBG0(("Using FIXED interrupt type")); 12672 mpt->m_intr_type = DDI_INTR_TYPE_FIXED; 12673 return (TRUE); 12674 } else { 12675 NDBG0(("FIXED interrupt registration failed")); 12676 return (FALSE); 12677 } 12678 } 12679 12680 return (FALSE); 12681 } 12682 12683 static void 12684 mptsas_unregister_intrs(mptsas_t *mpt) 12685 { 12686 mptsas_rem_intrs(mpt); 12687 } 12688 12689 /* 12690 * mptsas_add_intrs: 12691 * 12692 * Register FIXED or MSI interrupts. 12693 */ 12694 static int 12695 mptsas_add_intrs(mptsas_t *mpt, int intr_type) 12696 { 12697 dev_info_t *dip = mpt->m_dip; 12698 int avail, actual, count = 0; 12699 int i, flag, ret; 12700 12701 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type)); 12702 12703 /* Get number of interrupts */ 12704 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 12705 if ((ret != DDI_SUCCESS) || (count <= 0)) { 12706 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, " 12707 "ret %d count %d\n", ret, count); 12708 12709 return (DDI_FAILURE); 12710 } 12711 12712 /* Get number of available interrupts */ 12713 ret = ddi_intr_get_navail(dip, intr_type, &avail); 12714 if ((ret != DDI_SUCCESS) || (avail == 0)) { 12715 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, " 12716 "ret %d avail %d\n", ret, avail); 12717 12718 return (DDI_FAILURE); 12719 } 12720 12721 if (avail < count) { 12722 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, " 12723 "navail() returned %d", count, avail); 12724 } 12725 12726 /* Mpt only have one interrupt routine */ 12727 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 12728 count = 1; 12729 } 12730 12731 /* Allocate an array of interrupt handles */ 12732 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t); 12733 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP); 12734 12735 flag = DDI_INTR_ALLOC_NORMAL; 12736 12737 /* call ddi_intr_alloc() */ 12738 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0, 12739 count, &actual, flag); 12740 12741 if ((ret != DDI_SUCCESS) || (actual == 0)) { 12742 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n", 12743 ret); 12744 kmem_free(mpt->m_htable, mpt->m_intr_size); 12745 return (DDI_FAILURE); 12746 } 12747 12748 /* use interrupt count returned or abort? */ 12749 if (actual < count) { 12750 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n", 12751 count, actual); 12752 } 12753 12754 mpt->m_intr_cnt = actual; 12755 12756 /* 12757 * Get priority for first msi, assume remaining are all the same 12758 */ 12759 if ((ret = ddi_intr_get_pri(mpt->m_htable[0], 12760 &mpt->m_intr_pri)) != DDI_SUCCESS) { 12761 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret); 12762 12763 /* Free already allocated intr */ 12764 for (i = 0; i < actual; i++) { 12765 (void) ddi_intr_free(mpt->m_htable[i]); 12766 } 12767 12768 kmem_free(mpt->m_htable, mpt->m_intr_size); 12769 return (DDI_FAILURE); 12770 } 12771 12772 /* Test for high level mutex */ 12773 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) { 12774 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: " 12775 "Hi level interrupt not supported\n"); 12776 12777 /* Free already allocated intr */ 12778 for (i = 0; i < actual; i++) { 12779 (void) ddi_intr_free(mpt->m_htable[i]); 12780 } 12781 12782 kmem_free(mpt->m_htable, mpt->m_intr_size); 12783 return (DDI_FAILURE); 12784 } 12785 12786 /* Call ddi_intr_add_handler() */ 12787 for (i = 0; i < actual; i++) { 12788 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr, 12789 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 12790 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() " 12791 "failed %d\n", ret); 12792 12793 /* Free already allocated intr */ 12794 for (i = 0; i < actual; i++) { 12795 (void) ddi_intr_free(mpt->m_htable[i]); 12796 } 12797 12798 kmem_free(mpt->m_htable, mpt->m_intr_size); 12799 return (DDI_FAILURE); 12800 } 12801 } 12802 12803 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap)) 12804 != DDI_SUCCESS) { 12805 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret); 12806 12807 /* Free already allocated intr */ 12808 for (i = 0; i < actual; i++) { 12809 (void) ddi_intr_free(mpt->m_htable[i]); 12810 } 12811 12812 kmem_free(mpt->m_htable, mpt->m_intr_size); 12813 return (DDI_FAILURE); 12814 } 12815 12816 /* 12817 * Enable interrupts 12818 */ 12819 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 12820 /* Call ddi_intr_block_enable() for MSI interrupts */ 12821 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt); 12822 } else { 12823 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 12824 for (i = 0; i < mpt->m_intr_cnt; i++) { 12825 (void) ddi_intr_enable(mpt->m_htable[i]); 12826 } 12827 } 12828 return (DDI_SUCCESS); 12829 } 12830 12831 /* 12832 * mptsas_rem_intrs: 12833 * 12834 * Unregister FIXED or MSI interrupts 12835 */ 12836 static void 12837 mptsas_rem_intrs(mptsas_t *mpt) 12838 { 12839 int i; 12840 12841 NDBG6(("mptsas_rem_intrs")); 12842 12843 /* Disable all interrupts */ 12844 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 12845 /* Call ddi_intr_block_disable() */ 12846 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt); 12847 } else { 12848 for (i = 0; i < mpt->m_intr_cnt; i++) { 12849 (void) ddi_intr_disable(mpt->m_htable[i]); 12850 } 12851 } 12852 12853 /* Call ddi_intr_remove_handler() */ 12854 for (i = 0; i < mpt->m_intr_cnt; i++) { 12855 (void) ddi_intr_remove_handler(mpt->m_htable[i]); 12856 (void) ddi_intr_free(mpt->m_htable[i]); 12857 } 12858 12859 kmem_free(mpt->m_htable, mpt->m_intr_size); 12860 } 12861 12862 /* 12863 * The IO fault service error handling callback function 12864 */ 12865 /*ARGSUSED*/ 12866 static int 12867 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 12868 { 12869 /* 12870 * as the driver can always deal with an error in any dma or 12871 * access handle, we can just return the fme_status value. 12872 */ 12873 pci_ereport_post(dip, err, NULL); 12874 return (err->fme_status); 12875 } 12876 12877 /* 12878 * mptsas_fm_init - initialize fma capabilities and register with IO 12879 * fault services. 12880 */ 12881 static void 12882 mptsas_fm_init(mptsas_t *mpt) 12883 { 12884 /* 12885 * Need to change iblock to priority for new MSI intr 12886 */ 12887 ddi_iblock_cookie_t fm_ibc; 12888 12889 /* Only register with IO Fault Services if we have some capability */ 12890 if (mpt->m_fm_capabilities) { 12891 /* Adjust access and dma attributes for FMA */ 12892 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 12893 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 12894 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 12895 12896 /* 12897 * Register capabilities with IO Fault Services. 12898 * mpt->m_fm_capabilities will be updated to indicate 12899 * capabilities actually supported (not requested.) 12900 */ 12901 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc); 12902 12903 /* 12904 * Initialize pci ereport capabilities if ereport 12905 * capable (should always be.) 12906 */ 12907 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 12908 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 12909 pci_ereport_setup(mpt->m_dip); 12910 } 12911 12912 /* 12913 * Register error callback if error callback capable. 12914 */ 12915 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 12916 ddi_fm_handler_register(mpt->m_dip, 12917 mptsas_fm_error_cb, (void *) mpt); 12918 } 12919 } 12920 } 12921 12922 /* 12923 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO 12924 * fault services. 12925 * 12926 */ 12927 static void 12928 mptsas_fm_fini(mptsas_t *mpt) 12929 { 12930 /* Only unregister FMA capabilities if registered */ 12931 if (mpt->m_fm_capabilities) { 12932 12933 /* 12934 * Un-register error callback if error callback capable. 12935 */ 12936 12937 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 12938 ddi_fm_handler_unregister(mpt->m_dip); 12939 } 12940 12941 /* 12942 * Release any resources allocated by pci_ereport_setup() 12943 */ 12944 12945 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 12946 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 12947 pci_ereport_teardown(mpt->m_dip); 12948 } 12949 12950 /* Unregister from IO Fault Services */ 12951 ddi_fm_fini(mpt->m_dip); 12952 12953 /* Adjust access and dma attributes for FMA */ 12954 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 12955 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 12956 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 12957 12958 } 12959 } 12960 12961 int 12962 mptsas_check_acc_handle(ddi_acc_handle_t handle) 12963 { 12964 ddi_fm_error_t de; 12965 12966 if (handle == NULL) 12967 return (DDI_FAILURE); 12968 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0); 12969 return (de.fme_status); 12970 } 12971 12972 int 12973 mptsas_check_dma_handle(ddi_dma_handle_t handle) 12974 { 12975 ddi_fm_error_t de; 12976 12977 if (handle == NULL) 12978 return (DDI_FAILURE); 12979 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0); 12980 return (de.fme_status); 12981 } 12982 12983 void 12984 mptsas_fm_ereport(mptsas_t *mpt, char *detail) 12985 { 12986 uint64_t ena; 12987 char buf[FM_MAX_CLASS]; 12988 12989 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 12990 ena = fm_ena_generate(0, FM_ENA_FMT1); 12991 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) { 12992 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP, 12993 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 12994 } 12995 } 12996 12997 static int 12998 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 12999 uint16_t *dev_handle, mptsas_target_t **pptgt) 13000 { 13001 int rval; 13002 uint32_t dev_info; 13003 uint64_t sas_wwn; 13004 mptsas_phymask_t phymask; 13005 uint8_t physport, phynum, config, disk; 13006 mptsas_slots_t *slots = mpt->m_active; 13007 uint64_t devicename; 13008 uint16_t pdev_hdl; 13009 mptsas_target_t *tmp_tgt = NULL; 13010 uint16_t bay_num, enclosure; 13011 13012 ASSERT(*pptgt == NULL); 13013 13014 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle, 13015 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl, 13016 &bay_num, &enclosure); 13017 if (rval != DDI_SUCCESS) { 13018 rval = DEV_INFO_FAIL_PAGE0; 13019 return (rval); 13020 } 13021 13022 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET | 13023 MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13024 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) { 13025 rval = DEV_INFO_WRONG_DEVICE_TYPE; 13026 return (rval); 13027 } 13028 13029 /* 13030 * Check if the dev handle is for a Phys Disk. If so, set return value 13031 * and exit. Don't add Phys Disks to hash. 13032 */ 13033 for (config = 0; config < slots->m_num_raid_configs; config++) { 13034 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 13035 if (*dev_handle == slots->m_raidconfig[config]. 13036 m_physdisk_devhdl[disk]) { 13037 rval = DEV_INFO_PHYS_DISK; 13038 return (rval); 13039 } 13040 } 13041 } 13042 13043 /* 13044 * Get SATA Device Name from SAS device page0 for 13045 * sata device, if device name doesn't exist, set m_sas_wwn to 13046 * 0 for direct attached SATA. For the device behind the expander 13047 * we still can use STP address assigned by expander. 13048 */ 13049 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13050 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 13051 mutex_exit(&mpt->m_mutex); 13052 /* alloc a tmp_tgt to send the cmd */ 13053 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), 13054 KM_SLEEP); 13055 tmp_tgt->m_devhdl = *dev_handle; 13056 tmp_tgt->m_deviceinfo = dev_info; 13057 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 13058 tmp_tgt->m_qfull_retry_interval = 13059 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 13060 tmp_tgt->m_t_throttle = MAX_THROTTLE; 13061 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0); 13062 kmem_free(tmp_tgt, sizeof (struct mptsas_target)); 13063 mutex_enter(&mpt->m_mutex); 13064 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) { 13065 sas_wwn = devicename; 13066 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) { 13067 sas_wwn = 0; 13068 } 13069 } 13070 13071 phymask = mptsas_physport_to_phymask(mpt, physport); 13072 *pptgt = mptsas_tgt_alloc(&slots->m_tgttbl, *dev_handle, sas_wwn, 13073 dev_info, phymask, phynum, mpt); 13074 if (*pptgt == NULL) { 13075 mptsas_log(mpt, CE_WARN, "Failed to allocated target" 13076 "structure!"); 13077 rval = DEV_INFO_FAIL_ALLOC; 13078 return (rval); 13079 } 13080 (*pptgt)->m_enclosure = enclosure; 13081 (*pptgt)->m_slot_num = bay_num; 13082 return (DEV_INFO_SUCCESS); 13083 } 13084 13085 uint64_t 13086 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun) 13087 { 13088 uint64_t sata_guid = 0, *pwwn = NULL; 13089 int target = ptgt->m_devhdl; 13090 uchar_t *inq83 = NULL; 13091 int inq83_len = 0xFF; 13092 uchar_t *dblk = NULL; 13093 int inq83_retry = 3; 13094 int rval = DDI_FAILURE; 13095 13096 inq83 = kmem_zalloc(inq83_len, KM_SLEEP); 13097 13098 inq83_retry: 13099 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 13100 inq83_len, NULL, 1); 13101 if (rval != DDI_SUCCESS) { 13102 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 13103 "0x83 for target:%x, lun:%x failed!", target, lun); 13104 goto out; 13105 } 13106 /* According to SAT2, the first descriptor is logic unit name */ 13107 dblk = &inq83[4]; 13108 if ((dblk[1] & 0x30) != 0) { 13109 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated."); 13110 goto out; 13111 } 13112 pwwn = (uint64_t *)(void *)(&dblk[4]); 13113 if ((dblk[4] & 0xf0) == 0x50) { 13114 sata_guid = BE_64(*pwwn); 13115 goto out; 13116 } else if (dblk[4] == 'A') { 13117 NDBG20(("SATA drive has no NAA format GUID.")); 13118 goto out; 13119 } else { 13120 /* The data is not ready, wait and retry */ 13121 inq83_retry--; 13122 if (inq83_retry <= 0) { 13123 goto out; 13124 } 13125 NDBG20(("The GUID is not ready, retry...")); 13126 delay(1 * drv_usectohz(1000000)); 13127 goto inq83_retry; 13128 } 13129 out: 13130 kmem_free(inq83, inq83_len); 13131 return (sata_guid); 13132 } 13133 13134 static int 13135 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page, 13136 unsigned char *buf, int len, int *reallen, uchar_t evpd) 13137 { 13138 uchar_t cdb[CDB_GROUP0]; 13139 struct scsi_address ap; 13140 struct buf *data_bp = NULL; 13141 int resid = 0; 13142 int ret = DDI_FAILURE; 13143 13144 ASSERT(len <= 0xffff); 13145 13146 ap.a_target = MPTSAS_INVALID_DEVHDL; 13147 ap.a_lun = (uchar_t)(lun); 13148 ap.a_hba_tran = mpt->m_tran; 13149 13150 data_bp = scsi_alloc_consistent_buf(&ap, 13151 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL); 13152 if (data_bp == NULL) { 13153 return (ret); 13154 } 13155 bzero(cdb, CDB_GROUP0); 13156 cdb[0] = SCMD_INQUIRY; 13157 cdb[1] = evpd; 13158 cdb[2] = page; 13159 cdb[3] = (len & 0xff00) >> 8; 13160 cdb[4] = (len & 0x00ff); 13161 cdb[5] = 0; 13162 13163 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp, 13164 &resid); 13165 if (ret == DDI_SUCCESS) { 13166 if (reallen) { 13167 *reallen = len - resid; 13168 } 13169 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len); 13170 } 13171 if (data_bp) { 13172 scsi_free_consistent_buf(data_bp); 13173 } 13174 return (ret); 13175 } 13176 13177 static int 13178 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 13179 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 13180 int *resid) 13181 { 13182 struct scsi_pkt *pktp = NULL; 13183 scsi_hba_tran_t *tran_clone = NULL; 13184 mptsas_tgt_private_t *tgt_private = NULL; 13185 int ret = DDI_FAILURE; 13186 13187 /* 13188 * scsi_hba_tran_t->tran_tgt_private is used to pass the address 13189 * information to scsi_init_pkt, allocate a scsi_hba_tran structure 13190 * to simulate the cmds from sd 13191 */ 13192 tran_clone = kmem_alloc( 13193 sizeof (scsi_hba_tran_t), KM_SLEEP); 13194 if (tran_clone == NULL) { 13195 goto out; 13196 } 13197 bcopy((caddr_t)mpt->m_tran, 13198 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t)); 13199 tgt_private = kmem_alloc( 13200 sizeof (mptsas_tgt_private_t), KM_SLEEP); 13201 if (tgt_private == NULL) { 13202 goto out; 13203 } 13204 tgt_private->t_lun = ap->a_lun; 13205 tgt_private->t_private = ptgt; 13206 tran_clone->tran_tgt_private = tgt_private; 13207 ap->a_hba_tran = tran_clone; 13208 13209 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL, 13210 data_bp, cdblen, sizeof (struct scsi_arq_status), 13211 0, PKT_CONSISTENT, NULL, NULL); 13212 if (pktp == NULL) { 13213 goto out; 13214 } 13215 bcopy(cdb, pktp->pkt_cdbp, cdblen); 13216 pktp->pkt_flags = FLAG_NOPARITY; 13217 if (scsi_poll(pktp) < 0) { 13218 goto out; 13219 } 13220 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) { 13221 goto out; 13222 } 13223 if (resid != NULL) { 13224 *resid = pktp->pkt_resid; 13225 } 13226 13227 ret = DDI_SUCCESS; 13228 out: 13229 if (pktp) { 13230 scsi_destroy_pkt(pktp); 13231 } 13232 if (tran_clone) { 13233 kmem_free(tran_clone, sizeof (scsi_hba_tran_t)); 13234 } 13235 if (tgt_private) { 13236 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 13237 } 13238 return (ret); 13239 } 13240 static int 13241 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun) 13242 { 13243 char *cp = NULL; 13244 char *ptr = NULL; 13245 size_t s = 0; 13246 char *wwid_str = NULL; 13247 char *lun_str = NULL; 13248 long lunnum; 13249 long phyid = -1; 13250 int rc = DDI_FAILURE; 13251 13252 ptr = name; 13253 ASSERT(ptr[0] == 'w' || ptr[0] == 'p'); 13254 ptr++; 13255 if ((cp = strchr(ptr, ',')) == NULL) { 13256 return (DDI_FAILURE); 13257 } 13258 13259 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13260 s = (uintptr_t)cp - (uintptr_t)ptr; 13261 13262 bcopy(ptr, wwid_str, s); 13263 wwid_str[s] = '\0'; 13264 13265 ptr = ++cp; 13266 13267 if ((cp = strchr(ptr, '\0')) == NULL) { 13268 goto out; 13269 } 13270 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13271 s = (uintptr_t)cp - (uintptr_t)ptr; 13272 13273 bcopy(ptr, lun_str, s); 13274 lun_str[s] = '\0'; 13275 13276 if (name[0] == 'p') { 13277 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid); 13278 } else { 13279 rc = scsi_wwnstr_to_wwn(wwid_str, wwid); 13280 } 13281 if (rc != DDI_SUCCESS) 13282 goto out; 13283 13284 if (phyid != -1) { 13285 ASSERT(phyid < MPTSAS_MAX_PHYS); 13286 *phy = (uint8_t)phyid; 13287 } 13288 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum); 13289 if (rc != 0) 13290 goto out; 13291 13292 *lun = (int)lunnum; 13293 rc = DDI_SUCCESS; 13294 out: 13295 if (wwid_str) 13296 kmem_free(wwid_str, SCSI_MAXNAMELEN); 13297 if (lun_str) 13298 kmem_free(lun_str, SCSI_MAXNAMELEN); 13299 13300 return (rc); 13301 } 13302 13303 /* 13304 * mptsas_parse_smp_name() is to parse sas wwn string 13305 * which format is "wWWN" 13306 */ 13307 static int 13308 mptsas_parse_smp_name(char *name, uint64_t *wwn) 13309 { 13310 char *ptr = name; 13311 13312 if (*ptr != 'w') { 13313 return (DDI_FAILURE); 13314 } 13315 13316 ptr++; 13317 if (scsi_wwnstr_to_wwn(ptr, wwn)) { 13318 return (DDI_FAILURE); 13319 } 13320 return (DDI_SUCCESS); 13321 } 13322 13323 static int 13324 mptsas_bus_config(dev_info_t *pdip, uint_t flag, 13325 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 13326 { 13327 int ret = NDI_FAILURE; 13328 int circ = 0; 13329 int circ1 = 0; 13330 mptsas_t *mpt; 13331 char *ptr = NULL; 13332 char *devnm = NULL; 13333 uint64_t wwid = 0; 13334 uint8_t phy = 0xFF; 13335 int lun = 0; 13336 uint_t mflags = flag; 13337 int bconfig = TRUE; 13338 13339 if (scsi_hba_iport_unit_address(pdip) == 0) { 13340 return (DDI_FAILURE); 13341 } 13342 13343 mpt = DIP2MPT(pdip); 13344 if (!mpt) { 13345 return (DDI_FAILURE); 13346 } 13347 /* 13348 * Hold the nexus across the bus_config 13349 */ 13350 ndi_devi_enter(scsi_vhci_dip, &circ); 13351 ndi_devi_enter(pdip, &circ1); 13352 switch (op) { 13353 case BUS_CONFIG_ONE: 13354 /* parse wwid/target name out of name given */ 13355 if ((ptr = strchr((char *)arg, '@')) == NULL) { 13356 ret = NDI_FAILURE; 13357 break; 13358 } 13359 ptr++; 13360 if (strncmp((char *)arg, "smp", 3) == 0) { 13361 /* 13362 * This is a SMP target device 13363 */ 13364 ret = mptsas_parse_smp_name(ptr, &wwid); 13365 if (ret != DDI_SUCCESS) { 13366 ret = NDI_FAILURE; 13367 break; 13368 } 13369 ret = mptsas_config_smp(pdip, wwid, childp); 13370 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) { 13371 /* 13372 * OBP could pass down a non-canonical form 13373 * bootpath without LUN part when LUN is 0. 13374 * So driver need adjust the string. 13375 */ 13376 if (strchr(ptr, ',') == NULL) { 13377 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13378 (void) sprintf(devnm, "%s,0", (char *)arg); 13379 ptr = strchr(devnm, '@'); 13380 ptr++; 13381 } 13382 13383 /* 13384 * The device path is wWWID format and the device 13385 * is not SMP target device. 13386 */ 13387 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun); 13388 if (ret != DDI_SUCCESS) { 13389 ret = NDI_FAILURE; 13390 break; 13391 } 13392 *childp = NULL; 13393 if (ptr[0] == 'w') { 13394 ret = mptsas_config_one_addr(pdip, wwid, 13395 lun, childp); 13396 } else if (ptr[0] == 'p') { 13397 ret = mptsas_config_one_phy(pdip, phy, lun, 13398 childp); 13399 } 13400 13401 /* 13402 * If this is CD/DVD device in OBP path, the 13403 * ndi_busop_bus_config can be skipped as config one 13404 * operation is done above. 13405 */ 13406 if ((ret == NDI_SUCCESS) && (*childp != NULL) && 13407 (strcmp(ddi_node_name(*childp), "cdrom") == 0) && 13408 (strncmp((char *)arg, "disk", 4) == 0)) { 13409 bconfig = FALSE; 13410 ndi_hold_devi(*childp); 13411 } 13412 } else { 13413 ret = NDI_FAILURE; 13414 break; 13415 } 13416 13417 /* 13418 * DDI group instructed us to use this flag. 13419 */ 13420 mflags |= NDI_MDI_FALLBACK; 13421 break; 13422 case BUS_CONFIG_DRIVER: 13423 case BUS_CONFIG_ALL: 13424 mptsas_config_all(pdip); 13425 ret = NDI_SUCCESS; 13426 break; 13427 } 13428 13429 if ((ret == NDI_SUCCESS) && bconfig) { 13430 ret = ndi_busop_bus_config(pdip, mflags, op, 13431 (devnm == NULL) ? arg : devnm, childp, 0); 13432 } 13433 13434 ndi_devi_exit(pdip, circ1); 13435 ndi_devi_exit(scsi_vhci_dip, circ); 13436 if (devnm != NULL) 13437 kmem_free(devnm, SCSI_MAXNAMELEN); 13438 return (ret); 13439 } 13440 13441 static int 13442 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip, 13443 mptsas_target_t *ptgt) 13444 { 13445 int rval = DDI_FAILURE; 13446 struct scsi_inquiry *sd_inq = NULL; 13447 mptsas_t *mpt = DIP2MPT(pdip); 13448 13449 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 13450 13451 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq, 13452 SUN_INQSIZE, 0, (uchar_t)0); 13453 13454 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 13455 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun); 13456 } else { 13457 rval = DDI_FAILURE; 13458 } 13459 13460 kmem_free(sd_inq, SUN_INQSIZE); 13461 return (rval); 13462 } 13463 13464 static int 13465 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 13466 dev_info_t **lundip) 13467 { 13468 int rval; 13469 mptsas_t *mpt = DIP2MPT(pdip); 13470 int phymask; 13471 mptsas_target_t *ptgt = NULL; 13472 13473 /* 13474 * Get the physical port associated to the iport 13475 */ 13476 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 13477 "phymask", 0); 13478 13479 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr); 13480 if (ptgt == NULL) { 13481 /* 13482 * didn't match any device by searching 13483 */ 13484 return (DDI_FAILURE); 13485 } 13486 /* 13487 * If the LUN already exists and the status is online, 13488 * we just return the pointer to dev_info_t directly. 13489 * For the mdi_pathinfo node, we'll handle it in 13490 * mptsas_create_virt_lun() 13491 * TODO should be also in mptsas_handle_dr 13492 */ 13493 13494 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun); 13495 if (*lundip != NULL) { 13496 /* 13497 * TODO Another senario is, we hotplug the same disk 13498 * on the same slot, the devhdl changed, is this 13499 * possible? 13500 * tgt_private->t_private != ptgt 13501 */ 13502 if (sasaddr != ptgt->m_sas_wwn) { 13503 /* 13504 * The device has changed although the devhdl is the 13505 * same (Enclosure mapping mode, change drive on the 13506 * same slot) 13507 */ 13508 return (DDI_FAILURE); 13509 } 13510 return (DDI_SUCCESS); 13511 } 13512 13513 if (phymask == 0) { 13514 /* 13515 * Configure IR volume 13516 */ 13517 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip); 13518 return (rval); 13519 } 13520 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 13521 13522 return (rval); 13523 } 13524 13525 static int 13526 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 13527 dev_info_t **lundip) 13528 { 13529 int rval; 13530 mptsas_t *mpt = DIP2MPT(pdip); 13531 int phymask; 13532 mptsas_target_t *ptgt = NULL; 13533 13534 /* 13535 * Get the physical port associated to the iport 13536 */ 13537 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 13538 "phymask", 0); 13539 13540 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy); 13541 if (ptgt == NULL) { 13542 /* 13543 * didn't match any device by searching 13544 */ 13545 return (DDI_FAILURE); 13546 } 13547 13548 /* 13549 * If the LUN already exists and the status is online, 13550 * we just return the pointer to dev_info_t directly. 13551 * For the mdi_pathinfo node, we'll handle it in 13552 * mptsas_create_virt_lun(). 13553 */ 13554 13555 *lundip = mptsas_find_child_phy(pdip, phy); 13556 if (*lundip != NULL) { 13557 return (DDI_SUCCESS); 13558 } 13559 13560 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 13561 13562 return (rval); 13563 } 13564 13565 static int 13566 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num, 13567 uint8_t *lun_addr_type) 13568 { 13569 uint32_t lun_idx = 0; 13570 13571 ASSERT(lun_num != NULL); 13572 ASSERT(lun_addr_type != NULL); 13573 13574 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 13575 /* determine report luns addressing type */ 13576 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) { 13577 /* 13578 * Vendors in the field have been found to be concatenating 13579 * bus/target/lun to equal the complete lun value instead 13580 * of switching to flat space addressing 13581 */ 13582 /* 00b - peripheral device addressing method */ 13583 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL: 13584 /* FALLTHRU */ 13585 /* 10b - logical unit addressing method */ 13586 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT: 13587 /* FALLTHRU */ 13588 /* 01b - flat space addressing method */ 13589 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE: 13590 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */ 13591 *lun_addr_type = (buf[lun_idx] & 13592 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6; 13593 *lun_num = (buf[lun_idx] & 0x3F) << 8; 13594 *lun_num |= buf[lun_idx + 1]; 13595 return (DDI_SUCCESS); 13596 default: 13597 return (DDI_FAILURE); 13598 } 13599 } 13600 13601 static int 13602 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt) 13603 { 13604 struct buf *repluns_bp = NULL; 13605 struct scsi_address ap; 13606 uchar_t cdb[CDB_GROUP5]; 13607 int ret = DDI_FAILURE; 13608 int retry = 0; 13609 int lun_list_len = 0; 13610 uint16_t lun_num = 0; 13611 uint8_t lun_addr_type = 0; 13612 uint32_t lun_cnt = 0; 13613 uint32_t lun_total = 0; 13614 dev_info_t *cdip = NULL; 13615 uint16_t *saved_repluns = NULL; 13616 char *buffer = NULL; 13617 int buf_len = 128; 13618 mptsas_t *mpt = DIP2MPT(pdip); 13619 uint64_t sas_wwn = 0; 13620 uint8_t phy = 0xFF; 13621 uint32_t dev_info = 0; 13622 13623 mutex_enter(&mpt->m_mutex); 13624 sas_wwn = ptgt->m_sas_wwn; 13625 phy = ptgt->m_phynum; 13626 dev_info = ptgt->m_deviceinfo; 13627 mutex_exit(&mpt->m_mutex); 13628 13629 if (sas_wwn == 0) { 13630 /* 13631 * It's a SATA without Device Name 13632 * So don't try multi-LUNs 13633 */ 13634 if (mptsas_find_child_phy(pdip, phy)) { 13635 return (DDI_SUCCESS); 13636 } else { 13637 /* 13638 * need configure and create node 13639 */ 13640 return (DDI_FAILURE); 13641 } 13642 } 13643 13644 /* 13645 * WWN (SAS address or Device Name exist) 13646 */ 13647 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13648 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 13649 /* 13650 * SATA device with Device Name 13651 * So don't try multi-LUNs 13652 */ 13653 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) { 13654 return (DDI_SUCCESS); 13655 } else { 13656 return (DDI_FAILURE); 13657 } 13658 } 13659 13660 do { 13661 ap.a_target = MPTSAS_INVALID_DEVHDL; 13662 ap.a_lun = 0; 13663 ap.a_hba_tran = mpt->m_tran; 13664 repluns_bp = scsi_alloc_consistent_buf(&ap, 13665 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL); 13666 if (repluns_bp == NULL) { 13667 retry++; 13668 continue; 13669 } 13670 bzero(cdb, CDB_GROUP5); 13671 cdb[0] = SCMD_REPORT_LUNS; 13672 cdb[6] = (buf_len & 0xff000000) >> 24; 13673 cdb[7] = (buf_len & 0x00ff0000) >> 16; 13674 cdb[8] = (buf_len & 0x0000ff00) >> 8; 13675 cdb[9] = (buf_len & 0x000000ff); 13676 13677 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5, 13678 repluns_bp, NULL); 13679 if (ret != DDI_SUCCESS) { 13680 scsi_free_consistent_buf(repluns_bp); 13681 retry++; 13682 continue; 13683 } 13684 lun_list_len = BE_32(*(int *)((void *)( 13685 repluns_bp->b_un.b_addr))); 13686 if (buf_len >= lun_list_len + 8) { 13687 ret = DDI_SUCCESS; 13688 break; 13689 } 13690 scsi_free_consistent_buf(repluns_bp); 13691 buf_len = lun_list_len + 8; 13692 13693 } while (retry < 3); 13694 13695 if (ret != DDI_SUCCESS) 13696 return (ret); 13697 buffer = (char *)repluns_bp->b_un.b_addr; 13698 /* 13699 * find out the number of luns returned by the SCSI ReportLun call 13700 * and allocate buffer space 13701 */ 13702 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 13703 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP); 13704 if (saved_repluns == NULL) { 13705 scsi_free_consistent_buf(repluns_bp); 13706 return (DDI_FAILURE); 13707 } 13708 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) { 13709 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer), 13710 &lun_num, &lun_addr_type) != DDI_SUCCESS) { 13711 continue; 13712 } 13713 saved_repluns[lun_cnt] = lun_num; 13714 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) 13715 ret = DDI_SUCCESS; 13716 else 13717 ret = mptsas_probe_lun(pdip, lun_num, &cdip, 13718 ptgt); 13719 if ((ret == DDI_SUCCESS) && (cdip != NULL)) { 13720 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip, 13721 MPTSAS_DEV_GONE); 13722 } 13723 } 13724 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt); 13725 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total); 13726 scsi_free_consistent_buf(repluns_bp); 13727 return (DDI_SUCCESS); 13728 } 13729 13730 static int 13731 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip) 13732 { 13733 int rval = DDI_FAILURE; 13734 struct scsi_inquiry *sd_inq = NULL; 13735 mptsas_t *mpt = DIP2MPT(pdip); 13736 mptsas_target_t *ptgt = NULL; 13737 13738 mutex_enter(&mpt->m_mutex); 13739 ptgt = mptsas_search_by_devhdl(&mpt->m_active->m_tgttbl, target); 13740 mutex_exit(&mpt->m_mutex); 13741 if (ptgt == NULL) { 13742 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x " 13743 "not found.", target); 13744 return (rval); 13745 } 13746 13747 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 13748 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq, 13749 SUN_INQSIZE, 0, (uchar_t)0); 13750 13751 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 13752 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt, 13753 0); 13754 } else { 13755 rval = DDI_FAILURE; 13756 } 13757 13758 kmem_free(sd_inq, SUN_INQSIZE); 13759 return (rval); 13760 } 13761 13762 /* 13763 * configure all RAID volumes for virtual iport 13764 */ 13765 static void 13766 mptsas_config_all_viport(dev_info_t *pdip) 13767 { 13768 mptsas_t *mpt = DIP2MPT(pdip); 13769 int config, vol; 13770 int target; 13771 dev_info_t *lundip = NULL; 13772 mptsas_slots_t *slots = mpt->m_active; 13773 13774 /* 13775 * Get latest RAID info and search for any Volume DevHandles. If any 13776 * are found, configure the volume. 13777 */ 13778 mutex_enter(&mpt->m_mutex); 13779 for (config = 0; config < slots->m_num_raid_configs; config++) { 13780 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 13781 if (slots->m_raidconfig[config].m_raidvol[vol].m_israid 13782 == 1) { 13783 target = slots->m_raidconfig[config]. 13784 m_raidvol[vol].m_raidhandle; 13785 mutex_exit(&mpt->m_mutex); 13786 (void) mptsas_config_raid(pdip, target, 13787 &lundip); 13788 mutex_enter(&mpt->m_mutex); 13789 } 13790 } 13791 } 13792 mutex_exit(&mpt->m_mutex); 13793 } 13794 13795 static void 13796 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns, 13797 int lun_cnt, mptsas_target_t *ptgt) 13798 { 13799 dev_info_t *child = NULL, *savechild = NULL; 13800 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 13801 uint64_t sas_wwn, wwid; 13802 uint8_t phy; 13803 int lun; 13804 int i; 13805 int find; 13806 char *addr; 13807 char *nodename; 13808 mptsas_t *mpt = DIP2MPT(pdip); 13809 13810 mutex_enter(&mpt->m_mutex); 13811 wwid = ptgt->m_sas_wwn; 13812 mutex_exit(&mpt->m_mutex); 13813 13814 child = ddi_get_child(pdip); 13815 while (child) { 13816 find = 0; 13817 savechild = child; 13818 child = ddi_get_next_sibling(child); 13819 13820 nodename = ddi_node_name(savechild); 13821 if (strcmp(nodename, "smp") == 0) { 13822 continue; 13823 } 13824 13825 addr = ddi_get_name_addr(savechild); 13826 if (addr == NULL) { 13827 continue; 13828 } 13829 13830 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) != 13831 DDI_SUCCESS) { 13832 continue; 13833 } 13834 13835 if (wwid == sas_wwn) { 13836 for (i = 0; i < lun_cnt; i++) { 13837 if (repluns[i] == lun) { 13838 find = 1; 13839 break; 13840 } 13841 } 13842 } else { 13843 continue; 13844 } 13845 if (find == 0) { 13846 /* 13847 * The lun has not been there already 13848 */ 13849 (void) mptsas_offline_lun(pdip, savechild, NULL, 13850 NDI_DEVI_REMOVE); 13851 } 13852 } 13853 13854 pip = mdi_get_next_client_path(pdip, NULL); 13855 while (pip) { 13856 find = 0; 13857 savepip = pip; 13858 addr = MDI_PI(pip)->pi_addr; 13859 13860 pip = mdi_get_next_client_path(pdip, pip); 13861 13862 if (addr == NULL) { 13863 continue; 13864 } 13865 13866 if (mptsas_parse_address(addr, &sas_wwn, &phy, 13867 &lun) != DDI_SUCCESS) { 13868 continue; 13869 } 13870 13871 if (sas_wwn == wwid) { 13872 for (i = 0; i < lun_cnt; i++) { 13873 if (repluns[i] == lun) { 13874 find = 1; 13875 break; 13876 } 13877 } 13878 } else { 13879 continue; 13880 } 13881 13882 if (find == 0) { 13883 /* 13884 * The lun has not been there already 13885 */ 13886 (void) mptsas_offline_lun(pdip, NULL, savepip, 13887 NDI_DEVI_REMOVE); 13888 } 13889 } 13890 } 13891 13892 void 13893 mptsas_update_hashtab(struct mptsas *mpt) 13894 { 13895 uint32_t page_address; 13896 int rval = 0; 13897 uint16_t dev_handle; 13898 mptsas_target_t *ptgt = NULL; 13899 mptsas_smp_t smp_node; 13900 13901 /* 13902 * Get latest RAID info. 13903 */ 13904 (void) mptsas_get_raid_info(mpt); 13905 13906 dev_handle = mpt->m_smp_devhdl; 13907 for (; mpt->m_done_traverse_smp == 0; ) { 13908 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 13909 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle; 13910 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node) 13911 != DDI_SUCCESS) { 13912 break; 13913 } 13914 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl; 13915 (void) mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node); 13916 } 13917 13918 /* 13919 * Config target devices 13920 */ 13921 dev_handle = mpt->m_dev_handle; 13922 13923 /* 13924 * Do loop to get sas device page 0 by GetNextHandle till the 13925 * the last handle. If the sas device is a SATA/SSP target, 13926 * we try to config it. 13927 */ 13928 for (; mpt->m_done_traverse_dev == 0; ) { 13929 ptgt = NULL; 13930 page_address = 13931 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 13932 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 13933 (uint32_t)dev_handle; 13934 rval = mptsas_get_target_device_info(mpt, page_address, 13935 &dev_handle, &ptgt); 13936 if ((rval == DEV_INFO_FAIL_PAGE0) || 13937 (rval == DEV_INFO_FAIL_ALLOC)) { 13938 break; 13939 } 13940 13941 mpt->m_dev_handle = dev_handle; 13942 } 13943 13944 } 13945 13946 void 13947 mptsas_invalid_hashtab(mptsas_hash_table_t *hashtab) 13948 { 13949 mptsas_hash_data_t *data; 13950 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST); 13951 while (data != NULL) { 13952 data->devhdl = MPTSAS_INVALID_DEVHDL; 13953 data->device_info = 0; 13954 /* 13955 * For tgttbl, clear dr_flag. 13956 */ 13957 data->dr_flag = MPTSAS_DR_INACTIVE; 13958 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT); 13959 } 13960 } 13961 13962 void 13963 mptsas_update_driver_data(struct mptsas *mpt) 13964 { 13965 /* 13966 * TODO after hard reset, update the driver data structures 13967 * 1. update port/phymask mapping table mpt->m_phy_info 13968 * 2. invalid all the entries in hash table 13969 * m_devhdl = 0xffff and m_deviceinfo = 0 13970 * 3. call sas_device_page/expander_page to update hash table 13971 */ 13972 mptsas_update_phymask(mpt); 13973 /* 13974 * Invalid the existing entries 13975 */ 13976 mptsas_invalid_hashtab(&mpt->m_active->m_tgttbl); 13977 mptsas_invalid_hashtab(&mpt->m_active->m_smptbl); 13978 mpt->m_done_traverse_dev = 0; 13979 mpt->m_done_traverse_smp = 0; 13980 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL; 13981 mptsas_update_hashtab(mpt); 13982 } 13983 13984 static void 13985 mptsas_config_all(dev_info_t *pdip) 13986 { 13987 dev_info_t *smpdip = NULL; 13988 mptsas_t *mpt = DIP2MPT(pdip); 13989 int phymask = 0; 13990 mptsas_phymask_t phy_mask; 13991 mptsas_target_t *ptgt = NULL; 13992 mptsas_smp_t *psmp; 13993 13994 /* 13995 * Get the phymask associated to the iport 13996 */ 13997 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 13998 "phymask", 0); 13999 14000 /* 14001 * Enumerate RAID volumes here (phymask == 0). 14002 */ 14003 if (phymask == 0) { 14004 mptsas_config_all_viport(pdip); 14005 return; 14006 } 14007 14008 mutex_enter(&mpt->m_mutex); 14009 14010 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) { 14011 mptsas_update_hashtab(mpt); 14012 } 14013 14014 psmp = (mptsas_smp_t *)mptsas_hash_traverse(&mpt->m_active->m_smptbl, 14015 MPTSAS_HASH_FIRST); 14016 while (psmp != NULL) { 14017 phy_mask = psmp->m_phymask; 14018 if (phy_mask == phymask) { 14019 smpdip = NULL; 14020 mutex_exit(&mpt->m_mutex); 14021 (void) mptsas_online_smp(pdip, psmp, &smpdip); 14022 mutex_enter(&mpt->m_mutex); 14023 } 14024 psmp = (mptsas_smp_t *)mptsas_hash_traverse( 14025 &mpt->m_active->m_smptbl, MPTSAS_HASH_NEXT); 14026 } 14027 14028 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 14029 MPTSAS_HASH_FIRST); 14030 while (ptgt != NULL) { 14031 phy_mask = ptgt->m_phymask; 14032 if (phy_mask == phymask) { 14033 mutex_exit(&mpt->m_mutex); 14034 (void) mptsas_config_target(pdip, ptgt); 14035 mutex_enter(&mpt->m_mutex); 14036 } 14037 14038 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 14039 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 14040 } 14041 mutex_exit(&mpt->m_mutex); 14042 } 14043 14044 static int 14045 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt) 14046 { 14047 int rval = DDI_FAILURE; 14048 dev_info_t *tdip; 14049 14050 rval = mptsas_config_luns(pdip, ptgt); 14051 if (rval != DDI_SUCCESS) { 14052 /* 14053 * The return value means the SCMD_REPORT_LUNS 14054 * did not execute successfully. The target maybe 14055 * doesn't support such command. 14056 */ 14057 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt); 14058 } 14059 return (rval); 14060 } 14061 14062 /* 14063 * Return fail if not all the childs/paths are freed. 14064 * if there is any path under the HBA, the return value will be always fail 14065 * because we didn't call mdi_pi_free for path 14066 */ 14067 static int 14068 mptsas_offline_target(dev_info_t *pdip, char *name) 14069 { 14070 dev_info_t *child = NULL, *prechild = NULL; 14071 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 14072 int tmp_rval, rval = DDI_SUCCESS; 14073 char *addr, *cp; 14074 size_t s; 14075 mptsas_t *mpt = DIP2MPT(pdip); 14076 14077 child = ddi_get_child(pdip); 14078 while (child) { 14079 addr = ddi_get_name_addr(child); 14080 prechild = child; 14081 child = ddi_get_next_sibling(child); 14082 14083 if (addr == NULL) { 14084 continue; 14085 } 14086 if ((cp = strchr(addr, ',')) == NULL) { 14087 continue; 14088 } 14089 14090 s = (uintptr_t)cp - (uintptr_t)addr; 14091 14092 if (strncmp(addr, name, s) != 0) { 14093 continue; 14094 } 14095 14096 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL, 14097 NDI_DEVI_REMOVE); 14098 if (tmp_rval != DDI_SUCCESS) { 14099 rval = DDI_FAILURE; 14100 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 14101 prechild, MPTSAS_DEV_GONE) != 14102 DDI_PROP_SUCCESS) { 14103 mptsas_log(mpt, CE_WARN, "mptsas driver " 14104 "unable to create property for " 14105 "SAS %s (MPTSAS_DEV_GONE)", addr); 14106 } 14107 } 14108 } 14109 14110 pip = mdi_get_next_client_path(pdip, NULL); 14111 while (pip) { 14112 addr = MDI_PI(pip)->pi_addr; 14113 savepip = pip; 14114 pip = mdi_get_next_client_path(pdip, pip); 14115 if (addr == NULL) { 14116 continue; 14117 } 14118 14119 if ((cp = strchr(addr, ',')) == NULL) { 14120 continue; 14121 } 14122 14123 s = (uintptr_t)cp - (uintptr_t)addr; 14124 14125 if (strncmp(addr, name, s) != 0) { 14126 continue; 14127 } 14128 14129 (void) mptsas_offline_lun(pdip, NULL, savepip, 14130 NDI_DEVI_REMOVE); 14131 /* 14132 * driver will not invoke mdi_pi_free, so path will not 14133 * be freed forever, return DDI_FAILURE. 14134 */ 14135 rval = DDI_FAILURE; 14136 } 14137 return (rval); 14138 } 14139 14140 static int 14141 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 14142 mdi_pathinfo_t *rpip, uint_t flags) 14143 { 14144 int rval = DDI_FAILURE; 14145 char *devname; 14146 dev_info_t *cdip, *parent; 14147 14148 if (rpip != NULL) { 14149 parent = scsi_vhci_dip; 14150 cdip = mdi_pi_get_client(rpip); 14151 } else if (rdip != NULL) { 14152 parent = pdip; 14153 cdip = rdip; 14154 } else { 14155 return (DDI_FAILURE); 14156 } 14157 14158 /* 14159 * Make sure node is attached otherwise 14160 * it won't have related cache nodes to 14161 * clean up. i_ddi_devi_attached is 14162 * similiar to i_ddi_node_state(cdip) >= 14163 * DS_ATTACHED. 14164 */ 14165 if (i_ddi_devi_attached(cdip)) { 14166 14167 /* Get full devname */ 14168 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 14169 (void) ddi_deviname(cdip, devname); 14170 /* Clean cache */ 14171 (void) devfs_clean(parent, devname + 1, 14172 DV_CLEAN_FORCE); 14173 kmem_free(devname, MAXNAMELEN + 1); 14174 } 14175 if (rpip != NULL) { 14176 if (MDI_PI_IS_OFFLINE(rpip)) { 14177 rval = DDI_SUCCESS; 14178 } else { 14179 rval = mdi_pi_offline(rpip, 0); 14180 } 14181 } else { 14182 rval = ndi_devi_offline(cdip, flags); 14183 } 14184 14185 return (rval); 14186 } 14187 14188 static dev_info_t * 14189 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn) 14190 { 14191 dev_info_t *child = NULL; 14192 char *smp_wwn = NULL; 14193 14194 child = ddi_get_child(parent); 14195 while (child) { 14196 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child, 14197 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn) 14198 != DDI_SUCCESS) { 14199 child = ddi_get_next_sibling(child); 14200 continue; 14201 } 14202 14203 if (strcmp(smp_wwn, str_wwn) == 0) { 14204 ddi_prop_free(smp_wwn); 14205 break; 14206 } 14207 child = ddi_get_next_sibling(child); 14208 ddi_prop_free(smp_wwn); 14209 } 14210 return (child); 14211 } 14212 14213 static int 14214 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags) 14215 { 14216 int rval = DDI_FAILURE; 14217 char *devname; 14218 char wwn_str[MPTSAS_WWN_STRLEN]; 14219 dev_info_t *cdip; 14220 14221 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr); 14222 14223 cdip = mptsas_find_smp_child(pdip, wwn_str); 14224 14225 if (cdip == NULL) 14226 return (DDI_SUCCESS); 14227 14228 /* 14229 * Make sure node is attached otherwise 14230 * it won't have related cache nodes to 14231 * clean up. i_ddi_devi_attached is 14232 * similiar to i_ddi_node_state(cdip) >= 14233 * DS_ATTACHED. 14234 */ 14235 if (i_ddi_devi_attached(cdip)) { 14236 14237 /* Get full devname */ 14238 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 14239 (void) ddi_deviname(cdip, devname); 14240 /* Clean cache */ 14241 (void) devfs_clean(pdip, devname + 1, 14242 DV_CLEAN_FORCE); 14243 kmem_free(devname, MAXNAMELEN + 1); 14244 } 14245 14246 rval = ndi_devi_offline(cdip, flags); 14247 14248 return (rval); 14249 } 14250 14251 static dev_info_t * 14252 mptsas_find_child(dev_info_t *pdip, char *name) 14253 { 14254 dev_info_t *child = NULL; 14255 char *rname = NULL; 14256 int rval = DDI_FAILURE; 14257 14258 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14259 14260 child = ddi_get_child(pdip); 14261 while (child) { 14262 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN); 14263 if (rval != DDI_SUCCESS) { 14264 child = ddi_get_next_sibling(child); 14265 bzero(rname, SCSI_MAXNAMELEN); 14266 continue; 14267 } 14268 14269 if (strcmp(rname, name) == 0) { 14270 break; 14271 } 14272 child = ddi_get_next_sibling(child); 14273 bzero(rname, SCSI_MAXNAMELEN); 14274 } 14275 14276 kmem_free(rname, SCSI_MAXNAMELEN); 14277 14278 return (child); 14279 } 14280 14281 14282 static dev_info_t * 14283 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun) 14284 { 14285 dev_info_t *child = NULL; 14286 char *name = NULL; 14287 char *addr = NULL; 14288 14289 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14290 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14291 (void) sprintf(name, "%016"PRIx64, sasaddr); 14292 (void) sprintf(addr, "w%s,%x", name, lun); 14293 child = mptsas_find_child(pdip, addr); 14294 kmem_free(name, SCSI_MAXNAMELEN); 14295 kmem_free(addr, SCSI_MAXNAMELEN); 14296 return (child); 14297 } 14298 14299 static dev_info_t * 14300 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy) 14301 { 14302 dev_info_t *child; 14303 char *addr; 14304 14305 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14306 (void) sprintf(addr, "p%x,0", phy); 14307 child = mptsas_find_child(pdip, addr); 14308 kmem_free(addr, SCSI_MAXNAMELEN); 14309 return (child); 14310 } 14311 14312 static mdi_pathinfo_t * 14313 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy) 14314 { 14315 mdi_pathinfo_t *path; 14316 char *addr = NULL; 14317 14318 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14319 (void) sprintf(addr, "p%x,0", phy); 14320 path = mdi_pi_find(pdip, NULL, addr); 14321 kmem_free(addr, SCSI_MAXNAMELEN); 14322 return (path); 14323 } 14324 14325 static mdi_pathinfo_t * 14326 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun) 14327 { 14328 mdi_pathinfo_t *path; 14329 char *name = NULL; 14330 char *addr = NULL; 14331 14332 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14333 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14334 (void) sprintf(name, "%016"PRIx64, sasaddr); 14335 (void) sprintf(addr, "w%s,%x", name, lun); 14336 path = mdi_pi_find(parent, NULL, addr); 14337 kmem_free(name, SCSI_MAXNAMELEN); 14338 kmem_free(addr, SCSI_MAXNAMELEN); 14339 14340 return (path); 14341 } 14342 14343 static int 14344 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 14345 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 14346 { 14347 int i = 0; 14348 uchar_t *inq83 = NULL; 14349 int inq83_len1 = 0xFF; 14350 int inq83_len = 0; 14351 int rval = DDI_FAILURE; 14352 ddi_devid_t devid; 14353 char *guid = NULL; 14354 int target = ptgt->m_devhdl; 14355 mdi_pathinfo_t *pip = NULL; 14356 mptsas_t *mpt = DIP2MPT(pdip); 14357 14358 /* 14359 * For DVD/CD ROM and tape devices and optical 14360 * devices, we won't try to enumerate them under 14361 * scsi_vhci, so no need to try page83 14362 */ 14363 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT || 14364 sd_inq->inq_dtype == DTYPE_OPTICAL || 14365 sd_inq->inq_dtype == DTYPE_ESI)) 14366 goto create_lun; 14367 14368 /* 14369 * The LCA returns good SCSI status, but corrupt page 83 data the first 14370 * time it is queried. The solution is to keep trying to request page83 14371 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in 14372 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver 14373 * give up to get VPD page at this stage and fail the enumeration. 14374 */ 14375 14376 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP); 14377 14378 for (i = 0; i < mptsas_inq83_retry_timeout; i++) { 14379 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 14380 inq83_len1, &inq83_len, 1); 14381 if (rval != 0) { 14382 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 14383 "0x83 for target:%x, lun:%x failed!", target, lun); 14384 goto out; 14385 } 14386 /* 14387 * create DEVID from inquiry data 14388 */ 14389 if ((rval = ddi_devid_scsi_encode( 14390 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq, 14391 sizeof (struct scsi_inquiry), NULL, 0, inq83, 14392 (size_t)inq83_len, &devid)) == DDI_SUCCESS) { 14393 /* 14394 * extract GUID from DEVID 14395 */ 14396 guid = ddi_devid_to_guid(devid); 14397 14398 /* 14399 * Do not enable MPXIO if the strlen(guid) is greater 14400 * than MPTSAS_MAX_GUID_LEN, this constrain would be 14401 * handled by framework later. 14402 */ 14403 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) { 14404 ddi_devid_free_guid(guid); 14405 guid = NULL; 14406 if (mpt->m_mpxio_enable == TRUE) { 14407 mptsas_log(mpt, CE_NOTE, "!Target:%x, " 14408 "lun:%x doesn't have a valid GUID, " 14409 "multipathing for this drive is " 14410 "not enabled", target, lun); 14411 } 14412 } 14413 14414 /* 14415 * devid no longer needed 14416 */ 14417 ddi_devid_free(devid); 14418 break; 14419 } else if (rval == DDI_NOT_WELL_FORMED) { 14420 /* 14421 * return value of ddi_devid_scsi_encode equal to 14422 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth 14423 * to retry inquiry page 0x83 and get GUID. 14424 */ 14425 NDBG20(("Not well formed devid, retry...")); 14426 delay(1 * drv_usectohz(1000000)); 14427 continue; 14428 } else { 14429 mptsas_log(mpt, CE_WARN, "!Encode devid failed for " 14430 "path target:%x, lun:%x", target, lun); 14431 rval = DDI_FAILURE; 14432 goto create_lun; 14433 } 14434 } 14435 14436 if (i == mptsas_inq83_retry_timeout) { 14437 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout " 14438 "for path target:%x, lun:%x", target, lun); 14439 } 14440 14441 rval = DDI_FAILURE; 14442 14443 create_lun: 14444 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) { 14445 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip, 14446 ptgt, lun); 14447 } 14448 if (rval != DDI_SUCCESS) { 14449 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip, 14450 ptgt, lun); 14451 14452 } 14453 out: 14454 if (guid != NULL) { 14455 /* 14456 * guid no longer needed 14457 */ 14458 ddi_devid_free_guid(guid); 14459 } 14460 if (inq83 != NULL) 14461 kmem_free(inq83, inq83_len1); 14462 return (rval); 14463 } 14464 14465 static int 14466 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid, 14467 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun) 14468 { 14469 int target; 14470 char *nodename = NULL; 14471 char **compatible = NULL; 14472 int ncompatible = 0; 14473 int mdi_rtn = MDI_FAILURE; 14474 int rval = DDI_FAILURE; 14475 char *old_guid = NULL; 14476 mptsas_t *mpt = DIP2MPT(pdip); 14477 char *lun_addr = NULL; 14478 char *wwn_str = NULL; 14479 char *attached_wwn_str = NULL; 14480 char *component = NULL; 14481 uint8_t phy = 0xFF; 14482 uint64_t sas_wwn; 14483 int64_t lun64 = 0; 14484 uint32_t devinfo; 14485 uint16_t dev_hdl; 14486 uint16_t pdev_hdl; 14487 uint64_t dev_sas_wwn; 14488 uint64_t pdev_sas_wwn; 14489 uint32_t pdev_info; 14490 uint8_t physport; 14491 uint8_t phy_id; 14492 uint32_t page_address; 14493 uint16_t bay_num, enclosure; 14494 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 14495 uint32_t dev_info; 14496 14497 mutex_enter(&mpt->m_mutex); 14498 target = ptgt->m_devhdl; 14499 sas_wwn = ptgt->m_sas_wwn; 14500 devinfo = ptgt->m_deviceinfo; 14501 phy = ptgt->m_phynum; 14502 mutex_exit(&mpt->m_mutex); 14503 14504 if (sas_wwn) { 14505 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun); 14506 } else { 14507 *pip = mptsas_find_path_phy(pdip, phy); 14508 } 14509 14510 if (*pip != NULL) { 14511 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 14512 ASSERT(*lun_dip != NULL); 14513 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip, 14514 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM), 14515 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) { 14516 if (strncmp(guid, old_guid, strlen(guid)) == 0) { 14517 /* 14518 * Same path back online again. 14519 */ 14520 (void) ddi_prop_free(old_guid); 14521 if ((!MDI_PI_IS_ONLINE(*pip)) && 14522 (!MDI_PI_IS_STANDBY(*pip)) && 14523 (ptgt->m_tgt_unconfigured == 0)) { 14524 rval = mdi_pi_online(*pip, 0); 14525 mutex_enter(&mpt->m_mutex); 14526 (void) mptsas_set_led_status(mpt, ptgt, 14527 0); 14528 mutex_exit(&mpt->m_mutex); 14529 } else { 14530 rval = DDI_SUCCESS; 14531 } 14532 if (rval != DDI_SUCCESS) { 14533 mptsas_log(mpt, CE_WARN, "path:target: " 14534 "%x, lun:%x online failed!", target, 14535 lun); 14536 *pip = NULL; 14537 *lun_dip = NULL; 14538 } 14539 return (rval); 14540 } else { 14541 /* 14542 * The GUID of the LUN has changed which maybe 14543 * because customer mapped another volume to the 14544 * same LUN. 14545 */ 14546 mptsas_log(mpt, CE_WARN, "The GUID of the " 14547 "target:%x, lun:%x was changed, maybe " 14548 "because someone mapped another volume " 14549 "to the same LUN", target, lun); 14550 (void) ddi_prop_free(old_guid); 14551 if (!MDI_PI_IS_OFFLINE(*pip)) { 14552 rval = mdi_pi_offline(*pip, 0); 14553 if (rval != MDI_SUCCESS) { 14554 mptsas_log(mpt, CE_WARN, "path:" 14555 "target:%x, lun:%x offline " 14556 "failed!", target, lun); 14557 *pip = NULL; 14558 *lun_dip = NULL; 14559 return (DDI_FAILURE); 14560 } 14561 } 14562 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) { 14563 mptsas_log(mpt, CE_WARN, "path:target:" 14564 "%x, lun:%x free failed!", target, 14565 lun); 14566 *pip = NULL; 14567 *lun_dip = NULL; 14568 return (DDI_FAILURE); 14569 } 14570 } 14571 } else { 14572 mptsas_log(mpt, CE_WARN, "Can't get client-guid " 14573 "property for path:target:%x, lun:%x", target, lun); 14574 *pip = NULL; 14575 *lun_dip = NULL; 14576 return (DDI_FAILURE); 14577 } 14578 } 14579 scsi_hba_nodename_compatible_get(inq, NULL, 14580 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible); 14581 14582 /* 14583 * if nodename can't be determined then print a message and skip it 14584 */ 14585 if (nodename == NULL) { 14586 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible " 14587 "driver for target%d lun %d dtype:0x%02x", target, lun, 14588 inq->inq_dtype); 14589 return (DDI_FAILURE); 14590 } 14591 14592 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 14593 /* The property is needed by MPAPI */ 14594 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 14595 14596 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14597 if (guid) { 14598 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun); 14599 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 14600 } else { 14601 (void) sprintf(lun_addr, "p%x,%x", phy, lun); 14602 (void) sprintf(wwn_str, "p%x", phy); 14603 } 14604 14605 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename, 14606 guid, lun_addr, compatible, ncompatible, 14607 0, pip); 14608 if (mdi_rtn == MDI_SUCCESS) { 14609 14610 if (mdi_prop_update_string(*pip, MDI_GUID, 14611 guid) != DDI_SUCCESS) { 14612 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14613 "create prop for target %d lun %d (MDI_GUID)", 14614 target, lun); 14615 mdi_rtn = MDI_FAILURE; 14616 goto virt_create_done; 14617 } 14618 14619 if (mdi_prop_update_int(*pip, LUN_PROP, 14620 lun) != DDI_SUCCESS) { 14621 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14622 "create prop for target %d lun %d (LUN_PROP)", 14623 target, lun); 14624 mdi_rtn = MDI_FAILURE; 14625 goto virt_create_done; 14626 } 14627 lun64 = (int64_t)lun; 14628 if (mdi_prop_update_int64(*pip, LUN64_PROP, 14629 lun64) != DDI_SUCCESS) { 14630 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14631 "create prop for target %d (LUN64_PROP)", 14632 target); 14633 mdi_rtn = MDI_FAILURE; 14634 goto virt_create_done; 14635 } 14636 if (mdi_prop_update_string_array(*pip, "compatible", 14637 compatible, ncompatible) != 14638 DDI_PROP_SUCCESS) { 14639 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14640 "create prop for target %d lun %d (COMPATIBLE)", 14641 target, lun); 14642 mdi_rtn = MDI_FAILURE; 14643 goto virt_create_done; 14644 } 14645 if (sas_wwn && (mdi_prop_update_string(*pip, 14646 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) { 14647 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14648 "create prop for target %d lun %d " 14649 "(target-port)", target, lun); 14650 mdi_rtn = MDI_FAILURE; 14651 goto virt_create_done; 14652 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip, 14653 "sata-phy", phy) != DDI_PROP_SUCCESS)) { 14654 /* 14655 * Direct attached SATA device without DeviceName 14656 */ 14657 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14658 "create prop for SAS target %d lun %d " 14659 "(sata-phy)", target, lun); 14660 mdi_rtn = MDI_FAILURE; 14661 goto virt_create_done; 14662 } 14663 mutex_enter(&mpt->m_mutex); 14664 14665 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14666 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14667 (uint32_t)ptgt->m_devhdl; 14668 rval = mptsas_get_sas_device_page0(mpt, page_address, 14669 &dev_hdl, &dev_sas_wwn, &dev_info, &physport, 14670 &phy_id, &pdev_hdl, &bay_num, &enclosure); 14671 if (rval != DDI_SUCCESS) { 14672 mutex_exit(&mpt->m_mutex); 14673 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 14674 "parent device for handle %d", page_address); 14675 mdi_rtn = MDI_FAILURE; 14676 goto virt_create_done; 14677 } 14678 14679 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14680 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 14681 rval = mptsas_get_sas_device_page0(mpt, page_address, 14682 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 14683 &phy_id, &pdev_hdl, &bay_num, &enclosure); 14684 if (rval != DDI_SUCCESS) { 14685 mutex_exit(&mpt->m_mutex); 14686 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 14687 "device info for handle %d", page_address); 14688 mdi_rtn = MDI_FAILURE; 14689 goto virt_create_done; 14690 } 14691 14692 mutex_exit(&mpt->m_mutex); 14693 14694 /* 14695 * If this device direct attached to the controller 14696 * set the attached-port to the base wwid 14697 */ 14698 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 14699 != DEVINFO_DIRECT_ATTACHED) { 14700 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 14701 pdev_sas_wwn); 14702 } else { 14703 /* 14704 * Update the iport's attached-port to guid 14705 */ 14706 if (sas_wwn == 0) { 14707 (void) sprintf(wwn_str, "p%x", phy); 14708 } else { 14709 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 14710 } 14711 if (ddi_prop_update_string(DDI_DEV_T_NONE, 14712 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 14713 DDI_PROP_SUCCESS) { 14714 mptsas_log(mpt, CE_WARN, 14715 "mptsas unable to create " 14716 "property for iport target-port" 14717 " %s (sas_wwn)", 14718 wwn_str); 14719 mdi_rtn = MDI_FAILURE; 14720 goto virt_create_done; 14721 } 14722 14723 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 14724 mpt->un.m_base_wwid); 14725 } 14726 14727 if (mdi_prop_update_string(*pip, 14728 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 14729 DDI_PROP_SUCCESS) { 14730 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14731 "property for iport attached-port %s (sas_wwn)", 14732 attached_wwn_str); 14733 mdi_rtn = MDI_FAILURE; 14734 goto virt_create_done; 14735 } 14736 14737 14738 if (inq->inq_dtype == 0) { 14739 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 14740 /* 14741 * set obp path for pathinfo 14742 */ 14743 (void) snprintf(component, MAXPATHLEN, 14744 "disk@%s", lun_addr); 14745 14746 if (mdi_pi_pathname_obp_set(*pip, component) != 14747 DDI_SUCCESS) { 14748 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 14749 "unable to set obp-path for object %s", 14750 component); 14751 mdi_rtn = MDI_FAILURE; 14752 goto virt_create_done; 14753 } 14754 } 14755 14756 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 14757 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 14758 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 14759 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip, 14760 "pm-capable", 1)) != 14761 DDI_PROP_SUCCESS) { 14762 mptsas_log(mpt, CE_WARN, "mptsas driver" 14763 "failed to create pm-capable " 14764 "property, target %d", target); 14765 mdi_rtn = MDI_FAILURE; 14766 goto virt_create_done; 14767 } 14768 } 14769 /* 14770 * Create the phy-num property 14771 */ 14772 if (mdi_prop_update_int(*pip, "phy-num", 14773 ptgt->m_phynum) != DDI_SUCCESS) { 14774 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 14775 "create phy-num property for target %d lun %d", 14776 target, lun); 14777 mdi_rtn = MDI_FAILURE; 14778 goto virt_create_done; 14779 } 14780 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr)); 14781 mdi_rtn = mdi_pi_online(*pip, 0); 14782 if (mdi_rtn == MDI_SUCCESS) { 14783 mutex_enter(&mpt->m_mutex); 14784 if (mptsas_set_led_status(mpt, ptgt, 0) != 14785 DDI_SUCCESS) { 14786 NDBG14(("mptsas: clear LED for slot %x " 14787 "failed", ptgt->m_slot_num)); 14788 } 14789 mutex_exit(&mpt->m_mutex); 14790 } 14791 if (mdi_rtn == MDI_NOT_SUPPORTED) { 14792 mdi_rtn = MDI_FAILURE; 14793 } 14794 virt_create_done: 14795 if (*pip && mdi_rtn != MDI_SUCCESS) { 14796 (void) mdi_pi_free(*pip, 0); 14797 *pip = NULL; 14798 *lun_dip = NULL; 14799 } 14800 } 14801 14802 scsi_hba_nodename_compatible_free(nodename, compatible); 14803 if (lun_addr != NULL) { 14804 kmem_free(lun_addr, SCSI_MAXNAMELEN); 14805 } 14806 if (wwn_str != NULL) { 14807 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 14808 } 14809 if (component != NULL) { 14810 kmem_free(component, MAXPATHLEN); 14811 } 14812 14813 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 14814 } 14815 14816 static int 14817 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq, 14818 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 14819 { 14820 int target; 14821 int rval; 14822 int ndi_rtn = NDI_FAILURE; 14823 uint64_t be_sas_wwn; 14824 char *nodename = NULL; 14825 char **compatible = NULL; 14826 int ncompatible = 0; 14827 int instance = 0; 14828 mptsas_t *mpt = DIP2MPT(pdip); 14829 char *wwn_str = NULL; 14830 char *component = NULL; 14831 char *attached_wwn_str = NULL; 14832 uint8_t phy = 0xFF; 14833 uint64_t sas_wwn; 14834 uint32_t devinfo; 14835 uint16_t dev_hdl; 14836 uint16_t pdev_hdl; 14837 uint64_t pdev_sas_wwn; 14838 uint64_t dev_sas_wwn; 14839 uint32_t pdev_info; 14840 uint8_t physport; 14841 uint8_t phy_id; 14842 uint32_t page_address; 14843 uint16_t bay_num, enclosure; 14844 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 14845 uint32_t dev_info; 14846 int64_t lun64 = 0; 14847 14848 mutex_enter(&mpt->m_mutex); 14849 target = ptgt->m_devhdl; 14850 sas_wwn = ptgt->m_sas_wwn; 14851 devinfo = ptgt->m_deviceinfo; 14852 phy = ptgt->m_phynum; 14853 mutex_exit(&mpt->m_mutex); 14854 14855 /* 14856 * generate compatible property with binding-set "mpt" 14857 */ 14858 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL, 14859 &nodename, &compatible, &ncompatible); 14860 14861 /* 14862 * if nodename can't be determined then print a message and skip it 14863 */ 14864 if (nodename == NULL) { 14865 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver " 14866 "for target %d lun %d", target, lun); 14867 return (DDI_FAILURE); 14868 } 14869 14870 ndi_rtn = ndi_devi_alloc(pdip, nodename, 14871 DEVI_SID_NODEID, lun_dip); 14872 14873 /* 14874 * if lun alloc success, set props 14875 */ 14876 if (ndi_rtn == NDI_SUCCESS) { 14877 14878 if (ndi_prop_update_int(DDI_DEV_T_NONE, 14879 *lun_dip, LUN_PROP, lun) != 14880 DDI_PROP_SUCCESS) { 14881 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14882 "property for target %d lun %d (LUN_PROP)", 14883 target, lun); 14884 ndi_rtn = NDI_FAILURE; 14885 goto phys_create_done; 14886 } 14887 14888 lun64 = (int64_t)lun; 14889 if (ndi_prop_update_int64(DDI_DEV_T_NONE, 14890 *lun_dip, LUN64_PROP, lun64) != 14891 DDI_PROP_SUCCESS) { 14892 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14893 "property for target %d lun64 %d (LUN64_PROP)", 14894 target, lun); 14895 ndi_rtn = NDI_FAILURE; 14896 goto phys_create_done; 14897 } 14898 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, 14899 *lun_dip, "compatible", compatible, ncompatible) 14900 != DDI_PROP_SUCCESS) { 14901 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14902 "property for target %d lun %d (COMPATIBLE)", 14903 target, lun); 14904 ndi_rtn = NDI_FAILURE; 14905 goto phys_create_done; 14906 } 14907 14908 /* 14909 * We need the SAS WWN for non-multipath devices, so 14910 * we'll use the same property as that multipathing 14911 * devices need to present for MPAPI. If we don't have 14912 * a WWN (e.g. parallel SCSI), don't create the prop. 14913 */ 14914 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 14915 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 14916 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE, 14917 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) 14918 != DDI_PROP_SUCCESS) { 14919 mptsas_log(mpt, CE_WARN, "mptsas unable to " 14920 "create property for SAS target %d lun %d " 14921 "(target-port)", target, lun); 14922 ndi_rtn = NDI_FAILURE; 14923 goto phys_create_done; 14924 } 14925 14926 be_sas_wwn = BE_64(sas_wwn); 14927 if (sas_wwn && ndi_prop_update_byte_array( 14928 DDI_DEV_T_NONE, *lun_dip, "port-wwn", 14929 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) { 14930 mptsas_log(mpt, CE_WARN, "mptsas unable to " 14931 "create property for SAS target %d lun %d " 14932 "(port-wwn)", target, lun); 14933 ndi_rtn = NDI_FAILURE; 14934 goto phys_create_done; 14935 } else if ((sas_wwn == 0) && (ndi_prop_update_int( 14936 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) != 14937 DDI_PROP_SUCCESS)) { 14938 /* 14939 * Direct attached SATA device without DeviceName 14940 */ 14941 mptsas_log(mpt, CE_WARN, "mptsas unable to " 14942 "create property for SAS target %d lun %d " 14943 "(sata-phy)", target, lun); 14944 ndi_rtn = NDI_FAILURE; 14945 goto phys_create_done; 14946 } 14947 14948 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 14949 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) { 14950 mptsas_log(mpt, CE_WARN, "mptsas unable to" 14951 "create property for SAS target %d lun %d" 14952 " (SAS_PROP)", target, lun); 14953 ndi_rtn = NDI_FAILURE; 14954 goto phys_create_done; 14955 } 14956 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE, 14957 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) { 14958 mptsas_log(mpt, CE_WARN, "mptsas unable " 14959 "to create guid property for target %d " 14960 "lun %d", target, lun); 14961 ndi_rtn = NDI_FAILURE; 14962 goto phys_create_done; 14963 } 14964 14965 /* 14966 * The following code is to set properties for SM-HBA support, 14967 * it doesn't apply to RAID volumes 14968 */ 14969 if (ptgt->m_phymask == 0) 14970 goto phys_raid_lun; 14971 14972 mutex_enter(&mpt->m_mutex); 14973 14974 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14975 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14976 (uint32_t)ptgt->m_devhdl; 14977 rval = mptsas_get_sas_device_page0(mpt, page_address, 14978 &dev_hdl, &dev_sas_wwn, &dev_info, 14979 &physport, &phy_id, &pdev_hdl, 14980 &bay_num, &enclosure); 14981 if (rval != DDI_SUCCESS) { 14982 mutex_exit(&mpt->m_mutex); 14983 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 14984 "parent device for handle %d.", page_address); 14985 ndi_rtn = NDI_FAILURE; 14986 goto phys_create_done; 14987 } 14988 14989 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 14990 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 14991 rval = mptsas_get_sas_device_page0(mpt, page_address, 14992 &dev_hdl, &pdev_sas_wwn, &pdev_info, 14993 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure); 14994 if (rval != DDI_SUCCESS) { 14995 mutex_exit(&mpt->m_mutex); 14996 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 14997 "device for handle %d.", page_address); 14998 ndi_rtn = NDI_FAILURE; 14999 goto phys_create_done; 15000 } 15001 15002 mutex_exit(&mpt->m_mutex); 15003 15004 /* 15005 * If this device direct attached to the controller 15006 * set the attached-port to the base wwid 15007 */ 15008 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15009 != DEVINFO_DIRECT_ATTACHED) { 15010 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15011 pdev_sas_wwn); 15012 } else { 15013 /* 15014 * Update the iport's attached-port to guid 15015 */ 15016 if (sas_wwn == 0) { 15017 (void) sprintf(wwn_str, "p%x", phy); 15018 } else { 15019 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15020 } 15021 if (ddi_prop_update_string(DDI_DEV_T_NONE, 15022 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15023 DDI_PROP_SUCCESS) { 15024 mptsas_log(mpt, CE_WARN, 15025 "mptsas unable to create " 15026 "property for iport target-port" 15027 " %s (sas_wwn)", 15028 wwn_str); 15029 ndi_rtn = NDI_FAILURE; 15030 goto phys_create_done; 15031 } 15032 15033 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15034 mpt->un.m_base_wwid); 15035 } 15036 15037 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15038 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 15039 DDI_PROP_SUCCESS) { 15040 mptsas_log(mpt, CE_WARN, 15041 "mptsas unable to create " 15042 "property for iport attached-port %s (sas_wwn)", 15043 attached_wwn_str); 15044 ndi_rtn = NDI_FAILURE; 15045 goto phys_create_done; 15046 } 15047 15048 if (IS_ATAPI_DEVICE(dev_info)) { 15049 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15050 *lun_dip, MPTSAS_VARIANT, "atapi") != 15051 DDI_PROP_SUCCESS) { 15052 mptsas_log(mpt, CE_WARN, 15053 "mptsas unable to create " 15054 "property for device variant "); 15055 ndi_rtn = NDI_FAILURE; 15056 goto phys_create_done; 15057 } 15058 } 15059 15060 if (IS_SATA_DEVICE(dev_info)) { 15061 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15062 *lun_dip, MPTSAS_VARIANT, "sata") != 15063 DDI_PROP_SUCCESS) { 15064 mptsas_log(mpt, CE_WARN, 15065 "mptsas unable to create " 15066 "property for device variant "); 15067 ndi_rtn = NDI_FAILURE; 15068 goto phys_create_done; 15069 } 15070 } 15071 phys_raid_lun: 15072 /* 15073 * if this is a SAS controller, and the target is a SATA 15074 * drive, set the 'pm-capable' property for sd and if on 15075 * an OPL platform, also check if this is an ATAPI 15076 * device. 15077 */ 15078 instance = ddi_get_instance(mpt->m_dip); 15079 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 15080 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 15081 NDBG2(("mptsas%d: creating pm-capable property, " 15082 "target %d", instance, target)); 15083 15084 if ((ndi_prop_update_int(DDI_DEV_T_NONE, 15085 *lun_dip, "pm-capable", 1)) != 15086 DDI_PROP_SUCCESS) { 15087 mptsas_log(mpt, CE_WARN, "mptsas " 15088 "failed to create pm-capable " 15089 "property, target %d", target); 15090 ndi_rtn = NDI_FAILURE; 15091 goto phys_create_done; 15092 } 15093 15094 } 15095 15096 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) { 15097 /* 15098 * add 'obp-path' properties for devinfo 15099 */ 15100 bzero(wwn_str, sizeof (wwn_str)); 15101 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 15102 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 15103 if (guid) { 15104 (void) snprintf(component, MAXPATHLEN, 15105 "disk@w%s,%x", wwn_str, lun); 15106 } else { 15107 (void) snprintf(component, MAXPATHLEN, 15108 "disk@p%x,%x", phy, lun); 15109 } 15110 if (ddi_pathname_obp_set(*lun_dip, component) 15111 != DDI_SUCCESS) { 15112 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 15113 "unable to set obp-path for SAS " 15114 "object %s", component); 15115 ndi_rtn = NDI_FAILURE; 15116 goto phys_create_done; 15117 } 15118 } 15119 /* 15120 * Create the phy-num property for non-raid disk 15121 */ 15122 if (ptgt->m_phymask != 0) { 15123 if (ndi_prop_update_int(DDI_DEV_T_NONE, 15124 *lun_dip, "phy-num", ptgt->m_phynum) != 15125 DDI_PROP_SUCCESS) { 15126 mptsas_log(mpt, CE_WARN, "mptsas driver " 15127 "failed to create phy-num property for " 15128 "target %d", target); 15129 ndi_rtn = NDI_FAILURE; 15130 goto phys_create_done; 15131 } 15132 } 15133 phys_create_done: 15134 /* 15135 * If props were setup ok, online the lun 15136 */ 15137 if (ndi_rtn == NDI_SUCCESS) { 15138 /* 15139 * Try to online the new node 15140 */ 15141 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH); 15142 } 15143 if (ndi_rtn == NDI_SUCCESS) { 15144 mutex_enter(&mpt->m_mutex); 15145 if (mptsas_set_led_status(mpt, ptgt, 0) != 15146 DDI_SUCCESS) { 15147 NDBG14(("mptsas: clear LED for tgt %x " 15148 "failed", ptgt->m_slot_num)); 15149 } 15150 mutex_exit(&mpt->m_mutex); 15151 } 15152 15153 /* 15154 * If success set rtn flag, else unwire alloc'd lun 15155 */ 15156 if (ndi_rtn != NDI_SUCCESS) { 15157 NDBG12(("mptsas driver unable to online " 15158 "target %d lun %d", target, lun)); 15159 ndi_prop_remove_all(*lun_dip); 15160 (void) ndi_devi_free(*lun_dip); 15161 *lun_dip = NULL; 15162 } 15163 } 15164 15165 scsi_hba_nodename_compatible_free(nodename, compatible); 15166 15167 if (wwn_str != NULL) { 15168 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 15169 } 15170 if (component != NULL) { 15171 kmem_free(component, MAXPATHLEN); 15172 } 15173 15174 15175 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 15176 } 15177 15178 static int 15179 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn) 15180 { 15181 mptsas_t *mpt = DIP2MPT(pdip); 15182 struct smp_device smp_sd; 15183 15184 /* XXX An HBA driver should not be allocating an smp_device. */ 15185 bzero(&smp_sd, sizeof (struct smp_device)); 15186 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran; 15187 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE); 15188 15189 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS) 15190 return (NDI_FAILURE); 15191 return (NDI_SUCCESS); 15192 } 15193 15194 static int 15195 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip) 15196 { 15197 mptsas_t *mpt = DIP2MPT(pdip); 15198 mptsas_smp_t *psmp = NULL; 15199 int rval; 15200 int phymask; 15201 15202 /* 15203 * Get the physical port associated to the iport 15204 * PHYMASK TODO 15205 */ 15206 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 15207 "phymask", 0); 15208 /* 15209 * Find the smp node in hash table with specified sas address and 15210 * physical port 15211 */ 15212 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn); 15213 if (psmp == NULL) { 15214 return (DDI_FAILURE); 15215 } 15216 15217 rval = mptsas_online_smp(pdip, psmp, smp_dip); 15218 15219 return (rval); 15220 } 15221 15222 static int 15223 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 15224 dev_info_t **smp_dip) 15225 { 15226 char wwn_str[MPTSAS_WWN_STRLEN]; 15227 char attached_wwn_str[MPTSAS_WWN_STRLEN]; 15228 int ndi_rtn = NDI_FAILURE; 15229 int rval = 0; 15230 mptsas_smp_t dev_info; 15231 uint32_t page_address; 15232 mptsas_t *mpt = DIP2MPT(pdip); 15233 uint16_t dev_hdl; 15234 uint64_t sas_wwn; 15235 uint64_t smp_sas_wwn; 15236 uint8_t physport; 15237 uint8_t phy_id; 15238 uint16_t pdev_hdl; 15239 uint8_t numphys = 0; 15240 uint16_t i = 0; 15241 char phymask[MPTSAS_MAX_PHYS]; 15242 char *iport = NULL; 15243 mptsas_phymask_t phy_mask = 0; 15244 uint16_t attached_devhdl; 15245 uint16_t bay_num, enclosure; 15246 15247 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr); 15248 15249 /* 15250 * Probe smp device, prevent the node of removed device from being 15251 * configured succesfully 15252 */ 15253 if (mptsas_probe_smp(pdip, smp_node->m_sasaddr) != NDI_SUCCESS) { 15254 return (DDI_FAILURE); 15255 } 15256 15257 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) { 15258 return (DDI_SUCCESS); 15259 } 15260 15261 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip); 15262 15263 /* 15264 * if lun alloc success, set props 15265 */ 15266 if (ndi_rtn == NDI_SUCCESS) { 15267 /* 15268 * Set the flavor of the child to be SMP flavored 15269 */ 15270 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP); 15271 15272 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15273 *smp_dip, SMP_WWN, wwn_str) != 15274 DDI_PROP_SUCCESS) { 15275 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15276 "property for smp device %s (sas_wwn)", 15277 wwn_str); 15278 ndi_rtn = NDI_FAILURE; 15279 goto smp_create_done; 15280 } 15281 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_sasaddr); 15282 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15283 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != 15284 DDI_PROP_SUCCESS) { 15285 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15286 "property for iport target-port %s (sas_wwn)", 15287 wwn_str); 15288 ndi_rtn = NDI_FAILURE; 15289 goto smp_create_done; 15290 } 15291 15292 mutex_enter(&mpt->m_mutex); 15293 15294 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 15295 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl; 15296 rval = mptsas_get_sas_expander_page0(mpt, page_address, 15297 &dev_info); 15298 if (rval != DDI_SUCCESS) { 15299 mutex_exit(&mpt->m_mutex); 15300 mptsas_log(mpt, CE_WARN, 15301 "mptsas unable to get expander " 15302 "parent device info for %x", page_address); 15303 ndi_rtn = NDI_FAILURE; 15304 goto smp_create_done; 15305 } 15306 15307 smp_node->m_pdevhdl = dev_info.m_pdevhdl; 15308 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15309 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15310 (uint32_t)dev_info.m_pdevhdl; 15311 rval = mptsas_get_sas_device_page0(mpt, page_address, 15312 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, 15313 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure); 15314 if (rval != DDI_SUCCESS) { 15315 mutex_exit(&mpt->m_mutex); 15316 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 15317 "device info for %x", page_address); 15318 ndi_rtn = NDI_FAILURE; 15319 goto smp_create_done; 15320 } 15321 15322 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15323 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15324 (uint32_t)dev_info.m_devhdl; 15325 rval = mptsas_get_sas_device_page0(mpt, page_address, 15326 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo, 15327 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure); 15328 if (rval != DDI_SUCCESS) { 15329 mutex_exit(&mpt->m_mutex); 15330 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 15331 "device info for %x", page_address); 15332 ndi_rtn = NDI_FAILURE; 15333 goto smp_create_done; 15334 } 15335 mutex_exit(&mpt->m_mutex); 15336 15337 /* 15338 * If this smp direct attached to the controller 15339 * set the attached-port to the base wwid 15340 */ 15341 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15342 != DEVINFO_DIRECT_ATTACHED) { 15343 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 15344 sas_wwn); 15345 } else { 15346 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 15347 mpt->un.m_base_wwid); 15348 } 15349 15350 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15351 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) != 15352 DDI_PROP_SUCCESS) { 15353 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15354 "property for smp attached-port %s (sas_wwn)", 15355 attached_wwn_str); 15356 ndi_rtn = NDI_FAILURE; 15357 goto smp_create_done; 15358 } 15359 15360 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 15361 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) { 15362 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15363 "create property for SMP %s (SMP_PROP) ", 15364 wwn_str); 15365 ndi_rtn = NDI_FAILURE; 15366 goto smp_create_done; 15367 } 15368 15369 /* 15370 * check the smp to see whether it direct 15371 * attached to the controller 15372 */ 15373 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15374 != DEVINFO_DIRECT_ATTACHED) { 15375 goto smp_create_done; 15376 } 15377 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 15378 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1); 15379 if (numphys > 0) { 15380 goto smp_create_done; 15381 } 15382 /* 15383 * this iport is an old iport, we need to 15384 * reconfig the props for it. 15385 */ 15386 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 15387 MPTSAS_VIRTUAL_PORT, 0) != 15388 DDI_PROP_SUCCESS) { 15389 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 15390 MPTSAS_VIRTUAL_PORT); 15391 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 15392 "prop update failed"); 15393 goto smp_create_done; 15394 } 15395 15396 mutex_enter(&mpt->m_mutex); 15397 numphys = 0; 15398 iport = ddi_get_name_addr(pdip); 15399 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 15400 bzero(phymask, sizeof (phymask)); 15401 (void) sprintf(phymask, 15402 "%x", mpt->m_phy_info[i].phy_mask); 15403 if (strcmp(phymask, iport) == 0) { 15404 phy_mask = mpt->m_phy_info[i].phy_mask; 15405 break; 15406 } 15407 } 15408 15409 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 15410 if ((phy_mask >> i) & 0x01) { 15411 numphys++; 15412 } 15413 } 15414 /* 15415 * Update PHY info for smhba 15416 */ 15417 if (mptsas_smhba_phy_init(mpt)) { 15418 mutex_exit(&mpt->m_mutex); 15419 mptsas_log(mpt, CE_WARN, "mptsas phy update " 15420 "failed"); 15421 goto smp_create_done; 15422 } 15423 mutex_exit(&mpt->m_mutex); 15424 15425 mptsas_smhba_set_phy_props(mpt, iport, pdip, 15426 numphys, &attached_devhdl); 15427 15428 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 15429 MPTSAS_NUM_PHYS, numphys) != 15430 DDI_PROP_SUCCESS) { 15431 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 15432 MPTSAS_NUM_PHYS); 15433 mptsas_log(mpt, CE_WARN, "mptsas update " 15434 "num phys props failed"); 15435 goto smp_create_done; 15436 } 15437 /* 15438 * Add parent's props for SMHBA support 15439 */ 15440 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip, 15441 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15442 DDI_PROP_SUCCESS) { 15443 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 15444 SCSI_ADDR_PROP_ATTACHED_PORT); 15445 mptsas_log(mpt, CE_WARN, "mptsas update iport" 15446 "attached-port failed"); 15447 goto smp_create_done; 15448 } 15449 15450 smp_create_done: 15451 /* 15452 * If props were setup ok, online the lun 15453 */ 15454 if (ndi_rtn == NDI_SUCCESS) { 15455 /* 15456 * Try to online the new node 15457 */ 15458 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH); 15459 } 15460 15461 /* 15462 * If success set rtn flag, else unwire alloc'd lun 15463 */ 15464 if (ndi_rtn != NDI_SUCCESS) { 15465 NDBG12(("mptsas unable to online " 15466 "SMP target %s", wwn_str)); 15467 ndi_prop_remove_all(*smp_dip); 15468 (void) ndi_devi_free(*smp_dip); 15469 } 15470 } 15471 15472 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 15473 } 15474 15475 /* smp transport routine */ 15476 static int mptsas_smp_start(struct smp_pkt *smp_pkt) 15477 { 15478 uint64_t wwn; 15479 Mpi2SmpPassthroughRequest_t req; 15480 Mpi2SmpPassthroughReply_t rep; 15481 uint32_t direction = 0; 15482 mptsas_t *mpt; 15483 int ret; 15484 uint64_t tmp64; 15485 15486 mpt = (mptsas_t *)smp_pkt->smp_pkt_address-> 15487 smp_a_hba_tran->smp_tran_hba_private; 15488 15489 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE); 15490 /* 15491 * Need to compose a SMP request message 15492 * and call mptsas_do_passthru() function 15493 */ 15494 bzero(&req, sizeof (req)); 15495 bzero(&rep, sizeof (rep)); 15496 req.PassthroughFlags = 0; 15497 req.PhysicalPort = 0xff; 15498 req.ChainOffset = 0; 15499 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH; 15500 15501 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) { 15502 smp_pkt->smp_pkt_reason = ERANGE; 15503 return (DDI_FAILURE); 15504 } 15505 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4)); 15506 15507 req.MsgFlags = 0; 15508 tmp64 = LE_64(wwn); 15509 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE); 15510 if (smp_pkt->smp_pkt_rspsize > 0) { 15511 direction |= MPTSAS_PASS_THRU_DIRECTION_READ; 15512 } 15513 if (smp_pkt->smp_pkt_reqsize > 0) { 15514 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE; 15515 } 15516 15517 mutex_enter(&mpt->m_mutex); 15518 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, 15519 (uint8_t *)smp_pkt->smp_pkt_rsp, 15520 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep), 15521 smp_pkt->smp_pkt_rspsize - 4, direction, 15522 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4, 15523 smp_pkt->smp_pkt_timeout, FKIOCTL); 15524 mutex_exit(&mpt->m_mutex); 15525 if (ret != 0) { 15526 cmn_err(CE_WARN, "smp_start do passthru error %d", ret); 15527 smp_pkt->smp_pkt_reason = (uchar_t)(ret); 15528 return (DDI_FAILURE); 15529 } 15530 /* do passthrough success, check the smp status */ 15531 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 15532 switch (LE_16(rep.IOCStatus)) { 15533 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 15534 smp_pkt->smp_pkt_reason = ENODEV; 15535 break; 15536 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 15537 smp_pkt->smp_pkt_reason = EOVERFLOW; 15538 break; 15539 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 15540 smp_pkt->smp_pkt_reason = EIO; 15541 break; 15542 default: 15543 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc" 15544 "status:%x", LE_16(rep.IOCStatus)); 15545 smp_pkt->smp_pkt_reason = EIO; 15546 break; 15547 } 15548 return (DDI_FAILURE); 15549 } 15550 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) { 15551 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x", 15552 rep.SASStatus); 15553 smp_pkt->smp_pkt_reason = EIO; 15554 return (DDI_FAILURE); 15555 } 15556 15557 return (DDI_SUCCESS); 15558 } 15559 15560 /* 15561 * If we didn't get a match, we need to get sas page0 for each device, and 15562 * untill we get a match. If failed, return NULL 15563 */ 15564 static mptsas_target_t * 15565 mptsas_phy_to_tgt(mptsas_t *mpt, int phymask, uint8_t phy) 15566 { 15567 int i, j = 0; 15568 int rval = 0; 15569 uint16_t cur_handle; 15570 uint32_t page_address; 15571 mptsas_target_t *ptgt = NULL; 15572 15573 /* 15574 * PHY named device must be direct attached and attaches to 15575 * narrow port, if the iport is not parent of the device which 15576 * we are looking for. 15577 */ 15578 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 15579 if ((1 << i) & phymask) 15580 j++; 15581 } 15582 15583 if (j > 1) 15584 return (NULL); 15585 15586 /* 15587 * Must be a narrow port and single device attached to the narrow port 15588 * So the physical port num of device which is equal to the iport's 15589 * port num is the device what we are looking for. 15590 */ 15591 15592 if (mpt->m_phy_info[phy].phy_mask != phymask) 15593 return (NULL); 15594 15595 mutex_enter(&mpt->m_mutex); 15596 15597 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 15598 MPTSAS_HASH_FIRST); 15599 while (ptgt != NULL) { 15600 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) { 15601 mutex_exit(&mpt->m_mutex); 15602 return (ptgt); 15603 } 15604 15605 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 15606 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 15607 } 15608 15609 if (mpt->m_done_traverse_dev) { 15610 mutex_exit(&mpt->m_mutex); 15611 return (NULL); 15612 } 15613 15614 /* If didn't get a match, come here */ 15615 cur_handle = mpt->m_dev_handle; 15616 for (; ; ) { 15617 ptgt = NULL; 15618 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 15619 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle; 15620 rval = mptsas_get_target_device_info(mpt, page_address, 15621 &cur_handle, &ptgt); 15622 if ((rval == DEV_INFO_FAIL_PAGE0) || 15623 (rval == DEV_INFO_FAIL_ALLOC)) { 15624 break; 15625 } 15626 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 15627 (rval == DEV_INFO_PHYS_DISK)) { 15628 continue; 15629 } 15630 mpt->m_dev_handle = cur_handle; 15631 15632 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) { 15633 break; 15634 } 15635 } 15636 15637 mutex_exit(&mpt->m_mutex); 15638 return (ptgt); 15639 } 15640 15641 /* 15642 * The ptgt->m_sas_wwn contains the wwid for each disk. 15643 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid 15644 * If we didn't get a match, we need to get sas page0 for each device, and 15645 * untill we get a match 15646 * If failed, return NULL 15647 */ 15648 static mptsas_target_t * 15649 mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask, uint64_t wwid) 15650 { 15651 int rval = 0; 15652 uint16_t cur_handle; 15653 uint32_t page_address; 15654 mptsas_target_t *tmp_tgt = NULL; 15655 15656 mutex_enter(&mpt->m_mutex); 15657 tmp_tgt = (struct mptsas_target *)mptsas_hash_search( 15658 &mpt->m_active->m_tgttbl, wwid, phymask); 15659 if (tmp_tgt != NULL) { 15660 mutex_exit(&mpt->m_mutex); 15661 return (tmp_tgt); 15662 } 15663 15664 if (phymask == 0) { 15665 /* 15666 * It's IR volume 15667 */ 15668 rval = mptsas_get_raid_info(mpt); 15669 if (rval) { 15670 tmp_tgt = (struct mptsas_target *)mptsas_hash_search( 15671 &mpt->m_active->m_tgttbl, wwid, phymask); 15672 } 15673 mutex_exit(&mpt->m_mutex); 15674 return (tmp_tgt); 15675 } 15676 15677 if (mpt->m_done_traverse_dev) { 15678 mutex_exit(&mpt->m_mutex); 15679 return (NULL); 15680 } 15681 15682 /* If didn't get a match, come here */ 15683 cur_handle = mpt->m_dev_handle; 15684 for (; ; ) { 15685 tmp_tgt = NULL; 15686 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 15687 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle; 15688 rval = mptsas_get_target_device_info(mpt, page_address, 15689 &cur_handle, &tmp_tgt); 15690 if ((rval == DEV_INFO_FAIL_PAGE0) || 15691 (rval == DEV_INFO_FAIL_ALLOC)) { 15692 tmp_tgt = NULL; 15693 break; 15694 } 15695 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 15696 (rval == DEV_INFO_PHYS_DISK)) { 15697 continue; 15698 } 15699 mpt->m_dev_handle = cur_handle; 15700 if ((tmp_tgt->m_sas_wwn) && (tmp_tgt->m_sas_wwn == wwid) && 15701 (tmp_tgt->m_phymask == phymask)) { 15702 break; 15703 } 15704 } 15705 15706 mutex_exit(&mpt->m_mutex); 15707 return (tmp_tgt); 15708 } 15709 15710 static mptsas_smp_t * 15711 mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask, uint64_t wwid) 15712 { 15713 int rval = 0; 15714 uint16_t cur_handle; 15715 uint32_t page_address; 15716 mptsas_smp_t smp_node, *psmp = NULL; 15717 15718 mutex_enter(&mpt->m_mutex); 15719 psmp = (struct mptsas_smp *)mptsas_hash_search(&mpt->m_active->m_smptbl, 15720 wwid, phymask); 15721 if (psmp != NULL) { 15722 mutex_exit(&mpt->m_mutex); 15723 return (psmp); 15724 } 15725 15726 if (mpt->m_done_traverse_smp) { 15727 mutex_exit(&mpt->m_mutex); 15728 return (NULL); 15729 } 15730 15731 /* If didn't get a match, come here */ 15732 cur_handle = mpt->m_smp_devhdl; 15733 for (; ; ) { 15734 psmp = NULL; 15735 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 15736 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle; 15737 rval = mptsas_get_sas_expander_page0(mpt, page_address, 15738 &smp_node); 15739 if (rval != DDI_SUCCESS) { 15740 break; 15741 } 15742 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl; 15743 psmp = mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node); 15744 ASSERT(psmp); 15745 if ((psmp->m_sasaddr) && (psmp->m_sasaddr == wwid) && 15746 (psmp->m_phymask == phymask)) { 15747 break; 15748 } 15749 } 15750 15751 mutex_exit(&mpt->m_mutex); 15752 return (psmp); 15753 } 15754 15755 /* helper functions using hash */ 15756 15757 /* 15758 * Can't have duplicate entries for same devhdl, 15759 * if there are invalid entries, the devhdl should be set to 0xffff 15760 */ 15761 static void * 15762 mptsas_search_by_devhdl(mptsas_hash_table_t *hashtab, uint16_t devhdl) 15763 { 15764 mptsas_hash_data_t *data; 15765 15766 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST); 15767 while (data != NULL) { 15768 if (data->devhdl == devhdl) { 15769 break; 15770 } 15771 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT); 15772 } 15773 return (data); 15774 } 15775 15776 mptsas_target_t * 15777 mptsas_tgt_alloc(mptsas_hash_table_t *hashtab, uint16_t devhdl, uint64_t wwid, 15778 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum, mptsas_t *mpt) 15779 { 15780 mptsas_target_t *tmp_tgt = NULL; 15781 15782 tmp_tgt = mptsas_hash_search(hashtab, wwid, phymask); 15783 if (tmp_tgt != NULL) { 15784 NDBG20(("Hash item already exist")); 15785 tmp_tgt->m_deviceinfo = devinfo; 15786 tmp_tgt->m_devhdl = devhdl; 15787 return (tmp_tgt); 15788 } 15789 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP); 15790 if (tmp_tgt == NULL) { 15791 cmn_err(CE_WARN, "Fatal, allocated tgt failed"); 15792 return (NULL); 15793 } 15794 tmp_tgt->m_devhdl = devhdl; 15795 tmp_tgt->m_sas_wwn = wwid; 15796 tmp_tgt->m_deviceinfo = devinfo; 15797 tmp_tgt->m_phymask = phymask; 15798 tmp_tgt->m_phynum = phynum; 15799 /* Initialized the tgt structure */ 15800 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 15801 tmp_tgt->m_qfull_retry_interval = 15802 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 15803 tmp_tgt->m_t_throttle = MAX_THROTTLE; 15804 mutex_init(&tmp_tgt->m_tgt_intr_mutex, NULL, MUTEX_DRIVER, 15805 DDI_INTR_PRI(mpt->m_intr_pri)); 15806 15807 mptsas_hash_add(hashtab, tmp_tgt); 15808 15809 return (tmp_tgt); 15810 } 15811 15812 static void 15813 mptsas_tgt_free(mptsas_hash_table_t *hashtab, uint64_t wwid, 15814 mptsas_phymask_t phymask) 15815 { 15816 mptsas_target_t *tmp_tgt; 15817 tmp_tgt = mptsas_hash_rem(hashtab, wwid, phymask); 15818 if (tmp_tgt == NULL) { 15819 cmn_err(CE_WARN, "Tgt not found, nothing to free"); 15820 } else { 15821 mutex_destroy(&tmp_tgt->m_tgt_intr_mutex); 15822 kmem_free(tmp_tgt, sizeof (struct mptsas_target)); 15823 } 15824 } 15825 15826 /* 15827 * Return the entry in the hash table 15828 */ 15829 static mptsas_smp_t * 15830 mptsas_smp_alloc(mptsas_hash_table_t *hashtab, mptsas_smp_t *data) 15831 { 15832 uint64_t key1 = data->m_sasaddr; 15833 mptsas_phymask_t key2 = data->m_phymask; 15834 mptsas_smp_t *ret_data; 15835 15836 ret_data = mptsas_hash_search(hashtab, key1, key2); 15837 if (ret_data != NULL) { 15838 bcopy(data, ret_data, sizeof (mptsas_smp_t)); 15839 return (ret_data); 15840 } 15841 15842 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP); 15843 bcopy(data, ret_data, sizeof (mptsas_smp_t)); 15844 mptsas_hash_add(hashtab, ret_data); 15845 return (ret_data); 15846 } 15847 15848 static void 15849 mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid, 15850 mptsas_phymask_t phymask) 15851 { 15852 mptsas_smp_t *tmp_smp; 15853 tmp_smp = mptsas_hash_rem(hashtab, wwid, phymask); 15854 if (tmp_smp == NULL) { 15855 cmn_err(CE_WARN, "Smp element not found, nothing to free"); 15856 } else { 15857 kmem_free(tmp_smp, sizeof (struct mptsas_smp)); 15858 } 15859 } 15860 15861 /* 15862 * Hash operation functions 15863 * key1 is the sas_wwn, key2 is the phymask 15864 */ 15865 static void 15866 mptsas_hash_init(mptsas_hash_table_t *hashtab) 15867 { 15868 if (hashtab == NULL) { 15869 return; 15870 } 15871 bzero(hashtab->head, sizeof (mptsas_hash_node_t) * 15872 MPTSAS_HASH_ARRAY_SIZE); 15873 hashtab->cur = NULL; 15874 hashtab->line = 0; 15875 } 15876 15877 static void 15878 mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen) 15879 { 15880 uint16_t line = 0; 15881 mptsas_hash_node_t *cur = NULL, *last = NULL; 15882 15883 if (hashtab == NULL) { 15884 return; 15885 } 15886 for (line = 0; line < MPTSAS_HASH_ARRAY_SIZE; line++) { 15887 cur = hashtab->head[line]; 15888 while (cur != NULL) { 15889 last = cur; 15890 cur = cur->next; 15891 kmem_free(last->data, datalen); 15892 kmem_free(last, sizeof (mptsas_hash_node_t)); 15893 } 15894 } 15895 } 15896 15897 /* 15898 * You must guarantee the element doesn't exist in the hash table 15899 * before you call mptsas_hash_add() 15900 */ 15901 static void 15902 mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data) 15903 { 15904 uint64_t key1 = ((mptsas_hash_data_t *)data)->key1; 15905 mptsas_phymask_t key2 = ((mptsas_hash_data_t *)data)->key2; 15906 mptsas_hash_node_t **head = NULL; 15907 mptsas_hash_node_t *node = NULL; 15908 15909 if (hashtab == NULL) { 15910 return; 15911 } 15912 ASSERT(mptsas_hash_search(hashtab, key1, key2) == NULL); 15913 node = kmem_zalloc(sizeof (mptsas_hash_node_t), KM_NOSLEEP); 15914 node->data = data; 15915 15916 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]); 15917 if (*head == NULL) { 15918 *head = node; 15919 } else { 15920 node->next = *head; 15921 *head = node; 15922 } 15923 } 15924 15925 static void * 15926 mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1, 15927 mptsas_phymask_t key2) 15928 { 15929 mptsas_hash_node_t **head = NULL; 15930 mptsas_hash_node_t *last = NULL, *cur = NULL; 15931 mptsas_hash_data_t *data; 15932 if (hashtab == NULL) { 15933 return (NULL); 15934 } 15935 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]); 15936 cur = *head; 15937 while (cur != NULL) { 15938 data = cur->data; 15939 if ((data->key1 == key1) && (data->key2 == key2)) { 15940 if (last == NULL) { 15941 (*head) = cur->next; 15942 } else { 15943 last->next = cur->next; 15944 } 15945 kmem_free(cur, sizeof (mptsas_hash_node_t)); 15946 return (data); 15947 } else { 15948 last = cur; 15949 cur = cur->next; 15950 } 15951 } 15952 return (NULL); 15953 } 15954 15955 static void * 15956 mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1, 15957 mptsas_phymask_t key2) 15958 { 15959 mptsas_hash_node_t *cur = NULL; 15960 mptsas_hash_data_t *data; 15961 if (hashtab == NULL) { 15962 return (NULL); 15963 } 15964 cur = hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]; 15965 while (cur != NULL) { 15966 data = cur->data; 15967 if ((data->key1 == key1) && (data->key2 == key2)) { 15968 return (data); 15969 } else { 15970 cur = cur->next; 15971 } 15972 } 15973 return (NULL); 15974 } 15975 15976 static void * 15977 mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos) 15978 { 15979 mptsas_hash_node_t *this = NULL; 15980 15981 if (hashtab == NULL) { 15982 return (NULL); 15983 } 15984 15985 if (pos == MPTSAS_HASH_FIRST) { 15986 hashtab->line = 0; 15987 hashtab->cur = NULL; 15988 this = hashtab->head[0]; 15989 } else { 15990 if (hashtab->cur == NULL) { 15991 return (NULL); 15992 } else { 15993 this = hashtab->cur->next; 15994 } 15995 } 15996 15997 while (this == NULL) { 15998 hashtab->line++; 15999 if (hashtab->line >= MPTSAS_HASH_ARRAY_SIZE) { 16000 /* the traverse reaches the end */ 16001 hashtab->cur = NULL; 16002 return (NULL); 16003 } else { 16004 this = hashtab->head[hashtab->line]; 16005 } 16006 } 16007 hashtab->cur = this; 16008 return (this->data); 16009 } 16010 16011 /* 16012 * Functions for SGPIO LED support 16013 */ 16014 static dev_info_t * 16015 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask) 16016 { 16017 dev_info_t *dip; 16018 int prop; 16019 dip = e_ddi_hold_devi_by_dev(dev, 0); 16020 if (dip == NULL) 16021 return (dip); 16022 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 16023 "phymask", 0); 16024 *phymask = (mptsas_phymask_t)prop; 16025 ddi_release_devi(dip); 16026 return (dip); 16027 } 16028 static mptsas_target_t * 16029 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask) 16030 { 16031 uint8_t phynum; 16032 uint64_t wwn; 16033 int lun; 16034 mptsas_target_t *ptgt = NULL; 16035 16036 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) { 16037 return (NULL); 16038 } 16039 if (addr[0] == 'w') { 16040 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn); 16041 } else { 16042 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum); 16043 } 16044 return (ptgt); 16045 } 16046 16047 #ifdef MPTSAS_GET_LED 16048 static int 16049 mptsas_get_led_status(mptsas_t *mpt, mptsas_target_t *ptgt, 16050 uint32_t *slotstatus) 16051 { 16052 return (mptsas_send_sep(mpt, ptgt, slotstatus, 16053 MPI2_SEP_REQ_ACTION_READ_STATUS)); 16054 } 16055 #endif 16056 static int 16057 mptsas_set_led_status(mptsas_t *mpt, mptsas_target_t *ptgt, uint32_t slotstatus) 16058 { 16059 NDBG14(("mptsas_ioctl: set LED status %x for slot %x", 16060 slotstatus, ptgt->m_slot_num)); 16061 return (mptsas_send_sep(mpt, ptgt, &slotstatus, 16062 MPI2_SEP_REQ_ACTION_WRITE_STATUS)); 16063 } 16064 /* 16065 * send sep request, use enclosure/slot addressing 16066 */ 16067 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt, 16068 uint32_t *status, uint8_t act) 16069 { 16070 Mpi2SepRequest_t req; 16071 Mpi2SepReply_t rep; 16072 int ret; 16073 16074 ASSERT(mutex_owned(&mpt->m_mutex)); 16075 16076 bzero(&req, sizeof (req)); 16077 bzero(&rep, sizeof (rep)); 16078 16079 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR; 16080 req.Action = act; 16081 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS; 16082 req.EnclosureHandle = LE_16(ptgt->m_enclosure); 16083 req.Slot = LE_16(ptgt->m_slot_num); 16084 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16085 req.SlotStatus = LE_32(*status); 16086 } 16087 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 16088 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 16089 if (ret != 0) { 16090 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP " 16091 "Processor Request message error %d", ret); 16092 return (DDI_FAILURE); 16093 } 16094 /* do passthrough success, check the ioc status */ 16095 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 16096 if ((LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) == 16097 MPI2_IOCSTATUS_INVALID_FIELD) { 16098 mptsas_log(mpt, CE_NOTE, "send sep act %x: Not " 16099 "supported action, loginfo %x", act, 16100 LE_32(rep.IOCLogInfo)); 16101 return (DDI_FAILURE); 16102 } 16103 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc " 16104 "status:%x", act, LE_16(rep.IOCStatus)); 16105 return (DDI_FAILURE); 16106 } 16107 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16108 *status = LE_32(rep.SlotStatus); 16109 } 16110 16111 return (DDI_SUCCESS); 16112 } 16113 16114 int 16115 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 16116 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 16117 uint32_t alloc_size, ddi_dma_cookie_t *cookiep) 16118 { 16119 ddi_dma_cookie_t new_cookie; 16120 size_t alloc_len; 16121 uint_t ncookie; 16122 16123 if (cookiep == NULL) 16124 cookiep = &new_cookie; 16125 16126 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP, 16127 NULL, dma_hdp) != DDI_SUCCESS) { 16128 dma_hdp = NULL; 16129 return (FALSE); 16130 } 16131 16132 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr, 16133 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len, 16134 acc_hdp) != DDI_SUCCESS) { 16135 ddi_dma_free_handle(dma_hdp); 16136 dma_hdp = NULL; 16137 return (FALSE); 16138 } 16139 16140 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len, 16141 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL, 16142 cookiep, &ncookie) != DDI_DMA_MAPPED) { 16143 (void) ddi_dma_mem_free(acc_hdp); 16144 ddi_dma_free_handle(dma_hdp); 16145 dma_hdp = NULL; 16146 return (FALSE); 16147 } 16148 16149 return (TRUE); 16150 } 16151 16152 void 16153 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp) 16154 { 16155 if (*dma_hdp == NULL) 16156 return; 16157 16158 (void) ddi_dma_unbind_handle(*dma_hdp); 16159 (void) ddi_dma_mem_free(acc_hdp); 16160 ddi_dma_free_handle(dma_hdp); 16161 dma_hdp = NULL; 16162 } 16163 16164 static int 16165 mptsas_outstanding_cmds_n(mptsas_t *mpt) 16166 { 16167 int n = 0, i; 16168 for (i = 0; i < mpt->m_slot_freeq_pair_n; i++) { 16169 mutex_enter(&mpt->m_slot_freeq_pairp[i]. 16170 m_slot_allocq.s.m_fq_mutex); 16171 mutex_enter(&mpt->m_slot_freeq_pairp[i]. 16172 m_slot_releq.s.m_fq_mutex); 16173 n += (mpt->m_slot_freeq_pairp[i].m_slot_allocq.s.m_fq_n_init - 16174 mpt->m_slot_freeq_pairp[i].m_slot_allocq.s.m_fq_n - 16175 mpt->m_slot_freeq_pairp[i].m_slot_releq.s.m_fq_n); 16176 mutex_exit(&mpt->m_slot_freeq_pairp[i]. 16177 m_slot_releq.s.m_fq_mutex); 16178 mutex_exit(&mpt->m_slot_freeq_pairp[i]. 16179 m_slot_allocq.s.m_fq_mutex); 16180 } 16181 if (mpt->m_max_requests - 2 < n) 16182 panic("mptsas: free slot allocq and releq crazy"); 16183 return (n); 16184 } 16185