1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Copyright (c) 2000 to 2010, LSI Corporation. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms of all code within 32 * this file that is exclusively owned by LSI, with or without 33 * modification, is permitted provided that, in addition to the CDDL 1.0 34 * License requirements, the following conditions are met: 35 * 36 * Neither the name of the author nor the names of its contributors may be 37 * used to endorse or promote products derived from this software without 38 * specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 43 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 44 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 46 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 47 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 48 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 51 * DAMAGE. 52 */ 53 54 /* 55 * mptsas - This is a driver based on LSI Logic's MPT2.0 interface. 56 * 57 */ 58 59 #if defined(lint) || defined(DEBUG) 60 #define MPTSAS_DEBUG 61 #endif 62 63 /* 64 * standard header files. 65 */ 66 #include <sys/note.h> 67 #include <sys/scsi/scsi.h> 68 #include <sys/pci.h> 69 #include <sys/file.h> 70 #include <sys/policy.h> 71 #include <sys/sysevent.h> 72 #include <sys/sysevent/eventdefs.h> 73 #include <sys/sysevent/dr.h> 74 #include <sys/sata/sata_defs.h> 75 76 #pragma pack(1) 77 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h> 78 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h> 79 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 80 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h> 81 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h> 82 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h> 83 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h> 85 #pragma pack() 86 87 /* 88 * private header files. 89 * 90 */ 91 #include <sys/scsi/impl/scsi_reset_notify.h> 92 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h> 93 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 94 #include <sys/raidioctl.h> 95 96 #include <sys/fs/dv_node.h> /* devfs_clean */ 97 98 /* 99 * FMA header files 100 */ 101 #include <sys/ddifm.h> 102 #include <sys/fm/protocol.h> 103 #include <sys/fm/util.h> 104 #include <sys/fm/io/ddi.h> 105 106 /* 107 * autoconfiguration data and routines. 108 */ 109 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 110 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 111 static int mptsas_power(dev_info_t *dip, int component, int level); 112 113 /* 114 * cb_ops function 115 */ 116 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 117 cred_t *credp, int *rval); 118 #ifdef __sparc 119 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd); 120 #else /* __sparc */ 121 static int mptsas_quiesce(dev_info_t *devi); 122 #endif /* __sparc */ 123 124 /* 125 * Resource initilaization for hardware 126 */ 127 static void mptsas_setup_cmd_reg(mptsas_t *mpt); 128 static void mptsas_disable_bus_master(mptsas_t *mpt); 129 static void mptsas_hba_fini(mptsas_t *mpt); 130 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp); 131 static int mptsas_alloc_request_frames(mptsas_t *mpt); 132 static int mptsas_alloc_reply_frames(mptsas_t *mpt); 133 static int mptsas_alloc_free_queue(mptsas_t *mpt); 134 static int mptsas_alloc_post_queue(mptsas_t *mpt); 135 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 136 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 137 138 /* 139 * SCSA function prototypes 140 */ 141 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt); 142 static int mptsas_scsi_reset(struct scsi_address *ap, int level); 143 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt); 144 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly); 145 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, 146 int tgtonly); 147 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt); 148 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap, 149 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 150 int tgtlen, int flags, int (*callback)(), caddr_t arg); 151 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt); 152 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap, 153 struct scsi_pkt *pkt); 154 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 155 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 156 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 157 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 158 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 159 void (*callback)(caddr_t), caddr_t arg); 160 static int mptsas_get_name(struct scsi_device *sd, char *name, int len); 161 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len); 162 static int mptsas_scsi_quiesce(dev_info_t *dip); 163 static int mptsas_scsi_unquiesce(dev_info_t *dip); 164 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags, 165 ddi_bus_config_op_t op, void *arg, dev_info_t **childp); 166 167 /* 168 * SMP functions 169 */ 170 static int mptsas_smp_start(struct smp_pkt *smp_pkt); 171 172 /* 173 * internal function prototypes. 174 */ 175 static int mptsas_quiesce_bus(mptsas_t *mpt); 176 static int mptsas_unquiesce_bus(mptsas_t *mpt); 177 178 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size); 179 static void mptsas_free_handshake_msg(mptsas_t *mpt); 180 181 static void mptsas_ncmds_checkdrain(void *arg); 182 183 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd); 184 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 185 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 186 static void mptsas_accept_tx_waitq(mptsas_t *mpt); 187 188 static int mptsas_do_detach(dev_info_t *dev); 189 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl); 190 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, 191 struct scsi_pkt *pkt); 192 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp); 193 194 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd); 195 static void mptsas_handle_event(void *args); 196 static int mptsas_handle_event_sync(void *args); 197 static void mptsas_handle_dr(void *args); 198 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 199 dev_info_t *pdip); 200 201 static void mptsas_restart_cmd(void *); 202 203 static void mptsas_flush_hba(mptsas_t *mpt); 204 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, 205 uint8_t tasktype); 206 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, 207 uchar_t reason, uint_t stat); 208 209 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2); 210 static void mptsas_process_intr(mptsas_t *mpt, 211 pMpi2ReplyDescriptorsUnion_t reply_desc_union); 212 static void mptsas_handle_scsi_io_success(mptsas_t *mpt, 213 pMpi2ReplyDescriptorsUnion_t reply_desc); 214 static void mptsas_handle_address_reply(mptsas_t *mpt, 215 pMpi2ReplyDescriptorsUnion_t reply_desc); 216 static int mptsas_wait_intr(mptsas_t *mpt, int polltime); 217 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, 218 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl); 219 220 static void mptsas_watch(void *arg); 221 static void mptsas_watchsubr(mptsas_t *mpt); 222 static void mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl); 223 224 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd); 225 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 226 uint8_t *data, uint32_t request_size, uint32_t reply_size, 227 uint32_t data_size, uint32_t direction, uint8_t *dataout, 228 uint32_t dataout_size, short timeout, int mode); 229 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl); 230 231 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, 232 uint32_t unique_id); 233 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd); 234 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt, 235 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code); 236 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt, 237 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 238 uint32_t diag_type); 239 static int mptsas_diag_register(mptsas_t *mpt, 240 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code); 241 static int mptsas_diag_unregister(mptsas_t *mpt, 242 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code); 243 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 244 uint32_t *return_code); 245 static int mptsas_diag_read_buffer(mptsas_t *mpt, 246 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 247 uint32_t *return_code, int ioctl_mode); 248 static int mptsas_diag_release(mptsas_t *mpt, 249 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code); 250 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, 251 uint8_t *diag_action, uint32_t length, uint32_t *return_code, 252 int ioctl_mode); 253 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data, 254 int mode); 255 256 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 257 int cmdlen, int tgtlen, int statuslen, int kf); 258 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd); 259 260 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags); 261 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg); 262 263 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg, 264 int kmflags); 265 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg); 266 267 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 268 mptsas_cmd_t *cmd); 269 static void mptsas_check_task_mgt(mptsas_t *mpt, 270 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd); 271 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 272 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 273 int *resid); 274 275 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag); 276 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 277 278 static void mptsas_restart_hba(mptsas_t *mpt); 279 static void mptsas_restart_waitq(mptsas_t *mpt); 280 281 static void mptsas_deliver_doneq_thread(mptsas_t *mpt); 282 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 283 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t); 284 285 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t); 286 static void mptsas_doneq_empty(mptsas_t *mpt); 287 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg); 288 289 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt); 290 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 291 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt); 292 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 293 294 295 static void mptsas_start_watch_reset_delay(); 296 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt); 297 static void mptsas_watch_reset_delay(void *arg); 298 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt); 299 300 /* 301 * helper functions 302 */ 303 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 304 305 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name); 306 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy); 307 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, 308 int lun); 309 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr, 310 int lun); 311 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy); 312 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn); 313 314 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, 315 int *lun); 316 static int mptsas_parse_smp_name(char *name, uint64_t *wwn); 317 318 static mptsas_target_t *mptsas_phy_to_tgt(dev_info_t *pdip, uint8_t phy); 319 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, int port, 320 uint64_t wwid); 321 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, int port, 322 uint64_t wwid); 323 324 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, 325 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd); 326 327 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 328 uint16_t *handle, mptsas_target_t **pptgt); 329 static void mptsas_update_phymask(mptsas_t *mpt); 330 331 /* 332 * Enumeration / DR functions 333 */ 334 static void mptsas_config_all(dev_info_t *pdip); 335 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 336 dev_info_t **lundip); 337 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 338 dev_info_t **lundip); 339 340 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt); 341 static int mptsas_offline_target(dev_info_t *pdip, char *name); 342 343 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target, 344 dev_info_t **dip); 345 346 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt); 347 static int mptsas_probe_lun(dev_info_t *pdip, int lun, 348 dev_info_t **dip, mptsas_target_t *ptgt); 349 350 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 351 dev_info_t **dip, mptsas_target_t *ptgt, int lun); 352 353 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 354 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun); 355 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 356 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, 357 int lun); 358 359 static void mptsas_offline_missed_luns(dev_info_t *pdip, 360 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt); 361 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 362 mdi_pathinfo_t *rpip, uint_t flags); 363 364 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, 365 dev_info_t **smp_dip); 366 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 367 uint_t flags); 368 369 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, 370 int mode, int *rval); 371 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, 372 int mode, int *rval); 373 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, 374 int mode, int *rval); 375 static void mptsas_record_event(void *args); 376 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, 377 int mode); 378 379 static void mptsas_hash_init(mptsas_hash_table_t *hashtab); 380 static void mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen); 381 static void mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data); 382 static void * mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1, 383 mptsas_phymask_t key2); 384 static void * mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1, 385 mptsas_phymask_t key2); 386 static void * mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos); 387 388 mptsas_target_t *mptsas_tgt_alloc(mptsas_hash_table_t *, uint16_t, uint64_t, 389 uint32_t, mptsas_phymask_t, uint8_t); 390 static mptsas_smp_t *mptsas_smp_alloc(mptsas_hash_table_t *hashtab, 391 mptsas_smp_t *data); 392 static void mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid, 393 mptsas_phymask_t phymask); 394 static void mptsas_tgt_free(mptsas_hash_table_t *, uint64_t, mptsas_phymask_t); 395 static void * mptsas_search_by_devhdl(mptsas_hash_table_t *, uint16_t); 396 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 397 dev_info_t **smp_dip); 398 399 /* 400 * Power management functions 401 */ 402 static void mptsas_idle_pm(void *arg); 403 static int mptsas_init_pm(mptsas_t *mpt); 404 405 /* 406 * MPT MSI tunable: 407 * 408 * By default MSI is enabled on all supported platforms. 409 */ 410 boolean_t mptsas_enable_msi = B_TRUE; 411 412 static int mptsas_add_intrs(mptsas_t *, int); 413 static void mptsas_rem_intrs(mptsas_t *); 414 415 /* 416 * FMA Prototypes 417 */ 418 static void mptsas_fm_init(mptsas_t *mpt); 419 static void mptsas_fm_fini(mptsas_t *mpt); 420 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *); 421 422 extern pri_t minclsyspri, maxclsyspri; 423 424 /* 425 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is 426 * under this device that the paths to a physical device are created when 427 * MPxIO is used. 428 */ 429 extern dev_info_t *scsi_vhci_dip; 430 431 /* 432 * Tunable timeout value for Inquiry VPD page 0x83 433 * By default the value is 30 seconds. 434 */ 435 int mptsas_inq83_retry_timeout = 30; 436 437 /* 438 * This is used to allocate memory for message frame storage, not for 439 * data I/O DMA. All message frames must be stored in the first 4G of 440 * physical memory. 441 */ 442 ddi_dma_attr_t mptsas_dma_attrs = { 443 DMA_ATTR_V0, /* attribute layout version */ 444 0x0ull, /* address low - should be 0 (longlong) */ 445 0xffffffffull, /* address high - 32-bit max range */ 446 0x00ffffffull, /* count max - max DMA object size */ 447 4, /* allocation alignment requirements */ 448 0x78, /* burstsizes - binary encoded values */ 449 1, /* minxfer - gran. of DMA engine */ 450 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 451 0xffffffffull, /* max segment size (DMA boundary) */ 452 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 453 512, /* granularity - device transfer size */ 454 0 /* flags, set to 0 */ 455 }; 456 457 /* 458 * This is used for data I/O DMA memory allocation. (full 64-bit DMA 459 * physical addresses are supported.) 460 */ 461 ddi_dma_attr_t mptsas_dma_attrs64 = { 462 DMA_ATTR_V0, /* attribute layout version */ 463 0x0ull, /* address low - should be 0 (longlong) */ 464 0xffffffffffffffffull, /* address high - 64-bit max */ 465 0x00ffffffull, /* count max - max DMA object size */ 466 4, /* allocation alignment requirements */ 467 0x78, /* burstsizes - binary encoded values */ 468 1, /* minxfer - gran. of DMA engine */ 469 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 470 0xffffffffull, /* max segment size (DMA boundary) */ 471 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 472 512, /* granularity - device transfer size */ 473 DDI_DMA_RELAXED_ORDERING /* flags, enable relaxed ordering */ 474 }; 475 476 ddi_device_acc_attr_t mptsas_dev_attr = { 477 DDI_DEVICE_ATTR_V1, 478 DDI_STRUCTURE_LE_ACC, 479 DDI_STRICTORDER_ACC, 480 DDI_DEFAULT_ACC 481 }; 482 483 static struct cb_ops mptsas_cb_ops = { 484 scsi_hba_open, /* open */ 485 scsi_hba_close, /* close */ 486 nodev, /* strategy */ 487 nodev, /* print */ 488 nodev, /* dump */ 489 nodev, /* read */ 490 nodev, /* write */ 491 mptsas_ioctl, /* ioctl */ 492 nodev, /* devmap */ 493 nodev, /* mmap */ 494 nodev, /* segmap */ 495 nochpoll, /* chpoll */ 496 ddi_prop_op, /* cb_prop_op */ 497 NULL, /* streamtab */ 498 D_MP, /* cb_flag */ 499 CB_REV, /* rev */ 500 nodev, /* aread */ 501 nodev /* awrite */ 502 }; 503 504 static struct dev_ops mptsas_ops = { 505 DEVO_REV, /* devo_rev, */ 506 0, /* refcnt */ 507 ddi_no_info, /* info */ 508 nulldev, /* identify */ 509 nulldev, /* probe */ 510 mptsas_attach, /* attach */ 511 mptsas_detach, /* detach */ 512 #ifdef __sparc 513 mptsas_reset, 514 #else 515 nodev, /* reset */ 516 #endif /* __sparc */ 517 &mptsas_cb_ops, /* driver operations */ 518 NULL, /* bus operations */ 519 mptsas_power, /* power management */ 520 #ifdef __sparc 521 ddi_quiesce_not_needed 522 #else 523 mptsas_quiesce /* quiesce */ 524 #endif /* __sparc */ 525 }; 526 527 528 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.23" 529 530 static struct modldrv modldrv = { 531 &mod_driverops, /* Type of module. This one is a driver */ 532 MPTSAS_MOD_STRING, /* Name of the module. */ 533 &mptsas_ops, /* driver ops */ 534 }; 535 536 static struct modlinkage modlinkage = { 537 MODREV_1, &modldrv, NULL 538 }; 539 #define TARGET_PROP "target" 540 #define LUN_PROP "lun" 541 #define SAS_PROP "sas-mpt" 542 #define MDI_GUID "wwn" 543 #define NDI_GUID "guid" 544 #define MPTSAS_DEV_GONE "mptsas_dev_gone" 545 546 /* 547 * Local static data 548 */ 549 #if defined(MPTSAS_DEBUG) 550 uint32_t mptsas_debug_flags = 0; 551 #endif /* defined(MPTSAS_DEBUG) */ 552 uint32_t mptsas_debug_resets = 0; 553 554 static kmutex_t mptsas_global_mutex; 555 static void *mptsas_state; /* soft state ptr */ 556 static krwlock_t mptsas_global_rwlock; 557 558 static kmutex_t mptsas_log_mutex; 559 static char mptsas_log_buf[256]; 560 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf)) 561 562 static mptsas_t *mptsas_head, *mptsas_tail; 563 static clock_t mptsas_scsi_watchdog_tick; 564 static clock_t mptsas_tick; 565 static timeout_id_t mptsas_reset_watch; 566 static timeout_id_t mptsas_timeout_id; 567 static int mptsas_timeouts_enabled = 0; 568 569 /* 570 * warlock directives 571 */ 572 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \ 573 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status)) 574 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt)) 575 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address)) 576 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private)) 577 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private)) 578 579 #ifdef MPTSAS_DEBUG 580 void debug_enter(char *); 581 #endif 582 583 /* 584 * Notes: 585 * - scsi_hba_init(9F) initializes SCSI HBA modules 586 * - must call scsi_hba_fini(9F) if modload() fails 587 */ 588 int 589 _init(void) 590 { 591 int status; 592 /* CONSTCOND */ 593 ASSERT(NO_COMPETING_THREADS); 594 595 NDBG0(("_init")); 596 597 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE, 598 MPTSAS_INITIAL_SOFT_SPACE); 599 if (status != 0) { 600 return (status); 601 } 602 603 if ((status = scsi_hba_init(&modlinkage)) != 0) { 604 ddi_soft_state_fini(&mptsas_state); 605 return (status); 606 } 607 608 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL); 609 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL); 610 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL); 611 612 if ((status = mod_install(&modlinkage)) != 0) { 613 mutex_destroy(&mptsas_log_mutex); 614 rw_destroy(&mptsas_global_rwlock); 615 mutex_destroy(&mptsas_global_mutex); 616 ddi_soft_state_fini(&mptsas_state); 617 scsi_hba_fini(&modlinkage); 618 } 619 620 return (status); 621 } 622 623 /* 624 * Notes: 625 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules 626 */ 627 int 628 _fini(void) 629 { 630 int status; 631 /* CONSTCOND */ 632 ASSERT(NO_COMPETING_THREADS); 633 634 NDBG0(("_fini")); 635 636 if ((status = mod_remove(&modlinkage)) == 0) { 637 ddi_soft_state_fini(&mptsas_state); 638 scsi_hba_fini(&modlinkage); 639 mutex_destroy(&mptsas_global_mutex); 640 rw_destroy(&mptsas_global_rwlock); 641 mutex_destroy(&mptsas_log_mutex); 642 } 643 return (status); 644 } 645 646 /* 647 * The loadable-module _info(9E) entry point 648 */ 649 int 650 _info(struct modinfo *modinfop) 651 { 652 /* CONSTCOND */ 653 ASSERT(NO_COMPETING_THREADS); 654 NDBG0(("mptsas _info")); 655 656 return (mod_info(&modlinkage, modinfop)); 657 } 658 659 660 static int 661 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 662 { 663 dev_info_t *pdip; 664 mptsas_t *mpt; 665 scsi_hba_tran_t *hba_tran; 666 char *iport = NULL; 667 char phymask[MPTSAS_MAX_PHYS]; 668 mptsas_phymask_t phy_mask = 0; 669 int physport = -1; 670 int dynamic_port = 0; 671 uint32_t page_address; 672 char initiator_wwnstr[MPTSAS_WWN_STRLEN]; 673 int rval = DDI_FAILURE; 674 int i = 0; 675 uint64_t wwid = 0; 676 uint8_t portwidth = 0; 677 678 /* CONSTCOND */ 679 ASSERT(NO_COMPETING_THREADS); 680 681 switch (cmd) { 682 case DDI_ATTACH: 683 break; 684 685 case DDI_RESUME: 686 /* 687 * If this a scsi-iport node, nothing to do here. 688 */ 689 return (DDI_SUCCESS); 690 691 default: 692 return (DDI_FAILURE); 693 } 694 695 pdip = ddi_get_parent(dip); 696 697 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) == 698 NULL) { 699 cmn_err(CE_WARN, "Failed attach iport because fail to " 700 "get tran vector for the HBA node"); 701 return (DDI_FAILURE); 702 } 703 704 mpt = TRAN2MPT(hba_tran); 705 ASSERT(mpt != NULL); 706 if (mpt == NULL) 707 return (DDI_FAILURE); 708 709 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == 710 NULL) { 711 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to " 712 "get tran vector for the iport node"); 713 return (DDI_FAILURE); 714 } 715 716 /* 717 * Overwrite parent's tran_hba_private to iport's tran vector 718 */ 719 hba_tran->tran_hba_private = mpt; 720 721 ddi_report_dev(dip); 722 723 /* 724 * Get SAS address for initiator port according dev_handle 725 */ 726 iport = ddi_get_name_addr(dip); 727 if (iport && strncmp(iport, "v0", 2) == 0) { 728 return (DDI_SUCCESS); 729 } 730 731 mutex_enter(&mpt->m_mutex); 732 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 733 bzero(phymask, sizeof (phymask)); 734 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask); 735 if (strcmp(phymask, iport) == 0) { 736 break; 737 } 738 } 739 740 if (i == MPTSAS_MAX_PHYS) { 741 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port" 742 "seems not exist", iport); 743 mutex_exit(&mpt->m_mutex); 744 return (DDI_FAILURE); 745 } 746 747 phy_mask = mpt->m_phy_info[i].phy_mask; 748 physport = mpt->m_phy_info[i].port_num; 749 750 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION) 751 dynamic_port = 1; 752 else 753 dynamic_port = 0; 754 755 page_address = (MPI2_SASPORT_PGAD_FORM_PORT_NUM | 756 (MPI2_SASPORT_PGAD_PORTNUMBER_MASK & physport)); 757 758 rval = mptsas_get_sas_port_page0(mpt, page_address, &wwid, &portwidth); 759 if (rval != DDI_SUCCESS) { 760 mptsas_log(mpt, CE_WARN, "Failed attach port %s because get" 761 "SAS address of initiator failed!", iport); 762 mutex_exit(&mpt->m_mutex); 763 return (DDI_FAILURE); 764 } 765 mutex_exit(&mpt->m_mutex); 766 767 bzero(initiator_wwnstr, sizeof (initiator_wwnstr)); 768 (void) sprintf(initiator_wwnstr, "%016"PRIx64, 769 wwid); 770 771 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 772 "initiator-port", initiator_wwnstr) != 773 DDI_PROP_SUCCESS) { 774 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "initiator-port"); 775 return (DDI_FAILURE); 776 } 777 778 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 779 "phymask", phy_mask) != 780 DDI_PROP_SUCCESS) { 781 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask"); 782 return (DDI_FAILURE); 783 } 784 785 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 786 "dynamic-port", dynamic_port) != 787 DDI_PROP_SUCCESS) { 788 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port"); 789 return (DDI_FAILURE); 790 } 791 /* 792 * register sas hba iport with mdi (MPxIO/vhci) 793 */ 794 if (mdi_phci_register(MDI_HCI_CLASS_SCSI, 795 dip, 0) == MDI_SUCCESS) { 796 mpt->m_mpxio_enable = TRUE; 797 } 798 return (DDI_SUCCESS); 799 } 800 801 /* 802 * Notes: 803 * Set up all device state and allocate data structures, 804 * mutexes, condition variables, etc. for device operation. 805 * Add interrupts needed. 806 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE. 807 */ 808 static int 809 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 810 { 811 mptsas_t *mpt = NULL; 812 int instance, i, j; 813 int doneq_thread_num; 814 char buf[64]; 815 char intr_added = 0; 816 char map_setup = 0; 817 char config_setup = 0; 818 char hba_attach_setup = 0; 819 char smp_attach_setup = 0; 820 char mutex_init_done = 0; 821 char event_taskq_create = 0; 822 char dr_taskq_create = 0; 823 char doneq_thread_create = 0; 824 scsi_hba_tran_t *hba_tran; 825 int intr_types; 826 uint_t mem_bar = MEM_SPACE; 827 mptsas_phymask_t mask = 0x0; 828 int tran_flags = 0; 829 int rval = DDI_FAILURE; 830 831 /* CONSTCOND */ 832 ASSERT(NO_COMPETING_THREADS); 833 834 if (scsi_hba_iport_unit_address(dip)) { 835 return (mptsas_iport_attach(dip, cmd)); 836 } 837 838 switch (cmd) { 839 case DDI_ATTACH: 840 break; 841 842 case DDI_RESUME: 843 if ((hba_tran = ddi_get_driver_private(dip)) == NULL) 844 return (DDI_FAILURE); 845 846 mpt = TRAN2MPT(hba_tran); 847 848 if (!mpt) { 849 return (DDI_FAILURE); 850 } 851 852 /* 853 * Reset hardware and softc to "no outstanding commands" 854 * Note that a check condition can result on first command 855 * to a target. 856 */ 857 mutex_enter(&mpt->m_mutex); 858 859 /* 860 * raise power. 861 */ 862 if (mpt->m_options & MPTSAS_OPT_PM) { 863 mutex_exit(&mpt->m_mutex); 864 (void) pm_busy_component(dip, 0); 865 if (mpt->m_power_level != PM_LEVEL_D0) { 866 rval = pm_raise_power(dip, 0, PM_LEVEL_D0); 867 } else { 868 rval = pm_power_has_changed(dip, 0, 869 PM_LEVEL_D0); 870 } 871 if (rval == DDI_SUCCESS) { 872 mutex_enter(&mpt->m_mutex); 873 } else { 874 /* 875 * The pm_raise_power() call above failed, 876 * and that can only occur if we were unable 877 * to reset the hardware. This is probably 878 * due to unhealty hardware, and because 879 * important filesystems(such as the root 880 * filesystem) could be on the attached disks, 881 * it would not be a good idea to continue, 882 * as we won't be entirely certain we are 883 * writing correct data. So we panic() here 884 * to not only prevent possible data corruption, 885 * but to give developers or end users a hope 886 * of identifying and correcting any problems. 887 */ 888 fm_panic("mptsas could not reset hardware " 889 "during resume"); 890 } 891 } 892 893 mpt->m_suspended = 0; 894 895 /* 896 * Reinitialize ioc 897 */ 898 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 899 mutex_exit(&mpt->m_mutex); 900 if (mpt->m_options & MPTSAS_OPT_PM) { 901 (void) pm_idle_component(dip, 0); 902 } 903 fm_panic("mptsas init chip fail during resume"); 904 } 905 /* 906 * mptsas_update_driver_data needs interrupts so enable them 907 * first. 908 */ 909 MPTSAS_ENABLE_INTR(mpt); 910 mptsas_update_driver_data(mpt); 911 912 /* start requests, if possible */ 913 mptsas_restart_hba(mpt); 914 915 mutex_exit(&mpt->m_mutex); 916 917 /* 918 * Restart watch thread 919 */ 920 mutex_enter(&mptsas_global_mutex); 921 if (mptsas_timeout_id == 0) { 922 mptsas_timeout_id = timeout(mptsas_watch, NULL, 923 mptsas_tick); 924 mptsas_timeouts_enabled = 1; 925 } 926 mutex_exit(&mptsas_global_mutex); 927 928 /* report idle status to pm framework */ 929 if (mpt->m_options & MPTSAS_OPT_PM) { 930 (void) pm_idle_component(dip, 0); 931 } 932 933 return (DDI_SUCCESS); 934 935 default: 936 return (DDI_FAILURE); 937 938 } 939 940 instance = ddi_get_instance(dip); 941 942 /* 943 * Allocate softc information. 944 */ 945 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) { 946 mptsas_log(NULL, CE_WARN, 947 "mptsas%d: cannot allocate soft state", instance); 948 goto fail; 949 } 950 951 mpt = ddi_get_soft_state(mptsas_state, instance); 952 953 if (mpt == NULL) { 954 mptsas_log(NULL, CE_WARN, 955 "mptsas%d: cannot get soft state", instance); 956 goto fail; 957 } 958 959 /* Allocate a transport structure */ 960 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(dip, SCSI_HBA_CANSLEEP); 961 ASSERT(mpt->m_tran != NULL); 962 963 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */ 964 scsi_size_clean(dip); 965 966 mpt->m_dip = dip; 967 mpt->m_instance = instance; 968 969 /* Make a per-instance copy of the structures */ 970 mpt->m_io_dma_attr = mptsas_dma_attrs64; 971 mpt->m_msg_dma_attr = mptsas_dma_attrs; 972 mpt->m_reg_acc_attr = mptsas_dev_attr; 973 mpt->m_dev_acc_attr = mptsas_dev_attr; 974 975 /* 976 * Initialize FMA 977 */ 978 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip, 979 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 980 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 981 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 982 983 mptsas_fm_init(mpt); 984 985 if (pci_config_setup(mpt->m_dip, 986 &mpt->m_config_handle) != DDI_SUCCESS) { 987 mptsas_log(mpt, CE_WARN, "cannot map configuration space."); 988 goto fail; 989 } 990 config_setup++; 991 992 if (mptsas_alloc_handshake_msg(mpt, 993 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) { 994 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg."); 995 goto fail; 996 } 997 998 /* 999 * This is a workaround for a XMITS ASIC bug which does not 1000 * drive the CBE upper bits. 1001 */ 1002 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) & 1003 PCI_STAT_PERROR) { 1004 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT, 1005 PCI_STAT_PERROR); 1006 } 1007 1008 /* 1009 * Setup configuration space 1010 */ 1011 if (mptsas_config_space_init(mpt) == FALSE) { 1012 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed"); 1013 goto fail; 1014 } 1015 1016 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg, 1017 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) { 1018 mptsas_log(mpt, CE_WARN, "map setup failed"); 1019 goto fail; 1020 } 1021 map_setup++; 1022 1023 /* 1024 * A taskq is created for dealing with the event handler 1025 */ 1026 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq", 1027 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1028 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed"); 1029 goto fail; 1030 } 1031 event_taskq_create++; 1032 1033 /* 1034 * A taskq is created for dealing with dr events 1035 */ 1036 if ((mpt->m_dr_taskq = ddi_taskq_create(dip, 1037 "mptsas_dr_taskq", 1038 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1039 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery " 1040 "failed"); 1041 goto fail; 1042 } 1043 dr_taskq_create++; 1044 1045 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1046 0, "mptsas_doneq_thread_threshold_prop", 10); 1047 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1048 0, "mptsas_doneq_length_threshold_prop", 8); 1049 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1050 0, "mptsas_doneq_thread_n_prop", 8); 1051 1052 if (mpt->m_doneq_thread_n) { 1053 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL); 1054 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL); 1055 1056 mutex_enter(&mpt->m_doneq_mutex); 1057 mpt->m_doneq_thread_id = 1058 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t) 1059 * mpt->m_doneq_thread_n, KM_SLEEP); 1060 1061 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1062 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL, 1063 CV_DRIVER, NULL); 1064 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL, 1065 MUTEX_DRIVER, NULL); 1066 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1067 mpt->m_doneq_thread_id[j].flag |= 1068 MPTSAS_DONEQ_THREAD_ACTIVE; 1069 mpt->m_doneq_thread_id[j].arg.mpt = mpt; 1070 mpt->m_doneq_thread_id[j].arg.t = j; 1071 mpt->m_doneq_thread_id[j].threadp = 1072 thread_create(NULL, 0, mptsas_doneq_thread, 1073 &mpt->m_doneq_thread_id[j].arg, 1074 0, &p0, TS_RUN, minclsyspri); 1075 mpt->m_doneq_thread_id[j].donetail = 1076 &mpt->m_doneq_thread_id[j].doneq; 1077 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1078 } 1079 mutex_exit(&mpt->m_doneq_mutex); 1080 doneq_thread_create++; 1081 } 1082 1083 /* Get supported interrupt types */ 1084 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 1085 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types " 1086 "failed\n"); 1087 goto fail; 1088 } 1089 1090 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types)); 1091 1092 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) { 1093 /* 1094 * Try MSI, but fall back to FIXED 1095 */ 1096 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) { 1097 NDBG0(("Using MSI interrupt type")); 1098 mpt->m_intr_type = DDI_INTR_TYPE_MSI; 1099 goto intr_done; 1100 } 1101 } 1102 1103 if (intr_types & DDI_INTR_TYPE_FIXED) { 1104 1105 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) { 1106 NDBG0(("Using FIXED interrupt type")); 1107 mpt->m_intr_type = DDI_INTR_TYPE_FIXED; 1108 1109 goto intr_done; 1110 } 1111 1112 NDBG0(("FIXED interrupt registration failed")); 1113 } 1114 1115 goto fail; 1116 1117 intr_done: 1118 intr_added++; 1119 1120 /* Initialize mutex used in interrupt handler */ 1121 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, 1122 DDI_INTR_PRI(mpt->m_intr_pri)); 1123 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER, 1124 DDI_INTR_PRI(mpt->m_intr_pri)); 1125 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL); 1126 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL); 1127 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL); 1128 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL); 1129 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL); 1130 mutex_init_done++; 1131 1132 /* 1133 * Disable hardware interrupt since we're not ready to 1134 * handle it yet. 1135 */ 1136 MPTSAS_DISABLE_INTR(mpt); 1137 1138 /* 1139 * Enable interrupts 1140 */ 1141 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 1142 /* Call ddi_intr_block_enable() for MSI interrupts */ 1143 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt); 1144 } else { 1145 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 1146 for (i = 0; i < mpt->m_intr_cnt; i++) { 1147 (void) ddi_intr_enable(mpt->m_htable[i]); 1148 } 1149 } 1150 1151 mutex_enter(&mpt->m_mutex); 1152 /* 1153 * Initialize power management component 1154 */ 1155 if (mpt->m_options & MPTSAS_OPT_PM) { 1156 if (mptsas_init_pm(mpt)) { 1157 mutex_exit(&mpt->m_mutex); 1158 mptsas_log(mpt, CE_WARN, "mptsas pm initialization " 1159 "failed"); 1160 goto fail; 1161 } 1162 } 1163 1164 /* 1165 * Initialize chip 1166 */ 1167 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) { 1168 mutex_exit(&mpt->m_mutex); 1169 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed"); 1170 goto fail; 1171 } 1172 mutex_exit(&mpt->m_mutex); 1173 1174 /* 1175 * initialize SCSI HBA transport structure 1176 */ 1177 hba_tran->tran_hba_private = mpt; 1178 hba_tran->tran_tgt_private = NULL; 1179 1180 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init; 1181 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free; 1182 1183 hba_tran->tran_start = mptsas_scsi_start; 1184 hba_tran->tran_reset = mptsas_scsi_reset; 1185 hba_tran->tran_abort = mptsas_scsi_abort; 1186 hba_tran->tran_getcap = mptsas_scsi_getcap; 1187 hba_tran->tran_setcap = mptsas_scsi_setcap; 1188 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt; 1189 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt; 1190 1191 hba_tran->tran_dmafree = mptsas_scsi_dmafree; 1192 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt; 1193 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify; 1194 1195 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr; 1196 hba_tran->tran_get_name = mptsas_get_name; 1197 1198 hba_tran->tran_quiesce = mptsas_scsi_quiesce; 1199 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce; 1200 hba_tran->tran_bus_reset = NULL; 1201 1202 hba_tran->tran_add_eventcall = NULL; 1203 hba_tran->tran_get_eventcookie = NULL; 1204 hba_tran->tran_post_event = NULL; 1205 hba_tran->tran_remove_eventcall = NULL; 1206 1207 hba_tran->tran_bus_config = mptsas_bus_config; 1208 1209 hba_tran->tran_interconnect_type = INTERCONNECT_SAS; 1210 1211 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) { 1212 goto fail; 1213 } 1214 1215 /* 1216 * Register the iport for multiple port HBA 1217 */ 1218 /* 1219 * initial value of mask is 0 1220 */ 1221 mutex_enter(&mpt->m_mutex); 1222 for (i = 0; i < mpt->m_num_phys; i++) { 1223 mptsas_phymask_t phy_mask = 0x0; 1224 char phy_mask_name[MPTSAS_MAX_PHYS]; 1225 uint8_t current_port; 1226 1227 if (mpt->m_phy_info[i].attached_devhdl == 0) 1228 continue; 1229 1230 bzero(phy_mask_name, sizeof (phy_mask_name)); 1231 1232 current_port = mpt->m_phy_info[i].port_num; 1233 1234 if ((mask & (1 << i)) != 0) 1235 continue; 1236 1237 for (j = 0; j < mpt->m_num_phys; j++) { 1238 if (mpt->m_phy_info[j].attached_devhdl && 1239 (mpt->m_phy_info[j].port_num == current_port)) { 1240 phy_mask |= (1 << j); 1241 } 1242 } 1243 mask = mask | phy_mask; 1244 1245 for (j = 0; j < mpt->m_num_phys; j++) { 1246 if ((phy_mask >> j) & 0x01) { 1247 mpt->m_phy_info[j].phy_mask = phy_mask; 1248 } 1249 } 1250 1251 (void) sprintf(phy_mask_name, "%x", phy_mask); 1252 1253 mutex_exit(&mpt->m_mutex); 1254 /* 1255 * register a iport 1256 */ 1257 (void) scsi_hba_iport_register(dip, phy_mask_name); 1258 mutex_enter(&mpt->m_mutex); 1259 } 1260 mutex_exit(&mpt->m_mutex); 1261 /* 1262 * register a virtual port for RAID volume always 1263 */ 1264 (void) scsi_hba_iport_register(dip, "v0"); 1265 /* 1266 * All children of the HBA are iports. We need tran was cloned. 1267 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be 1268 * inherited to iport's tran vector. 1269 */ 1270 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE); 1271 1272 if (scsi_hba_attach_setup(dip, &mpt->m_msg_dma_attr, 1273 hba_tran, tran_flags) != DDI_SUCCESS) { 1274 mptsas_log(mpt, CE_WARN, "hba attach setup failed"); 1275 goto fail; 1276 } 1277 hba_attach_setup++; 1278 1279 mpt->m_smptran = smp_hba_tran_alloc(dip); 1280 ASSERT(mpt->m_smptran != NULL); 1281 mpt->m_smptran->smp_tran_hba_private = mpt; 1282 mpt->m_smptran->smp_tran_start = mptsas_smp_start; 1283 if (smp_hba_attach_setup(dip, mpt->m_smptran) != DDI_SUCCESS) { 1284 mptsas_log(mpt, CE_WARN, "smp attach setup failed"); 1285 goto fail; 1286 } 1287 smp_attach_setup++; 1288 1289 /* 1290 * Initialize smp hash table 1291 */ 1292 mptsas_hash_init(&mpt->m_active->m_smptbl); 1293 mpt->m_smp_devhdl = 0xFFFF; 1294 1295 /* 1296 * create kmem cache for packets 1297 */ 1298 (void) sprintf(buf, "mptsas%d_cache", instance); 1299 mpt->m_kmem_cache = kmem_cache_create(buf, 1300 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8, 1301 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor, 1302 NULL, (void *)mpt, NULL, 0); 1303 1304 if (mpt->m_kmem_cache == NULL) { 1305 mptsas_log(mpt, CE_WARN, "creating kmem cache failed"); 1306 goto fail; 1307 } 1308 1309 /* 1310 * create kmem cache for extra SGL frames if SGL cannot 1311 * be accomodated into main request frame. 1312 */ 1313 (void) sprintf(buf, "mptsas%d_cache_frames", instance); 1314 mpt->m_cache_frames = kmem_cache_create(buf, 1315 sizeof (mptsas_cache_frames_t), 8, 1316 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor, 1317 NULL, (void *)mpt, NULL, 0); 1318 1319 if (mpt->m_cache_frames == NULL) { 1320 mptsas_log(mpt, CE_WARN, "creating cache for frames failed"); 1321 goto fail; 1322 } 1323 1324 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 1325 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY); 1326 if (mpt->m_scsi_reset_delay == 0) { 1327 mptsas_log(mpt, CE_NOTE, 1328 "scsi_reset_delay of 0 is not recommended," 1329 " resetting to SCSI_DEFAULT_RESET_DELAY\n"); 1330 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY; 1331 } 1332 1333 /* 1334 * Initialize the wait and done FIFO queue 1335 */ 1336 mpt->m_donetail = &mpt->m_doneq; 1337 mpt->m_waitqtail = &mpt->m_waitq; 1338 1339 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 1340 mpt->m_tx_draining = 0; 1341 1342 /* 1343 * ioc cmd queue initialize 1344 */ 1345 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq; 1346 1347 mpt->m_dev_handle = 0xFFFF; 1348 1349 MPTSAS_ENABLE_INTR(mpt); 1350 1351 /* 1352 * enable event notification 1353 */ 1354 mutex_enter(&mpt->m_mutex); 1355 if (mptsas_ioc_enable_event_notification(mpt)) { 1356 mutex_exit(&mpt->m_mutex); 1357 goto fail; 1358 } 1359 mutex_exit(&mpt->m_mutex); 1360 1361 1362 /* Check all dma handles allocated in attach */ 1363 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) 1364 != DDI_SUCCESS) || 1365 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) 1366 != DDI_SUCCESS) || 1367 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) 1368 != DDI_SUCCESS) || 1369 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) 1370 != DDI_SUCCESS) || 1371 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) 1372 != DDI_SUCCESS)) { 1373 goto fail; 1374 } 1375 1376 /* Check all acc handles allocated in attach */ 1377 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 1378 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) 1379 != DDI_SUCCESS) || 1380 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) 1381 != DDI_SUCCESS) || 1382 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) 1383 != DDI_SUCCESS) || 1384 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) 1385 != DDI_SUCCESS) || 1386 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) 1387 != DDI_SUCCESS) || 1388 (mptsas_check_acc_handle(mpt->m_config_handle) 1389 != DDI_SUCCESS)) { 1390 goto fail; 1391 } 1392 1393 /* 1394 * After this point, we are not going to fail the attach. 1395 */ 1396 /* 1397 * used for mptsas_watch 1398 */ 1399 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1400 if (mptsas_head == NULL) { 1401 mptsas_head = mpt; 1402 } else { 1403 mptsas_tail->m_next = mpt; 1404 } 1405 mptsas_tail = mpt; 1406 rw_exit(&mptsas_global_rwlock); 1407 1408 mutex_enter(&mptsas_global_mutex); 1409 if (mptsas_timeouts_enabled == 0) { 1410 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY, 1411 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK); 1412 1413 mptsas_tick = mptsas_scsi_watchdog_tick * 1414 drv_usectohz((clock_t)1000000); 1415 1416 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 1417 mptsas_timeouts_enabled = 1; 1418 } 1419 mutex_exit(&mptsas_global_mutex); 1420 1421 /* Print message of HBA present */ 1422 ddi_report_dev(dip); 1423 1424 /* report idle status to pm framework */ 1425 if (mpt->m_options & MPTSAS_OPT_PM) { 1426 (void) pm_idle_component(dip, 0); 1427 } 1428 1429 return (DDI_SUCCESS); 1430 1431 fail: 1432 mptsas_log(mpt, CE_WARN, "attach failed"); 1433 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 1434 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 1435 if (mpt) { 1436 mutex_enter(&mptsas_global_mutex); 1437 1438 if (mptsas_timeout_id && (mptsas_head == NULL)) { 1439 timeout_id_t tid = mptsas_timeout_id; 1440 mptsas_timeouts_enabled = 0; 1441 mptsas_timeout_id = 0; 1442 mutex_exit(&mptsas_global_mutex); 1443 (void) untimeout(tid); 1444 mutex_enter(&mptsas_global_mutex); 1445 } 1446 mutex_exit(&mptsas_global_mutex); 1447 /* deallocate in reverse order */ 1448 if (mpt->m_cache_frames) { 1449 kmem_cache_destroy(mpt->m_cache_frames); 1450 } 1451 if (mpt->m_kmem_cache) { 1452 kmem_cache_destroy(mpt->m_kmem_cache); 1453 } 1454 if (hba_attach_setup) { 1455 (void) scsi_hba_detach(dip); 1456 } 1457 if (smp_attach_setup) { 1458 (void) smp_hba_detach(dip); 1459 } 1460 if (intr_added) { 1461 mptsas_rem_intrs(mpt); 1462 } 1463 if (doneq_thread_create) { 1464 mutex_enter(&mpt->m_doneq_mutex); 1465 doneq_thread_num = mpt->m_doneq_thread_n; 1466 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1467 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1468 mpt->m_doneq_thread_id[j].flag &= 1469 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1470 cv_signal(&mpt->m_doneq_thread_id[j].cv); 1471 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1472 } 1473 while (mpt->m_doneq_thread_n) { 1474 cv_wait(&mpt->m_doneq_thread_cv, 1475 &mpt->m_doneq_mutex); 1476 } 1477 for (j = 0; j < doneq_thread_num; j++) { 1478 cv_destroy(&mpt->m_doneq_thread_id[j].cv); 1479 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex); 1480 } 1481 kmem_free(mpt->m_doneq_thread_id, 1482 sizeof (mptsas_doneq_thread_list_t) 1483 * doneq_thread_num); 1484 mutex_exit(&mpt->m_doneq_mutex); 1485 cv_destroy(&mpt->m_doneq_thread_cv); 1486 mutex_destroy(&mpt->m_doneq_mutex); 1487 } 1488 if (event_taskq_create) { 1489 ddi_taskq_destroy(mpt->m_event_taskq); 1490 } 1491 if (dr_taskq_create) { 1492 ddi_taskq_destroy(mpt->m_dr_taskq); 1493 } 1494 if (mutex_init_done) { 1495 mutex_destroy(&mpt->m_tx_waitq_mutex); 1496 mutex_destroy(&mpt->m_mutex); 1497 cv_destroy(&mpt->m_cv); 1498 cv_destroy(&mpt->m_passthru_cv); 1499 cv_destroy(&mpt->m_fw_cv); 1500 cv_destroy(&mpt->m_config_cv); 1501 cv_destroy(&mpt->m_fw_diag_cv); 1502 } 1503 mptsas_free_handshake_msg(mpt); 1504 mptsas_hba_fini(mpt); 1505 if (map_setup) { 1506 mptsas_cfg_fini(mpt); 1507 } 1508 if (config_setup) { 1509 pci_config_teardown(&mpt->m_config_handle); 1510 } 1511 if (mpt->m_tran) { 1512 scsi_hba_tran_free(mpt->m_tran); 1513 mpt->m_tran = NULL; 1514 } 1515 if (mpt->m_smptran) { 1516 smp_hba_tran_free(mpt->m_smptran); 1517 mpt->m_smptran = NULL; 1518 } 1519 mptsas_fm_fini(mpt); 1520 ddi_soft_state_free(mptsas_state, instance); 1521 ddi_prop_remove_all(dip); 1522 } 1523 return (DDI_FAILURE); 1524 } 1525 1526 static int 1527 mptsas_suspend(dev_info_t *devi) 1528 { 1529 mptsas_t *mpt, *g; 1530 scsi_hba_tran_t *tran; 1531 1532 if (scsi_hba_iport_unit_address(devi)) { 1533 return (DDI_SUCCESS); 1534 } 1535 1536 if ((tran = ddi_get_driver_private(devi)) == NULL) 1537 return (DDI_SUCCESS); 1538 1539 mpt = TRAN2MPT(tran); 1540 if (!mpt) { 1541 return (DDI_SUCCESS); 1542 } 1543 1544 mutex_enter(&mpt->m_mutex); 1545 1546 if (mpt->m_suspended++) { 1547 mutex_exit(&mpt->m_mutex); 1548 return (DDI_SUCCESS); 1549 } 1550 1551 /* 1552 * Cancel timeout threads for this mpt 1553 */ 1554 if (mpt->m_quiesce_timeid) { 1555 timeout_id_t tid = mpt->m_quiesce_timeid; 1556 mpt->m_quiesce_timeid = 0; 1557 mutex_exit(&mpt->m_mutex); 1558 (void) untimeout(tid); 1559 mutex_enter(&mpt->m_mutex); 1560 } 1561 1562 if (mpt->m_restart_cmd_timeid) { 1563 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1564 mpt->m_restart_cmd_timeid = 0; 1565 mutex_exit(&mpt->m_mutex); 1566 (void) untimeout(tid); 1567 mutex_enter(&mpt->m_mutex); 1568 } 1569 1570 if (mpt->m_pm_timeid != 0) { 1571 timeout_id_t tid = mpt->m_pm_timeid; 1572 mpt->m_pm_timeid = 0; 1573 mutex_exit(&mpt->m_mutex); 1574 (void) untimeout(tid); 1575 /* 1576 * Report idle status for last ioctl since 1577 * calls to pm_busy_component(9F) are stacked. 1578 */ 1579 (void) pm_idle_component(mpt->m_dip, 0); 1580 mutex_enter(&mpt->m_mutex); 1581 } 1582 mutex_exit(&mpt->m_mutex); 1583 1584 /* 1585 * Cancel watch threads if all mpts suspended 1586 */ 1587 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1588 for (g = mptsas_head; g != NULL; g = g->m_next) { 1589 if (!g->m_suspended) 1590 break; 1591 } 1592 rw_exit(&mptsas_global_rwlock); 1593 1594 mutex_enter(&mptsas_global_mutex); 1595 if (g == NULL) { 1596 timeout_id_t tid; 1597 1598 mptsas_timeouts_enabled = 0; 1599 if (mptsas_timeout_id) { 1600 tid = mptsas_timeout_id; 1601 mptsas_timeout_id = 0; 1602 mutex_exit(&mptsas_global_mutex); 1603 (void) untimeout(tid); 1604 mutex_enter(&mptsas_global_mutex); 1605 } 1606 if (mptsas_reset_watch) { 1607 tid = mptsas_reset_watch; 1608 mptsas_reset_watch = 0; 1609 mutex_exit(&mptsas_global_mutex); 1610 (void) untimeout(tid); 1611 mutex_enter(&mptsas_global_mutex); 1612 } 1613 } 1614 mutex_exit(&mptsas_global_mutex); 1615 1616 mutex_enter(&mpt->m_mutex); 1617 1618 /* 1619 * If this mpt is not in full power(PM_LEVEL_D0), just return. 1620 */ 1621 if ((mpt->m_options & MPTSAS_OPT_PM) && 1622 (mpt->m_power_level != PM_LEVEL_D0)) { 1623 mutex_exit(&mpt->m_mutex); 1624 return (DDI_SUCCESS); 1625 } 1626 1627 /* Disable HBA interrupts in hardware */ 1628 MPTSAS_DISABLE_INTR(mpt); 1629 /* 1630 * Send RAID action system shutdown to sync IR 1631 */ 1632 mptsas_raid_action_system_shutdown(mpt); 1633 1634 mutex_exit(&mpt->m_mutex); 1635 1636 /* drain the taskq */ 1637 ddi_taskq_wait(mpt->m_event_taskq); 1638 ddi_taskq_wait(mpt->m_dr_taskq); 1639 1640 return (DDI_SUCCESS); 1641 } 1642 1643 #ifdef __sparc 1644 /*ARGSUSED*/ 1645 static int 1646 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd) 1647 { 1648 mptsas_t *mpt; 1649 scsi_hba_tran_t *tran; 1650 1651 /* 1652 * If this call is for iport, just return. 1653 */ 1654 if (scsi_hba_iport_unit_address(devi)) 1655 return (DDI_SUCCESS); 1656 1657 if ((tran = ddi_get_driver_private(devi)) == NULL) 1658 return (DDI_SUCCESS); 1659 1660 if ((mpt = TRAN2MPT(tran)) == NULL) 1661 return (DDI_SUCCESS); 1662 1663 /* 1664 * Send RAID action system shutdown to sync IR. Disable HBA 1665 * interrupts in hardware first. 1666 */ 1667 MPTSAS_DISABLE_INTR(mpt); 1668 mptsas_raid_action_system_shutdown(mpt); 1669 1670 return (DDI_SUCCESS); 1671 } 1672 #else /* __sparc */ 1673 /* 1674 * quiesce(9E) entry point. 1675 * 1676 * This function is called when the system is single-threaded at high 1677 * PIL with preemption disabled. Therefore, this function must not be 1678 * blocked. 1679 * 1680 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 1681 * DDI_FAILURE indicates an error condition and should almost never happen. 1682 */ 1683 static int 1684 mptsas_quiesce(dev_info_t *devi) 1685 { 1686 mptsas_t *mpt; 1687 scsi_hba_tran_t *tran; 1688 1689 /* 1690 * If this call is for iport, just return. 1691 */ 1692 if (scsi_hba_iport_unit_address(devi)) 1693 return (DDI_SUCCESS); 1694 1695 if ((tran = ddi_get_driver_private(devi)) == NULL) 1696 return (DDI_SUCCESS); 1697 1698 if ((mpt = TRAN2MPT(tran)) == NULL) 1699 return (DDI_SUCCESS); 1700 1701 /* Disable HBA interrupts in hardware */ 1702 MPTSAS_DISABLE_INTR(mpt); 1703 /* Send RAID action system shutdonw to sync IR */ 1704 mptsas_raid_action_system_shutdown(mpt); 1705 1706 return (DDI_SUCCESS); 1707 } 1708 #endif /* __sparc */ 1709 1710 /* 1711 * detach(9E). Remove all device allocations and system resources; 1712 * disable device interrupts. 1713 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem. 1714 */ 1715 static int 1716 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 1717 { 1718 /* CONSTCOND */ 1719 ASSERT(NO_COMPETING_THREADS); 1720 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd)); 1721 1722 switch (cmd) { 1723 case DDI_DETACH: 1724 return (mptsas_do_detach(devi)); 1725 1726 case DDI_SUSPEND: 1727 return (mptsas_suspend(devi)); 1728 1729 default: 1730 return (DDI_FAILURE); 1731 } 1732 /* NOTREACHED */ 1733 } 1734 1735 static int 1736 mptsas_do_detach(dev_info_t *dip) 1737 { 1738 mptsas_t *mpt, *m; 1739 scsi_hba_tran_t *tran; 1740 mptsas_slots_t *active; 1741 int circ = 0; 1742 int circ1 = 0; 1743 mdi_pathinfo_t *pip = NULL; 1744 int i; 1745 int doneq_thread_num = 0; 1746 1747 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip)); 1748 1749 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL) 1750 return (DDI_FAILURE); 1751 1752 mpt = TRAN2MPT(tran); 1753 if (!mpt) { 1754 return (DDI_FAILURE); 1755 } 1756 /* 1757 * Still have pathinfo child, should not detach mpt driver 1758 */ 1759 if (scsi_hba_iport_unit_address(dip)) { 1760 if (mpt->m_mpxio_enable) { 1761 /* 1762 * MPxIO enabled for the iport 1763 */ 1764 ndi_devi_enter(scsi_vhci_dip, &circ1); 1765 ndi_devi_enter(dip, &circ); 1766 while (pip = mdi_get_next_client_path(dip, NULL)) { 1767 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) { 1768 continue; 1769 } 1770 ndi_devi_exit(dip, circ); 1771 ndi_devi_exit(scsi_vhci_dip, circ1); 1772 NDBG12(("detach failed because of " 1773 "outstanding path info")); 1774 return (DDI_FAILURE); 1775 } 1776 ndi_devi_exit(dip, circ); 1777 ndi_devi_exit(scsi_vhci_dip, circ1); 1778 (void) mdi_phci_unregister(dip, 0); 1779 } 1780 1781 ddi_prop_remove_all(dip); 1782 1783 return (DDI_SUCCESS); 1784 } 1785 1786 /* Make sure power level is D0 before accessing registers */ 1787 if (mpt->m_options & MPTSAS_OPT_PM) { 1788 (void) pm_busy_component(dip, 0); 1789 if (mpt->m_power_level != PM_LEVEL_D0) { 1790 if (pm_raise_power(dip, 0, PM_LEVEL_D0) != 1791 DDI_SUCCESS) { 1792 mptsas_log(mpt, CE_WARN, 1793 "mptsas%d: Raise power request failed.", 1794 mpt->m_instance); 1795 (void) pm_idle_component(dip, 0); 1796 return (DDI_FAILURE); 1797 } 1798 } 1799 } 1800 1801 mutex_enter(&mpt->m_mutex); 1802 MPTSAS_DISABLE_INTR(mpt); 1803 mutex_exit(&mpt->m_mutex); 1804 mptsas_rem_intrs(mpt); 1805 ddi_taskq_destroy(mpt->m_event_taskq); 1806 ddi_taskq_destroy(mpt->m_dr_taskq); 1807 1808 if (mpt->m_doneq_thread_n) { 1809 mutex_enter(&mpt->m_doneq_mutex); 1810 doneq_thread_num = mpt->m_doneq_thread_n; 1811 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 1812 mutex_enter(&mpt->m_doneq_thread_id[i].mutex); 1813 mpt->m_doneq_thread_id[i].flag &= 1814 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1815 cv_signal(&mpt->m_doneq_thread_id[i].cv); 1816 mutex_exit(&mpt->m_doneq_thread_id[i].mutex); 1817 } 1818 while (mpt->m_doneq_thread_n) { 1819 cv_wait(&mpt->m_doneq_thread_cv, 1820 &mpt->m_doneq_mutex); 1821 } 1822 for (i = 0; i < doneq_thread_num; i++) { 1823 cv_destroy(&mpt->m_doneq_thread_id[i].cv); 1824 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex); 1825 } 1826 kmem_free(mpt->m_doneq_thread_id, 1827 sizeof (mptsas_doneq_thread_list_t) 1828 * doneq_thread_num); 1829 mutex_exit(&mpt->m_doneq_mutex); 1830 cv_destroy(&mpt->m_doneq_thread_cv); 1831 mutex_destroy(&mpt->m_doneq_mutex); 1832 } 1833 1834 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf); 1835 1836 /* 1837 * Remove device instance from the global linked list 1838 */ 1839 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1840 if (mptsas_head == mpt) { 1841 m = mptsas_head = mpt->m_next; 1842 } else { 1843 for (m = mptsas_head; m != NULL; m = m->m_next) { 1844 if (m->m_next == mpt) { 1845 m->m_next = mpt->m_next; 1846 break; 1847 } 1848 } 1849 if (m == NULL) { 1850 mptsas_log(mpt, CE_PANIC, "Not in softc list!"); 1851 } 1852 } 1853 1854 if (mptsas_tail == mpt) { 1855 mptsas_tail = m; 1856 } 1857 rw_exit(&mptsas_global_rwlock); 1858 1859 /* 1860 * Cancel timeout threads for this mpt 1861 */ 1862 mutex_enter(&mpt->m_mutex); 1863 if (mpt->m_quiesce_timeid) { 1864 timeout_id_t tid = mpt->m_quiesce_timeid; 1865 mpt->m_quiesce_timeid = 0; 1866 mutex_exit(&mpt->m_mutex); 1867 (void) untimeout(tid); 1868 mutex_enter(&mpt->m_mutex); 1869 } 1870 1871 if (mpt->m_restart_cmd_timeid) { 1872 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1873 mpt->m_restart_cmd_timeid = 0; 1874 mutex_exit(&mpt->m_mutex); 1875 (void) untimeout(tid); 1876 mutex_enter(&mpt->m_mutex); 1877 } 1878 1879 if (mpt->m_pm_timeid != 0) { 1880 timeout_id_t tid = mpt->m_pm_timeid; 1881 mpt->m_pm_timeid = 0; 1882 mutex_exit(&mpt->m_mutex); 1883 (void) untimeout(tid); 1884 /* 1885 * Report idle status for last ioctl since 1886 * calls to pm_busy_component(9F) are stacked. 1887 */ 1888 (void) pm_idle_component(mpt->m_dip, 0); 1889 mutex_enter(&mpt->m_mutex); 1890 } 1891 mutex_exit(&mpt->m_mutex); 1892 1893 /* 1894 * last mpt? ... if active, CANCEL watch threads. 1895 */ 1896 mutex_enter(&mptsas_global_mutex); 1897 if (mptsas_head == NULL) { 1898 timeout_id_t tid; 1899 /* 1900 * Clear mptsas_timeouts_enable so that the watch thread 1901 * gets restarted on DDI_ATTACH 1902 */ 1903 mptsas_timeouts_enabled = 0; 1904 if (mptsas_timeout_id) { 1905 tid = mptsas_timeout_id; 1906 mptsas_timeout_id = 0; 1907 mutex_exit(&mptsas_global_mutex); 1908 (void) untimeout(tid); 1909 mutex_enter(&mptsas_global_mutex); 1910 } 1911 if (mptsas_reset_watch) { 1912 tid = mptsas_reset_watch; 1913 mptsas_reset_watch = 0; 1914 mutex_exit(&mptsas_global_mutex); 1915 (void) untimeout(tid); 1916 mutex_enter(&mptsas_global_mutex); 1917 } 1918 } 1919 mutex_exit(&mptsas_global_mutex); 1920 1921 /* 1922 * Delete nt_active. 1923 */ 1924 active = mpt->m_active; 1925 mutex_enter(&mpt->m_mutex); 1926 mptsas_hash_uninit(&active->m_smptbl, sizeof (mptsas_smp_t)); 1927 mutex_exit(&mpt->m_mutex); 1928 1929 if (active) { 1930 kmem_free(active, active->m_size); 1931 mpt->m_active = NULL; 1932 } 1933 1934 /* deallocate everything that was allocated in mptsas_attach */ 1935 mptsas_fm_fini(mpt); 1936 kmem_cache_destroy(mpt->m_cache_frames); 1937 kmem_cache_destroy(mpt->m_kmem_cache); 1938 1939 (void) scsi_hba_detach(dip); 1940 (void) smp_hba_detach(dip); 1941 mptsas_free_handshake_msg(mpt); 1942 mptsas_hba_fini(mpt); 1943 mptsas_cfg_fini(mpt); 1944 1945 /* Lower the power informing PM Framework */ 1946 if (mpt->m_options & MPTSAS_OPT_PM) { 1947 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS) 1948 mptsas_log(mpt, CE_WARN, 1949 "!mptsas%d: Lower power request failed " 1950 "during detach, ignoring.", 1951 mpt->m_instance); 1952 } 1953 1954 mutex_destroy(&mpt->m_tx_waitq_mutex); 1955 mutex_destroy(&mpt->m_mutex); 1956 cv_destroy(&mpt->m_cv); 1957 cv_destroy(&mpt->m_passthru_cv); 1958 cv_destroy(&mpt->m_fw_cv); 1959 cv_destroy(&mpt->m_config_cv); 1960 cv_destroy(&mpt->m_fw_diag_cv); 1961 1962 pci_config_teardown(&mpt->m_config_handle); 1963 if (mpt->m_tran) { 1964 scsi_hba_tran_free(mpt->m_tran); 1965 mpt->m_tran = NULL; 1966 } 1967 1968 if (mpt->m_smptran) { 1969 smp_hba_tran_free(mpt->m_smptran); 1970 mpt->m_smptran = NULL; 1971 } 1972 1973 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip)); 1974 ddi_prop_remove_all(dip); 1975 1976 return (DDI_SUCCESS); 1977 } 1978 1979 static int 1980 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size) 1981 { 1982 ddi_dma_attr_t task_dma_attrs; 1983 ddi_dma_cookie_t tmp_dma_cookie; 1984 size_t alloc_len; 1985 uint_t ncookie; 1986 1987 /* allocate Task Management ddi_dma resources */ 1988 task_dma_attrs = mpt->m_msg_dma_attr; 1989 task_dma_attrs.dma_attr_sgllen = 1; 1990 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size); 1991 1992 if (ddi_dma_alloc_handle(mpt->m_dip, &task_dma_attrs, 1993 DDI_DMA_SLEEP, NULL, &mpt->m_hshk_dma_hdl) != DDI_SUCCESS) { 1994 mpt->m_hshk_dma_hdl = NULL; 1995 return (DDI_FAILURE); 1996 } 1997 1998 if (ddi_dma_mem_alloc(mpt->m_hshk_dma_hdl, alloc_size, 1999 &mpt->m_dev_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2000 &mpt->m_hshk_memp, &alloc_len, &mpt->m_hshk_acc_hdl) 2001 != DDI_SUCCESS) { 2002 ddi_dma_free_handle(&mpt->m_hshk_dma_hdl); 2003 mpt->m_hshk_dma_hdl = NULL; 2004 return (DDI_FAILURE); 2005 } 2006 2007 if (ddi_dma_addr_bind_handle(mpt->m_hshk_dma_hdl, NULL, 2008 mpt->m_hshk_memp, alloc_len, (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), 2009 DDI_DMA_SLEEP, NULL, &tmp_dma_cookie, &ncookie) 2010 != DDI_DMA_MAPPED) { 2011 (void) ddi_dma_mem_free(&mpt->m_hshk_acc_hdl); 2012 ddi_dma_free_handle(&mpt->m_hshk_dma_hdl); 2013 mpt->m_hshk_dma_hdl = NULL; 2014 return (DDI_FAILURE); 2015 } 2016 mpt->m_hshk_dma_size = alloc_size; 2017 return (DDI_SUCCESS); 2018 } 2019 2020 static void 2021 mptsas_free_handshake_msg(mptsas_t *mpt) 2022 { 2023 if (mpt->m_hshk_dma_hdl != NULL) { 2024 (void) ddi_dma_unbind_handle(mpt->m_hshk_dma_hdl); 2025 (void) ddi_dma_mem_free(&mpt->m_hshk_acc_hdl); 2026 ddi_dma_free_handle(&mpt->m_hshk_dma_hdl); 2027 mpt->m_hshk_dma_hdl = NULL; 2028 mpt->m_hshk_dma_size = 0; 2029 } 2030 } 2031 2032 static int 2033 mptsas_power(dev_info_t *dip, int component, int level) 2034 { 2035 #ifndef __lock_lint 2036 _NOTE(ARGUNUSED(component)) 2037 #endif 2038 mptsas_t *mpt; 2039 int rval = DDI_SUCCESS; 2040 int polls = 0; 2041 uint32_t ioc_status; 2042 2043 if (scsi_hba_iport_unit_address(dip) != 0) 2044 return (DDI_SUCCESS); 2045 2046 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip)); 2047 if (mpt == NULL) { 2048 return (DDI_FAILURE); 2049 } 2050 2051 mutex_enter(&mpt->m_mutex); 2052 2053 /* 2054 * If the device is busy, don't lower its power level 2055 */ 2056 if (mpt->m_busy && (mpt->m_power_level > level)) { 2057 mutex_exit(&mpt->m_mutex); 2058 return (DDI_FAILURE); 2059 } 2060 2061 switch (level) { 2062 case PM_LEVEL_D0: 2063 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance)); 2064 MPTSAS_POWER_ON(mpt); 2065 /* 2066 * Wait up to 30 seconds for IOC to come out of reset. 2067 */ 2068 while (((ioc_status = ddi_get32(mpt->m_datap, 2069 &mpt->m_reg->Doorbell)) & 2070 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 2071 if (polls++ > 3000) { 2072 break; 2073 } 2074 delay(drv_usectohz(10000)); 2075 } 2076 /* 2077 * If IOC is not in operational state, try to hard reset it. 2078 */ 2079 if ((ioc_status & MPI2_IOC_STATE_MASK) != 2080 MPI2_IOC_STATE_OPERATIONAL) { 2081 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 2082 mptsas_log(mpt, CE_WARN, 2083 "mptsas_power: hard reset failed"); 2084 mutex_exit(&mpt->m_mutex); 2085 return (DDI_FAILURE); 2086 } 2087 } 2088 mpt->m_power_level = PM_LEVEL_D0; 2089 break; 2090 case PM_LEVEL_D3: 2091 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance)); 2092 MPTSAS_POWER_OFF(mpt); 2093 break; 2094 default: 2095 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.", 2096 mpt->m_instance, level); 2097 rval = DDI_FAILURE; 2098 break; 2099 } 2100 mutex_exit(&mpt->m_mutex); 2101 return (rval); 2102 } 2103 2104 /* 2105 * Initialize configuration space and figure out which 2106 * chip and revison of the chip the mpt driver is using. 2107 */ 2108 int 2109 mptsas_config_space_init(mptsas_t *mpt) 2110 { 2111 ushort_t caps_ptr, cap, cap_count; 2112 2113 NDBG0(("mptsas_config_space_init")); 2114 2115 mptsas_setup_cmd_reg(mpt); 2116 2117 /* 2118 * Get the chip device id: 2119 */ 2120 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID); 2121 2122 /* 2123 * Save the revision. 2124 */ 2125 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID); 2126 2127 /* 2128 * Save the SubSystem Vendor and Device IDs 2129 */ 2130 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID); 2131 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID); 2132 2133 /* 2134 * Set the latency timer to 0x40 as specified by the upa -> pci 2135 * bridge chip design team. This may be done by the sparc pci 2136 * bus nexus driver, but the driver should make sure the latency 2137 * timer is correct for performance reasons. 2138 */ 2139 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER, 2140 MPTSAS_LATENCY_TIMER); 2141 2142 /* 2143 * Check if capabilities list is supported and if so, 2144 * get initial capabilities pointer and clear bits 0,1. 2145 */ 2146 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) 2147 & PCI_STAT_CAP) { 2148 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 2149 PCI_CONF_CAP_PTR), 4); 2150 } else { 2151 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 2152 } 2153 2154 /* 2155 * Walk capabilities if supported. 2156 */ 2157 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 2158 2159 /* 2160 * Check that we haven't exceeded the maximum number of 2161 * capabilities and that the pointer is in a valid range. 2162 */ 2163 if (++cap_count > 48) { 2164 mptsas_log(mpt, CE_WARN, 2165 "too many device capabilities.\n"); 2166 return (FALSE); 2167 } 2168 if (caps_ptr < 64) { 2169 mptsas_log(mpt, CE_WARN, 2170 "capabilities pointer 0x%x out of range.\n", 2171 caps_ptr); 2172 return (FALSE); 2173 } 2174 2175 /* 2176 * Get next capability and check that it is valid. 2177 * For now, we only support power management. 2178 */ 2179 cap = pci_config_get8(mpt->m_config_handle, caps_ptr); 2180 switch (cap) { 2181 case PCI_CAP_ID_PM: 2182 mptsas_log(mpt, CE_NOTE, 2183 "?mptsas%d supports power management.\n", 2184 mpt->m_instance); 2185 mpt->m_options |= MPTSAS_OPT_PM; 2186 2187 /* Save PMCSR offset */ 2188 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR; 2189 break; 2190 2191 /* 2192 * 0x5 is Message signaled interrupts and 0x7 2193 * is pci-x capable. Both are unsupported for now 2194 * but supported by the 1030 chip so we don't 2195 * need to keep printing out the notice. 2196 * 0x10 is PCI-E support (1064E/1068E) 2197 * 0x11 is MSIX supported by the 1064/1068 2198 */ 2199 case 0x5: 2200 case 0x7: 2201 case 0x10: 2202 case 0x11: 2203 break; 2204 default: 2205 mptsas_log(mpt, CE_NOTE, 2206 "?mptsas%d unrecognized capability " 2207 "0x%x.\n", mpt->m_instance, cap); 2208 break; 2209 } 2210 2211 /* 2212 * Get next capabilities pointer and clear bits 0,1. 2213 */ 2214 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 2215 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 2216 } 2217 2218 return (TRUE); 2219 } 2220 2221 static void 2222 mptsas_setup_cmd_reg(mptsas_t *mpt) 2223 { 2224 ushort_t cmdreg; 2225 2226 /* 2227 * Set the command register to the needed values. 2228 */ 2229 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2230 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE | 2231 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE); 2232 cmdreg &= ~PCI_COMM_IO; 2233 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2234 } 2235 2236 static void 2237 mptsas_disable_bus_master(mptsas_t *mpt) 2238 { 2239 ushort_t cmdreg; 2240 2241 /* 2242 * Clear the master enable bit in the PCI command register. 2243 * This prevents any bus mastering activity like DMA. 2244 */ 2245 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2246 cmdreg &= ~PCI_COMM_ME; 2247 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2248 } 2249 2250 int 2251 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep) 2252 { 2253 ddi_dma_attr_t attrs; 2254 uint_t ncookie; 2255 size_t alloc_len; 2256 2257 attrs = mpt->m_io_dma_attr; 2258 attrs.dma_attr_sgllen = 1; 2259 2260 ASSERT(dma_statep != NULL); 2261 2262 if (ddi_dma_alloc_handle(mpt->m_dip, &attrs, 2263 DDI_DMA_SLEEP, NULL, &dma_statep->handle) != DDI_SUCCESS) { 2264 mptsas_log(mpt, CE_WARN, 2265 "unable to allocate dma handle."); 2266 return (DDI_FAILURE); 2267 } 2268 2269 if (ddi_dma_mem_alloc(dma_statep->handle, dma_statep->size, 2270 &mpt->m_dev_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2271 &dma_statep->memp, &alloc_len, &dma_statep->accessp) != 2272 DDI_SUCCESS) { 2273 ddi_dma_free_handle(&dma_statep->handle); 2274 dma_statep->handle = NULL; 2275 mptsas_log(mpt, CE_WARN, 2276 "unable to allocate memory for dma xfer."); 2277 return (DDI_FAILURE); 2278 } 2279 2280 if (ddi_dma_addr_bind_handle(dma_statep->handle, NULL, dma_statep->memp, 2281 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 2282 NULL, &dma_statep->cookie, &ncookie) != DDI_DMA_MAPPED) { 2283 ddi_dma_mem_free(&dma_statep->accessp); 2284 dma_statep->accessp = NULL; 2285 ddi_dma_free_handle(&dma_statep->handle); 2286 dma_statep->handle = NULL; 2287 mptsas_log(mpt, CE_WARN, "unable to bind DMA resources."); 2288 return (DDI_FAILURE); 2289 } 2290 return (DDI_SUCCESS); 2291 } 2292 2293 void 2294 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep) 2295 { 2296 ASSERT(dma_statep != NULL); 2297 if (dma_statep->handle != NULL) { 2298 (void) ddi_dma_unbind_handle(dma_statep->handle); 2299 (void) ddi_dma_mem_free(&dma_statep->accessp); 2300 ddi_dma_free_handle(&dma_statep->handle); 2301 } 2302 } 2303 2304 int 2305 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()) 2306 { 2307 ddi_dma_attr_t attrs; 2308 ddi_dma_handle_t dma_handle; 2309 caddr_t memp; 2310 uint_t ncookie; 2311 ddi_dma_cookie_t cookie; 2312 ddi_acc_handle_t accessp; 2313 size_t alloc_len; 2314 int rval; 2315 2316 ASSERT(mutex_owned(&mpt->m_mutex)); 2317 2318 attrs = mpt->m_msg_dma_attr; 2319 attrs.dma_attr_sgllen = 1; 2320 attrs.dma_attr_granular = size; 2321 2322 if (ddi_dma_alloc_handle(mpt->m_dip, &attrs, 2323 DDI_DMA_SLEEP, NULL, &dma_handle) != DDI_SUCCESS) { 2324 mptsas_log(mpt, CE_WARN, 2325 "unable to allocate dma handle."); 2326 return (DDI_FAILURE); 2327 } 2328 2329 if (ddi_dma_mem_alloc(dma_handle, size, 2330 &mpt->m_dev_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, 2331 &memp, &alloc_len, &accessp) != DDI_SUCCESS) { 2332 ddi_dma_free_handle(&dma_handle); 2333 mptsas_log(mpt, CE_WARN, 2334 "unable to allocate request structure."); 2335 return (DDI_FAILURE); 2336 } 2337 2338 if (ddi_dma_addr_bind_handle(dma_handle, NULL, memp, 2339 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 2340 NULL, &cookie, &ncookie) != DDI_DMA_MAPPED) { 2341 (void) ddi_dma_mem_free(&accessp); 2342 ddi_dma_free_handle(&dma_handle); 2343 mptsas_log(mpt, CE_WARN, "unable to bind DMA resources."); 2344 return (DDI_FAILURE); 2345 } 2346 2347 rval = (*callback) (mpt, memp, var, accessp); 2348 2349 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) || 2350 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) { 2351 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 2352 rval = DDI_FAILURE; 2353 } 2354 2355 if (dma_handle != NULL) { 2356 (void) ddi_dma_unbind_handle(dma_handle); 2357 (void) ddi_dma_mem_free(&accessp); 2358 ddi_dma_free_handle(&dma_handle); 2359 } 2360 2361 return (rval); 2362 2363 } 2364 2365 static int 2366 mptsas_alloc_request_frames(mptsas_t *mpt) 2367 { 2368 ddi_dma_attr_t frame_dma_attrs; 2369 caddr_t memp; 2370 uint_t ncookie; 2371 ddi_dma_cookie_t cookie; 2372 size_t alloc_len; 2373 size_t mem_size; 2374 2375 /* 2376 * The size of the request frame pool is: 2377 * Number of Request Frames * Request Frame Size 2378 */ 2379 mem_size = mpt->m_max_requests * mpt->m_req_frame_size; 2380 2381 /* 2382 * set the DMA attributes. System Request Message Frames must be 2383 * aligned on a 16-byte boundry. 2384 */ 2385 frame_dma_attrs = mpt->m_msg_dma_attr; 2386 frame_dma_attrs.dma_attr_align = 16; 2387 frame_dma_attrs.dma_attr_sgllen = 1; 2388 2389 /* 2390 * allocate the request frame pool. 2391 */ 2392 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attrs, 2393 DDI_DMA_SLEEP, NULL, &mpt->m_dma_req_frame_hdl) != DDI_SUCCESS) { 2394 mptsas_log(mpt, CE_WARN, 2395 "Unable to allocate dma handle."); 2396 return (DDI_FAILURE); 2397 } 2398 2399 if (ddi_dma_mem_alloc(mpt->m_dma_req_frame_hdl, 2400 mem_size, &mpt->m_dev_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 2401 NULL, (caddr_t *)&memp, &alloc_len, &mpt->m_acc_req_frame_hdl) 2402 != DDI_SUCCESS) { 2403 ddi_dma_free_handle(&mpt->m_dma_req_frame_hdl); 2404 mpt->m_dma_req_frame_hdl = NULL; 2405 mptsas_log(mpt, CE_WARN, 2406 "Unable to allocate request frames."); 2407 return (DDI_FAILURE); 2408 } 2409 2410 if (ddi_dma_addr_bind_handle(mpt->m_dma_req_frame_hdl, NULL, 2411 memp, alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2412 DDI_DMA_SLEEP, NULL, &cookie, &ncookie) != DDI_DMA_MAPPED) { 2413 (void) ddi_dma_mem_free(&mpt->m_acc_req_frame_hdl); 2414 ddi_dma_free_handle(&mpt->m_dma_req_frame_hdl); 2415 mpt->m_dma_req_frame_hdl = NULL; 2416 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources."); 2417 return (DDI_FAILURE); 2418 } 2419 2420 /* 2421 * Store the request frame memory address. This chip uses this 2422 * address to dma to and from the driver's frame. The second 2423 * address is the address mpt uses to fill in the frame. 2424 */ 2425 mpt->m_req_frame_dma_addr = cookie.dmac_laddress; 2426 mpt->m_req_frame = memp; 2427 2428 /* 2429 * Clear the request frame pool. 2430 */ 2431 bzero(mpt->m_req_frame, alloc_len); 2432 2433 return (DDI_SUCCESS); 2434 } 2435 2436 static int 2437 mptsas_alloc_reply_frames(mptsas_t *mpt) 2438 { 2439 ddi_dma_attr_t frame_dma_attrs; 2440 caddr_t memp; 2441 uint_t ncookie; 2442 ddi_dma_cookie_t cookie; 2443 size_t alloc_len; 2444 size_t mem_size; 2445 2446 /* 2447 * The size of the reply frame pool is: 2448 * Number of Reply Frames * Reply Frame Size 2449 */ 2450 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size; 2451 2452 /* 2453 * set the DMA attributes. System Reply Message Frames must be 2454 * aligned on a 4-byte boundry. This is the default. 2455 */ 2456 frame_dma_attrs = mpt->m_msg_dma_attr; 2457 frame_dma_attrs.dma_attr_sgllen = 1; 2458 2459 /* 2460 * allocate the reply frame pool 2461 */ 2462 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attrs, 2463 DDI_DMA_SLEEP, NULL, &mpt->m_dma_reply_frame_hdl) != DDI_SUCCESS) { 2464 mptsas_log(mpt, CE_WARN, 2465 "Unable to allocate dma handle."); 2466 return (DDI_FAILURE); 2467 } 2468 2469 if (ddi_dma_mem_alloc(mpt->m_dma_reply_frame_hdl, 2470 mem_size, &mpt->m_dev_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 2471 NULL, (caddr_t *)&memp, &alloc_len, &mpt->m_acc_reply_frame_hdl) 2472 != DDI_SUCCESS) { 2473 ddi_dma_free_handle(&mpt->m_dma_reply_frame_hdl); 2474 mpt->m_dma_reply_frame_hdl = NULL; 2475 mptsas_log(mpt, CE_WARN, 2476 "Unable to allocate reply frames."); 2477 return (DDI_FAILURE); 2478 } 2479 2480 if (ddi_dma_addr_bind_handle(mpt->m_dma_reply_frame_hdl, NULL, 2481 memp, alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2482 DDI_DMA_SLEEP, NULL, &cookie, &ncookie) != DDI_DMA_MAPPED) { 2483 (void) ddi_dma_mem_free(&mpt->m_acc_reply_frame_hdl); 2484 ddi_dma_free_handle(&mpt->m_dma_reply_frame_hdl); 2485 mpt->m_dma_reply_frame_hdl = NULL; 2486 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources."); 2487 return (DDI_FAILURE); 2488 } 2489 2490 /* 2491 * Store the reply frame memory address. This chip uses this 2492 * address to dma to and from the driver's frame. The second 2493 * address is the address mpt uses to process the frame. 2494 */ 2495 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress; 2496 mpt->m_reply_frame = memp; 2497 2498 /* 2499 * Clear the reply frame pool. 2500 */ 2501 bzero(mpt->m_reply_frame, alloc_len); 2502 2503 return (DDI_SUCCESS); 2504 } 2505 2506 static int 2507 mptsas_alloc_free_queue(mptsas_t *mpt) 2508 { 2509 ddi_dma_attr_t frame_dma_attrs; 2510 caddr_t memp; 2511 uint_t ncookie; 2512 ddi_dma_cookie_t cookie; 2513 size_t alloc_len; 2514 size_t mem_size; 2515 2516 /* 2517 * The reply free queue size is: 2518 * Reply Free Queue Depth * 4 2519 * The "4" is the size of one 32 bit address (low part of 64-bit 2520 * address) 2521 */ 2522 mem_size = mpt->m_free_queue_depth * 4; 2523 2524 /* 2525 * set the DMA attributes The Reply Free Queue must be aligned on a 2526 * 16-byte boundry. 2527 */ 2528 frame_dma_attrs = mpt->m_msg_dma_attr; 2529 frame_dma_attrs.dma_attr_align = 16; 2530 frame_dma_attrs.dma_attr_sgllen = 1; 2531 2532 /* 2533 * allocate the reply free queue 2534 */ 2535 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attrs, 2536 DDI_DMA_SLEEP, NULL, &mpt->m_dma_free_queue_hdl) != DDI_SUCCESS) { 2537 mptsas_log(mpt, CE_WARN, 2538 "Unable to allocate dma handle."); 2539 return (DDI_FAILURE); 2540 } 2541 2542 if (ddi_dma_mem_alloc(mpt->m_dma_free_queue_hdl, 2543 mem_size, &mpt->m_dev_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 2544 NULL, (caddr_t *)&memp, &alloc_len, &mpt->m_acc_free_queue_hdl) 2545 != DDI_SUCCESS) { 2546 ddi_dma_free_handle(&mpt->m_dma_free_queue_hdl); 2547 mpt->m_dma_free_queue_hdl = NULL; 2548 mptsas_log(mpt, CE_WARN, 2549 "Unable to allocate free queue."); 2550 return (DDI_FAILURE); 2551 } 2552 2553 if (ddi_dma_addr_bind_handle(mpt->m_dma_free_queue_hdl, NULL, 2554 memp, alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2555 DDI_DMA_SLEEP, NULL, &cookie, &ncookie) != DDI_DMA_MAPPED) { 2556 (void) ddi_dma_mem_free(&mpt->m_acc_free_queue_hdl); 2557 ddi_dma_free_handle(&mpt->m_dma_free_queue_hdl); 2558 mpt->m_dma_free_queue_hdl = NULL; 2559 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources."); 2560 return (DDI_FAILURE); 2561 } 2562 2563 /* 2564 * Store the reply free queue memory address. This chip uses this 2565 * address to read from the reply free queue. The second address 2566 * is the address mpt uses to manage the queue. 2567 */ 2568 mpt->m_free_queue_dma_addr = cookie.dmac_laddress; 2569 mpt->m_free_queue = memp; 2570 2571 /* 2572 * Clear the reply free queue memory. 2573 */ 2574 bzero(mpt->m_free_queue, alloc_len); 2575 2576 return (DDI_SUCCESS); 2577 } 2578 2579 static int 2580 mptsas_alloc_post_queue(mptsas_t *mpt) 2581 { 2582 ddi_dma_attr_t frame_dma_attrs; 2583 caddr_t memp; 2584 uint_t ncookie; 2585 ddi_dma_cookie_t cookie; 2586 size_t alloc_len; 2587 size_t mem_size; 2588 2589 /* 2590 * The reply descriptor post queue size is: 2591 * Reply Descriptor Post Queue Depth * 8 2592 * The "8" is the size of each descriptor (8 bytes or 64 bits). 2593 */ 2594 mem_size = mpt->m_post_queue_depth * 8; 2595 2596 /* 2597 * set the DMA attributes. The Reply Descriptor Post Queue must be 2598 * aligned on a 16-byte boundry. 2599 */ 2600 frame_dma_attrs = mpt->m_msg_dma_attr; 2601 frame_dma_attrs.dma_attr_align = 16; 2602 frame_dma_attrs.dma_attr_sgllen = 1; 2603 2604 /* 2605 * allocate the reply post queue 2606 */ 2607 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attrs, 2608 DDI_DMA_SLEEP, NULL, &mpt->m_dma_post_queue_hdl) != DDI_SUCCESS) { 2609 mptsas_log(mpt, CE_WARN, 2610 "Unable to allocate dma handle."); 2611 return (DDI_FAILURE); 2612 } 2613 2614 if (ddi_dma_mem_alloc(mpt->m_dma_post_queue_hdl, 2615 mem_size, &mpt->m_dev_acc_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 2616 NULL, (caddr_t *)&memp, &alloc_len, &mpt->m_acc_post_queue_hdl) 2617 != DDI_SUCCESS) { 2618 ddi_dma_free_handle(&mpt->m_dma_post_queue_hdl); 2619 mpt->m_dma_post_queue_hdl = NULL; 2620 mptsas_log(mpt, CE_WARN, 2621 "Unable to allocate post queue."); 2622 return (DDI_FAILURE); 2623 } 2624 2625 if (ddi_dma_addr_bind_handle(mpt->m_dma_post_queue_hdl, NULL, 2626 memp, alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2627 DDI_DMA_SLEEP, NULL, &cookie, &ncookie) != DDI_DMA_MAPPED) { 2628 (void) ddi_dma_mem_free(&mpt->m_acc_post_queue_hdl); 2629 ddi_dma_free_handle(&mpt->m_dma_post_queue_hdl); 2630 mpt->m_dma_post_queue_hdl = NULL; 2631 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources."); 2632 return (DDI_FAILURE); 2633 } 2634 2635 /* 2636 * Store the reply descriptor post queue memory address. This chip 2637 * uses this address to write to the reply descriptor post queue. The 2638 * second address is the address mpt uses to manage the queue. 2639 */ 2640 mpt->m_post_queue_dma_addr = cookie.dmac_laddress; 2641 mpt->m_post_queue = memp; 2642 2643 /* 2644 * Clear the reply post queue memory. 2645 */ 2646 bzero(mpt->m_post_queue, alloc_len); 2647 2648 return (DDI_SUCCESS); 2649 } 2650 2651 static int 2652 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2653 { 2654 mptsas_cache_frames_t *frames = NULL; 2655 if (cmd->cmd_extra_frames == NULL) { 2656 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP); 2657 if (frames == NULL) { 2658 return (DDI_FAILURE); 2659 } 2660 cmd->cmd_extra_frames = frames; 2661 } 2662 return (DDI_SUCCESS); 2663 } 2664 2665 static void 2666 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2667 { 2668 if (cmd->cmd_extra_frames) { 2669 kmem_cache_free(mpt->m_cache_frames, 2670 (void *)cmd->cmd_extra_frames); 2671 cmd->cmd_extra_frames = NULL; 2672 } 2673 } 2674 2675 static void 2676 mptsas_cfg_fini(mptsas_t *mpt) 2677 { 2678 NDBG0(("mptsas_cfg_fini")); 2679 ddi_regs_map_free(&mpt->m_datap); 2680 } 2681 2682 static void 2683 mptsas_hba_fini(mptsas_t *mpt) 2684 { 2685 NDBG0(("mptsas_hba_fini")); 2686 2687 /* 2688 * Disable any bus mastering ability (i.e: DMA) prior to freeing any 2689 * allocated DMA resources. 2690 */ 2691 if (mpt->m_config_handle != NULL) 2692 mptsas_disable_bus_master(mpt); 2693 2694 /* 2695 * Free up any allocated memory 2696 */ 2697 if (mpt->m_dma_req_frame_hdl != NULL) { 2698 (void) ddi_dma_unbind_handle(mpt->m_dma_req_frame_hdl); 2699 ddi_dma_mem_free(&mpt->m_acc_req_frame_hdl); 2700 ddi_dma_free_handle(&mpt->m_dma_req_frame_hdl); 2701 mpt->m_dma_req_frame_hdl = NULL; 2702 } 2703 2704 if (mpt->m_dma_reply_frame_hdl != NULL) { 2705 (void) ddi_dma_unbind_handle(mpt->m_dma_reply_frame_hdl); 2706 ddi_dma_mem_free(&mpt->m_acc_reply_frame_hdl); 2707 ddi_dma_free_handle(&mpt->m_dma_reply_frame_hdl); 2708 mpt->m_dma_reply_frame_hdl = NULL; 2709 } 2710 2711 if (mpt->m_dma_free_queue_hdl != NULL) { 2712 (void) ddi_dma_unbind_handle(mpt->m_dma_free_queue_hdl); 2713 ddi_dma_mem_free(&mpt->m_acc_free_queue_hdl); 2714 ddi_dma_free_handle(&mpt->m_dma_free_queue_hdl); 2715 mpt->m_dma_free_queue_hdl = NULL; 2716 } 2717 2718 if (mpt->m_dma_post_queue_hdl != NULL) { 2719 (void) ddi_dma_unbind_handle(mpt->m_dma_post_queue_hdl); 2720 ddi_dma_mem_free(&mpt->m_acc_post_queue_hdl); 2721 ddi_dma_free_handle(&mpt->m_dma_post_queue_hdl); 2722 mpt->m_dma_post_queue_hdl = NULL; 2723 } 2724 2725 if (mpt->m_replyh_args != NULL) { 2726 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 2727 * mpt->m_max_replies); 2728 } 2729 } 2730 2731 static int 2732 mptsas_name_child(dev_info_t *lun_dip, char *name, int len) 2733 { 2734 int lun = 0; 2735 char *sas_wwn = NULL; 2736 int phynum = -1; 2737 int reallen = 0; 2738 2739 /* Get the target num */ 2740 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS, 2741 LUN_PROP, 0); 2742 2743 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS, 2744 SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn) == DDI_PROP_SUCCESS) { 2745 /* 2746 * Stick in the address of the form "wWWN,LUN" 2747 */ 2748 reallen = snprintf(name, len, "w%s,%x", sas_wwn, lun); 2749 ddi_prop_free(sas_wwn); 2750 } else if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, 2751 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) { 2752 /* 2753 * Stick in the address of form "pPHY,LUN" 2754 */ 2755 reallen = snprintf(name, len, "p%x,%x", phynum, lun); 2756 } else { 2757 return (DDI_FAILURE); 2758 } 2759 2760 ASSERT(reallen < len); 2761 if (reallen >= len) { 2762 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter " 2763 "length too small, it needs to be %d bytes", reallen + 1); 2764 } 2765 return (DDI_SUCCESS); 2766 } 2767 2768 /* 2769 * tran_tgt_init(9E) - target device instance initialization 2770 */ 2771 static int 2772 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 2773 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 2774 { 2775 #ifndef __lock_lint 2776 _NOTE(ARGUNUSED(hba_tran)) 2777 #endif 2778 2779 /* 2780 * At this point, the scsi_device structure already exists 2781 * and has been initialized. 2782 * 2783 * Use this function to allocate target-private data structures, 2784 * if needed by this HBA. Add revised flow-control and queue 2785 * properties for child here, if desired and if you can tell they 2786 * support tagged queueing by now. 2787 */ 2788 mptsas_t *mpt; 2789 int lun = sd->sd_address.a_lun; 2790 mdi_pathinfo_t *pip = NULL; 2791 mptsas_tgt_private_t *tgt_private = NULL; 2792 mptsas_target_t *ptgt = NULL; 2793 char *psas_wwn = NULL; 2794 int phymask = 0; 2795 uint64_t sas_wwn = 0; 2796 mpt = SDEV2MPT(sd); 2797 2798 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0); 2799 2800 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d", 2801 (void *)hba_dip, (void *)tgt_dip, lun)); 2802 2803 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 2804 (void) ndi_merge_node(tgt_dip, mptsas_name_child); 2805 ddi_set_name_addr(tgt_dip, NULL); 2806 return (DDI_FAILURE); 2807 } 2808 /* 2809 * phymask is 0 means the virtual port for RAID 2810 */ 2811 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0, 2812 "phymask", 0); 2813 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 2814 if ((pip = (void *)(sd->sd_private)) == NULL) { 2815 /* 2816 * Very bad news if this occurs. Somehow scsi_vhci has 2817 * lost the pathinfo node for this target. 2818 */ 2819 return (DDI_NOT_WELL_FORMED); 2820 } 2821 2822 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) != 2823 DDI_PROP_SUCCESS) { 2824 mptsas_log(mpt, CE_WARN, "Get lun property failed\n"); 2825 return (DDI_FAILURE); 2826 } 2827 2828 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT, 2829 &psas_wwn) == MDI_SUCCESS) { 2830 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 2831 sas_wwn = 0; 2832 } 2833 (void) mdi_prop_free(psas_wwn); 2834 } 2835 } else { 2836 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip, 2837 DDI_PROP_DONTPASS, LUN_PROP, 0); 2838 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip, 2839 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) == 2840 DDI_PROP_SUCCESS) { 2841 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 2842 sas_wwn = 0; 2843 } 2844 ddi_prop_free(psas_wwn); 2845 } else { 2846 sas_wwn = 0; 2847 } 2848 } 2849 ASSERT((sas_wwn != 0) || (phymask != 0)); 2850 mutex_enter(&mpt->m_mutex); 2851 ptgt = mptsas_hash_search(&mpt->m_active->m_tgttbl, sas_wwn, phymask); 2852 mutex_exit(&mpt->m_mutex); 2853 if (ptgt == NULL) { 2854 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or " 2855 "gone already! phymask:%x, saswwn %"PRIx64, phymask, 2856 sas_wwn); 2857 return (DDI_FAILURE); 2858 } 2859 if (hba_tran->tran_tgt_private == NULL) { 2860 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t), 2861 KM_SLEEP); 2862 tgt_private->t_lun = lun; 2863 tgt_private->t_private = ptgt; 2864 hba_tran->tran_tgt_private = tgt_private; 2865 } 2866 2867 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 2868 return (DDI_SUCCESS); 2869 } 2870 mutex_enter(&mpt->m_mutex); 2871 2872 if (ptgt->m_deviceinfo & 2873 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 2874 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 2875 uchar_t *inq89 = NULL; 2876 int inq89_len = 0x238; 2877 int reallen = 0; 2878 int rval = 0; 2879 struct sata_id *sid = NULL; 2880 char model[SATA_ID_MODEL_LEN + 1]; 2881 char fw[SATA_ID_FW_LEN + 1]; 2882 char *vid, *pid; 2883 int i; 2884 2885 mutex_exit(&mpt->m_mutex); 2886 /* 2887 * According SCSI/ATA Translation -2 (SAT-2) revision 01a 2888 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY 2889 * DEVICE data or ATA IDENTIFY PACKET DEVICE data. 2890 */ 2891 inq89 = kmem_zalloc(inq89_len, KM_SLEEP); 2892 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89, 2893 inq89, inq89_len, &reallen, 1); 2894 2895 if (rval != 0) { 2896 if (inq89 != NULL) { 2897 kmem_free(inq89, inq89_len); 2898 } 2899 2900 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 2901 "0x89 for SATA target:%x failed!", ptgt->m_devhdl); 2902 return (DDI_SUCCESS); 2903 } 2904 sid = (void *)(&inq89[60]); 2905 2906 swab(sid->ai_model, model, SATA_ID_MODEL_LEN); 2907 swab(sid->ai_fw, fw, SATA_ID_FW_LEN); 2908 2909 model[SATA_ID_MODEL_LEN] = 0; 2910 fw[SATA_ID_FW_LEN] = 0; 2911 2912 /* 2913 * split model into into vid/pid 2914 */ 2915 for (i = 0, pid = model; i < SATA_ID_MODEL_LEN; i++, pid++) 2916 if ((*pid == ' ') || (*pid == '\t')) 2917 break; 2918 if (i < SATA_ID_MODEL_LEN) { 2919 vid = model; 2920 /* 2921 * terminate vid, establish pid 2922 */ 2923 *pid++ = 0; 2924 } else { 2925 /* 2926 * vid will stay "ATA ", the rule is same 2927 * as sata framework implementation. 2928 */ 2929 vid = NULL; 2930 /* 2931 * model is all pid 2932 */ 2933 pid = model; 2934 } 2935 2936 /* 2937 * override SCSA "inquiry-*" properties 2938 */ 2939 if (vid) 2940 (void) scsi_device_prop_update_inqstring(sd, 2941 INQUIRY_VENDOR_ID, vid, strlen(vid)); 2942 if (pid) 2943 (void) scsi_device_prop_update_inqstring(sd, 2944 INQUIRY_PRODUCT_ID, pid, strlen(pid)); 2945 (void) scsi_device_prop_update_inqstring(sd, 2946 INQUIRY_REVISION_ID, fw, strlen(fw)); 2947 2948 if (inq89 != NULL) { 2949 kmem_free(inq89, inq89_len); 2950 } 2951 } else { 2952 mutex_exit(&mpt->m_mutex); 2953 } 2954 2955 return (DDI_SUCCESS); 2956 } 2957 /* 2958 * tran_tgt_free(9E) - target device instance deallocation 2959 */ 2960 static void 2961 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 2962 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 2963 { 2964 #ifndef __lock_lint 2965 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd)) 2966 #endif 2967 2968 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private; 2969 2970 if (tgt_private != NULL) { 2971 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 2972 hba_tran->tran_tgt_private = NULL; 2973 } 2974 } 2975 2976 /* 2977 * scsi_pkt handling 2978 * 2979 * Visible to the external world via the transport structure. 2980 */ 2981 2982 /* 2983 * Notes: 2984 * - transport the command to the addressed SCSI target/lun device 2985 * - normal operation is to schedule the command to be transported, 2986 * and return TRAN_ACCEPT if this is successful. 2987 * - if NO_INTR, tran_start must poll device for command completion 2988 */ 2989 static int 2990 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt) 2991 { 2992 #ifndef __lock_lint 2993 _NOTE(ARGUNUSED(ap)) 2994 #endif 2995 mptsas_t *mpt = PKT2MPT(pkt); 2996 mptsas_cmd_t *cmd = PKT2CMD(pkt); 2997 int rval; 2998 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 2999 3000 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt)); 3001 ASSERT(ptgt); 3002 if (ptgt == NULL) 3003 return (TRAN_FATAL_ERROR); 3004 3005 /* 3006 * prepare the pkt before taking mutex. 3007 */ 3008 rval = mptsas_prepare_pkt(cmd); 3009 if (rval != TRAN_ACCEPT) { 3010 return (rval); 3011 } 3012 3013 /* 3014 * Send the command to target/lun, however your HBA requires it. 3015 * If busy, return TRAN_BUSY; if there's some other formatting error 3016 * in the packet, return TRAN_BADPKT; otherwise, fall through to the 3017 * return of TRAN_ACCEPT. 3018 * 3019 * Remember that access to shared resources, including the mptsas_t 3020 * data structure and the HBA hardware registers, must be protected 3021 * with mutexes, here and everywhere. 3022 * 3023 * Also remember that at interrupt time, you'll get an argument 3024 * to the interrupt handler which is a pointer to your mptsas_t 3025 * structure; you'll have to remember which commands are outstanding 3026 * and which scsi_pkt is the currently-running command so the 3027 * interrupt handler can refer to the pkt to set completion 3028 * status, call the target driver back through pkt_comp, etc. 3029 * 3030 * If the instance lock is held by other thread, don't spin to wait 3031 * for it. Instead, queue the cmd and next time when the instance lock 3032 * is not held, accept all the queued cmd. A extra tx_waitq is 3033 * introduced to protect the queue. 3034 * 3035 * The polled cmd will not be queud and accepted as usual. 3036 * 3037 * Under the tx_waitq mutex, record whether a thread is draining 3038 * the tx_waitq. An IO requesting thread that finds the instance 3039 * mutex contended appends to the tx_waitq and while holding the 3040 * tx_wait mutex, if the draining flag is not set, sets it and then 3041 * proceeds to spin for the instance mutex. This scheme ensures that 3042 * the last cmd in a burst be processed. 3043 * 3044 * we enable this feature only when the helper threads are enabled, 3045 * at which we think the loads are heavy. 3046 * 3047 * per instance mutex m_tx_waitq_mutex is introduced to protect the 3048 * m_tx_waitqtail, m_tx_waitq, m_tx_draining. 3049 */ 3050 3051 if (mpt->m_doneq_thread_n) { 3052 if (mutex_tryenter(&mpt->m_mutex) != 0) { 3053 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3054 mutex_exit(&mpt->m_mutex); 3055 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3056 mutex_enter(&mpt->m_mutex); 3057 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3058 mutex_exit(&mpt->m_mutex); 3059 } else { 3060 mutex_enter(&mpt->m_tx_waitq_mutex); 3061 /* 3062 * ptgt->m_dr_flag is protected by m_mutex or 3063 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex 3064 * is acquired. 3065 */ 3066 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3067 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3068 /* 3069 * The command should be allowed to 3070 * retry by returning TRAN_BUSY to 3071 * to stall the I/O's which come from 3072 * scsi_vhci since the device/path is 3073 * in unstable state now. 3074 */ 3075 mutex_exit(&mpt->m_tx_waitq_mutex); 3076 return (TRAN_BUSY); 3077 } else { 3078 /* 3079 * The device is offline, just fail the 3080 * command by returning 3081 * TRAN_FATAL_ERROR. 3082 */ 3083 mutex_exit(&mpt->m_tx_waitq_mutex); 3084 return (TRAN_FATAL_ERROR); 3085 } 3086 } 3087 if (mpt->m_tx_draining) { 3088 cmd->cmd_flags |= CFLAG_TXQ; 3089 *mpt->m_tx_waitqtail = cmd; 3090 mpt->m_tx_waitqtail = &cmd->cmd_linkp; 3091 mutex_exit(&mpt->m_tx_waitq_mutex); 3092 } else { /* drain the queue */ 3093 mpt->m_tx_draining = 1; 3094 mutex_exit(&mpt->m_tx_waitq_mutex); 3095 mutex_enter(&mpt->m_mutex); 3096 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3097 mutex_exit(&mpt->m_mutex); 3098 } 3099 } 3100 } else { 3101 mutex_enter(&mpt->m_mutex); 3102 /* 3103 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3104 * in this case, m_mutex is acquired. 3105 */ 3106 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3107 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3108 /* 3109 * commands should be allowed to retry by 3110 * returning TRAN_BUSY to stall the I/O's 3111 * which come from scsi_vhci since the device/ 3112 * path is in unstable state now. 3113 */ 3114 mutex_exit(&mpt->m_mutex); 3115 return (TRAN_BUSY); 3116 } else { 3117 /* 3118 * The device is offline, just fail the 3119 * command by returning TRAN_FATAL_ERROR. 3120 */ 3121 mutex_exit(&mpt->m_mutex); 3122 return (TRAN_FATAL_ERROR); 3123 } 3124 } 3125 rval = mptsas_accept_pkt(mpt, cmd); 3126 mutex_exit(&mpt->m_mutex); 3127 } 3128 3129 return (rval); 3130 } 3131 3132 /* 3133 * Accept all the queued cmds(if any) before accept the current one. 3134 */ 3135 static int 3136 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3137 { 3138 int rval; 3139 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3140 3141 ASSERT(mutex_owned(&mpt->m_mutex)); 3142 /* 3143 * The call to mptsas_accept_tx_waitq() must always be performed 3144 * because that is where mpt->m_tx_draining is cleared. 3145 */ 3146 mutex_enter(&mpt->m_tx_waitq_mutex); 3147 mptsas_accept_tx_waitq(mpt); 3148 mutex_exit(&mpt->m_tx_waitq_mutex); 3149 /* 3150 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3151 * in this case, m_mutex is acquired. 3152 */ 3153 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3154 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3155 /* 3156 * The command should be allowed to retry by returning 3157 * TRAN_BUSY to stall the I/O's which come from 3158 * scsi_vhci since the device/path is in unstable state 3159 * now. 3160 */ 3161 return (TRAN_BUSY); 3162 } else { 3163 /* 3164 * The device is offline, just fail the command by 3165 * return TRAN_FATAL_ERROR. 3166 */ 3167 return (TRAN_FATAL_ERROR); 3168 } 3169 } 3170 rval = mptsas_accept_pkt(mpt, cmd); 3171 3172 return (rval); 3173 } 3174 3175 static int 3176 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3177 { 3178 int rval = TRAN_ACCEPT; 3179 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3180 3181 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd)); 3182 3183 ASSERT(mutex_owned(&mpt->m_mutex)); 3184 3185 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) { 3186 rval = mptsas_prepare_pkt(cmd); 3187 if (rval != TRAN_ACCEPT) { 3188 cmd->cmd_flags &= ~CFLAG_TRANFLAG; 3189 return (rval); 3190 } 3191 } 3192 3193 /* 3194 * reset the throttle if we were draining 3195 */ 3196 if ((ptgt->m_t_ncmds == 0) && 3197 (ptgt->m_t_throttle == DRAIN_THROTTLE)) { 3198 NDBG23(("reset throttle")); 3199 ASSERT(ptgt->m_reset_delay == 0); 3200 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 3201 } 3202 3203 /* 3204 * If HBA is being reset, the DevHandles are being re-initialized, 3205 * which means that they could be invalid even if the target is still 3206 * attached. Check if being reset and if DevHandle is being 3207 * re-initialized. If this is the case, return BUSY so the I/O can be 3208 * retried later. 3209 */ 3210 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) { 3211 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 3212 if (cmd->cmd_flags & CFLAG_TXQ) { 3213 mptsas_doneq_add(mpt, cmd); 3214 mptsas_doneq_empty(mpt); 3215 return (rval); 3216 } else { 3217 return (TRAN_BUSY); 3218 } 3219 } 3220 3221 /* 3222 * If device handle has already been invalidated, just 3223 * fail the command. In theory, command from scsi_vhci 3224 * client is impossible send down command with invalid 3225 * devhdl since devhdl is set after path offline, target 3226 * driver is not suppose to select a offlined path. 3227 */ 3228 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) { 3229 NDBG20(("rejecting command, it might because invalid devhdl " 3230 "request.")); 3231 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED); 3232 if (cmd->cmd_flags & CFLAG_TXQ) { 3233 mptsas_doneq_add(mpt, cmd); 3234 mptsas_doneq_empty(mpt); 3235 return (rval); 3236 } else { 3237 return (TRAN_FATAL_ERROR); 3238 } 3239 } 3240 /* 3241 * The first case is the normal case. mpt gets a command from the 3242 * target driver and starts it. 3243 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 3244 * commands is m_max_requests - 2. 3245 */ 3246 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 3247 (ptgt->m_t_throttle > HOLD_THROTTLE) && 3248 (ptgt->m_t_ncmds < ptgt->m_t_throttle) && 3249 (ptgt->m_reset_delay == 0) && 3250 (ptgt->m_t_nwait == 0) && 3251 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) { 3252 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 3253 (void) mptsas_start_cmd(mpt, cmd); 3254 } else { 3255 mptsas_waitq_add(mpt, cmd); 3256 } 3257 } else { 3258 /* 3259 * Add this pkt to the work queue 3260 */ 3261 mptsas_waitq_add(mpt, cmd); 3262 3263 if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3264 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME); 3265 3266 /* 3267 * Only flush the doneq if this is not a TM 3268 * cmd. For TM cmds the flushing of the 3269 * doneq will be done in those routines. 3270 */ 3271 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 3272 mptsas_doneq_empty(mpt); 3273 } 3274 } 3275 } 3276 return (rval); 3277 } 3278 3279 int 3280 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 3281 { 3282 mptsas_slots_t *slots; 3283 int slot; 3284 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3285 3286 ASSERT(mutex_owned(&mpt->m_mutex)); 3287 slots = mpt->m_active; 3288 3289 /* 3290 * Account for reserved TM request slot and reserved SMID of 0. 3291 */ 3292 ASSERT(slots->m_n_slots == (mpt->m_max_requests - 2)); 3293 3294 /* 3295 * m_tags is equivalent to the SMID when sending requests. Since the 3296 * SMID cannot be 0, start out at one if rolling over past the size 3297 * of the request queue depth. Also, don't use the last SMID, which is 3298 * reserved for TM requests. 3299 */ 3300 slot = (slots->m_tags)++; 3301 if (slots->m_tags > slots->m_n_slots) { 3302 slots->m_tags = 1; 3303 } 3304 3305 alloc_tag: 3306 /* Validate tag, should never fail. */ 3307 if (slots->m_slot[slot] == NULL) { 3308 /* 3309 * Make sure SMID is not using reserved value of 0 3310 * and the TM request slot. 3311 */ 3312 ASSERT((slot > 0) && (slot <= slots->m_n_slots)); 3313 cmd->cmd_slot = slot; 3314 slots->m_slot[slot] = cmd; 3315 mpt->m_ncmds++; 3316 3317 /* 3318 * only increment per target ncmds if this is not a 3319 * command that has no target associated with it (i.e. a 3320 * event acknoledgment) 3321 */ 3322 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 3323 ptgt->m_t_ncmds++; 3324 } 3325 cmd->cmd_active_timeout = cmd->cmd_pkt->pkt_time; 3326 3327 /* 3328 * If initial timout is less than or equal to one tick, bump 3329 * the timeout by a tick so that command doesn't timeout before 3330 * its allotted time. 3331 */ 3332 if (cmd->cmd_active_timeout <= mptsas_scsi_watchdog_tick) { 3333 cmd->cmd_active_timeout += mptsas_scsi_watchdog_tick; 3334 } 3335 return (TRUE); 3336 } else { 3337 int i; 3338 3339 /* 3340 * If slot in use, scan until a free one is found. Don't use 0 3341 * or final slot, which is reserved for TM requests. 3342 */ 3343 for (i = 0; i < slots->m_n_slots; i++) { 3344 slot = slots->m_tags; 3345 if (++(slots->m_tags) > slots->m_n_slots) { 3346 slots->m_tags = 1; 3347 } 3348 if (slots->m_slot[slot] == NULL) { 3349 NDBG22(("found free slot %d", slot)); 3350 goto alloc_tag; 3351 } 3352 } 3353 } 3354 return (FALSE); 3355 } 3356 3357 /* 3358 * prepare the pkt: 3359 * the pkt may have been resubmitted or just reused so 3360 * initialize some fields and do some checks. 3361 */ 3362 static int 3363 mptsas_prepare_pkt(mptsas_cmd_t *cmd) 3364 { 3365 struct scsi_pkt *pkt = CMD2PKT(cmd); 3366 3367 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd)); 3368 3369 /* 3370 * Reinitialize some fields that need it; the packet may 3371 * have been resubmitted 3372 */ 3373 pkt->pkt_reason = CMD_CMPLT; 3374 pkt->pkt_state = 0; 3375 pkt->pkt_statistics = 0; 3376 pkt->pkt_resid = 0; 3377 cmd->cmd_age = 0; 3378 cmd->cmd_pkt_flags = pkt->pkt_flags; 3379 3380 /* 3381 * zero status byte. 3382 */ 3383 *(pkt->pkt_scbp) = 0; 3384 3385 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3386 pkt->pkt_resid = cmd->cmd_dmacount; 3387 3388 /* 3389 * consistent packets need to be sync'ed first 3390 * (only for data going out) 3391 */ 3392 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 3393 (cmd->cmd_flags & CFLAG_DMASEND)) { 3394 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 3395 DDI_DMA_SYNC_FORDEV); 3396 } 3397 } 3398 3399 cmd->cmd_flags = 3400 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) | 3401 CFLAG_PREPARED | CFLAG_IN_TRANSPORT; 3402 3403 return (TRAN_ACCEPT); 3404 } 3405 3406 /* 3407 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command 3408 * 3409 * One of three possibilities: 3410 * - allocate scsi_pkt 3411 * - allocate scsi_pkt and DMA resources 3412 * - allocate DMA resources to an already-allocated pkt 3413 */ 3414 static struct scsi_pkt * 3415 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt, 3416 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags, 3417 int (*callback)(), caddr_t arg) 3418 { 3419 mptsas_cmd_t *cmd, *new_cmd; 3420 mptsas_t *mpt = ADDR2MPT(ap); 3421 int failure = 1; 3422 uint_t oldcookiec; 3423 mptsas_target_t *ptgt = NULL; 3424 int rval; 3425 mptsas_tgt_private_t *tgt_private; 3426 int kf; 3427 3428 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP; 3429 3430 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 3431 tran_tgt_private; 3432 ASSERT(tgt_private != NULL); 3433 if (tgt_private == NULL) { 3434 return (NULL); 3435 } 3436 ptgt = tgt_private->t_private; 3437 ASSERT(ptgt != NULL); 3438 if (ptgt == NULL) 3439 return (NULL); 3440 ap->a_target = ptgt->m_devhdl; 3441 ap->a_lun = tgt_private->t_lun; 3442 3443 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC); 3444 #ifdef MPTSAS_TEST_EXTRN_ALLOC 3445 statuslen *= 100; tgtlen *= 4; 3446 #endif 3447 NDBG3(("mptsas_scsi_init_pkt:\n" 3448 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x", 3449 ap->a_target, (void *)pkt, (void *)bp, 3450 cmdlen, statuslen, tgtlen, flags)); 3451 3452 /* 3453 * Allocate the new packet. 3454 */ 3455 if (pkt == NULL) { 3456 ddi_dma_handle_t save_dma_handle; 3457 ddi_dma_handle_t save_arq_dma_handle; 3458 struct buf *save_arq_bp; 3459 ddi_dma_cookie_t save_arqcookie; 3460 3461 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf); 3462 3463 if (cmd) { 3464 save_dma_handle = cmd->cmd_dmahandle; 3465 save_arq_dma_handle = cmd->cmd_arqhandle; 3466 save_arq_bp = cmd->cmd_arq_buf; 3467 save_arqcookie = cmd->cmd_arqcookie; 3468 bzero(cmd, sizeof (*cmd) + scsi_pkt_size()); 3469 cmd->cmd_dmahandle = save_dma_handle; 3470 cmd->cmd_arqhandle = save_arq_dma_handle; 3471 cmd->cmd_arq_buf = save_arq_bp; 3472 cmd->cmd_arqcookie = save_arqcookie; 3473 3474 pkt = (void *)((uchar_t *)cmd + 3475 sizeof (struct mptsas_cmd)); 3476 pkt->pkt_ha_private = (opaque_t)cmd; 3477 pkt->pkt_address = *ap; 3478 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private; 3479 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 3480 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb; 3481 cmd->cmd_pkt = (struct scsi_pkt *)pkt; 3482 cmd->cmd_cdblen = (uchar_t)cmdlen; 3483 cmd->cmd_scblen = statuslen; 3484 cmd->cmd_rqslen = SENSE_LENGTH; 3485 cmd->cmd_tgt_addr = ptgt; 3486 failure = 0; 3487 } 3488 3489 if (failure || (cmdlen > sizeof (cmd->cmd_cdb)) || 3490 (tgtlen > PKT_PRIV_LEN) || 3491 (statuslen > EXTCMDS_STATUS_SIZE)) { 3492 if (failure == 0) { 3493 /* 3494 * if extern alloc fails, all will be 3495 * deallocated, including cmd 3496 */ 3497 failure = mptsas_pkt_alloc_extern(mpt, cmd, 3498 cmdlen, tgtlen, statuslen, kf); 3499 } 3500 if (failure) { 3501 /* 3502 * if extern allocation fails, it will 3503 * deallocate the new pkt as well 3504 */ 3505 return (NULL); 3506 } 3507 } 3508 new_cmd = cmd; 3509 3510 } else { 3511 cmd = PKT2CMD(pkt); 3512 new_cmd = NULL; 3513 } 3514 3515 3516 /* grab cmd->cmd_cookiec here as oldcookiec */ 3517 3518 oldcookiec = cmd->cmd_cookiec; 3519 3520 /* 3521 * If the dma was broken up into PARTIAL transfers cmd_nwin will be 3522 * greater than 0 and we'll need to grab the next dma window 3523 */ 3524 /* 3525 * SLM-not doing extra command frame right now; may add later 3526 */ 3527 3528 if (cmd->cmd_nwin > 0) { 3529 3530 /* 3531 * Make sure we havn't gone past the the total number 3532 * of windows 3533 */ 3534 if (++cmd->cmd_winindex >= cmd->cmd_nwin) { 3535 return (NULL); 3536 } 3537 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex, 3538 &cmd->cmd_dma_offset, &cmd->cmd_dma_len, 3539 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) { 3540 return (NULL); 3541 } 3542 goto get_dma_cookies; 3543 } 3544 3545 3546 if (flags & PKT_XARQ) { 3547 cmd->cmd_flags |= CFLAG_XARQ; 3548 } 3549 3550 /* 3551 * DMA resource allocation. This version assumes your 3552 * HBA has some sort of bus-mastering or onboard DMA capability, with a 3553 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the 3554 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget. 3555 */ 3556 if (bp && (bp->b_bcount != 0) && 3557 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) { 3558 3559 int cnt, dma_flags; 3560 mptti_t *dmap; /* ptr to the S/G list */ 3561 3562 /* 3563 * Set up DMA memory and position to the next DMA segment. 3564 */ 3565 ASSERT(cmd->cmd_dmahandle != NULL); 3566 3567 if (bp->b_flags & B_READ) { 3568 dma_flags = DDI_DMA_READ; 3569 cmd->cmd_flags &= ~CFLAG_DMASEND; 3570 } else { 3571 dma_flags = DDI_DMA_WRITE; 3572 cmd->cmd_flags |= CFLAG_DMASEND; 3573 } 3574 if (flags & PKT_CONSISTENT) { 3575 cmd->cmd_flags |= CFLAG_CMDIOPB; 3576 dma_flags |= DDI_DMA_CONSISTENT; 3577 } 3578 3579 if (flags & PKT_DMA_PARTIAL) { 3580 dma_flags |= DDI_DMA_PARTIAL; 3581 } 3582 3583 /* 3584 * workaround for byte hole issue on psycho and 3585 * schizo pre 2.1 3586 */ 3587 if ((bp->b_flags & B_READ) && ((bp->b_flags & 3588 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) && 3589 ((uintptr_t)bp->b_un.b_addr & 0x7)) { 3590 dma_flags |= DDI_DMA_CONSISTENT; 3591 } 3592 3593 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp, 3594 dma_flags, callback, arg, 3595 &cmd->cmd_cookie, &cmd->cmd_cookiec); 3596 if (rval == DDI_DMA_PARTIAL_MAP) { 3597 (void) ddi_dma_numwin(cmd->cmd_dmahandle, 3598 &cmd->cmd_nwin); 3599 cmd->cmd_winindex = 0; 3600 (void) ddi_dma_getwin(cmd->cmd_dmahandle, 3601 cmd->cmd_winindex, &cmd->cmd_dma_offset, 3602 &cmd->cmd_dma_len, &cmd->cmd_cookie, 3603 &cmd->cmd_cookiec); 3604 } else if (rval && (rval != DDI_DMA_MAPPED)) { 3605 switch (rval) { 3606 case DDI_DMA_NORESOURCES: 3607 bioerror(bp, 0); 3608 break; 3609 case DDI_DMA_BADATTR: 3610 case DDI_DMA_NOMAPPING: 3611 bioerror(bp, EFAULT); 3612 break; 3613 case DDI_DMA_TOOBIG: 3614 default: 3615 bioerror(bp, EINVAL); 3616 break; 3617 } 3618 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3619 if (new_cmd) { 3620 mptsas_scsi_destroy_pkt(ap, pkt); 3621 } 3622 return ((struct scsi_pkt *)NULL); 3623 } 3624 3625 get_dma_cookies: 3626 cmd->cmd_flags |= CFLAG_DMAVALID; 3627 ASSERT(cmd->cmd_cookiec > 0); 3628 3629 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) { 3630 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n", 3631 cmd->cmd_cookiec); 3632 bioerror(bp, EINVAL); 3633 if (new_cmd) { 3634 mptsas_scsi_destroy_pkt(ap, pkt); 3635 } 3636 return ((struct scsi_pkt *)NULL); 3637 } 3638 3639 /* 3640 * Allocate extra SGL buffer if needed. 3641 */ 3642 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) && 3643 (cmd->cmd_extra_frames == NULL)) { 3644 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) == 3645 DDI_FAILURE) { 3646 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc " 3647 "failed"); 3648 bioerror(bp, ENOMEM); 3649 if (new_cmd) { 3650 mptsas_scsi_destroy_pkt(ap, pkt); 3651 } 3652 return ((struct scsi_pkt *)NULL); 3653 } 3654 } 3655 3656 /* 3657 * Always use scatter-gather transfer 3658 * Use the loop below to store physical addresses of 3659 * DMA segments, from the DMA cookies, into your HBA's 3660 * scatter-gather list. 3661 * We need to ensure we have enough kmem alloc'd 3662 * for the sg entries since we are no longer using an 3663 * array inside mptsas_cmd_t. 3664 * 3665 * We check cmd->cmd_cookiec against oldcookiec so 3666 * the scatter-gather list is correctly allocated 3667 */ 3668 3669 if (oldcookiec != cmd->cmd_cookiec) { 3670 if (cmd->cmd_sg != (mptti_t *)NULL) { 3671 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * 3672 oldcookiec); 3673 cmd->cmd_sg = NULL; 3674 } 3675 } 3676 3677 if (cmd->cmd_sg == (mptti_t *)NULL) { 3678 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3679 cmd->cmd_cookiec), kf); 3680 3681 if (cmd->cmd_sg == (mptti_t *)NULL) { 3682 mptsas_log(mpt, CE_WARN, 3683 "unable to kmem_alloc enough memory " 3684 "for scatter/gather list"); 3685 /* 3686 * if we have an ENOMEM condition we need to behave 3687 * the same way as the rest of this routine 3688 */ 3689 3690 bioerror(bp, ENOMEM); 3691 if (new_cmd) { 3692 mptsas_scsi_destroy_pkt(ap, pkt); 3693 } 3694 return ((struct scsi_pkt *)NULL); 3695 } 3696 } 3697 3698 dmap = cmd->cmd_sg; 3699 3700 ASSERT(cmd->cmd_cookie.dmac_size != 0); 3701 3702 /* 3703 * store the first segment into the S/G list 3704 */ 3705 dmap->count = cmd->cmd_cookie.dmac_size; 3706 dmap->addr.address64.Low = (uint32_t) 3707 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3708 dmap->addr.address64.High = (uint32_t) 3709 (cmd->cmd_cookie.dmac_laddress >> 32); 3710 3711 /* 3712 * dmacount counts the size of the dma for this window 3713 * (if partial dma is being used). totaldmacount 3714 * keeps track of the total amount of dma we have 3715 * transferred for all the windows (needed to calculate 3716 * the resid value below). 3717 */ 3718 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size; 3719 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3720 3721 /* 3722 * We already stored the first DMA scatter gather segment, 3723 * start at 1 if we need to store more. 3724 */ 3725 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) { 3726 /* 3727 * Get next DMA cookie 3728 */ 3729 ddi_dma_nextcookie(cmd->cmd_dmahandle, 3730 &cmd->cmd_cookie); 3731 dmap++; 3732 3733 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size; 3734 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3735 3736 /* 3737 * store the segment parms into the S/G list 3738 */ 3739 dmap->count = cmd->cmd_cookie.dmac_size; 3740 dmap->addr.address64.Low = (uint32_t) 3741 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3742 dmap->addr.address64.High = (uint32_t) 3743 (cmd->cmd_cookie.dmac_laddress >> 32); 3744 } 3745 3746 /* 3747 * If this was partially allocated we set the resid 3748 * the amount of data NOT transferred in this window 3749 * If there is only one window, the resid will be 0 3750 */ 3751 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount); 3752 NDBG16(("mptsas_dmaget: cmd_dmacount=%d.", cmd->cmd_dmacount)); 3753 } 3754 return (pkt); 3755 } 3756 3757 /* 3758 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation 3759 * 3760 * Notes: 3761 * - also frees DMA resources if allocated 3762 * - implicit DMA synchonization 3763 */ 3764 static void 3765 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 3766 { 3767 mptsas_cmd_t *cmd = PKT2CMD(pkt); 3768 mptsas_t *mpt = ADDR2MPT(ap); 3769 3770 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p", 3771 ap->a_target, (void *)pkt)); 3772 3773 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3774 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 3775 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3776 } 3777 3778 if (cmd->cmd_sg) { 3779 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec); 3780 cmd->cmd_sg = NULL; 3781 } 3782 3783 mptsas_free_extra_sgl_frame(mpt, cmd); 3784 3785 if ((cmd->cmd_flags & 3786 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN | 3787 CFLAG_SCBEXTERN)) == 0) { 3788 cmd->cmd_flags = CFLAG_FREE; 3789 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 3790 } else { 3791 mptsas_pkt_destroy_extern(mpt, cmd); 3792 } 3793 } 3794 3795 /* 3796 * kmem cache constructor and destructor: 3797 * When constructing, we bzero the cmd and allocate the dma handle 3798 * When destructing, just free the dma handle 3799 */ 3800 static int 3801 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags) 3802 { 3803 mptsas_cmd_t *cmd = buf; 3804 mptsas_t *mpt = cdrarg; 3805 struct scsi_address ap; 3806 uint_t cookiec; 3807 ddi_dma_attr_t arq_dma_attr; 3808 int (*callback)(caddr_t); 3809 3810 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 3811 3812 NDBG4(("mptsas_kmem_cache_constructor")); 3813 3814 ap.a_hba_tran = mpt->m_tran; 3815 ap.a_target = 0; 3816 ap.a_lun = 0; 3817 3818 /* 3819 * allocate a dma handle 3820 */ 3821 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback, 3822 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) { 3823 cmd->cmd_dmahandle = NULL; 3824 return (-1); 3825 } 3826 3827 cmd->cmd_arq_buf = scsi_alloc_consistent_buf(&ap, (struct buf *)NULL, 3828 SENSE_LENGTH, B_READ, callback, NULL); 3829 if (cmd->cmd_arq_buf == NULL) { 3830 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3831 cmd->cmd_dmahandle = NULL; 3832 return (-1); 3833 } 3834 3835 /* 3836 * allocate a arq handle 3837 */ 3838 arq_dma_attr = mpt->m_msg_dma_attr; 3839 arq_dma_attr.dma_attr_sgllen = 1; 3840 if ((ddi_dma_alloc_handle(mpt->m_dip, &arq_dma_attr, callback, 3841 NULL, &cmd->cmd_arqhandle)) != DDI_SUCCESS) { 3842 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3843 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3844 cmd->cmd_dmahandle = NULL; 3845 cmd->cmd_arqhandle = NULL; 3846 return (-1); 3847 } 3848 3849 if (ddi_dma_buf_bind_handle(cmd->cmd_arqhandle, 3850 cmd->cmd_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT), 3851 callback, NULL, &cmd->cmd_arqcookie, &cookiec) != DDI_SUCCESS) { 3852 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3853 ddi_dma_free_handle(&cmd->cmd_arqhandle); 3854 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3855 cmd->cmd_dmahandle = NULL; 3856 cmd->cmd_arqhandle = NULL; 3857 cmd->cmd_arq_buf = NULL; 3858 return (-1); 3859 } 3860 3861 return (0); 3862 } 3863 3864 static void 3865 mptsas_kmem_cache_destructor(void *buf, void *cdrarg) 3866 { 3867 #ifndef __lock_lint 3868 _NOTE(ARGUNUSED(cdrarg)) 3869 #endif 3870 mptsas_cmd_t *cmd = buf; 3871 3872 NDBG4(("mptsas_kmem_cache_destructor")); 3873 3874 if (cmd->cmd_arqhandle) { 3875 (void) ddi_dma_unbind_handle(cmd->cmd_arqhandle); 3876 ddi_dma_free_handle(&cmd->cmd_arqhandle); 3877 cmd->cmd_arqhandle = NULL; 3878 } 3879 if (cmd->cmd_arq_buf) { 3880 scsi_free_consistent_buf(cmd->cmd_arq_buf); 3881 cmd->cmd_arq_buf = NULL; 3882 } 3883 if (cmd->cmd_dmahandle) { 3884 ddi_dma_free_handle(&cmd->cmd_dmahandle); 3885 cmd->cmd_dmahandle = NULL; 3886 } 3887 } 3888 3889 static int 3890 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags) 3891 { 3892 mptsas_cache_frames_t *p = buf; 3893 mptsas_t *mpt = cdrarg; 3894 ddi_dma_attr_t frame_dma_attr; 3895 size_t mem_size, alloc_len; 3896 ddi_dma_cookie_t cookie; 3897 uint_t ncookie; 3898 int (*callback)(caddr_t) = (kmflags == KM_SLEEP) 3899 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 3900 3901 frame_dma_attr = mpt->m_msg_dma_attr; 3902 frame_dma_attr.dma_attr_align = 0x10; 3903 frame_dma_attr.dma_attr_sgllen = 1; 3904 3905 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL, 3906 &p->m_dma_hdl) != DDI_SUCCESS) { 3907 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for" 3908 " extra SGL."); 3909 return (DDI_FAILURE); 3910 } 3911 3912 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size; 3913 3914 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr, 3915 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr, 3916 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) { 3917 ddi_dma_free_handle(&p->m_dma_hdl); 3918 p->m_dma_hdl = NULL; 3919 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for" 3920 " extra SGL."); 3921 return (DDI_FAILURE); 3922 } 3923 3924 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr, 3925 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL, 3926 &cookie, &ncookie) != DDI_DMA_MAPPED) { 3927 (void) ddi_dma_mem_free(&p->m_acc_hdl); 3928 ddi_dma_free_handle(&p->m_dma_hdl); 3929 p->m_dma_hdl = NULL; 3930 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for" 3931 " extra SGL"); 3932 return (DDI_FAILURE); 3933 } 3934 3935 /* 3936 * Store the SGL memory address. This chip uses this 3937 * address to dma to and from the driver. The second 3938 * address is the address mpt uses to fill in the SGL. 3939 */ 3940 p->m_phys_addr = cookie.dmac_address; 3941 3942 return (DDI_SUCCESS); 3943 } 3944 3945 static void 3946 mptsas_cache_frames_destructor(void *buf, void *cdrarg) 3947 { 3948 #ifndef __lock_lint 3949 _NOTE(ARGUNUSED(cdrarg)) 3950 #endif 3951 mptsas_cache_frames_t *p = buf; 3952 if (p->m_dma_hdl != NULL) { 3953 (void) ddi_dma_unbind_handle(p->m_dma_hdl); 3954 (void) ddi_dma_mem_free(&p->m_acc_hdl); 3955 ddi_dma_free_handle(&p->m_dma_hdl); 3956 p->m_phys_addr = NULL; 3957 p->m_frames_addr = NULL; 3958 p->m_dma_hdl = NULL; 3959 p->m_acc_hdl = NULL; 3960 } 3961 3962 } 3963 3964 /* 3965 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd) 3966 * for non-standard length cdb, pkt_private, status areas 3967 * if allocation fails, then deallocate all external space and the pkt 3968 */ 3969 /* ARGSUSED */ 3970 static int 3971 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 3972 int cmdlen, int tgtlen, int statuslen, int kf) 3973 { 3974 caddr_t cdbp, scbp, tgt; 3975 int (*callback)(caddr_t) = (kf == KM_SLEEP) ? 3976 DDI_DMA_SLEEP : DDI_DMA_DONTWAIT; 3977 struct scsi_address ap; 3978 size_t senselength; 3979 ddi_dma_attr_t ext_arq_dma_attr; 3980 uint_t cookiec; 3981 3982 NDBG3(("mptsas_pkt_alloc_extern: " 3983 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x", 3984 (void *)cmd, cmdlen, tgtlen, statuslen, kf)); 3985 3986 tgt = cdbp = scbp = NULL; 3987 cmd->cmd_scblen = statuslen; 3988 cmd->cmd_privlen = (uchar_t)tgtlen; 3989 3990 if (cmdlen > sizeof (cmd->cmd_cdb)) { 3991 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) { 3992 goto fail; 3993 } 3994 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp; 3995 cmd->cmd_flags |= CFLAG_CDBEXTERN; 3996 } 3997 if (tgtlen > PKT_PRIV_LEN) { 3998 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) { 3999 goto fail; 4000 } 4001 cmd->cmd_flags |= CFLAG_PRIVEXTERN; 4002 cmd->cmd_pkt->pkt_private = tgt; 4003 } 4004 if (statuslen > EXTCMDS_STATUS_SIZE) { 4005 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) { 4006 goto fail; 4007 } 4008 cmd->cmd_flags |= CFLAG_SCBEXTERN; 4009 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp; 4010 4011 /* allocate sense data buf for DMA */ 4012 4013 senselength = statuslen - MPTSAS_GET_ITEM_OFF( 4014 struct scsi_arq_status, sts_sensedata); 4015 cmd->cmd_rqslen = (uchar_t)senselength; 4016 4017 ap.a_hba_tran = mpt->m_tran; 4018 ap.a_target = 0; 4019 ap.a_lun = 0; 4020 4021 cmd->cmd_ext_arq_buf = scsi_alloc_consistent_buf(&ap, 4022 (struct buf *)NULL, senselength, B_READ, 4023 callback, NULL); 4024 4025 if (cmd->cmd_ext_arq_buf == NULL) { 4026 goto fail; 4027 } 4028 /* 4029 * allocate a extern arq handle and bind the buf 4030 */ 4031 ext_arq_dma_attr = mpt->m_msg_dma_attr; 4032 ext_arq_dma_attr.dma_attr_sgllen = 1; 4033 if ((ddi_dma_alloc_handle(mpt->m_dip, 4034 &ext_arq_dma_attr, callback, 4035 NULL, &cmd->cmd_ext_arqhandle)) != DDI_SUCCESS) { 4036 goto fail; 4037 } 4038 4039 if (ddi_dma_buf_bind_handle(cmd->cmd_ext_arqhandle, 4040 cmd->cmd_ext_arq_buf, (DDI_DMA_READ | DDI_DMA_CONSISTENT), 4041 callback, NULL, &cmd->cmd_ext_arqcookie, 4042 &cookiec) 4043 != DDI_SUCCESS) { 4044 goto fail; 4045 } 4046 cmd->cmd_flags |= CFLAG_EXTARQBUFVALID; 4047 } 4048 return (0); 4049 fail: 4050 mptsas_pkt_destroy_extern(mpt, cmd); 4051 return (1); 4052 } 4053 4054 /* 4055 * deallocate external pkt space and deallocate the pkt 4056 */ 4057 static void 4058 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd) 4059 { 4060 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd)); 4061 4062 if (cmd->cmd_flags & CFLAG_FREE) { 4063 mptsas_log(mpt, CE_PANIC, 4064 "mptsas_pkt_destroy_extern: freeing free packet"); 4065 _NOTE(NOT_REACHED) 4066 /* NOTREACHED */ 4067 } 4068 if (cmd->cmd_flags & CFLAG_CDBEXTERN) { 4069 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen); 4070 } 4071 if (cmd->cmd_flags & CFLAG_SCBEXTERN) { 4072 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen); 4073 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) { 4074 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle); 4075 } 4076 if (cmd->cmd_ext_arqhandle) { 4077 ddi_dma_free_handle(&cmd->cmd_ext_arqhandle); 4078 cmd->cmd_ext_arqhandle = NULL; 4079 } 4080 if (cmd->cmd_ext_arq_buf) 4081 scsi_free_consistent_buf(cmd->cmd_ext_arq_buf); 4082 } 4083 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) { 4084 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen); 4085 } 4086 cmd->cmd_flags = CFLAG_FREE; 4087 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4088 } 4089 4090 /* 4091 * tran_sync_pkt(9E) - explicit DMA synchronization 4092 */ 4093 /*ARGSUSED*/ 4094 static void 4095 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4096 { 4097 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4098 4099 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p", 4100 ap->a_target, (void *)pkt)); 4101 4102 if (cmd->cmd_dmahandle) { 4103 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4104 (cmd->cmd_flags & CFLAG_DMASEND) ? 4105 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 4106 } 4107 } 4108 4109 /* 4110 * tran_dmafree(9E) - deallocate DMA resources allocated for command 4111 */ 4112 /*ARGSUSED*/ 4113 static void 4114 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 4115 { 4116 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4117 mptsas_t *mpt = ADDR2MPT(ap); 4118 4119 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p", 4120 ap->a_target, (void *)pkt)); 4121 4122 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4123 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4124 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4125 } 4126 4127 if (cmd->cmd_flags & CFLAG_EXTARQBUFVALID) { 4128 (void) ddi_dma_unbind_handle(cmd->cmd_ext_arqhandle); 4129 cmd->cmd_flags &= ~CFLAG_EXTARQBUFVALID; 4130 } 4131 4132 mptsas_free_extra_sgl_frame(mpt, cmd); 4133 } 4134 4135 static void 4136 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd) 4137 { 4138 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 4139 (!(cmd->cmd_flags & CFLAG_DMASEND))) { 4140 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4141 DDI_DMA_SYNC_FORCPU); 4142 } 4143 (*pkt->pkt_comp)(pkt); 4144 } 4145 4146 static void 4147 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control, 4148 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4149 { 4150 uint_t cookiec; 4151 mptti_t *dmap; 4152 uint32_t flags; 4153 pMpi2SGESimple64_t sge; 4154 pMpi2SGEChain64_t sgechain; 4155 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID); 4156 4157 /* 4158 * Save the number of entries in the DMA 4159 * Scatter/Gather list 4160 */ 4161 cookiec = cmd->cmd_cookiec; 4162 4163 NDBG1(("mptsas_sge_setup: cookiec=%d", cookiec)); 4164 4165 /* 4166 * Set read/write bit in control. 4167 */ 4168 if (cmd->cmd_flags & CFLAG_DMASEND) { 4169 *control |= MPI2_SCSIIO_CONTROL_WRITE; 4170 } else { 4171 *control |= MPI2_SCSIIO_CONTROL_READ; 4172 } 4173 4174 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount); 4175 4176 /* 4177 * We have 2 cases here. First where we can fit all the 4178 * SG elements into the main frame, and the case 4179 * where we can't. 4180 * If we have more cookies than we can attach to a frame 4181 * we will need to use a chain element to point 4182 * a location of memory where the rest of the S/G 4183 * elements reside. 4184 */ 4185 if (cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) { 4186 dmap = cmd->cmd_sg; 4187 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4188 while (cookiec--) { 4189 ddi_put32(acc_hdl, 4190 &sge->Address.Low, dmap->addr.address64.Low); 4191 ddi_put32(acc_hdl, 4192 &sge->Address.High, dmap->addr.address64.High); 4193 ddi_put32(acc_hdl, &sge->FlagsLength, 4194 dmap->count); 4195 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4196 flags |= ((uint32_t) 4197 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4198 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4199 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4200 MPI2_SGE_FLAGS_SHIFT); 4201 4202 /* 4203 * If this is the last cookie, we set the flags 4204 * to indicate so 4205 */ 4206 if (cookiec == 0) { 4207 flags |= 4208 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT 4209 | MPI2_SGE_FLAGS_END_OF_BUFFER 4210 | MPI2_SGE_FLAGS_END_OF_LIST) << 4211 MPI2_SGE_FLAGS_SHIFT); 4212 } 4213 if (cmd->cmd_flags & CFLAG_DMASEND) { 4214 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC << 4215 MPI2_SGE_FLAGS_SHIFT); 4216 } else { 4217 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST << 4218 MPI2_SGE_FLAGS_SHIFT); 4219 } 4220 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4221 dmap++; 4222 sge++; 4223 } 4224 } else { 4225 /* 4226 * Hereby we start to deal with multiple frames. 4227 * The process is as follows: 4228 * 1. Determine how many frames are needed for SGL element 4229 * storage; Note that all frames are stored in contiguous 4230 * memory space and in 64-bit DMA mode each element is 4231 * 3 double-words (12 bytes) long. 4232 * 2. Fill up the main frame. We need to do this separately 4233 * since it contains the SCSI IO request header and needs 4234 * dedicated processing. Note that the last 4 double-words 4235 * of the SCSI IO header is for SGL element storage 4236 * (MPI2_SGE_IO_UNION). 4237 * 3. Fill the chain element in the main frame, so the DMA 4238 * engine can use the following frames. 4239 * 4. Enter a loop to fill the remaining frames. Note that the 4240 * last frame contains no chain element. The remaining 4241 * frames go into the mpt SGL buffer allocated on the fly, 4242 * not immediately following the main message frame, as in 4243 * Gen1. 4244 * Some restrictions: 4245 * 1. For 64-bit DMA, the simple element and chain element 4246 * are both of 3 double-words (12 bytes) in size, even 4247 * though all frames are stored in the first 4G of mem 4248 * range and the higher 32-bits of the address are always 0. 4249 * 2. On some controllers (like the 1064/1068), a frame can 4250 * hold SGL elements with the last 1 or 2 double-words 4251 * (4 or 8 bytes) un-used. On these controllers, we should 4252 * recognize that there's not enough room for another SGL 4253 * element and move the sge pointer to the next frame. 4254 */ 4255 int i, j, k, l, frames, sgemax; 4256 int temp; 4257 uint8_t chainflags; 4258 uint16_t chainlength; 4259 mptsas_cache_frames_t *p; 4260 4261 /* 4262 * Sgemax is the number of SGE's that will fit 4263 * each extra frame and frames is total 4264 * number of frames we'll need. 1 sge entry per 4265 * frame is reseverd for the chain element thus the -1 below. 4266 */ 4267 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) 4268 - 1); 4269 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4270 4271 /* 4272 * A little check to see if we need to round up the number 4273 * of frames we need 4274 */ 4275 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4276 sgemax) > 1) { 4277 frames = (temp + 1); 4278 } else { 4279 frames = temp; 4280 } 4281 dmap = cmd->cmd_sg; 4282 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4283 4284 /* 4285 * First fill in the main frame 4286 */ 4287 for (j = 1; j < MPTSAS_MAX_FRAME_SGES64(mpt); j++) { 4288 ddi_put32(acc_hdl, &sge->Address.Low, 4289 dmap->addr.address64.Low); 4290 ddi_put32(acc_hdl, &sge->Address.High, 4291 dmap->addr.address64.High); 4292 ddi_put32(acc_hdl, &sge->FlagsLength, dmap->count); 4293 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4294 flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4295 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4296 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4297 MPI2_SGE_FLAGS_SHIFT); 4298 4299 /* 4300 * If this is the last SGE of this frame 4301 * we set the end of list flag 4302 */ 4303 if (j == (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) { 4304 flags |= ((uint32_t) 4305 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4306 MPI2_SGE_FLAGS_SHIFT); 4307 } 4308 if (cmd->cmd_flags & CFLAG_DMASEND) { 4309 flags |= 4310 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4311 MPI2_SGE_FLAGS_SHIFT); 4312 } else { 4313 flags |= 4314 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4315 MPI2_SGE_FLAGS_SHIFT); 4316 } 4317 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4318 dmap++; 4319 sge++; 4320 } 4321 4322 /* 4323 * Fill in the chain element in the main frame. 4324 * About calculation on ChainOffset: 4325 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4326 * in the end reserved for SGL element storage 4327 * (MPI2_SGE_IO_UNION); we should count it in our 4328 * calculation. See its definition in the header file. 4329 * 2. Constant j is the counter of the current SGL element 4330 * that will be processed, and (j - 1) is the number of 4331 * SGL elements that have been processed (stored in the 4332 * main frame). 4333 * 3. ChainOffset value should be in units of double-words (4 4334 * bytes) so the last value should be divided by 4. 4335 */ 4336 ddi_put8(acc_hdl, &frame->ChainOffset, 4337 (sizeof (MPI2_SCSI_IO_REQUEST) - 4338 sizeof (MPI2_SGE_IO_UNION) + 4339 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4340 sgechain = (pMpi2SGEChain64_t)sge; 4341 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4342 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4343 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4344 ddi_put8(acc_hdl, &sgechain->Flags, chainflags); 4345 4346 /* 4347 * The size of the next frame is the accurate size of space 4348 * (in bytes) used to store the SGL elements. j is the counter 4349 * of SGL elements. (j - 1) is the number of SGL elements that 4350 * have been processed (stored in frames). 4351 */ 4352 if (frames >= 2) { 4353 chainlength = mpt->m_req_frame_size / 4354 sizeof (MPI2_SGE_SIMPLE64) * 4355 sizeof (MPI2_SGE_SIMPLE64); 4356 } else { 4357 chainlength = ((cookiec - (j - 1)) * 4358 sizeof (MPI2_SGE_SIMPLE64)); 4359 } 4360 4361 p = cmd->cmd_extra_frames; 4362 4363 ddi_put16(acc_hdl, &sgechain->Length, chainlength); 4364 ddi_put32(acc_hdl, &sgechain->Address.Low, 4365 p->m_phys_addr); 4366 /* SGL is allocated in the first 4G mem range */ 4367 ddi_put32(acc_hdl, &sgechain->Address.High, 0); 4368 4369 /* 4370 * If there are more than 2 frames left we have to 4371 * fill in the next chain offset to the location of 4372 * the chain element in the next frame. 4373 * sgemax is the number of simple elements in an extra 4374 * frame. Note that the value NextChainOffset should be 4375 * in double-words (4 bytes). 4376 */ 4377 if (frames >= 2) { 4378 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 4379 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4380 } else { 4381 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0); 4382 } 4383 4384 /* 4385 * Jump to next frame; 4386 * Starting here, chain buffers go into the per command SGL. 4387 * This buffer is allocated when chain buffers are needed. 4388 */ 4389 sge = (pMpi2SGESimple64_t)p->m_frames_addr; 4390 i = cookiec; 4391 4392 /* 4393 * Start filling in frames with SGE's. If we 4394 * reach the end of frame and still have SGE's 4395 * to fill we need to add a chain element and 4396 * use another frame. j will be our counter 4397 * for what cookie we are at and i will be 4398 * the total cookiec. k is the current frame 4399 */ 4400 for (k = 1; k <= frames; k++) { 4401 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4402 4403 /* 4404 * If we have reached the end of frame 4405 * and we have more SGE's to fill in 4406 * we have to fill the final entry 4407 * with a chain element and then 4408 * continue to the next frame 4409 */ 4410 if ((l == (sgemax + 1)) && (k != frames)) { 4411 sgechain = (pMpi2SGEChain64_t)sge; 4412 j--; 4413 chainflags = ( 4414 MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4415 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4416 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4417 ddi_put8(p->m_acc_hdl, 4418 &sgechain->Flags, chainflags); 4419 /* 4420 * k is the frame counter and (k + 1) 4421 * is the number of the next frame. 4422 * Note that frames are in contiguous 4423 * memory space. 4424 */ 4425 ddi_put32(p->m_acc_hdl, 4426 &sgechain->Address.Low, 4427 (p->m_phys_addr + 4428 (mpt->m_req_frame_size * k))); 4429 ddi_put32(p->m_acc_hdl, 4430 &sgechain->Address.High, 0); 4431 4432 /* 4433 * If there are more than 2 frames left 4434 * we have to next chain offset to 4435 * the location of the chain element 4436 * in the next frame and fill in the 4437 * length of the next chain 4438 */ 4439 if ((frames - k) >= 2) { 4440 ddi_put8(p->m_acc_hdl, 4441 &sgechain->NextChainOffset, 4442 (sgemax * 4443 sizeof (MPI2_SGE_SIMPLE64)) 4444 >> 2); 4445 ddi_put16(p->m_acc_hdl, 4446 &sgechain->Length, 4447 mpt->m_req_frame_size / 4448 sizeof (MPI2_SGE_SIMPLE64) * 4449 sizeof (MPI2_SGE_SIMPLE64)); 4450 } else { 4451 /* 4452 * This is the last frame. Set 4453 * the NextChainOffset to 0 and 4454 * Length is the total size of 4455 * all remaining simple elements 4456 */ 4457 ddi_put8(p->m_acc_hdl, 4458 &sgechain->NextChainOffset, 4459 0); 4460 ddi_put16(p->m_acc_hdl, 4461 &sgechain->Length, 4462 (cookiec - j) * 4463 sizeof (MPI2_SGE_SIMPLE64)); 4464 } 4465 4466 /* Jump to the next frame */ 4467 sge = (pMpi2SGESimple64_t) 4468 ((char *)p->m_frames_addr + 4469 (int)mpt->m_req_frame_size * k); 4470 4471 continue; 4472 } 4473 4474 ddi_put32(p->m_acc_hdl, 4475 &sge->Address.Low, 4476 dmap->addr.address64.Low); 4477 ddi_put32(p->m_acc_hdl, 4478 &sge->Address.High, 4479 dmap->addr.address64.High); 4480 ddi_put32(p->m_acc_hdl, 4481 &sge->FlagsLength, dmap->count); 4482 flags = ddi_get32(p->m_acc_hdl, 4483 &sge->FlagsLength); 4484 flags |= ((uint32_t)( 4485 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4486 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4487 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4488 MPI2_SGE_FLAGS_SHIFT); 4489 4490 /* 4491 * If we are at the end of the frame and 4492 * there is another frame to fill in 4493 * we set the last simple element as last 4494 * element 4495 */ 4496 if ((l == sgemax) && (k != frames)) { 4497 flags |= ((uint32_t) 4498 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4499 MPI2_SGE_FLAGS_SHIFT); 4500 } 4501 4502 /* 4503 * If this is the final cookie we 4504 * indicate it by setting the flags 4505 */ 4506 if (j == i) { 4507 flags |= ((uint32_t) 4508 (MPI2_SGE_FLAGS_LAST_ELEMENT | 4509 MPI2_SGE_FLAGS_END_OF_BUFFER | 4510 MPI2_SGE_FLAGS_END_OF_LIST) << 4511 MPI2_SGE_FLAGS_SHIFT); 4512 } 4513 if (cmd->cmd_flags & CFLAG_DMASEND) { 4514 flags |= 4515 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4516 MPI2_SGE_FLAGS_SHIFT); 4517 } else { 4518 flags |= 4519 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4520 MPI2_SGE_FLAGS_SHIFT); 4521 } 4522 ddi_put32(p->m_acc_hdl, 4523 &sge->FlagsLength, flags); 4524 dmap++; 4525 sge++; 4526 } 4527 } 4528 4529 /* 4530 * Sync DMA with the chain buffers that were just created 4531 */ 4532 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 4533 } 4534 } 4535 4536 /* 4537 * Interrupt handling 4538 * Utility routine. Poll for status of a command sent to HBA 4539 * without interrupts (a FLAG_NOINTR command). 4540 */ 4541 int 4542 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime) 4543 { 4544 int rval = TRUE; 4545 4546 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd)); 4547 4548 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 4549 mptsas_restart_hba(mpt); 4550 } 4551 4552 /* 4553 * Wait, using drv_usecwait(), long enough for the command to 4554 * reasonably return from the target if the target isn't 4555 * "dead". A polled command may well be sent from scsi_poll, and 4556 * there are retries built in to scsi_poll if the transport 4557 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second 4558 * and retries the transport up to scsi_poll_busycnt times 4559 * (currently 60) if 4560 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or 4561 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY 4562 * 4563 * limit the waiting to avoid a hang in the event that the 4564 * cmd never gets started but we are still receiving interrupts 4565 */ 4566 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) { 4567 if (mptsas_wait_intr(mpt, polltime) == FALSE) { 4568 NDBG5(("mptsas_poll: command incomplete")); 4569 rval = FALSE; 4570 break; 4571 } 4572 } 4573 4574 if (rval == FALSE) { 4575 4576 /* 4577 * this isn't supposed to happen, the hba must be wedged 4578 * Mark this cmd as a timeout. 4579 */ 4580 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT, 4581 (STAT_TIMEOUT|STAT_ABORTED)); 4582 4583 if (poll_cmd->cmd_queued == FALSE) { 4584 4585 NDBG5(("mptsas_poll: not on waitq")); 4586 4587 poll_cmd->cmd_pkt->pkt_state |= 4588 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD); 4589 } else { 4590 4591 /* find and remove it from the waitq */ 4592 NDBG5(("mptsas_poll: delete from waitq")); 4593 mptsas_waitq_delete(mpt, poll_cmd); 4594 } 4595 4596 } 4597 mptsas_fma_check(mpt, poll_cmd); 4598 NDBG5(("mptsas_poll: done")); 4599 return (rval); 4600 } 4601 4602 /* 4603 * Used for polling cmds and TM function 4604 */ 4605 static int 4606 mptsas_wait_intr(mptsas_t *mpt, int polltime) 4607 { 4608 int cnt; 4609 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 4610 uint32_t int_mask; 4611 4612 NDBG5(("mptsas_wait_intr")); 4613 4614 mpt->m_polled_intr = 1; 4615 4616 /* 4617 * Get the current interrupt mask and disable interrupts. When 4618 * re-enabling ints, set mask to saved value. 4619 */ 4620 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask); 4621 MPTSAS_DISABLE_INTR(mpt); 4622 4623 /* 4624 * Keep polling for at least (polltime * 1000) seconds 4625 */ 4626 for (cnt = 0; cnt < polltime; cnt++) { 4627 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 4628 DDI_DMA_SYNC_FORCPU); 4629 4630 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 4631 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 4632 4633 if (ddi_get32(mpt->m_acc_post_queue_hdl, 4634 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 4635 ddi_get32(mpt->m_acc_post_queue_hdl, 4636 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 4637 drv_usecwait(1000); 4638 continue; 4639 } 4640 4641 /* 4642 * The reply is valid, process it according to its 4643 * type. 4644 */ 4645 mptsas_process_intr(mpt, reply_desc_union); 4646 4647 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 4648 mpt->m_post_index = 0; 4649 } 4650 4651 /* 4652 * Update the global reply index 4653 */ 4654 ddi_put32(mpt->m_datap, 4655 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 4656 mpt->m_polled_intr = 0; 4657 4658 /* 4659 * Re-enable interrupts and quit. 4660 */ 4661 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, 4662 int_mask); 4663 return (TRUE); 4664 4665 } 4666 4667 /* 4668 * Clear polling flag, re-enable interrupts and quit. 4669 */ 4670 mpt->m_polled_intr = 0; 4671 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask); 4672 return (FALSE); 4673 } 4674 4675 static void 4676 mptsas_handle_scsi_io_success(mptsas_t *mpt, 4677 pMpi2ReplyDescriptorsUnion_t reply_desc) 4678 { 4679 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success; 4680 uint16_t SMID; 4681 mptsas_slots_t *slots = mpt->m_active; 4682 mptsas_cmd_t *cmd = NULL; 4683 struct scsi_pkt *pkt; 4684 4685 ASSERT(mutex_owned(&mpt->m_mutex)); 4686 4687 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc; 4688 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID); 4689 4690 /* 4691 * This is a success reply so just complete the IO. First, do a sanity 4692 * check on the SMID. The final slot is used for TM requests, which 4693 * would not come into this reply handler. 4694 */ 4695 if ((SMID == 0) || (SMID > slots->m_n_slots)) { 4696 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 4697 SMID); 4698 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4699 return; 4700 } 4701 4702 cmd = slots->m_slot[SMID]; 4703 4704 /* 4705 * print warning and return if the slot is empty 4706 */ 4707 if (cmd == NULL) { 4708 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 4709 "in slot %d", SMID); 4710 return; 4711 } 4712 4713 pkt = CMD2PKT(cmd); 4714 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 4715 STATE_GOT_STATUS); 4716 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4717 pkt->pkt_state |= STATE_XFERRED_DATA; 4718 } 4719 pkt->pkt_resid = 0; 4720 4721 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 4722 cmd->cmd_flags |= CFLAG_FINISHED; 4723 cv_broadcast(&mpt->m_passthru_cv); 4724 return; 4725 } else { 4726 mptsas_remove_cmd(mpt, cmd); 4727 } 4728 4729 if (cmd->cmd_flags & CFLAG_RETRY) { 4730 /* 4731 * The target returned QFULL or busy, do not add tihs 4732 * pkt to the doneq since the hba will retry 4733 * this cmd. 4734 * 4735 * The pkt has already been resubmitted in 4736 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 4737 * Remove this cmd_flag here. 4738 */ 4739 cmd->cmd_flags &= ~CFLAG_RETRY; 4740 } else { 4741 mptsas_doneq_add(mpt, cmd); 4742 } 4743 } 4744 4745 static void 4746 mptsas_handle_address_reply(mptsas_t *mpt, 4747 pMpi2ReplyDescriptorsUnion_t reply_desc) 4748 { 4749 pMpi2AddressReplyDescriptor_t address_reply; 4750 pMPI2DefaultReply_t reply; 4751 mptsas_fw_diagnostic_buffer_t *pBuffer; 4752 uint32_t reply_addr; 4753 uint16_t SMID, iocstatus; 4754 mptsas_slots_t *slots = mpt->m_active; 4755 mptsas_cmd_t *cmd = NULL; 4756 uint8_t function, buffer_type; 4757 m_replyh_arg_t *args; 4758 int reply_frame_no; 4759 4760 ASSERT(mutex_owned(&mpt->m_mutex)); 4761 4762 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc; 4763 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl, 4764 &address_reply->ReplyFrameAddress); 4765 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID); 4766 4767 /* 4768 * If reply frame is not in the proper range we should ignore this 4769 * message and exit the interrupt handler. 4770 */ 4771 if ((reply_addr < mpt->m_reply_frame_dma_addr) || 4772 (reply_addr >= (mpt->m_reply_frame_dma_addr + 4773 (mpt->m_reply_frame_size * mpt->m_max_replies))) || 4774 ((reply_addr - mpt->m_reply_frame_dma_addr) % 4775 mpt->m_reply_frame_size != 0)) { 4776 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame " 4777 "address 0x%x\n", reply_addr); 4778 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 4779 return; 4780 } 4781 4782 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 4783 DDI_DMA_SYNC_FORCPU); 4784 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr - 4785 mpt->m_reply_frame_dma_addr)); 4786 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function); 4787 4788 /* 4789 * don't get slot information and command for events since these values 4790 * don't exist 4791 */ 4792 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) && 4793 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) { 4794 /* 4795 * This could be a TM reply, which use the last allocated SMID, 4796 * so allow for that. 4797 */ 4798 if ((SMID == 0) || (SMID > (slots->m_n_slots + 1))) { 4799 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of " 4800 "%d\n", SMID); 4801 ddi_fm_service_impact(mpt->m_dip, 4802 DDI_SERVICE_UNAFFECTED); 4803 return; 4804 } 4805 4806 cmd = slots->m_slot[SMID]; 4807 4808 /* 4809 * print warning and return if the slot is empty 4810 */ 4811 if (cmd == NULL) { 4812 mptsas_log(mpt, CE_WARN, "?NULL command for address " 4813 "reply in slot %d", SMID); 4814 return; 4815 } 4816 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 4817 (cmd->cmd_flags & CFLAG_CONFIG) || 4818 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 4819 cmd->cmd_rfm = reply_addr; 4820 cmd->cmd_flags |= CFLAG_FINISHED; 4821 cv_broadcast(&mpt->m_passthru_cv); 4822 cv_broadcast(&mpt->m_config_cv); 4823 cv_broadcast(&mpt->m_fw_diag_cv); 4824 return; 4825 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) { 4826 mptsas_remove_cmd(mpt, cmd); 4827 } 4828 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID)); 4829 } 4830 /* 4831 * Depending on the function, we need to handle 4832 * the reply frame (and cmd) differently. 4833 */ 4834 switch (function) { 4835 case MPI2_FUNCTION_SCSI_IO_REQUEST: 4836 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd); 4837 break; 4838 case MPI2_FUNCTION_SCSI_TASK_MGMT: 4839 cmd->cmd_rfm = reply_addr; 4840 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply, 4841 cmd); 4842 break; 4843 case MPI2_FUNCTION_FW_DOWNLOAD: 4844 cmd->cmd_flags |= CFLAG_FINISHED; 4845 cv_signal(&mpt->m_fw_cv); 4846 break; 4847 case MPI2_FUNCTION_EVENT_NOTIFICATION: 4848 reply_frame_no = (reply_addr - mpt->m_reply_frame_dma_addr) / 4849 mpt->m_reply_frame_size; 4850 args = &mpt->m_replyh_args[reply_frame_no]; 4851 args->mpt = (void *)mpt; 4852 args->rfm = reply_addr; 4853 4854 /* 4855 * Record the event if its type is enabled in 4856 * this mpt instance by ioctl. 4857 */ 4858 mptsas_record_event(args); 4859 4860 /* 4861 * Handle time critical events 4862 * NOT_RESPONDING/ADDED only now 4863 */ 4864 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) { 4865 /* 4866 * Would not return main process, 4867 * just let taskq resolve ack action 4868 * and ack would be sent in taskq thread 4869 */ 4870 NDBG20(("send mptsas_handle_event_sync success")); 4871 } 4872 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event, 4873 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 4874 mptsas_log(mpt, CE_WARN, "No memory available" 4875 "for dispatch taskq"); 4876 /* 4877 * Return the reply frame to the free queue. 4878 */ 4879 ddi_put32(mpt->m_acc_free_queue_hdl, 4880 &((uint32_t *)(void *) 4881 mpt->m_free_queue)[mpt->m_free_index], reply_addr); 4882 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 4883 DDI_DMA_SYNC_FORDEV); 4884 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 4885 mpt->m_free_index = 0; 4886 } 4887 4888 ddi_put32(mpt->m_datap, 4889 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index); 4890 } 4891 return; 4892 case MPI2_FUNCTION_DIAG_BUFFER_POST: 4893 /* 4894 * If SMID is 0, this implies that the reply is due to a 4895 * release function with a status that the buffer has been 4896 * released. Set the buffer flags accordingly. 4897 */ 4898 if (SMID == 0) { 4899 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 4900 &reply->IOCStatus); 4901 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl, 4902 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType)); 4903 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) { 4904 pBuffer = 4905 &mpt->m_fw_diag_buffer_list[buffer_type]; 4906 pBuffer->valid_data = TRUE; 4907 pBuffer->owned_by_firmware = FALSE; 4908 pBuffer->immediate = FALSE; 4909 } 4910 } else { 4911 /* 4912 * Normal handling of diag post reply with SMID. 4913 */ 4914 cmd = slots->m_slot[SMID]; 4915 4916 /* 4917 * print warning and return if the slot is empty 4918 */ 4919 if (cmd == NULL) { 4920 mptsas_log(mpt, CE_WARN, "?NULL command for " 4921 "address reply in slot %d", SMID); 4922 return; 4923 } 4924 cmd->cmd_rfm = reply_addr; 4925 cmd->cmd_flags |= CFLAG_FINISHED; 4926 cv_broadcast(&mpt->m_fw_diag_cv); 4927 } 4928 return; 4929 default: 4930 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function); 4931 break; 4932 } 4933 4934 /* 4935 * Return the reply frame to the free queue. 4936 */ 4937 ddi_put32(mpt->m_acc_free_queue_hdl, 4938 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 4939 reply_addr); 4940 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 4941 DDI_DMA_SYNC_FORDEV); 4942 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 4943 mpt->m_free_index = 0; 4944 } 4945 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 4946 mpt->m_free_index); 4947 4948 if (cmd->cmd_flags & CFLAG_FW_CMD) 4949 return; 4950 4951 if (cmd->cmd_flags & CFLAG_RETRY) { 4952 /* 4953 * The target returned QFULL or busy, do not add tihs 4954 * pkt to the doneq since the hba will retry 4955 * this cmd. 4956 * 4957 * The pkt has already been resubmitted in 4958 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 4959 * Remove this cmd_flag here. 4960 */ 4961 cmd->cmd_flags &= ~CFLAG_RETRY; 4962 } else { 4963 mptsas_doneq_add(mpt, cmd); 4964 } 4965 } 4966 4967 static void 4968 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 4969 mptsas_cmd_t *cmd) 4970 { 4971 uint8_t scsi_status, scsi_state; 4972 uint16_t ioc_status; 4973 uint32_t xferred, sensecount, responsedata, loginfo = 0; 4974 struct scsi_pkt *pkt; 4975 struct scsi_arq_status *arqstat; 4976 struct buf *bp; 4977 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 4978 uint8_t *sensedata = NULL; 4979 4980 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) == 4981 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) { 4982 bp = cmd->cmd_ext_arq_buf; 4983 } else { 4984 bp = cmd->cmd_arq_buf; 4985 } 4986 4987 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus); 4988 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 4989 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState); 4990 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount); 4991 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount); 4992 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl, 4993 &reply->ResponseInfo); 4994 4995 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 4996 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 4997 &reply->IOCLogInfo); 4998 mptsas_log(mpt, CE_NOTE, 4999 "?Log info 0x%x received for target %d.\n" 5000 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5001 loginfo, Tgt(cmd), scsi_status, ioc_status, 5002 scsi_state); 5003 } 5004 5005 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5006 scsi_status, ioc_status, scsi_state)); 5007 5008 pkt = CMD2PKT(cmd); 5009 *(pkt->pkt_scbp) = scsi_status; 5010 5011 if (loginfo == 0x31170000) { 5012 /* 5013 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY 5014 * 0x31170000 comes, that means the device missing delay 5015 * is in progressing, the command need retry later. 5016 */ 5017 *(pkt->pkt_scbp) = STATUS_BUSY; 5018 return; 5019 } 5020 5021 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) && 5022 ((ioc_status & MPI2_IOCSTATUS_MASK) == 5023 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) { 5024 pkt->pkt_reason = CMD_INCOMPLETE; 5025 pkt->pkt_state |= STATE_GOT_BUS; 5026 if (ptgt->m_reset_delay == 0) { 5027 mptsas_set_throttle(mpt, ptgt, 5028 DRAIN_THROTTLE); 5029 } 5030 return; 5031 } 5032 5033 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) { 5034 responsedata &= 0x000000FF; 5035 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) { 5036 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n"); 5037 pkt->pkt_reason = CMD_TLR_OFF; 5038 return; 5039 } 5040 } 5041 5042 5043 switch (scsi_status) { 5044 case MPI2_SCSI_STATUS_CHECK_CONDITION: 5045 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5046 arqstat = (void*)(pkt->pkt_scbp); 5047 arqstat->sts_rqpkt_status = *((struct scsi_status *) 5048 (pkt->pkt_scbp)); 5049 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 5050 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE); 5051 if (cmd->cmd_flags & CFLAG_XARQ) { 5052 pkt->pkt_state |= STATE_XARQ_DONE; 5053 } 5054 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5055 pkt->pkt_state |= STATE_XFERRED_DATA; 5056 } 5057 arqstat->sts_rqpkt_reason = pkt->pkt_reason; 5058 arqstat->sts_rqpkt_state = pkt->pkt_state; 5059 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA; 5060 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics; 5061 sensedata = (uint8_t *)&arqstat->sts_sensedata; 5062 5063 bcopy((uchar_t *)bp->b_un.b_addr, sensedata, 5064 ((cmd->cmd_rqslen >= sensecount) ? sensecount : 5065 cmd->cmd_rqslen)); 5066 arqstat->sts_rqpkt_resid = (cmd->cmd_rqslen - sensecount); 5067 cmd->cmd_flags |= CFLAG_CMDARQ; 5068 /* 5069 * Set proper status for pkt if autosense was valid 5070 */ 5071 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { 5072 struct scsi_status zero_status = { 0 }; 5073 arqstat->sts_rqpkt_status = zero_status; 5074 } 5075 5076 /* 5077 * ASC=0x47 is parity error 5078 * ASC=0x48 is initiator detected error received 5079 */ 5080 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) && 5081 ((scsi_sense_asc(sensedata) == 0x47) || 5082 (scsi_sense_asc(sensedata) == 0x48))) { 5083 mptsas_log(mpt, CE_NOTE, "Aborted_command!"); 5084 } 5085 5086 /* 5087 * ASC/ASCQ=0x3F/0x0E means report_luns data changed 5088 * ASC/ASCQ=0x25/0x00 means invalid lun 5089 */ 5090 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) && 5091 (scsi_sense_asc(sensedata) == 0x3F) && 5092 (scsi_sense_ascq(sensedata) == 0x0E)) || 5093 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) && 5094 (scsi_sense_asc(sensedata) == 0x25) && 5095 (scsi_sense_ascq(sensedata) == 0x00))) { 5096 mptsas_topo_change_list_t *topo_node = NULL; 5097 5098 topo_node = kmem_zalloc( 5099 sizeof (mptsas_topo_change_list_t), 5100 KM_NOSLEEP); 5101 if (topo_node == NULL) { 5102 mptsas_log(mpt, CE_NOTE, "No memory" 5103 "resource for handle SAS dynamic" 5104 "reconfigure.\n"); 5105 break; 5106 } 5107 topo_node->mpt = mpt; 5108 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET; 5109 topo_node->un.phymask = ptgt->m_phymask; 5110 topo_node->devhdl = ptgt->m_devhdl; 5111 topo_node->object = (void *)ptgt; 5112 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED; 5113 5114 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 5115 mptsas_handle_dr, 5116 (void *)topo_node, 5117 DDI_NOSLEEP)) != DDI_SUCCESS) { 5118 mptsas_log(mpt, CE_NOTE, "mptsas start taskq" 5119 "for handle SAS dynamic reconfigure" 5120 "failed. \n"); 5121 } 5122 } 5123 break; 5124 case MPI2_SCSI_STATUS_GOOD: 5125 switch (ioc_status & MPI2_IOCSTATUS_MASK) { 5126 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 5127 pkt->pkt_reason = CMD_DEV_GONE; 5128 pkt->pkt_state |= STATE_GOT_BUS; 5129 if (ptgt->m_reset_delay == 0) { 5130 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5131 } 5132 NDBG31(("lost disk for target%d, command:%x", 5133 Tgt(cmd), pkt->pkt_cdbp[0])); 5134 break; 5135 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 5136 NDBG31(("data overrun: xferred=%d", xferred)); 5137 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5138 pkt->pkt_reason = CMD_DATA_OVR; 5139 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5140 | STATE_SENT_CMD | STATE_GOT_STATUS 5141 | STATE_XFERRED_DATA); 5142 pkt->pkt_resid = 0; 5143 break; 5144 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 5145 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 5146 NDBG31(("data underrun: xferred=%d", xferred)); 5147 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5148 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5149 | STATE_SENT_CMD | STATE_GOT_STATUS); 5150 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5151 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5152 pkt->pkt_state |= STATE_XFERRED_DATA; 5153 } 5154 break; 5155 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 5156 mptsas_set_pkt_reason(mpt, 5157 cmd, CMD_RESET, STAT_BUS_RESET); 5158 break; 5159 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 5160 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 5161 mptsas_set_pkt_reason(mpt, 5162 cmd, CMD_RESET, STAT_DEV_RESET); 5163 break; 5164 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 5165 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 5166 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET); 5167 mptsas_set_pkt_reason(mpt, 5168 cmd, CMD_TERMINATED, STAT_TERMINATED); 5169 break; 5170 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 5171 case MPI2_IOCSTATUS_BUSY: 5172 /* 5173 * set throttles to drain 5174 */ 5175 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 5176 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST); 5177 while (ptgt != NULL) { 5178 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5179 5180 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 5181 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 5182 } 5183 5184 /* 5185 * retry command 5186 */ 5187 cmd->cmd_flags |= CFLAG_RETRY; 5188 cmd->cmd_pkt_flags |= FLAG_HEAD; 5189 5190 (void) mptsas_accept_pkt(mpt, cmd); 5191 break; 5192 default: 5193 mptsas_log(mpt, CE_WARN, 5194 "unknown ioc_status = %x\n", ioc_status); 5195 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer " 5196 "count = %x, scsi_status = %x", scsi_state, 5197 xferred, scsi_status); 5198 break; 5199 } 5200 break; 5201 case MPI2_SCSI_STATUS_TASK_SET_FULL: 5202 mptsas_handle_qfull(mpt, cmd); 5203 break; 5204 case MPI2_SCSI_STATUS_BUSY: 5205 NDBG31(("scsi_status busy received")); 5206 break; 5207 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT: 5208 NDBG31(("scsi_status reservation conflict received")); 5209 break; 5210 default: 5211 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n", 5212 scsi_status, ioc_status); 5213 mptsas_log(mpt, CE_WARN, 5214 "mptsas_process_intr: invalid scsi status\n"); 5215 break; 5216 } 5217 } 5218 5219 static void 5220 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply, 5221 mptsas_cmd_t *cmd) 5222 { 5223 uint8_t task_type; 5224 uint16_t ioc_status; 5225 uint32_t log_info; 5226 uint16_t dev_handle; 5227 struct scsi_pkt *pkt = CMD2PKT(cmd); 5228 5229 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType); 5230 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5231 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo); 5232 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle); 5233 5234 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5235 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x " 5236 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n", 5237 task_type, ioc_status, log_info, dev_handle); 5238 pkt->pkt_reason = CMD_INCOMPLETE; 5239 return; 5240 } 5241 5242 switch (task_type) { 5243 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 5244 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 5245 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 5246 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA: 5247 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET: 5248 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION: 5249 break; 5250 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 5251 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 5252 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 5253 mptsas_flush_target(mpt, dev_handle, Lun(cmd), task_type); 5254 break; 5255 default: 5256 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 5257 task_type); 5258 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status); 5259 break; 5260 } 5261 } 5262 5263 static void 5264 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg) 5265 { 5266 mptsas_t *mpt = arg->mpt; 5267 uint64_t t = arg->t; 5268 mptsas_cmd_t *cmd; 5269 struct scsi_pkt *pkt; 5270 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 5271 5272 mutex_enter(&item->mutex); 5273 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) { 5274 if (!item->doneq) { 5275 cv_wait(&item->cv, &item->mutex); 5276 } 5277 pkt = NULL; 5278 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) { 5279 cmd->cmd_flags |= CFLAG_COMPLETED; 5280 pkt = CMD2PKT(cmd); 5281 } 5282 mutex_exit(&item->mutex); 5283 if (pkt) { 5284 mptsas_pkt_comp(pkt, cmd); 5285 } 5286 mutex_enter(&item->mutex); 5287 } 5288 mutex_exit(&item->mutex); 5289 mutex_enter(&mpt->m_doneq_mutex); 5290 mpt->m_doneq_thread_n--; 5291 cv_broadcast(&mpt->m_doneq_thread_cv); 5292 mutex_exit(&mpt->m_doneq_mutex); 5293 } 5294 5295 5296 /* 5297 * mpt interrupt handler. 5298 */ 5299 static uint_t 5300 mptsas_intr(caddr_t arg1, caddr_t arg2) 5301 { 5302 mptsas_t *mpt = (void *)arg1; 5303 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5304 uchar_t did_reply = FALSE; 5305 5306 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2)); 5307 5308 mutex_enter(&mpt->m_mutex); 5309 5310 /* 5311 * If interrupts are shared by two channels then check whether this 5312 * interrupt is genuinely for this channel by making sure first the 5313 * chip is in high power state. 5314 */ 5315 if ((mpt->m_options & MPTSAS_OPT_PM) && 5316 (mpt->m_power_level != PM_LEVEL_D0)) { 5317 mutex_exit(&mpt->m_mutex); 5318 return (DDI_INTR_UNCLAIMED); 5319 } 5320 5321 /* 5322 * If polling, interrupt was triggered by some shared interrupt because 5323 * IOC interrupts are disabled during polling, so polling routine will 5324 * handle any replies. Considering this, if polling is happening, 5325 * return with interrupt unclaimed. 5326 */ 5327 if (mpt->m_polled_intr) { 5328 mutex_exit(&mpt->m_mutex); 5329 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt"); 5330 return (DDI_INTR_UNCLAIMED); 5331 } 5332 5333 /* 5334 * Read the istat register. 5335 */ 5336 if ((INTPENDING(mpt)) != 0) { 5337 /* 5338 * read fifo until empty. 5339 */ 5340 #ifndef __lock_lint 5341 _NOTE(CONSTCOND) 5342 #endif 5343 while (TRUE) { 5344 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5345 DDI_DMA_SYNC_FORCPU); 5346 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5347 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5348 5349 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5350 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5351 ddi_get32(mpt->m_acc_post_queue_hdl, 5352 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5353 break; 5354 } 5355 5356 /* 5357 * The reply is valid, process it according to its 5358 * type. Also, set a flag for updating the reply index 5359 * after they've all been processed. 5360 */ 5361 did_reply = TRUE; 5362 5363 mptsas_process_intr(mpt, reply_desc_union); 5364 5365 /* 5366 * Increment post index and roll over if needed. 5367 */ 5368 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5369 mpt->m_post_index = 0; 5370 } 5371 } 5372 5373 /* 5374 * Update the global reply index if at least one reply was 5375 * processed. 5376 */ 5377 if (did_reply) { 5378 ddi_put32(mpt->m_datap, 5379 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5380 } 5381 } else { 5382 mutex_exit(&mpt->m_mutex); 5383 return (DDI_INTR_UNCLAIMED); 5384 } 5385 NDBG1(("mptsas_intr complete")); 5386 5387 /* 5388 * If no helper threads are created, process the doneq in ISR. If 5389 * helpers are created, use the doneq length as a metric to measure the 5390 * load on the interrupt CPU. If it is long enough, which indicates the 5391 * load is heavy, then we deliver the IO completions to the helpers. 5392 * This measurement has some limitations, although it is simple and 5393 * straightforward and works well for most of the cases at present. 5394 */ 5395 if (!mpt->m_doneq_thread_n || 5396 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) { 5397 mptsas_doneq_empty(mpt); 5398 } else { 5399 mptsas_deliver_doneq_thread(mpt); 5400 } 5401 5402 /* 5403 * If there are queued cmd, start them now. 5404 */ 5405 if (mpt->m_waitq != NULL) { 5406 mptsas_restart_waitq(mpt); 5407 } 5408 5409 mutex_exit(&mpt->m_mutex); 5410 return (DDI_INTR_CLAIMED); 5411 } 5412 5413 static void 5414 mptsas_process_intr(mptsas_t *mpt, 5415 pMpi2ReplyDescriptorsUnion_t reply_desc_union) 5416 { 5417 uint8_t reply_type; 5418 5419 ASSERT(mutex_owned(&mpt->m_mutex)); 5420 5421 /* 5422 * The reply is valid, process it according to its 5423 * type. Also, set a flag for updated the reply index 5424 * after they've all been processed. 5425 */ 5426 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 5427 &reply_desc_union->Default.ReplyFlags); 5428 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 5429 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS) { 5430 mptsas_handle_scsi_io_success(mpt, reply_desc_union); 5431 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 5432 mptsas_handle_address_reply(mpt, reply_desc_union); 5433 } else { 5434 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type); 5435 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5436 } 5437 5438 /* 5439 * Clear the reply descriptor for re-use and increment 5440 * index. 5441 */ 5442 ddi_put64(mpt->m_acc_post_queue_hdl, 5443 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index], 5444 0xFFFFFFFFFFFFFFFF); 5445 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5446 DDI_DMA_SYNC_FORDEV); 5447 } 5448 5449 /* 5450 * handle qfull condition 5451 */ 5452 static void 5453 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd) 5454 { 5455 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5456 5457 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) || 5458 (ptgt->m_qfull_retries == 0)) { 5459 /* 5460 * We have exhausted the retries on QFULL, or, 5461 * the target driver has indicated that it 5462 * wants to handle QFULL itself by setting 5463 * qfull-retries capability to 0. In either case 5464 * we want the target driver's QFULL handling 5465 * to kick in. We do this by having pkt_reason 5466 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL. 5467 */ 5468 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5469 } else { 5470 if (ptgt->m_reset_delay == 0) { 5471 ptgt->m_t_throttle = 5472 max((ptgt->m_t_ncmds - 2), 0); 5473 } 5474 5475 cmd->cmd_pkt_flags |= FLAG_HEAD; 5476 cmd->cmd_flags &= ~(CFLAG_TRANFLAG); 5477 cmd->cmd_flags |= CFLAG_RETRY; 5478 5479 (void) mptsas_accept_pkt(mpt, cmd); 5480 5481 /* 5482 * when target gives queue full status with no commands 5483 * outstanding (m_t_ncmds == 0), throttle is set to 0 5484 * (HOLD_THROTTLE), and the queue full handling start 5485 * (see psarc/1994/313); if there are commands outstanding, 5486 * throttle is set to (m_t_ncmds - 2) 5487 */ 5488 if (ptgt->m_t_throttle == HOLD_THROTTLE) { 5489 /* 5490 * By setting throttle to QFULL_THROTTLE, we 5491 * avoid submitting new commands and in 5492 * mptsas_restart_cmd find out slots which need 5493 * their throttles to be cleared. 5494 */ 5495 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE); 5496 if (mpt->m_restart_cmd_timeid == 0) { 5497 mpt->m_restart_cmd_timeid = 5498 timeout(mptsas_restart_cmd, mpt, 5499 ptgt->m_qfull_retry_interval); 5500 } 5501 } 5502 } 5503 } 5504 5505 mptsas_phymask_t 5506 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport) 5507 { 5508 mptsas_phymask_t phy_mask = 0; 5509 uint8_t i = 0; 5510 5511 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance)); 5512 5513 ASSERT(mutex_owned(&mpt->m_mutex)); 5514 5515 /* 5516 * If physport is 0xFF, this is a RAID volume. Use phymask of 0. 5517 */ 5518 if (physport == 0xFF) { 5519 return (0); 5520 } 5521 5522 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 5523 if (mpt->m_phy_info[i].attached_devhdl && 5524 (mpt->m_phy_info[i].phy_mask != 0) && 5525 (mpt->m_phy_info[i].port_num == physport)) { 5526 phy_mask = mpt->m_phy_info[i].phy_mask; 5527 break; 5528 } 5529 } 5530 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ", 5531 mpt->m_instance, physport, phy_mask)); 5532 return (phy_mask); 5533 } 5534 5535 /* 5536 * mpt free device handle after device gone, by use of passthrough 5537 */ 5538 static int 5539 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl) 5540 { 5541 Mpi2SasIoUnitControlRequest_t req; 5542 Mpi2SasIoUnitControlReply_t rep; 5543 int ret; 5544 5545 ASSERT(mutex_owned(&mpt->m_mutex)); 5546 5547 /* 5548 * Need to compose a SAS IO Unit Control request message 5549 * and call mptsas_do_passthru() function 5550 */ 5551 bzero(&req, sizeof (req)); 5552 bzero(&rep, sizeof (rep)); 5553 5554 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; 5555 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE; 5556 req.DevHandle = LE_16(devhdl); 5557 5558 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 5559 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 5560 if (ret != 0) { 5561 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 5562 "Control error %d", ret); 5563 return (DDI_FAILURE); 5564 } 5565 5566 /* do passthrough success, check the ioc status */ 5567 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 5568 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 5569 "Control IOCStatus %d", LE_16(rep.IOCStatus)); 5570 return (DDI_FAILURE); 5571 } 5572 5573 return (DDI_SUCCESS); 5574 } 5575 5576 static void 5577 mptsas_update_phymask(mptsas_t *mpt) 5578 { 5579 mptsas_phymask_t mask = 0, phy_mask; 5580 char *phy_mask_name; 5581 uint8_t current_port; 5582 int i, j; 5583 5584 NDBG20(("mptsas%d update phymask ", mpt->m_instance)); 5585 5586 ASSERT(mutex_owned(&mpt->m_mutex)); 5587 5588 (void) mptsas_get_sas_io_unit_page(mpt); 5589 5590 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 5591 5592 for (i = 0; i < mpt->m_num_phys; i++) { 5593 phy_mask = 0x00; 5594 5595 if (mpt->m_phy_info[i].attached_devhdl == 0) 5596 continue; 5597 5598 bzero(phy_mask_name, sizeof (phy_mask_name)); 5599 5600 current_port = mpt->m_phy_info[i].port_num; 5601 5602 if ((mask & (1 << i)) != 0) 5603 continue; 5604 5605 for (j = 0; j < mpt->m_num_phys; j++) { 5606 if (mpt->m_phy_info[j].attached_devhdl && 5607 (mpt->m_phy_info[j].port_num == current_port)) { 5608 phy_mask |= (1 << j); 5609 } 5610 } 5611 mask = mask | phy_mask; 5612 5613 for (j = 0; j < mpt->m_num_phys; j++) { 5614 if ((phy_mask >> j) & 0x01) { 5615 mpt->m_phy_info[j].phy_mask = phy_mask; 5616 } 5617 } 5618 5619 (void) sprintf(phy_mask_name, "%x", phy_mask); 5620 5621 mutex_exit(&mpt->m_mutex); 5622 /* 5623 * register a iport, if the port has already been existed 5624 * SCSA will do nothing and just return. 5625 */ 5626 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 5627 mutex_enter(&mpt->m_mutex); 5628 } 5629 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 5630 NDBG20(("mptsas%d update phymask return", mpt->m_instance)); 5631 } 5632 5633 /* 5634 * mptsas_handle_dr is a task handler for DR, the DR action includes: 5635 * 1. Directly attched Device Added/Removed. 5636 * 2. Expander Device Added/Removed. 5637 * 3. Indirectly Attached Device Added/Expander. 5638 * 4. LUNs of a existing device status change. 5639 * 5. RAID volume created/deleted. 5640 * 6. Member of RAID volume is released because of RAID deletion. 5641 * 7. Physical disks are removed because of RAID creation. 5642 */ 5643 static void 5644 mptsas_handle_dr(void *args) { 5645 mptsas_topo_change_list_t *topo_node = NULL; 5646 mptsas_topo_change_list_t *save_node = NULL; 5647 mptsas_t *mpt; 5648 dev_info_t *parent = NULL; 5649 mptsas_phymask_t phymask = 0; 5650 char *phy_mask_name; 5651 uint8_t flags = 0, physport = 0xff; 5652 uint8_t port_update = 0; 5653 uint_t event; 5654 5655 topo_node = (mptsas_topo_change_list_t *)args; 5656 5657 mpt = topo_node->mpt; 5658 event = topo_node->event; 5659 flags = topo_node->flags; 5660 5661 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 5662 5663 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance)); 5664 5665 switch (event) { 5666 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 5667 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 5668 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) || 5669 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 5670 /* 5671 * Direct attached or expander attached device added 5672 * into system or a Phys Disk that is being unhidden. 5673 */ 5674 port_update = 1; 5675 } 5676 break; 5677 case MPTSAS_DR_EVENT_RECONFIG_SMP: 5678 /* 5679 * New expander added into system, it must be the head 5680 * of topo_change_list_t 5681 */ 5682 port_update = 1; 5683 break; 5684 default: 5685 port_update = 0; 5686 break; 5687 } 5688 /* 5689 * All cases port_update == 1 may cause initiator port form change 5690 */ 5691 mutex_enter(&mpt->m_mutex); 5692 if (mpt->m_port_chng && port_update) { 5693 /* 5694 * mpt->m_port_chng flag indicates some PHYs of initiator 5695 * port have changed to online. So when expander added or 5696 * directly attached device online event come, we force to 5697 * update port information by issueing SAS IO Unit Page and 5698 * update PHYMASKs. 5699 */ 5700 (void) mptsas_update_phymask(mpt); 5701 mpt->m_port_chng = 0; 5702 5703 } 5704 mutex_exit(&mpt->m_mutex); 5705 while (topo_node) { 5706 phymask = 0; 5707 if (parent == NULL) { 5708 physport = topo_node->un.physport; 5709 event = topo_node->event; 5710 flags = topo_node->flags; 5711 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET | 5712 MPTSAS_DR_EVENT_OFFLINE_SMP)) { 5713 /* 5714 * For all offline events, phymask is known 5715 */ 5716 phymask = topo_node->un.phymask; 5717 goto find_parent; 5718 } 5719 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 5720 goto handle_topo_change; 5721 } 5722 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) { 5723 phymask = topo_node->un.phymask; 5724 goto find_parent; 5725 } 5726 5727 if ((flags == 5728 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) && 5729 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) { 5730 /* 5731 * There is no any field in IR_CONFIG_CHANGE 5732 * event indicate physport/phynum, let's get 5733 * parent after SAS Device Page0 request. 5734 */ 5735 goto handle_topo_change; 5736 } 5737 5738 mutex_enter(&mpt->m_mutex); 5739 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 5740 /* 5741 * If the direct attached device added or a 5742 * phys disk is being unhidden, argument 5743 * physport actually is PHY#, so we have to get 5744 * phymask according PHY#. 5745 */ 5746 physport = mpt->m_phy_info[physport].port_num; 5747 } 5748 5749 /* 5750 * Translate physport to phymask so that we can search 5751 * parent dip. 5752 */ 5753 phymask = mptsas_physport_to_phymask(mpt, 5754 physport); 5755 mutex_exit(&mpt->m_mutex); 5756 5757 find_parent: 5758 bzero(phy_mask_name, MPTSAS_MAX_PHYS); 5759 /* 5760 * For RAID topology change node, write the iport name 5761 * as v0. 5762 */ 5763 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 5764 (void) sprintf(phy_mask_name, "v0"); 5765 } else { 5766 /* 5767 * phymask can bo 0 if the drive has been 5768 * pulled by the time an add event is 5769 * processed. If phymask is 0, just skip this 5770 * event and continue. 5771 */ 5772 if (phymask == 0) { 5773 mutex_enter(&mpt->m_mutex); 5774 save_node = topo_node; 5775 topo_node = topo_node->next; 5776 ASSERT(save_node); 5777 kmem_free(save_node, 5778 sizeof (mptsas_topo_change_list_t)); 5779 mutex_exit(&mpt->m_mutex); 5780 5781 parent = NULL; 5782 continue; 5783 } 5784 (void) sprintf(phy_mask_name, "%x", phymask); 5785 } 5786 parent = scsi_hba_iport_find(mpt->m_dip, 5787 phy_mask_name); 5788 if (parent == NULL) { 5789 mptsas_log(mpt, CE_WARN, "Failed to find an " 5790 "iport, should not happen!"); 5791 goto out; 5792 } 5793 5794 } 5795 ASSERT(parent); 5796 handle_topo_change: 5797 5798 mutex_enter(&mpt->m_mutex); 5799 5800 mptsas_handle_topo_change(topo_node, parent); 5801 save_node = topo_node; 5802 topo_node = topo_node->next; 5803 ASSERT(save_node); 5804 kmem_free(save_node, sizeof (mptsas_topo_change_list_t)); 5805 mutex_exit(&mpt->m_mutex); 5806 5807 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 5808 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) || 5809 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) { 5810 /* 5811 * If direct attached device associated, make sure 5812 * reset the parent before start the next one. But 5813 * all devices associated with expander shares the 5814 * parent. Also, reset parent if this is for RAID. 5815 */ 5816 parent = NULL; 5817 } 5818 } 5819 out: 5820 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 5821 } 5822 5823 static void 5824 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 5825 dev_info_t *parent) 5826 { 5827 mptsas_target_t *ptgt = NULL; 5828 mptsas_smp_t *psmp = NULL; 5829 mptsas_t *mpt = (void *)topo_node->mpt; 5830 uint16_t devhdl; 5831 uint64_t sas_wwn = 0; 5832 int rval = 0; 5833 uint32_t page_address; 5834 uint8_t phy, flags; 5835 char *addr = NULL; 5836 dev_info_t *lundip; 5837 int circ = 0, circ1 = 0; 5838 5839 NDBG20(("mptsas%d handle_topo_change enter", mpt->m_instance)); 5840 5841 ASSERT(mutex_owned(&mpt->m_mutex)); 5842 5843 switch (topo_node->event) { 5844 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 5845 { 5846 char *phy_mask_name; 5847 mptsas_phymask_t phymask = 0; 5848 5849 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 5850 /* 5851 * Get latest RAID info. 5852 */ 5853 (void) mptsas_get_raid_info(mpt); 5854 ptgt = mptsas_search_by_devhdl( 5855 &mpt->m_active->m_tgttbl, topo_node->devhdl); 5856 if (ptgt == NULL) 5857 break; 5858 } else { 5859 ptgt = (void *)topo_node->object; 5860 } 5861 5862 if (ptgt == NULL) { 5863 /* 5864 * If a Phys Disk was deleted, RAID info needs to be 5865 * updated to reflect the new topology. 5866 */ 5867 (void) mptsas_get_raid_info(mpt); 5868 5869 /* 5870 * Get sas device page 0 by DevHandle to make sure if 5871 * SSP/SATA end device exist. 5872 */ 5873 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 5874 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 5875 topo_node->devhdl; 5876 5877 rval = mptsas_get_target_device_info(mpt, page_address, 5878 &devhdl, &ptgt); 5879 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) { 5880 mptsas_log(mpt, CE_NOTE, 5881 "mptsas_handle_topo_change: target %d is " 5882 "not a SAS/SATA device. \n", 5883 topo_node->devhdl); 5884 } else if (rval == DEV_INFO_FAIL_ALLOC) { 5885 mptsas_log(mpt, CE_NOTE, 5886 "mptsas_handle_topo_change: could not " 5887 "allocate memory. \n"); 5888 } 5889 /* 5890 * If rval is DEV_INFO_PHYS_DISK than there is nothing 5891 * else to do, just leave. 5892 */ 5893 if (rval != DEV_INFO_SUCCESS) { 5894 return; 5895 } 5896 } 5897 5898 ASSERT(ptgt->m_devhdl == topo_node->devhdl); 5899 5900 mutex_exit(&mpt->m_mutex); 5901 flags = topo_node->flags; 5902 5903 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) { 5904 phymask = ptgt->m_phymask; 5905 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 5906 (void) sprintf(phy_mask_name, "%x", phymask); 5907 parent = scsi_hba_iport_find(mpt->m_dip, 5908 phy_mask_name); 5909 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 5910 if (parent == NULL) { 5911 mptsas_log(mpt, CE_WARN, "Failed to find a " 5912 "iport for PD, should not happen!"); 5913 mutex_enter(&mpt->m_mutex); 5914 break; 5915 } 5916 } 5917 5918 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 5919 ndi_devi_enter(parent, &circ1); 5920 (void) mptsas_config_raid(parent, topo_node->devhdl, 5921 &lundip); 5922 ndi_devi_exit(parent, circ1); 5923 } else { 5924 /* 5925 * hold nexus for bus configure 5926 */ 5927 ndi_devi_enter(scsi_vhci_dip, &circ); 5928 ndi_devi_enter(parent, &circ1); 5929 rval = mptsas_config_target(parent, ptgt); 5930 /* 5931 * release nexus for bus configure 5932 */ 5933 ndi_devi_exit(parent, circ1); 5934 ndi_devi_exit(scsi_vhci_dip, circ); 5935 5936 } 5937 mutex_enter(&mpt->m_mutex); 5938 5939 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, " 5940 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl, 5941 ptgt->m_phymask)); 5942 break; 5943 } 5944 case MPTSAS_DR_EVENT_OFFLINE_TARGET: 5945 { 5946 mptsas_hash_table_t *tgttbl = &mpt->m_active->m_tgttbl; 5947 devhdl = topo_node->devhdl; 5948 ptgt = mptsas_search_by_devhdl(tgttbl, devhdl); 5949 if (ptgt == NULL) 5950 break; 5951 5952 sas_wwn = ptgt->m_sas_wwn; 5953 phy = ptgt->m_phynum; 5954 5955 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 5956 5957 if (sas_wwn) { 5958 (void) sprintf(addr, "w%016"PRIx64, sas_wwn); 5959 } else { 5960 (void) sprintf(addr, "p%x", phy); 5961 } 5962 ASSERT(ptgt->m_devhdl == devhdl); 5963 5964 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) || 5965 (topo_node->flags == 5966 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 5967 /* 5968 * Get latest RAID info if RAID volume status changes 5969 * or Phys Disk status changes 5970 */ 5971 (void) mptsas_get_raid_info(mpt); 5972 } 5973 /* 5974 * Abort all outstanding command on the device 5975 */ 5976 rval = mptsas_do_scsi_reset(mpt, devhdl); 5977 if (rval) { 5978 NDBG20(("mptsas%d handle_topo_change to reset target " 5979 "before offline devhdl:%x, phymask:%x, rval:%x", 5980 mpt->m_instance, ptgt->m_devhdl, ptgt->m_phymask, 5981 rval)); 5982 } 5983 5984 mutex_exit(&mpt->m_mutex); 5985 5986 ndi_devi_enter(scsi_vhci_dip, &circ); 5987 ndi_devi_enter(parent, &circ1); 5988 rval = mptsas_offline_target(parent, addr); 5989 ndi_devi_exit(parent, circ1); 5990 ndi_devi_exit(scsi_vhci_dip, circ); 5991 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, " 5992 "phymask:%x, rval:%x", mpt->m_instance, 5993 ptgt->m_devhdl, ptgt->m_phymask, rval)); 5994 5995 kmem_free(addr, SCSI_MAXNAMELEN); 5996 5997 mutex_enter(&mpt->m_mutex); 5998 if (rval == DDI_SUCCESS) { 5999 mptsas_tgt_free(&mpt->m_active->m_tgttbl, 6000 ptgt->m_sas_wwn, ptgt->m_phymask); 6001 ptgt = NULL; 6002 } else { 6003 /* 6004 * clean DR_INTRANSITION flag to allow I/O down to 6005 * PHCI driver since failover finished. 6006 * Invalidate the devhdl 6007 */ 6008 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL; 6009 mutex_enter(&mpt->m_tx_waitq_mutex); 6010 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE; 6011 mutex_exit(&mpt->m_tx_waitq_mutex); 6012 } 6013 6014 /* 6015 * Send SAS IO Unit Control to free the dev handle 6016 */ 6017 flags = topo_node->flags; 6018 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6019 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) { 6020 rval = mptsas_free_devhdl(mpt, devhdl); 6021 6022 NDBG20(("mptsas%d handle_topo_change to remove " 6023 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6024 rval)); 6025 } 6026 break; 6027 } 6028 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE: 6029 { 6030 devhdl = topo_node->devhdl; 6031 /* 6032 * If this is the remove handle event, do a reset first. 6033 */ 6034 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6035 rval = mptsas_do_scsi_reset(mpt, devhdl); 6036 if (rval) { 6037 NDBG20(("mpt%d reset target before remove " 6038 "devhdl:%x, rval:%x", mpt->m_instance, 6039 devhdl, rval)); 6040 } 6041 } 6042 6043 /* 6044 * Send SAS IO Unit Control to free the dev handle 6045 */ 6046 rval = mptsas_free_devhdl(mpt, devhdl); 6047 NDBG20(("mptsas%d handle_topo_change to remove " 6048 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6049 rval)); 6050 break; 6051 } 6052 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6053 { 6054 mptsas_smp_t smp; 6055 dev_info_t *smpdip; 6056 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl; 6057 6058 devhdl = topo_node->devhdl; 6059 6060 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 6061 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl; 6062 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp); 6063 if (rval != DDI_SUCCESS) { 6064 mptsas_log(mpt, CE_WARN, "failed to online smp, " 6065 "handle %x", devhdl); 6066 return; 6067 } 6068 6069 psmp = mptsas_smp_alloc(smptbl, &smp); 6070 if (psmp == NULL) { 6071 return; 6072 } 6073 6074 mutex_exit(&mpt->m_mutex); 6075 ndi_devi_enter(parent, &circ1); 6076 (void) mptsas_online_smp(parent, psmp, &smpdip); 6077 ndi_devi_exit(parent, circ1); 6078 mutex_enter(&mpt->m_mutex); 6079 break; 6080 } 6081 case MPTSAS_DR_EVENT_OFFLINE_SMP: 6082 { 6083 mptsas_hash_table_t *smptbl = &mpt->m_active->m_smptbl; 6084 devhdl = topo_node->devhdl; 6085 psmp = mptsas_search_by_devhdl(smptbl, devhdl); 6086 if (psmp == NULL) 6087 break; 6088 /* 6089 * The mptsas_smp_t data is released only if the dip is offlined 6090 * successfully. 6091 */ 6092 mutex_exit(&mpt->m_mutex); 6093 ndi_devi_enter(parent, &circ1); 6094 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE); 6095 ndi_devi_exit(parent, circ1); 6096 mutex_enter(&mpt->m_mutex); 6097 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, " 6098 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval)); 6099 if (rval == DDI_SUCCESS) { 6100 mptsas_smp_free(smptbl, psmp->m_sasaddr, 6101 psmp->m_phymask); 6102 } else { 6103 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL; 6104 } 6105 break; 6106 } 6107 default: 6108 return; 6109 } 6110 } 6111 6112 /* 6113 * Record the event if its type is enabled in mpt instance by ioctl. 6114 */ 6115 static void 6116 mptsas_record_event(void *args) 6117 { 6118 m_replyh_arg_t *replyh_arg; 6119 pMpi2EventNotificationReply_t eventreply; 6120 uint32_t event, rfm; 6121 mptsas_t *mpt; 6122 int i, j; 6123 uint16_t event_data_len; 6124 boolean_t sendAEN = FALSE; 6125 6126 replyh_arg = (m_replyh_arg_t *)args; 6127 rfm = replyh_arg->rfm; 6128 mpt = replyh_arg->mpt; 6129 6130 eventreply = (pMpi2EventNotificationReply_t) 6131 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr)); 6132 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6133 6134 6135 /* 6136 * Generate a system event to let anyone who cares know that a 6137 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the 6138 * event mask is set to. 6139 */ 6140 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) { 6141 sendAEN = TRUE; 6142 } 6143 6144 /* 6145 * Record the event only if it is not masked. Determine which dword 6146 * and bit of event mask to test. 6147 */ 6148 i = (uint8_t)(event / 32); 6149 j = (uint8_t)(event % 32); 6150 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) { 6151 i = mpt->m_event_index; 6152 mpt->m_events[i].Type = event; 6153 mpt->m_events[i].Number = ++mpt->m_event_number; 6154 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4); 6155 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl, 6156 &eventreply->EventDataLength); 6157 6158 if (event_data_len > 0) { 6159 /* 6160 * Limit data to size in m_event entry 6161 */ 6162 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) { 6163 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH; 6164 } 6165 for (j = 0; j < event_data_len; j++) { 6166 mpt->m_events[i].Data[j] = 6167 ddi_get32(mpt->m_acc_reply_frame_hdl, 6168 &(eventreply->EventData[j])); 6169 } 6170 6171 /* 6172 * check for index wrap-around 6173 */ 6174 if (++i == MPTSAS_EVENT_QUEUE_SIZE) { 6175 i = 0; 6176 } 6177 mpt->m_event_index = (uint8_t)i; 6178 6179 /* 6180 * Set flag to send the event. 6181 */ 6182 sendAEN = TRUE; 6183 } 6184 } 6185 6186 /* 6187 * Generate a system event if flag is set to let anyone who cares know 6188 * that an event has occurred. 6189 */ 6190 if (sendAEN) { 6191 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS", 6192 "SAS", NULL, NULL, DDI_NOSLEEP); 6193 } 6194 } 6195 6196 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS 6197 /* 6198 * handle sync events from ioc in interrupt 6199 * return value: 6200 * DDI_SUCCESS: The event is handled by this func 6201 * DDI_FAILURE: Event is not handled 6202 */ 6203 static int 6204 mptsas_handle_event_sync(void *args) 6205 { 6206 m_replyh_arg_t *replyh_arg; 6207 pMpi2EventNotificationReply_t eventreply; 6208 uint32_t event, rfm; 6209 mptsas_t *mpt; 6210 uint_t iocstatus; 6211 6212 replyh_arg = (m_replyh_arg_t *)args; 6213 rfm = replyh_arg->rfm; 6214 mpt = replyh_arg->mpt; 6215 6216 ASSERT(mutex_owned(&mpt->m_mutex)); 6217 6218 eventreply = (pMpi2EventNotificationReply_t) 6219 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr)); 6220 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6221 6222 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 6223 &eventreply->IOCStatus)) { 6224 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 6225 mptsas_log(mpt, CE_WARN, 6226 "!mptsas_handle_event_sync: IOCStatus=0x%x, " 6227 "IOCLogInfo=0x%x", iocstatus, 6228 ddi_get32(mpt->m_acc_reply_frame_hdl, 6229 &eventreply->IOCLogInfo)); 6230 } else { 6231 mptsas_log(mpt, CE_WARN, 6232 "mptsas_handle_event_sync: IOCStatus=0x%x, " 6233 "IOCLogInfo=0x%x", iocstatus, 6234 ddi_get32(mpt->m_acc_reply_frame_hdl, 6235 &eventreply->IOCLogInfo)); 6236 } 6237 } 6238 6239 /* 6240 * figure out what kind of event we got and handle accordingly 6241 */ 6242 switch (event) { 6243 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 6244 { 6245 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list; 6246 uint8_t num_entries, expstatus, phy; 6247 uint8_t phystatus, physport, state, i; 6248 uint8_t start_phy_num, link_rate; 6249 uint16_t dev_handle, reason_code; 6250 uint16_t enc_handle, expd_handle; 6251 char string[80], curr[80], prev[80]; 6252 mptsas_topo_change_list_t *topo_head = NULL; 6253 mptsas_topo_change_list_t *topo_tail = NULL; 6254 mptsas_topo_change_list_t *topo_node = NULL; 6255 mptsas_target_t *ptgt; 6256 mptsas_smp_t *psmp; 6257 mptsas_hash_table_t *tgttbl, *smptbl; 6258 uint8_t flags = 0, exp_flag; 6259 6260 NDBG20(("mptsas_handle_event_sync: SAS topology change")); 6261 6262 tgttbl = &mpt->m_active->m_tgttbl; 6263 smptbl = &mpt->m_active->m_smptbl; 6264 6265 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t) 6266 eventreply->EventData; 6267 6268 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6269 &sas_topo_change_list->EnclosureHandle); 6270 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6271 &sas_topo_change_list->ExpanderDevHandle); 6272 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 6273 &sas_topo_change_list->NumEntries); 6274 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 6275 &sas_topo_change_list->StartPhyNum); 6276 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 6277 &sas_topo_change_list->ExpStatus); 6278 physport = ddi_get8(mpt->m_acc_reply_frame_hdl, 6279 &sas_topo_change_list->PhysicalPort); 6280 6281 string[0] = 0; 6282 if (expd_handle) { 6283 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED; 6284 switch (expstatus) { 6285 case MPI2_EVENT_SAS_TOPO_ES_ADDED: 6286 (void) sprintf(string, " added"); 6287 /* 6288 * New expander device added 6289 */ 6290 mpt->m_port_chng = 1; 6291 topo_node = kmem_zalloc( 6292 sizeof (mptsas_topo_change_list_t), 6293 KM_SLEEP); 6294 topo_node->mpt = mpt; 6295 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP; 6296 topo_node->un.physport = physport; 6297 topo_node->devhdl = expd_handle; 6298 topo_node->flags = flags; 6299 topo_node->object = NULL; 6300 if (topo_head == NULL) { 6301 topo_head = topo_tail = topo_node; 6302 } else { 6303 topo_tail->next = topo_node; 6304 topo_tail = topo_node; 6305 } 6306 break; 6307 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING: 6308 (void) sprintf(string, " not responding, " 6309 "removed"); 6310 psmp = mptsas_search_by_devhdl(smptbl, 6311 expd_handle); 6312 if (psmp == NULL) 6313 break; 6314 6315 topo_node = kmem_zalloc( 6316 sizeof (mptsas_topo_change_list_t), 6317 KM_SLEEP); 6318 topo_node->mpt = mpt; 6319 topo_node->un.phymask = psmp->m_phymask; 6320 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP; 6321 topo_node->devhdl = expd_handle; 6322 topo_node->flags = flags; 6323 topo_node->object = NULL; 6324 if (topo_head == NULL) { 6325 topo_head = topo_tail = topo_node; 6326 } else { 6327 topo_tail->next = topo_node; 6328 topo_tail = topo_node; 6329 } 6330 break; 6331 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING: 6332 break; 6333 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING: 6334 (void) sprintf(string, " not responding, " 6335 "delaying removal"); 6336 break; 6337 default: 6338 break; 6339 } 6340 } else { 6341 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE; 6342 } 6343 6344 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n", 6345 enc_handle, expd_handle, string)); 6346 for (i = 0; i < num_entries; i++) { 6347 phy = i + start_phy_num; 6348 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 6349 &sas_topo_change_list->PHY[i].PhyStatus); 6350 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6351 &sas_topo_change_list->PHY[i].AttachedDevHandle); 6352 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK; 6353 /* 6354 * Filter out processing of Phy Vacant Status unless 6355 * the reason code is "Not Responding". Process all 6356 * other combinations of Phy Status and Reason Codes. 6357 */ 6358 if ((phystatus & 6359 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) && 6360 (reason_code != 6361 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) { 6362 continue; 6363 } 6364 curr[0] = 0; 6365 prev[0] = 0; 6366 string[0] = 0; 6367 switch (reason_code) { 6368 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED: 6369 { 6370 NDBG20(("mptsas%d phy %d physical_port %d " 6371 "dev_handle %d added", mpt->m_instance, phy, 6372 physport, dev_handle)); 6373 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 6374 &sas_topo_change_list->PHY[i].LinkRate); 6375 state = (link_rate & 6376 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 6377 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 6378 switch (state) { 6379 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 6380 (void) sprintf(curr, "is disabled"); 6381 break; 6382 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 6383 (void) sprintf(curr, "is offline, " 6384 "failed speed negotiation"); 6385 break; 6386 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 6387 (void) sprintf(curr, "SATA OOB " 6388 "complete"); 6389 break; 6390 case SMP_RESET_IN_PROGRESS: 6391 (void) sprintf(curr, "SMP reset in " 6392 "progress"); 6393 break; 6394 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 6395 (void) sprintf(curr, "is online at " 6396 "1.5 Gbps"); 6397 break; 6398 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 6399 (void) sprintf(curr, "is online at 3.0 " 6400 "Gbps"); 6401 break; 6402 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 6403 (void) sprintf(curr, "is online at 6.0 " 6404 "Gbps"); 6405 break; 6406 default: 6407 (void) sprintf(curr, "state is " 6408 "unknown"); 6409 break; 6410 } 6411 /* 6412 * New target device added into the system. 6413 * Set association flag according to if an 6414 * expander is used or not. 6415 */ 6416 exp_flag = 6417 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 6418 if (flags == 6419 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 6420 flags = exp_flag; 6421 } 6422 topo_node = kmem_zalloc( 6423 sizeof (mptsas_topo_change_list_t), 6424 KM_SLEEP); 6425 topo_node->mpt = mpt; 6426 topo_node->event = 6427 MPTSAS_DR_EVENT_RECONFIG_TARGET; 6428 if (expd_handle == 0) { 6429 /* 6430 * Per MPI 2, if expander dev handle 6431 * is 0, it's a directly attached 6432 * device. So driver use PHY to decide 6433 * which iport is associated 6434 */ 6435 physport = phy; 6436 mpt->m_port_chng = 1; 6437 } 6438 topo_node->un.physport = physport; 6439 topo_node->devhdl = dev_handle; 6440 topo_node->flags = flags; 6441 topo_node->object = NULL; 6442 if (topo_head == NULL) { 6443 topo_head = topo_tail = topo_node; 6444 } else { 6445 topo_tail->next = topo_node; 6446 topo_tail = topo_node; 6447 } 6448 break; 6449 } 6450 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING: 6451 { 6452 NDBG20(("mptsas%d phy %d physical_port %d " 6453 "dev_handle %d removed", mpt->m_instance, 6454 phy, physport, dev_handle)); 6455 /* 6456 * Set association flag according to if an 6457 * expander is used or not. 6458 */ 6459 exp_flag = 6460 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 6461 if (flags == 6462 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 6463 flags = exp_flag; 6464 } 6465 /* 6466 * Target device is removed from the system 6467 * Before the device is really offline from 6468 * from system. 6469 */ 6470 ptgt = mptsas_search_by_devhdl(tgttbl, 6471 dev_handle); 6472 /* 6473 * If ptgt is NULL here, it means that the 6474 * DevHandle is not in the hash table. This is 6475 * reasonable sometimes. For example, if a 6476 * disk was pulled, then added, then pulled 6477 * again, the disk will not have been put into 6478 * the hash table because the add event will 6479 * have an invalid phymask. BUT, this does not 6480 * mean that the DevHandle is invalid. The 6481 * controller will still have a valid DevHandle 6482 * that must be removed. To do this, use the 6483 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event. 6484 */ 6485 if (ptgt == NULL) { 6486 topo_node = kmem_zalloc( 6487 sizeof (mptsas_topo_change_list_t), 6488 KM_SLEEP); 6489 topo_node->mpt = mpt; 6490 topo_node->un.phymask = 0; 6491 topo_node->event = 6492 MPTSAS_TOPO_FLAG_REMOVE_HANDLE; 6493 topo_node->devhdl = dev_handle; 6494 topo_node->flags = flags; 6495 topo_node->object = NULL; 6496 if (topo_head == NULL) { 6497 topo_head = topo_tail = 6498 topo_node; 6499 } else { 6500 topo_tail->next = topo_node; 6501 topo_tail = topo_node; 6502 } 6503 break; 6504 } 6505 6506 /* 6507 * Update DR flag immediately avoid I/O failure 6508 * before failover finish. Pay attention to the 6509 * mutex protect, we need grab m_tx_waitq_mutex 6510 * during set m_dr_flag because we won't add 6511 * the following command into waitq, instead, 6512 * we need return TRAN_BUSY in the tran_start 6513 * context. 6514 */ 6515 mutex_enter(&mpt->m_tx_waitq_mutex); 6516 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 6517 mutex_exit(&mpt->m_tx_waitq_mutex); 6518 6519 topo_node = kmem_zalloc( 6520 sizeof (mptsas_topo_change_list_t), 6521 KM_SLEEP); 6522 topo_node->mpt = mpt; 6523 topo_node->un.phymask = ptgt->m_phymask; 6524 topo_node->event = 6525 MPTSAS_DR_EVENT_OFFLINE_TARGET; 6526 topo_node->devhdl = dev_handle; 6527 topo_node->flags = flags; 6528 topo_node->object = NULL; 6529 if (topo_head == NULL) { 6530 topo_head = topo_tail = topo_node; 6531 } else { 6532 topo_tail->next = topo_node; 6533 topo_tail = topo_node; 6534 } 6535 6536 break; 6537 } 6538 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED: 6539 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 6540 &sas_topo_change_list->PHY[i].LinkRate); 6541 state = (link_rate & 6542 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 6543 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 6544 switch (state) { 6545 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 6546 (void) sprintf(curr, "is disabled"); 6547 break; 6548 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 6549 (void) sprintf(curr, "is offline, " 6550 "failed speed negotiation"); 6551 break; 6552 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 6553 (void) sprintf(curr, "SATA OOB " 6554 "complete"); 6555 break; 6556 case SMP_RESET_IN_PROGRESS: 6557 (void) sprintf(curr, "SMP reset in " 6558 "progress"); 6559 break; 6560 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 6561 (void) sprintf(curr, "is online at " 6562 "1.5 Gbps"); 6563 if ((expd_handle == 0) && 6564 (enc_handle == 1)) { 6565 mpt->m_port_chng = 1; 6566 } 6567 break; 6568 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 6569 (void) sprintf(curr, "is online at 3.0 " 6570 "Gbps"); 6571 if ((expd_handle == 0) && 6572 (enc_handle == 1)) { 6573 mpt->m_port_chng = 1; 6574 } 6575 break; 6576 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 6577 (void) sprintf(curr, "is online at " 6578 "6.0 Gbps"); 6579 if ((expd_handle == 0) && 6580 (enc_handle == 1)) { 6581 mpt->m_port_chng = 1; 6582 } 6583 break; 6584 default: 6585 (void) sprintf(curr, "state is " 6586 "unknown"); 6587 break; 6588 } 6589 6590 state = (link_rate & 6591 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >> 6592 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT; 6593 switch (state) { 6594 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 6595 (void) sprintf(prev, ", was disabled"); 6596 break; 6597 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 6598 (void) sprintf(prev, ", was offline, " 6599 "failed speed negotiation"); 6600 break; 6601 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 6602 (void) sprintf(prev, ", was SATA OOB " 6603 "complete"); 6604 break; 6605 case SMP_RESET_IN_PROGRESS: 6606 (void) sprintf(prev, ", was SMP reset " 6607 "in progress"); 6608 break; 6609 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 6610 (void) sprintf(prev, ", was online at " 6611 "1.5 Gbps"); 6612 break; 6613 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 6614 (void) sprintf(prev, ", was online at " 6615 "3.0 Gbps"); 6616 break; 6617 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 6618 (void) sprintf(prev, ", was online at " 6619 "6.0 Gbps"); 6620 break; 6621 default: 6622 break; 6623 } 6624 (void) sprintf(&string[strlen(string)], "link " 6625 "changed, "); 6626 break; 6627 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE: 6628 continue; 6629 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING: 6630 (void) sprintf(&string[strlen(string)], 6631 "target not responding, delaying " 6632 "removal"); 6633 break; 6634 } 6635 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n", 6636 mpt->m_instance, phy, dev_handle, string, curr, 6637 prev)); 6638 } 6639 if (topo_head != NULL) { 6640 /* 6641 * Launch DR taskq to handle topology change 6642 */ 6643 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 6644 mptsas_handle_dr, (void *)topo_head, 6645 DDI_NOSLEEP)) != DDI_SUCCESS) { 6646 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 6647 "for handle SAS DR event failed. \n"); 6648 } 6649 } 6650 break; 6651 } 6652 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 6653 { 6654 Mpi2EventDataIrConfigChangeList_t *irChangeList; 6655 mptsas_topo_change_list_t *topo_head = NULL; 6656 mptsas_topo_change_list_t *topo_tail = NULL; 6657 mptsas_topo_change_list_t *topo_node = NULL; 6658 mptsas_target_t *ptgt; 6659 mptsas_hash_table_t *tgttbl; 6660 uint8_t num_entries, i, reason; 6661 uint16_t volhandle, diskhandle; 6662 6663 irChangeList = (pMpi2EventDataIrConfigChangeList_t) 6664 eventreply->EventData; 6665 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 6666 &irChangeList->NumElements); 6667 6668 tgttbl = &mpt->m_active->m_tgttbl; 6669 6670 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received", 6671 mpt->m_instance)); 6672 6673 for (i = 0; i < num_entries; i++) { 6674 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 6675 &irChangeList->ConfigElement[i].ReasonCode); 6676 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6677 &irChangeList->ConfigElement[i].VolDevHandle); 6678 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 6679 &irChangeList->ConfigElement[i].PhysDiskDevHandle); 6680 6681 switch (reason) { 6682 case MPI2_EVENT_IR_CHANGE_RC_ADDED: 6683 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED: 6684 { 6685 NDBG20(("mptsas %d volume added\n", 6686 mpt->m_instance)); 6687 6688 topo_node = kmem_zalloc( 6689 sizeof (mptsas_topo_change_list_t), 6690 KM_SLEEP); 6691 6692 topo_node->mpt = mpt; 6693 topo_node->event = 6694 MPTSAS_DR_EVENT_RECONFIG_TARGET; 6695 topo_node->un.physport = 0xff; 6696 topo_node->devhdl = volhandle; 6697 topo_node->flags = 6698 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 6699 topo_node->object = NULL; 6700 if (topo_head == NULL) { 6701 topo_head = topo_tail = topo_node; 6702 } else { 6703 topo_tail->next = topo_node; 6704 topo_tail = topo_node; 6705 } 6706 break; 6707 } 6708 case MPI2_EVENT_IR_CHANGE_RC_REMOVED: 6709 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED: 6710 { 6711 NDBG20(("mptsas %d volume deleted\n", 6712 mpt->m_instance)); 6713 ptgt = mptsas_search_by_devhdl(tgttbl, 6714 volhandle); 6715 if (ptgt == NULL) 6716 break; 6717 6718 /* 6719 * Clear any flags related to volume 6720 */ 6721 (void) mptsas_delete_volume(mpt, volhandle); 6722 6723 /* 6724 * Update DR flag immediately avoid I/O failure 6725 */ 6726 mutex_enter(&mpt->m_tx_waitq_mutex); 6727 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 6728 mutex_exit(&mpt->m_tx_waitq_mutex); 6729 6730 topo_node = kmem_zalloc( 6731 sizeof (mptsas_topo_change_list_t), 6732 KM_SLEEP); 6733 topo_node->mpt = mpt; 6734 topo_node->un.phymask = ptgt->m_phymask; 6735 topo_node->event = 6736 MPTSAS_DR_EVENT_OFFLINE_TARGET; 6737 topo_node->devhdl = volhandle; 6738 topo_node->flags = 6739 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 6740 topo_node->object = (void *)ptgt; 6741 if (topo_head == NULL) { 6742 topo_head = topo_tail = topo_node; 6743 } else { 6744 topo_tail->next = topo_node; 6745 topo_tail = topo_node; 6746 } 6747 break; 6748 } 6749 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED: 6750 case MPI2_EVENT_IR_CHANGE_RC_HIDE: 6751 { 6752 ptgt = mptsas_search_by_devhdl(tgttbl, 6753 diskhandle); 6754 if (ptgt == NULL) 6755 break; 6756 6757 /* 6758 * Update DR flag immediately avoid I/O failure 6759 */ 6760 mutex_enter(&mpt->m_tx_waitq_mutex); 6761 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 6762 mutex_exit(&mpt->m_tx_waitq_mutex); 6763 6764 topo_node = kmem_zalloc( 6765 sizeof (mptsas_topo_change_list_t), 6766 KM_SLEEP); 6767 topo_node->mpt = mpt; 6768 topo_node->un.phymask = ptgt->m_phymask; 6769 topo_node->event = 6770 MPTSAS_DR_EVENT_OFFLINE_TARGET; 6771 topo_node->devhdl = diskhandle; 6772 topo_node->flags = 6773 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 6774 topo_node->object = (void *)ptgt; 6775 if (topo_head == NULL) { 6776 topo_head = topo_tail = topo_node; 6777 } else { 6778 topo_tail->next = topo_node; 6779 topo_tail = topo_node; 6780 } 6781 break; 6782 } 6783 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE: 6784 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED: 6785 { 6786 /* 6787 * The physical drive is released by a IR 6788 * volume. But we cannot get the the physport 6789 * or phynum from the event data, so we only 6790 * can get the physport/phynum after SAS 6791 * Device Page0 request for the devhdl. 6792 */ 6793 topo_node = kmem_zalloc( 6794 sizeof (mptsas_topo_change_list_t), 6795 KM_SLEEP); 6796 topo_node->mpt = mpt; 6797 topo_node->un.phymask = 0; 6798 topo_node->event = 6799 MPTSAS_DR_EVENT_RECONFIG_TARGET; 6800 topo_node->devhdl = diskhandle; 6801 topo_node->flags = 6802 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 6803 topo_node->object = NULL; 6804 mpt->m_port_chng = 1; 6805 if (topo_head == NULL) { 6806 topo_head = topo_tail = topo_node; 6807 } else { 6808 topo_tail->next = topo_node; 6809 topo_tail = topo_node; 6810 } 6811 break; 6812 } 6813 default: 6814 break; 6815 } 6816 } 6817 6818 if (topo_head != NULL) { 6819 /* 6820 * Launch DR taskq to handle topology change 6821 */ 6822 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 6823 mptsas_handle_dr, (void *)topo_head, 6824 DDI_NOSLEEP)) != DDI_SUCCESS) { 6825 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 6826 "for handle SAS DR event failed. \n"); 6827 } 6828 } 6829 break; 6830 } 6831 default: 6832 return (DDI_FAILURE); 6833 } 6834 6835 return (DDI_SUCCESS); 6836 } 6837 6838 /* 6839 * handle events from ioc 6840 */ 6841 static void 6842 mptsas_handle_event(void *args) 6843 { 6844 m_replyh_arg_t *replyh_arg; 6845 pMpi2EventNotificationReply_t eventreply; 6846 uint32_t event, iocloginfo, rfm; 6847 uint32_t status; 6848 uint8_t port; 6849 mptsas_t *mpt; 6850 uint_t iocstatus; 6851 6852 replyh_arg = (m_replyh_arg_t *)args; 6853 rfm = replyh_arg->rfm; 6854 mpt = replyh_arg->mpt; 6855 6856 mutex_enter(&mpt->m_mutex); 6857 6858 eventreply = (pMpi2EventNotificationReply_t) 6859 (mpt->m_reply_frame + (rfm - mpt->m_reply_frame_dma_addr)); 6860 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6861 6862 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 6863 &eventreply->IOCStatus)) { 6864 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 6865 mptsas_log(mpt, CE_WARN, 6866 "!mptsas_handle_event: IOCStatus=0x%x, " 6867 "IOCLogInfo=0x%x", iocstatus, 6868 ddi_get32(mpt->m_acc_reply_frame_hdl, 6869 &eventreply->IOCLogInfo)); 6870 } else { 6871 mptsas_log(mpt, CE_WARN, 6872 "mptsas_handle_event: IOCStatus=0x%x, " 6873 "IOCLogInfo=0x%x", iocstatus, 6874 ddi_get32(mpt->m_acc_reply_frame_hdl, 6875 &eventreply->IOCLogInfo)); 6876 } 6877 } 6878 6879 /* 6880 * figure out what kind of event we got and handle accordingly 6881 */ 6882 switch (event) { 6883 case MPI2_EVENT_LOG_ENTRY_ADDED: 6884 break; 6885 case MPI2_EVENT_LOG_DATA: 6886 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 6887 &eventreply->IOCLogInfo); 6888 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance, 6889 iocloginfo)); 6890 break; 6891 case MPI2_EVENT_STATE_CHANGE: 6892 NDBG20(("mptsas%d state change.", mpt->m_instance)); 6893 break; 6894 case MPI2_EVENT_HARD_RESET_RECEIVED: 6895 NDBG20(("mptsas%d event change.", mpt->m_instance)); 6896 break; 6897 case MPI2_EVENT_SAS_DISCOVERY: 6898 { 6899 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery; 6900 char string[80]; 6901 uint8_t rc; 6902 6903 sasdiscovery = 6904 (pMpi2EventDataSasDiscovery_t)eventreply->EventData; 6905 6906 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 6907 &sasdiscovery->ReasonCode); 6908 port = ddi_get8(mpt->m_acc_reply_frame_hdl, 6909 &sasdiscovery->PhysicalPort); 6910 status = ddi_get32(mpt->m_acc_reply_frame_hdl, 6911 &sasdiscovery->DiscoveryStatus); 6912 6913 string[0] = 0; 6914 switch (rc) { 6915 case MPI2_EVENT_SAS_DISC_RC_STARTED: 6916 (void) sprintf(string, "STARTING"); 6917 break; 6918 case MPI2_EVENT_SAS_DISC_RC_COMPLETED: 6919 (void) sprintf(string, "COMPLETED"); 6920 break; 6921 default: 6922 (void) sprintf(string, "UNKNOWN"); 6923 break; 6924 } 6925 6926 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string, 6927 port, status)); 6928 6929 break; 6930 } 6931 case MPI2_EVENT_EVENT_CHANGE: 6932 NDBG20(("mptsas%d event change.", mpt->m_instance)); 6933 break; 6934 case MPI2_EVENT_TASK_SET_FULL: 6935 { 6936 pMpi2EventDataTaskSetFull_t taskfull; 6937 6938 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData; 6939 6940 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n", 6941 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 6942 &taskfull->CurrentDepth))); 6943 break; 6944 } 6945 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 6946 { 6947 /* 6948 * SAS TOPOLOGY CHANGE LIST Event has already been handled 6949 * in mptsas_handle_event_sync() of interrupt context 6950 */ 6951 break; 6952 } 6953 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 6954 { 6955 pMpi2EventDataSasEnclDevStatusChange_t encstatus; 6956 uint8_t rc; 6957 char string[80]; 6958 6959 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t) 6960 eventreply->EventData; 6961 6962 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 6963 &encstatus->ReasonCode); 6964 switch (rc) { 6965 case MPI2_EVENT_SAS_ENCL_RC_ADDED: 6966 (void) sprintf(string, "added"); 6967 break; 6968 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING: 6969 (void) sprintf(string, ", not responding"); 6970 break; 6971 default: 6972 break; 6973 } 6974 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure %x%s\n", 6975 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 6976 &encstatus->EnclosureHandle), string)); 6977 break; 6978 } 6979 6980 /* 6981 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by 6982 * mptsas_handle_event_sync,in here just send ack message. 6983 */ 6984 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 6985 { 6986 pMpi2EventDataSasDeviceStatusChange_t statuschange; 6987 uint8_t rc; 6988 uint16_t devhdl; 6989 uint64_t wwn = 0; 6990 uint32_t wwn_lo, wwn_hi; 6991 6992 statuschange = (pMpi2EventDataSasDeviceStatusChange_t) 6993 eventreply->EventData; 6994 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 6995 &statuschange->ReasonCode); 6996 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl, 6997 (uint32_t *)(void *)&statuschange->SASAddress); 6998 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl, 6999 (uint32_t *)(void *)&statuschange->SASAddress + 1); 7000 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo; 7001 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7002 &statuschange->DevHandle); 7003 7004 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64, 7005 wwn)); 7006 7007 switch (rc) { 7008 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7009 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x", 7010 ddi_get8(mpt->m_acc_reply_frame_hdl, 7011 &statuschange->ASC), 7012 ddi_get8(mpt->m_acc_reply_frame_hdl, 7013 &statuschange->ASCQ))); 7014 break; 7015 7016 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7017 NDBG20(("Device not supported")); 7018 break; 7019 7020 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7021 NDBG20(("IOC internally generated the Target Reset " 7022 "for devhdl:%x", devhdl)); 7023 break; 7024 7025 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET: 7026 NDBG20(("IOC's internally generated Target Reset " 7027 "completed for devhdl:%x", devhdl)); 7028 break; 7029 7030 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7031 NDBG20(("IOC internally generated Abort Task")); 7032 break; 7033 7034 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL: 7035 NDBG20(("IOC's internally generated Abort Task " 7036 "completed")); 7037 break; 7038 7039 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 7040 NDBG20(("IOC internally generated Abort Task Set")); 7041 break; 7042 7043 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 7044 NDBG20(("IOC internally generated Clear Task Set")); 7045 break; 7046 7047 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 7048 NDBG20(("IOC internally generated Query Task")); 7049 break; 7050 7051 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION: 7052 NDBG20(("Device sent an Asynchronous Notification")); 7053 break; 7054 7055 default: 7056 break; 7057 } 7058 break; 7059 } 7060 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7061 { 7062 /* 7063 * IR TOPOLOGY CHANGE LIST Event has already been handled 7064 * in mpt_handle_event_sync() of interrupt context 7065 */ 7066 break; 7067 } 7068 case MPI2_EVENT_IR_OPERATION_STATUS: 7069 { 7070 Mpi2EventDataIrOperationStatus_t *irOpStatus; 7071 char reason_str[80]; 7072 uint8_t rc, percent; 7073 uint16_t handle; 7074 7075 irOpStatus = (pMpi2EventDataIrOperationStatus_t) 7076 eventreply->EventData; 7077 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7078 &irOpStatus->RAIDOperation); 7079 percent = ddi_get8(mpt->m_acc_reply_frame_hdl, 7080 &irOpStatus->PercentComplete); 7081 handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7082 &irOpStatus->VolDevHandle); 7083 7084 switch (rc) { 7085 case MPI2_EVENT_IR_RAIDOP_RESYNC: 7086 (void) sprintf(reason_str, "resync"); 7087 break; 7088 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION: 7089 (void) sprintf(reason_str, "online capacity " 7090 "expansion"); 7091 break; 7092 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK: 7093 (void) sprintf(reason_str, "consistency check"); 7094 break; 7095 default: 7096 (void) sprintf(reason_str, "unknown reason %x", 7097 rc); 7098 } 7099 7100 NDBG20(("mptsas%d raid operational status: (%s)" 7101 "\thandle(0x%04x), percent complete(%d)\n", 7102 mpt->m_instance, reason_str, handle, percent)); 7103 break; 7104 } 7105 case MPI2_EVENT_IR_VOLUME: 7106 { 7107 Mpi2EventDataIrVolume_t *irVolume; 7108 uint16_t devhandle; 7109 uint32_t state; 7110 int config, vol; 7111 mptsas_slots_t *slots = mpt->m_active; 7112 uint8_t found = FALSE; 7113 7114 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData; 7115 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 7116 &irVolume->NewValue); 7117 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7118 &irVolume->VolDevHandle); 7119 7120 NDBG20(("EVENT_IR_VOLUME event is received")); 7121 7122 /* 7123 * Get latest RAID info and then find the DevHandle for this 7124 * event in the configuration. If the DevHandle is not found 7125 * just exit the event. 7126 */ 7127 (void) mptsas_get_raid_info(mpt); 7128 for (config = 0; (config < slots->m_num_raid_configs) && 7129 (!found); config++) { 7130 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 7131 if (slots->m_raidconfig[config].m_raidvol[vol]. 7132 m_raidhandle == devhandle) { 7133 found = TRUE; 7134 break; 7135 } 7136 } 7137 } 7138 if (!found) { 7139 break; 7140 } 7141 7142 switch (irVolume->ReasonCode) { 7143 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED: 7144 { 7145 uint32_t i; 7146 slots->m_raidconfig[config].m_raidvol[vol].m_settings = 7147 state; 7148 7149 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING; 7150 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed" 7151 ", auto-config of hot-swap drives is %s" 7152 ", write caching is %s" 7153 ", hot-spare pool mask is %02x\n", 7154 vol, state & 7155 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE 7156 ? "disabled" : "enabled", 7157 i == MPI2_RAIDVOL0_SETTING_UNCHANGED 7158 ? "controlled by member disks" : 7159 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING 7160 ? "disabled" : 7161 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING 7162 ? "enabled" : 7163 "incorrectly set", 7164 (state >> 16) & 0xff); 7165 break; 7166 } 7167 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED: 7168 { 7169 slots->m_raidconfig[config].m_raidvol[vol].m_state = 7170 (uint8_t)state; 7171 7172 mptsas_log(mpt, CE_NOTE, 7173 "Volume %d is now %s\n", vol, 7174 state == MPI2_RAID_VOL_STATE_OPTIMAL 7175 ? "optimal" : 7176 state == MPI2_RAID_VOL_STATE_DEGRADED 7177 ? "degraded" : 7178 state == MPI2_RAID_VOL_STATE_ONLINE 7179 ? "online" : 7180 state == MPI2_RAID_VOL_STATE_INITIALIZING 7181 ? "initializing" : 7182 state == MPI2_RAID_VOL_STATE_FAILED 7183 ? "failed" : 7184 state == MPI2_RAID_VOL_STATE_MISSING 7185 ? "missing" : 7186 "state unknown"); 7187 break; 7188 } 7189 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED: 7190 { 7191 slots->m_raidconfig[config].m_raidvol[vol]. 7192 m_statusflags = state; 7193 7194 mptsas_log(mpt, CE_NOTE, 7195 " Volume %d is now %s%s%s%s%s%s%s%s%s\n", 7196 vol, 7197 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED 7198 ? ", enabled" : ", disabled", 7199 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED 7200 ? ", quiesced" : "", 7201 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE 7202 ? ", inactive" : ", active", 7203 state & 7204 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL 7205 ? ", bad block table is full" : "", 7206 state & 7207 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 7208 ? ", resync in progress" : "", 7209 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT 7210 ? ", background initialization in progress" : "", 7211 state & 7212 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION 7213 ? ", capacity expansion in progress" : "", 7214 state & 7215 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK 7216 ? ", consistency check in progress" : "", 7217 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB 7218 ? ", data scrub in progress" : ""); 7219 break; 7220 } 7221 default: 7222 break; 7223 } 7224 break; 7225 } 7226 case MPI2_EVENT_IR_PHYSICAL_DISK: 7227 { 7228 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk; 7229 uint16_t devhandle, enchandle, slot; 7230 uint32_t status, state; 7231 uint8_t physdisknum, reason; 7232 7233 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *) 7234 eventreply->EventData; 7235 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl, 7236 &irPhysDisk->PhysDiskNum); 7237 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7238 &irPhysDisk->PhysDiskDevHandle); 7239 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7240 &irPhysDisk->EnclosureHandle); 7241 slot = ddi_get16(mpt->m_acc_reply_frame_hdl, 7242 &irPhysDisk->Slot); 7243 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 7244 &irPhysDisk->NewValue); 7245 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 7246 &irPhysDisk->ReasonCode); 7247 7248 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received")); 7249 7250 switch (reason) { 7251 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED: 7252 mptsas_log(mpt, CE_NOTE, 7253 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 7254 "for enclosure with handle 0x%x is now in hot " 7255 "spare pool %d", 7256 physdisknum, devhandle, slot, enchandle, 7257 (state >> 16) & 0xff); 7258 break; 7259 7260 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED: 7261 status = state; 7262 mptsas_log(mpt, CE_NOTE, 7263 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 7264 "for enclosure with handle 0x%x is now " 7265 "%s%s%s%s%s\n", physdisknum, devhandle, slot, 7266 enchandle, 7267 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME 7268 ? ", inactive" : ", active", 7269 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 7270 ? ", out of sync" : "", 7271 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED 7272 ? ", quiesced" : "", 7273 status & 7274 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED 7275 ? ", write cache enabled" : "", 7276 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET 7277 ? ", capacity expansion target" : ""); 7278 break; 7279 7280 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED: 7281 mptsas_log(mpt, CE_NOTE, 7282 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 7283 "for enclosure with handle 0x%x is now %s\n", 7284 physdisknum, devhandle, slot, enchandle, 7285 state == MPI2_RAID_PD_STATE_OPTIMAL 7286 ? "optimal" : 7287 state == MPI2_RAID_PD_STATE_REBUILDING 7288 ? "rebuilding" : 7289 state == MPI2_RAID_PD_STATE_DEGRADED 7290 ? "degraded" : 7291 state == MPI2_RAID_PD_STATE_HOT_SPARE 7292 ? "a hot spare" : 7293 state == MPI2_RAID_PD_STATE_ONLINE 7294 ? "online" : 7295 state == MPI2_RAID_PD_STATE_OFFLINE 7296 ? "offline" : 7297 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE 7298 ? "not compatible" : 7299 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED 7300 ? "not configured" : 7301 "state unknown"); 7302 break; 7303 } 7304 break; 7305 } 7306 default: 7307 NDBG20(("mptsas%d: unknown event %x received", 7308 mpt->m_instance, event)); 7309 break; 7310 } 7311 7312 /* 7313 * Return the reply frame to the free queue. 7314 */ 7315 ddi_put32(mpt->m_acc_free_queue_hdl, 7316 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm); 7317 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 7318 DDI_DMA_SYNC_FORDEV); 7319 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 7320 mpt->m_free_index = 0; 7321 } 7322 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 7323 mpt->m_free_index); 7324 mutex_exit(&mpt->m_mutex); 7325 } 7326 7327 /* 7328 * invoked from timeout() to restart qfull cmds with throttle == 0 7329 */ 7330 static void 7331 mptsas_restart_cmd(void *arg) 7332 { 7333 mptsas_t *mpt = arg; 7334 mptsas_target_t *ptgt = NULL; 7335 7336 mutex_enter(&mpt->m_mutex); 7337 7338 mpt->m_restart_cmd_timeid = 0; 7339 7340 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 7341 MPTSAS_HASH_FIRST); 7342 while (ptgt != NULL) { 7343 if (ptgt->m_reset_delay == 0) { 7344 if (ptgt->m_t_throttle == QFULL_THROTTLE) { 7345 mptsas_set_throttle(mpt, ptgt, 7346 MAX_THROTTLE); 7347 } 7348 } 7349 7350 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 7351 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 7352 } 7353 mptsas_restart_hba(mpt); 7354 mutex_exit(&mpt->m_mutex); 7355 } 7356 7357 void 7358 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 7359 { 7360 int slot; 7361 mptsas_slots_t *slots = mpt->m_active; 7362 int t; 7363 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 7364 7365 ASSERT(cmd != NULL); 7366 ASSERT(cmd->cmd_queued == FALSE); 7367 7368 /* 7369 * Task Management cmds are removed in their own routines. Also, 7370 * we don't want to modify timeout based on TM cmds. 7371 */ 7372 if (cmd->cmd_flags & CFLAG_TM_CMD) { 7373 return; 7374 } 7375 7376 t = Tgt(cmd); 7377 slot = cmd->cmd_slot; 7378 7379 /* 7380 * remove the cmd. 7381 */ 7382 if (cmd == slots->m_slot[slot]) { 7383 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p", (void *)cmd)); 7384 slots->m_slot[slot] = NULL; 7385 mpt->m_ncmds--; 7386 7387 /* 7388 * only decrement per target ncmds if command 7389 * has a target associated with it. 7390 */ 7391 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 7392 ptgt->m_t_ncmds--; 7393 /* 7394 * reset throttle if we just ran an untagged command 7395 * to a tagged target 7396 */ 7397 if ((ptgt->m_t_ncmds == 0) && 7398 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) { 7399 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 7400 } 7401 } 7402 7403 } 7404 7405 /* 7406 * This is all we need to do for ioc commands. 7407 */ 7408 if (cmd->cmd_flags & CFLAG_CMDIOC) { 7409 mptsas_return_to_pool(mpt, cmd); 7410 return; 7411 } 7412 7413 /* 7414 * Figure out what to set tag Q timeout for... 7415 * 7416 * Optimize: If we have duplicate's of same timeout 7417 * we're using, then we'll use it again until we run 7418 * out of duplicates. This should be the normal case 7419 * for block and raw I/O. 7420 * If no duplicates, we have to scan through tag que and 7421 * find the longest timeout value and use it. This is 7422 * going to take a while... 7423 * Add 1 to m_n_slots to account for TM request. 7424 */ 7425 if (cmd->cmd_pkt->pkt_time == ptgt->m_timebase) { 7426 if (--(ptgt->m_dups) == 0) { 7427 if (ptgt->m_t_ncmds) { 7428 mptsas_cmd_t *ssp; 7429 uint_t n = 0; 7430 ushort_t nslots = (slots->m_n_slots + 1); 7431 ushort_t i; 7432 /* 7433 * This crude check assumes we don't do 7434 * this too often which seems reasonable 7435 * for block and raw I/O. 7436 */ 7437 for (i = 0; i < nslots; i++) { 7438 ssp = slots->m_slot[i]; 7439 if (ssp && (Tgt(ssp) == t) && 7440 (ssp->cmd_pkt->pkt_time > n)) { 7441 n = ssp->cmd_pkt->pkt_time; 7442 ptgt->m_dups = 1; 7443 } else if (ssp && (Tgt(ssp) == t) && 7444 (ssp->cmd_pkt->pkt_time == n)) { 7445 ptgt->m_dups++; 7446 } 7447 } 7448 ptgt->m_timebase = n; 7449 } else { 7450 ptgt->m_dups = 0; 7451 ptgt->m_timebase = 0; 7452 } 7453 } 7454 } 7455 ptgt->m_timeout = ptgt->m_timebase; 7456 7457 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]); 7458 } 7459 7460 /* 7461 * accept all cmds on the tx_waitq if any and then 7462 * start a fresh request from the top of the device queue. 7463 * 7464 * since there are always cmds queued on the tx_waitq, and rare cmds on 7465 * the instance waitq, so this function should not be invoked in the ISR, 7466 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the 7467 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU. 7468 */ 7469 static void 7470 mptsas_restart_hba(mptsas_t *mpt) 7471 { 7472 ASSERT(mutex_owned(&mpt->m_mutex)); 7473 7474 mutex_enter(&mpt->m_tx_waitq_mutex); 7475 if (mpt->m_tx_waitq) { 7476 mptsas_accept_tx_waitq(mpt); 7477 } 7478 mutex_exit(&mpt->m_tx_waitq_mutex); 7479 mptsas_restart_waitq(mpt); 7480 } 7481 7482 /* 7483 * start a fresh request from the top of the device queue 7484 */ 7485 static void 7486 mptsas_restart_waitq(mptsas_t *mpt) 7487 { 7488 mptsas_cmd_t *cmd, *next_cmd; 7489 mptsas_target_t *ptgt = NULL; 7490 7491 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt)); 7492 7493 ASSERT(mutex_owned(&mpt->m_mutex)); 7494 7495 /* 7496 * If there is a reset delay, don't start any cmds. Otherwise, start 7497 * as many cmds as possible. 7498 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 7499 * commands is m_max_requests - 2. 7500 */ 7501 cmd = mpt->m_waitq; 7502 7503 while (cmd != NULL) { 7504 next_cmd = cmd->cmd_linkp; 7505 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 7506 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 7507 /* 7508 * passthru command get slot need 7509 * set CFLAG_PREPARED. 7510 */ 7511 cmd->cmd_flags |= CFLAG_PREPARED; 7512 mptsas_waitq_delete(mpt, cmd); 7513 mptsas_start_passthru(mpt, cmd); 7514 } 7515 cmd = next_cmd; 7516 continue; 7517 } 7518 if (cmd->cmd_flags & CFLAG_CONFIG) { 7519 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 7520 /* 7521 * Send the config page request and delete it 7522 * from the waitq. 7523 */ 7524 cmd->cmd_flags |= CFLAG_PREPARED; 7525 mptsas_waitq_delete(mpt, cmd); 7526 mptsas_start_config_page_access(mpt, cmd); 7527 } 7528 cmd = next_cmd; 7529 continue; 7530 } 7531 if (cmd->cmd_flags & CFLAG_FW_DIAG) { 7532 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 7533 /* 7534 * Send the FW Diag request and delete if from 7535 * the waitq. 7536 */ 7537 cmd->cmd_flags |= CFLAG_PREPARED; 7538 mptsas_waitq_delete(mpt, cmd); 7539 mptsas_start_diag(mpt, cmd); 7540 } 7541 cmd = next_cmd; 7542 continue; 7543 } 7544 7545 ptgt = cmd->cmd_tgt_addr; 7546 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) && 7547 (ptgt->m_t_ncmds == 0)) { 7548 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 7549 } 7550 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 7551 (ptgt && (ptgt->m_reset_delay == 0)) && 7552 (ptgt && (ptgt->m_t_ncmds < 7553 ptgt->m_t_throttle))) { 7554 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 7555 mptsas_waitq_delete(mpt, cmd); 7556 (void) mptsas_start_cmd(mpt, cmd); 7557 } 7558 } 7559 cmd = next_cmd; 7560 } 7561 } 7562 /* 7563 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait). 7564 * Accept all those queued cmds before new cmd is accept so that the 7565 * cmds are sent in order. 7566 */ 7567 static void 7568 mptsas_accept_tx_waitq(mptsas_t *mpt) 7569 { 7570 mptsas_cmd_t *cmd; 7571 7572 ASSERT(mutex_owned(&mpt->m_mutex)); 7573 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex)); 7574 7575 /* 7576 * A Bus Reset could occur at any time and flush the tx_waitq, 7577 * so we cannot count on the tx_waitq to contain even one cmd. 7578 * And when the m_tx_waitq_mutex is released and run 7579 * mptsas_accept_pkt(), the tx_waitq may be flushed. 7580 */ 7581 cmd = mpt->m_tx_waitq; 7582 for (;;) { 7583 if ((cmd = mpt->m_tx_waitq) == NULL) { 7584 mpt->m_tx_draining = 0; 7585 break; 7586 } 7587 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) { 7588 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 7589 } 7590 cmd->cmd_linkp = NULL; 7591 mutex_exit(&mpt->m_tx_waitq_mutex); 7592 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT) 7593 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed " 7594 "to accept cmd on queue\n"); 7595 mutex_enter(&mpt->m_tx_waitq_mutex); 7596 } 7597 } 7598 7599 7600 /* 7601 * mpt tag type lookup 7602 */ 7603 static char mptsas_tag_lookup[] = 7604 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG}; 7605 7606 static int 7607 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 7608 { 7609 struct scsi_pkt *pkt = CMD2PKT(cmd); 7610 uint32_t control = 0; 7611 int n; 7612 caddr_t mem; 7613 pMpi2SCSIIORequest_t io_request; 7614 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 7615 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 7616 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 7617 uint16_t SMID, io_flags = 0; 7618 uint32_t request_desc_low, request_desc_high; 7619 7620 NDBG1(("mptsas_start_cmd: cmd=0x%p", (void *)cmd)); 7621 7622 /* 7623 * Set SMID and increment index. Rollover to 1 instead of 0 if index 7624 * is at the max. 0 is an invalid SMID, so we call the first index 1. 7625 */ 7626 SMID = cmd->cmd_slot; 7627 7628 /* 7629 * It is possible for back to back device reset to 7630 * happen before the reset delay has expired. That's 7631 * ok, just let the device reset go out on the bus. 7632 */ 7633 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 7634 ASSERT(ptgt->m_reset_delay == 0); 7635 } 7636 7637 /* 7638 * if a non-tagged cmd is submitted to an active tagged target 7639 * then drain before submitting this cmd; SCSI-2 allows RQSENSE 7640 * to be untagged 7641 */ 7642 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) && 7643 (ptgt->m_t_ncmds > 1) && 7644 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) && 7645 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) { 7646 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 7647 NDBG23(("target=%d, untagged cmd, start draining\n", 7648 ptgt->m_devhdl)); 7649 7650 if (ptgt->m_reset_delay == 0) { 7651 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 7652 } 7653 7654 mptsas_remove_cmd(mpt, cmd); 7655 cmd->cmd_pkt_flags |= FLAG_HEAD; 7656 mptsas_waitq_add(mpt, cmd); 7657 } 7658 return (DDI_FAILURE); 7659 } 7660 7661 /* 7662 * Set correct tag bits. 7663 */ 7664 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) { 7665 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags & 7666 FLAG_TAGMASK) >> 12)]) { 7667 case MSG_SIMPLE_QTAG: 7668 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 7669 break; 7670 case MSG_HEAD_QTAG: 7671 control |= MPI2_SCSIIO_CONTROL_HEADOFQ; 7672 break; 7673 case MSG_ORDERED_QTAG: 7674 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ; 7675 break; 7676 default: 7677 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n"); 7678 break; 7679 } 7680 } else { 7681 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) { 7682 ptgt->m_t_throttle = 1; 7683 } 7684 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 7685 } 7686 7687 if (cmd->cmd_pkt_flags & FLAG_TLR) { 7688 control |= MPI2_SCSIIO_CONTROL_TLR_ON; 7689 } 7690 7691 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 7692 io_request = (pMpi2SCSIIORequest_t)mem; 7693 7694 bzero(io_request, sizeof (Mpi2SCSIIORequest_t)); 7695 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof 7696 (MPI2_SCSI_IO_REQUEST, SGL) / 4); 7697 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0, 7698 MPI2_FUNCTION_SCSI_IO_REQUEST); 7699 7700 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp, 7701 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR); 7702 7703 io_flags = cmd->cmd_cdblen; 7704 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags); 7705 /* 7706 * setup the Scatter/Gather DMA list for this request 7707 */ 7708 if (cmd->cmd_cookiec > 0) { 7709 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl); 7710 } else { 7711 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength, 7712 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT | 7713 MPI2_SGE_FLAGS_END_OF_BUFFER | 7714 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 7715 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT); 7716 } 7717 7718 /* 7719 * save ARQ information 7720 */ 7721 ddi_put8(acc_hdl, &io_request->SenseBufferLength, cmd->cmd_rqslen); 7722 if ((cmd->cmd_flags & (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) == 7723 (CFLAG_SCBEXTERN | CFLAG_EXTARQBUFVALID)) { 7724 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, 7725 cmd->cmd_ext_arqcookie.dmac_address); 7726 } else { 7727 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, 7728 cmd->cmd_arqcookie.dmac_address); 7729 } 7730 7731 ddi_put32(acc_hdl, &io_request->Control, control); 7732 7733 NDBG31(("starting message=0x%p, with cmd=0x%p", 7734 (void *)(uintptr_t)mpt->m_req_frame_dma_addr, (void *)cmd)); 7735 7736 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 7737 7738 /* 7739 * Build request descriptor and write it to the request desc post reg. 7740 */ 7741 request_desc_low = (SMID << 16) + MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 7742 request_desc_high = ptgt->m_devhdl << 16; 7743 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high); 7744 7745 /* 7746 * Start timeout. 7747 */ 7748 #ifdef MPTSAS_TEST 7749 /* 7750 * Temporarily set timebase = 0; needed for 7751 * timeout torture test. 7752 */ 7753 if (mptsas_test_timeouts) { 7754 ptgt->m_timebase = 0; 7755 } 7756 #endif 7757 n = pkt->pkt_time - ptgt->m_timebase; 7758 7759 if (n == 0) { 7760 (ptgt->m_dups)++; 7761 ptgt->m_timeout = ptgt->m_timebase; 7762 } else if (n > 0) { 7763 ptgt->m_timeout = 7764 ptgt->m_timebase = pkt->pkt_time; 7765 ptgt->m_dups = 1; 7766 } else if (n < 0) { 7767 ptgt->m_timeout = ptgt->m_timebase; 7768 } 7769 #ifdef MPTSAS_TEST 7770 /* 7771 * Set back to a number higher than 7772 * mptsas_scsi_watchdog_tick 7773 * so timeouts will happen in mptsas_watchsubr 7774 */ 7775 if (mptsas_test_timeouts) { 7776 ptgt->m_timebase = 60; 7777 } 7778 #endif 7779 7780 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 7781 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 7782 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 7783 return (DDI_FAILURE); 7784 } 7785 return (DDI_SUCCESS); 7786 } 7787 7788 /* 7789 * Select a helper thread to handle current doneq 7790 */ 7791 static void 7792 mptsas_deliver_doneq_thread(mptsas_t *mpt) 7793 { 7794 uint64_t t, i; 7795 uint32_t min = 0xffffffff; 7796 mptsas_doneq_thread_list_t *item; 7797 7798 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 7799 item = &mpt->m_doneq_thread_id[i]; 7800 /* 7801 * If the completed command on help thread[i] less than 7802 * doneq_thread_threshold, then pick the thread[i]. Otherwise 7803 * pick a thread which has least completed command. 7804 */ 7805 7806 mutex_enter(&item->mutex); 7807 if (item->len < mpt->m_doneq_thread_threshold) { 7808 t = i; 7809 mutex_exit(&item->mutex); 7810 break; 7811 } 7812 if (item->len < min) { 7813 min = item->len; 7814 t = i; 7815 } 7816 mutex_exit(&item->mutex); 7817 } 7818 mutex_enter(&mpt->m_doneq_thread_id[t].mutex); 7819 mptsas_doneq_mv(mpt, t); 7820 cv_signal(&mpt->m_doneq_thread_id[t].cv); 7821 mutex_exit(&mpt->m_doneq_thread_id[t].mutex); 7822 } 7823 7824 /* 7825 * move the current global doneq to the doneq of thead[t] 7826 */ 7827 static void 7828 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t) 7829 { 7830 mptsas_cmd_t *cmd; 7831 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 7832 7833 ASSERT(mutex_owned(&item->mutex)); 7834 while ((cmd = mpt->m_doneq) != NULL) { 7835 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) { 7836 mpt->m_donetail = &mpt->m_doneq; 7837 } 7838 cmd->cmd_linkp = NULL; 7839 *item->donetail = cmd; 7840 item->donetail = &cmd->cmd_linkp; 7841 mpt->m_doneq_len--; 7842 item->len++; 7843 } 7844 } 7845 7846 void 7847 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd) 7848 { 7849 struct scsi_pkt *pkt = CMD2PKT(cmd); 7850 7851 /* Check all acc and dma handles */ 7852 if ((mptsas_check_acc_handle(mpt->m_datap) != 7853 DDI_SUCCESS) || 7854 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 7855 DDI_SUCCESS) || 7856 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 7857 DDI_SUCCESS) || 7858 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 7859 DDI_SUCCESS) || 7860 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 7861 DDI_SUCCESS) || 7862 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 7863 DDI_SUCCESS) || 7864 (mptsas_check_acc_handle(mpt->m_config_handle) != 7865 DDI_SUCCESS)) { 7866 ddi_fm_service_impact(mpt->m_dip, 7867 DDI_SERVICE_UNAFFECTED); 7868 ddi_fm_acc_err_clear(mpt->m_config_handle, 7869 DDI_FME_VER0); 7870 pkt->pkt_reason = CMD_TRAN_ERR; 7871 pkt->pkt_statistics = 0; 7872 } 7873 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 7874 DDI_SUCCESS) || 7875 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 7876 DDI_SUCCESS) || 7877 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 7878 DDI_SUCCESS) || 7879 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 7880 DDI_SUCCESS) || 7881 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 7882 DDI_SUCCESS)) { 7883 ddi_fm_service_impact(mpt->m_dip, 7884 DDI_SERVICE_UNAFFECTED); 7885 pkt->pkt_reason = CMD_TRAN_ERR; 7886 pkt->pkt_statistics = 0; 7887 } 7888 if (cmd->cmd_dmahandle && 7889 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) { 7890 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 7891 pkt->pkt_reason = CMD_TRAN_ERR; 7892 pkt->pkt_statistics = 0; 7893 } 7894 if ((cmd->cmd_extra_frames && 7895 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) != 7896 DDI_SUCCESS) || 7897 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) != 7898 DDI_SUCCESS)))) { 7899 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 7900 pkt->pkt_reason = CMD_TRAN_ERR; 7901 pkt->pkt_statistics = 0; 7902 } 7903 if (cmd->cmd_arqhandle && 7904 (mptsas_check_dma_handle(cmd->cmd_arqhandle) != DDI_SUCCESS)) { 7905 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 7906 pkt->pkt_reason = CMD_TRAN_ERR; 7907 pkt->pkt_statistics = 0; 7908 } 7909 if (cmd->cmd_ext_arqhandle && 7910 (mptsas_check_dma_handle(cmd->cmd_ext_arqhandle) != DDI_SUCCESS)) { 7911 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 7912 pkt->pkt_reason = CMD_TRAN_ERR; 7913 pkt->pkt_statistics = 0; 7914 } 7915 } 7916 7917 /* 7918 * These routines manipulate the queue of commands that 7919 * are waiting for their completion routines to be called. 7920 * The queue is usually in FIFO order but on an MP system 7921 * it's possible for the completion routines to get out 7922 * of order. If that's a problem you need to add a global 7923 * mutex around the code that calls the completion routine 7924 * in the interrupt handler. 7925 */ 7926 static void 7927 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 7928 { 7929 struct scsi_pkt *pkt = CMD2PKT(cmd); 7930 7931 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd)); 7932 7933 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0); 7934 cmd->cmd_linkp = NULL; 7935 cmd->cmd_flags |= CFLAG_FINISHED; 7936 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT; 7937 7938 mptsas_fma_check(mpt, cmd); 7939 7940 /* 7941 * only add scsi pkts that have completion routines to 7942 * the doneq. no intr cmds do not have callbacks. 7943 */ 7944 if (pkt && (pkt->pkt_comp)) { 7945 *mpt->m_donetail = cmd; 7946 mpt->m_donetail = &cmd->cmd_linkp; 7947 mpt->m_doneq_len++; 7948 } 7949 } 7950 7951 static mptsas_cmd_t * 7952 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t) 7953 { 7954 mptsas_cmd_t *cmd; 7955 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 7956 7957 /* pop one off the done queue */ 7958 if ((cmd = item->doneq) != NULL) { 7959 /* if the queue is now empty fix the tail pointer */ 7960 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd)); 7961 if ((item->doneq = cmd->cmd_linkp) == NULL) { 7962 item->donetail = &item->doneq; 7963 } 7964 cmd->cmd_linkp = NULL; 7965 item->len--; 7966 } 7967 return (cmd); 7968 } 7969 7970 static void 7971 mptsas_doneq_empty(mptsas_t *mpt) 7972 { 7973 if (mpt->m_doneq && !mpt->m_in_callback) { 7974 mptsas_cmd_t *cmd, *next; 7975 struct scsi_pkt *pkt; 7976 7977 mpt->m_in_callback = 1; 7978 cmd = mpt->m_doneq; 7979 mpt->m_doneq = NULL; 7980 mpt->m_donetail = &mpt->m_doneq; 7981 mpt->m_doneq_len = 0; 7982 7983 mutex_exit(&mpt->m_mutex); 7984 /* 7985 * run the completion routines of all the 7986 * completed commands 7987 */ 7988 while (cmd != NULL) { 7989 next = cmd->cmd_linkp; 7990 cmd->cmd_linkp = NULL; 7991 /* run this command's completion routine */ 7992 cmd->cmd_flags |= CFLAG_COMPLETED; 7993 pkt = CMD2PKT(cmd); 7994 mptsas_pkt_comp(pkt, cmd); 7995 cmd = next; 7996 } 7997 mutex_enter(&mpt->m_mutex); 7998 mpt->m_in_callback = 0; 7999 } 8000 } 8001 8002 /* 8003 * These routines manipulate the target's queue of pending requests 8004 */ 8005 void 8006 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 8007 { 8008 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd)); 8009 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8010 cmd->cmd_queued = TRUE; 8011 if (ptgt) 8012 ptgt->m_t_nwait++; 8013 if (cmd->cmd_pkt_flags & FLAG_HEAD) { 8014 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) { 8015 mpt->m_waitqtail = &cmd->cmd_linkp; 8016 } 8017 mpt->m_waitq = cmd; 8018 } else { 8019 cmd->cmd_linkp = NULL; 8020 *(mpt->m_waitqtail) = cmd; 8021 mpt->m_waitqtail = &cmd->cmd_linkp; 8022 } 8023 } 8024 8025 static mptsas_cmd_t * 8026 mptsas_waitq_rm(mptsas_t *mpt) 8027 { 8028 mptsas_cmd_t *cmd; 8029 mptsas_target_t *ptgt; 8030 NDBG7(("mptsas_waitq_rm")); 8031 8032 MPTSAS_WAITQ_RM(mpt, cmd); 8033 8034 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd)); 8035 if (cmd) { 8036 ptgt = cmd->cmd_tgt_addr; 8037 if (ptgt) { 8038 ptgt->m_t_nwait--; 8039 ASSERT(ptgt->m_t_nwait >= 0); 8040 } 8041 } 8042 return (cmd); 8043 } 8044 8045 /* 8046 * remove specified cmd from the middle of the wait queue. 8047 */ 8048 static void 8049 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 8050 { 8051 mptsas_cmd_t *prevp = mpt->m_waitq; 8052 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8053 8054 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8055 (void *)mpt, (void *)cmd)); 8056 if (ptgt) { 8057 ptgt->m_t_nwait--; 8058 ASSERT(ptgt->m_t_nwait >= 0); 8059 } 8060 8061 if (prevp == cmd) { 8062 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL) 8063 mpt->m_waitqtail = &mpt->m_waitq; 8064 8065 cmd->cmd_linkp = NULL; 8066 cmd->cmd_queued = FALSE; 8067 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8068 (void *)mpt, (void *)cmd)); 8069 return; 8070 } 8071 8072 while (prevp != NULL) { 8073 if (prevp->cmd_linkp == cmd) { 8074 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 8075 mpt->m_waitqtail = &prevp->cmd_linkp; 8076 8077 cmd->cmd_linkp = NULL; 8078 cmd->cmd_queued = FALSE; 8079 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8080 (void *)mpt, (void *)cmd)); 8081 return; 8082 } 8083 prevp = prevp->cmd_linkp; 8084 } 8085 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch"); 8086 } 8087 8088 static mptsas_cmd_t * 8089 mptsas_tx_waitq_rm(mptsas_t *mpt) 8090 { 8091 mptsas_cmd_t *cmd; 8092 NDBG7(("mptsas_tx_waitq_rm")); 8093 8094 MPTSAS_TX_WAITQ_RM(mpt, cmd); 8095 8096 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd)); 8097 8098 return (cmd); 8099 } 8100 8101 /* 8102 * remove specified cmd from the middle of the tx_waitq. 8103 */ 8104 static void 8105 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 8106 { 8107 mptsas_cmd_t *prevp = mpt->m_tx_waitq; 8108 8109 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 8110 (void *)mpt, (void *)cmd)); 8111 8112 if (prevp == cmd) { 8113 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) 8114 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 8115 8116 cmd->cmd_linkp = NULL; 8117 cmd->cmd_queued = FALSE; 8118 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 8119 (void *)mpt, (void *)cmd)); 8120 return; 8121 } 8122 8123 while (prevp != NULL) { 8124 if (prevp->cmd_linkp == cmd) { 8125 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 8126 mpt->m_tx_waitqtail = &prevp->cmd_linkp; 8127 8128 cmd->cmd_linkp = NULL; 8129 cmd->cmd_queued = FALSE; 8130 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 8131 (void *)mpt, (void *)cmd)); 8132 return; 8133 } 8134 prevp = prevp->cmd_linkp; 8135 } 8136 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch"); 8137 } 8138 8139 /* 8140 * device and bus reset handling 8141 * 8142 * Notes: 8143 * - RESET_ALL: reset the controller 8144 * - RESET_TARGET: reset the target specified in scsi_address 8145 */ 8146 static int 8147 mptsas_scsi_reset(struct scsi_address *ap, int level) 8148 { 8149 mptsas_t *mpt = ADDR2MPT(ap); 8150 int rval; 8151 mptsas_tgt_private_t *tgt_private; 8152 mptsas_target_t *ptgt = NULL; 8153 8154 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private; 8155 ptgt = tgt_private->t_private; 8156 if (ptgt == NULL) { 8157 return (FALSE); 8158 } 8159 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl, 8160 level)); 8161 8162 mutex_enter(&mpt->m_mutex); 8163 /* 8164 * if we are not in panic set up a reset delay for this target 8165 */ 8166 if (!ddi_in_panic()) { 8167 mptsas_setup_bus_reset_delay(mpt); 8168 } else { 8169 drv_usecwait(mpt->m_scsi_reset_delay * 1000); 8170 } 8171 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl); 8172 mutex_exit(&mpt->m_mutex); 8173 8174 /* 8175 * The transport layer expect to only see TRUE and 8176 * FALSE. Therefore, we will adjust the return value 8177 * if mptsas_do_scsi_reset returns FAILED. 8178 */ 8179 if (rval == FAILED) 8180 rval = FALSE; 8181 return (rval); 8182 } 8183 8184 static int 8185 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl) 8186 { 8187 int rval = FALSE; 8188 uint8_t config, disk; 8189 mptsas_slots_t *slots = mpt->m_active; 8190 8191 ASSERT(mutex_owned(&mpt->m_mutex)); 8192 8193 if (mptsas_debug_resets) { 8194 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d", 8195 devhdl); 8196 } 8197 8198 /* 8199 * Issue a Target Reset message to the target specified but not to a 8200 * disk making up a raid volume. Just look through the RAID config 8201 * Phys Disk list of DevHandles. If the target's DevHandle is in this 8202 * list, then don't reset this target. 8203 */ 8204 for (config = 0; config < slots->m_num_raid_configs; config++) { 8205 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 8206 if (devhdl == slots->m_raidconfig[config]. 8207 m_physdisk_devhdl[disk]) { 8208 return (TRUE); 8209 } 8210 } 8211 } 8212 8213 rval = mptsas_ioc_task_management(mpt, 8214 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0); 8215 8216 mptsas_doneq_empty(mpt); 8217 return (rval); 8218 } 8219 8220 static int 8221 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 8222 void (*callback)(caddr_t), caddr_t arg) 8223 { 8224 mptsas_t *mpt = ADDR2MPT(ap); 8225 8226 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target)); 8227 8228 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg, 8229 &mpt->m_mutex, &mpt->m_reset_notify_listf)); 8230 } 8231 8232 static int 8233 mptsas_get_name(struct scsi_device *sd, char *name, int len) 8234 { 8235 dev_info_t *lun_dip = NULL; 8236 8237 ASSERT(sd != NULL); 8238 ASSERT(name != NULL); 8239 lun_dip = sd->sd_dev; 8240 ASSERT(lun_dip != NULL); 8241 8242 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) { 8243 return (1); 8244 } else { 8245 return (0); 8246 } 8247 } 8248 8249 static int 8250 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len) 8251 { 8252 return (mptsas_get_name(sd, name, len)); 8253 } 8254 8255 void 8256 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what) 8257 { 8258 8259 NDBG25(("mptsas_set_throttle: throttle=%x", what)); 8260 8261 /* 8262 * if the bus is draining/quiesced, no changes to the throttles 8263 * are allowed. Not allowing change of throttles during draining 8264 * limits error recovery but will reduce draining time 8265 * 8266 * all throttles should have been set to HOLD_THROTTLE 8267 */ 8268 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) { 8269 return; 8270 } 8271 8272 if (what == HOLD_THROTTLE) { 8273 ptgt->m_t_throttle = HOLD_THROTTLE; 8274 } else if (ptgt->m_reset_delay == 0) { 8275 ptgt->m_t_throttle = what; 8276 } 8277 } 8278 8279 /* 8280 * Clean up from a device reset. 8281 * For the case of target reset, this function clears the waitq of all 8282 * commands for a particular target. For the case of abort task set, this 8283 * function clears the waitq of all commonds for a particular target/lun. 8284 */ 8285 static void 8286 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype) 8287 { 8288 mptsas_slots_t *slots = mpt->m_active; 8289 mptsas_cmd_t *cmd, *next_cmd; 8290 int slot; 8291 uchar_t reason; 8292 uint_t stat; 8293 8294 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun)); 8295 8296 /* 8297 * Make sure the I/O Controller has flushed all cmds 8298 * that are associated with this target for a target reset 8299 * and target/lun for abort task set. 8300 * Account for TM requests, which use the last SMID. 8301 */ 8302 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) { 8303 if ((cmd = slots->m_slot[slot]) == NULL) 8304 continue; 8305 reason = CMD_RESET; 8306 stat = STAT_DEV_RESET; 8307 switch (tasktype) { 8308 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 8309 if (Tgt(cmd) == target) { 8310 NDBG25(("mptsas_flush_target discovered non-" 8311 "NULL cmd in slot %d, tasktype 0x%x", slot, 8312 tasktype)); 8313 mptsas_dump_cmd(mpt, cmd); 8314 mptsas_remove_cmd(mpt, cmd); 8315 mptsas_set_pkt_reason(mpt, cmd, reason, stat); 8316 mptsas_doneq_add(mpt, cmd); 8317 } 8318 break; 8319 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 8320 reason = CMD_ABORTED; 8321 stat = STAT_ABORTED; 8322 /*FALLTHROUGH*/ 8323 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 8324 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 8325 8326 NDBG25(("mptsas_flush_target discovered non-" 8327 "NULL cmd in slot %d, tasktype 0x%x", slot, 8328 tasktype)); 8329 mptsas_dump_cmd(mpt, cmd); 8330 mptsas_remove_cmd(mpt, cmd); 8331 mptsas_set_pkt_reason(mpt, cmd, reason, 8332 stat); 8333 mptsas_doneq_add(mpt, cmd); 8334 } 8335 break; 8336 default: 8337 break; 8338 } 8339 } 8340 8341 /* 8342 * Flush the waitq and tx_waitq of this target's cmds 8343 */ 8344 cmd = mpt->m_waitq; 8345 8346 reason = CMD_RESET; 8347 stat = STAT_DEV_RESET; 8348 8349 switch (tasktype) { 8350 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 8351 while (cmd != NULL) { 8352 next_cmd = cmd->cmd_linkp; 8353 if (Tgt(cmd) == target) { 8354 mptsas_waitq_delete(mpt, cmd); 8355 mptsas_set_pkt_reason(mpt, cmd, 8356 reason, stat); 8357 mptsas_doneq_add(mpt, cmd); 8358 } 8359 cmd = next_cmd; 8360 } 8361 mutex_enter(&mpt->m_tx_waitq_mutex); 8362 cmd = mpt->m_tx_waitq; 8363 while (cmd != NULL) { 8364 next_cmd = cmd->cmd_linkp; 8365 if (Tgt(cmd) == target) { 8366 mptsas_tx_waitq_delete(mpt, cmd); 8367 mutex_exit(&mpt->m_tx_waitq_mutex); 8368 mptsas_set_pkt_reason(mpt, cmd, 8369 reason, stat); 8370 mptsas_doneq_add(mpt, cmd); 8371 mutex_enter(&mpt->m_tx_waitq_mutex); 8372 } 8373 cmd = next_cmd; 8374 } 8375 mutex_exit(&mpt->m_tx_waitq_mutex); 8376 break; 8377 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 8378 reason = CMD_ABORTED; 8379 stat = STAT_ABORTED; 8380 /*FALLTHROUGH*/ 8381 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 8382 while (cmd != NULL) { 8383 next_cmd = cmd->cmd_linkp; 8384 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 8385 mptsas_waitq_delete(mpt, cmd); 8386 mptsas_set_pkt_reason(mpt, cmd, 8387 reason, stat); 8388 mptsas_doneq_add(mpt, cmd); 8389 } 8390 cmd = next_cmd; 8391 } 8392 mutex_enter(&mpt->m_tx_waitq_mutex); 8393 cmd = mpt->m_tx_waitq; 8394 while (cmd != NULL) { 8395 next_cmd = cmd->cmd_linkp; 8396 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 8397 mptsas_tx_waitq_delete(mpt, cmd); 8398 mutex_exit(&mpt->m_tx_waitq_mutex); 8399 mptsas_set_pkt_reason(mpt, cmd, 8400 reason, stat); 8401 mptsas_doneq_add(mpt, cmd); 8402 mutex_enter(&mpt->m_tx_waitq_mutex); 8403 } 8404 cmd = next_cmd; 8405 } 8406 mutex_exit(&mpt->m_tx_waitq_mutex); 8407 break; 8408 default: 8409 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 8410 tasktype); 8411 break; 8412 } 8413 } 8414 8415 /* 8416 * Clean up hba state, abort all outstanding command and commands in waitq 8417 * reset timeout of all targets. 8418 */ 8419 static void 8420 mptsas_flush_hba(mptsas_t *mpt) 8421 { 8422 mptsas_slots_t *slots = mpt->m_active; 8423 mptsas_cmd_t *cmd; 8424 int slot; 8425 8426 NDBG25(("mptsas_flush_hba")); 8427 8428 /* 8429 * The I/O Controller should have already sent back 8430 * all commands via the scsi I/O reply frame. Make 8431 * sure all commands have been flushed. 8432 * Account for TM request, which use the last SMID. 8433 */ 8434 for (slot = 0; slot <= mpt->m_active->m_n_slots; slot++) { 8435 if ((cmd = slots->m_slot[slot]) == NULL) 8436 continue; 8437 8438 if (cmd->cmd_flags & CFLAG_CMDIOC) { 8439 /* 8440 * Need to make sure to tell everyone that might be 8441 * waiting on this command that it's going to fail. If 8442 * we get here, this command will never timeout because 8443 * the active command table is going to be re-allocated, 8444 * so there will be nothing to check against a time out. 8445 * Instead, mark the command as failed due to reset. 8446 */ 8447 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 8448 STAT_BUS_RESET); 8449 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 8450 (cmd->cmd_flags & CFLAG_CONFIG) || 8451 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 8452 cmd->cmd_flags |= CFLAG_FINISHED; 8453 cv_broadcast(&mpt->m_passthru_cv); 8454 cv_broadcast(&mpt->m_config_cv); 8455 cv_broadcast(&mpt->m_fw_diag_cv); 8456 } 8457 continue; 8458 } 8459 8460 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d", 8461 slot)); 8462 mptsas_dump_cmd(mpt, cmd); 8463 8464 mptsas_remove_cmd(mpt, cmd); 8465 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 8466 mptsas_doneq_add(mpt, cmd); 8467 } 8468 8469 /* 8470 * Flush the waitq. 8471 */ 8472 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) { 8473 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 8474 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 8475 (cmd->cmd_flags & CFLAG_CONFIG) || 8476 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 8477 cmd->cmd_flags |= CFLAG_FINISHED; 8478 cv_broadcast(&mpt->m_passthru_cv); 8479 cv_broadcast(&mpt->m_config_cv); 8480 cv_broadcast(&mpt->m_fw_diag_cv); 8481 } else { 8482 mptsas_doneq_add(mpt, cmd); 8483 } 8484 } 8485 8486 /* 8487 * Flush the tx_waitq 8488 */ 8489 mutex_enter(&mpt->m_tx_waitq_mutex); 8490 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) { 8491 mutex_exit(&mpt->m_tx_waitq_mutex); 8492 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 8493 mptsas_doneq_add(mpt, cmd); 8494 mutex_enter(&mpt->m_tx_waitq_mutex); 8495 } 8496 mutex_exit(&mpt->m_tx_waitq_mutex); 8497 } 8498 8499 /* 8500 * set pkt_reason and OR in pkt_statistics flag 8501 */ 8502 static void 8503 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason, 8504 uint_t stat) 8505 { 8506 #ifndef __lock_lint 8507 _NOTE(ARGUNUSED(mpt)) 8508 #endif 8509 8510 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x", 8511 (void *)cmd, reason, stat)); 8512 8513 if (cmd) { 8514 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) { 8515 cmd->cmd_pkt->pkt_reason = reason; 8516 } 8517 cmd->cmd_pkt->pkt_statistics |= stat; 8518 } 8519 } 8520 8521 static void 8522 mptsas_start_watch_reset_delay() 8523 { 8524 NDBG22(("mptsas_start_watch_reset_delay")); 8525 8526 mutex_enter(&mptsas_global_mutex); 8527 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) { 8528 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL, 8529 drv_usectohz((clock_t) 8530 MPTSAS_WATCH_RESET_DELAY_TICK * 1000)); 8531 ASSERT(mptsas_reset_watch != NULL); 8532 } 8533 mutex_exit(&mptsas_global_mutex); 8534 } 8535 8536 static void 8537 mptsas_setup_bus_reset_delay(mptsas_t *mpt) 8538 { 8539 mptsas_target_t *ptgt = NULL; 8540 8541 NDBG22(("mptsas_setup_bus_reset_delay")); 8542 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 8543 MPTSAS_HASH_FIRST); 8544 while (ptgt != NULL) { 8545 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 8546 ptgt->m_reset_delay = mpt->m_scsi_reset_delay; 8547 8548 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 8549 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 8550 } 8551 8552 mptsas_start_watch_reset_delay(); 8553 } 8554 8555 /* 8556 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every 8557 * mpt instance for active reset delays 8558 */ 8559 static void 8560 mptsas_watch_reset_delay(void *arg) 8561 { 8562 #ifndef __lock_lint 8563 _NOTE(ARGUNUSED(arg)) 8564 #endif 8565 8566 mptsas_t *mpt; 8567 int not_done = 0; 8568 8569 NDBG22(("mptsas_watch_reset_delay")); 8570 8571 mutex_enter(&mptsas_global_mutex); 8572 mptsas_reset_watch = 0; 8573 mutex_exit(&mptsas_global_mutex); 8574 rw_enter(&mptsas_global_rwlock, RW_READER); 8575 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) { 8576 if (mpt->m_tran == 0) { 8577 continue; 8578 } 8579 mutex_enter(&mpt->m_mutex); 8580 not_done += mptsas_watch_reset_delay_subr(mpt); 8581 mutex_exit(&mpt->m_mutex); 8582 } 8583 rw_exit(&mptsas_global_rwlock); 8584 8585 if (not_done) { 8586 mptsas_start_watch_reset_delay(); 8587 } 8588 } 8589 8590 static int 8591 mptsas_watch_reset_delay_subr(mptsas_t *mpt) 8592 { 8593 int done = 0; 8594 int restart = 0; 8595 mptsas_target_t *ptgt = NULL; 8596 8597 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt)); 8598 8599 ASSERT(mutex_owned(&mpt->m_mutex)); 8600 8601 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 8602 MPTSAS_HASH_FIRST); 8603 while (ptgt != NULL) { 8604 if (ptgt->m_reset_delay != 0) { 8605 ptgt->m_reset_delay -= 8606 MPTSAS_WATCH_RESET_DELAY_TICK; 8607 if (ptgt->m_reset_delay <= 0) { 8608 ptgt->m_reset_delay = 0; 8609 mptsas_set_throttle(mpt, ptgt, 8610 MAX_THROTTLE); 8611 restart++; 8612 } else { 8613 done = -1; 8614 } 8615 } 8616 8617 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 8618 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 8619 } 8620 8621 if (restart > 0) { 8622 mptsas_restart_hba(mpt); 8623 } 8624 return (done); 8625 } 8626 8627 #ifdef MPTSAS_TEST 8628 static void 8629 mptsas_test_reset(mptsas_t *mpt, int target) 8630 { 8631 mptsas_target_t *ptgt = NULL; 8632 8633 if (mptsas_rtest == target) { 8634 if (mptsas_do_scsi_reset(mpt, target) == TRUE) { 8635 mptsas_rtest = -1; 8636 } 8637 if (mptsas_rtest == -1) { 8638 NDBG22(("mptsas_test_reset success")); 8639 } 8640 } 8641 } 8642 #endif 8643 8644 /* 8645 * abort handling: 8646 * 8647 * Notes: 8648 * - if pkt is not NULL, abort just that command 8649 * - if pkt is NULL, abort all outstanding commands for target 8650 */ 8651 static int 8652 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 8653 { 8654 mptsas_t *mpt = ADDR2MPT(ap); 8655 int rval; 8656 mptsas_tgt_private_t *tgt_private; 8657 int target, lun; 8658 8659 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 8660 tran_tgt_private; 8661 ASSERT(tgt_private != NULL); 8662 target = tgt_private->t_private->m_devhdl; 8663 lun = tgt_private->t_lun; 8664 8665 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun)); 8666 8667 mutex_enter(&mpt->m_mutex); 8668 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt); 8669 mutex_exit(&mpt->m_mutex); 8670 return (rval); 8671 } 8672 8673 static int 8674 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt) 8675 { 8676 mptsas_cmd_t *sp = NULL; 8677 mptsas_slots_t *slots = mpt->m_active; 8678 int rval = FALSE; 8679 8680 ASSERT(mutex_owned(&mpt->m_mutex)); 8681 8682 /* 8683 * Abort the command pkt on the target/lun in ap. If pkt is 8684 * NULL, abort all outstanding commands on that target/lun. 8685 * If you can abort them, return 1, else return 0. 8686 * Each packet that's aborted should be sent back to the target 8687 * driver through the callback routine, with pkt_reason set to 8688 * CMD_ABORTED. 8689 * 8690 * abort cmd pkt on HBA hardware; clean out of outstanding 8691 * command lists, etc. 8692 */ 8693 if (pkt != NULL) { 8694 /* abort the specified packet */ 8695 sp = PKT2CMD(pkt); 8696 8697 if (sp->cmd_queued) { 8698 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted", 8699 (void *)sp)); 8700 mptsas_waitq_delete(mpt, sp); 8701 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED, 8702 STAT_ABORTED); 8703 mptsas_doneq_add(mpt, sp); 8704 rval = TRUE; 8705 goto done; 8706 } 8707 8708 /* 8709 * Have mpt firmware abort this command 8710 */ 8711 8712 if (slots->m_slot[sp->cmd_slot] != NULL) { 8713 rval = mptsas_ioc_task_management(mpt, 8714 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target, 8715 lun, NULL, 0, 0); 8716 8717 /* 8718 * The transport layer expects only TRUE and FALSE. 8719 * Therefore, if mptsas_ioc_task_management returns 8720 * FAILED we will return FALSE. 8721 */ 8722 if (rval == FAILED) 8723 rval = FALSE; 8724 goto done; 8725 } 8726 } 8727 8728 /* 8729 * If pkt is NULL then abort task set 8730 */ 8731 rval = mptsas_ioc_task_management(mpt, 8732 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0); 8733 8734 /* 8735 * The transport layer expects only TRUE and FALSE. 8736 * Therefore, if mptsas_ioc_task_management returns 8737 * FAILED we will return FALSE. 8738 */ 8739 if (rval == FAILED) 8740 rval = FALSE; 8741 8742 #ifdef MPTSAS_TEST 8743 if (rval && mptsas_test_stop) { 8744 debug_enter("mptsas_do_scsi_abort"); 8745 } 8746 #endif 8747 8748 done: 8749 mptsas_doneq_empty(mpt); 8750 return (rval); 8751 } 8752 8753 /* 8754 * capability handling: 8755 * (*tran_getcap). Get the capability named, and return its value. 8756 */ 8757 static int 8758 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly) 8759 { 8760 mptsas_t *mpt = ADDR2MPT(ap); 8761 int ckey; 8762 int rval = FALSE; 8763 8764 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x", 8765 ap->a_target, cap, tgtonly)); 8766 8767 mutex_enter(&mpt->m_mutex); 8768 8769 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 8770 mutex_exit(&mpt->m_mutex); 8771 return (UNDEFINED); 8772 } 8773 8774 switch (ckey) { 8775 case SCSI_CAP_DMA_MAX: 8776 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer; 8777 break; 8778 case SCSI_CAP_ARQ: 8779 rval = TRUE; 8780 break; 8781 case SCSI_CAP_MSG_OUT: 8782 case SCSI_CAP_PARITY: 8783 case SCSI_CAP_UNTAGGED_QING: 8784 rval = TRUE; 8785 break; 8786 case SCSI_CAP_TAGGED_QING: 8787 rval = TRUE; 8788 break; 8789 case SCSI_CAP_RESET_NOTIFICATION: 8790 rval = TRUE; 8791 break; 8792 case SCSI_CAP_LINKED_CMDS: 8793 rval = FALSE; 8794 break; 8795 case SCSI_CAP_QFULL_RETRIES: 8796 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran-> 8797 tran_tgt_private))->t_private->m_qfull_retries; 8798 break; 8799 case SCSI_CAP_QFULL_RETRY_INTERVAL: 8800 rval = drv_hztousec(((mptsas_tgt_private_t *) 8801 (ap->a_hba_tran->tran_tgt_private))-> 8802 t_private->m_qfull_retry_interval) / 1000; 8803 break; 8804 case SCSI_CAP_CDB_LEN: 8805 rval = CDB_GROUP4; 8806 break; 8807 case SCSI_CAP_INTERCONNECT_TYPE: 8808 rval = INTERCONNECT_SAS; 8809 break; 8810 case SCSI_CAP_TRAN_LAYER_RETRIES: 8811 if (mpt->m_ioc_capabilities & 8812 MPI2_IOCFACTS_CAPABILITY_TLR) 8813 rval = TRUE; 8814 else 8815 rval = FALSE; 8816 break; 8817 default: 8818 rval = UNDEFINED; 8819 break; 8820 } 8821 8822 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval)); 8823 8824 mutex_exit(&mpt->m_mutex); 8825 return (rval); 8826 } 8827 8828 /* 8829 * (*tran_setcap). Set the capability named to the value given. 8830 */ 8831 static int 8832 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly) 8833 { 8834 mptsas_t *mpt = ADDR2MPT(ap); 8835 int ckey; 8836 int rval = FALSE; 8837 8838 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x", 8839 ap->a_target, cap, value, tgtonly)); 8840 8841 if (!tgtonly) { 8842 return (rval); 8843 } 8844 8845 mutex_enter(&mpt->m_mutex); 8846 8847 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 8848 mutex_exit(&mpt->m_mutex); 8849 return (UNDEFINED); 8850 } 8851 8852 switch (ckey) { 8853 case SCSI_CAP_DMA_MAX: 8854 case SCSI_CAP_MSG_OUT: 8855 case SCSI_CAP_PARITY: 8856 case SCSI_CAP_INITIATOR_ID: 8857 case SCSI_CAP_LINKED_CMDS: 8858 case SCSI_CAP_UNTAGGED_QING: 8859 case SCSI_CAP_RESET_NOTIFICATION: 8860 /* 8861 * None of these are settable via 8862 * the capability interface. 8863 */ 8864 break; 8865 case SCSI_CAP_ARQ: 8866 /* 8867 * We cannot turn off arq so return false if asked to 8868 */ 8869 if (value) { 8870 rval = TRUE; 8871 } else { 8872 rval = FALSE; 8873 } 8874 break; 8875 case SCSI_CAP_TAGGED_QING: 8876 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *) 8877 (ap->a_hba_tran->tran_tgt_private))->t_private, 8878 MAX_THROTTLE); 8879 rval = TRUE; 8880 break; 8881 case SCSI_CAP_QFULL_RETRIES: 8882 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 8883 t_private->m_qfull_retries = (uchar_t)value; 8884 rval = TRUE; 8885 break; 8886 case SCSI_CAP_QFULL_RETRY_INTERVAL: 8887 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 8888 t_private->m_qfull_retry_interval = 8889 drv_usectohz(value * 1000); 8890 rval = TRUE; 8891 break; 8892 default: 8893 rval = UNDEFINED; 8894 break; 8895 } 8896 mutex_exit(&mpt->m_mutex); 8897 return (rval); 8898 } 8899 8900 /* 8901 * Utility routine for mptsas_ifsetcap/ifgetcap 8902 */ 8903 /*ARGSUSED*/ 8904 static int 8905 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp) 8906 { 8907 NDBG24(("mptsas_scsi_capchk: cap=%s", cap)); 8908 8909 if (!cap) 8910 return (FALSE); 8911 8912 *cidxp = scsi_hba_lookup_capstr(cap); 8913 return (TRUE); 8914 } 8915 8916 static int 8917 mptsas_alloc_active_slots(mptsas_t *mpt, int flag) 8918 { 8919 mptsas_slots_t *old_active = mpt->m_active; 8920 mptsas_slots_t *new_active; 8921 size_t size; 8922 int rval = -1; 8923 8924 if (mpt->m_ncmds) { 8925 NDBG9(("cannot change size of active slots array")); 8926 return (rval); 8927 } 8928 8929 size = MPTSAS_SLOTS_SIZE(mpt); 8930 new_active = kmem_zalloc(size, flag); 8931 if (new_active == NULL) { 8932 NDBG1(("new active alloc failed")); 8933 } else { 8934 /* 8935 * Since SMID 0 is reserved and the TM slot is reserved, the 8936 * number of slots that can be used at any one time is 8937 * m_max_requests - 2. 8938 */ 8939 mpt->m_active = new_active; 8940 mpt->m_active->m_n_slots = (mpt->m_max_requests - 2); 8941 mpt->m_active->m_size = size; 8942 mpt->m_active->m_tags = 1; 8943 if (old_active) { 8944 kmem_free(old_active, old_active->m_size); 8945 } 8946 rval = 0; 8947 } 8948 8949 return (rval); 8950 } 8951 8952 /* 8953 * Error logging, printing, and debug print routines. 8954 */ 8955 static char *mptsas_label = "mpt_sas"; 8956 8957 /*PRINTFLIKE3*/ 8958 void 8959 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...) 8960 { 8961 dev_info_t *dev; 8962 va_list ap; 8963 8964 if (mpt) { 8965 dev = mpt->m_dip; 8966 } else { 8967 dev = 0; 8968 } 8969 8970 mutex_enter(&mptsas_log_mutex); 8971 8972 va_start(ap, fmt); 8973 (void) vsprintf(mptsas_log_buf, fmt, ap); 8974 va_end(ap); 8975 8976 if (level == CE_CONT) { 8977 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf); 8978 } else { 8979 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf); 8980 } 8981 8982 mutex_exit(&mptsas_log_mutex); 8983 } 8984 8985 #ifdef MPTSAS_DEBUG 8986 /*PRINTFLIKE1*/ 8987 void 8988 mptsas_printf(char *fmt, ...) 8989 { 8990 dev_info_t *dev = 0; 8991 va_list ap; 8992 8993 mutex_enter(&mptsas_log_mutex); 8994 8995 va_start(ap, fmt); 8996 (void) vsprintf(mptsas_log_buf, fmt, ap); 8997 va_end(ap); 8998 8999 #ifdef PROM_PRINTF 9000 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf); 9001 #else 9002 scsi_log(dev, mptsas_label, SCSI_DEBUG, "%s\n", mptsas_log_buf); 9003 #endif 9004 mutex_exit(&mptsas_log_mutex); 9005 } 9006 #endif 9007 9008 /* 9009 * timeout handling 9010 */ 9011 static void 9012 mptsas_watch(void *arg) 9013 { 9014 #ifndef __lock_lint 9015 _NOTE(ARGUNUSED(arg)) 9016 #endif 9017 9018 mptsas_t *mpt; 9019 uint32_t doorbell; 9020 9021 NDBG30(("mptsas_watch")); 9022 9023 rw_enter(&mptsas_global_rwlock, RW_READER); 9024 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) { 9025 9026 mutex_enter(&mpt->m_mutex); 9027 9028 /* Skip device if not powered on */ 9029 if (mpt->m_options & MPTSAS_OPT_PM) { 9030 if (mpt->m_power_level == PM_LEVEL_D0) { 9031 (void) pm_busy_component(mpt->m_dip, 0); 9032 mpt->m_busy = 1; 9033 } else { 9034 mutex_exit(&mpt->m_mutex); 9035 continue; 9036 } 9037 } 9038 9039 /* 9040 * Check if controller is in a FAULT state. If so, reset it. 9041 */ 9042 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell); 9043 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 9044 doorbell &= MPI2_DOORBELL_DATA_MASK; 9045 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, " 9046 "code: %04x", doorbell); 9047 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 9048 mptsas_log(mpt, CE_WARN, "Reset failed" 9049 "after fault was detected"); 9050 } 9051 } 9052 9053 /* 9054 * For now, always call mptsas_watchsubr. 9055 */ 9056 mptsas_watchsubr(mpt); 9057 9058 if (mpt->m_options & MPTSAS_OPT_PM) { 9059 mpt->m_busy = 0; 9060 (void) pm_idle_component(mpt->m_dip, 0); 9061 } 9062 9063 mutex_exit(&mpt->m_mutex); 9064 } 9065 rw_exit(&mptsas_global_rwlock); 9066 9067 mutex_enter(&mptsas_global_mutex); 9068 if (mptsas_timeouts_enabled) 9069 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 9070 mutex_exit(&mptsas_global_mutex); 9071 } 9072 9073 static void 9074 mptsas_watchsubr(mptsas_t *mpt) 9075 { 9076 int i; 9077 mptsas_cmd_t *cmd; 9078 mptsas_target_t *ptgt = NULL; 9079 9080 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt)); 9081 9082 #ifdef MPTSAS_TEST 9083 if (mptsas_enable_untagged) { 9084 mptsas_test_untagged++; 9085 } 9086 #endif 9087 9088 /* 9089 * Check for commands stuck in active slot 9090 * Account for TM requests, which use the last SMID. 9091 */ 9092 for (i = 0; i <= mpt->m_active->m_n_slots; i++) { 9093 if ((cmd = mpt->m_active->m_slot[i]) != NULL) { 9094 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 9095 cmd->cmd_active_timeout -= 9096 mptsas_scsi_watchdog_tick; 9097 if (cmd->cmd_active_timeout <= 0) { 9098 /* 9099 * There seems to be a command stuck 9100 * in the active slot. Drain throttle. 9101 */ 9102 mptsas_set_throttle(mpt, 9103 cmd->cmd_tgt_addr, 9104 DRAIN_THROTTLE); 9105 } 9106 } 9107 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 9108 (cmd->cmd_flags & CFLAG_CONFIG) || 9109 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 9110 cmd->cmd_active_timeout -= 9111 mptsas_scsi_watchdog_tick; 9112 if (cmd->cmd_active_timeout <= 0) { 9113 /* 9114 * passthrough command timeout 9115 */ 9116 cmd->cmd_flags |= (CFLAG_FINISHED | 9117 CFLAG_TIMEOUT); 9118 cv_broadcast(&mpt->m_passthru_cv); 9119 cv_broadcast(&mpt->m_config_cv); 9120 cv_broadcast(&mpt->m_fw_diag_cv); 9121 } 9122 } 9123 } 9124 } 9125 9126 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 9127 MPTSAS_HASH_FIRST); 9128 while (ptgt != NULL) { 9129 /* 9130 * If we were draining due to a qfull condition, 9131 * go back to full throttle. 9132 */ 9133 if ((ptgt->m_t_throttle < MAX_THROTTLE) && 9134 (ptgt->m_t_throttle > HOLD_THROTTLE) && 9135 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) { 9136 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 9137 mptsas_restart_hba(mpt); 9138 } 9139 9140 if ((ptgt->m_t_ncmds > 0) && 9141 (ptgt->m_timebase)) { 9142 9143 if (ptgt->m_timebase <= 9144 mptsas_scsi_watchdog_tick) { 9145 ptgt->m_timebase += 9146 mptsas_scsi_watchdog_tick; 9147 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9148 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 9149 continue; 9150 } 9151 9152 ptgt->m_timeout -= mptsas_scsi_watchdog_tick; 9153 9154 if (ptgt->m_timeout < 0) { 9155 mptsas_cmd_timeout(mpt, ptgt->m_devhdl); 9156 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9157 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 9158 continue; 9159 } 9160 9161 if ((ptgt->m_timeout) <= 9162 mptsas_scsi_watchdog_tick) { 9163 NDBG23(("pending timeout")); 9164 mptsas_set_throttle(mpt, ptgt, 9165 DRAIN_THROTTLE); 9166 } 9167 } 9168 9169 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9170 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 9171 } 9172 } 9173 9174 /* 9175 * timeout recovery 9176 */ 9177 static void 9178 mptsas_cmd_timeout(mptsas_t *mpt, uint16_t devhdl) 9179 { 9180 9181 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl)); 9182 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for " 9183 "Target %d", devhdl); 9184 9185 /* 9186 * If the current target is not the target passed in, 9187 * try to reset that target. 9188 */ 9189 NDBG29(("mptsas_cmd_timeout: device reset")); 9190 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) { 9191 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout " 9192 "recovery failed!", devhdl); 9193 } 9194 } 9195 9196 /* 9197 * Device / Hotplug control 9198 */ 9199 static int 9200 mptsas_scsi_quiesce(dev_info_t *dip) 9201 { 9202 mptsas_t *mpt; 9203 scsi_hba_tran_t *tran; 9204 9205 tran = ddi_get_driver_private(dip); 9206 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 9207 return (-1); 9208 9209 return (mptsas_quiesce_bus(mpt)); 9210 } 9211 9212 static int 9213 mptsas_scsi_unquiesce(dev_info_t *dip) 9214 { 9215 mptsas_t *mpt; 9216 scsi_hba_tran_t *tran; 9217 9218 tran = ddi_get_driver_private(dip); 9219 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 9220 return (-1); 9221 9222 return (mptsas_unquiesce_bus(mpt)); 9223 } 9224 9225 static int 9226 mptsas_quiesce_bus(mptsas_t *mpt) 9227 { 9228 mptsas_target_t *ptgt = NULL; 9229 9230 NDBG28(("mptsas_quiesce_bus")); 9231 mutex_enter(&mpt->m_mutex); 9232 9233 /* Set all the throttles to zero */ 9234 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 9235 MPTSAS_HASH_FIRST); 9236 while (ptgt != NULL) { 9237 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 9238 9239 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9240 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 9241 } 9242 9243 /* If there are any outstanding commands in the queue */ 9244 if (mpt->m_ncmds) { 9245 mpt->m_softstate |= MPTSAS_SS_DRAINING; 9246 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 9247 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000))); 9248 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) { 9249 /* 9250 * Quiesce has been interrupted 9251 */ 9252 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 9253 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9254 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST); 9255 while (ptgt != NULL) { 9256 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 9257 9258 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9259 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 9260 } 9261 mptsas_restart_hba(mpt); 9262 if (mpt->m_quiesce_timeid != 0) { 9263 timeout_id_t tid = mpt->m_quiesce_timeid; 9264 mpt->m_quiesce_timeid = 0; 9265 mutex_exit(&mpt->m_mutex); 9266 (void) untimeout(tid); 9267 return (-1); 9268 } 9269 mutex_exit(&mpt->m_mutex); 9270 return (-1); 9271 } else { 9272 /* Bus has been quiesced */ 9273 ASSERT(mpt->m_quiesce_timeid == 0); 9274 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 9275 mpt->m_softstate |= MPTSAS_SS_QUIESCED; 9276 mutex_exit(&mpt->m_mutex); 9277 return (0); 9278 } 9279 } 9280 /* Bus was not busy - QUIESCED */ 9281 mutex_exit(&mpt->m_mutex); 9282 9283 return (0); 9284 } 9285 9286 static int 9287 mptsas_unquiesce_bus(mptsas_t *mpt) 9288 { 9289 mptsas_target_t *ptgt = NULL; 9290 9291 NDBG28(("mptsas_unquiesce_bus")); 9292 mutex_enter(&mpt->m_mutex); 9293 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED; 9294 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 9295 MPTSAS_HASH_FIRST); 9296 while (ptgt != NULL) { 9297 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 9298 9299 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9300 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 9301 } 9302 mptsas_restart_hba(mpt); 9303 mutex_exit(&mpt->m_mutex); 9304 return (0); 9305 } 9306 9307 static void 9308 mptsas_ncmds_checkdrain(void *arg) 9309 { 9310 mptsas_t *mpt = arg; 9311 mptsas_target_t *ptgt = NULL; 9312 9313 mutex_enter(&mpt->m_mutex); 9314 if (mpt->m_softstate & MPTSAS_SS_DRAINING) { 9315 mpt->m_quiesce_timeid = 0; 9316 if (mpt->m_ncmds == 0) { 9317 /* Command queue has been drained */ 9318 cv_signal(&mpt->m_cv); 9319 } else { 9320 /* 9321 * The throttle may have been reset because 9322 * of a SCSI bus reset 9323 */ 9324 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9325 &mpt->m_active->m_tgttbl, MPTSAS_HASH_FIRST); 9326 while (ptgt != NULL) { 9327 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 9328 9329 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 9330 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 9331 } 9332 9333 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 9334 mpt, (MPTSAS_QUIESCE_TIMEOUT * 9335 drv_usectohz(1000000))); 9336 } 9337 } 9338 mutex_exit(&mpt->m_mutex); 9339 } 9340 9341 /*ARGSUSED*/ 9342 static void 9343 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 9344 { 9345 int i; 9346 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp; 9347 char buf[128]; 9348 9349 buf[0] = '\0'; 9350 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd, 9351 Tgt(cmd), Lun(cmd))); 9352 (void) sprintf(&buf[0], "\tcdb=["); 9353 for (i = 0; i < (int)cmd->cmd_cdblen; i++) { 9354 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++); 9355 } 9356 (void) sprintf(&buf[strlen(buf)], " ]"); 9357 NDBG25(("?%s\n", buf)); 9358 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n", 9359 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics, 9360 cmd->cmd_pkt->pkt_state)); 9361 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", *(cmd->cmd_pkt->pkt_scbp), 9362 cmd->cmd_flags)); 9363 } 9364 9365 static void 9366 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd) 9367 { 9368 caddr_t memp; 9369 pMPI2RequestHeader_t request_hdrp; 9370 struct scsi_pkt *pkt = cmd->cmd_pkt; 9371 mptsas_pt_request_t *pt = pkt->pkt_ha_private; 9372 uint32_t request_size, data_size, dataout_size; 9373 uint32_t direction; 9374 ddi_dma_cookie_t data_cookie; 9375 ddi_dma_cookie_t dataout_cookie; 9376 uint32_t request_desc_low, request_desc_high = 0; 9377 uint32_t i, sense_bufp; 9378 uint8_t desc_type; 9379 uint8_t *request, function; 9380 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 9381 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 9382 9383 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 9384 9385 request = pt->request; 9386 direction = pt->direction; 9387 request_size = pt->request_size; 9388 data_size = pt->data_size; 9389 dataout_size = pt->dataout_size; 9390 data_cookie = pt->data_cookie; 9391 dataout_cookie = pt->dataout_cookie; 9392 9393 /* 9394 * Store the passthrough message in memory location 9395 * corresponding to our slot number 9396 */ 9397 memp = mpt->m_req_frame + (mpt->m_req_frame_size * cmd->cmd_slot); 9398 request_hdrp = (pMPI2RequestHeader_t)memp; 9399 bzero(memp, mpt->m_req_frame_size); 9400 9401 for (i = 0; i < request_size; i++) { 9402 bcopy(request + i, memp + i, 1); 9403 } 9404 9405 if (data_size || dataout_size) { 9406 pMpi2SGESimple64_t sgep; 9407 uint32_t sge_flags; 9408 9409 sgep = (pMpi2SGESimple64_t)((uint8_t *)request_hdrp + 9410 request_size); 9411 if (dataout_size) { 9412 9413 sge_flags = dataout_size | 9414 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 9415 MPI2_SGE_FLAGS_END_OF_BUFFER | 9416 MPI2_SGE_FLAGS_HOST_TO_IOC | 9417 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 9418 MPI2_SGE_FLAGS_SHIFT); 9419 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags); 9420 ddi_put32(acc_hdl, &sgep->Address.Low, 9421 (uint32_t)(dataout_cookie.dmac_laddress & 9422 0xffffffffull)); 9423 ddi_put32(acc_hdl, &sgep->Address.High, 9424 (uint32_t)(dataout_cookie.dmac_laddress 9425 >> 32)); 9426 sgep++; 9427 } 9428 sge_flags = data_size; 9429 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 9430 MPI2_SGE_FLAGS_LAST_ELEMENT | 9431 MPI2_SGE_FLAGS_END_OF_BUFFER | 9432 MPI2_SGE_FLAGS_END_OF_LIST | 9433 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 9434 MPI2_SGE_FLAGS_SHIFT); 9435 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 9436 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 9437 MPI2_SGE_FLAGS_SHIFT); 9438 } else { 9439 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 9440 MPI2_SGE_FLAGS_SHIFT); 9441 } 9442 ddi_put32(acc_hdl, &sgep->FlagsLength, 9443 sge_flags); 9444 ddi_put32(acc_hdl, &sgep->Address.Low, 9445 (uint32_t)(data_cookie.dmac_laddress & 9446 0xffffffffull)); 9447 ddi_put32(acc_hdl, &sgep->Address.High, 9448 (uint32_t)(data_cookie.dmac_laddress >> 32)); 9449 } 9450 9451 function = request_hdrp->Function; 9452 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 9453 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 9454 pMpi2SCSIIORequest_t scsi_io_req; 9455 9456 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp; 9457 /* 9458 * Put SGE for data and data_out buffer at the end of 9459 * scsi_io_request message header.(64 bytes in total) 9460 * Following above SGEs, the residual space will be 9461 * used by sense data. 9462 */ 9463 ddi_put8(acc_hdl, 9464 &scsi_io_req->SenseBufferLength, 9465 (uint8_t)(request_size - 64)); 9466 9467 sense_bufp = mpt->m_req_frame_dma_addr + 9468 (mpt->m_req_frame_size * cmd->cmd_slot); 9469 sense_bufp += 64; 9470 ddi_put32(acc_hdl, 9471 &scsi_io_req->SenseBufferLowAddress, sense_bufp); 9472 9473 /* 9474 * Set SGLOffset0 value 9475 */ 9476 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0, 9477 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4); 9478 9479 /* 9480 * Setup descriptor info. RAID passthrough must use the 9481 * default request descriptor which is already set, so if this 9482 * is a SCSI IO request, change the descriptor to SCSI IO. 9483 */ 9484 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 9485 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 9486 } 9487 request_desc_high = (ddi_get16(acc_hdl, 9488 &scsi_io_req->DevHandle) << 16); 9489 } 9490 9491 /* 9492 * We must wait till the message has been completed before 9493 * beginning the next message so we wait for this one to 9494 * finish. 9495 */ 9496 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 9497 request_desc_low = (cmd->cmd_slot << 16) + desc_type; 9498 cmd->cmd_rfm = NULL; 9499 MPTSAS_START_CMD(mpt, request_desc_low, request_desc_high); 9500 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 9501 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 9502 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 9503 } 9504 } 9505 9506 9507 9508 static int 9509 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 9510 uint8_t *data, uint32_t request_size, uint32_t reply_size, 9511 uint32_t data_size, uint32_t direction, uint8_t *dataout, 9512 uint32_t dataout_size, short timeout, int mode) 9513 { 9514 mptsas_pt_request_t pt; 9515 mptsas_dma_alloc_state_t data_dma_state; 9516 mptsas_dma_alloc_state_t dataout_dma_state; 9517 caddr_t memp; 9518 mptsas_cmd_t *cmd = NULL; 9519 struct scsi_pkt *pkt; 9520 uint32_t reply_len = 0, sense_len = 0; 9521 pMPI2RequestHeader_t request_hdrp; 9522 pMPI2RequestHeader_t request_msg; 9523 pMPI2DefaultReply_t reply_msg; 9524 Mpi2SCSIIOReply_t rep_msg; 9525 int i, status = 0, pt_flags = 0, rv = 0; 9526 int rvalue; 9527 uint8_t function; 9528 9529 ASSERT(mutex_owned(&mpt->m_mutex)); 9530 9531 reply_msg = (pMPI2DefaultReply_t)(&rep_msg); 9532 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY)); 9533 request_msg = kmem_zalloc(request_size, KM_SLEEP); 9534 9535 mutex_exit(&mpt->m_mutex); 9536 /* 9537 * copy in the request buffer since it could be used by 9538 * another thread when the pt request into waitq 9539 */ 9540 if (ddi_copyin(request, request_msg, request_size, mode)) { 9541 mutex_enter(&mpt->m_mutex); 9542 status = EFAULT; 9543 mptsas_log(mpt, CE_WARN, "failed to copy request data"); 9544 goto out; 9545 } 9546 mutex_enter(&mpt->m_mutex); 9547 9548 function = request_msg->Function; 9549 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) { 9550 pMpi2SCSITaskManagementRequest_t task; 9551 task = (pMpi2SCSITaskManagementRequest_t)request_msg; 9552 mptsas_setup_bus_reset_delay(mpt); 9553 rv = mptsas_ioc_task_management(mpt, task->TaskType, 9554 task->DevHandle, (int)task->LUN[1], reply, reply_size, 9555 mode); 9556 9557 if (rv != TRUE) { 9558 status = EIO; 9559 mptsas_log(mpt, CE_WARN, "task management failed"); 9560 } 9561 goto out; 9562 } 9563 9564 if (data_size != 0) { 9565 data_dma_state.size = data_size; 9566 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) { 9567 status = ENOMEM; 9568 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 9569 "resource"); 9570 goto out; 9571 } 9572 pt_flags |= MPTSAS_DATA_ALLOCATED; 9573 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 9574 mutex_exit(&mpt->m_mutex); 9575 for (i = 0; i < data_size; i++) { 9576 if (ddi_copyin(data + i, (uint8_t *) 9577 data_dma_state.memp + i, 1, mode)) { 9578 mutex_enter(&mpt->m_mutex); 9579 status = EFAULT; 9580 mptsas_log(mpt, CE_WARN, "failed to " 9581 "copy read data"); 9582 goto out; 9583 } 9584 } 9585 mutex_enter(&mpt->m_mutex); 9586 } 9587 } 9588 9589 if (dataout_size != 0) { 9590 dataout_dma_state.size = dataout_size; 9591 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) { 9592 status = ENOMEM; 9593 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 9594 "resource"); 9595 goto out; 9596 } 9597 pt_flags |= MPTSAS_DATAOUT_ALLOCATED; 9598 mutex_exit(&mpt->m_mutex); 9599 for (i = 0; i < dataout_size; i++) { 9600 if (ddi_copyin(dataout + i, (uint8_t *) 9601 dataout_dma_state.memp + i, 1, mode)) { 9602 mutex_enter(&mpt->m_mutex); 9603 mptsas_log(mpt, CE_WARN, "failed to copy out" 9604 " data"); 9605 status = EFAULT; 9606 goto out; 9607 } 9608 } 9609 mutex_enter(&mpt->m_mutex); 9610 } 9611 9612 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 9613 status = EAGAIN; 9614 mptsas_log(mpt, CE_NOTE, "event ack command pool is full"); 9615 goto out; 9616 } 9617 pt_flags |= MPTSAS_REQUEST_POOL_CMD; 9618 9619 bzero((caddr_t)cmd, sizeof (*cmd)); 9620 bzero((caddr_t)pkt, scsi_pkt_size()); 9621 bzero((caddr_t)&pt, sizeof (pt)); 9622 9623 cmd->ioc_cmd_slot = (uint32_t)(rvalue); 9624 9625 pt.request = (uint8_t *)request_msg; 9626 pt.direction = direction; 9627 pt.request_size = request_size; 9628 pt.data_size = data_size; 9629 pt.dataout_size = dataout_size; 9630 pt.data_cookie = data_dma_state.cookie; 9631 pt.dataout_cookie = dataout_dma_state.cookie; 9632 9633 /* 9634 * Form a blank cmd/pkt to store the acknowledgement message 9635 */ 9636 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0]; 9637 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 9638 pkt->pkt_ha_private = (opaque_t)&pt; 9639 pkt->pkt_flags = FLAG_HEAD; 9640 pkt->pkt_time = timeout; 9641 cmd->cmd_pkt = pkt; 9642 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU; 9643 9644 /* 9645 * Save the command in a slot 9646 */ 9647 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 9648 /* 9649 * Once passthru command get slot, set cmd_flags 9650 * CFLAG_PREPARED. 9651 */ 9652 cmd->cmd_flags |= CFLAG_PREPARED; 9653 mptsas_start_passthru(mpt, cmd); 9654 } else { 9655 mptsas_waitq_add(mpt, cmd); 9656 } 9657 9658 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 9659 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex); 9660 } 9661 9662 if (cmd->cmd_flags & CFLAG_PREPARED) { 9663 memp = mpt->m_req_frame + (mpt->m_req_frame_size * 9664 cmd->cmd_slot); 9665 request_hdrp = (pMPI2RequestHeader_t)memp; 9666 } 9667 9668 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 9669 status = ETIMEDOUT; 9670 mptsas_log(mpt, CE_WARN, "passthrough command timeout"); 9671 pt_flags |= MPTSAS_CMD_TIMEOUT; 9672 goto out; 9673 } 9674 9675 if (cmd->cmd_rfm) { 9676 /* 9677 * cmd_rfm is zero means the command reply is a CONTEXT 9678 * reply and no PCI Write to post the free reply SMFA 9679 * because no reply message frame is used. 9680 * cmd_rfm is non-zero means the reply is a ADDRESS 9681 * reply and reply message frame is used. 9682 */ 9683 pt_flags |= MPTSAS_ADDRESS_REPLY; 9684 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 9685 DDI_DMA_SYNC_FORCPU); 9686 reply_msg = (pMPI2DefaultReply_t) 9687 (mpt->m_reply_frame + (cmd->cmd_rfm - 9688 mpt->m_reply_frame_dma_addr)); 9689 } 9690 9691 mptsas_fma_check(mpt, cmd); 9692 if (pkt->pkt_reason == CMD_TRAN_ERR) { 9693 status = EAGAIN; 9694 mptsas_log(mpt, CE_WARN, "passthru fma error"); 9695 goto out; 9696 } 9697 if (pkt->pkt_reason == CMD_RESET) { 9698 status = EAGAIN; 9699 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru"); 9700 goto out; 9701 } 9702 9703 if (pkt->pkt_reason == CMD_INCOMPLETE) { 9704 status = EIO; 9705 mptsas_log(mpt, CE_WARN, "passthrough command incomplete"); 9706 goto out; 9707 } 9708 9709 mutex_exit(&mpt->m_mutex); 9710 if (cmd->cmd_flags & CFLAG_PREPARED) { 9711 function = request_hdrp->Function; 9712 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 9713 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 9714 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 9715 sense_len = reply_size - reply_len; 9716 } else { 9717 reply_len = reply_size; 9718 sense_len = 0; 9719 } 9720 9721 for (i = 0; i < reply_len; i++) { 9722 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1, 9723 mode)) { 9724 mutex_enter(&mpt->m_mutex); 9725 status = EFAULT; 9726 mptsas_log(mpt, CE_WARN, "failed to copy out " 9727 "reply data"); 9728 goto out; 9729 } 9730 } 9731 for (i = 0; i < sense_len; i++) { 9732 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i, 9733 reply + reply_len + i, 1, mode)) { 9734 mutex_enter(&mpt->m_mutex); 9735 status = EFAULT; 9736 mptsas_log(mpt, CE_WARN, "failed to copy out " 9737 "sense data"); 9738 goto out; 9739 } 9740 } 9741 } 9742 9743 if (data_size) { 9744 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) { 9745 (void) ddi_dma_sync(data_dma_state.handle, 0, 0, 9746 DDI_DMA_SYNC_FORCPU); 9747 for (i = 0; i < data_size; i++) { 9748 if (ddi_copyout((uint8_t *)( 9749 data_dma_state.memp + i), data + i, 1, 9750 mode)) { 9751 mutex_enter(&mpt->m_mutex); 9752 status = EFAULT; 9753 mptsas_log(mpt, CE_WARN, "failed to " 9754 "copy out the reply data"); 9755 goto out; 9756 } 9757 } 9758 } 9759 } 9760 mutex_enter(&mpt->m_mutex); 9761 out: 9762 /* 9763 * Put the reply frame back on the free queue, increment the free 9764 * index, and write the new index to the free index register. But only 9765 * if this reply is an ADDRESS reply. 9766 */ 9767 if (pt_flags & MPTSAS_ADDRESS_REPLY) { 9768 ddi_put32(mpt->m_acc_free_queue_hdl, 9769 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 9770 cmd->cmd_rfm); 9771 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 9772 DDI_DMA_SYNC_FORDEV); 9773 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 9774 mpt->m_free_index = 0; 9775 } 9776 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 9777 mpt->m_free_index); 9778 } 9779 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 9780 mptsas_remove_cmd(mpt, cmd); 9781 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD); 9782 } 9783 if (pt_flags & MPTSAS_REQUEST_POOL_CMD) 9784 mptsas_return_to_pool(mpt, cmd); 9785 if (pt_flags & MPTSAS_DATA_ALLOCATED) { 9786 if (mptsas_check_dma_handle(data_dma_state.handle) != 9787 DDI_SUCCESS) { 9788 ddi_fm_service_impact(mpt->m_dip, 9789 DDI_SERVICE_UNAFFECTED); 9790 status = EFAULT; 9791 } 9792 mptsas_dma_free(&data_dma_state); 9793 } 9794 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) { 9795 if (mptsas_check_dma_handle(dataout_dma_state.handle) != 9796 DDI_SUCCESS) { 9797 ddi_fm_service_impact(mpt->m_dip, 9798 DDI_SERVICE_UNAFFECTED); 9799 status = EFAULT; 9800 } 9801 mptsas_dma_free(&dataout_dma_state); 9802 } 9803 if (pt_flags & MPTSAS_CMD_TIMEOUT) { 9804 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 9805 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed"); 9806 } 9807 } 9808 if (request_msg) 9809 kmem_free(request_msg, request_size); 9810 9811 return (status); 9812 } 9813 9814 static int 9815 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode) 9816 { 9817 /* 9818 * If timeout is 0, set timeout to default of 60 seconds. 9819 */ 9820 if (data->Timeout == 0) { 9821 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT; 9822 } 9823 9824 if (((data->DataSize == 0) && 9825 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) || 9826 ((data->DataSize != 0) && 9827 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) || 9828 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) || 9829 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) && 9830 (data->DataOutSize != 0))))) { 9831 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) { 9832 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ; 9833 } else { 9834 data->DataOutSize = 0; 9835 } 9836 /* 9837 * Send passthru request messages 9838 */ 9839 return (mptsas_do_passthru(mpt, 9840 (uint8_t *)((uintptr_t)data->PtrRequest), 9841 (uint8_t *)((uintptr_t)data->PtrReply), 9842 (uint8_t *)((uintptr_t)data->PtrData), 9843 data->RequestSize, data->ReplySize, 9844 data->DataSize, data->DataDirection, 9845 (uint8_t *)((uintptr_t)data->PtrDataOut), 9846 data->DataOutSize, data->Timeout, mode)); 9847 } else { 9848 return (EINVAL); 9849 } 9850 } 9851 9852 static uint8_t 9853 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id) 9854 { 9855 uint8_t index; 9856 9857 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) { 9858 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) { 9859 return (index); 9860 } 9861 } 9862 9863 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND); 9864 } 9865 9866 static void 9867 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd) 9868 { 9869 pMpi2DiagBufferPostRequest_t pDiag_post_msg; 9870 pMpi2DiagReleaseRequest_t pDiag_release_msg; 9871 struct scsi_pkt *pkt = cmd->cmd_pkt; 9872 mptsas_diag_request_t *diag = pkt->pkt_ha_private; 9873 uint32_t request_desc_low, i; 9874 9875 ASSERT(mutex_owned(&mpt->m_mutex)); 9876 9877 /* 9878 * Form the diag message depending on the post or release function. 9879 */ 9880 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) { 9881 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t) 9882 (mpt->m_req_frame + (mpt->m_req_frame_size * 9883 cmd->cmd_slot)); 9884 bzero(pDiag_post_msg, mpt->m_req_frame_size); 9885 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function, 9886 diag->function); 9887 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType, 9888 diag->pBuffer->buffer_type); 9889 ddi_put8(mpt->m_acc_req_frame_hdl, 9890 &pDiag_post_msg->ExtendedType, 9891 diag->pBuffer->extended_type); 9892 ddi_put32(mpt->m_acc_req_frame_hdl, 9893 &pDiag_post_msg->BufferLength, 9894 diag->pBuffer->buffer_data.size); 9895 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4); 9896 i++) { 9897 ddi_put32(mpt->m_acc_req_frame_hdl, 9898 &pDiag_post_msg->ProductSpecific[i], 9899 diag->pBuffer->product_specific[i]); 9900 } 9901 ddi_put32(mpt->m_acc_req_frame_hdl, 9902 &pDiag_post_msg->BufferAddress.Low, 9903 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 9904 & 0xffffffffull)); 9905 ddi_put32(mpt->m_acc_req_frame_hdl, 9906 &pDiag_post_msg->BufferAddress.High, 9907 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 9908 >> 32)); 9909 } else { 9910 pDiag_release_msg = (pMpi2DiagReleaseRequest_t) 9911 (mpt->m_req_frame + (mpt->m_req_frame_size * 9912 cmd->cmd_slot)); 9913 bzero(pDiag_release_msg, mpt->m_req_frame_size); 9914 ddi_put8(mpt->m_acc_req_frame_hdl, 9915 &pDiag_release_msg->Function, diag->function); 9916 ddi_put8(mpt->m_acc_req_frame_hdl, 9917 &pDiag_release_msg->BufferType, 9918 diag->pBuffer->buffer_type); 9919 } 9920 9921 /* 9922 * Send the message 9923 */ 9924 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0, 9925 DDI_DMA_SYNC_FORDEV); 9926 request_desc_low = (cmd->cmd_slot << 16) + 9927 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 9928 cmd->cmd_rfm = NULL; 9929 MPTSAS_START_CMD(mpt, request_desc_low, 0); 9930 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 9931 DDI_SUCCESS) || 9932 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 9933 DDI_SUCCESS)) { 9934 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 9935 } 9936 } 9937 9938 static int 9939 mptsas_post_fw_diag_buffer(mptsas_t *mpt, 9940 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code) 9941 { 9942 mptsas_diag_request_t diag; 9943 int status, slot_num, post_flags = 0; 9944 mptsas_cmd_t *cmd = NULL; 9945 struct scsi_pkt *pkt; 9946 pMpi2DiagBufferPostReply_t reply; 9947 uint16_t iocstatus; 9948 uint32_t iocloginfo, transfer_length; 9949 9950 /* 9951 * If buffer is not enabled, just leave. 9952 */ 9953 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED; 9954 if (!pBuffer->enabled) { 9955 status = DDI_FAILURE; 9956 goto out; 9957 } 9958 9959 /* 9960 * Clear some flags initially. 9961 */ 9962 pBuffer->force_release = FALSE; 9963 pBuffer->valid_data = FALSE; 9964 pBuffer->owned_by_firmware = FALSE; 9965 9966 /* 9967 * Get a cmd buffer from the cmd buffer pool 9968 */ 9969 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 9970 status = DDI_FAILURE; 9971 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag"); 9972 goto out; 9973 } 9974 post_flags |= MPTSAS_REQUEST_POOL_CMD; 9975 9976 bzero((caddr_t)cmd, sizeof (*cmd)); 9977 bzero((caddr_t)pkt, scsi_pkt_size()); 9978 9979 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 9980 9981 diag.pBuffer = pBuffer; 9982 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST; 9983 9984 /* 9985 * Form a blank cmd/pkt to store the acknowledgement message 9986 */ 9987 pkt->pkt_ha_private = (opaque_t)&diag; 9988 pkt->pkt_flags = FLAG_HEAD; 9989 pkt->pkt_time = 60; 9990 cmd->cmd_pkt = pkt; 9991 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 9992 9993 /* 9994 * Save the command in a slot 9995 */ 9996 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 9997 /* 9998 * Once passthru command get slot, set cmd_flags 9999 * CFLAG_PREPARED. 10000 */ 10001 cmd->cmd_flags |= CFLAG_PREPARED; 10002 mptsas_start_diag(mpt, cmd); 10003 } else { 10004 mptsas_waitq_add(mpt, cmd); 10005 } 10006 10007 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 10008 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 10009 } 10010 10011 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 10012 status = DDI_FAILURE; 10013 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout"); 10014 goto out; 10015 } 10016 10017 /* 10018 * cmd_rfm points to the reply message if a reply was given. Check the 10019 * IOCStatus to make sure everything went OK with the FW diag request 10020 * and set buffer flags. 10021 */ 10022 if (cmd->cmd_rfm) { 10023 post_flags |= MPTSAS_ADDRESS_REPLY; 10024 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 10025 DDI_DMA_SYNC_FORCPU); 10026 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame + 10027 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr)); 10028 10029 /* 10030 * Get the reply message data 10031 */ 10032 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 10033 &reply->IOCStatus); 10034 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 10035 &reply->IOCLogInfo); 10036 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl, 10037 &reply->TransferLength); 10038 10039 /* 10040 * If post failed quit. 10041 */ 10042 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) { 10043 status = DDI_FAILURE; 10044 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, " 10045 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus, 10046 iocloginfo, transfer_length)); 10047 goto out; 10048 } 10049 10050 /* 10051 * Post was successful. 10052 */ 10053 pBuffer->valid_data = TRUE; 10054 pBuffer->owned_by_firmware = TRUE; 10055 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 10056 status = DDI_SUCCESS; 10057 } 10058 10059 out: 10060 /* 10061 * Put the reply frame back on the free queue, increment the free 10062 * index, and write the new index to the free index register. But only 10063 * if this reply is an ADDRESS reply. 10064 */ 10065 if (post_flags & MPTSAS_ADDRESS_REPLY) { 10066 ddi_put32(mpt->m_acc_free_queue_hdl, 10067 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 10068 cmd->cmd_rfm); 10069 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 10070 DDI_DMA_SYNC_FORDEV); 10071 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 10072 mpt->m_free_index = 0; 10073 } 10074 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 10075 mpt->m_free_index); 10076 } 10077 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 10078 mptsas_remove_cmd(mpt, cmd); 10079 post_flags &= (~MPTSAS_REQUEST_POOL_CMD); 10080 } 10081 if (post_flags & MPTSAS_REQUEST_POOL_CMD) { 10082 mptsas_return_to_pool(mpt, cmd); 10083 } 10084 10085 return (status); 10086 } 10087 10088 static int 10089 mptsas_release_fw_diag_buffer(mptsas_t *mpt, 10090 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 10091 uint32_t diag_type) 10092 { 10093 mptsas_diag_request_t diag; 10094 int status, slot_num, rel_flags = 0; 10095 mptsas_cmd_t *cmd = NULL; 10096 struct scsi_pkt *pkt; 10097 pMpi2DiagReleaseReply_t reply; 10098 uint16_t iocstatus; 10099 uint32_t iocloginfo; 10100 10101 /* 10102 * If buffer is not enabled, just leave. 10103 */ 10104 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED; 10105 if (!pBuffer->enabled) { 10106 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported " 10107 "by the IOC"); 10108 status = DDI_FAILURE; 10109 goto out; 10110 } 10111 10112 /* 10113 * Clear some flags initially. 10114 */ 10115 pBuffer->force_release = FALSE; 10116 pBuffer->valid_data = FALSE; 10117 pBuffer->owned_by_firmware = FALSE; 10118 10119 /* 10120 * Get a cmd buffer from the cmd buffer pool 10121 */ 10122 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 10123 status = DDI_FAILURE; 10124 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW " 10125 "Diag"); 10126 goto out; 10127 } 10128 rel_flags |= MPTSAS_REQUEST_POOL_CMD; 10129 10130 bzero((caddr_t)cmd, sizeof (*cmd)); 10131 bzero((caddr_t)pkt, scsi_pkt_size()); 10132 10133 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 10134 10135 diag.pBuffer = pBuffer; 10136 diag.function = MPI2_FUNCTION_DIAG_RELEASE; 10137 10138 /* 10139 * Form a blank cmd/pkt to store the acknowledgement message 10140 */ 10141 pkt->pkt_ha_private = (opaque_t)&diag; 10142 pkt->pkt_flags = FLAG_HEAD; 10143 pkt->pkt_time = 60; 10144 cmd->cmd_pkt = pkt; 10145 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 10146 10147 /* 10148 * Save the command in a slot 10149 */ 10150 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 10151 /* 10152 * Once passthru command get slot, set cmd_flags 10153 * CFLAG_PREPARED. 10154 */ 10155 cmd->cmd_flags |= CFLAG_PREPARED; 10156 mptsas_start_diag(mpt, cmd); 10157 } else { 10158 mptsas_waitq_add(mpt, cmd); 10159 } 10160 10161 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 10162 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 10163 } 10164 10165 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 10166 status = DDI_FAILURE; 10167 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout"); 10168 goto out; 10169 } 10170 10171 /* 10172 * cmd_rfm points to the reply message if a reply was given. Check the 10173 * IOCStatus to make sure everything went OK with the FW diag request 10174 * and set buffer flags. 10175 */ 10176 if (cmd->cmd_rfm) { 10177 rel_flags |= MPTSAS_ADDRESS_REPLY; 10178 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 10179 DDI_DMA_SYNC_FORCPU); 10180 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame + 10181 (cmd->cmd_rfm - mpt->m_reply_frame_dma_addr)); 10182 10183 /* 10184 * Get the reply message data 10185 */ 10186 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 10187 &reply->IOCStatus); 10188 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 10189 &reply->IOCLogInfo); 10190 10191 /* 10192 * If release failed quit. 10193 */ 10194 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) || 10195 pBuffer->owned_by_firmware) { 10196 status = DDI_FAILURE; 10197 NDBG13(("release FW Diag Buffer failed: " 10198 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, 10199 iocloginfo)); 10200 goto out; 10201 } 10202 10203 /* 10204 * Release was successful. 10205 */ 10206 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 10207 status = DDI_SUCCESS; 10208 10209 /* 10210 * If this was for an UNREGISTER diag type command, clear the 10211 * unique ID. 10212 */ 10213 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) { 10214 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 10215 } 10216 } 10217 10218 out: 10219 /* 10220 * Put the reply frame back on the free queue, increment the free 10221 * index, and write the new index to the free index register. But only 10222 * if this reply is an ADDRESS reply. 10223 */ 10224 if (rel_flags & MPTSAS_ADDRESS_REPLY) { 10225 ddi_put32(mpt->m_acc_free_queue_hdl, 10226 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 10227 cmd->cmd_rfm); 10228 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 10229 DDI_DMA_SYNC_FORDEV); 10230 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 10231 mpt->m_free_index = 0; 10232 } 10233 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 10234 mpt->m_free_index); 10235 } 10236 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 10237 mptsas_remove_cmd(mpt, cmd); 10238 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD); 10239 } 10240 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) { 10241 mptsas_return_to_pool(mpt, cmd); 10242 } 10243 10244 return (status); 10245 } 10246 10247 static int 10248 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register, 10249 uint32_t *return_code) 10250 { 10251 mptsas_fw_diagnostic_buffer_t *pBuffer; 10252 uint8_t extended_type, buffer_type, i; 10253 uint32_t buffer_size; 10254 uint32_t unique_id; 10255 int status; 10256 10257 ASSERT(mutex_owned(&mpt->m_mutex)); 10258 10259 extended_type = diag_register->ExtendedType; 10260 buffer_type = diag_register->BufferType; 10261 buffer_size = diag_register->RequestedBufferSize; 10262 unique_id = diag_register->UniqueId; 10263 10264 /* 10265 * Check for valid buffer type 10266 */ 10267 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) { 10268 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10269 return (DDI_FAILURE); 10270 } 10271 10272 /* 10273 * Get the current buffer and look up the unique ID. The unique ID 10274 * should not be found. If it is, the ID is already in use. 10275 */ 10276 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10277 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type]; 10278 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10279 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10280 return (DDI_FAILURE); 10281 } 10282 10283 /* 10284 * The buffer's unique ID should not be registered yet, and the given 10285 * unique ID cannot be 0. 10286 */ 10287 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) || 10288 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 10289 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10290 return (DDI_FAILURE); 10291 } 10292 10293 /* 10294 * If this buffer is already posted as immediate, just change owner. 10295 */ 10296 if (pBuffer->immediate && pBuffer->owned_by_firmware && 10297 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 10298 pBuffer->immediate = FALSE; 10299 pBuffer->unique_id = unique_id; 10300 return (DDI_SUCCESS); 10301 } 10302 10303 /* 10304 * Post a new buffer after checking if it's enabled. The DMA buffer 10305 * that is allocated will be contiguous (sgl_len = 1). 10306 */ 10307 if (!pBuffer->enabled) { 10308 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 10309 return (DDI_FAILURE); 10310 } 10311 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t)); 10312 pBuffer->buffer_data.size = buffer_size; 10313 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) { 10314 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for " 10315 "diag buffer: size = %d bytes", buffer_size); 10316 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 10317 return (DDI_FAILURE); 10318 } 10319 10320 /* 10321 * Copy the given info to the diag buffer and post the buffer. 10322 */ 10323 pBuffer->buffer_type = buffer_type; 10324 pBuffer->immediate = FALSE; 10325 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) { 10326 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4); 10327 i++) { 10328 pBuffer->product_specific[i] = 10329 diag_register->ProductSpecific[i]; 10330 } 10331 } 10332 pBuffer->extended_type = extended_type; 10333 pBuffer->unique_id = unique_id; 10334 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code); 10335 10336 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 10337 DDI_SUCCESS) { 10338 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in " 10339 "mptsas_diag_register."); 10340 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 10341 status = DDI_FAILURE; 10342 } 10343 10344 /* 10345 * In case there was a failure, free the DMA buffer. 10346 */ 10347 if (status == DDI_FAILURE) { 10348 mptsas_dma_free(&pBuffer->buffer_data); 10349 } 10350 10351 return (status); 10352 } 10353 10354 static int 10355 mptsas_diag_unregister(mptsas_t *mpt, 10356 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code) 10357 { 10358 mptsas_fw_diagnostic_buffer_t *pBuffer; 10359 uint8_t i; 10360 uint32_t unique_id; 10361 int status; 10362 10363 ASSERT(mutex_owned(&mpt->m_mutex)); 10364 10365 unique_id = diag_unregister->UniqueId; 10366 10367 /* 10368 * Get the current buffer and look up the unique ID. The unique ID 10369 * should be there. 10370 */ 10371 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10372 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10373 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10374 return (DDI_FAILURE); 10375 } 10376 10377 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 10378 10379 /* 10380 * Try to release the buffer from FW before freeing it. If release 10381 * fails, don't free the DMA buffer in case FW tries to access it 10382 * later. If buffer is not owned by firmware, can't release it. 10383 */ 10384 if (!pBuffer->owned_by_firmware) { 10385 status = DDI_SUCCESS; 10386 } else { 10387 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, 10388 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER); 10389 } 10390 10391 /* 10392 * At this point, return the current status no matter what happens with 10393 * the DMA buffer. 10394 */ 10395 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 10396 if (status == DDI_SUCCESS) { 10397 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 10398 DDI_SUCCESS) { 10399 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed " 10400 "in mptsas_diag_unregister."); 10401 ddi_fm_service_impact(mpt->m_dip, 10402 DDI_SERVICE_UNAFFECTED); 10403 } 10404 mptsas_dma_free(&pBuffer->buffer_data); 10405 } 10406 10407 return (status); 10408 } 10409 10410 static int 10411 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 10412 uint32_t *return_code) 10413 { 10414 mptsas_fw_diagnostic_buffer_t *pBuffer; 10415 uint8_t i; 10416 uint32_t unique_id; 10417 10418 ASSERT(mutex_owned(&mpt->m_mutex)); 10419 10420 unique_id = diag_query->UniqueId; 10421 10422 /* 10423 * If ID is valid, query on ID. 10424 * If ID is invalid, query on buffer type. 10425 */ 10426 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) { 10427 i = diag_query->BufferType; 10428 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) { 10429 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10430 return (DDI_FAILURE); 10431 } 10432 } else { 10433 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10434 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10435 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10436 return (DDI_FAILURE); 10437 } 10438 } 10439 10440 /* 10441 * Fill query structure with the diag buffer info. 10442 */ 10443 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 10444 diag_query->BufferType = pBuffer->buffer_type; 10445 diag_query->ExtendedType = pBuffer->extended_type; 10446 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) { 10447 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4); 10448 i++) { 10449 diag_query->ProductSpecific[i] = 10450 pBuffer->product_specific[i]; 10451 } 10452 } 10453 diag_query->TotalBufferSize = pBuffer->buffer_data.size; 10454 diag_query->DriverAddedBufferSize = 0; 10455 diag_query->UniqueId = pBuffer->unique_id; 10456 diag_query->ApplicationFlags = 0; 10457 diag_query->DiagnosticFlags = 0; 10458 10459 /* 10460 * Set/Clear application flags 10461 */ 10462 if (pBuffer->immediate) { 10463 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED; 10464 } else { 10465 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED; 10466 } 10467 if (pBuffer->valid_data || pBuffer->owned_by_firmware) { 10468 diag_query->ApplicationFlags |= 10469 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 10470 } else { 10471 diag_query->ApplicationFlags &= 10472 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 10473 } 10474 if (pBuffer->owned_by_firmware) { 10475 diag_query->ApplicationFlags |= 10476 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 10477 } else { 10478 diag_query->ApplicationFlags &= 10479 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 10480 } 10481 10482 return (DDI_SUCCESS); 10483 } 10484 10485 static int 10486 mptsas_diag_read_buffer(mptsas_t *mpt, 10487 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 10488 uint32_t *return_code, int ioctl_mode) 10489 { 10490 mptsas_fw_diagnostic_buffer_t *pBuffer; 10491 uint8_t i, *pData; 10492 uint32_t unique_id, byte; 10493 int status; 10494 10495 ASSERT(mutex_owned(&mpt->m_mutex)); 10496 10497 unique_id = diag_read_buffer->UniqueId; 10498 10499 /* 10500 * Get the current buffer and look up the unique ID. The unique ID 10501 * should be there. 10502 */ 10503 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10504 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10505 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10506 return (DDI_FAILURE); 10507 } 10508 10509 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 10510 10511 /* 10512 * Make sure requested read is within limits 10513 */ 10514 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead > 10515 pBuffer->buffer_data.size) { 10516 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10517 return (DDI_FAILURE); 10518 } 10519 10520 /* 10521 * Copy the requested data from DMA to the diag_read_buffer. The DMA 10522 * buffer that was allocated is one contiguous buffer. 10523 */ 10524 pData = (uint8_t *)(pBuffer->buffer_data.memp + 10525 diag_read_buffer->StartingOffset); 10526 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0, 10527 DDI_DMA_SYNC_FORCPU); 10528 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) { 10529 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode) 10530 != 0) { 10531 return (DDI_FAILURE); 10532 } 10533 } 10534 diag_read_buffer->Status = 0; 10535 10536 /* 10537 * Set or clear the Force Release flag. 10538 */ 10539 if (pBuffer->force_release) { 10540 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 10541 } else { 10542 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 10543 } 10544 10545 /* 10546 * If buffer is to be reregistered, make sure it's not already owned by 10547 * firmware first. 10548 */ 10549 status = DDI_SUCCESS; 10550 if (!pBuffer->owned_by_firmware) { 10551 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) { 10552 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, 10553 return_code); 10554 } 10555 } 10556 10557 return (status); 10558 } 10559 10560 static int 10561 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release, 10562 uint32_t *return_code) 10563 { 10564 mptsas_fw_diagnostic_buffer_t *pBuffer; 10565 uint8_t i; 10566 uint32_t unique_id; 10567 int status; 10568 10569 ASSERT(mutex_owned(&mpt->m_mutex)); 10570 10571 unique_id = diag_release->UniqueId; 10572 10573 /* 10574 * Get the current buffer and look up the unique ID. The unique ID 10575 * should be there. 10576 */ 10577 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 10578 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 10579 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 10580 return (DDI_FAILURE); 10581 } 10582 10583 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 10584 10585 /* 10586 * If buffer is not owned by firmware, it's already been released. 10587 */ 10588 if (!pBuffer->owned_by_firmware) { 10589 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED; 10590 return (DDI_FAILURE); 10591 } 10592 10593 /* 10594 * Release the buffer. 10595 */ 10596 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code, 10597 MPTSAS_FW_DIAG_TYPE_RELEASE); 10598 return (status); 10599 } 10600 10601 static int 10602 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action, 10603 uint32_t length, uint32_t *return_code, int ioctl_mode) 10604 { 10605 mptsas_fw_diag_register_t diag_register; 10606 mptsas_fw_diag_unregister_t diag_unregister; 10607 mptsas_fw_diag_query_t diag_query; 10608 mptsas_diag_read_buffer_t diag_read_buffer; 10609 mptsas_fw_diag_release_t diag_release; 10610 int status = DDI_SUCCESS; 10611 uint32_t original_return_code, read_buf_len; 10612 10613 ASSERT(mutex_owned(&mpt->m_mutex)); 10614 10615 original_return_code = *return_code; 10616 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 10617 10618 switch (action) { 10619 case MPTSAS_FW_DIAG_TYPE_REGISTER: 10620 if (!length) { 10621 *return_code = 10622 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10623 status = DDI_FAILURE; 10624 break; 10625 } 10626 if (ddi_copyin(diag_action, &diag_register, 10627 sizeof (diag_register), ioctl_mode) != 0) { 10628 return (DDI_FAILURE); 10629 } 10630 status = mptsas_diag_register(mpt, &diag_register, 10631 return_code); 10632 break; 10633 10634 case MPTSAS_FW_DIAG_TYPE_UNREGISTER: 10635 if (length < sizeof (diag_unregister)) { 10636 *return_code = 10637 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10638 status = DDI_FAILURE; 10639 break; 10640 } 10641 if (ddi_copyin(diag_action, &diag_unregister, 10642 sizeof (diag_unregister), ioctl_mode) != 0) { 10643 return (DDI_FAILURE); 10644 } 10645 status = mptsas_diag_unregister(mpt, &diag_unregister, 10646 return_code); 10647 break; 10648 10649 case MPTSAS_FW_DIAG_TYPE_QUERY: 10650 if (length < sizeof (diag_query)) { 10651 *return_code = 10652 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10653 status = DDI_FAILURE; 10654 break; 10655 } 10656 if (ddi_copyin(diag_action, &diag_query, 10657 sizeof (diag_query), ioctl_mode) != 0) { 10658 return (DDI_FAILURE); 10659 } 10660 status = mptsas_diag_query(mpt, &diag_query, 10661 return_code); 10662 if (status == DDI_SUCCESS) { 10663 if (ddi_copyout(&diag_query, diag_action, 10664 sizeof (diag_query), ioctl_mode) != 0) { 10665 return (DDI_FAILURE); 10666 } 10667 } 10668 break; 10669 10670 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER: 10671 if (ddi_copyin(diag_action, &diag_read_buffer, 10672 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) { 10673 return (DDI_FAILURE); 10674 } 10675 read_buf_len = sizeof (diag_read_buffer) - 10676 sizeof (diag_read_buffer.DataBuffer) + 10677 diag_read_buffer.BytesToRead; 10678 if (length < read_buf_len) { 10679 *return_code = 10680 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10681 status = DDI_FAILURE; 10682 break; 10683 } 10684 status = mptsas_diag_read_buffer(mpt, 10685 &diag_read_buffer, diag_action + 10686 sizeof (diag_read_buffer) - 4, return_code, 10687 ioctl_mode); 10688 if (status == DDI_SUCCESS) { 10689 if (ddi_copyout(&diag_read_buffer, diag_action, 10690 sizeof (diag_read_buffer) - 4, ioctl_mode) 10691 != 0) { 10692 return (DDI_FAILURE); 10693 } 10694 } 10695 break; 10696 10697 case MPTSAS_FW_DIAG_TYPE_RELEASE: 10698 if (length < sizeof (diag_release)) { 10699 *return_code = 10700 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10701 status = DDI_FAILURE; 10702 break; 10703 } 10704 if (ddi_copyin(diag_action, &diag_release, 10705 sizeof (diag_release), ioctl_mode) != 0) { 10706 return (DDI_FAILURE); 10707 } 10708 status = mptsas_diag_release(mpt, &diag_release, 10709 return_code); 10710 break; 10711 10712 default: 10713 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 10714 status = DDI_FAILURE; 10715 break; 10716 } 10717 10718 if ((status == DDI_FAILURE) && 10719 (original_return_code == MPTSAS_FW_DIAG_NEW) && 10720 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) { 10721 status = DDI_SUCCESS; 10722 } 10723 10724 return (status); 10725 } 10726 10727 static int 10728 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode) 10729 { 10730 int status; 10731 mptsas_diag_action_t driver_data; 10732 10733 ASSERT(mutex_owned(&mpt->m_mutex)); 10734 10735 /* 10736 * Copy the user data to a driver data buffer. 10737 */ 10738 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t), 10739 mode) == 0) { 10740 /* 10741 * Send diag action request if Action is valid 10742 */ 10743 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER || 10744 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER || 10745 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY || 10746 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER || 10747 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) { 10748 status = mptsas_do_diag_action(mpt, driver_data.Action, 10749 (void *)(uintptr_t)driver_data.PtrDiagAction, 10750 driver_data.Length, &driver_data.ReturnCode, 10751 mode); 10752 if (status == DDI_SUCCESS) { 10753 if (ddi_copyout(&driver_data.ReturnCode, 10754 &user_data->ReturnCode, 10755 sizeof (user_data->ReturnCode), mode) 10756 != 0) { 10757 status = EFAULT; 10758 } else { 10759 status = 0; 10760 } 10761 } else { 10762 status = EIO; 10763 } 10764 } else { 10765 status = EINVAL; 10766 } 10767 } else { 10768 status = EFAULT; 10769 } 10770 10771 return (status); 10772 } 10773 10774 /* 10775 * This routine handles the "event query" ioctl. 10776 */ 10777 static int 10778 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode, 10779 int *rval) 10780 { 10781 int status; 10782 mptsas_event_query_t driverdata; 10783 uint8_t i; 10784 10785 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE; 10786 10787 mutex_enter(&mpt->m_mutex); 10788 for (i = 0; i < 4; i++) { 10789 driverdata.Types[i] = mpt->m_event_mask[i]; 10790 } 10791 mutex_exit(&mpt->m_mutex); 10792 10793 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) { 10794 status = EFAULT; 10795 } else { 10796 *rval = MPTIOCTL_STATUS_GOOD; 10797 status = 0; 10798 } 10799 10800 return (status); 10801 } 10802 10803 /* 10804 * This routine handles the "event enable" ioctl. 10805 */ 10806 static int 10807 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode, 10808 int *rval) 10809 { 10810 int status; 10811 mptsas_event_enable_t driverdata; 10812 uint8_t i; 10813 10814 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 10815 mutex_enter(&mpt->m_mutex); 10816 for (i = 0; i < 4; i++) { 10817 mpt->m_event_mask[i] = driverdata.Types[i]; 10818 } 10819 mutex_exit(&mpt->m_mutex); 10820 10821 *rval = MPTIOCTL_STATUS_GOOD; 10822 status = 0; 10823 } else { 10824 status = EFAULT; 10825 } 10826 return (status); 10827 } 10828 10829 /* 10830 * This routine handles the "event report" ioctl. 10831 */ 10832 static int 10833 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode, 10834 int *rval) 10835 { 10836 int status; 10837 mptsas_event_report_t driverdata; 10838 10839 mutex_enter(&mpt->m_mutex); 10840 10841 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size), 10842 mode) == 0) { 10843 if (driverdata.Size >= sizeof (mpt->m_events)) { 10844 if (ddi_copyout(mpt->m_events, data->Events, 10845 sizeof (mpt->m_events), mode) != 0) { 10846 status = EFAULT; 10847 } else { 10848 if (driverdata.Size > sizeof (mpt->m_events)) { 10849 driverdata.Size = 10850 sizeof (mpt->m_events); 10851 if (ddi_copyout(&driverdata.Size, 10852 &data->Size, 10853 sizeof (driverdata.Size), 10854 mode) != 0) { 10855 status = EFAULT; 10856 } else { 10857 *rval = MPTIOCTL_STATUS_GOOD; 10858 status = 0; 10859 } 10860 } else { 10861 *rval = MPTIOCTL_STATUS_GOOD; 10862 status = 0; 10863 } 10864 } 10865 } else { 10866 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 10867 status = 0; 10868 } 10869 } else { 10870 status = EFAULT; 10871 } 10872 10873 mutex_exit(&mpt->m_mutex); 10874 return (status); 10875 } 10876 10877 static void 10878 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 10879 { 10880 int *reg_data; 10881 uint_t reglen; 10882 10883 /* 10884 * Lookup the 'reg' property and extract the other data 10885 */ 10886 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 10887 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 10888 DDI_PROP_SUCCESS) { 10889 /* 10890 * Extract the PCI data from the 'reg' property first DWORD. 10891 * The entry looks like the following: 10892 * First DWORD: 10893 * Bits 0 - 7 8-bit Register number 10894 * Bits 8 - 10 3-bit Function number 10895 * Bits 11 - 15 5-bit Device number 10896 * Bits 16 - 23 8-bit Bus number 10897 * Bits 24 - 25 2-bit Address Space type identifier 10898 * 10899 */ 10900 adapter_data->PciInformation.u.bits.BusNumber = 10901 (reg_data[0] & 0x00FF0000) >> 16; 10902 adapter_data->PciInformation.u.bits.DeviceNumber = 10903 (reg_data[0] & 0x0000F800) >> 11; 10904 adapter_data->PciInformation.u.bits.FunctionNumber = 10905 (reg_data[0] & 0x00000700) >> 8; 10906 ddi_prop_free((void *)reg_data); 10907 } else { 10908 /* 10909 * If we can't determine the PCI data then we fill in FF's for 10910 * the data to indicate this. 10911 */ 10912 adapter_data->PCIDeviceHwId = 0xFFFFFFFF; 10913 adapter_data->MpiPortNumber = 0xFFFFFFFF; 10914 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF; 10915 } 10916 10917 /* 10918 * Saved in the mpt->m_fwversion 10919 */ 10920 adapter_data->MpiFirmwareVersion = mpt->m_fwversion; 10921 } 10922 10923 static void 10924 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 10925 { 10926 char *driver_verstr = MPTSAS_MOD_STRING; 10927 10928 mptsas_lookup_pci_data(mpt, adapter_data); 10929 adapter_data->AdapterType = MPTIOCTL_ADAPTER_TYPE_SAS2; 10930 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid; 10931 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid; 10932 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid; 10933 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid; 10934 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr); 10935 adapter_data->BiosVersion = 0; 10936 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion); 10937 } 10938 10939 static void 10940 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info) 10941 { 10942 int *reg_data, i; 10943 uint_t reglen; 10944 10945 /* 10946 * Lookup the 'reg' property and extract the other data 10947 */ 10948 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 10949 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 10950 DDI_PROP_SUCCESS) { 10951 /* 10952 * Extract the PCI data from the 'reg' property first DWORD. 10953 * The entry looks like the following: 10954 * First DWORD: 10955 * Bits 8 - 10 3-bit Function number 10956 * Bits 11 - 15 5-bit Device number 10957 * Bits 16 - 23 8-bit Bus number 10958 */ 10959 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16; 10960 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11; 10961 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8; 10962 ddi_prop_free((void *)reg_data); 10963 } else { 10964 /* 10965 * If we can't determine the PCI info then we fill in FF's for 10966 * the data to indicate this. 10967 */ 10968 pci_info->BusNumber = 0xFFFFFFFF; 10969 pci_info->DeviceNumber = 0xFF; 10970 pci_info->FunctionNumber = 0xFF; 10971 } 10972 10973 /* 10974 * Now get the interrupt vector and the pci header. The vector can 10975 * only be 0 right now. The header is the first 256 bytes of config 10976 * space. 10977 */ 10978 pci_info->InterruptVector = 0; 10979 for (i = 0; i < sizeof (pci_info->PciHeader); i++) { 10980 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle, 10981 i); 10982 } 10983 } 10984 10985 static int 10986 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode) 10987 { 10988 int status = 0; 10989 mptsas_reg_access_t driverdata; 10990 10991 mutex_enter(&mpt->m_mutex); 10992 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 10993 switch (driverdata.Command) { 10994 /* 10995 * IO access is not supported. 10996 */ 10997 case REG_IO_READ: 10998 case REG_IO_WRITE: 10999 mptsas_log(mpt, CE_WARN, "IO access is not " 11000 "supported. Use memory access."); 11001 status = EINVAL; 11002 break; 11003 11004 case REG_MEM_READ: 11005 driverdata.RegData = ddi_get32(mpt->m_datap, 11006 (uint32_t *)(void *)mpt->m_reg + 11007 driverdata.RegOffset); 11008 if (ddi_copyout(&driverdata.RegData, 11009 &data->RegData, 11010 sizeof (driverdata.RegData), mode) != 0) { 11011 mptsas_log(mpt, CE_WARN, "Register " 11012 "Read Failed"); 11013 status = EFAULT; 11014 } 11015 break; 11016 11017 case REG_MEM_WRITE: 11018 ddi_put32(mpt->m_datap, 11019 (uint32_t *)(void *)mpt->m_reg + 11020 driverdata.RegOffset, 11021 driverdata.RegData); 11022 break; 11023 11024 default: 11025 status = EINVAL; 11026 break; 11027 } 11028 } else { 11029 status = EFAULT; 11030 } 11031 11032 mutex_exit(&mpt->m_mutex); 11033 return (status); 11034 } 11035 11036 static int 11037 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp, 11038 int *rval) 11039 { 11040 int status = 0; 11041 mptsas_t *mpt; 11042 mptsas_update_flash_t flashdata; 11043 mptsas_pass_thru_t passthru_data; 11044 mptsas_adapter_data_t adapter_data; 11045 mptsas_pci_info_t pci_info; 11046 int copylen; 11047 11048 *rval = MPTIOCTL_STATUS_GOOD; 11049 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev))); 11050 if (mpt == NULL) { 11051 return (scsi_hba_ioctl(dev, cmd, data, mode, credp, rval)); 11052 } 11053 if (secpolicy_sys_config(credp, B_FALSE) != 0) { 11054 return (EPERM); 11055 } 11056 11057 /* Make sure power level is D0 before accessing registers */ 11058 mutex_enter(&mpt->m_mutex); 11059 if (mpt->m_options & MPTSAS_OPT_PM) { 11060 (void) pm_busy_component(mpt->m_dip, 0); 11061 if (mpt->m_power_level != PM_LEVEL_D0) { 11062 mutex_exit(&mpt->m_mutex); 11063 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) != 11064 DDI_SUCCESS) { 11065 mptsas_log(mpt, CE_WARN, 11066 "mptsas%d: mptsas_ioctl: Raise power " 11067 "request failed.", mpt->m_instance); 11068 (void) pm_idle_component(mpt->m_dip, 0); 11069 return (ENXIO); 11070 } 11071 } else { 11072 mutex_exit(&mpt->m_mutex); 11073 } 11074 } else { 11075 mutex_exit(&mpt->m_mutex); 11076 } 11077 11078 switch (cmd) { 11079 case MPTIOCTL_UPDATE_FLASH: 11080 if (ddi_copyin((void *)data, &flashdata, 11081 sizeof (struct mptsas_update_flash), mode)) { 11082 status = EFAULT; 11083 break; 11084 } 11085 11086 mutex_enter(&mpt->m_mutex); 11087 if (mptsas_update_flash(mpt, 11088 (caddr_t)(long)flashdata.PtrBuffer, 11089 flashdata.ImageSize, flashdata.ImageType, mode)) { 11090 status = EFAULT; 11091 } 11092 11093 /* 11094 * Reset the chip to start using the new 11095 * firmware. Reset if failed also. 11096 */ 11097 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 11098 status = EFAULT; 11099 } 11100 mutex_exit(&mpt->m_mutex); 11101 break; 11102 case MPTIOCTL_PASS_THRU: 11103 /* 11104 * The user has requested to pass through a command to 11105 * be executed by the MPT firmware. Call our routine 11106 * which does this. Only allow one passthru IOCTL at 11107 * one time. 11108 */ 11109 if (ddi_copyin((void *)data, &passthru_data, 11110 sizeof (mptsas_pass_thru_t), mode)) { 11111 status = EFAULT; 11112 break; 11113 } 11114 mutex_enter(&mpt->m_mutex); 11115 if (mpt->m_passthru_in_progress) { 11116 mutex_exit(&mpt->m_mutex); 11117 return (EBUSY); 11118 } 11119 mpt->m_passthru_in_progress = 1; 11120 status = mptsas_pass_thru(mpt, &passthru_data, mode); 11121 mpt->m_passthru_in_progress = 0; 11122 mutex_exit(&mpt->m_mutex); 11123 11124 break; 11125 case MPTIOCTL_GET_ADAPTER_DATA: 11126 /* 11127 * The user has requested to read adapter data. Call 11128 * our routine which does this. 11129 */ 11130 bzero(&adapter_data, sizeof (mptsas_adapter_data_t)); 11131 if (ddi_copyin((void *)data, (void *)&adapter_data, 11132 sizeof (mptsas_adapter_data_t), mode)) { 11133 status = EFAULT; 11134 break; 11135 } 11136 if (adapter_data.StructureLength >= 11137 sizeof (mptsas_adapter_data_t)) { 11138 adapter_data.StructureLength = (uint32_t) 11139 sizeof (mptsas_adapter_data_t); 11140 copylen = sizeof (mptsas_adapter_data_t); 11141 mutex_enter(&mpt->m_mutex); 11142 mptsas_read_adapter_data(mpt, &adapter_data); 11143 mutex_exit(&mpt->m_mutex); 11144 } else { 11145 adapter_data.StructureLength = (uint32_t) 11146 sizeof (mptsas_adapter_data_t); 11147 copylen = sizeof (adapter_data.StructureLength); 11148 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 11149 } 11150 if (ddi_copyout((void *)(&adapter_data), (void *)data, 11151 copylen, mode) != 0) { 11152 status = EFAULT; 11153 } 11154 break; 11155 case MPTIOCTL_GET_PCI_INFO: 11156 /* 11157 * The user has requested to read pci info. Call 11158 * our routine which does this. 11159 */ 11160 bzero(&pci_info, sizeof (mptsas_pci_info_t)); 11161 mutex_enter(&mpt->m_mutex); 11162 mptsas_read_pci_info(mpt, &pci_info); 11163 mutex_exit(&mpt->m_mutex); 11164 if (ddi_copyout((void *)(&pci_info), (void *)data, 11165 sizeof (mptsas_pci_info_t), mode) != 0) { 11166 status = EFAULT; 11167 } 11168 break; 11169 case MPTIOCTL_RESET_ADAPTER: 11170 mutex_enter(&mpt->m_mutex); 11171 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 11172 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL " 11173 "failed"); 11174 status = EFAULT; 11175 } 11176 mutex_exit(&mpt->m_mutex); 11177 break; 11178 case MPTIOCTL_DIAG_ACTION: 11179 /* 11180 * The user has done a diag buffer action. Call our 11181 * routine which does this. Only allow one diag action 11182 * at one time. 11183 */ 11184 mutex_enter(&mpt->m_mutex); 11185 if (mpt->m_diag_action_in_progress) { 11186 mutex_exit(&mpt->m_mutex); 11187 return (EBUSY); 11188 } 11189 mpt->m_diag_action_in_progress = 1; 11190 status = mptsas_diag_action(mpt, 11191 (mptsas_diag_action_t *)data, mode); 11192 mpt->m_diag_action_in_progress = 0; 11193 mutex_exit(&mpt->m_mutex); 11194 break; 11195 case MPTIOCTL_EVENT_QUERY: 11196 /* 11197 * The user has done an event query. Call our routine 11198 * which does this. 11199 */ 11200 status = mptsas_event_query(mpt, 11201 (mptsas_event_query_t *)data, mode, rval); 11202 break; 11203 case MPTIOCTL_EVENT_ENABLE: 11204 /* 11205 * The user has done an event enable. Call our routine 11206 * which does this. 11207 */ 11208 status = mptsas_event_enable(mpt, 11209 (mptsas_event_enable_t *)data, mode, rval); 11210 break; 11211 case MPTIOCTL_EVENT_REPORT: 11212 /* 11213 * The user has done an event report. Call our routine 11214 * which does this. 11215 */ 11216 status = mptsas_event_report(mpt, 11217 (mptsas_event_report_t *)data, mode, rval); 11218 break; 11219 case MPTIOCTL_REG_ACCESS: 11220 /* 11221 * The user has requested register access. Call our 11222 * routine which does this. 11223 */ 11224 status = mptsas_reg_access(mpt, 11225 (mptsas_reg_access_t *)data, mode); 11226 break; 11227 default: 11228 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, 11229 rval); 11230 break; 11231 } 11232 11233 /* 11234 * Report idle status to pm after grace period because 11235 * multiple ioctls may be queued and raising power 11236 * for every ioctl is time consuming. If a timeout is 11237 * pending for the previous ioctl, cancel the timeout and 11238 * report idle status to pm because calls to pm_busy_component(9F) 11239 * are stacked. 11240 */ 11241 mutex_enter(&mpt->m_mutex); 11242 if (mpt->m_options & MPTSAS_OPT_PM) { 11243 if (mpt->m_pm_timeid != 0) { 11244 timeout_id_t tid = mpt->m_pm_timeid; 11245 mpt->m_pm_timeid = 0; 11246 mutex_exit(&mpt->m_mutex); 11247 (void) untimeout(tid); 11248 /* 11249 * Report idle status for previous ioctl since 11250 * calls to pm_busy_component(9F) are stacked. 11251 */ 11252 (void) pm_idle_component(mpt->m_dip, 0); 11253 mutex_enter(&mpt->m_mutex); 11254 } 11255 mpt->m_pm_timeid = timeout(mptsas_idle_pm, mpt, 11256 drv_usectohz((clock_t)mpt->m_pm_idle_delay * 1000000)); 11257 } 11258 mutex_exit(&mpt->m_mutex); 11259 11260 return (status); 11261 } 11262 11263 int 11264 mptsas_restart_ioc(mptsas_t *mpt) 11265 { 11266 int rval = DDI_SUCCESS; 11267 mptsas_target_t *ptgt = NULL; 11268 11269 ASSERT(mutex_owned(&mpt->m_mutex)); 11270 11271 /* 11272 * Set a flag telling I/O path that we're processing a reset. This is 11273 * needed because after the reset is complete, the hash table still 11274 * needs to be rebuilt. If I/Os are started before the hash table is 11275 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked 11276 * so that they can be retried. 11277 */ 11278 mpt->m_in_reset = TRUE; 11279 11280 /* 11281 * Set all throttles to HOLD 11282 */ 11283 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 11284 MPTSAS_HASH_FIRST); 11285 while (ptgt != NULL) { 11286 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 11287 11288 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 11289 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 11290 } 11291 11292 /* 11293 * Disable interrupts 11294 */ 11295 MPTSAS_DISABLE_INTR(mpt); 11296 11297 /* 11298 * Abort all commands: outstanding commands, commands in waitq and 11299 * tx_waitq. 11300 */ 11301 mptsas_flush_hba(mpt); 11302 11303 /* 11304 * Reinitialize the chip. 11305 */ 11306 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 11307 rval = DDI_FAILURE; 11308 } 11309 11310 /* 11311 * Enable interrupts again 11312 */ 11313 MPTSAS_ENABLE_INTR(mpt); 11314 11315 /* 11316 * If mptsas_init_chip was successful, update the driver data. 11317 */ 11318 if (rval == DDI_SUCCESS) { 11319 mptsas_update_driver_data(mpt); 11320 } 11321 11322 /* 11323 * Reset the throttles 11324 */ 11325 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 11326 MPTSAS_HASH_FIRST); 11327 while (ptgt != NULL) { 11328 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 11329 11330 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 11331 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 11332 } 11333 11334 mptsas_doneq_empty(mpt); 11335 mptsas_restart_hba(mpt); 11336 11337 if (rval != DDI_SUCCESS) { 11338 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 11339 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 11340 } 11341 11342 /* 11343 * Clear the reset flag so that I/Os can continue. 11344 */ 11345 mpt->m_in_reset = FALSE; 11346 11347 return (rval); 11348 } 11349 11350 int 11351 mptsas_init_chip(mptsas_t *mpt, int first_time) 11352 { 11353 ddi_dma_cookie_t cookie; 11354 uint32_t i; 11355 mptsas_slots_t *new_active; 11356 11357 /* 11358 * Check to see if the firmware image is valid 11359 */ 11360 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) & 11361 MPI2_DIAG_FLASH_BAD_SIG) { 11362 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!"); 11363 goto fail; 11364 } 11365 11366 /* 11367 * Reset the chip 11368 */ 11369 if (mptsas_ioc_reset(mpt) == MPTSAS_RESET_FAIL) { 11370 mptsas_log(mpt, CE_WARN, "hard reset failed!"); 11371 goto fail; 11372 } 11373 11374 if (first_time == FALSE) { 11375 /* 11376 * De-allocate buffers before re-allocating them using the 11377 * latest IOC facts. 11378 */ 11379 mptsas_hba_fini(mpt); 11380 11381 /* 11382 * Setup configuration space 11383 */ 11384 if (mptsas_config_space_init(mpt) == FALSE) { 11385 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init " 11386 "failed!"); 11387 goto fail; 11388 } 11389 } 11390 11391 /* 11392 * IOC facts can change after a diag reset so all buffers that are 11393 * based on these numbers must be de-allocated and re-allocated. Get 11394 * new IOC facts each time chip is initialized. 11395 */ 11396 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) { 11397 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed"); 11398 goto fail; 11399 } 11400 /* 11401 * Re-allocate active slots here if not the first reset. Since 11402 * m_active could have a different number of slots allocated after a 11403 * reset, just de-allocate the old m_active structure and re-allocate a 11404 * new one. Save the tables and IR info from the old m_active. 11405 */ 11406 if (first_time == FALSE) { 11407 new_active = kmem_zalloc(MPTSAS_SLOTS_SIZE(mpt), KM_SLEEP); 11408 if (new_active == NULL) { 11409 mptsas_log(mpt, CE_WARN, "Re-alloc of active slots " 11410 "failed!"); 11411 goto fail; 11412 } else { 11413 new_active->m_n_slots = (mpt->m_max_requests - 2); 11414 new_active->m_size = MPTSAS_SLOTS_SIZE(mpt); 11415 new_active->m_tags = 1; 11416 new_active->m_tgttbl = mpt->m_active->m_tgttbl; 11417 new_active->m_smptbl = mpt->m_active->m_smptbl; 11418 new_active->m_num_raid_configs = 11419 mpt->m_active->m_num_raid_configs; 11420 for (i = 0; i < new_active->m_num_raid_configs; i++) { 11421 new_active->m_raidconfig[i] = 11422 mpt->m_active->m_raidconfig[i]; 11423 } 11424 kmem_free(mpt->m_active, mpt->m_active->m_size); 11425 mpt->m_active = new_active; 11426 } 11427 } 11428 11429 /* 11430 * Allocate request message frames, reply free queue, reply descriptor 11431 * post queue, and reply message frames using latest IOC facts. 11432 */ 11433 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) { 11434 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed"); 11435 goto fail; 11436 } 11437 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) { 11438 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!"); 11439 goto fail; 11440 } 11441 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) { 11442 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!"); 11443 goto fail; 11444 } 11445 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) { 11446 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!"); 11447 goto fail; 11448 } 11449 11450 /* 11451 * Re-Initialize ioc to operational state 11452 */ 11453 if (mptsas_ioc_init(mpt) == DDI_FAILURE) { 11454 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed"); 11455 goto fail; 11456 } 11457 11458 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) * 11459 mpt->m_max_replies, KM_SLEEP); 11460 11461 /* 11462 * Initialize reply post index. Reply free index is initialized after 11463 * the next loop. 11464 */ 11465 mpt->m_post_index = 0; 11466 11467 /* 11468 * Initialize the Reply Free Queue with the physical addresses of our 11469 * reply frames. 11470 */ 11471 cookie.dmac_address = mpt->m_reply_frame_dma_addr; 11472 for (i = 0; i < mpt->m_max_replies; i++) { 11473 ddi_put32(mpt->m_acc_free_queue_hdl, 11474 &((uint32_t *)(void *)mpt->m_free_queue)[i], 11475 cookie.dmac_address); 11476 cookie.dmac_address += mpt->m_reply_frame_size; 11477 } 11478 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11479 DDI_DMA_SYNC_FORDEV); 11480 11481 /* 11482 * Initialize the reply free index to one past the last frame on the 11483 * queue. This will signify that the queue is empty to start with. 11484 */ 11485 mpt->m_free_index = i; 11486 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i); 11487 11488 /* 11489 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's. 11490 */ 11491 for (i = 0; i < mpt->m_post_queue_depth; i++) { 11492 ddi_put64(mpt->m_acc_post_queue_hdl, 11493 &((uint64_t *)(void *)mpt->m_post_queue)[i], 11494 0xFFFFFFFFFFFFFFFF); 11495 } 11496 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 11497 DDI_DMA_SYNC_FORDEV); 11498 11499 /* 11500 * Enable ports 11501 */ 11502 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) { 11503 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed"); 11504 goto fail; 11505 } 11506 11507 /* 11508 * Fill in the phy_info structure and get the base WWID 11509 */ 11510 11511 if (first_time == TRUE) { 11512 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) { 11513 mptsas_log(mpt, CE_WARN, 11514 "mptsas_get_manufacture_page5 failed!"); 11515 goto fail; 11516 } 11517 11518 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) { 11519 mptsas_log(mpt, CE_WARN, 11520 "mptsas_get_sas_io_unit_page_hndshk failed!"); 11521 goto fail; 11522 } 11523 } 11524 11525 /* 11526 * enable events 11527 */ 11528 if (first_time == FALSE) { 11529 if (mptsas_ioc_enable_event_notification(mpt)) { 11530 goto fail; 11531 } 11532 } 11533 11534 /* 11535 * We need checks in attach and these. 11536 * chip_init is called in mult. places 11537 */ 11538 11539 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 11540 DDI_SUCCESS) || 11541 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 11542 DDI_SUCCESS) || 11543 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 11544 DDI_SUCCESS) || 11545 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 11546 DDI_SUCCESS) || 11547 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 11548 DDI_SUCCESS)) { 11549 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11550 goto fail; 11551 } 11552 11553 /* Check all acc handles */ 11554 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 11555 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 11556 DDI_SUCCESS) || 11557 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 11558 DDI_SUCCESS) || 11559 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 11560 DDI_SUCCESS) || 11561 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 11562 DDI_SUCCESS) || 11563 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 11564 DDI_SUCCESS) || 11565 (mptsas_check_acc_handle(mpt->m_config_handle) != 11566 DDI_SUCCESS)) { 11567 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11568 goto fail; 11569 } 11570 11571 return (DDI_SUCCESS); 11572 11573 fail: 11574 return (DDI_FAILURE); 11575 } 11576 11577 static int 11578 mptsas_init_pm(mptsas_t *mpt) 11579 { 11580 char pmc_name[16]; 11581 char *pmc[] = { 11582 NULL, 11583 "0=Off (PCI D3 State)", 11584 "3=On (PCI D0 State)", 11585 NULL 11586 }; 11587 uint16_t pmcsr_stat; 11588 11589 /* 11590 * If power management is supported by this chip, create 11591 * pm-components property for the power management framework 11592 */ 11593 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance); 11594 pmc[0] = pmc_name; 11595 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip, 11596 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 11597 mpt->m_options &= ~MPTSAS_OPT_PM; 11598 mptsas_log(mpt, CE_WARN, 11599 "mptsas%d: pm-component property creation failed.", 11600 mpt->m_instance); 11601 return (DDI_FAILURE); 11602 } 11603 11604 /* 11605 * Power on device. 11606 */ 11607 (void) pm_busy_component(mpt->m_dip, 0); 11608 pmcsr_stat = pci_config_get16(mpt->m_config_handle, 11609 mpt->m_pmcsr_offset); 11610 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) { 11611 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device", 11612 mpt->m_instance); 11613 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, 11614 PCI_PMCSR_D0); 11615 } 11616 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 11617 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed"); 11618 return (DDI_FAILURE); 11619 } 11620 mpt->m_power_level = PM_LEVEL_D0; 11621 /* 11622 * Set pm idle delay. 11623 */ 11624 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 11625 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT); 11626 11627 return (DDI_SUCCESS); 11628 } 11629 11630 /* 11631 * mptsas_add_intrs: 11632 * 11633 * Register FIXED or MSI interrupts. 11634 */ 11635 static int 11636 mptsas_add_intrs(mptsas_t *mpt, int intr_type) 11637 { 11638 dev_info_t *dip = mpt->m_dip; 11639 int avail, actual, count = 0; 11640 int i, flag, ret; 11641 11642 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type)); 11643 11644 /* Get number of interrupts */ 11645 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 11646 if ((ret != DDI_SUCCESS) || (count <= 0)) { 11647 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, " 11648 "ret %d count %d\n", ret, count); 11649 11650 return (DDI_FAILURE); 11651 } 11652 11653 /* Get number of available interrupts */ 11654 ret = ddi_intr_get_navail(dip, intr_type, &avail); 11655 if ((ret != DDI_SUCCESS) || (avail == 0)) { 11656 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, " 11657 "ret %d avail %d\n", ret, avail); 11658 11659 return (DDI_FAILURE); 11660 } 11661 11662 if (avail < count) { 11663 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, " 11664 "navail() returned %d", count, avail); 11665 } 11666 11667 /* Mpt only have one interrupt routine */ 11668 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 11669 count = 1; 11670 } 11671 11672 /* Allocate an array of interrupt handles */ 11673 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t); 11674 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP); 11675 11676 flag = DDI_INTR_ALLOC_NORMAL; 11677 11678 /* call ddi_intr_alloc() */ 11679 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0, 11680 count, &actual, flag); 11681 11682 if ((ret != DDI_SUCCESS) || (actual == 0)) { 11683 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n", 11684 ret); 11685 kmem_free(mpt->m_htable, mpt->m_intr_size); 11686 return (DDI_FAILURE); 11687 } 11688 11689 /* use interrupt count returned or abort? */ 11690 if (actual < count) { 11691 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n", 11692 count, actual); 11693 } 11694 11695 mpt->m_intr_cnt = actual; 11696 11697 /* 11698 * Get priority for first msi, assume remaining are all the same 11699 */ 11700 if ((ret = ddi_intr_get_pri(mpt->m_htable[0], 11701 &mpt->m_intr_pri)) != DDI_SUCCESS) { 11702 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret); 11703 11704 /* Free already allocated intr */ 11705 for (i = 0; i < actual; i++) { 11706 (void) ddi_intr_free(mpt->m_htable[i]); 11707 } 11708 11709 kmem_free(mpt->m_htable, mpt->m_intr_size); 11710 return (DDI_FAILURE); 11711 } 11712 11713 /* Test for high level mutex */ 11714 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) { 11715 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: " 11716 "Hi level interrupt not supported\n"); 11717 11718 /* Free already allocated intr */ 11719 for (i = 0; i < actual; i++) { 11720 (void) ddi_intr_free(mpt->m_htable[i]); 11721 } 11722 11723 kmem_free(mpt->m_htable, mpt->m_intr_size); 11724 return (DDI_FAILURE); 11725 } 11726 11727 /* Call ddi_intr_add_handler() */ 11728 for (i = 0; i < actual; i++) { 11729 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr, 11730 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 11731 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() " 11732 "failed %d\n", ret); 11733 11734 /* Free already allocated intr */ 11735 for (i = 0; i < actual; i++) { 11736 (void) ddi_intr_free(mpt->m_htable[i]); 11737 } 11738 11739 kmem_free(mpt->m_htable, mpt->m_intr_size); 11740 return (DDI_FAILURE); 11741 } 11742 } 11743 11744 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap)) 11745 != DDI_SUCCESS) { 11746 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret); 11747 11748 /* Free already allocated intr */ 11749 for (i = 0; i < actual; i++) { 11750 (void) ddi_intr_free(mpt->m_htable[i]); 11751 } 11752 11753 kmem_free(mpt->m_htable, mpt->m_intr_size); 11754 return (DDI_FAILURE); 11755 } 11756 11757 return (DDI_SUCCESS); 11758 } 11759 11760 /* 11761 * mptsas_rem_intrs: 11762 * 11763 * Unregister FIXED or MSI interrupts 11764 */ 11765 static void 11766 mptsas_rem_intrs(mptsas_t *mpt) 11767 { 11768 int i; 11769 11770 NDBG6(("mptsas_rem_intrs")); 11771 11772 /* Disable all interrupts */ 11773 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 11774 /* Call ddi_intr_block_disable() */ 11775 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt); 11776 } else { 11777 for (i = 0; i < mpt->m_intr_cnt; i++) { 11778 (void) ddi_intr_disable(mpt->m_htable[i]); 11779 } 11780 } 11781 11782 /* Call ddi_intr_remove_handler() */ 11783 for (i = 0; i < mpt->m_intr_cnt; i++) { 11784 (void) ddi_intr_remove_handler(mpt->m_htable[i]); 11785 (void) ddi_intr_free(mpt->m_htable[i]); 11786 } 11787 11788 kmem_free(mpt->m_htable, mpt->m_intr_size); 11789 } 11790 11791 /* 11792 * The IO fault service error handling callback function 11793 */ 11794 /*ARGSUSED*/ 11795 static int 11796 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 11797 { 11798 /* 11799 * as the driver can always deal with an error in any dma or 11800 * access handle, we can just return the fme_status value. 11801 */ 11802 pci_ereport_post(dip, err, NULL); 11803 return (err->fme_status); 11804 } 11805 11806 /* 11807 * mptsas_fm_init - initialize fma capabilities and register with IO 11808 * fault services. 11809 */ 11810 static void 11811 mptsas_fm_init(mptsas_t *mpt) 11812 { 11813 /* 11814 * Need to change iblock to priority for new MSI intr 11815 */ 11816 ddi_iblock_cookie_t fm_ibc; 11817 11818 /* Only register with IO Fault Services if we have some capability */ 11819 if (mpt->m_fm_capabilities) { 11820 /* Adjust access and dma attributes for FMA */ 11821 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 11822 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 11823 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 11824 11825 /* 11826 * Register capabilities with IO Fault Services. 11827 * mpt->m_fm_capabilities will be updated to indicate 11828 * capabilities actually supported (not requested.) 11829 */ 11830 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc); 11831 11832 /* 11833 * Initialize pci ereport capabilities if ereport 11834 * capable (should always be.) 11835 */ 11836 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 11837 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 11838 pci_ereport_setup(mpt->m_dip); 11839 } 11840 11841 /* 11842 * Register error callback if error callback capable. 11843 */ 11844 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 11845 ddi_fm_handler_register(mpt->m_dip, 11846 mptsas_fm_error_cb, (void *) mpt); 11847 } 11848 } 11849 } 11850 11851 /* 11852 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO 11853 * fault services. 11854 * 11855 */ 11856 static void 11857 mptsas_fm_fini(mptsas_t *mpt) 11858 { 11859 /* Only unregister FMA capabilities if registered */ 11860 if (mpt->m_fm_capabilities) { 11861 11862 /* 11863 * Un-register error callback if error callback capable. 11864 */ 11865 11866 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 11867 ddi_fm_handler_unregister(mpt->m_dip); 11868 } 11869 11870 /* 11871 * Release any resources allocated by pci_ereport_setup() 11872 */ 11873 11874 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 11875 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 11876 pci_ereport_teardown(mpt->m_dip); 11877 } 11878 11879 /* Unregister from IO Fault Services */ 11880 ddi_fm_fini(mpt->m_dip); 11881 11882 /* Adjust access and dma attributes for FMA */ 11883 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 11884 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 11885 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 11886 11887 } 11888 } 11889 11890 int 11891 mptsas_check_acc_handle(ddi_acc_handle_t handle) 11892 { 11893 ddi_fm_error_t de; 11894 11895 if (handle == NULL) 11896 return (DDI_FAILURE); 11897 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0); 11898 return (de.fme_status); 11899 } 11900 11901 int 11902 mptsas_check_dma_handle(ddi_dma_handle_t handle) 11903 { 11904 ddi_fm_error_t de; 11905 11906 if (handle == NULL) 11907 return (DDI_FAILURE); 11908 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0); 11909 return (de.fme_status); 11910 } 11911 11912 void 11913 mptsas_fm_ereport(mptsas_t *mpt, char *detail) 11914 { 11915 uint64_t ena; 11916 char buf[FM_MAX_CLASS]; 11917 11918 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 11919 ena = fm_ena_generate(0, FM_ENA_FMT1); 11920 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) { 11921 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP, 11922 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 11923 } 11924 } 11925 11926 static int 11927 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 11928 uint16_t *dev_handle, mptsas_target_t **pptgt) 11929 { 11930 int rval; 11931 uint32_t dev_info; 11932 uint64_t sas_wwn; 11933 mptsas_phymask_t phymask; 11934 uint8_t physport, phynum, config, disk; 11935 mptsas_slots_t *slots = mpt->m_active; 11936 uint64_t devicename; 11937 mptsas_target_t *tmp_tgt = NULL; 11938 11939 ASSERT(*pptgt == NULL); 11940 11941 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle, 11942 &sas_wwn, &dev_info, &physport, &phynum); 11943 if (rval != DDI_SUCCESS) { 11944 rval = DEV_INFO_FAIL_PAGE0; 11945 return (rval); 11946 } 11947 11948 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET | 11949 MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 11950 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) { 11951 rval = DEV_INFO_WRONG_DEVICE_TYPE; 11952 return (rval); 11953 } 11954 11955 /* 11956 * Get SATA Device Name from SAS device page0 for 11957 * sata device, if device name doesn't exist, set m_sas_wwn to 11958 * 0 for direct attached SATA. For the device behind the expander 11959 * we still can use STP address assigned by expander. 11960 */ 11961 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 11962 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 11963 mutex_exit(&mpt->m_mutex); 11964 /* alloc a tmp_tgt to send the cmd */ 11965 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), 11966 KM_SLEEP); 11967 tmp_tgt->m_devhdl = *dev_handle; 11968 tmp_tgt->m_deviceinfo = dev_info; 11969 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 11970 tmp_tgt->m_qfull_retry_interval = 11971 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 11972 tmp_tgt->m_t_throttle = MAX_THROTTLE; 11973 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0); 11974 kmem_free(tmp_tgt, sizeof (struct mptsas_target)); 11975 mutex_enter(&mpt->m_mutex); 11976 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) { 11977 sas_wwn = devicename; 11978 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) { 11979 sas_wwn = 0; 11980 } 11981 } 11982 11983 /* 11984 * Check if the dev handle is for a Phys Disk. If so, set return value 11985 * and exit. Don't add Phys Disks to hash. 11986 */ 11987 for (config = 0; config < slots->m_num_raid_configs; config++) { 11988 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 11989 if (*dev_handle == slots->m_raidconfig[config]. 11990 m_physdisk_devhdl[disk]) { 11991 rval = DEV_INFO_PHYS_DISK; 11992 return (rval); 11993 } 11994 } 11995 } 11996 11997 phymask = mptsas_physport_to_phymask(mpt, physport); 11998 *pptgt = mptsas_tgt_alloc(&slots->m_tgttbl, *dev_handle, sas_wwn, 11999 dev_info, phymask, phynum); 12000 if (*pptgt == NULL) { 12001 mptsas_log(mpt, CE_WARN, "Failed to allocated target" 12002 "structure!"); 12003 rval = DEV_INFO_FAIL_ALLOC; 12004 return (rval); 12005 } 12006 return (DEV_INFO_SUCCESS); 12007 } 12008 12009 uint64_t 12010 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun) 12011 { 12012 uint64_t sata_guid = 0, *pwwn = NULL; 12013 int target = ptgt->m_devhdl; 12014 uchar_t *inq83 = NULL; 12015 int inq83_len = 0xFF; 12016 uchar_t *dblk = NULL; 12017 int inq83_retry = 3; 12018 int rval = DDI_FAILURE; 12019 12020 inq83 = kmem_zalloc(inq83_len, KM_SLEEP); 12021 12022 inq83_retry: 12023 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 12024 inq83_len, NULL, 1); 12025 if (rval != DDI_SUCCESS) { 12026 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 12027 "0x83 for target:%x, lun:%x failed!", target, lun); 12028 goto out; 12029 } 12030 /* According to SAT2, the first descriptor is logic unit name */ 12031 dblk = &inq83[4]; 12032 if ((dblk[1] & 0x30) != 0) { 12033 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated."); 12034 goto out; 12035 } 12036 pwwn = (uint64_t *)(void *)(&dblk[4]); 12037 if ((dblk[4] & 0xf0) == 0x50) { 12038 sata_guid = BE_64(*pwwn); 12039 goto out; 12040 } else if (dblk[4] == 'A') { 12041 NDBG20(("SATA drive has no NAA format GUID.")); 12042 goto out; 12043 } else { 12044 /* The data is not ready, wait and retry */ 12045 inq83_retry--; 12046 if (inq83_retry <= 0) { 12047 goto out; 12048 } 12049 NDBG20(("The GUID is not ready, retry...")); 12050 delay(1 * drv_usectohz(1000000)); 12051 goto inq83_retry; 12052 } 12053 out: 12054 kmem_free(inq83, inq83_len); 12055 return (sata_guid); 12056 } 12057 12058 static int 12059 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page, 12060 unsigned char *buf, int len, int *reallen, uchar_t evpd) 12061 { 12062 uchar_t cdb[CDB_GROUP0]; 12063 struct scsi_address ap; 12064 struct buf *data_bp = NULL; 12065 int resid = 0; 12066 int ret = DDI_FAILURE; 12067 12068 ASSERT(len <= 0xffff); 12069 12070 ap.a_target = MPTSAS_INVALID_DEVHDL; 12071 ap.a_lun = (uchar_t)(lun); 12072 ap.a_hba_tran = mpt->m_tran; 12073 12074 data_bp = scsi_alloc_consistent_buf(&ap, 12075 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL); 12076 if (data_bp == NULL) { 12077 return (ret); 12078 } 12079 bzero(cdb, CDB_GROUP0); 12080 cdb[0] = SCMD_INQUIRY; 12081 cdb[1] = evpd; 12082 cdb[2] = page; 12083 cdb[3] = (len & 0xff00) >> 8; 12084 cdb[4] = (len & 0x00ff); 12085 cdb[5] = 0; 12086 12087 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp, 12088 &resid); 12089 if (ret == DDI_SUCCESS) { 12090 if (reallen) { 12091 *reallen = len - resid; 12092 } 12093 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len); 12094 } 12095 if (data_bp) { 12096 scsi_free_consistent_buf(data_bp); 12097 } 12098 return (ret); 12099 } 12100 12101 static int 12102 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 12103 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 12104 int *resid) 12105 { 12106 struct scsi_pkt *pktp = NULL; 12107 scsi_hba_tran_t *tran_clone = NULL; 12108 mptsas_tgt_private_t *tgt_private = NULL; 12109 int ret = DDI_FAILURE; 12110 12111 /* 12112 * scsi_hba_tran_t->tran_tgt_private is used to pass the address 12113 * information to scsi_init_pkt, allocate a scsi_hba_tran structure 12114 * to simulate the cmds from sd 12115 */ 12116 tran_clone = kmem_alloc( 12117 sizeof (scsi_hba_tran_t), KM_SLEEP); 12118 if (tran_clone == NULL) { 12119 goto out; 12120 } 12121 bcopy((caddr_t)mpt->m_tran, 12122 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t)); 12123 tgt_private = kmem_alloc( 12124 sizeof (mptsas_tgt_private_t), KM_SLEEP); 12125 if (tgt_private == NULL) { 12126 goto out; 12127 } 12128 tgt_private->t_lun = ap->a_lun; 12129 tgt_private->t_private = ptgt; 12130 tran_clone->tran_tgt_private = tgt_private; 12131 ap->a_hba_tran = tran_clone; 12132 12133 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL, 12134 data_bp, cdblen, sizeof (struct scsi_arq_status), 12135 0, PKT_CONSISTENT, NULL, NULL); 12136 if (pktp == NULL) { 12137 goto out; 12138 } 12139 bcopy(cdb, pktp->pkt_cdbp, cdblen); 12140 pktp->pkt_flags = FLAG_NOPARITY; 12141 if (scsi_poll(pktp) < 0) { 12142 goto out; 12143 } 12144 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) { 12145 goto out; 12146 } 12147 if (resid != NULL) { 12148 *resid = pktp->pkt_resid; 12149 } 12150 12151 ret = DDI_SUCCESS; 12152 out: 12153 if (pktp) { 12154 scsi_destroy_pkt(pktp); 12155 } 12156 if (tran_clone) { 12157 kmem_free(tran_clone, sizeof (scsi_hba_tran_t)); 12158 } 12159 if (tgt_private) { 12160 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 12161 } 12162 return (ret); 12163 } 12164 static int 12165 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun) 12166 { 12167 char *cp = NULL; 12168 char *ptr = NULL; 12169 size_t s = 0; 12170 char *wwid_str = NULL; 12171 char *lun_str = NULL; 12172 long lunnum; 12173 long phyid = -1; 12174 int rc = DDI_FAILURE; 12175 12176 ptr = name; 12177 ASSERT(ptr[0] == 'w' || ptr[0] == 'p'); 12178 ptr++; 12179 if ((cp = strchr(ptr, ',')) == NULL) { 12180 return (DDI_FAILURE); 12181 } 12182 12183 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 12184 s = (uintptr_t)cp - (uintptr_t)ptr; 12185 12186 bcopy(ptr, wwid_str, s); 12187 wwid_str[s] = '\0'; 12188 12189 ptr = ++cp; 12190 12191 if ((cp = strchr(ptr, '\0')) == NULL) { 12192 goto out; 12193 } 12194 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 12195 s = (uintptr_t)cp - (uintptr_t)ptr; 12196 12197 bcopy(ptr, lun_str, s); 12198 lun_str[s] = '\0'; 12199 12200 if (name[0] == 'p') { 12201 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid); 12202 } else { 12203 rc = scsi_wwnstr_to_wwn(wwid_str, wwid); 12204 } 12205 if (rc != DDI_SUCCESS) 12206 goto out; 12207 12208 if (phyid != -1) { 12209 ASSERT(phyid < MPTSAS_MAX_PHYS); 12210 *phy = (uint8_t)phyid; 12211 } 12212 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum); 12213 if (rc != 0) 12214 goto out; 12215 12216 *lun = (int)lunnum; 12217 rc = DDI_SUCCESS; 12218 out: 12219 if (wwid_str) 12220 kmem_free(wwid_str, SCSI_MAXNAMELEN); 12221 if (lun_str) 12222 kmem_free(lun_str, SCSI_MAXNAMELEN); 12223 12224 return (rc); 12225 } 12226 12227 /* 12228 * mptsas_parse_smp_name() is to parse sas wwn string 12229 * which format is "wWWN" 12230 */ 12231 static int 12232 mptsas_parse_smp_name(char *name, uint64_t *wwn) 12233 { 12234 char *ptr = name; 12235 12236 if (*ptr != 'w') { 12237 return (DDI_FAILURE); 12238 } 12239 12240 ptr++; 12241 if (scsi_wwnstr_to_wwn(ptr, wwn)) { 12242 return (DDI_FAILURE); 12243 } 12244 return (DDI_SUCCESS); 12245 } 12246 12247 static int 12248 mptsas_bus_config(dev_info_t *pdip, uint_t flag, 12249 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 12250 { 12251 int ret = NDI_FAILURE; 12252 int circ = 0; 12253 int circ1 = 0; 12254 mptsas_t *mpt; 12255 char *ptr = NULL; 12256 char *devnm = NULL; 12257 uint64_t wwid = 0; 12258 uint8_t phy = 0xFF; 12259 int lun = 0; 12260 uint_t mflags = flag; 12261 12262 if (scsi_hba_iport_unit_address(pdip) == 0) { 12263 return (DDI_FAILURE); 12264 } 12265 12266 mpt = DIP2MPT(pdip); 12267 if (!mpt) { 12268 return (DDI_FAILURE); 12269 } 12270 12271 /* 12272 * Hold the nexus across the bus_config 12273 */ 12274 ndi_devi_enter(scsi_vhci_dip, &circ); 12275 ndi_devi_enter(pdip, &circ1); 12276 switch (op) { 12277 case BUS_CONFIG_ONE: 12278 /* parse wwid/target name out of name given */ 12279 if ((ptr = strchr((char *)arg, '@')) == NULL) { 12280 ret = NDI_FAILURE; 12281 break; 12282 } 12283 ptr++; 12284 if (strncmp((char *)arg, "smp", 3) == 0) { 12285 /* 12286 * This is a SMP target device 12287 */ 12288 ret = mptsas_parse_smp_name(ptr, &wwid); 12289 if (ret != DDI_SUCCESS) { 12290 ret = NDI_FAILURE; 12291 break; 12292 } 12293 ret = mptsas_config_smp(pdip, wwid, childp); 12294 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) { 12295 /* 12296 * OBP could pass down a non-canonical form 12297 * bootpath without LUN part when LUN is 0. 12298 * So driver need adjust the string. 12299 */ 12300 if (strchr(ptr, ',') == NULL) { 12301 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 12302 (void) sprintf(devnm, "%s,0", (char *)arg); 12303 ptr = strchr(devnm, '@'); 12304 ptr++; 12305 } 12306 12307 /* 12308 * The device path is wWWID format and the device 12309 * is not SMP target device. 12310 */ 12311 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun); 12312 if (ret != DDI_SUCCESS) { 12313 ret = NDI_FAILURE; 12314 break; 12315 } 12316 if (ptr[0] == 'w') { 12317 ret = mptsas_config_one_addr(pdip, wwid, 12318 lun, childp); 12319 } else if (ptr[0] == 'p') { 12320 ret = mptsas_config_one_phy(pdip, phy, lun, 12321 childp); 12322 } 12323 } else { 12324 ret = NDI_FAILURE; 12325 break; 12326 } 12327 12328 /* 12329 * DDI group instructed us to use this flag. 12330 */ 12331 mflags |= NDI_MDI_FALLBACK; 12332 break; 12333 case BUS_CONFIG_DRIVER: 12334 case BUS_CONFIG_ALL: 12335 mptsas_config_all(pdip); 12336 ret = NDI_SUCCESS; 12337 break; 12338 } 12339 12340 if (ret == NDI_SUCCESS) { 12341 ret = ndi_busop_bus_config(pdip, mflags, op, 12342 (devnm == NULL) ? arg : devnm, childp, 0); 12343 } 12344 12345 ndi_devi_exit(pdip, circ1); 12346 ndi_devi_exit(scsi_vhci_dip, circ); 12347 if (devnm != NULL) 12348 kmem_free(devnm, SCSI_MAXNAMELEN); 12349 return (ret); 12350 } 12351 12352 static int 12353 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip, 12354 mptsas_target_t *ptgt) 12355 { 12356 int rval = DDI_FAILURE; 12357 struct scsi_inquiry *sd_inq = NULL; 12358 mptsas_t *mpt = DIP2MPT(pdip); 12359 12360 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 12361 12362 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq, 12363 SUN_INQSIZE, 0, (uchar_t)0); 12364 12365 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 12366 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun); 12367 } else { 12368 rval = DDI_FAILURE; 12369 } 12370 12371 kmem_free(sd_inq, SUN_INQSIZE); 12372 return (rval); 12373 } 12374 12375 static int 12376 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 12377 dev_info_t **lundip) 12378 { 12379 int rval; 12380 mptsas_t *mpt = DIP2MPT(pdip); 12381 int phymask; 12382 mptsas_target_t *ptgt = NULL; 12383 12384 /* 12385 * Get the physical port associated to the iport 12386 */ 12387 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 12388 "phymask", 0); 12389 12390 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr); 12391 if (ptgt == NULL) { 12392 /* 12393 * didn't match any device by searching 12394 */ 12395 return (DDI_FAILURE); 12396 } 12397 /* 12398 * If the LUN already exists and the status is online, 12399 * we just return the pointer to dev_info_t directly. 12400 * For the mdi_pathinfo node, we'll handle it in 12401 * mptsas_create_virt_lun() 12402 * TODO should be also in mptsas_handle_dr 12403 */ 12404 12405 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun); 12406 if (*lundip != NULL) { 12407 /* 12408 * TODO Another senario is, we hotplug the same disk 12409 * on the same slot, the devhdl changed, is this 12410 * possible? 12411 * tgt_private->t_private != ptgt 12412 */ 12413 if (sasaddr != ptgt->m_sas_wwn) { 12414 /* 12415 * The device has changed although the devhdl is the 12416 * same (Enclosure mapping mode, change drive on the 12417 * same slot) 12418 */ 12419 return (DDI_FAILURE); 12420 } 12421 return (DDI_SUCCESS); 12422 } 12423 12424 if (phymask == 0) { 12425 /* 12426 * Configure IR volume 12427 */ 12428 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip); 12429 return (rval); 12430 } 12431 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 12432 12433 return (rval); 12434 } 12435 12436 static int 12437 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 12438 dev_info_t **lundip) 12439 { 12440 int rval; 12441 mptsas_target_t *ptgt = NULL; 12442 12443 ptgt = mptsas_phy_to_tgt(pdip, phy); 12444 if (ptgt == NULL) { 12445 /* 12446 * didn't match any device by searching 12447 */ 12448 return (DDI_FAILURE); 12449 } 12450 12451 /* 12452 * If the LUN already exists and the status is online, 12453 * we just return the pointer to dev_info_t directly. 12454 * For the mdi_pathinfo node, we'll handle it in 12455 * mptsas_create_virt_lun(). 12456 */ 12457 12458 *lundip = mptsas_find_child_phy(pdip, phy); 12459 if (*lundip != NULL) { 12460 return (DDI_SUCCESS); 12461 } 12462 12463 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 12464 12465 return (rval); 12466 } 12467 12468 static int 12469 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num, 12470 uint8_t *lun_addr_type) 12471 { 12472 uint32_t lun_idx = 0; 12473 12474 ASSERT(lun_num != NULL); 12475 ASSERT(lun_addr_type != NULL); 12476 12477 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 12478 /* determine report luns addressing type */ 12479 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) { 12480 /* 12481 * Vendors in the field have been found to be concatenating 12482 * bus/target/lun to equal the complete lun value instead 12483 * of switching to flat space addressing 12484 */ 12485 /* 00b - peripheral device addressing method */ 12486 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL: 12487 /* FALLTHRU */ 12488 /* 10b - logical unit addressing method */ 12489 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT: 12490 /* FALLTHRU */ 12491 /* 01b - flat space addressing method */ 12492 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE: 12493 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */ 12494 *lun_addr_type = (buf[lun_idx] & 12495 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6; 12496 *lun_num = (buf[lun_idx] & 0x3F) << 8; 12497 *lun_num |= buf[lun_idx + 1]; 12498 return (DDI_SUCCESS); 12499 default: 12500 return (DDI_FAILURE); 12501 } 12502 } 12503 12504 static int 12505 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt) 12506 { 12507 struct buf *repluns_bp = NULL; 12508 struct scsi_address ap; 12509 uchar_t cdb[CDB_GROUP5]; 12510 int ret = DDI_FAILURE; 12511 int retry = 0; 12512 int lun_list_len = 0; 12513 uint16_t lun_num = 0; 12514 uint8_t lun_addr_type = 0; 12515 uint32_t lun_cnt = 0; 12516 uint32_t lun_total = 0; 12517 dev_info_t *cdip = NULL; 12518 uint16_t *saved_repluns = NULL; 12519 char *buffer = NULL; 12520 int buf_len = 128; 12521 mptsas_t *mpt = DIP2MPT(pdip); 12522 uint64_t sas_wwn = 0; 12523 uint8_t phy = 0xFF; 12524 uint32_t dev_info = 0; 12525 12526 mutex_enter(&mpt->m_mutex); 12527 sas_wwn = ptgt->m_sas_wwn; 12528 phy = ptgt->m_phynum; 12529 dev_info = ptgt->m_deviceinfo; 12530 mutex_exit(&mpt->m_mutex); 12531 12532 if (sas_wwn == 0) { 12533 /* 12534 * It's a SATA without Device Name 12535 * So don't try multi-LUNs 12536 */ 12537 if (mptsas_find_child_phy(pdip, phy)) { 12538 return (DDI_SUCCESS); 12539 } else { 12540 /* 12541 * need configure and create node 12542 */ 12543 return (DDI_FAILURE); 12544 } 12545 } 12546 12547 /* 12548 * WWN (SAS address or Device Name exist) 12549 */ 12550 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 12551 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 12552 /* 12553 * SATA device with Device Name 12554 * So don't try multi-LUNs 12555 */ 12556 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) { 12557 return (DDI_SUCCESS); 12558 } else { 12559 return (DDI_FAILURE); 12560 } 12561 } 12562 12563 do { 12564 ap.a_target = MPTSAS_INVALID_DEVHDL; 12565 ap.a_lun = 0; 12566 ap.a_hba_tran = mpt->m_tran; 12567 repluns_bp = scsi_alloc_consistent_buf(&ap, 12568 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL); 12569 if (repluns_bp == NULL) { 12570 retry++; 12571 continue; 12572 } 12573 bzero(cdb, CDB_GROUP5); 12574 cdb[0] = SCMD_REPORT_LUNS; 12575 cdb[6] = (buf_len & 0xff000000) >> 24; 12576 cdb[7] = (buf_len & 0x00ff0000) >> 16; 12577 cdb[8] = (buf_len & 0x0000ff00) >> 8; 12578 cdb[9] = (buf_len & 0x000000ff); 12579 12580 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5, 12581 repluns_bp, NULL); 12582 if (ret != DDI_SUCCESS) { 12583 scsi_free_consistent_buf(repluns_bp); 12584 retry++; 12585 continue; 12586 } 12587 lun_list_len = BE_32(*(int *)((void *)( 12588 repluns_bp->b_un.b_addr))); 12589 if (buf_len >= lun_list_len + 8) { 12590 ret = DDI_SUCCESS; 12591 break; 12592 } 12593 scsi_free_consistent_buf(repluns_bp); 12594 buf_len = lun_list_len + 8; 12595 12596 } while (retry < 3); 12597 12598 if (ret != DDI_SUCCESS) 12599 return (ret); 12600 buffer = (char *)repluns_bp->b_un.b_addr; 12601 /* 12602 * find out the number of luns returned by the SCSI ReportLun call 12603 * and allocate buffer space 12604 */ 12605 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 12606 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP); 12607 if (saved_repluns == NULL) { 12608 scsi_free_consistent_buf(repluns_bp); 12609 return (DDI_FAILURE); 12610 } 12611 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) { 12612 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer), 12613 &lun_num, &lun_addr_type) != DDI_SUCCESS) { 12614 continue; 12615 } 12616 saved_repluns[lun_cnt] = lun_num; 12617 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) 12618 ret = DDI_SUCCESS; 12619 else 12620 ret = mptsas_probe_lun(pdip, lun_num, &cdip, 12621 ptgt); 12622 if ((ret == DDI_SUCCESS) && (cdip != NULL)) { 12623 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip, 12624 MPTSAS_DEV_GONE); 12625 } 12626 } 12627 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt); 12628 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total); 12629 scsi_free_consistent_buf(repluns_bp); 12630 return (DDI_SUCCESS); 12631 } 12632 12633 static int 12634 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip) 12635 { 12636 int rval = DDI_FAILURE; 12637 struct scsi_inquiry *sd_inq = NULL; 12638 mptsas_t *mpt = DIP2MPT(pdip); 12639 mptsas_target_t *ptgt = NULL; 12640 12641 mutex_enter(&mpt->m_mutex); 12642 ptgt = mptsas_search_by_devhdl(&mpt->m_active->m_tgttbl, target); 12643 mutex_exit(&mpt->m_mutex); 12644 if (ptgt == NULL) { 12645 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x " 12646 "not found.", target); 12647 return (rval); 12648 } 12649 12650 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 12651 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq, 12652 SUN_INQSIZE, 0, (uchar_t)0); 12653 12654 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 12655 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt, 12656 0); 12657 } else { 12658 rval = DDI_FAILURE; 12659 } 12660 12661 kmem_free(sd_inq, SUN_INQSIZE); 12662 return (rval); 12663 } 12664 12665 /* 12666 * configure all RAID volumes for virtual iport 12667 */ 12668 static void 12669 mptsas_config_all_viport(dev_info_t *pdip) 12670 { 12671 mptsas_t *mpt = DIP2MPT(pdip); 12672 int config, vol; 12673 int target; 12674 dev_info_t *lundip = NULL; 12675 mptsas_slots_t *slots = mpt->m_active; 12676 12677 /* 12678 * Get latest RAID info and search for any Volume DevHandles. If any 12679 * are found, configure the volume. 12680 */ 12681 mutex_enter(&mpt->m_mutex); 12682 for (config = 0; config < slots->m_num_raid_configs; config++) { 12683 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 12684 if (slots->m_raidconfig[config].m_raidvol[vol].m_israid 12685 == 1) { 12686 target = slots->m_raidconfig[config]. 12687 m_raidvol[vol].m_raidhandle; 12688 mutex_exit(&mpt->m_mutex); 12689 (void) mptsas_config_raid(pdip, target, 12690 &lundip); 12691 mutex_enter(&mpt->m_mutex); 12692 } 12693 } 12694 } 12695 mutex_exit(&mpt->m_mutex); 12696 } 12697 12698 static void 12699 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns, 12700 int lun_cnt, mptsas_target_t *ptgt) 12701 { 12702 dev_info_t *child = NULL, *savechild = NULL; 12703 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 12704 uint64_t sas_wwn, wwid; 12705 uint8_t phy; 12706 int lun; 12707 int i; 12708 int find; 12709 char *addr; 12710 char *nodename; 12711 mptsas_t *mpt = DIP2MPT(pdip); 12712 12713 mutex_enter(&mpt->m_mutex); 12714 wwid = ptgt->m_sas_wwn; 12715 mutex_exit(&mpt->m_mutex); 12716 12717 child = ddi_get_child(pdip); 12718 while (child) { 12719 find = 0; 12720 savechild = child; 12721 child = ddi_get_next_sibling(child); 12722 12723 nodename = ddi_node_name(savechild); 12724 if (strcmp(nodename, "smp") == 0) { 12725 continue; 12726 } 12727 12728 addr = ddi_get_name_addr(savechild); 12729 if (addr == NULL) { 12730 continue; 12731 } 12732 12733 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) != 12734 DDI_SUCCESS) { 12735 continue; 12736 } 12737 12738 if (wwid == sas_wwn) { 12739 for (i = 0; i < lun_cnt; i++) { 12740 if (repluns[i] == lun) { 12741 find = 1; 12742 break; 12743 } 12744 } 12745 } else { 12746 continue; 12747 } 12748 if (find == 0) { 12749 /* 12750 * The lun has not been there already 12751 */ 12752 (void) mptsas_offline_lun(pdip, savechild, NULL, 12753 NDI_DEVI_REMOVE); 12754 } 12755 } 12756 12757 pip = mdi_get_next_client_path(pdip, NULL); 12758 while (pip) { 12759 find = 0; 12760 savepip = pip; 12761 addr = MDI_PI(pip)->pi_addr; 12762 12763 pip = mdi_get_next_client_path(pdip, pip); 12764 12765 if (addr == NULL) { 12766 continue; 12767 } 12768 12769 if (mptsas_parse_address(addr, &sas_wwn, &phy, 12770 &lun) != DDI_SUCCESS) { 12771 continue; 12772 } 12773 12774 if (sas_wwn == wwid) { 12775 for (i = 0; i < lun_cnt; i++) { 12776 if (repluns[i] == lun) { 12777 find = 1; 12778 break; 12779 } 12780 } 12781 } else { 12782 continue; 12783 } 12784 12785 if (find == 0) { 12786 /* 12787 * The lun has not been there already 12788 */ 12789 (void) mptsas_offline_lun(pdip, NULL, savepip, 12790 NDI_DEVI_REMOVE); 12791 } 12792 } 12793 } 12794 12795 void 12796 mptsas_update_hashtab(struct mptsas *mpt) 12797 { 12798 uint32_t page_address; 12799 int rval = 0; 12800 uint16_t dev_handle; 12801 mptsas_target_t *ptgt = NULL; 12802 mptsas_smp_t smp_node; 12803 12804 /* 12805 * Get latest RAID info. 12806 */ 12807 (void) mptsas_get_raid_info(mpt); 12808 12809 dev_handle = mpt->m_smp_devhdl; 12810 for (; mpt->m_done_traverse_smp == 0; ) { 12811 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 12812 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle; 12813 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node) 12814 != DDI_SUCCESS) { 12815 break; 12816 } 12817 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl; 12818 (void) mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node); 12819 } 12820 12821 /* 12822 * Config target devices 12823 */ 12824 dev_handle = mpt->m_dev_handle; 12825 12826 /* 12827 * Do loop to get sas device page 0 by GetNextHandle till the 12828 * the last handle. If the sas device is a SATA/SSP target, 12829 * we try to config it. 12830 */ 12831 for (; mpt->m_done_traverse_dev == 0; ) { 12832 ptgt = NULL; 12833 page_address = 12834 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 12835 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 12836 (uint32_t)dev_handle; 12837 rval = mptsas_get_target_device_info(mpt, page_address, 12838 &dev_handle, &ptgt); 12839 if ((rval == DEV_INFO_FAIL_PAGE0) || 12840 (rval == DEV_INFO_FAIL_ALLOC)) { 12841 break; 12842 } 12843 12844 mpt->m_dev_handle = dev_handle; 12845 } 12846 12847 } 12848 12849 void 12850 mptsas_invalid_hashtab(mptsas_hash_table_t *hashtab) 12851 { 12852 mptsas_hash_data_t *data; 12853 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST); 12854 while (data != NULL) { 12855 data->devhdl = MPTSAS_INVALID_DEVHDL; 12856 data->device_info = 0; 12857 /* 12858 * For tgttbl, clear dr_flag. 12859 */ 12860 data->dr_flag = MPTSAS_DR_INACTIVE; 12861 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT); 12862 } 12863 } 12864 12865 void 12866 mptsas_update_driver_data(struct mptsas *mpt) 12867 { 12868 /* 12869 * TODO after hard reset, update the driver data structures 12870 * 1. update port/phymask mapping table mpt->m_phy_info 12871 * 2. invalid all the entries in hash table 12872 * m_devhdl = 0xffff and m_deviceinfo = 0 12873 * 3. call sas_device_page/expander_page to update hash table 12874 */ 12875 mptsas_update_phymask(mpt); 12876 /* 12877 * Invalid the existing entries 12878 */ 12879 mptsas_invalid_hashtab(&mpt->m_active->m_tgttbl); 12880 mptsas_invalid_hashtab(&mpt->m_active->m_smptbl); 12881 mpt->m_done_traverse_dev = 0; 12882 mpt->m_done_traverse_smp = 0; 12883 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL; 12884 mptsas_update_hashtab(mpt); 12885 } 12886 12887 static void 12888 mptsas_config_all(dev_info_t *pdip) 12889 { 12890 dev_info_t *smpdip = NULL; 12891 mptsas_t *mpt = DIP2MPT(pdip); 12892 int phymask = 0; 12893 mptsas_phymask_t phy_mask; 12894 mptsas_target_t *ptgt = NULL; 12895 mptsas_smp_t *psmp; 12896 12897 /* 12898 * Get the phymask associated to the iport 12899 */ 12900 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 12901 "phymask", 0); 12902 12903 /* 12904 * Enumerate RAID volumes here (phymask == 0). 12905 */ 12906 if (phymask == 0) { 12907 mptsas_config_all_viport(pdip); 12908 return; 12909 } 12910 12911 mutex_enter(&mpt->m_mutex); 12912 12913 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp) { 12914 mptsas_update_hashtab(mpt); 12915 } 12916 12917 psmp = (mptsas_smp_t *)mptsas_hash_traverse(&mpt->m_active->m_smptbl, 12918 MPTSAS_HASH_FIRST); 12919 while (psmp != NULL) { 12920 phy_mask = psmp->m_phymask; 12921 if (phy_mask == phymask) { 12922 smpdip = NULL; 12923 mutex_exit(&mpt->m_mutex); 12924 (void) mptsas_online_smp(pdip, psmp, &smpdip); 12925 mutex_enter(&mpt->m_mutex); 12926 } 12927 psmp = (mptsas_smp_t *)mptsas_hash_traverse( 12928 &mpt->m_active->m_smptbl, MPTSAS_HASH_NEXT); 12929 } 12930 12931 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 12932 MPTSAS_HASH_FIRST); 12933 while (ptgt != NULL) { 12934 phy_mask = ptgt->m_phymask; 12935 if (phy_mask == phymask) { 12936 mutex_exit(&mpt->m_mutex); 12937 (void) mptsas_config_target(pdip, ptgt); 12938 mutex_enter(&mpt->m_mutex); 12939 } 12940 12941 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 12942 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 12943 } 12944 mutex_exit(&mpt->m_mutex); 12945 } 12946 12947 static int 12948 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt) 12949 { 12950 int rval = DDI_FAILURE; 12951 dev_info_t *tdip; 12952 12953 rval = mptsas_config_luns(pdip, ptgt); 12954 if (rval != DDI_SUCCESS) { 12955 /* 12956 * The return value means the SCMD_REPORT_LUNS 12957 * did not execute successfully. The target maybe 12958 * doesn't support such command. 12959 */ 12960 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt); 12961 } 12962 return (rval); 12963 } 12964 12965 /* 12966 * Return fail if not all the childs/paths are freed. 12967 * if there is any path under the HBA, the return value will be always fail 12968 * because we didn't call mdi_pi_free for path 12969 */ 12970 static int 12971 mptsas_offline_target(dev_info_t *pdip, char *name) 12972 { 12973 dev_info_t *child = NULL, *prechild = NULL; 12974 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 12975 int tmp_rval, rval = DDI_SUCCESS; 12976 char *addr, *cp; 12977 size_t s; 12978 mptsas_t *mpt = DIP2MPT(pdip); 12979 12980 child = ddi_get_child(pdip); 12981 while (child) { 12982 addr = ddi_get_name_addr(child); 12983 prechild = child; 12984 child = ddi_get_next_sibling(child); 12985 12986 if (addr == NULL) { 12987 continue; 12988 } 12989 if ((cp = strchr(addr, ',')) == NULL) { 12990 continue; 12991 } 12992 12993 s = (uintptr_t)cp - (uintptr_t)addr; 12994 12995 if (strncmp(addr, name, s) != 0) { 12996 continue; 12997 } 12998 12999 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL, 13000 NDI_DEVI_REMOVE); 13001 if (tmp_rval != DDI_SUCCESS) { 13002 rval = DDI_FAILURE; 13003 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 13004 prechild, MPTSAS_DEV_GONE) != 13005 DDI_PROP_SUCCESS) { 13006 mptsas_log(mpt, CE_WARN, "mptsas driver " 13007 "unable to create property for " 13008 "SAS %s (MPTSAS_DEV_GONE)", addr); 13009 } 13010 } 13011 } 13012 13013 pip = mdi_get_next_client_path(pdip, NULL); 13014 while (pip) { 13015 addr = MDI_PI(pip)->pi_addr; 13016 savepip = pip; 13017 pip = mdi_get_next_client_path(pdip, pip); 13018 if (addr == NULL) { 13019 continue; 13020 } 13021 13022 if ((cp = strchr(addr, ',')) == NULL) { 13023 continue; 13024 } 13025 13026 s = (uintptr_t)cp - (uintptr_t)addr; 13027 13028 if (strncmp(addr, name, s) != 0) { 13029 continue; 13030 } 13031 13032 (void) mptsas_offline_lun(pdip, NULL, savepip, 13033 NDI_DEVI_REMOVE); 13034 /* 13035 * driver will not invoke mdi_pi_free, so path will not 13036 * be freed forever, return DDI_FAILURE. 13037 */ 13038 rval = DDI_FAILURE; 13039 } 13040 return (rval); 13041 } 13042 13043 static int 13044 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 13045 mdi_pathinfo_t *rpip, uint_t flags) 13046 { 13047 int rval = DDI_FAILURE; 13048 char *devname; 13049 dev_info_t *cdip, *parent; 13050 13051 if (rpip != NULL) { 13052 parent = scsi_vhci_dip; 13053 cdip = mdi_pi_get_client(rpip); 13054 } else if (rdip != NULL) { 13055 parent = pdip; 13056 cdip = rdip; 13057 } else { 13058 return (DDI_FAILURE); 13059 } 13060 13061 /* 13062 * Make sure node is attached otherwise 13063 * it won't have related cache nodes to 13064 * clean up. i_ddi_devi_attached is 13065 * similiar to i_ddi_node_state(cdip) >= 13066 * DS_ATTACHED. 13067 */ 13068 if (i_ddi_devi_attached(cdip)) { 13069 13070 /* Get full devname */ 13071 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 13072 (void) ddi_deviname(cdip, devname); 13073 /* Clean cache */ 13074 (void) devfs_clean(parent, devname + 1, 13075 DV_CLEAN_FORCE); 13076 kmem_free(devname, MAXNAMELEN + 1); 13077 } 13078 if (rpip != NULL) { 13079 if (MDI_PI_IS_OFFLINE(rpip)) { 13080 rval = DDI_SUCCESS; 13081 } else { 13082 rval = mdi_pi_offline(rpip, 0); 13083 } 13084 } else { 13085 rval = ndi_devi_offline(cdip, flags); 13086 } 13087 13088 return (rval); 13089 } 13090 13091 static dev_info_t * 13092 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn) 13093 { 13094 dev_info_t *child = NULL; 13095 char *smp_wwn = NULL; 13096 13097 child = ddi_get_child(parent); 13098 while (child) { 13099 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child, 13100 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn) 13101 != DDI_SUCCESS) { 13102 child = ddi_get_next_sibling(child); 13103 continue; 13104 } 13105 13106 if (strcmp(smp_wwn, str_wwn) == 0) { 13107 ddi_prop_free(smp_wwn); 13108 break; 13109 } 13110 child = ddi_get_next_sibling(child); 13111 ddi_prop_free(smp_wwn); 13112 } 13113 return (child); 13114 } 13115 13116 static int 13117 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags) 13118 { 13119 int rval = DDI_FAILURE; 13120 char *devname; 13121 char wwn_str[MPTSAS_WWN_STRLEN]; 13122 dev_info_t *cdip; 13123 13124 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr); 13125 13126 cdip = mptsas_find_smp_child(pdip, wwn_str); 13127 13128 if (cdip == NULL) 13129 return (DDI_SUCCESS); 13130 13131 /* 13132 * Make sure node is attached otherwise 13133 * it won't have related cache nodes to 13134 * clean up. i_ddi_devi_attached is 13135 * similiar to i_ddi_node_state(cdip) >= 13136 * DS_ATTACHED. 13137 */ 13138 if (i_ddi_devi_attached(cdip)) { 13139 13140 /* Get full devname */ 13141 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 13142 (void) ddi_deviname(cdip, devname); 13143 /* Clean cache */ 13144 (void) devfs_clean(pdip, devname + 1, 13145 DV_CLEAN_FORCE); 13146 kmem_free(devname, MAXNAMELEN + 1); 13147 } 13148 13149 rval = ndi_devi_offline(cdip, flags); 13150 13151 return (rval); 13152 } 13153 13154 static dev_info_t * 13155 mptsas_find_child(dev_info_t *pdip, char *name) 13156 { 13157 dev_info_t *child = NULL; 13158 char *rname = NULL; 13159 int rval = DDI_FAILURE; 13160 13161 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13162 13163 child = ddi_get_child(pdip); 13164 while (child) { 13165 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN); 13166 if (rval != DDI_SUCCESS) { 13167 child = ddi_get_next_sibling(child); 13168 bzero(rname, SCSI_MAXNAMELEN); 13169 continue; 13170 } 13171 13172 if (strcmp(rname, name) == 0) { 13173 break; 13174 } 13175 child = ddi_get_next_sibling(child); 13176 bzero(rname, SCSI_MAXNAMELEN); 13177 } 13178 13179 kmem_free(rname, SCSI_MAXNAMELEN); 13180 13181 return (child); 13182 } 13183 13184 13185 static dev_info_t * 13186 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun) 13187 { 13188 dev_info_t *child = NULL; 13189 char *name = NULL; 13190 char *addr = NULL; 13191 13192 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13193 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13194 (void) sprintf(name, "%016"PRIx64, sasaddr); 13195 (void) sprintf(addr, "w%s,%x", name, lun); 13196 child = mptsas_find_child(pdip, addr); 13197 kmem_free(name, SCSI_MAXNAMELEN); 13198 kmem_free(addr, SCSI_MAXNAMELEN); 13199 return (child); 13200 } 13201 13202 static dev_info_t * 13203 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy) 13204 { 13205 dev_info_t *child; 13206 char *addr; 13207 13208 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13209 (void) sprintf(addr, "p%x,0", phy); 13210 child = mptsas_find_child(pdip, addr); 13211 kmem_free(addr, SCSI_MAXNAMELEN); 13212 return (child); 13213 } 13214 13215 static mdi_pathinfo_t * 13216 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy) 13217 { 13218 mdi_pathinfo_t *path; 13219 char *addr = NULL; 13220 13221 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13222 (void) sprintf(addr, "p%x,0", phy); 13223 path = mdi_pi_find(pdip, NULL, addr); 13224 kmem_free(addr, SCSI_MAXNAMELEN); 13225 return (path); 13226 } 13227 13228 static mdi_pathinfo_t * 13229 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun) 13230 { 13231 mdi_pathinfo_t *path; 13232 char *name = NULL; 13233 char *addr = NULL; 13234 13235 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13236 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13237 (void) sprintf(name, "%016"PRIx64, sasaddr); 13238 (void) sprintf(addr, "w%s,%x", name, lun); 13239 path = mdi_pi_find(parent, NULL, addr); 13240 kmem_free(name, SCSI_MAXNAMELEN); 13241 kmem_free(addr, SCSI_MAXNAMELEN); 13242 13243 return (path); 13244 } 13245 13246 static int 13247 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 13248 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 13249 { 13250 int i = 0; 13251 uchar_t *inq83 = NULL; 13252 int inq83_len1 = 0xFF; 13253 int inq83_len = 0; 13254 int rval = DDI_FAILURE; 13255 ddi_devid_t devid; 13256 char *guid = NULL; 13257 int target = ptgt->m_devhdl; 13258 mdi_pathinfo_t *pip = NULL; 13259 mptsas_t *mpt = DIP2MPT(pdip); 13260 13261 /* 13262 * For DVD/CD ROM and tape devices and optical 13263 * devices, we won't try to enumerate them under 13264 * scsi_vhci, so no need to try page83 13265 */ 13266 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT || 13267 sd_inq->inq_dtype == DTYPE_OPTICAL || 13268 sd_inq->inq_dtype == DTYPE_ESI)) 13269 goto create_lun; 13270 13271 /* 13272 * The LCA returns good SCSI status, but corrupt page 83 data the first 13273 * time it is queried. The solution is to keep trying to request page83 13274 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in 13275 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver 13276 * give up to get VPD page at this stage and fail the enumeration. 13277 */ 13278 13279 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP); 13280 13281 for (i = 0; i < mptsas_inq83_retry_timeout; i++) { 13282 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 13283 inq83_len1, &inq83_len, 1); 13284 if (rval != 0) { 13285 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 13286 "0x83 for target:%x, lun:%x failed!", target, lun); 13287 goto out; 13288 } 13289 /* 13290 * create DEVID from inquiry data 13291 */ 13292 if ((rval = ddi_devid_scsi_encode( 13293 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq, 13294 sizeof (struct scsi_inquiry), NULL, 0, inq83, 13295 (size_t)inq83_len, &devid)) == DDI_SUCCESS) { 13296 /* 13297 * extract GUID from DEVID 13298 */ 13299 guid = ddi_devid_to_guid(devid); 13300 13301 /* 13302 * Do not enable MPXIO if the strlen(guid) is greater 13303 * than MPTSAS_MAX_GUID_LEN, this constrain would be 13304 * handled by framework later. 13305 */ 13306 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) { 13307 ddi_devid_free_guid(guid); 13308 guid = NULL; 13309 if (mpt->m_mpxio_enable == TRUE) { 13310 mptsas_log(mpt, CE_NOTE, "!Target:%x, " 13311 "lun:%x doesn't have a valid GUID, " 13312 "multipathing for this drive is " 13313 "not enabled", target, lun); 13314 } 13315 } 13316 13317 /* 13318 * devid no longer needed 13319 */ 13320 ddi_devid_free(devid); 13321 break; 13322 } else if (rval == DDI_NOT_WELL_FORMED) { 13323 /* 13324 * return value of ddi_devid_scsi_encode equal to 13325 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth 13326 * to retry inquiry page 0x83 and get GUID. 13327 */ 13328 NDBG20(("Not well formed devid, retry...")); 13329 delay(1 * drv_usectohz(1000000)); 13330 continue; 13331 } else { 13332 mptsas_log(mpt, CE_WARN, "!Encode devid failed for " 13333 "path target:%x, lun:%x", target, lun); 13334 rval = DDI_FAILURE; 13335 goto create_lun; 13336 } 13337 } 13338 13339 if (i == mptsas_inq83_retry_timeout) { 13340 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout " 13341 "for path target:%x, lun:%x", target, lun); 13342 } 13343 13344 rval = DDI_FAILURE; 13345 13346 create_lun: 13347 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) { 13348 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip, 13349 ptgt, lun); 13350 } 13351 if (rval != DDI_SUCCESS) { 13352 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip, 13353 ptgt, lun); 13354 } 13355 out: 13356 if (guid != NULL) { 13357 /* 13358 * guid no longer needed 13359 */ 13360 ddi_devid_free_guid(guid); 13361 } 13362 if (inq83 != NULL) 13363 kmem_free(inq83, inq83_len1); 13364 return (rval); 13365 } 13366 13367 static int 13368 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid, 13369 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun) 13370 { 13371 int target; 13372 char *nodename = NULL; 13373 char **compatible = NULL; 13374 int ncompatible = 0; 13375 int mdi_rtn = MDI_FAILURE; 13376 int rval = DDI_FAILURE; 13377 char *old_guid = NULL; 13378 mptsas_t *mpt = DIP2MPT(pdip); 13379 char *lun_addr = NULL; 13380 char *wwn_str = NULL; 13381 char *component = NULL; 13382 uint8_t phy = 0xFF; 13383 uint64_t sas_wwn; 13384 uint32_t devinfo; 13385 13386 mutex_enter(&mpt->m_mutex); 13387 target = ptgt->m_devhdl; 13388 sas_wwn = ptgt->m_sas_wwn; 13389 devinfo = ptgt->m_deviceinfo; 13390 phy = ptgt->m_phynum; 13391 mutex_exit(&mpt->m_mutex); 13392 13393 if (sas_wwn) { 13394 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun); 13395 } else { 13396 *pip = mptsas_find_path_phy(pdip, phy); 13397 } 13398 13399 if (*pip != NULL) { 13400 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 13401 ASSERT(*lun_dip != NULL); 13402 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip, 13403 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM), 13404 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) { 13405 if (strncmp(guid, old_guid, strlen(guid)) == 0) { 13406 /* 13407 * Same path back online again. 13408 */ 13409 (void) ddi_prop_free(old_guid); 13410 if (!MDI_PI_IS_ONLINE(*pip) && 13411 !MDI_PI_IS_STANDBY(*pip)) { 13412 rval = mdi_pi_online(*pip, 0); 13413 } else { 13414 rval = DDI_SUCCESS; 13415 } 13416 if (rval != DDI_SUCCESS) { 13417 mptsas_log(mpt, CE_WARN, "path:target: " 13418 "%x, lun:%x online failed!", target, 13419 lun); 13420 *pip = NULL; 13421 *lun_dip = NULL; 13422 } 13423 return (rval); 13424 } else { 13425 /* 13426 * The GUID of the LUN has changed which maybe 13427 * because customer mapped another volume to the 13428 * same LUN. 13429 */ 13430 mptsas_log(mpt, CE_WARN, "The GUID of the " 13431 "target:%x, lun:%x was changed, maybe " 13432 "because someone mapped another volume " 13433 "to the same LUN", target, lun); 13434 (void) ddi_prop_free(old_guid); 13435 if (!MDI_PI_IS_OFFLINE(*pip)) { 13436 rval = mdi_pi_offline(*pip, 0); 13437 if (rval != MDI_SUCCESS) { 13438 mptsas_log(mpt, CE_WARN, "path:" 13439 "target:%x, lun:%x offline " 13440 "failed!", target, lun); 13441 *pip = NULL; 13442 *lun_dip = NULL; 13443 return (DDI_FAILURE); 13444 } 13445 } 13446 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) { 13447 mptsas_log(mpt, CE_WARN, "path:target:" 13448 "%x, lun:%x free failed!", target, 13449 lun); 13450 *pip = NULL; 13451 *lun_dip = NULL; 13452 return (DDI_FAILURE); 13453 } 13454 } 13455 } else { 13456 mptsas_log(mpt, CE_WARN, "Can't get client-guid " 13457 "property for path:target:%x, lun:%x", target, lun); 13458 *pip = NULL; 13459 *lun_dip = NULL; 13460 return (DDI_FAILURE); 13461 } 13462 } 13463 scsi_hba_nodename_compatible_get(inq, NULL, 13464 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible); 13465 13466 /* 13467 * if nodename can't be determined then print a message and skip it 13468 */ 13469 if (nodename == NULL) { 13470 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible " 13471 "driver for target%d lun %d dtype:0x%02x", target, lun, 13472 inq->inq_dtype); 13473 return (DDI_FAILURE); 13474 } 13475 13476 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 13477 /* The property is needed by MPAPI */ 13478 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 13479 13480 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13481 if (sas_wwn) 13482 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun); 13483 else 13484 (void) sprintf(lun_addr, "p%x,%x", phy, lun); 13485 13486 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename, 13487 guid, lun_addr, compatible, ncompatible, 13488 0, pip); 13489 if (mdi_rtn == MDI_SUCCESS) { 13490 13491 if (mdi_prop_update_string(*pip, MDI_GUID, 13492 guid) != DDI_SUCCESS) { 13493 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 13494 "create property for target %d lun %d (MDI_GUID)", 13495 target, lun); 13496 mdi_rtn = MDI_FAILURE; 13497 goto virt_create_done; 13498 } 13499 13500 if (mdi_prop_update_int(*pip, LUN_PROP, 13501 lun) != DDI_SUCCESS) { 13502 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 13503 "create property for target %d lun %d (LUN_PROP)", 13504 target, lun); 13505 mdi_rtn = MDI_FAILURE; 13506 goto virt_create_done; 13507 } 13508 if (mdi_prop_update_string_array(*pip, "compatible", 13509 compatible, ncompatible) != 13510 DDI_PROP_SUCCESS) { 13511 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 13512 "create property for target %d lun %d (COMPATIBLE)", 13513 target, lun); 13514 mdi_rtn = MDI_FAILURE; 13515 goto virt_create_done; 13516 } 13517 if (sas_wwn && (mdi_prop_update_string(*pip, 13518 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) { 13519 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 13520 "create property for target %d lun %d " 13521 "(target-port)", target, lun); 13522 mdi_rtn = MDI_FAILURE; 13523 goto virt_create_done; 13524 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip, 13525 "sata-phy", phy) != DDI_PROP_SUCCESS)) { 13526 /* 13527 * Direct attached SATA device without DeviceName 13528 */ 13529 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 13530 "create property for SAS target %d lun %d " 13531 "(sata-phy)", target, lun); 13532 mdi_rtn = NDI_FAILURE; 13533 goto virt_create_done; 13534 } 13535 13536 if (inq->inq_dtype == 0) { 13537 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 13538 /* 13539 * set obp path for pathinfo 13540 */ 13541 (void) snprintf(component, MAXPATHLEN, 13542 "disk@%s", lun_addr); 13543 13544 if (mdi_pi_pathname_obp_set(*pip, component) != 13545 DDI_SUCCESS) { 13546 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 13547 "unable to set obp-path for object %s", 13548 component); 13549 mdi_rtn = MDI_FAILURE; 13550 goto virt_create_done; 13551 } 13552 } 13553 13554 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 13555 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13556 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 13557 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip, 13558 "pm-capable", 1)) != 13559 DDI_PROP_SUCCESS) { 13560 mptsas_log(mpt, CE_WARN, "mptsas driver" 13561 "failed to create pm-capable " 13562 "property, target %d", target); 13563 mdi_rtn = MDI_FAILURE; 13564 goto virt_create_done; 13565 } 13566 } 13567 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr)); 13568 mdi_rtn = mdi_pi_online(*pip, 0); 13569 if (mdi_rtn == MDI_NOT_SUPPORTED) { 13570 mdi_rtn = MDI_FAILURE; 13571 } 13572 virt_create_done: 13573 if (*pip && mdi_rtn != MDI_SUCCESS) { 13574 (void) mdi_pi_free(*pip, 0); 13575 *pip = NULL; 13576 *lun_dip = NULL; 13577 } 13578 } 13579 13580 scsi_hba_nodename_compatible_free(nodename, compatible); 13581 if (lun_addr != NULL) { 13582 kmem_free(lun_addr, SCSI_MAXNAMELEN); 13583 } 13584 if (wwn_str != NULL) { 13585 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 13586 } 13587 if (component != NULL) { 13588 kmem_free(component, MAXPATHLEN); 13589 } 13590 13591 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 13592 } 13593 13594 static int 13595 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq, 13596 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 13597 { 13598 int target; 13599 int ndi_rtn = NDI_FAILURE; 13600 uint64_t be_sas_wwn; 13601 char *nodename = NULL; 13602 char **compatible = NULL; 13603 int ncompatible = 0; 13604 int instance = 0; 13605 mptsas_t *mpt = DIP2MPT(pdip); 13606 char *wwn_str = NULL; 13607 char *component = NULL; 13608 uint8_t phy = 0xFF; 13609 uint64_t sas_wwn; 13610 uint32_t devinfo; 13611 13612 mutex_enter(&mpt->m_mutex); 13613 target = ptgt->m_devhdl; 13614 sas_wwn = ptgt->m_sas_wwn; 13615 devinfo = ptgt->m_deviceinfo; 13616 phy = ptgt->m_phynum; 13617 mutex_exit(&mpt->m_mutex); 13618 13619 /* 13620 * generate compatible property with binding-set "mpt" 13621 */ 13622 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL, 13623 &nodename, &compatible, &ncompatible); 13624 13625 /* 13626 * if nodename can't be determined then print a message and skip it 13627 */ 13628 if (nodename == NULL) { 13629 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver " 13630 "for target %d lun %d", target, lun); 13631 return (DDI_FAILURE); 13632 } 13633 13634 ndi_rtn = ndi_devi_alloc(pdip, nodename, 13635 DEVI_SID_NODEID, lun_dip); 13636 13637 /* 13638 * if lun alloc success, set props 13639 */ 13640 if (ndi_rtn == NDI_SUCCESS) { 13641 13642 if (ndi_prop_update_int(DDI_DEV_T_NONE, 13643 *lun_dip, LUN_PROP, lun) != 13644 DDI_PROP_SUCCESS) { 13645 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 13646 "property for target %d lun %d (LUN_PROP)", 13647 target, lun); 13648 ndi_rtn = NDI_FAILURE; 13649 goto phys_create_done; 13650 } 13651 13652 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, 13653 *lun_dip, "compatible", compatible, ncompatible) 13654 != DDI_PROP_SUCCESS) { 13655 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 13656 "property for target %d lun %d (COMPATIBLE)", 13657 target, lun); 13658 ndi_rtn = NDI_FAILURE; 13659 goto phys_create_done; 13660 } 13661 13662 /* 13663 * We need the SAS WWN for non-multipath devices, so 13664 * we'll use the same property as that multipathing 13665 * devices need to present for MPAPI. If we don't have 13666 * a WWN (e.g. parallel SCSI), don't create the prop. 13667 */ 13668 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 13669 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 13670 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE, 13671 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) 13672 != DDI_PROP_SUCCESS) { 13673 mptsas_log(mpt, CE_WARN, "mptsas unable to " 13674 "create property for SAS target %d lun %d " 13675 "(target-port)", target, lun); 13676 ndi_rtn = NDI_FAILURE; 13677 goto phys_create_done; 13678 } 13679 be_sas_wwn = BE_64(sas_wwn); 13680 if (sas_wwn && ndi_prop_update_byte_array( 13681 DDI_DEV_T_NONE, *lun_dip, "port-wwn", 13682 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) { 13683 mptsas_log(mpt, CE_WARN, "mptsas unable to " 13684 "create property for SAS target %d lun %d " 13685 "(port-wwn)", target, lun); 13686 ndi_rtn = NDI_FAILURE; 13687 goto phys_create_done; 13688 } else if ((sas_wwn == 0) && (ndi_prop_update_int( 13689 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) != 13690 DDI_PROP_SUCCESS)) { 13691 /* 13692 * Direct attached SATA device without DeviceName 13693 */ 13694 mptsas_log(mpt, CE_WARN, "mptsas unable to " 13695 "create property for SAS target %d lun %d " 13696 "(sata-phy)", target, lun); 13697 ndi_rtn = NDI_FAILURE; 13698 goto phys_create_done; 13699 } 13700 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 13701 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) { 13702 mptsas_log(mpt, CE_WARN, "mptsas unable to" 13703 "create property for SAS target %d lun %d" 13704 " (SAS_PROP)", target, lun); 13705 ndi_rtn = NDI_FAILURE; 13706 goto phys_create_done; 13707 } 13708 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE, 13709 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) { 13710 mptsas_log(mpt, CE_WARN, "mptsas unable " 13711 "to create guid property for target %d " 13712 "lun %d", target, lun); 13713 ndi_rtn = NDI_FAILURE; 13714 goto phys_create_done; 13715 } 13716 13717 /* 13718 * if this is a SAS controller, and the target is a SATA 13719 * drive, set the 'pm-capable' property for sd and if on 13720 * an OPL platform, also check if this is an ATAPI 13721 * device. 13722 */ 13723 instance = ddi_get_instance(mpt->m_dip); 13724 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13725 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 13726 NDBG2(("mptsas%d: creating pm-capable property, " 13727 "target %d", instance, target)); 13728 13729 if ((ndi_prop_update_int(DDI_DEV_T_NONE, 13730 *lun_dip, "pm-capable", 1)) != 13731 DDI_PROP_SUCCESS) { 13732 mptsas_log(mpt, CE_WARN, "mptsas " 13733 "failed to create pm-capable " 13734 "property, target %d", target); 13735 ndi_rtn = NDI_FAILURE; 13736 goto phys_create_done; 13737 } 13738 13739 } 13740 13741 if (inq->inq_dtype == 0) { 13742 /* 13743 * add 'obp-path' properties for devinfo 13744 */ 13745 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 13746 if (sas_wwn) { 13747 (void) snprintf(component, MAXPATHLEN, 13748 "disk@w%s,%x", wwn_str, lun); 13749 } else { 13750 (void) snprintf(component, MAXPATHLEN, 13751 "disk@p%x,%x", phy, lun); 13752 } 13753 if (ddi_pathname_obp_set(*lun_dip, component) 13754 != DDI_SUCCESS) { 13755 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 13756 "unable to set obp-path for SAS " 13757 "object %s", component); 13758 ndi_rtn = NDI_FAILURE; 13759 goto phys_create_done; 13760 } 13761 } 13762 13763 phys_create_done: 13764 /* 13765 * If props were setup ok, online the lun 13766 */ 13767 if (ndi_rtn == NDI_SUCCESS) { 13768 /* 13769 * Try to online the new node 13770 */ 13771 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH); 13772 } 13773 13774 /* 13775 * If success set rtn flag, else unwire alloc'd lun 13776 */ 13777 if (ndi_rtn != NDI_SUCCESS) { 13778 NDBG12(("mptsas driver unable to online " 13779 "target %d lun %d", target, lun)); 13780 ndi_prop_remove_all(*lun_dip); 13781 (void) ndi_devi_free(*lun_dip); 13782 *lun_dip = NULL; 13783 } 13784 } 13785 13786 scsi_hba_nodename_compatible_free(nodename, compatible); 13787 13788 if (wwn_str != NULL) { 13789 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 13790 } 13791 if (component != NULL) { 13792 kmem_free(component, MAXPATHLEN); 13793 } 13794 13795 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 13796 } 13797 13798 static int 13799 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn) 13800 { 13801 mptsas_t *mpt = DIP2MPT(pdip); 13802 struct smp_device smp_sd; 13803 13804 /* XXX An HBA driver should not be allocating an smp_device. */ 13805 bzero(&smp_sd, sizeof (struct smp_device)); 13806 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran; 13807 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE); 13808 13809 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS) 13810 return (NDI_FAILURE); 13811 return (NDI_SUCCESS); 13812 } 13813 13814 static int 13815 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip) 13816 { 13817 mptsas_t *mpt = DIP2MPT(pdip); 13818 mptsas_smp_t *psmp = NULL; 13819 int rval; 13820 int phymask; 13821 13822 /* 13823 * Get the physical port associated to the iport 13824 * PHYMASK TODO 13825 */ 13826 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 13827 "phymask", 0); 13828 /* 13829 * Find the smp node in hash table with specified sas address and 13830 * physical port 13831 */ 13832 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn); 13833 if (psmp == NULL) { 13834 return (DDI_FAILURE); 13835 } 13836 13837 rval = mptsas_online_smp(pdip, psmp, smp_dip); 13838 13839 return (rval); 13840 } 13841 13842 static int 13843 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 13844 dev_info_t **smp_dip) 13845 { 13846 char wwn_str[MPTSAS_WWN_STRLEN]; 13847 int ndi_rtn = NDI_FAILURE; 13848 mptsas_t *mpt = DIP2MPT(pdip); 13849 13850 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_sasaddr); 13851 13852 /* 13853 * Probe smp device, prevent the node of removed device from being 13854 * configured succesfully 13855 */ 13856 if (mptsas_probe_smp(pdip, smp_node->m_sasaddr) != NDI_SUCCESS) { 13857 return (DDI_FAILURE); 13858 } 13859 13860 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) { 13861 return (DDI_SUCCESS); 13862 } 13863 13864 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip); 13865 13866 /* 13867 * if lun alloc success, set props 13868 */ 13869 if (ndi_rtn == NDI_SUCCESS) { 13870 /* 13871 * Set the flavor of the child to be SMP flavored 13872 */ 13873 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP); 13874 13875 if (ndi_prop_update_string(DDI_DEV_T_NONE, 13876 *smp_dip, SMP_WWN, wwn_str) != 13877 DDI_PROP_SUCCESS) { 13878 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 13879 "property for smp device %s (sas_wwn)", 13880 wwn_str); 13881 ndi_rtn = NDI_FAILURE; 13882 goto smp_create_done; 13883 } 13884 13885 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 13886 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) { 13887 mptsas_log(mpt, CE_WARN, "mptsas unable to " 13888 "create property for SMP %s (SMP_PROP) ", 13889 wwn_str); 13890 ndi_rtn = NDI_FAILURE; 13891 goto smp_create_done; 13892 } 13893 13894 smp_create_done: 13895 /* 13896 * If props were setup ok, online the lun 13897 */ 13898 if (ndi_rtn == NDI_SUCCESS) { 13899 /* 13900 * Try to online the new node 13901 */ 13902 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH); 13903 } 13904 13905 /* 13906 * If success set rtn flag, else unwire alloc'd lun 13907 */ 13908 if (ndi_rtn != NDI_SUCCESS) { 13909 NDBG12(("mptsas unable to online " 13910 "SMP target %s", wwn_str)); 13911 ndi_prop_remove_all(*smp_dip); 13912 (void) ndi_devi_free(*smp_dip); 13913 } 13914 } 13915 13916 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 13917 } 13918 13919 /* smp transport routine */ 13920 static int mptsas_smp_start(struct smp_pkt *smp_pkt) 13921 { 13922 uint64_t wwn; 13923 Mpi2SmpPassthroughRequest_t req; 13924 Mpi2SmpPassthroughReply_t rep; 13925 uint32_t direction = 0; 13926 mptsas_t *mpt; 13927 int ret; 13928 uint64_t tmp64; 13929 13930 mpt = (mptsas_t *)smp_pkt->smp_pkt_address-> 13931 smp_a_hba_tran->smp_tran_hba_private; 13932 13933 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE); 13934 /* 13935 * Need to compose a SMP request message 13936 * and call mptsas_do_passthru() function 13937 */ 13938 bzero(&req, sizeof (req)); 13939 bzero(&rep, sizeof (rep)); 13940 req.PassthroughFlags = 0; 13941 req.PhysicalPort = 0xff; 13942 req.ChainOffset = 0; 13943 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH; 13944 13945 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) { 13946 smp_pkt->smp_pkt_reason = ERANGE; 13947 return (DDI_FAILURE); 13948 } 13949 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4)); 13950 13951 req.MsgFlags = 0; 13952 tmp64 = LE_64(wwn); 13953 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE); 13954 if (smp_pkt->smp_pkt_rspsize > 0) { 13955 direction |= MPTSAS_PASS_THRU_DIRECTION_READ; 13956 } 13957 if (smp_pkt->smp_pkt_reqsize > 0) { 13958 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE; 13959 } 13960 13961 mutex_enter(&mpt->m_mutex); 13962 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, 13963 (uint8_t *)smp_pkt->smp_pkt_rsp, 13964 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep), 13965 smp_pkt->smp_pkt_rspsize - 4, direction, 13966 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4, 13967 smp_pkt->smp_pkt_timeout, FKIOCTL); 13968 mutex_exit(&mpt->m_mutex); 13969 if (ret != 0) { 13970 cmn_err(CE_WARN, "smp_start do passthru error %d", ret); 13971 smp_pkt->smp_pkt_reason = (uchar_t)(ret); 13972 return (DDI_FAILURE); 13973 } 13974 /* do passthrough success, check the smp status */ 13975 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 13976 switch (LE_16(rep.IOCStatus)) { 13977 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 13978 smp_pkt->smp_pkt_reason = ENODEV; 13979 break; 13980 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 13981 smp_pkt->smp_pkt_reason = EOVERFLOW; 13982 break; 13983 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 13984 smp_pkt->smp_pkt_reason = EIO; 13985 break; 13986 default: 13987 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc" 13988 "status:%x", LE_16(rep.IOCStatus)); 13989 smp_pkt->smp_pkt_reason = EIO; 13990 break; 13991 } 13992 return (DDI_FAILURE); 13993 } 13994 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) { 13995 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x", 13996 rep.SASStatus); 13997 smp_pkt->smp_pkt_reason = EIO; 13998 return (DDI_FAILURE); 13999 } 14000 14001 return (DDI_SUCCESS); 14002 } 14003 14004 static void 14005 mptsas_idle_pm(void *arg) 14006 { 14007 mptsas_t *mpt = arg; 14008 14009 (void) pm_idle_component(mpt->m_dip, 0); 14010 mutex_enter(&mpt->m_mutex); 14011 mpt->m_pm_timeid = 0; 14012 mutex_exit(&mpt->m_mutex); 14013 } 14014 14015 /* 14016 * If we didn't get a match, we need to get sas page0 for each device, and 14017 * untill we get a match. If failed, return NULL 14018 * TODO should be implemented similar to mptsas_wwid_to_ptgt? 14019 */ 14020 static mptsas_target_t * 14021 mptsas_phy_to_tgt(dev_info_t *pdip, uint8_t phy) 14022 { 14023 int i, j = 0; 14024 int rval = 0; 14025 uint16_t cur_handle; 14026 uint32_t page_address; 14027 mptsas_target_t *ptgt = NULL; 14028 mptsas_t *mpt = DIP2MPT(pdip); 14029 int phymask; 14030 14031 /* 14032 * Get the physical port associated to the iport 14033 */ 14034 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14035 "phymask", 0); 14036 14037 if (phymask == 0) 14038 return (NULL); 14039 14040 /* 14041 * PHY named device must be direct attached and attaches to 14042 * narrow port, if the iport is not parent of the device which 14043 * we are looking for. 14044 */ 14045 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 14046 if ((1 << i) & phymask) 14047 j++; 14048 } 14049 14050 if (j > 1) 14051 return (NULL); 14052 14053 /* 14054 * Must be a narrow port and single device attached to the narrow port 14055 * So the physical port num of device which is equal to the iport's 14056 * port num is the device what we are looking for. 14057 */ 14058 14059 if (mpt->m_phy_info[phy].phy_mask != phymask) 14060 return (NULL); 14061 14062 mutex_enter(&mpt->m_mutex); 14063 14064 ptgt = (mptsas_target_t *)mptsas_hash_traverse(&mpt->m_active->m_tgttbl, 14065 MPTSAS_HASH_FIRST); 14066 while (ptgt != NULL) { 14067 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) { 14068 mutex_exit(&mpt->m_mutex); 14069 return (ptgt); 14070 } 14071 14072 ptgt = (mptsas_target_t *)mptsas_hash_traverse( 14073 &mpt->m_active->m_tgttbl, MPTSAS_HASH_NEXT); 14074 } 14075 14076 if (mpt->m_done_traverse_dev) { 14077 mutex_exit(&mpt->m_mutex); 14078 return (NULL); 14079 } 14080 14081 /* If didn't get a match, come here */ 14082 cur_handle = mpt->m_dev_handle; 14083 for (; ; ) { 14084 ptgt = NULL; 14085 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 14086 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle; 14087 rval = mptsas_get_target_device_info(mpt, page_address, 14088 &cur_handle, &ptgt); 14089 if ((rval == DEV_INFO_FAIL_PAGE0) || 14090 (rval == DEV_INFO_FAIL_ALLOC)) { 14091 break; 14092 } 14093 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 14094 (rval == DEV_INFO_PHYS_DISK)) { 14095 continue; 14096 } 14097 mpt->m_dev_handle = cur_handle; 14098 14099 if ((ptgt->m_sas_wwn == 0) && (ptgt->m_phynum == phy)) { 14100 break; 14101 } 14102 } 14103 14104 mutex_exit(&mpt->m_mutex); 14105 return (ptgt); 14106 } 14107 14108 /* 14109 * The ptgt->m_sas_wwn contains the wwid for each disk. 14110 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid 14111 * If we didn't get a match, we need to get sas page0 for each device, and 14112 * untill we get a match 14113 * If failed, return NULL 14114 */ 14115 static mptsas_target_t * 14116 mptsas_wwid_to_ptgt(mptsas_t *mpt, int phymask, uint64_t wwid) 14117 { 14118 int rval = 0; 14119 uint16_t cur_handle; 14120 uint32_t page_address; 14121 mptsas_target_t *tmp_tgt = NULL; 14122 14123 mutex_enter(&mpt->m_mutex); 14124 tmp_tgt = (struct mptsas_target *)mptsas_hash_search( 14125 &mpt->m_active->m_tgttbl, wwid, phymask); 14126 if (tmp_tgt != NULL) { 14127 mutex_exit(&mpt->m_mutex); 14128 return (tmp_tgt); 14129 } 14130 14131 if (phymask == 0) { 14132 /* 14133 * It's IR volume 14134 */ 14135 rval = mptsas_get_raid_info(mpt); 14136 if (rval) { 14137 tmp_tgt = (struct mptsas_target *)mptsas_hash_search( 14138 &mpt->m_active->m_tgttbl, wwid, phymask); 14139 } 14140 mutex_exit(&mpt->m_mutex); 14141 return (tmp_tgt); 14142 } 14143 14144 if (mpt->m_done_traverse_dev) { 14145 mutex_exit(&mpt->m_mutex); 14146 return (NULL); 14147 } 14148 14149 /* If didn't get a match, come here */ 14150 cur_handle = mpt->m_dev_handle; 14151 for (; ; ) { 14152 tmp_tgt = NULL; 14153 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 14154 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle; 14155 rval = mptsas_get_target_device_info(mpt, page_address, 14156 &cur_handle, &tmp_tgt); 14157 if ((rval == DEV_INFO_FAIL_PAGE0) || 14158 (rval == DEV_INFO_FAIL_ALLOC)) { 14159 tmp_tgt = NULL; 14160 break; 14161 } 14162 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 14163 (rval == DEV_INFO_PHYS_DISK)) { 14164 continue; 14165 } 14166 mpt->m_dev_handle = cur_handle; 14167 if ((tmp_tgt->m_sas_wwn) && (tmp_tgt->m_sas_wwn == wwid) && 14168 (tmp_tgt->m_phymask == phymask)) { 14169 break; 14170 } 14171 } 14172 14173 mutex_exit(&mpt->m_mutex); 14174 return (tmp_tgt); 14175 } 14176 14177 static mptsas_smp_t * 14178 mptsas_wwid_to_psmp(mptsas_t *mpt, int phymask, uint64_t wwid) 14179 { 14180 int rval = 0; 14181 uint16_t cur_handle; 14182 uint32_t page_address; 14183 mptsas_smp_t smp_node, *psmp = NULL; 14184 14185 mutex_enter(&mpt->m_mutex); 14186 psmp = (struct mptsas_smp *)mptsas_hash_search(&mpt->m_active->m_smptbl, 14187 wwid, phymask); 14188 if (psmp != NULL) { 14189 mutex_exit(&mpt->m_mutex); 14190 return (psmp); 14191 } 14192 14193 if (mpt->m_done_traverse_smp) { 14194 mutex_exit(&mpt->m_mutex); 14195 return (NULL); 14196 } 14197 14198 /* If didn't get a match, come here */ 14199 cur_handle = mpt->m_smp_devhdl; 14200 for (; ; ) { 14201 psmp = NULL; 14202 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 14203 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle; 14204 rval = mptsas_get_sas_expander_page0(mpt, page_address, 14205 &smp_node); 14206 if (rval != DDI_SUCCESS) { 14207 break; 14208 } 14209 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl; 14210 psmp = mptsas_smp_alloc(&mpt->m_active->m_smptbl, &smp_node); 14211 ASSERT(psmp); 14212 if ((psmp->m_sasaddr) && (psmp->m_sasaddr == wwid) && 14213 (psmp->m_phymask == phymask)) { 14214 break; 14215 } 14216 } 14217 14218 mutex_exit(&mpt->m_mutex); 14219 return (psmp); 14220 } 14221 14222 /* helper functions using hash */ 14223 14224 /* 14225 * Can't have duplicate entries for same devhdl, 14226 * if there are invalid entries, the devhdl should be set to 0xffff 14227 */ 14228 static void * 14229 mptsas_search_by_devhdl(mptsas_hash_table_t *hashtab, uint16_t devhdl) 14230 { 14231 mptsas_hash_data_t *data; 14232 14233 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_FIRST); 14234 while (data != NULL) { 14235 if (data->devhdl == devhdl) { 14236 break; 14237 } 14238 data = mptsas_hash_traverse(hashtab, MPTSAS_HASH_NEXT); 14239 } 14240 return (data); 14241 } 14242 14243 mptsas_target_t * 14244 mptsas_tgt_alloc(mptsas_hash_table_t *hashtab, uint16_t devhdl, uint64_t wwid, 14245 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum) 14246 { 14247 mptsas_target_t *tmp_tgt = NULL; 14248 14249 tmp_tgt = mptsas_hash_search(hashtab, wwid, phymask); 14250 if (tmp_tgt != NULL) { 14251 NDBG20(("Hash item already exist")); 14252 tmp_tgt->m_deviceinfo = devinfo; 14253 tmp_tgt->m_devhdl = devhdl; 14254 return (tmp_tgt); 14255 } 14256 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP); 14257 if (tmp_tgt == NULL) { 14258 cmn_err(CE_WARN, "Fatal, allocated tgt failed"); 14259 return (NULL); 14260 } 14261 tmp_tgt->m_devhdl = devhdl; 14262 tmp_tgt->m_sas_wwn = wwid; 14263 tmp_tgt->m_deviceinfo = devinfo; 14264 tmp_tgt->m_phymask = phymask; 14265 tmp_tgt->m_phynum = phynum; 14266 /* Initialized the tgt structure */ 14267 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 14268 tmp_tgt->m_qfull_retry_interval = 14269 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 14270 tmp_tgt->m_t_throttle = MAX_THROTTLE; 14271 14272 mptsas_hash_add(hashtab, tmp_tgt); 14273 14274 return (tmp_tgt); 14275 } 14276 14277 static void 14278 mptsas_tgt_free(mptsas_hash_table_t *hashtab, uint64_t wwid, 14279 mptsas_phymask_t phymask) 14280 { 14281 mptsas_target_t *tmp_tgt; 14282 tmp_tgt = mptsas_hash_rem(hashtab, wwid, phymask); 14283 if (tmp_tgt == NULL) { 14284 cmn_err(CE_WARN, "Tgt not found, nothing to free"); 14285 } else { 14286 kmem_free(tmp_tgt, sizeof (struct mptsas_target)); 14287 } 14288 } 14289 14290 /* 14291 * Return the entry in the hash table 14292 */ 14293 static mptsas_smp_t * 14294 mptsas_smp_alloc(mptsas_hash_table_t *hashtab, mptsas_smp_t *data) 14295 { 14296 uint64_t key1 = data->m_sasaddr; 14297 mptsas_phymask_t key2 = data->m_phymask; 14298 mptsas_smp_t *ret_data; 14299 14300 ret_data = mptsas_hash_search(hashtab, key1, key2); 14301 if (ret_data != NULL) { 14302 bcopy(data, ret_data, sizeof (mptsas_smp_t)); 14303 return (ret_data); 14304 } 14305 14306 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP); 14307 bcopy(data, ret_data, sizeof (mptsas_smp_t)); 14308 mptsas_hash_add(hashtab, ret_data); 14309 return (ret_data); 14310 } 14311 14312 static void 14313 mptsas_smp_free(mptsas_hash_table_t *hashtab, uint64_t wwid, 14314 mptsas_phymask_t phymask) 14315 { 14316 mptsas_smp_t *tmp_smp; 14317 tmp_smp = mptsas_hash_rem(hashtab, wwid, phymask); 14318 if (tmp_smp == NULL) { 14319 cmn_err(CE_WARN, "Smp element not found, nothing to free"); 14320 } else { 14321 kmem_free(tmp_smp, sizeof (struct mptsas_smp)); 14322 } 14323 } 14324 14325 /* 14326 * Hash operation functions 14327 * key1 is the sas_wwn, key2 is the phymask 14328 */ 14329 static void 14330 mptsas_hash_init(mptsas_hash_table_t *hashtab) 14331 { 14332 if (hashtab == NULL) { 14333 return; 14334 } 14335 bzero(hashtab->head, sizeof (mptsas_hash_node_t) * 14336 MPTSAS_HASH_ARRAY_SIZE); 14337 hashtab->cur = NULL; 14338 hashtab->line = 0; 14339 } 14340 14341 static void 14342 mptsas_hash_uninit(mptsas_hash_table_t *hashtab, size_t datalen) 14343 { 14344 uint16_t line = 0; 14345 mptsas_hash_node_t *cur = NULL, *last = NULL; 14346 14347 if (hashtab == NULL) { 14348 return; 14349 } 14350 for (line = 0; line < MPTSAS_HASH_ARRAY_SIZE; line++) { 14351 cur = hashtab->head[line]; 14352 while (cur != NULL) { 14353 last = cur; 14354 cur = cur->next; 14355 kmem_free(last->data, datalen); 14356 kmem_free(last, sizeof (mptsas_hash_node_t)); 14357 } 14358 } 14359 } 14360 14361 /* 14362 * You must guarantee the element doesn't exist in the hash table 14363 * before you call mptsas_hash_add() 14364 */ 14365 static void 14366 mptsas_hash_add(mptsas_hash_table_t *hashtab, void *data) 14367 { 14368 uint64_t key1 = ((mptsas_hash_data_t *)data)->key1; 14369 mptsas_phymask_t key2 = ((mptsas_hash_data_t *)data)->key2; 14370 mptsas_hash_node_t **head = NULL; 14371 mptsas_hash_node_t *node = NULL; 14372 14373 if (hashtab == NULL) { 14374 return; 14375 } 14376 ASSERT(mptsas_hash_search(hashtab, key1, key2) == NULL); 14377 node = kmem_zalloc(sizeof (mptsas_hash_node_t), KM_NOSLEEP); 14378 node->data = data; 14379 14380 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]); 14381 if (*head == NULL) { 14382 *head = node; 14383 } else { 14384 node->next = *head; 14385 *head = node; 14386 } 14387 } 14388 14389 static void * 14390 mptsas_hash_rem(mptsas_hash_table_t *hashtab, uint64_t key1, 14391 mptsas_phymask_t key2) 14392 { 14393 mptsas_hash_node_t **head = NULL; 14394 mptsas_hash_node_t *last = NULL, *cur = NULL; 14395 mptsas_hash_data_t *data; 14396 if (hashtab == NULL) { 14397 return (NULL); 14398 } 14399 head = &(hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]); 14400 cur = *head; 14401 while (cur != NULL) { 14402 data = cur->data; 14403 if ((data->key1 == key1) && (data->key2 == key2)) { 14404 if (last == NULL) { 14405 (*head) = cur->next; 14406 } else { 14407 last->next = cur->next; 14408 } 14409 kmem_free(cur, sizeof (mptsas_hash_node_t)); 14410 return (data); 14411 } else { 14412 last = cur; 14413 cur = cur->next; 14414 } 14415 } 14416 return (NULL); 14417 } 14418 14419 static void * 14420 mptsas_hash_search(mptsas_hash_table_t *hashtab, uint64_t key1, 14421 mptsas_phymask_t key2) 14422 { 14423 mptsas_hash_node_t *cur = NULL; 14424 mptsas_hash_data_t *data; 14425 if (hashtab == NULL) { 14426 return (NULL); 14427 } 14428 cur = hashtab->head[key1 % MPTSAS_HASH_ARRAY_SIZE]; 14429 while (cur != NULL) { 14430 data = cur->data; 14431 if ((data->key1 == key1) && (data->key2 == key2)) { 14432 return (data); 14433 } else { 14434 cur = cur->next; 14435 } 14436 } 14437 return (NULL); 14438 } 14439 14440 static void * 14441 mptsas_hash_traverse(mptsas_hash_table_t *hashtab, int pos) 14442 { 14443 mptsas_hash_node_t *this = NULL; 14444 14445 if (hashtab == NULL) { 14446 return (NULL); 14447 } 14448 14449 if (pos == MPTSAS_HASH_FIRST) { 14450 hashtab->line = 0; 14451 hashtab->cur = NULL; 14452 this = hashtab->head[0]; 14453 } else { 14454 if (hashtab->cur == NULL) { 14455 return (NULL); 14456 } else { 14457 this = hashtab->cur->next; 14458 } 14459 } 14460 14461 while (this == NULL) { 14462 hashtab->line++; 14463 if (hashtab->line >= MPTSAS_HASH_ARRAY_SIZE) { 14464 /* the traverse reaches the end */ 14465 hashtab->cur = NULL; 14466 return (NULL); 14467 } else { 14468 this = hashtab->head[hashtab->line]; 14469 } 14470 } 14471 hashtab->cur = this; 14472 return (this->data); 14473 } 14474