1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 30 31 /* 32 * SiliconImage 3124/3132 sata controller driver 33 */ 34 35 /* 36 * 37 * 38 * Few Design notes 39 * 40 * 41 * I. General notes 42 * 43 * Even though the driver is named as si3124, it is actually meant to 44 * work with both 3124 and 3132 controllers. 45 * 46 * The current file si3124.c is the main driver code. The si3124reg.h 47 * holds the register definitions from SiI 3124/3132 data sheets. The 48 * si3124var.h holds the driver specific definitions which are not 49 * directly derived from data sheets. 50 * 51 * 52 * II. Data structures 53 * 54 * si_ctl_state_t: This holds the driver private information for each 55 * controller instance. Each of the sata ports within a single 56 * controller are represented by si_port_state_t. The 57 * sictl_global_acc_handle and sictl_global_address map the 58 * controller-wide global register space and are derived from pci 59 * BAR 0. The sictl_port_acc_handle and sictl_port_addr map the 60 * per-port register space and are derived from pci BAR 1. 61 * 62 * si_port_state_t: This holds the per port information. The siport_mutex 63 * holds the per port mutex. The siport_pending_tags is the bit mask of 64 * commands posted to controller. The siport_slot_pkts[] holds the 65 * pending sata packets. The siport_port_type holds the device type 66 * connected directly to the port while the siport_portmult_state 67 * holds the similar information for the devices behind a port 68 * multiplier. 69 * 70 * si_prb_t: This contains the PRB being posted to the controller. 71 * The two SGE entries contained within si_prb_t itself are not 72 * really used to hold any scatter gather entries. The scatter gather 73 * list is maintained external to PRB and is linked from one 74 * of the contained SGEs inside the PRB. For atapi devices, the 75 * first contained SGE holds the PACKET and second contained 76 * SGE holds the link to an external SGT. For non-atapi devices, 77 * the first contained SGE works as link to external SGT while 78 * second SGE is blank. 79 * 80 * external SGT tables: The external SGT tables pointed to from 81 * within si_prb_t are actually abstracted as si_sgblock_t. Each 82 * si_sgblock_t contains SI_MAX_SGT_TABLES_PER_PRB number of 83 * SGT tables linked in a chain. Currently this max value of 84 * SGT tables per block is hard coded as 10 which translates 85 * to a maximum of 31 dma cookies per single dma transfer. 86 * 87 * 88 * III. Driver operation 89 * 90 * Command Issuing: We use the "indirect method of command issuance". The 91 * PRB contains the command [and atapi PACKET] and a link to the 92 * external SGT chain. We write the physical address of the PRB into 93 * command activation register. There are 31 command slots for 94 * each port. After posting a command, we remember the posted slot & 95 * the sata packet in siport_pending_tags & siport_slot_pkts[] 96 * respectively. 97 * 98 * Command completion: On a successful completion, intr_command_complete() 99 * receives the control. The slot_status register holds the outstanding 100 * commands. Any reading of slot_status register automatically clears 101 * the interrupt. By comparing the slot_status register contents with 102 * per port siport_pending_tags, we determine which of the previously 103 * posted commands have finished. 104 * 105 * Timeout handling: Every 5 seconds, the watchdog handler scans thru the 106 * pending packets. The satapkt->satapkt_hba_driver_private field is 107 * overloaded with the count of watchdog cycles a packet has survived. 108 * If a packet has not completed within satapkt->satapkt_time, it is 109 * failed with error code of SATA_PKT_TIMEOUT. There is one watchdog 110 * handler running for each instance of controller. 111 * 112 * Error handling: For 3124, whenever any single command has encountered 113 * an error, the whole port execution completely stalls; there is no 114 * way of canceling or aborting the particular failed command. If 115 * the port is connected to a port multiplier, we can however RESUME 116 * other non-error devices connected to the port multiplier. 117 * The only way to recover the failed commands is to either initialize 118 * the port or reset the port/device. Both port initialize and reset 119 * operations result in discarding any of pending commands on the port. 120 * All such discarded commands are sent up to framework with PKT_RESET 121 * satapkt_reason. The assumption is that framework [and sd] would 122 * retry these commands again. The failed command itself however is 123 * sent up with PKT_DEV_ERROR. 124 * 125 * Here is the implementation strategy based on SiliconImage email 126 * regarding how they handle the errors for their Windows driver: 127 * 128 * a) for DEVICEERROR: 129 * If the port is connected to port multiplier, then 130 * 1) Resume the port 131 * 2) Wait for all the non-failed commands to complete 132 * 3) Perform a Port Initialize 133 * 134 * If the port is not connected to port multiplier, issue 135 * a Port Initialize. 136 * 137 * b) for SDBERROR: [SDBERROR means failed command is an NCQ command] 138 * Handle exactly like DEVICEERROR handling. 139 * After the Port Initialize done, do a Read Log Extended. 140 * 141 * c) for SENDFISERROR: 142 * If the port is connected to port multiplier, then 143 * 1) Resume the port 144 * 2) Wait for all the non-failed commands to complete 145 * 3) Perform a Port Initialize 146 * 147 * If the port is not connected to port multiplier, issue 148 * a Device Reset. 149 * 150 * d) for DATAFISERROR: 151 * If the port was executing an NCQ command, issue a Device 152 * Reset. 153 * 154 * Otherwise, follow the same error recovery as DEVICEERROR. 155 * 156 * e) for any other error, simply issue a Device Reset. 157 * 158 * To synchronize the interactions between various control flows (e.g. 159 * error recovery, timeout handling, si_poll_timeout, incoming flow 160 * from framework etc.), the following precautions are taken care of: 161 * a) During mopping_in_progress, no more commands are 162 * accepted from the framework. 163 * 164 * b) While draining the port multiplier commands, we should 165 * handle the possibility of any of the other waited commands 166 * failing (possibly with a different error code) 167 * 168 * Atapi handling: For atapi devices, we use the first SGE within the PRB 169 * to fill the scsi cdb while the second SGE points to external SGT. 170 * 171 * Queuing: Queue management is achieved external to the driver inside sd. 172 * Based on sata_hba_tran->qdepth and IDENTIFY data, the framework 173 * enables or disables the queuing. The qdepth for si3124 is 31 174 * commands. 175 * 176 * Port Multiplier: Enumeration of port multiplier is handled during the 177 * controller initialization and also during the a hotplug operation. 178 * Current logic takes care of situation where a port multiplier 179 * is hotplugged into a port which had a cdisk connected previously 180 * and vice versa. 181 * 182 * Register poll timeouts: Currently most of poll timeouts on register 183 * reads is set to 0.5 seconds except for a value of 10 seconds 184 * while reading the device signature. [Such a big timeout values 185 * for device signature were found needed during cold reboots 186 * for devices behind port multiplier]. 187 * 188 * 189 * IV. Known Issues 190 * 191 * 1) Currently the atapi packet length is hard coded to 12 bytes 192 * This is wrong. The framework should determine it just like they 193 * determine ad_cdb_len in legacy atapi.c. It should even reject 194 * init_pkt() for greater CDB lengths. See atapi.c. Revisit this 195 * in 2nd phase of framework project. 196 * 197 * 2) Do real REQUEST SENSE command instead of faking for ATAPI case. 198 * 199 */ 200 201 202 #include <sys/note.h> 203 #include <sys/scsi/scsi.h> 204 #include <sys/pci.h> 205 #include <sys/sata/sata_hba.h> 206 #include <sys/sata/adapters/si3124/si3124reg.h> 207 #include <sys/sata/adapters/si3124/si3124var.h> 208 209 /* 210 * Function prototypes for driver entry points 211 */ 212 static int si_attach(dev_info_t *, ddi_attach_cmd_t); 213 static int si_detach(dev_info_t *, ddi_detach_cmd_t); 214 static int si_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 215 static int si_power(dev_info_t *, int, int); 216 217 /* 218 * Function prototypes for SATA Framework interfaces 219 */ 220 static int si_register_sata_hba_tran(si_ctl_state_t *); 221 static int si_unregister_sata_hba_tran(si_ctl_state_t *); 222 223 static int si_tran_probe_port(dev_info_t *, sata_device_t *); 224 static int si_tran_start(dev_info_t *, sata_pkt_t *spkt); 225 static int si_tran_abort(dev_info_t *, sata_pkt_t *, int); 226 static int si_tran_reset_dport(dev_info_t *, sata_device_t *); 227 static int si_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 228 static int si_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 229 230 /* 231 * Local function prototypes 232 */ 233 234 static int si_alloc_port_state(si_ctl_state_t *, int); 235 static void si_dealloc_port_state(si_ctl_state_t *, int); 236 static int si_alloc_sgbpool(si_ctl_state_t *, int); 237 static void si_dealloc_sgbpool(si_ctl_state_t *, int); 238 static int si_alloc_prbpool(si_ctl_state_t *, int); 239 static void si_dealloc_prbpool(si_ctl_state_t *, int); 240 241 static void si_find_dev_signature(si_ctl_state_t *, si_port_state_t *, 242 int, int); 243 static void si_poll_cmd(si_ctl_state_t *, si_port_state_t *, int, int, 244 sata_pkt_t *); 245 static int si_claim_free_slot(si_ctl_state_t *, si_port_state_t *, int); 246 static int si_deliver_satapkt(si_ctl_state_t *, si_port_state_t *, int, 247 sata_pkt_t *); 248 249 static int si_initialize_controller(si_ctl_state_t *); 250 static void si_deinititalize_controller(si_ctl_state_t *); 251 static void si_init_port(si_ctl_state_t *, int); 252 static int si_enumerate_port_multiplier(si_ctl_state_t *, 253 si_port_state_t *, int); 254 static int si_read_portmult_reg(si_ctl_state_t *, si_port_state_t *, 255 int, int, int, uint32_t *); 256 static int si_write_portmult_reg(si_ctl_state_t *, si_port_state_t *, 257 int, int, int, uint32_t); 258 static void si_set_sense_data(sata_pkt_t *, int); 259 260 static uint_t si_intr(caddr_t, caddr_t); 261 static int si_intr_command_complete(si_ctl_state_t *, 262 si_port_state_t *, int); 263 static int si_intr_command_error(si_ctl_state_t *, 264 si_port_state_t *, int); 265 static void si_error_recovery_DEVICEERROR(si_ctl_state_t *, 266 si_port_state_t *, int); 267 static void si_error_recovery_SDBERROR(si_ctl_state_t *, 268 si_port_state_t *, int); 269 static void si_error_recovery_DATAFISERROR(si_ctl_state_t *, 270 si_port_state_t *, int); 271 static void si_error_recovery_SENDFISERROR(si_ctl_state_t *, 272 si_port_state_t *, int); 273 static void si_error_recovery_default(si_ctl_state_t *, 274 si_port_state_t *, int); 275 static uint8_t si_read_log_ext(si_ctl_state_t *, 276 si_port_state_t *si_portp, int); 277 static void si_log_error_message(si_ctl_state_t *, int, uint32_t); 278 static int si_intr_port_ready(si_ctl_state_t *, si_port_state_t *, int); 279 static int si_intr_pwr_change(si_ctl_state_t *, si_port_state_t *, int); 280 static int si_intr_phy_ready_change(si_ctl_state_t *, si_port_state_t *, int); 281 static int si_intr_comwake_rcvd(si_ctl_state_t *, si_port_state_t *, int); 282 static int si_intr_unrecognised_fis(si_ctl_state_t *, si_port_state_t *, int); 283 static int si_intr_dev_xchanged(si_ctl_state_t *, si_port_state_t *, int); 284 static int si_intr_decode_err_threshold(si_ctl_state_t *, 285 si_port_state_t *, int); 286 static int si_intr_crc_err_threshold(si_ctl_state_t *, si_port_state_t *, int); 287 static int si_intr_handshake_err_threshold(si_ctl_state_t *, 288 si_port_state_t *, int); 289 static int si_intr_set_devbits_notify(si_ctl_state_t *, si_port_state_t *, int); 290 static void si_handle_attention_raised(si_ctl_state_t *, 291 si_port_state_t *, int); 292 293 static void si_enable_port_interrupts(si_ctl_state_t *, int); 294 static void si_enable_all_interrupts(si_ctl_state_t *); 295 static void si_disable_port_interrupts(si_ctl_state_t *, int); 296 static void si_disable_all_interrupts(si_ctl_state_t *); 297 static void fill_dev_sregisters(si_ctl_state_t *, int, sata_device_t *); 298 static int si_add_legacy_intrs(si_ctl_state_t *); 299 static int si_add_msi_intrs(si_ctl_state_t *); 300 static void si_rem_intrs(si_ctl_state_t *); 301 302 static int si_reset_dport_wait_till_ready(si_ctl_state_t *, 303 si_port_state_t *, int, int); 304 static int si_initialize_port_wait_till_ready(si_ctl_state_t *, int); 305 306 static void si_timeout_pkts(si_ctl_state_t *, si_port_state_t *, int, uint32_t); 307 static void si_watchdog_handler(si_ctl_state_t *); 308 309 static void si_log(si_ctl_state_t *, uint_t, char *, ...); 310 311 312 /* 313 * DMA attributes for the data buffer 314 */ 315 316 static ddi_dma_attr_t buffer_dma_attr = { 317 DMA_ATTR_V0, /* dma_attr_version */ 318 0, /* dma_attr_addr_lo: lowest bus address */ 319 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 320 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 321 1, /* dma_attr_align: single byte aligned */ 322 1, /* dma_attr_burstsizes */ 323 1, /* dma_attr_minxfer */ 324 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 325 0xffffffffull, /* dma_attr_seg */ 326 SI_MAX_SGL_LENGTH, /* dma_attr_sgllen */ 327 512, /* dma_attr_granular */ 328 0, /* dma_attr_flags */ 329 }; 330 331 /* 332 * DMA attributes for incore RPB and SGT pool 333 */ 334 static ddi_dma_attr_t prb_sgt_dma_attr = { 335 DMA_ATTR_V0, /* dma_attr_version */ 336 0, /* dma_attr_addr_lo: lowest bus address */ 337 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 338 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 339 8, /* dma_attr_align: quad word aligned */ 340 1, /* dma_attr_burstsizes */ 341 1, /* dma_attr_minxfer */ 342 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 343 0xffffffffull, /* dma_attr_seg */ 344 1, /* dma_attr_sgllen */ 345 1, /* dma_attr_granular */ 346 0, /* dma_attr_flags */ 347 }; 348 349 /* Device access attributes */ 350 static ddi_device_acc_attr_t accattr = { 351 DDI_DEVICE_ATTR_V0, 352 DDI_STRUCTURE_LE_ACC, 353 DDI_STRICTORDER_ACC 354 }; 355 356 357 static struct dev_ops sictl_dev_ops = { 358 DEVO_REV, /* devo_rev */ 359 0, /* refcnt */ 360 si_getinfo, /* info */ 361 nulldev, /* identify */ 362 nulldev, /* probe */ 363 si_attach, /* attach */ 364 si_detach, /* detach */ 365 nodev, /* no reset */ 366 (struct cb_ops *)0, /* driver operations */ 367 NULL, /* bus operations */ 368 si_power /* power */ 369 }; 370 371 static sata_tran_hotplug_ops_t si_tran_hotplug_ops = { 372 SATA_TRAN_HOTPLUG_OPS_REV_1, 373 si_tran_hotplug_port_activate, 374 si_tran_hotplug_port_deactivate 375 }; 376 377 378 static int si_watchdog_timeout = 5; /* 5 seconds */ 379 static int si_watchdog_tick; 380 381 extern struct mod_ops mod_driverops; 382 383 static struct modldrv modldrv = { 384 &mod_driverops, /* driverops */ 385 "si3124 driver v%I%", 386 &sictl_dev_ops, /* driver ops */ 387 }; 388 389 static struct modlinkage modlinkage = { 390 MODREV_1, 391 &modldrv, 392 NULL 393 }; 394 395 396 /* The following are needed for si_log() */ 397 static kmutex_t si_log_mutex; 398 static char si_log_buf[512]; 399 uint32_t si_debug_flags = 0x0; 400 static int is_msi_supported = 0; 401 402 /* Opaque state pointer to be initialized by ddi_soft_state_init() */ 403 static void *si_statep = NULL; 404 405 /* 406 * si3124 module initialization. 407 * 408 */ 409 int 410 _init(void) 411 { 412 int error; 413 414 error = ddi_soft_state_init(&si_statep, sizeof (si_ctl_state_t), 0); 415 if (error != 0) { 416 return (error); 417 } 418 419 mutex_init(&si_log_mutex, NULL, MUTEX_DRIVER, NULL); 420 421 if ((error = sata_hba_init(&modlinkage)) != 0) { 422 mutex_destroy(&si_log_mutex); 423 ddi_soft_state_fini(&si_statep); 424 return (error); 425 } 426 427 error = mod_install(&modlinkage); 428 if (error != 0) { 429 sata_hba_fini(&modlinkage); 430 mutex_destroy(&si_log_mutex); 431 ddi_soft_state_fini(&si_statep); 432 return (error); 433 } 434 435 si_watchdog_tick = drv_usectohz((clock_t)si_watchdog_timeout * 1000000); 436 437 return (error); 438 } 439 440 /* 441 * si3124 module uninitialize. 442 * 443 */ 444 int 445 _fini(void) 446 { 447 int error; 448 449 error = mod_remove(&modlinkage); 450 if (error != 0) { 451 return (error); 452 } 453 454 /* Remove the resources allocated in _init(). */ 455 sata_hba_fini(&modlinkage); 456 mutex_destroy(&si_log_mutex); 457 ddi_soft_state_fini(&si_statep); 458 459 return (error); 460 } 461 462 /* 463 * _info entry point 464 * 465 */ 466 int 467 _info(struct modinfo *modinfop) 468 { 469 return (mod_info(&modlinkage, modinfop)); 470 } 471 472 473 /* 474 * The attach entry point for dev_ops. 475 * 476 * We initialize the controller, initialize the soft state, register 477 * the interrupt handlers and then register ourselves with sata framework. 478 */ 479 static int 480 si_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 481 { 482 si_ctl_state_t *si_ctlp; 483 int instance; 484 int status; 485 int attach_state; 486 int intr_types; 487 sata_device_t sdevice; 488 489 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_attach enter"); 490 instance = ddi_get_instance(dip); 491 attach_state = ATTACH_PROGRESS_NONE; 492 493 switch (cmd) { 494 495 case DDI_ATTACH: 496 497 /* Allocate si_softc. */ 498 status = ddi_soft_state_zalloc(si_statep, instance); 499 if (status != DDI_SUCCESS) { 500 goto err_out; 501 } 502 503 si_ctlp = ddi_get_soft_state(si_statep, instance); 504 si_ctlp->sictl_devinfop = dip; 505 506 attach_state |= ATTACH_PROGRESS_STATEP_ALLOC; 507 508 /* Configure pci config space handle. */ 509 status = pci_config_setup(dip, &si_ctlp->sictl_pci_conf_handle); 510 if (status != DDI_SUCCESS) { 511 goto err_out; 512 } 513 514 si_ctlp->sictl_devid = 515 pci_config_get16(si_ctlp->sictl_pci_conf_handle, 516 PCI_CONF_DEVID); 517 if (si_ctlp->sictl_devid == SI3132_DEV_ID) { 518 si_ctlp->sictl_num_ports = SI3132_MAX_PORTS; 519 } else { 520 si_ctlp->sictl_num_ports = SI3124_MAX_PORTS; 521 } 522 523 attach_state |= ATTACH_PROGRESS_CONF_HANDLE; 524 525 /* Now map the bar0; the bar0 contains the global registers. */ 526 status = ddi_regs_map_setup(dip, 527 PCI_BAR0, 528 (caddr_t *)&si_ctlp->sictl_global_addr, 529 0, 530 0, 531 &accattr, 532 &si_ctlp->sictl_global_acc_handle); 533 if (status != DDI_SUCCESS) { 534 goto err_out; 535 } 536 537 attach_state |= ATTACH_PROGRESS_BAR0_MAP; 538 539 /* Now map bar1; the bar1 contains the port registers. */ 540 status = ddi_regs_map_setup(dip, 541 PCI_BAR1, 542 (caddr_t *)&si_ctlp->sictl_port_addr, 543 0, 544 0, 545 &accattr, 546 &si_ctlp->sictl_port_acc_handle); 547 if (status != DDI_SUCCESS) { 548 goto err_out; 549 } 550 551 attach_state |= ATTACH_PROGRESS_BAR1_MAP; 552 553 /* 554 * Disable all the interrupts before adding interrupt 555 * handler(s). The interrupts shall be re-enabled selectively 556 * out of si_init_port(). 557 */ 558 si_disable_all_interrupts(si_ctlp); 559 560 /* Get supported interrupt types. */ 561 if (ddi_intr_get_supported_types(dip, &intr_types) 562 != DDI_SUCCESS) { 563 SIDBG0(SIDBG_INIT, NULL, 564 "ddi_intr_get_supported_types failed"); 565 goto err_out; 566 } 567 568 SIDBG1(SIDBG_INIT, NULL, 569 "ddi_intr_get_supported_types() returned: 0x%x", 570 intr_types); 571 572 if (is_msi_supported && (intr_types & DDI_INTR_TYPE_MSI)) { 573 SIDBG0(SIDBG_INIT, NULL, "Using MSI interrupt type"); 574 575 /* 576 * Try MSI first, but fall back to legacy if MSI 577 * attach fails. 578 */ 579 if (si_add_msi_intrs(si_ctlp) == DDI_SUCCESS) { 580 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_MSI; 581 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 582 SIDBG0(SIDBG_INIT, NULL, 583 "MSI interrupt setup done"); 584 } else { 585 SIDBG0(SIDBG_INIT, NULL, 586 "MSI registration failed " 587 "will try Legacy interrupts"); 588 } 589 } 590 591 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED) && 592 (intr_types & DDI_INTR_TYPE_FIXED)) { 593 /* 594 * Either the MSI interrupt setup has failed or only 595 * fixed interrupts are available on the system. 596 */ 597 SIDBG0(SIDBG_INIT, NULL, "Using Legacy interrupt type"); 598 599 if (si_add_legacy_intrs(si_ctlp) == DDI_SUCCESS) { 600 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_FIXED; 601 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 602 SIDBG0(SIDBG_INIT, NULL, 603 "Legacy interrupt setup done"); 604 } else { 605 SIDBG0(SIDBG_INIT, NULL, 606 "legacy interrupt setup failed"); 607 goto err_out; 608 } 609 } 610 611 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED)) { 612 SIDBG0(SIDBG_INIT, NULL, 613 "si3124: No interrupts registered"); 614 goto err_out; 615 } 616 617 618 /* Initialize the mutex. */ 619 mutex_init(&si_ctlp->sictl_mutex, NULL, MUTEX_DRIVER, 620 (void *)(uint64_t)si_ctlp->sictl_intr_pri); 621 622 attach_state |= ATTACH_PROGRESS_MUTEX_INIT; 623 624 /* 625 * Initialize the controller and driver core. 626 */ 627 si_ctlp->sictl_flags |= SI_ATTACH; 628 status = si_initialize_controller(si_ctlp); 629 si_ctlp->sictl_flags &= ~SI_ATTACH; 630 if (status) { 631 goto err_out; 632 } 633 634 attach_state |= ATTACH_PROGRESS_HW_INIT; 635 636 if (si_register_sata_hba_tran(si_ctlp)) { 637 SIDBG0(SIDBG_INIT, NULL, 638 "si3124: setting sata hba tran failed"); 639 goto err_out; 640 } 641 642 si_ctlp->sictl_timeout_id = timeout( 643 (void (*)(void *))si_watchdog_handler, 644 (caddr_t)si_ctlp, si_watchdog_tick); 645 646 si_ctlp->sictl_power_level = PM_LEVEL_D0; 647 648 return (DDI_SUCCESS); 649 650 case DDI_RESUME: 651 si_ctlp = ddi_get_soft_state(si_statep, instance); 652 653 status = si_initialize_controller(si_ctlp); 654 if (status) { 655 return (DDI_FAILURE); 656 } 657 658 si_ctlp->sictl_timeout_id = timeout( 659 (void (*)(void *))si_watchdog_handler, 660 (caddr_t)si_ctlp, si_watchdog_tick); 661 662 (void) pm_power_has_changed(dip, 0, PM_LEVEL_D0); 663 664 /* Notify SATA framework about RESUME. */ 665 if (sata_hba_attach(si_ctlp->sictl_devinfop, 666 si_ctlp->sictl_sata_hba_tran, 667 DDI_RESUME) != DDI_SUCCESS) { 668 return (DDI_FAILURE); 669 } 670 671 /* 672 * Notify the "framework" that it should reprobe ports to see 673 * if any device got changed while suspended. 674 */ 675 bzero((void *)&sdevice, sizeof (sata_device_t)); 676 sata_hba_event_notify(dip, &sdevice, 677 SATA_EVNT_PWR_LEVEL_CHANGED); 678 SIDBG0(SIDBG_INIT|SIDBG_EVENT, si_ctlp, 679 "sending event up: SATA_EVNT_PWR_LEVEL_CHANGED"); 680 681 (void) pm_idle_component(si_ctlp->sictl_devinfop, 0); 682 683 si_ctlp->sictl_power_level = PM_LEVEL_D0; 684 685 return (DDI_SUCCESS); 686 687 default: 688 return (DDI_FAILURE); 689 690 } 691 692 err_out: 693 if (attach_state & ATTACH_PROGRESS_HW_INIT) { 694 si_ctlp->sictl_flags |= SI_DETACH; 695 /* We want to set SI_DETACH to deallocate all memory */ 696 si_deinititalize_controller(si_ctlp); 697 si_ctlp->sictl_flags &= ~SI_DETACH; 698 } 699 700 if (attach_state & ATTACH_PROGRESS_MUTEX_INIT) { 701 mutex_destroy(&si_ctlp->sictl_mutex); 702 } 703 704 if (attach_state & ATTACH_PROGRESS_INTR_ADDED) { 705 si_rem_intrs(si_ctlp); 706 } 707 708 if (attach_state & ATTACH_PROGRESS_BAR1_MAP) { 709 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 710 } 711 712 if (attach_state & ATTACH_PROGRESS_BAR0_MAP) { 713 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 714 } 715 716 if (attach_state & ATTACH_PROGRESS_CONF_HANDLE) { 717 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 718 } 719 720 if (attach_state & ATTACH_PROGRESS_STATEP_ALLOC) { 721 ddi_soft_state_free(si_statep, instance); 722 } 723 724 return (DDI_FAILURE); 725 } 726 727 728 /* 729 * The detach entry point for dev_ops. 730 * 731 * We undo the things we did in si_attach(). 732 */ 733 static int 734 si_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 735 { 736 si_ctl_state_t *si_ctlp; 737 int instance; 738 739 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_detach enter"); 740 instance = ddi_get_instance(dip); 741 si_ctlp = ddi_get_soft_state(si_statep, instance); 742 743 switch (cmd) { 744 745 case DDI_DETACH: 746 747 mutex_enter(&si_ctlp->sictl_mutex); 748 749 /* disable the interrupts for an uninterrupted detach */ 750 si_disable_all_interrupts(si_ctlp); 751 752 mutex_exit(&si_ctlp->sictl_mutex); 753 /* unregister from the sata framework. */ 754 if (si_unregister_sata_hba_tran(si_ctlp) != SI_SUCCESS) { 755 si_enable_all_interrupts(si_ctlp); 756 return (DDI_FAILURE); 757 } 758 mutex_enter(&si_ctlp->sictl_mutex); 759 760 /* now cancel the timeout handler. */ 761 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 762 (void) untimeout(si_ctlp->sictl_timeout_id); 763 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 764 765 /* deinitialize the controller. */ 766 si_ctlp->sictl_flags |= SI_DETACH; 767 si_deinititalize_controller(si_ctlp); 768 si_ctlp->sictl_flags &= ~SI_DETACH; 769 770 /* destroy any mutexes */ 771 mutex_exit(&si_ctlp->sictl_mutex); 772 mutex_destroy(&si_ctlp->sictl_mutex); 773 774 /* remove the interrupts */ 775 si_rem_intrs(si_ctlp); 776 777 /* remove the reg maps. */ 778 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 779 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 780 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 781 782 /* free the soft state. */ 783 ddi_soft_state_free(si_statep, instance); 784 785 return (DDI_SUCCESS); 786 787 case DDI_SUSPEND: 788 /* Inform SATA framework */ 789 if (sata_hba_detach(dip, cmd) != DDI_SUCCESS) { 790 return (DDI_FAILURE); 791 } 792 793 mutex_enter(&si_ctlp->sictl_mutex); 794 795 /* 796 * Device needs to be at full power in case it is needed to 797 * handle dump(9e) to save CPR state after DDI_SUSPEND 798 * completes. This is OK since presumably power will be 799 * removed anyways. No outstanding transactions should be 800 * on the controller since the children are already quiesed. 801 * 802 * If any ioctls/cfgadm support is added that touches 803 * hardware, those entry points will need to check for 804 * suspend and then block or return errors until resume. 805 * 806 */ 807 if (pm_busy_component(si_ctlp->sictl_devinfop, 0) == 808 DDI_SUCCESS) { 809 mutex_exit(&si_ctlp->sictl_mutex); 810 (void) pm_raise_power(si_ctlp->sictl_devinfop, 0, 811 PM_LEVEL_D0); 812 mutex_enter(&si_ctlp->sictl_mutex); 813 } 814 815 si_deinititalize_controller(si_ctlp); 816 817 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 818 (void) untimeout(si_ctlp->sictl_timeout_id); 819 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 820 821 SIDBG1(SIDBG_POWER, NULL, "si3124%d: DDI_SUSPEND", instance); 822 823 mutex_exit(&si_ctlp->sictl_mutex); 824 825 return (DDI_SUCCESS); 826 827 default: 828 return (DDI_FAILURE); 829 830 } 831 832 } 833 834 static int 835 si_power(dev_info_t *dip, int component, int level) 836 { 837 #ifndef __lock_lint 838 _NOTE(ARGUNUSED(component)) 839 #endif /* __lock_lint */ 840 841 si_ctl_state_t *si_ctlp; 842 int instance = ddi_get_instance(dip); 843 int rval = DDI_SUCCESS; 844 int old_level; 845 sata_device_t sdevice; 846 847 si_ctlp = ddi_get_soft_state(si_statep, instance); 848 849 if (si_ctlp == NULL) { 850 return (DDI_FAILURE); 851 } 852 853 SIDBG0(SIDBG_ENTRY, NULL, "si_power enter"); 854 855 mutex_enter(&si_ctlp->sictl_mutex); 856 old_level = si_ctlp->sictl_power_level; 857 858 switch (level) { 859 case PM_LEVEL_D0: /* fully on */ 860 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 861 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D0); 862 #ifndef __lock_lint 863 delay(drv_usectohz(10000)); 864 #endif /* __lock_lint */ 865 si_ctlp->sictl_power_level = PM_LEVEL_D0; 866 (void) pci_restore_config_regs(si_ctlp->sictl_devinfop); 867 868 SIDBG2(SIDBG_POWER, si_ctlp, 869 "si3124%d: turning power ON. old level %d", 870 instance, old_level); 871 /* 872 * If called from attach, just raise device power, 873 * restore config registers (if they were saved 874 * from a previous detach that lowered power), 875 * and exit. 876 */ 877 if (si_ctlp->sictl_flags & SI_ATTACH) 878 break; 879 880 mutex_exit(&si_ctlp->sictl_mutex); 881 (void) si_initialize_controller(si_ctlp); 882 mutex_enter(&si_ctlp->sictl_mutex); 883 884 si_ctlp->sictl_timeout_id = timeout( 885 (void (*)(void *))si_watchdog_handler, 886 (caddr_t)si_ctlp, si_watchdog_tick); 887 888 bzero((void *)&sdevice, sizeof (sata_device_t)); 889 sata_hba_event_notify( 890 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 891 &sdevice, SATA_EVNT_PWR_LEVEL_CHANGED); 892 SIDBG0(SIDBG_EVENT|SIDBG_POWER, si_ctlp, 893 "sending event up: PWR_LEVEL_CHANGED"); 894 895 break; 896 897 case PM_LEVEL_D3: /* fully off */ 898 if (!(si_ctlp->sictl_flags & SI_DETACH)) { 899 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 900 (void) untimeout(si_ctlp->sictl_timeout_id); 901 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 902 903 si_deinititalize_controller(si_ctlp); 904 905 si_ctlp->sictl_power_level = PM_LEVEL_D3; 906 } 907 908 (void) pci_save_config_regs(si_ctlp->sictl_devinfop); 909 910 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 911 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D3HOT); 912 913 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 914 "old level %d", instance, old_level); 915 916 break; 917 918 default: 919 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 920 "old level %d", instance, old_level); 921 rval = DDI_FAILURE; 922 break; 923 } 924 925 mutex_exit(&si_ctlp->sictl_mutex); 926 927 return (rval); 928 } 929 930 931 /* 932 * The info entry point for dev_ops. 933 * 934 */ 935 static int 936 si_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 937 void *arg, 938 void **result) 939 { 940 #ifndef __lock_lint 941 _NOTE(ARGUNUSED(dip)) 942 #endif /* __lock_lint */ 943 si_ctl_state_t *si_ctlp; 944 int instance; 945 dev_t dev; 946 947 dev = (dev_t)arg; 948 instance = getminor(dev); 949 950 switch (infocmd) { 951 case DDI_INFO_DEVT2DEVINFO: 952 si_ctlp = ddi_get_soft_state(si_statep, instance); 953 if (si_ctlp != NULL) { 954 *result = si_ctlp->sictl_devinfop; 955 return (DDI_SUCCESS); 956 } else { 957 *result = NULL; 958 return (DDI_FAILURE); 959 } 960 case DDI_INFO_DEVT2INSTANCE: 961 *(int *)result = instance; 962 break; 963 default: 964 break; 965 } 966 return (DDI_SUCCESS); 967 } 968 969 970 971 /* 972 * Registers the si3124 with sata framework. 973 */ 974 static int 975 si_register_sata_hba_tran(si_ctl_state_t *si_ctlp) 976 { 977 struct sata_hba_tran *sata_hba_tran; 978 979 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 980 "si_register_sata_hba_tran entry"); 981 982 mutex_enter(&si_ctlp->sictl_mutex); 983 984 /* Allocate memory for the sata_hba_tran */ 985 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 986 987 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV; 988 sata_hba_tran->sata_tran_hba_dip = si_ctlp->sictl_devinfop; 989 sata_hba_tran->sata_tran_hba_dma_attr = &buffer_dma_attr; 990 991 sata_hba_tran->sata_tran_hba_num_cports = si_ctlp->sictl_num_ports; 992 sata_hba_tran->sata_tran_hba_features_support = 0; 993 sata_hba_tran->sata_tran_hba_qdepth = SI_NUM_SLOTS; 994 995 sata_hba_tran->sata_tran_probe_port = si_tran_probe_port; 996 sata_hba_tran->sata_tran_start = si_tran_start; 997 sata_hba_tran->sata_tran_abort = si_tran_abort; 998 sata_hba_tran->sata_tran_reset_dport = si_tran_reset_dport; 999 sata_hba_tran->sata_tran_selftest = NULL; 1000 sata_hba_tran->sata_tran_hotplug_ops = &si_tran_hotplug_ops; 1001 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1002 sata_hba_tran->sata_tran_ioctl = NULL; 1003 mutex_exit(&si_ctlp->sictl_mutex); 1004 1005 /* Attach it to SATA framework */ 1006 if (sata_hba_attach(si_ctlp->sictl_devinfop, sata_hba_tran, DDI_ATTACH) 1007 != DDI_SUCCESS) { 1008 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1009 return (SI_FAILURE); 1010 } 1011 1012 mutex_enter(&si_ctlp->sictl_mutex); 1013 si_ctlp->sictl_sata_hba_tran = sata_hba_tran; 1014 mutex_exit(&si_ctlp->sictl_mutex); 1015 1016 return (SI_SUCCESS); 1017 } 1018 1019 1020 /* 1021 * Unregisters the si3124 with sata framework. 1022 */ 1023 static int 1024 si_unregister_sata_hba_tran(si_ctl_state_t *si_ctlp) 1025 { 1026 1027 /* Detach from the SATA framework. */ 1028 if (sata_hba_detach(si_ctlp->sictl_devinfop, DDI_DETACH) != 1029 DDI_SUCCESS) { 1030 return (SI_FAILURE); 1031 } 1032 1033 /* Deallocate sata_hba_tran. */ 1034 kmem_free((void *)si_ctlp->sictl_sata_hba_tran, 1035 sizeof (sata_hba_tran_t)); 1036 1037 si_ctlp->sictl_sata_hba_tran = NULL; 1038 1039 return (SI_SUCCESS); 1040 } 1041 1042 /* 1043 * Called by sata framework to probe a port. We return the 1044 * cached information from a previous hardware probe. 1045 * 1046 * The actual hardware probing itself was done either from within 1047 * si_initialize_controller() during the driver attach or 1048 * from a phy ready change interrupt handler. 1049 */ 1050 static int 1051 si_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1052 { 1053 1054 si_ctl_state_t *si_ctlp; 1055 uint8_t cport = sd->satadev_addr.cport; 1056 uint8_t pmport = sd->satadev_addr.pmport; 1057 uint8_t qual = sd->satadev_addr.qual; 1058 uint8_t port_type; 1059 si_port_state_t *si_portp; 1060 si_portmult_state_t *si_portmultp; 1061 1062 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1063 1064 SIDBG3(SIDBG_ENTRY, si_ctlp, 1065 "si_tran_probe_port: cport: 0x%x, pmport: 0x%x, qual: 0x%x", 1066 cport, pmport, qual); 1067 1068 if (cport >= SI_MAX_PORTS) { 1069 sd->satadev_type = SATA_DTYPE_NONE; 1070 sd->satadev_state = SATA_STATE_PROBED; 1071 return (SATA_FAILURE); 1072 } 1073 1074 mutex_enter(&si_ctlp->sictl_mutex); 1075 si_portp = si_ctlp->sictl_ports[cport]; 1076 mutex_exit(&si_ctlp->sictl_mutex); 1077 if (si_portp == NULL) { 1078 sd->satadev_type = SATA_DTYPE_NONE; 1079 sd->satadev_state = SATA_STATE_PROBED; 1080 return (SATA_FAILURE); 1081 } 1082 1083 mutex_enter(&si_portp->siport_mutex); 1084 1085 if (qual == SATA_ADDR_PMPORT) { 1086 if (pmport >= si_portp->siport_portmult_state.sipm_num_ports) { 1087 sd->satadev_type = SATA_DTYPE_NONE; 1088 sd->satadev_state = SATA_STATE_PROBED; 1089 mutex_exit(&si_portp->siport_mutex); 1090 return (SATA_FAILURE); 1091 } else { 1092 si_portmultp = &si_portp->siport_portmult_state; 1093 port_type = si_portmultp->sipm_port_type[pmport]; 1094 } 1095 } else { 1096 port_type = si_portp->siport_port_type; 1097 } 1098 1099 switch (port_type) { 1100 1101 case PORT_TYPE_DISK: 1102 sd->satadev_type = SATA_DTYPE_ATADISK; 1103 sd->satadev_state = SATA_STATE_PROBED; 1104 break; 1105 1106 case PORT_TYPE_ATAPI: 1107 sd->satadev_type = SATA_DTYPE_ATAPICD; 1108 sd->satadev_state = SATA_STATE_PROBED; 1109 break; 1110 1111 case PORT_TYPE_MULTIPLIER: 1112 sd->satadev_type = SATA_DTYPE_PMULT; 1113 sd->satadev_add_info = 1114 si_portp->siport_portmult_state.sipm_num_ports; 1115 sd->satadev_state = SATA_STATE_PROBED; 1116 break; 1117 1118 case PORT_TYPE_UNKNOWN: 1119 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1120 sd->satadev_state = SATA_STATE_PROBED; 1121 1122 default: 1123 /* we don't support any other device types. */ 1124 sd->satadev_type = SATA_DTYPE_NONE; 1125 sd->satadev_state = SATA_STATE_PROBED; 1126 break; 1127 } 1128 1129 if (qual == SATA_ADDR_PMPORT) { 1130 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1131 pmport, PSCR_REG0, &sd->satadev_scr.sstatus); 1132 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1133 pmport, PSCR_REG1, &sd->satadev_scr.serror); 1134 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1135 pmport, PSCR_REG2, &sd->satadev_scr.scontrol); 1136 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1137 pmport, PSCR_REG3, &sd->satadev_scr.sactive); 1138 } else { 1139 fill_dev_sregisters(si_ctlp, cport, sd); 1140 if (!(si_portp->siport_active)) { 1141 /* 1142 * Since we are implementing the port deactivation 1143 * in software only, we need to fake a valid value 1144 * for sstatus when the device is in deactivated state. 1145 */ 1146 SSTATUS_SET_DET(sd->satadev_scr.sstatus, 1147 SSTATUS_DET_PHYOFFLINE); 1148 SSTATUS_SET_IPM(sd->satadev_scr.sstatus, 1149 SSTATUS_IPM_NODEV_NOPHY); 1150 } 1151 } 1152 1153 mutex_exit(&si_portp->siport_mutex); 1154 return (SATA_SUCCESS); 1155 } 1156 1157 /* 1158 * Called by sata framework to transport a sata packet down stream. 1159 * 1160 * The actual work of building the FIS & transporting it to the hardware 1161 * is done out of the subroutine si_deliver_satapkt(). 1162 */ 1163 static int 1164 si_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1165 { 1166 si_ctl_state_t *si_ctlp; 1167 uint8_t cport; 1168 si_port_state_t *si_portp; 1169 int slot; 1170 1171 cport = spkt->satapkt_device.satadev_addr.cport; 1172 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1173 mutex_enter(&si_ctlp->sictl_mutex); 1174 si_portp = si_ctlp->sictl_ports[cport]; 1175 mutex_exit(&si_ctlp->sictl_mutex); 1176 1177 SIDBG1(SIDBG_ENTRY, si_ctlp, 1178 "si_tran_start entry: port: 0x%x", cport); 1179 1180 mutex_enter(&si_portp->siport_mutex); 1181 1182 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1183 !si_portp->siport_active) { 1184 /* 1185 * si_intr_phy_ready_change() may have rendered it to 1186 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1187 * it inactive. 1188 */ 1189 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1190 fill_dev_sregisters(si_ctlp, cport, &spkt->satapkt_device); 1191 mutex_exit(&si_portp->siport_mutex); 1192 return (SATA_TRAN_PORT_ERROR); 1193 } 1194 1195 if (spkt->satapkt_cmd.satacmd_flags & SATA_CLEAR_DEV_RESET_STATE) { 1196 si_portp->siport_reset_in_progress = 0; 1197 SIDBG1(SIDBG_ENTRY, si_ctlp, 1198 "si_tran_start clearing the " 1199 "reset_in_progress for port: 0x%x", cport); 1200 } 1201 1202 if (si_portp->siport_reset_in_progress && 1203 !(spkt->satapkt_cmd.satacmd_flags & 1204 SATA_IGNORE_DEV_RESET_STATE)) { 1205 1206 spkt->satapkt_reason = SATA_PKT_BUSY; 1207 SIDBG1(SIDBG_ERRS, si_ctlp, 1208 "si_tran_start returning BUSY while " 1209 "reset in progress: port: 0x%x", cport); 1210 mutex_exit(&si_portp->siport_mutex); 1211 return (SATA_TRAN_BUSY); 1212 } 1213 1214 if (si_portp->mopping_in_progress) { 1215 spkt->satapkt_reason = SATA_PKT_BUSY; 1216 SIDBG1(SIDBG_ERRS, si_ctlp, 1217 "si_tran_start returning BUSY while " 1218 "mopping in progress: port: 0x%x", cport); 1219 mutex_exit(&si_portp->siport_mutex); 1220 return (SATA_TRAN_BUSY); 1221 } 1222 1223 if ((slot = si_deliver_satapkt(si_ctlp, si_portp, cport, spkt)) 1224 == SI_FAILURE) { 1225 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1226 SIDBG1(SIDBG_ERRS, si_ctlp, 1227 "si_tran_start returning QUEUE_FULL: port: 0x%x", 1228 cport); 1229 mutex_exit(&si_portp->siport_mutex); 1230 return (SATA_TRAN_QUEUE_FULL); 1231 } 1232 1233 if (spkt->satapkt_op_mode & (SATA_OPMODE_POLLING|SATA_OPMODE_SYNCH)) { 1234 /* we need to poll now */ 1235 mutex_exit(&si_portp->siport_mutex); 1236 si_poll_cmd(si_ctlp, si_portp, cport, slot, spkt); 1237 mutex_enter(&si_portp->siport_mutex); 1238 } 1239 1240 mutex_exit(&si_portp->siport_mutex); 1241 return (SATA_TRAN_ACCEPTED); 1242 } 1243 1244 #define SENDUP_PACKET(si_portp, satapkt, reason) \ 1245 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1246 SATAC_WRITE_FPDMA_QUEUED) || \ 1247 (satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1248 SATAC_READ_FPDMA_QUEUED)) { \ 1249 si_portp->siport_pending_ncq_count--; \ 1250 } \ 1251 if (satapkt) { \ 1252 satapkt->satapkt_reason = reason; \ 1253 /* \ 1254 * We set the satapkt_reason in both synch and \ 1255 * non-synch cases. \ 1256 */ \ 1257 } \ 1258 if (satapkt && \ 1259 !(satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1260 satapkt->satapkt_comp) { \ 1261 mutex_exit(&si_portp->siport_mutex); \ 1262 (*satapkt->satapkt_comp)(satapkt); \ 1263 mutex_enter(&si_portp->siport_mutex); \ 1264 } 1265 1266 /* 1267 * Mopping is necessitated because of the si3124 hardware limitation. 1268 * The only way to recover from errors or to abort a command is to 1269 * reset the port/device but such a reset also results in throwing 1270 * away all the unfinished pending commands. 1271 * 1272 * A port or device is reset in four scenarios: 1273 * a) some commands failed with errors 1274 * b) or we need to timeout some commands 1275 * c) or we need to abort some commands 1276 * d) or we need reset the port at the request of sata framework 1277 * 1278 * In all these scenarios, we need to send any pending unfinished 1279 * commands up to sata framework. 1280 * 1281 * Only one mopping process at a time is allowed; this is achieved 1282 * by using siport_mop_mutex. 1283 */ 1284 static void 1285 si_mop_commands(si_ctl_state_t *si_ctlp, 1286 si_port_state_t *si_portp, 1287 uint8_t port, 1288 1289 uint32_t slot_status, 1290 uint32_t failed_tags, 1291 uint32_t timedout_tags, 1292 uint32_t aborting_tags, 1293 uint32_t reset_tags) 1294 { 1295 uint32_t finished_tags, unfinished_tags; 1296 int tmpslot; 1297 sata_pkt_t *satapkt; 1298 si_prb_t *prb; 1299 uint32_t *prb_word_ptr; 1300 int i; 1301 1302 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1303 "si_mop_commands entered: slot_status: 0x%x", 1304 slot_status); 1305 1306 SIDBG4(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1307 "si_mop_commands: failed_tags: 0x%x, timedout_tags: 0x%x" 1308 "aborting_tags: 0x%x, reset_tags: 0x%x", 1309 failed_tags, 1310 timedout_tags, 1311 aborting_tags, 1312 reset_tags); 1313 /* 1314 * We could be here for four reasons: abort, reset, 1315 * timeout or error handling. Only one such mopping 1316 * is allowed at a time. 1317 * 1318 * Note that we are already holding the main per port 1319 * mutex; all we need now is siport_mop_mutex. 1320 */ 1321 mutex_enter(&si_portp->siport_mop_mutex); 1322 mutex_enter(&si_portp->siport_mutex); 1323 1324 si_portp->mopping_in_progress = 1; 1325 1326 finished_tags = si_portp->siport_pending_tags & 1327 ~slot_status & SI_SLOT_MASK; 1328 1329 unfinished_tags = slot_status & SI_SLOT_MASK & 1330 ~failed_tags & 1331 ~aborting_tags & 1332 ~reset_tags & 1333 ~timedout_tags; 1334 1335 /* Send up the finished_tags with SATA_PKT_COMPLETED. */ 1336 while (finished_tags) { 1337 tmpslot = ddi_ffs(finished_tags) - 1; 1338 if (tmpslot == -1) { 1339 break; 1340 } 1341 1342 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1343 ASSERT(satapkt != NULL); 1344 SIDBG1(SIDBG_ERRS, si_ctlp, 1345 "si_mop_commands sending up completed satapkt: %x", 1346 satapkt); 1347 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 1348 1349 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1350 CLEAR_BIT(finished_tags, tmpslot); 1351 } 1352 1353 ASSERT(finished_tags == 0); 1354 1355 /* Send up failed_tags with SATA_PKT_DEV_ERROR. */ 1356 while (failed_tags) { 1357 tmpslot = ddi_ffs(failed_tags) - 1; 1358 if (tmpslot == -1) { 1359 break; 1360 } 1361 SIDBG1(SIDBG_ERRS, si_ctlp, "si3124: si_mop_commands: " 1362 "handling failed slot: 0x%x", tmpslot); 1363 1364 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1365 ASSERT(satapkt != NULL); 1366 if (satapkt->satapkt_device.satadev_type == 1367 SATA_DTYPE_ATAPICD) { 1368 si_set_sense_data(satapkt, SATA_PKT_DEV_ERROR); 1369 } 1370 1371 /* 1372 * The LRAM contains the the modified FIS. 1373 * Read the modified FIS to obtain the Error & Status. 1374 */ 1375 prb = &(si_portp->siport_prbpool[tmpslot]); 1376 prb_word_ptr = (uint32_t *)prb; 1377 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 1378 prb_word_ptr[i] = ddi_get32( 1379 si_ctlp->sictl_port_acc_handle, 1380 (uint32_t *)(PORT_LRAM(si_ctlp, port, 1381 tmpslot)+i*4)); 1382 } 1383 1384 satapkt->satapkt_cmd.satacmd_status_reg = 1385 GET_FIS_COMMAND(prb->prb_fis); 1386 satapkt->satapkt_cmd.satacmd_error_reg = 1387 GET_FIS_FEATURES(prb->prb_fis); 1388 1389 /* 1390 * In the case of NCQ command failures, the error is 1391 * overwritten by the one obtained from issuing of a 1392 * READ LOG EXTENDED command. 1393 */ 1394 if (si_portp->siport_err_tags_SDBERROR & (1 << tmpslot)) { 1395 satapkt->satapkt_cmd.satacmd_error_reg = 1396 si_read_log_ext(si_ctlp, si_portp, port); 1397 } 1398 1399 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_DEV_ERROR); 1400 1401 CLEAR_BIT(failed_tags, tmpslot); 1402 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1403 } 1404 1405 ASSERT(failed_tags == 0); 1406 1407 /* Send up timedout_tags with SATA_PKT_TIMEOUT. */ 1408 while (timedout_tags) { 1409 tmpslot = ddi_ffs(timedout_tags) - 1; 1410 if (tmpslot == -1) { 1411 break; 1412 } 1413 1414 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1415 ASSERT(satapkt != NULL); 1416 SIDBG1(SIDBG_ERRS, si_ctlp, 1417 "si_mop_commands sending " 1418 "spkt up with PKT_TIMEOUT: %x", 1419 satapkt); 1420 1421 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_TIMEOUT); 1422 1423 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1424 CLEAR_BIT(timedout_tags, tmpslot); 1425 } 1426 1427 ASSERT(timedout_tags == 0); 1428 1429 /* Send up aborting packets with SATA_PKT_ABORTED. */ 1430 while (aborting_tags) { 1431 tmpslot = ddi_ffs(unfinished_tags) - 1; 1432 if (tmpslot == -1) { 1433 break; 1434 } 1435 1436 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1437 ASSERT(satapkt != NULL); 1438 SIDBG1(SIDBG_ERRS, si_ctlp, 1439 "si_mop_commands aborting spkt: %x", 1440 satapkt); 1441 if (satapkt->satapkt_device.satadev_type == 1442 SATA_DTYPE_ATAPICD) { 1443 si_set_sense_data(satapkt, SATA_PKT_ABORTED); 1444 } 1445 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_ABORTED); 1446 1447 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1448 CLEAR_BIT(aborting_tags, tmpslot); 1449 1450 } 1451 1452 ASSERT(aborting_tags == 0); 1453 1454 /* Reset tags are sent up to framework with SATA_PKT_RESET. */ 1455 while (reset_tags) { 1456 tmpslot = ddi_ffs(reset_tags) - 1; 1457 if (tmpslot == -1) { 1458 break; 1459 } 1460 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1461 ASSERT(satapkt != NULL); 1462 SIDBG1(SIDBG_ERRS, si_ctlp, 1463 "si_mop_commands sending PKT_RESET for " 1464 "reset spkt: %x", 1465 satapkt); 1466 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_RESET); 1467 1468 CLEAR_BIT(reset_tags, tmpslot); 1469 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1470 } 1471 1472 ASSERT(reset_tags == 0); 1473 1474 /* Send up the unfinished_tags with SATA_PKT_BUSY. */ 1475 while (unfinished_tags) { 1476 tmpslot = ddi_ffs(unfinished_tags) - 1; 1477 if (tmpslot == -1) { 1478 break; 1479 } 1480 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1481 ASSERT(satapkt != NULL); 1482 SIDBG1(SIDBG_ERRS, si_ctlp, 1483 "si_mop_commands sending PKT_BUSY for " 1484 "retry spkt: %x", 1485 satapkt); 1486 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_BUSY); 1487 1488 CLEAR_BIT(unfinished_tags, tmpslot); 1489 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1490 } 1491 1492 ASSERT(unfinished_tags == 0); 1493 1494 si_portp->mopping_in_progress = 0; 1495 1496 mutex_exit(&si_portp->siport_mutex); 1497 mutex_exit(&si_portp->siport_mop_mutex); 1498 1499 } 1500 1501 /* 1502 * Called by the sata framework to abort the previously sent packet(s). 1503 * 1504 * We reset the device and mop the commands on the port. 1505 */ 1506 static int 1507 si_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1508 { 1509 uint32_t slot_status; 1510 uint8_t port; 1511 int tmpslot; 1512 uint32_t aborting_tags; 1513 uint32_t finished_tags; 1514 si_port_state_t *si_portp; 1515 si_ctl_state_t *si_ctlp; 1516 1517 port = spkt->satapkt_device.satadev_addr.cport; 1518 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1519 mutex_enter(&si_ctlp->sictl_mutex); 1520 si_portp = si_ctlp->sictl_ports[port]; 1521 mutex_exit(&si_ctlp->sictl_mutex); 1522 1523 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_tran_abort on port: %x", port); 1524 1525 mutex_enter(&si_portp->siport_mutex); 1526 1527 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1528 !si_portp->siport_active) { 1529 /* 1530 * si_intr_phy_ready_change() may have rendered it to 1531 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1532 * it inactive. 1533 */ 1534 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1535 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1536 mutex_exit(&si_portp->siport_mutex); 1537 return (SATA_FAILURE); 1538 } 1539 1540 if (flag == SATA_ABORT_ALL_PACKETS) { 1541 aborting_tags = si_portp->siport_pending_tags; 1542 } else { 1543 /* 1544 * Need to abort a single packet. 1545 * Search our siport_slot_pkts[] list for matching spkt. 1546 */ 1547 aborting_tags = 0xffffffff; /* 0xffffffff is impossible tag */ 1548 for (tmpslot = 0; tmpslot < SI_NUM_SLOTS; tmpslot++) { 1549 if (si_portp->siport_slot_pkts[tmpslot] == spkt) { 1550 aborting_tags = (0x1 << tmpslot); 1551 break; 1552 } 1553 } 1554 1555 if (aborting_tags == 0xffffffff) { 1556 /* requested packet is not on pending list. */ 1557 fill_dev_sregisters(si_ctlp, port, 1558 &spkt->satapkt_device); 1559 mutex_exit(&si_portp->siport_mutex); 1560 return (SATA_FAILURE); 1561 } 1562 } 1563 1564 1565 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1566 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1567 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, 1568 port, SI_DEVICE_RESET); 1569 1570 /* 1571 * Compute which have finished and which need to be retried. 1572 * 1573 * The finished tags are siport_pending_tags minus the slot_status. 1574 * The aborting_tags have to be reduced by finished_tags since we 1575 * can't possibly abort a tag which had finished already. 1576 */ 1577 finished_tags = si_portp->siport_pending_tags & 1578 ~slot_status & SI_SLOT_MASK; 1579 aborting_tags &= ~finished_tags; 1580 1581 mutex_exit(&si_portp->siport_mutex); 1582 si_mop_commands(si_ctlp, 1583 si_portp, 1584 port, 1585 slot_status, 1586 0, /* failed_tags */ 1587 0, /* timedout_tags */ 1588 aborting_tags, 1589 0); /* reset_tags */ 1590 mutex_enter(&si_portp->siport_mutex); 1591 1592 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1593 mutex_exit(&si_portp->siport_mutex); 1594 return (SATA_SUCCESS); 1595 } 1596 1597 1598 /* 1599 * Used to reject all the pending packets on a port during a reset 1600 * operation. 1601 * 1602 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 1603 * before calling us. 1604 */ 1605 static void 1606 si_reject_all_reset_pkts( 1607 si_ctl_state_t *si_ctlp, 1608 si_port_state_t *si_portp, 1609 int port) 1610 { 1611 uint32_t slot_status; 1612 uint32_t reset_tags; 1613 1614 _NOTE(ASSUMING_PROTECTED(si_portp)) 1615 1616 SIDBG1(SIDBG_ENTRY, si_ctlp, 1617 "si_reject_all_reset_pkts on port: %x", 1618 port); 1619 1620 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1621 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1622 1623 /* Compute which tags need to be sent up. */ 1624 reset_tags = slot_status & SI_SLOT_MASK; 1625 1626 mutex_exit(&si_portp->siport_mutex); 1627 si_mop_commands(si_ctlp, 1628 si_portp, 1629 port, 1630 slot_status, 1631 0, /* failed_tags */ 1632 0, /* timedout_tags */ 1633 0, /* aborting_tags */ 1634 reset_tags); 1635 mutex_enter(&si_portp->siport_mutex); 1636 1637 } 1638 1639 1640 /* 1641 * Called by sata framework to reset a port(s) or device. 1642 * 1643 */ 1644 static int 1645 si_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 1646 { 1647 si_ctl_state_t *si_ctlp; 1648 uint8_t port = sd->satadev_addr.cport; 1649 int i; 1650 si_port_state_t *si_portp; 1651 int retval = SI_SUCCESS; 1652 1653 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1654 SIDBG1(SIDBG_ENTRY, si_ctlp, 1655 "si_tran_reset_port entry: port: 0x%x", 1656 port); 1657 1658 switch (sd->satadev_addr.qual) { 1659 case SATA_ADDR_CPORT: 1660 mutex_enter(&si_ctlp->sictl_mutex); 1661 si_portp = si_ctlp->sictl_ports[port]; 1662 mutex_exit(&si_ctlp->sictl_mutex); 1663 1664 mutex_enter(&si_portp->siport_mutex); 1665 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1666 SI_PORT_RESET); 1667 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1668 mutex_exit(&si_portp->siport_mutex); 1669 1670 break; 1671 1672 case SATA_ADDR_DCPORT: 1673 mutex_enter(&si_ctlp->sictl_mutex); 1674 si_portp = si_ctlp->sictl_ports[port]; 1675 mutex_exit(&si_ctlp->sictl_mutex); 1676 1677 mutex_enter(&si_portp->siport_mutex); 1678 1679 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1680 !si_portp->siport_active) { 1681 mutex_exit(&si_portp->siport_mutex); 1682 retval = SI_FAILURE; 1683 break; 1684 } 1685 1686 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1687 SI_DEVICE_RESET); 1688 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1689 mutex_exit(&si_portp->siport_mutex); 1690 1691 break; 1692 1693 case SATA_ADDR_CNTRL: 1694 for (i = 0; i < si_ctlp->sictl_num_ports; i++) { 1695 mutex_enter(&si_ctlp->sictl_mutex); 1696 si_portp = si_ctlp->sictl_ports[port]; 1697 mutex_exit(&si_ctlp->sictl_mutex); 1698 1699 mutex_enter(&si_portp->siport_mutex); 1700 retval = si_reset_dport_wait_till_ready(si_ctlp, 1701 si_portp, i, SI_PORT_RESET); 1702 if (retval) { 1703 mutex_exit(&si_portp->siport_mutex); 1704 break; 1705 } 1706 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1707 mutex_exit(&si_portp->siport_mutex); 1708 } 1709 break; 1710 1711 case SATA_ADDR_PMPORT: 1712 case SATA_ADDR_DPMPORT: 1713 SIDBG0(SIDBG_VERBOSE, si_ctlp, 1714 "port mult reset not implemented yet"); 1715 /* FALLSTHROUGH */ 1716 1717 default: 1718 retval = SI_FAILURE; 1719 1720 } 1721 1722 return (retval); 1723 } 1724 1725 1726 /* 1727 * Called by sata framework to activate a port as part of hotplug. 1728 * 1729 * Note: Not port-mult aware. 1730 */ 1731 static int 1732 si_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 1733 { 1734 si_ctl_state_t *si_ctlp; 1735 si_port_state_t *si_portp; 1736 uint8_t port; 1737 1738 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1739 port = satadev->satadev_addr.cport; 1740 mutex_enter(&si_ctlp->sictl_mutex); 1741 si_portp = si_ctlp->sictl_ports[port]; 1742 mutex_exit(&si_ctlp->sictl_mutex); 1743 1744 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_tran_hotplug_port_activate entry"); 1745 1746 mutex_enter(&si_portp->siport_mutex); 1747 si_enable_port_interrupts(si_ctlp, port); 1748 1749 /* 1750 * Reset the device so that a si_find_dev_signature() would trigger. 1751 * But this reset is an internal operation; the sata framework does 1752 * not need to know about it. 1753 */ 1754 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1755 SI_DEVICE_RESET|SI_RESET_NO_EVENTS_UP); 1756 1757 satadev->satadev_state = SATA_STATE_READY; 1758 1759 si_portp->siport_active = PORT_ACTIVE; 1760 1761 fill_dev_sregisters(si_ctlp, port, satadev); 1762 1763 mutex_exit(&si_portp->siport_mutex); 1764 return (SATA_SUCCESS); 1765 } 1766 1767 /* 1768 * Called by sata framework to deactivate a port as part of hotplug. 1769 * 1770 * Note: Not port-mult aware. 1771 */ 1772 static int 1773 si_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 1774 { 1775 si_ctl_state_t *si_ctlp; 1776 si_port_state_t *si_portp; 1777 uint8_t port; 1778 1779 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1780 port = satadev->satadev_addr.cport; 1781 mutex_enter(&si_ctlp->sictl_mutex); 1782 si_portp = si_ctlp->sictl_ports[port]; 1783 mutex_exit(&si_ctlp->sictl_mutex); 1784 1785 SIDBG0(SIDBG_ENTRY, NULL, "si_tran_hotplug_port_deactivate entry"); 1786 1787 mutex_enter(&si_portp->siport_mutex); 1788 if (si_portp->siport_pending_tags & SI_SLOT_MASK) { 1789 /* 1790 * There are pending commands on this port. 1791 * Fail the deactivate request. 1792 */ 1793 satadev->satadev_state = SATA_STATE_READY; 1794 mutex_exit(&si_portp->siport_mutex); 1795 return (SATA_FAILURE); 1796 } 1797 1798 /* mark the device as not accessible any more. */ 1799 si_portp->siport_active = PORT_INACTIVE; 1800 1801 /* disable the interrupts on the port. */ 1802 si_disable_port_interrupts(si_ctlp, port); 1803 1804 satadev->satadev_state = SATA_PSTATE_SHUTDOWN; 1805 1806 fill_dev_sregisters(si_ctlp, port, satadev); 1807 /* 1808 * Since we are implementing the port deactivation in software only, 1809 * we need to fake a valid value for sstatus. 1810 */ 1811 SSTATUS_SET_DET(satadev->satadev_scr.sstatus, SSTATUS_DET_PHYOFFLINE); 1812 SSTATUS_SET_IPM(satadev->satadev_scr.sstatus, SSTATUS_IPM_NODEV_NOPHY); 1813 1814 mutex_exit(&si_portp->siport_mutex); 1815 return (SATA_SUCCESS); 1816 } 1817 1818 1819 /* 1820 * Allocates the si_port_state_t. 1821 */ 1822 static int 1823 si_alloc_port_state(si_ctl_state_t *si_ctlp, int port) 1824 { 1825 si_port_state_t *si_portp; 1826 1827 si_ctlp->sictl_ports[port] = (si_port_state_t *)kmem_zalloc( 1828 sizeof (si_port_state_t), KM_SLEEP); 1829 1830 si_portp = si_ctlp->sictl_ports[port]; 1831 mutex_init(&si_portp->siport_mutex, NULL, MUTEX_DRIVER, 1832 (void *)(uint64_t)si_ctlp->sictl_intr_pri); 1833 mutex_init(&si_portp->siport_mop_mutex, NULL, MUTEX_DRIVER, 1834 (void *)(uint64_t)si_ctlp->sictl_intr_pri); 1835 mutex_enter(&si_portp->siport_mutex); 1836 1837 /* allocate prb & sgt pkts for this port. */ 1838 if (si_alloc_prbpool(si_ctlp, port)) { 1839 mutex_exit(&si_portp->siport_mutex); 1840 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1841 return (SI_FAILURE); 1842 } 1843 if (si_alloc_sgbpool(si_ctlp, port)) { 1844 si_dealloc_prbpool(si_ctlp, port); 1845 mutex_exit(&si_portp->siport_mutex); 1846 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1847 return (SI_FAILURE); 1848 } 1849 1850 si_portp->siport_active = PORT_ACTIVE; 1851 mutex_exit(&si_portp->siport_mutex); 1852 1853 return (SI_SUCCESS); 1854 1855 } 1856 1857 /* 1858 * Deallocates the si_port_state_t. 1859 */ 1860 static void 1861 si_dealloc_port_state(si_ctl_state_t *si_ctlp, int port) 1862 { 1863 si_port_state_t *si_portp; 1864 si_portp = si_ctlp->sictl_ports[port]; 1865 1866 mutex_enter(&si_portp->siport_mutex); 1867 si_dealloc_sgbpool(si_ctlp, port); 1868 si_dealloc_prbpool(si_ctlp, port); 1869 mutex_exit(&si_portp->siport_mutex); 1870 1871 mutex_destroy(&si_portp->siport_mutex); 1872 mutex_destroy(&si_portp->siport_mop_mutex); 1873 1874 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1875 1876 } 1877 1878 /* 1879 * Allocates the SGB (Scatter Gather Block) incore buffer. 1880 */ 1881 static int 1882 si_alloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1883 { 1884 si_port_state_t *si_portp; 1885 uint_t cookie_count; 1886 size_t incore_sgbpool_size = SI_NUM_SLOTS * sizeof (si_sgblock_t); 1887 size_t ret_len; 1888 ddi_dma_cookie_t sgbpool_dma_cookie; 1889 1890 si_portp = si_ctlp->sictl_ports[port]; 1891 1892 /* allocate sgbpool dma handle. */ 1893 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 1894 &prb_sgt_dma_attr, 1895 DDI_DMA_SLEEP, 1896 NULL, 1897 &si_portp->siport_sgbpool_dma_handle) != 1898 DDI_SUCCESS) { 1899 1900 return (SI_FAILURE); 1901 } 1902 1903 /* allocate the memory for sgbpool. */ 1904 if (ddi_dma_mem_alloc(si_portp->siport_sgbpool_dma_handle, 1905 incore_sgbpool_size, 1906 &accattr, 1907 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1908 DDI_DMA_SLEEP, 1909 NULL, 1910 (caddr_t *)&si_portp->siport_sgbpool, 1911 &ret_len, 1912 &si_portp->siport_sgbpool_acc_handle) != NULL) { 1913 1914 /* error.. free the dma handle. */ 1915 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1916 return (SI_FAILURE); 1917 } 1918 1919 /* now bind it */ 1920 if (ddi_dma_addr_bind_handle(si_portp->siport_sgbpool_dma_handle, 1921 NULL, 1922 (caddr_t)si_portp->siport_sgbpool, 1923 incore_sgbpool_size, 1924 DDI_DMA_CONSISTENT, 1925 DDI_DMA_SLEEP, 1926 NULL, 1927 &sgbpool_dma_cookie, 1928 &cookie_count) != DDI_DMA_MAPPED) { 1929 /* error.. free the dma handle & free the memory. */ 1930 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1931 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1932 return (SI_FAILURE); 1933 } 1934 1935 si_portp->siport_sgbpool_physaddr = sgbpool_dma_cookie.dmac_laddress; 1936 return (SI_SUCCESS); 1937 } 1938 1939 /* 1940 * Deallocates the SGB (Scatter Gather Block) incore buffer. 1941 */ 1942 static void 1943 si_dealloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1944 { 1945 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 1946 1947 /* Unbind the dma handle first. */ 1948 (void) ddi_dma_unbind_handle(si_portp->siport_sgbpool_dma_handle); 1949 1950 /* Then free the underlying memory. */ 1951 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1952 1953 /* Now free the handle itself. */ 1954 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1955 1956 } 1957 1958 /* 1959 * Allocates the PRB (Port Request Block) incore packets. 1960 */ 1961 static int 1962 si_alloc_prbpool(si_ctl_state_t *si_ctlp, int port) 1963 { 1964 si_port_state_t *si_portp; 1965 uint_t cookie_count; 1966 size_t incore_pkt_size = SI_NUM_SLOTS * sizeof (si_prb_t); 1967 size_t ret_len; 1968 ddi_dma_cookie_t prbpool_dma_cookie; 1969 1970 si_portp = si_ctlp->sictl_ports[port]; 1971 1972 /* allocate prb pkts. */ 1973 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 1974 &prb_sgt_dma_attr, 1975 DDI_DMA_SLEEP, 1976 NULL, 1977 &si_portp->siport_prbpool_dma_handle) != 1978 DDI_SUCCESS) { 1979 1980 return (SI_FAILURE); 1981 } 1982 1983 if (ddi_dma_mem_alloc(si_portp->siport_prbpool_dma_handle, 1984 incore_pkt_size, 1985 &accattr, 1986 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1987 DDI_DMA_SLEEP, 1988 NULL, 1989 (caddr_t *)&si_portp->siport_prbpool, 1990 &ret_len, 1991 &si_portp->siport_prbpool_acc_handle) != NULL) { 1992 1993 /* error.. free the dma handle. */ 1994 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 1995 return (SI_FAILURE); 1996 } 1997 1998 if (ddi_dma_addr_bind_handle(si_portp->siport_prbpool_dma_handle, 1999 NULL, 2000 (caddr_t)si_portp->siport_prbpool, 2001 incore_pkt_size, 2002 DDI_DMA_CONSISTENT, 2003 DDI_DMA_SLEEP, 2004 NULL, 2005 &prbpool_dma_cookie, 2006 &cookie_count) != DDI_DMA_MAPPED) { 2007 /* error.. free the dma handle & free the memory. */ 2008 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2009 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2010 return (SI_FAILURE); 2011 } 2012 2013 si_portp->siport_prbpool_physaddr = 2014 prbpool_dma_cookie.dmac_laddress; 2015 return (SI_SUCCESS); 2016 } 2017 2018 /* 2019 * Deallocates the PRB (Port Request Block) incore packets. 2020 */ 2021 static void 2022 si_dealloc_prbpool(si_ctl_state_t *si_ctlp, int port) 2023 { 2024 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 2025 2026 /* Unbind the prb dma handle first. */ 2027 (void) ddi_dma_unbind_handle(si_portp->siport_prbpool_dma_handle); 2028 2029 /* Then free the underlying memory. */ 2030 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2031 2032 /* Now free the handle itself. */ 2033 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2034 2035 } 2036 2037 2038 2039 /* 2040 * Soft-reset the port to find the signature of the device connected to 2041 * the port. 2042 */ 2043 static void 2044 si_find_dev_signature( 2045 si_ctl_state_t *si_ctlp, 2046 si_port_state_t *si_portp, 2047 int port, 2048 int pmp) 2049 { 2050 si_prb_t *prb; 2051 uint32_t slot_status, signature; 2052 int slot, loop_count; 2053 2054 SIDBG2(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 2055 "si_find_dev_signature enter: port: %x, pmp: %x", 2056 port, pmp); 2057 2058 /* Build a Soft Reset PRB in host memory. */ 2059 mutex_enter(&si_portp->siport_mutex); 2060 2061 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2062 if (slot == -1) { 2063 /* Empty slot could not be found. */ 2064 if (pmp != PORTMULT_CONTROL_PORT) { 2065 /* We are behind port multiplier. */ 2066 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2067 PORT_TYPE_NODEV; 2068 } else { 2069 si_portp->siport_port_type = PORT_TYPE_NODEV; 2070 } 2071 2072 mutex_exit(&si_portp->siport_mutex); 2073 return; 2074 } 2075 prb = &si_portp->siport_prbpool[slot]; 2076 bzero((void *)prb, sizeof (si_prb_t)); 2077 2078 SET_FIS_PMP(prb->prb_fis, pmp); 2079 SET_PRB_CONTROL_SOFT_RESET(prb); 2080 2081 #if SI_DEBUG 2082 if (si_debug_flags & SIDBG_DUMP_PRB) { 2083 char *ptr; 2084 int j; 2085 2086 ptr = (char *)prb; 2087 cmn_err(CE_WARN, "si_find_dev_signature, prb: "); 2088 for (j = 0; j < (sizeof (si_prb_t)); j++) { 2089 if (j%4 == 0) { 2090 cmn_err(CE_WARN, "----"); 2091 } 2092 cmn_err(CE_WARN, "%x ", ptr[j]); 2093 } 2094 2095 } 2096 #endif /* SI_DEBUG */ 2097 2098 /* deliver soft reset prb to empty slot. */ 2099 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2100 2101 loop_count = 0; 2102 /* Loop till the soft reset is finished. */ 2103 do { 2104 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2105 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2106 2107 if (loop_count++ > SI_POLLRATE_SOFT_RESET) { 2108 /* We are effectively timing out after 10 sec. */ 2109 break; 2110 } 2111 2112 /* Wait for 10 millisec */ 2113 #ifndef __lock_lint 2114 delay(SI_10MS_TICKS); 2115 #endif /* __lock_lint */ 2116 2117 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 2118 2119 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 2120 "si_find_dev_signature: loop count: %d, slot_status: 0x%x", 2121 loop_count, slot_status); 2122 2123 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2124 2125 /* Read device signature from command slot. */ 2126 signature = ddi_get32(si_ctlp->sictl_port_acc_handle, 2127 (uint32_t *)(PORT_SIGNATURE_MSB(si_ctlp, port, slot))); 2128 signature <<= 8; 2129 signature |= (0xff & ddi_get32(si_ctlp->sictl_port_acc_handle, 2130 (uint32_t *)(PORT_SIGNATURE_LSB(si_ctlp, 2131 port, slot)))); 2132 2133 SIDBG1(SIDBG_INIT, si_ctlp, "Device signature: 0x%x", signature); 2134 2135 if (signature == SI_SIGNATURE_PORT_MULTIPLIER) { 2136 2137 SIDBG2(SIDBG_INIT, si_ctlp, 2138 "Found multiplier at cport: 0x%d, pmport: 0x%x", 2139 port, pmp); 2140 2141 if (pmp != PORTMULT_CONTROL_PORT) { 2142 /* 2143 * It is wrong to chain a port multiplier behind 2144 * another port multiplier. 2145 */ 2146 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2147 PORT_TYPE_NODEV; 2148 } else { 2149 si_portp->siport_port_type = PORT_TYPE_MULTIPLIER; 2150 mutex_exit(&si_portp->siport_mutex); 2151 (void) si_enumerate_port_multiplier(si_ctlp, 2152 si_portp, port); 2153 mutex_enter(&si_portp->siport_mutex); 2154 } 2155 si_init_port(si_ctlp, port); 2156 2157 } else if (signature == SI_SIGNATURE_ATAPI) { 2158 if (pmp != PORTMULT_CONTROL_PORT) { 2159 /* We are behind port multiplier. */ 2160 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2161 PORT_TYPE_ATAPI; 2162 } else { 2163 si_portp->siport_port_type = PORT_TYPE_ATAPI; 2164 si_init_port(si_ctlp, port); 2165 } 2166 SIDBG2(SIDBG_INIT, si_ctlp, 2167 "Found atapi at : cport: %x, pmport: %x", 2168 port, pmp); 2169 2170 } else if (signature == SI_SIGNATURE_DISK) { 2171 2172 if (pmp != PORTMULT_CONTROL_PORT) { 2173 /* We are behind port multiplier. */ 2174 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2175 PORT_TYPE_DISK; 2176 } else { 2177 si_portp->siport_port_type = PORT_TYPE_DISK; 2178 si_init_port(si_ctlp, port); 2179 } 2180 SIDBG2(SIDBG_INIT, si_ctlp, 2181 "found disk at : cport: %x, pmport: %x", 2182 port, pmp); 2183 2184 } else { 2185 if (pmp != PORTMULT_CONTROL_PORT) { 2186 /* We are behind port multiplier. */ 2187 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2188 PORT_TYPE_UNKNOWN; 2189 } else { 2190 si_portp->siport_port_type = PORT_TYPE_UNKNOWN; 2191 } 2192 SIDBG3(SIDBG_INIT, si_ctlp, 2193 "Found unknown signature 0x%x at: port: %x, pmp: %x", 2194 signature, port, pmp); 2195 } 2196 2197 mutex_exit(&si_portp->siport_mutex); 2198 } 2199 2200 2201 /* 2202 * Polls for the completion of the command. This is safe with both 2203 * interrupts enabled or disabled. 2204 */ 2205 static void 2206 si_poll_cmd( 2207 si_ctl_state_t *si_ctlp, 2208 si_port_state_t *si_portp, 2209 int port, 2210 int slot, 2211 sata_pkt_t *satapkt) 2212 { 2213 uint32_t slot_status; 2214 int pkt_timeout_ticks; 2215 uint32_t port_intr_status; 2216 int in_panic = ddi_in_panic(); 2217 2218 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_poll_cmd entered: port: 0x%x", port); 2219 2220 pkt_timeout_ticks = drv_usectohz((clock_t)satapkt->satapkt_time * 2221 1000000); 2222 2223 mutex_enter(&si_portp->siport_mutex); 2224 2225 /* we start out with SATA_PKT_COMPLETED as the satapkt_reason */ 2226 satapkt->satapkt_reason = SATA_PKT_COMPLETED; 2227 2228 do { 2229 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2230 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2231 2232 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2233 if (in_panic) { 2234 /* 2235 * If we are in panic, we can't rely on 2236 * timers; so, busy wait instead of delay(). 2237 */ 2238 mutex_exit(&si_portp->siport_mutex); 2239 drv_usecwait(SI_1MS_USECS); 2240 mutex_enter(&si_portp->siport_mutex); 2241 } else { 2242 mutex_exit(&si_portp->siport_mutex); 2243 #ifndef __lock_lint 2244 delay(SI_1MS_TICKS); 2245 #endif /* __lock_lint */ 2246 mutex_enter(&si_portp->siport_mutex); 2247 } 2248 } else { 2249 break; 2250 } 2251 2252 pkt_timeout_ticks -= SI_1MS_TICKS; 2253 2254 } while (pkt_timeout_ticks > 0); 2255 2256 if (satapkt->satapkt_reason != SATA_PKT_COMPLETED) { 2257 /* The si_mop_command() got to our packet before us */ 2258 goto poll_done; 2259 } 2260 2261 /* 2262 * Interrupts and timers may not be working properly in a crash dump 2263 * situation; we may need to handle all the three conditions here: 2264 * successful completion, packet failure and packet timeout. 2265 */ 2266 if (IS_ATTENTION_RAISED(slot_status)) { /* error seen on port */ 2267 2268 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 2269 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 2270 2271 SIDBG2(SIDBG_VERBOSE, si_ctlp, 2272 "si_poll_cmd: port_intr_status: 0x%x, port: %x", 2273 port_intr_status, port); 2274 2275 if (port_intr_status & INTR_COMMAND_ERROR) { 2276 mutex_exit(&si_portp->siport_mutex); 2277 (void) si_intr_command_error(si_ctlp, si_portp, port); 2278 mutex_enter(&si_portp->siport_mutex); 2279 2280 goto poll_done; 2281 2282 /* 2283 * Why do we need to call si_intr_command_error() ? 2284 * 2285 * Answer: Even if the current packet is not the 2286 * offending command, we need to restart the stalled 2287 * port; (may be, the interrupts are not working well 2288 * in panic condition). The call to routine 2289 * si_intr_command_error() will achieve that. 2290 * 2291 * What if the interrupts are working fine and the 2292 * si_intr_command_error() gets called once more from 2293 * interrupt context ? 2294 * 2295 * Answer: The second instance of routine 2296 * si_intr_command_error() will not mop anything 2297 * since the first error handler has already blown 2298 * away the hardware pending queues through reset. 2299 * 2300 * Will the si_intr_command_error() hurt current 2301 * packet ? 2302 * 2303 * Answer: No. 2304 */ 2305 } else { 2306 /* Ignore any non-error interrupts at this stage */ 2307 ddi_put32(si_ctlp->sictl_port_acc_handle, 2308 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, 2309 port)), 2310 port_intr_status & INTR_MASK); 2311 } 2312 2313 2314 } else if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2315 satapkt->satapkt_reason = SATA_PKT_TIMEOUT; 2316 } /* else: the command completed successfully */ 2317 2318 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == 2319 SATAC_WRITE_FPDMA_QUEUED) || 2320 (satapkt->satapkt_cmd.satacmd_cmd_reg == 2321 SATAC_READ_FPDMA_QUEUED)) { 2322 si_portp->siport_pending_ncq_count--; 2323 } 2324 2325 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2326 2327 poll_done: 2328 mutex_exit(&si_portp->siport_mutex); 2329 2330 /* 2331 * tidbit: What is the interaction of abort with polling ? 2332 * What happens if the current polled pkt is aborted in parallel ? 2333 * 2334 * Answer: Assuming that the si_mop_commands() completes ahead 2335 * of polling, all it does is to set the satapkt_reason to 2336 * SPKT_PKT_ABORTED. That would be fine with us. 2337 * 2338 * The same logic applies to reset interacting with polling. 2339 */ 2340 } 2341 2342 2343 /* 2344 * Searches for and claims a free slot. 2345 * 2346 * Returns: SI_FAILURE if no slots found 2347 * claimed slot number if successful 2348 * 2349 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2350 * before calling us. 2351 */ 2352 /*ARGSUSED*/ 2353 static int 2354 si_claim_free_slot(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 2355 { 2356 uint32_t free_slots; 2357 int slot; 2358 2359 _NOTE(ASSUMING_PROTECTED(si_portp)) 2360 2361 SIDBG1(SIDBG_ENTRY, si_ctlp, 2362 "si_claim_free_slot entry: siport_pending_tags: %x", 2363 si_portp->siport_pending_tags); 2364 2365 free_slots = (~si_portp->siport_pending_tags) & SI_SLOT_MASK; 2366 slot = ddi_ffs(free_slots) - 1; 2367 if (slot == -1) { 2368 SIDBG0(SIDBG_VERBOSE, si_ctlp, 2369 "si_claim_free_slot: no empty slots"); 2370 return (SI_FAILURE); 2371 } 2372 2373 si_portp->siport_pending_tags |= (0x1 << slot); 2374 SIDBG1(SIDBG_VERBOSE, si_ctlp, "si_claim_free_slot: found slot: 0x%x", 2375 slot); 2376 return (slot); 2377 } 2378 2379 /* 2380 * Builds the PRB for the sata packet and delivers it to controller. 2381 * 2382 * Returns: 2383 * slot number if we can obtain a slot successfully 2384 * otherwise, return SI_FAILURE 2385 * 2386 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2387 * before calling us. 2388 */ 2389 static int 2390 si_deliver_satapkt( 2391 si_ctl_state_t *si_ctlp, 2392 si_port_state_t *si_portp, 2393 int port, 2394 sata_pkt_t *spkt) 2395 { 2396 int slot; 2397 si_prb_t *prb; 2398 sata_cmd_t *cmd; 2399 si_sge_t *sgep; /* scatter gather entry pointer */ 2400 si_sgt_t *sgtp; /* scatter gather table pointer */ 2401 si_sgblock_t *sgbp; /* scatter gather block pointer */ 2402 int i, j, cookie_index; 2403 int ncookies; 2404 int is_atapi = 0; 2405 ddi_dma_cookie_t cookie; 2406 2407 _NOTE(ASSUMING_PROTECTED(si_portp)) 2408 2409 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2410 if (slot == -1) { 2411 return (SI_FAILURE); 2412 } 2413 2414 if (spkt->satapkt_device.satadev_type == SATA_DTYPE_ATAPICD) { 2415 is_atapi = 1; 2416 } 2417 2418 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 2419 !si_portp->siport_active) { 2420 /* 2421 * si_intr_phy_ready_change() may have rendered it to 2422 * PORT_TYPE_NODEV. cfgadm operation may have rendered 2423 * it inactive. 2424 */ 2425 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2426 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 2427 2428 return (SI_FAILURE); 2429 } 2430 2431 2432 prb = &(si_portp->siport_prbpool[slot]); 2433 bzero((void *)prb, sizeof (si_prb_t)); 2434 2435 cmd = &spkt->satapkt_cmd; 2436 2437 SIDBG4(SIDBG_ENTRY, si_ctlp, 2438 "si_deliver_satpkt entry: cmd_reg: 0x%x, slot: 0x%x, \ 2439 port: %x, satapkt: %x", 2440 cmd->satacmd_cmd_reg, slot, port, (uint32_t)(intptr_t)spkt); 2441 2442 /* Now fill the prb. */ 2443 if (is_atapi) { 2444 if (spkt->satapkt_cmd.satacmd_flags == SATA_DIR_READ) { 2445 SET_PRB_CONTROL_PKT_READ(prb); 2446 } else if (spkt->satapkt_cmd.satacmd_flags == SATA_DIR_WRITE) { 2447 SET_PRB_CONTROL_PKT_WRITE(prb); 2448 } 2449 } 2450 2451 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 2452 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 2453 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 2454 SET_FIS_PMP(prb->prb_fis, 2455 spkt->satapkt_device.satadev_addr.pmport); 2456 } 2457 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 2458 SET_FIS_COMMAND(prb->prb_fis, cmd->satacmd_cmd_reg); 2459 SET_FIS_FEATURES(prb->prb_fis, cmd->satacmd_features_reg); 2460 SET_FIS_SECTOR_COUNT(prb->prb_fis, cmd->satacmd_sec_count_lsb); 2461 2462 switch (cmd->satacmd_addr_type) { 2463 2464 case ATA_ADDR_LBA: 2465 /* fallthru */ 2466 2467 case ATA_ADDR_LBA28: 2468 /* LBA[7:0] */ 2469 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2470 2471 /* LBA[15:8] */ 2472 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2473 2474 /* LBA[23:16] */ 2475 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2476 2477 /* LBA [27:24] (also called dev_head) */ 2478 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2479 2480 break; 2481 2482 case ATA_ADDR_LBA48: 2483 /* LBA[7:0] */ 2484 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2485 2486 /* LBA[15:8] */ 2487 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2488 2489 /* LBA[23:16] */ 2490 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2491 2492 /* LBA [31:24] */ 2493 SET_FIS_SECTOR_EXP(prb->prb_fis, cmd->satacmd_lba_low_msb); 2494 2495 /* LBA [39:32] */ 2496 SET_FIS_CYL_LOW_EXP(prb->prb_fis, cmd->satacmd_lba_mid_msb); 2497 2498 /* LBA [47:40] */ 2499 SET_FIS_CYL_HI_EXP(prb->prb_fis, cmd->satacmd_lba_high_msb); 2500 2501 /* Set dev_head */ 2502 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2503 2504 /* Set the extended sector count and features */ 2505 SET_FIS_SECTOR_COUNT_EXP(prb->prb_fis, 2506 cmd->satacmd_sec_count_msb); 2507 SET_FIS_FEATURES_EXP(prb->prb_fis, 2508 cmd->satacmd_features_reg_ext); 2509 2510 break; 2511 2512 } 2513 2514 if (cmd->satacmd_flags & SATA_QUEUED_CMD) { 2515 /* 2516 * For queued commands, the TAG for the sector count lsb is 2517 * generated from current slot number. 2518 */ 2519 SET_FIS_SECTOR_COUNT(prb->prb_fis, slot << 3); 2520 } 2521 2522 if ((cmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) || 2523 (cmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED)) { 2524 si_portp->siport_pending_ncq_count++; 2525 } 2526 2527 /* *** now fill the scatter gather list ******* */ 2528 2529 if (is_atapi) { /* It is an ATAPI drive */ 2530 /* atapi command goes into sge0 */ 2531 bcopy(cmd->satacmd_acdb, &prb->prb_sge0, sizeof (si_sge_t)); 2532 2533 /* Now fill sge1 with pointer to external SGT. */ 2534 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2535 prb->prb_sge1.sge_addr = 2536 si_portp->siport_sgbpool_physaddr + 2537 slot*sizeof (si_sgblock_t); 2538 SET_SGE_LNK(prb->prb_sge1); 2539 } else { 2540 SET_SGE_TRM(prb->prb_sge1); 2541 } 2542 } else { 2543 /* Fill the sge0 */ 2544 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2545 prb->prb_sge0.sge_addr = 2546 si_portp->siport_sgbpool_physaddr + 2547 slot*sizeof (si_sgblock_t); 2548 SET_SGE_LNK(prb->prb_sge0); 2549 2550 } else { 2551 SET_SGE_TRM(prb->prb_sge0); 2552 } 2553 2554 /* sge1 is left empty in non-ATAPI case */ 2555 } 2556 2557 bzero(&si_portp->siport_sgbpool[slot], sizeof (si_sgblock_t)); 2558 2559 ncookies = spkt->satapkt_cmd.satacmd_num_dma_cookies; 2560 ASSERT(ncookies <= SI_MAX_SGL_LENGTH); 2561 2562 SIDBG1(SIDBG_COOKIES, si_ctlp, "total ncookies: %d", ncookies); 2563 if (ncookies == 0) { 2564 sgbp = &si_portp->siport_sgbpool[slot]; 2565 sgtp = &sgbp->sgb_sgt[0]; 2566 sgep = &sgtp->sgt_sge[0]; 2567 2568 /* No cookies. Terminate the chain. */ 2569 SIDBG0(SIDBG_COOKIES, si_ctlp, "empty cookies: terminating."); 2570 2571 sgep->sge_addr_low = 0; 2572 sgep->sge_addr_high = 0; 2573 sgep->sge_data_count = 0; 2574 SET_SGE_TRM((*sgep)); 2575 2576 goto sgl_fill_done; 2577 } 2578 2579 for (i = 0, cookie_index = 0, sgbp = &si_portp->siport_sgbpool[slot]; 2580 i < SI_MAX_SGT_TABLES_PER_PRB; i++) { 2581 2582 sgtp = &sgbp->sgb_sgt[i]; 2583 2584 /* Now fill the first 3 entries of SGT in the loop below. */ 2585 for (j = 0, sgep = &sgtp->sgt_sge[0]; 2586 ((j < 3) && (cookie_index < ncookies-1)); 2587 j++, cookie_index++, sgep++) { 2588 ASSERT(cookie_index < ncookies); 2589 SIDBG2(SIDBG_COOKIES, si_ctlp, 2590 "inner loop: cookie_index: %d, ncookies: %d", 2591 cookie_index, 2592 ncookies); 2593 cookie = spkt->satapkt_cmd. 2594 satacmd_dma_cookie_list[cookie_index]; 2595 2596 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2597 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2598 sgep->sge_data_count = cookie.dmac_size; 2599 } 2600 2601 /* 2602 * If this happens to be the last cookie, we terminate it here. 2603 * Otherwise, we link to next SGT. 2604 */ 2605 2606 if (cookie_index == ncookies-1) { 2607 /* This is the last cookie. Terminate the chain. */ 2608 SIDBG2(SIDBG_COOKIES, si_ctlp, 2609 "filling the last: cookie_index: %d, " 2610 "ncookies: %d", 2611 cookie_index, 2612 ncookies); 2613 cookie = spkt->satapkt_cmd. 2614 satacmd_dma_cookie_list[cookie_index]; 2615 2616 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2617 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2618 sgep->sge_data_count = cookie.dmac_size; 2619 SET_SGE_TRM((*sgep)); 2620 2621 break; /* we break the loop */ 2622 2623 } else { 2624 /* This is not the last one. So link it. */ 2625 SIDBG2(SIDBG_COOKIES, si_ctlp, 2626 "linking SGT: cookie_index: %d, ncookies: %d", 2627 cookie_index, 2628 ncookies); 2629 sgep->sge_addr = si_portp->siport_sgbpool_physaddr + 2630 slot * sizeof (si_sgblock_t) + 2631 (i+1) * sizeof (si_sgt_t); 2632 2633 SET_SGE_LNK((*sgep)); 2634 } 2635 2636 } 2637 2638 /* *** finished filling the scatter gather list ******* */ 2639 2640 sgl_fill_done: 2641 /* Now remember the sata packet in siport_slot_pkts[]. */ 2642 si_portp->siport_slot_pkts[slot] = spkt; 2643 2644 /* 2645 * We are overloading satapkt_hba_driver_private with 2646 * watched_cycle count. 2647 */ 2648 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 2649 2650 if (is_atapi) { 2651 /* program the packet_lenth if it is atapi device. */ 2652 2653 2654 #ifdef ATAPI_2nd_PHASE 2655 /* 2656 * Framework needs to calculate the acdb_len based on 2657 * identify packet data. This needs to be accomplished 2658 * in second phase of the project. 2659 */ 2660 ASSERT((cmd->satacmd_acdb_len == 12) || 2661 (cmd->satacmd_acdb_len == 16)); 2662 SIDBG1(SIDBG_VERBOSE, si_ctlp, "deliver: acdb_len: %d", 2663 cmd->satacmd_acdb_len); 2664 2665 if (cmd->satacmd_acdb_len == 16) { 2666 ddi_put32(si_ctlp->sictl_port_acc_handle, 2667 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 2668 PORT_CONTROL_SET_BITS_PACKET_LEN); 2669 } else { 2670 ddi_put32(si_ctlp->sictl_port_acc_handle, 2671 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2672 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2673 } 2674 2675 #else /* ATAPI_2nd_PHASE */ 2676 /* hard coding for now to 12 bytes */ 2677 ddi_put32(si_ctlp->sictl_port_acc_handle, 2678 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2679 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2680 #endif /* ATAPI_2nd_PHASE */ 2681 } 2682 2683 2684 #if SI_DEBUG 2685 if (si_debug_flags & SIDBG_DUMP_PRB) { 2686 if (!(is_atapi && (prb->prb_sge0.sge_addr_low == 0))) { 2687 /* 2688 * Do not dump the atapi Test-Unit-Ready commands. 2689 * The sd_media_watch spews too many of these. 2690 */ 2691 int *ptr; 2692 si_sge_t *tmpsgep; 2693 int j; 2694 2695 ptr = (int *)prb; 2696 cmn_err(CE_WARN, "si_deliver_satpkt prb: "); 2697 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 2698 cmn_err(CE_WARN, "%x ", ptr[j]); 2699 } 2700 2701 cmn_err(CE_WARN, 2702 "si_deliver_satpkt sgt: low, high, count link"); 2703 for (j = 0, 2704 tmpsgep = (si_sge_t *) 2705 &si_portp->siport_sgbpool[slot]; 2706 j < (sizeof (si_sgblock_t)/ sizeof (si_sge_t)); 2707 j++, tmpsgep++) { 2708 ptr = (int *)tmpsgep; 2709 cmn_err(CE_WARN, "%x %x %x %x", 2710 ptr[0], 2711 ptr[1], 2712 ptr[2], 2713 ptr[3]); 2714 if (IS_SGE_TRM_SET((*tmpsgep))) { 2715 break; 2716 } 2717 2718 } 2719 } 2720 2721 } 2722 #endif /* SI_DEBUG */ 2723 2724 /* Deliver PRB */ 2725 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2726 2727 return (slot); 2728 } 2729 2730 /* 2731 * Initialize the controller and set up driver data structures. 2732 * 2733 * This routine can be called from three separate cases: DDI_ATTACH, PM_LEVEL_D0 2734 * and DDI_RESUME. The DDI_ATTACH case is different from other two cases; the 2735 * memory allocation & device signature probing are attempted only during 2736 * DDI_ATTACH case. In the case of PM_LEVEL_D0 & DDI_RESUME, we are starting 2737 * from a previously initialized state; so there is no need to allocate memory 2738 * or to attempt probing the device signatures. 2739 */ 2740 static int 2741 si_initialize_controller(si_ctl_state_t *si_ctlp) 2742 { 2743 uint32_t port_status; 2744 uint32_t SStatus; 2745 uint32_t SControl; 2746 int port; 2747 int loop_count = 0; 2748 si_port_state_t *si_portp; 2749 2750 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 2751 "si3124: si_initialize_controller entered"); 2752 2753 mutex_enter(&si_ctlp->sictl_mutex); 2754 2755 /* Remove the Global Reset. */ 2756 ddi_put32(si_ctlp->sictl_global_acc_handle, 2757 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 2758 GLOBAL_CONTROL_REG_BITS_CLEAR); 2759 2760 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 2761 2762 if (si_ctlp->sictl_flags & SI_ATTACH) { 2763 /* 2764 * We allocate the port state only during attach 2765 * sequence. We don't want to do it during 2766 * suspend/resume sequence. 2767 */ 2768 if (si_alloc_port_state(si_ctlp, port)) { 2769 mutex_exit(&si_ctlp->sictl_mutex); 2770 return (SI_FAILURE); 2771 } 2772 } 2773 2774 si_portp = si_ctlp->sictl_ports[port]; 2775 mutex_enter(&si_portp->siport_mutex); 2776 2777 /* Clear Port Reset. */ 2778 ddi_put32(si_ctlp->sictl_port_acc_handle, 2779 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2780 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 2781 2782 /* 2783 * Arm the interrupts for: Cmd completion, Cmd error, 2784 * Port Ready, PM Change, PhyRdyChange, Commwake, 2785 * UnrecFIS, Devxchanged, SDBNotify. 2786 */ 2787 ddi_put32(si_ctlp->sictl_port_acc_handle, 2788 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 2789 (INTR_COMMAND_COMPLETE | 2790 INTR_COMMAND_ERROR | 2791 INTR_PORT_READY | 2792 INTR_POWER_CHANGE | 2793 INTR_PHYRDY_CHANGE | 2794 INTR_COMWAKE_RECEIVED | 2795 INTR_UNRECOG_FIS | 2796 INTR_DEV_XCHANGED | 2797 INTR_SETDEVBITS_NOTIFY)); 2798 2799 /* Now enable the interrupts. */ 2800 si_enable_port_interrupts(si_ctlp, port); 2801 2802 /* 2803 * The following PHY initialization is redundant in 2804 * in x86 since the BIOS anyway does this as part of 2805 * device enumeration during the power up. But this 2806 * is a required step in sparc since there is no BIOS. 2807 * 2808 * The way to initialize the PHY is to write a 1 and then 2809 * a 0 to DET field of SControl register. 2810 */ 2811 2812 /* 2813 * Fetch the current SControl before writing the 2814 * DET part with 1 2815 */ 2816 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2817 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2818 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 2819 ddi_put32(si_ctlp->sictl_port_acc_handle, 2820 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2821 SControl); 2822 #ifndef __lock_lint 2823 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 2824 #endif /* __lock_lint */ 2825 2826 /* 2827 * Now fetch the SControl again and rewrite the 2828 * DET part with 0 2829 */ 2830 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2831 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2832 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 2833 ddi_put32(si_ctlp->sictl_port_acc_handle, 2834 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2835 SControl); 2836 2837 /* 2838 * PHY may be initialized by now. Check the DET field of 2839 * SStatus to determine if there is a device present. 2840 * 2841 * The DET field is valid only if IPM field indicates that 2842 * the interface is in active state. 2843 */ 2844 2845 loop_count = 0; 2846 do { 2847 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 2848 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 2849 2850 if (SSTATUS_GET_IPM(SStatus) != 2851 SSTATUS_IPM_INTERFACE_ACTIVE) { 2852 /* 2853 * If the interface is not active, the DET field 2854 * is considered not accurate. So we want to 2855 * continue looping. 2856 */ 2857 SSTATUS_SET_DET(SStatus, 2858 SSTATUS_DET_NODEV_NOPHY); 2859 } 2860 2861 if (loop_count++ > SI_POLLRATE_SSTATUS) { 2862 /* 2863 * We are effectively timing out after 0.1 sec. 2864 */ 2865 break; 2866 } 2867 2868 /* Wait for 10 millisec */ 2869 #ifndef __lock_lint 2870 delay(SI_10MS_TICKS); 2871 #endif /* __lock_lint */ 2872 2873 } while (SSTATUS_GET_DET(SStatus) != 2874 SSTATUS_DET_DEVPRESENT_PHYONLINE); 2875 2876 SIDBG2(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2877 "si_initialize_controller: 1st loop count: %d, " 2878 "SStatus: 0x%x", 2879 loop_count, 2880 SStatus); 2881 2882 if ((SSTATUS_GET_IPM(SStatus) != 2883 SSTATUS_IPM_INTERFACE_ACTIVE) || 2884 (SSTATUS_GET_DET(SStatus) != 2885 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 2886 /* 2887 * Either the port is not active or there 2888 * is no device present. 2889 */ 2890 si_ctlp->sictl_ports[port]->siport_port_type = 2891 PORT_TYPE_NODEV; 2892 mutex_exit(&si_portp->siport_mutex); 2893 continue; 2894 } 2895 2896 /* Wait until Port Ready */ 2897 loop_count = 0; 2898 do { 2899 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2900 (uint32_t *)PORT_STATUS(si_ctlp, port)); 2901 2902 if (loop_count++ > SI_POLLRATE_PORTREADY) { 2903 /* 2904 * We are effectively timing out after 0.5 sec. 2905 */ 2906 break; 2907 } 2908 2909 /* Wait for 10 millisec */ 2910 #ifndef __lock_lint 2911 delay(SI_10MS_TICKS); 2912 #endif /* __lock_lint */ 2913 2914 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 2915 2916 SIDBG1(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2917 "si_initialize_controller: 2nd loop count: %d", 2918 loop_count); 2919 2920 if (si_ctlp->sictl_flags & SI_ATTACH) { 2921 /* 2922 * We want to probe for dev signature only during attach 2923 * case. Don't do it during suspend/resume sequence. 2924 */ 2925 if (port_status & PORT_STATUS_BITS_PORT_READY) { 2926 mutex_exit(&si_portp->siport_mutex); 2927 si_find_dev_signature(si_ctlp, si_portp, port, 2928 PORTMULT_CONTROL_PORT); 2929 mutex_enter(&si_portp->siport_mutex); 2930 } else { 2931 si_ctlp->sictl_ports[port]->siport_port_type = 2932 PORT_TYPE_NODEV; 2933 } 2934 } 2935 2936 mutex_exit(&si_portp->siport_mutex); 2937 } 2938 2939 mutex_exit(&si_ctlp->sictl_mutex); 2940 return (SI_SUCCESS); 2941 } 2942 2943 /* 2944 * Reverse of si_initialize_controller(). 2945 * 2946 * WARNING, WARNING: The caller is expected to obtain the sictl_mutex 2947 * before calling us. 2948 */ 2949 static void 2950 si_deinititalize_controller(si_ctl_state_t *si_ctlp) 2951 { 2952 int port; 2953 2954 _NOTE(ASSUMING_PROTECTED(si_ctlp)) 2955 2956 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 2957 "si3124: si_deinititalize_controller entered"); 2958 2959 /* disable all the interrupts. */ 2960 si_disable_all_interrupts(si_ctlp); 2961 2962 if (si_ctlp->sictl_flags & SI_DETACH) { 2963 /* 2964 * We want to dealloc all the memory in detach case. 2965 */ 2966 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 2967 si_dealloc_port_state(si_ctlp, port); 2968 } 2969 } 2970 2971 } 2972 2973 /* 2974 * Prepare the port ready for usage. 2975 * 2976 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2977 * before calling us. 2978 */ 2979 static void 2980 si_init_port(si_ctl_state_t *si_ctlp, int port) 2981 { 2982 2983 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 2984 "si_init_port entered: port: 0x%x", 2985 port); 2986 2987 /* Initialize the port. */ 2988 ddi_put32(si_ctlp->sictl_port_acc_handle, 2989 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 2990 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 2991 2992 /* 2993 * Clear the InterruptNCOR (Interupt No Clear on Read). 2994 * This step ensures that a mere reading of slot_status will clear 2995 * the interrupt; no explicit clearing of interrupt condition 2996 * will be needed for successful completion of commands. 2997 */ 2998 ddi_put32(si_ctlp->sictl_port_acc_handle, 2999 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3000 PORT_CONTROL_CLEAR_BITS_INTR_NCoR); 3001 3002 /* clear any pending interrupts at this point */ 3003 ddi_put32(si_ctlp->sictl_port_acc_handle, 3004 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3005 INTR_MASK); 3006 3007 } 3008 3009 3010 /* 3011 * Enumerate the devices connected to the port multiplier. 3012 * Once a device is detected, we call si_find_dev_signature() 3013 * to find the type of device connected. Even though we are 3014 * called from within si_find_dev_signature(), there is no 3015 * recursion possible. 3016 */ 3017 static int 3018 si_enumerate_port_multiplier( 3019 si_ctl_state_t *si_ctlp, 3020 si_port_state_t *si_portp, 3021 int port) 3022 { 3023 uint32_t num_dev_ports = 0; 3024 int pmport; 3025 uint32_t SControl = 0; 3026 uint32_t SStatus = 0; 3027 uint32_t SError = 0; 3028 int loop_count = 0; 3029 3030 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 3031 "si_enumerate_port_multiplier entered: port: %d", 3032 port); 3033 3034 mutex_enter(&si_portp->siport_mutex); 3035 3036 /* Enable Port Multiplier context switching. */ 3037 ddi_put32(si_ctlp->sictl_port_acc_handle, 3038 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3039 PORT_CONTROL_SET_BITS_PM_ENABLE); 3040 3041 /* 3042 * Read the num dev ports connected. 3043 * GSCR[2] contains the number of device ports. 3044 */ 3045 if (si_read_portmult_reg(si_ctlp, si_portp, port, PORTMULT_CONTROL_PORT, 3046 PSCR_REG2, &num_dev_ports)) { 3047 mutex_exit(&si_portp->siport_mutex); 3048 return (SI_FAILURE); 3049 } 3050 si_portp->siport_portmult_state.sipm_num_ports = num_dev_ports; 3051 3052 SIDBG1(SIDBG_INIT, si_ctlp, 3053 "si_enumerate_port_multiplier: ports found: %d", 3054 num_dev_ports); 3055 3056 for (pmport = 0; pmport < num_dev_ports-1; pmport++) { 3057 /* 3058 * Enable PHY by writing a 1, then a 0 to SControl 3059 * (i.e. PSCR[2]) DET field. 3060 */ 3061 if (si_read_portmult_reg(si_ctlp, si_portp, port, pmport, 3062 PSCR_REG2, &SControl)) { 3063 continue; 3064 } 3065 3066 /* First write a 1 to DET field of SControl. */ 3067 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 3068 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3069 PSCR_REG2, SControl)) { 3070 continue; 3071 } 3072 #ifndef __lock_lint 3073 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 3074 #endif /* __lock_lint */ 3075 3076 /* Then write a 0 to the DET field of SControl. */ 3077 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 3078 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3079 PSCR_REG2, SControl)) { 3080 continue; 3081 } 3082 3083 /* Wait for PHYRDY by polling SStatus (i.e. PSCR[0]). */ 3084 loop_count = 0; 3085 do { 3086 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3087 pmport, PSCR_REG0, &SStatus)) { 3088 break; 3089 } 3090 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3091 "looping for PHYRDY: SStatus: %x", 3092 SStatus); 3093 3094 if (SSTATUS_GET_IPM(SStatus) != 3095 SSTATUS_IPM_INTERFACE_ACTIVE) { 3096 /* 3097 * If the interface is not active, the DET field 3098 * is considered not accurate. So we want to 3099 * continue looping. 3100 */ 3101 SSTATUS_SET_DET(SStatus, 3102 SSTATUS_DET_NODEV_NOPHY); 3103 } 3104 3105 if (loop_count++ > SI_POLLRATE_SSTATUS) { 3106 /* 3107 * We are effectively timing out after 0.1 sec. 3108 */ 3109 break; 3110 } 3111 3112 /* Wait for 10 millisec */ 3113 #ifndef __lock_lint 3114 delay(SI_10MS_TICKS); 3115 #endif /* __lock_lint */ 3116 3117 } while (SSTATUS_GET_DET(SStatus) != 3118 SSTATUS_DET_DEVPRESENT_PHYONLINE); 3119 3120 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 3121 "si_enumerate_port_multiplier: " 3122 "loop count: %d, SStatus: 0x%x", 3123 loop_count, 3124 SStatus); 3125 3126 if ((SSTATUS_GET_IPM(SStatus) == 3127 SSTATUS_IPM_INTERFACE_ACTIVE) && 3128 (SSTATUS_GET_DET(SStatus) == 3129 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 3130 /* The interface is active and the device is present */ 3131 SIDBG1(SIDBG_INIT, si_ctlp, 3132 "Status: %x, device exists", 3133 SStatus); 3134 /* 3135 * Clear error bits in SError register (i.e. PSCR[1] 3136 * by writing back error bits. 3137 */ 3138 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3139 pmport, PSCR_REG1, &SError)) { 3140 continue; 3141 } 3142 SIDBG1(SIDBG_INIT, si_ctlp, 3143 "SError bits are: %x", SError); 3144 if (si_write_portmult_reg(si_ctlp, si_portp, port, 3145 pmport, PSCR_REG1, SError)) { 3146 continue; 3147 } 3148 3149 /* There exists a device. */ 3150 mutex_exit(&si_portp->siport_mutex); 3151 si_find_dev_signature(si_ctlp, si_portp, port, pmport); 3152 mutex_enter(&si_portp->siport_mutex); 3153 } 3154 } 3155 3156 mutex_exit(&si_portp->siport_mutex); 3157 3158 return (SI_SUCCESS); 3159 } 3160 3161 3162 /* 3163 * Read a port multiplier register. 3164 * 3165 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3166 * before calling us. 3167 */ 3168 static int 3169 si_read_portmult_reg( 3170 si_ctl_state_t *si_ctlp, 3171 si_port_state_t *si_portp, 3172 int port, 3173 int pmport, 3174 int regnum, 3175 uint32_t *regval) 3176 { 3177 int slot; 3178 si_prb_t *prb; 3179 uint32_t *prb_word_ptr; 3180 int i; 3181 uint32_t slot_status; 3182 int loop_count = 0; 3183 3184 _NOTE(ASSUMING_PROTECTED(si_portp)) 3185 3186 SIDBG3(SIDBG_ENTRY, si_ctlp, "si_read_portmult_reg: port: %x," 3187 "pmport: %x, regnum: %x", 3188 port, pmport, regnum); 3189 3190 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3191 if (slot == -1) { 3192 return (SI_FAILURE); 3193 } 3194 3195 prb = &(si_portp->siport_prbpool[slot]); 3196 bzero((void *)prb, sizeof (si_prb_t)); 3197 3198 /* Now fill the prb. */ 3199 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3200 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3201 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3202 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_PM_REG); 3203 3204 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3205 SET_FIS_FEATURES(prb->prb_fis, regnum); 3206 3207 /* no real data transfer is involved. */ 3208 SET_SGE_TRM(prb->prb_sge0); 3209 3210 #if SI_DEBUG 3211 if (si_debug_flags & SIDBG_DUMP_PRB) { 3212 int *ptr; 3213 int j; 3214 3215 ptr = (int *)prb; 3216 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3217 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3218 cmn_err(CE_WARN, "%x ", ptr[j]); 3219 } 3220 3221 } 3222 #endif /* SI_DEBUG */ 3223 3224 /* Deliver PRB */ 3225 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3226 3227 /* Loop till the command is finished. */ 3228 do { 3229 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3230 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3231 3232 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3233 "looping read_pm slot_status: 0x%x", 3234 slot_status); 3235 3236 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3237 /* We are effectively timing out after 0.5 sec. */ 3238 break; 3239 } 3240 3241 /* Wait for 10 millisec */ 3242 #ifndef __lock_lint 3243 delay(SI_10MS_TICKS); 3244 #endif /* __lock_lint */ 3245 3246 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3247 3248 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3249 "read_portmult_reg: loop count: %d", 3250 loop_count); 3251 3252 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3253 3254 /* Now inspect the port LRAM for the modified FIS. */ 3255 prb_word_ptr = (uint32_t *)prb; 3256 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3257 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3258 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3259 } 3260 3261 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3262 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3263 /* command failed. */ 3264 return (SI_FAILURE); 3265 } 3266 3267 /* command succeeded. */ 3268 *regval = (GET_FIS_SECTOR_COUNT(prb->prb_fis) & 0xff) | 3269 ((GET_FIS_SECTOR(prb->prb_fis) << 8) & 0xff00) | 3270 ((GET_FIS_CYL_LOW(prb->prb_fis) << 16) & 0xff0000) | 3271 ((GET_FIS_CYL_HI(prb->prb_fis) << 24) & 0xff000000); 3272 3273 return (SI_SUCCESS); 3274 } 3275 3276 /* 3277 * Write a port multiplier register. 3278 * 3279 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3280 * before calling us. 3281 */ 3282 static int 3283 si_write_portmult_reg( 3284 si_ctl_state_t *si_ctlp, 3285 si_port_state_t *si_portp, 3286 int port, 3287 int pmport, 3288 int regnum, 3289 uint32_t regval) 3290 { 3291 int slot; 3292 si_prb_t *prb; 3293 uint32_t *prb_word_ptr; 3294 uint32_t slot_status; 3295 int i; 3296 int loop_count = 0; 3297 3298 _NOTE(ASSUMING_PROTECTED(si_portp)) 3299 3300 SIDBG4(SIDBG_ENTRY, si_ctlp, 3301 "si_write_portmult_reg: port: %x, pmport: %x," 3302 "regnum: %x, regval: %x", 3303 port, pmport, regnum, regval); 3304 3305 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3306 if (slot == -1) { 3307 return (SI_FAILURE); 3308 } 3309 3310 prb = &(si_portp->siport_prbpool[slot]); 3311 bzero((void *)prb, sizeof (si_prb_t)); 3312 3313 /* Now fill the prb. */ 3314 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3315 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3316 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3317 3318 SET_FIS_COMMAND(prb->prb_fis, SATAC_WRITE_PM_REG); 3319 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3320 SET_FIS_FEATURES(prb->prb_fis, regnum); 3321 3322 SET_FIS_SECTOR_COUNT(prb->prb_fis, regval & 0xff); 3323 SET_FIS_SECTOR(prb->prb_fis, (regval >> 8) & 0xff); 3324 SET_FIS_CYL_LOW(prb->prb_fis, (regval >> 16) & 0xff); 3325 SET_FIS_CYL_HI(prb->prb_fis, (regval >> 24) & 0xff); 3326 3327 /* no real data transfer is involved. */ 3328 SET_SGE_TRM(prb->prb_sge0); 3329 3330 #if SI_DEBUG 3331 if (si_debug_flags & SIDBG_DUMP_PRB) { 3332 int *ptr; 3333 int j; 3334 3335 ptr = (int *)prb; 3336 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3337 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3338 cmn_err(CE_WARN, "%x ", ptr[j]); 3339 } 3340 3341 } 3342 #endif /* SI_DEBUG */ 3343 3344 /* Deliver PRB */ 3345 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3346 3347 /* Loop till the command is finished. */ 3348 do { 3349 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3350 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3351 3352 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3353 "looping write_pmp slot_status: 0x%x", 3354 slot_status); 3355 3356 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3357 /* We are effectively timing out after 0.5 sec. */ 3358 break; 3359 } 3360 3361 /* Wait for 10 millisec */ 3362 #ifndef __lock_lint 3363 delay(SI_10MS_TICKS); 3364 #endif /* __lock_lint */ 3365 3366 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3367 3368 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3369 "write_portmult_reg: loop count: %d", 3370 loop_count); 3371 3372 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3373 3374 /* Now inspect the port LRAM for the modified FIS. */ 3375 prb_word_ptr = (uint32_t *)prb; 3376 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3377 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3378 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3379 } 3380 3381 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3382 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3383 /* command failed */ 3384 return (SI_FAILURE); 3385 } 3386 3387 /* command succeeded */ 3388 return (SI_SUCCESS); 3389 } 3390 3391 3392 /* 3393 * Set the auto sense data for ATAPI devices. 3394 * 3395 * Note: Currently the sense data is simulated; this code will be enhanced 3396 * in second phase to fetch the real sense data from the atapi device. 3397 */ 3398 static void 3399 si_set_sense_data(sata_pkt_t *satapkt, int reason) 3400 { 3401 struct scsi_extended_sense *sense; 3402 3403 sense = (struct scsi_extended_sense *) 3404 satapkt->satapkt_cmd.satacmd_rqsense; 3405 bzero(sense, sizeof (struct scsi_extended_sense)); 3406 sense->es_valid = 1; /* Valid sense */ 3407 sense->es_class = 7; /* Response code 0x70 - current err */ 3408 sense->es_key = 0; 3409 sense->es_info_1 = 0; 3410 sense->es_info_2 = 0; 3411 sense->es_info_3 = 0; 3412 sense->es_info_4 = 0; 3413 sense->es_add_len = 6; /* Additional length */ 3414 sense->es_cmd_info[0] = 0; 3415 sense->es_cmd_info[1] = 0; 3416 sense->es_cmd_info[2] = 0; 3417 sense->es_cmd_info[3] = 0; 3418 sense->es_add_code = 0; 3419 sense->es_qual_code = 0; 3420 3421 if ((reason == SATA_PKT_DEV_ERROR) || (reason == SATA_PKT_TIMEOUT)) { 3422 sense->es_key = KEY_HARDWARE_ERROR; 3423 } 3424 } 3425 3426 3427 /* 3428 * Interrupt service handler. We loop through each of the ports to find 3429 * if the interrupt belongs to any of them. 3430 * 3431 * Bulk of the interrupt handling is actually done out of subroutines 3432 * like si_intr_command_complete() etc. 3433 */ 3434 /*ARGSUSED*/ 3435 static uint_t 3436 si_intr(caddr_t arg1, caddr_t arg2) 3437 { 3438 3439 si_ctl_state_t *si_ctlp = (si_ctl_state_t *)arg1; 3440 si_port_state_t *si_portp; 3441 uint32_t global_intr_status; 3442 uint32_t mask, port_intr_status; 3443 int port; 3444 3445 global_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3446 (uint32_t *)GLOBAL_INTERRUPT_STATUS(si_ctlp)); 3447 3448 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3449 "si_intr: global_int_status: 0x%x", 3450 global_intr_status); 3451 3452 if (!(global_intr_status & SI31xx_INTR_PORT_MASK)) { 3453 /* Sorry, the interrupt is not ours. */ 3454 return (DDI_INTR_UNCLAIMED); 3455 } 3456 3457 /* Loop for all the ports. */ 3458 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 3459 3460 mask = 0x1 << port; 3461 if (!(global_intr_status & mask)) { 3462 continue; 3463 } 3464 3465 mutex_enter(&si_ctlp->sictl_mutex); 3466 si_portp = si_ctlp->sictl_ports[port]; 3467 mutex_exit(&si_ctlp->sictl_mutex); 3468 3469 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3470 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 3471 3472 SIDBG2(SIDBG_VERBOSE, si_ctlp, 3473 "s_intr: port_intr_status: 0x%x, port: %x", 3474 port_intr_status, 3475 port); 3476 3477 if (port_intr_status & INTR_COMMAND_COMPLETE) { 3478 (void) si_intr_command_complete(si_ctlp, si_portp, 3479 port); 3480 } 3481 3482 /* Clear the interrupts */ 3483 ddi_put32(si_ctlp->sictl_port_acc_handle, 3484 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3485 port_intr_status & INTR_MASK); 3486 3487 /* 3488 * Note that we did not clear the interrupt for command 3489 * completion interrupt. Reading of slot_status takes care 3490 * of clearing the interrupt for command completion case. 3491 */ 3492 3493 if (port_intr_status & INTR_COMMAND_ERROR) { 3494 (void) si_intr_command_error(si_ctlp, si_portp, port); 3495 } 3496 3497 if (port_intr_status & INTR_PORT_READY) { 3498 (void) si_intr_port_ready(si_ctlp, si_portp, port); 3499 } 3500 3501 if (port_intr_status & INTR_POWER_CHANGE) { 3502 (void) si_intr_pwr_change(si_ctlp, si_portp, port); 3503 } 3504 3505 if (port_intr_status & INTR_PHYRDY_CHANGE) { 3506 (void) si_intr_phy_ready_change(si_ctlp, si_portp, 3507 port); 3508 } 3509 3510 if (port_intr_status & INTR_COMWAKE_RECEIVED) { 3511 (void) si_intr_comwake_rcvd(si_ctlp, si_portp, 3512 port); 3513 } 3514 3515 if (port_intr_status & INTR_UNRECOG_FIS) { 3516 (void) si_intr_unrecognised_fis(si_ctlp, si_portp, 3517 port); 3518 } 3519 3520 if (port_intr_status & INTR_DEV_XCHANGED) { 3521 (void) si_intr_dev_xchanged(si_ctlp, si_portp, port); 3522 } 3523 3524 if (port_intr_status & INTR_8B10B_DECODE_ERROR) { 3525 (void) si_intr_decode_err_threshold(si_ctlp, si_portp, 3526 port); 3527 } 3528 3529 if (port_intr_status & INTR_CRC_ERROR) { 3530 (void) si_intr_crc_err_threshold(si_ctlp, si_portp, 3531 port); 3532 } 3533 3534 if (port_intr_status & INTR_HANDSHAKE_ERROR) { 3535 (void) si_intr_handshake_err_threshold(si_ctlp, 3536 si_portp, port); 3537 } 3538 3539 if (port_intr_status & INTR_SETDEVBITS_NOTIFY) { 3540 (void) si_intr_set_devbits_notify(si_ctlp, si_portp, 3541 port); 3542 } 3543 } 3544 3545 return (DDI_INTR_CLAIMED); 3546 } 3547 3548 /* 3549 * Interrupt which indicates that one or more commands have successfully 3550 * completed. 3551 * 3552 * Since we disabled W1C (write-one-to-clear) previously, mere reading 3553 * of slot_status register clears the interrupt. There is no need to 3554 * explicitly clear the interrupt. 3555 */ 3556 static int 3557 si_intr_command_complete( 3558 si_ctl_state_t *si_ctlp, 3559 si_port_state_t *si_portp, 3560 int port) 3561 { 3562 3563 uint32_t slot_status; 3564 uint32_t finished_tags; 3565 int finished_slot; 3566 sata_pkt_t *satapkt; 3567 3568 SIDBG0(SIDBG_ENTRY|SIDBG_INTR, si_ctlp, 3569 "si_intr_command_complete enter"); 3570 3571 mutex_enter(&si_portp->siport_mutex); 3572 3573 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3574 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3575 3576 if (!si_portp->siport_pending_tags) { 3577 /* 3578 * Spurious interrupt. Nothing to be done. 3579 * Do read the slot_status to clear the interrupt. 3580 */ 3581 mutex_exit(&si_portp->siport_mutex); 3582 return (SI_SUCCESS); 3583 } 3584 3585 SIDBG2(SIDBG_VERBOSE, si_ctlp, "si3124: si_intr_command_complete: " 3586 "pending_tags: %x, slot_status: %x", 3587 si_portp->siport_pending_tags, 3588 slot_status); 3589 3590 finished_tags = si_portp->siport_pending_tags & 3591 ~slot_status & SI_SLOT_MASK; 3592 while (finished_tags) { 3593 finished_slot = ddi_ffs(finished_tags) - 1; 3594 if (finished_slot == -1) { 3595 break; 3596 } 3597 3598 satapkt = si_portp->siport_slot_pkts[finished_slot]; 3599 3600 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 3601 3602 CLEAR_BIT(si_portp->siport_pending_tags, finished_slot); 3603 CLEAR_BIT(finished_tags, finished_slot); 3604 } 3605 3606 SIDBG2(SIDBG_PKTCOMP, si_ctlp, 3607 "command_complete done: pend_tags: 0x%x, slot_status: 0x%x", 3608 si_portp->siport_pending_tags, 3609 slot_status); 3610 3611 /* 3612 * tidbit: no need to clear the interrupt since reading of 3613 * slot_status automatically clears the interrupt in the case 3614 * of a successful command completion. 3615 */ 3616 3617 mutex_exit(&si_portp->siport_mutex); 3618 3619 return (SI_SUCCESS); 3620 } 3621 3622 /* 3623 * Interrupt which indicates that a command did not complete successfully. 3624 * 3625 * The port halts whenever a command error interrupt is received. 3626 * The only way to restart it is to reset or reinitialize the port 3627 * but such an operation throws away all the pending commands on 3628 * the port. 3629 * 3630 * We reset the device and mop the commands on the port. 3631 */ 3632 static int 3633 si_intr_command_error( 3634 si_ctl_state_t *si_ctlp, 3635 si_port_state_t *si_portp, 3636 int port) 3637 { 3638 uint32_t command_error, slot_status; 3639 uint32_t failed_tags; 3640 3641 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3642 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3643 3644 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3645 "si_intr_command_error: command_error: 0x%x", 3646 command_error); 3647 3648 mutex_enter(&si_portp->siport_mutex); 3649 3650 /* 3651 * Remember the slot_status since any of the recovery handler 3652 * can blow it away with reset operation. 3653 */ 3654 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3655 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3656 3657 si_log_error_message(si_ctlp, port, command_error); 3658 3659 switch (command_error) { 3660 3661 case CMD_ERR_DEVICEERRROR: 3662 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3663 break; 3664 3665 case CMD_ERR_SDBERROR: 3666 si_error_recovery_SDBERROR(si_ctlp, si_portp, port); 3667 break; 3668 3669 case CMD_ERR_DATAFISERROR: 3670 si_error_recovery_DATAFISERROR(si_ctlp, si_portp, port); 3671 break; 3672 3673 case CMD_ERR_SENDFISERROR: 3674 si_error_recovery_SENDFISERROR(si_ctlp, si_portp, port); 3675 break; 3676 3677 default: 3678 si_error_recovery_default(si_ctlp, si_portp, port); 3679 break; 3680 3681 } 3682 3683 /* 3684 * Compute the failed_tags by adding up the error tags. 3685 * 3686 * The siport_err_tags_SDBERROR and siport_err_tags_nonSDBERROR 3687 * were filled in by the si_error_recovery_* routines. 3688 */ 3689 failed_tags = si_portp->siport_pending_tags & 3690 (si_portp->siport_err_tags_SDBERROR | 3691 si_portp->siport_err_tags_nonSDBERROR); 3692 3693 SIDBG3(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si_intr_command_error: " 3694 "err_tags_SDBERROR: 0x%x, " 3695 "err_tags_nonSDBERRROR: 0x%x, " 3696 "failed_tags: 0x%x", 3697 si_portp->siport_err_tags_SDBERROR, 3698 si_portp->siport_err_tags_nonSDBERROR, 3699 failed_tags); 3700 3701 SIDBG2(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si3124: si_intr_command_error: " 3702 "slot_status:0x%x, pending_tags: 0x%x", 3703 slot_status, 3704 si_portp->siport_pending_tags); 3705 3706 mutex_exit(&si_portp->siport_mutex); 3707 si_mop_commands(si_ctlp, 3708 si_portp, 3709 port, 3710 slot_status, 3711 failed_tags, 3712 0, /* timedout_tags */ 3713 0, /* aborting_tags */ 3714 0); /* reset_tags */ 3715 mutex_enter(&si_portp->siport_mutex); 3716 3717 ASSERT(si_portp->siport_pending_tags == 0); 3718 3719 si_portp->siport_err_tags_SDBERROR = 0; 3720 si_portp->siport_err_tags_nonSDBERROR = 0; 3721 3722 mutex_exit(&si_portp->siport_mutex); 3723 3724 return (SI_SUCCESS); 3725 } 3726 3727 /* 3728 * There is a subtle difference between errors on a normal port and 3729 * a port-mult port. When an error happens on a normal port, the port 3730 * is halted effectively until the port is reset or initialized. 3731 * However, in port-mult port errors, port does not get halted since 3732 * other non-error devices behind the port multiplier can still 3733 * continue to operate. So we wait till all the commands are drained 3734 * instead of resetting it right away. 3735 * 3736 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3737 * before calling us. 3738 */ 3739 static void 3740 si_recover_portmult_errors( 3741 si_ctl_state_t *si_ctlp, 3742 si_port_state_t *si_portp, 3743 int port) 3744 { 3745 uint32_t command_error, slot_status, port_status; 3746 int failed_slot; 3747 int loop_count = 0; 3748 3749 _NOTE(ASSUMING_PROTECTED(si_portp)) 3750 3751 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3752 "si_recover_portmult_errors: port: 0x%x", 3753 port); 3754 3755 /* Resume the port */ 3756 ddi_put32(si_ctlp->sictl_port_acc_handle, 3757 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3758 PORT_CONTROL_SET_BITS_RESUME); 3759 3760 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3761 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3762 3763 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3764 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3765 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3766 3767 if (command_error == CMD_ERR_SDBERROR) { 3768 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3769 } else { 3770 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3771 } 3772 3773 /* Now we drain the pending commands. */ 3774 do { 3775 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3776 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3777 3778 /* 3779 * Since we have not yet returned DDI_INTR_CLAIMED, 3780 * our interrupt handler is guaranteed not to be called again. 3781 * So we need to check IS_ATTENTION_RAISED() for further 3782 * decisions. 3783 * 3784 * This is a too big a delay for an interrupt context. 3785 * But this is supposed to be a rare condition. 3786 */ 3787 3788 if (IS_ATTENTION_RAISED(slot_status)) { 3789 /* Resume again */ 3790 ddi_put32(si_ctlp->sictl_port_acc_handle, 3791 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3792 PORT_CONTROL_SET_BITS_RESUME); 3793 3794 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3795 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3796 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3797 command_error = ddi_get32( 3798 si_ctlp->sictl_port_acc_handle, 3799 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, 3800 port))); 3801 if (command_error == CMD_ERR_SDBERROR) { 3802 si_portp->siport_err_tags_SDBERROR |= 3803 (0x1 << failed_slot); 3804 } else { 3805 si_portp->siport_err_tags_nonSDBERROR |= 3806 (0x1 << failed_slot); 3807 } 3808 } 3809 3810 if (loop_count++ > SI_POLLRATE_RECOVERPORTMULT) { 3811 /* We are effectively timing out after 10 sec. */ 3812 break; 3813 } 3814 3815 /* Wait for 10 millisec */ 3816 #ifndef __lock_lint 3817 delay(SI_10MS_TICKS); 3818 #endif /* __lock_lint */ 3819 3820 } while (slot_status & SI_SLOT_MASK); 3821 3822 /* 3823 * The above loop can be improved for 3132 since we could obtain the 3824 * Port Multiplier Context of the device in error. Then we could 3825 * do a better job in filtering out commands for the device in error. 3826 * The loop could finish much earlier with such a logic. 3827 */ 3828 3829 /* Clear the RESUME bit. */ 3830 ddi_put32(si_ctlp->sictl_port_acc_handle, 3831 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3832 PORT_CONTROL_CLEAR_BITS_RESUME); 3833 3834 } 3835 3836 /* 3837 * If we are connected to port multiplier, drain the non-failed devices. 3838 * Otherwise, we initialize the port (which effectively fails all the 3839 * pending commands in the hope that sd would retry them later). 3840 * 3841 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3842 * before calling us. 3843 */ 3844 static void 3845 si_error_recovery_DEVICEERROR( 3846 si_ctl_state_t *si_ctlp, 3847 si_port_state_t *si_portp, 3848 int port) 3849 { 3850 uint32_t port_status; 3851 int failed_slot; 3852 3853 _NOTE(ASSUMING_PROTECTED(si_portp)) 3854 3855 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3856 "si_error_recovery_DEVICEERROR: port: 0x%x", 3857 port); 3858 3859 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3860 si_recover_portmult_errors(si_ctlp, si_portp, port); 3861 } else { 3862 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3863 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3864 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3865 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3866 } 3867 3868 /* In either case (port-mult or not), we reinitialize the port. */ 3869 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3870 } 3871 3872 /* 3873 * Handle exactly like DEVICEERROR. Remember the tags with SDBERROR 3874 * to perform read_log_ext on them later. SDBERROR means that the 3875 * error was for an NCQ command. 3876 * 3877 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3878 * before calling us. 3879 */ 3880 static void 3881 si_error_recovery_SDBERROR( 3882 si_ctl_state_t *si_ctlp, 3883 si_port_state_t *si_portp, 3884 int port) 3885 { 3886 uint32_t port_status; 3887 int failed_slot; 3888 3889 _NOTE(ASSUMING_PROTECTED(si_portp)) 3890 3891 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3892 "si3124: si_error_recovery_SDBERROR: port: 0x%x", 3893 port); 3894 3895 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3896 si_recover_portmult_errors(si_ctlp, si_portp, port); 3897 } else { 3898 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3899 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3900 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3901 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3902 } 3903 3904 /* In either case (port-mult or not), we reinitialize the port. */ 3905 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3906 } 3907 3908 /* 3909 * Handle exactly like DEVICEERROR except resetting the port if there was 3910 * an NCQ command on the port. 3911 * 3912 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3913 * before calling us. 3914 */ 3915 static void 3916 si_error_recovery_DATAFISERROR( 3917 si_ctl_state_t *si_ctlp, 3918 si_port_state_t *si_portp, 3919 int port) 3920 { 3921 uint32_t port_status; 3922 int failed_slot; 3923 3924 _NOTE(ASSUMING_PROTECTED(si_portp)) 3925 3926 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3927 "si3124: si_error_recovery_DATAFISERROR: port: 0x%x", 3928 port); 3929 3930 /* reset device if we were waiting for any ncq commands. */ 3931 if (si_portp->siport_pending_ncq_count) { 3932 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3933 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3934 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3935 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3936 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 3937 SI_DEVICE_RESET); 3938 return; 3939 } 3940 3941 /* 3942 * If we don't have any ncq commands pending, the rest of 3943 * the process is similar to the one for DEVICEERROR. 3944 */ 3945 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3946 } 3947 3948 /* 3949 * We handle just like DEVICERROR except that we reset the device instead 3950 * of initializing the port. 3951 * 3952 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3953 * before calling us. 3954 */ 3955 static void 3956 si_error_recovery_SENDFISERROR( 3957 si_ctl_state_t *si_ctlp, 3958 si_port_state_t *si_portp, 3959 int port) 3960 { 3961 uint32_t port_status; 3962 int failed_slot; 3963 3964 _NOTE(ASSUMING_PROTECTED(si_portp)) 3965 3966 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3967 "si3124: si_error_recovery_SENDFISERROR: port: 0x%x", 3968 port); 3969 3970 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3971 si_recover_portmult_errors(si_ctlp, si_portp, port); 3972 } else { 3973 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3974 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3975 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3976 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3977 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 3978 SI_DEVICE_RESET); 3979 } 3980 } 3981 3982 /* 3983 * The default behavior for all other errors is to reset the device. 3984 * 3985 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3986 * before calling us. 3987 */ 3988 static void 3989 si_error_recovery_default( 3990 si_ctl_state_t *si_ctlp, 3991 si_port_state_t *si_portp, 3992 int port) 3993 { 3994 uint32_t port_status; 3995 int failed_slot; 3996 3997 _NOTE(ASSUMING_PROTECTED(si_portp)) 3998 3999 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 4000 "si3124: si_error_recovery_default: port: 0x%x", 4001 port); 4002 4003 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4004 (uint32_t *)PORT_STATUS(si_ctlp, port)); 4005 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 4006 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 4007 4008 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 4009 SI_DEVICE_RESET); 4010 } 4011 4012 /* 4013 * Read Log Ext with PAGE 10 to retrieve the error for an NCQ command. 4014 * 4015 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4016 * before calling us. 4017 */ 4018 static uint8_t 4019 si_read_log_ext(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 4020 { 4021 int slot; 4022 si_prb_t *prb; 4023 int i; 4024 uint32_t slot_status; 4025 int loop_count = 0; 4026 uint32_t *prb_word_ptr; 4027 uint8_t error; 4028 4029 _NOTE(ASSUMING_PROTECTED(si_portp)) 4030 4031 SIDBG1(SIDBG_ENTRY|SIDBG_ERRS, si_ctlp, 4032 "si_read_log_ext: port: %x", port); 4033 4034 slot = si_claim_free_slot(si_ctlp, si_portp, port); 4035 if (slot == -1) { 4036 return (0); 4037 } 4038 4039 prb = &(si_portp->siport_prbpool[slot]); 4040 bzero((void *)prb, sizeof (si_prb_t)); 4041 4042 /* Now fill the prb */ 4043 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 4044 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 4045 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 4046 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_LOG_EXT); 4047 SET_FIS_SECTOR(prb->prb_fis, SATA_LOG_PAGE_10); 4048 4049 /* no real data transfer is involved */ 4050 SET_SGE_TRM(prb->prb_sge0); 4051 4052 #if SI_DEBUG 4053 if (si_debug_flags & SIDBG_DUMP_PRB) { 4054 int *ptr; 4055 int j; 4056 4057 ptr = (int *)prb; 4058 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 4059 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 4060 cmn_err(CE_WARN, "%x ", ptr[j]); 4061 } 4062 4063 } 4064 #endif /* SI_DEBUG */ 4065 4066 /* Deliver PRB */ 4067 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 4068 4069 /* Loop till the command is finished. */ 4070 do { 4071 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4072 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 4073 4074 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4075 "looping read_log_ext slot_status: 0x%x", 4076 slot_status); 4077 4078 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 4079 /* We are effectively timing out after 0.5 sec. */ 4080 break; 4081 } 4082 4083 /* Wait for 10 millisec */ 4084 #ifndef __lock_lint 4085 delay(SI_10MS_TICKS); 4086 #endif /* __lock_lint */ 4087 4088 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 4089 4090 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 4091 /* 4092 * If we fail with the READ LOG EXT command, we need to 4093 * initialize the port to clear the slot_status register. 4094 * We don't need to worry about any other valid commands 4095 * being thrown away because we are already in recovery 4096 * mode and READ LOG EXT is the only pending command. 4097 */ 4098 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 4099 } 4100 4101 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4102 "read_portmult_reg: loop count: %d", 4103 loop_count); 4104 4105 /* 4106 * The LRAM contains the the modified FIS. 4107 * Read the modified FIS to obtain the Error. 4108 */ 4109 prb_word_ptr = (uint32_t *)prb; 4110 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 4111 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 4112 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 4113 } 4114 error = GET_FIS_FEATURES(prb->prb_fis); 4115 4116 CLEAR_BIT(si_portp->siport_pending_tags, slot); 4117 4118 return (error); 4119 4120 } 4121 4122 /* 4123 * Dump the error message to the log. 4124 */ 4125 static void 4126 si_log_error_message(si_ctl_state_t *si_ctlp, int port, uint32_t command_error) 4127 { 4128 char *errstr; 4129 4130 switch (command_error) { 4131 4132 case CMD_ERR_DEVICEERRROR: 4133 errstr = "Standard Error: Error bit set in register - device" 4134 " to host FIS"; 4135 break; 4136 4137 case CMD_ERR_SDBERROR: 4138 errstr = "NCQ Error: Error bit set in register - device" 4139 " to host FIS"; 4140 break; 4141 4142 case CMD_ERR_DATAFISERROR: 4143 errstr = "Error in data FIS not detected by device"; 4144 break; 4145 4146 case CMD_ERR_SENDFISERROR: 4147 errstr = "Initial command FIS transmission failed"; 4148 break; 4149 4150 case CMD_ERR_INCONSISTENTSTATE: 4151 errstr = "Inconsistency in protocol"; 4152 break; 4153 4154 case CMD_ERR_DIRECTIONERROR: 4155 errstr = "DMA direction flag does not match the command"; 4156 break; 4157 4158 case CMD_ERR_UNDERRUNERROR: 4159 errstr = "Run out of scatter gather entries while writing data"; 4160 break; 4161 4162 case CMD_ERR_OVERRUNERROR: 4163 errstr = "Run out of scatter gather entries while reading data"; 4164 break; 4165 4166 case CMD_ERR_PACKETPROTOCOLERROR: 4167 errstr = "Packet protocol error"; 4168 break; 4169 4170 case CMD_ERR_PLDSGTERRORBOUNDARY: 4171 errstr = "Scatter/gather table not on quadword boundary"; 4172 break; 4173 4174 case CMD_ERR_PLDSGTERRORTARETABORT: 4175 errstr = "PCI(X) Target abort while fetching scatter/gather" 4176 " table"; 4177 break; 4178 4179 case CMD_ERR_PLDSGTERRORMASTERABORT: 4180 errstr = "PCI(X) Master abort while fetching scatter/gather" 4181 " table"; 4182 break; 4183 4184 case CMD_ERR_PLDSGTERRORPCIERR: 4185 errstr = "PCI(X) parity error while fetching scatter/gather" 4186 " table"; 4187 break; 4188 4189 case CMD_ERR_PLDCMDERRORBOUNDARY: 4190 errstr = "PRB not on quadword boundary"; 4191 break; 4192 4193 case CMD_ERR_PLDCMDERRORTARGETABORT: 4194 errstr = "PCI(X) Target abort while fetching PRB"; 4195 break; 4196 4197 case CMD_ERR_PLDCMDERRORMASTERABORT: 4198 errstr = "PCI(X) Master abort while fetching PRB"; 4199 break; 4200 4201 case CMD_ERR_PLDCMDERORPCIERR: 4202 errstr = "PCI(X) parity error while fetching PRB"; 4203 break; 4204 4205 case CMD_ERR_PSDERRORTARGETABORT: 4206 errstr = "PCI(X) Target abort during data transfer"; 4207 break; 4208 4209 case CMD_ERR_PSDERRORMASTERABORT: 4210 errstr = "PCI(X) Master abort during data transfer"; 4211 break; 4212 4213 case CMD_ERR_PSDERRORPCIERR: 4214 errstr = "PCI(X) parity error during data transfer"; 4215 break; 4216 4217 case CMD_ERR_SENDSERVICEERROR: 4218 errstr = "FIS received while sending service FIS in" 4219 " legacy queuing operation"; 4220 break; 4221 4222 default: 4223 errstr = "Unknown Error"; 4224 break; 4225 4226 } 4227 4228 SIDBG2(SIDBG_ERRS, si_ctlp, 4229 "command error: port: 0x%x, error: %s", 4230 port, 4231 errstr); 4232 4233 } 4234 4235 4236 /* 4237 * Interrupt which indicates that the Port Ready state has changed 4238 * from zero to one. 4239 * 4240 * We are not interested in this interrupt; we just log a debug message. 4241 */ 4242 /*ARGSUSED*/ 4243 static int 4244 si_intr_port_ready( 4245 si_ctl_state_t *si_ctlp, 4246 si_port_state_t *si_portp, 4247 int port) 4248 { 4249 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_ready"); 4250 return (SI_SUCCESS); 4251 } 4252 4253 /* 4254 * Interrupt which indicates that the port power management state 4255 * has been modified. 4256 * 4257 * We are not interested in this interrupt; we just log a debug message. 4258 */ 4259 /*ARGSUSED*/ 4260 static int 4261 si_intr_pwr_change( 4262 si_ctl_state_t *si_ctlp, 4263 si_port_state_t *si_portp, 4264 int port) 4265 { 4266 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_pwr_change"); 4267 return (SI_SUCCESS); 4268 } 4269 4270 /* 4271 * Interrupt which indicates that the PHY sate has changed either from 4272 * Not-Ready to Ready or from Ready to Not-Ready. 4273 */ 4274 static int 4275 si_intr_phy_ready_change( 4276 si_ctl_state_t *si_ctlp, 4277 si_port_state_t *si_portp, 4278 int port) 4279 { 4280 sata_device_t sdevice; 4281 uint32_t SStatus = 0; /* No dev present & PHY not established. */ 4282 int dev_exists_now = 0; 4283 int dev_existed_previously = 0; 4284 4285 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_phy_rdy_change"); 4286 4287 mutex_enter(&si_ctlp->sictl_mutex); 4288 if ((si_ctlp->sictl_sata_hba_tran == NULL) || (si_portp == NULL)) { 4289 /* the whole controller setup is not yet done. */ 4290 mutex_exit(&si_ctlp->sictl_mutex); 4291 return (SI_SUCCESS); 4292 } 4293 4294 mutex_exit(&si_ctlp->sictl_mutex); 4295 4296 mutex_enter(&si_portp->siport_mutex); 4297 4298 /* SStatus tells the presence of device. */ 4299 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4300 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 4301 dev_exists_now = 4302 (SSTATUS_GET_DET(SStatus) == SSTATUS_DET_DEVPRESENT_PHYONLINE); 4303 4304 if (si_portp->siport_port_type != PORT_TYPE_NODEV) { 4305 dev_existed_previously = 1; 4306 } 4307 4308 bzero((void *)&sdevice, sizeof (sata_device_t)); 4309 sdevice.satadev_addr.cport = port; 4310 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 4311 4312 /* we don't have a way of determining the exact port-mult port. */ 4313 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 4314 sdevice.satadev_addr.qual = SATA_ADDR_PMPORT; 4315 } else { 4316 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4317 } 4318 4319 sdevice.satadev_state = SATA_PSTATE_PWRON; 4320 4321 if (dev_exists_now) { 4322 if (dev_existed_previously) { 4323 4324 /* Things are fine now. The loss was temporary. */ 4325 SIDBG0(SIDBG_INTR, NULL, 4326 "phyrdy: doing BOTH EVENTS TOGETHER"); 4327 if (si_portp->siport_active) { 4328 SIDBG0(SIDBG_EVENT, si_ctlp, 4329 "sending event: LINK_LOST & " 4330 "LINK_ESTABLISHED"); 4331 4332 sata_hba_event_notify( 4333 si_ctlp->sictl_sata_hba_tran->\ 4334 sata_tran_hba_dip, 4335 &sdevice, 4336 SATA_EVNT_LINK_LOST| 4337 SATA_EVNT_LINK_ESTABLISHED); 4338 } 4339 4340 } else { 4341 4342 /* A new device has been detected. */ 4343 mutex_exit(&si_portp->siport_mutex); 4344 si_find_dev_signature(si_ctlp, si_portp, port, 4345 PORTMULT_CONTROL_PORT); 4346 mutex_enter(&si_portp->siport_mutex); 4347 SIDBG0(SIDBG_INTR, NULL, "phyrdy: doing ATTACH event"); 4348 if (si_portp->siport_active) { 4349 SIDBG0(SIDBG_EVENT, si_ctlp, 4350 "sending event up: LINK_ESTABLISHED"); 4351 4352 sata_hba_event_notify( 4353 si_ctlp->sictl_sata_hba_tran->\ 4354 sata_tran_hba_dip, 4355 &sdevice, 4356 SATA_EVNT_LINK_ESTABLISHED); 4357 } 4358 4359 } 4360 } else { /* No device exists now */ 4361 4362 if (dev_existed_previously) { 4363 4364 /* An existing device is lost. */ 4365 if (si_portp->siport_active) { 4366 SIDBG0(SIDBG_EVENT, si_ctlp, 4367 "sending event up: LINK_LOST"); 4368 4369 sata_hba_event_notify( 4370 si_ctlp->sictl_sata_hba_tran-> 4371 sata_tran_hba_dip, 4372 &sdevice, 4373 SATA_EVNT_LINK_LOST); 4374 } 4375 si_portp->siport_port_type = PORT_TYPE_NODEV; 4376 4377 } else { 4378 4379 /* spurious interrupt */ 4380 SIDBG0(SIDBG_INTR, NULL, 4381 "spurious phy ready interrupt"); 4382 } 4383 } 4384 4385 mutex_exit(&si_portp->siport_mutex); 4386 return (SI_SUCCESS); 4387 } 4388 4389 4390 /* 4391 * Interrupt which indicates that a COMWAKE OOB signal has been decoded 4392 * on the receiver. 4393 * 4394 * We are not interested in this interrupt; we just log a debug message. 4395 */ 4396 /*ARGSUSED*/ 4397 static int 4398 si_intr_comwake_rcvd( 4399 si_ctl_state_t *si_ctlp, 4400 si_port_state_t *si_portp, 4401 int port) 4402 { 4403 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_commwake_rcvd"); 4404 return (SI_SUCCESS); 4405 } 4406 4407 /* 4408 * Interrupt which indicates that the F-bit has been set in SError 4409 * Diag field. 4410 * 4411 * We are not interested in this interrupt; we just log a debug message. 4412 */ 4413 /*ARGSUSED*/ 4414 static int 4415 si_intr_unrecognised_fis( 4416 si_ctl_state_t *si_ctlp, 4417 si_port_state_t *si_portp, 4418 int port) 4419 { 4420 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_unrecognised_fis"); 4421 return (SI_SUCCESS); 4422 } 4423 4424 /* 4425 * Interrupt which indicates that the X-bit has been set in SError 4426 * Diag field. 4427 * 4428 * We are not interested in this interrupt; we just log a debug message. 4429 */ 4430 /*ARGSUSED*/ 4431 static int 4432 si_intr_dev_xchanged( 4433 si_ctl_state_t *si_ctlp, 4434 si_port_state_t *si_portp, 4435 int port) 4436 { 4437 4438 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_dev_xchanged"); 4439 return (SI_SUCCESS); 4440 } 4441 4442 /* 4443 * Interrupt which indicates that the 8b/10 Decode Error counter has 4444 * exceeded the programmed non-zero threshold value. 4445 * 4446 * We are not interested in this interrupt; we just log a debug message. 4447 */ 4448 /*ARGSUSED*/ 4449 static int 4450 si_intr_decode_err_threshold( 4451 si_ctl_state_t *si_ctlp, 4452 si_port_state_t *si_portp, 4453 int port) 4454 { 4455 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_err_threshold"); 4456 return (SI_SUCCESS); 4457 } 4458 4459 /* 4460 * Interrupt which indicates that the CRC Error counter has exceeded the 4461 * programmed non-zero threshold value. 4462 * 4463 * We are not interested in this interrupt; we just log a debug message. 4464 */ 4465 /*ARGSUSED*/ 4466 static int 4467 si_intr_crc_err_threshold( 4468 si_ctl_state_t *si_ctlp, 4469 si_port_state_t *si_portp, 4470 int port) 4471 { 4472 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_crc_threshold"); 4473 return (SI_SUCCESS); 4474 } 4475 4476 /* 4477 * Interrupt which indicates that the Handshake Error counter has 4478 * exceeded the programmed non-zero threshold value. 4479 * 4480 * We are not interested in this interrupt; we just log a debug message. 4481 */ 4482 /*ARGSUSED*/ 4483 static int 4484 si_intr_handshake_err_threshold( 4485 si_ctl_state_t *si_ctlp, 4486 si_port_state_t *si_portp, 4487 int port) 4488 { 4489 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 4490 "si_intr_handshake_err_threshold"); 4491 return (SI_SUCCESS); 4492 } 4493 4494 /* 4495 * Interrupt which indicates that a "Set Device Bits" FIS has been 4496 * received with N-bit set in the control field. 4497 * 4498 * We are not interested in this interrupt; we just log a debug message. 4499 */ 4500 /*ARGSUSED*/ 4501 static int 4502 si_intr_set_devbits_notify( 4503 si_ctl_state_t *si_ctlp, 4504 si_port_state_t *si_portp, 4505 int port) 4506 { 4507 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_set_devbits_notify"); 4508 return (SI_SUCCESS); 4509 } 4510 4511 4512 /* 4513 * Enable the interrupts for a particular port. 4514 * 4515 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4516 * before calling us. 4517 */ 4518 static void 4519 si_enable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4520 { 4521 uint32_t mask; 4522 4523 /* get the current settings first. */ 4524 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4525 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4526 4527 SIDBG1(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 4528 "si_enable_port_interrupts: current mask: 0x%x", 4529 mask); 4530 4531 /* enable the bit for current port. */ 4532 SET_BIT(mask, port); 4533 4534 /* now use this mask to enable the interrupt. */ 4535 ddi_put32(si_ctlp->sictl_global_acc_handle, 4536 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4537 mask); 4538 } 4539 4540 /* 4541 * Enable interrupts for all the ports. 4542 */ 4543 static void 4544 si_enable_all_interrupts(si_ctl_state_t *si_ctlp) 4545 { 4546 int port; 4547 4548 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4549 si_enable_port_interrupts(si_ctlp, port); 4550 } 4551 } 4552 4553 /* 4554 * Disable interrupts for a particular port. 4555 * 4556 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4557 * before calling us. 4558 */ 4559 static void 4560 si_disable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4561 { 4562 uint32_t mask; 4563 4564 /* get the current settings first. */ 4565 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4566 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4567 4568 /* clear the bit for current port. */ 4569 CLEAR_BIT(mask, port); 4570 4571 /* now use this mask to disable the interrupt. */ 4572 ddi_put32(si_ctlp->sictl_global_acc_handle, 4573 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4574 mask); 4575 4576 } 4577 4578 /* 4579 * Disable interrupts for all the ports. 4580 */ 4581 static void 4582 si_disable_all_interrupts(si_ctl_state_t *si_ctlp) 4583 { 4584 int port; 4585 4586 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4587 si_disable_port_interrupts(si_ctlp, port); 4588 } 4589 } 4590 4591 /* 4592 * Fetches the latest sstatus, scontrol, serror, sactive registers 4593 * and stuffs them into sata_device_t structure. 4594 */ 4595 static void 4596 fill_dev_sregisters(si_ctl_state_t *si_ctlp, int port, sata_device_t *satadev) 4597 { 4598 satadev->satadev_scr.sstatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4599 (uint32_t *)(PORT_SSTATUS(si_ctlp, port))); 4600 satadev->satadev_scr.serror = ddi_get32(si_ctlp->sictl_port_acc_handle, 4601 (uint32_t *)(PORT_SERROR(si_ctlp, port))); 4602 satadev->satadev_scr.sactive = ddi_get32(si_ctlp->sictl_port_acc_handle, 4603 (uint32_t *)(PORT_SACTIVE(si_ctlp, port))); 4604 satadev->satadev_scr.scontrol = 4605 ddi_get32(si_ctlp->sictl_port_acc_handle, 4606 (uint32_t *)(PORT_SCONTROL(si_ctlp, port))); 4607 4608 } 4609 4610 /* 4611 * si_add_legacy_intrs() handles INTx and legacy interrupts. 4612 */ 4613 static int 4614 si_add_legacy_intrs(si_ctl_state_t *si_ctlp) 4615 { 4616 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4617 int actual, count = 0; 4618 int x, y, rc, inum = 0; 4619 4620 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_add_legacy_intrs"); 4621 4622 /* get number of interrupts. */ 4623 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &count); 4624 if ((rc != DDI_SUCCESS) || (count == 0)) { 4625 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4626 "ddi_intr_get_nintrs() failed, " 4627 "rc %d count %d\n", rc, count); 4628 return (DDI_FAILURE); 4629 } 4630 4631 /* Allocate an array of interrupt handles. */ 4632 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4633 si_ctlp->sictl_htable = kmem_zalloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4634 4635 /* call ddi_intr_alloc(). */ 4636 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_FIXED, 4637 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 4638 4639 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4640 SIDBG1(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4641 "ddi_intr_alloc() failed, rc %d\n", rc); 4642 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4643 return (DDI_FAILURE); 4644 } 4645 4646 if (actual < count) { 4647 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4648 "Requested: %d, Received: %d", count, actual); 4649 4650 for (x = 0; x < actual; x++) { 4651 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4652 } 4653 4654 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4655 return (DDI_FAILURE); 4656 } 4657 4658 si_ctlp->sictl_intr_cnt = actual; 4659 4660 /* Get intr priority. */ 4661 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4662 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4663 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4664 "ddi_intr_get_pri() failed"); 4665 4666 for (x = 0; x < actual; x++) { 4667 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4668 } 4669 4670 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4671 return (DDI_FAILURE); 4672 } 4673 4674 /* Test for high level mutex. */ 4675 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4676 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4677 "si_add_legacy_intrs: Hi level intr not supported"); 4678 4679 for (x = 0; x < actual; x++) { 4680 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4681 } 4682 4683 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4684 4685 return (DDI_FAILURE); 4686 } 4687 4688 /* Call ddi_intr_add_handler(). */ 4689 for (x = 0; x < actual; x++) { 4690 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4691 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4692 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4693 "ddi_intr_add_handler() failed"); 4694 4695 for (y = 0; y < actual; y++) { 4696 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4697 } 4698 4699 kmem_free(si_ctlp->sictl_htable, 4700 si_ctlp->sictl_intr_size); 4701 return (DDI_FAILURE); 4702 } 4703 } 4704 4705 /* Call ddi_intr_enable() for legacy interrupts. */ 4706 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4707 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4708 } 4709 4710 return (DDI_SUCCESS); 4711 } 4712 4713 /* 4714 * si_add_msictl_intrs() handles MSI interrupts. 4715 */ 4716 static int 4717 si_add_msi_intrs(si_ctl_state_t *si_ctlp) 4718 { 4719 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4720 int count, avail, actual; 4721 int x, y, rc, inum = 0; 4722 4723 SIDBG0(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, "si_add_msi_intrs"); 4724 4725 /* get number of interrupts. */ 4726 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSI, &count); 4727 if ((rc != DDI_SUCCESS) || (count == 0)) { 4728 SIDBG2(SIDBG_INIT, si_ctlp, 4729 "ddi_intr_get_nintrs() failed, " 4730 "rc %d count %d\n", rc, count); 4731 return (DDI_FAILURE); 4732 } 4733 4734 /* get number of available interrupts. */ 4735 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSI, &avail); 4736 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4737 SIDBG2(SIDBG_INIT, si_ctlp, 4738 "ddi_intr_get_navail() failed, " 4739 "rc %d avail %d\n", rc, avail); 4740 return (DDI_FAILURE); 4741 } 4742 4743 if (avail < count) { 4744 SIDBG2(SIDBG_INIT, si_ctlp, 4745 "ddi_intr_get_nvail returned %d, navail() returned %d", 4746 count, avail); 4747 } 4748 4749 /* Allocate an array of interrupt handles. */ 4750 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4751 si_ctlp->sictl_htable = kmem_alloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4752 4753 /* call ddi_intr_alloc(). */ 4754 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_MSI, 4755 inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 4756 4757 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4758 SIDBG1(SIDBG_INIT, si_ctlp, 4759 "ddi_intr_alloc() failed, rc %d\n", rc); 4760 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4761 return (DDI_FAILURE); 4762 } 4763 4764 /* use interrupt count returned */ 4765 if (actual < count) { 4766 SIDBG2(SIDBG_INIT, si_ctlp, 4767 "Requested: %d, Received: %d", count, actual); 4768 } 4769 4770 si_ctlp->sictl_intr_cnt = actual; 4771 4772 /* 4773 * Get priority for first msi, assume remaining are all the same. 4774 */ 4775 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4776 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4777 SIDBG0(SIDBG_INIT, si_ctlp, "ddi_intr_get_pri() failed"); 4778 4779 /* Free already allocated intr. */ 4780 for (y = 0; y < actual; y++) { 4781 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4782 } 4783 4784 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4785 return (DDI_FAILURE); 4786 } 4787 4788 /* Test for high level mutex. */ 4789 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4790 SIDBG0(SIDBG_INIT, si_ctlp, 4791 "si_add_msi_intrs: Hi level intr not supported"); 4792 4793 /* Free already allocated intr. */ 4794 for (y = 0; y < actual; y++) { 4795 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4796 } 4797 4798 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4799 4800 return (DDI_FAILURE); 4801 } 4802 4803 /* Call ddi_intr_add_handler(). */ 4804 for (x = 0; x < actual; x++) { 4805 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4806 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4807 SIDBG0(SIDBG_INIT, si_ctlp, 4808 "ddi_intr_add_handler() failed"); 4809 4810 /* Free already allocated intr. */ 4811 for (y = 0; y < actual; y++) { 4812 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4813 } 4814 4815 kmem_free(si_ctlp->sictl_htable, 4816 si_ctlp->sictl_intr_size); 4817 return (DDI_FAILURE); 4818 } 4819 } 4820 4821 (void) ddi_intr_get_cap(si_ctlp->sictl_htable[0], 4822 &si_ctlp->sictl_intr_cap); 4823 4824 if (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 4825 /* Call ddi_intr_block_enable() for MSI. */ 4826 (void) ddi_intr_block_enable(si_ctlp->sictl_htable, 4827 si_ctlp->sictl_intr_cnt); 4828 } else { 4829 /* Call ddi_intr_enable() for MSI non block enable. */ 4830 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4831 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4832 } 4833 } 4834 4835 return (DDI_SUCCESS); 4836 } 4837 4838 /* 4839 * Removes the registered interrupts irrespective of whether they 4840 * were legacy or MSI. 4841 */ 4842 static void 4843 si_rem_intrs(si_ctl_state_t *si_ctlp) 4844 { 4845 int x; 4846 4847 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_rem_intrs entered"); 4848 4849 /* Disable all interrupts. */ 4850 if ((si_ctlp->sictl_intr_type == DDI_INTR_TYPE_MSI) && 4851 (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 4852 /* Call ddi_intr_block_disable(). */ 4853 (void) ddi_intr_block_disable(si_ctlp->sictl_htable, 4854 si_ctlp->sictl_intr_cnt); 4855 } else { 4856 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4857 (void) ddi_intr_disable(si_ctlp->sictl_htable[x]); 4858 } 4859 } 4860 4861 /* Call ddi_intr_remove_handler(). */ 4862 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4863 (void) ddi_intr_remove_handler(si_ctlp->sictl_htable[x]); 4864 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4865 } 4866 4867 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4868 } 4869 4870 /* 4871 * Resets either the port or the device connected to the port based on 4872 * the flag variable. 4873 * 4874 * The reset effectively throws away all the pending commands. So, the caller 4875 * has to make provision to handle the pending commands. 4876 * 4877 * After the reset, we wait till the port is ready again. 4878 * 4879 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4880 * before calling us. 4881 * 4882 * Note: Not port-mult aware. 4883 */ 4884 static int 4885 si_reset_dport_wait_till_ready( 4886 si_ctl_state_t *si_ctlp, 4887 si_port_state_t *si_portp, 4888 int port, 4889 int flag) 4890 { 4891 uint32_t port_status; 4892 int loop_count = 0; 4893 sata_device_t sdevice; 4894 uint32_t SStatus; 4895 uint32_t SControl; 4896 4897 _NOTE(ASSUMING_PROTECTED(si_portp)) 4898 4899 if (flag == SI_PORT_RESET) { 4900 ddi_put32(si_ctlp->sictl_port_acc_handle, 4901 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4902 PORT_CONTROL_SET_BITS_PORT_RESET); 4903 4904 /* Port reset is not self clearing. So clear it now. */ 4905 ddi_put32(si_ctlp->sictl_port_acc_handle, 4906 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 4907 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 4908 } else { 4909 /* Reset the device. */ 4910 ddi_put32(si_ctlp->sictl_port_acc_handle, 4911 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4912 PORT_CONTROL_SET_BITS_DEV_RESET); 4913 4914 /* 4915 * tidbit: this bit is self clearing; so there is no need 4916 * for manual clear as we did for port reset. 4917 */ 4918 } 4919 4920 /* Set the reset in progress flag */ 4921 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 4922 si_portp->siport_reset_in_progress = 1; 4923 } 4924 4925 /* 4926 * For some reason, we are losing the interrupt enablement after 4927 * any reset condition. So restore them back now. 4928 */ 4929 SIDBG1(SIDBG_INIT, si_ctlp, 4930 "current interrupt enable set: 0x%x", 4931 ddi_get32(si_ctlp->sictl_port_acc_handle, 4932 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port))); 4933 4934 ddi_put32(si_ctlp->sictl_port_acc_handle, 4935 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 4936 (INTR_COMMAND_COMPLETE | 4937 INTR_COMMAND_ERROR | 4938 INTR_PORT_READY | 4939 INTR_POWER_CHANGE | 4940 INTR_PHYRDY_CHANGE | 4941 INTR_COMWAKE_RECEIVED | 4942 INTR_UNRECOG_FIS | 4943 INTR_DEV_XCHANGED | 4944 INTR_SETDEVBITS_NOTIFY)); 4945 4946 si_enable_port_interrupts(si_ctlp, port); 4947 4948 /* 4949 * Every reset needs a PHY initialization. 4950 * 4951 * The way to initialize the PHY is to write a 1 and then 4952 * a 0 to DET field of SControl register. 4953 */ 4954 4955 /* Fetch the current SControl before writing the DET part with 1. */ 4956 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 4957 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 4958 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 4959 ddi_put32(si_ctlp->sictl_port_acc_handle, 4960 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 4961 SControl); 4962 #ifndef __lock_lint 4963 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 4964 #endif /* __lock_lint */ 4965 4966 /* Now fetch the SControl again and rewrite the DET part with 0 */ 4967 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 4968 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 4969 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 4970 ddi_put32(si_ctlp->sictl_port_acc_handle, 4971 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 4972 SControl); 4973 4974 /* 4975 * PHY may be initialized by now. Check the DET field of SStatus 4976 * to determine if there is a device present. 4977 * 4978 * The DET field is valid only if IPM field indicates that 4979 * the interface is in active state. 4980 */ 4981 4982 loop_count = 0; 4983 do { 4984 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4985 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 4986 4987 if (SSTATUS_GET_IPM(SStatus) != 4988 SSTATUS_IPM_INTERFACE_ACTIVE) { 4989 /* 4990 * If the interface is not active, the DET field 4991 * is considered not accurate. So we want to 4992 * continue looping. 4993 */ 4994 SSTATUS_SET_DET(SStatus, SSTATUS_DET_NODEV_NOPHY); 4995 } 4996 4997 if (loop_count++ > SI_POLLRATE_SSTATUS) { 4998 /* We are effectively timing out after 0.1 sec. */ 4999 break; 5000 } 5001 5002 /* Wait for 10 millisec */ 5003 #ifndef __lock_lint 5004 delay(SI_10MS_TICKS); 5005 #endif /* __lock_lint */ 5006 5007 } while (SSTATUS_GET_DET(SStatus) != SSTATUS_DET_DEVPRESENT_PHYONLINE); 5008 5009 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 5010 "si_reset_dport_wait_till_ready: loop count: %d, \ 5011 SStatus: 0x%x", 5012 loop_count, 5013 SStatus); 5014 5015 /* Now check for port readiness. */ 5016 loop_count = 0; 5017 do { 5018 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5019 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5020 5021 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5022 /* We are effectively timing out after 0.5 sec. */ 5023 break; 5024 } 5025 5026 /* Wait for 10 millisec */ 5027 #ifndef __lock_lint 5028 delay(SI_10MS_TICKS); 5029 #endif /* __lock_lint */ 5030 5031 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5032 5033 SIDBG3(SIDBG_POLL_LOOP, si_ctlp, 5034 "si_reset_dport_wait_till_ready: loop count: %d, \ 5035 port_status: 0x%x, SStatus: 0x%x", 5036 loop_count, 5037 port_status, 5038 SStatus); 5039 5040 /* Indicate to the framework that a reset has happened. */ 5041 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 5042 5043 bzero((void *)&sdevice, sizeof (sata_device_t)); 5044 sdevice.satadev_addr.cport = port; 5045 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 5046 5047 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 5048 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT; 5049 } else { 5050 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5051 } 5052 sdevice.satadev_state = SATA_DSTATE_RESET | 5053 SATA_DSTATE_PWR_ACTIVE; 5054 if (si_ctlp->sictl_sata_hba_tran) { 5055 sata_hba_event_notify( 5056 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 5057 &sdevice, 5058 SATA_EVNT_DEVICE_RESET); 5059 } 5060 5061 SIDBG0(SIDBG_EVENT, si_ctlp, 5062 "sending event up: SATA_EVNT_RESET"); 5063 } 5064 5065 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5066 (SSTATUS_GET_DET(SStatus) == 5067 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5068 /* The interface is active and the device is present */ 5069 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5070 /* But the port is is not ready for some reason */ 5071 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5072 "si_reset_dport_wait_till_ready failed"); 5073 return (SI_FAILURE); 5074 } 5075 } 5076 5077 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5078 "si_reset_dport_wait_till_ready returning success"); 5079 5080 return (SI_SUCCESS); 5081 } 5082 5083 /* 5084 * Initializes the port. 5085 * 5086 * Initialization effectively throws away all the pending commands on 5087 * the port. So, the caller has to make provision to handle the pending 5088 * commands. 5089 * 5090 * After the port initialization, we wait till the port is ready again. 5091 * 5092 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 5093 * before calling us. 5094 */ 5095 static int 5096 si_initialize_port_wait_till_ready(si_ctl_state_t *si_ctlp, int port) 5097 { 5098 uint32_t port_status; 5099 int loop_count = 0; 5100 uint32_t SStatus; 5101 5102 /* Initialize the port. */ 5103 ddi_put32(si_ctlp->sictl_port_acc_handle, 5104 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 5105 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 5106 5107 /* Wait until Port Ready */ 5108 loop_count = 0; 5109 do { 5110 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5111 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5112 5113 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5114 SIDBG1(SIDBG_INTR, si_ctlp, 5115 "si_initialize_port_wait is timing out: " 5116 "port_status: %x", 5117 port_status); 5118 /* We are effectively timing out after 0.5 sec. */ 5119 break; 5120 } 5121 5122 /* Wait for 10 millisec */ 5123 #ifndef __lock_lint 5124 delay(SI_10MS_TICKS); 5125 #endif /* __lock_lint */ 5126 5127 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5128 5129 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 5130 "si_initialize_port_wait_till_ready: loop count: %d", 5131 loop_count); 5132 5133 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 5134 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 5135 5136 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5137 (SSTATUS_GET_DET(SStatus) == 5138 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5139 /* The interface is active and the device is present */ 5140 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5141 /* But the port is is not ready for some reason */ 5142 return (SI_FAILURE); 5143 } 5144 } 5145 5146 return (SI_SUCCESS); 5147 } 5148 5149 5150 /* 5151 * si_watchdog_handler() calls us if it detects that there are some 5152 * commands which timed out. We recalculate the timed out commands once 5153 * again since some of them may have finished recently. 5154 */ 5155 static void 5156 si_timeout_pkts( 5157 si_ctl_state_t *si_ctlp, 5158 si_port_state_t *si_portp, 5159 int port, 5160 uint32_t timedout_tags) 5161 { 5162 uint32_t slot_status; 5163 uint32_t finished_tags; 5164 5165 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, "si_timeout_pkts entry"); 5166 5167 mutex_enter(&si_portp->siport_mutex); 5168 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5169 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 5170 5171 /* 5172 * Initialize the controller. The only way to timeout the commands 5173 * is to reset or initialize the controller. We mop commands after 5174 * the initialization. 5175 */ 5176 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 5177 5178 /* 5179 * Recompute the timedout tags since some of them may have finished 5180 * meanwhile. 5181 */ 5182 finished_tags = si_portp->siport_pending_tags & 5183 ~slot_status & SI_SLOT_MASK; 5184 timedout_tags &= ~finished_tags; 5185 5186 SIDBG2(SIDBG_TIMEOUT, si_ctlp, 5187 "si_timeout_pkts: finished: %x, timeout: %x", 5188 finished_tags, 5189 timedout_tags); 5190 5191 mutex_exit(&si_portp->siport_mutex); 5192 si_mop_commands(si_ctlp, 5193 si_portp, 5194 port, 5195 slot_status, 5196 0, /* failed_tags */ 5197 timedout_tags, 5198 0, /* aborting_tags */ 5199 0); /* reset_tags */ 5200 5201 } 5202 5203 5204 5205 /* 5206 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 5207 * for long time. 5208 */ 5209 static void 5210 si_watchdog_handler(si_ctl_state_t *si_ctlp) 5211 { 5212 uint32_t pending_tags = 0; 5213 uint32_t timedout_tags = 0; 5214 si_port_state_t *si_portp; 5215 int port; 5216 int tmpslot; 5217 sata_pkt_t *satapkt; 5218 5219 /* max number of cycles this packet should survive */ 5220 int max_life_cycles; 5221 5222 /* how many cycles this packet survived so far */ 5223 int watched_cycles; 5224 5225 mutex_enter(&si_ctlp->sictl_mutex); 5226 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, 5227 "si_watchdog_handler entered"); 5228 5229 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 5230 5231 si_portp = si_ctlp->sictl_ports[port]; 5232 if (si_portp == NULL) { 5233 continue; 5234 } 5235 5236 mutex_enter(&si_portp->siport_mutex); 5237 5238 if (si_portp->siport_port_type == PORT_TYPE_NODEV) { 5239 mutex_exit(&si_portp->siport_mutex); 5240 continue; 5241 } 5242 5243 pending_tags = si_portp->siport_pending_tags; 5244 timedout_tags = 0; 5245 while (pending_tags) { 5246 tmpslot = ddi_ffs(pending_tags) - 1; 5247 if (tmpslot == -1) { 5248 break; 5249 } 5250 satapkt = si_portp->siport_slot_pkts[tmpslot]; 5251 5252 if ((satapkt != NULL) && satapkt->satapkt_time) { 5253 5254 /* 5255 * We are overloading satapkt_hba_driver_private 5256 * with watched_cycle count. 5257 * 5258 * If a packet has survived for more than it's 5259 * max life cycles, it is a candidate for time 5260 * out. 5261 */ 5262 watched_cycles = (int)(intptr_t) 5263 satapkt->satapkt_hba_driver_private; 5264 watched_cycles++; 5265 max_life_cycles = (satapkt->satapkt_time + 5266 si_watchdog_timeout - 1) / 5267 si_watchdog_timeout; 5268 if (watched_cycles > max_life_cycles) { 5269 timedout_tags |= (0x1 << tmpslot); 5270 SIDBG1(SIDBG_TIMEOUT|SIDBG_VERBOSE, 5271 si_ctlp, 5272 "watchdog: timedout_tags: 0x%x", 5273 timedout_tags); 5274 } 5275 satapkt->satapkt_hba_driver_private = 5276 (void *)(intptr_t)watched_cycles; 5277 } 5278 5279 CLEAR_BIT(pending_tags, tmpslot); 5280 } 5281 5282 if (timedout_tags) { 5283 mutex_exit(&si_portp->siport_mutex); 5284 mutex_exit(&si_ctlp->sictl_mutex); 5285 si_timeout_pkts(si_ctlp, si_portp, port, timedout_tags); 5286 mutex_enter(&si_ctlp->sictl_mutex); 5287 mutex_enter(&si_portp->siport_mutex); 5288 } 5289 5290 mutex_exit(&si_portp->siport_mutex); 5291 } 5292 5293 /* Reinstall the watchdog timeout handler. */ 5294 if (!(si_ctlp->sictl_flags & SI_NO_TIMEOUTS)) { 5295 si_ctlp->sictl_timeout_id = 5296 timeout((void (*)(void *))si_watchdog_handler, 5297 (caddr_t)si_ctlp, si_watchdog_tick); 5298 } 5299 mutex_exit(&si_ctlp->sictl_mutex); 5300 } 5301 5302 5303 /* 5304 * Logs the message. 5305 */ 5306 static void 5307 si_log(si_ctl_state_t *si_ctlp, uint_t level, char *fmt, ...) 5308 { 5309 va_list ap; 5310 5311 mutex_enter(&si_log_mutex); 5312 5313 va_start(ap, fmt); 5314 if (si_ctlp) { 5315 (void) sprintf(si_log_buf, "%s-[%d]:", 5316 ddi_get_name(si_ctlp->sictl_devinfop), 5317 ddi_get_instance(si_ctlp->sictl_devinfop)); 5318 } else { 5319 (void) sprintf(si_log_buf, "si3124:"); 5320 } 5321 (void) vsprintf(si_log_buf, fmt, ap); 5322 va_end(ap); 5323 5324 cmn_err(level, "%s", si_log_buf); 5325 5326 mutex_exit(&si_log_mutex); 5327 5328 } 5329