1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2006, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 27 /* 28 * SiliconImage 3124/3132 sata controller driver 29 */ 30 31 /* 32 * 33 * 34 * Few Design notes 35 * 36 * 37 * I. General notes 38 * 39 * Even though the driver is named as si3124, it is actually meant to 40 * work with both 3124 and 3132 controllers. 41 * 42 * The current file si3124.c is the main driver code. The si3124reg.h 43 * holds the register definitions from SiI 3124/3132 data sheets. The 44 * si3124var.h holds the driver specific definitions which are not 45 * directly derived from data sheets. 46 * 47 * 48 * II. Data structures 49 * 50 * si_ctl_state_t: This holds the driver private information for each 51 * controller instance. Each of the sata ports within a single 52 * controller are represented by si_port_state_t. The 53 * sictl_global_acc_handle and sictl_global_address map the 54 * controller-wide global register space and are derived from pci 55 * BAR 0. The sictl_port_acc_handle and sictl_port_addr map the 56 * per-port register space and are derived from pci BAR 1. 57 * 58 * si_port_state_t: This holds the per port information. The siport_mutex 59 * holds the per port mutex. The siport_pending_tags is the bit mask of 60 * commands posted to controller. The siport_slot_pkts[] holds the 61 * pending sata packets. The siport_port_type holds the device type 62 * connected directly to the port while the siport_portmult_state 63 * holds the similar information for the devices behind a port 64 * multiplier. 65 * 66 * si_prb_t: This contains the PRB being posted to the controller. 67 * The two SGE entries contained within si_prb_t itself are not 68 * really used to hold any scatter gather entries. The scatter gather 69 * list is maintained external to PRB and is linked from one 70 * of the contained SGEs inside the PRB. For atapi devices, the 71 * first contained SGE holds the PACKET and second contained 72 * SGE holds the link to an external SGT. For non-atapi devices, 73 * the first contained SGE works as link to external SGT while 74 * second SGE is blank. 75 * 76 * external SGT tables: The external SGT tables pointed to from 77 * within si_prb_t are actually abstracted as si_sgblock_t. Each 78 * si_sgblock_t contains SI_MAX_SGT_TABLES_PER_PRB number of 79 * SGT tables linked in a chain. Currently this max value of 80 * SGT tables per block is hard coded as 10 which translates 81 * to a maximum of 31 dma cookies per single dma transfer. 82 * 83 * 84 * III. Driver operation 85 * 86 * Command Issuing: We use the "indirect method of command issuance". The 87 * PRB contains the command [and atapi PACKET] and a link to the 88 * external SGT chain. We write the physical address of the PRB into 89 * command activation register. There are 31 command slots for 90 * each port. After posting a command, we remember the posted slot & 91 * the sata packet in siport_pending_tags & siport_slot_pkts[] 92 * respectively. 93 * 94 * Command completion: On a successful completion, intr_command_complete() 95 * receives the control. The slot_status register holds the outstanding 96 * commands. Any reading of slot_status register automatically clears 97 * the interrupt. By comparing the slot_status register contents with 98 * per port siport_pending_tags, we determine which of the previously 99 * posted commands have finished. 100 * 101 * Timeout handling: Every 5 seconds, the watchdog handler scans thru the 102 * pending packets. The satapkt->satapkt_hba_driver_private field is 103 * overloaded with the count of watchdog cycles a packet has survived. 104 * If a packet has not completed within satapkt->satapkt_time, it is 105 * failed with error code of SATA_PKT_TIMEOUT. There is one watchdog 106 * handler running for each instance of controller. 107 * 108 * Error handling: For 3124, whenever any single command has encountered 109 * an error, the whole port execution completely stalls; there is no 110 * way of canceling or aborting the particular failed command. If 111 * the port is connected to a port multiplier, we can however RESUME 112 * other non-error devices connected to the port multiplier. 113 * The only way to recover the failed commands is to either initialize 114 * the port or reset the port/device. Both port initialize and reset 115 * operations result in discarding any of pending commands on the port. 116 * All such discarded commands are sent up to framework with PKT_RESET 117 * satapkt_reason. The assumption is that framework [and sd] would 118 * retry these commands again. The failed command itself however is 119 * sent up with PKT_DEV_ERROR. 120 * 121 * Here is the implementation strategy based on SiliconImage email 122 * regarding how they handle the errors for their Windows driver: 123 * 124 * a) for DEVICEERROR: 125 * If the port is connected to port multiplier, then 126 * 1) Resume the port 127 * 2) Wait for all the non-failed commands to complete 128 * 3) Perform a Port Initialize 129 * 130 * If the port is not connected to port multiplier, issue 131 * a Port Initialize. 132 * 133 * b) for SDBERROR: [SDBERROR means failed command is an NCQ command] 134 * Handle exactly like DEVICEERROR handling. 135 * After the Port Initialize done, do a Read Log Extended. 136 * 137 * c) for SENDFISERROR: 138 * If the port is connected to port multiplier, then 139 * 1) Resume the port 140 * 2) Wait for all the non-failed commands to complete 141 * 3) Perform a Port Initialize 142 * 143 * If the port is not connected to port multiplier, issue 144 * a Device Reset. 145 * 146 * d) for DATAFISERROR: 147 * If the port was executing an NCQ command, issue a Device 148 * Reset. 149 * 150 * Otherwise, follow the same error recovery as DEVICEERROR. 151 * 152 * e) for any other error, simply issue a Device Reset. 153 * 154 * To synchronize the interactions between various control flows (e.g. 155 * error recovery, timeout handling, si_poll_timeout, incoming flow 156 * from framework etc.), the following precautions are taken care of: 157 * a) During mopping_in_progress, no more commands are 158 * accepted from the framework. 159 * 160 * b) While draining the port multiplier commands, we should 161 * handle the possibility of any of the other waited commands 162 * failing (possibly with a different error code) 163 * 164 * Atapi handling: For atapi devices, we use the first SGE within the PRB 165 * to fill the scsi cdb while the second SGE points to external SGT. 166 * 167 * Queuing: Queue management is achieved external to the driver inside sd. 168 * Based on sata_hba_tran->qdepth and IDENTIFY data, the framework 169 * enables or disables the queuing. The qdepth for si3124 is 31 170 * commands. 171 * 172 * Port Multiplier: Enumeration of port multiplier is handled during the 173 * controller initialization and also during the a hotplug operation. 174 * Current logic takes care of situation where a port multiplier 175 * is hotplugged into a port which had a cdisk connected previously 176 * and vice versa. 177 * 178 * Register poll timeouts: Currently most of poll timeouts on register 179 * reads is set to 0.5 seconds except for a value of 10 seconds 180 * while reading the device signature. [Such a big timeout values 181 * for device signature were found needed during cold reboots 182 * for devices behind port multiplier]. 183 * 184 * 185 * IV. Known Issues 186 * 187 * 1) Currently the atapi packet length is hard coded to 12 bytes 188 * This is wrong. The framework should determine it just like they 189 * determine ad_cdb_len in legacy atapi.c. It should even reject 190 * init_pkt() for greater CDB lengths. See atapi.c. Revisit this 191 * in 2nd phase of framework project. 192 * 193 * 2) Do real REQUEST SENSE command instead of faking for ATAPI case. 194 * 195 */ 196 197 198 #include <sys/note.h> 199 #include <sys/scsi/scsi.h> 200 #include <sys/pci.h> 201 #include <sys/sata/sata_hba.h> 202 #include <sys/sata/adapters/si3124/si3124reg.h> 203 #include <sys/sata/adapters/si3124/si3124var.h> 204 #include <sys/sdt.h> 205 206 /* 207 * Function prototypes for driver entry points 208 */ 209 static int si_attach(dev_info_t *, ddi_attach_cmd_t); 210 static int si_detach(dev_info_t *, ddi_detach_cmd_t); 211 static int si_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 212 static int si_power(dev_info_t *, int, int); 213 static int si_quiesce(dev_info_t *); 214 /* 215 * Function prototypes for SATA Framework interfaces 216 */ 217 static int si_register_sata_hba_tran(si_ctl_state_t *); 218 static int si_unregister_sata_hba_tran(si_ctl_state_t *); 219 220 static int si_tran_probe_port(dev_info_t *, sata_device_t *); 221 static int si_tran_start(dev_info_t *, sata_pkt_t *spkt); 222 static int si_tran_abort(dev_info_t *, sata_pkt_t *, int); 223 static int si_tran_reset_dport(dev_info_t *, sata_device_t *); 224 static int si_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 225 static int si_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 226 227 /* 228 * Local function prototypes 229 */ 230 231 static int si_alloc_port_state(si_ctl_state_t *, int); 232 static void si_dealloc_port_state(si_ctl_state_t *, int); 233 static int si_alloc_sgbpool(si_ctl_state_t *, int); 234 static void si_dealloc_sgbpool(si_ctl_state_t *, int); 235 static int si_alloc_prbpool(si_ctl_state_t *, int); 236 static void si_dealloc_prbpool(si_ctl_state_t *, int); 237 238 static void si_find_dev_signature(si_ctl_state_t *, si_port_state_t *, 239 int, int); 240 static void si_poll_cmd(si_ctl_state_t *, si_port_state_t *, int, int, 241 sata_pkt_t *); 242 static int si_claim_free_slot(si_ctl_state_t *, si_port_state_t *, int); 243 static int si_deliver_satapkt(si_ctl_state_t *, si_port_state_t *, int, 244 sata_pkt_t *); 245 246 static int si_initialize_controller(si_ctl_state_t *); 247 static void si_deinitialize_controller(si_ctl_state_t *); 248 static void si_init_port(si_ctl_state_t *, int); 249 static int si_enumerate_port_multiplier(si_ctl_state_t *, 250 si_port_state_t *, int); 251 static int si_read_portmult_reg(si_ctl_state_t *, si_port_state_t *, 252 int, int, int, uint32_t *); 253 static int si_write_portmult_reg(si_ctl_state_t *, si_port_state_t *, 254 int, int, int, uint32_t); 255 static void si_set_sense_data(sata_pkt_t *, int); 256 257 static uint_t si_intr(caddr_t, caddr_t); 258 static int si_intr_command_complete(si_ctl_state_t *, 259 si_port_state_t *, int); 260 static int si_intr_command_error(si_ctl_state_t *, 261 si_port_state_t *, int); 262 static void si_error_recovery_DEVICEERROR(si_ctl_state_t *, 263 si_port_state_t *, int); 264 static void si_error_recovery_SDBERROR(si_ctl_state_t *, 265 si_port_state_t *, int); 266 static void si_error_recovery_DATAFISERROR(si_ctl_state_t *, 267 si_port_state_t *, int); 268 static void si_error_recovery_SENDFISERROR(si_ctl_state_t *, 269 si_port_state_t *, int); 270 static void si_error_recovery_default(si_ctl_state_t *, 271 si_port_state_t *, int); 272 static uint8_t si_read_log_ext(si_ctl_state_t *, 273 si_port_state_t *si_portp, int); 274 static void si_log_error_message(si_ctl_state_t *, int, uint32_t); 275 static int si_intr_port_ready(si_ctl_state_t *, si_port_state_t *, int); 276 static int si_intr_pwr_change(si_ctl_state_t *, si_port_state_t *, int); 277 static int si_intr_phy_ready_change(si_ctl_state_t *, si_port_state_t *, int); 278 static int si_intr_comwake_rcvd(si_ctl_state_t *, si_port_state_t *, int); 279 static int si_intr_unrecognised_fis(si_ctl_state_t *, si_port_state_t *, int); 280 static int si_intr_dev_xchanged(si_ctl_state_t *, si_port_state_t *, int); 281 static int si_intr_decode_err_threshold(si_ctl_state_t *, 282 si_port_state_t *, int); 283 static int si_intr_crc_err_threshold(si_ctl_state_t *, si_port_state_t *, int); 284 static int si_intr_handshake_err_threshold(si_ctl_state_t *, 285 si_port_state_t *, int); 286 static int si_intr_set_devbits_notify(si_ctl_state_t *, si_port_state_t *, int); 287 288 static void si_enable_port_interrupts(si_ctl_state_t *, int); 289 static void si_enable_all_interrupts(si_ctl_state_t *); 290 static void si_disable_port_interrupts(si_ctl_state_t *, int); 291 static void si_disable_all_interrupts(si_ctl_state_t *); 292 static void fill_dev_sregisters(si_ctl_state_t *, int, sata_device_t *); 293 static int si_add_legacy_intrs(si_ctl_state_t *); 294 static int si_add_msi_intrs(si_ctl_state_t *); 295 static void si_rem_intrs(si_ctl_state_t *); 296 297 static int si_reset_dport_wait_till_ready(si_ctl_state_t *, 298 si_port_state_t *, int, int); 299 static int si_clear_port(si_ctl_state_t *, int); 300 static int si_initialize_port_wait_till_ready(si_ctl_state_t *, int); 301 302 static void si_timeout_pkts(si_ctl_state_t *, si_port_state_t *, int, uint32_t); 303 static void si_watchdog_handler(si_ctl_state_t *); 304 305 #if SI_DEBUG 306 static void si_log(si_ctl_state_t *, uint_t, char *, ...); 307 #endif /* SI_DEBUG */ 308 309 static void si_copy_out_regs(sata_cmd_t *, si_ctl_state_t *, uint8_t, uint8_t); 310 311 /* 312 * DMA attributes for the data buffer 313 */ 314 315 static ddi_dma_attr_t buffer_dma_attr = { 316 DMA_ATTR_V0, /* dma_attr_version */ 317 0, /* dma_attr_addr_lo: lowest bus address */ 318 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 319 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 320 1, /* dma_attr_align: single byte aligned */ 321 1, /* dma_attr_burstsizes */ 322 1, /* dma_attr_minxfer */ 323 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 324 0xffffffffull, /* dma_attr_seg */ 325 SI_MAX_SGL_LENGTH, /* dma_attr_sgllen */ 326 512, /* dma_attr_granular */ 327 0, /* dma_attr_flags */ 328 }; 329 330 /* 331 * DMA attributes for incore RPB and SGT pool 332 */ 333 static ddi_dma_attr_t prb_sgt_dma_attr = { 334 DMA_ATTR_V0, /* dma_attr_version */ 335 0, /* dma_attr_addr_lo: lowest bus address */ 336 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 337 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 338 8, /* dma_attr_align: quad word aligned */ 339 1, /* dma_attr_burstsizes */ 340 1, /* dma_attr_minxfer */ 341 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 342 0xffffffffull, /* dma_attr_seg */ 343 1, /* dma_attr_sgllen */ 344 1, /* dma_attr_granular */ 345 0, /* dma_attr_flags */ 346 }; 347 348 /* Device access attributes */ 349 static ddi_device_acc_attr_t accattr = { 350 DDI_DEVICE_ATTR_V0, 351 DDI_STRUCTURE_LE_ACC, 352 DDI_STRICTORDER_ACC 353 }; 354 355 356 static struct dev_ops sictl_dev_ops = { 357 DEVO_REV, /* devo_rev */ 358 0, /* refcnt */ 359 si_getinfo, /* info */ 360 nulldev, /* identify */ 361 nulldev, /* probe */ 362 si_attach, /* attach */ 363 si_detach, /* detach */ 364 nodev, /* no reset */ 365 (struct cb_ops *)0, /* driver operations */ 366 NULL, /* bus operations */ 367 si_power, /* power */ 368 si_quiesce, /* devo_quiesce */ 369 }; 370 371 static sata_tran_hotplug_ops_t si_tran_hotplug_ops = { 372 SATA_TRAN_HOTPLUG_OPS_REV_1, 373 si_tran_hotplug_port_activate, 374 si_tran_hotplug_port_deactivate 375 }; 376 377 378 static int si_watchdog_timeout = 5; /* 5 seconds */ 379 static int si_watchdog_tick; 380 381 extern struct mod_ops mod_driverops; 382 383 static struct modldrv modldrv = { 384 &mod_driverops, /* driverops */ 385 "si3124 driver", 386 &sictl_dev_ops, /* driver ops */ 387 }; 388 389 static struct modlinkage modlinkage = { 390 MODREV_1, 391 &modldrv, 392 NULL 393 }; 394 395 396 /* The following are needed for si_log() */ 397 static kmutex_t si_log_mutex; 398 #if SI_DEBUG 399 static char si_log_buf[512]; 400 #endif /* SI_DEBUG */ 401 uint32_t si_debug_flags = 0x0; 402 static int is_msi_supported = 0; 403 404 /* Opaque state pointer to be initialized by ddi_soft_state_init() */ 405 static void *si_statep = NULL; 406 407 /* 408 * si3124 module initialization. 409 * 410 */ 411 int 412 _init(void) 413 { 414 int error; 415 416 error = ddi_soft_state_init(&si_statep, sizeof (si_ctl_state_t), 0); 417 if (error != 0) { 418 return (error); 419 } 420 421 mutex_init(&si_log_mutex, NULL, MUTEX_DRIVER, NULL); 422 423 if ((error = sata_hba_init(&modlinkage)) != 0) { 424 mutex_destroy(&si_log_mutex); 425 ddi_soft_state_fini(&si_statep); 426 return (error); 427 } 428 429 error = mod_install(&modlinkage); 430 if (error != 0) { 431 sata_hba_fini(&modlinkage); 432 mutex_destroy(&si_log_mutex); 433 ddi_soft_state_fini(&si_statep); 434 return (error); 435 } 436 437 si_watchdog_tick = drv_usectohz((clock_t)si_watchdog_timeout * 1000000); 438 439 return (error); 440 } 441 442 /* 443 * si3124 module uninitialize. 444 * 445 */ 446 int 447 _fini(void) 448 { 449 int error; 450 451 error = mod_remove(&modlinkage); 452 if (error != 0) { 453 return (error); 454 } 455 456 /* Remove the resources allocated in _init(). */ 457 sata_hba_fini(&modlinkage); 458 mutex_destroy(&si_log_mutex); 459 ddi_soft_state_fini(&si_statep); 460 461 return (error); 462 } 463 464 /* 465 * _info entry point 466 * 467 */ 468 int 469 _info(struct modinfo *modinfop) 470 { 471 return (mod_info(&modlinkage, modinfop)); 472 } 473 474 475 /* 476 * The attach entry point for dev_ops. 477 * 478 * We initialize the controller, initialize the soft state, register 479 * the interrupt handlers and then register ourselves with sata framework. 480 */ 481 static int 482 si_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 483 { 484 si_ctl_state_t *si_ctlp; 485 int instance; 486 int status; 487 int attach_state; 488 int intr_types; 489 sata_device_t sdevice; 490 491 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_attach enter"); 492 instance = ddi_get_instance(dip); 493 attach_state = ATTACH_PROGRESS_NONE; 494 495 switch (cmd) { 496 497 case DDI_ATTACH: 498 499 /* Allocate si_softc. */ 500 status = ddi_soft_state_zalloc(si_statep, instance); 501 if (status != DDI_SUCCESS) { 502 goto err_out; 503 } 504 505 si_ctlp = ddi_get_soft_state(si_statep, instance); 506 si_ctlp->sictl_devinfop = dip; 507 508 attach_state |= ATTACH_PROGRESS_STATEP_ALLOC; 509 510 /* Configure pci config space handle. */ 511 status = pci_config_setup(dip, &si_ctlp->sictl_pci_conf_handle); 512 if (status != DDI_SUCCESS) { 513 goto err_out; 514 } 515 516 si_ctlp->sictl_devid = 517 pci_config_get16(si_ctlp->sictl_pci_conf_handle, 518 PCI_CONF_DEVID); 519 if (si_ctlp->sictl_devid == SI3132_DEV_ID) { 520 si_ctlp->sictl_num_ports = SI3132_MAX_PORTS; 521 } else { 522 si_ctlp->sictl_num_ports = SI3124_MAX_PORTS; 523 } 524 525 attach_state |= ATTACH_PROGRESS_CONF_HANDLE; 526 527 /* Now map the bar0; the bar0 contains the global registers. */ 528 status = ddi_regs_map_setup(dip, 529 PCI_BAR0, 530 (caddr_t *)&si_ctlp->sictl_global_addr, 531 0, 532 0, 533 &accattr, 534 &si_ctlp->sictl_global_acc_handle); 535 if (status != DDI_SUCCESS) { 536 goto err_out; 537 } 538 539 attach_state |= ATTACH_PROGRESS_BAR0_MAP; 540 541 /* Now map bar1; the bar1 contains the port registers. */ 542 status = ddi_regs_map_setup(dip, 543 PCI_BAR1, 544 (caddr_t *)&si_ctlp->sictl_port_addr, 545 0, 546 0, 547 &accattr, 548 &si_ctlp->sictl_port_acc_handle); 549 if (status != DDI_SUCCESS) { 550 goto err_out; 551 } 552 553 attach_state |= ATTACH_PROGRESS_BAR1_MAP; 554 555 /* 556 * Disable all the interrupts before adding interrupt 557 * handler(s). The interrupts shall be re-enabled selectively 558 * out of si_init_port(). 559 */ 560 si_disable_all_interrupts(si_ctlp); 561 562 /* Get supported interrupt types. */ 563 if (ddi_intr_get_supported_types(dip, &intr_types) 564 != DDI_SUCCESS) { 565 SIDBG0(SIDBG_INIT, NULL, 566 "ddi_intr_get_supported_types failed"); 567 goto err_out; 568 } 569 570 SIDBG1(SIDBG_INIT, NULL, 571 "ddi_intr_get_supported_types() returned: 0x%x", 572 intr_types); 573 574 if (is_msi_supported && (intr_types & DDI_INTR_TYPE_MSI)) { 575 SIDBG0(SIDBG_INIT, NULL, "Using MSI interrupt type"); 576 577 /* 578 * Try MSI first, but fall back to legacy if MSI 579 * attach fails. 580 */ 581 if (si_add_msi_intrs(si_ctlp) == DDI_SUCCESS) { 582 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_MSI; 583 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 584 SIDBG0(SIDBG_INIT, NULL, 585 "MSI interrupt setup done"); 586 } 587 #if SI_DEBUG 588 else { 589 SIDBG0(SIDBG_INIT, NULL, 590 "MSI registration failed " 591 "will try Legacy interrupts"); 592 } 593 #endif /* SI_DEBUG */ 594 } 595 596 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED) && 597 (intr_types & DDI_INTR_TYPE_FIXED)) { 598 /* 599 * Either the MSI interrupt setup has failed or only 600 * fixed interrupts are available on the system. 601 */ 602 SIDBG0(SIDBG_INIT, NULL, "Using Legacy interrupt type"); 603 604 if (si_add_legacy_intrs(si_ctlp) == DDI_SUCCESS) { 605 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_FIXED; 606 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 607 SIDBG0(SIDBG_INIT, NULL, 608 "Legacy interrupt setup done"); 609 } else { 610 SIDBG0(SIDBG_INIT, NULL, 611 "legacy interrupt setup failed"); 612 goto err_out; 613 } 614 } 615 616 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED)) { 617 SIDBG0(SIDBG_INIT, NULL, 618 "si3124: No interrupts registered"); 619 goto err_out; 620 } 621 622 623 /* Initialize the mutex. */ 624 mutex_init(&si_ctlp->sictl_mutex, NULL, MUTEX_DRIVER, 625 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 626 627 attach_state |= ATTACH_PROGRESS_MUTEX_INIT; 628 629 /* 630 * Initialize the controller and driver core. 631 */ 632 si_ctlp->sictl_flags |= SI_ATTACH; 633 status = si_initialize_controller(si_ctlp); 634 si_ctlp->sictl_flags &= ~SI_ATTACH; 635 if (status) { 636 goto err_out; 637 } 638 639 attach_state |= ATTACH_PROGRESS_HW_INIT; 640 641 if (si_register_sata_hba_tran(si_ctlp)) { 642 SIDBG0(SIDBG_INIT, NULL, 643 "si3124: setting sata hba tran failed"); 644 goto err_out; 645 } 646 647 si_ctlp->sictl_timeout_id = timeout( 648 (void (*)(void *))si_watchdog_handler, 649 (caddr_t)si_ctlp, si_watchdog_tick); 650 651 si_ctlp->sictl_power_level = PM_LEVEL_D0; 652 653 return (DDI_SUCCESS); 654 655 case DDI_RESUME: 656 si_ctlp = ddi_get_soft_state(si_statep, instance); 657 658 status = si_initialize_controller(si_ctlp); 659 if (status) { 660 return (DDI_FAILURE); 661 } 662 663 si_ctlp->sictl_timeout_id = timeout( 664 (void (*)(void *))si_watchdog_handler, 665 (caddr_t)si_ctlp, si_watchdog_tick); 666 667 (void) pm_power_has_changed(dip, 0, PM_LEVEL_D0); 668 669 /* Notify SATA framework about RESUME. */ 670 if (sata_hba_attach(si_ctlp->sictl_devinfop, 671 si_ctlp->sictl_sata_hba_tran, 672 DDI_RESUME) != DDI_SUCCESS) { 673 return (DDI_FAILURE); 674 } 675 676 /* 677 * Notify the "framework" that it should reprobe ports to see 678 * if any device got changed while suspended. 679 */ 680 bzero((void *)&sdevice, sizeof (sata_device_t)); 681 sata_hba_event_notify(dip, &sdevice, 682 SATA_EVNT_PWR_LEVEL_CHANGED); 683 SIDBG0(SIDBG_INIT|SIDBG_EVENT, si_ctlp, 684 "sending event up: SATA_EVNT_PWR_LEVEL_CHANGED"); 685 686 (void) pm_idle_component(si_ctlp->sictl_devinfop, 0); 687 688 si_ctlp->sictl_power_level = PM_LEVEL_D0; 689 690 return (DDI_SUCCESS); 691 692 default: 693 return (DDI_FAILURE); 694 695 } 696 697 err_out: 698 if (attach_state & ATTACH_PROGRESS_HW_INIT) { 699 si_ctlp->sictl_flags |= SI_DETACH; 700 /* We want to set SI_DETACH to deallocate all memory */ 701 si_deinitialize_controller(si_ctlp); 702 si_ctlp->sictl_flags &= ~SI_DETACH; 703 } 704 705 if (attach_state & ATTACH_PROGRESS_MUTEX_INIT) { 706 mutex_destroy(&si_ctlp->sictl_mutex); 707 } 708 709 if (attach_state & ATTACH_PROGRESS_INTR_ADDED) { 710 si_rem_intrs(si_ctlp); 711 } 712 713 if (attach_state & ATTACH_PROGRESS_BAR1_MAP) { 714 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 715 } 716 717 if (attach_state & ATTACH_PROGRESS_BAR0_MAP) { 718 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 719 } 720 721 if (attach_state & ATTACH_PROGRESS_CONF_HANDLE) { 722 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 723 } 724 725 if (attach_state & ATTACH_PROGRESS_STATEP_ALLOC) { 726 ddi_soft_state_free(si_statep, instance); 727 } 728 729 return (DDI_FAILURE); 730 } 731 732 733 /* 734 * The detach entry point for dev_ops. 735 * 736 * We undo the things we did in si_attach(). 737 */ 738 static int 739 si_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 740 { 741 si_ctl_state_t *si_ctlp; 742 int instance; 743 744 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_detach enter"); 745 instance = ddi_get_instance(dip); 746 si_ctlp = ddi_get_soft_state(si_statep, instance); 747 748 switch (cmd) { 749 750 case DDI_DETACH: 751 752 mutex_enter(&si_ctlp->sictl_mutex); 753 754 /* disable the interrupts for an uninterrupted detach */ 755 si_disable_all_interrupts(si_ctlp); 756 757 mutex_exit(&si_ctlp->sictl_mutex); 758 /* unregister from the sata framework. */ 759 if (si_unregister_sata_hba_tran(si_ctlp) != SI_SUCCESS) { 760 si_enable_all_interrupts(si_ctlp); 761 return (DDI_FAILURE); 762 } 763 mutex_enter(&si_ctlp->sictl_mutex); 764 765 /* now cancel the timeout handler. */ 766 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 767 (void) untimeout(si_ctlp->sictl_timeout_id); 768 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 769 770 /* de-initialize the controller. */ 771 si_ctlp->sictl_flags |= SI_DETACH; 772 si_deinitialize_controller(si_ctlp); 773 si_ctlp->sictl_flags &= ~SI_DETACH; 774 775 /* destroy any mutexes */ 776 mutex_exit(&si_ctlp->sictl_mutex); 777 mutex_destroy(&si_ctlp->sictl_mutex); 778 779 /* remove the interrupts */ 780 si_rem_intrs(si_ctlp); 781 782 /* remove the reg maps. */ 783 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 784 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 785 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 786 787 /* free the soft state. */ 788 ddi_soft_state_free(si_statep, instance); 789 790 return (DDI_SUCCESS); 791 792 case DDI_SUSPEND: 793 /* Inform SATA framework */ 794 if (sata_hba_detach(dip, cmd) != DDI_SUCCESS) { 795 return (DDI_FAILURE); 796 } 797 798 mutex_enter(&si_ctlp->sictl_mutex); 799 800 /* 801 * Device needs to be at full power in case it is needed to 802 * handle dump(9e) to save CPR state after DDI_SUSPEND 803 * completes. This is OK since presumably power will be 804 * removed anyways. No outstanding transactions should be 805 * on the controller since the children are already quiesced. 806 * 807 * If any ioctls/cfgadm support is added that touches 808 * hardware, those entry points will need to check for 809 * suspend and then block or return errors until resume. 810 * 811 */ 812 if (pm_busy_component(si_ctlp->sictl_devinfop, 0) == 813 DDI_SUCCESS) { 814 mutex_exit(&si_ctlp->sictl_mutex); 815 (void) pm_raise_power(si_ctlp->sictl_devinfop, 0, 816 PM_LEVEL_D0); 817 mutex_enter(&si_ctlp->sictl_mutex); 818 } 819 820 si_deinitialize_controller(si_ctlp); 821 822 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 823 (void) untimeout(si_ctlp->sictl_timeout_id); 824 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 825 826 SIDBG1(SIDBG_POWER, NULL, "si3124%d: DDI_SUSPEND", instance); 827 828 mutex_exit(&si_ctlp->sictl_mutex); 829 830 return (DDI_SUCCESS); 831 832 default: 833 return (DDI_FAILURE); 834 835 } 836 837 } 838 839 static int 840 si_power(dev_info_t *dip, int component, int level) 841 { 842 #ifndef __lock_lint 843 _NOTE(ARGUNUSED(component)) 844 #endif /* __lock_lint */ 845 846 si_ctl_state_t *si_ctlp; 847 int instance = ddi_get_instance(dip); 848 int rval = DDI_SUCCESS; 849 #if SI_DEBUG 850 int old_level; 851 #endif /* SI_DEBUG */ 852 sata_device_t sdevice; 853 854 si_ctlp = ddi_get_soft_state(si_statep, instance); 855 856 if (si_ctlp == NULL) { 857 return (DDI_FAILURE); 858 } 859 860 SIDBG0(SIDBG_ENTRY, NULL, "si_power enter"); 861 862 mutex_enter(&si_ctlp->sictl_mutex); 863 #if SI_DEBUG 864 old_level = si_ctlp->sictl_power_level; 865 #endif /* SI_DEBUG */ 866 867 switch (level) { 868 case PM_LEVEL_D0: /* fully on */ 869 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 870 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D0); 871 #ifndef __lock_lint 872 delay(drv_usectohz(10000)); 873 #endif /* __lock_lint */ 874 si_ctlp->sictl_power_level = PM_LEVEL_D0; 875 (void) pci_restore_config_regs(si_ctlp->sictl_devinfop); 876 877 SIDBG2(SIDBG_POWER, si_ctlp, 878 "si3124%d: turning power ON. old level %d", 879 instance, old_level); 880 /* 881 * If called from attach, just raise device power, 882 * restore config registers (if they were saved 883 * from a previous detach that lowered power), 884 * and exit. 885 */ 886 if (si_ctlp->sictl_flags & SI_ATTACH) 887 break; 888 889 mutex_exit(&si_ctlp->sictl_mutex); 890 (void) si_initialize_controller(si_ctlp); 891 mutex_enter(&si_ctlp->sictl_mutex); 892 893 si_ctlp->sictl_timeout_id = timeout( 894 (void (*)(void *))si_watchdog_handler, 895 (caddr_t)si_ctlp, si_watchdog_tick); 896 897 bzero((void *)&sdevice, sizeof (sata_device_t)); 898 sata_hba_event_notify( 899 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 900 &sdevice, SATA_EVNT_PWR_LEVEL_CHANGED); 901 SIDBG0(SIDBG_EVENT|SIDBG_POWER, si_ctlp, 902 "sending event up: PWR_LEVEL_CHANGED"); 903 904 break; 905 906 case PM_LEVEL_D3: /* fully off */ 907 if (!(si_ctlp->sictl_flags & SI_DETACH)) { 908 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 909 (void) untimeout(si_ctlp->sictl_timeout_id); 910 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 911 912 si_deinitialize_controller(si_ctlp); 913 914 si_ctlp->sictl_power_level = PM_LEVEL_D3; 915 } 916 917 (void) pci_save_config_regs(si_ctlp->sictl_devinfop); 918 919 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 920 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D3HOT); 921 922 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 923 "old level %d", instance, old_level); 924 925 break; 926 927 default: 928 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 929 "old level %d", instance, old_level); 930 rval = DDI_FAILURE; 931 break; 932 } 933 934 mutex_exit(&si_ctlp->sictl_mutex); 935 936 return (rval); 937 } 938 939 940 /* 941 * The info entry point for dev_ops. 942 * 943 */ 944 static int 945 si_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 946 void *arg, 947 void **result) 948 { 949 #ifndef __lock_lint 950 _NOTE(ARGUNUSED(dip)) 951 #endif /* __lock_lint */ 952 si_ctl_state_t *si_ctlp; 953 int instance; 954 dev_t dev; 955 956 dev = (dev_t)arg; 957 instance = getminor(dev); 958 959 switch (infocmd) { 960 case DDI_INFO_DEVT2DEVINFO: 961 si_ctlp = ddi_get_soft_state(si_statep, instance); 962 if (si_ctlp != NULL) { 963 *result = si_ctlp->sictl_devinfop; 964 return (DDI_SUCCESS); 965 } else { 966 *result = NULL; 967 return (DDI_FAILURE); 968 } 969 case DDI_INFO_DEVT2INSTANCE: 970 *(int *)result = instance; 971 break; 972 default: 973 break; 974 } 975 return (DDI_SUCCESS); 976 } 977 978 979 980 /* 981 * Registers the si3124 with sata framework. 982 */ 983 static int 984 si_register_sata_hba_tran(si_ctl_state_t *si_ctlp) 985 { 986 struct sata_hba_tran *sata_hba_tran; 987 988 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 989 "si_register_sata_hba_tran entry"); 990 991 mutex_enter(&si_ctlp->sictl_mutex); 992 993 /* Allocate memory for the sata_hba_tran */ 994 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 995 996 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV; 997 sata_hba_tran->sata_tran_hba_dip = si_ctlp->sictl_devinfop; 998 sata_hba_tran->sata_tran_hba_dma_attr = &buffer_dma_attr; 999 1000 sata_hba_tran->sata_tran_hba_num_cports = si_ctlp->sictl_num_ports; 1001 sata_hba_tran->sata_tran_hba_features_support = 0; 1002 sata_hba_tran->sata_tran_hba_qdepth = SI_NUM_SLOTS; 1003 1004 sata_hba_tran->sata_tran_probe_port = si_tran_probe_port; 1005 sata_hba_tran->sata_tran_start = si_tran_start; 1006 sata_hba_tran->sata_tran_abort = si_tran_abort; 1007 sata_hba_tran->sata_tran_reset_dport = si_tran_reset_dport; 1008 sata_hba_tran->sata_tran_selftest = NULL; 1009 sata_hba_tran->sata_tran_hotplug_ops = &si_tran_hotplug_ops; 1010 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1011 sata_hba_tran->sata_tran_ioctl = NULL; 1012 mutex_exit(&si_ctlp->sictl_mutex); 1013 1014 /* Attach it to SATA framework */ 1015 if (sata_hba_attach(si_ctlp->sictl_devinfop, sata_hba_tran, DDI_ATTACH) 1016 != DDI_SUCCESS) { 1017 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1018 return (SI_FAILURE); 1019 } 1020 1021 mutex_enter(&si_ctlp->sictl_mutex); 1022 si_ctlp->sictl_sata_hba_tran = sata_hba_tran; 1023 mutex_exit(&si_ctlp->sictl_mutex); 1024 1025 return (SI_SUCCESS); 1026 } 1027 1028 1029 /* 1030 * Unregisters the si3124 with sata framework. 1031 */ 1032 static int 1033 si_unregister_sata_hba_tran(si_ctl_state_t *si_ctlp) 1034 { 1035 1036 /* Detach from the SATA framework. */ 1037 if (sata_hba_detach(si_ctlp->sictl_devinfop, DDI_DETACH) != 1038 DDI_SUCCESS) { 1039 return (SI_FAILURE); 1040 } 1041 1042 /* Deallocate sata_hba_tran. */ 1043 kmem_free((void *)si_ctlp->sictl_sata_hba_tran, 1044 sizeof (sata_hba_tran_t)); 1045 1046 si_ctlp->sictl_sata_hba_tran = NULL; 1047 1048 return (SI_SUCCESS); 1049 } 1050 1051 /* 1052 * Called by sata framework to probe a port. We return the 1053 * cached information from a previous hardware probe. 1054 * 1055 * The actual hardware probing itself was done either from within 1056 * si_initialize_controller() during the driver attach or 1057 * from a phy ready change interrupt handler. 1058 */ 1059 static int 1060 si_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1061 { 1062 1063 si_ctl_state_t *si_ctlp; 1064 uint8_t cport = sd->satadev_addr.cport; 1065 uint8_t pmport = sd->satadev_addr.pmport; 1066 uint8_t qual = sd->satadev_addr.qual; 1067 uint8_t port_type; 1068 si_port_state_t *si_portp; 1069 si_portmult_state_t *si_portmultp; 1070 1071 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1072 1073 SIDBG3(SIDBG_ENTRY, si_ctlp, 1074 "si_tran_probe_port: cport: 0x%x, pmport: 0x%x, qual: 0x%x", 1075 cport, pmport, qual); 1076 1077 if (cport >= SI_MAX_PORTS) { 1078 sd->satadev_type = SATA_DTYPE_NONE; 1079 sd->satadev_state = SATA_STATE_UNKNOWN; /* invalid port */ 1080 return (SATA_FAILURE); 1081 } 1082 1083 mutex_enter(&si_ctlp->sictl_mutex); 1084 si_portp = si_ctlp->sictl_ports[cport]; 1085 mutex_exit(&si_ctlp->sictl_mutex); 1086 if (si_portp == NULL) { 1087 sd->satadev_type = SATA_DTYPE_NONE; 1088 sd->satadev_state = SATA_STATE_UNKNOWN; 1089 return (SATA_FAILURE); 1090 } 1091 1092 mutex_enter(&si_portp->siport_mutex); 1093 1094 if (qual == SATA_ADDR_PMPORT) { 1095 if (pmport >= si_portp->siport_portmult_state.sipm_num_ports) { 1096 sd->satadev_type = SATA_DTYPE_NONE; 1097 sd->satadev_state = SATA_STATE_UNKNOWN; 1098 mutex_exit(&si_portp->siport_mutex); 1099 return (SATA_FAILURE); 1100 } else { 1101 si_portmultp = &si_portp->siport_portmult_state; 1102 port_type = si_portmultp->sipm_port_type[pmport]; 1103 } 1104 } else { 1105 port_type = si_portp->siport_port_type; 1106 } 1107 1108 switch (port_type) { 1109 1110 case PORT_TYPE_DISK: 1111 sd->satadev_type = SATA_DTYPE_ATADISK; 1112 break; 1113 1114 case PORT_TYPE_ATAPI: 1115 sd->satadev_type = SATA_DTYPE_ATAPICD; 1116 break; 1117 1118 case PORT_TYPE_MULTIPLIER: 1119 sd->satadev_type = SATA_DTYPE_PMULT; 1120 sd->satadev_add_info = 1121 si_portp->siport_portmult_state.sipm_num_ports; 1122 break; 1123 1124 case PORT_TYPE_UNKNOWN: 1125 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1126 break; 1127 1128 default: 1129 /* we don't support any other device types. */ 1130 sd->satadev_type = SATA_DTYPE_NONE; 1131 break; 1132 } 1133 sd->satadev_state = SATA_STATE_READY; 1134 1135 if (qual == SATA_ADDR_PMPORT) { 1136 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1137 pmport, PSCR_REG0, &sd->satadev_scr.sstatus); 1138 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1139 pmport, PSCR_REG1, &sd->satadev_scr.serror); 1140 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1141 pmport, PSCR_REG2, &sd->satadev_scr.scontrol); 1142 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1143 pmport, PSCR_REG3, &sd->satadev_scr.sactive); 1144 } else { 1145 fill_dev_sregisters(si_ctlp, cport, sd); 1146 if (!(si_portp->siport_active)) { 1147 /* 1148 * Since we are implementing the port deactivation 1149 * in software only, we need to fake a valid value 1150 * for sstatus when the device is in deactivated state. 1151 */ 1152 SSTATUS_SET_DET(sd->satadev_scr.sstatus, 1153 SSTATUS_DET_PHYOFFLINE); 1154 SSTATUS_SET_IPM(sd->satadev_scr.sstatus, 1155 SSTATUS_IPM_NODEV_NOPHY); 1156 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1157 } 1158 } 1159 1160 mutex_exit(&si_portp->siport_mutex); 1161 return (SATA_SUCCESS); 1162 } 1163 1164 /* 1165 * Called by sata framework to transport a sata packet down stream. 1166 * 1167 * The actual work of building the FIS & transporting it to the hardware 1168 * is done out of the subroutine si_deliver_satapkt(). 1169 */ 1170 static int 1171 si_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1172 { 1173 si_ctl_state_t *si_ctlp; 1174 uint8_t cport; 1175 si_port_state_t *si_portp; 1176 int slot; 1177 1178 cport = spkt->satapkt_device.satadev_addr.cport; 1179 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1180 mutex_enter(&si_ctlp->sictl_mutex); 1181 si_portp = si_ctlp->sictl_ports[cport]; 1182 mutex_exit(&si_ctlp->sictl_mutex); 1183 1184 SIDBG1(SIDBG_ENTRY, si_ctlp, 1185 "si_tran_start entry: port: 0x%x", cport); 1186 1187 mutex_enter(&si_portp->siport_mutex); 1188 1189 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1190 !si_portp->siport_active) { 1191 /* 1192 * si_intr_phy_ready_change() may have rendered it to 1193 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1194 * it inactive. 1195 */ 1196 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1197 fill_dev_sregisters(si_ctlp, cport, &spkt->satapkt_device); 1198 mutex_exit(&si_portp->siport_mutex); 1199 return (SATA_TRAN_PORT_ERROR); 1200 } 1201 1202 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1203 si_portp->siport_reset_in_progress = 0; 1204 SIDBG1(SIDBG_ENTRY, si_ctlp, 1205 "si_tran_start clearing the " 1206 "reset_in_progress for port: 0x%x", cport); 1207 } 1208 1209 if (si_portp->siport_reset_in_progress && 1210 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1211 ! ddi_in_panic()) { 1212 1213 spkt->satapkt_reason = SATA_PKT_BUSY; 1214 SIDBG1(SIDBG_ERRS, si_ctlp, 1215 "si_tran_start returning BUSY while " 1216 "reset in progress: port: 0x%x", cport); 1217 mutex_exit(&si_portp->siport_mutex); 1218 return (SATA_TRAN_BUSY); 1219 } 1220 1221 if (si_portp->mopping_in_progress > 0) { 1222 spkt->satapkt_reason = SATA_PKT_BUSY; 1223 SIDBG1(SIDBG_ERRS, si_ctlp, 1224 "si_tran_start returning BUSY while " 1225 "mopping in progress: port: 0x%x", cport); 1226 mutex_exit(&si_portp->siport_mutex); 1227 return (SATA_TRAN_BUSY); 1228 } 1229 1230 if ((slot = si_deliver_satapkt(si_ctlp, si_portp, cport, spkt)) 1231 == SI_FAILURE) { 1232 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1233 SIDBG1(SIDBG_ERRS, si_ctlp, 1234 "si_tran_start returning QUEUE_FULL: port: 0x%x", 1235 cport); 1236 mutex_exit(&si_portp->siport_mutex); 1237 return (SATA_TRAN_QUEUE_FULL); 1238 } 1239 1240 if (spkt->satapkt_op_mode & (SATA_OPMODE_POLLING|SATA_OPMODE_SYNCH)) { 1241 /* we need to poll now */ 1242 si_poll_cmd(si_ctlp, si_portp, cport, slot, spkt); 1243 1244 } 1245 1246 mutex_exit(&si_portp->siport_mutex); 1247 return (SATA_TRAN_ACCEPTED); 1248 } 1249 1250 #define SENDUP_PACKET(si_portp, satapkt, reason) \ 1251 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1252 SATAC_WRITE_FPDMA_QUEUED) || \ 1253 (satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1254 SATAC_READ_FPDMA_QUEUED)) { \ 1255 si_portp->siport_pending_ncq_count--; \ 1256 } \ 1257 if (satapkt) { \ 1258 satapkt->satapkt_reason = reason; \ 1259 /* \ 1260 * We set the satapkt_reason in both synch and \ 1261 * non-synch cases. \ 1262 */ \ 1263 } \ 1264 if (satapkt && \ 1265 !(satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1266 satapkt->satapkt_comp) { \ 1267 mutex_exit(&si_portp->siport_mutex); \ 1268 (*satapkt->satapkt_comp)(satapkt); \ 1269 mutex_enter(&si_portp->siport_mutex); \ 1270 } 1271 1272 /* 1273 * Mopping is necessitated because of the si3124 hardware limitation. 1274 * The only way to recover from errors or to abort a command is to 1275 * reset the port/device but such a reset also results in throwing 1276 * away all the unfinished pending commands. 1277 * 1278 * A port or device is reset in four scenarios: 1279 * a) some commands failed with errors 1280 * b) or we need to timeout some commands 1281 * c) or we need to abort some commands 1282 * d) or we need reset the port at the request of sata framework 1283 * 1284 * In all these scenarios, we need to send any pending unfinished 1285 * commands up to sata framework. 1286 * 1287 * WARNING!!! siport_mutex should be acquired before the function is called. 1288 */ 1289 static void 1290 si_mop_commands(si_ctl_state_t *si_ctlp, 1291 si_port_state_t *si_portp, 1292 uint8_t port, 1293 1294 uint32_t slot_status, 1295 uint32_t failed_tags, 1296 uint32_t timedout_tags, 1297 uint32_t aborting_tags, 1298 uint32_t reset_tags) 1299 { 1300 uint32_t finished_tags, unfinished_tags; 1301 int tmpslot; 1302 sata_pkt_t *satapkt; 1303 struct sata_cmd_flags *flagsp; 1304 1305 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1306 "si_mop_commands entered: slot_status: 0x%x", 1307 slot_status); 1308 1309 SIDBG4(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1310 "si_mop_commands: failed_tags: 0x%x, timedout_tags: 0x%x" 1311 "aborting_tags: 0x%x, reset_tags: 0x%x", 1312 failed_tags, 1313 timedout_tags, 1314 aborting_tags, 1315 reset_tags); 1316 1317 /* 1318 * We could be here for four reasons: abort, reset, 1319 * timeout or error handling. Only one such mopping 1320 * is allowed at a time. 1321 */ 1322 1323 finished_tags = si_portp->siport_pending_tags & 1324 ~slot_status & SI_SLOT_MASK; 1325 1326 unfinished_tags = slot_status & SI_SLOT_MASK & 1327 ~failed_tags & 1328 ~aborting_tags & 1329 ~reset_tags & 1330 ~timedout_tags; 1331 1332 /* Send up the finished_tags with SATA_PKT_COMPLETED. */ 1333 while (finished_tags) { 1334 tmpslot = ddi_ffs(finished_tags) - 1; 1335 if (tmpslot == -1) { 1336 break; 1337 } 1338 1339 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1340 ASSERT(satapkt != NULL); 1341 1342 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 1343 si_copy_out_regs(&satapkt->satapkt_cmd, si_ctlp, 1344 port, tmpslot); 1345 } 1346 1347 SIDBG1(SIDBG_ERRS, si_ctlp, 1348 "si_mop_commands sending up completed satapkt: %x", 1349 satapkt); 1350 1351 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1352 CLEAR_BIT(finished_tags, tmpslot); 1353 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 1354 } 1355 1356 ASSERT(finished_tags == 0); 1357 1358 /* Send up failed_tags with SATA_PKT_DEV_ERROR. */ 1359 while (failed_tags) { 1360 tmpslot = ddi_ffs(failed_tags) - 1; 1361 if (tmpslot == -1) { 1362 break; 1363 } 1364 SIDBG1(SIDBG_ERRS, si_ctlp, "si3124: si_mop_commands: " 1365 "handling failed slot: 0x%x", tmpslot); 1366 1367 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1368 ASSERT(satapkt != NULL); 1369 if (satapkt->satapkt_device.satadev_type == 1370 SATA_DTYPE_ATAPICD) { 1371 si_set_sense_data(satapkt, SATA_PKT_DEV_ERROR); 1372 } 1373 1374 1375 flagsp = &satapkt->satapkt_cmd.satacmd_flags; 1376 1377 flagsp->sata_copy_out_lba_low_msb = B_TRUE; 1378 flagsp->sata_copy_out_lba_mid_msb = B_TRUE; 1379 flagsp->sata_copy_out_lba_high_msb = B_TRUE; 1380 flagsp->sata_copy_out_lba_low_lsb = B_TRUE; 1381 flagsp->sata_copy_out_lba_mid_lsb = B_TRUE; 1382 flagsp->sata_copy_out_lba_high_lsb = B_TRUE; 1383 flagsp->sata_copy_out_error_reg = B_TRUE; 1384 flagsp->sata_copy_out_sec_count_msb = B_TRUE; 1385 flagsp->sata_copy_out_sec_count_lsb = B_TRUE; 1386 flagsp->sata_copy_out_device_reg = B_TRUE; 1387 1388 si_copy_out_regs(&satapkt->satapkt_cmd, si_ctlp, port, tmpslot); 1389 1390 /* 1391 * In the case of NCQ command failures, the error is 1392 * overwritten by the one obtained from issuing of a 1393 * READ LOG EXTENDED command. 1394 */ 1395 if (si_portp->siport_err_tags_SDBERROR & (1 << tmpslot)) { 1396 satapkt->satapkt_cmd.satacmd_error_reg = 1397 si_read_log_ext(si_ctlp, si_portp, port); 1398 } 1399 1400 CLEAR_BIT(failed_tags, tmpslot); 1401 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1402 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_DEV_ERROR); 1403 } 1404 1405 ASSERT(failed_tags == 0); 1406 1407 /* Send up timedout_tags with SATA_PKT_TIMEOUT. */ 1408 while (timedout_tags) { 1409 tmpslot = ddi_ffs(timedout_tags) - 1; 1410 if (tmpslot == -1) { 1411 break; 1412 } 1413 1414 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1415 ASSERT(satapkt != NULL); 1416 SIDBG1(SIDBG_ERRS, si_ctlp, 1417 "si_mop_commands sending " 1418 "spkt up with PKT_TIMEOUT: %x", 1419 satapkt); 1420 1421 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1422 CLEAR_BIT(timedout_tags, tmpslot); 1423 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_TIMEOUT); 1424 } 1425 1426 ASSERT(timedout_tags == 0); 1427 1428 /* Send up aborting packets with SATA_PKT_ABORTED. */ 1429 while (aborting_tags) { 1430 tmpslot = ddi_ffs(aborting_tags) - 1; 1431 if (tmpslot == -1) { 1432 break; 1433 } 1434 1435 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1436 ASSERT(satapkt != NULL); 1437 SIDBG1(SIDBG_ERRS, si_ctlp, 1438 "si_mop_commands aborting spkt: %x", 1439 satapkt); 1440 if (satapkt->satapkt_device.satadev_type == 1441 SATA_DTYPE_ATAPICD) { 1442 si_set_sense_data(satapkt, SATA_PKT_ABORTED); 1443 } 1444 1445 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1446 CLEAR_BIT(aborting_tags, tmpslot); 1447 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_ABORTED); 1448 1449 } 1450 1451 ASSERT(aborting_tags == 0); 1452 1453 /* Reset tags are sent up to framework with SATA_PKT_RESET. */ 1454 while (reset_tags) { 1455 tmpslot = ddi_ffs(reset_tags) - 1; 1456 if (tmpslot == -1) { 1457 break; 1458 } 1459 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1460 ASSERT(satapkt != NULL); 1461 SIDBG1(SIDBG_ERRS, si_ctlp, 1462 "si_mop_commands sending PKT_RESET for " 1463 "reset spkt: %x", 1464 satapkt); 1465 1466 CLEAR_BIT(reset_tags, tmpslot); 1467 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1468 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_RESET); 1469 } 1470 1471 ASSERT(reset_tags == 0); 1472 1473 /* Send up the unfinished_tags with SATA_PKT_BUSY. */ 1474 while (unfinished_tags) { 1475 tmpslot = ddi_ffs(unfinished_tags) - 1; 1476 if (tmpslot == -1) { 1477 break; 1478 } 1479 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1480 ASSERT(satapkt != NULL); 1481 SIDBG1(SIDBG_ERRS, si_ctlp, 1482 "si_mop_commands sending PKT_BUSY for " 1483 "retry spkt: %x", 1484 satapkt); 1485 1486 CLEAR_BIT(unfinished_tags, tmpslot); 1487 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1488 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_BUSY); 1489 } 1490 1491 ASSERT(unfinished_tags == 0); 1492 1493 si_portp->mopping_in_progress--; 1494 ASSERT(si_portp->mopping_in_progress >= 0); 1495 } 1496 1497 /* 1498 * Called by the sata framework to abort the previously sent packet(s). 1499 * 1500 * We reset the device and mop the commands on the port. 1501 */ 1502 static int 1503 si_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1504 { 1505 uint32_t slot_status; 1506 uint8_t port; 1507 int tmpslot; 1508 uint32_t aborting_tags; 1509 uint32_t finished_tags; 1510 si_port_state_t *si_portp; 1511 si_ctl_state_t *si_ctlp; 1512 1513 port = spkt->satapkt_device.satadev_addr.cport; 1514 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1515 mutex_enter(&si_ctlp->sictl_mutex); 1516 si_portp = si_ctlp->sictl_ports[port]; 1517 mutex_exit(&si_ctlp->sictl_mutex); 1518 1519 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_tran_abort on port: %x", port); 1520 1521 mutex_enter(&si_portp->siport_mutex); 1522 1523 /* 1524 * If already mopping, then no need to abort anything. 1525 */ 1526 if (si_portp->mopping_in_progress > 0) { 1527 SIDBG1(SIDBG_INFO, si_ctlp, 1528 "si_tran_abort: port %d mopping " 1529 "in progress, so just return", port); 1530 mutex_exit(&si_portp->siport_mutex); 1531 return (SATA_SUCCESS); 1532 } 1533 1534 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1535 !si_portp->siport_active) { 1536 /* 1537 * si_intr_phy_ready_change() may have rendered it to 1538 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1539 * it inactive. 1540 */ 1541 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1542 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1543 mutex_exit(&si_portp->siport_mutex); 1544 return (SATA_FAILURE); 1545 } 1546 1547 if (flag == SATA_ABORT_ALL_PACKETS) { 1548 aborting_tags = si_portp->siport_pending_tags; 1549 } else { 1550 /* 1551 * Need to abort a single packet. 1552 * Search our siport_slot_pkts[] list for matching spkt. 1553 */ 1554 aborting_tags = 0xffffffff; /* 0xffffffff is impossible tag */ 1555 for (tmpslot = 0; tmpslot < SI_NUM_SLOTS; tmpslot++) { 1556 if (si_portp->siport_slot_pkts[tmpslot] == spkt) { 1557 aborting_tags = (0x1 << tmpslot); 1558 break; 1559 } 1560 } 1561 1562 if (aborting_tags == 0xffffffff) { 1563 /* requested packet is not on pending list. */ 1564 fill_dev_sregisters(si_ctlp, port, 1565 &spkt->satapkt_device); 1566 mutex_exit(&si_portp->siport_mutex); 1567 return (SATA_FAILURE); 1568 } 1569 } 1570 1571 si_portp->mopping_in_progress++; 1572 1573 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1574 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1575 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, 1576 port, SI_DEVICE_RESET); 1577 1578 /* 1579 * Compute which have finished and which need to be retried. 1580 * 1581 * The finished tags are siport_pending_tags minus the slot_status. 1582 * The aborting_tags have to be reduced by finished_tags since we 1583 * can't possibly abort a tag which had finished already. 1584 */ 1585 finished_tags = si_portp->siport_pending_tags & 1586 ~slot_status & SI_SLOT_MASK; 1587 aborting_tags &= ~finished_tags; 1588 1589 si_mop_commands(si_ctlp, 1590 si_portp, 1591 port, 1592 slot_status, 1593 0, /* failed_tags */ 1594 0, /* timedout_tags */ 1595 aborting_tags, 1596 0); /* reset_tags */ 1597 1598 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1599 mutex_exit(&si_portp->siport_mutex); 1600 return (SATA_SUCCESS); 1601 } 1602 1603 1604 /* 1605 * Used to reject all the pending packets on a port during a reset 1606 * operation. 1607 * 1608 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 1609 * before calling us. 1610 */ 1611 static void 1612 si_reject_all_reset_pkts( 1613 si_ctl_state_t *si_ctlp, 1614 si_port_state_t *si_portp, 1615 int port) 1616 { 1617 uint32_t slot_status; 1618 uint32_t reset_tags; 1619 1620 _NOTE(ASSUMING_PROTECTED(si_portp)) 1621 1622 SIDBG1(SIDBG_ENTRY, si_ctlp, 1623 "si_reject_all_reset_pkts on port: %x", 1624 port); 1625 1626 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1627 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1628 1629 /* Compute which tags need to be sent up. */ 1630 reset_tags = slot_status & SI_SLOT_MASK; 1631 1632 si_portp->mopping_in_progress++; 1633 1634 si_mop_commands(si_ctlp, 1635 si_portp, 1636 port, 1637 slot_status, 1638 0, /* failed_tags */ 1639 0, /* timedout_tags */ 1640 0, /* aborting_tags */ 1641 reset_tags); 1642 } 1643 1644 1645 /* 1646 * Called by sata framework to reset a port(s) or device. 1647 * 1648 */ 1649 static int 1650 si_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 1651 { 1652 si_ctl_state_t *si_ctlp; 1653 uint8_t port = sd->satadev_addr.cport; 1654 int i; 1655 si_port_state_t *si_portp; 1656 int retval = SI_SUCCESS; 1657 1658 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1659 SIDBG1(SIDBG_ENTRY, si_ctlp, 1660 "si_tran_reset_port entry: port: 0x%x", 1661 port); 1662 1663 switch (sd->satadev_addr.qual) { 1664 case SATA_ADDR_CPORT: 1665 mutex_enter(&si_ctlp->sictl_mutex); 1666 si_portp = si_ctlp->sictl_ports[port]; 1667 mutex_exit(&si_ctlp->sictl_mutex); 1668 1669 mutex_enter(&si_portp->siport_mutex); 1670 1671 /* 1672 * If already mopping, then no need to reset or mop again. 1673 */ 1674 if (si_portp->mopping_in_progress > 0) { 1675 SIDBG1(SIDBG_INFO, si_ctlp, 1676 "si_tran_reset_dport: CPORT port %d mopping " 1677 "in progress, so just return", port); 1678 mutex_exit(&si_portp->siport_mutex); 1679 retval = SI_SUCCESS; 1680 break; 1681 } 1682 1683 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1684 SI_PORT_RESET); 1685 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1686 mutex_exit(&si_portp->siport_mutex); 1687 1688 break; 1689 1690 case SATA_ADDR_DCPORT: 1691 mutex_enter(&si_ctlp->sictl_mutex); 1692 si_portp = si_ctlp->sictl_ports[port]; 1693 mutex_exit(&si_ctlp->sictl_mutex); 1694 1695 mutex_enter(&si_portp->siport_mutex); 1696 1697 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1698 !si_portp->siport_active) { 1699 mutex_exit(&si_portp->siport_mutex); 1700 retval = SI_FAILURE; 1701 break; 1702 } 1703 1704 /* 1705 * If already mopping, then no need to reset or mop again. 1706 */ 1707 if (si_portp->mopping_in_progress > 0) { 1708 SIDBG1(SIDBG_INFO, si_ctlp, 1709 "si_tran_reset_dport: DCPORT port %d mopping " 1710 "in progress, so just return", port); 1711 mutex_exit(&si_portp->siport_mutex); 1712 retval = SI_SUCCESS; 1713 break; 1714 } 1715 1716 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1717 SI_DEVICE_RESET); 1718 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1719 mutex_exit(&si_portp->siport_mutex); 1720 1721 break; 1722 1723 case SATA_ADDR_CNTRL: 1724 for (i = 0; i < si_ctlp->sictl_num_ports; i++) { 1725 mutex_enter(&si_ctlp->sictl_mutex); 1726 si_portp = si_ctlp->sictl_ports[i]; 1727 mutex_exit(&si_ctlp->sictl_mutex); 1728 1729 mutex_enter(&si_portp->siport_mutex); 1730 1731 /* 1732 * If mopping, then all the pending commands are being 1733 * mopped, therefore there is nothing else to do. 1734 */ 1735 if (si_portp->mopping_in_progress > 0) { 1736 SIDBG1(SIDBG_INFO, si_ctlp, 1737 "si_tran_reset_dport: CNTRL port %d mopping" 1738 " in progress, so just return", i); 1739 mutex_exit(&si_portp->siport_mutex); 1740 retval = SI_SUCCESS; 1741 break; 1742 } 1743 1744 retval = si_reset_dport_wait_till_ready(si_ctlp, 1745 si_portp, i, SI_PORT_RESET); 1746 if (retval) { 1747 mutex_exit(&si_portp->siport_mutex); 1748 break; 1749 } 1750 si_reject_all_reset_pkts(si_ctlp, si_portp, i); 1751 mutex_exit(&si_portp->siport_mutex); 1752 } 1753 break; 1754 1755 case SATA_ADDR_PMPORT: 1756 case SATA_ADDR_DPMPORT: 1757 SIDBG0(SIDBG_VERBOSE, si_ctlp, 1758 "port mult reset not implemented yet"); 1759 /* FALLSTHROUGH */ 1760 1761 default: 1762 retval = SI_FAILURE; 1763 1764 } 1765 1766 return (retval); 1767 } 1768 1769 1770 /* 1771 * Called by sata framework to activate a port as part of hotplug. 1772 * 1773 * Note: Not port-mult aware. 1774 */ 1775 static int 1776 si_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 1777 { 1778 si_ctl_state_t *si_ctlp; 1779 si_port_state_t *si_portp; 1780 uint8_t port; 1781 1782 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1783 port = satadev->satadev_addr.cport; 1784 mutex_enter(&si_ctlp->sictl_mutex); 1785 si_portp = si_ctlp->sictl_ports[port]; 1786 mutex_exit(&si_ctlp->sictl_mutex); 1787 1788 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_tran_hotplug_port_activate entry"); 1789 1790 mutex_enter(&si_portp->siport_mutex); 1791 si_enable_port_interrupts(si_ctlp, port); 1792 1793 /* 1794 * Reset the device so that a si_find_dev_signature() would trigger. 1795 * But this reset is an internal operation; the sata framework does 1796 * not need to know about it. 1797 */ 1798 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1799 SI_DEVICE_RESET|SI_RESET_NO_EVENTS_UP); 1800 1801 satadev->satadev_state = SATA_STATE_READY; 1802 1803 si_portp->siport_active = PORT_ACTIVE; 1804 1805 fill_dev_sregisters(si_ctlp, port, satadev); 1806 1807 mutex_exit(&si_portp->siport_mutex); 1808 return (SATA_SUCCESS); 1809 } 1810 1811 /* 1812 * Called by sata framework to deactivate a port as part of hotplug. 1813 * 1814 * Note: Not port-mult aware. 1815 */ 1816 static int 1817 si_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 1818 { 1819 si_ctl_state_t *si_ctlp; 1820 si_port_state_t *si_portp; 1821 uint8_t port; 1822 1823 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1824 port = satadev->satadev_addr.cport; 1825 mutex_enter(&si_ctlp->sictl_mutex); 1826 si_portp = si_ctlp->sictl_ports[port]; 1827 mutex_exit(&si_ctlp->sictl_mutex); 1828 1829 SIDBG0(SIDBG_ENTRY, NULL, "si_tran_hotplug_port_deactivate entry"); 1830 1831 mutex_enter(&si_portp->siport_mutex); 1832 if (si_portp->siport_pending_tags & SI_SLOT_MASK) { 1833 /* 1834 * There are pending commands on this port. 1835 * Fail the deactivate request. 1836 */ 1837 satadev->satadev_state = SATA_STATE_READY; 1838 mutex_exit(&si_portp->siport_mutex); 1839 return (SATA_FAILURE); 1840 } 1841 1842 /* mark the device as not accessible any more. */ 1843 si_portp->siport_active = PORT_INACTIVE; 1844 1845 /* disable the interrupts on the port. */ 1846 si_disable_port_interrupts(si_ctlp, port); 1847 1848 satadev->satadev_state = SATA_PSTATE_SHUTDOWN; 1849 1850 fill_dev_sregisters(si_ctlp, port, satadev); 1851 /* 1852 * Since we are implementing the port deactivation in software only, 1853 * we need to fake a valid value for sstatus. 1854 */ 1855 SSTATUS_SET_DET(satadev->satadev_scr.sstatus, SSTATUS_DET_PHYOFFLINE); 1856 SSTATUS_SET_IPM(satadev->satadev_scr.sstatus, SSTATUS_IPM_NODEV_NOPHY); 1857 1858 mutex_exit(&si_portp->siport_mutex); 1859 return (SATA_SUCCESS); 1860 } 1861 1862 1863 /* 1864 * Allocates the si_port_state_t. 1865 */ 1866 static int 1867 si_alloc_port_state(si_ctl_state_t *si_ctlp, int port) 1868 { 1869 si_port_state_t *si_portp; 1870 1871 si_ctlp->sictl_ports[port] = (si_port_state_t *)kmem_zalloc( 1872 sizeof (si_port_state_t), KM_SLEEP); 1873 1874 si_portp = si_ctlp->sictl_ports[port]; 1875 mutex_init(&si_portp->siport_mutex, NULL, MUTEX_DRIVER, 1876 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 1877 mutex_enter(&si_portp->siport_mutex); 1878 1879 /* allocate prb & sgt pkts for this port. */ 1880 if (si_alloc_prbpool(si_ctlp, port)) { 1881 mutex_exit(&si_portp->siport_mutex); 1882 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1883 return (SI_FAILURE); 1884 } 1885 if (si_alloc_sgbpool(si_ctlp, port)) { 1886 si_dealloc_prbpool(si_ctlp, port); 1887 mutex_exit(&si_portp->siport_mutex); 1888 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1889 return (SI_FAILURE); 1890 } 1891 1892 si_portp->siport_active = PORT_ACTIVE; 1893 mutex_exit(&si_portp->siport_mutex); 1894 1895 return (SI_SUCCESS); 1896 1897 } 1898 1899 /* 1900 * Deallocates the si_port_state_t. 1901 */ 1902 static void 1903 si_dealloc_port_state(si_ctl_state_t *si_ctlp, int port) 1904 { 1905 si_port_state_t *si_portp; 1906 si_portp = si_ctlp->sictl_ports[port]; 1907 1908 mutex_enter(&si_portp->siport_mutex); 1909 si_dealloc_sgbpool(si_ctlp, port); 1910 si_dealloc_prbpool(si_ctlp, port); 1911 mutex_exit(&si_portp->siport_mutex); 1912 1913 mutex_destroy(&si_portp->siport_mutex); 1914 1915 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1916 1917 } 1918 1919 /* 1920 * Allocates the SGB (Scatter Gather Block) incore buffer. 1921 */ 1922 static int 1923 si_alloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1924 { 1925 si_port_state_t *si_portp; 1926 uint_t cookie_count; 1927 size_t incore_sgbpool_size = SI_NUM_SLOTS * sizeof (si_sgblock_t); 1928 size_t ret_len; 1929 ddi_dma_cookie_t sgbpool_dma_cookie; 1930 1931 si_portp = si_ctlp->sictl_ports[port]; 1932 1933 /* allocate sgbpool dma handle. */ 1934 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 1935 &prb_sgt_dma_attr, 1936 DDI_DMA_SLEEP, 1937 NULL, 1938 &si_portp->siport_sgbpool_dma_handle) != 1939 DDI_SUCCESS) { 1940 1941 return (SI_FAILURE); 1942 } 1943 1944 /* allocate the memory for sgbpool. */ 1945 if (ddi_dma_mem_alloc(si_portp->siport_sgbpool_dma_handle, 1946 incore_sgbpool_size, 1947 &accattr, 1948 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1949 DDI_DMA_SLEEP, 1950 NULL, 1951 (caddr_t *)&si_portp->siport_sgbpool, 1952 &ret_len, 1953 &si_portp->siport_sgbpool_acc_handle) != NULL) { 1954 1955 /* error.. free the dma handle. */ 1956 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1957 return (SI_FAILURE); 1958 } 1959 1960 /* now bind it */ 1961 if (ddi_dma_addr_bind_handle(si_portp->siport_sgbpool_dma_handle, 1962 NULL, 1963 (caddr_t)si_portp->siport_sgbpool, 1964 incore_sgbpool_size, 1965 DDI_DMA_CONSISTENT, 1966 DDI_DMA_SLEEP, 1967 NULL, 1968 &sgbpool_dma_cookie, 1969 &cookie_count) != DDI_DMA_MAPPED) { 1970 /* error.. free the dma handle & free the memory. */ 1971 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1972 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1973 return (SI_FAILURE); 1974 } 1975 1976 si_portp->siport_sgbpool_physaddr = sgbpool_dma_cookie.dmac_laddress; 1977 return (SI_SUCCESS); 1978 } 1979 1980 /* 1981 * Deallocates the SGB (Scatter Gather Block) incore buffer. 1982 */ 1983 static void 1984 si_dealloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1985 { 1986 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 1987 1988 /* Unbind the dma handle first. */ 1989 (void) ddi_dma_unbind_handle(si_portp->siport_sgbpool_dma_handle); 1990 1991 /* Then free the underlying memory. */ 1992 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1993 1994 /* Now free the handle itself. */ 1995 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1996 1997 } 1998 1999 /* 2000 * Allocates the PRB (Port Request Block) incore packets. 2001 */ 2002 static int 2003 si_alloc_prbpool(si_ctl_state_t *si_ctlp, int port) 2004 { 2005 si_port_state_t *si_portp; 2006 uint_t cookie_count; 2007 size_t incore_pkt_size = SI_NUM_SLOTS * sizeof (si_prb_t); 2008 size_t ret_len; 2009 ddi_dma_cookie_t prbpool_dma_cookie; 2010 2011 si_portp = si_ctlp->sictl_ports[port]; 2012 2013 /* allocate prb pkts. */ 2014 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 2015 &prb_sgt_dma_attr, 2016 DDI_DMA_SLEEP, 2017 NULL, 2018 &si_portp->siport_prbpool_dma_handle) != 2019 DDI_SUCCESS) { 2020 2021 return (SI_FAILURE); 2022 } 2023 2024 if (ddi_dma_mem_alloc(si_portp->siport_prbpool_dma_handle, 2025 incore_pkt_size, 2026 &accattr, 2027 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2028 DDI_DMA_SLEEP, 2029 NULL, 2030 (caddr_t *)&si_portp->siport_prbpool, 2031 &ret_len, 2032 &si_portp->siport_prbpool_acc_handle) != NULL) { 2033 2034 /* error.. free the dma handle. */ 2035 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2036 return (SI_FAILURE); 2037 } 2038 2039 if (ddi_dma_addr_bind_handle(si_portp->siport_prbpool_dma_handle, 2040 NULL, 2041 (caddr_t)si_portp->siport_prbpool, 2042 incore_pkt_size, 2043 DDI_DMA_CONSISTENT, 2044 DDI_DMA_SLEEP, 2045 NULL, 2046 &prbpool_dma_cookie, 2047 &cookie_count) != DDI_DMA_MAPPED) { 2048 /* error.. free the dma handle & free the memory. */ 2049 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2050 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2051 return (SI_FAILURE); 2052 } 2053 2054 si_portp->siport_prbpool_physaddr = 2055 prbpool_dma_cookie.dmac_laddress; 2056 return (SI_SUCCESS); 2057 } 2058 2059 /* 2060 * Deallocates the PRB (Port Request Block) incore packets. 2061 */ 2062 static void 2063 si_dealloc_prbpool(si_ctl_state_t *si_ctlp, int port) 2064 { 2065 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 2066 2067 /* Unbind the prb dma handle first. */ 2068 (void) ddi_dma_unbind_handle(si_portp->siport_prbpool_dma_handle); 2069 2070 /* Then free the underlying memory. */ 2071 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2072 2073 /* Now free the handle itself. */ 2074 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2075 2076 } 2077 2078 2079 2080 /* 2081 * Soft-reset the port to find the signature of the device connected to 2082 * the port. 2083 */ 2084 static void 2085 si_find_dev_signature( 2086 si_ctl_state_t *si_ctlp, 2087 si_port_state_t *si_portp, 2088 int port, 2089 int pmp) 2090 { 2091 si_prb_t *prb; 2092 uint32_t slot_status, signature; 2093 int slot, loop_count; 2094 2095 SIDBG2(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 2096 "si_find_dev_signature enter: port: %x, pmp: %x", 2097 port, pmp); 2098 2099 /* Build a Soft Reset PRB in host memory. */ 2100 mutex_enter(&si_portp->siport_mutex); 2101 2102 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2103 if (slot == -1) { 2104 /* Empty slot could not be found. */ 2105 if (pmp != PORTMULT_CONTROL_PORT) { 2106 /* We are behind port multiplier. */ 2107 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2108 PORT_TYPE_NODEV; 2109 } else { 2110 si_portp->siport_port_type = PORT_TYPE_NODEV; 2111 } 2112 2113 mutex_exit(&si_portp->siport_mutex); 2114 return; 2115 } 2116 prb = &si_portp->siport_prbpool[slot]; 2117 bzero((void *)prb, sizeof (si_prb_t)); 2118 2119 SET_FIS_PMP(prb->prb_fis, pmp); 2120 SET_PRB_CONTROL_SOFT_RESET(prb); 2121 2122 #if SI_DEBUG 2123 if (si_debug_flags & SIDBG_DUMP_PRB) { 2124 char *ptr; 2125 int j; 2126 2127 ptr = (char *)prb; 2128 cmn_err(CE_WARN, "si_find_dev_signature, prb: "); 2129 for (j = 0; j < (sizeof (si_prb_t)); j++) { 2130 if (j%4 == 0) { 2131 cmn_err(CE_WARN, "----"); 2132 } 2133 cmn_err(CE_WARN, "%x ", ptr[j]); 2134 } 2135 2136 } 2137 #endif /* SI_DEBUG */ 2138 2139 /* deliver soft reset prb to empty slot. */ 2140 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2141 2142 loop_count = 0; 2143 /* Loop till the soft reset is finished. */ 2144 do { 2145 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2146 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2147 2148 if (loop_count++ > SI_POLLRATE_SOFT_RESET) { 2149 /* We are effectively timing out after 10 sec. */ 2150 break; 2151 } 2152 2153 /* Wait for 10 millisec */ 2154 #ifndef __lock_lint 2155 delay(SI_10MS_TICKS); 2156 #endif /* __lock_lint */ 2157 2158 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 2159 2160 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 2161 "si_find_dev_signature: loop count: %d, slot_status: 0x%x", 2162 loop_count, slot_status); 2163 2164 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2165 2166 /* Read device signature from command slot. */ 2167 signature = ddi_get32(si_ctlp->sictl_port_acc_handle, 2168 (uint32_t *)(PORT_SIGNATURE_MSB(si_ctlp, port, slot))); 2169 signature <<= 8; 2170 signature |= (0xff & ddi_get32(si_ctlp->sictl_port_acc_handle, 2171 (uint32_t *)(PORT_SIGNATURE_LSB(si_ctlp, 2172 port, slot)))); 2173 2174 SIDBG1(SIDBG_INIT, si_ctlp, "Device signature: 0x%x", signature); 2175 2176 if (signature == SI_SIGNATURE_PORT_MULTIPLIER) { 2177 2178 SIDBG2(SIDBG_INIT, si_ctlp, 2179 "Found multiplier at cport: 0x%d, pmport: 0x%x", 2180 port, pmp); 2181 2182 if (pmp != PORTMULT_CONTROL_PORT) { 2183 /* 2184 * It is wrong to chain a port multiplier behind 2185 * another port multiplier. 2186 */ 2187 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2188 PORT_TYPE_NODEV; 2189 } else { 2190 si_portp->siport_port_type = PORT_TYPE_MULTIPLIER; 2191 mutex_exit(&si_portp->siport_mutex); 2192 (void) si_enumerate_port_multiplier(si_ctlp, 2193 si_portp, port); 2194 mutex_enter(&si_portp->siport_mutex); 2195 } 2196 si_init_port(si_ctlp, port); 2197 2198 } else if (signature == SI_SIGNATURE_ATAPI) { 2199 if (pmp != PORTMULT_CONTROL_PORT) { 2200 /* We are behind port multiplier. */ 2201 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2202 PORT_TYPE_ATAPI; 2203 } else { 2204 si_portp->siport_port_type = PORT_TYPE_ATAPI; 2205 si_init_port(si_ctlp, port); 2206 } 2207 SIDBG2(SIDBG_INIT, si_ctlp, 2208 "Found atapi at : cport: %x, pmport: %x", 2209 port, pmp); 2210 2211 } else if (signature == SI_SIGNATURE_DISK) { 2212 2213 if (pmp != PORTMULT_CONTROL_PORT) { 2214 /* We are behind port multiplier. */ 2215 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2216 PORT_TYPE_DISK; 2217 } else { 2218 si_portp->siport_port_type = PORT_TYPE_DISK; 2219 si_init_port(si_ctlp, port); 2220 } 2221 SIDBG2(SIDBG_INIT, si_ctlp, 2222 "found disk at : cport: %x, pmport: %x", 2223 port, pmp); 2224 2225 } else { 2226 if (pmp != PORTMULT_CONTROL_PORT) { 2227 /* We are behind port multiplier. */ 2228 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2229 PORT_TYPE_UNKNOWN; 2230 } else { 2231 si_portp->siport_port_type = PORT_TYPE_UNKNOWN; 2232 } 2233 SIDBG3(SIDBG_INIT, si_ctlp, 2234 "Found unknown signature 0x%x at: port: %x, pmp: %x", 2235 signature, port, pmp); 2236 } 2237 2238 mutex_exit(&si_portp->siport_mutex); 2239 } 2240 2241 2242 /* 2243 * Polls for the completion of the command. This is safe with both 2244 * interrupts enabled or disabled. 2245 */ 2246 static void 2247 si_poll_cmd( 2248 si_ctl_state_t *si_ctlp, 2249 si_port_state_t *si_portp, 2250 int port, 2251 int slot, 2252 sata_pkt_t *satapkt) 2253 { 2254 uint32_t slot_status; 2255 int pkt_timeout_ticks; 2256 uint32_t port_intr_status; 2257 int in_panic = ddi_in_panic(); 2258 2259 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_poll_cmd entered: port: 0x%x", port); 2260 2261 pkt_timeout_ticks = drv_usectohz((clock_t)satapkt->satapkt_time * 2262 1000000); 2263 2264 2265 /* we start out with SATA_PKT_COMPLETED as the satapkt_reason */ 2266 satapkt->satapkt_reason = SATA_PKT_COMPLETED; 2267 2268 do { 2269 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2270 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2271 2272 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2273 if (in_panic) { 2274 /* 2275 * If we are in panic, we can't rely on 2276 * timers; so, busy wait instead of delay(). 2277 */ 2278 mutex_exit(&si_portp->siport_mutex); 2279 drv_usecwait(SI_1MS_USECS); 2280 mutex_enter(&si_portp->siport_mutex); 2281 } else { 2282 mutex_exit(&si_portp->siport_mutex); 2283 #ifndef __lock_lint 2284 delay(SI_1MS_TICKS); 2285 #endif /* __lock_lint */ 2286 mutex_enter(&si_portp->siport_mutex); 2287 } 2288 } else { 2289 break; 2290 } 2291 2292 pkt_timeout_ticks -= SI_1MS_TICKS; 2293 2294 } while (pkt_timeout_ticks > 0); 2295 2296 if (satapkt->satapkt_reason != SATA_PKT_COMPLETED) { 2297 /* The si_mop_command() got to our packet before us */ 2298 2299 return; 2300 } 2301 2302 /* 2303 * Interrupts and timers may not be working properly in a crash dump 2304 * situation; we may need to handle all the three conditions here: 2305 * successful completion, packet failure and packet timeout. 2306 */ 2307 if (IS_ATTENTION_RAISED(slot_status)) { /* error seen on port */ 2308 2309 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 2310 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 2311 2312 SIDBG2(SIDBG_VERBOSE, si_ctlp, 2313 "si_poll_cmd: port_intr_status: 0x%x, port: %x", 2314 port_intr_status, port); 2315 2316 if (port_intr_status & INTR_COMMAND_ERROR) { 2317 mutex_exit(&si_portp->siport_mutex); 2318 (void) si_intr_command_error(si_ctlp, si_portp, port); 2319 mutex_enter(&si_portp->siport_mutex); 2320 2321 return; 2322 2323 /* 2324 * Why do we need to call si_intr_command_error() ? 2325 * 2326 * Answer: Even if the current packet is not the 2327 * offending command, we need to restart the stalled 2328 * port; (may be, the interrupts are not working well 2329 * in panic condition). The call to routine 2330 * si_intr_command_error() will achieve that. 2331 * 2332 * What if the interrupts are working fine and the 2333 * si_intr_command_error() gets called once more from 2334 * interrupt context ? 2335 * 2336 * Answer: The second instance of routine 2337 * si_intr_command_error() will not mop anything 2338 * since the first error handler has already blown 2339 * away the hardware pending queues through reset. 2340 * 2341 * Will the si_intr_command_error() hurt current 2342 * packet ? 2343 * 2344 * Answer: No. 2345 */ 2346 } else { 2347 /* Ignore any non-error interrupts at this stage */ 2348 ddi_put32(si_ctlp->sictl_port_acc_handle, 2349 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, 2350 port)), 2351 port_intr_status & INTR_MASK); 2352 } 2353 2354 } else if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2355 satapkt->satapkt_reason = SATA_PKT_TIMEOUT; 2356 2357 } /* else: the command completed successfully */ 2358 2359 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 2360 si_copy_out_regs(&satapkt->satapkt_cmd, si_ctlp, port, slot); 2361 } 2362 2363 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == 2364 SATAC_WRITE_FPDMA_QUEUED) || 2365 (satapkt->satapkt_cmd.satacmd_cmd_reg == 2366 SATAC_READ_FPDMA_QUEUED)) { 2367 si_portp->siport_pending_ncq_count--; 2368 } 2369 2370 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2371 2372 /* 2373 * tidbit: What is the interaction of abort with polling ? 2374 * What happens if the current polled pkt is aborted in parallel ? 2375 * 2376 * Answer: Assuming that the si_mop_commands() completes ahead 2377 * of polling, all it does is to set the satapkt_reason to 2378 * SPKT_PKT_ABORTED. That would be fine with us. 2379 * 2380 * The same logic applies to reset interacting with polling. 2381 */ 2382 } 2383 2384 2385 /* 2386 * Searches for and claims a free slot. 2387 * 2388 * Returns: SI_FAILURE if no slots found 2389 * claimed slot number if successful 2390 * 2391 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2392 * before calling us. 2393 */ 2394 /*ARGSUSED*/ 2395 static int 2396 si_claim_free_slot(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 2397 { 2398 uint32_t free_slots; 2399 int slot; 2400 2401 _NOTE(ASSUMING_PROTECTED(si_portp)) 2402 2403 SIDBG1(SIDBG_ENTRY, si_ctlp, 2404 "si_claim_free_slot entry: siport_pending_tags: %x", 2405 si_portp->siport_pending_tags); 2406 2407 free_slots = (~si_portp->siport_pending_tags) & SI_SLOT_MASK; 2408 slot = ddi_ffs(free_slots) - 1; 2409 if (slot == -1) { 2410 SIDBG0(SIDBG_VERBOSE, si_ctlp, 2411 "si_claim_free_slot: no empty slots"); 2412 return (SI_FAILURE); 2413 } 2414 2415 si_portp->siport_pending_tags |= (0x1 << slot); 2416 SIDBG1(SIDBG_VERBOSE, si_ctlp, "si_claim_free_slot: found slot: 0x%x", 2417 slot); 2418 return (slot); 2419 } 2420 2421 /* 2422 * Builds the PRB for the sata packet and delivers it to controller. 2423 * 2424 * Returns: 2425 * slot number if we can obtain a slot successfully 2426 * otherwise, return SI_FAILURE 2427 * 2428 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2429 * before calling us. 2430 */ 2431 static int 2432 si_deliver_satapkt( 2433 si_ctl_state_t *si_ctlp, 2434 si_port_state_t *si_portp, 2435 int port, 2436 sata_pkt_t *spkt) 2437 { 2438 int slot; 2439 si_prb_t *prb; 2440 sata_cmd_t *cmd; 2441 si_sge_t *sgep; /* scatter gather entry pointer */ 2442 si_sgt_t *sgtp; /* scatter gather table pointer */ 2443 si_sgblock_t *sgbp; /* scatter gather block pointer */ 2444 int i, j, cookie_index; 2445 int ncookies; 2446 int is_atapi = 0; 2447 ddi_dma_cookie_t cookie; 2448 2449 _NOTE(ASSUMING_PROTECTED(si_portp)) 2450 2451 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2452 if (slot == -1) { 2453 return (SI_FAILURE); 2454 } 2455 2456 if (spkt->satapkt_device.satadev_type == SATA_DTYPE_ATAPICD) { 2457 is_atapi = 1; 2458 } 2459 2460 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 2461 !si_portp->siport_active) { 2462 /* 2463 * si_intr_phy_ready_change() may have rendered it to 2464 * PORT_TYPE_NODEV. cfgadm operation may have rendered 2465 * it inactive. 2466 */ 2467 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2468 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 2469 2470 return (SI_FAILURE); 2471 } 2472 2473 2474 prb = &(si_portp->siport_prbpool[slot]); 2475 bzero((void *)prb, sizeof (si_prb_t)); 2476 2477 cmd = &spkt->satapkt_cmd; 2478 2479 SIDBG4(SIDBG_ENTRY, si_ctlp, 2480 "si_deliver_satpkt entry: cmd_reg: 0x%x, slot: 0x%x, \ 2481 port: %x, satapkt: %x", 2482 cmd->satacmd_cmd_reg, slot, port, (uint32_t)(intptr_t)spkt); 2483 2484 /* Now fill the prb. */ 2485 if (is_atapi) { 2486 if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction == 2487 SATA_DIR_READ) { 2488 SET_PRB_CONTROL_PKT_READ(prb); 2489 } else if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction 2490 == SATA_DIR_WRITE) { 2491 SET_PRB_CONTROL_PKT_WRITE(prb); 2492 } 2493 } 2494 2495 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 2496 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 2497 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 2498 SET_FIS_PMP(prb->prb_fis, 2499 spkt->satapkt_device.satadev_addr.pmport); 2500 } 2501 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 2502 SET_FIS_COMMAND(prb->prb_fis, cmd->satacmd_cmd_reg); 2503 SET_FIS_FEATURES(prb->prb_fis, cmd->satacmd_features_reg); 2504 SET_FIS_SECTOR_COUNT(prb->prb_fis, cmd->satacmd_sec_count_lsb); 2505 2506 switch (cmd->satacmd_addr_type) { 2507 2508 case ATA_ADDR_LBA: 2509 /* fallthru */ 2510 2511 case ATA_ADDR_LBA28: 2512 /* LBA[7:0] */ 2513 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2514 2515 /* LBA[15:8] */ 2516 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2517 2518 /* LBA[23:16] */ 2519 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2520 2521 /* LBA [27:24] (also called dev_head) */ 2522 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2523 2524 break; 2525 2526 case ATA_ADDR_LBA48: 2527 /* LBA[7:0] */ 2528 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2529 2530 /* LBA[15:8] */ 2531 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2532 2533 /* LBA[23:16] */ 2534 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2535 2536 /* LBA [31:24] */ 2537 SET_FIS_SECTOR_EXP(prb->prb_fis, cmd->satacmd_lba_low_msb); 2538 2539 /* LBA [39:32] */ 2540 SET_FIS_CYL_LOW_EXP(prb->prb_fis, cmd->satacmd_lba_mid_msb); 2541 2542 /* LBA [47:40] */ 2543 SET_FIS_CYL_HI_EXP(prb->prb_fis, cmd->satacmd_lba_high_msb); 2544 2545 /* Set dev_head */ 2546 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2547 2548 /* Set the extended sector count and features */ 2549 SET_FIS_SECTOR_COUNT_EXP(prb->prb_fis, 2550 cmd->satacmd_sec_count_msb); 2551 SET_FIS_FEATURES_EXP(prb->prb_fis, 2552 cmd->satacmd_features_reg_ext); 2553 2554 break; 2555 2556 } 2557 2558 if (cmd->satacmd_flags.sata_queued) { 2559 /* 2560 * For queued commands, the TAG for the sector count lsb is 2561 * generated from current slot number. 2562 */ 2563 SET_FIS_SECTOR_COUNT(prb->prb_fis, slot << 3); 2564 } 2565 2566 if ((cmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) || 2567 (cmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED)) { 2568 si_portp->siport_pending_ncq_count++; 2569 } 2570 2571 /* *** now fill the scatter gather list ******* */ 2572 2573 if (is_atapi) { /* It is an ATAPI drive */ 2574 /* atapi command goes into sge0 */ 2575 bcopy(cmd->satacmd_acdb, &prb->prb_sge0, sizeof (si_sge_t)); 2576 2577 /* Now fill sge1 with pointer to external SGT. */ 2578 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2579 prb->prb_sge1.sge_addr = 2580 si_portp->siport_sgbpool_physaddr + 2581 slot*sizeof (si_sgblock_t); 2582 SET_SGE_LNK(prb->prb_sge1); 2583 } else { 2584 SET_SGE_TRM(prb->prb_sge1); 2585 } 2586 } else { 2587 /* Fill the sge0 */ 2588 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2589 prb->prb_sge0.sge_addr = 2590 si_portp->siport_sgbpool_physaddr + 2591 slot*sizeof (si_sgblock_t); 2592 SET_SGE_LNK(prb->prb_sge0); 2593 2594 } else { 2595 SET_SGE_TRM(prb->prb_sge0); 2596 } 2597 2598 /* sge1 is left empty in non-ATAPI case */ 2599 } 2600 2601 bzero(&si_portp->siport_sgbpool[slot], sizeof (si_sgblock_t)); 2602 2603 ncookies = spkt->satapkt_cmd.satacmd_num_dma_cookies; 2604 ASSERT(ncookies <= SI_MAX_SGL_LENGTH); 2605 2606 SIDBG1(SIDBG_COOKIES, si_ctlp, "total ncookies: %d", ncookies); 2607 if (ncookies == 0) { 2608 sgbp = &si_portp->siport_sgbpool[slot]; 2609 sgtp = &sgbp->sgb_sgt[0]; 2610 sgep = &sgtp->sgt_sge[0]; 2611 2612 /* No cookies. Terminate the chain. */ 2613 SIDBG0(SIDBG_COOKIES, si_ctlp, "empty cookies: terminating."); 2614 2615 sgep->sge_addr_low = 0; 2616 sgep->sge_addr_high = 0; 2617 sgep->sge_data_count = 0; 2618 SET_SGE_TRM((*sgep)); 2619 2620 goto sgl_fill_done; 2621 } 2622 2623 for (i = 0, cookie_index = 0, sgbp = &si_portp->siport_sgbpool[slot]; 2624 i < SI_MAX_SGT_TABLES_PER_PRB; i++) { 2625 2626 sgtp = &sgbp->sgb_sgt[i]; 2627 2628 /* Now fill the first 3 entries of SGT in the loop below. */ 2629 for (j = 0, sgep = &sgtp->sgt_sge[0]; 2630 ((j < 3) && (cookie_index < ncookies-1)); 2631 j++, cookie_index++, sgep++) { 2632 ASSERT(cookie_index < ncookies); 2633 SIDBG2(SIDBG_COOKIES, si_ctlp, 2634 "inner loop: cookie_index: %d, ncookies: %d", 2635 cookie_index, 2636 ncookies); 2637 cookie = spkt->satapkt_cmd. 2638 satacmd_dma_cookie_list[cookie_index]; 2639 2640 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2641 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2642 sgep->sge_data_count = (uint32_t)cookie.dmac_size; 2643 } 2644 2645 /* 2646 * If this happens to be the last cookie, we terminate it here. 2647 * Otherwise, we link to next SGT. 2648 */ 2649 2650 if (cookie_index == ncookies-1) { 2651 /* This is the last cookie. Terminate the chain. */ 2652 SIDBG2(SIDBG_COOKIES, si_ctlp, 2653 "filling the last: cookie_index: %d, " 2654 "ncookies: %d", 2655 cookie_index, 2656 ncookies); 2657 cookie = spkt->satapkt_cmd. 2658 satacmd_dma_cookie_list[cookie_index]; 2659 2660 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2661 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2662 sgep->sge_data_count = (uint32_t)cookie.dmac_size; 2663 SET_SGE_TRM((*sgep)); 2664 2665 break; /* we break the loop */ 2666 2667 } else { 2668 /* This is not the last one. So link it. */ 2669 SIDBG2(SIDBG_COOKIES, si_ctlp, 2670 "linking SGT: cookie_index: %d, ncookies: %d", 2671 cookie_index, 2672 ncookies); 2673 sgep->sge_addr = si_portp->siport_sgbpool_physaddr + 2674 slot * sizeof (si_sgblock_t) + 2675 (i+1) * sizeof (si_sgt_t); 2676 2677 SET_SGE_LNK((*sgep)); 2678 } 2679 2680 } 2681 2682 /* *** finished filling the scatter gather list ******* */ 2683 2684 sgl_fill_done: 2685 /* Now remember the sata packet in siport_slot_pkts[]. */ 2686 si_portp->siport_slot_pkts[slot] = spkt; 2687 2688 /* 2689 * We are overloading satapkt_hba_driver_private with 2690 * watched_cycle count. 2691 */ 2692 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 2693 2694 if (is_atapi) { 2695 /* program the packet_lenth if it is atapi device. */ 2696 2697 2698 #ifdef ATAPI_2nd_PHASE 2699 /* 2700 * Framework needs to calculate the acdb_len based on 2701 * identify packet data. This needs to be accomplished 2702 * in second phase of the project. 2703 */ 2704 ASSERT((cmd->satacmd_acdb_len == 12) || 2705 (cmd->satacmd_acdb_len == 16)); 2706 SIDBG1(SIDBG_VERBOSE, si_ctlp, "deliver: acdb_len: %d", 2707 cmd->satacmd_acdb_len); 2708 2709 if (cmd->satacmd_acdb_len == 16) { 2710 ddi_put32(si_ctlp->sictl_port_acc_handle, 2711 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 2712 PORT_CONTROL_SET_BITS_PACKET_LEN); 2713 } else { 2714 ddi_put32(si_ctlp->sictl_port_acc_handle, 2715 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2716 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2717 } 2718 2719 #else /* ATAPI_2nd_PHASE */ 2720 /* hard coding for now to 12 bytes */ 2721 ddi_put32(si_ctlp->sictl_port_acc_handle, 2722 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2723 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2724 #endif /* ATAPI_2nd_PHASE */ 2725 } 2726 2727 2728 #if SI_DEBUG 2729 if (si_debug_flags & SIDBG_DUMP_PRB) { 2730 if (!(is_atapi && (prb->prb_sge0.sge_addr_low == 0))) { 2731 /* 2732 * Do not dump the atapi Test-Unit-Ready commands. 2733 * The sd_media_watch spews too many of these. 2734 */ 2735 int *ptr; 2736 si_sge_t *tmpsgep; 2737 int j; 2738 2739 ptr = (int *)(void *)prb; 2740 cmn_err(CE_WARN, "si_deliver_satpkt prb: "); 2741 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 2742 cmn_err(CE_WARN, "%x ", ptr[j]); 2743 } 2744 2745 cmn_err(CE_WARN, 2746 "si_deliver_satpkt sgt: low, high, count link"); 2747 for (j = 0, 2748 tmpsgep = (si_sge_t *) 2749 &si_portp->siport_sgbpool[slot]; 2750 j < (sizeof (si_sgblock_t)/ sizeof (si_sge_t)); 2751 j++, tmpsgep++) { 2752 ptr = (int *)(void *)tmpsgep; 2753 cmn_err(CE_WARN, "%x %x %x %x", 2754 ptr[0], 2755 ptr[1], 2756 ptr[2], 2757 ptr[3]); 2758 if (IS_SGE_TRM_SET((*tmpsgep))) { 2759 break; 2760 } 2761 2762 } 2763 } 2764 2765 } 2766 #endif /* SI_DEBUG */ 2767 2768 /* Deliver PRB */ 2769 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2770 2771 return (slot); 2772 } 2773 2774 /* 2775 * Initialize the controller and set up driver data structures. 2776 * 2777 * This routine can be called from three separate cases: DDI_ATTACH, PM_LEVEL_D0 2778 * and DDI_RESUME. The DDI_ATTACH case is different from other two cases; the 2779 * memory allocation & device signature probing are attempted only during 2780 * DDI_ATTACH case. In the case of PM_LEVEL_D0 & DDI_RESUME, we are starting 2781 * from a previously initialized state; so there is no need to allocate memory 2782 * or to attempt probing the device signatures. 2783 */ 2784 static int 2785 si_initialize_controller(si_ctl_state_t *si_ctlp) 2786 { 2787 uint32_t port_status; 2788 uint32_t SStatus; 2789 uint32_t SControl; 2790 int port; 2791 int loop_count = 0; 2792 si_port_state_t *si_portp; 2793 2794 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 2795 "si3124: si_initialize_controller entered"); 2796 2797 mutex_enter(&si_ctlp->sictl_mutex); 2798 2799 /* Remove the Global Reset. */ 2800 ddi_put32(si_ctlp->sictl_global_acc_handle, 2801 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 2802 GLOBAL_CONTROL_REG_BITS_CLEAR); 2803 2804 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 2805 2806 if (si_ctlp->sictl_flags & SI_ATTACH) { 2807 /* 2808 * We allocate the port state only during attach 2809 * sequence. We don't want to do it during 2810 * suspend/resume sequence. 2811 */ 2812 if (si_alloc_port_state(si_ctlp, port)) { 2813 mutex_exit(&si_ctlp->sictl_mutex); 2814 return (SI_FAILURE); 2815 } 2816 } 2817 2818 si_portp = si_ctlp->sictl_ports[port]; 2819 mutex_enter(&si_portp->siport_mutex); 2820 2821 /* Clear Port Reset. */ 2822 ddi_put32(si_ctlp->sictl_port_acc_handle, 2823 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 2824 PORT_CONTROL_SET_BITS_PORT_RESET); 2825 ddi_put32(si_ctlp->sictl_port_acc_handle, 2826 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2827 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 2828 2829 /* 2830 * Arm the interrupts for: Cmd completion, Cmd error, 2831 * Port Ready, PM Change, PhyRdyChange, Commwake, 2832 * UnrecFIS, Devxchanged, SDBNotify. 2833 */ 2834 ddi_put32(si_ctlp->sictl_port_acc_handle, 2835 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 2836 (INTR_COMMAND_COMPLETE | 2837 INTR_COMMAND_ERROR | 2838 INTR_PORT_READY | 2839 INTR_POWER_CHANGE | 2840 INTR_PHYRDY_CHANGE | 2841 INTR_COMWAKE_RECEIVED | 2842 INTR_UNRECOG_FIS | 2843 INTR_DEV_XCHANGED | 2844 INTR_SETDEVBITS_NOTIFY)); 2845 2846 /* Now enable the interrupts. */ 2847 si_enable_port_interrupts(si_ctlp, port); 2848 2849 /* 2850 * The following PHY initialization is redundant in 2851 * in x86 since the BIOS anyway does this as part of 2852 * device enumeration during the power up. But this 2853 * is a required step in sparc since there is no BIOS. 2854 * 2855 * The way to initialize the PHY is to write a 1 and then 2856 * a 0 to DET field of SControl register. 2857 */ 2858 2859 /* 2860 * Fetch the current SControl before writing the 2861 * DET part with 1 2862 */ 2863 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2864 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2865 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 2866 ddi_put32(si_ctlp->sictl_port_acc_handle, 2867 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2868 SControl); 2869 #ifndef __lock_lint 2870 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 2871 #endif /* __lock_lint */ 2872 2873 /* 2874 * Now fetch the SControl again and rewrite the 2875 * DET part with 0 2876 */ 2877 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2878 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2879 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 2880 ddi_put32(si_ctlp->sictl_port_acc_handle, 2881 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2882 SControl); 2883 2884 /* 2885 * PHY may be initialized by now. Check the DET field of 2886 * SStatus to determine if there is a device present. 2887 * 2888 * The DET field is valid only if IPM field indicates that 2889 * the interface is in active state. 2890 */ 2891 2892 loop_count = 0; 2893 do { 2894 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 2895 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 2896 2897 if (SSTATUS_GET_IPM(SStatus) != 2898 SSTATUS_IPM_INTERFACE_ACTIVE) { 2899 /* 2900 * If the interface is not active, the DET field 2901 * is considered not accurate. So we want to 2902 * continue looping. 2903 */ 2904 SSTATUS_SET_DET(SStatus, 2905 SSTATUS_DET_NODEV_NOPHY); 2906 } 2907 2908 if (loop_count++ > SI_POLLRATE_SSTATUS) { 2909 /* 2910 * We are effectively timing out after 0.1 sec. 2911 */ 2912 break; 2913 } 2914 2915 /* Wait for 10 millisec */ 2916 #ifndef __lock_lint 2917 delay(SI_10MS_TICKS); 2918 #endif /* __lock_lint */ 2919 2920 } while (SSTATUS_GET_DET(SStatus) != 2921 SSTATUS_DET_DEVPRESENT_PHYONLINE); 2922 2923 SIDBG2(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2924 "si_initialize_controller: 1st loop count: %d, " 2925 "SStatus: 0x%x", 2926 loop_count, 2927 SStatus); 2928 2929 if ((SSTATUS_GET_IPM(SStatus) != 2930 SSTATUS_IPM_INTERFACE_ACTIVE) || 2931 (SSTATUS_GET_DET(SStatus) != 2932 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 2933 /* 2934 * Either the port is not active or there 2935 * is no device present. 2936 */ 2937 si_ctlp->sictl_ports[port]->siport_port_type = 2938 PORT_TYPE_NODEV; 2939 mutex_exit(&si_portp->siport_mutex); 2940 continue; 2941 } 2942 2943 /* Wait until Port Ready */ 2944 loop_count = 0; 2945 do { 2946 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2947 (uint32_t *)PORT_STATUS(si_ctlp, port)); 2948 2949 if (loop_count++ > SI_POLLRATE_PORTREADY) { 2950 /* 2951 * We are effectively timing out after 0.5 sec. 2952 */ 2953 break; 2954 } 2955 2956 /* Wait for 10 millisec */ 2957 #ifndef __lock_lint 2958 delay(SI_10MS_TICKS); 2959 #endif /* __lock_lint */ 2960 2961 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 2962 2963 SIDBG1(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2964 "si_initialize_controller: 2nd loop count: %d", 2965 loop_count); 2966 2967 if (si_ctlp->sictl_flags & SI_ATTACH) { 2968 /* 2969 * We want to probe for dev signature only during attach 2970 * case. Don't do it during suspend/resume sequence. 2971 */ 2972 if (port_status & PORT_STATUS_BITS_PORT_READY) { 2973 mutex_exit(&si_portp->siport_mutex); 2974 si_find_dev_signature(si_ctlp, si_portp, port, 2975 PORTMULT_CONTROL_PORT); 2976 mutex_enter(&si_portp->siport_mutex); 2977 } else { 2978 si_ctlp->sictl_ports[port]->siport_port_type = 2979 PORT_TYPE_NODEV; 2980 } 2981 } 2982 2983 mutex_exit(&si_portp->siport_mutex); 2984 } 2985 2986 mutex_exit(&si_ctlp->sictl_mutex); 2987 return (SI_SUCCESS); 2988 } 2989 2990 /* 2991 * Reverse of si_initialize_controller(). 2992 * 2993 * WARNING, WARNING: The caller is expected to obtain the sictl_mutex 2994 * before calling us. 2995 */ 2996 static void 2997 si_deinitialize_controller(si_ctl_state_t *si_ctlp) 2998 { 2999 int port; 3000 3001 _NOTE(ASSUMING_PROTECTED(si_ctlp)) 3002 3003 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 3004 "si3124: si_deinitialize_controller entered"); 3005 3006 /* disable all the interrupts. */ 3007 si_disable_all_interrupts(si_ctlp); 3008 3009 if (si_ctlp->sictl_flags & SI_DETACH) { 3010 /* 3011 * We want to dealloc all the memory in detach case. 3012 */ 3013 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 3014 si_dealloc_port_state(si_ctlp, port); 3015 } 3016 } 3017 3018 } 3019 3020 /* 3021 * Prepare the port ready for usage. 3022 * 3023 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3024 * before calling us. 3025 */ 3026 static void 3027 si_init_port(si_ctl_state_t *si_ctlp, int port) 3028 { 3029 3030 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 3031 "si_init_port entered: port: 0x%x", 3032 port); 3033 3034 /* Initialize the port. */ 3035 ddi_put32(si_ctlp->sictl_port_acc_handle, 3036 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3037 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 3038 3039 /* 3040 * Clear the InterruptNCOR (Interrupt No Clear on Read). 3041 * This step ensures that a mere reading of slot_status will clear 3042 * the interrupt; no explicit clearing of interrupt condition 3043 * will be needed for successful completion of commands. 3044 */ 3045 ddi_put32(si_ctlp->sictl_port_acc_handle, 3046 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3047 PORT_CONTROL_CLEAR_BITS_INTR_NCoR); 3048 3049 /* clear any pending interrupts at this point */ 3050 ddi_put32(si_ctlp->sictl_port_acc_handle, 3051 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3052 INTR_MASK); 3053 3054 } 3055 3056 3057 /* 3058 * Enumerate the devices connected to the port multiplier. 3059 * Once a device is detected, we call si_find_dev_signature() 3060 * to find the type of device connected. Even though we are 3061 * called from within si_find_dev_signature(), there is no 3062 * recursion possible. 3063 */ 3064 static int 3065 si_enumerate_port_multiplier( 3066 si_ctl_state_t *si_ctlp, 3067 si_port_state_t *si_portp, 3068 int port) 3069 { 3070 uint32_t num_dev_ports = 0; 3071 int pmport; 3072 uint32_t SControl = 0; 3073 uint32_t SStatus = 0; 3074 uint32_t SError = 0; 3075 int loop_count = 0; 3076 3077 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 3078 "si_enumerate_port_multiplier entered: port: %d", 3079 port); 3080 3081 mutex_enter(&si_portp->siport_mutex); 3082 3083 /* Enable Port Multiplier context switching. */ 3084 ddi_put32(si_ctlp->sictl_port_acc_handle, 3085 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3086 PORT_CONTROL_SET_BITS_PM_ENABLE); 3087 3088 /* 3089 * Read the num dev ports connected. 3090 * GSCR[2] contains the number of device ports. 3091 */ 3092 if (si_read_portmult_reg(si_ctlp, si_portp, port, PORTMULT_CONTROL_PORT, 3093 PSCR_REG2, &num_dev_ports)) { 3094 mutex_exit(&si_portp->siport_mutex); 3095 return (SI_FAILURE); 3096 } 3097 si_portp->siport_portmult_state.sipm_num_ports = num_dev_ports; 3098 3099 SIDBG1(SIDBG_INIT, si_ctlp, 3100 "si_enumerate_port_multiplier: ports found: %d", 3101 num_dev_ports); 3102 3103 for (pmport = 0; pmport < num_dev_ports-1; pmport++) { 3104 /* 3105 * Enable PHY by writing a 1, then a 0 to SControl 3106 * (i.e. PSCR[2]) DET field. 3107 */ 3108 if (si_read_portmult_reg(si_ctlp, si_portp, port, pmport, 3109 PSCR_REG2, &SControl)) { 3110 continue; 3111 } 3112 3113 /* First write a 1 to DET field of SControl. */ 3114 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 3115 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3116 PSCR_REG2, SControl)) { 3117 continue; 3118 } 3119 #ifndef __lock_lint 3120 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 3121 #endif /* __lock_lint */ 3122 3123 /* Then write a 0 to the DET field of SControl. */ 3124 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 3125 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3126 PSCR_REG2, SControl)) { 3127 continue; 3128 } 3129 3130 /* Wait for PHYRDY by polling SStatus (i.e. PSCR[0]). */ 3131 loop_count = 0; 3132 do { 3133 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3134 pmport, PSCR_REG0, &SStatus)) { 3135 break; 3136 } 3137 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3138 "looping for PHYRDY: SStatus: %x", 3139 SStatus); 3140 3141 if (SSTATUS_GET_IPM(SStatus) != 3142 SSTATUS_IPM_INTERFACE_ACTIVE) { 3143 /* 3144 * If the interface is not active, the DET field 3145 * is considered not accurate. So we want to 3146 * continue looping. 3147 */ 3148 SSTATUS_SET_DET(SStatus, 3149 SSTATUS_DET_NODEV_NOPHY); 3150 } 3151 3152 if (loop_count++ > SI_POLLRATE_SSTATUS) { 3153 /* 3154 * We are effectively timing out after 0.1 sec. 3155 */ 3156 break; 3157 } 3158 3159 /* Wait for 10 millisec */ 3160 #ifndef __lock_lint 3161 delay(SI_10MS_TICKS); 3162 #endif /* __lock_lint */ 3163 3164 } while (SSTATUS_GET_DET(SStatus) != 3165 SSTATUS_DET_DEVPRESENT_PHYONLINE); 3166 3167 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 3168 "si_enumerate_port_multiplier: " 3169 "loop count: %d, SStatus: 0x%x", 3170 loop_count, 3171 SStatus); 3172 3173 if ((SSTATUS_GET_IPM(SStatus) == 3174 SSTATUS_IPM_INTERFACE_ACTIVE) && 3175 (SSTATUS_GET_DET(SStatus) == 3176 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 3177 /* The interface is active and the device is present */ 3178 SIDBG1(SIDBG_INIT, si_ctlp, 3179 "Status: %x, device exists", 3180 SStatus); 3181 /* 3182 * Clear error bits in SError register (i.e. PSCR[1] 3183 * by writing back error bits. 3184 */ 3185 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3186 pmport, PSCR_REG1, &SError)) { 3187 continue; 3188 } 3189 SIDBG1(SIDBG_INIT, si_ctlp, 3190 "SError bits are: %x", SError); 3191 if (si_write_portmult_reg(si_ctlp, si_portp, port, 3192 pmport, PSCR_REG1, SError)) { 3193 continue; 3194 } 3195 3196 /* There exists a device. */ 3197 mutex_exit(&si_portp->siport_mutex); 3198 si_find_dev_signature(si_ctlp, si_portp, port, pmport); 3199 mutex_enter(&si_portp->siport_mutex); 3200 } 3201 } 3202 3203 mutex_exit(&si_portp->siport_mutex); 3204 3205 return (SI_SUCCESS); 3206 } 3207 3208 3209 /* 3210 * Read a port multiplier register. 3211 * 3212 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3213 * before calling us. 3214 */ 3215 static int 3216 si_read_portmult_reg( 3217 si_ctl_state_t *si_ctlp, 3218 si_port_state_t *si_portp, 3219 int port, 3220 int pmport, 3221 int regnum, 3222 uint32_t *regval) 3223 { 3224 int slot; 3225 si_prb_t *prb; 3226 uint32_t *prb_word_ptr; 3227 int i; 3228 uint32_t slot_status; 3229 int loop_count = 0; 3230 3231 _NOTE(ASSUMING_PROTECTED(si_portp)) 3232 3233 SIDBG3(SIDBG_ENTRY, si_ctlp, "si_read_portmult_reg: port: %x," 3234 "pmport: %x, regnum: %x", 3235 port, pmport, regnum); 3236 3237 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3238 if (slot == -1) { 3239 return (SI_FAILURE); 3240 } 3241 3242 prb = &(si_portp->siport_prbpool[slot]); 3243 bzero((void *)prb, sizeof (si_prb_t)); 3244 3245 /* Now fill the prb. */ 3246 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3247 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3248 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3249 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_PM_REG); 3250 3251 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3252 SET_FIS_FEATURES(prb->prb_fis, regnum); 3253 3254 /* no real data transfer is involved. */ 3255 SET_SGE_TRM(prb->prb_sge0); 3256 3257 #if SI_DEBUG 3258 if (si_debug_flags & SIDBG_DUMP_PRB) { 3259 int *ptr; 3260 int j; 3261 3262 ptr = (int *)(void *)prb; 3263 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3264 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3265 cmn_err(CE_WARN, "%x ", ptr[j]); 3266 } 3267 3268 } 3269 #endif /* SI_DEBUG */ 3270 3271 /* Deliver PRB */ 3272 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3273 3274 /* Loop till the command is finished. */ 3275 do { 3276 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3277 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3278 3279 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3280 "looping read_pm slot_status: 0x%x", 3281 slot_status); 3282 3283 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3284 /* We are effectively timing out after 0.5 sec. */ 3285 break; 3286 } 3287 3288 /* Wait for 10 millisec */ 3289 #ifndef __lock_lint 3290 delay(SI_10MS_TICKS); 3291 #endif /* __lock_lint */ 3292 3293 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3294 3295 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3296 "read_portmult_reg: loop count: %d", 3297 loop_count); 3298 3299 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3300 3301 /* Now inspect the port LRAM for the modified FIS. */ 3302 prb_word_ptr = (uint32_t *)(void *)prb; 3303 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3304 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3305 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3306 } 3307 3308 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3309 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3310 /* command failed. */ 3311 return (SI_FAILURE); 3312 } 3313 3314 /* command succeeded. */ 3315 *regval = (GET_FIS_SECTOR_COUNT(prb->prb_fis) & 0xff) | 3316 ((GET_FIS_SECTOR(prb->prb_fis) << 8) & 0xff00) | 3317 ((GET_FIS_CYL_LOW(prb->prb_fis) << 16) & 0xff0000) | 3318 ((GET_FIS_CYL_HI(prb->prb_fis) << 24) & 0xff000000); 3319 3320 return (SI_SUCCESS); 3321 } 3322 3323 /* 3324 * Write a port multiplier register. 3325 * 3326 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3327 * before calling us. 3328 */ 3329 static int 3330 si_write_portmult_reg( 3331 si_ctl_state_t *si_ctlp, 3332 si_port_state_t *si_portp, 3333 int port, 3334 int pmport, 3335 int regnum, 3336 uint32_t regval) 3337 { 3338 int slot; 3339 si_prb_t *prb; 3340 uint32_t *prb_word_ptr; 3341 uint32_t slot_status; 3342 int i; 3343 int loop_count = 0; 3344 3345 _NOTE(ASSUMING_PROTECTED(si_portp)) 3346 3347 SIDBG4(SIDBG_ENTRY, si_ctlp, 3348 "si_write_portmult_reg: port: %x, pmport: %x," 3349 "regnum: %x, regval: %x", 3350 port, pmport, regnum, regval); 3351 3352 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3353 if (slot == -1) { 3354 return (SI_FAILURE); 3355 } 3356 3357 prb = &(si_portp->siport_prbpool[slot]); 3358 bzero((void *)prb, sizeof (si_prb_t)); 3359 3360 /* Now fill the prb. */ 3361 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3362 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3363 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3364 3365 SET_FIS_COMMAND(prb->prb_fis, SATAC_WRITE_PM_REG); 3366 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3367 SET_FIS_FEATURES(prb->prb_fis, regnum); 3368 3369 SET_FIS_SECTOR_COUNT(prb->prb_fis, regval & 0xff); 3370 SET_FIS_SECTOR(prb->prb_fis, (regval >> 8) & 0xff); 3371 SET_FIS_CYL_LOW(prb->prb_fis, (regval >> 16) & 0xff); 3372 SET_FIS_CYL_HI(prb->prb_fis, (regval >> 24) & 0xff); 3373 3374 /* no real data transfer is involved. */ 3375 SET_SGE_TRM(prb->prb_sge0); 3376 3377 #if SI_DEBUG 3378 if (si_debug_flags & SIDBG_DUMP_PRB) { 3379 int *ptr; 3380 int j; 3381 3382 ptr = (int *)(void *)prb; 3383 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3384 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3385 cmn_err(CE_WARN, "%x ", ptr[j]); 3386 } 3387 3388 } 3389 #endif /* SI_DEBUG */ 3390 3391 /* Deliver PRB */ 3392 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3393 3394 /* Loop till the command is finished. */ 3395 do { 3396 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3397 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3398 3399 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3400 "looping write_pmp slot_status: 0x%x", 3401 slot_status); 3402 3403 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3404 /* We are effectively timing out after 0.5 sec. */ 3405 break; 3406 } 3407 3408 /* Wait for 10 millisec */ 3409 #ifndef __lock_lint 3410 delay(SI_10MS_TICKS); 3411 #endif /* __lock_lint */ 3412 3413 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3414 3415 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3416 "write_portmult_reg: loop count: %d", 3417 loop_count); 3418 3419 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3420 3421 /* Now inspect the port LRAM for the modified FIS. */ 3422 prb_word_ptr = (uint32_t *)(void *)prb; 3423 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3424 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3425 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3426 } 3427 3428 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3429 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3430 /* command failed */ 3431 return (SI_FAILURE); 3432 } 3433 3434 /* command succeeded */ 3435 return (SI_SUCCESS); 3436 } 3437 3438 3439 /* 3440 * Set the auto sense data for ATAPI devices. 3441 * 3442 * Note: Currently the sense data is simulated; this code will be enhanced 3443 * in second phase to fetch the real sense data from the atapi device. 3444 */ 3445 static void 3446 si_set_sense_data(sata_pkt_t *satapkt, int reason) 3447 { 3448 struct scsi_extended_sense *sense; 3449 3450 sense = (struct scsi_extended_sense *) 3451 satapkt->satapkt_cmd.satacmd_rqsense; 3452 bzero(sense, sizeof (struct scsi_extended_sense)); 3453 sense->es_valid = 1; /* Valid sense */ 3454 sense->es_class = 7; /* Response code 0x70 - current err */ 3455 sense->es_key = 0; 3456 sense->es_info_1 = 0; 3457 sense->es_info_2 = 0; 3458 sense->es_info_3 = 0; 3459 sense->es_info_4 = 0; 3460 sense->es_add_len = 6; /* Additional length */ 3461 sense->es_cmd_info[0] = 0; 3462 sense->es_cmd_info[1] = 0; 3463 sense->es_cmd_info[2] = 0; 3464 sense->es_cmd_info[3] = 0; 3465 sense->es_add_code = 0; 3466 sense->es_qual_code = 0; 3467 3468 if ((reason == SATA_PKT_DEV_ERROR) || (reason == SATA_PKT_TIMEOUT)) { 3469 sense->es_key = KEY_HARDWARE_ERROR; 3470 } 3471 } 3472 3473 3474 /* 3475 * Interrupt service handler. We loop through each of the ports to find 3476 * if the interrupt belongs to any of them. 3477 * 3478 * Bulk of the interrupt handling is actually done out of subroutines 3479 * like si_intr_command_complete() etc. 3480 */ 3481 /*ARGSUSED*/ 3482 static uint_t 3483 si_intr(caddr_t arg1, caddr_t arg2) 3484 { 3485 si_ctl_state_t *si_ctlp = (si_ctl_state_t *)(void *)arg1; 3486 si_port_state_t *si_portp; 3487 uint32_t global_intr_status; 3488 uint32_t mask, port_intr_status; 3489 int port; 3490 3491 global_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3492 (uint32_t *)GLOBAL_INTERRUPT_STATUS(si_ctlp)); 3493 3494 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3495 "si_intr: global_int_status: 0x%x", 3496 global_intr_status); 3497 3498 if (!(global_intr_status & SI31xx_INTR_PORT_MASK)) { 3499 /* Sorry, the interrupt is not ours. */ 3500 return (DDI_INTR_UNCLAIMED); 3501 } 3502 3503 /* Loop for all the ports. */ 3504 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 3505 3506 mask = 0x1 << port; 3507 if (!(global_intr_status & mask)) { 3508 continue; 3509 } 3510 3511 mutex_enter(&si_ctlp->sictl_mutex); 3512 si_portp = si_ctlp->sictl_ports[port]; 3513 mutex_exit(&si_ctlp->sictl_mutex); 3514 3515 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3516 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 3517 3518 SIDBG2(SIDBG_VERBOSE, si_ctlp, 3519 "s_intr: port_intr_status: 0x%x, port: %x", 3520 port_intr_status, 3521 port); 3522 3523 if (port_intr_status & INTR_COMMAND_COMPLETE) { 3524 (void) si_intr_command_complete(si_ctlp, si_portp, 3525 port); 3526 } else { 3527 /* Clear the interrupts */ 3528 ddi_put32(si_ctlp->sictl_port_acc_handle, 3529 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3530 port_intr_status & INTR_MASK); 3531 } 3532 3533 /* 3534 * Note that we did not clear the interrupt for command 3535 * completion interrupt. Reading of slot_status takes care 3536 * of clearing the interrupt for command completion case. 3537 */ 3538 3539 if (port_intr_status & INTR_COMMAND_ERROR) { 3540 (void) si_intr_command_error(si_ctlp, si_portp, port); 3541 } 3542 3543 if (port_intr_status & INTR_PORT_READY) { 3544 (void) si_intr_port_ready(si_ctlp, si_portp, port); 3545 } 3546 3547 if (port_intr_status & INTR_POWER_CHANGE) { 3548 (void) si_intr_pwr_change(si_ctlp, si_portp, port); 3549 } 3550 3551 if (port_intr_status & INTR_PHYRDY_CHANGE) { 3552 (void) si_intr_phy_ready_change(si_ctlp, si_portp, 3553 port); 3554 } 3555 3556 if (port_intr_status & INTR_COMWAKE_RECEIVED) { 3557 (void) si_intr_comwake_rcvd(si_ctlp, si_portp, 3558 port); 3559 } 3560 3561 if (port_intr_status & INTR_UNRECOG_FIS) { 3562 (void) si_intr_unrecognised_fis(si_ctlp, si_portp, 3563 port); 3564 } 3565 3566 if (port_intr_status & INTR_DEV_XCHANGED) { 3567 (void) si_intr_dev_xchanged(si_ctlp, si_portp, port); 3568 } 3569 3570 if (port_intr_status & INTR_8B10B_DECODE_ERROR) { 3571 (void) si_intr_decode_err_threshold(si_ctlp, si_portp, 3572 port); 3573 } 3574 3575 if (port_intr_status & INTR_CRC_ERROR) { 3576 (void) si_intr_crc_err_threshold(si_ctlp, si_portp, 3577 port); 3578 } 3579 3580 if (port_intr_status & INTR_HANDSHAKE_ERROR) { 3581 (void) si_intr_handshake_err_threshold(si_ctlp, 3582 si_portp, port); 3583 } 3584 3585 if (port_intr_status & INTR_SETDEVBITS_NOTIFY) { 3586 (void) si_intr_set_devbits_notify(si_ctlp, si_portp, 3587 port); 3588 } 3589 } 3590 3591 return (DDI_INTR_CLAIMED); 3592 } 3593 3594 /* 3595 * Interrupt which indicates that one or more commands have successfully 3596 * completed. 3597 * 3598 * Since we disabled W1C (write-one-to-clear) previously, mere reading 3599 * of slot_status register clears the interrupt. There is no need to 3600 * explicitly clear the interrupt. 3601 */ 3602 static int 3603 si_intr_command_complete( 3604 si_ctl_state_t *si_ctlp, 3605 si_port_state_t *si_portp, 3606 int port) 3607 { 3608 3609 uint32_t slot_status; 3610 uint32_t finished_tags; 3611 int finished_slot; 3612 sata_pkt_t *satapkt; 3613 3614 SIDBG0(SIDBG_ENTRY|SIDBG_INTR, si_ctlp, 3615 "si_intr_command_complete enter"); 3616 3617 mutex_enter(&si_portp->siport_mutex); 3618 3619 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3620 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3621 3622 if (!si_portp->siport_pending_tags) { 3623 /* 3624 * Spurious interrupt. Nothing to be done. 3625 * The interrupt was cleared when slot_status was read. 3626 */ 3627 mutex_exit(&si_portp->siport_mutex); 3628 return (SI_SUCCESS); 3629 } 3630 3631 SIDBG2(SIDBG_VERBOSE, si_ctlp, "si3124: si_intr_command_complete: " 3632 "pending_tags: %x, slot_status: %x", 3633 si_portp->siport_pending_tags, 3634 slot_status); 3635 3636 finished_tags = si_portp->siport_pending_tags & 3637 ~slot_status & SI_SLOT_MASK; 3638 while (finished_tags) { 3639 3640 finished_slot = ddi_ffs(finished_tags) - 1; 3641 if (finished_slot == -1) { 3642 break; 3643 } 3644 3645 satapkt = si_portp->siport_slot_pkts[finished_slot]; 3646 3647 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 3648 si_copy_out_regs(&satapkt->satapkt_cmd, si_ctlp, port, 3649 finished_slot); 3650 } 3651 3652 CLEAR_BIT(si_portp->siport_pending_tags, finished_slot); 3653 CLEAR_BIT(finished_tags, finished_slot); 3654 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 3655 } 3656 3657 SIDBG2(SIDBG_PKTCOMP, si_ctlp, 3658 "command_complete done: pend_tags: 0x%x, slot_status: 0x%x", 3659 si_portp->siport_pending_tags, 3660 slot_status); 3661 3662 /* 3663 * tidbit: no need to clear the interrupt since reading of 3664 * slot_status automatically clears the interrupt in the case 3665 * of a successful command completion. 3666 */ 3667 3668 mutex_exit(&si_portp->siport_mutex); 3669 3670 return (SI_SUCCESS); 3671 } 3672 3673 /* 3674 * Interrupt which indicates that a command did not complete successfully. 3675 * 3676 * The port halts whenever a command error interrupt is received. 3677 * The only way to restart it is to reset or reinitialize the port 3678 * but such an operation throws away all the pending commands on 3679 * the port. 3680 * 3681 * We reset the device and mop the commands on the port. 3682 */ 3683 static int 3684 si_intr_command_error( 3685 si_ctl_state_t *si_ctlp, 3686 si_port_state_t *si_portp, 3687 int port) 3688 { 3689 uint32_t command_error, slot_status; 3690 uint32_t failed_tags; 3691 3692 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3693 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3694 3695 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3696 "si_intr_command_error: command_error: 0x%x", 3697 command_error); 3698 3699 mutex_enter(&si_portp->siport_mutex); 3700 3701 /* 3702 * Remember the slot_status since any of the recovery handler 3703 * can blow it away with reset operation. 3704 */ 3705 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3706 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3707 3708 si_log_error_message(si_ctlp, port, command_error); 3709 3710 switch (command_error) { 3711 3712 case CMD_ERR_DEVICEERRROR: 3713 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3714 break; 3715 3716 case CMD_ERR_SDBERROR: 3717 si_error_recovery_SDBERROR(si_ctlp, si_portp, port); 3718 break; 3719 3720 case CMD_ERR_DATAFISERROR: 3721 si_error_recovery_DATAFISERROR(si_ctlp, si_portp, port); 3722 break; 3723 3724 case CMD_ERR_SENDFISERROR: 3725 si_error_recovery_SENDFISERROR(si_ctlp, si_portp, port); 3726 break; 3727 3728 default: 3729 si_error_recovery_default(si_ctlp, si_portp, port); 3730 break; 3731 3732 } 3733 3734 /* 3735 * Compute the failed_tags by adding up the error tags. 3736 * 3737 * The siport_err_tags_SDBERROR and siport_err_tags_nonSDBERROR 3738 * were filled in by the si_error_recovery_* routines. 3739 */ 3740 failed_tags = si_portp->siport_pending_tags & 3741 (si_portp->siport_err_tags_SDBERROR | 3742 si_portp->siport_err_tags_nonSDBERROR); 3743 3744 SIDBG3(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si_intr_command_error: " 3745 "err_tags_SDBERROR: 0x%x, " 3746 "err_tags_nonSDBERRROR: 0x%x, " 3747 "failed_tags: 0x%x", 3748 si_portp->siport_err_tags_SDBERROR, 3749 si_portp->siport_err_tags_nonSDBERROR, 3750 failed_tags); 3751 3752 SIDBG2(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si3124: si_intr_command_error: " 3753 "slot_status:0x%x, pending_tags: 0x%x", 3754 slot_status, 3755 si_portp->siport_pending_tags); 3756 3757 si_portp->mopping_in_progress++; 3758 3759 si_mop_commands(si_ctlp, 3760 si_portp, 3761 port, 3762 slot_status, 3763 failed_tags, 3764 0, /* timedout_tags */ 3765 0, /* aborting_tags */ 3766 0); /* reset_tags */ 3767 3768 ASSERT(si_portp->siport_pending_tags == 0); 3769 3770 si_portp->siport_err_tags_SDBERROR = 0; 3771 si_portp->siport_err_tags_nonSDBERROR = 0; 3772 3773 mutex_exit(&si_portp->siport_mutex); 3774 3775 return (SI_SUCCESS); 3776 } 3777 3778 /* 3779 * There is a subtle difference between errors on a normal port and 3780 * a port-mult port. When an error happens on a normal port, the port 3781 * is halted effectively until the port is reset or initialized. 3782 * However, in port-mult port errors, port does not get halted since 3783 * other non-error devices behind the port multiplier can still 3784 * continue to operate. So we wait till all the commands are drained 3785 * instead of resetting it right away. 3786 * 3787 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3788 * before calling us. 3789 */ 3790 static void 3791 si_recover_portmult_errors( 3792 si_ctl_state_t *si_ctlp, 3793 si_port_state_t *si_portp, 3794 int port) 3795 { 3796 uint32_t command_error, slot_status, port_status; 3797 int failed_slot; 3798 int loop_count = 0; 3799 3800 _NOTE(ASSUMING_PROTECTED(si_portp)) 3801 3802 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3803 "si_recover_portmult_errors: port: 0x%x", 3804 port); 3805 3806 /* Resume the port */ 3807 ddi_put32(si_ctlp->sictl_port_acc_handle, 3808 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3809 PORT_CONTROL_SET_BITS_RESUME); 3810 3811 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3812 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3813 3814 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3815 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3816 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3817 3818 if (command_error == CMD_ERR_SDBERROR) { 3819 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3820 } else { 3821 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3822 } 3823 3824 /* Now we drain the pending commands. */ 3825 do { 3826 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3827 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3828 3829 /* 3830 * Since we have not yet returned DDI_INTR_CLAIMED, 3831 * our interrupt handler is guaranteed not to be called again. 3832 * So we need to check IS_ATTENTION_RAISED() for further 3833 * decisions. 3834 * 3835 * This is a too big a delay for an interrupt context. 3836 * But this is supposed to be a rare condition. 3837 */ 3838 3839 if (IS_ATTENTION_RAISED(slot_status)) { 3840 /* Resume again */ 3841 ddi_put32(si_ctlp->sictl_port_acc_handle, 3842 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3843 PORT_CONTROL_SET_BITS_RESUME); 3844 3845 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3846 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3847 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3848 command_error = ddi_get32( 3849 si_ctlp->sictl_port_acc_handle, 3850 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, 3851 port))); 3852 if (command_error == CMD_ERR_SDBERROR) { 3853 si_portp->siport_err_tags_SDBERROR |= 3854 (0x1 << failed_slot); 3855 } else { 3856 si_portp->siport_err_tags_nonSDBERROR |= 3857 (0x1 << failed_slot); 3858 } 3859 } 3860 3861 if (loop_count++ > SI_POLLRATE_RECOVERPORTMULT) { 3862 /* We are effectively timing out after 10 sec. */ 3863 break; 3864 } 3865 3866 /* Wait for 10 millisec */ 3867 #ifndef __lock_lint 3868 delay(SI_10MS_TICKS); 3869 #endif /* __lock_lint */ 3870 3871 } while (slot_status & SI_SLOT_MASK); 3872 3873 /* 3874 * The above loop can be improved for 3132 since we could obtain the 3875 * Port Multiplier Context of the device in error. Then we could 3876 * do a better job in filtering out commands for the device in error. 3877 * The loop could finish much earlier with such a logic. 3878 */ 3879 3880 /* Clear the RESUME bit. */ 3881 ddi_put32(si_ctlp->sictl_port_acc_handle, 3882 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3883 PORT_CONTROL_CLEAR_BITS_RESUME); 3884 3885 } 3886 3887 /* 3888 * If we are connected to port multiplier, drain the non-failed devices. 3889 * Otherwise, we initialize the port (which effectively fails all the 3890 * pending commands in the hope that sd would retry them later). 3891 * 3892 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3893 * before calling us. 3894 */ 3895 static void 3896 si_error_recovery_DEVICEERROR( 3897 si_ctl_state_t *si_ctlp, 3898 si_port_state_t *si_portp, 3899 int port) 3900 { 3901 uint32_t port_status; 3902 int failed_slot; 3903 3904 _NOTE(ASSUMING_PROTECTED(si_portp)) 3905 3906 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3907 "si_error_recovery_DEVICEERROR: port: 0x%x", 3908 port); 3909 3910 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3911 si_recover_portmult_errors(si_ctlp, si_portp, port); 3912 } else { 3913 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3914 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3915 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3916 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3917 } 3918 3919 /* In either case (port-mult or not), we reinitialize the port. */ 3920 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3921 } 3922 3923 /* 3924 * Handle exactly like DEVICEERROR. Remember the tags with SDBERROR 3925 * to perform read_log_ext on them later. SDBERROR means that the 3926 * error was for an NCQ command. 3927 * 3928 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3929 * before calling us. 3930 */ 3931 static void 3932 si_error_recovery_SDBERROR( 3933 si_ctl_state_t *si_ctlp, 3934 si_port_state_t *si_portp, 3935 int port) 3936 { 3937 uint32_t port_status; 3938 int failed_slot; 3939 3940 _NOTE(ASSUMING_PROTECTED(si_portp)) 3941 3942 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3943 "si3124: si_error_recovery_SDBERROR: port: 0x%x", 3944 port); 3945 3946 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3947 si_recover_portmult_errors(si_ctlp, si_portp, port); 3948 } else { 3949 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3950 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3951 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3952 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3953 } 3954 3955 /* In either case (port-mult or not), we reinitialize the port. */ 3956 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3957 } 3958 3959 /* 3960 * Handle exactly like DEVICEERROR except resetting the port if there was 3961 * an NCQ command on the port. 3962 * 3963 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3964 * before calling us. 3965 */ 3966 static void 3967 si_error_recovery_DATAFISERROR( 3968 si_ctl_state_t *si_ctlp, 3969 si_port_state_t *si_portp, 3970 int port) 3971 { 3972 uint32_t port_status; 3973 int failed_slot; 3974 3975 _NOTE(ASSUMING_PROTECTED(si_portp)) 3976 3977 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3978 "si3124: si_error_recovery_DATAFISERROR: port: 0x%x", 3979 port); 3980 3981 /* reset device if we were waiting for any ncq commands. */ 3982 if (si_portp->siport_pending_ncq_count) { 3983 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3984 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3985 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3986 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3987 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 3988 SI_DEVICE_RESET); 3989 return; 3990 } 3991 3992 /* 3993 * If we don't have any ncq commands pending, the rest of 3994 * the process is similar to the one for DEVICEERROR. 3995 */ 3996 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3997 } 3998 3999 /* 4000 * We handle just like DEVICERROR except that we reset the device instead 4001 * of initializing the port. 4002 * 4003 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4004 * before calling us. 4005 */ 4006 static void 4007 si_error_recovery_SENDFISERROR( 4008 si_ctl_state_t *si_ctlp, 4009 si_port_state_t *si_portp, 4010 int port) 4011 { 4012 uint32_t port_status; 4013 int failed_slot; 4014 4015 _NOTE(ASSUMING_PROTECTED(si_portp)) 4016 4017 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 4018 "si3124: si_error_recovery_SENDFISERROR: port: 0x%x", 4019 port); 4020 4021 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 4022 si_recover_portmult_errors(si_ctlp, si_portp, port); 4023 } else { 4024 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4025 (uint32_t *)PORT_STATUS(si_ctlp, port)); 4026 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 4027 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 4028 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 4029 SI_DEVICE_RESET); 4030 } 4031 } 4032 4033 /* 4034 * The default behavior for all other errors is to reset the device. 4035 * 4036 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4037 * before calling us. 4038 */ 4039 static void 4040 si_error_recovery_default( 4041 si_ctl_state_t *si_ctlp, 4042 si_port_state_t *si_portp, 4043 int port) 4044 { 4045 uint32_t port_status; 4046 int failed_slot; 4047 4048 _NOTE(ASSUMING_PROTECTED(si_portp)) 4049 4050 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 4051 "si3124: si_error_recovery_default: port: 0x%x", 4052 port); 4053 4054 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4055 (uint32_t *)PORT_STATUS(si_ctlp, port)); 4056 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 4057 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 4058 4059 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 4060 SI_DEVICE_RESET); 4061 } 4062 4063 /* 4064 * Read Log Ext with PAGE 10 to retrieve the error for an NCQ command. 4065 * 4066 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4067 * before calling us. 4068 */ 4069 static uint8_t 4070 si_read_log_ext(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 4071 { 4072 int slot; 4073 si_prb_t *prb; 4074 int i; 4075 uint32_t slot_status; 4076 int loop_count = 0; 4077 uint32_t *prb_word_ptr; 4078 uint8_t error; 4079 4080 _NOTE(ASSUMING_PROTECTED(si_portp)) 4081 4082 SIDBG1(SIDBG_ENTRY|SIDBG_ERRS, si_ctlp, 4083 "si_read_log_ext: port: %x", port); 4084 4085 slot = si_claim_free_slot(si_ctlp, si_portp, port); 4086 if (slot == -1) { 4087 return (0); 4088 } 4089 4090 prb = &(si_portp->siport_prbpool[slot]); 4091 bzero((void *)prb, sizeof (si_prb_t)); 4092 4093 /* Now fill the prb */ 4094 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 4095 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 4096 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 4097 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_LOG_EXT); 4098 SET_FIS_SECTOR(prb->prb_fis, SATA_LOG_PAGE_10); 4099 4100 /* no real data transfer is involved */ 4101 SET_SGE_TRM(prb->prb_sge0); 4102 4103 #if SI_DEBUG 4104 if (si_debug_flags & SIDBG_DUMP_PRB) { 4105 int *ptr; 4106 int j; 4107 4108 ptr = (int *)(void *)prb; 4109 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 4110 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 4111 cmn_err(CE_WARN, "%x ", ptr[j]); 4112 } 4113 4114 } 4115 #endif /* SI_DEBUG */ 4116 4117 /* Deliver PRB */ 4118 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 4119 4120 /* Loop till the command is finished. */ 4121 do { 4122 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4123 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 4124 4125 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4126 "looping read_log_ext slot_status: 0x%x", 4127 slot_status); 4128 4129 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 4130 /* We are effectively timing out after 0.5 sec. */ 4131 break; 4132 } 4133 4134 /* Wait for 10 millisec */ 4135 #ifndef __lock_lint 4136 delay(SI_10MS_TICKS); 4137 #endif /* __lock_lint */ 4138 4139 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 4140 4141 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 4142 /* 4143 * If we fail with the READ LOG EXT command, we need to 4144 * initialize the port to clear the slot_status register. 4145 * We don't need to worry about any other valid commands 4146 * being thrown away because we are already in recovery 4147 * mode and READ LOG EXT is the only pending command. 4148 */ 4149 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 4150 } 4151 4152 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4153 "read_portmult_reg: loop count: %d", 4154 loop_count); 4155 4156 /* 4157 * The LRAM contains the the modified FIS. 4158 * Read the modified FIS to obtain the Error. 4159 */ 4160 prb_word_ptr = (uint32_t *)(void *)prb; 4161 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 4162 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 4163 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 4164 } 4165 error = GET_FIS_FEATURES(prb->prb_fis); 4166 4167 CLEAR_BIT(si_portp->siport_pending_tags, slot); 4168 4169 return (error); 4170 4171 } 4172 4173 /* 4174 * Dump the error message to the log. 4175 */ 4176 static void 4177 si_log_error_message(si_ctl_state_t *si_ctlp, int port, uint32_t command_error) 4178 { 4179 #if SI_DEBUG 4180 #ifndef __lock_lint 4181 _NOTE(ARGUNUSED(si_ctlp)) 4182 _NOTE(ARGUNUSED(port)) 4183 #endif /* __lock_lint */ 4184 4185 char *errstr; 4186 4187 switch (command_error) { 4188 4189 case CMD_ERR_DEVICEERRROR: 4190 errstr = "Standard Error: Error bit set in register - device" 4191 " to host FIS"; 4192 break; 4193 4194 case CMD_ERR_SDBERROR: 4195 errstr = "NCQ Error: Error bit set in register - device" 4196 " to host FIS"; 4197 break; 4198 4199 case CMD_ERR_DATAFISERROR: 4200 errstr = "Error in data FIS not detected by device"; 4201 break; 4202 4203 case CMD_ERR_SENDFISERROR: 4204 errstr = "Initial command FIS transmission failed"; 4205 break; 4206 4207 case CMD_ERR_INCONSISTENTSTATE: 4208 errstr = "Inconsistency in protocol"; 4209 break; 4210 4211 case CMD_ERR_DIRECTIONERROR: 4212 errstr = "DMA direction flag does not match the command"; 4213 break; 4214 4215 case CMD_ERR_UNDERRUNERROR: 4216 errstr = "Run out of scatter gather entries while writing data"; 4217 break; 4218 4219 case CMD_ERR_OVERRUNERROR: 4220 errstr = "Run out of scatter gather entries while reading data"; 4221 break; 4222 4223 case CMD_ERR_PACKETPROTOCOLERROR: 4224 errstr = "Packet protocol error"; 4225 break; 4226 4227 case CMD_ERR_PLDSGTERRORBOUNDARY: 4228 errstr = "Scatter/gather table not on quadword boundary"; 4229 break; 4230 4231 case CMD_ERR_PLDSGTERRORTARETABORT: 4232 errstr = "PCI(X) Target abort while fetching scatter/gather" 4233 " table"; 4234 break; 4235 4236 case CMD_ERR_PLDSGTERRORMASTERABORT: 4237 errstr = "PCI(X) Master abort while fetching scatter/gather" 4238 " table"; 4239 break; 4240 4241 case CMD_ERR_PLDSGTERRORPCIERR: 4242 errstr = "PCI(X) parity error while fetching scatter/gather" 4243 " table"; 4244 break; 4245 4246 case CMD_ERR_PLDCMDERRORBOUNDARY: 4247 errstr = "PRB not on quadword boundary"; 4248 break; 4249 4250 case CMD_ERR_PLDCMDERRORTARGETABORT: 4251 errstr = "PCI(X) Target abort while fetching PRB"; 4252 break; 4253 4254 case CMD_ERR_PLDCMDERRORMASTERABORT: 4255 errstr = "PCI(X) Master abort while fetching PRB"; 4256 break; 4257 4258 case CMD_ERR_PLDCMDERORPCIERR: 4259 errstr = "PCI(X) parity error while fetching PRB"; 4260 break; 4261 4262 case CMD_ERR_PSDERRORTARGETABORT: 4263 errstr = "PCI(X) Target abort during data transfer"; 4264 break; 4265 4266 case CMD_ERR_PSDERRORMASTERABORT: 4267 errstr = "PCI(X) Master abort during data transfer"; 4268 break; 4269 4270 case CMD_ERR_PSDERRORPCIERR: 4271 errstr = "PCI(X) parity error during data transfer"; 4272 break; 4273 4274 case CMD_ERR_SENDSERVICEERROR: 4275 errstr = "FIS received while sending service FIS in" 4276 " legacy queuing operation"; 4277 break; 4278 4279 default: 4280 errstr = "Unknown Error"; 4281 break; 4282 4283 } 4284 4285 SIDBG2(SIDBG_ERRS, si_ctlp, 4286 "command error: port: 0x%x, error: %s", 4287 port, 4288 errstr); 4289 #else 4290 #ifndef __lock_lint 4291 _NOTE(ARGUNUSED(si_ctlp)) 4292 _NOTE(ARGUNUSED(port)) 4293 _NOTE(ARGUNUSED(command_error)) 4294 #endif /* __lock_lint */ 4295 4296 #endif /* SI_DEBUG */ 4297 } 4298 4299 4300 /* 4301 * Interrupt which indicates that the Port Ready state has changed 4302 * from zero to one. 4303 * 4304 * We are not interested in this interrupt; we just log a debug message. 4305 */ 4306 /*ARGSUSED*/ 4307 static int 4308 si_intr_port_ready( 4309 si_ctl_state_t *si_ctlp, 4310 si_port_state_t *si_portp, 4311 int port) 4312 { 4313 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_ready"); 4314 return (SI_SUCCESS); 4315 } 4316 4317 /* 4318 * Interrupt which indicates that the port power management state 4319 * has been modified. 4320 * 4321 * We are not interested in this interrupt; we just log a debug message. 4322 */ 4323 /*ARGSUSED*/ 4324 static int 4325 si_intr_pwr_change( 4326 si_ctl_state_t *si_ctlp, 4327 si_port_state_t *si_portp, 4328 int port) 4329 { 4330 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_pwr_change"); 4331 return (SI_SUCCESS); 4332 } 4333 4334 /* 4335 * Interrupt which indicates that the PHY sate has changed either from 4336 * Not-Ready to Ready or from Ready to Not-Ready. 4337 */ 4338 static int 4339 si_intr_phy_ready_change( 4340 si_ctl_state_t *si_ctlp, 4341 si_port_state_t *si_portp, 4342 int port) 4343 { 4344 sata_device_t sdevice; 4345 uint32_t SStatus = 0; /* No dev present & PHY not established. */ 4346 int dev_exists_now = 0; 4347 int dev_existed_previously = 0; 4348 4349 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_phy_rdy_change"); 4350 4351 mutex_enter(&si_ctlp->sictl_mutex); 4352 if ((si_ctlp->sictl_sata_hba_tran == NULL) || (si_portp == NULL)) { 4353 /* the whole controller setup is not yet done. */ 4354 mutex_exit(&si_ctlp->sictl_mutex); 4355 return (SI_SUCCESS); 4356 } 4357 4358 mutex_exit(&si_ctlp->sictl_mutex); 4359 4360 mutex_enter(&si_portp->siport_mutex); 4361 4362 /* SStatus tells the presence of device. */ 4363 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4364 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 4365 dev_exists_now = 4366 (SSTATUS_GET_DET(SStatus) == SSTATUS_DET_DEVPRESENT_PHYONLINE); 4367 4368 if (si_portp->siport_port_type != PORT_TYPE_NODEV) { 4369 dev_existed_previously = 1; 4370 } 4371 4372 bzero((void *)&sdevice, sizeof (sata_device_t)); 4373 4374 sdevice.satadev_addr.cport = (uint8_t)port; 4375 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 4376 4377 /* we don't have a way of determining the exact port-mult port. */ 4378 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 4379 sdevice.satadev_addr.qual = SATA_ADDR_PMPORT; 4380 } else { 4381 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4382 } 4383 4384 sdevice.satadev_state = SATA_STATE_READY; /* port state */ 4385 4386 if (dev_exists_now) { 4387 if (dev_existed_previously) { 4388 4389 /* Things are fine now. The loss was temporary. */ 4390 SIDBG0(SIDBG_INTR, NULL, 4391 "phyrdy: doing BOTH EVENTS TOGETHER"); 4392 if (si_portp->siport_active) { 4393 SIDBG0(SIDBG_EVENT, si_ctlp, 4394 "sending event: LINK_LOST & " 4395 "LINK_ESTABLISHED"); 4396 4397 sata_hba_event_notify( 4398 si_ctlp->sictl_sata_hba_tran->\ 4399 sata_tran_hba_dip, 4400 &sdevice, 4401 SATA_EVNT_LINK_LOST| 4402 SATA_EVNT_LINK_ESTABLISHED); 4403 } 4404 4405 } else { 4406 4407 /* A new device has been detected. */ 4408 mutex_exit(&si_portp->siport_mutex); 4409 si_find_dev_signature(si_ctlp, si_portp, port, 4410 PORTMULT_CONTROL_PORT); 4411 mutex_enter(&si_portp->siport_mutex); 4412 SIDBG0(SIDBG_INTR, NULL, "phyrdy: doing ATTACH event"); 4413 if (si_portp->siport_active) { 4414 SIDBG0(SIDBG_EVENT, si_ctlp, 4415 "sending event up: LINK_ESTABLISHED"); 4416 4417 sata_hba_event_notify( 4418 si_ctlp->sictl_sata_hba_tran->\ 4419 sata_tran_hba_dip, 4420 &sdevice, 4421 SATA_EVNT_LINK_ESTABLISHED); 4422 } 4423 4424 } 4425 } else { /* No device exists now */ 4426 4427 if (dev_existed_previously) { 4428 4429 /* An existing device is lost. */ 4430 if (si_portp->siport_active) { 4431 SIDBG0(SIDBG_EVENT, si_ctlp, 4432 "sending event up: LINK_LOST"); 4433 4434 sata_hba_event_notify( 4435 si_ctlp->sictl_sata_hba_tran-> 4436 sata_tran_hba_dip, 4437 &sdevice, 4438 SATA_EVNT_LINK_LOST); 4439 } 4440 si_portp->siport_port_type = PORT_TYPE_NODEV; 4441 4442 } 4443 #if SI_DEBUG 4444 else { 4445 4446 /* spurious interrupt */ 4447 SIDBG0(SIDBG_INTR, NULL, 4448 "spurious phy ready interrupt"); 4449 } 4450 #endif /* SI_DEBUG */ 4451 } 4452 4453 mutex_exit(&si_portp->siport_mutex); 4454 return (SI_SUCCESS); 4455 } 4456 4457 4458 /* 4459 * Interrupt which indicates that a COMWAKE OOB signal has been decoded 4460 * on the receiver. 4461 * 4462 * We are not interested in this interrupt; we just log a debug message. 4463 */ 4464 /*ARGSUSED*/ 4465 static int 4466 si_intr_comwake_rcvd( 4467 si_ctl_state_t *si_ctlp, 4468 si_port_state_t *si_portp, 4469 int port) 4470 { 4471 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_commwake_rcvd"); 4472 return (SI_SUCCESS); 4473 } 4474 4475 /* 4476 * Interrupt which indicates that the F-bit has been set in SError 4477 * Diag field. 4478 * 4479 * We are not interested in this interrupt; we just log a debug message. 4480 */ 4481 /*ARGSUSED*/ 4482 static int 4483 si_intr_unrecognised_fis( 4484 si_ctl_state_t *si_ctlp, 4485 si_port_state_t *si_portp, 4486 int port) 4487 { 4488 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_unrecognised_fis"); 4489 return (SI_SUCCESS); 4490 } 4491 4492 /* 4493 * Interrupt which indicates that the X-bit has been set in SError 4494 * Diag field. 4495 * 4496 * We are not interested in this interrupt; we just log a debug message. 4497 */ 4498 /*ARGSUSED*/ 4499 static int 4500 si_intr_dev_xchanged( 4501 si_ctl_state_t *si_ctlp, 4502 si_port_state_t *si_portp, 4503 int port) 4504 { 4505 4506 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_dev_xchanged"); 4507 return (SI_SUCCESS); 4508 } 4509 4510 /* 4511 * Interrupt which indicates that the 8b/10 Decode Error counter has 4512 * exceeded the programmed non-zero threshold value. 4513 * 4514 * We are not interested in this interrupt; we just log a debug message. 4515 */ 4516 /*ARGSUSED*/ 4517 static int 4518 si_intr_decode_err_threshold( 4519 si_ctl_state_t *si_ctlp, 4520 si_port_state_t *si_portp, 4521 int port) 4522 { 4523 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_err_threshold"); 4524 return (SI_SUCCESS); 4525 } 4526 4527 /* 4528 * Interrupt which indicates that the CRC Error counter has exceeded the 4529 * programmed non-zero threshold value. 4530 * 4531 * We are not interested in this interrupt; we just log a debug message. 4532 */ 4533 /*ARGSUSED*/ 4534 static int 4535 si_intr_crc_err_threshold( 4536 si_ctl_state_t *si_ctlp, 4537 si_port_state_t *si_portp, 4538 int port) 4539 { 4540 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_crc_threshold"); 4541 return (SI_SUCCESS); 4542 } 4543 4544 /* 4545 * Interrupt which indicates that the Handshake Error counter has 4546 * exceeded the programmed non-zero threshold value. 4547 * 4548 * We are not interested in this interrupt; we just log a debug message. 4549 */ 4550 /*ARGSUSED*/ 4551 static int 4552 si_intr_handshake_err_threshold( 4553 si_ctl_state_t *si_ctlp, 4554 si_port_state_t *si_portp, 4555 int port) 4556 { 4557 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 4558 "si_intr_handshake_err_threshold"); 4559 return (SI_SUCCESS); 4560 } 4561 4562 /* 4563 * Interrupt which indicates that a "Set Device Bits" FIS has been 4564 * received with N-bit set in the control field. 4565 * 4566 * We are not interested in this interrupt; we just log a debug message. 4567 */ 4568 /*ARGSUSED*/ 4569 static int 4570 si_intr_set_devbits_notify( 4571 si_ctl_state_t *si_ctlp, 4572 si_port_state_t *si_portp, 4573 int port) 4574 { 4575 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_set_devbits_notify"); 4576 return (SI_SUCCESS); 4577 } 4578 4579 4580 /* 4581 * Enable the interrupts for a particular port. 4582 * 4583 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4584 * before calling us. 4585 */ 4586 static void 4587 si_enable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4588 { 4589 uint32_t mask; 4590 4591 /* get the current settings first. */ 4592 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4593 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4594 4595 SIDBG1(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 4596 "si_enable_port_interrupts: current mask: 0x%x", 4597 mask); 4598 4599 /* enable the bit for current port. */ 4600 SET_BIT(mask, port); 4601 4602 /* now use this mask to enable the interrupt. */ 4603 ddi_put32(si_ctlp->sictl_global_acc_handle, 4604 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4605 mask); 4606 } 4607 4608 /* 4609 * Enable interrupts for all the ports. 4610 */ 4611 static void 4612 si_enable_all_interrupts(si_ctl_state_t *si_ctlp) 4613 { 4614 int port; 4615 4616 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4617 si_enable_port_interrupts(si_ctlp, port); 4618 } 4619 } 4620 4621 /* 4622 * Disable interrupts for a particular port. 4623 * 4624 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4625 * before calling us. 4626 */ 4627 static void 4628 si_disable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4629 { 4630 uint32_t mask; 4631 4632 /* get the current settings first. */ 4633 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4634 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4635 4636 /* clear the bit for current port. */ 4637 CLEAR_BIT(mask, port); 4638 4639 /* now use this mask to disable the interrupt. */ 4640 ddi_put32(si_ctlp->sictl_global_acc_handle, 4641 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4642 mask); 4643 4644 } 4645 4646 /* 4647 * Disable interrupts for all the ports. 4648 */ 4649 static void 4650 si_disable_all_interrupts(si_ctl_state_t *si_ctlp) 4651 { 4652 int port; 4653 4654 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4655 si_disable_port_interrupts(si_ctlp, port); 4656 } 4657 } 4658 4659 /* 4660 * Fetches the latest sstatus, scontrol, serror, sactive registers 4661 * and stuffs them into sata_device_t structure. 4662 */ 4663 static void 4664 fill_dev_sregisters(si_ctl_state_t *si_ctlp, int port, sata_device_t *satadev) 4665 { 4666 satadev->satadev_scr.sstatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4667 (uint32_t *)(PORT_SSTATUS(si_ctlp, port))); 4668 satadev->satadev_scr.serror = ddi_get32(si_ctlp->sictl_port_acc_handle, 4669 (uint32_t *)(PORT_SERROR(si_ctlp, port))); 4670 satadev->satadev_scr.sactive = ddi_get32(si_ctlp->sictl_port_acc_handle, 4671 (uint32_t *)(PORT_SACTIVE(si_ctlp, port))); 4672 satadev->satadev_scr.scontrol = 4673 ddi_get32(si_ctlp->sictl_port_acc_handle, 4674 (uint32_t *)(PORT_SCONTROL(si_ctlp, port))); 4675 4676 } 4677 4678 /* 4679 * si_add_legacy_intrs() handles INTx and legacy interrupts. 4680 */ 4681 static int 4682 si_add_legacy_intrs(si_ctl_state_t *si_ctlp) 4683 { 4684 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4685 int actual, count = 0; 4686 int x, y, rc, inum = 0; 4687 4688 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_add_legacy_intrs"); 4689 4690 /* get number of interrupts. */ 4691 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &count); 4692 if ((rc != DDI_SUCCESS) || (count == 0)) { 4693 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4694 "ddi_intr_get_nintrs() failed, " 4695 "rc %d count %d\n", rc, count); 4696 return (DDI_FAILURE); 4697 } 4698 4699 /* Allocate an array of interrupt handles. */ 4700 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4701 si_ctlp->sictl_htable = kmem_zalloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4702 4703 /* call ddi_intr_alloc(). */ 4704 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_FIXED, 4705 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 4706 4707 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4708 SIDBG1(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4709 "ddi_intr_alloc() failed, rc %d\n", rc); 4710 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4711 return (DDI_FAILURE); 4712 } 4713 4714 if (actual < count) { 4715 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4716 "Requested: %d, Received: %d", count, actual); 4717 4718 for (x = 0; x < actual; x++) { 4719 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4720 } 4721 4722 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4723 return (DDI_FAILURE); 4724 } 4725 4726 si_ctlp->sictl_intr_cnt = actual; 4727 4728 /* Get intr priority. */ 4729 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4730 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4731 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4732 "ddi_intr_get_pri() failed"); 4733 4734 for (x = 0; x < actual; x++) { 4735 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4736 } 4737 4738 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4739 return (DDI_FAILURE); 4740 } 4741 4742 /* Test for high level mutex. */ 4743 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4744 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4745 "si_add_legacy_intrs: Hi level intr not supported"); 4746 4747 for (x = 0; x < actual; x++) { 4748 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4749 } 4750 4751 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4752 4753 return (DDI_FAILURE); 4754 } 4755 4756 /* Call ddi_intr_add_handler(). */ 4757 for (x = 0; x < actual; x++) { 4758 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4759 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4760 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4761 "ddi_intr_add_handler() failed"); 4762 4763 for (y = 0; y < actual; y++) { 4764 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4765 } 4766 4767 kmem_free(si_ctlp->sictl_htable, 4768 si_ctlp->sictl_intr_size); 4769 return (DDI_FAILURE); 4770 } 4771 } 4772 4773 /* Call ddi_intr_enable() for legacy interrupts. */ 4774 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4775 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4776 } 4777 4778 return (DDI_SUCCESS); 4779 } 4780 4781 /* 4782 * si_add_msictl_intrs() handles MSI interrupts. 4783 */ 4784 static int 4785 si_add_msi_intrs(si_ctl_state_t *si_ctlp) 4786 { 4787 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4788 int count, avail, actual; 4789 int x, y, rc, inum = 0; 4790 4791 SIDBG0(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, "si_add_msi_intrs"); 4792 4793 /* get number of interrupts. */ 4794 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSI, &count); 4795 if ((rc != DDI_SUCCESS) || (count == 0)) { 4796 SIDBG2(SIDBG_INIT, si_ctlp, 4797 "ddi_intr_get_nintrs() failed, " 4798 "rc %d count %d\n", rc, count); 4799 return (DDI_FAILURE); 4800 } 4801 4802 /* get number of available interrupts. */ 4803 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSI, &avail); 4804 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4805 SIDBG2(SIDBG_INIT, si_ctlp, 4806 "ddi_intr_get_navail() failed, " 4807 "rc %d avail %d\n", rc, avail); 4808 return (DDI_FAILURE); 4809 } 4810 4811 #if SI_DEBUG 4812 if (avail < count) { 4813 SIDBG2(SIDBG_INIT, si_ctlp, 4814 "ddi_intr_get_nvail returned %d, navail() returned %d", 4815 count, avail); 4816 } 4817 #endif /* SI_DEBUG */ 4818 4819 /* Allocate an array of interrupt handles. */ 4820 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4821 si_ctlp->sictl_htable = kmem_alloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4822 4823 /* call ddi_intr_alloc(). */ 4824 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_MSI, 4825 inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 4826 4827 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4828 SIDBG1(SIDBG_INIT, si_ctlp, 4829 "ddi_intr_alloc() failed, rc %d\n", rc); 4830 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4831 return (DDI_FAILURE); 4832 } 4833 4834 #if SI_DEBUG 4835 /* use interrupt count returned */ 4836 if (actual < count) { 4837 SIDBG2(SIDBG_INIT, si_ctlp, 4838 "Requested: %d, Received: %d", count, actual); 4839 } 4840 #endif /* SI_DEBUG */ 4841 4842 si_ctlp->sictl_intr_cnt = actual; 4843 4844 /* 4845 * Get priority for first msi, assume remaining are all the same. 4846 */ 4847 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4848 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4849 SIDBG0(SIDBG_INIT, si_ctlp, "ddi_intr_get_pri() failed"); 4850 4851 /* Free already allocated intr. */ 4852 for (y = 0; y < actual; y++) { 4853 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4854 } 4855 4856 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4857 return (DDI_FAILURE); 4858 } 4859 4860 /* Test for high level mutex. */ 4861 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4862 SIDBG0(SIDBG_INIT, si_ctlp, 4863 "si_add_msi_intrs: Hi level intr not supported"); 4864 4865 /* Free already allocated intr. */ 4866 for (y = 0; y < actual; y++) { 4867 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4868 } 4869 4870 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4871 4872 return (DDI_FAILURE); 4873 } 4874 4875 /* Call ddi_intr_add_handler(). */ 4876 for (x = 0; x < actual; x++) { 4877 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4878 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4879 SIDBG0(SIDBG_INIT, si_ctlp, 4880 "ddi_intr_add_handler() failed"); 4881 4882 /* Free already allocated intr. */ 4883 for (y = 0; y < actual; y++) { 4884 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4885 } 4886 4887 kmem_free(si_ctlp->sictl_htable, 4888 si_ctlp->sictl_intr_size); 4889 return (DDI_FAILURE); 4890 } 4891 } 4892 4893 (void) ddi_intr_get_cap(si_ctlp->sictl_htable[0], 4894 &si_ctlp->sictl_intr_cap); 4895 4896 if (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 4897 /* Call ddi_intr_block_enable() for MSI. */ 4898 (void) ddi_intr_block_enable(si_ctlp->sictl_htable, 4899 si_ctlp->sictl_intr_cnt); 4900 } else { 4901 /* Call ddi_intr_enable() for MSI non block enable. */ 4902 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4903 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4904 } 4905 } 4906 4907 return (DDI_SUCCESS); 4908 } 4909 4910 /* 4911 * Removes the registered interrupts irrespective of whether they 4912 * were legacy or MSI. 4913 */ 4914 static void 4915 si_rem_intrs(si_ctl_state_t *si_ctlp) 4916 { 4917 int x; 4918 4919 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_rem_intrs entered"); 4920 4921 /* Disable all interrupts. */ 4922 if ((si_ctlp->sictl_intr_type == DDI_INTR_TYPE_MSI) && 4923 (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 4924 /* Call ddi_intr_block_disable(). */ 4925 (void) ddi_intr_block_disable(si_ctlp->sictl_htable, 4926 si_ctlp->sictl_intr_cnt); 4927 } else { 4928 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4929 (void) ddi_intr_disable(si_ctlp->sictl_htable[x]); 4930 } 4931 } 4932 4933 /* Call ddi_intr_remove_handler(). */ 4934 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4935 (void) ddi_intr_remove_handler(si_ctlp->sictl_htable[x]); 4936 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4937 } 4938 4939 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4940 } 4941 4942 /* 4943 * Resets either the port or the device connected to the port based on 4944 * the flag variable. 4945 * 4946 * The reset effectively throws away all the pending commands. So, the caller 4947 * has to make provision to handle the pending commands. 4948 * 4949 * After the reset, we wait till the port is ready again. 4950 * 4951 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4952 * before calling us. 4953 * 4954 * Note: Not port-mult aware. 4955 */ 4956 static int 4957 si_reset_dport_wait_till_ready( 4958 si_ctl_state_t *si_ctlp, 4959 si_port_state_t *si_portp, 4960 int port, 4961 int flag) 4962 { 4963 uint32_t port_status; 4964 int loop_count = 0; 4965 sata_device_t sdevice; 4966 uint32_t SStatus; 4967 uint32_t SControl; 4968 uint32_t port_intr_status; 4969 4970 _NOTE(ASSUMING_PROTECTED(si_portp)) 4971 4972 if (flag == SI_PORT_RESET) { 4973 ddi_put32(si_ctlp->sictl_port_acc_handle, 4974 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4975 PORT_CONTROL_SET_BITS_PORT_RESET); 4976 4977 /* Port reset is not self clearing. So clear it now. */ 4978 ddi_put32(si_ctlp->sictl_port_acc_handle, 4979 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 4980 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 4981 } else { 4982 /* Reset the device. */ 4983 ddi_put32(si_ctlp->sictl_port_acc_handle, 4984 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4985 PORT_CONTROL_SET_BITS_DEV_RESET); 4986 4987 /* 4988 * tidbit: this bit is self clearing; so there is no need 4989 * for manual clear as we did for port reset. 4990 */ 4991 } 4992 4993 /* Set the reset in progress flag */ 4994 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 4995 si_portp->siport_reset_in_progress = 1; 4996 } 4997 4998 4999 /* 5000 * Every reset needs a PHY initialization. 5001 * 5002 * The way to initialize the PHY is to write a 1 and then 5003 * a 0 to DET field of SControl register. 5004 */ 5005 5006 /* Fetch the current SControl before writing the DET part with 1. */ 5007 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 5008 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 5009 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 5010 ddi_put32(si_ctlp->sictl_port_acc_handle, 5011 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 5012 SControl); 5013 #ifndef __lock_lint 5014 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 5015 #endif /* __lock_lint */ 5016 5017 /* Now fetch the SControl again and rewrite the DET part with 0 */ 5018 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 5019 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 5020 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 5021 ddi_put32(si_ctlp->sictl_port_acc_handle, 5022 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 5023 SControl); 5024 5025 /* 5026 * PHY may be initialized by now. Check the DET field of SStatus 5027 * to determine if there is a device present. 5028 * 5029 * The DET field is valid only if IPM field indicates that 5030 * the interface is in active state. 5031 */ 5032 5033 loop_count = 0; 5034 do { 5035 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 5036 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 5037 5038 if (SSTATUS_GET_IPM(SStatus) != 5039 SSTATUS_IPM_INTERFACE_ACTIVE) { 5040 /* 5041 * If the interface is not active, the DET field 5042 * is considered not accurate. So we want to 5043 * continue looping. 5044 */ 5045 SSTATUS_SET_DET(SStatus, SSTATUS_DET_NODEV_NOPHY); 5046 } 5047 5048 if (loop_count++ > SI_POLLRATE_SSTATUS) { 5049 /* We are effectively timing out after 0.1 sec. */ 5050 break; 5051 } 5052 5053 /* Wait for 10 millisec */ 5054 #ifndef __lock_lint 5055 delay(SI_10MS_TICKS); 5056 #endif /* __lock_lint */ 5057 5058 } while (SSTATUS_GET_DET(SStatus) != SSTATUS_DET_DEVPRESENT_PHYONLINE); 5059 5060 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 5061 "si_reset_dport_wait_till_ready: loop count: %d, \ 5062 SStatus: 0x%x", 5063 loop_count, 5064 SStatus); 5065 5066 /* Now check for port readiness. */ 5067 loop_count = 0; 5068 do { 5069 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5070 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5071 5072 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5073 /* We are effectively timing out after 0.5 sec. */ 5074 break; 5075 } 5076 5077 /* Wait for 10 millisec */ 5078 #ifndef __lock_lint 5079 delay(SI_10MS_TICKS); 5080 #endif /* __lock_lint */ 5081 5082 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5083 5084 SIDBG3(SIDBG_POLL_LOOP, si_ctlp, 5085 "si_reset_dport_wait_till_ready: loop count: %d, \ 5086 port_status: 0x%x, SStatus: 0x%x", 5087 loop_count, 5088 port_status, 5089 SStatus); 5090 5091 /* Indicate to the framework that a reset has happened. */ 5092 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 5093 5094 bzero((void *)&sdevice, sizeof (sata_device_t)); 5095 5096 sdevice.satadev_addr.cport = (uint8_t)port; 5097 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 5098 5099 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 5100 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT; 5101 } else { 5102 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5103 } 5104 sdevice.satadev_state = SATA_DSTATE_RESET | 5105 SATA_DSTATE_PWR_ACTIVE; 5106 if (si_ctlp->sictl_sata_hba_tran) { 5107 sata_hba_event_notify( 5108 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 5109 &sdevice, 5110 SATA_EVNT_DEVICE_RESET); 5111 } 5112 5113 SIDBG0(SIDBG_EVENT, si_ctlp, 5114 "sending event up: SATA_EVNT_RESET"); 5115 } 5116 5117 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5118 (SSTATUS_GET_DET(SStatus) == 5119 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5120 /* The interface is active and the device is present */ 5121 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5122 /* But the port is is not ready for some reason */ 5123 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5124 "si_reset_dport_wait_till_ready failed"); 5125 return (SI_FAILURE); 5126 } 5127 } 5128 5129 5130 /* 5131 * For some reason, we are losing the interrupt enablement after 5132 * any reset condition. So restore them back now. 5133 */ 5134 5135 SIDBG1(SIDBG_INIT, si_ctlp, 5136 "current interrupt enable set: 0x%x", 5137 ddi_get32(si_ctlp->sictl_port_acc_handle, 5138 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port))); 5139 5140 ddi_put32(si_ctlp->sictl_port_acc_handle, 5141 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 5142 (INTR_COMMAND_COMPLETE | 5143 INTR_COMMAND_ERROR | 5144 INTR_PORT_READY | 5145 INTR_POWER_CHANGE | 5146 INTR_PHYRDY_CHANGE | 5147 INTR_COMWAKE_RECEIVED | 5148 INTR_UNRECOG_FIS | 5149 INTR_DEV_XCHANGED | 5150 INTR_SETDEVBITS_NOTIFY)); 5151 5152 si_enable_port_interrupts(si_ctlp, port); 5153 5154 /* 5155 * make sure interrupts are cleared 5156 */ 5157 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 5158 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 5159 5160 ddi_put32(si_ctlp->sictl_port_acc_handle, 5161 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, 5162 port)), 5163 port_intr_status & INTR_MASK); 5164 5165 5166 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5167 "si_reset_dport_wait_till_ready returning success"); 5168 5169 return (SI_SUCCESS); 5170 } 5171 5172 /* 5173 * Initializes the port. 5174 * 5175 * Initialization effectively throws away all the pending commands on 5176 * the port. So, the caller has to make provision to handle the pending 5177 * commands. 5178 * 5179 * After the port initialization, we wait till the port is ready again. 5180 * 5181 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 5182 * before calling us. 5183 */ 5184 static int 5185 si_initialize_port_wait_till_ready(si_ctl_state_t *si_ctlp, int port) 5186 { 5187 uint32_t port_status; 5188 int loop_count = 0; 5189 uint32_t SStatus; 5190 5191 /* Initialize the port. */ 5192 ddi_put32(si_ctlp->sictl_port_acc_handle, 5193 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 5194 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 5195 5196 /* Wait until Port Ready */ 5197 loop_count = 0; 5198 do { 5199 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5200 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5201 5202 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5203 SIDBG1(SIDBG_INTR, si_ctlp, 5204 "si_initialize_port_wait is timing out: " 5205 "port_status: %x", 5206 port_status); 5207 /* We are effectively timing out after 0.5 sec. */ 5208 break; 5209 } 5210 5211 /* Wait for 10 millisec */ 5212 #ifndef __lock_lint 5213 delay(SI_10MS_TICKS); 5214 #endif /* __lock_lint */ 5215 5216 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5217 5218 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 5219 "si_initialize_port_wait_till_ready: loop count: %d", 5220 loop_count); 5221 5222 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 5223 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 5224 5225 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5226 (SSTATUS_GET_DET(SStatus) == 5227 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5228 /* The interface is active and the device is present */ 5229 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5230 /* But the port is is not ready for some reason */ 5231 return (SI_FAILURE); 5232 } 5233 } 5234 5235 return (SI_SUCCESS); 5236 } 5237 5238 5239 /* 5240 * si_watchdog_handler() calls us if it detects that there are some 5241 * commands which timed out. We recalculate the timed out commands once 5242 * again since some of them may have finished recently. 5243 */ 5244 static void 5245 si_timeout_pkts( 5246 si_ctl_state_t *si_ctlp, 5247 si_port_state_t *si_portp, 5248 int port, 5249 uint32_t timedout_tags) 5250 { 5251 uint32_t slot_status; 5252 uint32_t finished_tags; 5253 5254 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, "si_timeout_pkts entry"); 5255 5256 mutex_enter(&si_portp->siport_mutex); 5257 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5258 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 5259 5260 si_portp->mopping_in_progress++; 5261 5262 /* 5263 * Initialize the controller. The only way to timeout the commands 5264 * is to reset or initialize the controller. We mop commands after 5265 * the initialization. 5266 */ 5267 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 5268 5269 /* 5270 * Recompute the timedout tags since some of them may have finished 5271 * meanwhile. 5272 */ 5273 finished_tags = si_portp->siport_pending_tags & 5274 ~slot_status & SI_SLOT_MASK; 5275 timedout_tags &= ~finished_tags; 5276 5277 SIDBG2(SIDBG_TIMEOUT, si_ctlp, 5278 "si_timeout_pkts: finished: %x, timeout: %x", 5279 finished_tags, 5280 timedout_tags); 5281 5282 si_mop_commands(si_ctlp, 5283 si_portp, 5284 port, 5285 slot_status, 5286 0, /* failed_tags */ 5287 timedout_tags, 5288 0, /* aborting_tags */ 5289 0); /* reset_tags */ 5290 5291 mutex_exit(&si_portp->siport_mutex); 5292 } 5293 5294 5295 5296 /* 5297 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 5298 * for long time. 5299 */ 5300 static void 5301 si_watchdog_handler(si_ctl_state_t *si_ctlp) 5302 { 5303 uint32_t pending_tags = 0; 5304 uint32_t timedout_tags = 0; 5305 si_port_state_t *si_portp; 5306 int port; 5307 int tmpslot; 5308 sata_pkt_t *satapkt; 5309 5310 /* max number of cycles this packet should survive */ 5311 int max_life_cycles; 5312 5313 /* how many cycles this packet survived so far */ 5314 int watched_cycles; 5315 5316 mutex_enter(&si_ctlp->sictl_mutex); 5317 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, 5318 "si_watchdog_handler entered"); 5319 5320 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 5321 5322 si_portp = si_ctlp->sictl_ports[port]; 5323 if (si_portp == NULL) { 5324 continue; 5325 } 5326 5327 mutex_enter(&si_portp->siport_mutex); 5328 5329 if (si_portp->siport_port_type == PORT_TYPE_NODEV) { 5330 mutex_exit(&si_portp->siport_mutex); 5331 continue; 5332 } 5333 5334 /* Skip the check for those ports in error recovery */ 5335 if (si_portp->mopping_in_progress > 0) { 5336 SIDBG1(SIDBG_INFO, si_ctlp, 5337 "si_watchdog_handler: port %d mopping " 5338 "in progress, so just return", port); 5339 mutex_exit(&si_portp->siport_mutex); 5340 continue; 5341 } 5342 5343 pending_tags = si_portp->siport_pending_tags; 5344 timedout_tags = 0; 5345 while (pending_tags) { 5346 tmpslot = ddi_ffs(pending_tags) - 1; 5347 if (tmpslot == -1) { 5348 break; 5349 } 5350 satapkt = si_portp->siport_slot_pkts[tmpslot]; 5351 5352 if ((satapkt != NULL) && satapkt->satapkt_time) { 5353 5354 /* 5355 * We are overloading satapkt_hba_driver_private 5356 * with watched_cycle count. 5357 * 5358 * If a packet has survived for more than it's 5359 * max life cycles, it is a candidate for time 5360 * out. 5361 */ 5362 watched_cycles = (int)(intptr_t) 5363 satapkt->satapkt_hba_driver_private; 5364 watched_cycles++; 5365 max_life_cycles = (satapkt->satapkt_time + 5366 si_watchdog_timeout - 1) / 5367 si_watchdog_timeout; 5368 if (watched_cycles > max_life_cycles) { 5369 timedout_tags |= (0x1 << tmpslot); 5370 SIDBG1(SIDBG_TIMEOUT|SIDBG_VERBOSE, 5371 si_ctlp, 5372 "watchdog: timedout_tags: 0x%x", 5373 timedout_tags); 5374 } 5375 satapkt->satapkt_hba_driver_private = 5376 (void *)(intptr_t)watched_cycles; 5377 } 5378 5379 CLEAR_BIT(pending_tags, tmpslot); 5380 } 5381 5382 if (timedout_tags) { 5383 mutex_exit(&si_portp->siport_mutex); 5384 mutex_exit(&si_ctlp->sictl_mutex); 5385 si_timeout_pkts(si_ctlp, si_portp, port, timedout_tags); 5386 mutex_enter(&si_ctlp->sictl_mutex); 5387 mutex_enter(&si_portp->siport_mutex); 5388 } 5389 5390 mutex_exit(&si_portp->siport_mutex); 5391 } 5392 5393 /* Reinstall the watchdog timeout handler. */ 5394 if (!(si_ctlp->sictl_flags & SI_NO_TIMEOUTS)) { 5395 si_ctlp->sictl_timeout_id = 5396 timeout((void (*)(void *))si_watchdog_handler, 5397 (caddr_t)si_ctlp, si_watchdog_tick); 5398 } 5399 mutex_exit(&si_ctlp->sictl_mutex); 5400 } 5401 5402 #if SI_DEBUG 5403 /* 5404 * Logs the message. 5405 */ 5406 static void 5407 si_log(si_ctl_state_t *si_ctlp, uint_t level, char *fmt, ...) 5408 { 5409 va_list ap; 5410 5411 mutex_enter(&si_log_mutex); 5412 5413 va_start(ap, fmt); 5414 if (si_ctlp) { 5415 (void) sprintf(si_log_buf, "%s-[%d]:", 5416 ddi_get_name(si_ctlp->sictl_devinfop), 5417 ddi_get_instance(si_ctlp->sictl_devinfop)); 5418 } else { 5419 (void) sprintf(si_log_buf, "si3124:"); 5420 } 5421 (void) vsprintf(si_log_buf, fmt, ap); 5422 va_end(ap); 5423 5424 cmn_err(level, "%s", si_log_buf); 5425 5426 mutex_exit(&si_log_mutex); 5427 5428 } 5429 #endif /* SI_DEBUG */ 5430 5431 static void 5432 si_copy_out_regs(sata_cmd_t *scmd, si_ctl_state_t *si_ctlp, uint8_t port, 5433 uint8_t slot) 5434 { 5435 uint32_t *fis_word_ptr; 5436 si_prb_t *prb; 5437 int i; 5438 5439 /* 5440 * The LRAM contains the the modified FIS after command completion, so 5441 * first copy it back to the in-core PRB pool. To save read cycles, 5442 * just copy over the FIS portion of the PRB pool. 5443 */ 5444 prb = &si_ctlp->sictl_ports[port]->siport_prbpool[slot]; 5445 5446 fis_word_ptr = (uint32_t *)(void *)(&prb->prb_fis); 5447 5448 for (i = 0; i < (sizeof (fis_reg_h2d_t)/4); i++) { 5449 fis_word_ptr[i] = ddi_get32( 5450 si_ctlp->sictl_port_acc_handle, 5451 (uint32_t *)(PORT_LRAM(si_ctlp, port, 5452 slot) + i * 4 + 0x08)); 5453 } 5454 5455 /* 5456 * always get the status register 5457 */ 5458 scmd->satacmd_status_reg = GET_FIS_COMMAND(prb->prb_fis); 5459 5460 DTRACE_PROBE1(satacmd_status_reg, int, scmd->satacmd_status_reg); 5461 5462 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) { 5463 scmd->satacmd_sec_count_msb = 5464 GET_FIS_SECTOR_COUNT_EXP(prb->prb_fis); 5465 SIDBG1(SIDBG_VERBOSE, NULL, 5466 "copyout satacmd_sec_count_msb %x\n", 5467 scmd->satacmd_sec_count_msb); 5468 } 5469 5470 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) { 5471 scmd->satacmd_lba_low_msb = GET_FIS_SECTOR_EXP(prb->prb_fis); 5472 SIDBG1(SIDBG_VERBOSE, NULL, "copyout satacmd_lba_low_msb %x\n", 5473 scmd->satacmd_lba_low_msb); 5474 } 5475 5476 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) { 5477 scmd->satacmd_lba_mid_msb = GET_FIS_CYL_LOW_EXP(prb->prb_fis); 5478 SIDBG1(SIDBG_VERBOSE, NULL, "copyout satacmd_lba_mid_msb %x\n", 5479 scmd->satacmd_lba_mid_msb); 5480 } 5481 5482 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) { 5483 scmd->satacmd_lba_high_msb = GET_FIS_CYL_HI_EXP(prb->prb_fis); 5484 SIDBG1(SIDBG_VERBOSE, NULL, "copyout satacmd_lba_high_msb %x\n", 5485 scmd->satacmd_lba_high_msb); 5486 } 5487 5488 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) { 5489 scmd->satacmd_sec_count_lsb = 5490 GET_FIS_SECTOR_COUNT(prb->prb_fis); 5491 SIDBG1(SIDBG_VERBOSE, NULL, 5492 "copyout satacmd_sec_count_lsb %x\n", 5493 scmd->satacmd_sec_count_lsb); 5494 } 5495 5496 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) { 5497 scmd->satacmd_lba_low_lsb = GET_FIS_SECTOR(prb->prb_fis); 5498 SIDBG1(SIDBG_VERBOSE, NULL, "copyout satacmd_lba_low_lsb %x\n", 5499 scmd->satacmd_lba_low_lsb); 5500 } 5501 5502 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) { 5503 scmd->satacmd_lba_mid_lsb = GET_FIS_CYL_LOW(prb->prb_fis); 5504 SIDBG1(SIDBG_VERBOSE, NULL, "copyout satacmd_lba_mid_lsb %x\n", 5505 scmd->satacmd_lba_mid_lsb); 5506 } 5507 5508 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) { 5509 scmd->satacmd_lba_high_lsb = GET_FIS_CYL_HI(prb->prb_fis); 5510 SIDBG1(SIDBG_VERBOSE, NULL, "copyout satacmd_lba_high_lsb %x\n", 5511 scmd->satacmd_lba_high_lsb); 5512 } 5513 5514 if (scmd->satacmd_flags.sata_copy_out_device_reg) { 5515 scmd->satacmd_device_reg = GET_FIS_DEV_HEAD(prb->prb_fis); 5516 SIDBG1(SIDBG_VERBOSE, NULL, "copyout satacmd_device_reg %x\n", 5517 scmd->satacmd_device_reg); 5518 } 5519 5520 if (scmd->satacmd_flags.sata_copy_out_error_reg) { 5521 scmd->satacmd_error_reg = GET_FIS_FEATURES(prb->prb_fis); 5522 SIDBG1(SIDBG_VERBOSE, NULL, "copyout satacmd_error_reg %x\n", 5523 scmd->satacmd_error_reg); 5524 } 5525 } 5526 5527 /* 5528 * This function clear the special port by send the PORT RESET 5529 * After reset was sent, all commands running on the port 5530 * is aborted 5531 */ 5532 static int 5533 si_clear_port(si_ctl_state_t *si_ctlp, int port) 5534 { 5535 5536 if (si_ctlp == NULL) 5537 return (SI_FAILURE); 5538 /* 5539 * reset this port so that all existing command 5540 * is clear 5541 */ 5542 ddi_put32(si_ctlp->sictl_port_acc_handle, 5543 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 5544 PORT_CONTROL_SET_BITS_PORT_RESET); 5545 5546 /* Port reset is not self clearing. So clear it now. */ 5547 ddi_put32(si_ctlp->sictl_port_acc_handle, 5548 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 5549 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 5550 return (SI_SUCCESS); 5551 } 5552 5553 /* 5554 * quiesce(9E) entry point. 5555 * This function is called when the system is single-threaded at high 5556 * PIL with preemption disabled. Therefore, this function must not be 5557 * blocked. 5558 * 5559 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 5560 * DDI_FAILURE indicates an error condition and should almost never happen. 5561 */ 5562 static int 5563 si_quiesce(dev_info_t *dip) 5564 { 5565 si_ctl_state_t *si_ctlp; 5566 int instance; 5567 int port; 5568 5569 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_quiesce enter"); 5570 instance = ddi_get_instance(dip); 5571 si_ctlp = ddi_get_soft_state(si_statep, instance); 5572 if (si_ctlp == NULL) 5573 return (DDI_FAILURE); 5574 5575 /* 5576 * Disable all the interrupts before quiesce 5577 */ 5578 5579 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 5580 si_disable_port_interrupts(si_ctlp, port); 5581 (void) si_clear_port(si_ctlp, port); 5582 } 5583 5584 return (DDI_SUCCESS); 5585 } 5586