1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 30 31 /* 32 * SiliconImage 3124/3132 sata controller driver 33 */ 34 35 /* 36 * 37 * 38 * Few Design notes 39 * 40 * 41 * I. General notes 42 * 43 * Even though the driver is named as si3124, it is actually meant to 44 * work with both 3124 and 3132 controllers. 45 * 46 * The current file si3124.c is the main driver code. The si3124reg.h 47 * holds the register definitions from SiI 3124/3132 data sheets. The 48 * si3124var.h holds the driver specific definitions which are not 49 * directly derived from data sheets. 50 * 51 * 52 * II. Data structures 53 * 54 * si_ctl_state_t: This holds the driver private information for each 55 * controller instance. Each of the sata ports within a single 56 * controller are represented by si_port_state_t. The 57 * sictl_global_acc_handle and sictl_global_address map the 58 * controller-wide global register space and are derived from pci 59 * BAR 0. The sictl_port_acc_handle and sictl_port_addr map the 60 * per-port register space and are derived from pci BAR 1. 61 * 62 * si_port_state_t: This holds the per port information. The siport_mutex 63 * holds the per port mutex. The siport_pending_tags is the bit mask of 64 * commands posted to controller. The siport_slot_pkts[] holds the 65 * pending sata packets. The siport_port_type holds the device type 66 * connected directly to the port while the siport_portmult_state 67 * holds the similar information for the devices behind a port 68 * multiplier. 69 * 70 * si_prb_t: This contains the PRB being posted to the controller. 71 * The two SGE entries contained within si_prb_t itself are not 72 * really used to hold any scatter gather entries. The scatter gather 73 * list is maintained external to PRB and is linked from one 74 * of the contained SGEs inside the PRB. For atapi devices, the 75 * first contained SGE holds the PACKET and second contained 76 * SGE holds the link to an external SGT. For non-atapi devices, 77 * the first contained SGE works as link to external SGT while 78 * second SGE is blank. 79 * 80 * external SGT tables: The external SGT tables pointed to from 81 * within si_prb_t are actually abstracted as si_sgblock_t. Each 82 * si_sgblock_t contains SI_MAX_SGT_TABLES_PER_PRB number of 83 * SGT tables linked in a chain. Currently this max value of 84 * SGT tables per block is hard coded as 10 which translates 85 * to a maximum of 31 dma cookies per single dma transfer. 86 * 87 * 88 * III. Driver operation 89 * 90 * Command Issuing: We use the "indirect method of command issuance". The 91 * PRB contains the command [and atapi PACKET] and a link to the 92 * external SGT chain. We write the physical address of the PRB into 93 * command activation register. There are 31 command slots for 94 * each port. After posting a command, we remember the posted slot & 95 * the sata packet in siport_pending_tags & siport_slot_pkts[] 96 * respectively. 97 * 98 * Command completion: On a successful completion, intr_command_complete() 99 * receives the control. The slot_status register holds the outstanding 100 * commands. Any reading of slot_status register automatically clears 101 * the interrupt. By comparing the slot_status register contents with 102 * per port siport_pending_tags, we determine which of the previously 103 * posted commands have finished. 104 * 105 * Timeout handling: Every 5 seconds, the watchdog handler scans thru the 106 * pending packets. The satapkt->satapkt_hba_driver_private field is 107 * overloaded with the count of watchdog cycles a packet has survived. 108 * If a packet has not completed within satapkt->satapkt_time, it is 109 * failed with error code of SATA_PKT_TIMEOUT. There is one watchdog 110 * handler running for each instance of controller. 111 * 112 * Error handling: For 3124, whenever any single command has encountered 113 * an error, the whole port execution completely stalls; there is no 114 * way of canceling or aborting the particular failed command. If 115 * the port is connected to a port multiplier, we can however RESUME 116 * other non-error devices connected to the port multiplier. 117 * The only way to recover the failed commands is to either initialize 118 * the port or reset the port/device. Both port initialize and reset 119 * operations result in discarding any of pending commands on the port. 120 * All such discarded commands are sent up to framework with PKT_RESET 121 * satapkt_reason. The assumption is that framework [and sd] would 122 * retry these commands again. The failed command itself however is 123 * sent up with PKT_DEV_ERROR. 124 * 125 * Here is the implementation strategy based on SiliconImage email 126 * regarding how they handle the errors for their Windows driver: 127 * 128 * a) for DEVICEERROR: 129 * If the port is connected to port multiplier, then 130 * 1) Resume the port 131 * 2) Wait for all the non-failed commands to complete 132 * 3) Perform a Port Initialize 133 * 134 * If the port is not connected to port multiplier, issue 135 * a Port Initialize. 136 * 137 * b) for SDBERROR: [SDBERROR means failed command is an NCQ command] 138 * Handle exactly like DEVICEERROR handling. 139 * After the Port Initialize done, do a Read Log Extended. 140 * 141 * c) for SENDFISERROR: 142 * If the port is connected to port multiplier, then 143 * 1) Resume the port 144 * 2) Wait for all the non-failed commands to complete 145 * 3) Perform a Port Initialize 146 * 147 * If the port is not connected to port multiplier, issue 148 * a Device Reset. 149 * 150 * d) for DATAFISERROR: 151 * If the port was executing an NCQ command, issue a Device 152 * Reset. 153 * 154 * Otherwise, follow the same error recovery as DEVICEERROR. 155 * 156 * e) for any other error, simply issue a Device Reset. 157 * 158 * To synchronize the interactions between various control flows (e.g. 159 * error recovery, timeout handling, si_poll_timeout, incoming flow 160 * from framework etc.), the following precautions are taken care of: 161 * a) During mopping_in_progress, no more commands are 162 * accepted from the framework. 163 * 164 * b) While draining the port multiplier commands, we should 165 * handle the possibility of any of the other waited commands 166 * failing (possibly with a different error code) 167 * 168 * Atapi handling: For atapi devices, we use the first SGE within the PRB 169 * to fill the scsi cdb while the second SGE points to external SGT. 170 * 171 * Queuing: Queue management is achieved external to the driver inside sd. 172 * Based on sata_hba_tran->qdepth and IDENTIFY data, the framework 173 * enables or disables the queuing. The qdepth for si3124 is 31 174 * commands. 175 * 176 * Port Multiplier: Enumeration of port multiplier is handled during the 177 * controller initialization and also during the a hotplug operation. 178 * Current logic takes care of situation where a port multiplier 179 * is hotplugged into a port which had a cdisk connected previously 180 * and vice versa. 181 * 182 * Register poll timeouts: Currently most of poll timeouts on register 183 * reads is set to 0.5 seconds except for a value of 10 seconds 184 * while reading the device signature. [Such a big timeout values 185 * for device signature were found needed during cold reboots 186 * for devices behind port multiplier]. 187 * 188 * 189 * IV. Known Issues 190 * 191 * 1) Currently the atapi packet length is hard coded to 12 bytes 192 * This is wrong. The framework should determine it just like they 193 * determine ad_cdb_len in legacy atapi.c. It should even reject 194 * init_pkt() for greater CDB lengths. See atapi.c. Revisit this 195 * in 2nd phase of framework project. 196 * 197 * 2) Do real REQUEST SENSE command instead of faking for ATAPI case. 198 * 199 */ 200 201 202 #include <sys/note.h> 203 #include <sys/scsi/scsi.h> 204 #include <sys/pci.h> 205 #include <sys/sata/sata_hba.h> 206 #include <sys/sata/adapters/si3124/si3124reg.h> 207 #include <sys/sata/adapters/si3124/si3124var.h> 208 209 /* 210 * Function prototypes for driver entry points 211 */ 212 static int si_attach(dev_info_t *, ddi_attach_cmd_t); 213 static int si_detach(dev_info_t *, ddi_detach_cmd_t); 214 static int si_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 215 static int si_power(dev_info_t *, int, int); 216 217 /* 218 * Function prototypes for SATA Framework interfaces 219 */ 220 static int si_register_sata_hba_tran(si_ctl_state_t *); 221 static int si_unregister_sata_hba_tran(si_ctl_state_t *); 222 223 static int si_tran_probe_port(dev_info_t *, sata_device_t *); 224 static int si_tran_start(dev_info_t *, sata_pkt_t *spkt); 225 static int si_tran_abort(dev_info_t *, sata_pkt_t *, int); 226 static int si_tran_reset_dport(dev_info_t *, sata_device_t *); 227 static int si_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 228 static int si_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 229 230 /* 231 * Local function prototypes 232 */ 233 234 static int si_alloc_port_state(si_ctl_state_t *, int); 235 static void si_dealloc_port_state(si_ctl_state_t *, int); 236 static int si_alloc_sgbpool(si_ctl_state_t *, int); 237 static void si_dealloc_sgbpool(si_ctl_state_t *, int); 238 static int si_alloc_prbpool(si_ctl_state_t *, int); 239 static void si_dealloc_prbpool(si_ctl_state_t *, int); 240 241 static void si_find_dev_signature(si_ctl_state_t *, si_port_state_t *, 242 int, int); 243 static void si_poll_cmd(si_ctl_state_t *, si_port_state_t *, int, int, 244 sata_pkt_t *); 245 static int si_claim_free_slot(si_ctl_state_t *, si_port_state_t *, int); 246 static int si_deliver_satapkt(si_ctl_state_t *, si_port_state_t *, int, 247 sata_pkt_t *); 248 249 static int si_initialize_controller(si_ctl_state_t *); 250 static void si_deinititalize_controller(si_ctl_state_t *); 251 static void si_init_port(si_ctl_state_t *, int); 252 static int si_enumerate_port_multiplier(si_ctl_state_t *, 253 si_port_state_t *, int); 254 static int si_read_portmult_reg(si_ctl_state_t *, si_port_state_t *, 255 int, int, int, uint32_t *); 256 static int si_write_portmult_reg(si_ctl_state_t *, si_port_state_t *, 257 int, int, int, uint32_t); 258 static void si_set_sense_data(sata_pkt_t *, int); 259 260 static uint_t si_intr(caddr_t, caddr_t); 261 static int si_intr_command_complete(si_ctl_state_t *, 262 si_port_state_t *, int); 263 static int si_intr_command_error(si_ctl_state_t *, 264 si_port_state_t *, int); 265 static void si_error_recovery_DEVICEERROR(si_ctl_state_t *, 266 si_port_state_t *, int); 267 static void si_error_recovery_SDBERROR(si_ctl_state_t *, 268 si_port_state_t *, int); 269 static void si_error_recovery_DATAFISERROR(si_ctl_state_t *, 270 si_port_state_t *, int); 271 static void si_error_recovery_SENDFISERROR(si_ctl_state_t *, 272 si_port_state_t *, int); 273 static void si_error_recovery_default(si_ctl_state_t *, 274 si_port_state_t *, int); 275 static uint8_t si_read_log_ext(si_ctl_state_t *, 276 si_port_state_t *si_portp, int); 277 static void si_log_error_message(si_ctl_state_t *, int, uint32_t); 278 static int si_intr_port_ready(si_ctl_state_t *, si_port_state_t *, int); 279 static int si_intr_pwr_change(si_ctl_state_t *, si_port_state_t *, int); 280 static int si_intr_phy_ready_change(si_ctl_state_t *, si_port_state_t *, int); 281 static int si_intr_comwake_rcvd(si_ctl_state_t *, si_port_state_t *, int); 282 static int si_intr_unrecognised_fis(si_ctl_state_t *, si_port_state_t *, int); 283 static int si_intr_dev_xchanged(si_ctl_state_t *, si_port_state_t *, int); 284 static int si_intr_decode_err_threshold(si_ctl_state_t *, 285 si_port_state_t *, int); 286 static int si_intr_crc_err_threshold(si_ctl_state_t *, si_port_state_t *, int); 287 static int si_intr_handshake_err_threshold(si_ctl_state_t *, 288 si_port_state_t *, int); 289 static int si_intr_set_devbits_notify(si_ctl_state_t *, si_port_state_t *, int); 290 static void si_handle_attention_raised(si_ctl_state_t *, 291 si_port_state_t *, int); 292 293 static void si_enable_port_interrupts(si_ctl_state_t *, int); 294 static void si_enable_all_interrupts(si_ctl_state_t *); 295 static void si_disable_port_interrupts(si_ctl_state_t *, int); 296 static void si_disable_all_interrupts(si_ctl_state_t *); 297 static void fill_dev_sregisters(si_ctl_state_t *, int, sata_device_t *); 298 static int si_add_legacy_intrs(si_ctl_state_t *); 299 static int si_add_msi_intrs(si_ctl_state_t *); 300 static void si_rem_intrs(si_ctl_state_t *); 301 302 static int si_reset_dport_wait_till_ready(si_ctl_state_t *, 303 si_port_state_t *, int, int); 304 static int si_initialize_port_wait_till_ready(si_ctl_state_t *, int); 305 306 static void si_timeout_pkts(si_ctl_state_t *, si_port_state_t *, int, uint32_t); 307 static void si_watchdog_handler(si_ctl_state_t *); 308 309 static void si_log(si_ctl_state_t *, uint_t, char *, ...); 310 311 static void si_copy_out_regs(sata_cmd_t *, fis_reg_h2d_t *); 312 313 /* 314 * DMA attributes for the data buffer 315 */ 316 317 static ddi_dma_attr_t buffer_dma_attr = { 318 DMA_ATTR_V0, /* dma_attr_version */ 319 0, /* dma_attr_addr_lo: lowest bus address */ 320 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 321 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 322 1, /* dma_attr_align: single byte aligned */ 323 1, /* dma_attr_burstsizes */ 324 1, /* dma_attr_minxfer */ 325 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 326 0xffffffffull, /* dma_attr_seg */ 327 SI_MAX_SGL_LENGTH, /* dma_attr_sgllen */ 328 512, /* dma_attr_granular */ 329 0, /* dma_attr_flags */ 330 }; 331 332 /* 333 * DMA attributes for incore RPB and SGT pool 334 */ 335 static ddi_dma_attr_t prb_sgt_dma_attr = { 336 DMA_ATTR_V0, /* dma_attr_version */ 337 0, /* dma_attr_addr_lo: lowest bus address */ 338 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 339 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 340 8, /* dma_attr_align: quad word aligned */ 341 1, /* dma_attr_burstsizes */ 342 1, /* dma_attr_minxfer */ 343 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 344 0xffffffffull, /* dma_attr_seg */ 345 1, /* dma_attr_sgllen */ 346 1, /* dma_attr_granular */ 347 0, /* dma_attr_flags */ 348 }; 349 350 /* Device access attributes */ 351 static ddi_device_acc_attr_t accattr = { 352 DDI_DEVICE_ATTR_V0, 353 DDI_STRUCTURE_LE_ACC, 354 DDI_STRICTORDER_ACC 355 }; 356 357 358 static struct dev_ops sictl_dev_ops = { 359 DEVO_REV, /* devo_rev */ 360 0, /* refcnt */ 361 si_getinfo, /* info */ 362 nulldev, /* identify */ 363 nulldev, /* probe */ 364 si_attach, /* attach */ 365 si_detach, /* detach */ 366 nodev, /* no reset */ 367 (struct cb_ops *)0, /* driver operations */ 368 NULL, /* bus operations */ 369 si_power /* power */ 370 }; 371 372 static sata_tran_hotplug_ops_t si_tran_hotplug_ops = { 373 SATA_TRAN_HOTPLUG_OPS_REV_1, 374 si_tran_hotplug_port_activate, 375 si_tran_hotplug_port_deactivate 376 }; 377 378 379 static int si_watchdog_timeout = 5; /* 5 seconds */ 380 static int si_watchdog_tick; 381 382 extern struct mod_ops mod_driverops; 383 384 static struct modldrv modldrv = { 385 &mod_driverops, /* driverops */ 386 "si3124 driver v%I%", 387 &sictl_dev_ops, /* driver ops */ 388 }; 389 390 static struct modlinkage modlinkage = { 391 MODREV_1, 392 &modldrv, 393 NULL 394 }; 395 396 397 /* The following are needed for si_log() */ 398 static kmutex_t si_log_mutex; 399 static char si_log_buf[512]; 400 uint32_t si_debug_flags = 0x0; 401 static int is_msi_supported = 0; 402 403 /* Opaque state pointer to be initialized by ddi_soft_state_init() */ 404 static void *si_statep = NULL; 405 406 /* 407 * si3124 module initialization. 408 * 409 */ 410 int 411 _init(void) 412 { 413 int error; 414 415 error = ddi_soft_state_init(&si_statep, sizeof (si_ctl_state_t), 0); 416 if (error != 0) { 417 return (error); 418 } 419 420 mutex_init(&si_log_mutex, NULL, MUTEX_DRIVER, NULL); 421 422 if ((error = sata_hba_init(&modlinkage)) != 0) { 423 mutex_destroy(&si_log_mutex); 424 ddi_soft_state_fini(&si_statep); 425 return (error); 426 } 427 428 error = mod_install(&modlinkage); 429 if (error != 0) { 430 sata_hba_fini(&modlinkage); 431 mutex_destroy(&si_log_mutex); 432 ddi_soft_state_fini(&si_statep); 433 return (error); 434 } 435 436 si_watchdog_tick = drv_usectohz((clock_t)si_watchdog_timeout * 1000000); 437 438 return (error); 439 } 440 441 /* 442 * si3124 module uninitialize. 443 * 444 */ 445 int 446 _fini(void) 447 { 448 int error; 449 450 error = mod_remove(&modlinkage); 451 if (error != 0) { 452 return (error); 453 } 454 455 /* Remove the resources allocated in _init(). */ 456 sata_hba_fini(&modlinkage); 457 mutex_destroy(&si_log_mutex); 458 ddi_soft_state_fini(&si_statep); 459 460 return (error); 461 } 462 463 /* 464 * _info entry point 465 * 466 */ 467 int 468 _info(struct modinfo *modinfop) 469 { 470 return (mod_info(&modlinkage, modinfop)); 471 } 472 473 474 /* 475 * The attach entry point for dev_ops. 476 * 477 * We initialize the controller, initialize the soft state, register 478 * the interrupt handlers and then register ourselves with sata framework. 479 */ 480 static int 481 si_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 482 { 483 si_ctl_state_t *si_ctlp; 484 int instance; 485 int status; 486 int attach_state; 487 int intr_types; 488 sata_device_t sdevice; 489 490 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_attach enter"); 491 instance = ddi_get_instance(dip); 492 attach_state = ATTACH_PROGRESS_NONE; 493 494 switch (cmd) { 495 496 case DDI_ATTACH: 497 498 /* Allocate si_softc. */ 499 status = ddi_soft_state_zalloc(si_statep, instance); 500 if (status != DDI_SUCCESS) { 501 goto err_out; 502 } 503 504 si_ctlp = ddi_get_soft_state(si_statep, instance); 505 si_ctlp->sictl_devinfop = dip; 506 507 attach_state |= ATTACH_PROGRESS_STATEP_ALLOC; 508 509 /* Configure pci config space handle. */ 510 status = pci_config_setup(dip, &si_ctlp->sictl_pci_conf_handle); 511 if (status != DDI_SUCCESS) { 512 goto err_out; 513 } 514 515 si_ctlp->sictl_devid = 516 pci_config_get16(si_ctlp->sictl_pci_conf_handle, 517 PCI_CONF_DEVID); 518 if (si_ctlp->sictl_devid == SI3132_DEV_ID) { 519 si_ctlp->sictl_num_ports = SI3132_MAX_PORTS; 520 } else { 521 si_ctlp->sictl_num_ports = SI3124_MAX_PORTS; 522 } 523 524 attach_state |= ATTACH_PROGRESS_CONF_HANDLE; 525 526 /* Now map the bar0; the bar0 contains the global registers. */ 527 status = ddi_regs_map_setup(dip, 528 PCI_BAR0, 529 (caddr_t *)&si_ctlp->sictl_global_addr, 530 0, 531 0, 532 &accattr, 533 &si_ctlp->sictl_global_acc_handle); 534 if (status != DDI_SUCCESS) { 535 goto err_out; 536 } 537 538 attach_state |= ATTACH_PROGRESS_BAR0_MAP; 539 540 /* Now map bar1; the bar1 contains the port registers. */ 541 status = ddi_regs_map_setup(dip, 542 PCI_BAR1, 543 (caddr_t *)&si_ctlp->sictl_port_addr, 544 0, 545 0, 546 &accattr, 547 &si_ctlp->sictl_port_acc_handle); 548 if (status != DDI_SUCCESS) { 549 goto err_out; 550 } 551 552 attach_state |= ATTACH_PROGRESS_BAR1_MAP; 553 554 /* 555 * Disable all the interrupts before adding interrupt 556 * handler(s). The interrupts shall be re-enabled selectively 557 * out of si_init_port(). 558 */ 559 si_disable_all_interrupts(si_ctlp); 560 561 /* Get supported interrupt types. */ 562 if (ddi_intr_get_supported_types(dip, &intr_types) 563 != DDI_SUCCESS) { 564 SIDBG0(SIDBG_INIT, NULL, 565 "ddi_intr_get_supported_types failed"); 566 goto err_out; 567 } 568 569 SIDBG1(SIDBG_INIT, NULL, 570 "ddi_intr_get_supported_types() returned: 0x%x", 571 intr_types); 572 573 if (is_msi_supported && (intr_types & DDI_INTR_TYPE_MSI)) { 574 SIDBG0(SIDBG_INIT, NULL, "Using MSI interrupt type"); 575 576 /* 577 * Try MSI first, but fall back to legacy if MSI 578 * attach fails. 579 */ 580 if (si_add_msi_intrs(si_ctlp) == DDI_SUCCESS) { 581 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_MSI; 582 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 583 SIDBG0(SIDBG_INIT, NULL, 584 "MSI interrupt setup done"); 585 } else { 586 SIDBG0(SIDBG_INIT, NULL, 587 "MSI registration failed " 588 "will try Legacy interrupts"); 589 } 590 } 591 592 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED) && 593 (intr_types & DDI_INTR_TYPE_FIXED)) { 594 /* 595 * Either the MSI interrupt setup has failed or only 596 * fixed interrupts are available on the system. 597 */ 598 SIDBG0(SIDBG_INIT, NULL, "Using Legacy interrupt type"); 599 600 if (si_add_legacy_intrs(si_ctlp) == DDI_SUCCESS) { 601 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_FIXED; 602 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 603 SIDBG0(SIDBG_INIT, NULL, 604 "Legacy interrupt setup done"); 605 } else { 606 SIDBG0(SIDBG_INIT, NULL, 607 "legacy interrupt setup failed"); 608 goto err_out; 609 } 610 } 611 612 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED)) { 613 SIDBG0(SIDBG_INIT, NULL, 614 "si3124: No interrupts registered"); 615 goto err_out; 616 } 617 618 619 /* Initialize the mutex. */ 620 mutex_init(&si_ctlp->sictl_mutex, NULL, MUTEX_DRIVER, 621 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 622 623 attach_state |= ATTACH_PROGRESS_MUTEX_INIT; 624 625 /* 626 * Initialize the controller and driver core. 627 */ 628 si_ctlp->sictl_flags |= SI_ATTACH; 629 status = si_initialize_controller(si_ctlp); 630 si_ctlp->sictl_flags &= ~SI_ATTACH; 631 if (status) { 632 goto err_out; 633 } 634 635 attach_state |= ATTACH_PROGRESS_HW_INIT; 636 637 if (si_register_sata_hba_tran(si_ctlp)) { 638 SIDBG0(SIDBG_INIT, NULL, 639 "si3124: setting sata hba tran failed"); 640 goto err_out; 641 } 642 643 si_ctlp->sictl_timeout_id = timeout( 644 (void (*)(void *))si_watchdog_handler, 645 (caddr_t)si_ctlp, si_watchdog_tick); 646 647 si_ctlp->sictl_power_level = PM_LEVEL_D0; 648 649 return (DDI_SUCCESS); 650 651 case DDI_RESUME: 652 si_ctlp = ddi_get_soft_state(si_statep, instance); 653 654 status = si_initialize_controller(si_ctlp); 655 if (status) { 656 return (DDI_FAILURE); 657 } 658 659 si_ctlp->sictl_timeout_id = timeout( 660 (void (*)(void *))si_watchdog_handler, 661 (caddr_t)si_ctlp, si_watchdog_tick); 662 663 (void) pm_power_has_changed(dip, 0, PM_LEVEL_D0); 664 665 /* Notify SATA framework about RESUME. */ 666 if (sata_hba_attach(si_ctlp->sictl_devinfop, 667 si_ctlp->sictl_sata_hba_tran, 668 DDI_RESUME) != DDI_SUCCESS) { 669 return (DDI_FAILURE); 670 } 671 672 /* 673 * Notify the "framework" that it should reprobe ports to see 674 * if any device got changed while suspended. 675 */ 676 bzero((void *)&sdevice, sizeof (sata_device_t)); 677 sata_hba_event_notify(dip, &sdevice, 678 SATA_EVNT_PWR_LEVEL_CHANGED); 679 SIDBG0(SIDBG_INIT|SIDBG_EVENT, si_ctlp, 680 "sending event up: SATA_EVNT_PWR_LEVEL_CHANGED"); 681 682 (void) pm_idle_component(si_ctlp->sictl_devinfop, 0); 683 684 si_ctlp->sictl_power_level = PM_LEVEL_D0; 685 686 return (DDI_SUCCESS); 687 688 default: 689 return (DDI_FAILURE); 690 691 } 692 693 err_out: 694 if (attach_state & ATTACH_PROGRESS_HW_INIT) { 695 si_ctlp->sictl_flags |= SI_DETACH; 696 /* We want to set SI_DETACH to deallocate all memory */ 697 si_deinititalize_controller(si_ctlp); 698 si_ctlp->sictl_flags &= ~SI_DETACH; 699 } 700 701 if (attach_state & ATTACH_PROGRESS_MUTEX_INIT) { 702 mutex_destroy(&si_ctlp->sictl_mutex); 703 } 704 705 if (attach_state & ATTACH_PROGRESS_INTR_ADDED) { 706 si_rem_intrs(si_ctlp); 707 } 708 709 if (attach_state & ATTACH_PROGRESS_BAR1_MAP) { 710 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 711 } 712 713 if (attach_state & ATTACH_PROGRESS_BAR0_MAP) { 714 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 715 } 716 717 if (attach_state & ATTACH_PROGRESS_CONF_HANDLE) { 718 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 719 } 720 721 if (attach_state & ATTACH_PROGRESS_STATEP_ALLOC) { 722 ddi_soft_state_free(si_statep, instance); 723 } 724 725 return (DDI_FAILURE); 726 } 727 728 729 /* 730 * The detach entry point for dev_ops. 731 * 732 * We undo the things we did in si_attach(). 733 */ 734 static int 735 si_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 736 { 737 si_ctl_state_t *si_ctlp; 738 int instance; 739 740 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_detach enter"); 741 instance = ddi_get_instance(dip); 742 si_ctlp = ddi_get_soft_state(si_statep, instance); 743 744 switch (cmd) { 745 746 case DDI_DETACH: 747 748 mutex_enter(&si_ctlp->sictl_mutex); 749 750 /* disable the interrupts for an uninterrupted detach */ 751 si_disable_all_interrupts(si_ctlp); 752 753 mutex_exit(&si_ctlp->sictl_mutex); 754 /* unregister from the sata framework. */ 755 if (si_unregister_sata_hba_tran(si_ctlp) != SI_SUCCESS) { 756 si_enable_all_interrupts(si_ctlp); 757 return (DDI_FAILURE); 758 } 759 mutex_enter(&si_ctlp->sictl_mutex); 760 761 /* now cancel the timeout handler. */ 762 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 763 (void) untimeout(si_ctlp->sictl_timeout_id); 764 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 765 766 /* deinitialize the controller. */ 767 si_ctlp->sictl_flags |= SI_DETACH; 768 si_deinititalize_controller(si_ctlp); 769 si_ctlp->sictl_flags &= ~SI_DETACH; 770 771 /* destroy any mutexes */ 772 mutex_exit(&si_ctlp->sictl_mutex); 773 mutex_destroy(&si_ctlp->sictl_mutex); 774 775 /* remove the interrupts */ 776 si_rem_intrs(si_ctlp); 777 778 /* remove the reg maps. */ 779 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 780 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 781 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 782 783 /* free the soft state. */ 784 ddi_soft_state_free(si_statep, instance); 785 786 return (DDI_SUCCESS); 787 788 case DDI_SUSPEND: 789 /* Inform SATA framework */ 790 if (sata_hba_detach(dip, cmd) != DDI_SUCCESS) { 791 return (DDI_FAILURE); 792 } 793 794 mutex_enter(&si_ctlp->sictl_mutex); 795 796 /* 797 * Device needs to be at full power in case it is needed to 798 * handle dump(9e) to save CPR state after DDI_SUSPEND 799 * completes. This is OK since presumably power will be 800 * removed anyways. No outstanding transactions should be 801 * on the controller since the children are already quiesed. 802 * 803 * If any ioctls/cfgadm support is added that touches 804 * hardware, those entry points will need to check for 805 * suspend and then block or return errors until resume. 806 * 807 */ 808 if (pm_busy_component(si_ctlp->sictl_devinfop, 0) == 809 DDI_SUCCESS) { 810 mutex_exit(&si_ctlp->sictl_mutex); 811 (void) pm_raise_power(si_ctlp->sictl_devinfop, 0, 812 PM_LEVEL_D0); 813 mutex_enter(&si_ctlp->sictl_mutex); 814 } 815 816 si_deinititalize_controller(si_ctlp); 817 818 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 819 (void) untimeout(si_ctlp->sictl_timeout_id); 820 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 821 822 SIDBG1(SIDBG_POWER, NULL, "si3124%d: DDI_SUSPEND", instance); 823 824 mutex_exit(&si_ctlp->sictl_mutex); 825 826 return (DDI_SUCCESS); 827 828 default: 829 return (DDI_FAILURE); 830 831 } 832 833 } 834 835 static int 836 si_power(dev_info_t *dip, int component, int level) 837 { 838 #ifndef __lock_lint 839 _NOTE(ARGUNUSED(component)) 840 #endif /* __lock_lint */ 841 842 si_ctl_state_t *si_ctlp; 843 int instance = ddi_get_instance(dip); 844 int rval = DDI_SUCCESS; 845 int old_level; 846 sata_device_t sdevice; 847 848 si_ctlp = ddi_get_soft_state(si_statep, instance); 849 850 if (si_ctlp == NULL) { 851 return (DDI_FAILURE); 852 } 853 854 SIDBG0(SIDBG_ENTRY, NULL, "si_power enter"); 855 856 mutex_enter(&si_ctlp->sictl_mutex); 857 old_level = si_ctlp->sictl_power_level; 858 859 switch (level) { 860 case PM_LEVEL_D0: /* fully on */ 861 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 862 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D0); 863 #ifndef __lock_lint 864 delay(drv_usectohz(10000)); 865 #endif /* __lock_lint */ 866 si_ctlp->sictl_power_level = PM_LEVEL_D0; 867 (void) pci_restore_config_regs(si_ctlp->sictl_devinfop); 868 869 SIDBG2(SIDBG_POWER, si_ctlp, 870 "si3124%d: turning power ON. old level %d", 871 instance, old_level); 872 /* 873 * If called from attach, just raise device power, 874 * restore config registers (if they were saved 875 * from a previous detach that lowered power), 876 * and exit. 877 */ 878 if (si_ctlp->sictl_flags & SI_ATTACH) 879 break; 880 881 mutex_exit(&si_ctlp->sictl_mutex); 882 (void) si_initialize_controller(si_ctlp); 883 mutex_enter(&si_ctlp->sictl_mutex); 884 885 si_ctlp->sictl_timeout_id = timeout( 886 (void (*)(void *))si_watchdog_handler, 887 (caddr_t)si_ctlp, si_watchdog_tick); 888 889 bzero((void *)&sdevice, sizeof (sata_device_t)); 890 sata_hba_event_notify( 891 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 892 &sdevice, SATA_EVNT_PWR_LEVEL_CHANGED); 893 SIDBG0(SIDBG_EVENT|SIDBG_POWER, si_ctlp, 894 "sending event up: PWR_LEVEL_CHANGED"); 895 896 break; 897 898 case PM_LEVEL_D3: /* fully off */ 899 if (!(si_ctlp->sictl_flags & SI_DETACH)) { 900 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 901 (void) untimeout(si_ctlp->sictl_timeout_id); 902 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 903 904 si_deinititalize_controller(si_ctlp); 905 906 si_ctlp->sictl_power_level = PM_LEVEL_D3; 907 } 908 909 (void) pci_save_config_regs(si_ctlp->sictl_devinfop); 910 911 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 912 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D3HOT); 913 914 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 915 "old level %d", instance, old_level); 916 917 break; 918 919 default: 920 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 921 "old level %d", instance, old_level); 922 rval = DDI_FAILURE; 923 break; 924 } 925 926 mutex_exit(&si_ctlp->sictl_mutex); 927 928 return (rval); 929 } 930 931 932 /* 933 * The info entry point for dev_ops. 934 * 935 */ 936 static int 937 si_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 938 void *arg, 939 void **result) 940 { 941 #ifndef __lock_lint 942 _NOTE(ARGUNUSED(dip)) 943 #endif /* __lock_lint */ 944 si_ctl_state_t *si_ctlp; 945 int instance; 946 dev_t dev; 947 948 dev = (dev_t)arg; 949 instance = getminor(dev); 950 951 switch (infocmd) { 952 case DDI_INFO_DEVT2DEVINFO: 953 si_ctlp = ddi_get_soft_state(si_statep, instance); 954 if (si_ctlp != NULL) { 955 *result = si_ctlp->sictl_devinfop; 956 return (DDI_SUCCESS); 957 } else { 958 *result = NULL; 959 return (DDI_FAILURE); 960 } 961 case DDI_INFO_DEVT2INSTANCE: 962 *(int *)result = instance; 963 break; 964 default: 965 break; 966 } 967 return (DDI_SUCCESS); 968 } 969 970 971 972 /* 973 * Registers the si3124 with sata framework. 974 */ 975 static int 976 si_register_sata_hba_tran(si_ctl_state_t *si_ctlp) 977 { 978 struct sata_hba_tran *sata_hba_tran; 979 980 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 981 "si_register_sata_hba_tran entry"); 982 983 mutex_enter(&si_ctlp->sictl_mutex); 984 985 /* Allocate memory for the sata_hba_tran */ 986 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 987 988 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV; 989 sata_hba_tran->sata_tran_hba_dip = si_ctlp->sictl_devinfop; 990 sata_hba_tran->sata_tran_hba_dma_attr = &buffer_dma_attr; 991 992 sata_hba_tran->sata_tran_hba_num_cports = si_ctlp->sictl_num_ports; 993 sata_hba_tran->sata_tran_hba_features_support = 0; 994 sata_hba_tran->sata_tran_hba_qdepth = SI_NUM_SLOTS; 995 996 sata_hba_tran->sata_tran_probe_port = si_tran_probe_port; 997 sata_hba_tran->sata_tran_start = si_tran_start; 998 sata_hba_tran->sata_tran_abort = si_tran_abort; 999 sata_hba_tran->sata_tran_reset_dport = si_tran_reset_dport; 1000 sata_hba_tran->sata_tran_selftest = NULL; 1001 sata_hba_tran->sata_tran_hotplug_ops = &si_tran_hotplug_ops; 1002 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1003 sata_hba_tran->sata_tran_ioctl = NULL; 1004 mutex_exit(&si_ctlp->sictl_mutex); 1005 1006 /* Attach it to SATA framework */ 1007 if (sata_hba_attach(si_ctlp->sictl_devinfop, sata_hba_tran, DDI_ATTACH) 1008 != DDI_SUCCESS) { 1009 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1010 return (SI_FAILURE); 1011 } 1012 1013 mutex_enter(&si_ctlp->sictl_mutex); 1014 si_ctlp->sictl_sata_hba_tran = sata_hba_tran; 1015 mutex_exit(&si_ctlp->sictl_mutex); 1016 1017 return (SI_SUCCESS); 1018 } 1019 1020 1021 /* 1022 * Unregisters the si3124 with sata framework. 1023 */ 1024 static int 1025 si_unregister_sata_hba_tran(si_ctl_state_t *si_ctlp) 1026 { 1027 1028 /* Detach from the SATA framework. */ 1029 if (sata_hba_detach(si_ctlp->sictl_devinfop, DDI_DETACH) != 1030 DDI_SUCCESS) { 1031 return (SI_FAILURE); 1032 } 1033 1034 /* Deallocate sata_hba_tran. */ 1035 kmem_free((void *)si_ctlp->sictl_sata_hba_tran, 1036 sizeof (sata_hba_tran_t)); 1037 1038 si_ctlp->sictl_sata_hba_tran = NULL; 1039 1040 return (SI_SUCCESS); 1041 } 1042 1043 /* 1044 * Called by sata framework to probe a port. We return the 1045 * cached information from a previous hardware probe. 1046 * 1047 * The actual hardware probing itself was done either from within 1048 * si_initialize_controller() during the driver attach or 1049 * from a phy ready change interrupt handler. 1050 */ 1051 static int 1052 si_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1053 { 1054 1055 si_ctl_state_t *si_ctlp; 1056 uint8_t cport = sd->satadev_addr.cport; 1057 uint8_t pmport = sd->satadev_addr.pmport; 1058 uint8_t qual = sd->satadev_addr.qual; 1059 uint8_t port_type; 1060 si_port_state_t *si_portp; 1061 si_portmult_state_t *si_portmultp; 1062 1063 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1064 1065 SIDBG3(SIDBG_ENTRY, si_ctlp, 1066 "si_tran_probe_port: cport: 0x%x, pmport: 0x%x, qual: 0x%x", 1067 cport, pmport, qual); 1068 1069 if (cport >= SI_MAX_PORTS) { 1070 sd->satadev_type = SATA_DTYPE_NONE; 1071 sd->satadev_state = SATA_STATE_PROBED; 1072 return (SATA_FAILURE); 1073 } 1074 1075 mutex_enter(&si_ctlp->sictl_mutex); 1076 si_portp = si_ctlp->sictl_ports[cport]; 1077 mutex_exit(&si_ctlp->sictl_mutex); 1078 if (si_portp == NULL) { 1079 sd->satadev_type = SATA_DTYPE_NONE; 1080 sd->satadev_state = SATA_STATE_PROBED; 1081 return (SATA_FAILURE); 1082 } 1083 1084 mutex_enter(&si_portp->siport_mutex); 1085 1086 if (qual == SATA_ADDR_PMPORT) { 1087 if (pmport >= si_portp->siport_portmult_state.sipm_num_ports) { 1088 sd->satadev_type = SATA_DTYPE_NONE; 1089 sd->satadev_state = SATA_STATE_PROBED; 1090 mutex_exit(&si_portp->siport_mutex); 1091 return (SATA_FAILURE); 1092 } else { 1093 si_portmultp = &si_portp->siport_portmult_state; 1094 port_type = si_portmultp->sipm_port_type[pmport]; 1095 } 1096 } else { 1097 port_type = si_portp->siport_port_type; 1098 } 1099 1100 switch (port_type) { 1101 1102 case PORT_TYPE_DISK: 1103 sd->satadev_type = SATA_DTYPE_ATADISK; 1104 sd->satadev_state = SATA_STATE_PROBED; 1105 break; 1106 1107 case PORT_TYPE_ATAPI: 1108 sd->satadev_type = SATA_DTYPE_ATAPICD; 1109 sd->satadev_state = SATA_STATE_PROBED; 1110 break; 1111 1112 case PORT_TYPE_MULTIPLIER: 1113 sd->satadev_type = SATA_DTYPE_PMULT; 1114 sd->satadev_add_info = 1115 si_portp->siport_portmult_state.sipm_num_ports; 1116 sd->satadev_state = SATA_STATE_PROBED; 1117 break; 1118 1119 case PORT_TYPE_UNKNOWN: 1120 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1121 sd->satadev_state = SATA_STATE_PROBED; 1122 1123 default: 1124 /* we don't support any other device types. */ 1125 sd->satadev_type = SATA_DTYPE_NONE; 1126 sd->satadev_state = SATA_STATE_PROBED; 1127 break; 1128 } 1129 1130 if (qual == SATA_ADDR_PMPORT) { 1131 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1132 pmport, PSCR_REG0, &sd->satadev_scr.sstatus); 1133 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1134 pmport, PSCR_REG1, &sd->satadev_scr.serror); 1135 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1136 pmport, PSCR_REG2, &sd->satadev_scr.scontrol); 1137 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1138 pmport, PSCR_REG3, &sd->satadev_scr.sactive); 1139 } else { 1140 fill_dev_sregisters(si_ctlp, cport, sd); 1141 if (!(si_portp->siport_active)) { 1142 /* 1143 * Since we are implementing the port deactivation 1144 * in software only, we need to fake a valid value 1145 * for sstatus when the device is in deactivated state. 1146 */ 1147 SSTATUS_SET_DET(sd->satadev_scr.sstatus, 1148 SSTATUS_DET_PHYOFFLINE); 1149 SSTATUS_SET_IPM(sd->satadev_scr.sstatus, 1150 SSTATUS_IPM_NODEV_NOPHY); 1151 } 1152 } 1153 1154 mutex_exit(&si_portp->siport_mutex); 1155 return (SATA_SUCCESS); 1156 } 1157 1158 /* 1159 * Called by sata framework to transport a sata packet down stream. 1160 * 1161 * The actual work of building the FIS & transporting it to the hardware 1162 * is done out of the subroutine si_deliver_satapkt(). 1163 */ 1164 static int 1165 si_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1166 { 1167 si_ctl_state_t *si_ctlp; 1168 uint8_t cport; 1169 si_port_state_t *si_portp; 1170 int slot; 1171 1172 cport = spkt->satapkt_device.satadev_addr.cport; 1173 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1174 mutex_enter(&si_ctlp->sictl_mutex); 1175 si_portp = si_ctlp->sictl_ports[cport]; 1176 mutex_exit(&si_ctlp->sictl_mutex); 1177 1178 SIDBG1(SIDBG_ENTRY, si_ctlp, 1179 "si_tran_start entry: port: 0x%x", cport); 1180 1181 mutex_enter(&si_portp->siport_mutex); 1182 1183 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1184 !si_portp->siport_active) { 1185 /* 1186 * si_intr_phy_ready_change() may have rendered it to 1187 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1188 * it inactive. 1189 */ 1190 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1191 fill_dev_sregisters(si_ctlp, cport, &spkt->satapkt_device); 1192 mutex_exit(&si_portp->siport_mutex); 1193 return (SATA_TRAN_PORT_ERROR); 1194 } 1195 1196 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1197 si_portp->siport_reset_in_progress = 0; 1198 SIDBG1(SIDBG_ENTRY, si_ctlp, 1199 "si_tran_start clearing the " 1200 "reset_in_progress for port: 0x%x", cport); 1201 } 1202 1203 if (si_portp->siport_reset_in_progress && 1204 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1205 ! ddi_in_panic()) { 1206 1207 spkt->satapkt_reason = SATA_PKT_BUSY; 1208 SIDBG1(SIDBG_ERRS, si_ctlp, 1209 "si_tran_start returning BUSY while " 1210 "reset in progress: port: 0x%x", cport); 1211 mutex_exit(&si_portp->siport_mutex); 1212 return (SATA_TRAN_BUSY); 1213 } 1214 1215 if (si_portp->mopping_in_progress) { 1216 spkt->satapkt_reason = SATA_PKT_BUSY; 1217 SIDBG1(SIDBG_ERRS, si_ctlp, 1218 "si_tran_start returning BUSY while " 1219 "mopping in progress: port: 0x%x", cport); 1220 mutex_exit(&si_portp->siport_mutex); 1221 return (SATA_TRAN_BUSY); 1222 } 1223 1224 if ((slot = si_deliver_satapkt(si_ctlp, si_portp, cport, spkt)) 1225 == SI_FAILURE) { 1226 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1227 SIDBG1(SIDBG_ERRS, si_ctlp, 1228 "si_tran_start returning QUEUE_FULL: port: 0x%x", 1229 cport); 1230 mutex_exit(&si_portp->siport_mutex); 1231 return (SATA_TRAN_QUEUE_FULL); 1232 } 1233 1234 if (spkt->satapkt_op_mode & (SATA_OPMODE_POLLING|SATA_OPMODE_SYNCH)) { 1235 /* we need to poll now */ 1236 mutex_exit(&si_portp->siport_mutex); 1237 si_poll_cmd(si_ctlp, si_portp, cport, slot, spkt); 1238 mutex_enter(&si_portp->siport_mutex); 1239 } 1240 1241 mutex_exit(&si_portp->siport_mutex); 1242 return (SATA_TRAN_ACCEPTED); 1243 } 1244 1245 #define SENDUP_PACKET(si_portp, satapkt, reason) \ 1246 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1247 SATAC_WRITE_FPDMA_QUEUED) || \ 1248 (satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1249 SATAC_READ_FPDMA_QUEUED)) { \ 1250 si_portp->siport_pending_ncq_count--; \ 1251 } \ 1252 if (satapkt) { \ 1253 satapkt->satapkt_reason = reason; \ 1254 /* \ 1255 * We set the satapkt_reason in both synch and \ 1256 * non-synch cases. \ 1257 */ \ 1258 } \ 1259 if (satapkt && \ 1260 !(satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1261 satapkt->satapkt_comp) { \ 1262 mutex_exit(&si_portp->siport_mutex); \ 1263 (*satapkt->satapkt_comp)(satapkt); \ 1264 mutex_enter(&si_portp->siport_mutex); \ 1265 } 1266 1267 /* 1268 * Mopping is necessitated because of the si3124 hardware limitation. 1269 * The only way to recover from errors or to abort a command is to 1270 * reset the port/device but such a reset also results in throwing 1271 * away all the unfinished pending commands. 1272 * 1273 * A port or device is reset in four scenarios: 1274 * a) some commands failed with errors 1275 * b) or we need to timeout some commands 1276 * c) or we need to abort some commands 1277 * d) or we need reset the port at the request of sata framework 1278 * 1279 * In all these scenarios, we need to send any pending unfinished 1280 * commands up to sata framework. 1281 * 1282 * Only one mopping process at a time is allowed; this is achieved 1283 * by using siport_mop_mutex. 1284 */ 1285 static void 1286 si_mop_commands(si_ctl_state_t *si_ctlp, 1287 si_port_state_t *si_portp, 1288 uint8_t port, 1289 1290 uint32_t slot_status, 1291 uint32_t failed_tags, 1292 uint32_t timedout_tags, 1293 uint32_t aborting_tags, 1294 uint32_t reset_tags) 1295 { 1296 uint32_t finished_tags, unfinished_tags; 1297 int tmpslot; 1298 sata_pkt_t *satapkt; 1299 si_prb_t *prb; 1300 uint32_t *prb_word_ptr; 1301 int i; 1302 1303 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1304 "si_mop_commands entered: slot_status: 0x%x", 1305 slot_status); 1306 1307 SIDBG4(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1308 "si_mop_commands: failed_tags: 0x%x, timedout_tags: 0x%x" 1309 "aborting_tags: 0x%x, reset_tags: 0x%x", 1310 failed_tags, 1311 timedout_tags, 1312 aborting_tags, 1313 reset_tags); 1314 /* 1315 * We could be here for four reasons: abort, reset, 1316 * timeout or error handling. Only one such mopping 1317 * is allowed at a time. 1318 * 1319 * Note that we are already holding the main per port 1320 * mutex; all we need now is siport_mop_mutex. 1321 */ 1322 mutex_enter(&si_portp->siport_mop_mutex); 1323 mutex_enter(&si_portp->siport_mutex); 1324 1325 si_portp->mopping_in_progress = 1; 1326 1327 finished_tags = si_portp->siport_pending_tags & 1328 ~slot_status & SI_SLOT_MASK; 1329 1330 unfinished_tags = slot_status & SI_SLOT_MASK & 1331 ~failed_tags & 1332 ~aborting_tags & 1333 ~reset_tags & 1334 ~timedout_tags; 1335 1336 /* Send up the finished_tags with SATA_PKT_COMPLETED. */ 1337 while (finished_tags) { 1338 tmpslot = ddi_ffs(finished_tags) - 1; 1339 if (tmpslot == -1) { 1340 break; 1341 } 1342 1343 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1344 ASSERT(satapkt != NULL); 1345 prb = &si_portp->siport_prbpool[tmpslot]; 1346 ASSERT(prb != NULL); 1347 satapkt->satapkt_cmd.satacmd_status_reg = 1348 GET_FIS_COMMAND(prb->prb_fis); 1349 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 1350 si_copy_out_regs(&satapkt->satapkt_cmd, &prb->prb_fis); 1351 1352 SIDBG1(SIDBG_ERRS, si_ctlp, 1353 "si_mop_commands sending up completed satapkt: %x", 1354 satapkt); 1355 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 1356 1357 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1358 CLEAR_BIT(finished_tags, tmpslot); 1359 } 1360 1361 ASSERT(finished_tags == 0); 1362 1363 /* Send up failed_tags with SATA_PKT_DEV_ERROR. */ 1364 while (failed_tags) { 1365 tmpslot = ddi_ffs(failed_tags) - 1; 1366 if (tmpslot == -1) { 1367 break; 1368 } 1369 SIDBG1(SIDBG_ERRS, si_ctlp, "si3124: si_mop_commands: " 1370 "handling failed slot: 0x%x", tmpslot); 1371 1372 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1373 ASSERT(satapkt != NULL); 1374 if (satapkt->satapkt_device.satadev_type == 1375 SATA_DTYPE_ATAPICD) { 1376 si_set_sense_data(satapkt, SATA_PKT_DEV_ERROR); 1377 } 1378 1379 /* 1380 * The LRAM contains the the modified FIS. 1381 * Read the modified FIS to obtain the Error & Status. 1382 */ 1383 prb = &(si_portp->siport_prbpool[tmpslot]); 1384 prb_word_ptr = (uint32_t *)prb; 1385 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 1386 prb_word_ptr[i] = ddi_get32( 1387 si_ctlp->sictl_port_acc_handle, 1388 (uint32_t *)(PORT_LRAM(si_ctlp, port, 1389 tmpslot)+i*4)); 1390 } 1391 1392 satapkt->satapkt_cmd.satacmd_status_reg = 1393 GET_FIS_COMMAND(prb->prb_fis); 1394 satapkt->satapkt_cmd.satacmd_error_reg = 1395 GET_FIS_FEATURES(prb->prb_fis); 1396 satapkt->satapkt_cmd.satacmd_sec_count_lsb = 1397 GET_FIS_SECTOR_COUNT(prb->prb_fis); 1398 satapkt->satapkt_cmd.satacmd_lba_low_lsb = 1399 GET_FIS_SECTOR(prb->prb_fis); 1400 satapkt->satapkt_cmd.satacmd_lba_mid_lsb = 1401 GET_FIS_CYL_LOW(prb->prb_fis); 1402 satapkt->satapkt_cmd.satacmd_lba_high_lsb = 1403 GET_FIS_CYL_HI(prb->prb_fis); 1404 satapkt->satapkt_cmd.satacmd_device_reg = 1405 GET_FIS_DEV_HEAD(prb->prb_fis); 1406 1407 if (satapkt->satapkt_cmd.satacmd_addr_type == ATA_ADDR_LBA48) { 1408 satapkt->satapkt_cmd.satacmd_sec_count_msb = 1409 GET_FIS_SECTOR_COUNT_EXP(prb->prb_fis); 1410 satapkt->satapkt_cmd.satacmd_lba_low_msb = 1411 GET_FIS_SECTOR_EXP(prb->prb_fis); 1412 satapkt->satapkt_cmd.satacmd_lba_mid_msb = 1413 GET_FIS_CYL_LOW_EXP(prb->prb_fis); 1414 satapkt->satapkt_cmd.satacmd_lba_high_msb = 1415 GET_FIS_CYL_HI_EXP(prb->prb_fis); 1416 } 1417 1418 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 1419 si_copy_out_regs(&satapkt->satapkt_cmd, &prb->prb_fis); 1420 1421 /* 1422 * In the case of NCQ command failures, the error is 1423 * overwritten by the one obtained from issuing of a 1424 * READ LOG EXTENDED command. 1425 */ 1426 if (si_portp->siport_err_tags_SDBERROR & (1 << tmpslot)) { 1427 satapkt->satapkt_cmd.satacmd_error_reg = 1428 si_read_log_ext(si_ctlp, si_portp, port); 1429 } 1430 1431 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_DEV_ERROR); 1432 1433 CLEAR_BIT(failed_tags, tmpslot); 1434 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1435 } 1436 1437 ASSERT(failed_tags == 0); 1438 1439 /* Send up timedout_tags with SATA_PKT_TIMEOUT. */ 1440 while (timedout_tags) { 1441 tmpslot = ddi_ffs(timedout_tags) - 1; 1442 if (tmpslot == -1) { 1443 break; 1444 } 1445 1446 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1447 ASSERT(satapkt != NULL); 1448 SIDBG1(SIDBG_ERRS, si_ctlp, 1449 "si_mop_commands sending " 1450 "spkt up with PKT_TIMEOUT: %x", 1451 satapkt); 1452 1453 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_TIMEOUT); 1454 1455 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1456 CLEAR_BIT(timedout_tags, tmpslot); 1457 } 1458 1459 ASSERT(timedout_tags == 0); 1460 1461 /* Send up aborting packets with SATA_PKT_ABORTED. */ 1462 while (aborting_tags) { 1463 tmpslot = ddi_ffs(unfinished_tags) - 1; 1464 if (tmpslot == -1) { 1465 break; 1466 } 1467 1468 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1469 ASSERT(satapkt != NULL); 1470 SIDBG1(SIDBG_ERRS, si_ctlp, 1471 "si_mop_commands aborting spkt: %x", 1472 satapkt); 1473 if (satapkt->satapkt_device.satadev_type == 1474 SATA_DTYPE_ATAPICD) { 1475 si_set_sense_data(satapkt, SATA_PKT_ABORTED); 1476 } 1477 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_ABORTED); 1478 1479 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1480 CLEAR_BIT(aborting_tags, tmpslot); 1481 1482 } 1483 1484 ASSERT(aborting_tags == 0); 1485 1486 /* Reset tags are sent up to framework with SATA_PKT_RESET. */ 1487 while (reset_tags) { 1488 tmpslot = ddi_ffs(reset_tags) - 1; 1489 if (tmpslot == -1) { 1490 break; 1491 } 1492 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1493 ASSERT(satapkt != NULL); 1494 SIDBG1(SIDBG_ERRS, si_ctlp, 1495 "si_mop_commands sending PKT_RESET for " 1496 "reset spkt: %x", 1497 satapkt); 1498 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_RESET); 1499 1500 CLEAR_BIT(reset_tags, tmpslot); 1501 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1502 } 1503 1504 ASSERT(reset_tags == 0); 1505 1506 /* Send up the unfinished_tags with SATA_PKT_BUSY. */ 1507 while (unfinished_tags) { 1508 tmpslot = ddi_ffs(unfinished_tags) - 1; 1509 if (tmpslot == -1) { 1510 break; 1511 } 1512 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1513 ASSERT(satapkt != NULL); 1514 SIDBG1(SIDBG_ERRS, si_ctlp, 1515 "si_mop_commands sending PKT_BUSY for " 1516 "retry spkt: %x", 1517 satapkt); 1518 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_BUSY); 1519 1520 CLEAR_BIT(unfinished_tags, tmpslot); 1521 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1522 } 1523 1524 ASSERT(unfinished_tags == 0); 1525 1526 si_portp->mopping_in_progress = 0; 1527 1528 mutex_exit(&si_portp->siport_mutex); 1529 mutex_exit(&si_portp->siport_mop_mutex); 1530 1531 } 1532 1533 /* 1534 * Called by the sata framework to abort the previously sent packet(s). 1535 * 1536 * We reset the device and mop the commands on the port. 1537 */ 1538 static int 1539 si_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1540 { 1541 uint32_t slot_status; 1542 uint8_t port; 1543 int tmpslot; 1544 uint32_t aborting_tags; 1545 uint32_t finished_tags; 1546 si_port_state_t *si_portp; 1547 si_ctl_state_t *si_ctlp; 1548 1549 port = spkt->satapkt_device.satadev_addr.cport; 1550 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1551 mutex_enter(&si_ctlp->sictl_mutex); 1552 si_portp = si_ctlp->sictl_ports[port]; 1553 mutex_exit(&si_ctlp->sictl_mutex); 1554 1555 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_tran_abort on port: %x", port); 1556 1557 mutex_enter(&si_portp->siport_mutex); 1558 1559 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1560 !si_portp->siport_active) { 1561 /* 1562 * si_intr_phy_ready_change() may have rendered it to 1563 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1564 * it inactive. 1565 */ 1566 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1567 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1568 mutex_exit(&si_portp->siport_mutex); 1569 return (SATA_FAILURE); 1570 } 1571 1572 if (flag == SATA_ABORT_ALL_PACKETS) { 1573 aborting_tags = si_portp->siport_pending_tags; 1574 } else { 1575 /* 1576 * Need to abort a single packet. 1577 * Search our siport_slot_pkts[] list for matching spkt. 1578 */ 1579 aborting_tags = 0xffffffff; /* 0xffffffff is impossible tag */ 1580 for (tmpslot = 0; tmpslot < SI_NUM_SLOTS; tmpslot++) { 1581 if (si_portp->siport_slot_pkts[tmpslot] == spkt) { 1582 aborting_tags = (0x1 << tmpslot); 1583 break; 1584 } 1585 } 1586 1587 if (aborting_tags == 0xffffffff) { 1588 /* requested packet is not on pending list. */ 1589 fill_dev_sregisters(si_ctlp, port, 1590 &spkt->satapkt_device); 1591 mutex_exit(&si_portp->siport_mutex); 1592 return (SATA_FAILURE); 1593 } 1594 } 1595 1596 1597 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1598 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1599 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, 1600 port, SI_DEVICE_RESET); 1601 1602 /* 1603 * Compute which have finished and which need to be retried. 1604 * 1605 * The finished tags are siport_pending_tags minus the slot_status. 1606 * The aborting_tags have to be reduced by finished_tags since we 1607 * can't possibly abort a tag which had finished already. 1608 */ 1609 finished_tags = si_portp->siport_pending_tags & 1610 ~slot_status & SI_SLOT_MASK; 1611 aborting_tags &= ~finished_tags; 1612 1613 mutex_exit(&si_portp->siport_mutex); 1614 si_mop_commands(si_ctlp, 1615 si_portp, 1616 port, 1617 slot_status, 1618 0, /* failed_tags */ 1619 0, /* timedout_tags */ 1620 aborting_tags, 1621 0); /* reset_tags */ 1622 mutex_enter(&si_portp->siport_mutex); 1623 1624 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1625 mutex_exit(&si_portp->siport_mutex); 1626 return (SATA_SUCCESS); 1627 } 1628 1629 1630 /* 1631 * Used to reject all the pending packets on a port during a reset 1632 * operation. 1633 * 1634 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 1635 * before calling us. 1636 */ 1637 static void 1638 si_reject_all_reset_pkts( 1639 si_ctl_state_t *si_ctlp, 1640 si_port_state_t *si_portp, 1641 int port) 1642 { 1643 uint32_t slot_status; 1644 uint32_t reset_tags; 1645 1646 _NOTE(ASSUMING_PROTECTED(si_portp)) 1647 1648 SIDBG1(SIDBG_ENTRY, si_ctlp, 1649 "si_reject_all_reset_pkts on port: %x", 1650 port); 1651 1652 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1653 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1654 1655 /* Compute which tags need to be sent up. */ 1656 reset_tags = slot_status & SI_SLOT_MASK; 1657 1658 mutex_exit(&si_portp->siport_mutex); 1659 si_mop_commands(si_ctlp, 1660 si_portp, 1661 port, 1662 slot_status, 1663 0, /* failed_tags */ 1664 0, /* timedout_tags */ 1665 0, /* aborting_tags */ 1666 reset_tags); 1667 mutex_enter(&si_portp->siport_mutex); 1668 1669 } 1670 1671 1672 /* 1673 * Called by sata framework to reset a port(s) or device. 1674 * 1675 */ 1676 static int 1677 si_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 1678 { 1679 si_ctl_state_t *si_ctlp; 1680 uint8_t port = sd->satadev_addr.cport; 1681 int i; 1682 si_port_state_t *si_portp; 1683 int retval = SI_SUCCESS; 1684 1685 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1686 SIDBG1(SIDBG_ENTRY, si_ctlp, 1687 "si_tran_reset_port entry: port: 0x%x", 1688 port); 1689 1690 switch (sd->satadev_addr.qual) { 1691 case SATA_ADDR_CPORT: 1692 mutex_enter(&si_ctlp->sictl_mutex); 1693 si_portp = si_ctlp->sictl_ports[port]; 1694 mutex_exit(&si_ctlp->sictl_mutex); 1695 1696 mutex_enter(&si_portp->siport_mutex); 1697 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1698 SI_PORT_RESET); 1699 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1700 mutex_exit(&si_portp->siport_mutex); 1701 1702 break; 1703 1704 case SATA_ADDR_DCPORT: 1705 mutex_enter(&si_ctlp->sictl_mutex); 1706 si_portp = si_ctlp->sictl_ports[port]; 1707 mutex_exit(&si_ctlp->sictl_mutex); 1708 1709 mutex_enter(&si_portp->siport_mutex); 1710 1711 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1712 !si_portp->siport_active) { 1713 mutex_exit(&si_portp->siport_mutex); 1714 retval = SI_FAILURE; 1715 break; 1716 } 1717 1718 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1719 SI_DEVICE_RESET); 1720 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1721 mutex_exit(&si_portp->siport_mutex); 1722 1723 break; 1724 1725 case SATA_ADDR_CNTRL: 1726 for (i = 0; i < si_ctlp->sictl_num_ports; i++) { 1727 mutex_enter(&si_ctlp->sictl_mutex); 1728 si_portp = si_ctlp->sictl_ports[port]; 1729 mutex_exit(&si_ctlp->sictl_mutex); 1730 1731 mutex_enter(&si_portp->siport_mutex); 1732 retval = si_reset_dport_wait_till_ready(si_ctlp, 1733 si_portp, i, SI_PORT_RESET); 1734 if (retval) { 1735 mutex_exit(&si_portp->siport_mutex); 1736 break; 1737 } 1738 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1739 mutex_exit(&si_portp->siport_mutex); 1740 } 1741 break; 1742 1743 case SATA_ADDR_PMPORT: 1744 case SATA_ADDR_DPMPORT: 1745 SIDBG0(SIDBG_VERBOSE, si_ctlp, 1746 "port mult reset not implemented yet"); 1747 /* FALLSTHROUGH */ 1748 1749 default: 1750 retval = SI_FAILURE; 1751 1752 } 1753 1754 return (retval); 1755 } 1756 1757 1758 /* 1759 * Called by sata framework to activate a port as part of hotplug. 1760 * 1761 * Note: Not port-mult aware. 1762 */ 1763 static int 1764 si_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 1765 { 1766 si_ctl_state_t *si_ctlp; 1767 si_port_state_t *si_portp; 1768 uint8_t port; 1769 1770 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1771 port = satadev->satadev_addr.cport; 1772 mutex_enter(&si_ctlp->sictl_mutex); 1773 si_portp = si_ctlp->sictl_ports[port]; 1774 mutex_exit(&si_ctlp->sictl_mutex); 1775 1776 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_tran_hotplug_port_activate entry"); 1777 1778 mutex_enter(&si_portp->siport_mutex); 1779 si_enable_port_interrupts(si_ctlp, port); 1780 1781 /* 1782 * Reset the device so that a si_find_dev_signature() would trigger. 1783 * But this reset is an internal operation; the sata framework does 1784 * not need to know about it. 1785 */ 1786 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1787 SI_DEVICE_RESET|SI_RESET_NO_EVENTS_UP); 1788 1789 satadev->satadev_state = SATA_STATE_READY; 1790 1791 si_portp->siport_active = PORT_ACTIVE; 1792 1793 fill_dev_sregisters(si_ctlp, port, satadev); 1794 1795 mutex_exit(&si_portp->siport_mutex); 1796 return (SATA_SUCCESS); 1797 } 1798 1799 /* 1800 * Called by sata framework to deactivate a port as part of hotplug. 1801 * 1802 * Note: Not port-mult aware. 1803 */ 1804 static int 1805 si_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 1806 { 1807 si_ctl_state_t *si_ctlp; 1808 si_port_state_t *si_portp; 1809 uint8_t port; 1810 1811 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1812 port = satadev->satadev_addr.cport; 1813 mutex_enter(&si_ctlp->sictl_mutex); 1814 si_portp = si_ctlp->sictl_ports[port]; 1815 mutex_exit(&si_ctlp->sictl_mutex); 1816 1817 SIDBG0(SIDBG_ENTRY, NULL, "si_tran_hotplug_port_deactivate entry"); 1818 1819 mutex_enter(&si_portp->siport_mutex); 1820 if (si_portp->siport_pending_tags & SI_SLOT_MASK) { 1821 /* 1822 * There are pending commands on this port. 1823 * Fail the deactivate request. 1824 */ 1825 satadev->satadev_state = SATA_STATE_READY; 1826 mutex_exit(&si_portp->siport_mutex); 1827 return (SATA_FAILURE); 1828 } 1829 1830 /* mark the device as not accessible any more. */ 1831 si_portp->siport_active = PORT_INACTIVE; 1832 1833 /* disable the interrupts on the port. */ 1834 si_disable_port_interrupts(si_ctlp, port); 1835 1836 satadev->satadev_state = SATA_PSTATE_SHUTDOWN; 1837 1838 fill_dev_sregisters(si_ctlp, port, satadev); 1839 /* 1840 * Since we are implementing the port deactivation in software only, 1841 * we need to fake a valid value for sstatus. 1842 */ 1843 SSTATUS_SET_DET(satadev->satadev_scr.sstatus, SSTATUS_DET_PHYOFFLINE); 1844 SSTATUS_SET_IPM(satadev->satadev_scr.sstatus, SSTATUS_IPM_NODEV_NOPHY); 1845 1846 mutex_exit(&si_portp->siport_mutex); 1847 return (SATA_SUCCESS); 1848 } 1849 1850 1851 /* 1852 * Allocates the si_port_state_t. 1853 */ 1854 static int 1855 si_alloc_port_state(si_ctl_state_t *si_ctlp, int port) 1856 { 1857 si_port_state_t *si_portp; 1858 1859 si_ctlp->sictl_ports[port] = (si_port_state_t *)kmem_zalloc( 1860 sizeof (si_port_state_t), KM_SLEEP); 1861 1862 si_portp = si_ctlp->sictl_ports[port]; 1863 mutex_init(&si_portp->siport_mutex, NULL, MUTEX_DRIVER, 1864 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 1865 mutex_init(&si_portp->siport_mop_mutex, NULL, MUTEX_DRIVER, 1866 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 1867 mutex_enter(&si_portp->siport_mutex); 1868 1869 /* allocate prb & sgt pkts for this port. */ 1870 if (si_alloc_prbpool(si_ctlp, port)) { 1871 mutex_exit(&si_portp->siport_mutex); 1872 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1873 return (SI_FAILURE); 1874 } 1875 if (si_alloc_sgbpool(si_ctlp, port)) { 1876 si_dealloc_prbpool(si_ctlp, port); 1877 mutex_exit(&si_portp->siport_mutex); 1878 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1879 return (SI_FAILURE); 1880 } 1881 1882 si_portp->siport_active = PORT_ACTIVE; 1883 mutex_exit(&si_portp->siport_mutex); 1884 1885 return (SI_SUCCESS); 1886 1887 } 1888 1889 /* 1890 * Deallocates the si_port_state_t. 1891 */ 1892 static void 1893 si_dealloc_port_state(si_ctl_state_t *si_ctlp, int port) 1894 { 1895 si_port_state_t *si_portp; 1896 si_portp = si_ctlp->sictl_ports[port]; 1897 1898 mutex_enter(&si_portp->siport_mutex); 1899 si_dealloc_sgbpool(si_ctlp, port); 1900 si_dealloc_prbpool(si_ctlp, port); 1901 mutex_exit(&si_portp->siport_mutex); 1902 1903 mutex_destroy(&si_portp->siport_mutex); 1904 mutex_destroy(&si_portp->siport_mop_mutex); 1905 1906 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1907 1908 } 1909 1910 /* 1911 * Allocates the SGB (Scatter Gather Block) incore buffer. 1912 */ 1913 static int 1914 si_alloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1915 { 1916 si_port_state_t *si_portp; 1917 uint_t cookie_count; 1918 size_t incore_sgbpool_size = SI_NUM_SLOTS * sizeof (si_sgblock_t); 1919 size_t ret_len; 1920 ddi_dma_cookie_t sgbpool_dma_cookie; 1921 1922 si_portp = si_ctlp->sictl_ports[port]; 1923 1924 /* allocate sgbpool dma handle. */ 1925 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 1926 &prb_sgt_dma_attr, 1927 DDI_DMA_SLEEP, 1928 NULL, 1929 &si_portp->siport_sgbpool_dma_handle) != 1930 DDI_SUCCESS) { 1931 1932 return (SI_FAILURE); 1933 } 1934 1935 /* allocate the memory for sgbpool. */ 1936 if (ddi_dma_mem_alloc(si_portp->siport_sgbpool_dma_handle, 1937 incore_sgbpool_size, 1938 &accattr, 1939 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1940 DDI_DMA_SLEEP, 1941 NULL, 1942 (caddr_t *)&si_portp->siport_sgbpool, 1943 &ret_len, 1944 &si_portp->siport_sgbpool_acc_handle) != NULL) { 1945 1946 /* error.. free the dma handle. */ 1947 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1948 return (SI_FAILURE); 1949 } 1950 1951 /* now bind it */ 1952 if (ddi_dma_addr_bind_handle(si_portp->siport_sgbpool_dma_handle, 1953 NULL, 1954 (caddr_t)si_portp->siport_sgbpool, 1955 incore_sgbpool_size, 1956 DDI_DMA_CONSISTENT, 1957 DDI_DMA_SLEEP, 1958 NULL, 1959 &sgbpool_dma_cookie, 1960 &cookie_count) != DDI_DMA_MAPPED) { 1961 /* error.. free the dma handle & free the memory. */ 1962 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1963 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1964 return (SI_FAILURE); 1965 } 1966 1967 si_portp->siport_sgbpool_physaddr = sgbpool_dma_cookie.dmac_laddress; 1968 return (SI_SUCCESS); 1969 } 1970 1971 /* 1972 * Deallocates the SGB (Scatter Gather Block) incore buffer. 1973 */ 1974 static void 1975 si_dealloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1976 { 1977 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 1978 1979 /* Unbind the dma handle first. */ 1980 (void) ddi_dma_unbind_handle(si_portp->siport_sgbpool_dma_handle); 1981 1982 /* Then free the underlying memory. */ 1983 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1984 1985 /* Now free the handle itself. */ 1986 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1987 1988 } 1989 1990 /* 1991 * Allocates the PRB (Port Request Block) incore packets. 1992 */ 1993 static int 1994 si_alloc_prbpool(si_ctl_state_t *si_ctlp, int port) 1995 { 1996 si_port_state_t *si_portp; 1997 uint_t cookie_count; 1998 size_t incore_pkt_size = SI_NUM_SLOTS * sizeof (si_prb_t); 1999 size_t ret_len; 2000 ddi_dma_cookie_t prbpool_dma_cookie; 2001 2002 si_portp = si_ctlp->sictl_ports[port]; 2003 2004 /* allocate prb pkts. */ 2005 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 2006 &prb_sgt_dma_attr, 2007 DDI_DMA_SLEEP, 2008 NULL, 2009 &si_portp->siport_prbpool_dma_handle) != 2010 DDI_SUCCESS) { 2011 2012 return (SI_FAILURE); 2013 } 2014 2015 if (ddi_dma_mem_alloc(si_portp->siport_prbpool_dma_handle, 2016 incore_pkt_size, 2017 &accattr, 2018 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2019 DDI_DMA_SLEEP, 2020 NULL, 2021 (caddr_t *)&si_portp->siport_prbpool, 2022 &ret_len, 2023 &si_portp->siport_prbpool_acc_handle) != NULL) { 2024 2025 /* error.. free the dma handle. */ 2026 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2027 return (SI_FAILURE); 2028 } 2029 2030 if (ddi_dma_addr_bind_handle(si_portp->siport_prbpool_dma_handle, 2031 NULL, 2032 (caddr_t)si_portp->siport_prbpool, 2033 incore_pkt_size, 2034 DDI_DMA_CONSISTENT, 2035 DDI_DMA_SLEEP, 2036 NULL, 2037 &prbpool_dma_cookie, 2038 &cookie_count) != DDI_DMA_MAPPED) { 2039 /* error.. free the dma handle & free the memory. */ 2040 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2041 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2042 return (SI_FAILURE); 2043 } 2044 2045 si_portp->siport_prbpool_physaddr = 2046 prbpool_dma_cookie.dmac_laddress; 2047 return (SI_SUCCESS); 2048 } 2049 2050 /* 2051 * Deallocates the PRB (Port Request Block) incore packets. 2052 */ 2053 static void 2054 si_dealloc_prbpool(si_ctl_state_t *si_ctlp, int port) 2055 { 2056 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 2057 2058 /* Unbind the prb dma handle first. */ 2059 (void) ddi_dma_unbind_handle(si_portp->siport_prbpool_dma_handle); 2060 2061 /* Then free the underlying memory. */ 2062 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2063 2064 /* Now free the handle itself. */ 2065 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2066 2067 } 2068 2069 2070 2071 /* 2072 * Soft-reset the port to find the signature of the device connected to 2073 * the port. 2074 */ 2075 static void 2076 si_find_dev_signature( 2077 si_ctl_state_t *si_ctlp, 2078 si_port_state_t *si_portp, 2079 int port, 2080 int pmp) 2081 { 2082 si_prb_t *prb; 2083 uint32_t slot_status, signature; 2084 int slot, loop_count; 2085 2086 SIDBG2(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 2087 "si_find_dev_signature enter: port: %x, pmp: %x", 2088 port, pmp); 2089 2090 /* Build a Soft Reset PRB in host memory. */ 2091 mutex_enter(&si_portp->siport_mutex); 2092 2093 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2094 if (slot == -1) { 2095 /* Empty slot could not be found. */ 2096 if (pmp != PORTMULT_CONTROL_PORT) { 2097 /* We are behind port multiplier. */ 2098 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2099 PORT_TYPE_NODEV; 2100 } else { 2101 si_portp->siport_port_type = PORT_TYPE_NODEV; 2102 } 2103 2104 mutex_exit(&si_portp->siport_mutex); 2105 return; 2106 } 2107 prb = &si_portp->siport_prbpool[slot]; 2108 bzero((void *)prb, sizeof (si_prb_t)); 2109 2110 SET_FIS_PMP(prb->prb_fis, pmp); 2111 SET_PRB_CONTROL_SOFT_RESET(prb); 2112 2113 #if SI_DEBUG 2114 if (si_debug_flags & SIDBG_DUMP_PRB) { 2115 char *ptr; 2116 int j; 2117 2118 ptr = (char *)prb; 2119 cmn_err(CE_WARN, "si_find_dev_signature, prb: "); 2120 for (j = 0; j < (sizeof (si_prb_t)); j++) { 2121 if (j%4 == 0) { 2122 cmn_err(CE_WARN, "----"); 2123 } 2124 cmn_err(CE_WARN, "%x ", ptr[j]); 2125 } 2126 2127 } 2128 #endif /* SI_DEBUG */ 2129 2130 /* deliver soft reset prb to empty slot. */ 2131 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2132 2133 loop_count = 0; 2134 /* Loop till the soft reset is finished. */ 2135 do { 2136 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2137 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2138 2139 if (loop_count++ > SI_POLLRATE_SOFT_RESET) { 2140 /* We are effectively timing out after 10 sec. */ 2141 break; 2142 } 2143 2144 /* Wait for 10 millisec */ 2145 #ifndef __lock_lint 2146 delay(SI_10MS_TICKS); 2147 #endif /* __lock_lint */ 2148 2149 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 2150 2151 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 2152 "si_find_dev_signature: loop count: %d, slot_status: 0x%x", 2153 loop_count, slot_status); 2154 2155 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2156 2157 /* Read device signature from command slot. */ 2158 signature = ddi_get32(si_ctlp->sictl_port_acc_handle, 2159 (uint32_t *)(PORT_SIGNATURE_MSB(si_ctlp, port, slot))); 2160 signature <<= 8; 2161 signature |= (0xff & ddi_get32(si_ctlp->sictl_port_acc_handle, 2162 (uint32_t *)(PORT_SIGNATURE_LSB(si_ctlp, 2163 port, slot)))); 2164 2165 SIDBG1(SIDBG_INIT, si_ctlp, "Device signature: 0x%x", signature); 2166 2167 if (signature == SI_SIGNATURE_PORT_MULTIPLIER) { 2168 2169 SIDBG2(SIDBG_INIT, si_ctlp, 2170 "Found multiplier at cport: 0x%d, pmport: 0x%x", 2171 port, pmp); 2172 2173 if (pmp != PORTMULT_CONTROL_PORT) { 2174 /* 2175 * It is wrong to chain a port multiplier behind 2176 * another port multiplier. 2177 */ 2178 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2179 PORT_TYPE_NODEV; 2180 } else { 2181 si_portp->siport_port_type = PORT_TYPE_MULTIPLIER; 2182 mutex_exit(&si_portp->siport_mutex); 2183 (void) si_enumerate_port_multiplier(si_ctlp, 2184 si_portp, port); 2185 mutex_enter(&si_portp->siport_mutex); 2186 } 2187 si_init_port(si_ctlp, port); 2188 2189 } else if (signature == SI_SIGNATURE_ATAPI) { 2190 if (pmp != PORTMULT_CONTROL_PORT) { 2191 /* We are behind port multiplier. */ 2192 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2193 PORT_TYPE_ATAPI; 2194 } else { 2195 si_portp->siport_port_type = PORT_TYPE_ATAPI; 2196 si_init_port(si_ctlp, port); 2197 } 2198 SIDBG2(SIDBG_INIT, si_ctlp, 2199 "Found atapi at : cport: %x, pmport: %x", 2200 port, pmp); 2201 2202 } else if (signature == SI_SIGNATURE_DISK) { 2203 2204 if (pmp != PORTMULT_CONTROL_PORT) { 2205 /* We are behind port multiplier. */ 2206 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2207 PORT_TYPE_DISK; 2208 } else { 2209 si_portp->siport_port_type = PORT_TYPE_DISK; 2210 si_init_port(si_ctlp, port); 2211 } 2212 SIDBG2(SIDBG_INIT, si_ctlp, 2213 "found disk at : cport: %x, pmport: %x", 2214 port, pmp); 2215 2216 } else { 2217 if (pmp != PORTMULT_CONTROL_PORT) { 2218 /* We are behind port multiplier. */ 2219 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2220 PORT_TYPE_UNKNOWN; 2221 } else { 2222 si_portp->siport_port_type = PORT_TYPE_UNKNOWN; 2223 } 2224 SIDBG3(SIDBG_INIT, si_ctlp, 2225 "Found unknown signature 0x%x at: port: %x, pmp: %x", 2226 signature, port, pmp); 2227 } 2228 2229 mutex_exit(&si_portp->siport_mutex); 2230 } 2231 2232 2233 /* 2234 * Polls for the completion of the command. This is safe with both 2235 * interrupts enabled or disabled. 2236 */ 2237 static void 2238 si_poll_cmd( 2239 si_ctl_state_t *si_ctlp, 2240 si_port_state_t *si_portp, 2241 int port, 2242 int slot, 2243 sata_pkt_t *satapkt) 2244 { 2245 uint32_t slot_status; 2246 int pkt_timeout_ticks; 2247 uint32_t port_intr_status; 2248 int in_panic = ddi_in_panic(); 2249 2250 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_poll_cmd entered: port: 0x%x", port); 2251 2252 pkt_timeout_ticks = drv_usectohz((clock_t)satapkt->satapkt_time * 2253 1000000); 2254 2255 mutex_enter(&si_portp->siport_mutex); 2256 2257 /* we start out with SATA_PKT_COMPLETED as the satapkt_reason */ 2258 satapkt->satapkt_reason = SATA_PKT_COMPLETED; 2259 2260 do { 2261 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2262 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2263 2264 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2265 if (in_panic) { 2266 /* 2267 * If we are in panic, we can't rely on 2268 * timers; so, busy wait instead of delay(). 2269 */ 2270 mutex_exit(&si_portp->siport_mutex); 2271 drv_usecwait(SI_1MS_USECS); 2272 mutex_enter(&si_portp->siport_mutex); 2273 } else { 2274 mutex_exit(&si_portp->siport_mutex); 2275 #ifndef __lock_lint 2276 delay(SI_1MS_TICKS); 2277 #endif /* __lock_lint */ 2278 mutex_enter(&si_portp->siport_mutex); 2279 } 2280 } else { 2281 break; 2282 } 2283 2284 pkt_timeout_ticks -= SI_1MS_TICKS; 2285 2286 } while (pkt_timeout_ticks > 0); 2287 2288 if (satapkt->satapkt_reason != SATA_PKT_COMPLETED) { 2289 /* The si_mop_command() got to our packet before us */ 2290 goto poll_done; 2291 } 2292 2293 /* 2294 * Interrupts and timers may not be working properly in a crash dump 2295 * situation; we may need to handle all the three conditions here: 2296 * successful completion, packet failure and packet timeout. 2297 */ 2298 if (IS_ATTENTION_RAISED(slot_status)) { /* error seen on port */ 2299 2300 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 2301 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 2302 2303 SIDBG2(SIDBG_VERBOSE, si_ctlp, 2304 "si_poll_cmd: port_intr_status: 0x%x, port: %x", 2305 port_intr_status, port); 2306 2307 if (port_intr_status & INTR_COMMAND_ERROR) { 2308 mutex_exit(&si_portp->siport_mutex); 2309 (void) si_intr_command_error(si_ctlp, si_portp, port); 2310 mutex_enter(&si_portp->siport_mutex); 2311 2312 goto poll_done; 2313 2314 /* 2315 * Why do we need to call si_intr_command_error() ? 2316 * 2317 * Answer: Even if the current packet is not the 2318 * offending command, we need to restart the stalled 2319 * port; (may be, the interrupts are not working well 2320 * in panic condition). The call to routine 2321 * si_intr_command_error() will achieve that. 2322 * 2323 * What if the interrupts are working fine and the 2324 * si_intr_command_error() gets called once more from 2325 * interrupt context ? 2326 * 2327 * Answer: The second instance of routine 2328 * si_intr_command_error() will not mop anything 2329 * since the first error handler has already blown 2330 * away the hardware pending queues through reset. 2331 * 2332 * Will the si_intr_command_error() hurt current 2333 * packet ? 2334 * 2335 * Answer: No. 2336 */ 2337 } else { 2338 /* Ignore any non-error interrupts at this stage */ 2339 ddi_put32(si_ctlp->sictl_port_acc_handle, 2340 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, 2341 port)), 2342 port_intr_status & INTR_MASK); 2343 } 2344 2345 2346 } else if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2347 satapkt->satapkt_reason = SATA_PKT_TIMEOUT; 2348 } /* else: the command completed successfully */ 2349 2350 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == 2351 SATAC_WRITE_FPDMA_QUEUED) || 2352 (satapkt->satapkt_cmd.satacmd_cmd_reg == 2353 SATAC_READ_FPDMA_QUEUED)) { 2354 si_portp->siport_pending_ncq_count--; 2355 } 2356 2357 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2358 2359 poll_done: 2360 mutex_exit(&si_portp->siport_mutex); 2361 2362 /* 2363 * tidbit: What is the interaction of abort with polling ? 2364 * What happens if the current polled pkt is aborted in parallel ? 2365 * 2366 * Answer: Assuming that the si_mop_commands() completes ahead 2367 * of polling, all it does is to set the satapkt_reason to 2368 * SPKT_PKT_ABORTED. That would be fine with us. 2369 * 2370 * The same logic applies to reset interacting with polling. 2371 */ 2372 } 2373 2374 2375 /* 2376 * Searches for and claims a free slot. 2377 * 2378 * Returns: SI_FAILURE if no slots found 2379 * claimed slot number if successful 2380 * 2381 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2382 * before calling us. 2383 */ 2384 /*ARGSUSED*/ 2385 static int 2386 si_claim_free_slot(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 2387 { 2388 uint32_t free_slots; 2389 int slot; 2390 2391 _NOTE(ASSUMING_PROTECTED(si_portp)) 2392 2393 SIDBG1(SIDBG_ENTRY, si_ctlp, 2394 "si_claim_free_slot entry: siport_pending_tags: %x", 2395 si_portp->siport_pending_tags); 2396 2397 free_slots = (~si_portp->siport_pending_tags) & SI_SLOT_MASK; 2398 slot = ddi_ffs(free_slots) - 1; 2399 if (slot == -1) { 2400 SIDBG0(SIDBG_VERBOSE, si_ctlp, 2401 "si_claim_free_slot: no empty slots"); 2402 return (SI_FAILURE); 2403 } 2404 2405 si_portp->siport_pending_tags |= (0x1 << slot); 2406 SIDBG1(SIDBG_VERBOSE, si_ctlp, "si_claim_free_slot: found slot: 0x%x", 2407 slot); 2408 return (slot); 2409 } 2410 2411 /* 2412 * Builds the PRB for the sata packet and delivers it to controller. 2413 * 2414 * Returns: 2415 * slot number if we can obtain a slot successfully 2416 * otherwise, return SI_FAILURE 2417 * 2418 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2419 * before calling us. 2420 */ 2421 static int 2422 si_deliver_satapkt( 2423 si_ctl_state_t *si_ctlp, 2424 si_port_state_t *si_portp, 2425 int port, 2426 sata_pkt_t *spkt) 2427 { 2428 int slot; 2429 si_prb_t *prb; 2430 sata_cmd_t *cmd; 2431 si_sge_t *sgep; /* scatter gather entry pointer */ 2432 si_sgt_t *sgtp; /* scatter gather table pointer */ 2433 si_sgblock_t *sgbp; /* scatter gather block pointer */ 2434 int i, j, cookie_index; 2435 int ncookies; 2436 int is_atapi = 0; 2437 ddi_dma_cookie_t cookie; 2438 2439 _NOTE(ASSUMING_PROTECTED(si_portp)) 2440 2441 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2442 if (slot == -1) { 2443 return (SI_FAILURE); 2444 } 2445 2446 if (spkt->satapkt_device.satadev_type == SATA_DTYPE_ATAPICD) { 2447 is_atapi = 1; 2448 } 2449 2450 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 2451 !si_portp->siport_active) { 2452 /* 2453 * si_intr_phy_ready_change() may have rendered it to 2454 * PORT_TYPE_NODEV. cfgadm operation may have rendered 2455 * it inactive. 2456 */ 2457 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2458 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 2459 2460 return (SI_FAILURE); 2461 } 2462 2463 2464 prb = &(si_portp->siport_prbpool[slot]); 2465 bzero((void *)prb, sizeof (si_prb_t)); 2466 2467 cmd = &spkt->satapkt_cmd; 2468 2469 SIDBG4(SIDBG_ENTRY, si_ctlp, 2470 "si_deliver_satpkt entry: cmd_reg: 0x%x, slot: 0x%x, \ 2471 port: %x, satapkt: %x", 2472 cmd->satacmd_cmd_reg, slot, port, (uint32_t)(intptr_t)spkt); 2473 2474 /* Now fill the prb. */ 2475 if (is_atapi) { 2476 if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction == 2477 SATA_DIR_READ) { 2478 SET_PRB_CONTROL_PKT_READ(prb); 2479 } else if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction 2480 == SATA_DIR_WRITE) { 2481 SET_PRB_CONTROL_PKT_WRITE(prb); 2482 } 2483 } 2484 2485 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 2486 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 2487 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 2488 SET_FIS_PMP(prb->prb_fis, 2489 spkt->satapkt_device.satadev_addr.pmport); 2490 } 2491 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 2492 SET_FIS_COMMAND(prb->prb_fis, cmd->satacmd_cmd_reg); 2493 SET_FIS_FEATURES(prb->prb_fis, cmd->satacmd_features_reg); 2494 SET_FIS_SECTOR_COUNT(prb->prb_fis, cmd->satacmd_sec_count_lsb); 2495 2496 switch (cmd->satacmd_addr_type) { 2497 2498 case ATA_ADDR_LBA: 2499 /* fallthru */ 2500 2501 case ATA_ADDR_LBA28: 2502 /* LBA[7:0] */ 2503 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2504 2505 /* LBA[15:8] */ 2506 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2507 2508 /* LBA[23:16] */ 2509 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2510 2511 /* LBA [27:24] (also called dev_head) */ 2512 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2513 2514 break; 2515 2516 case ATA_ADDR_LBA48: 2517 /* LBA[7:0] */ 2518 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2519 2520 /* LBA[15:8] */ 2521 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2522 2523 /* LBA[23:16] */ 2524 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2525 2526 /* LBA [31:24] */ 2527 SET_FIS_SECTOR_EXP(prb->prb_fis, cmd->satacmd_lba_low_msb); 2528 2529 /* LBA [39:32] */ 2530 SET_FIS_CYL_LOW_EXP(prb->prb_fis, cmd->satacmd_lba_mid_msb); 2531 2532 /* LBA [47:40] */ 2533 SET_FIS_CYL_HI_EXP(prb->prb_fis, cmd->satacmd_lba_high_msb); 2534 2535 /* Set dev_head */ 2536 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2537 2538 /* Set the extended sector count and features */ 2539 SET_FIS_SECTOR_COUNT_EXP(prb->prb_fis, 2540 cmd->satacmd_sec_count_msb); 2541 SET_FIS_FEATURES_EXP(prb->prb_fis, 2542 cmd->satacmd_features_reg_ext); 2543 2544 break; 2545 2546 } 2547 2548 if (cmd->satacmd_flags.sata_queued) { 2549 /* 2550 * For queued commands, the TAG for the sector count lsb is 2551 * generated from current slot number. 2552 */ 2553 SET_FIS_SECTOR_COUNT(prb->prb_fis, slot << 3); 2554 } 2555 2556 if ((cmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) || 2557 (cmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED)) { 2558 si_portp->siport_pending_ncq_count++; 2559 } 2560 2561 /* *** now fill the scatter gather list ******* */ 2562 2563 if (is_atapi) { /* It is an ATAPI drive */ 2564 /* atapi command goes into sge0 */ 2565 bcopy(cmd->satacmd_acdb, &prb->prb_sge0, sizeof (si_sge_t)); 2566 2567 /* Now fill sge1 with pointer to external SGT. */ 2568 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2569 prb->prb_sge1.sge_addr = 2570 si_portp->siport_sgbpool_physaddr + 2571 slot*sizeof (si_sgblock_t); 2572 SET_SGE_LNK(prb->prb_sge1); 2573 } else { 2574 SET_SGE_TRM(prb->prb_sge1); 2575 } 2576 } else { 2577 /* Fill the sge0 */ 2578 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2579 prb->prb_sge0.sge_addr = 2580 si_portp->siport_sgbpool_physaddr + 2581 slot*sizeof (si_sgblock_t); 2582 SET_SGE_LNK(prb->prb_sge0); 2583 2584 } else { 2585 SET_SGE_TRM(prb->prb_sge0); 2586 } 2587 2588 /* sge1 is left empty in non-ATAPI case */ 2589 } 2590 2591 bzero(&si_portp->siport_sgbpool[slot], sizeof (si_sgblock_t)); 2592 2593 ncookies = spkt->satapkt_cmd.satacmd_num_dma_cookies; 2594 ASSERT(ncookies <= SI_MAX_SGL_LENGTH); 2595 2596 SIDBG1(SIDBG_COOKIES, si_ctlp, "total ncookies: %d", ncookies); 2597 if (ncookies == 0) { 2598 sgbp = &si_portp->siport_sgbpool[slot]; 2599 sgtp = &sgbp->sgb_sgt[0]; 2600 sgep = &sgtp->sgt_sge[0]; 2601 2602 /* No cookies. Terminate the chain. */ 2603 SIDBG0(SIDBG_COOKIES, si_ctlp, "empty cookies: terminating."); 2604 2605 sgep->sge_addr_low = 0; 2606 sgep->sge_addr_high = 0; 2607 sgep->sge_data_count = 0; 2608 SET_SGE_TRM((*sgep)); 2609 2610 goto sgl_fill_done; 2611 } 2612 2613 for (i = 0, cookie_index = 0, sgbp = &si_portp->siport_sgbpool[slot]; 2614 i < SI_MAX_SGT_TABLES_PER_PRB; i++) { 2615 2616 sgtp = &sgbp->sgb_sgt[i]; 2617 2618 /* Now fill the first 3 entries of SGT in the loop below. */ 2619 for (j = 0, sgep = &sgtp->sgt_sge[0]; 2620 ((j < 3) && (cookie_index < ncookies-1)); 2621 j++, cookie_index++, sgep++) { 2622 ASSERT(cookie_index < ncookies); 2623 SIDBG2(SIDBG_COOKIES, si_ctlp, 2624 "inner loop: cookie_index: %d, ncookies: %d", 2625 cookie_index, 2626 ncookies); 2627 cookie = spkt->satapkt_cmd. 2628 satacmd_dma_cookie_list[cookie_index]; 2629 2630 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2631 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2632 sgep->sge_data_count = cookie.dmac_size; 2633 } 2634 2635 /* 2636 * If this happens to be the last cookie, we terminate it here. 2637 * Otherwise, we link to next SGT. 2638 */ 2639 2640 if (cookie_index == ncookies-1) { 2641 /* This is the last cookie. Terminate the chain. */ 2642 SIDBG2(SIDBG_COOKIES, si_ctlp, 2643 "filling the last: cookie_index: %d, " 2644 "ncookies: %d", 2645 cookie_index, 2646 ncookies); 2647 cookie = spkt->satapkt_cmd. 2648 satacmd_dma_cookie_list[cookie_index]; 2649 2650 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2651 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2652 sgep->sge_data_count = cookie.dmac_size; 2653 SET_SGE_TRM((*sgep)); 2654 2655 break; /* we break the loop */ 2656 2657 } else { 2658 /* This is not the last one. So link it. */ 2659 SIDBG2(SIDBG_COOKIES, si_ctlp, 2660 "linking SGT: cookie_index: %d, ncookies: %d", 2661 cookie_index, 2662 ncookies); 2663 sgep->sge_addr = si_portp->siport_sgbpool_physaddr + 2664 slot * sizeof (si_sgblock_t) + 2665 (i+1) * sizeof (si_sgt_t); 2666 2667 SET_SGE_LNK((*sgep)); 2668 } 2669 2670 } 2671 2672 /* *** finished filling the scatter gather list ******* */ 2673 2674 sgl_fill_done: 2675 /* Now remember the sata packet in siport_slot_pkts[]. */ 2676 si_portp->siport_slot_pkts[slot] = spkt; 2677 2678 /* 2679 * We are overloading satapkt_hba_driver_private with 2680 * watched_cycle count. 2681 */ 2682 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 2683 2684 if (is_atapi) { 2685 /* program the packet_lenth if it is atapi device. */ 2686 2687 2688 #ifdef ATAPI_2nd_PHASE 2689 /* 2690 * Framework needs to calculate the acdb_len based on 2691 * identify packet data. This needs to be accomplished 2692 * in second phase of the project. 2693 */ 2694 ASSERT((cmd->satacmd_acdb_len == 12) || 2695 (cmd->satacmd_acdb_len == 16)); 2696 SIDBG1(SIDBG_VERBOSE, si_ctlp, "deliver: acdb_len: %d", 2697 cmd->satacmd_acdb_len); 2698 2699 if (cmd->satacmd_acdb_len == 16) { 2700 ddi_put32(si_ctlp->sictl_port_acc_handle, 2701 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 2702 PORT_CONTROL_SET_BITS_PACKET_LEN); 2703 } else { 2704 ddi_put32(si_ctlp->sictl_port_acc_handle, 2705 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2706 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2707 } 2708 2709 #else /* ATAPI_2nd_PHASE */ 2710 /* hard coding for now to 12 bytes */ 2711 ddi_put32(si_ctlp->sictl_port_acc_handle, 2712 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2713 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2714 #endif /* ATAPI_2nd_PHASE */ 2715 } 2716 2717 2718 #if SI_DEBUG 2719 if (si_debug_flags & SIDBG_DUMP_PRB) { 2720 if (!(is_atapi && (prb->prb_sge0.sge_addr_low == 0))) { 2721 /* 2722 * Do not dump the atapi Test-Unit-Ready commands. 2723 * The sd_media_watch spews too many of these. 2724 */ 2725 int *ptr; 2726 si_sge_t *tmpsgep; 2727 int j; 2728 2729 ptr = (int *)prb; 2730 cmn_err(CE_WARN, "si_deliver_satpkt prb: "); 2731 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 2732 cmn_err(CE_WARN, "%x ", ptr[j]); 2733 } 2734 2735 cmn_err(CE_WARN, 2736 "si_deliver_satpkt sgt: low, high, count link"); 2737 for (j = 0, 2738 tmpsgep = (si_sge_t *) 2739 &si_portp->siport_sgbpool[slot]; 2740 j < (sizeof (si_sgblock_t)/ sizeof (si_sge_t)); 2741 j++, tmpsgep++) { 2742 ptr = (int *)tmpsgep; 2743 cmn_err(CE_WARN, "%x %x %x %x", 2744 ptr[0], 2745 ptr[1], 2746 ptr[2], 2747 ptr[3]); 2748 if (IS_SGE_TRM_SET((*tmpsgep))) { 2749 break; 2750 } 2751 2752 } 2753 } 2754 2755 } 2756 #endif /* SI_DEBUG */ 2757 2758 /* Deliver PRB */ 2759 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2760 2761 return (slot); 2762 } 2763 2764 /* 2765 * Initialize the controller and set up driver data structures. 2766 * 2767 * This routine can be called from three separate cases: DDI_ATTACH, PM_LEVEL_D0 2768 * and DDI_RESUME. The DDI_ATTACH case is different from other two cases; the 2769 * memory allocation & device signature probing are attempted only during 2770 * DDI_ATTACH case. In the case of PM_LEVEL_D0 & DDI_RESUME, we are starting 2771 * from a previously initialized state; so there is no need to allocate memory 2772 * or to attempt probing the device signatures. 2773 */ 2774 static int 2775 si_initialize_controller(si_ctl_state_t *si_ctlp) 2776 { 2777 uint32_t port_status; 2778 uint32_t SStatus; 2779 uint32_t SControl; 2780 int port; 2781 int loop_count = 0; 2782 si_port_state_t *si_portp; 2783 2784 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 2785 "si3124: si_initialize_controller entered"); 2786 2787 mutex_enter(&si_ctlp->sictl_mutex); 2788 2789 /* Remove the Global Reset. */ 2790 ddi_put32(si_ctlp->sictl_global_acc_handle, 2791 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 2792 GLOBAL_CONTROL_REG_BITS_CLEAR); 2793 2794 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 2795 2796 if (si_ctlp->sictl_flags & SI_ATTACH) { 2797 /* 2798 * We allocate the port state only during attach 2799 * sequence. We don't want to do it during 2800 * suspend/resume sequence. 2801 */ 2802 if (si_alloc_port_state(si_ctlp, port)) { 2803 mutex_exit(&si_ctlp->sictl_mutex); 2804 return (SI_FAILURE); 2805 } 2806 } 2807 2808 si_portp = si_ctlp->sictl_ports[port]; 2809 mutex_enter(&si_portp->siport_mutex); 2810 2811 /* Clear Port Reset. */ 2812 ddi_put32(si_ctlp->sictl_port_acc_handle, 2813 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2814 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 2815 2816 /* 2817 * Arm the interrupts for: Cmd completion, Cmd error, 2818 * Port Ready, PM Change, PhyRdyChange, Commwake, 2819 * UnrecFIS, Devxchanged, SDBNotify. 2820 */ 2821 ddi_put32(si_ctlp->sictl_port_acc_handle, 2822 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 2823 (INTR_COMMAND_COMPLETE | 2824 INTR_COMMAND_ERROR | 2825 INTR_PORT_READY | 2826 INTR_POWER_CHANGE | 2827 INTR_PHYRDY_CHANGE | 2828 INTR_COMWAKE_RECEIVED | 2829 INTR_UNRECOG_FIS | 2830 INTR_DEV_XCHANGED | 2831 INTR_SETDEVBITS_NOTIFY)); 2832 2833 /* Now enable the interrupts. */ 2834 si_enable_port_interrupts(si_ctlp, port); 2835 2836 /* 2837 * The following PHY initialization is redundant in 2838 * in x86 since the BIOS anyway does this as part of 2839 * device enumeration during the power up. But this 2840 * is a required step in sparc since there is no BIOS. 2841 * 2842 * The way to initialize the PHY is to write a 1 and then 2843 * a 0 to DET field of SControl register. 2844 */ 2845 2846 /* 2847 * Fetch the current SControl before writing the 2848 * DET part with 1 2849 */ 2850 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2851 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2852 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 2853 ddi_put32(si_ctlp->sictl_port_acc_handle, 2854 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2855 SControl); 2856 #ifndef __lock_lint 2857 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 2858 #endif /* __lock_lint */ 2859 2860 /* 2861 * Now fetch the SControl again and rewrite the 2862 * DET part with 0 2863 */ 2864 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2865 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2866 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 2867 ddi_put32(si_ctlp->sictl_port_acc_handle, 2868 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2869 SControl); 2870 2871 /* 2872 * PHY may be initialized by now. Check the DET field of 2873 * SStatus to determine if there is a device present. 2874 * 2875 * The DET field is valid only if IPM field indicates that 2876 * the interface is in active state. 2877 */ 2878 2879 loop_count = 0; 2880 do { 2881 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 2882 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 2883 2884 if (SSTATUS_GET_IPM(SStatus) != 2885 SSTATUS_IPM_INTERFACE_ACTIVE) { 2886 /* 2887 * If the interface is not active, the DET field 2888 * is considered not accurate. So we want to 2889 * continue looping. 2890 */ 2891 SSTATUS_SET_DET(SStatus, 2892 SSTATUS_DET_NODEV_NOPHY); 2893 } 2894 2895 if (loop_count++ > SI_POLLRATE_SSTATUS) { 2896 /* 2897 * We are effectively timing out after 0.1 sec. 2898 */ 2899 break; 2900 } 2901 2902 /* Wait for 10 millisec */ 2903 #ifndef __lock_lint 2904 delay(SI_10MS_TICKS); 2905 #endif /* __lock_lint */ 2906 2907 } while (SSTATUS_GET_DET(SStatus) != 2908 SSTATUS_DET_DEVPRESENT_PHYONLINE); 2909 2910 SIDBG2(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2911 "si_initialize_controller: 1st loop count: %d, " 2912 "SStatus: 0x%x", 2913 loop_count, 2914 SStatus); 2915 2916 if ((SSTATUS_GET_IPM(SStatus) != 2917 SSTATUS_IPM_INTERFACE_ACTIVE) || 2918 (SSTATUS_GET_DET(SStatus) != 2919 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 2920 /* 2921 * Either the port is not active or there 2922 * is no device present. 2923 */ 2924 si_ctlp->sictl_ports[port]->siport_port_type = 2925 PORT_TYPE_NODEV; 2926 mutex_exit(&si_portp->siport_mutex); 2927 continue; 2928 } 2929 2930 /* Wait until Port Ready */ 2931 loop_count = 0; 2932 do { 2933 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2934 (uint32_t *)PORT_STATUS(si_ctlp, port)); 2935 2936 if (loop_count++ > SI_POLLRATE_PORTREADY) { 2937 /* 2938 * We are effectively timing out after 0.5 sec. 2939 */ 2940 break; 2941 } 2942 2943 /* Wait for 10 millisec */ 2944 #ifndef __lock_lint 2945 delay(SI_10MS_TICKS); 2946 #endif /* __lock_lint */ 2947 2948 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 2949 2950 SIDBG1(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2951 "si_initialize_controller: 2nd loop count: %d", 2952 loop_count); 2953 2954 if (si_ctlp->sictl_flags & SI_ATTACH) { 2955 /* 2956 * We want to probe for dev signature only during attach 2957 * case. Don't do it during suspend/resume sequence. 2958 */ 2959 if (port_status & PORT_STATUS_BITS_PORT_READY) { 2960 mutex_exit(&si_portp->siport_mutex); 2961 si_find_dev_signature(si_ctlp, si_portp, port, 2962 PORTMULT_CONTROL_PORT); 2963 mutex_enter(&si_portp->siport_mutex); 2964 } else { 2965 si_ctlp->sictl_ports[port]->siport_port_type = 2966 PORT_TYPE_NODEV; 2967 } 2968 } 2969 2970 mutex_exit(&si_portp->siport_mutex); 2971 } 2972 2973 mutex_exit(&si_ctlp->sictl_mutex); 2974 return (SI_SUCCESS); 2975 } 2976 2977 /* 2978 * Reverse of si_initialize_controller(). 2979 * 2980 * WARNING, WARNING: The caller is expected to obtain the sictl_mutex 2981 * before calling us. 2982 */ 2983 static void 2984 si_deinititalize_controller(si_ctl_state_t *si_ctlp) 2985 { 2986 int port; 2987 2988 _NOTE(ASSUMING_PROTECTED(si_ctlp)) 2989 2990 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 2991 "si3124: si_deinititalize_controller entered"); 2992 2993 /* disable all the interrupts. */ 2994 si_disable_all_interrupts(si_ctlp); 2995 2996 if (si_ctlp->sictl_flags & SI_DETACH) { 2997 /* 2998 * We want to dealloc all the memory in detach case. 2999 */ 3000 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 3001 si_dealloc_port_state(si_ctlp, port); 3002 } 3003 } 3004 3005 } 3006 3007 /* 3008 * Prepare the port ready for usage. 3009 * 3010 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3011 * before calling us. 3012 */ 3013 static void 3014 si_init_port(si_ctl_state_t *si_ctlp, int port) 3015 { 3016 3017 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 3018 "si_init_port entered: port: 0x%x", 3019 port); 3020 3021 /* Initialize the port. */ 3022 ddi_put32(si_ctlp->sictl_port_acc_handle, 3023 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3024 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 3025 3026 /* 3027 * Clear the InterruptNCOR (Interupt No Clear on Read). 3028 * This step ensures that a mere reading of slot_status will clear 3029 * the interrupt; no explicit clearing of interrupt condition 3030 * will be needed for successful completion of commands. 3031 */ 3032 ddi_put32(si_ctlp->sictl_port_acc_handle, 3033 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3034 PORT_CONTROL_CLEAR_BITS_INTR_NCoR); 3035 3036 /* clear any pending interrupts at this point */ 3037 ddi_put32(si_ctlp->sictl_port_acc_handle, 3038 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3039 INTR_MASK); 3040 3041 } 3042 3043 3044 /* 3045 * Enumerate the devices connected to the port multiplier. 3046 * Once a device is detected, we call si_find_dev_signature() 3047 * to find the type of device connected. Even though we are 3048 * called from within si_find_dev_signature(), there is no 3049 * recursion possible. 3050 */ 3051 static int 3052 si_enumerate_port_multiplier( 3053 si_ctl_state_t *si_ctlp, 3054 si_port_state_t *si_portp, 3055 int port) 3056 { 3057 uint32_t num_dev_ports = 0; 3058 int pmport; 3059 uint32_t SControl = 0; 3060 uint32_t SStatus = 0; 3061 uint32_t SError = 0; 3062 int loop_count = 0; 3063 3064 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 3065 "si_enumerate_port_multiplier entered: port: %d", 3066 port); 3067 3068 mutex_enter(&si_portp->siport_mutex); 3069 3070 /* Enable Port Multiplier context switching. */ 3071 ddi_put32(si_ctlp->sictl_port_acc_handle, 3072 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3073 PORT_CONTROL_SET_BITS_PM_ENABLE); 3074 3075 /* 3076 * Read the num dev ports connected. 3077 * GSCR[2] contains the number of device ports. 3078 */ 3079 if (si_read_portmult_reg(si_ctlp, si_portp, port, PORTMULT_CONTROL_PORT, 3080 PSCR_REG2, &num_dev_ports)) { 3081 mutex_exit(&si_portp->siport_mutex); 3082 return (SI_FAILURE); 3083 } 3084 si_portp->siport_portmult_state.sipm_num_ports = num_dev_ports; 3085 3086 SIDBG1(SIDBG_INIT, si_ctlp, 3087 "si_enumerate_port_multiplier: ports found: %d", 3088 num_dev_ports); 3089 3090 for (pmport = 0; pmport < num_dev_ports-1; pmport++) { 3091 /* 3092 * Enable PHY by writing a 1, then a 0 to SControl 3093 * (i.e. PSCR[2]) DET field. 3094 */ 3095 if (si_read_portmult_reg(si_ctlp, si_portp, port, pmport, 3096 PSCR_REG2, &SControl)) { 3097 continue; 3098 } 3099 3100 /* First write a 1 to DET field of SControl. */ 3101 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 3102 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3103 PSCR_REG2, SControl)) { 3104 continue; 3105 } 3106 #ifndef __lock_lint 3107 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 3108 #endif /* __lock_lint */ 3109 3110 /* Then write a 0 to the DET field of SControl. */ 3111 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 3112 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3113 PSCR_REG2, SControl)) { 3114 continue; 3115 } 3116 3117 /* Wait for PHYRDY by polling SStatus (i.e. PSCR[0]). */ 3118 loop_count = 0; 3119 do { 3120 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3121 pmport, PSCR_REG0, &SStatus)) { 3122 break; 3123 } 3124 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3125 "looping for PHYRDY: SStatus: %x", 3126 SStatus); 3127 3128 if (SSTATUS_GET_IPM(SStatus) != 3129 SSTATUS_IPM_INTERFACE_ACTIVE) { 3130 /* 3131 * If the interface is not active, the DET field 3132 * is considered not accurate. So we want to 3133 * continue looping. 3134 */ 3135 SSTATUS_SET_DET(SStatus, 3136 SSTATUS_DET_NODEV_NOPHY); 3137 } 3138 3139 if (loop_count++ > SI_POLLRATE_SSTATUS) { 3140 /* 3141 * We are effectively timing out after 0.1 sec. 3142 */ 3143 break; 3144 } 3145 3146 /* Wait for 10 millisec */ 3147 #ifndef __lock_lint 3148 delay(SI_10MS_TICKS); 3149 #endif /* __lock_lint */ 3150 3151 } while (SSTATUS_GET_DET(SStatus) != 3152 SSTATUS_DET_DEVPRESENT_PHYONLINE); 3153 3154 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 3155 "si_enumerate_port_multiplier: " 3156 "loop count: %d, SStatus: 0x%x", 3157 loop_count, 3158 SStatus); 3159 3160 if ((SSTATUS_GET_IPM(SStatus) == 3161 SSTATUS_IPM_INTERFACE_ACTIVE) && 3162 (SSTATUS_GET_DET(SStatus) == 3163 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 3164 /* The interface is active and the device is present */ 3165 SIDBG1(SIDBG_INIT, si_ctlp, 3166 "Status: %x, device exists", 3167 SStatus); 3168 /* 3169 * Clear error bits in SError register (i.e. PSCR[1] 3170 * by writing back error bits. 3171 */ 3172 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3173 pmport, PSCR_REG1, &SError)) { 3174 continue; 3175 } 3176 SIDBG1(SIDBG_INIT, si_ctlp, 3177 "SError bits are: %x", SError); 3178 if (si_write_portmult_reg(si_ctlp, si_portp, port, 3179 pmport, PSCR_REG1, SError)) { 3180 continue; 3181 } 3182 3183 /* There exists a device. */ 3184 mutex_exit(&si_portp->siport_mutex); 3185 si_find_dev_signature(si_ctlp, si_portp, port, pmport); 3186 mutex_enter(&si_portp->siport_mutex); 3187 } 3188 } 3189 3190 mutex_exit(&si_portp->siport_mutex); 3191 3192 return (SI_SUCCESS); 3193 } 3194 3195 3196 /* 3197 * Read a port multiplier register. 3198 * 3199 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3200 * before calling us. 3201 */ 3202 static int 3203 si_read_portmult_reg( 3204 si_ctl_state_t *si_ctlp, 3205 si_port_state_t *si_portp, 3206 int port, 3207 int pmport, 3208 int regnum, 3209 uint32_t *regval) 3210 { 3211 int slot; 3212 si_prb_t *prb; 3213 uint32_t *prb_word_ptr; 3214 int i; 3215 uint32_t slot_status; 3216 int loop_count = 0; 3217 3218 _NOTE(ASSUMING_PROTECTED(si_portp)) 3219 3220 SIDBG3(SIDBG_ENTRY, si_ctlp, "si_read_portmult_reg: port: %x," 3221 "pmport: %x, regnum: %x", 3222 port, pmport, regnum); 3223 3224 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3225 if (slot == -1) { 3226 return (SI_FAILURE); 3227 } 3228 3229 prb = &(si_portp->siport_prbpool[slot]); 3230 bzero((void *)prb, sizeof (si_prb_t)); 3231 3232 /* Now fill the prb. */ 3233 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3234 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3235 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3236 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_PM_REG); 3237 3238 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3239 SET_FIS_FEATURES(prb->prb_fis, regnum); 3240 3241 /* no real data transfer is involved. */ 3242 SET_SGE_TRM(prb->prb_sge0); 3243 3244 #if SI_DEBUG 3245 if (si_debug_flags & SIDBG_DUMP_PRB) { 3246 int *ptr; 3247 int j; 3248 3249 ptr = (int *)prb; 3250 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3251 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3252 cmn_err(CE_WARN, "%x ", ptr[j]); 3253 } 3254 3255 } 3256 #endif /* SI_DEBUG */ 3257 3258 /* Deliver PRB */ 3259 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3260 3261 /* Loop till the command is finished. */ 3262 do { 3263 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3264 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3265 3266 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3267 "looping read_pm slot_status: 0x%x", 3268 slot_status); 3269 3270 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3271 /* We are effectively timing out after 0.5 sec. */ 3272 break; 3273 } 3274 3275 /* Wait for 10 millisec */ 3276 #ifndef __lock_lint 3277 delay(SI_10MS_TICKS); 3278 #endif /* __lock_lint */ 3279 3280 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3281 3282 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3283 "read_portmult_reg: loop count: %d", 3284 loop_count); 3285 3286 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3287 3288 /* Now inspect the port LRAM for the modified FIS. */ 3289 prb_word_ptr = (uint32_t *)prb; 3290 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3291 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3292 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3293 } 3294 3295 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3296 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3297 /* command failed. */ 3298 return (SI_FAILURE); 3299 } 3300 3301 /* command succeeded. */ 3302 *regval = (GET_FIS_SECTOR_COUNT(prb->prb_fis) & 0xff) | 3303 ((GET_FIS_SECTOR(prb->prb_fis) << 8) & 0xff00) | 3304 ((GET_FIS_CYL_LOW(prb->prb_fis) << 16) & 0xff0000) | 3305 ((GET_FIS_CYL_HI(prb->prb_fis) << 24) & 0xff000000); 3306 3307 return (SI_SUCCESS); 3308 } 3309 3310 /* 3311 * Write a port multiplier register. 3312 * 3313 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3314 * before calling us. 3315 */ 3316 static int 3317 si_write_portmult_reg( 3318 si_ctl_state_t *si_ctlp, 3319 si_port_state_t *si_portp, 3320 int port, 3321 int pmport, 3322 int regnum, 3323 uint32_t regval) 3324 { 3325 int slot; 3326 si_prb_t *prb; 3327 uint32_t *prb_word_ptr; 3328 uint32_t slot_status; 3329 int i; 3330 int loop_count = 0; 3331 3332 _NOTE(ASSUMING_PROTECTED(si_portp)) 3333 3334 SIDBG4(SIDBG_ENTRY, si_ctlp, 3335 "si_write_portmult_reg: port: %x, pmport: %x," 3336 "regnum: %x, regval: %x", 3337 port, pmport, regnum, regval); 3338 3339 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3340 if (slot == -1) { 3341 return (SI_FAILURE); 3342 } 3343 3344 prb = &(si_portp->siport_prbpool[slot]); 3345 bzero((void *)prb, sizeof (si_prb_t)); 3346 3347 /* Now fill the prb. */ 3348 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3349 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3350 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3351 3352 SET_FIS_COMMAND(prb->prb_fis, SATAC_WRITE_PM_REG); 3353 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3354 SET_FIS_FEATURES(prb->prb_fis, regnum); 3355 3356 SET_FIS_SECTOR_COUNT(prb->prb_fis, regval & 0xff); 3357 SET_FIS_SECTOR(prb->prb_fis, (regval >> 8) & 0xff); 3358 SET_FIS_CYL_LOW(prb->prb_fis, (regval >> 16) & 0xff); 3359 SET_FIS_CYL_HI(prb->prb_fis, (regval >> 24) & 0xff); 3360 3361 /* no real data transfer is involved. */ 3362 SET_SGE_TRM(prb->prb_sge0); 3363 3364 #if SI_DEBUG 3365 if (si_debug_flags & SIDBG_DUMP_PRB) { 3366 int *ptr; 3367 int j; 3368 3369 ptr = (int *)prb; 3370 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3371 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3372 cmn_err(CE_WARN, "%x ", ptr[j]); 3373 } 3374 3375 } 3376 #endif /* SI_DEBUG */ 3377 3378 /* Deliver PRB */ 3379 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3380 3381 /* Loop till the command is finished. */ 3382 do { 3383 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3384 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3385 3386 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3387 "looping write_pmp slot_status: 0x%x", 3388 slot_status); 3389 3390 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3391 /* We are effectively timing out after 0.5 sec. */ 3392 break; 3393 } 3394 3395 /* Wait for 10 millisec */ 3396 #ifndef __lock_lint 3397 delay(SI_10MS_TICKS); 3398 #endif /* __lock_lint */ 3399 3400 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3401 3402 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3403 "write_portmult_reg: loop count: %d", 3404 loop_count); 3405 3406 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3407 3408 /* Now inspect the port LRAM for the modified FIS. */ 3409 prb_word_ptr = (uint32_t *)prb; 3410 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3411 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3412 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3413 } 3414 3415 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3416 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3417 /* command failed */ 3418 return (SI_FAILURE); 3419 } 3420 3421 /* command succeeded */ 3422 return (SI_SUCCESS); 3423 } 3424 3425 3426 /* 3427 * Set the auto sense data for ATAPI devices. 3428 * 3429 * Note: Currently the sense data is simulated; this code will be enhanced 3430 * in second phase to fetch the real sense data from the atapi device. 3431 */ 3432 static void 3433 si_set_sense_data(sata_pkt_t *satapkt, int reason) 3434 { 3435 struct scsi_extended_sense *sense; 3436 3437 sense = (struct scsi_extended_sense *) 3438 satapkt->satapkt_cmd.satacmd_rqsense; 3439 bzero(sense, sizeof (struct scsi_extended_sense)); 3440 sense->es_valid = 1; /* Valid sense */ 3441 sense->es_class = 7; /* Response code 0x70 - current err */ 3442 sense->es_key = 0; 3443 sense->es_info_1 = 0; 3444 sense->es_info_2 = 0; 3445 sense->es_info_3 = 0; 3446 sense->es_info_4 = 0; 3447 sense->es_add_len = 6; /* Additional length */ 3448 sense->es_cmd_info[0] = 0; 3449 sense->es_cmd_info[1] = 0; 3450 sense->es_cmd_info[2] = 0; 3451 sense->es_cmd_info[3] = 0; 3452 sense->es_add_code = 0; 3453 sense->es_qual_code = 0; 3454 3455 if ((reason == SATA_PKT_DEV_ERROR) || (reason == SATA_PKT_TIMEOUT)) { 3456 sense->es_key = KEY_HARDWARE_ERROR; 3457 } 3458 } 3459 3460 3461 /* 3462 * Interrupt service handler. We loop through each of the ports to find 3463 * if the interrupt belongs to any of them. 3464 * 3465 * Bulk of the interrupt handling is actually done out of subroutines 3466 * like si_intr_command_complete() etc. 3467 */ 3468 /*ARGSUSED*/ 3469 static uint_t 3470 si_intr(caddr_t arg1, caddr_t arg2) 3471 { 3472 3473 si_ctl_state_t *si_ctlp = (si_ctl_state_t *)arg1; 3474 si_port_state_t *si_portp; 3475 uint32_t global_intr_status; 3476 uint32_t mask, port_intr_status; 3477 int port; 3478 3479 global_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3480 (uint32_t *)GLOBAL_INTERRUPT_STATUS(si_ctlp)); 3481 3482 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3483 "si_intr: global_int_status: 0x%x", 3484 global_intr_status); 3485 3486 if (!(global_intr_status & SI31xx_INTR_PORT_MASK)) { 3487 /* Sorry, the interrupt is not ours. */ 3488 return (DDI_INTR_UNCLAIMED); 3489 } 3490 3491 /* Loop for all the ports. */ 3492 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 3493 3494 mask = 0x1 << port; 3495 if (!(global_intr_status & mask)) { 3496 continue; 3497 } 3498 3499 mutex_enter(&si_ctlp->sictl_mutex); 3500 si_portp = si_ctlp->sictl_ports[port]; 3501 mutex_exit(&si_ctlp->sictl_mutex); 3502 3503 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3504 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 3505 3506 SIDBG2(SIDBG_VERBOSE, si_ctlp, 3507 "s_intr: port_intr_status: 0x%x, port: %x", 3508 port_intr_status, 3509 port); 3510 3511 if (port_intr_status & INTR_COMMAND_COMPLETE) { 3512 (void) si_intr_command_complete(si_ctlp, si_portp, 3513 port); 3514 } 3515 3516 /* Clear the interrupts */ 3517 ddi_put32(si_ctlp->sictl_port_acc_handle, 3518 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3519 port_intr_status & INTR_MASK); 3520 3521 /* 3522 * Note that we did not clear the interrupt for command 3523 * completion interrupt. Reading of slot_status takes care 3524 * of clearing the interrupt for command completion case. 3525 */ 3526 3527 if (port_intr_status & INTR_COMMAND_ERROR) { 3528 (void) si_intr_command_error(si_ctlp, si_portp, port); 3529 } 3530 3531 if (port_intr_status & INTR_PORT_READY) { 3532 (void) si_intr_port_ready(si_ctlp, si_portp, port); 3533 } 3534 3535 if (port_intr_status & INTR_POWER_CHANGE) { 3536 (void) si_intr_pwr_change(si_ctlp, si_portp, port); 3537 } 3538 3539 if (port_intr_status & INTR_PHYRDY_CHANGE) { 3540 (void) si_intr_phy_ready_change(si_ctlp, si_portp, 3541 port); 3542 } 3543 3544 if (port_intr_status & INTR_COMWAKE_RECEIVED) { 3545 (void) si_intr_comwake_rcvd(si_ctlp, si_portp, 3546 port); 3547 } 3548 3549 if (port_intr_status & INTR_UNRECOG_FIS) { 3550 (void) si_intr_unrecognised_fis(si_ctlp, si_portp, 3551 port); 3552 } 3553 3554 if (port_intr_status & INTR_DEV_XCHANGED) { 3555 (void) si_intr_dev_xchanged(si_ctlp, si_portp, port); 3556 } 3557 3558 if (port_intr_status & INTR_8B10B_DECODE_ERROR) { 3559 (void) si_intr_decode_err_threshold(si_ctlp, si_portp, 3560 port); 3561 } 3562 3563 if (port_intr_status & INTR_CRC_ERROR) { 3564 (void) si_intr_crc_err_threshold(si_ctlp, si_portp, 3565 port); 3566 } 3567 3568 if (port_intr_status & INTR_HANDSHAKE_ERROR) { 3569 (void) si_intr_handshake_err_threshold(si_ctlp, 3570 si_portp, port); 3571 } 3572 3573 if (port_intr_status & INTR_SETDEVBITS_NOTIFY) { 3574 (void) si_intr_set_devbits_notify(si_ctlp, si_portp, 3575 port); 3576 } 3577 } 3578 3579 return (DDI_INTR_CLAIMED); 3580 } 3581 3582 /* 3583 * Interrupt which indicates that one or more commands have successfully 3584 * completed. 3585 * 3586 * Since we disabled W1C (write-one-to-clear) previously, mere reading 3587 * of slot_status register clears the interrupt. There is no need to 3588 * explicitly clear the interrupt. 3589 */ 3590 static int 3591 si_intr_command_complete( 3592 si_ctl_state_t *si_ctlp, 3593 si_port_state_t *si_portp, 3594 int port) 3595 { 3596 3597 uint32_t slot_status; 3598 uint32_t finished_tags; 3599 int finished_slot; 3600 sata_pkt_t *satapkt; 3601 3602 SIDBG0(SIDBG_ENTRY|SIDBG_INTR, si_ctlp, 3603 "si_intr_command_complete enter"); 3604 3605 mutex_enter(&si_portp->siport_mutex); 3606 3607 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3608 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3609 3610 if (!si_portp->siport_pending_tags) { 3611 /* 3612 * Spurious interrupt. Nothing to be done. 3613 * Do read the slot_status to clear the interrupt. 3614 */ 3615 mutex_exit(&si_portp->siport_mutex); 3616 return (SI_SUCCESS); 3617 } 3618 3619 SIDBG2(SIDBG_VERBOSE, si_ctlp, "si3124: si_intr_command_complete: " 3620 "pending_tags: %x, slot_status: %x", 3621 si_portp->siport_pending_tags, 3622 slot_status); 3623 3624 finished_tags = si_portp->siport_pending_tags & 3625 ~slot_status & SI_SLOT_MASK; 3626 while (finished_tags) { 3627 si_prb_t *prb; 3628 3629 finished_slot = ddi_ffs(finished_tags) - 1; 3630 if (finished_slot == -1) { 3631 break; 3632 } 3633 prb = &si_portp->siport_prbpool[finished_slot]; 3634 3635 satapkt = si_portp->siport_slot_pkts[finished_slot]; 3636 satapkt->satapkt_cmd.satacmd_status_reg = 3637 GET_FIS_COMMAND(prb->prb_fis); 3638 3639 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 3640 si_copy_out_regs(&satapkt->satapkt_cmd, &prb->prb_fis); 3641 3642 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 3643 3644 CLEAR_BIT(si_portp->siport_pending_tags, finished_slot); 3645 CLEAR_BIT(finished_tags, finished_slot); 3646 } 3647 3648 SIDBG2(SIDBG_PKTCOMP, si_ctlp, 3649 "command_complete done: pend_tags: 0x%x, slot_status: 0x%x", 3650 si_portp->siport_pending_tags, 3651 slot_status); 3652 3653 /* 3654 * tidbit: no need to clear the interrupt since reading of 3655 * slot_status automatically clears the interrupt in the case 3656 * of a successful command completion. 3657 */ 3658 3659 mutex_exit(&si_portp->siport_mutex); 3660 3661 return (SI_SUCCESS); 3662 } 3663 3664 /* 3665 * Interrupt which indicates that a command did not complete successfully. 3666 * 3667 * The port halts whenever a command error interrupt is received. 3668 * The only way to restart it is to reset or reinitialize the port 3669 * but such an operation throws away all the pending commands on 3670 * the port. 3671 * 3672 * We reset the device and mop the commands on the port. 3673 */ 3674 static int 3675 si_intr_command_error( 3676 si_ctl_state_t *si_ctlp, 3677 si_port_state_t *si_portp, 3678 int port) 3679 { 3680 uint32_t command_error, slot_status; 3681 uint32_t failed_tags; 3682 3683 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3684 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3685 3686 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3687 "si_intr_command_error: command_error: 0x%x", 3688 command_error); 3689 3690 mutex_enter(&si_portp->siport_mutex); 3691 3692 /* 3693 * Remember the slot_status since any of the recovery handler 3694 * can blow it away with reset operation. 3695 */ 3696 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3697 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3698 3699 si_log_error_message(si_ctlp, port, command_error); 3700 3701 switch (command_error) { 3702 3703 case CMD_ERR_DEVICEERRROR: 3704 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3705 break; 3706 3707 case CMD_ERR_SDBERROR: 3708 si_error_recovery_SDBERROR(si_ctlp, si_portp, port); 3709 break; 3710 3711 case CMD_ERR_DATAFISERROR: 3712 si_error_recovery_DATAFISERROR(si_ctlp, si_portp, port); 3713 break; 3714 3715 case CMD_ERR_SENDFISERROR: 3716 si_error_recovery_SENDFISERROR(si_ctlp, si_portp, port); 3717 break; 3718 3719 default: 3720 si_error_recovery_default(si_ctlp, si_portp, port); 3721 break; 3722 3723 } 3724 3725 /* 3726 * Compute the failed_tags by adding up the error tags. 3727 * 3728 * The siport_err_tags_SDBERROR and siport_err_tags_nonSDBERROR 3729 * were filled in by the si_error_recovery_* routines. 3730 */ 3731 failed_tags = si_portp->siport_pending_tags & 3732 (si_portp->siport_err_tags_SDBERROR | 3733 si_portp->siport_err_tags_nonSDBERROR); 3734 3735 SIDBG3(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si_intr_command_error: " 3736 "err_tags_SDBERROR: 0x%x, " 3737 "err_tags_nonSDBERRROR: 0x%x, " 3738 "failed_tags: 0x%x", 3739 si_portp->siport_err_tags_SDBERROR, 3740 si_portp->siport_err_tags_nonSDBERROR, 3741 failed_tags); 3742 3743 SIDBG2(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si3124: si_intr_command_error: " 3744 "slot_status:0x%x, pending_tags: 0x%x", 3745 slot_status, 3746 si_portp->siport_pending_tags); 3747 3748 mutex_exit(&si_portp->siport_mutex); 3749 si_mop_commands(si_ctlp, 3750 si_portp, 3751 port, 3752 slot_status, 3753 failed_tags, 3754 0, /* timedout_tags */ 3755 0, /* aborting_tags */ 3756 0); /* reset_tags */ 3757 mutex_enter(&si_portp->siport_mutex); 3758 3759 ASSERT(si_portp->siport_pending_tags == 0); 3760 3761 si_portp->siport_err_tags_SDBERROR = 0; 3762 si_portp->siport_err_tags_nonSDBERROR = 0; 3763 3764 mutex_exit(&si_portp->siport_mutex); 3765 3766 return (SI_SUCCESS); 3767 } 3768 3769 /* 3770 * There is a subtle difference between errors on a normal port and 3771 * a port-mult port. When an error happens on a normal port, the port 3772 * is halted effectively until the port is reset or initialized. 3773 * However, in port-mult port errors, port does not get halted since 3774 * other non-error devices behind the port multiplier can still 3775 * continue to operate. So we wait till all the commands are drained 3776 * instead of resetting it right away. 3777 * 3778 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3779 * before calling us. 3780 */ 3781 static void 3782 si_recover_portmult_errors( 3783 si_ctl_state_t *si_ctlp, 3784 si_port_state_t *si_portp, 3785 int port) 3786 { 3787 uint32_t command_error, slot_status, port_status; 3788 int failed_slot; 3789 int loop_count = 0; 3790 3791 _NOTE(ASSUMING_PROTECTED(si_portp)) 3792 3793 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3794 "si_recover_portmult_errors: port: 0x%x", 3795 port); 3796 3797 /* Resume the port */ 3798 ddi_put32(si_ctlp->sictl_port_acc_handle, 3799 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3800 PORT_CONTROL_SET_BITS_RESUME); 3801 3802 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3803 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3804 3805 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3806 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3807 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3808 3809 if (command_error == CMD_ERR_SDBERROR) { 3810 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3811 } else { 3812 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3813 } 3814 3815 /* Now we drain the pending commands. */ 3816 do { 3817 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3818 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3819 3820 /* 3821 * Since we have not yet returned DDI_INTR_CLAIMED, 3822 * our interrupt handler is guaranteed not to be called again. 3823 * So we need to check IS_ATTENTION_RAISED() for further 3824 * decisions. 3825 * 3826 * This is a too big a delay for an interrupt context. 3827 * But this is supposed to be a rare condition. 3828 */ 3829 3830 if (IS_ATTENTION_RAISED(slot_status)) { 3831 /* Resume again */ 3832 ddi_put32(si_ctlp->sictl_port_acc_handle, 3833 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3834 PORT_CONTROL_SET_BITS_RESUME); 3835 3836 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3837 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3838 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3839 command_error = ddi_get32( 3840 si_ctlp->sictl_port_acc_handle, 3841 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, 3842 port))); 3843 if (command_error == CMD_ERR_SDBERROR) { 3844 si_portp->siport_err_tags_SDBERROR |= 3845 (0x1 << failed_slot); 3846 } else { 3847 si_portp->siport_err_tags_nonSDBERROR |= 3848 (0x1 << failed_slot); 3849 } 3850 } 3851 3852 if (loop_count++ > SI_POLLRATE_RECOVERPORTMULT) { 3853 /* We are effectively timing out after 10 sec. */ 3854 break; 3855 } 3856 3857 /* Wait for 10 millisec */ 3858 #ifndef __lock_lint 3859 delay(SI_10MS_TICKS); 3860 #endif /* __lock_lint */ 3861 3862 } while (slot_status & SI_SLOT_MASK); 3863 3864 /* 3865 * The above loop can be improved for 3132 since we could obtain the 3866 * Port Multiplier Context of the device in error. Then we could 3867 * do a better job in filtering out commands for the device in error. 3868 * The loop could finish much earlier with such a logic. 3869 */ 3870 3871 /* Clear the RESUME bit. */ 3872 ddi_put32(si_ctlp->sictl_port_acc_handle, 3873 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3874 PORT_CONTROL_CLEAR_BITS_RESUME); 3875 3876 } 3877 3878 /* 3879 * If we are connected to port multiplier, drain the non-failed devices. 3880 * Otherwise, we initialize the port (which effectively fails all the 3881 * pending commands in the hope that sd would retry them later). 3882 * 3883 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3884 * before calling us. 3885 */ 3886 static void 3887 si_error_recovery_DEVICEERROR( 3888 si_ctl_state_t *si_ctlp, 3889 si_port_state_t *si_portp, 3890 int port) 3891 { 3892 uint32_t port_status; 3893 int failed_slot; 3894 3895 _NOTE(ASSUMING_PROTECTED(si_portp)) 3896 3897 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3898 "si_error_recovery_DEVICEERROR: port: 0x%x", 3899 port); 3900 3901 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3902 si_recover_portmult_errors(si_ctlp, si_portp, port); 3903 } else { 3904 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3905 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3906 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3907 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3908 } 3909 3910 /* In either case (port-mult or not), we reinitialize the port. */ 3911 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3912 } 3913 3914 /* 3915 * Handle exactly like DEVICEERROR. Remember the tags with SDBERROR 3916 * to perform read_log_ext on them later. SDBERROR means that the 3917 * error was for an NCQ command. 3918 * 3919 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3920 * before calling us. 3921 */ 3922 static void 3923 si_error_recovery_SDBERROR( 3924 si_ctl_state_t *si_ctlp, 3925 si_port_state_t *si_portp, 3926 int port) 3927 { 3928 uint32_t port_status; 3929 int failed_slot; 3930 3931 _NOTE(ASSUMING_PROTECTED(si_portp)) 3932 3933 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3934 "si3124: si_error_recovery_SDBERROR: port: 0x%x", 3935 port); 3936 3937 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3938 si_recover_portmult_errors(si_ctlp, si_portp, port); 3939 } else { 3940 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3941 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3942 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3943 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3944 } 3945 3946 /* In either case (port-mult or not), we reinitialize the port. */ 3947 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3948 } 3949 3950 /* 3951 * Handle exactly like DEVICEERROR except resetting the port if there was 3952 * an NCQ command on the port. 3953 * 3954 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3955 * before calling us. 3956 */ 3957 static void 3958 si_error_recovery_DATAFISERROR( 3959 si_ctl_state_t *si_ctlp, 3960 si_port_state_t *si_portp, 3961 int port) 3962 { 3963 uint32_t port_status; 3964 int failed_slot; 3965 3966 _NOTE(ASSUMING_PROTECTED(si_portp)) 3967 3968 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3969 "si3124: si_error_recovery_DATAFISERROR: port: 0x%x", 3970 port); 3971 3972 /* reset device if we were waiting for any ncq commands. */ 3973 if (si_portp->siport_pending_ncq_count) { 3974 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3975 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3976 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3977 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3978 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 3979 SI_DEVICE_RESET); 3980 return; 3981 } 3982 3983 /* 3984 * If we don't have any ncq commands pending, the rest of 3985 * the process is similar to the one for DEVICEERROR. 3986 */ 3987 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3988 } 3989 3990 /* 3991 * We handle just like DEVICERROR except that we reset the device instead 3992 * of initializing the port. 3993 * 3994 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3995 * before calling us. 3996 */ 3997 static void 3998 si_error_recovery_SENDFISERROR( 3999 si_ctl_state_t *si_ctlp, 4000 si_port_state_t *si_portp, 4001 int port) 4002 { 4003 uint32_t port_status; 4004 int failed_slot; 4005 4006 _NOTE(ASSUMING_PROTECTED(si_portp)) 4007 4008 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 4009 "si3124: si_error_recovery_SENDFISERROR: port: 0x%x", 4010 port); 4011 4012 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 4013 si_recover_portmult_errors(si_ctlp, si_portp, port); 4014 } else { 4015 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4016 (uint32_t *)PORT_STATUS(si_ctlp, port)); 4017 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 4018 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 4019 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 4020 SI_DEVICE_RESET); 4021 } 4022 } 4023 4024 /* 4025 * The default behavior for all other errors is to reset the device. 4026 * 4027 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4028 * before calling us. 4029 */ 4030 static void 4031 si_error_recovery_default( 4032 si_ctl_state_t *si_ctlp, 4033 si_port_state_t *si_portp, 4034 int port) 4035 { 4036 uint32_t port_status; 4037 int failed_slot; 4038 4039 _NOTE(ASSUMING_PROTECTED(si_portp)) 4040 4041 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 4042 "si3124: si_error_recovery_default: port: 0x%x", 4043 port); 4044 4045 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4046 (uint32_t *)PORT_STATUS(si_ctlp, port)); 4047 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 4048 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 4049 4050 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 4051 SI_DEVICE_RESET); 4052 } 4053 4054 /* 4055 * Read Log Ext with PAGE 10 to retrieve the error for an NCQ command. 4056 * 4057 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4058 * before calling us. 4059 */ 4060 static uint8_t 4061 si_read_log_ext(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 4062 { 4063 int slot; 4064 si_prb_t *prb; 4065 int i; 4066 uint32_t slot_status; 4067 int loop_count = 0; 4068 uint32_t *prb_word_ptr; 4069 uint8_t error; 4070 4071 _NOTE(ASSUMING_PROTECTED(si_portp)) 4072 4073 SIDBG1(SIDBG_ENTRY|SIDBG_ERRS, si_ctlp, 4074 "si_read_log_ext: port: %x", port); 4075 4076 slot = si_claim_free_slot(si_ctlp, si_portp, port); 4077 if (slot == -1) { 4078 return (0); 4079 } 4080 4081 prb = &(si_portp->siport_prbpool[slot]); 4082 bzero((void *)prb, sizeof (si_prb_t)); 4083 4084 /* Now fill the prb */ 4085 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 4086 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 4087 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 4088 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_LOG_EXT); 4089 SET_FIS_SECTOR(prb->prb_fis, SATA_LOG_PAGE_10); 4090 4091 /* no real data transfer is involved */ 4092 SET_SGE_TRM(prb->prb_sge0); 4093 4094 #if SI_DEBUG 4095 if (si_debug_flags & SIDBG_DUMP_PRB) { 4096 int *ptr; 4097 int j; 4098 4099 ptr = (int *)prb; 4100 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 4101 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 4102 cmn_err(CE_WARN, "%x ", ptr[j]); 4103 } 4104 4105 } 4106 #endif /* SI_DEBUG */ 4107 4108 /* Deliver PRB */ 4109 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 4110 4111 /* Loop till the command is finished. */ 4112 do { 4113 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4114 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 4115 4116 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4117 "looping read_log_ext slot_status: 0x%x", 4118 slot_status); 4119 4120 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 4121 /* We are effectively timing out after 0.5 sec. */ 4122 break; 4123 } 4124 4125 /* Wait for 10 millisec */ 4126 #ifndef __lock_lint 4127 delay(SI_10MS_TICKS); 4128 #endif /* __lock_lint */ 4129 4130 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 4131 4132 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 4133 /* 4134 * If we fail with the READ LOG EXT command, we need to 4135 * initialize the port to clear the slot_status register. 4136 * We don't need to worry about any other valid commands 4137 * being thrown away because we are already in recovery 4138 * mode and READ LOG EXT is the only pending command. 4139 */ 4140 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 4141 } 4142 4143 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4144 "read_portmult_reg: loop count: %d", 4145 loop_count); 4146 4147 /* 4148 * The LRAM contains the the modified FIS. 4149 * Read the modified FIS to obtain the Error. 4150 */ 4151 prb_word_ptr = (uint32_t *)prb; 4152 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 4153 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 4154 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 4155 } 4156 error = GET_FIS_FEATURES(prb->prb_fis); 4157 4158 CLEAR_BIT(si_portp->siport_pending_tags, slot); 4159 4160 return (error); 4161 4162 } 4163 4164 /* 4165 * Dump the error message to the log. 4166 */ 4167 static void 4168 si_log_error_message(si_ctl_state_t *si_ctlp, int port, uint32_t command_error) 4169 { 4170 char *errstr; 4171 4172 switch (command_error) { 4173 4174 case CMD_ERR_DEVICEERRROR: 4175 errstr = "Standard Error: Error bit set in register - device" 4176 " to host FIS"; 4177 break; 4178 4179 case CMD_ERR_SDBERROR: 4180 errstr = "NCQ Error: Error bit set in register - device" 4181 " to host FIS"; 4182 break; 4183 4184 case CMD_ERR_DATAFISERROR: 4185 errstr = "Error in data FIS not detected by device"; 4186 break; 4187 4188 case CMD_ERR_SENDFISERROR: 4189 errstr = "Initial command FIS transmission failed"; 4190 break; 4191 4192 case CMD_ERR_INCONSISTENTSTATE: 4193 errstr = "Inconsistency in protocol"; 4194 break; 4195 4196 case CMD_ERR_DIRECTIONERROR: 4197 errstr = "DMA direction flag does not match the command"; 4198 break; 4199 4200 case CMD_ERR_UNDERRUNERROR: 4201 errstr = "Run out of scatter gather entries while writing data"; 4202 break; 4203 4204 case CMD_ERR_OVERRUNERROR: 4205 errstr = "Run out of scatter gather entries while reading data"; 4206 break; 4207 4208 case CMD_ERR_PACKETPROTOCOLERROR: 4209 errstr = "Packet protocol error"; 4210 break; 4211 4212 case CMD_ERR_PLDSGTERRORBOUNDARY: 4213 errstr = "Scatter/gather table not on quadword boundary"; 4214 break; 4215 4216 case CMD_ERR_PLDSGTERRORTARETABORT: 4217 errstr = "PCI(X) Target abort while fetching scatter/gather" 4218 " table"; 4219 break; 4220 4221 case CMD_ERR_PLDSGTERRORMASTERABORT: 4222 errstr = "PCI(X) Master abort while fetching scatter/gather" 4223 " table"; 4224 break; 4225 4226 case CMD_ERR_PLDSGTERRORPCIERR: 4227 errstr = "PCI(X) parity error while fetching scatter/gather" 4228 " table"; 4229 break; 4230 4231 case CMD_ERR_PLDCMDERRORBOUNDARY: 4232 errstr = "PRB not on quadword boundary"; 4233 break; 4234 4235 case CMD_ERR_PLDCMDERRORTARGETABORT: 4236 errstr = "PCI(X) Target abort while fetching PRB"; 4237 break; 4238 4239 case CMD_ERR_PLDCMDERRORMASTERABORT: 4240 errstr = "PCI(X) Master abort while fetching PRB"; 4241 break; 4242 4243 case CMD_ERR_PLDCMDERORPCIERR: 4244 errstr = "PCI(X) parity error while fetching PRB"; 4245 break; 4246 4247 case CMD_ERR_PSDERRORTARGETABORT: 4248 errstr = "PCI(X) Target abort during data transfer"; 4249 break; 4250 4251 case CMD_ERR_PSDERRORMASTERABORT: 4252 errstr = "PCI(X) Master abort during data transfer"; 4253 break; 4254 4255 case CMD_ERR_PSDERRORPCIERR: 4256 errstr = "PCI(X) parity error during data transfer"; 4257 break; 4258 4259 case CMD_ERR_SENDSERVICEERROR: 4260 errstr = "FIS received while sending service FIS in" 4261 " legacy queuing operation"; 4262 break; 4263 4264 default: 4265 errstr = "Unknown Error"; 4266 break; 4267 4268 } 4269 4270 SIDBG2(SIDBG_ERRS, si_ctlp, 4271 "command error: port: 0x%x, error: %s", 4272 port, 4273 errstr); 4274 4275 } 4276 4277 4278 /* 4279 * Interrupt which indicates that the Port Ready state has changed 4280 * from zero to one. 4281 * 4282 * We are not interested in this interrupt; we just log a debug message. 4283 */ 4284 /*ARGSUSED*/ 4285 static int 4286 si_intr_port_ready( 4287 si_ctl_state_t *si_ctlp, 4288 si_port_state_t *si_portp, 4289 int port) 4290 { 4291 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_ready"); 4292 return (SI_SUCCESS); 4293 } 4294 4295 /* 4296 * Interrupt which indicates that the port power management state 4297 * has been modified. 4298 * 4299 * We are not interested in this interrupt; we just log a debug message. 4300 */ 4301 /*ARGSUSED*/ 4302 static int 4303 si_intr_pwr_change( 4304 si_ctl_state_t *si_ctlp, 4305 si_port_state_t *si_portp, 4306 int port) 4307 { 4308 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_pwr_change"); 4309 return (SI_SUCCESS); 4310 } 4311 4312 /* 4313 * Interrupt which indicates that the PHY sate has changed either from 4314 * Not-Ready to Ready or from Ready to Not-Ready. 4315 */ 4316 static int 4317 si_intr_phy_ready_change( 4318 si_ctl_state_t *si_ctlp, 4319 si_port_state_t *si_portp, 4320 int port) 4321 { 4322 sata_device_t sdevice; 4323 uint32_t SStatus = 0; /* No dev present & PHY not established. */ 4324 int dev_exists_now = 0; 4325 int dev_existed_previously = 0; 4326 4327 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_phy_rdy_change"); 4328 4329 mutex_enter(&si_ctlp->sictl_mutex); 4330 if ((si_ctlp->sictl_sata_hba_tran == NULL) || (si_portp == NULL)) { 4331 /* the whole controller setup is not yet done. */ 4332 mutex_exit(&si_ctlp->sictl_mutex); 4333 return (SI_SUCCESS); 4334 } 4335 4336 mutex_exit(&si_ctlp->sictl_mutex); 4337 4338 mutex_enter(&si_portp->siport_mutex); 4339 4340 /* SStatus tells the presence of device. */ 4341 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4342 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 4343 dev_exists_now = 4344 (SSTATUS_GET_DET(SStatus) == SSTATUS_DET_DEVPRESENT_PHYONLINE); 4345 4346 if (si_portp->siport_port_type != PORT_TYPE_NODEV) { 4347 dev_existed_previously = 1; 4348 } 4349 4350 bzero((void *)&sdevice, sizeof (sata_device_t)); 4351 sdevice.satadev_addr.cport = port; 4352 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 4353 4354 /* we don't have a way of determining the exact port-mult port. */ 4355 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 4356 sdevice.satadev_addr.qual = SATA_ADDR_PMPORT; 4357 } else { 4358 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4359 } 4360 4361 sdevice.satadev_state = SATA_PSTATE_PWRON; 4362 4363 if (dev_exists_now) { 4364 if (dev_existed_previously) { 4365 4366 /* Things are fine now. The loss was temporary. */ 4367 SIDBG0(SIDBG_INTR, NULL, 4368 "phyrdy: doing BOTH EVENTS TOGETHER"); 4369 if (si_portp->siport_active) { 4370 SIDBG0(SIDBG_EVENT, si_ctlp, 4371 "sending event: LINK_LOST & " 4372 "LINK_ESTABLISHED"); 4373 4374 sata_hba_event_notify( 4375 si_ctlp->sictl_sata_hba_tran->\ 4376 sata_tran_hba_dip, 4377 &sdevice, 4378 SATA_EVNT_LINK_LOST| 4379 SATA_EVNT_LINK_ESTABLISHED); 4380 } 4381 4382 } else { 4383 4384 /* A new device has been detected. */ 4385 mutex_exit(&si_portp->siport_mutex); 4386 si_find_dev_signature(si_ctlp, si_portp, port, 4387 PORTMULT_CONTROL_PORT); 4388 mutex_enter(&si_portp->siport_mutex); 4389 SIDBG0(SIDBG_INTR, NULL, "phyrdy: doing ATTACH event"); 4390 if (si_portp->siport_active) { 4391 SIDBG0(SIDBG_EVENT, si_ctlp, 4392 "sending event up: LINK_ESTABLISHED"); 4393 4394 sata_hba_event_notify( 4395 si_ctlp->sictl_sata_hba_tran->\ 4396 sata_tran_hba_dip, 4397 &sdevice, 4398 SATA_EVNT_LINK_ESTABLISHED); 4399 } 4400 4401 } 4402 } else { /* No device exists now */ 4403 4404 if (dev_existed_previously) { 4405 4406 /* An existing device is lost. */ 4407 if (si_portp->siport_active) { 4408 SIDBG0(SIDBG_EVENT, si_ctlp, 4409 "sending event up: LINK_LOST"); 4410 4411 sata_hba_event_notify( 4412 si_ctlp->sictl_sata_hba_tran-> 4413 sata_tran_hba_dip, 4414 &sdevice, 4415 SATA_EVNT_LINK_LOST); 4416 } 4417 si_portp->siport_port_type = PORT_TYPE_NODEV; 4418 4419 } else { 4420 4421 /* spurious interrupt */ 4422 SIDBG0(SIDBG_INTR, NULL, 4423 "spurious phy ready interrupt"); 4424 } 4425 } 4426 4427 mutex_exit(&si_portp->siport_mutex); 4428 return (SI_SUCCESS); 4429 } 4430 4431 4432 /* 4433 * Interrupt which indicates that a COMWAKE OOB signal has been decoded 4434 * on the receiver. 4435 * 4436 * We are not interested in this interrupt; we just log a debug message. 4437 */ 4438 /*ARGSUSED*/ 4439 static int 4440 si_intr_comwake_rcvd( 4441 si_ctl_state_t *si_ctlp, 4442 si_port_state_t *si_portp, 4443 int port) 4444 { 4445 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_commwake_rcvd"); 4446 return (SI_SUCCESS); 4447 } 4448 4449 /* 4450 * Interrupt which indicates that the F-bit has been set in SError 4451 * Diag field. 4452 * 4453 * We are not interested in this interrupt; we just log a debug message. 4454 */ 4455 /*ARGSUSED*/ 4456 static int 4457 si_intr_unrecognised_fis( 4458 si_ctl_state_t *si_ctlp, 4459 si_port_state_t *si_portp, 4460 int port) 4461 { 4462 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_unrecognised_fis"); 4463 return (SI_SUCCESS); 4464 } 4465 4466 /* 4467 * Interrupt which indicates that the X-bit has been set in SError 4468 * Diag field. 4469 * 4470 * We are not interested in this interrupt; we just log a debug message. 4471 */ 4472 /*ARGSUSED*/ 4473 static int 4474 si_intr_dev_xchanged( 4475 si_ctl_state_t *si_ctlp, 4476 si_port_state_t *si_portp, 4477 int port) 4478 { 4479 4480 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_dev_xchanged"); 4481 return (SI_SUCCESS); 4482 } 4483 4484 /* 4485 * Interrupt which indicates that the 8b/10 Decode Error counter has 4486 * exceeded the programmed non-zero threshold value. 4487 * 4488 * We are not interested in this interrupt; we just log a debug message. 4489 */ 4490 /*ARGSUSED*/ 4491 static int 4492 si_intr_decode_err_threshold( 4493 si_ctl_state_t *si_ctlp, 4494 si_port_state_t *si_portp, 4495 int port) 4496 { 4497 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_err_threshold"); 4498 return (SI_SUCCESS); 4499 } 4500 4501 /* 4502 * Interrupt which indicates that the CRC Error counter has exceeded the 4503 * programmed non-zero threshold value. 4504 * 4505 * We are not interested in this interrupt; we just log a debug message. 4506 */ 4507 /*ARGSUSED*/ 4508 static int 4509 si_intr_crc_err_threshold( 4510 si_ctl_state_t *si_ctlp, 4511 si_port_state_t *si_portp, 4512 int port) 4513 { 4514 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_crc_threshold"); 4515 return (SI_SUCCESS); 4516 } 4517 4518 /* 4519 * Interrupt which indicates that the Handshake Error counter has 4520 * exceeded the programmed non-zero threshold value. 4521 * 4522 * We are not interested in this interrupt; we just log a debug message. 4523 */ 4524 /*ARGSUSED*/ 4525 static int 4526 si_intr_handshake_err_threshold( 4527 si_ctl_state_t *si_ctlp, 4528 si_port_state_t *si_portp, 4529 int port) 4530 { 4531 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 4532 "si_intr_handshake_err_threshold"); 4533 return (SI_SUCCESS); 4534 } 4535 4536 /* 4537 * Interrupt which indicates that a "Set Device Bits" FIS has been 4538 * received with N-bit set in the control field. 4539 * 4540 * We are not interested in this interrupt; we just log a debug message. 4541 */ 4542 /*ARGSUSED*/ 4543 static int 4544 si_intr_set_devbits_notify( 4545 si_ctl_state_t *si_ctlp, 4546 si_port_state_t *si_portp, 4547 int port) 4548 { 4549 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_set_devbits_notify"); 4550 return (SI_SUCCESS); 4551 } 4552 4553 4554 /* 4555 * Enable the interrupts for a particular port. 4556 * 4557 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4558 * before calling us. 4559 */ 4560 static void 4561 si_enable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4562 { 4563 uint32_t mask; 4564 4565 /* get the current settings first. */ 4566 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4567 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4568 4569 SIDBG1(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 4570 "si_enable_port_interrupts: current mask: 0x%x", 4571 mask); 4572 4573 /* enable the bit for current port. */ 4574 SET_BIT(mask, port); 4575 4576 /* now use this mask to enable the interrupt. */ 4577 ddi_put32(si_ctlp->sictl_global_acc_handle, 4578 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4579 mask); 4580 } 4581 4582 /* 4583 * Enable interrupts for all the ports. 4584 */ 4585 static void 4586 si_enable_all_interrupts(si_ctl_state_t *si_ctlp) 4587 { 4588 int port; 4589 4590 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4591 si_enable_port_interrupts(si_ctlp, port); 4592 } 4593 } 4594 4595 /* 4596 * Disable interrupts for a particular port. 4597 * 4598 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4599 * before calling us. 4600 */ 4601 static void 4602 si_disable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4603 { 4604 uint32_t mask; 4605 4606 /* get the current settings first. */ 4607 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4608 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4609 4610 /* clear the bit for current port. */ 4611 CLEAR_BIT(mask, port); 4612 4613 /* now use this mask to disable the interrupt. */ 4614 ddi_put32(si_ctlp->sictl_global_acc_handle, 4615 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4616 mask); 4617 4618 } 4619 4620 /* 4621 * Disable interrupts for all the ports. 4622 */ 4623 static void 4624 si_disable_all_interrupts(si_ctl_state_t *si_ctlp) 4625 { 4626 int port; 4627 4628 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4629 si_disable_port_interrupts(si_ctlp, port); 4630 } 4631 } 4632 4633 /* 4634 * Fetches the latest sstatus, scontrol, serror, sactive registers 4635 * and stuffs them into sata_device_t structure. 4636 */ 4637 static void 4638 fill_dev_sregisters(si_ctl_state_t *si_ctlp, int port, sata_device_t *satadev) 4639 { 4640 satadev->satadev_scr.sstatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4641 (uint32_t *)(PORT_SSTATUS(si_ctlp, port))); 4642 satadev->satadev_scr.serror = ddi_get32(si_ctlp->sictl_port_acc_handle, 4643 (uint32_t *)(PORT_SERROR(si_ctlp, port))); 4644 satadev->satadev_scr.sactive = ddi_get32(si_ctlp->sictl_port_acc_handle, 4645 (uint32_t *)(PORT_SACTIVE(si_ctlp, port))); 4646 satadev->satadev_scr.scontrol = 4647 ddi_get32(si_ctlp->sictl_port_acc_handle, 4648 (uint32_t *)(PORT_SCONTROL(si_ctlp, port))); 4649 4650 } 4651 4652 /* 4653 * si_add_legacy_intrs() handles INTx and legacy interrupts. 4654 */ 4655 static int 4656 si_add_legacy_intrs(si_ctl_state_t *si_ctlp) 4657 { 4658 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4659 int actual, count = 0; 4660 int x, y, rc, inum = 0; 4661 4662 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_add_legacy_intrs"); 4663 4664 /* get number of interrupts. */ 4665 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &count); 4666 if ((rc != DDI_SUCCESS) || (count == 0)) { 4667 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4668 "ddi_intr_get_nintrs() failed, " 4669 "rc %d count %d\n", rc, count); 4670 return (DDI_FAILURE); 4671 } 4672 4673 /* Allocate an array of interrupt handles. */ 4674 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4675 si_ctlp->sictl_htable = kmem_zalloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4676 4677 /* call ddi_intr_alloc(). */ 4678 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_FIXED, 4679 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 4680 4681 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4682 SIDBG1(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4683 "ddi_intr_alloc() failed, rc %d\n", rc); 4684 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4685 return (DDI_FAILURE); 4686 } 4687 4688 if (actual < count) { 4689 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4690 "Requested: %d, Received: %d", count, actual); 4691 4692 for (x = 0; x < actual; x++) { 4693 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4694 } 4695 4696 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4697 return (DDI_FAILURE); 4698 } 4699 4700 si_ctlp->sictl_intr_cnt = actual; 4701 4702 /* Get intr priority. */ 4703 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4704 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4705 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4706 "ddi_intr_get_pri() failed"); 4707 4708 for (x = 0; x < actual; x++) { 4709 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4710 } 4711 4712 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4713 return (DDI_FAILURE); 4714 } 4715 4716 /* Test for high level mutex. */ 4717 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4718 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4719 "si_add_legacy_intrs: Hi level intr not supported"); 4720 4721 for (x = 0; x < actual; x++) { 4722 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4723 } 4724 4725 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4726 4727 return (DDI_FAILURE); 4728 } 4729 4730 /* Call ddi_intr_add_handler(). */ 4731 for (x = 0; x < actual; x++) { 4732 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4733 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4734 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4735 "ddi_intr_add_handler() failed"); 4736 4737 for (y = 0; y < actual; y++) { 4738 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4739 } 4740 4741 kmem_free(si_ctlp->sictl_htable, 4742 si_ctlp->sictl_intr_size); 4743 return (DDI_FAILURE); 4744 } 4745 } 4746 4747 /* Call ddi_intr_enable() for legacy interrupts. */ 4748 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4749 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4750 } 4751 4752 return (DDI_SUCCESS); 4753 } 4754 4755 /* 4756 * si_add_msictl_intrs() handles MSI interrupts. 4757 */ 4758 static int 4759 si_add_msi_intrs(si_ctl_state_t *si_ctlp) 4760 { 4761 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4762 int count, avail, actual; 4763 int x, y, rc, inum = 0; 4764 4765 SIDBG0(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, "si_add_msi_intrs"); 4766 4767 /* get number of interrupts. */ 4768 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSI, &count); 4769 if ((rc != DDI_SUCCESS) || (count == 0)) { 4770 SIDBG2(SIDBG_INIT, si_ctlp, 4771 "ddi_intr_get_nintrs() failed, " 4772 "rc %d count %d\n", rc, count); 4773 return (DDI_FAILURE); 4774 } 4775 4776 /* get number of available interrupts. */ 4777 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSI, &avail); 4778 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4779 SIDBG2(SIDBG_INIT, si_ctlp, 4780 "ddi_intr_get_navail() failed, " 4781 "rc %d avail %d\n", rc, avail); 4782 return (DDI_FAILURE); 4783 } 4784 4785 if (avail < count) { 4786 SIDBG2(SIDBG_INIT, si_ctlp, 4787 "ddi_intr_get_nvail returned %d, navail() returned %d", 4788 count, avail); 4789 } 4790 4791 /* Allocate an array of interrupt handles. */ 4792 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4793 si_ctlp->sictl_htable = kmem_alloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4794 4795 /* call ddi_intr_alloc(). */ 4796 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_MSI, 4797 inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 4798 4799 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4800 SIDBG1(SIDBG_INIT, si_ctlp, 4801 "ddi_intr_alloc() failed, rc %d\n", rc); 4802 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4803 return (DDI_FAILURE); 4804 } 4805 4806 /* use interrupt count returned */ 4807 if (actual < count) { 4808 SIDBG2(SIDBG_INIT, si_ctlp, 4809 "Requested: %d, Received: %d", count, actual); 4810 } 4811 4812 si_ctlp->sictl_intr_cnt = actual; 4813 4814 /* 4815 * Get priority for first msi, assume remaining are all the same. 4816 */ 4817 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4818 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4819 SIDBG0(SIDBG_INIT, si_ctlp, "ddi_intr_get_pri() failed"); 4820 4821 /* Free already allocated intr. */ 4822 for (y = 0; y < actual; y++) { 4823 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4824 } 4825 4826 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4827 return (DDI_FAILURE); 4828 } 4829 4830 /* Test for high level mutex. */ 4831 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4832 SIDBG0(SIDBG_INIT, si_ctlp, 4833 "si_add_msi_intrs: Hi level intr not supported"); 4834 4835 /* Free already allocated intr. */ 4836 for (y = 0; y < actual; y++) { 4837 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4838 } 4839 4840 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4841 4842 return (DDI_FAILURE); 4843 } 4844 4845 /* Call ddi_intr_add_handler(). */ 4846 for (x = 0; x < actual; x++) { 4847 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4848 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4849 SIDBG0(SIDBG_INIT, si_ctlp, 4850 "ddi_intr_add_handler() failed"); 4851 4852 /* Free already allocated intr. */ 4853 for (y = 0; y < actual; y++) { 4854 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4855 } 4856 4857 kmem_free(si_ctlp->sictl_htable, 4858 si_ctlp->sictl_intr_size); 4859 return (DDI_FAILURE); 4860 } 4861 } 4862 4863 (void) ddi_intr_get_cap(si_ctlp->sictl_htable[0], 4864 &si_ctlp->sictl_intr_cap); 4865 4866 if (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 4867 /* Call ddi_intr_block_enable() for MSI. */ 4868 (void) ddi_intr_block_enable(si_ctlp->sictl_htable, 4869 si_ctlp->sictl_intr_cnt); 4870 } else { 4871 /* Call ddi_intr_enable() for MSI non block enable. */ 4872 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4873 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4874 } 4875 } 4876 4877 return (DDI_SUCCESS); 4878 } 4879 4880 /* 4881 * Removes the registered interrupts irrespective of whether they 4882 * were legacy or MSI. 4883 */ 4884 static void 4885 si_rem_intrs(si_ctl_state_t *si_ctlp) 4886 { 4887 int x; 4888 4889 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_rem_intrs entered"); 4890 4891 /* Disable all interrupts. */ 4892 if ((si_ctlp->sictl_intr_type == DDI_INTR_TYPE_MSI) && 4893 (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 4894 /* Call ddi_intr_block_disable(). */ 4895 (void) ddi_intr_block_disable(si_ctlp->sictl_htable, 4896 si_ctlp->sictl_intr_cnt); 4897 } else { 4898 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4899 (void) ddi_intr_disable(si_ctlp->sictl_htable[x]); 4900 } 4901 } 4902 4903 /* Call ddi_intr_remove_handler(). */ 4904 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4905 (void) ddi_intr_remove_handler(si_ctlp->sictl_htable[x]); 4906 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4907 } 4908 4909 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4910 } 4911 4912 /* 4913 * Resets either the port or the device connected to the port based on 4914 * the flag variable. 4915 * 4916 * The reset effectively throws away all the pending commands. So, the caller 4917 * has to make provision to handle the pending commands. 4918 * 4919 * After the reset, we wait till the port is ready again. 4920 * 4921 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4922 * before calling us. 4923 * 4924 * Note: Not port-mult aware. 4925 */ 4926 static int 4927 si_reset_dport_wait_till_ready( 4928 si_ctl_state_t *si_ctlp, 4929 si_port_state_t *si_portp, 4930 int port, 4931 int flag) 4932 { 4933 uint32_t port_status; 4934 int loop_count = 0; 4935 sata_device_t sdevice; 4936 uint32_t SStatus; 4937 uint32_t SControl; 4938 4939 _NOTE(ASSUMING_PROTECTED(si_portp)) 4940 4941 if (flag == SI_PORT_RESET) { 4942 ddi_put32(si_ctlp->sictl_port_acc_handle, 4943 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4944 PORT_CONTROL_SET_BITS_PORT_RESET); 4945 4946 /* Port reset is not self clearing. So clear it now. */ 4947 ddi_put32(si_ctlp->sictl_port_acc_handle, 4948 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 4949 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 4950 } else { 4951 /* Reset the device. */ 4952 ddi_put32(si_ctlp->sictl_port_acc_handle, 4953 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4954 PORT_CONTROL_SET_BITS_DEV_RESET); 4955 4956 /* 4957 * tidbit: this bit is self clearing; so there is no need 4958 * for manual clear as we did for port reset. 4959 */ 4960 } 4961 4962 /* Set the reset in progress flag */ 4963 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 4964 si_portp->siport_reset_in_progress = 1; 4965 } 4966 4967 /* 4968 * For some reason, we are losing the interrupt enablement after 4969 * any reset condition. So restore them back now. 4970 */ 4971 SIDBG1(SIDBG_INIT, si_ctlp, 4972 "current interrupt enable set: 0x%x", 4973 ddi_get32(si_ctlp->sictl_port_acc_handle, 4974 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port))); 4975 4976 ddi_put32(si_ctlp->sictl_port_acc_handle, 4977 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 4978 (INTR_COMMAND_COMPLETE | 4979 INTR_COMMAND_ERROR | 4980 INTR_PORT_READY | 4981 INTR_POWER_CHANGE | 4982 INTR_PHYRDY_CHANGE | 4983 INTR_COMWAKE_RECEIVED | 4984 INTR_UNRECOG_FIS | 4985 INTR_DEV_XCHANGED | 4986 INTR_SETDEVBITS_NOTIFY)); 4987 4988 si_enable_port_interrupts(si_ctlp, port); 4989 4990 /* 4991 * Every reset needs a PHY initialization. 4992 * 4993 * The way to initialize the PHY is to write a 1 and then 4994 * a 0 to DET field of SControl register. 4995 */ 4996 4997 /* Fetch the current SControl before writing the DET part with 1. */ 4998 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 4999 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 5000 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 5001 ddi_put32(si_ctlp->sictl_port_acc_handle, 5002 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 5003 SControl); 5004 #ifndef __lock_lint 5005 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 5006 #endif /* __lock_lint */ 5007 5008 /* Now fetch the SControl again and rewrite the DET part with 0 */ 5009 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 5010 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 5011 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 5012 ddi_put32(si_ctlp->sictl_port_acc_handle, 5013 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 5014 SControl); 5015 5016 /* 5017 * PHY may be initialized by now. Check the DET field of SStatus 5018 * to determine if there is a device present. 5019 * 5020 * The DET field is valid only if IPM field indicates that 5021 * the interface is in active state. 5022 */ 5023 5024 loop_count = 0; 5025 do { 5026 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 5027 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 5028 5029 if (SSTATUS_GET_IPM(SStatus) != 5030 SSTATUS_IPM_INTERFACE_ACTIVE) { 5031 /* 5032 * If the interface is not active, the DET field 5033 * is considered not accurate. So we want to 5034 * continue looping. 5035 */ 5036 SSTATUS_SET_DET(SStatus, SSTATUS_DET_NODEV_NOPHY); 5037 } 5038 5039 if (loop_count++ > SI_POLLRATE_SSTATUS) { 5040 /* We are effectively timing out after 0.1 sec. */ 5041 break; 5042 } 5043 5044 /* Wait for 10 millisec */ 5045 #ifndef __lock_lint 5046 delay(SI_10MS_TICKS); 5047 #endif /* __lock_lint */ 5048 5049 } while (SSTATUS_GET_DET(SStatus) != SSTATUS_DET_DEVPRESENT_PHYONLINE); 5050 5051 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 5052 "si_reset_dport_wait_till_ready: loop count: %d, \ 5053 SStatus: 0x%x", 5054 loop_count, 5055 SStatus); 5056 5057 /* Now check for port readiness. */ 5058 loop_count = 0; 5059 do { 5060 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5061 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5062 5063 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5064 /* We are effectively timing out after 0.5 sec. */ 5065 break; 5066 } 5067 5068 /* Wait for 10 millisec */ 5069 #ifndef __lock_lint 5070 delay(SI_10MS_TICKS); 5071 #endif /* __lock_lint */ 5072 5073 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5074 5075 SIDBG3(SIDBG_POLL_LOOP, si_ctlp, 5076 "si_reset_dport_wait_till_ready: loop count: %d, \ 5077 port_status: 0x%x, SStatus: 0x%x", 5078 loop_count, 5079 port_status, 5080 SStatus); 5081 5082 /* Indicate to the framework that a reset has happened. */ 5083 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 5084 5085 bzero((void *)&sdevice, sizeof (sata_device_t)); 5086 sdevice.satadev_addr.cport = port; 5087 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 5088 5089 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 5090 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT; 5091 } else { 5092 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5093 } 5094 sdevice.satadev_state = SATA_DSTATE_RESET | 5095 SATA_DSTATE_PWR_ACTIVE; 5096 if (si_ctlp->sictl_sata_hba_tran) { 5097 sata_hba_event_notify( 5098 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 5099 &sdevice, 5100 SATA_EVNT_DEVICE_RESET); 5101 } 5102 5103 SIDBG0(SIDBG_EVENT, si_ctlp, 5104 "sending event up: SATA_EVNT_RESET"); 5105 } 5106 5107 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5108 (SSTATUS_GET_DET(SStatus) == 5109 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5110 /* The interface is active and the device is present */ 5111 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5112 /* But the port is is not ready for some reason */ 5113 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5114 "si_reset_dport_wait_till_ready failed"); 5115 return (SI_FAILURE); 5116 } 5117 } 5118 5119 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5120 "si_reset_dport_wait_till_ready returning success"); 5121 5122 return (SI_SUCCESS); 5123 } 5124 5125 /* 5126 * Initializes the port. 5127 * 5128 * Initialization effectively throws away all the pending commands on 5129 * the port. So, the caller has to make provision to handle the pending 5130 * commands. 5131 * 5132 * After the port initialization, we wait till the port is ready again. 5133 * 5134 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 5135 * before calling us. 5136 */ 5137 static int 5138 si_initialize_port_wait_till_ready(si_ctl_state_t *si_ctlp, int port) 5139 { 5140 uint32_t port_status; 5141 int loop_count = 0; 5142 uint32_t SStatus; 5143 5144 /* Initialize the port. */ 5145 ddi_put32(si_ctlp->sictl_port_acc_handle, 5146 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 5147 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 5148 5149 /* Wait until Port Ready */ 5150 loop_count = 0; 5151 do { 5152 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5153 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5154 5155 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5156 SIDBG1(SIDBG_INTR, si_ctlp, 5157 "si_initialize_port_wait is timing out: " 5158 "port_status: %x", 5159 port_status); 5160 /* We are effectively timing out after 0.5 sec. */ 5161 break; 5162 } 5163 5164 /* Wait for 10 millisec */ 5165 #ifndef __lock_lint 5166 delay(SI_10MS_TICKS); 5167 #endif /* __lock_lint */ 5168 5169 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5170 5171 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 5172 "si_initialize_port_wait_till_ready: loop count: %d", 5173 loop_count); 5174 5175 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 5176 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 5177 5178 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5179 (SSTATUS_GET_DET(SStatus) == 5180 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5181 /* The interface is active and the device is present */ 5182 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5183 /* But the port is is not ready for some reason */ 5184 return (SI_FAILURE); 5185 } 5186 } 5187 5188 return (SI_SUCCESS); 5189 } 5190 5191 5192 /* 5193 * si_watchdog_handler() calls us if it detects that there are some 5194 * commands which timed out. We recalculate the timed out commands once 5195 * again since some of them may have finished recently. 5196 */ 5197 static void 5198 si_timeout_pkts( 5199 si_ctl_state_t *si_ctlp, 5200 si_port_state_t *si_portp, 5201 int port, 5202 uint32_t timedout_tags) 5203 { 5204 uint32_t slot_status; 5205 uint32_t finished_tags; 5206 5207 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, "si_timeout_pkts entry"); 5208 5209 mutex_enter(&si_portp->siport_mutex); 5210 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5211 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 5212 5213 /* 5214 * Initialize the controller. The only way to timeout the commands 5215 * is to reset or initialize the controller. We mop commands after 5216 * the initialization. 5217 */ 5218 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 5219 5220 /* 5221 * Recompute the timedout tags since some of them may have finished 5222 * meanwhile. 5223 */ 5224 finished_tags = si_portp->siport_pending_tags & 5225 ~slot_status & SI_SLOT_MASK; 5226 timedout_tags &= ~finished_tags; 5227 5228 SIDBG2(SIDBG_TIMEOUT, si_ctlp, 5229 "si_timeout_pkts: finished: %x, timeout: %x", 5230 finished_tags, 5231 timedout_tags); 5232 5233 mutex_exit(&si_portp->siport_mutex); 5234 si_mop_commands(si_ctlp, 5235 si_portp, 5236 port, 5237 slot_status, 5238 0, /* failed_tags */ 5239 timedout_tags, 5240 0, /* aborting_tags */ 5241 0); /* reset_tags */ 5242 5243 } 5244 5245 5246 5247 /* 5248 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 5249 * for long time. 5250 */ 5251 static void 5252 si_watchdog_handler(si_ctl_state_t *si_ctlp) 5253 { 5254 uint32_t pending_tags = 0; 5255 uint32_t timedout_tags = 0; 5256 si_port_state_t *si_portp; 5257 int port; 5258 int tmpslot; 5259 sata_pkt_t *satapkt; 5260 5261 /* max number of cycles this packet should survive */ 5262 int max_life_cycles; 5263 5264 /* how many cycles this packet survived so far */ 5265 int watched_cycles; 5266 5267 mutex_enter(&si_ctlp->sictl_mutex); 5268 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, 5269 "si_watchdog_handler entered"); 5270 5271 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 5272 5273 si_portp = si_ctlp->sictl_ports[port]; 5274 if (si_portp == NULL) { 5275 continue; 5276 } 5277 5278 mutex_enter(&si_portp->siport_mutex); 5279 5280 if (si_portp->siport_port_type == PORT_TYPE_NODEV) { 5281 mutex_exit(&si_portp->siport_mutex); 5282 continue; 5283 } 5284 5285 pending_tags = si_portp->siport_pending_tags; 5286 timedout_tags = 0; 5287 while (pending_tags) { 5288 tmpslot = ddi_ffs(pending_tags) - 1; 5289 if (tmpslot == -1) { 5290 break; 5291 } 5292 satapkt = si_portp->siport_slot_pkts[tmpslot]; 5293 5294 if ((satapkt != NULL) && satapkt->satapkt_time) { 5295 5296 /* 5297 * We are overloading satapkt_hba_driver_private 5298 * with watched_cycle count. 5299 * 5300 * If a packet has survived for more than it's 5301 * max life cycles, it is a candidate for time 5302 * out. 5303 */ 5304 watched_cycles = (int)(intptr_t) 5305 satapkt->satapkt_hba_driver_private; 5306 watched_cycles++; 5307 max_life_cycles = (satapkt->satapkt_time + 5308 si_watchdog_timeout - 1) / 5309 si_watchdog_timeout; 5310 if (watched_cycles > max_life_cycles) { 5311 timedout_tags |= (0x1 << tmpslot); 5312 SIDBG1(SIDBG_TIMEOUT|SIDBG_VERBOSE, 5313 si_ctlp, 5314 "watchdog: timedout_tags: 0x%x", 5315 timedout_tags); 5316 } 5317 satapkt->satapkt_hba_driver_private = 5318 (void *)(intptr_t)watched_cycles; 5319 } 5320 5321 CLEAR_BIT(pending_tags, tmpslot); 5322 } 5323 5324 if (timedout_tags) { 5325 mutex_exit(&si_portp->siport_mutex); 5326 mutex_exit(&si_ctlp->sictl_mutex); 5327 si_timeout_pkts(si_ctlp, si_portp, port, timedout_tags); 5328 mutex_enter(&si_ctlp->sictl_mutex); 5329 mutex_enter(&si_portp->siport_mutex); 5330 } 5331 5332 mutex_exit(&si_portp->siport_mutex); 5333 } 5334 5335 /* Reinstall the watchdog timeout handler. */ 5336 if (!(si_ctlp->sictl_flags & SI_NO_TIMEOUTS)) { 5337 si_ctlp->sictl_timeout_id = 5338 timeout((void (*)(void *))si_watchdog_handler, 5339 (caddr_t)si_ctlp, si_watchdog_tick); 5340 } 5341 mutex_exit(&si_ctlp->sictl_mutex); 5342 } 5343 5344 5345 /* 5346 * Logs the message. 5347 */ 5348 static void 5349 si_log(si_ctl_state_t *si_ctlp, uint_t level, char *fmt, ...) 5350 { 5351 va_list ap; 5352 5353 mutex_enter(&si_log_mutex); 5354 5355 va_start(ap, fmt); 5356 if (si_ctlp) { 5357 (void) sprintf(si_log_buf, "%s-[%d]:", 5358 ddi_get_name(si_ctlp->sictl_devinfop), 5359 ddi_get_instance(si_ctlp->sictl_devinfop)); 5360 } else { 5361 (void) sprintf(si_log_buf, "si3124:"); 5362 } 5363 (void) vsprintf(si_log_buf, fmt, ap); 5364 va_end(ap); 5365 5366 cmn_err(level, "%s", si_log_buf); 5367 5368 mutex_exit(&si_log_mutex); 5369 5370 } 5371 5372 static void 5373 si_copy_out_regs(sata_cmd_t *scmd, fis_reg_h2d_t *fisp) 5374 { 5375 fis_reg_h2d_t fis = *fisp; 5376 5377 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 5378 scmd->satacmd_sec_count_msb = GET_FIS_SECTOR_COUNT_EXP(fis); 5379 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 5380 scmd->satacmd_lba_low_msb = GET_FIS_SECTOR_EXP(fis); 5381 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 5382 scmd->satacmd_lba_mid_msb = GET_FIS_CYL_LOW_EXP(fis); 5383 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 5384 scmd->satacmd_lba_high_msb = GET_FIS_CYL_HI_EXP(fis); 5385 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 5386 scmd->satacmd_sec_count_lsb = GET_FIS_SECTOR_COUNT(fis); 5387 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 5388 scmd->satacmd_lba_low_lsb = GET_FIS_SECTOR(fis); 5389 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 5390 scmd->satacmd_lba_mid_lsb = GET_FIS_CYL_LOW(fis); 5391 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 5392 scmd->satacmd_lba_high_lsb = GET_FIS_CYL_HI(fis); 5393 if (scmd->satacmd_flags.sata_copy_out_device_reg) 5394 scmd->satacmd_device_reg = GET_FIS_DEV_HEAD(fis); 5395 if (scmd->satacmd_flags.sata_copy_out_error_reg) 5396 scmd->satacmd_error_reg = GET_FIS_FEATURES(fis); 5397 } 5398