1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 30 31 /* 32 * SiliconImage 3124/3132 sata controller driver 33 */ 34 35 /* 36 * 37 * 38 * Few Design notes 39 * 40 * 41 * I. General notes 42 * 43 * Even though the driver is named as si3124, it is actually meant to 44 * work with both 3124 and 3132 controllers. 45 * 46 * The current file si3124.c is the main driver code. The si3124reg.h 47 * holds the register definitions from SiI 3124/3132 data sheets. The 48 * si3124var.h holds the driver specific definitions which are not 49 * directly derived from data sheets. 50 * 51 * 52 * II. Data structures 53 * 54 * si_ctl_state_t: This holds the driver private information for each 55 * controller instance. Each of the sata ports within a single 56 * controller are represented by si_port_state_t. The 57 * sictl_global_acc_handle and sictl_global_address map the 58 * controller-wide global register space and are derived from pci 59 * BAR 0. The sictl_port_acc_handle and sictl_port_addr map the 60 * per-port register space and are derived from pci BAR 1. 61 * 62 * si_port_state_t: This holds the per port information. The siport_mutex 63 * holds the per port mutex. The siport_pending_tags is the bit mask of 64 * commands posted to controller. The siport_slot_pkts[] holds the 65 * pending sata packets. The siport_port_type holds the device type 66 * connected directly to the port while the siport_portmult_state 67 * holds the similar information for the devices behind a port 68 * multiplier. 69 * 70 * si_prb_t: This contains the PRB being posted to the controller. 71 * The two SGE entries contained within si_prb_t itself are not 72 * really used to hold any scatter gather entries. The scatter gather 73 * list is maintained external to PRB and is linked from one 74 * of the contained SGEs inside the PRB. For atapi devices, the 75 * first contained SGE holds the PACKET and second contained 76 * SGE holds the link to an external SGT. For non-atapi devices, 77 * the first contained SGE works as link to external SGT while 78 * second SGE is blank. 79 * 80 * external SGT tables: The external SGT tables pointed to from 81 * within si_prb_t are actually abstracted as si_sgblock_t. Each 82 * si_sgblock_t contains SI_MAX_SGT_TABLES_PER_PRB number of 83 * SGT tables linked in a chain. Currently this max value of 84 * SGT tables per block is hard coded as 10 which translates 85 * to a maximum of 31 dma cookies per single dma transfer. 86 * 87 * 88 * III. Driver operation 89 * 90 * Command Issuing: We use the "indirect method of command issuance". The 91 * PRB contains the command [and atapi PACKET] and a link to the 92 * external SGT chain. We write the physical address of the PRB into 93 * command activation register. There are 31 command slots for 94 * each port. After posting a command, we remember the posted slot & 95 * the sata packet in siport_pending_tags & siport_slot_pkts[] 96 * respectively. 97 * 98 * Command completion: On a successful completion, intr_command_complete() 99 * receives the control. The slot_status register holds the outstanding 100 * commands. Any reading of slot_status register automatically clears 101 * the interrupt. By comparing the slot_status register contents with 102 * per port siport_pending_tags, we determine which of the previously 103 * posted commands have finished. 104 * 105 * Timeout handling: Every 5 seconds, the watchdog handler scans thru the 106 * pending packets. The satapkt->satapkt_hba_driver_private field is 107 * overloaded with the count of watchdog cycles a packet has survived. 108 * If a packet has not completed within satapkt->satapkt_time, it is 109 * failed with error code of SATA_PKT_TIMEOUT. There is one watchdog 110 * handler running for each instance of controller. 111 * 112 * Error handling: For 3124, whenever any single command has encountered 113 * an error, the whole port execution completely stalls; there is no 114 * way of canceling or aborting the particular failed command. If 115 * the port is connected to a port multiplier, we can however RESUME 116 * other non-error devices connected to the port multiplier. 117 * The only way to recover the failed commands is to either initialize 118 * the port or reset the port/device. Both port initialize and reset 119 * operations result in discarding any of pending commands on the port. 120 * All such discarded commands are sent up to framework with PKT_RESET 121 * satapkt_reason. The assumption is that framework [and sd] would 122 * retry these commands again. The failed command itself however is 123 * sent up with PKT_DEV_ERROR. 124 * 125 * Here is the implementation strategy based on SiliconImage email 126 * regarding how they handle the errors for their Windows driver: 127 * 128 * a) for DEVICEERROR: 129 * If the port is connected to port multiplier, then 130 * 1) Resume the port 131 * 2) Wait for all the non-failed commands to complete 132 * 3) Perform a Port Initialize 133 * 134 * If the port is not connected to port multiplier, issue 135 * a Port Initialize. 136 * 137 * b) for SDBERROR: [SDBERROR means failed command is an NCQ command] 138 * Handle exactly like DEVICEERROR handling. 139 * After the Port Initialize done, do a Read Log Extended. 140 * 141 * c) for SENDFISERROR: 142 * If the port is connected to port multiplier, then 143 * 1) Resume the port 144 * 2) Wait for all the non-failed commands to complete 145 * 3) Perform a Port Initialize 146 * 147 * If the port is not connected to port multiplier, issue 148 * a Device Reset. 149 * 150 * d) for DATAFISERROR: 151 * If the port was executing an NCQ command, issue a Device 152 * Reset. 153 * 154 * Otherwise, follow the same error recovery as DEVICEERROR. 155 * 156 * e) for any other error, simply issue a Device Reset. 157 * 158 * To synchronize the interactions between various control flows (e.g. 159 * error recovery, timeout handling, si_poll_timeout, incoming flow 160 * from framework etc.), the following precautions are taken care of: 161 * a) During mopping_in_progress, no more commands are 162 * accepted from the framework. 163 * 164 * b) While draining the port multiplier commands, we should 165 * handle the possibility of any of the other waited commands 166 * failing (possibly with a different error code) 167 * 168 * Atapi handling: For atapi devices, we use the first SGE within the PRB 169 * to fill the scsi cdb while the second SGE points to external SGT. 170 * 171 * Queuing: Queue management is achieved external to the driver inside sd. 172 * Based on sata_hba_tran->qdepth and IDENTIFY data, the framework 173 * enables or disables the queuing. The qdepth for si3124 is 31 174 * commands. 175 * 176 * Port Multiplier: Enumeration of port multiplier is handled during the 177 * controller initialization and also during the a hotplug operation. 178 * Current logic takes care of situation where a port multiplier 179 * is hotplugged into a port which had a cdisk connected previously 180 * and vice versa. 181 * 182 * Register poll timeouts: Currently most of poll timeouts on register 183 * reads is set to 0.5 seconds except for a value of 10 seconds 184 * while reading the device signature. [Such a big timeout values 185 * for device signature were found needed during cold reboots 186 * for devices behind port multiplier]. 187 * 188 * 189 * IV. Known Issues 190 * 191 * 1) Currently the atapi packet length is hard coded to 12 bytes 192 * This is wrong. The framework should determine it just like they 193 * determine ad_cdb_len in legacy atapi.c. It should even reject 194 * init_pkt() for greater CDB lengths. See atapi.c. Revisit this 195 * in 2nd phase of framework project. 196 * 197 * 2) Do real REQUEST SENSE command instead of faking for ATAPI case. 198 * 199 */ 200 201 202 #include <sys/note.h> 203 #include <sys/scsi/scsi.h> 204 #include <sys/pci.h> 205 #include <sys/sata/sata_hba.h> 206 #include <sys/sata/adapters/si3124/si3124reg.h> 207 #include <sys/sata/adapters/si3124/si3124var.h> 208 209 /* 210 * Function prototypes for driver entry points 211 */ 212 static int si_attach(dev_info_t *, ddi_attach_cmd_t); 213 static int si_detach(dev_info_t *, ddi_detach_cmd_t); 214 static int si_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 215 static int si_power(dev_info_t *, int, int); 216 217 /* 218 * Function prototypes for SATA Framework interfaces 219 */ 220 static int si_register_sata_hba_tran(si_ctl_state_t *); 221 static int si_unregister_sata_hba_tran(si_ctl_state_t *); 222 223 static int si_tran_probe_port(dev_info_t *, sata_device_t *); 224 static int si_tran_start(dev_info_t *, sata_pkt_t *spkt); 225 static int si_tran_abort(dev_info_t *, sata_pkt_t *, int); 226 static int si_tran_reset_dport(dev_info_t *, sata_device_t *); 227 static int si_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 228 static int si_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 229 230 /* 231 * Local function prototypes 232 */ 233 234 static int si_alloc_port_state(si_ctl_state_t *, int); 235 static void si_dealloc_port_state(si_ctl_state_t *, int); 236 static int si_alloc_sgbpool(si_ctl_state_t *, int); 237 static void si_dealloc_sgbpool(si_ctl_state_t *, int); 238 static int si_alloc_prbpool(si_ctl_state_t *, int); 239 static void si_dealloc_prbpool(si_ctl_state_t *, int); 240 241 static void si_find_dev_signature(si_ctl_state_t *, si_port_state_t *, 242 int, int); 243 static void si_poll_cmd(si_ctl_state_t *, si_port_state_t *, int, int, 244 sata_pkt_t *); 245 static int si_claim_free_slot(si_ctl_state_t *, si_port_state_t *, int); 246 static int si_deliver_satapkt(si_ctl_state_t *, si_port_state_t *, int, 247 sata_pkt_t *); 248 249 static int si_initialize_controller(si_ctl_state_t *); 250 static void si_deinititalize_controller(si_ctl_state_t *); 251 static void si_init_port(si_ctl_state_t *, int); 252 static int si_enumerate_port_multiplier(si_ctl_state_t *, 253 si_port_state_t *, int); 254 static int si_read_portmult_reg(si_ctl_state_t *, si_port_state_t *, 255 int, int, int, uint32_t *); 256 static int si_write_portmult_reg(si_ctl_state_t *, si_port_state_t *, 257 int, int, int, uint32_t); 258 static void si_set_sense_data(sata_pkt_t *, int); 259 260 static uint_t si_intr(caddr_t, caddr_t); 261 static int si_intr_command_complete(si_ctl_state_t *, 262 si_port_state_t *, int); 263 static int si_intr_command_error(si_ctl_state_t *, 264 si_port_state_t *, int); 265 static void si_error_recovery_DEVICEERROR(si_ctl_state_t *, 266 si_port_state_t *, int); 267 static void si_error_recovery_SDBERROR(si_ctl_state_t *, 268 si_port_state_t *, int); 269 static void si_error_recovery_DATAFISERROR(si_ctl_state_t *, 270 si_port_state_t *, int); 271 static void si_error_recovery_SENDFISERROR(si_ctl_state_t *, 272 si_port_state_t *, int); 273 static void si_error_recovery_default(si_ctl_state_t *, 274 si_port_state_t *, int); 275 static uint8_t si_read_log_ext(si_ctl_state_t *, 276 si_port_state_t *si_portp, int); 277 static void si_log_error_message(si_ctl_state_t *, int, uint32_t); 278 static int si_intr_port_ready(si_ctl_state_t *, si_port_state_t *, int); 279 static int si_intr_pwr_change(si_ctl_state_t *, si_port_state_t *, int); 280 static int si_intr_phy_ready_change(si_ctl_state_t *, si_port_state_t *, int); 281 static int si_intr_comwake_rcvd(si_ctl_state_t *, si_port_state_t *, int); 282 static int si_intr_unrecognised_fis(si_ctl_state_t *, si_port_state_t *, int); 283 static int si_intr_dev_xchanged(si_ctl_state_t *, si_port_state_t *, int); 284 static int si_intr_decode_err_threshold(si_ctl_state_t *, 285 si_port_state_t *, int); 286 static int si_intr_crc_err_threshold(si_ctl_state_t *, si_port_state_t *, int); 287 static int si_intr_handshake_err_threshold(si_ctl_state_t *, 288 si_port_state_t *, int); 289 static int si_intr_set_devbits_notify(si_ctl_state_t *, si_port_state_t *, int); 290 static void si_handle_attention_raised(si_ctl_state_t *, 291 si_port_state_t *, int); 292 293 static void si_enable_port_interrupts(si_ctl_state_t *, int); 294 static void si_enable_all_interrupts(si_ctl_state_t *); 295 static void si_disable_port_interrupts(si_ctl_state_t *, int); 296 static void si_disable_all_interrupts(si_ctl_state_t *); 297 static void fill_dev_sregisters(si_ctl_state_t *, int, sata_device_t *); 298 static int si_add_legacy_intrs(si_ctl_state_t *); 299 static int si_add_msi_intrs(si_ctl_state_t *); 300 static void si_rem_intrs(si_ctl_state_t *); 301 302 static int si_reset_dport_wait_till_ready(si_ctl_state_t *, 303 si_port_state_t *, int, int); 304 static int si_initialize_port_wait_till_ready(si_ctl_state_t *, int); 305 306 static void si_timeout_pkts(si_ctl_state_t *, si_port_state_t *, int, uint32_t); 307 static void si_watchdog_handler(si_ctl_state_t *); 308 309 static void si_log(si_ctl_state_t *, uint_t, char *, ...); 310 311 static void si_copy_out_regs(sata_cmd_t *, fis_reg_h2d_t *); 312 313 /* 314 * DMA attributes for the data buffer 315 */ 316 317 static ddi_dma_attr_t buffer_dma_attr = { 318 DMA_ATTR_V0, /* dma_attr_version */ 319 0, /* dma_attr_addr_lo: lowest bus address */ 320 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 321 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 322 1, /* dma_attr_align: single byte aligned */ 323 1, /* dma_attr_burstsizes */ 324 1, /* dma_attr_minxfer */ 325 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 326 0xffffffffull, /* dma_attr_seg */ 327 SI_MAX_SGL_LENGTH, /* dma_attr_sgllen */ 328 512, /* dma_attr_granular */ 329 0, /* dma_attr_flags */ 330 }; 331 332 /* 333 * DMA attributes for incore RPB and SGT pool 334 */ 335 static ddi_dma_attr_t prb_sgt_dma_attr = { 336 DMA_ATTR_V0, /* dma_attr_version */ 337 0, /* dma_attr_addr_lo: lowest bus address */ 338 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 339 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 340 8, /* dma_attr_align: quad word aligned */ 341 1, /* dma_attr_burstsizes */ 342 1, /* dma_attr_minxfer */ 343 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 344 0xffffffffull, /* dma_attr_seg */ 345 1, /* dma_attr_sgllen */ 346 1, /* dma_attr_granular */ 347 0, /* dma_attr_flags */ 348 }; 349 350 /* Device access attributes */ 351 static ddi_device_acc_attr_t accattr = { 352 DDI_DEVICE_ATTR_V0, 353 DDI_STRUCTURE_LE_ACC, 354 DDI_STRICTORDER_ACC 355 }; 356 357 358 static struct dev_ops sictl_dev_ops = { 359 DEVO_REV, /* devo_rev */ 360 0, /* refcnt */ 361 si_getinfo, /* info */ 362 nulldev, /* identify */ 363 nulldev, /* probe */ 364 si_attach, /* attach */ 365 si_detach, /* detach */ 366 nodev, /* no reset */ 367 (struct cb_ops *)0, /* driver operations */ 368 NULL, /* bus operations */ 369 si_power /* power */ 370 }; 371 372 static sata_tran_hotplug_ops_t si_tran_hotplug_ops = { 373 SATA_TRAN_HOTPLUG_OPS_REV_1, 374 si_tran_hotplug_port_activate, 375 si_tran_hotplug_port_deactivate 376 }; 377 378 379 static int si_watchdog_timeout = 5; /* 5 seconds */ 380 static int si_watchdog_tick; 381 382 extern struct mod_ops mod_driverops; 383 384 static struct modldrv modldrv = { 385 &mod_driverops, /* driverops */ 386 "si3124 driver v%I%", 387 &sictl_dev_ops, /* driver ops */ 388 }; 389 390 static struct modlinkage modlinkage = { 391 MODREV_1, 392 &modldrv, 393 NULL 394 }; 395 396 397 /* The following are needed for si_log() */ 398 static kmutex_t si_log_mutex; 399 static char si_log_buf[512]; 400 uint32_t si_debug_flags = 0x0; 401 static int is_msi_supported = 0; 402 403 /* Opaque state pointer to be initialized by ddi_soft_state_init() */ 404 static void *si_statep = NULL; 405 406 /* 407 * si3124 module initialization. 408 * 409 */ 410 int 411 _init(void) 412 { 413 int error; 414 415 error = ddi_soft_state_init(&si_statep, sizeof (si_ctl_state_t), 0); 416 if (error != 0) { 417 return (error); 418 } 419 420 mutex_init(&si_log_mutex, NULL, MUTEX_DRIVER, NULL); 421 422 if ((error = sata_hba_init(&modlinkage)) != 0) { 423 mutex_destroy(&si_log_mutex); 424 ddi_soft_state_fini(&si_statep); 425 return (error); 426 } 427 428 error = mod_install(&modlinkage); 429 if (error != 0) { 430 sata_hba_fini(&modlinkage); 431 mutex_destroy(&si_log_mutex); 432 ddi_soft_state_fini(&si_statep); 433 return (error); 434 } 435 436 si_watchdog_tick = drv_usectohz((clock_t)si_watchdog_timeout * 1000000); 437 438 return (error); 439 } 440 441 /* 442 * si3124 module uninitialize. 443 * 444 */ 445 int 446 _fini(void) 447 { 448 int error; 449 450 error = mod_remove(&modlinkage); 451 if (error != 0) { 452 return (error); 453 } 454 455 /* Remove the resources allocated in _init(). */ 456 sata_hba_fini(&modlinkage); 457 mutex_destroy(&si_log_mutex); 458 ddi_soft_state_fini(&si_statep); 459 460 return (error); 461 } 462 463 /* 464 * _info entry point 465 * 466 */ 467 int 468 _info(struct modinfo *modinfop) 469 { 470 return (mod_info(&modlinkage, modinfop)); 471 } 472 473 474 /* 475 * The attach entry point for dev_ops. 476 * 477 * We initialize the controller, initialize the soft state, register 478 * the interrupt handlers and then register ourselves with sata framework. 479 */ 480 static int 481 si_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 482 { 483 si_ctl_state_t *si_ctlp; 484 int instance; 485 int status; 486 int attach_state; 487 int intr_types; 488 sata_device_t sdevice; 489 490 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_attach enter"); 491 instance = ddi_get_instance(dip); 492 attach_state = ATTACH_PROGRESS_NONE; 493 494 switch (cmd) { 495 496 case DDI_ATTACH: 497 498 /* Allocate si_softc. */ 499 status = ddi_soft_state_zalloc(si_statep, instance); 500 if (status != DDI_SUCCESS) { 501 goto err_out; 502 } 503 504 si_ctlp = ddi_get_soft_state(si_statep, instance); 505 si_ctlp->sictl_devinfop = dip; 506 507 attach_state |= ATTACH_PROGRESS_STATEP_ALLOC; 508 509 /* Configure pci config space handle. */ 510 status = pci_config_setup(dip, &si_ctlp->sictl_pci_conf_handle); 511 if (status != DDI_SUCCESS) { 512 goto err_out; 513 } 514 515 si_ctlp->sictl_devid = 516 pci_config_get16(si_ctlp->sictl_pci_conf_handle, 517 PCI_CONF_DEVID); 518 if (si_ctlp->sictl_devid == SI3132_DEV_ID) { 519 si_ctlp->sictl_num_ports = SI3132_MAX_PORTS; 520 } else { 521 si_ctlp->sictl_num_ports = SI3124_MAX_PORTS; 522 } 523 524 attach_state |= ATTACH_PROGRESS_CONF_HANDLE; 525 526 /* Now map the bar0; the bar0 contains the global registers. */ 527 status = ddi_regs_map_setup(dip, 528 PCI_BAR0, 529 (caddr_t *)&si_ctlp->sictl_global_addr, 530 0, 531 0, 532 &accattr, 533 &si_ctlp->sictl_global_acc_handle); 534 if (status != DDI_SUCCESS) { 535 goto err_out; 536 } 537 538 attach_state |= ATTACH_PROGRESS_BAR0_MAP; 539 540 /* Now map bar1; the bar1 contains the port registers. */ 541 status = ddi_regs_map_setup(dip, 542 PCI_BAR1, 543 (caddr_t *)&si_ctlp->sictl_port_addr, 544 0, 545 0, 546 &accattr, 547 &si_ctlp->sictl_port_acc_handle); 548 if (status != DDI_SUCCESS) { 549 goto err_out; 550 } 551 552 attach_state |= ATTACH_PROGRESS_BAR1_MAP; 553 554 /* 555 * Disable all the interrupts before adding interrupt 556 * handler(s). The interrupts shall be re-enabled selectively 557 * out of si_init_port(). 558 */ 559 si_disable_all_interrupts(si_ctlp); 560 561 /* Get supported interrupt types. */ 562 if (ddi_intr_get_supported_types(dip, &intr_types) 563 != DDI_SUCCESS) { 564 SIDBG0(SIDBG_INIT, NULL, 565 "ddi_intr_get_supported_types failed"); 566 goto err_out; 567 } 568 569 SIDBG1(SIDBG_INIT, NULL, 570 "ddi_intr_get_supported_types() returned: 0x%x", 571 intr_types); 572 573 if (is_msi_supported && (intr_types & DDI_INTR_TYPE_MSI)) { 574 SIDBG0(SIDBG_INIT, NULL, "Using MSI interrupt type"); 575 576 /* 577 * Try MSI first, but fall back to legacy if MSI 578 * attach fails. 579 */ 580 if (si_add_msi_intrs(si_ctlp) == DDI_SUCCESS) { 581 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_MSI; 582 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 583 SIDBG0(SIDBG_INIT, NULL, 584 "MSI interrupt setup done"); 585 } else { 586 SIDBG0(SIDBG_INIT, NULL, 587 "MSI registration failed " 588 "will try Legacy interrupts"); 589 } 590 } 591 592 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED) && 593 (intr_types & DDI_INTR_TYPE_FIXED)) { 594 /* 595 * Either the MSI interrupt setup has failed or only 596 * fixed interrupts are available on the system. 597 */ 598 SIDBG0(SIDBG_INIT, NULL, "Using Legacy interrupt type"); 599 600 if (si_add_legacy_intrs(si_ctlp) == DDI_SUCCESS) { 601 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_FIXED; 602 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 603 SIDBG0(SIDBG_INIT, NULL, 604 "Legacy interrupt setup done"); 605 } else { 606 SIDBG0(SIDBG_INIT, NULL, 607 "legacy interrupt setup failed"); 608 goto err_out; 609 } 610 } 611 612 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED)) { 613 SIDBG0(SIDBG_INIT, NULL, 614 "si3124: No interrupts registered"); 615 goto err_out; 616 } 617 618 619 /* Initialize the mutex. */ 620 mutex_init(&si_ctlp->sictl_mutex, NULL, MUTEX_DRIVER, 621 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 622 623 attach_state |= ATTACH_PROGRESS_MUTEX_INIT; 624 625 /* 626 * Initialize the controller and driver core. 627 */ 628 si_ctlp->sictl_flags |= SI_ATTACH; 629 status = si_initialize_controller(si_ctlp); 630 si_ctlp->sictl_flags &= ~SI_ATTACH; 631 if (status) { 632 goto err_out; 633 } 634 635 attach_state |= ATTACH_PROGRESS_HW_INIT; 636 637 if (si_register_sata_hba_tran(si_ctlp)) { 638 SIDBG0(SIDBG_INIT, NULL, 639 "si3124: setting sata hba tran failed"); 640 goto err_out; 641 } 642 643 si_ctlp->sictl_timeout_id = timeout( 644 (void (*)(void *))si_watchdog_handler, 645 (caddr_t)si_ctlp, si_watchdog_tick); 646 647 si_ctlp->sictl_power_level = PM_LEVEL_D0; 648 649 return (DDI_SUCCESS); 650 651 case DDI_RESUME: 652 si_ctlp = ddi_get_soft_state(si_statep, instance); 653 654 status = si_initialize_controller(si_ctlp); 655 if (status) { 656 return (DDI_FAILURE); 657 } 658 659 si_ctlp->sictl_timeout_id = timeout( 660 (void (*)(void *))si_watchdog_handler, 661 (caddr_t)si_ctlp, si_watchdog_tick); 662 663 (void) pm_power_has_changed(dip, 0, PM_LEVEL_D0); 664 665 /* Notify SATA framework about RESUME. */ 666 if (sata_hba_attach(si_ctlp->sictl_devinfop, 667 si_ctlp->sictl_sata_hba_tran, 668 DDI_RESUME) != DDI_SUCCESS) { 669 return (DDI_FAILURE); 670 } 671 672 /* 673 * Notify the "framework" that it should reprobe ports to see 674 * if any device got changed while suspended. 675 */ 676 bzero((void *)&sdevice, sizeof (sata_device_t)); 677 sata_hba_event_notify(dip, &sdevice, 678 SATA_EVNT_PWR_LEVEL_CHANGED); 679 SIDBG0(SIDBG_INIT|SIDBG_EVENT, si_ctlp, 680 "sending event up: SATA_EVNT_PWR_LEVEL_CHANGED"); 681 682 (void) pm_idle_component(si_ctlp->sictl_devinfop, 0); 683 684 si_ctlp->sictl_power_level = PM_LEVEL_D0; 685 686 return (DDI_SUCCESS); 687 688 default: 689 return (DDI_FAILURE); 690 691 } 692 693 err_out: 694 if (attach_state & ATTACH_PROGRESS_HW_INIT) { 695 si_ctlp->sictl_flags |= SI_DETACH; 696 /* We want to set SI_DETACH to deallocate all memory */ 697 si_deinititalize_controller(si_ctlp); 698 si_ctlp->sictl_flags &= ~SI_DETACH; 699 } 700 701 if (attach_state & ATTACH_PROGRESS_MUTEX_INIT) { 702 mutex_destroy(&si_ctlp->sictl_mutex); 703 } 704 705 if (attach_state & ATTACH_PROGRESS_INTR_ADDED) { 706 si_rem_intrs(si_ctlp); 707 } 708 709 if (attach_state & ATTACH_PROGRESS_BAR1_MAP) { 710 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 711 } 712 713 if (attach_state & ATTACH_PROGRESS_BAR0_MAP) { 714 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 715 } 716 717 if (attach_state & ATTACH_PROGRESS_CONF_HANDLE) { 718 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 719 } 720 721 if (attach_state & ATTACH_PROGRESS_STATEP_ALLOC) { 722 ddi_soft_state_free(si_statep, instance); 723 } 724 725 return (DDI_FAILURE); 726 } 727 728 729 /* 730 * The detach entry point for dev_ops. 731 * 732 * We undo the things we did in si_attach(). 733 */ 734 static int 735 si_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 736 { 737 si_ctl_state_t *si_ctlp; 738 int instance; 739 740 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_detach enter"); 741 instance = ddi_get_instance(dip); 742 si_ctlp = ddi_get_soft_state(si_statep, instance); 743 744 switch (cmd) { 745 746 case DDI_DETACH: 747 748 mutex_enter(&si_ctlp->sictl_mutex); 749 750 /* disable the interrupts for an uninterrupted detach */ 751 si_disable_all_interrupts(si_ctlp); 752 753 mutex_exit(&si_ctlp->sictl_mutex); 754 /* unregister from the sata framework. */ 755 if (si_unregister_sata_hba_tran(si_ctlp) != SI_SUCCESS) { 756 si_enable_all_interrupts(si_ctlp); 757 return (DDI_FAILURE); 758 } 759 mutex_enter(&si_ctlp->sictl_mutex); 760 761 /* now cancel the timeout handler. */ 762 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 763 (void) untimeout(si_ctlp->sictl_timeout_id); 764 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 765 766 /* deinitialize the controller. */ 767 si_ctlp->sictl_flags |= SI_DETACH; 768 si_deinititalize_controller(si_ctlp); 769 si_ctlp->sictl_flags &= ~SI_DETACH; 770 771 /* destroy any mutexes */ 772 mutex_exit(&si_ctlp->sictl_mutex); 773 mutex_destroy(&si_ctlp->sictl_mutex); 774 775 /* remove the interrupts */ 776 si_rem_intrs(si_ctlp); 777 778 /* remove the reg maps. */ 779 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 780 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 781 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 782 783 /* free the soft state. */ 784 ddi_soft_state_free(si_statep, instance); 785 786 return (DDI_SUCCESS); 787 788 case DDI_SUSPEND: 789 /* Inform SATA framework */ 790 if (sata_hba_detach(dip, cmd) != DDI_SUCCESS) { 791 return (DDI_FAILURE); 792 } 793 794 mutex_enter(&si_ctlp->sictl_mutex); 795 796 /* 797 * Device needs to be at full power in case it is needed to 798 * handle dump(9e) to save CPR state after DDI_SUSPEND 799 * completes. This is OK since presumably power will be 800 * removed anyways. No outstanding transactions should be 801 * on the controller since the children are already quiesed. 802 * 803 * If any ioctls/cfgadm support is added that touches 804 * hardware, those entry points will need to check for 805 * suspend and then block or return errors until resume. 806 * 807 */ 808 if (pm_busy_component(si_ctlp->sictl_devinfop, 0) == 809 DDI_SUCCESS) { 810 mutex_exit(&si_ctlp->sictl_mutex); 811 (void) pm_raise_power(si_ctlp->sictl_devinfop, 0, 812 PM_LEVEL_D0); 813 mutex_enter(&si_ctlp->sictl_mutex); 814 } 815 816 si_deinititalize_controller(si_ctlp); 817 818 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 819 (void) untimeout(si_ctlp->sictl_timeout_id); 820 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 821 822 SIDBG1(SIDBG_POWER, NULL, "si3124%d: DDI_SUSPEND", instance); 823 824 mutex_exit(&si_ctlp->sictl_mutex); 825 826 return (DDI_SUCCESS); 827 828 default: 829 return (DDI_FAILURE); 830 831 } 832 833 } 834 835 static int 836 si_power(dev_info_t *dip, int component, int level) 837 { 838 #ifndef __lock_lint 839 _NOTE(ARGUNUSED(component)) 840 #endif /* __lock_lint */ 841 842 si_ctl_state_t *si_ctlp; 843 int instance = ddi_get_instance(dip); 844 int rval = DDI_SUCCESS; 845 int old_level; 846 sata_device_t sdevice; 847 848 si_ctlp = ddi_get_soft_state(si_statep, instance); 849 850 if (si_ctlp == NULL) { 851 return (DDI_FAILURE); 852 } 853 854 SIDBG0(SIDBG_ENTRY, NULL, "si_power enter"); 855 856 mutex_enter(&si_ctlp->sictl_mutex); 857 old_level = si_ctlp->sictl_power_level; 858 859 switch (level) { 860 case PM_LEVEL_D0: /* fully on */ 861 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 862 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D0); 863 #ifndef __lock_lint 864 delay(drv_usectohz(10000)); 865 #endif /* __lock_lint */ 866 si_ctlp->sictl_power_level = PM_LEVEL_D0; 867 (void) pci_restore_config_regs(si_ctlp->sictl_devinfop); 868 869 SIDBG2(SIDBG_POWER, si_ctlp, 870 "si3124%d: turning power ON. old level %d", 871 instance, old_level); 872 /* 873 * If called from attach, just raise device power, 874 * restore config registers (if they were saved 875 * from a previous detach that lowered power), 876 * and exit. 877 */ 878 if (si_ctlp->sictl_flags & SI_ATTACH) 879 break; 880 881 mutex_exit(&si_ctlp->sictl_mutex); 882 (void) si_initialize_controller(si_ctlp); 883 mutex_enter(&si_ctlp->sictl_mutex); 884 885 si_ctlp->sictl_timeout_id = timeout( 886 (void (*)(void *))si_watchdog_handler, 887 (caddr_t)si_ctlp, si_watchdog_tick); 888 889 bzero((void *)&sdevice, sizeof (sata_device_t)); 890 sata_hba_event_notify( 891 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 892 &sdevice, SATA_EVNT_PWR_LEVEL_CHANGED); 893 SIDBG0(SIDBG_EVENT|SIDBG_POWER, si_ctlp, 894 "sending event up: PWR_LEVEL_CHANGED"); 895 896 break; 897 898 case PM_LEVEL_D3: /* fully off */ 899 if (!(si_ctlp->sictl_flags & SI_DETACH)) { 900 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 901 (void) untimeout(si_ctlp->sictl_timeout_id); 902 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 903 904 si_deinititalize_controller(si_ctlp); 905 906 si_ctlp->sictl_power_level = PM_LEVEL_D3; 907 } 908 909 (void) pci_save_config_regs(si_ctlp->sictl_devinfop); 910 911 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 912 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D3HOT); 913 914 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 915 "old level %d", instance, old_level); 916 917 break; 918 919 default: 920 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 921 "old level %d", instance, old_level); 922 rval = DDI_FAILURE; 923 break; 924 } 925 926 mutex_exit(&si_ctlp->sictl_mutex); 927 928 return (rval); 929 } 930 931 932 /* 933 * The info entry point for dev_ops. 934 * 935 */ 936 static int 937 si_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 938 void *arg, 939 void **result) 940 { 941 #ifndef __lock_lint 942 _NOTE(ARGUNUSED(dip)) 943 #endif /* __lock_lint */ 944 si_ctl_state_t *si_ctlp; 945 int instance; 946 dev_t dev; 947 948 dev = (dev_t)arg; 949 instance = getminor(dev); 950 951 switch (infocmd) { 952 case DDI_INFO_DEVT2DEVINFO: 953 si_ctlp = ddi_get_soft_state(si_statep, instance); 954 if (si_ctlp != NULL) { 955 *result = si_ctlp->sictl_devinfop; 956 return (DDI_SUCCESS); 957 } else { 958 *result = NULL; 959 return (DDI_FAILURE); 960 } 961 case DDI_INFO_DEVT2INSTANCE: 962 *(int *)result = instance; 963 break; 964 default: 965 break; 966 } 967 return (DDI_SUCCESS); 968 } 969 970 971 972 /* 973 * Registers the si3124 with sata framework. 974 */ 975 static int 976 si_register_sata_hba_tran(si_ctl_state_t *si_ctlp) 977 { 978 struct sata_hba_tran *sata_hba_tran; 979 980 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 981 "si_register_sata_hba_tran entry"); 982 983 mutex_enter(&si_ctlp->sictl_mutex); 984 985 /* Allocate memory for the sata_hba_tran */ 986 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 987 988 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV; 989 sata_hba_tran->sata_tran_hba_dip = si_ctlp->sictl_devinfop; 990 sata_hba_tran->sata_tran_hba_dma_attr = &buffer_dma_attr; 991 992 sata_hba_tran->sata_tran_hba_num_cports = si_ctlp->sictl_num_ports; 993 sata_hba_tran->sata_tran_hba_features_support = 0; 994 sata_hba_tran->sata_tran_hba_qdepth = SI_NUM_SLOTS; 995 996 sata_hba_tran->sata_tran_probe_port = si_tran_probe_port; 997 sata_hba_tran->sata_tran_start = si_tran_start; 998 sata_hba_tran->sata_tran_abort = si_tran_abort; 999 sata_hba_tran->sata_tran_reset_dport = si_tran_reset_dport; 1000 sata_hba_tran->sata_tran_selftest = NULL; 1001 sata_hba_tran->sata_tran_hotplug_ops = &si_tran_hotplug_ops; 1002 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1003 sata_hba_tran->sata_tran_ioctl = NULL; 1004 mutex_exit(&si_ctlp->sictl_mutex); 1005 1006 /* Attach it to SATA framework */ 1007 if (sata_hba_attach(si_ctlp->sictl_devinfop, sata_hba_tran, DDI_ATTACH) 1008 != DDI_SUCCESS) { 1009 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1010 return (SI_FAILURE); 1011 } 1012 1013 mutex_enter(&si_ctlp->sictl_mutex); 1014 si_ctlp->sictl_sata_hba_tran = sata_hba_tran; 1015 mutex_exit(&si_ctlp->sictl_mutex); 1016 1017 return (SI_SUCCESS); 1018 } 1019 1020 1021 /* 1022 * Unregisters the si3124 with sata framework. 1023 */ 1024 static int 1025 si_unregister_sata_hba_tran(si_ctl_state_t *si_ctlp) 1026 { 1027 1028 /* Detach from the SATA framework. */ 1029 if (sata_hba_detach(si_ctlp->sictl_devinfop, DDI_DETACH) != 1030 DDI_SUCCESS) { 1031 return (SI_FAILURE); 1032 } 1033 1034 /* Deallocate sata_hba_tran. */ 1035 kmem_free((void *)si_ctlp->sictl_sata_hba_tran, 1036 sizeof (sata_hba_tran_t)); 1037 1038 si_ctlp->sictl_sata_hba_tran = NULL; 1039 1040 return (SI_SUCCESS); 1041 } 1042 1043 /* 1044 * Called by sata framework to probe a port. We return the 1045 * cached information from a previous hardware probe. 1046 * 1047 * The actual hardware probing itself was done either from within 1048 * si_initialize_controller() during the driver attach or 1049 * from a phy ready change interrupt handler. 1050 */ 1051 static int 1052 si_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1053 { 1054 1055 si_ctl_state_t *si_ctlp; 1056 uint8_t cport = sd->satadev_addr.cport; 1057 uint8_t pmport = sd->satadev_addr.pmport; 1058 uint8_t qual = sd->satadev_addr.qual; 1059 uint8_t port_type; 1060 si_port_state_t *si_portp; 1061 si_portmult_state_t *si_portmultp; 1062 1063 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1064 1065 SIDBG3(SIDBG_ENTRY, si_ctlp, 1066 "si_tran_probe_port: cport: 0x%x, pmport: 0x%x, qual: 0x%x", 1067 cport, pmport, qual); 1068 1069 if (cport >= SI_MAX_PORTS) { 1070 sd->satadev_type = SATA_DTYPE_NONE; 1071 sd->satadev_state = SATA_STATE_PROBED; 1072 return (SATA_FAILURE); 1073 } 1074 1075 mutex_enter(&si_ctlp->sictl_mutex); 1076 si_portp = si_ctlp->sictl_ports[cport]; 1077 mutex_exit(&si_ctlp->sictl_mutex); 1078 if (si_portp == NULL) { 1079 sd->satadev_type = SATA_DTYPE_NONE; 1080 sd->satadev_state = SATA_STATE_PROBED; 1081 return (SATA_FAILURE); 1082 } 1083 1084 mutex_enter(&si_portp->siport_mutex); 1085 1086 if (qual == SATA_ADDR_PMPORT) { 1087 if (pmport >= si_portp->siport_portmult_state.sipm_num_ports) { 1088 sd->satadev_type = SATA_DTYPE_NONE; 1089 sd->satadev_state = SATA_STATE_PROBED; 1090 mutex_exit(&si_portp->siport_mutex); 1091 return (SATA_FAILURE); 1092 } else { 1093 si_portmultp = &si_portp->siport_portmult_state; 1094 port_type = si_portmultp->sipm_port_type[pmport]; 1095 } 1096 } else { 1097 port_type = si_portp->siport_port_type; 1098 } 1099 1100 switch (port_type) { 1101 1102 case PORT_TYPE_DISK: 1103 sd->satadev_type = SATA_DTYPE_ATADISK; 1104 sd->satadev_state = SATA_STATE_PROBED; 1105 break; 1106 1107 case PORT_TYPE_ATAPI: 1108 sd->satadev_type = SATA_DTYPE_ATAPICD; 1109 sd->satadev_state = SATA_STATE_PROBED; 1110 break; 1111 1112 case PORT_TYPE_MULTIPLIER: 1113 sd->satadev_type = SATA_DTYPE_PMULT; 1114 sd->satadev_add_info = 1115 si_portp->siport_portmult_state.sipm_num_ports; 1116 sd->satadev_state = SATA_STATE_PROBED; 1117 break; 1118 1119 case PORT_TYPE_UNKNOWN: 1120 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1121 sd->satadev_state = SATA_STATE_PROBED; 1122 1123 default: 1124 /* we don't support any other device types. */ 1125 sd->satadev_type = SATA_DTYPE_NONE; 1126 sd->satadev_state = SATA_STATE_PROBED; 1127 break; 1128 } 1129 1130 if (qual == SATA_ADDR_PMPORT) { 1131 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1132 pmport, PSCR_REG0, &sd->satadev_scr.sstatus); 1133 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1134 pmport, PSCR_REG1, &sd->satadev_scr.serror); 1135 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1136 pmport, PSCR_REG2, &sd->satadev_scr.scontrol); 1137 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1138 pmport, PSCR_REG3, &sd->satadev_scr.sactive); 1139 } else { 1140 fill_dev_sregisters(si_ctlp, cport, sd); 1141 if (!(si_portp->siport_active)) { 1142 /* 1143 * Since we are implementing the port deactivation 1144 * in software only, we need to fake a valid value 1145 * for sstatus when the device is in deactivated state. 1146 */ 1147 SSTATUS_SET_DET(sd->satadev_scr.sstatus, 1148 SSTATUS_DET_PHYOFFLINE); 1149 SSTATUS_SET_IPM(sd->satadev_scr.sstatus, 1150 SSTATUS_IPM_NODEV_NOPHY); 1151 } 1152 } 1153 1154 mutex_exit(&si_portp->siport_mutex); 1155 return (SATA_SUCCESS); 1156 } 1157 1158 /* 1159 * Called by sata framework to transport a sata packet down stream. 1160 * 1161 * The actual work of building the FIS & transporting it to the hardware 1162 * is done out of the subroutine si_deliver_satapkt(). 1163 */ 1164 static int 1165 si_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1166 { 1167 si_ctl_state_t *si_ctlp; 1168 uint8_t cport; 1169 si_port_state_t *si_portp; 1170 int slot; 1171 1172 cport = spkt->satapkt_device.satadev_addr.cport; 1173 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1174 mutex_enter(&si_ctlp->sictl_mutex); 1175 si_portp = si_ctlp->sictl_ports[cport]; 1176 mutex_exit(&si_ctlp->sictl_mutex); 1177 1178 SIDBG1(SIDBG_ENTRY, si_ctlp, 1179 "si_tran_start entry: port: 0x%x", cport); 1180 1181 mutex_enter(&si_portp->siport_mutex); 1182 1183 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1184 !si_portp->siport_active) { 1185 /* 1186 * si_intr_phy_ready_change() may have rendered it to 1187 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1188 * it inactive. 1189 */ 1190 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1191 fill_dev_sregisters(si_ctlp, cport, &spkt->satapkt_device); 1192 mutex_exit(&si_portp->siport_mutex); 1193 return (SATA_TRAN_PORT_ERROR); 1194 } 1195 1196 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1197 si_portp->siport_reset_in_progress = 0; 1198 SIDBG1(SIDBG_ENTRY, si_ctlp, 1199 "si_tran_start clearing the " 1200 "reset_in_progress for port: 0x%x", cport); 1201 } 1202 1203 if (si_portp->siport_reset_in_progress && 1204 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset) { 1205 1206 spkt->satapkt_reason = SATA_PKT_BUSY; 1207 SIDBG1(SIDBG_ERRS, si_ctlp, 1208 "si_tran_start returning BUSY while " 1209 "reset in progress: port: 0x%x", cport); 1210 mutex_exit(&si_portp->siport_mutex); 1211 return (SATA_TRAN_BUSY); 1212 } 1213 1214 if (si_portp->mopping_in_progress) { 1215 spkt->satapkt_reason = SATA_PKT_BUSY; 1216 SIDBG1(SIDBG_ERRS, si_ctlp, 1217 "si_tran_start returning BUSY while " 1218 "mopping in progress: port: 0x%x", cport); 1219 mutex_exit(&si_portp->siport_mutex); 1220 return (SATA_TRAN_BUSY); 1221 } 1222 1223 if ((slot = si_deliver_satapkt(si_ctlp, si_portp, cport, spkt)) 1224 == SI_FAILURE) { 1225 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1226 SIDBG1(SIDBG_ERRS, si_ctlp, 1227 "si_tran_start returning QUEUE_FULL: port: 0x%x", 1228 cport); 1229 mutex_exit(&si_portp->siport_mutex); 1230 return (SATA_TRAN_QUEUE_FULL); 1231 } 1232 1233 if (spkt->satapkt_op_mode & (SATA_OPMODE_POLLING|SATA_OPMODE_SYNCH)) { 1234 /* we need to poll now */ 1235 mutex_exit(&si_portp->siport_mutex); 1236 si_poll_cmd(si_ctlp, si_portp, cport, slot, spkt); 1237 mutex_enter(&si_portp->siport_mutex); 1238 } 1239 1240 mutex_exit(&si_portp->siport_mutex); 1241 return (SATA_TRAN_ACCEPTED); 1242 } 1243 1244 #define SENDUP_PACKET(si_portp, satapkt, reason) \ 1245 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1246 SATAC_WRITE_FPDMA_QUEUED) || \ 1247 (satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1248 SATAC_READ_FPDMA_QUEUED)) { \ 1249 si_portp->siport_pending_ncq_count--; \ 1250 } \ 1251 if (satapkt) { \ 1252 satapkt->satapkt_reason = reason; \ 1253 /* \ 1254 * We set the satapkt_reason in both synch and \ 1255 * non-synch cases. \ 1256 */ \ 1257 } \ 1258 if (satapkt && \ 1259 !(satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1260 satapkt->satapkt_comp) { \ 1261 mutex_exit(&si_portp->siport_mutex); \ 1262 (*satapkt->satapkt_comp)(satapkt); \ 1263 mutex_enter(&si_portp->siport_mutex); \ 1264 } 1265 1266 /* 1267 * Mopping is necessitated because of the si3124 hardware limitation. 1268 * The only way to recover from errors or to abort a command is to 1269 * reset the port/device but such a reset also results in throwing 1270 * away all the unfinished pending commands. 1271 * 1272 * A port or device is reset in four scenarios: 1273 * a) some commands failed with errors 1274 * b) or we need to timeout some commands 1275 * c) or we need to abort some commands 1276 * d) or we need reset the port at the request of sata framework 1277 * 1278 * In all these scenarios, we need to send any pending unfinished 1279 * commands up to sata framework. 1280 * 1281 * Only one mopping process at a time is allowed; this is achieved 1282 * by using siport_mop_mutex. 1283 */ 1284 static void 1285 si_mop_commands(si_ctl_state_t *si_ctlp, 1286 si_port_state_t *si_portp, 1287 uint8_t port, 1288 1289 uint32_t slot_status, 1290 uint32_t failed_tags, 1291 uint32_t timedout_tags, 1292 uint32_t aborting_tags, 1293 uint32_t reset_tags) 1294 { 1295 uint32_t finished_tags, unfinished_tags; 1296 int tmpslot; 1297 sata_pkt_t *satapkt; 1298 si_prb_t *prb; 1299 uint32_t *prb_word_ptr; 1300 int i; 1301 1302 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1303 "si_mop_commands entered: slot_status: 0x%x", 1304 slot_status); 1305 1306 SIDBG4(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1307 "si_mop_commands: failed_tags: 0x%x, timedout_tags: 0x%x" 1308 "aborting_tags: 0x%x, reset_tags: 0x%x", 1309 failed_tags, 1310 timedout_tags, 1311 aborting_tags, 1312 reset_tags); 1313 /* 1314 * We could be here for four reasons: abort, reset, 1315 * timeout or error handling. Only one such mopping 1316 * is allowed at a time. 1317 * 1318 * Note that we are already holding the main per port 1319 * mutex; all we need now is siport_mop_mutex. 1320 */ 1321 mutex_enter(&si_portp->siport_mop_mutex); 1322 mutex_enter(&si_portp->siport_mutex); 1323 1324 si_portp->mopping_in_progress = 1; 1325 1326 finished_tags = si_portp->siport_pending_tags & 1327 ~slot_status & SI_SLOT_MASK; 1328 1329 unfinished_tags = slot_status & SI_SLOT_MASK & 1330 ~failed_tags & 1331 ~aborting_tags & 1332 ~reset_tags & 1333 ~timedout_tags; 1334 1335 /* Send up the finished_tags with SATA_PKT_COMPLETED. */ 1336 while (finished_tags) { 1337 tmpslot = ddi_ffs(finished_tags) - 1; 1338 if (tmpslot == -1) { 1339 break; 1340 } 1341 1342 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1343 ASSERT(satapkt != NULL); 1344 prb = &si_portp->siport_prbpool[tmpslot]; 1345 ASSERT(prb != NULL); 1346 satapkt->satapkt_cmd.satacmd_status_reg = 1347 GET_FIS_COMMAND(prb->prb_fis); 1348 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 1349 si_copy_out_regs(&satapkt->satapkt_cmd, &prb->prb_fis); 1350 1351 SIDBG1(SIDBG_ERRS, si_ctlp, 1352 "si_mop_commands sending up completed satapkt: %x", 1353 satapkt); 1354 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 1355 1356 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1357 CLEAR_BIT(finished_tags, tmpslot); 1358 } 1359 1360 ASSERT(finished_tags == 0); 1361 1362 /* Send up failed_tags with SATA_PKT_DEV_ERROR. */ 1363 while (failed_tags) { 1364 tmpslot = ddi_ffs(failed_tags) - 1; 1365 if (tmpslot == -1) { 1366 break; 1367 } 1368 SIDBG1(SIDBG_ERRS, si_ctlp, "si3124: si_mop_commands: " 1369 "handling failed slot: 0x%x", tmpslot); 1370 1371 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1372 ASSERT(satapkt != NULL); 1373 if (satapkt->satapkt_device.satadev_type == 1374 SATA_DTYPE_ATAPICD) { 1375 si_set_sense_data(satapkt, SATA_PKT_DEV_ERROR); 1376 } 1377 1378 /* 1379 * The LRAM contains the the modified FIS. 1380 * Read the modified FIS to obtain the Error & Status. 1381 */ 1382 prb = &(si_portp->siport_prbpool[tmpslot]); 1383 prb_word_ptr = (uint32_t *)prb; 1384 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 1385 prb_word_ptr[i] = ddi_get32( 1386 si_ctlp->sictl_port_acc_handle, 1387 (uint32_t *)(PORT_LRAM(si_ctlp, port, 1388 tmpslot)+i*4)); 1389 } 1390 1391 satapkt->satapkt_cmd.satacmd_status_reg = 1392 GET_FIS_COMMAND(prb->prb_fis); 1393 satapkt->satapkt_cmd.satacmd_error_reg = 1394 GET_FIS_FEATURES(prb->prb_fis); 1395 satapkt->satapkt_cmd.satacmd_sec_count_lsb = 1396 GET_FIS_SECTOR_COUNT(prb->prb_fis); 1397 satapkt->satapkt_cmd.satacmd_lba_low_lsb = 1398 GET_FIS_SECTOR(prb->prb_fis); 1399 satapkt->satapkt_cmd.satacmd_lba_mid_lsb = 1400 GET_FIS_CYL_LOW(prb->prb_fis); 1401 satapkt->satapkt_cmd.satacmd_lba_high_lsb = 1402 GET_FIS_CYL_HI(prb->prb_fis); 1403 satapkt->satapkt_cmd.satacmd_device_reg = 1404 GET_FIS_DEV_HEAD(prb->prb_fis); 1405 1406 if (satapkt->satapkt_cmd.satacmd_addr_type == ATA_ADDR_LBA48) { 1407 satapkt->satapkt_cmd.satacmd_sec_count_msb = 1408 GET_FIS_SECTOR_COUNT_EXP(prb->prb_fis); 1409 satapkt->satapkt_cmd.satacmd_lba_low_msb = 1410 GET_FIS_SECTOR_EXP(prb->prb_fis); 1411 satapkt->satapkt_cmd.satacmd_lba_mid_msb = 1412 GET_FIS_CYL_LOW_EXP(prb->prb_fis); 1413 satapkt->satapkt_cmd.satacmd_lba_high_msb = 1414 GET_FIS_CYL_HI_EXP(prb->prb_fis); 1415 } 1416 1417 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 1418 si_copy_out_regs(&satapkt->satapkt_cmd, &prb->prb_fis); 1419 1420 /* 1421 * In the case of NCQ command failures, the error is 1422 * overwritten by the one obtained from issuing of a 1423 * READ LOG EXTENDED command. 1424 */ 1425 if (si_portp->siport_err_tags_SDBERROR & (1 << tmpslot)) { 1426 satapkt->satapkt_cmd.satacmd_error_reg = 1427 si_read_log_ext(si_ctlp, si_portp, port); 1428 } 1429 1430 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_DEV_ERROR); 1431 1432 CLEAR_BIT(failed_tags, tmpslot); 1433 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1434 } 1435 1436 ASSERT(failed_tags == 0); 1437 1438 /* Send up timedout_tags with SATA_PKT_TIMEOUT. */ 1439 while (timedout_tags) { 1440 tmpslot = ddi_ffs(timedout_tags) - 1; 1441 if (tmpslot == -1) { 1442 break; 1443 } 1444 1445 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1446 ASSERT(satapkt != NULL); 1447 SIDBG1(SIDBG_ERRS, si_ctlp, 1448 "si_mop_commands sending " 1449 "spkt up with PKT_TIMEOUT: %x", 1450 satapkt); 1451 1452 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_TIMEOUT); 1453 1454 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1455 CLEAR_BIT(timedout_tags, tmpslot); 1456 } 1457 1458 ASSERT(timedout_tags == 0); 1459 1460 /* Send up aborting packets with SATA_PKT_ABORTED. */ 1461 while (aborting_tags) { 1462 tmpslot = ddi_ffs(unfinished_tags) - 1; 1463 if (tmpslot == -1) { 1464 break; 1465 } 1466 1467 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1468 ASSERT(satapkt != NULL); 1469 SIDBG1(SIDBG_ERRS, si_ctlp, 1470 "si_mop_commands aborting spkt: %x", 1471 satapkt); 1472 if (satapkt->satapkt_device.satadev_type == 1473 SATA_DTYPE_ATAPICD) { 1474 si_set_sense_data(satapkt, SATA_PKT_ABORTED); 1475 } 1476 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_ABORTED); 1477 1478 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1479 CLEAR_BIT(aborting_tags, tmpslot); 1480 1481 } 1482 1483 ASSERT(aborting_tags == 0); 1484 1485 /* Reset tags are sent up to framework with SATA_PKT_RESET. */ 1486 while (reset_tags) { 1487 tmpslot = ddi_ffs(reset_tags) - 1; 1488 if (tmpslot == -1) { 1489 break; 1490 } 1491 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1492 ASSERT(satapkt != NULL); 1493 SIDBG1(SIDBG_ERRS, si_ctlp, 1494 "si_mop_commands sending PKT_RESET for " 1495 "reset spkt: %x", 1496 satapkt); 1497 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_RESET); 1498 1499 CLEAR_BIT(reset_tags, tmpslot); 1500 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1501 } 1502 1503 ASSERT(reset_tags == 0); 1504 1505 /* Send up the unfinished_tags with SATA_PKT_BUSY. */ 1506 while (unfinished_tags) { 1507 tmpslot = ddi_ffs(unfinished_tags) - 1; 1508 if (tmpslot == -1) { 1509 break; 1510 } 1511 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1512 ASSERT(satapkt != NULL); 1513 SIDBG1(SIDBG_ERRS, si_ctlp, 1514 "si_mop_commands sending PKT_BUSY for " 1515 "retry spkt: %x", 1516 satapkt); 1517 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_BUSY); 1518 1519 CLEAR_BIT(unfinished_tags, tmpslot); 1520 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1521 } 1522 1523 ASSERT(unfinished_tags == 0); 1524 1525 si_portp->mopping_in_progress = 0; 1526 1527 mutex_exit(&si_portp->siport_mutex); 1528 mutex_exit(&si_portp->siport_mop_mutex); 1529 1530 } 1531 1532 /* 1533 * Called by the sata framework to abort the previously sent packet(s). 1534 * 1535 * We reset the device and mop the commands on the port. 1536 */ 1537 static int 1538 si_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1539 { 1540 uint32_t slot_status; 1541 uint8_t port; 1542 int tmpslot; 1543 uint32_t aborting_tags; 1544 uint32_t finished_tags; 1545 si_port_state_t *si_portp; 1546 si_ctl_state_t *si_ctlp; 1547 1548 port = spkt->satapkt_device.satadev_addr.cport; 1549 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1550 mutex_enter(&si_ctlp->sictl_mutex); 1551 si_portp = si_ctlp->sictl_ports[port]; 1552 mutex_exit(&si_ctlp->sictl_mutex); 1553 1554 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_tran_abort on port: %x", port); 1555 1556 mutex_enter(&si_portp->siport_mutex); 1557 1558 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1559 !si_portp->siport_active) { 1560 /* 1561 * si_intr_phy_ready_change() may have rendered it to 1562 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1563 * it inactive. 1564 */ 1565 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1566 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1567 mutex_exit(&si_portp->siport_mutex); 1568 return (SATA_FAILURE); 1569 } 1570 1571 if (flag == SATA_ABORT_ALL_PACKETS) { 1572 aborting_tags = si_portp->siport_pending_tags; 1573 } else { 1574 /* 1575 * Need to abort a single packet. 1576 * Search our siport_slot_pkts[] list for matching spkt. 1577 */ 1578 aborting_tags = 0xffffffff; /* 0xffffffff is impossible tag */ 1579 for (tmpslot = 0; tmpslot < SI_NUM_SLOTS; tmpslot++) { 1580 if (si_portp->siport_slot_pkts[tmpslot] == spkt) { 1581 aborting_tags = (0x1 << tmpslot); 1582 break; 1583 } 1584 } 1585 1586 if (aborting_tags == 0xffffffff) { 1587 /* requested packet is not on pending list. */ 1588 fill_dev_sregisters(si_ctlp, port, 1589 &spkt->satapkt_device); 1590 mutex_exit(&si_portp->siport_mutex); 1591 return (SATA_FAILURE); 1592 } 1593 } 1594 1595 1596 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1597 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1598 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, 1599 port, SI_DEVICE_RESET); 1600 1601 /* 1602 * Compute which have finished and which need to be retried. 1603 * 1604 * The finished tags are siport_pending_tags minus the slot_status. 1605 * The aborting_tags have to be reduced by finished_tags since we 1606 * can't possibly abort a tag which had finished already. 1607 */ 1608 finished_tags = si_portp->siport_pending_tags & 1609 ~slot_status & SI_SLOT_MASK; 1610 aborting_tags &= ~finished_tags; 1611 1612 mutex_exit(&si_portp->siport_mutex); 1613 si_mop_commands(si_ctlp, 1614 si_portp, 1615 port, 1616 slot_status, 1617 0, /* failed_tags */ 1618 0, /* timedout_tags */ 1619 aborting_tags, 1620 0); /* reset_tags */ 1621 mutex_enter(&si_portp->siport_mutex); 1622 1623 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1624 mutex_exit(&si_portp->siport_mutex); 1625 return (SATA_SUCCESS); 1626 } 1627 1628 1629 /* 1630 * Used to reject all the pending packets on a port during a reset 1631 * operation. 1632 * 1633 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 1634 * before calling us. 1635 */ 1636 static void 1637 si_reject_all_reset_pkts( 1638 si_ctl_state_t *si_ctlp, 1639 si_port_state_t *si_portp, 1640 int port) 1641 { 1642 uint32_t slot_status; 1643 uint32_t reset_tags; 1644 1645 _NOTE(ASSUMING_PROTECTED(si_portp)) 1646 1647 SIDBG1(SIDBG_ENTRY, si_ctlp, 1648 "si_reject_all_reset_pkts on port: %x", 1649 port); 1650 1651 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1652 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1653 1654 /* Compute which tags need to be sent up. */ 1655 reset_tags = slot_status & SI_SLOT_MASK; 1656 1657 mutex_exit(&si_portp->siport_mutex); 1658 si_mop_commands(si_ctlp, 1659 si_portp, 1660 port, 1661 slot_status, 1662 0, /* failed_tags */ 1663 0, /* timedout_tags */ 1664 0, /* aborting_tags */ 1665 reset_tags); 1666 mutex_enter(&si_portp->siport_mutex); 1667 1668 } 1669 1670 1671 /* 1672 * Called by sata framework to reset a port(s) or device. 1673 * 1674 */ 1675 static int 1676 si_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 1677 { 1678 si_ctl_state_t *si_ctlp; 1679 uint8_t port = sd->satadev_addr.cport; 1680 int i; 1681 si_port_state_t *si_portp; 1682 int retval = SI_SUCCESS; 1683 1684 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1685 SIDBG1(SIDBG_ENTRY, si_ctlp, 1686 "si_tran_reset_port entry: port: 0x%x", 1687 port); 1688 1689 switch (sd->satadev_addr.qual) { 1690 case SATA_ADDR_CPORT: 1691 mutex_enter(&si_ctlp->sictl_mutex); 1692 si_portp = si_ctlp->sictl_ports[port]; 1693 mutex_exit(&si_ctlp->sictl_mutex); 1694 1695 mutex_enter(&si_portp->siport_mutex); 1696 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1697 SI_PORT_RESET); 1698 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1699 mutex_exit(&si_portp->siport_mutex); 1700 1701 break; 1702 1703 case SATA_ADDR_DCPORT: 1704 mutex_enter(&si_ctlp->sictl_mutex); 1705 si_portp = si_ctlp->sictl_ports[port]; 1706 mutex_exit(&si_ctlp->sictl_mutex); 1707 1708 mutex_enter(&si_portp->siport_mutex); 1709 1710 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1711 !si_portp->siport_active) { 1712 mutex_exit(&si_portp->siport_mutex); 1713 retval = SI_FAILURE; 1714 break; 1715 } 1716 1717 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1718 SI_DEVICE_RESET); 1719 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1720 mutex_exit(&si_portp->siport_mutex); 1721 1722 break; 1723 1724 case SATA_ADDR_CNTRL: 1725 for (i = 0; i < si_ctlp->sictl_num_ports; i++) { 1726 mutex_enter(&si_ctlp->sictl_mutex); 1727 si_portp = si_ctlp->sictl_ports[port]; 1728 mutex_exit(&si_ctlp->sictl_mutex); 1729 1730 mutex_enter(&si_portp->siport_mutex); 1731 retval = si_reset_dport_wait_till_ready(si_ctlp, 1732 si_portp, i, SI_PORT_RESET); 1733 if (retval) { 1734 mutex_exit(&si_portp->siport_mutex); 1735 break; 1736 } 1737 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1738 mutex_exit(&si_portp->siport_mutex); 1739 } 1740 break; 1741 1742 case SATA_ADDR_PMPORT: 1743 case SATA_ADDR_DPMPORT: 1744 SIDBG0(SIDBG_VERBOSE, si_ctlp, 1745 "port mult reset not implemented yet"); 1746 /* FALLSTHROUGH */ 1747 1748 default: 1749 retval = SI_FAILURE; 1750 1751 } 1752 1753 return (retval); 1754 } 1755 1756 1757 /* 1758 * Called by sata framework to activate a port as part of hotplug. 1759 * 1760 * Note: Not port-mult aware. 1761 */ 1762 static int 1763 si_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 1764 { 1765 si_ctl_state_t *si_ctlp; 1766 si_port_state_t *si_portp; 1767 uint8_t port; 1768 1769 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1770 port = satadev->satadev_addr.cport; 1771 mutex_enter(&si_ctlp->sictl_mutex); 1772 si_portp = si_ctlp->sictl_ports[port]; 1773 mutex_exit(&si_ctlp->sictl_mutex); 1774 1775 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_tran_hotplug_port_activate entry"); 1776 1777 mutex_enter(&si_portp->siport_mutex); 1778 si_enable_port_interrupts(si_ctlp, port); 1779 1780 /* 1781 * Reset the device so that a si_find_dev_signature() would trigger. 1782 * But this reset is an internal operation; the sata framework does 1783 * not need to know about it. 1784 */ 1785 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1786 SI_DEVICE_RESET|SI_RESET_NO_EVENTS_UP); 1787 1788 satadev->satadev_state = SATA_STATE_READY; 1789 1790 si_portp->siport_active = PORT_ACTIVE; 1791 1792 fill_dev_sregisters(si_ctlp, port, satadev); 1793 1794 mutex_exit(&si_portp->siport_mutex); 1795 return (SATA_SUCCESS); 1796 } 1797 1798 /* 1799 * Called by sata framework to deactivate a port as part of hotplug. 1800 * 1801 * Note: Not port-mult aware. 1802 */ 1803 static int 1804 si_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 1805 { 1806 si_ctl_state_t *si_ctlp; 1807 si_port_state_t *si_portp; 1808 uint8_t port; 1809 1810 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1811 port = satadev->satadev_addr.cport; 1812 mutex_enter(&si_ctlp->sictl_mutex); 1813 si_portp = si_ctlp->sictl_ports[port]; 1814 mutex_exit(&si_ctlp->sictl_mutex); 1815 1816 SIDBG0(SIDBG_ENTRY, NULL, "si_tran_hotplug_port_deactivate entry"); 1817 1818 mutex_enter(&si_portp->siport_mutex); 1819 if (si_portp->siport_pending_tags & SI_SLOT_MASK) { 1820 /* 1821 * There are pending commands on this port. 1822 * Fail the deactivate request. 1823 */ 1824 satadev->satadev_state = SATA_STATE_READY; 1825 mutex_exit(&si_portp->siport_mutex); 1826 return (SATA_FAILURE); 1827 } 1828 1829 /* mark the device as not accessible any more. */ 1830 si_portp->siport_active = PORT_INACTIVE; 1831 1832 /* disable the interrupts on the port. */ 1833 si_disable_port_interrupts(si_ctlp, port); 1834 1835 satadev->satadev_state = SATA_PSTATE_SHUTDOWN; 1836 1837 fill_dev_sregisters(si_ctlp, port, satadev); 1838 /* 1839 * Since we are implementing the port deactivation in software only, 1840 * we need to fake a valid value for sstatus. 1841 */ 1842 SSTATUS_SET_DET(satadev->satadev_scr.sstatus, SSTATUS_DET_PHYOFFLINE); 1843 SSTATUS_SET_IPM(satadev->satadev_scr.sstatus, SSTATUS_IPM_NODEV_NOPHY); 1844 1845 mutex_exit(&si_portp->siport_mutex); 1846 return (SATA_SUCCESS); 1847 } 1848 1849 1850 /* 1851 * Allocates the si_port_state_t. 1852 */ 1853 static int 1854 si_alloc_port_state(si_ctl_state_t *si_ctlp, int port) 1855 { 1856 si_port_state_t *si_portp; 1857 1858 si_ctlp->sictl_ports[port] = (si_port_state_t *)kmem_zalloc( 1859 sizeof (si_port_state_t), KM_SLEEP); 1860 1861 si_portp = si_ctlp->sictl_ports[port]; 1862 mutex_init(&si_portp->siport_mutex, NULL, MUTEX_DRIVER, 1863 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 1864 mutex_init(&si_portp->siport_mop_mutex, NULL, MUTEX_DRIVER, 1865 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 1866 mutex_enter(&si_portp->siport_mutex); 1867 1868 /* allocate prb & sgt pkts for this port. */ 1869 if (si_alloc_prbpool(si_ctlp, port)) { 1870 mutex_exit(&si_portp->siport_mutex); 1871 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1872 return (SI_FAILURE); 1873 } 1874 if (si_alloc_sgbpool(si_ctlp, port)) { 1875 si_dealloc_prbpool(si_ctlp, port); 1876 mutex_exit(&si_portp->siport_mutex); 1877 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1878 return (SI_FAILURE); 1879 } 1880 1881 si_portp->siport_active = PORT_ACTIVE; 1882 mutex_exit(&si_portp->siport_mutex); 1883 1884 return (SI_SUCCESS); 1885 1886 } 1887 1888 /* 1889 * Deallocates the si_port_state_t. 1890 */ 1891 static void 1892 si_dealloc_port_state(si_ctl_state_t *si_ctlp, int port) 1893 { 1894 si_port_state_t *si_portp; 1895 si_portp = si_ctlp->sictl_ports[port]; 1896 1897 mutex_enter(&si_portp->siport_mutex); 1898 si_dealloc_sgbpool(si_ctlp, port); 1899 si_dealloc_prbpool(si_ctlp, port); 1900 mutex_exit(&si_portp->siport_mutex); 1901 1902 mutex_destroy(&si_portp->siport_mutex); 1903 mutex_destroy(&si_portp->siport_mop_mutex); 1904 1905 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1906 1907 } 1908 1909 /* 1910 * Allocates the SGB (Scatter Gather Block) incore buffer. 1911 */ 1912 static int 1913 si_alloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1914 { 1915 si_port_state_t *si_portp; 1916 uint_t cookie_count; 1917 size_t incore_sgbpool_size = SI_NUM_SLOTS * sizeof (si_sgblock_t); 1918 size_t ret_len; 1919 ddi_dma_cookie_t sgbpool_dma_cookie; 1920 1921 si_portp = si_ctlp->sictl_ports[port]; 1922 1923 /* allocate sgbpool dma handle. */ 1924 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 1925 &prb_sgt_dma_attr, 1926 DDI_DMA_SLEEP, 1927 NULL, 1928 &si_portp->siport_sgbpool_dma_handle) != 1929 DDI_SUCCESS) { 1930 1931 return (SI_FAILURE); 1932 } 1933 1934 /* allocate the memory for sgbpool. */ 1935 if (ddi_dma_mem_alloc(si_portp->siport_sgbpool_dma_handle, 1936 incore_sgbpool_size, 1937 &accattr, 1938 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1939 DDI_DMA_SLEEP, 1940 NULL, 1941 (caddr_t *)&si_portp->siport_sgbpool, 1942 &ret_len, 1943 &si_portp->siport_sgbpool_acc_handle) != NULL) { 1944 1945 /* error.. free the dma handle. */ 1946 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1947 return (SI_FAILURE); 1948 } 1949 1950 /* now bind it */ 1951 if (ddi_dma_addr_bind_handle(si_portp->siport_sgbpool_dma_handle, 1952 NULL, 1953 (caddr_t)si_portp->siport_sgbpool, 1954 incore_sgbpool_size, 1955 DDI_DMA_CONSISTENT, 1956 DDI_DMA_SLEEP, 1957 NULL, 1958 &sgbpool_dma_cookie, 1959 &cookie_count) != DDI_DMA_MAPPED) { 1960 /* error.. free the dma handle & free the memory. */ 1961 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1962 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1963 return (SI_FAILURE); 1964 } 1965 1966 si_portp->siport_sgbpool_physaddr = sgbpool_dma_cookie.dmac_laddress; 1967 return (SI_SUCCESS); 1968 } 1969 1970 /* 1971 * Deallocates the SGB (Scatter Gather Block) incore buffer. 1972 */ 1973 static void 1974 si_dealloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1975 { 1976 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 1977 1978 /* Unbind the dma handle first. */ 1979 (void) ddi_dma_unbind_handle(si_portp->siport_sgbpool_dma_handle); 1980 1981 /* Then free the underlying memory. */ 1982 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1983 1984 /* Now free the handle itself. */ 1985 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1986 1987 } 1988 1989 /* 1990 * Allocates the PRB (Port Request Block) incore packets. 1991 */ 1992 static int 1993 si_alloc_prbpool(si_ctl_state_t *si_ctlp, int port) 1994 { 1995 si_port_state_t *si_portp; 1996 uint_t cookie_count; 1997 size_t incore_pkt_size = SI_NUM_SLOTS * sizeof (si_prb_t); 1998 size_t ret_len; 1999 ddi_dma_cookie_t prbpool_dma_cookie; 2000 2001 si_portp = si_ctlp->sictl_ports[port]; 2002 2003 /* allocate prb pkts. */ 2004 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 2005 &prb_sgt_dma_attr, 2006 DDI_DMA_SLEEP, 2007 NULL, 2008 &si_portp->siport_prbpool_dma_handle) != 2009 DDI_SUCCESS) { 2010 2011 return (SI_FAILURE); 2012 } 2013 2014 if (ddi_dma_mem_alloc(si_portp->siport_prbpool_dma_handle, 2015 incore_pkt_size, 2016 &accattr, 2017 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2018 DDI_DMA_SLEEP, 2019 NULL, 2020 (caddr_t *)&si_portp->siport_prbpool, 2021 &ret_len, 2022 &si_portp->siport_prbpool_acc_handle) != NULL) { 2023 2024 /* error.. free the dma handle. */ 2025 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2026 return (SI_FAILURE); 2027 } 2028 2029 if (ddi_dma_addr_bind_handle(si_portp->siport_prbpool_dma_handle, 2030 NULL, 2031 (caddr_t)si_portp->siport_prbpool, 2032 incore_pkt_size, 2033 DDI_DMA_CONSISTENT, 2034 DDI_DMA_SLEEP, 2035 NULL, 2036 &prbpool_dma_cookie, 2037 &cookie_count) != DDI_DMA_MAPPED) { 2038 /* error.. free the dma handle & free the memory. */ 2039 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2040 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2041 return (SI_FAILURE); 2042 } 2043 2044 si_portp->siport_prbpool_physaddr = 2045 prbpool_dma_cookie.dmac_laddress; 2046 return (SI_SUCCESS); 2047 } 2048 2049 /* 2050 * Deallocates the PRB (Port Request Block) incore packets. 2051 */ 2052 static void 2053 si_dealloc_prbpool(si_ctl_state_t *si_ctlp, int port) 2054 { 2055 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 2056 2057 /* Unbind the prb dma handle first. */ 2058 (void) ddi_dma_unbind_handle(si_portp->siport_prbpool_dma_handle); 2059 2060 /* Then free the underlying memory. */ 2061 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2062 2063 /* Now free the handle itself. */ 2064 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2065 2066 } 2067 2068 2069 2070 /* 2071 * Soft-reset the port to find the signature of the device connected to 2072 * the port. 2073 */ 2074 static void 2075 si_find_dev_signature( 2076 si_ctl_state_t *si_ctlp, 2077 si_port_state_t *si_portp, 2078 int port, 2079 int pmp) 2080 { 2081 si_prb_t *prb; 2082 uint32_t slot_status, signature; 2083 int slot, loop_count; 2084 2085 SIDBG2(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 2086 "si_find_dev_signature enter: port: %x, pmp: %x", 2087 port, pmp); 2088 2089 /* Build a Soft Reset PRB in host memory. */ 2090 mutex_enter(&si_portp->siport_mutex); 2091 2092 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2093 if (slot == -1) { 2094 /* Empty slot could not be found. */ 2095 if (pmp != PORTMULT_CONTROL_PORT) { 2096 /* We are behind port multiplier. */ 2097 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2098 PORT_TYPE_NODEV; 2099 } else { 2100 si_portp->siport_port_type = PORT_TYPE_NODEV; 2101 } 2102 2103 mutex_exit(&si_portp->siport_mutex); 2104 return; 2105 } 2106 prb = &si_portp->siport_prbpool[slot]; 2107 bzero((void *)prb, sizeof (si_prb_t)); 2108 2109 SET_FIS_PMP(prb->prb_fis, pmp); 2110 SET_PRB_CONTROL_SOFT_RESET(prb); 2111 2112 #if SI_DEBUG 2113 if (si_debug_flags & SIDBG_DUMP_PRB) { 2114 char *ptr; 2115 int j; 2116 2117 ptr = (char *)prb; 2118 cmn_err(CE_WARN, "si_find_dev_signature, prb: "); 2119 for (j = 0; j < (sizeof (si_prb_t)); j++) { 2120 if (j%4 == 0) { 2121 cmn_err(CE_WARN, "----"); 2122 } 2123 cmn_err(CE_WARN, "%x ", ptr[j]); 2124 } 2125 2126 } 2127 #endif /* SI_DEBUG */ 2128 2129 /* deliver soft reset prb to empty slot. */ 2130 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2131 2132 loop_count = 0; 2133 /* Loop till the soft reset is finished. */ 2134 do { 2135 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2136 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2137 2138 if (loop_count++ > SI_POLLRATE_SOFT_RESET) { 2139 /* We are effectively timing out after 10 sec. */ 2140 break; 2141 } 2142 2143 /* Wait for 10 millisec */ 2144 #ifndef __lock_lint 2145 delay(SI_10MS_TICKS); 2146 #endif /* __lock_lint */ 2147 2148 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 2149 2150 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 2151 "si_find_dev_signature: loop count: %d, slot_status: 0x%x", 2152 loop_count, slot_status); 2153 2154 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2155 2156 /* Read device signature from command slot. */ 2157 signature = ddi_get32(si_ctlp->sictl_port_acc_handle, 2158 (uint32_t *)(PORT_SIGNATURE_MSB(si_ctlp, port, slot))); 2159 signature <<= 8; 2160 signature |= (0xff & ddi_get32(si_ctlp->sictl_port_acc_handle, 2161 (uint32_t *)(PORT_SIGNATURE_LSB(si_ctlp, 2162 port, slot)))); 2163 2164 SIDBG1(SIDBG_INIT, si_ctlp, "Device signature: 0x%x", signature); 2165 2166 if (signature == SI_SIGNATURE_PORT_MULTIPLIER) { 2167 2168 SIDBG2(SIDBG_INIT, si_ctlp, 2169 "Found multiplier at cport: 0x%d, pmport: 0x%x", 2170 port, pmp); 2171 2172 if (pmp != PORTMULT_CONTROL_PORT) { 2173 /* 2174 * It is wrong to chain a port multiplier behind 2175 * another port multiplier. 2176 */ 2177 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2178 PORT_TYPE_NODEV; 2179 } else { 2180 si_portp->siport_port_type = PORT_TYPE_MULTIPLIER; 2181 mutex_exit(&si_portp->siport_mutex); 2182 (void) si_enumerate_port_multiplier(si_ctlp, 2183 si_portp, port); 2184 mutex_enter(&si_portp->siport_mutex); 2185 } 2186 si_init_port(si_ctlp, port); 2187 2188 } else if (signature == SI_SIGNATURE_ATAPI) { 2189 if (pmp != PORTMULT_CONTROL_PORT) { 2190 /* We are behind port multiplier. */ 2191 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2192 PORT_TYPE_ATAPI; 2193 } else { 2194 si_portp->siport_port_type = PORT_TYPE_ATAPI; 2195 si_init_port(si_ctlp, port); 2196 } 2197 SIDBG2(SIDBG_INIT, si_ctlp, 2198 "Found atapi at : cport: %x, pmport: %x", 2199 port, pmp); 2200 2201 } else if (signature == SI_SIGNATURE_DISK) { 2202 2203 if (pmp != PORTMULT_CONTROL_PORT) { 2204 /* We are behind port multiplier. */ 2205 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2206 PORT_TYPE_DISK; 2207 } else { 2208 si_portp->siport_port_type = PORT_TYPE_DISK; 2209 si_init_port(si_ctlp, port); 2210 } 2211 SIDBG2(SIDBG_INIT, si_ctlp, 2212 "found disk at : cport: %x, pmport: %x", 2213 port, pmp); 2214 2215 } else { 2216 if (pmp != PORTMULT_CONTROL_PORT) { 2217 /* We are behind port multiplier. */ 2218 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2219 PORT_TYPE_UNKNOWN; 2220 } else { 2221 si_portp->siport_port_type = PORT_TYPE_UNKNOWN; 2222 } 2223 SIDBG3(SIDBG_INIT, si_ctlp, 2224 "Found unknown signature 0x%x at: port: %x, pmp: %x", 2225 signature, port, pmp); 2226 } 2227 2228 mutex_exit(&si_portp->siport_mutex); 2229 } 2230 2231 2232 /* 2233 * Polls for the completion of the command. This is safe with both 2234 * interrupts enabled or disabled. 2235 */ 2236 static void 2237 si_poll_cmd( 2238 si_ctl_state_t *si_ctlp, 2239 si_port_state_t *si_portp, 2240 int port, 2241 int slot, 2242 sata_pkt_t *satapkt) 2243 { 2244 uint32_t slot_status; 2245 int pkt_timeout_ticks; 2246 uint32_t port_intr_status; 2247 int in_panic = ddi_in_panic(); 2248 2249 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_poll_cmd entered: port: 0x%x", port); 2250 2251 pkt_timeout_ticks = drv_usectohz((clock_t)satapkt->satapkt_time * 2252 1000000); 2253 2254 mutex_enter(&si_portp->siport_mutex); 2255 2256 /* we start out with SATA_PKT_COMPLETED as the satapkt_reason */ 2257 satapkt->satapkt_reason = SATA_PKT_COMPLETED; 2258 2259 do { 2260 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2261 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2262 2263 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2264 if (in_panic) { 2265 /* 2266 * If we are in panic, we can't rely on 2267 * timers; so, busy wait instead of delay(). 2268 */ 2269 mutex_exit(&si_portp->siport_mutex); 2270 drv_usecwait(SI_1MS_USECS); 2271 mutex_enter(&si_portp->siport_mutex); 2272 } else { 2273 mutex_exit(&si_portp->siport_mutex); 2274 #ifndef __lock_lint 2275 delay(SI_1MS_TICKS); 2276 #endif /* __lock_lint */ 2277 mutex_enter(&si_portp->siport_mutex); 2278 } 2279 } else { 2280 break; 2281 } 2282 2283 pkt_timeout_ticks -= SI_1MS_TICKS; 2284 2285 } while (pkt_timeout_ticks > 0); 2286 2287 if (satapkt->satapkt_reason != SATA_PKT_COMPLETED) { 2288 /* The si_mop_command() got to our packet before us */ 2289 goto poll_done; 2290 } 2291 2292 /* 2293 * Interrupts and timers may not be working properly in a crash dump 2294 * situation; we may need to handle all the three conditions here: 2295 * successful completion, packet failure and packet timeout. 2296 */ 2297 if (IS_ATTENTION_RAISED(slot_status)) { /* error seen on port */ 2298 2299 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 2300 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 2301 2302 SIDBG2(SIDBG_VERBOSE, si_ctlp, 2303 "si_poll_cmd: port_intr_status: 0x%x, port: %x", 2304 port_intr_status, port); 2305 2306 if (port_intr_status & INTR_COMMAND_ERROR) { 2307 mutex_exit(&si_portp->siport_mutex); 2308 (void) si_intr_command_error(si_ctlp, si_portp, port); 2309 mutex_enter(&si_portp->siport_mutex); 2310 2311 goto poll_done; 2312 2313 /* 2314 * Why do we need to call si_intr_command_error() ? 2315 * 2316 * Answer: Even if the current packet is not the 2317 * offending command, we need to restart the stalled 2318 * port; (may be, the interrupts are not working well 2319 * in panic condition). The call to routine 2320 * si_intr_command_error() will achieve that. 2321 * 2322 * What if the interrupts are working fine and the 2323 * si_intr_command_error() gets called once more from 2324 * interrupt context ? 2325 * 2326 * Answer: The second instance of routine 2327 * si_intr_command_error() will not mop anything 2328 * since the first error handler has already blown 2329 * away the hardware pending queues through reset. 2330 * 2331 * Will the si_intr_command_error() hurt current 2332 * packet ? 2333 * 2334 * Answer: No. 2335 */ 2336 } else { 2337 /* Ignore any non-error interrupts at this stage */ 2338 ddi_put32(si_ctlp->sictl_port_acc_handle, 2339 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, 2340 port)), 2341 port_intr_status & INTR_MASK); 2342 } 2343 2344 2345 } else if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2346 satapkt->satapkt_reason = SATA_PKT_TIMEOUT; 2347 } /* else: the command completed successfully */ 2348 2349 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == 2350 SATAC_WRITE_FPDMA_QUEUED) || 2351 (satapkt->satapkt_cmd.satacmd_cmd_reg == 2352 SATAC_READ_FPDMA_QUEUED)) { 2353 si_portp->siport_pending_ncq_count--; 2354 } 2355 2356 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2357 2358 poll_done: 2359 mutex_exit(&si_portp->siport_mutex); 2360 2361 /* 2362 * tidbit: What is the interaction of abort with polling ? 2363 * What happens if the current polled pkt is aborted in parallel ? 2364 * 2365 * Answer: Assuming that the si_mop_commands() completes ahead 2366 * of polling, all it does is to set the satapkt_reason to 2367 * SPKT_PKT_ABORTED. That would be fine with us. 2368 * 2369 * The same logic applies to reset interacting with polling. 2370 */ 2371 } 2372 2373 2374 /* 2375 * Searches for and claims a free slot. 2376 * 2377 * Returns: SI_FAILURE if no slots found 2378 * claimed slot number if successful 2379 * 2380 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2381 * before calling us. 2382 */ 2383 /*ARGSUSED*/ 2384 static int 2385 si_claim_free_slot(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 2386 { 2387 uint32_t free_slots; 2388 int slot; 2389 2390 _NOTE(ASSUMING_PROTECTED(si_portp)) 2391 2392 SIDBG1(SIDBG_ENTRY, si_ctlp, 2393 "si_claim_free_slot entry: siport_pending_tags: %x", 2394 si_portp->siport_pending_tags); 2395 2396 free_slots = (~si_portp->siport_pending_tags) & SI_SLOT_MASK; 2397 slot = ddi_ffs(free_slots) - 1; 2398 if (slot == -1) { 2399 SIDBG0(SIDBG_VERBOSE, si_ctlp, 2400 "si_claim_free_slot: no empty slots"); 2401 return (SI_FAILURE); 2402 } 2403 2404 si_portp->siport_pending_tags |= (0x1 << slot); 2405 SIDBG1(SIDBG_VERBOSE, si_ctlp, "si_claim_free_slot: found slot: 0x%x", 2406 slot); 2407 return (slot); 2408 } 2409 2410 /* 2411 * Builds the PRB for the sata packet and delivers it to controller. 2412 * 2413 * Returns: 2414 * slot number if we can obtain a slot successfully 2415 * otherwise, return SI_FAILURE 2416 * 2417 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2418 * before calling us. 2419 */ 2420 static int 2421 si_deliver_satapkt( 2422 si_ctl_state_t *si_ctlp, 2423 si_port_state_t *si_portp, 2424 int port, 2425 sata_pkt_t *spkt) 2426 { 2427 int slot; 2428 si_prb_t *prb; 2429 sata_cmd_t *cmd; 2430 si_sge_t *sgep; /* scatter gather entry pointer */ 2431 si_sgt_t *sgtp; /* scatter gather table pointer */ 2432 si_sgblock_t *sgbp; /* scatter gather block pointer */ 2433 int i, j, cookie_index; 2434 int ncookies; 2435 int is_atapi = 0; 2436 ddi_dma_cookie_t cookie; 2437 2438 _NOTE(ASSUMING_PROTECTED(si_portp)) 2439 2440 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2441 if (slot == -1) { 2442 return (SI_FAILURE); 2443 } 2444 2445 if (spkt->satapkt_device.satadev_type == SATA_DTYPE_ATAPICD) { 2446 is_atapi = 1; 2447 } 2448 2449 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 2450 !si_portp->siport_active) { 2451 /* 2452 * si_intr_phy_ready_change() may have rendered it to 2453 * PORT_TYPE_NODEV. cfgadm operation may have rendered 2454 * it inactive. 2455 */ 2456 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2457 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 2458 2459 return (SI_FAILURE); 2460 } 2461 2462 2463 prb = &(si_portp->siport_prbpool[slot]); 2464 bzero((void *)prb, sizeof (si_prb_t)); 2465 2466 cmd = &spkt->satapkt_cmd; 2467 2468 SIDBG4(SIDBG_ENTRY, si_ctlp, 2469 "si_deliver_satpkt entry: cmd_reg: 0x%x, slot: 0x%x, \ 2470 port: %x, satapkt: %x", 2471 cmd->satacmd_cmd_reg, slot, port, (uint32_t)(intptr_t)spkt); 2472 2473 /* Now fill the prb. */ 2474 if (is_atapi) { 2475 if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction == 2476 SATA_DIR_READ) { 2477 SET_PRB_CONTROL_PKT_READ(prb); 2478 } else if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction 2479 == SATA_DIR_WRITE) { 2480 SET_PRB_CONTROL_PKT_WRITE(prb); 2481 } 2482 } 2483 2484 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 2485 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 2486 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 2487 SET_FIS_PMP(prb->prb_fis, 2488 spkt->satapkt_device.satadev_addr.pmport); 2489 } 2490 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 2491 SET_FIS_COMMAND(prb->prb_fis, cmd->satacmd_cmd_reg); 2492 SET_FIS_FEATURES(prb->prb_fis, cmd->satacmd_features_reg); 2493 SET_FIS_SECTOR_COUNT(prb->prb_fis, cmd->satacmd_sec_count_lsb); 2494 2495 switch (cmd->satacmd_addr_type) { 2496 2497 case ATA_ADDR_LBA: 2498 /* fallthru */ 2499 2500 case ATA_ADDR_LBA28: 2501 /* LBA[7:0] */ 2502 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2503 2504 /* LBA[15:8] */ 2505 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2506 2507 /* LBA[23:16] */ 2508 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2509 2510 /* LBA [27:24] (also called dev_head) */ 2511 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2512 2513 break; 2514 2515 case ATA_ADDR_LBA48: 2516 /* LBA[7:0] */ 2517 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2518 2519 /* LBA[15:8] */ 2520 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2521 2522 /* LBA[23:16] */ 2523 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2524 2525 /* LBA [31:24] */ 2526 SET_FIS_SECTOR_EXP(prb->prb_fis, cmd->satacmd_lba_low_msb); 2527 2528 /* LBA [39:32] */ 2529 SET_FIS_CYL_LOW_EXP(prb->prb_fis, cmd->satacmd_lba_mid_msb); 2530 2531 /* LBA [47:40] */ 2532 SET_FIS_CYL_HI_EXP(prb->prb_fis, cmd->satacmd_lba_high_msb); 2533 2534 /* Set dev_head */ 2535 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2536 2537 /* Set the extended sector count and features */ 2538 SET_FIS_SECTOR_COUNT_EXP(prb->prb_fis, 2539 cmd->satacmd_sec_count_msb); 2540 SET_FIS_FEATURES_EXP(prb->prb_fis, 2541 cmd->satacmd_features_reg_ext); 2542 2543 break; 2544 2545 } 2546 2547 if (cmd->satacmd_flags.sata_queued) { 2548 /* 2549 * For queued commands, the TAG for the sector count lsb is 2550 * generated from current slot number. 2551 */ 2552 SET_FIS_SECTOR_COUNT(prb->prb_fis, slot << 3); 2553 } 2554 2555 if ((cmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) || 2556 (cmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED)) { 2557 si_portp->siport_pending_ncq_count++; 2558 } 2559 2560 /* *** now fill the scatter gather list ******* */ 2561 2562 if (is_atapi) { /* It is an ATAPI drive */ 2563 /* atapi command goes into sge0 */ 2564 bcopy(cmd->satacmd_acdb, &prb->prb_sge0, sizeof (si_sge_t)); 2565 2566 /* Now fill sge1 with pointer to external SGT. */ 2567 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2568 prb->prb_sge1.sge_addr = 2569 si_portp->siport_sgbpool_physaddr + 2570 slot*sizeof (si_sgblock_t); 2571 SET_SGE_LNK(prb->prb_sge1); 2572 } else { 2573 SET_SGE_TRM(prb->prb_sge1); 2574 } 2575 } else { 2576 /* Fill the sge0 */ 2577 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2578 prb->prb_sge0.sge_addr = 2579 si_portp->siport_sgbpool_physaddr + 2580 slot*sizeof (si_sgblock_t); 2581 SET_SGE_LNK(prb->prb_sge0); 2582 2583 } else { 2584 SET_SGE_TRM(prb->prb_sge0); 2585 } 2586 2587 /* sge1 is left empty in non-ATAPI case */ 2588 } 2589 2590 bzero(&si_portp->siport_sgbpool[slot], sizeof (si_sgblock_t)); 2591 2592 ncookies = spkt->satapkt_cmd.satacmd_num_dma_cookies; 2593 ASSERT(ncookies <= SI_MAX_SGL_LENGTH); 2594 2595 SIDBG1(SIDBG_COOKIES, si_ctlp, "total ncookies: %d", ncookies); 2596 if (ncookies == 0) { 2597 sgbp = &si_portp->siport_sgbpool[slot]; 2598 sgtp = &sgbp->sgb_sgt[0]; 2599 sgep = &sgtp->sgt_sge[0]; 2600 2601 /* No cookies. Terminate the chain. */ 2602 SIDBG0(SIDBG_COOKIES, si_ctlp, "empty cookies: terminating."); 2603 2604 sgep->sge_addr_low = 0; 2605 sgep->sge_addr_high = 0; 2606 sgep->sge_data_count = 0; 2607 SET_SGE_TRM((*sgep)); 2608 2609 goto sgl_fill_done; 2610 } 2611 2612 for (i = 0, cookie_index = 0, sgbp = &si_portp->siport_sgbpool[slot]; 2613 i < SI_MAX_SGT_TABLES_PER_PRB; i++) { 2614 2615 sgtp = &sgbp->sgb_sgt[i]; 2616 2617 /* Now fill the first 3 entries of SGT in the loop below. */ 2618 for (j = 0, sgep = &sgtp->sgt_sge[0]; 2619 ((j < 3) && (cookie_index < ncookies-1)); 2620 j++, cookie_index++, sgep++) { 2621 ASSERT(cookie_index < ncookies); 2622 SIDBG2(SIDBG_COOKIES, si_ctlp, 2623 "inner loop: cookie_index: %d, ncookies: %d", 2624 cookie_index, 2625 ncookies); 2626 cookie = spkt->satapkt_cmd. 2627 satacmd_dma_cookie_list[cookie_index]; 2628 2629 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2630 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2631 sgep->sge_data_count = cookie.dmac_size; 2632 } 2633 2634 /* 2635 * If this happens to be the last cookie, we terminate it here. 2636 * Otherwise, we link to next SGT. 2637 */ 2638 2639 if (cookie_index == ncookies-1) { 2640 /* This is the last cookie. Terminate the chain. */ 2641 SIDBG2(SIDBG_COOKIES, si_ctlp, 2642 "filling the last: cookie_index: %d, " 2643 "ncookies: %d", 2644 cookie_index, 2645 ncookies); 2646 cookie = spkt->satapkt_cmd. 2647 satacmd_dma_cookie_list[cookie_index]; 2648 2649 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2650 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2651 sgep->sge_data_count = cookie.dmac_size; 2652 SET_SGE_TRM((*sgep)); 2653 2654 break; /* we break the loop */ 2655 2656 } else { 2657 /* This is not the last one. So link it. */ 2658 SIDBG2(SIDBG_COOKIES, si_ctlp, 2659 "linking SGT: cookie_index: %d, ncookies: %d", 2660 cookie_index, 2661 ncookies); 2662 sgep->sge_addr = si_portp->siport_sgbpool_physaddr + 2663 slot * sizeof (si_sgblock_t) + 2664 (i+1) * sizeof (si_sgt_t); 2665 2666 SET_SGE_LNK((*sgep)); 2667 } 2668 2669 } 2670 2671 /* *** finished filling the scatter gather list ******* */ 2672 2673 sgl_fill_done: 2674 /* Now remember the sata packet in siport_slot_pkts[]. */ 2675 si_portp->siport_slot_pkts[slot] = spkt; 2676 2677 /* 2678 * We are overloading satapkt_hba_driver_private with 2679 * watched_cycle count. 2680 */ 2681 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 2682 2683 if (is_atapi) { 2684 /* program the packet_lenth if it is atapi device. */ 2685 2686 2687 #ifdef ATAPI_2nd_PHASE 2688 /* 2689 * Framework needs to calculate the acdb_len based on 2690 * identify packet data. This needs to be accomplished 2691 * in second phase of the project. 2692 */ 2693 ASSERT((cmd->satacmd_acdb_len == 12) || 2694 (cmd->satacmd_acdb_len == 16)); 2695 SIDBG1(SIDBG_VERBOSE, si_ctlp, "deliver: acdb_len: %d", 2696 cmd->satacmd_acdb_len); 2697 2698 if (cmd->satacmd_acdb_len == 16) { 2699 ddi_put32(si_ctlp->sictl_port_acc_handle, 2700 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 2701 PORT_CONTROL_SET_BITS_PACKET_LEN); 2702 } else { 2703 ddi_put32(si_ctlp->sictl_port_acc_handle, 2704 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2705 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2706 } 2707 2708 #else /* ATAPI_2nd_PHASE */ 2709 /* hard coding for now to 12 bytes */ 2710 ddi_put32(si_ctlp->sictl_port_acc_handle, 2711 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2712 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2713 #endif /* ATAPI_2nd_PHASE */ 2714 } 2715 2716 2717 #if SI_DEBUG 2718 if (si_debug_flags & SIDBG_DUMP_PRB) { 2719 if (!(is_atapi && (prb->prb_sge0.sge_addr_low == 0))) { 2720 /* 2721 * Do not dump the atapi Test-Unit-Ready commands. 2722 * The sd_media_watch spews too many of these. 2723 */ 2724 int *ptr; 2725 si_sge_t *tmpsgep; 2726 int j; 2727 2728 ptr = (int *)prb; 2729 cmn_err(CE_WARN, "si_deliver_satpkt prb: "); 2730 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 2731 cmn_err(CE_WARN, "%x ", ptr[j]); 2732 } 2733 2734 cmn_err(CE_WARN, 2735 "si_deliver_satpkt sgt: low, high, count link"); 2736 for (j = 0, 2737 tmpsgep = (si_sge_t *) 2738 &si_portp->siport_sgbpool[slot]; 2739 j < (sizeof (si_sgblock_t)/ sizeof (si_sge_t)); 2740 j++, tmpsgep++) { 2741 ptr = (int *)tmpsgep; 2742 cmn_err(CE_WARN, "%x %x %x %x", 2743 ptr[0], 2744 ptr[1], 2745 ptr[2], 2746 ptr[3]); 2747 if (IS_SGE_TRM_SET((*tmpsgep))) { 2748 break; 2749 } 2750 2751 } 2752 } 2753 2754 } 2755 #endif /* SI_DEBUG */ 2756 2757 /* Deliver PRB */ 2758 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2759 2760 return (slot); 2761 } 2762 2763 /* 2764 * Initialize the controller and set up driver data structures. 2765 * 2766 * This routine can be called from three separate cases: DDI_ATTACH, PM_LEVEL_D0 2767 * and DDI_RESUME. The DDI_ATTACH case is different from other two cases; the 2768 * memory allocation & device signature probing are attempted only during 2769 * DDI_ATTACH case. In the case of PM_LEVEL_D0 & DDI_RESUME, we are starting 2770 * from a previously initialized state; so there is no need to allocate memory 2771 * or to attempt probing the device signatures. 2772 */ 2773 static int 2774 si_initialize_controller(si_ctl_state_t *si_ctlp) 2775 { 2776 uint32_t port_status; 2777 uint32_t SStatus; 2778 uint32_t SControl; 2779 int port; 2780 int loop_count = 0; 2781 si_port_state_t *si_portp; 2782 2783 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 2784 "si3124: si_initialize_controller entered"); 2785 2786 mutex_enter(&si_ctlp->sictl_mutex); 2787 2788 /* Remove the Global Reset. */ 2789 ddi_put32(si_ctlp->sictl_global_acc_handle, 2790 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 2791 GLOBAL_CONTROL_REG_BITS_CLEAR); 2792 2793 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 2794 2795 if (si_ctlp->sictl_flags & SI_ATTACH) { 2796 /* 2797 * We allocate the port state only during attach 2798 * sequence. We don't want to do it during 2799 * suspend/resume sequence. 2800 */ 2801 if (si_alloc_port_state(si_ctlp, port)) { 2802 mutex_exit(&si_ctlp->sictl_mutex); 2803 return (SI_FAILURE); 2804 } 2805 } 2806 2807 si_portp = si_ctlp->sictl_ports[port]; 2808 mutex_enter(&si_portp->siport_mutex); 2809 2810 /* Clear Port Reset. */ 2811 ddi_put32(si_ctlp->sictl_port_acc_handle, 2812 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2813 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 2814 2815 /* 2816 * Arm the interrupts for: Cmd completion, Cmd error, 2817 * Port Ready, PM Change, PhyRdyChange, Commwake, 2818 * UnrecFIS, Devxchanged, SDBNotify. 2819 */ 2820 ddi_put32(si_ctlp->sictl_port_acc_handle, 2821 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 2822 (INTR_COMMAND_COMPLETE | 2823 INTR_COMMAND_ERROR | 2824 INTR_PORT_READY | 2825 INTR_POWER_CHANGE | 2826 INTR_PHYRDY_CHANGE | 2827 INTR_COMWAKE_RECEIVED | 2828 INTR_UNRECOG_FIS | 2829 INTR_DEV_XCHANGED | 2830 INTR_SETDEVBITS_NOTIFY)); 2831 2832 /* Now enable the interrupts. */ 2833 si_enable_port_interrupts(si_ctlp, port); 2834 2835 /* 2836 * The following PHY initialization is redundant in 2837 * in x86 since the BIOS anyway does this as part of 2838 * device enumeration during the power up. But this 2839 * is a required step in sparc since there is no BIOS. 2840 * 2841 * The way to initialize the PHY is to write a 1 and then 2842 * a 0 to DET field of SControl register. 2843 */ 2844 2845 /* 2846 * Fetch the current SControl before writing the 2847 * DET part with 1 2848 */ 2849 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2850 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2851 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 2852 ddi_put32(si_ctlp->sictl_port_acc_handle, 2853 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2854 SControl); 2855 #ifndef __lock_lint 2856 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 2857 #endif /* __lock_lint */ 2858 2859 /* 2860 * Now fetch the SControl again and rewrite the 2861 * DET part with 0 2862 */ 2863 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2864 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2865 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 2866 ddi_put32(si_ctlp->sictl_port_acc_handle, 2867 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2868 SControl); 2869 2870 /* 2871 * PHY may be initialized by now. Check the DET field of 2872 * SStatus to determine if there is a device present. 2873 * 2874 * The DET field is valid only if IPM field indicates that 2875 * the interface is in active state. 2876 */ 2877 2878 loop_count = 0; 2879 do { 2880 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 2881 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 2882 2883 if (SSTATUS_GET_IPM(SStatus) != 2884 SSTATUS_IPM_INTERFACE_ACTIVE) { 2885 /* 2886 * If the interface is not active, the DET field 2887 * is considered not accurate. So we want to 2888 * continue looping. 2889 */ 2890 SSTATUS_SET_DET(SStatus, 2891 SSTATUS_DET_NODEV_NOPHY); 2892 } 2893 2894 if (loop_count++ > SI_POLLRATE_SSTATUS) { 2895 /* 2896 * We are effectively timing out after 0.1 sec. 2897 */ 2898 break; 2899 } 2900 2901 /* Wait for 10 millisec */ 2902 #ifndef __lock_lint 2903 delay(SI_10MS_TICKS); 2904 #endif /* __lock_lint */ 2905 2906 } while (SSTATUS_GET_DET(SStatus) != 2907 SSTATUS_DET_DEVPRESENT_PHYONLINE); 2908 2909 SIDBG2(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2910 "si_initialize_controller: 1st loop count: %d, " 2911 "SStatus: 0x%x", 2912 loop_count, 2913 SStatus); 2914 2915 if ((SSTATUS_GET_IPM(SStatus) != 2916 SSTATUS_IPM_INTERFACE_ACTIVE) || 2917 (SSTATUS_GET_DET(SStatus) != 2918 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 2919 /* 2920 * Either the port is not active or there 2921 * is no device present. 2922 */ 2923 si_ctlp->sictl_ports[port]->siport_port_type = 2924 PORT_TYPE_NODEV; 2925 mutex_exit(&si_portp->siport_mutex); 2926 continue; 2927 } 2928 2929 /* Wait until Port Ready */ 2930 loop_count = 0; 2931 do { 2932 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2933 (uint32_t *)PORT_STATUS(si_ctlp, port)); 2934 2935 if (loop_count++ > SI_POLLRATE_PORTREADY) { 2936 /* 2937 * We are effectively timing out after 0.5 sec. 2938 */ 2939 break; 2940 } 2941 2942 /* Wait for 10 millisec */ 2943 #ifndef __lock_lint 2944 delay(SI_10MS_TICKS); 2945 #endif /* __lock_lint */ 2946 2947 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 2948 2949 SIDBG1(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2950 "si_initialize_controller: 2nd loop count: %d", 2951 loop_count); 2952 2953 if (si_ctlp->sictl_flags & SI_ATTACH) { 2954 /* 2955 * We want to probe for dev signature only during attach 2956 * case. Don't do it during suspend/resume sequence. 2957 */ 2958 if (port_status & PORT_STATUS_BITS_PORT_READY) { 2959 mutex_exit(&si_portp->siport_mutex); 2960 si_find_dev_signature(si_ctlp, si_portp, port, 2961 PORTMULT_CONTROL_PORT); 2962 mutex_enter(&si_portp->siport_mutex); 2963 } else { 2964 si_ctlp->sictl_ports[port]->siport_port_type = 2965 PORT_TYPE_NODEV; 2966 } 2967 } 2968 2969 mutex_exit(&si_portp->siport_mutex); 2970 } 2971 2972 mutex_exit(&si_ctlp->sictl_mutex); 2973 return (SI_SUCCESS); 2974 } 2975 2976 /* 2977 * Reverse of si_initialize_controller(). 2978 * 2979 * WARNING, WARNING: The caller is expected to obtain the sictl_mutex 2980 * before calling us. 2981 */ 2982 static void 2983 si_deinititalize_controller(si_ctl_state_t *si_ctlp) 2984 { 2985 int port; 2986 2987 _NOTE(ASSUMING_PROTECTED(si_ctlp)) 2988 2989 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 2990 "si3124: si_deinititalize_controller entered"); 2991 2992 /* disable all the interrupts. */ 2993 si_disable_all_interrupts(si_ctlp); 2994 2995 if (si_ctlp->sictl_flags & SI_DETACH) { 2996 /* 2997 * We want to dealloc all the memory in detach case. 2998 */ 2999 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 3000 si_dealloc_port_state(si_ctlp, port); 3001 } 3002 } 3003 3004 } 3005 3006 /* 3007 * Prepare the port ready for usage. 3008 * 3009 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3010 * before calling us. 3011 */ 3012 static void 3013 si_init_port(si_ctl_state_t *si_ctlp, int port) 3014 { 3015 3016 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 3017 "si_init_port entered: port: 0x%x", 3018 port); 3019 3020 /* Initialize the port. */ 3021 ddi_put32(si_ctlp->sictl_port_acc_handle, 3022 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3023 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 3024 3025 /* 3026 * Clear the InterruptNCOR (Interupt No Clear on Read). 3027 * This step ensures that a mere reading of slot_status will clear 3028 * the interrupt; no explicit clearing of interrupt condition 3029 * will be needed for successful completion of commands. 3030 */ 3031 ddi_put32(si_ctlp->sictl_port_acc_handle, 3032 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3033 PORT_CONTROL_CLEAR_BITS_INTR_NCoR); 3034 3035 /* clear any pending interrupts at this point */ 3036 ddi_put32(si_ctlp->sictl_port_acc_handle, 3037 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3038 INTR_MASK); 3039 3040 } 3041 3042 3043 /* 3044 * Enumerate the devices connected to the port multiplier. 3045 * Once a device is detected, we call si_find_dev_signature() 3046 * to find the type of device connected. Even though we are 3047 * called from within si_find_dev_signature(), there is no 3048 * recursion possible. 3049 */ 3050 static int 3051 si_enumerate_port_multiplier( 3052 si_ctl_state_t *si_ctlp, 3053 si_port_state_t *si_portp, 3054 int port) 3055 { 3056 uint32_t num_dev_ports = 0; 3057 int pmport; 3058 uint32_t SControl = 0; 3059 uint32_t SStatus = 0; 3060 uint32_t SError = 0; 3061 int loop_count = 0; 3062 3063 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 3064 "si_enumerate_port_multiplier entered: port: %d", 3065 port); 3066 3067 mutex_enter(&si_portp->siport_mutex); 3068 3069 /* Enable Port Multiplier context switching. */ 3070 ddi_put32(si_ctlp->sictl_port_acc_handle, 3071 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3072 PORT_CONTROL_SET_BITS_PM_ENABLE); 3073 3074 /* 3075 * Read the num dev ports connected. 3076 * GSCR[2] contains the number of device ports. 3077 */ 3078 if (si_read_portmult_reg(si_ctlp, si_portp, port, PORTMULT_CONTROL_PORT, 3079 PSCR_REG2, &num_dev_ports)) { 3080 mutex_exit(&si_portp->siport_mutex); 3081 return (SI_FAILURE); 3082 } 3083 si_portp->siport_portmult_state.sipm_num_ports = num_dev_ports; 3084 3085 SIDBG1(SIDBG_INIT, si_ctlp, 3086 "si_enumerate_port_multiplier: ports found: %d", 3087 num_dev_ports); 3088 3089 for (pmport = 0; pmport < num_dev_ports-1; pmport++) { 3090 /* 3091 * Enable PHY by writing a 1, then a 0 to SControl 3092 * (i.e. PSCR[2]) DET field. 3093 */ 3094 if (si_read_portmult_reg(si_ctlp, si_portp, port, pmport, 3095 PSCR_REG2, &SControl)) { 3096 continue; 3097 } 3098 3099 /* First write a 1 to DET field of SControl. */ 3100 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 3101 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3102 PSCR_REG2, SControl)) { 3103 continue; 3104 } 3105 #ifndef __lock_lint 3106 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 3107 #endif /* __lock_lint */ 3108 3109 /* Then write a 0 to the DET field of SControl. */ 3110 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 3111 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3112 PSCR_REG2, SControl)) { 3113 continue; 3114 } 3115 3116 /* Wait for PHYRDY by polling SStatus (i.e. PSCR[0]). */ 3117 loop_count = 0; 3118 do { 3119 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3120 pmport, PSCR_REG0, &SStatus)) { 3121 break; 3122 } 3123 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3124 "looping for PHYRDY: SStatus: %x", 3125 SStatus); 3126 3127 if (SSTATUS_GET_IPM(SStatus) != 3128 SSTATUS_IPM_INTERFACE_ACTIVE) { 3129 /* 3130 * If the interface is not active, the DET field 3131 * is considered not accurate. So we want to 3132 * continue looping. 3133 */ 3134 SSTATUS_SET_DET(SStatus, 3135 SSTATUS_DET_NODEV_NOPHY); 3136 } 3137 3138 if (loop_count++ > SI_POLLRATE_SSTATUS) { 3139 /* 3140 * We are effectively timing out after 0.1 sec. 3141 */ 3142 break; 3143 } 3144 3145 /* Wait for 10 millisec */ 3146 #ifndef __lock_lint 3147 delay(SI_10MS_TICKS); 3148 #endif /* __lock_lint */ 3149 3150 } while (SSTATUS_GET_DET(SStatus) != 3151 SSTATUS_DET_DEVPRESENT_PHYONLINE); 3152 3153 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 3154 "si_enumerate_port_multiplier: " 3155 "loop count: %d, SStatus: 0x%x", 3156 loop_count, 3157 SStatus); 3158 3159 if ((SSTATUS_GET_IPM(SStatus) == 3160 SSTATUS_IPM_INTERFACE_ACTIVE) && 3161 (SSTATUS_GET_DET(SStatus) == 3162 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 3163 /* The interface is active and the device is present */ 3164 SIDBG1(SIDBG_INIT, si_ctlp, 3165 "Status: %x, device exists", 3166 SStatus); 3167 /* 3168 * Clear error bits in SError register (i.e. PSCR[1] 3169 * by writing back error bits. 3170 */ 3171 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3172 pmport, PSCR_REG1, &SError)) { 3173 continue; 3174 } 3175 SIDBG1(SIDBG_INIT, si_ctlp, 3176 "SError bits are: %x", SError); 3177 if (si_write_portmult_reg(si_ctlp, si_portp, port, 3178 pmport, PSCR_REG1, SError)) { 3179 continue; 3180 } 3181 3182 /* There exists a device. */ 3183 mutex_exit(&si_portp->siport_mutex); 3184 si_find_dev_signature(si_ctlp, si_portp, port, pmport); 3185 mutex_enter(&si_portp->siport_mutex); 3186 } 3187 } 3188 3189 mutex_exit(&si_portp->siport_mutex); 3190 3191 return (SI_SUCCESS); 3192 } 3193 3194 3195 /* 3196 * Read a port multiplier register. 3197 * 3198 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3199 * before calling us. 3200 */ 3201 static int 3202 si_read_portmult_reg( 3203 si_ctl_state_t *si_ctlp, 3204 si_port_state_t *si_portp, 3205 int port, 3206 int pmport, 3207 int regnum, 3208 uint32_t *regval) 3209 { 3210 int slot; 3211 si_prb_t *prb; 3212 uint32_t *prb_word_ptr; 3213 int i; 3214 uint32_t slot_status; 3215 int loop_count = 0; 3216 3217 _NOTE(ASSUMING_PROTECTED(si_portp)) 3218 3219 SIDBG3(SIDBG_ENTRY, si_ctlp, "si_read_portmult_reg: port: %x," 3220 "pmport: %x, regnum: %x", 3221 port, pmport, regnum); 3222 3223 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3224 if (slot == -1) { 3225 return (SI_FAILURE); 3226 } 3227 3228 prb = &(si_portp->siport_prbpool[slot]); 3229 bzero((void *)prb, sizeof (si_prb_t)); 3230 3231 /* Now fill the prb. */ 3232 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3233 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3234 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3235 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_PM_REG); 3236 3237 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3238 SET_FIS_FEATURES(prb->prb_fis, regnum); 3239 3240 /* no real data transfer is involved. */ 3241 SET_SGE_TRM(prb->prb_sge0); 3242 3243 #if SI_DEBUG 3244 if (si_debug_flags & SIDBG_DUMP_PRB) { 3245 int *ptr; 3246 int j; 3247 3248 ptr = (int *)prb; 3249 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3250 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3251 cmn_err(CE_WARN, "%x ", ptr[j]); 3252 } 3253 3254 } 3255 #endif /* SI_DEBUG */ 3256 3257 /* Deliver PRB */ 3258 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3259 3260 /* Loop till the command is finished. */ 3261 do { 3262 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3263 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3264 3265 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3266 "looping read_pm slot_status: 0x%x", 3267 slot_status); 3268 3269 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3270 /* We are effectively timing out after 0.5 sec. */ 3271 break; 3272 } 3273 3274 /* Wait for 10 millisec */ 3275 #ifndef __lock_lint 3276 delay(SI_10MS_TICKS); 3277 #endif /* __lock_lint */ 3278 3279 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3280 3281 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3282 "read_portmult_reg: loop count: %d", 3283 loop_count); 3284 3285 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3286 3287 /* Now inspect the port LRAM for the modified FIS. */ 3288 prb_word_ptr = (uint32_t *)prb; 3289 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3290 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3291 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3292 } 3293 3294 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3295 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3296 /* command failed. */ 3297 return (SI_FAILURE); 3298 } 3299 3300 /* command succeeded. */ 3301 *regval = (GET_FIS_SECTOR_COUNT(prb->prb_fis) & 0xff) | 3302 ((GET_FIS_SECTOR(prb->prb_fis) << 8) & 0xff00) | 3303 ((GET_FIS_CYL_LOW(prb->prb_fis) << 16) & 0xff0000) | 3304 ((GET_FIS_CYL_HI(prb->prb_fis) << 24) & 0xff000000); 3305 3306 return (SI_SUCCESS); 3307 } 3308 3309 /* 3310 * Write a port multiplier register. 3311 * 3312 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3313 * before calling us. 3314 */ 3315 static int 3316 si_write_portmult_reg( 3317 si_ctl_state_t *si_ctlp, 3318 si_port_state_t *si_portp, 3319 int port, 3320 int pmport, 3321 int regnum, 3322 uint32_t regval) 3323 { 3324 int slot; 3325 si_prb_t *prb; 3326 uint32_t *prb_word_ptr; 3327 uint32_t slot_status; 3328 int i; 3329 int loop_count = 0; 3330 3331 _NOTE(ASSUMING_PROTECTED(si_portp)) 3332 3333 SIDBG4(SIDBG_ENTRY, si_ctlp, 3334 "si_write_portmult_reg: port: %x, pmport: %x," 3335 "regnum: %x, regval: %x", 3336 port, pmport, regnum, regval); 3337 3338 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3339 if (slot == -1) { 3340 return (SI_FAILURE); 3341 } 3342 3343 prb = &(si_portp->siport_prbpool[slot]); 3344 bzero((void *)prb, sizeof (si_prb_t)); 3345 3346 /* Now fill the prb. */ 3347 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3348 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3349 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3350 3351 SET_FIS_COMMAND(prb->prb_fis, SATAC_WRITE_PM_REG); 3352 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3353 SET_FIS_FEATURES(prb->prb_fis, regnum); 3354 3355 SET_FIS_SECTOR_COUNT(prb->prb_fis, regval & 0xff); 3356 SET_FIS_SECTOR(prb->prb_fis, (regval >> 8) & 0xff); 3357 SET_FIS_CYL_LOW(prb->prb_fis, (regval >> 16) & 0xff); 3358 SET_FIS_CYL_HI(prb->prb_fis, (regval >> 24) & 0xff); 3359 3360 /* no real data transfer is involved. */ 3361 SET_SGE_TRM(prb->prb_sge0); 3362 3363 #if SI_DEBUG 3364 if (si_debug_flags & SIDBG_DUMP_PRB) { 3365 int *ptr; 3366 int j; 3367 3368 ptr = (int *)prb; 3369 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3370 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3371 cmn_err(CE_WARN, "%x ", ptr[j]); 3372 } 3373 3374 } 3375 #endif /* SI_DEBUG */ 3376 3377 /* Deliver PRB */ 3378 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3379 3380 /* Loop till the command is finished. */ 3381 do { 3382 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3383 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3384 3385 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3386 "looping write_pmp slot_status: 0x%x", 3387 slot_status); 3388 3389 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3390 /* We are effectively timing out after 0.5 sec. */ 3391 break; 3392 } 3393 3394 /* Wait for 10 millisec */ 3395 #ifndef __lock_lint 3396 delay(SI_10MS_TICKS); 3397 #endif /* __lock_lint */ 3398 3399 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3400 3401 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3402 "write_portmult_reg: loop count: %d", 3403 loop_count); 3404 3405 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3406 3407 /* Now inspect the port LRAM for the modified FIS. */ 3408 prb_word_ptr = (uint32_t *)prb; 3409 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3410 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3411 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3412 } 3413 3414 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3415 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3416 /* command failed */ 3417 return (SI_FAILURE); 3418 } 3419 3420 /* command succeeded */ 3421 return (SI_SUCCESS); 3422 } 3423 3424 3425 /* 3426 * Set the auto sense data for ATAPI devices. 3427 * 3428 * Note: Currently the sense data is simulated; this code will be enhanced 3429 * in second phase to fetch the real sense data from the atapi device. 3430 */ 3431 static void 3432 si_set_sense_data(sata_pkt_t *satapkt, int reason) 3433 { 3434 struct scsi_extended_sense *sense; 3435 3436 sense = (struct scsi_extended_sense *) 3437 satapkt->satapkt_cmd.satacmd_rqsense; 3438 bzero(sense, sizeof (struct scsi_extended_sense)); 3439 sense->es_valid = 1; /* Valid sense */ 3440 sense->es_class = 7; /* Response code 0x70 - current err */ 3441 sense->es_key = 0; 3442 sense->es_info_1 = 0; 3443 sense->es_info_2 = 0; 3444 sense->es_info_3 = 0; 3445 sense->es_info_4 = 0; 3446 sense->es_add_len = 6; /* Additional length */ 3447 sense->es_cmd_info[0] = 0; 3448 sense->es_cmd_info[1] = 0; 3449 sense->es_cmd_info[2] = 0; 3450 sense->es_cmd_info[3] = 0; 3451 sense->es_add_code = 0; 3452 sense->es_qual_code = 0; 3453 3454 if ((reason == SATA_PKT_DEV_ERROR) || (reason == SATA_PKT_TIMEOUT)) { 3455 sense->es_key = KEY_HARDWARE_ERROR; 3456 } 3457 } 3458 3459 3460 /* 3461 * Interrupt service handler. We loop through each of the ports to find 3462 * if the interrupt belongs to any of them. 3463 * 3464 * Bulk of the interrupt handling is actually done out of subroutines 3465 * like si_intr_command_complete() etc. 3466 */ 3467 /*ARGSUSED*/ 3468 static uint_t 3469 si_intr(caddr_t arg1, caddr_t arg2) 3470 { 3471 3472 si_ctl_state_t *si_ctlp = (si_ctl_state_t *)arg1; 3473 si_port_state_t *si_portp; 3474 uint32_t global_intr_status; 3475 uint32_t mask, port_intr_status; 3476 int port; 3477 3478 global_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3479 (uint32_t *)GLOBAL_INTERRUPT_STATUS(si_ctlp)); 3480 3481 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3482 "si_intr: global_int_status: 0x%x", 3483 global_intr_status); 3484 3485 if (!(global_intr_status & SI31xx_INTR_PORT_MASK)) { 3486 /* Sorry, the interrupt is not ours. */ 3487 return (DDI_INTR_UNCLAIMED); 3488 } 3489 3490 /* Loop for all the ports. */ 3491 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 3492 3493 mask = 0x1 << port; 3494 if (!(global_intr_status & mask)) { 3495 continue; 3496 } 3497 3498 mutex_enter(&si_ctlp->sictl_mutex); 3499 si_portp = si_ctlp->sictl_ports[port]; 3500 mutex_exit(&si_ctlp->sictl_mutex); 3501 3502 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3503 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 3504 3505 SIDBG2(SIDBG_VERBOSE, si_ctlp, 3506 "s_intr: port_intr_status: 0x%x, port: %x", 3507 port_intr_status, 3508 port); 3509 3510 if (port_intr_status & INTR_COMMAND_COMPLETE) { 3511 (void) si_intr_command_complete(si_ctlp, si_portp, 3512 port); 3513 } 3514 3515 /* Clear the interrupts */ 3516 ddi_put32(si_ctlp->sictl_port_acc_handle, 3517 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3518 port_intr_status & INTR_MASK); 3519 3520 /* 3521 * Note that we did not clear the interrupt for command 3522 * completion interrupt. Reading of slot_status takes care 3523 * of clearing the interrupt for command completion case. 3524 */ 3525 3526 if (port_intr_status & INTR_COMMAND_ERROR) { 3527 (void) si_intr_command_error(si_ctlp, si_portp, port); 3528 } 3529 3530 if (port_intr_status & INTR_PORT_READY) { 3531 (void) si_intr_port_ready(si_ctlp, si_portp, port); 3532 } 3533 3534 if (port_intr_status & INTR_POWER_CHANGE) { 3535 (void) si_intr_pwr_change(si_ctlp, si_portp, port); 3536 } 3537 3538 if (port_intr_status & INTR_PHYRDY_CHANGE) { 3539 (void) si_intr_phy_ready_change(si_ctlp, si_portp, 3540 port); 3541 } 3542 3543 if (port_intr_status & INTR_COMWAKE_RECEIVED) { 3544 (void) si_intr_comwake_rcvd(si_ctlp, si_portp, 3545 port); 3546 } 3547 3548 if (port_intr_status & INTR_UNRECOG_FIS) { 3549 (void) si_intr_unrecognised_fis(si_ctlp, si_portp, 3550 port); 3551 } 3552 3553 if (port_intr_status & INTR_DEV_XCHANGED) { 3554 (void) si_intr_dev_xchanged(si_ctlp, si_portp, port); 3555 } 3556 3557 if (port_intr_status & INTR_8B10B_DECODE_ERROR) { 3558 (void) si_intr_decode_err_threshold(si_ctlp, si_portp, 3559 port); 3560 } 3561 3562 if (port_intr_status & INTR_CRC_ERROR) { 3563 (void) si_intr_crc_err_threshold(si_ctlp, si_portp, 3564 port); 3565 } 3566 3567 if (port_intr_status & INTR_HANDSHAKE_ERROR) { 3568 (void) si_intr_handshake_err_threshold(si_ctlp, 3569 si_portp, port); 3570 } 3571 3572 if (port_intr_status & INTR_SETDEVBITS_NOTIFY) { 3573 (void) si_intr_set_devbits_notify(si_ctlp, si_portp, 3574 port); 3575 } 3576 } 3577 3578 return (DDI_INTR_CLAIMED); 3579 } 3580 3581 /* 3582 * Interrupt which indicates that one or more commands have successfully 3583 * completed. 3584 * 3585 * Since we disabled W1C (write-one-to-clear) previously, mere reading 3586 * of slot_status register clears the interrupt. There is no need to 3587 * explicitly clear the interrupt. 3588 */ 3589 static int 3590 si_intr_command_complete( 3591 si_ctl_state_t *si_ctlp, 3592 si_port_state_t *si_portp, 3593 int port) 3594 { 3595 3596 uint32_t slot_status; 3597 uint32_t finished_tags; 3598 int finished_slot; 3599 sata_pkt_t *satapkt; 3600 3601 SIDBG0(SIDBG_ENTRY|SIDBG_INTR, si_ctlp, 3602 "si_intr_command_complete enter"); 3603 3604 mutex_enter(&si_portp->siport_mutex); 3605 3606 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3607 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3608 3609 if (!si_portp->siport_pending_tags) { 3610 /* 3611 * Spurious interrupt. Nothing to be done. 3612 * Do read the slot_status to clear the interrupt. 3613 */ 3614 mutex_exit(&si_portp->siport_mutex); 3615 return (SI_SUCCESS); 3616 } 3617 3618 SIDBG2(SIDBG_VERBOSE, si_ctlp, "si3124: si_intr_command_complete: " 3619 "pending_tags: %x, slot_status: %x", 3620 si_portp->siport_pending_tags, 3621 slot_status); 3622 3623 finished_tags = si_portp->siport_pending_tags & 3624 ~slot_status & SI_SLOT_MASK; 3625 while (finished_tags) { 3626 si_prb_t *prb; 3627 3628 finished_slot = ddi_ffs(finished_tags) - 1; 3629 if (finished_slot == -1) { 3630 break; 3631 } 3632 prb = &si_portp->siport_prbpool[finished_slot]; 3633 3634 satapkt = si_portp->siport_slot_pkts[finished_slot]; 3635 satapkt->satapkt_cmd.satacmd_status_reg = 3636 GET_FIS_COMMAND(prb->prb_fis); 3637 3638 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 3639 si_copy_out_regs(&satapkt->satapkt_cmd, &prb->prb_fis); 3640 3641 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 3642 3643 CLEAR_BIT(si_portp->siport_pending_tags, finished_slot); 3644 CLEAR_BIT(finished_tags, finished_slot); 3645 } 3646 3647 SIDBG2(SIDBG_PKTCOMP, si_ctlp, 3648 "command_complete done: pend_tags: 0x%x, slot_status: 0x%x", 3649 si_portp->siport_pending_tags, 3650 slot_status); 3651 3652 /* 3653 * tidbit: no need to clear the interrupt since reading of 3654 * slot_status automatically clears the interrupt in the case 3655 * of a successful command completion. 3656 */ 3657 3658 mutex_exit(&si_portp->siport_mutex); 3659 3660 return (SI_SUCCESS); 3661 } 3662 3663 /* 3664 * Interrupt which indicates that a command did not complete successfully. 3665 * 3666 * The port halts whenever a command error interrupt is received. 3667 * The only way to restart it is to reset or reinitialize the port 3668 * but such an operation throws away all the pending commands on 3669 * the port. 3670 * 3671 * We reset the device and mop the commands on the port. 3672 */ 3673 static int 3674 si_intr_command_error( 3675 si_ctl_state_t *si_ctlp, 3676 si_port_state_t *si_portp, 3677 int port) 3678 { 3679 uint32_t command_error, slot_status; 3680 uint32_t failed_tags; 3681 3682 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3683 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3684 3685 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3686 "si_intr_command_error: command_error: 0x%x", 3687 command_error); 3688 3689 mutex_enter(&si_portp->siport_mutex); 3690 3691 /* 3692 * Remember the slot_status since any of the recovery handler 3693 * can blow it away with reset operation. 3694 */ 3695 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3696 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3697 3698 si_log_error_message(si_ctlp, port, command_error); 3699 3700 switch (command_error) { 3701 3702 case CMD_ERR_DEVICEERRROR: 3703 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3704 break; 3705 3706 case CMD_ERR_SDBERROR: 3707 si_error_recovery_SDBERROR(si_ctlp, si_portp, port); 3708 break; 3709 3710 case CMD_ERR_DATAFISERROR: 3711 si_error_recovery_DATAFISERROR(si_ctlp, si_portp, port); 3712 break; 3713 3714 case CMD_ERR_SENDFISERROR: 3715 si_error_recovery_SENDFISERROR(si_ctlp, si_portp, port); 3716 break; 3717 3718 default: 3719 si_error_recovery_default(si_ctlp, si_portp, port); 3720 break; 3721 3722 } 3723 3724 /* 3725 * Compute the failed_tags by adding up the error tags. 3726 * 3727 * The siport_err_tags_SDBERROR and siport_err_tags_nonSDBERROR 3728 * were filled in by the si_error_recovery_* routines. 3729 */ 3730 failed_tags = si_portp->siport_pending_tags & 3731 (si_portp->siport_err_tags_SDBERROR | 3732 si_portp->siport_err_tags_nonSDBERROR); 3733 3734 SIDBG3(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si_intr_command_error: " 3735 "err_tags_SDBERROR: 0x%x, " 3736 "err_tags_nonSDBERRROR: 0x%x, " 3737 "failed_tags: 0x%x", 3738 si_portp->siport_err_tags_SDBERROR, 3739 si_portp->siport_err_tags_nonSDBERROR, 3740 failed_tags); 3741 3742 SIDBG2(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si3124: si_intr_command_error: " 3743 "slot_status:0x%x, pending_tags: 0x%x", 3744 slot_status, 3745 si_portp->siport_pending_tags); 3746 3747 mutex_exit(&si_portp->siport_mutex); 3748 si_mop_commands(si_ctlp, 3749 si_portp, 3750 port, 3751 slot_status, 3752 failed_tags, 3753 0, /* timedout_tags */ 3754 0, /* aborting_tags */ 3755 0); /* reset_tags */ 3756 mutex_enter(&si_portp->siport_mutex); 3757 3758 ASSERT(si_portp->siport_pending_tags == 0); 3759 3760 si_portp->siport_err_tags_SDBERROR = 0; 3761 si_portp->siport_err_tags_nonSDBERROR = 0; 3762 3763 mutex_exit(&si_portp->siport_mutex); 3764 3765 return (SI_SUCCESS); 3766 } 3767 3768 /* 3769 * There is a subtle difference between errors on a normal port and 3770 * a port-mult port. When an error happens on a normal port, the port 3771 * is halted effectively until the port is reset or initialized. 3772 * However, in port-mult port errors, port does not get halted since 3773 * other non-error devices behind the port multiplier can still 3774 * continue to operate. So we wait till all the commands are drained 3775 * instead of resetting it right away. 3776 * 3777 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3778 * before calling us. 3779 */ 3780 static void 3781 si_recover_portmult_errors( 3782 si_ctl_state_t *si_ctlp, 3783 si_port_state_t *si_portp, 3784 int port) 3785 { 3786 uint32_t command_error, slot_status, port_status; 3787 int failed_slot; 3788 int loop_count = 0; 3789 3790 _NOTE(ASSUMING_PROTECTED(si_portp)) 3791 3792 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3793 "si_recover_portmult_errors: port: 0x%x", 3794 port); 3795 3796 /* Resume the port */ 3797 ddi_put32(si_ctlp->sictl_port_acc_handle, 3798 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3799 PORT_CONTROL_SET_BITS_RESUME); 3800 3801 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3802 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3803 3804 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3805 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3806 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3807 3808 if (command_error == CMD_ERR_SDBERROR) { 3809 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3810 } else { 3811 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3812 } 3813 3814 /* Now we drain the pending commands. */ 3815 do { 3816 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3817 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3818 3819 /* 3820 * Since we have not yet returned DDI_INTR_CLAIMED, 3821 * our interrupt handler is guaranteed not to be called again. 3822 * So we need to check IS_ATTENTION_RAISED() for further 3823 * decisions. 3824 * 3825 * This is a too big a delay for an interrupt context. 3826 * But this is supposed to be a rare condition. 3827 */ 3828 3829 if (IS_ATTENTION_RAISED(slot_status)) { 3830 /* Resume again */ 3831 ddi_put32(si_ctlp->sictl_port_acc_handle, 3832 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3833 PORT_CONTROL_SET_BITS_RESUME); 3834 3835 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3836 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3837 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3838 command_error = ddi_get32( 3839 si_ctlp->sictl_port_acc_handle, 3840 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, 3841 port))); 3842 if (command_error == CMD_ERR_SDBERROR) { 3843 si_portp->siport_err_tags_SDBERROR |= 3844 (0x1 << failed_slot); 3845 } else { 3846 si_portp->siport_err_tags_nonSDBERROR |= 3847 (0x1 << failed_slot); 3848 } 3849 } 3850 3851 if (loop_count++ > SI_POLLRATE_RECOVERPORTMULT) { 3852 /* We are effectively timing out after 10 sec. */ 3853 break; 3854 } 3855 3856 /* Wait for 10 millisec */ 3857 #ifndef __lock_lint 3858 delay(SI_10MS_TICKS); 3859 #endif /* __lock_lint */ 3860 3861 } while (slot_status & SI_SLOT_MASK); 3862 3863 /* 3864 * The above loop can be improved for 3132 since we could obtain the 3865 * Port Multiplier Context of the device in error. Then we could 3866 * do a better job in filtering out commands for the device in error. 3867 * The loop could finish much earlier with such a logic. 3868 */ 3869 3870 /* Clear the RESUME bit. */ 3871 ddi_put32(si_ctlp->sictl_port_acc_handle, 3872 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3873 PORT_CONTROL_CLEAR_BITS_RESUME); 3874 3875 } 3876 3877 /* 3878 * If we are connected to port multiplier, drain the non-failed devices. 3879 * Otherwise, we initialize the port (which effectively fails all the 3880 * pending commands in the hope that sd would retry them later). 3881 * 3882 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3883 * before calling us. 3884 */ 3885 static void 3886 si_error_recovery_DEVICEERROR( 3887 si_ctl_state_t *si_ctlp, 3888 si_port_state_t *si_portp, 3889 int port) 3890 { 3891 uint32_t port_status; 3892 int failed_slot; 3893 3894 _NOTE(ASSUMING_PROTECTED(si_portp)) 3895 3896 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3897 "si_error_recovery_DEVICEERROR: port: 0x%x", 3898 port); 3899 3900 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3901 si_recover_portmult_errors(si_ctlp, si_portp, port); 3902 } else { 3903 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3904 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3905 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3906 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3907 } 3908 3909 /* In either case (port-mult or not), we reinitialize the port. */ 3910 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3911 } 3912 3913 /* 3914 * Handle exactly like DEVICEERROR. Remember the tags with SDBERROR 3915 * to perform read_log_ext on them later. SDBERROR means that the 3916 * error was for an NCQ command. 3917 * 3918 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3919 * before calling us. 3920 */ 3921 static void 3922 si_error_recovery_SDBERROR( 3923 si_ctl_state_t *si_ctlp, 3924 si_port_state_t *si_portp, 3925 int port) 3926 { 3927 uint32_t port_status; 3928 int failed_slot; 3929 3930 _NOTE(ASSUMING_PROTECTED(si_portp)) 3931 3932 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3933 "si3124: si_error_recovery_SDBERROR: port: 0x%x", 3934 port); 3935 3936 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3937 si_recover_portmult_errors(si_ctlp, si_portp, port); 3938 } else { 3939 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3940 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3941 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3942 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3943 } 3944 3945 /* In either case (port-mult or not), we reinitialize the port. */ 3946 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3947 } 3948 3949 /* 3950 * Handle exactly like DEVICEERROR except resetting the port if there was 3951 * an NCQ command on the port. 3952 * 3953 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3954 * before calling us. 3955 */ 3956 static void 3957 si_error_recovery_DATAFISERROR( 3958 si_ctl_state_t *si_ctlp, 3959 si_port_state_t *si_portp, 3960 int port) 3961 { 3962 uint32_t port_status; 3963 int failed_slot; 3964 3965 _NOTE(ASSUMING_PROTECTED(si_portp)) 3966 3967 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3968 "si3124: si_error_recovery_DATAFISERROR: port: 0x%x", 3969 port); 3970 3971 /* reset device if we were waiting for any ncq commands. */ 3972 if (si_portp->siport_pending_ncq_count) { 3973 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3974 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3975 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3976 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3977 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 3978 SI_DEVICE_RESET); 3979 return; 3980 } 3981 3982 /* 3983 * If we don't have any ncq commands pending, the rest of 3984 * the process is similar to the one for DEVICEERROR. 3985 */ 3986 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3987 } 3988 3989 /* 3990 * We handle just like DEVICERROR except that we reset the device instead 3991 * of initializing the port. 3992 * 3993 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3994 * before calling us. 3995 */ 3996 static void 3997 si_error_recovery_SENDFISERROR( 3998 si_ctl_state_t *si_ctlp, 3999 si_port_state_t *si_portp, 4000 int port) 4001 { 4002 uint32_t port_status; 4003 int failed_slot; 4004 4005 _NOTE(ASSUMING_PROTECTED(si_portp)) 4006 4007 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 4008 "si3124: si_error_recovery_SENDFISERROR: port: 0x%x", 4009 port); 4010 4011 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 4012 si_recover_portmult_errors(si_ctlp, si_portp, port); 4013 } else { 4014 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4015 (uint32_t *)PORT_STATUS(si_ctlp, port)); 4016 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 4017 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 4018 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 4019 SI_DEVICE_RESET); 4020 } 4021 } 4022 4023 /* 4024 * The default behavior for all other errors is to reset the device. 4025 * 4026 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4027 * before calling us. 4028 */ 4029 static void 4030 si_error_recovery_default( 4031 si_ctl_state_t *si_ctlp, 4032 si_port_state_t *si_portp, 4033 int port) 4034 { 4035 uint32_t port_status; 4036 int failed_slot; 4037 4038 _NOTE(ASSUMING_PROTECTED(si_portp)) 4039 4040 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 4041 "si3124: si_error_recovery_default: port: 0x%x", 4042 port); 4043 4044 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4045 (uint32_t *)PORT_STATUS(si_ctlp, port)); 4046 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 4047 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 4048 4049 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 4050 SI_DEVICE_RESET); 4051 } 4052 4053 /* 4054 * Read Log Ext with PAGE 10 to retrieve the error for an NCQ command. 4055 * 4056 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4057 * before calling us. 4058 */ 4059 static uint8_t 4060 si_read_log_ext(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 4061 { 4062 int slot; 4063 si_prb_t *prb; 4064 int i; 4065 uint32_t slot_status; 4066 int loop_count = 0; 4067 uint32_t *prb_word_ptr; 4068 uint8_t error; 4069 4070 _NOTE(ASSUMING_PROTECTED(si_portp)) 4071 4072 SIDBG1(SIDBG_ENTRY|SIDBG_ERRS, si_ctlp, 4073 "si_read_log_ext: port: %x", port); 4074 4075 slot = si_claim_free_slot(si_ctlp, si_portp, port); 4076 if (slot == -1) { 4077 return (0); 4078 } 4079 4080 prb = &(si_portp->siport_prbpool[slot]); 4081 bzero((void *)prb, sizeof (si_prb_t)); 4082 4083 /* Now fill the prb */ 4084 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 4085 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 4086 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 4087 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_LOG_EXT); 4088 SET_FIS_SECTOR(prb->prb_fis, SATA_LOG_PAGE_10); 4089 4090 /* no real data transfer is involved */ 4091 SET_SGE_TRM(prb->prb_sge0); 4092 4093 #if SI_DEBUG 4094 if (si_debug_flags & SIDBG_DUMP_PRB) { 4095 int *ptr; 4096 int j; 4097 4098 ptr = (int *)prb; 4099 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 4100 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 4101 cmn_err(CE_WARN, "%x ", ptr[j]); 4102 } 4103 4104 } 4105 #endif /* SI_DEBUG */ 4106 4107 /* Deliver PRB */ 4108 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 4109 4110 /* Loop till the command is finished. */ 4111 do { 4112 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4113 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 4114 4115 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4116 "looping read_log_ext slot_status: 0x%x", 4117 slot_status); 4118 4119 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 4120 /* We are effectively timing out after 0.5 sec. */ 4121 break; 4122 } 4123 4124 /* Wait for 10 millisec */ 4125 #ifndef __lock_lint 4126 delay(SI_10MS_TICKS); 4127 #endif /* __lock_lint */ 4128 4129 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 4130 4131 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 4132 /* 4133 * If we fail with the READ LOG EXT command, we need to 4134 * initialize the port to clear the slot_status register. 4135 * We don't need to worry about any other valid commands 4136 * being thrown away because we are already in recovery 4137 * mode and READ LOG EXT is the only pending command. 4138 */ 4139 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 4140 } 4141 4142 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4143 "read_portmult_reg: loop count: %d", 4144 loop_count); 4145 4146 /* 4147 * The LRAM contains the the modified FIS. 4148 * Read the modified FIS to obtain the Error. 4149 */ 4150 prb_word_ptr = (uint32_t *)prb; 4151 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 4152 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 4153 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 4154 } 4155 error = GET_FIS_FEATURES(prb->prb_fis); 4156 4157 CLEAR_BIT(si_portp->siport_pending_tags, slot); 4158 4159 return (error); 4160 4161 } 4162 4163 /* 4164 * Dump the error message to the log. 4165 */ 4166 static void 4167 si_log_error_message(si_ctl_state_t *si_ctlp, int port, uint32_t command_error) 4168 { 4169 char *errstr; 4170 4171 switch (command_error) { 4172 4173 case CMD_ERR_DEVICEERRROR: 4174 errstr = "Standard Error: Error bit set in register - device" 4175 " to host FIS"; 4176 break; 4177 4178 case CMD_ERR_SDBERROR: 4179 errstr = "NCQ Error: Error bit set in register - device" 4180 " to host FIS"; 4181 break; 4182 4183 case CMD_ERR_DATAFISERROR: 4184 errstr = "Error in data FIS not detected by device"; 4185 break; 4186 4187 case CMD_ERR_SENDFISERROR: 4188 errstr = "Initial command FIS transmission failed"; 4189 break; 4190 4191 case CMD_ERR_INCONSISTENTSTATE: 4192 errstr = "Inconsistency in protocol"; 4193 break; 4194 4195 case CMD_ERR_DIRECTIONERROR: 4196 errstr = "DMA direction flag does not match the command"; 4197 break; 4198 4199 case CMD_ERR_UNDERRUNERROR: 4200 errstr = "Run out of scatter gather entries while writing data"; 4201 break; 4202 4203 case CMD_ERR_OVERRUNERROR: 4204 errstr = "Run out of scatter gather entries while reading data"; 4205 break; 4206 4207 case CMD_ERR_PACKETPROTOCOLERROR: 4208 errstr = "Packet protocol error"; 4209 break; 4210 4211 case CMD_ERR_PLDSGTERRORBOUNDARY: 4212 errstr = "Scatter/gather table not on quadword boundary"; 4213 break; 4214 4215 case CMD_ERR_PLDSGTERRORTARETABORT: 4216 errstr = "PCI(X) Target abort while fetching scatter/gather" 4217 " table"; 4218 break; 4219 4220 case CMD_ERR_PLDSGTERRORMASTERABORT: 4221 errstr = "PCI(X) Master abort while fetching scatter/gather" 4222 " table"; 4223 break; 4224 4225 case CMD_ERR_PLDSGTERRORPCIERR: 4226 errstr = "PCI(X) parity error while fetching scatter/gather" 4227 " table"; 4228 break; 4229 4230 case CMD_ERR_PLDCMDERRORBOUNDARY: 4231 errstr = "PRB not on quadword boundary"; 4232 break; 4233 4234 case CMD_ERR_PLDCMDERRORTARGETABORT: 4235 errstr = "PCI(X) Target abort while fetching PRB"; 4236 break; 4237 4238 case CMD_ERR_PLDCMDERRORMASTERABORT: 4239 errstr = "PCI(X) Master abort while fetching PRB"; 4240 break; 4241 4242 case CMD_ERR_PLDCMDERORPCIERR: 4243 errstr = "PCI(X) parity error while fetching PRB"; 4244 break; 4245 4246 case CMD_ERR_PSDERRORTARGETABORT: 4247 errstr = "PCI(X) Target abort during data transfer"; 4248 break; 4249 4250 case CMD_ERR_PSDERRORMASTERABORT: 4251 errstr = "PCI(X) Master abort during data transfer"; 4252 break; 4253 4254 case CMD_ERR_PSDERRORPCIERR: 4255 errstr = "PCI(X) parity error during data transfer"; 4256 break; 4257 4258 case CMD_ERR_SENDSERVICEERROR: 4259 errstr = "FIS received while sending service FIS in" 4260 " legacy queuing operation"; 4261 break; 4262 4263 default: 4264 errstr = "Unknown Error"; 4265 break; 4266 4267 } 4268 4269 SIDBG2(SIDBG_ERRS, si_ctlp, 4270 "command error: port: 0x%x, error: %s", 4271 port, 4272 errstr); 4273 4274 } 4275 4276 4277 /* 4278 * Interrupt which indicates that the Port Ready state has changed 4279 * from zero to one. 4280 * 4281 * We are not interested in this interrupt; we just log a debug message. 4282 */ 4283 /*ARGSUSED*/ 4284 static int 4285 si_intr_port_ready( 4286 si_ctl_state_t *si_ctlp, 4287 si_port_state_t *si_portp, 4288 int port) 4289 { 4290 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_ready"); 4291 return (SI_SUCCESS); 4292 } 4293 4294 /* 4295 * Interrupt which indicates that the port power management state 4296 * has been modified. 4297 * 4298 * We are not interested in this interrupt; we just log a debug message. 4299 */ 4300 /*ARGSUSED*/ 4301 static int 4302 si_intr_pwr_change( 4303 si_ctl_state_t *si_ctlp, 4304 si_port_state_t *si_portp, 4305 int port) 4306 { 4307 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_pwr_change"); 4308 return (SI_SUCCESS); 4309 } 4310 4311 /* 4312 * Interrupt which indicates that the PHY sate has changed either from 4313 * Not-Ready to Ready or from Ready to Not-Ready. 4314 */ 4315 static int 4316 si_intr_phy_ready_change( 4317 si_ctl_state_t *si_ctlp, 4318 si_port_state_t *si_portp, 4319 int port) 4320 { 4321 sata_device_t sdevice; 4322 uint32_t SStatus = 0; /* No dev present & PHY not established. */ 4323 int dev_exists_now = 0; 4324 int dev_existed_previously = 0; 4325 4326 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_phy_rdy_change"); 4327 4328 mutex_enter(&si_ctlp->sictl_mutex); 4329 if ((si_ctlp->sictl_sata_hba_tran == NULL) || (si_portp == NULL)) { 4330 /* the whole controller setup is not yet done. */ 4331 mutex_exit(&si_ctlp->sictl_mutex); 4332 return (SI_SUCCESS); 4333 } 4334 4335 mutex_exit(&si_ctlp->sictl_mutex); 4336 4337 mutex_enter(&si_portp->siport_mutex); 4338 4339 /* SStatus tells the presence of device. */ 4340 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4341 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 4342 dev_exists_now = 4343 (SSTATUS_GET_DET(SStatus) == SSTATUS_DET_DEVPRESENT_PHYONLINE); 4344 4345 if (si_portp->siport_port_type != PORT_TYPE_NODEV) { 4346 dev_existed_previously = 1; 4347 } 4348 4349 bzero((void *)&sdevice, sizeof (sata_device_t)); 4350 sdevice.satadev_addr.cport = port; 4351 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 4352 4353 /* we don't have a way of determining the exact port-mult port. */ 4354 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 4355 sdevice.satadev_addr.qual = SATA_ADDR_PMPORT; 4356 } else { 4357 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4358 } 4359 4360 sdevice.satadev_state = SATA_PSTATE_PWRON; 4361 4362 if (dev_exists_now) { 4363 if (dev_existed_previously) { 4364 4365 /* Things are fine now. The loss was temporary. */ 4366 SIDBG0(SIDBG_INTR, NULL, 4367 "phyrdy: doing BOTH EVENTS TOGETHER"); 4368 if (si_portp->siport_active) { 4369 SIDBG0(SIDBG_EVENT, si_ctlp, 4370 "sending event: LINK_LOST & " 4371 "LINK_ESTABLISHED"); 4372 4373 sata_hba_event_notify( 4374 si_ctlp->sictl_sata_hba_tran->\ 4375 sata_tran_hba_dip, 4376 &sdevice, 4377 SATA_EVNT_LINK_LOST| 4378 SATA_EVNT_LINK_ESTABLISHED); 4379 } 4380 4381 } else { 4382 4383 /* A new device has been detected. */ 4384 mutex_exit(&si_portp->siport_mutex); 4385 si_find_dev_signature(si_ctlp, si_portp, port, 4386 PORTMULT_CONTROL_PORT); 4387 mutex_enter(&si_portp->siport_mutex); 4388 SIDBG0(SIDBG_INTR, NULL, "phyrdy: doing ATTACH event"); 4389 if (si_portp->siport_active) { 4390 SIDBG0(SIDBG_EVENT, si_ctlp, 4391 "sending event up: LINK_ESTABLISHED"); 4392 4393 sata_hba_event_notify( 4394 si_ctlp->sictl_sata_hba_tran->\ 4395 sata_tran_hba_dip, 4396 &sdevice, 4397 SATA_EVNT_LINK_ESTABLISHED); 4398 } 4399 4400 } 4401 } else { /* No device exists now */ 4402 4403 if (dev_existed_previously) { 4404 4405 /* An existing device is lost. */ 4406 if (si_portp->siport_active) { 4407 SIDBG0(SIDBG_EVENT, si_ctlp, 4408 "sending event up: LINK_LOST"); 4409 4410 sata_hba_event_notify( 4411 si_ctlp->sictl_sata_hba_tran-> 4412 sata_tran_hba_dip, 4413 &sdevice, 4414 SATA_EVNT_LINK_LOST); 4415 } 4416 si_portp->siport_port_type = PORT_TYPE_NODEV; 4417 4418 } else { 4419 4420 /* spurious interrupt */ 4421 SIDBG0(SIDBG_INTR, NULL, 4422 "spurious phy ready interrupt"); 4423 } 4424 } 4425 4426 mutex_exit(&si_portp->siport_mutex); 4427 return (SI_SUCCESS); 4428 } 4429 4430 4431 /* 4432 * Interrupt which indicates that a COMWAKE OOB signal has been decoded 4433 * on the receiver. 4434 * 4435 * We are not interested in this interrupt; we just log a debug message. 4436 */ 4437 /*ARGSUSED*/ 4438 static int 4439 si_intr_comwake_rcvd( 4440 si_ctl_state_t *si_ctlp, 4441 si_port_state_t *si_portp, 4442 int port) 4443 { 4444 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_commwake_rcvd"); 4445 return (SI_SUCCESS); 4446 } 4447 4448 /* 4449 * Interrupt which indicates that the F-bit has been set in SError 4450 * Diag field. 4451 * 4452 * We are not interested in this interrupt; we just log a debug message. 4453 */ 4454 /*ARGSUSED*/ 4455 static int 4456 si_intr_unrecognised_fis( 4457 si_ctl_state_t *si_ctlp, 4458 si_port_state_t *si_portp, 4459 int port) 4460 { 4461 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_unrecognised_fis"); 4462 return (SI_SUCCESS); 4463 } 4464 4465 /* 4466 * Interrupt which indicates that the X-bit has been set in SError 4467 * Diag field. 4468 * 4469 * We are not interested in this interrupt; we just log a debug message. 4470 */ 4471 /*ARGSUSED*/ 4472 static int 4473 si_intr_dev_xchanged( 4474 si_ctl_state_t *si_ctlp, 4475 si_port_state_t *si_portp, 4476 int port) 4477 { 4478 4479 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_dev_xchanged"); 4480 return (SI_SUCCESS); 4481 } 4482 4483 /* 4484 * Interrupt which indicates that the 8b/10 Decode Error counter has 4485 * exceeded the programmed non-zero threshold value. 4486 * 4487 * We are not interested in this interrupt; we just log a debug message. 4488 */ 4489 /*ARGSUSED*/ 4490 static int 4491 si_intr_decode_err_threshold( 4492 si_ctl_state_t *si_ctlp, 4493 si_port_state_t *si_portp, 4494 int port) 4495 { 4496 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_err_threshold"); 4497 return (SI_SUCCESS); 4498 } 4499 4500 /* 4501 * Interrupt which indicates that the CRC Error counter has exceeded the 4502 * programmed non-zero threshold value. 4503 * 4504 * We are not interested in this interrupt; we just log a debug message. 4505 */ 4506 /*ARGSUSED*/ 4507 static int 4508 si_intr_crc_err_threshold( 4509 si_ctl_state_t *si_ctlp, 4510 si_port_state_t *si_portp, 4511 int port) 4512 { 4513 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_crc_threshold"); 4514 return (SI_SUCCESS); 4515 } 4516 4517 /* 4518 * Interrupt which indicates that the Handshake Error counter has 4519 * exceeded the programmed non-zero threshold value. 4520 * 4521 * We are not interested in this interrupt; we just log a debug message. 4522 */ 4523 /*ARGSUSED*/ 4524 static int 4525 si_intr_handshake_err_threshold( 4526 si_ctl_state_t *si_ctlp, 4527 si_port_state_t *si_portp, 4528 int port) 4529 { 4530 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 4531 "si_intr_handshake_err_threshold"); 4532 return (SI_SUCCESS); 4533 } 4534 4535 /* 4536 * Interrupt which indicates that a "Set Device Bits" FIS has been 4537 * received with N-bit set in the control field. 4538 * 4539 * We are not interested in this interrupt; we just log a debug message. 4540 */ 4541 /*ARGSUSED*/ 4542 static int 4543 si_intr_set_devbits_notify( 4544 si_ctl_state_t *si_ctlp, 4545 si_port_state_t *si_portp, 4546 int port) 4547 { 4548 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_set_devbits_notify"); 4549 return (SI_SUCCESS); 4550 } 4551 4552 4553 /* 4554 * Enable the interrupts for a particular port. 4555 * 4556 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4557 * before calling us. 4558 */ 4559 static void 4560 si_enable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4561 { 4562 uint32_t mask; 4563 4564 /* get the current settings first. */ 4565 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4566 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4567 4568 SIDBG1(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 4569 "si_enable_port_interrupts: current mask: 0x%x", 4570 mask); 4571 4572 /* enable the bit for current port. */ 4573 SET_BIT(mask, port); 4574 4575 /* now use this mask to enable the interrupt. */ 4576 ddi_put32(si_ctlp->sictl_global_acc_handle, 4577 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4578 mask); 4579 } 4580 4581 /* 4582 * Enable interrupts for all the ports. 4583 */ 4584 static void 4585 si_enable_all_interrupts(si_ctl_state_t *si_ctlp) 4586 { 4587 int port; 4588 4589 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4590 si_enable_port_interrupts(si_ctlp, port); 4591 } 4592 } 4593 4594 /* 4595 * Disable interrupts for a particular port. 4596 * 4597 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4598 * before calling us. 4599 */ 4600 static void 4601 si_disable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4602 { 4603 uint32_t mask; 4604 4605 /* get the current settings first. */ 4606 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4607 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4608 4609 /* clear the bit for current port. */ 4610 CLEAR_BIT(mask, port); 4611 4612 /* now use this mask to disable the interrupt. */ 4613 ddi_put32(si_ctlp->sictl_global_acc_handle, 4614 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4615 mask); 4616 4617 } 4618 4619 /* 4620 * Disable interrupts for all the ports. 4621 */ 4622 static void 4623 si_disable_all_interrupts(si_ctl_state_t *si_ctlp) 4624 { 4625 int port; 4626 4627 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4628 si_disable_port_interrupts(si_ctlp, port); 4629 } 4630 } 4631 4632 /* 4633 * Fetches the latest sstatus, scontrol, serror, sactive registers 4634 * and stuffs them into sata_device_t structure. 4635 */ 4636 static void 4637 fill_dev_sregisters(si_ctl_state_t *si_ctlp, int port, sata_device_t *satadev) 4638 { 4639 satadev->satadev_scr.sstatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4640 (uint32_t *)(PORT_SSTATUS(si_ctlp, port))); 4641 satadev->satadev_scr.serror = ddi_get32(si_ctlp->sictl_port_acc_handle, 4642 (uint32_t *)(PORT_SERROR(si_ctlp, port))); 4643 satadev->satadev_scr.sactive = ddi_get32(si_ctlp->sictl_port_acc_handle, 4644 (uint32_t *)(PORT_SACTIVE(si_ctlp, port))); 4645 satadev->satadev_scr.scontrol = 4646 ddi_get32(si_ctlp->sictl_port_acc_handle, 4647 (uint32_t *)(PORT_SCONTROL(si_ctlp, port))); 4648 4649 } 4650 4651 /* 4652 * si_add_legacy_intrs() handles INTx and legacy interrupts. 4653 */ 4654 static int 4655 si_add_legacy_intrs(si_ctl_state_t *si_ctlp) 4656 { 4657 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4658 int actual, count = 0; 4659 int x, y, rc, inum = 0; 4660 4661 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_add_legacy_intrs"); 4662 4663 /* get number of interrupts. */ 4664 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &count); 4665 if ((rc != DDI_SUCCESS) || (count == 0)) { 4666 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4667 "ddi_intr_get_nintrs() failed, " 4668 "rc %d count %d\n", rc, count); 4669 return (DDI_FAILURE); 4670 } 4671 4672 /* Allocate an array of interrupt handles. */ 4673 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4674 si_ctlp->sictl_htable = kmem_zalloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4675 4676 /* call ddi_intr_alloc(). */ 4677 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_FIXED, 4678 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 4679 4680 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4681 SIDBG1(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4682 "ddi_intr_alloc() failed, rc %d\n", rc); 4683 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4684 return (DDI_FAILURE); 4685 } 4686 4687 if (actual < count) { 4688 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4689 "Requested: %d, Received: %d", count, actual); 4690 4691 for (x = 0; x < actual; x++) { 4692 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4693 } 4694 4695 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4696 return (DDI_FAILURE); 4697 } 4698 4699 si_ctlp->sictl_intr_cnt = actual; 4700 4701 /* Get intr priority. */ 4702 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4703 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4704 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4705 "ddi_intr_get_pri() failed"); 4706 4707 for (x = 0; x < actual; x++) { 4708 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4709 } 4710 4711 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4712 return (DDI_FAILURE); 4713 } 4714 4715 /* Test for high level mutex. */ 4716 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4717 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4718 "si_add_legacy_intrs: Hi level intr not supported"); 4719 4720 for (x = 0; x < actual; x++) { 4721 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4722 } 4723 4724 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4725 4726 return (DDI_FAILURE); 4727 } 4728 4729 /* Call ddi_intr_add_handler(). */ 4730 for (x = 0; x < actual; x++) { 4731 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4732 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4733 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4734 "ddi_intr_add_handler() failed"); 4735 4736 for (y = 0; y < actual; y++) { 4737 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4738 } 4739 4740 kmem_free(si_ctlp->sictl_htable, 4741 si_ctlp->sictl_intr_size); 4742 return (DDI_FAILURE); 4743 } 4744 } 4745 4746 /* Call ddi_intr_enable() for legacy interrupts. */ 4747 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4748 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4749 } 4750 4751 return (DDI_SUCCESS); 4752 } 4753 4754 /* 4755 * si_add_msictl_intrs() handles MSI interrupts. 4756 */ 4757 static int 4758 si_add_msi_intrs(si_ctl_state_t *si_ctlp) 4759 { 4760 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4761 int count, avail, actual; 4762 int x, y, rc, inum = 0; 4763 4764 SIDBG0(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, "si_add_msi_intrs"); 4765 4766 /* get number of interrupts. */ 4767 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSI, &count); 4768 if ((rc != DDI_SUCCESS) || (count == 0)) { 4769 SIDBG2(SIDBG_INIT, si_ctlp, 4770 "ddi_intr_get_nintrs() failed, " 4771 "rc %d count %d\n", rc, count); 4772 return (DDI_FAILURE); 4773 } 4774 4775 /* get number of available interrupts. */ 4776 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSI, &avail); 4777 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4778 SIDBG2(SIDBG_INIT, si_ctlp, 4779 "ddi_intr_get_navail() failed, " 4780 "rc %d avail %d\n", rc, avail); 4781 return (DDI_FAILURE); 4782 } 4783 4784 if (avail < count) { 4785 SIDBG2(SIDBG_INIT, si_ctlp, 4786 "ddi_intr_get_nvail returned %d, navail() returned %d", 4787 count, avail); 4788 } 4789 4790 /* Allocate an array of interrupt handles. */ 4791 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4792 si_ctlp->sictl_htable = kmem_alloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4793 4794 /* call ddi_intr_alloc(). */ 4795 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_MSI, 4796 inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 4797 4798 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4799 SIDBG1(SIDBG_INIT, si_ctlp, 4800 "ddi_intr_alloc() failed, rc %d\n", rc); 4801 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4802 return (DDI_FAILURE); 4803 } 4804 4805 /* use interrupt count returned */ 4806 if (actual < count) { 4807 SIDBG2(SIDBG_INIT, si_ctlp, 4808 "Requested: %d, Received: %d", count, actual); 4809 } 4810 4811 si_ctlp->sictl_intr_cnt = actual; 4812 4813 /* 4814 * Get priority for first msi, assume remaining are all the same. 4815 */ 4816 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4817 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4818 SIDBG0(SIDBG_INIT, si_ctlp, "ddi_intr_get_pri() failed"); 4819 4820 /* Free already allocated intr. */ 4821 for (y = 0; y < actual; y++) { 4822 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4823 } 4824 4825 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4826 return (DDI_FAILURE); 4827 } 4828 4829 /* Test for high level mutex. */ 4830 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4831 SIDBG0(SIDBG_INIT, si_ctlp, 4832 "si_add_msi_intrs: Hi level intr not supported"); 4833 4834 /* Free already allocated intr. */ 4835 for (y = 0; y < actual; y++) { 4836 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4837 } 4838 4839 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4840 4841 return (DDI_FAILURE); 4842 } 4843 4844 /* Call ddi_intr_add_handler(). */ 4845 for (x = 0; x < actual; x++) { 4846 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4847 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4848 SIDBG0(SIDBG_INIT, si_ctlp, 4849 "ddi_intr_add_handler() failed"); 4850 4851 /* Free already allocated intr. */ 4852 for (y = 0; y < actual; y++) { 4853 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4854 } 4855 4856 kmem_free(si_ctlp->sictl_htable, 4857 si_ctlp->sictl_intr_size); 4858 return (DDI_FAILURE); 4859 } 4860 } 4861 4862 (void) ddi_intr_get_cap(si_ctlp->sictl_htable[0], 4863 &si_ctlp->sictl_intr_cap); 4864 4865 if (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 4866 /* Call ddi_intr_block_enable() for MSI. */ 4867 (void) ddi_intr_block_enable(si_ctlp->sictl_htable, 4868 si_ctlp->sictl_intr_cnt); 4869 } else { 4870 /* Call ddi_intr_enable() for MSI non block enable. */ 4871 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4872 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4873 } 4874 } 4875 4876 return (DDI_SUCCESS); 4877 } 4878 4879 /* 4880 * Removes the registered interrupts irrespective of whether they 4881 * were legacy or MSI. 4882 */ 4883 static void 4884 si_rem_intrs(si_ctl_state_t *si_ctlp) 4885 { 4886 int x; 4887 4888 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_rem_intrs entered"); 4889 4890 /* Disable all interrupts. */ 4891 if ((si_ctlp->sictl_intr_type == DDI_INTR_TYPE_MSI) && 4892 (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 4893 /* Call ddi_intr_block_disable(). */ 4894 (void) ddi_intr_block_disable(si_ctlp->sictl_htable, 4895 si_ctlp->sictl_intr_cnt); 4896 } else { 4897 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4898 (void) ddi_intr_disable(si_ctlp->sictl_htable[x]); 4899 } 4900 } 4901 4902 /* Call ddi_intr_remove_handler(). */ 4903 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4904 (void) ddi_intr_remove_handler(si_ctlp->sictl_htable[x]); 4905 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4906 } 4907 4908 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4909 } 4910 4911 /* 4912 * Resets either the port or the device connected to the port based on 4913 * the flag variable. 4914 * 4915 * The reset effectively throws away all the pending commands. So, the caller 4916 * has to make provision to handle the pending commands. 4917 * 4918 * After the reset, we wait till the port is ready again. 4919 * 4920 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4921 * before calling us. 4922 * 4923 * Note: Not port-mult aware. 4924 */ 4925 static int 4926 si_reset_dport_wait_till_ready( 4927 si_ctl_state_t *si_ctlp, 4928 si_port_state_t *si_portp, 4929 int port, 4930 int flag) 4931 { 4932 uint32_t port_status; 4933 int loop_count = 0; 4934 sata_device_t sdevice; 4935 uint32_t SStatus; 4936 uint32_t SControl; 4937 4938 _NOTE(ASSUMING_PROTECTED(si_portp)) 4939 4940 if (flag == SI_PORT_RESET) { 4941 ddi_put32(si_ctlp->sictl_port_acc_handle, 4942 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4943 PORT_CONTROL_SET_BITS_PORT_RESET); 4944 4945 /* Port reset is not self clearing. So clear it now. */ 4946 ddi_put32(si_ctlp->sictl_port_acc_handle, 4947 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 4948 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 4949 } else { 4950 /* Reset the device. */ 4951 ddi_put32(si_ctlp->sictl_port_acc_handle, 4952 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4953 PORT_CONTROL_SET_BITS_DEV_RESET); 4954 4955 /* 4956 * tidbit: this bit is self clearing; so there is no need 4957 * for manual clear as we did for port reset. 4958 */ 4959 } 4960 4961 /* Set the reset in progress flag */ 4962 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 4963 si_portp->siport_reset_in_progress = 1; 4964 } 4965 4966 /* 4967 * For some reason, we are losing the interrupt enablement after 4968 * any reset condition. So restore them back now. 4969 */ 4970 SIDBG1(SIDBG_INIT, si_ctlp, 4971 "current interrupt enable set: 0x%x", 4972 ddi_get32(si_ctlp->sictl_port_acc_handle, 4973 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port))); 4974 4975 ddi_put32(si_ctlp->sictl_port_acc_handle, 4976 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 4977 (INTR_COMMAND_COMPLETE | 4978 INTR_COMMAND_ERROR | 4979 INTR_PORT_READY | 4980 INTR_POWER_CHANGE | 4981 INTR_PHYRDY_CHANGE | 4982 INTR_COMWAKE_RECEIVED | 4983 INTR_UNRECOG_FIS | 4984 INTR_DEV_XCHANGED | 4985 INTR_SETDEVBITS_NOTIFY)); 4986 4987 si_enable_port_interrupts(si_ctlp, port); 4988 4989 /* 4990 * Every reset needs a PHY initialization. 4991 * 4992 * The way to initialize the PHY is to write a 1 and then 4993 * a 0 to DET field of SControl register. 4994 */ 4995 4996 /* Fetch the current SControl before writing the DET part with 1. */ 4997 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 4998 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 4999 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 5000 ddi_put32(si_ctlp->sictl_port_acc_handle, 5001 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 5002 SControl); 5003 #ifndef __lock_lint 5004 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 5005 #endif /* __lock_lint */ 5006 5007 /* Now fetch the SControl again and rewrite the DET part with 0 */ 5008 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 5009 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 5010 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 5011 ddi_put32(si_ctlp->sictl_port_acc_handle, 5012 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 5013 SControl); 5014 5015 /* 5016 * PHY may be initialized by now. Check the DET field of SStatus 5017 * to determine if there is a device present. 5018 * 5019 * The DET field is valid only if IPM field indicates that 5020 * the interface is in active state. 5021 */ 5022 5023 loop_count = 0; 5024 do { 5025 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 5026 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 5027 5028 if (SSTATUS_GET_IPM(SStatus) != 5029 SSTATUS_IPM_INTERFACE_ACTIVE) { 5030 /* 5031 * If the interface is not active, the DET field 5032 * is considered not accurate. So we want to 5033 * continue looping. 5034 */ 5035 SSTATUS_SET_DET(SStatus, SSTATUS_DET_NODEV_NOPHY); 5036 } 5037 5038 if (loop_count++ > SI_POLLRATE_SSTATUS) { 5039 /* We are effectively timing out after 0.1 sec. */ 5040 break; 5041 } 5042 5043 /* Wait for 10 millisec */ 5044 #ifndef __lock_lint 5045 delay(SI_10MS_TICKS); 5046 #endif /* __lock_lint */ 5047 5048 } while (SSTATUS_GET_DET(SStatus) != SSTATUS_DET_DEVPRESENT_PHYONLINE); 5049 5050 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 5051 "si_reset_dport_wait_till_ready: loop count: %d, \ 5052 SStatus: 0x%x", 5053 loop_count, 5054 SStatus); 5055 5056 /* Now check for port readiness. */ 5057 loop_count = 0; 5058 do { 5059 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5060 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5061 5062 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5063 /* We are effectively timing out after 0.5 sec. */ 5064 break; 5065 } 5066 5067 /* Wait for 10 millisec */ 5068 #ifndef __lock_lint 5069 delay(SI_10MS_TICKS); 5070 #endif /* __lock_lint */ 5071 5072 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5073 5074 SIDBG3(SIDBG_POLL_LOOP, si_ctlp, 5075 "si_reset_dport_wait_till_ready: loop count: %d, \ 5076 port_status: 0x%x, SStatus: 0x%x", 5077 loop_count, 5078 port_status, 5079 SStatus); 5080 5081 /* Indicate to the framework that a reset has happened. */ 5082 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 5083 5084 bzero((void *)&sdevice, sizeof (sata_device_t)); 5085 sdevice.satadev_addr.cport = port; 5086 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 5087 5088 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 5089 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT; 5090 } else { 5091 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5092 } 5093 sdevice.satadev_state = SATA_DSTATE_RESET | 5094 SATA_DSTATE_PWR_ACTIVE; 5095 if (si_ctlp->sictl_sata_hba_tran) { 5096 sata_hba_event_notify( 5097 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 5098 &sdevice, 5099 SATA_EVNT_DEVICE_RESET); 5100 } 5101 5102 SIDBG0(SIDBG_EVENT, si_ctlp, 5103 "sending event up: SATA_EVNT_RESET"); 5104 } 5105 5106 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5107 (SSTATUS_GET_DET(SStatus) == 5108 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5109 /* The interface is active and the device is present */ 5110 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5111 /* But the port is is not ready for some reason */ 5112 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5113 "si_reset_dport_wait_till_ready failed"); 5114 return (SI_FAILURE); 5115 } 5116 } 5117 5118 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5119 "si_reset_dport_wait_till_ready returning success"); 5120 5121 return (SI_SUCCESS); 5122 } 5123 5124 /* 5125 * Initializes the port. 5126 * 5127 * Initialization effectively throws away all the pending commands on 5128 * the port. So, the caller has to make provision to handle the pending 5129 * commands. 5130 * 5131 * After the port initialization, we wait till the port is ready again. 5132 * 5133 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 5134 * before calling us. 5135 */ 5136 static int 5137 si_initialize_port_wait_till_ready(si_ctl_state_t *si_ctlp, int port) 5138 { 5139 uint32_t port_status; 5140 int loop_count = 0; 5141 uint32_t SStatus; 5142 5143 /* Initialize the port. */ 5144 ddi_put32(si_ctlp->sictl_port_acc_handle, 5145 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 5146 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 5147 5148 /* Wait until Port Ready */ 5149 loop_count = 0; 5150 do { 5151 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5152 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5153 5154 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5155 SIDBG1(SIDBG_INTR, si_ctlp, 5156 "si_initialize_port_wait is timing out: " 5157 "port_status: %x", 5158 port_status); 5159 /* We are effectively timing out after 0.5 sec. */ 5160 break; 5161 } 5162 5163 /* Wait for 10 millisec */ 5164 #ifndef __lock_lint 5165 delay(SI_10MS_TICKS); 5166 #endif /* __lock_lint */ 5167 5168 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5169 5170 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 5171 "si_initialize_port_wait_till_ready: loop count: %d", 5172 loop_count); 5173 5174 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 5175 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 5176 5177 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5178 (SSTATUS_GET_DET(SStatus) == 5179 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5180 /* The interface is active and the device is present */ 5181 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5182 /* But the port is is not ready for some reason */ 5183 return (SI_FAILURE); 5184 } 5185 } 5186 5187 return (SI_SUCCESS); 5188 } 5189 5190 5191 /* 5192 * si_watchdog_handler() calls us if it detects that there are some 5193 * commands which timed out. We recalculate the timed out commands once 5194 * again since some of them may have finished recently. 5195 */ 5196 static void 5197 si_timeout_pkts( 5198 si_ctl_state_t *si_ctlp, 5199 si_port_state_t *si_portp, 5200 int port, 5201 uint32_t timedout_tags) 5202 { 5203 uint32_t slot_status; 5204 uint32_t finished_tags; 5205 5206 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, "si_timeout_pkts entry"); 5207 5208 mutex_enter(&si_portp->siport_mutex); 5209 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5210 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 5211 5212 /* 5213 * Initialize the controller. The only way to timeout the commands 5214 * is to reset or initialize the controller. We mop commands after 5215 * the initialization. 5216 */ 5217 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 5218 5219 /* 5220 * Recompute the timedout tags since some of them may have finished 5221 * meanwhile. 5222 */ 5223 finished_tags = si_portp->siport_pending_tags & 5224 ~slot_status & SI_SLOT_MASK; 5225 timedout_tags &= ~finished_tags; 5226 5227 SIDBG2(SIDBG_TIMEOUT, si_ctlp, 5228 "si_timeout_pkts: finished: %x, timeout: %x", 5229 finished_tags, 5230 timedout_tags); 5231 5232 mutex_exit(&si_portp->siport_mutex); 5233 si_mop_commands(si_ctlp, 5234 si_portp, 5235 port, 5236 slot_status, 5237 0, /* failed_tags */ 5238 timedout_tags, 5239 0, /* aborting_tags */ 5240 0); /* reset_tags */ 5241 5242 } 5243 5244 5245 5246 /* 5247 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 5248 * for long time. 5249 */ 5250 static void 5251 si_watchdog_handler(si_ctl_state_t *si_ctlp) 5252 { 5253 uint32_t pending_tags = 0; 5254 uint32_t timedout_tags = 0; 5255 si_port_state_t *si_portp; 5256 int port; 5257 int tmpslot; 5258 sata_pkt_t *satapkt; 5259 5260 /* max number of cycles this packet should survive */ 5261 int max_life_cycles; 5262 5263 /* how many cycles this packet survived so far */ 5264 int watched_cycles; 5265 5266 mutex_enter(&si_ctlp->sictl_mutex); 5267 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, 5268 "si_watchdog_handler entered"); 5269 5270 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 5271 5272 si_portp = si_ctlp->sictl_ports[port]; 5273 if (si_portp == NULL) { 5274 continue; 5275 } 5276 5277 mutex_enter(&si_portp->siport_mutex); 5278 5279 if (si_portp->siport_port_type == PORT_TYPE_NODEV) { 5280 mutex_exit(&si_portp->siport_mutex); 5281 continue; 5282 } 5283 5284 pending_tags = si_portp->siport_pending_tags; 5285 timedout_tags = 0; 5286 while (pending_tags) { 5287 tmpslot = ddi_ffs(pending_tags) - 1; 5288 if (tmpslot == -1) { 5289 break; 5290 } 5291 satapkt = si_portp->siport_slot_pkts[tmpslot]; 5292 5293 if ((satapkt != NULL) && satapkt->satapkt_time) { 5294 5295 /* 5296 * We are overloading satapkt_hba_driver_private 5297 * with watched_cycle count. 5298 * 5299 * If a packet has survived for more than it's 5300 * max life cycles, it is a candidate for time 5301 * out. 5302 */ 5303 watched_cycles = (int)(intptr_t) 5304 satapkt->satapkt_hba_driver_private; 5305 watched_cycles++; 5306 max_life_cycles = (satapkt->satapkt_time + 5307 si_watchdog_timeout - 1) / 5308 si_watchdog_timeout; 5309 if (watched_cycles > max_life_cycles) { 5310 timedout_tags |= (0x1 << tmpslot); 5311 SIDBG1(SIDBG_TIMEOUT|SIDBG_VERBOSE, 5312 si_ctlp, 5313 "watchdog: timedout_tags: 0x%x", 5314 timedout_tags); 5315 } 5316 satapkt->satapkt_hba_driver_private = 5317 (void *)(intptr_t)watched_cycles; 5318 } 5319 5320 CLEAR_BIT(pending_tags, tmpslot); 5321 } 5322 5323 if (timedout_tags) { 5324 mutex_exit(&si_portp->siport_mutex); 5325 mutex_exit(&si_ctlp->sictl_mutex); 5326 si_timeout_pkts(si_ctlp, si_portp, port, timedout_tags); 5327 mutex_enter(&si_ctlp->sictl_mutex); 5328 mutex_enter(&si_portp->siport_mutex); 5329 } 5330 5331 mutex_exit(&si_portp->siport_mutex); 5332 } 5333 5334 /* Reinstall the watchdog timeout handler. */ 5335 if (!(si_ctlp->sictl_flags & SI_NO_TIMEOUTS)) { 5336 si_ctlp->sictl_timeout_id = 5337 timeout((void (*)(void *))si_watchdog_handler, 5338 (caddr_t)si_ctlp, si_watchdog_tick); 5339 } 5340 mutex_exit(&si_ctlp->sictl_mutex); 5341 } 5342 5343 5344 /* 5345 * Logs the message. 5346 */ 5347 static void 5348 si_log(si_ctl_state_t *si_ctlp, uint_t level, char *fmt, ...) 5349 { 5350 va_list ap; 5351 5352 mutex_enter(&si_log_mutex); 5353 5354 va_start(ap, fmt); 5355 if (si_ctlp) { 5356 (void) sprintf(si_log_buf, "%s-[%d]:", 5357 ddi_get_name(si_ctlp->sictl_devinfop), 5358 ddi_get_instance(si_ctlp->sictl_devinfop)); 5359 } else { 5360 (void) sprintf(si_log_buf, "si3124:"); 5361 } 5362 (void) vsprintf(si_log_buf, fmt, ap); 5363 va_end(ap); 5364 5365 cmn_err(level, "%s", si_log_buf); 5366 5367 mutex_exit(&si_log_mutex); 5368 5369 } 5370 5371 static void 5372 si_copy_out_regs(sata_cmd_t *scmd, fis_reg_h2d_t *fisp) 5373 { 5374 fis_reg_h2d_t fis = *fisp; 5375 5376 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 5377 scmd->satacmd_sec_count_msb = GET_FIS_SECTOR_COUNT_EXP(fis); 5378 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 5379 scmd->satacmd_lba_low_msb = GET_FIS_SECTOR_EXP(fis); 5380 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 5381 scmd->satacmd_lba_mid_msb = GET_FIS_CYL_LOW_EXP(fis); 5382 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 5383 scmd->satacmd_lba_high_msb = GET_FIS_CYL_HI_EXP(fis); 5384 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 5385 scmd->satacmd_sec_count_lsb = GET_FIS_SECTOR_COUNT(fis); 5386 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 5387 scmd->satacmd_lba_low_lsb = GET_FIS_SECTOR(fis); 5388 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 5389 scmd->satacmd_lba_mid_lsb = GET_FIS_CYL_LOW(fis); 5390 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 5391 scmd->satacmd_lba_high_lsb = GET_FIS_CYL_HI(fis); 5392 if (scmd->satacmd_flags.sata_copy_out_device_reg) 5393 scmd->satacmd_device_reg = GET_FIS_DEV_HEAD(fis); 5394 if (scmd->satacmd_flags.sata_copy_out_error_reg) 5395 scmd->satacmd_error_reg = GET_FIS_FEATURES(fis); 5396 } 5397