1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 31 */ 32 33 #include <sys/scsi/scsi.h> 34 #include <sys/pci.h> 35 #include <sys/sata/sata_hba.h> 36 #include <sys/sata/adapters/ahci/ahcireg.h> 37 #include <sys/sata/adapters/ahci/ahcivar.h> 38 39 /* 40 * Function prototypes for driver entry points 41 */ 42 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 43 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 44 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 45 46 /* 47 * Function prototypes for SATA Framework interfaces 48 */ 49 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 50 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 51 52 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 53 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 54 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 55 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 56 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 57 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 58 #if defined(__lock_lint) 59 static int ahci_selftest(dev_info_t *, sata_device_t *); 60 #endif 61 62 /* 63 * Local function prototypes 64 */ 65 static int ahci_initialize_controller(ahci_ctl_t *); 66 static void ahci_deallocate_controller(ahci_ctl_t *); 67 68 69 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 70 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 71 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 72 static void ahci_dealloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *); 73 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 74 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 75 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 76 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 77 78 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 79 static int ahci_start_port(ahci_ctl_t *, uint8_t); 80 static int ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 81 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 82 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 83 uint8_t, sata_pkt_t *); 84 static void ahci_poll_cmd(ahci_ctl_t *, ahci_port_t *, uint8_t, 85 int, sata_pkt_t *); 86 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *); 87 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 88 static void ahci_set_sense_data(sata_pkt_t *, int); 89 90 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 91 static int ahci_hba_reset(ahci_ctl_t *); 92 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 93 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 94 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 95 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 96 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 97 static int ahci_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 98 uint8_t); 99 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 100 uint8_t, int); 101 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint8_t, 102 uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); 103 static int ahci_recovery_fatal_error(ahci_ctl_t *, 104 ahci_port_t *, uint8_t, uint32_t); 105 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t, uint32_t); 106 static void ahci_watchdog_handler(ahci_ctl_t *); 107 108 static uint_t ahci_intr(caddr_t, caddr_t); 109 static int ahci_add_legacy_intrs(ahci_ctl_t *); 110 static int ahci_add_msi_intrs(ahci_ctl_t *); 111 static void ahci_rem_intrs(ahci_ctl_t *); 112 static void ahci_enable_all_intrs(ahci_ctl_t *); 113 static void ahci_disable_all_intrs(ahci_ctl_t *); 114 static void ahci_enable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 115 static void ahci_disable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 116 117 static int ahci_intr_d2h_register_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 118 static int ahci_intr_pio_setup_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 119 static int ahci_intr_dma_setup_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 120 static int ahci_intr_set_device_bits_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 121 static int ahci_intr_unknown_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 122 static int ahci_intr_descriptor_processed(ahci_ctl_t *, ahci_port_t *, 123 uint8_t); 124 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 125 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 126 ahci_port_t *, uint8_t); 127 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 128 static int ahci_intr_incorrect_port_multiplier(ahci_ctl_t *, 129 ahci_port_t *, uint8_t); 130 static int ahci_intr_overflow(ahci_ctl_t *, ahci_port_t *, uint8_t); 131 static int ahci_intr_interface_non_fatal_error(ahci_ctl_t *, 132 ahci_port_t *, uint8_t); 133 static int ahci_intr_interface_fatal_error(ahci_ctl_t *, ahci_port_t *, 134 uint8_t); 135 static int ahci_intr_host_bus_data_error(ahci_ctl_t *, ahci_port_t *, uint8_t); 136 static int ahci_intr_host_bus_fatal_error(ahci_ctl_t *, ahci_port_t *, 137 uint8_t); 138 static int ahci_intr_task_file_error(ahci_ctl_t *, ahci_port_t *, uint8_t); 139 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 140 141 static int ahci_get_num_implemented_ports(uint32_t); 142 static void ahci_log_error_message(ahci_ctl_t *, uint8_t, uint32_t); 143 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 144 145 146 /* 147 * DMA attributes for the data buffer 148 * 149 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 150 * does not support 64-bit addressing 151 */ 152 static ddi_dma_attr_t buffer_dma_attr = { 153 DMA_ATTR_V0, /* dma_attr_version */ 154 0, /* dma_attr_addr_lo: lowest bus address */ 155 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 156 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 157 2, /* dma_attr_align: word aligned */ 158 1, /* dma_attr_burstsizes */ 159 1, /* dma_attr_minxfer */ 160 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 161 0xffffffffull, /* dma_attr_seg */ 162 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 163 512, /* dma_attr_granular */ 164 0, /* dma_attr_flags */ 165 }; 166 167 /* 168 * DMA attributes for the rcvd FIS 169 * 170 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 171 * does not support 64-bit addressing 172 */ 173 static ddi_dma_attr_t rcvd_fis_dma_attr = { 174 DMA_ATTR_V0, /* dma_attr_version */ 175 0, /* dma_attr_addr_lo: lowest bus address */ 176 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 177 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 178 0x100, /* dma_attr_align: 256-byte aligned */ 179 1, /* dma_attr_burstsizes */ 180 1, /* dma_attr_minxfer */ 181 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 182 0xffffffffull, /* dma_attr_seg */ 183 1, /* dma_attr_sgllen */ 184 1, /* dma_attr_granular */ 185 0, /* dma_attr_flags */ 186 }; 187 188 /* 189 * DMA attributes for the command list 190 * 191 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 192 * does not support 64-bit addressing 193 */ 194 static ddi_dma_attr_t cmd_list_dma_attr = { 195 DMA_ATTR_V0, /* dma_attr_version */ 196 0, /* dma_attr_addr_lo: lowest bus address */ 197 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 198 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 199 0x400, /* dma_attr_align: 1K-byte aligned */ 200 1, /* dma_attr_burstsizes */ 201 1, /* dma_attr_minxfer */ 202 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 203 0xffffffffull, /* dma_attr_seg */ 204 1, /* dma_attr_sgllen */ 205 1, /* dma_attr_granular */ 206 0, /* dma_attr_flags */ 207 }; 208 209 /* 210 * DMA attributes for cmd tables 211 * 212 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 213 * does not support 64-bit addressing 214 */ 215 static ddi_dma_attr_t cmd_table_dma_attr = { 216 DMA_ATTR_V0, /* dma_attr_version */ 217 0, /* dma_attr_addr_lo: lowest bus address */ 218 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 219 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 220 0x80, /* dma_attr_align: 128-byte aligned */ 221 1, /* dma_attr_burstsizes */ 222 1, /* dma_attr_minxfer */ 223 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 224 0xffffffffull, /* dma_attr_seg */ 225 1, /* dma_attr_sgllen */ 226 1, /* dma_attr_granular */ 227 0, /* dma_attr_flags */ 228 }; 229 230 231 /* Device access attributes */ 232 static ddi_device_acc_attr_t accattr = { 233 DDI_DEVICE_ATTR_V0, 234 DDI_STRUCTURE_LE_ACC, 235 DDI_STRICTORDER_ACC 236 }; 237 238 239 static struct dev_ops ahcictl_dev_ops = { 240 DEVO_REV, /* devo_rev */ 241 0, /* refcnt */ 242 ahci_getinfo, /* info */ 243 nulldev, /* identify */ 244 nulldev, /* probe */ 245 ahci_attach, /* attach */ 246 ahci_detach, /* detach */ 247 nodev, /* no reset */ 248 (struct cb_ops *)0, /* driver operations */ 249 NULL, /* bus operations */ 250 NULL /* power */ 251 }; 252 253 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 254 SATA_TRAN_HOTPLUG_OPS_REV_1, 255 ahci_tran_hotplug_port_activate, 256 ahci_tran_hotplug_port_deactivate 257 }; 258 259 extern struct mod_ops mod_driverops; 260 261 static struct modldrv modldrv = { 262 &mod_driverops, /* driverops */ 263 "ahci driver %I%", 264 &ahcictl_dev_ops, /* driver ops */ 265 }; 266 267 static struct modlinkage modlinkage = { 268 MODREV_1, 269 &modldrv, 270 NULL 271 }; 272 273 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 274 static int ahci_watchdog_tick; 275 276 /* The following is needed for ahci_log() */ 277 static kmutex_t ahci_log_mutex; 278 static char ahci_log_buf[512]; 279 280 static size_t ahci_cmd_table_size; 281 282 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 283 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 284 285 /* 286 * AHCI MSI tunable: 287 * 288 * MSI will be enabled in phase 2. 289 */ 290 boolean_t ahci_msi_enabled = B_FALSE; 291 292 #if AHCI_DEBUG 293 uint32_t ahci_debug_flags = 0; 294 #endif 295 296 /* Opaque state pointer initialized by ddi_soft_state_init() */ 297 static void *ahci_statep = NULL; 298 299 /* 300 * ahci module initialization. 301 */ 302 int 303 _init(void) 304 { 305 int ret; 306 307 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 308 if (ret != 0) { 309 goto err_out; 310 } 311 312 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 313 314 if ((ret = sata_hba_init(&modlinkage)) != 0) { 315 mutex_destroy(&ahci_log_mutex); 316 ddi_soft_state_fini(&ahci_statep); 317 goto err_out; 318 } 319 320 ret = mod_install(&modlinkage); 321 if (ret != 0) { 322 sata_hba_fini(&modlinkage); 323 mutex_destroy(&ahci_log_mutex); 324 ddi_soft_state_fini(&ahci_statep); 325 goto err_out; 326 } 327 328 /* watchdog tick */ 329 ahci_watchdog_tick = drv_usectohz( 330 (clock_t)ahci_watchdog_timeout * 1000000); 331 return (ret); 332 333 err_out: 334 cmn_err(CE_WARN, "!Module init failed"); 335 return (ret); 336 } 337 338 /* 339 * ahci module uninitialize. 340 */ 341 int 342 _fini(void) 343 { 344 int ret; 345 346 ret = mod_remove(&modlinkage); 347 if (ret != 0) { 348 return (ret); 349 } 350 351 /* Remove the resources allocated in _init(). */ 352 sata_hba_fini(&modlinkage); 353 mutex_destroy(&ahci_log_mutex); 354 ddi_soft_state_fini(&ahci_statep); 355 356 return (ret); 357 } 358 359 /* 360 * _info entry point 361 */ 362 int 363 _info(struct modinfo *modinfop) 364 { 365 return (mod_info(&modlinkage, modinfop)); 366 } 367 368 /* 369 * The attach entry point for dev_ops. 370 */ 371 static int 372 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 373 { 374 ahci_ctl_t *ahci_ctlp; 375 int instance = ddi_get_instance(dip); 376 int status; 377 int attach_state; 378 uint32_t cap_status, ahci_version; 379 int intr_types; 380 ushort_t venid; 381 uint8_t revision; 382 383 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 384 385 switch (cmd) { 386 case DDI_ATTACH: 387 break; 388 389 case DDI_RESUME: 390 /* It will be implemented in Phase 2 */ 391 return (DDI_FAILURE); 392 393 default: 394 return (DDI_FAILURE); 395 } 396 397 instance = ddi_get_instance(dip); 398 attach_state = AHCI_ATTACH_STATE_NONE; 399 400 /* Allocate soft state */ 401 status = ddi_soft_state_zalloc(ahci_statep, instance); 402 if (status != DDI_SUCCESS) { 403 goto err_out; 404 } 405 406 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 407 ahci_ctlp->ahcictl_dip = dip; 408 409 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 410 411 /* 412 * Now map the AHCI base address; which includes global 413 * registers and port control registers 414 */ 415 status = ddi_regs_map_setup(dip, 416 AHCI_BASE_REG, 417 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 418 0, 419 0, 420 &accattr, 421 &ahci_ctlp->ahcictl_ahci_acc_handle); 422 if (status != DDI_SUCCESS) { 423 goto err_out; 424 } 425 426 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 427 428 /* Get the AHCI version information */ 429 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 430 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 431 432 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, "hba AHCI version = %x.%x", 433 (ahci_version & 0xffff0000) >> 16, 434 ((ahci_version & 0x0000ff00) >> 4 | 435 (ahci_version & 0x000000ff))); 436 437 /* We don't support controllers whose versions are lower than 1.0 */ 438 if (!(ahci_version & 0xffff0000)) { 439 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, "No support for lower than " 440 "AHCI version 1.0"); 441 goto err_out; 442 } 443 444 /* Get the HBA capabilities information */ 445 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 446 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 447 448 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 449 cap_status); 450 451 /* Get the number of command slots supported by the HBA */ 452 ahci_ctlp->ahcictl_num_cmd_slots = 453 ((cap_status & AHCI_HBA_CAP_NCS) >> 454 AHCI_HBA_CAP_NCS_SHIFT) + 1; 455 456 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: 0x%x", 457 ahci_ctlp->ahcictl_num_cmd_slots); 458 459 /* Get the bit map which indicates ports implemented by the HBA */ 460 ahci_ctlp->ahcictl_ports_implemented = 461 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 462 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 463 464 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 465 ahci_ctlp->ahcictl_ports_implemented); 466 467 /* 468 * According to the AHCI spec, CAP.NP should indicate the maximum 469 * number of ports supported by the HBA silicon, but we found 470 * this value of ICH8 chipset only indicates the number of ports 471 * implemented (exposed) by it. Therefore, the driver should calculate 472 * the potential maximum value by checking PI register, and use 473 * the maximum of this value and CAP.NP. 474 */ 475 ahci_ctlp->ahcictl_num_ports = max( 476 (cap_status & AHCI_HBA_CAP_NP) + 1, 477 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 478 479 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 480 ahci_ctlp->ahcictl_num_ports); 481 482 /* Get the number of implemented ports by the HBA */ 483 ahci_ctlp->ahcictl_num_implemented_ports = 484 ahci_get_num_implemented_ports( 485 ahci_ctlp->ahcictl_ports_implemented); 486 487 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 488 "hba number of implemented ports: 0x%x", 489 ahci_ctlp->ahcictl_num_implemented_ports); 490 491 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 492 493 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 494 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 495 "hba does not support 64-bit addressing"); 496 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 497 0xffffffffull; 498 } 499 500 /* 501 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 502 * controllers with 0x00 revision id work on 4-byte aligned buffer, 503 * which is a bug and was fixed after 0x00 revision id controllers. 504 */ 505 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 506 != DDI_SUCCESS) { 507 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "pci_config_setup failed"); 508 goto err_out; 509 } 510 511 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 512 PCI_CONF_VENID); 513 514 if (venid == VIA_VENID) { 515 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 516 PCI_CONF_REVID); 517 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 518 "revision id = 0x%x", revision); 519 if (revision == 0x00) { 520 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 521 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 522 "change ddi_attr_align to 0x4"); 523 } 524 } 525 526 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 527 528 /* 529 * Disable the whole controller interrupts before adding 530 * interrupt handlers(s). 531 */ 532 ahci_disable_all_intrs(ahci_ctlp); 533 534 /* Get supported interrupt types */ 535 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 536 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 537 "ddi_intr_get_supported_types failed"); 538 goto err_out; 539 } 540 541 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 542 "ddi_intr_get_supported_types() returned: 0x%x", 543 intr_types); 544 545 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 546 /* 547 * Try MSI first, but fall back to FIXED if failed 548 */ 549 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 550 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 551 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 552 "Using MSI interrupt type"); 553 goto intr_done; 554 } 555 556 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 557 "MSI registration failed, " 558 "trying FIXED interrupts"); 559 } 560 561 if (intr_types & DDI_INTR_TYPE_FIXED) { 562 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 563 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 564 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, NULL, 565 "Using FIXED interrupt type"); 566 goto intr_done; 567 } 568 569 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 570 "FIXED interrupt registration failed"); 571 } 572 573 cmn_err(CE_WARN, "!Interrupt registration failed"); 574 575 goto err_out; 576 577 intr_done: 578 579 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 580 581 /* Initialize the controller mutex */ 582 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 583 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 584 585 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 586 587 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 588 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 589 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 590 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 591 } 592 593 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 594 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 595 sizeof (ahci_prdt_item_t)); 596 597 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 598 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 599 " ahci_cmd_table_size is 0x%x", 600 ahci_dma_prdt_number, ahci_cmd_table_size); 601 602 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 603 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 604 ahci_dma_prdt_number; 605 606 /* 607 * Initialize the controller and driver core. 608 */ 609 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 610 status = ahci_initialize_controller(ahci_ctlp); 611 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 612 if (status != AHCI_SUCCESS) { 613 goto err_out; 614 } 615 616 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 617 618 /* Start one thread to check packet timeouts */ 619 ahci_ctlp->ahcictl_timeout_id = timeout( 620 (void (*)(void *))ahci_watchdog_handler, 621 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 622 623 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 624 625 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 626 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 627 "ahci: setting sata hba tran failed"); 628 goto err_out; 629 } 630 631 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 632 633 return (DDI_SUCCESS); 634 635 err_out: 636 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 637 mutex_enter(&ahci_ctlp->ahcictl_mutex); 638 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 639 ahci_ctlp->ahcictl_timeout_id = 0; 640 mutex_exit(&ahci_ctlp->ahcictl_mutex); 641 } 642 643 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 644 mutex_enter(&ahci_ctlp->ahcictl_mutex); 645 ahci_ctlp->ahcictl_flags |= AHCI_DETACH; 646 ahci_deallocate_controller(ahci_ctlp); 647 ahci_ctlp->ahcictl_flags &= ~AHCI_DETACH; 648 mutex_exit(&ahci_ctlp->ahcictl_mutex); 649 } 650 651 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 652 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 653 } 654 655 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 656 ahci_rem_intrs(ahci_ctlp); 657 } 658 659 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 660 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 661 } 662 663 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 664 ddi_soft_state_free(ahci_statep, instance); 665 } 666 667 return (DDI_FAILURE); 668 } 669 670 /* 671 * The detach entry point for dev_ops. 672 */ 673 static int 674 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 675 { 676 ahci_ctl_t *ahci_ctlp; 677 int instance; 678 int ret; 679 680 instance = ddi_get_instance(dip); 681 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 682 683 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 684 685 switch (cmd) { 686 case DDI_DETACH: 687 /* disable the interrupts for an uninterrupted detach */ 688 mutex_enter(&ahci_ctlp->ahcictl_mutex); 689 ahci_disable_all_intrs(ahci_ctlp); 690 mutex_exit(&ahci_ctlp->ahcictl_mutex); 691 692 /* unregister from the sata framework. */ 693 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 694 if (ret != AHCI_SUCCESS) { 695 mutex_enter(&ahci_ctlp->ahcictl_mutex); 696 ahci_enable_all_intrs(ahci_ctlp); 697 mutex_exit(&ahci_ctlp->ahcictl_mutex); 698 return (DDI_FAILURE); 699 } 700 701 mutex_enter(&ahci_ctlp->ahcictl_mutex); 702 703 /* stop the watchdog handler */ 704 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 705 ahci_ctlp->ahcictl_timeout_id = 0; 706 707 /* deallocate the controller structures */ 708 ahci_ctlp->ahcictl_flags |= AHCI_DETACH; 709 ahci_deallocate_controller(ahci_ctlp); 710 ahci_ctlp->ahcictl_flags &= ~AHCI_DETACH; 711 712 /* destroy any mutexes */ 713 mutex_exit(&ahci_ctlp->ahcictl_mutex); 714 715 (void) pm_lower_power(ahci_ctlp->ahcictl_dip, 0, 716 PM_LEVEL_D3); 717 718 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 719 720 /* remove the interrupts */ 721 ahci_rem_intrs(ahci_ctlp); 722 723 /* remove the reg maps. */ 724 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 725 726 /* free the soft state. */ 727 ddi_soft_state_free(ahci_statep, instance); 728 729 return (DDI_SUCCESS); 730 731 case DDI_SUSPEND: 732 /* It will be implemented in Phase 2 */ 733 return (DDI_FAILURE); 734 735 default: 736 return (DDI_FAILURE); 737 } 738 } 739 740 /* 741 * The info entry point for dev_ops. 742 * 743 */ 744 static int 745 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 746 void *arg, void **result) 747 { 748 #ifndef __lock_lint 749 _NOTE(ARGUNUSED(dip)) 750 #endif /* __lock_lint */ 751 752 ahci_ctl_t *ahci_ctlp; 753 int instance; 754 dev_t dev; 755 756 dev = (dev_t)arg; 757 instance = getminor(dev); 758 759 switch (infocmd) { 760 case DDI_INFO_DEVT2DEVINFO: 761 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 762 if (ahci_ctlp != NULL) { 763 *result = ahci_ctlp->ahcictl_dip; 764 return (DDI_SUCCESS); 765 } else { 766 *result = NULL; 767 return (DDI_FAILURE); 768 } 769 case DDI_INFO_DEVT2INSTANCE: 770 *(int *)result = instance; 771 break; 772 default: 773 break; 774 } 775 776 return (DDI_SUCCESS); 777 } 778 779 /* 780 * Registers the ahci with sata framework. 781 */ 782 static int 783 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 784 { 785 struct sata_hba_tran *sata_hba_tran; 786 787 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 788 "ahci_register_sata_hba_tran enter"); 789 790 mutex_enter(&ahci_ctlp->ahcictl_mutex); 791 792 /* Allocate memory for the sata_hba_tran */ 793 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 794 795 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV; 796 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 797 sata_hba_tran->sata_tran_hba_dma_attr = 798 &ahci_ctlp->ahcictl_buffer_dma_attr; 799 800 /* Report the number of implemented ports */ 801 sata_hba_tran->sata_tran_hba_num_cports = 802 ahci_ctlp->ahcictl_num_implemented_ports; 803 804 sata_hba_tran->sata_tran_hba_features_support = 0; 805 806 /* Get the data transfer capability for PIO command by the HBA */ 807 if (cap_status & AHCI_HBA_CAP_PMD) { 808 ahci_ctlp->ahcictl_flags |= AHCI_PMD; 809 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 810 "DRQ block data transfer for PIO command protocol"); 811 } else { 812 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA only supports single " 813 "DRQ block data transfer for PIO command protocol"); 814 } 815 816 /* Report the number of command slots */ 817 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 818 819 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 820 sata_hba_tran->sata_tran_start = ahci_tran_start; 821 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 822 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 823 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 824 #ifdef __lock_lint 825 sata_hba_tran->sata_tran_selftest = ahci_selftest; 826 #endif 827 /* 828 * When SATA framework adds support for pwrmgt the 829 * pwrmgt_ops needs to be updated 830 */ 831 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 832 sata_hba_tran->sata_tran_ioctl = NULL; 833 834 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 835 836 mutex_exit(&ahci_ctlp->ahcictl_mutex); 837 838 /* Attach it to SATA framework */ 839 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 840 != DDI_SUCCESS) { 841 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 842 mutex_enter(&ahci_ctlp->ahcictl_mutex); 843 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 844 mutex_exit(&ahci_ctlp->ahcictl_mutex); 845 return (AHCI_FAILURE); 846 } 847 848 return (AHCI_SUCCESS); 849 } 850 851 /* 852 * Unregisters the ahci with sata framework. 853 */ 854 static int 855 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 856 { 857 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 858 "ahci_unregister_sata_hba_tran enter"); 859 860 /* Detach from the SATA framework. */ 861 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 862 DDI_SUCCESS) { 863 return (AHCI_FAILURE); 864 } 865 866 /* Deallocate sata_hba_tran. */ 867 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 868 sizeof (sata_hba_tran_t)); 869 870 mutex_enter(&ahci_ctlp->ahcictl_mutex); 871 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 872 mutex_exit(&ahci_ctlp->ahcictl_mutex); 873 874 return (AHCI_SUCCESS); 875 } 876 877 /* 878 * ahci_tran_probe_port is called by SATA framework. It returns port state, 879 * port status registers and an attached device type via sata_device 880 * structure. 881 * 882 * We return the cached information from a previous hardware probe. The 883 * actual hardware probing itself was done either from within 884 * ahci_initialize_controller() during the driver attach or from a phy 885 * ready change interrupt handler. 886 */ 887 static int 888 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 889 { 890 ahci_ctl_t *ahci_ctlp; 891 ahci_port_t *ahci_portp; 892 uint8_t cport = sd->satadev_addr.cport; 893 uint8_t pmport = sd->satadev_addr.pmport; 894 uint8_t qual = sd->satadev_addr.qual; 895 uint8_t device_type; 896 uint32_t port_state; 897 uint8_t port; 898 899 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 900 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 901 902 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 903 "ahci_tran_probe_port enter: cport: 0x%x, " 904 "pmport: 0x%x, qual: 0x%x", cport, pmport, qual); 905 906 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 907 908 mutex_enter(&ahci_portp->ahciport_mutex); 909 910 port_state = ahci_portp->ahciport_port_state; 911 switch (port_state) { 912 913 case SATA_PSTATE_FAILED: 914 sd->satadev_state = SATA_PSTATE_FAILED; 915 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 916 "ahci_tran_probe_port %d: PORT FAILED", port); 917 goto out; 918 919 case SATA_PSTATE_SHUTDOWN: 920 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 921 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 922 "ahci_tran_probe_port %d: PORT SHUTDOWN", port); 923 goto out; 924 925 case SATA_PSTATE_PWROFF: 926 sd->satadev_state = SATA_PSTATE_PWROFF; 927 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 928 "ahci_tran_probe_port %d: PORT PWROFF", port); 929 goto out; 930 931 case SATA_PSTATE_PWRON: 932 sd->satadev_state = SATA_PSTATE_PWRON; 933 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 934 "ahci_tran_probe_port %d: PORT PWRON", port); 935 break; 936 937 default: 938 sd->satadev_state = port_state; 939 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 940 "ahci_tran_probe_port %d: PORT NORMAL %x", 941 port, port_state); 942 break; 943 } 944 945 device_type = ahci_portp->ahciport_device_type; 946 947 switch (device_type) { 948 949 case SATA_DTYPE_ATADISK: 950 sd->satadev_type = SATA_DTYPE_ATADISK; 951 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 952 "ahci_tran_probe_port %d: DISK found", port); 953 break; 954 955 case SATA_DTYPE_ATAPICD: 956 sd->satadev_type = SATA_DTYPE_ATAPICD; 957 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 958 "ahci_tran_probe_port %d: ATAPI found", port); 959 break; 960 961 case SATA_DTYPE_PMULT: 962 sd->satadev_type = SATA_DTYPE_PMULT; 963 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 964 "ahci_tran_probe_port %d: Port Multiplier found", 965 port); 966 break; 967 968 case SATA_DTYPE_UNKNOWN: 969 sd->satadev_type = SATA_DTYPE_UNKNOWN; 970 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 971 "ahci_tran_probe_port %d: Unknown device found", port); 972 break; 973 974 default: 975 /* we don't support any other device types */ 976 sd->satadev_type = SATA_DTYPE_NONE; 977 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 978 "ahci_tran_probe_port %d: No device found", port); 979 break; 980 } 981 982 out: 983 ahci_update_sata_registers(ahci_ctlp, port, sd); 984 mutex_exit(&ahci_portp->ahciport_mutex); 985 986 return (SATA_SUCCESS); 987 } 988 989 /* 990 * Called by sata framework to transport a sata packet down stream. 991 */ 992 static int 993 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 994 { 995 ahci_ctl_t *ahci_ctlp; 996 ahci_port_t *ahci_portp; 997 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 998 uint8_t port; 999 int slot; 1000 1001 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1002 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1003 1004 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1005 "ahci_tran_start enter: cport %d satapkt 0x%p", 1006 cport, (void *)spkt); 1007 1008 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1009 1010 mutex_enter(&ahci_portp->ahciport_mutex); 1011 1012 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1013 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1014 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1015 /* 1016 * In case the targer driver would send the packet before 1017 * sata framework can have the opportunity to process those 1018 * event reports. 1019 */ 1020 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1021 spkt->satapkt_device.satadev_state = 1022 ahci_portp->ahciport_port_state; 1023 ahci_update_sata_registers(ahci_ctlp, port, 1024 &spkt->satapkt_device); 1025 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1026 "ahci_tran_start returning PORT_ERROR while " 1027 "port in FAILED/SHUTDOWN/PWROFF state: " 1028 "cport: 0x%x", port); 1029 mutex_exit(&ahci_portp->ahciport_mutex); 1030 return (SATA_TRAN_PORT_ERROR); 1031 } 1032 1033 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1034 /* 1035 * ahci_intr_phyrdy_change() may have rendered it to 1036 * SATA_DTYPE_NONE. 1037 */ 1038 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1039 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1040 spkt->satapkt_device.satadev_state = 1041 ahci_portp->ahciport_port_state; 1042 ahci_update_sata_registers(ahci_ctlp, port, 1043 &spkt->satapkt_device); 1044 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1045 "ahci_tran_start returning PORT_ERROR while " 1046 "no device attached: cport: 0x%x", port); 1047 mutex_exit(&ahci_portp->ahciport_mutex); 1048 return (SATA_TRAN_PORT_ERROR); 1049 } 1050 1051 /* 1052 * SATA HBA driver should remember that a device was reset and it 1053 * is supposed to reject any packets which do not specify either 1054 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1055 * 1056 * This is to prevent a race condition when a device was arbitrarily 1057 * reset by the HBA driver (and lost it's setting) and a target 1058 * driver sending some commands to a device before the sata framework 1059 * has a chance to restore the device setting (such as cache enable/ 1060 * disable or other resettable stuff). 1061 */ 1062 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1063 ahci_portp->ahciport_reset_in_progress = 0; 1064 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1065 "ahci_tran_start clearing the " 1066 "reset_in_progress for port: 0x%x", port); 1067 } 1068 1069 if (ahci_portp->ahciport_reset_in_progress && 1070 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1071 ! ddi_in_panic()) { 1072 spkt->satapkt_reason = SATA_PKT_BUSY; 1073 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1074 "ahci_tran_start returning BUSY while " 1075 "reset in progress: cport: 0x%x", port); 1076 mutex_exit(&ahci_portp->ahciport_mutex); 1077 return (SATA_TRAN_BUSY); 1078 } 1079 1080 if (ahci_portp->ahciport_flags & AHCI_PORT_STATE_MOPPING) { 1081 spkt->satapkt_reason = SATA_PKT_BUSY; 1082 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1083 "ahci_tran_start returning BUSY while " 1084 "mopping in progress: port: 0x%x", port); 1085 mutex_exit(&ahci_portp->ahciport_mutex); 1086 return (SATA_TRAN_BUSY); 1087 } 1088 1089 if ((slot = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt)) 1090 == AHCI_FAILURE) { 1091 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1092 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1093 "returning QUEUE_FULL: port %d", port); 1094 mutex_exit(&ahci_portp->ahciport_mutex); 1095 return (SATA_TRAN_QUEUE_FULL); 1096 } 1097 1098 if (spkt->satapkt_op_mode & 1099 (SATA_OPMODE_POLLING | SATA_OPMODE_SYNCH)) { 1100 /* we need to poll now */ 1101 mutex_exit(&ahci_portp->ahciport_mutex); 1102 ahci_poll_cmd(ahci_ctlp, ahci_portp, port, slot, spkt); 1103 mutex_enter(&ahci_portp->ahciport_mutex); 1104 } 1105 1106 mutex_exit(&ahci_portp->ahciport_mutex); 1107 1108 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1109 "sata tran accepted: port %d", port); 1110 1111 return (SATA_TRAN_ACCEPTED); 1112 } 1113 1114 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1115 if (satapkt) { \ 1116 satapkt->satapkt_reason = reason; \ 1117 /* \ 1118 * We set the satapkt_reason in both sync and \ 1119 * non-sync cases. \ 1120 */ \ 1121 } \ 1122 if (satapkt && \ 1123 !(satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1124 satapkt->satapkt_comp) { \ 1125 mutex_exit(&ahci_portp->ahciport_mutex); \ 1126 (*satapkt->satapkt_comp)(satapkt); \ 1127 mutex_enter(&ahci_portp->ahciport_mutex); \ 1128 } 1129 1130 /* 1131 * Searches for and claims a free slot. 1132 * 1133 * Returns: AHCI_FAILURE if no slots found 1134 * claimed slot number if successful 1135 * 1136 * WARNING!!! ahciport_mutex should be acquired before the function 1137 * is called. 1138 */ 1139 /*ARGSUSED*/ 1140 static int 1141 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 1142 { 1143 uint32_t free_slots; 1144 int slot; 1145 1146 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1147 "ahciport_pending_tags = 0x%x", 1148 ahci_portp->ahciport_pending_tags); 1149 1150 free_slots = (~ahci_portp->ahciport_pending_tags) 1151 & AHCI_SLOT_MASK(ahci_ctlp); 1152 1153 slot = ddi_ffs(free_slots) - 1; 1154 if (slot == -1) { 1155 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1156 "ahci_claim_free_slot: no empty slots"); 1157 return (AHCI_FAILURE); 1158 } 1159 1160 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1161 1162 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1163 "ahci_claim_free_slot: found slot: 0x%x", slot); 1164 1165 return (slot); 1166 } 1167 1168 /* 1169 * Builds the Command Table for the sata packet and delivers it to controller. 1170 * 1171 * Returns: 1172 * slot number if we can obtain a slot successfully 1173 * otherwise, return AHCI_FAILURE 1174 * 1175 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1176 */ 1177 static int 1178 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1179 uint8_t port, sata_pkt_t *spkt) 1180 { 1181 int slot; 1182 sata_cmd_t *cmd; 1183 ahci_fis_h2d_register_t *h2d_register_fisp; 1184 ahci_cmd_table_t *cmd_table; 1185 ahci_cmd_header_t *cmd_header; 1186 int ncookies; 1187 int i; 1188 1189 spkt->satapkt_reason = SATA_PKT_BUSY; 1190 1191 cmd = &spkt->satapkt_cmd; 1192 1193 /* Check if there is an empty command slot */ 1194 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp); 1195 if (slot == AHCI_FAILURE) { 1196 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free slot"); 1197 return (AHCI_FAILURE); 1198 } 1199 1200 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1201 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, slot: 0x%x, " 1202 "port: %d, satapkt: 0x%p", cmd->satacmd_cmd_reg, 1203 slot, port, (void *)spkt); 1204 1205 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 1206 bzero((void *)cmd_table, ahci_cmd_table_size); 1207 1208 /* For data transfer operations, this is the H2D Register FIS */ 1209 h2d_register_fisp = 1210 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1211 1212 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1213 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1214 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1215 SET_FIS_PMP(h2d_register_fisp, 1216 spkt->satapkt_device.satadev_addr.pmport); 1217 } 1218 1219 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1220 SET_FIS_COMMAND(h2d_register_fisp, cmd->satacmd_cmd_reg); 1221 SET_FIS_FEATURES(h2d_register_fisp, cmd->satacmd_features_reg); 1222 SET_FIS_SECTOR_COUNT(h2d_register_fisp, cmd->satacmd_sec_count_lsb); 1223 1224 switch (cmd->satacmd_addr_type) { 1225 1226 case ATA_ADDR_LBA: 1227 /* fallthrough */ 1228 1229 case ATA_ADDR_LBA28: 1230 /* LBA[7:0] */ 1231 SET_FIS_SECTOR(h2d_register_fisp, cmd->satacmd_lba_low_lsb); 1232 1233 /* LBA[15:8] */ 1234 SET_FIS_CYL_LOW(h2d_register_fisp, cmd->satacmd_lba_mid_lsb); 1235 1236 /* LBA[23:16] */ 1237 SET_FIS_CYL_HI(h2d_register_fisp, cmd->satacmd_lba_high_lsb); 1238 1239 /* LBA [27:24] (also called dev_head) */ 1240 SET_FIS_DEV_HEAD(h2d_register_fisp, cmd->satacmd_device_reg); 1241 1242 break; 1243 1244 case ATA_ADDR_LBA48: 1245 /* LBA[7:0] */ 1246 SET_FIS_SECTOR(h2d_register_fisp, cmd->satacmd_lba_low_lsb); 1247 1248 /* LBA[15:8] */ 1249 SET_FIS_CYL_LOW(h2d_register_fisp, cmd->satacmd_lba_mid_lsb); 1250 1251 /* LBA[23:16] */ 1252 SET_FIS_CYL_HI(h2d_register_fisp, cmd->satacmd_lba_high_lsb); 1253 1254 /* LBA [31:24] */ 1255 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1256 cmd->satacmd_lba_low_msb); 1257 1258 /* LBA [39:32] */ 1259 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1260 cmd->satacmd_lba_mid_msb); 1261 1262 /* LBA [47:40] */ 1263 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1264 cmd->satacmd_lba_high_msb); 1265 1266 /* Set dev_head */ 1267 SET_FIS_DEV_HEAD(h2d_register_fisp, 1268 cmd->satacmd_device_reg); 1269 1270 /* Set the extended sector count and features */ 1271 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1272 cmd->satacmd_sec_count_msb); 1273 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1274 cmd->satacmd_features_reg_ext); 1275 break; 1276 } 1277 1278 ncookies = cmd->satacmd_num_dma_cookies; 1279 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1280 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1281 ncookies, ahci_dma_prdt_number); 1282 1283 ASSERT(ncookies <= ahci_dma_prdt_number); 1284 1285 /* *** now fill the scatter gather list ******* */ 1286 for (i = 0; i < ncookies; i++) { 1287 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1288 cmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1289 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1290 cmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1291 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1292 cmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1293 } 1294 1295 /* Set Command Header in Command List */ 1296 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 1297 BZERO_DESCR_INFO(cmd_header); 1298 BZERO_PRD_BYTE_COUNT(cmd_header); 1299 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1300 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1301 1302 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1303 "sata_data_direction = 0x%x", 1304 cmd->satacmd_flags.sata_data_direction); 1305 1306 if (cmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1307 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1308 1309 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1310 1311 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1312 ahci_portp->ahciport_slot_pkts[slot] = spkt; 1313 1314 /* 1315 * We are overloading satapkt_hba_driver_private with 1316 * watched_cycle count. 1317 */ 1318 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1319 1320 /* *** finished filling the scatter gather list , sync******* */ 1321 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 1322 0, 1323 ahci_cmd_table_size, 1324 DDI_DMA_SYNC_FORDEV); 1325 1326 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1327 slot * sizeof (ahci_cmd_header_t), 1328 sizeof (ahci_cmd_header_t), 1329 DDI_DMA_SYNC_FORDEV); 1330 1331 /* Indicate to the HBA that a command is active. */ 1332 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1333 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1334 (0x1 << slot)); 1335 1336 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1337 "exit: port %d", port); 1338 1339 return (slot); 1340 } 1341 1342 /* 1343 * Polls for the completion of the command. This is safe with both 1344 * interrupts enabled or disabled. 1345 */ 1346 static void 1347 ahci_poll_cmd(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1348 uint8_t port, int slot, sata_pkt_t *spkt) 1349 { 1350 uint32_t slot_status; 1351 int pkt_timeout_ticks; 1352 int in_panic = ddi_in_panic(); 1353 1354 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1355 "ahci_poll_cmd entered, port: %x", port); 1356 1357 pkt_timeout_ticks = 1358 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1359 1360 mutex_enter(&ahci_portp->ahciport_mutex); 1361 1362 /* we start out with SATA_PKT_COMPLETED as the satapkt_reason */ 1363 spkt->satapkt_reason = SATA_PKT_COMPLETED; 1364 1365 /* 1366 * The interrupt handler will return directly for poll commands in case 1367 * the interrupt has been generated before interrupts were disabled. 1368 */ 1369 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 1370 1371 do { 1372 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1373 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1374 1375 if (slot_status & (0x1 << slot)) { 1376 if (in_panic) { 1377 /* 1378 * If we are in panic, we can't rely on 1379 * timers; so, busy wait instead of delay(). 1380 */ 1381 mutex_exit(&ahci_portp->ahciport_mutex); 1382 drv_usecwait(AHCI_1MS_USECS); 1383 mutex_enter(&ahci_portp->ahciport_mutex); 1384 } else { 1385 mutex_exit(&ahci_portp->ahciport_mutex); 1386 #ifndef __lock_lint 1387 delay(AHCI_1MS_TICKS); 1388 #endif /* __lock_lint */ 1389 mutex_enter(&ahci_portp->ahciport_mutex); 1390 } 1391 } else { 1392 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "poll_cmd finished"); 1393 break; 1394 } 1395 1396 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1397 1398 } while (pkt_timeout_ticks > 0); 1399 1400 if (spkt->satapkt_reason != SATA_PKT_COMPLETED) { 1401 goto poll_done; 1402 } 1403 1404 if (slot_status & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)) { 1405 spkt->satapkt_reason = SATA_PKT_TIMEOUT; 1406 } 1407 1408 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 1409 ahci_portp->ahciport_slot_pkts[slot] = NULL; 1410 1411 poll_done: 1412 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 1413 mutex_exit(&ahci_portp->ahciport_mutex); 1414 } 1415 1416 /* 1417 * Called by the sata framework to abort the previously sent packet(s). 1418 * 1419 * Reset device to abort commands. 1420 */ 1421 static int 1422 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1423 { 1424 ahci_ctl_t *ahci_ctlp; 1425 ahci_port_t *ahci_portp; 1426 uint32_t slot_status; 1427 uint32_t aborted_tags, finished_tags; 1428 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1429 uint8_t port; 1430 int tmp_slot; 1431 1432 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1433 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1434 1435 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1436 "ahci_tran_abort on cport %d", cport); 1437 1438 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1439 1440 mutex_enter(&ahci_portp->ahciport_mutex); 1441 1442 /* 1443 * To prevent recursive enter to ahci_mop_commands, we need 1444 * check AHCI_PORT_STATE_MOPPING flag. 1445 */ 1446 if (ahci_portp->ahciport_flags & AHCI_PORT_STATE_MOPPING) { 1447 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1448 "ahci_tran_abort: port %d is in " 1449 "mopping process, so just return directly ", port); 1450 mutex_exit(&ahci_portp->ahciport_mutex); 1451 return (SATA_SUCCESS); 1452 } 1453 1454 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1455 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1456 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1457 /* 1458 * In case the targer driver would send the request before 1459 * sata framework can have the opportunity to process those 1460 * event reports. 1461 */ 1462 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1463 spkt->satapkt_device.satadev_state = 1464 ahci_portp->ahciport_port_state; 1465 ahci_update_sata_registers(ahci_ctlp, port, 1466 &spkt->satapkt_device); 1467 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1468 "ahci_tran_abort returning SATA_FAILURE while " 1469 "port in FAILED/SHUTDOWN/PWROFF state: " 1470 "cport: 0x%x", port); 1471 mutex_exit(&ahci_portp->ahciport_mutex); 1472 return (SATA_FAILURE); 1473 } 1474 1475 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1476 /* 1477 * ahci_intr_phyrdy_change() may have rendered it to 1478 * AHCI_PORT_TYPE_NODEV. 1479 */ 1480 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1481 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1482 spkt->satapkt_device.satadev_state = 1483 ahci_portp->ahciport_port_state; 1484 ahci_update_sata_registers(ahci_ctlp, port, 1485 &spkt->satapkt_device); 1486 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1487 "ahci_tran_abort returning SATA_FAILURE while " 1488 "no device attached: cport: 0x%x", port); 1489 mutex_exit(&ahci_portp->ahciport_mutex); 1490 return (SATA_FAILURE); 1491 } 1492 1493 if (flag == SATA_ABORT_ALL_PACKETS) { 1494 aborted_tags = ahci_portp->ahciport_pending_tags; 1495 cmn_err(CE_NOTE, "!ahci port %d abort all packets", port); 1496 } else { 1497 aborted_tags = 0xffffffff; 1498 /* 1499 * Aborting one specific packet, first search our 1500 * ahciport_slot_pkts[] list for matching spkt. 1501 */ 1502 for (tmp_slot = 0; 1503 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 1504 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 1505 aborted_tags = (0x1 << tmp_slot); 1506 break; 1507 } 1508 } 1509 1510 if (aborted_tags == 0xffffffff) { 1511 /* request packet is not on the pending list */ 1512 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1513 "Cannot find the aborting pkt 0x%p on the " 1514 "pending list", (void *)spkt); 1515 ahci_update_sata_registers(ahci_ctlp, port, 1516 &spkt->satapkt_device); 1517 mutex_exit(&ahci_portp->ahciport_mutex); 1518 return (SATA_FAILURE); 1519 } 1520 cmn_err(CE_NOTE, "!ahci port %d abort satapkt 0x%p", 1521 port, (void *)spkt); 1522 } 1523 1524 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1525 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1526 1527 ahci_portp->ahciport_flags |= AHCI_PORT_STATE_MOPPING; 1528 1529 /* 1530 * To abort the packet(s), first we are trying to clear PxCMD.ST 1531 * and PxCMD.FRE to stop the port, and if the port can be stopped 1532 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 1533 * then we just send back the aborted packet(s) with ABORTED flag 1534 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 1535 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 1536 * perform a COMRESET. 1537 */ 1538 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 1539 ahci_portp, port, NULL); 1540 1541 /* 1542 * Compute which have finished and which need to be retried. 1543 * 1544 * The finished tags are ahciport_pending_tags minus the slot_status. 1545 * The aborted_tags have to be reduced by finished_tags since we 1546 * can't possibly abort a tag which had finished already. 1547 */ 1548 finished_tags = ahci_portp->ahciport_pending_tags & 1549 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1550 1551 aborted_tags &= ~finished_tags; 1552 1553 mutex_exit(&ahci_portp->ahciport_mutex); 1554 ahci_mop_commands(ahci_ctlp, 1555 ahci_portp, 1556 port, 1557 slot_status, 1558 0, /* failed tags */ 1559 0, /* timeout tags */ 1560 aborted_tags, 1561 0); /* reset tags */ 1562 1563 mutex_enter(&ahci_portp->ahciport_mutex); 1564 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 1565 mutex_exit(&ahci_portp->ahciport_mutex); 1566 1567 return (SATA_SUCCESS); 1568 } 1569 1570 /* 1571 * Used to do device reset and reject all the pending packets on a device 1572 * during the reset operation. 1573 * 1574 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1575 */ 1576 static int 1577 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 1578 ahci_port_t *ahci_portp, uint8_t port) 1579 { 1580 uint32_t slot_status; 1581 uint32_t reset_tags, finished_tags; 1582 sata_device_t sdevice; 1583 int ret; 1584 1585 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1586 "ahci_reset_device_reject_pkts on port: %d", port); 1587 1588 /* 1589 * To prevent recursive enter to ahci_mop_commands, we need 1590 * check AHCI_PORT_STATE_MOPPING flag. 1591 */ 1592 if (ahci_portp->ahciport_flags & AHCI_PORT_STATE_MOPPING) { 1593 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1594 "ahci_reset_device_reject_pkts: port %d is in " 1595 "mopping process, so return directly ", port); 1596 return (SATA_SUCCESS); 1597 } 1598 1599 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1600 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1601 1602 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1603 1604 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 1605 != AHCI_SUCCESS) { 1606 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1607 "Try to do a port reset after software " 1608 "reset failed", port); 1609 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 1610 if (ret != AHCI_SUCCESS) { 1611 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 1612 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1613 "ahci_reset_device_reject_pkts: port %d " 1614 "failed", port); 1615 return (SATA_FAILURE); 1616 } 1617 } 1618 /* Set the reset in progress flag */ 1619 ahci_portp->ahciport_reset_in_progress = 1; 1620 1621 ahci_portp->ahciport_flags |= AHCI_PORT_STATE_MOPPING; 1622 1623 /* Indicate to the framework that a reset has happened */ 1624 bzero((void *)&sdevice, sizeof (sata_device_t)); 1625 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 1626 sdevice.satadev_addr.pmport = AHCI_PORTMULT_CONTROL_PORT; 1627 1628 if (ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT) { 1629 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT; 1630 } else { 1631 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 1632 } 1633 1634 sdevice.satadev_state = SATA_DSTATE_RESET | 1635 SATA_DSTATE_PWR_ACTIVE; 1636 mutex_exit(&ahci_portp->ahciport_mutex); 1637 sata_hba_event_notify( 1638 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 1639 &sdevice, 1640 SATA_EVNT_DEVICE_RESET); 1641 mutex_enter(&ahci_portp->ahciport_mutex); 1642 1643 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 1644 "port %d sending event up: SATA_EVNT_RESET", port); 1645 1646 /* Next try to mop the pending commands */ 1647 finished_tags = ahci_portp->ahciport_pending_tags & 1648 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1649 1650 reset_tags &= ~finished_tags; 1651 1652 mutex_exit(&ahci_portp->ahciport_mutex); 1653 ahci_mop_commands(ahci_ctlp, 1654 ahci_portp, 1655 port, 1656 slot_status, 1657 0, /* failed tags */ 1658 0, /* timeout tags */ 1659 0, /* aborted tags */ 1660 reset_tags); /* reset tags */ 1661 mutex_enter(&ahci_portp->ahciport_mutex); 1662 1663 return (SATA_SUCCESS); 1664 } 1665 1666 /* 1667 * Used to do port reset and reject all the pending packets on a port during 1668 * the reset operation. 1669 * 1670 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1671 */ 1672 static int 1673 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 1674 ahci_port_t *ahci_portp, uint8_t port) 1675 { 1676 uint32_t slot_status; 1677 uint32_t reset_tags, finished_tags; 1678 1679 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1680 "ahci_reset_port_reject_pkts on port: %d", port); 1681 1682 /* 1683 * To prevent recursive enter to ahci_mop_commands, we need 1684 * check AHCI_PORT_STATE_MOPPING flag. 1685 */ 1686 if (ahci_portp->ahciport_flags & AHCI_PORT_STATE_MOPPING) { 1687 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1688 "ahci_reset_port_reject_pkts: port %d is in " 1689 "mopping process, so return directly ", port); 1690 return (SATA_SUCCESS); 1691 } 1692 1693 ahci_portp->ahciport_flags |= AHCI_PORT_STATE_MOPPING; 1694 1695 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1696 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1697 1698 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1699 1700 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 1701 ahci_portp, port, AHCI_PORT_RESET) != AHCI_SUCCESS) 1702 return (SATA_FAILURE); 1703 1704 finished_tags = ahci_portp->ahciport_pending_tags & 1705 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1706 1707 reset_tags &= ~finished_tags; 1708 1709 mutex_exit(&ahci_portp->ahciport_mutex); 1710 ahci_mop_commands(ahci_ctlp, 1711 ahci_portp, 1712 port, 1713 slot_status, 1714 0, /* failed tags */ 1715 0, /* timeout tags */ 1716 0, /* aborted tags */ 1717 reset_tags); /* reset tags */ 1718 mutex_enter(&ahci_portp->ahciport_mutex); 1719 1720 return (SATA_SUCCESS); 1721 } 1722 1723 /* 1724 * Used to do hba reset and reject all the pending packets on all ports 1725 * during the reset operation. 1726 */ 1727 static int 1728 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 1729 { 1730 ahci_port_t *ahci_portp; 1731 uint32_t slot_status[AHCI_MAX_PORTS]; 1732 uint32_t reset_tags[AHCI_MAX_PORTS]; 1733 uint32_t finished_tags[AHCI_MAX_PORTS]; 1734 sata_device_t sdevice[AHCI_MAX_PORTS]; 1735 uint8_t port; 1736 int ret = SATA_SUCCESS; 1737 1738 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1739 "ahci_reset_hba_reject_pkts enter"); 1740 1741 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1742 1743 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 1744 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 1745 continue; 1746 } 1747 1748 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1749 1750 mutex_enter(&ahci_portp->ahciport_mutex); 1751 slot_status[port] = ddi_get32( 1752 ahci_ctlp->ahcictl_ahci_acc_handle, 1753 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1754 reset_tags[port] = slot_status[port] 1755 & AHCI_SLOT_MASK(ahci_ctlp); 1756 mutex_exit(&ahci_portp->ahciport_mutex); 1757 } 1758 1759 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 1760 ret = SATA_FAILURE; 1761 goto out; 1762 } 1763 1764 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 1765 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 1766 continue; 1767 } 1768 1769 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1770 1771 mutex_enter(&ahci_portp->ahciport_mutex); 1772 /* 1773 * To prevent recursive enter to ahci_mop_commands, we need 1774 * check AHCI_PORT_STATE_MOPPING flag. 1775 */ 1776 if (ahci_portp->ahciport_flags & AHCI_PORT_STATE_MOPPING) { 1777 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1778 "ahci_reset_hba_reject_pkts: port %d is in " 1779 "mopping process, so return directly ", port); 1780 mutex_exit(&ahci_portp->ahciport_mutex); 1781 continue; 1782 } 1783 1784 ahci_portp->ahciport_flags |= AHCI_PORT_STATE_MOPPING; 1785 1786 /* Indicate to the framework that a reset has happened */ 1787 bzero((void *)&sdevice[port], sizeof (sata_device_t)); 1788 sdevice[port].satadev_addr.cport = 1789 ahci_ctlp->ahcictl_port_to_cport[port]; 1790 sdevice[port].satadev_addr.pmport = AHCI_PORTMULT_CONTROL_PORT; 1791 1792 if (ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT) { 1793 sdevice[port].satadev_addr.qual = SATA_ADDR_DPMPORT; 1794 } else { 1795 sdevice[port].satadev_addr.qual = SATA_ADDR_DCPORT; 1796 } 1797 sdevice[port].satadev_state = SATA_DSTATE_RESET | 1798 SATA_DSTATE_PWR_ACTIVE; 1799 mutex_exit(&ahci_portp->ahciport_mutex); 1800 sata_hba_event_notify( 1801 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 1802 &sdevice[port], 1803 SATA_EVNT_DEVICE_RESET); 1804 mutex_enter(&ahci_portp->ahciport_mutex); 1805 1806 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 1807 "port %d sending event up: SATA_EVNT_RESET", 1808 port); 1809 1810 finished_tags[port] = ahci_portp->ahciport_pending_tags & 1811 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 1812 1813 reset_tags[port] &= ~finished_tags[port]; 1814 1815 mutex_exit(&ahci_portp->ahciport_mutex); 1816 ahci_mop_commands(ahci_ctlp, 1817 ahci_portp, 1818 port, 1819 slot_status[port], 1820 0, /* failed tags */ 1821 0, /* timeout tags */ 1822 0, /* aborted tags */ 1823 reset_tags[port]); /* reset tags */ 1824 } 1825 out: 1826 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1827 1828 return (ret); 1829 } 1830 1831 /* 1832 * Called by sata framework to reset a port(s) or device. 1833 */ 1834 static int 1835 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 1836 { 1837 ahci_ctl_t *ahci_ctlp; 1838 ahci_port_t *ahci_portp; 1839 uint8_t cport = sd->satadev_addr.cport; 1840 uint8_t port; 1841 int ret = SATA_SUCCESS; 1842 1843 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1844 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1845 1846 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1847 "ahci_tran_reset_port enter: cport: 0x%x", cport); 1848 1849 switch (sd->satadev_addr.qual) { 1850 case SATA_ADDR_CPORT: 1851 /* Port reset */ 1852 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1853 cmn_err(CE_NOTE, "!ahci port %d reset port", port); 1854 1855 mutex_enter(&ahci_portp->ahciport_mutex); 1856 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 1857 mutex_exit(&ahci_portp->ahciport_mutex); 1858 1859 break; 1860 1861 case SATA_ADDR_DCPORT: 1862 /* Device reset */ 1863 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1864 cmn_err(CE_NOTE, "!ahci port %d reset device", port); 1865 1866 mutex_enter(&ahci_portp->ahciport_mutex); 1867 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1868 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1869 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1870 /* 1871 * In case the targer driver would send the request 1872 * before sata framework can have the opportunity to 1873 * process those event reports. 1874 */ 1875 sd->satadev_state = ahci_portp->ahciport_port_state; 1876 ahci_update_sata_registers(ahci_ctlp, port, sd); 1877 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1878 "ahci_tran_reset_dport returning SATA_FAILURE " 1879 "while port in FAILED/SHUTDOWN/PWROFF state: " 1880 "cport: 0x%x", port); 1881 mutex_exit(&ahci_portp->ahciport_mutex); 1882 ret = SATA_FAILURE; 1883 break; 1884 } 1885 1886 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1887 /* 1888 * ahci_intr_phyrdy_change() may have rendered it to 1889 * AHCI_PORT_TYPE_NODEV. 1890 */ 1891 sd->satadev_type = SATA_DTYPE_NONE; 1892 sd->satadev_state = ahci_portp->ahciport_port_state; 1893 ahci_update_sata_registers(ahci_ctlp, port, sd); 1894 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1895 "ahci_tran_reset_dport returning SATA_FAILURE " 1896 "while no device attached: cport: 0x%x", port); 1897 mutex_exit(&ahci_portp->ahciport_mutex); 1898 ret = SATA_FAILURE; 1899 break; 1900 } 1901 1902 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 1903 ahci_portp, port); 1904 mutex_exit(&ahci_portp->ahciport_mutex); 1905 break; 1906 1907 case SATA_ADDR_CNTRL: 1908 /* Reset the whole controller */ 1909 cmn_err(CE_NOTE, "!ahci port %d reset the whole hba", port); 1910 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 1911 break; 1912 1913 case SATA_ADDR_PMPORT: 1914 case SATA_ADDR_DPMPORT: 1915 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1916 "port multiplier will be supported later"); 1917 /* FALLSTHROUGH */ 1918 default: 1919 ret = SATA_FAILURE; 1920 } 1921 1922 return (ret); 1923 } 1924 1925 /* 1926 * Called by sata framework to activate a port as part of hotplug. 1927 * (cfgadm -c connect satax/y) 1928 * Note: Not port-mult aware. 1929 */ 1930 static int 1931 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 1932 { 1933 ahci_ctl_t *ahci_ctlp; 1934 ahci_port_t *ahci_portp; 1935 uint8_t cport = satadev->satadev_addr.cport; 1936 uint8_t port; 1937 1938 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1939 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1940 1941 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1942 "ahci_tran_hotplug_port_activate cport %d enter", cport); 1943 1944 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1945 1946 mutex_enter(&ahci_portp->ahciport_mutex); 1947 cmn_err(CE_NOTE, "!ahci port %d activate", port); 1948 1949 /* Enable the interrupts on the port. */ 1950 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 1951 1952 /* 1953 * Reset the port so that the PHY communication would be re-established. 1954 * But this reset is an internal operation; the sata framework does 1955 * not need to know about it. 1956 */ 1957 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 1958 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP); 1959 1960 /* 1961 * Need to check the link status and device status of the port 1962 * and consider raising power if the port was in D3 state 1963 */ 1964 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 1965 satadev->satadev_state = SATA_PSTATE_PWRON; 1966 1967 ahci_update_sata_registers(ahci_ctlp, port, satadev); 1968 1969 mutex_exit(&ahci_portp->ahciport_mutex); 1970 return (SATA_SUCCESS); 1971 } 1972 1973 /* 1974 * Called by sata framework to deactivate a port as part of hotplug. 1975 * (cfgadm -c disconnect satax/y) 1976 * Note: Not port-mult aware. 1977 */ 1978 static int 1979 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 1980 { 1981 ahci_ctl_t *ahci_ctlp; 1982 ahci_port_t *ahci_portp; 1983 uint8_t cport = satadev->satadev_addr.cport; 1984 uint8_t port; 1985 1986 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1987 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1988 1989 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1990 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 1991 1992 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1993 1994 mutex_enter(&ahci_portp->ahciport_mutex); 1995 cmn_err(CE_NOTE, "!ahci port %d deactivate", port); 1996 1997 /* Disable the interrupts on the port. */ 1998 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 1999 2000 /* First to abort all the pending commands */ 2001 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2002 2003 /* Then shut down the port */ 2004 (void) ahci_port_into_notrunning_state(ahci_ctlp, 2005 ahci_portp, port); 2006 2007 /* Update ahciport_port_state */ 2008 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2009 2010 satadev->satadev_state = SATA_PSTATE_SHUTDOWN; 2011 2012 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2013 2014 mutex_exit(&ahci_portp->ahciport_mutex); 2015 return (SATA_SUCCESS); 2016 } 2017 2018 /* 2019 * To be used to mark all the pending pkts with ABORTED 2020 * when a device is unplugged or a port is deactivated. 2021 * 2022 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2023 */ 2024 static void 2025 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2026 ahci_port_t *ahci_portp, uint8_t port) 2027 { 2028 uint32_t slot_status; 2029 uint32_t abort_tags; 2030 2031 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2032 "ahci_reject_all_abort_pkts on port: %d", port); 2033 2034 /* 2035 * To prevent recursive enter to ahci_mop_commands, we need 2036 * check AHCI_PORT_STATE_MOPPING flag. 2037 */ 2038 if (ahci_portp->ahciport_flags & AHCI_PORT_STATE_MOPPING) { 2039 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2040 "ahci_reject_all_abort_pkts: port %d is in " 2041 "mopping process, so return directly ", port); 2042 return; 2043 } 2044 2045 ahci_portp->ahciport_flags |= AHCI_PORT_STATE_MOPPING; 2046 2047 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2048 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2049 2050 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2051 2052 mutex_exit(&ahci_portp->ahciport_mutex); 2053 ahci_mop_commands(ahci_ctlp, 2054 ahci_portp, 2055 port, 2056 slot_status, 2057 0, /* failed tags */ 2058 0, /* timeout tags */ 2059 abort_tags, /* aborting tags */ 2060 0); /* reset tags */ 2061 mutex_enter(&ahci_portp->ahciport_mutex); 2062 } 2063 2064 #if defined(__lock_lint) 2065 static int 2066 ahci_selftest(dev_info_t *dip, sata_device_t *device) 2067 { 2068 return (SATA_SUCCESS); 2069 } 2070 #endif 2071 2072 /* 2073 * Initialize the controller and set up driver data structures. 2074 * 2075 * This routine can be called from three seperate cases: DDI_ATTACH, 2076 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2077 * other two cases; the memory allocation and device signature probing 2078 * are attempted only during DDI_ATTACH case. 2079 * 2080 * WARNING!!! Disable the whole controller's interrupts before calling and 2081 * the interrupts will be enabled upon successfully return. 2082 */ 2083 static int 2084 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2085 { 2086 ahci_port_t *ahci_portp; 2087 uint32_t ghc_control; 2088 int port, cport = 0; 2089 2090 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2091 "ahci_initialize_controller enter"); 2092 2093 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2094 2095 /* 2096 * Indicate that system software is AHCI aware by setting 2097 * GHC.AE to 1 2098 */ 2099 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2100 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2101 2102 ghc_control |= AHCI_HBA_GHC_AE; 2103 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2104 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2105 ghc_control); 2106 2107 /* Initialize the implemented ports and structures */ 2108 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2109 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2110 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2111 "hba port %d not implemented", port); 2112 continue; 2113 } 2114 2115 /* only allocate port during attach */ 2116 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2117 #ifndef __lock_lint 2118 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2119 ahci_ctlp->ahcictl_port_to_cport[port] = 2120 (uint8_t)cport++; 2121 #endif /* __lock_lint */ 2122 if (ahci_alloc_port_state(ahci_ctlp, port) != 2123 AHCI_SUCCESS) { 2124 goto err_out; 2125 } 2126 } 2127 2128 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2129 mutex_enter(&ahci_portp->ahciport_mutex); 2130 2131 /* 2132 * Ensure that the controller is not in the running state 2133 * by checking every implemented port's PxCMD register 2134 */ 2135 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2136 != AHCI_SUCCESS) { 2137 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2138 "ahci_initialize_controller: failed to " 2139 "initialize port %d", port); 2140 /* 2141 * Set the port state to SATA_PSTATE_FAILED if 2142 * failed to initialize it. 2143 */ 2144 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 2145 } 2146 2147 mutex_exit(&ahci_portp->ahciport_mutex); 2148 } 2149 2150 /* Enable the whole controller interrupts */ 2151 ahci_enable_all_intrs(ahci_ctlp); 2152 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2153 2154 return (AHCI_SUCCESS); 2155 err_out: 2156 2157 for (port--; port >= 0; port--) { 2158 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2159 ahci_dealloc_port_state(ahci_ctlp, port); 2160 } 2161 } 2162 2163 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2164 2165 return (AHCI_FAILURE); 2166 } 2167 2168 /* 2169 * Reverse of ahci_initialize_controller(), only need to de-allocate 2170 * all ports' state structures for AHCI_DETACH case. 2171 * 2172 * WARNING!!! ahcictl_mutex should be acquired before the function is called. 2173 */ 2174 static void 2175 ahci_deallocate_controller(ahci_ctl_t *ahci_ctlp) 2176 { 2177 uint8_t port; 2178 2179 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2180 "ahci_deallocate_controller enter"); 2181 2182 /* disable all the interrupts. */ 2183 ahci_disable_all_intrs(ahci_ctlp); 2184 2185 if (ahci_ctlp->ahcictl_flags & AHCI_DETACH) { 2186 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2187 2188 /* if this port is implemented by the HBA */ 2189 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2190 ahci_dealloc_port_state(ahci_ctlp, port); 2191 } 2192 } 2193 } 2194 2195 /* 2196 * The routine is to initialize the port. First put the port in NOTRunning 2197 * state, then enable port interrupt and clear Serror register. And under 2198 * AHCI_ATTACH case, find device signature and then try to start the port. 2199 * 2200 * WARNING!!! ahcictl_mutex and ahciport_mutex should be acquired before 2201 * the function is called. 2202 */ 2203 static int 2204 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2205 ahci_port_t *ahci_portp, uint8_t port) 2206 { 2207 uint32_t port_cmd_status; 2208 2209 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2210 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2211 2212 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2213 "ahci_initialize_port: port %d " 2214 "port_cmd_status = 0x%x", port, port_cmd_status); 2215 /* 2216 * Check whether the port is in NotRunning state, if not, 2217 * put the port in NotRunning state 2218 */ 2219 if (!(port_cmd_status & 2220 (AHCI_CMD_STATUS_ST | 2221 AHCI_CMD_STATUS_CR | 2222 AHCI_CMD_STATUS_FRE | 2223 AHCI_CMD_STATUS_FR))) { 2224 2225 goto done_out; 2226 } 2227 2228 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2229 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT) != AHCI_SUCCESS) 2230 return (AHCI_FAILURE); 2231 2232 done_out: 2233 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2234 "port %d is in NotRunning state", port); 2235 2236 /* Enable port interrupts */ 2237 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2238 2239 /* 2240 * Only probe ports/devices and get the types of attached 2241 * devices during attach. 2242 */ 2243 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2244 if (ahci_find_dev_signature(ahci_ctlp, 2245 ahci_portp, port) != AHCI_SUCCESS) { 2246 2247 return (AHCI_FAILURE); 2248 } 2249 2250 /* Try to start the port */ 2251 if ((ahci_portp->ahciport_device_type 2252 == SATA_DTYPE_ATADISK) && 2253 (ahci_start_port(ahci_ctlp, port) 2254 != AHCI_SUCCESS)) { 2255 2256 return (AHCI_FAILURE); 2257 } 2258 } 2259 2260 return (AHCI_SUCCESS); 2261 } 2262 2263 /* 2264 * AHCI device reset ...; a single device on one of the ports is reset, 2265 * but the HBA and physical communication remain intact. This is the 2266 * least intrusive. 2267 * 2268 * When issuing a software reset sequence, there should not be other 2269 * commands in the command list, so we will first clear and then re-set 2270 * PxCMD.ST to clear PxCI. And before issuing the software reset, 2271 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 2272 * cleared. 2273 * 2274 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 2275 * set before the function is called. 2276 */ 2277 static int 2278 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 2279 uint8_t port) 2280 { 2281 ahci_fis_h2d_register_t *h2d_register_fisp; 2282 ahci_cmd_table_t *cmd_table; 2283 ahci_cmd_header_t *cmd_header; 2284 int32_t port_cmd_status, port_cmd_issue, port_task_file; 2285 int slot, loop_count; 2286 2287 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2288 "Port %d device resetting", port); 2289 2290 /* First to clear PxCMD.ST */ 2291 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2292 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2293 2294 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 2295 2296 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2297 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2298 port_cmd_status|AHCI_CMD_STATUS_ST); 2299 2300 /* And then to re-set PxCMD.ST */ 2301 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2302 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2303 2304 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2305 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2306 port_cmd_status|AHCI_CMD_STATUS_ST); 2307 2308 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 2309 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2310 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2311 2312 if (port_task_file & AHCI_TFD_STS_BSY || 2313 port_task_file & AHCI_TFD_STS_DRQ) { 2314 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 2315 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2316 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 2317 "but PxCMD.CLO isn't supported, so a port " 2318 "reset is needed."); 2319 return (AHCI_FAILURE); 2320 } 2321 } 2322 2323 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp); 2324 if (slot == AHCI_FAILURE) { 2325 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2326 "ahci_software_reset: no free slot"); 2327 return (AHCI_FAILURE); 2328 } 2329 2330 /* Now send the first R2H FIS with SRST set to 1 */ 2331 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 2332 bzero((void *)cmd_table, ahci_cmd_table_size); 2333 2334 h2d_register_fisp = 2335 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 2336 2337 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 2338 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 2339 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 2340 2341 /* Set Command Header in Command List */ 2342 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 2343 BZERO_DESCR_INFO(cmd_header); 2344 BZERO_PRD_BYTE_COUNT(cmd_header); 2345 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 2346 2347 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 2348 SET_RESET(cmd_header, 1); 2349 SET_WRITE(cmd_header, 1); 2350 2351 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 2352 0, 2353 ahci_cmd_table_size, 2354 DDI_DMA_SYNC_FORDEV); 2355 2356 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 2357 slot * sizeof (ahci_cmd_header_t), 2358 sizeof (ahci_cmd_header_t), 2359 DDI_DMA_SYNC_FORDEV); 2360 2361 /* Indicate to the HBA that a command is active. */ 2362 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2363 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 2364 (0x1 << slot)); 2365 2366 loop_count = 0; 2367 2368 /* Loop till the first command is finished */ 2369 do { 2370 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2371 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2372 2373 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 2374 /* We are effectively timing out after 0.1 sec. */ 2375 break; 2376 } 2377 /* Wait for 10 millisec */ 2378 #ifndef __lock_lint 2379 delay(AHCI_10MS_TICKS); 2380 #endif /* __lock_lint */ 2381 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 2382 2383 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 2384 "ahci_software_reset: 1st loop count: %d, " 2385 "port_cmd_issue = 0x%x, slot = 0x%x", 2386 loop_count, port_cmd_issue, slot); 2387 2388 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 2389 ahci_portp->ahciport_slot_pkts[slot] = NULL; 2390 2391 /* Now send the second R2H FIS with SRST cleard to zero */ 2392 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 2393 bzero((void *)cmd_table, ahci_cmd_table_size); 2394 2395 h2d_register_fisp = 2396 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 2397 2398 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 2399 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 2400 2401 /* Set Command Header in Command List */ 2402 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 2403 BZERO_DESCR_INFO(cmd_header); 2404 BZERO_PRD_BYTE_COUNT(cmd_header); 2405 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 2406 2407 SET_WRITE(cmd_header, 1); 2408 2409 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 2410 0, 2411 ahci_cmd_table_size, 2412 DDI_DMA_SYNC_FORDEV); 2413 2414 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 2415 slot * sizeof (ahci_cmd_header_t), 2416 sizeof (ahci_cmd_header_t), 2417 DDI_DMA_SYNC_FORDEV); 2418 2419 /* Indicate to the HBA that a command is active. */ 2420 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2421 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 2422 (0x1 << slot)); 2423 2424 loop_count = 0; 2425 2426 /* Loop till the second command is finished */ 2427 do { 2428 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2429 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2430 2431 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 2432 /* We are effectively timing out after 0.1 sec. */ 2433 break; 2434 } 2435 /* Wait for 10 millisec */ 2436 #ifndef __lock_lint 2437 delay(AHCI_10MS_TICKS); 2438 #endif /* __lock_lint */ 2439 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 2440 2441 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 2442 "ahci_software_reset: 2nd loop count: %d, " 2443 "port_cmd_issue = 0x%x, slot = 0x%x", 2444 loop_count, port_cmd_issue, slot); 2445 2446 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 2447 ahci_portp->ahciport_slot_pkts[slot] = NULL; 2448 2449 return (AHCI_SUCCESS); 2450 } 2451 2452 /* 2453 * AHCI port reset ...; the physical communication between the HBA and device 2454 * on a port are disabled. This is more intrusive. 2455 * 2456 * When an HBA or port reset occurs, Phy communication shall 2457 * be re-established with the device through a COMRESET followed by the 2458 * normal out-of-band communication sequence defined in Serial ATA. AT 2459 * the end of reset, the device, if working properly, will send a D2H 2460 * Register FIS, which contains the device signature. When the HBA receives 2461 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 2462 * the PxSIG register with the signature. 2463 * 2464 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 2465 * to individually spin-up attached devices. Please refer to chapter 10.9 of 2466 * AHCI 1.1 spec. 2467 */ 2468 /* 2469 * WARNING!!! ahciport_mutex should be acquired, intr should be disabled, 2470 * and PxCMD.ST and PxCMD.FRE should be also cleared before the function 2471 * is called. 2472 */ 2473 static int 2474 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 2475 { 2476 uint32_t cap_status, port_cmd_status; 2477 uint32_t port_scontrol, port_sstatus; 2478 uint32_t port_signature, port_intr_status, port_task_file; 2479 int loop_count; 2480 2481 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2482 "Port %d port resetting...", port); 2483 2484 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2485 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 2486 2487 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2488 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2489 2490 if (cap_status & AHCI_HBA_CAP_SSS) { 2491 /* 2492 * HBA support staggered spin-up, if the port has 2493 * not spin up yet, then force it to do spin-up 2494 */ 2495 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 2496 if (!(ahci_portp->ahciport_flags 2497 & AHCI_PORT_STATE_SPINUP)) { 2498 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2499 "Port %d PxCMD.SUD is zero, force " 2500 "it to do spin-up", port); 2501 ahci_portp->ahciport_flags |= 2502 AHCI_PORT_STATE_SPINUP; 2503 } 2504 } 2505 } else { 2506 /* 2507 * HBA doesn't support stagger spin-up, force it 2508 * to do normal COMRESET 2509 */ 2510 ASSERT(port_cmd_status & AHCI_CMD_STATUS_SUD); 2511 if (ahci_portp->ahciport_flags & 2512 AHCI_PORT_STATE_SPINUP) { 2513 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2514 "HBA does not support staggered spin-up " 2515 "force it to do normal COMRESET"); 2516 ahci_portp->ahciport_flags &= 2517 ~AHCI_PORT_STATE_SPINUP; 2518 } 2519 } 2520 2521 if (!(ahci_portp->ahciport_flags & AHCI_PORT_STATE_SPINUP)) { 2522 /* Do normal COMRESET */ 2523 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2524 "ahci_port_reset: do normal COMRESET", port); 2525 2526 ASSERT(port_cmd_status & AHCI_CMD_STATUS_SUD); 2527 2528 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2529 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2530 AHCI_SCONTROL_SET_DET(port_scontrol, 2531 AHCI_SCONTROL_DET_COMRESET); 2532 2533 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2534 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 2535 port_scontrol); 2536 2537 /* Enable PxCMD.FRE to read device */ 2538 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2539 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2540 port_cmd_status|AHCI_CMD_STATUS_FRE); 2541 2542 /* give time for COMRESET to percolate */ 2543 #ifndef __lock_lint 2544 delay(AHCI_1MS_TICKS*2); 2545 #endif /* __lock_lint */ 2546 2547 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 2548 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2549 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2550 AHCI_SCONTROL_SET_DET(port_scontrol, 2551 AHCI_SCONTROL_DET_NOACTION); 2552 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2553 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 2554 port_scontrol); 2555 } else { 2556 /* Do staggered spin-up */ 2557 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2558 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2559 AHCI_SCONTROL_SET_DET(port_scontrol, 2560 AHCI_SCONTROL_DET_NOACTION); 2561 2562 /* PxSCTL.DET must be 0 */ 2563 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2564 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 2565 port_scontrol); 2566 2567 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 2568 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2569 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2570 port_cmd_status); 2571 2572 /* 0 -> 1 edge */ 2573 #ifndef __lock_lint 2574 delay(AHCI_1MS_TICKS*2); 2575 #endif /* __lock_lint */ 2576 2577 /* Set PxCMD.SUD to 1 */ 2578 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2579 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2580 port_cmd_status |= AHCI_CMD_STATUS_SUD; 2581 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2582 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2583 port_cmd_status); 2584 2585 /* Enable PxCMD.FRE to read device */ 2586 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2587 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2588 port_cmd_status|AHCI_CMD_STATUS_FRE); 2589 } 2590 2591 /* 2592 * After PxSCTL.DET is set to 0h, software should wait for 2593 * communication to be re-established as indicated by bit 0 2594 * of PxSSTS.DET being set to '1'. 2595 */ 2596 loop_count = 0; 2597 do { 2598 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2599 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 2600 2601 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 2602 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2603 "COMINIT signal is received", port); 2604 /* 2605 * Clear PxSERR.DIAG.X to update PxTFD by the D2H FIS 2606 * received by HBA 2607 */ 2608 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2609 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 2610 AHCI_SERROR_DIAG_X); 2611 } 2612 2613 if (loop_count++ > AHCI_POLLRATE_PORT_COMRESET) { 2614 /* 2615 * We are effectively timing out after 0.1 sec. 2616 */ 2617 break; 2618 } 2619 2620 /* Wait for 10 millisec */ 2621 #ifndef __lock_lint 2622 delay(AHCI_10MS_TICKS); 2623 #endif /* __lock_lint */ 2624 2625 } while (!(port_intr_status & AHCI_INTR_STATUS_PCS)); 2626 2627 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 2628 "ahci_port_reset: 1st loop count: %d, " 2629 "port_intr_status = 0x%x", loop_count, port_intr_status); 2630 2631 /* 2632 * The DET field is valid only if IPM field indicates 2633 * that the interface is in active state. 2634 */ 2635 loop_count = 0; 2636 do { 2637 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2638 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 2639 2640 if (AHCI_SSTATUS_GET_IPM(port_sstatus) != 2641 AHCI_SSTATUS_IPM_INTERFACE_ACTIVE) { 2642 /* 2643 * If the interface is not active, the DET field 2644 * is considered not accurate. So we want to 2645 * continue looping. 2646 */ 2647 AHCI_SSTATUS_SET_DET(port_sstatus, 2648 AHCI_SSTATUS_DET_NODEV_NOPHY); 2649 } 2650 2651 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 2652 /* 2653 * We are effectively timing out after 0.1 sec. 2654 */ 2655 break; 2656 } 2657 2658 /* Wait for 10 millisec */ 2659 #ifndef __lock_lint 2660 delay(AHCI_10MS_TICKS); 2661 #endif /* __lock_lint */ 2662 2663 } while (AHCI_SSTATUS_GET_DET(port_sstatus) != 2664 AHCI_SSTATUS_DET_DEVPRESENT_PHYONLINE); 2665 2666 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 2667 "ahci_port_reset: 2nd loop count: %d, " 2668 "port_sstatus = 0x%x", loop_count, port_sstatus); 2669 2670 if ((AHCI_SSTATUS_GET_IPM(port_sstatus) != 2671 AHCI_SSTATUS_IPM_INTERFACE_ACTIVE) || 2672 (AHCI_SSTATUS_GET_DET(port_sstatus) != 2673 AHCI_SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 2674 /* 2675 * Either the port is not active or there 2676 * is no device present. 2677 */ 2678 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 2679 2680 (void) ahci_port_into_notrunning_state(ahci_ctlp, 2681 ahci_portp, port); 2682 } 2683 2684 if (AHCI_SSTATUS_GET_DET(port_sstatus) == 2685 AHCI_SSTATUS_DET_DEVPRESENT_PHYONLINE) { 2686 /* 2687 * If device exist, then first check PxTFD.STS.BSY 2688 */ 2689 loop_count = 0; 2690 do { 2691 port_task_file = 2692 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2693 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2694 2695 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_BSY) { 2696 /* 2697 * We are effectively timing out after 11 sec. 2698 */ 2699 break; 2700 } 2701 2702 port_intr_status = 2703 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2704 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 2705 2706 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 2707 /* 2708 * Clear PxSERR.DIAG.X to update PxTFD by 2709 * the D2H FIS received by HBA. 2710 */ 2711 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2712 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, 2713 port), AHCI_SERROR_DIAG_X); 2714 } 2715 2716 /* Wait for 10 millisec */ 2717 #ifndef __lock_lint 2718 delay(AHCI_10MS_TICKS); 2719 #endif /* __lock_lint */ 2720 2721 } while (port_task_file & AHCI_TFD_STS_BSY); 2722 2723 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 2724 "ahci_port_reset: 3rd loop count: %d, " 2725 "port_task_file = 0x%x", 2726 loop_count, port_task_file); 2727 2728 /* 2729 * Next check COMRESET is completed successfully 2730 */ 2731 loop_count = 0; 2732 do { 2733 port_task_file = 2734 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2735 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2736 2737 if (((port_task_file & AHCI_TFD_ERR_MASK) 2738 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 2739 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2740 "COMRESET success, D2H register FIS " 2741 "post to received FIS structure"); 2742 break; 2743 } 2744 2745 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 2746 /* 2747 * We are effectively timing out after 0.1 sec. 2748 */ 2749 break; 2750 } 2751 2752 /* Wait for 10 millisec */ 2753 #ifndef __lock_lint 2754 delay(AHCI_10MS_TICKS); 2755 #endif /* __lock_lint */ 2756 2757 } while (((port_task_file & AHCI_TFD_ERR_MASK) 2758 >> AHCI_TFD_ERR_SHIFT) != 0x1); 2759 2760 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 2761 "ahci_port_reset: 4th loop count: %d, " 2762 "port_task_file = 0x%x", 2763 loop_count, port_task_file); 2764 2765 port_signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2766 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 2767 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, "Port %d signature = 0x%x", 2768 port, port_signature); 2769 2770 /* 2771 * Check device status, if keep busy or COMRESET error 2772 * do device reset to patch some SATA disks' issue 2773 * 2774 * For VT8251, sometimes need to do the device reset 2775 */ 2776 if (port_task_file & AHCI_TFD_STS_BSY) { 2777 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "port %d keep busy " 2778 "need to do device reset", port); 2779 2780 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2781 != AHCI_SUCCESS) { 2782 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2783 "port %d device reset failed", port); 2784 return (AHCI_FAILURE); 2785 } 2786 2787 port_task_file = 2788 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2789 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2790 2791 if (port_task_file & AHCI_TFD_STS_BSY) { 2792 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 2793 "port %d keep busy after device reset " 2794 "port_task_file = 0x%x", 2795 port, port_task_file); 2796 return (AHCI_FAILURE); 2797 } 2798 } 2799 } 2800 2801 /* Clear port serror register for each implemented port. */ 2802 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2803 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 2804 AHCI_SERROR_CLEAR_ALL); 2805 2806 return (AHCI_SUCCESS); 2807 } 2808 2809 /* 2810 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 2811 * This is the most intrusive. 2812 * 2813 * When an HBA reset occurs, Phy communication shall 2814 * be re-established with the device through a COMRESET followed by the 2815 * normal out-of-band communication sequence defined in Serial ATA. AT 2816 * the end of reset, the device, if working properly, will send a D2H 2817 * Register FIS, which contains the device signature. When the HBA receives 2818 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 2819 * the PxSIG register with the signature. 2820 * 2821 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 2822 * 2823 * WARNING!!! ahcictl_mutex should be already held before the function 2824 * is called. 2825 */ 2826 static int 2827 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 2828 { 2829 ahci_port_t *ahci_portp; 2830 uint32_t ghc_control; 2831 uint8_t port; 2832 int loop_count; 2833 int rval = AHCI_SUCCESS; 2834 2835 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 2836 2837 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2838 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2839 2840 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 2841 ghc_control |= AHCI_HBA_GHC_HR; 2842 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2843 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 2844 2845 /* 2846 * Wait until HBA Reset complete or timeout 2847 */ 2848 loop_count = 0; 2849 do { 2850 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2851 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2852 2853 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 2854 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2855 "ahci hba reset is timing out, " 2856 "ghc_control = 0x%x", ghc_control); 2857 /* We are effectively timing out after 1 sec. */ 2858 break; 2859 } 2860 2861 /* Wait for 10 millisec */ 2862 #ifndef __lock_lint 2863 delay(AHCI_10MS_TICKS); 2864 #endif /* __lock_lint */ 2865 2866 } while (ghc_control & AHCI_HBA_GHC_HR); 2867 2868 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 2869 "ahci_hba_reset: 1st loop count: %d, " 2870 "ghc_control = 0x%x", loop_count, ghc_control); 2871 2872 if (ghc_control & AHCI_HBA_GHC_HR) { 2873 /* The hba is not reset for some reasons */ 2874 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2875 "hba reset failed: HBA in a hung or locked state"); 2876 return (AHCI_FAILURE); 2877 } 2878 2879 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2880 /* Only check implemented ports */ 2881 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2882 continue; 2883 } 2884 2885 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2886 mutex_enter(&ahci_portp->ahciport_mutex); 2887 2888 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 2889 != AHCI_SUCCESS) { 2890 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2891 rval = AHCI_FAILURE; 2892 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2893 "ahci_hba_reset: port %d failed", port); 2894 } 2895 2896 mutex_exit(&ahci_portp->ahciport_mutex); 2897 } 2898 2899 /* 2900 * Indicate that system software is AHCI aware by setting 2901 * GHC.AE to 1 2902 */ 2903 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2904 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2905 2906 ghc_control |= AHCI_HBA_GHC_AE; 2907 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2908 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 2909 2910 return (rval); 2911 } 2912 2913 /* 2914 * This routine is only called from AHCI_ATTACH or phyrdy change 2915 * case. It first calls port reset to initialize port, probe port and probe 2916 * device, then read PxSIG register to find the type of device attached to 2917 * the port. 2918 * 2919 * WARNING!!! ahciport_mutex should be acquired before the function 2920 * is called. 2921 */ 2922 static int 2923 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 2924 ahci_port_t *ahci_portp, uint8_t port) 2925 { 2926 uint32_t signature; 2927 int ret = AHCI_SUCCESS; 2928 2929 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2930 "port %d: ahci_find_dev_signature enter", port); 2931 2932 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2933 2934 /* Call port reset to check link status and get device signature */ 2935 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 2936 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2937 "ahci_find_dev_signature failed for port %d: ", port); 2938 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2939 return (AHCI_FAILURE); 2940 } 2941 2942 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2943 2944 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2945 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 2946 2947 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 2948 "port %d signature = 0x%x", port, signature); 2949 2950 switch (signature) { 2951 2952 case AHCI_SIGNATURE_DISK: 2953 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 2954 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2955 "Disk is found at port: %d", port); 2956 break; 2957 2958 case AHCI_SIGNATURE_ATAPI: 2959 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 2960 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2961 "ATAPI device is found at port: %d", port); 2962 break; 2963 2964 case AHCI_SIGNATURE_PORT_MULTIPLIER: 2965 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 2966 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2967 "Port Multiplier is found at port: %d", port); 2968 break; 2969 2970 case AHCI_SIGNATURE_NONE: 2971 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 2972 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2973 "No device is found at port: %d", port); 2974 break; 2975 2976 default: 2977 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 2978 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2979 "Unknown device is found at port: %d", port); 2980 } 2981 2982 return (ret); 2983 } 2984 2985 /* 2986 * Try to start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 2987 * to 1, then set it. 2988 * 2989 * WARNING!!! ahciport_mutex should be acquired before the function 2990 * is called. 2991 */ 2992 static int 2993 ahci_start_port(ahci_ctl_t *ahci_ctlp, uint8_t port) 2994 { 2995 uint32_t port_task_file, port_cmd_status; 2996 2997 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2998 "ahci_start_port: %d enter", port); 2999 3000 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3001 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3002 3003 if (port_task_file & AHCI_TFD_STS_BSY || 3004 port_task_file & AHCI_TFD_STS_DRQ) { 3005 3006 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3007 "Port %d cannot start!!! port_task_file = 0x%x", 3008 port, port_task_file); 3009 return (AHCI_FAILURE); 3010 3011 } else { 3012 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3013 "Port %d start!!! port_task_file = 0x%x", 3014 port, port_task_file); 3015 3016 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3017 port_cmd_status = 3018 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3019 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3020 3021 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3022 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3023 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3024 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3025 port_cmd_status); 3026 } 3027 3028 port_cmd_status = 3029 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3030 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3031 3032 port_cmd_status |= AHCI_CMD_STATUS_ST; 3033 3034 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3035 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3036 port_cmd_status); 3037 3038 return (AHCI_SUCCESS); 3039 } 3040 } 3041 3042 /* 3043 * Allocate the ahci_port_t including Received FIS and Command List. 3044 * The argument - port is the physical port number, and not logical 3045 * port number seen by the SATA framework. 3046 * 3047 * WARNING!!! ahcictl_mutex should be acquired before the function 3048 * is called. 3049 */ 3050 static int 3051 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3052 { 3053 ahci_port_t *ahci_portp; 3054 3055 ahci_portp = 3056 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3057 3058 #ifndef __lock_lint 3059 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3060 #endif /* __lock_lint */ 3061 3062 ahci_portp->ahciport_port_num = port; 3063 3064 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3065 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3066 mutex_enter(&ahci_portp->ahciport_mutex); 3067 3068 /* 3069 * Allocate memory for received FIS structure and 3070 * command list for this port 3071 */ 3072 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3073 goto err_case1; 3074 } 3075 3076 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3077 goto err_case2; 3078 } 3079 3080 mutex_exit(&ahci_portp->ahciport_mutex); 3081 3082 return (AHCI_SUCCESS); 3083 3084 err_case2: 3085 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3086 3087 err_case1: 3088 mutex_exit(&ahci_portp->ahciport_mutex); 3089 3090 mutex_destroy(&ahci_portp->ahciport_mutex); 3091 3092 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3093 3094 return (AHCI_FAILURE); 3095 } 3096 3097 /* 3098 * Reverse of ahci_dealloc_port_state(). 3099 * 3100 * WARNING!!! ahcictl_mutex should be acquired before the function 3101 * is called. 3102 */ 3103 static void 3104 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3105 { 3106 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3107 3108 ASSERT(ahci_portp != NULL); 3109 3110 mutex_enter(&ahci_portp->ahciport_mutex); 3111 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3112 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3113 mutex_exit(&ahci_portp->ahciport_mutex); 3114 3115 mutex_destroy(&ahci_portp->ahciport_mutex); 3116 3117 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3118 3119 #ifndef __lock_lint 3120 ahci_ctlp->ahcictl_ports[port] = NULL; 3121 #endif /* __lock_lint */ 3122 } 3123 3124 /* 3125 * Allocates memory for the Received FIS Structure 3126 * 3127 * WARNING!!! ahciport_mutex should be acquired before the function 3128 * is called. 3129 */ 3130 static int 3131 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3132 uint8_t port) 3133 { 3134 size_t rcvd_fis_size; 3135 size_t ret_len; 3136 ddi_dma_cookie_t rcvd_fis_dma_cookie; 3137 uint_t cookie_count; 3138 uint32_t cap_status; 3139 3140 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3141 3142 /* Check whether the HBA can access 64-bit data structures */ 3143 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3144 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3145 3146 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 3147 3148 /* 3149 * If 64-bit addressing is not supported, 3150 * change dma_attr_addr_hi of ahcictl_rcvd_fis_dma_attr 3151 */ 3152 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3153 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3154 "hba does not support 64-bit addressing"); 3155 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 3156 0xffffffffull; 3157 } 3158 3159 /* allocate rcvd FIS dma handle. */ 3160 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3161 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3162 DDI_DMA_SLEEP, 3163 NULL, 3164 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3165 DDI_SUCCESS) { 3166 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3167 "rcvd FIS dma handle alloc failed"); 3168 3169 return (AHCI_FAILURE); 3170 } 3171 3172 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3173 rcvd_fis_size, 3174 &accattr, 3175 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3176 DDI_DMA_SLEEP, 3177 NULL, 3178 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3179 &ret_len, 3180 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3181 3182 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3183 "rcvd FIS dma mem alloc fail"); 3184 /* error.. free the dma handle. */ 3185 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3186 return (AHCI_FAILURE); 3187 } 3188 3189 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3190 NULL, 3191 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3192 rcvd_fis_size, 3193 DDI_DMA_CONSISTENT, 3194 DDI_DMA_SLEEP, 3195 NULL, 3196 &rcvd_fis_dma_cookie, 3197 &cookie_count) != DDI_DMA_MAPPED) { 3198 3199 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3200 "rcvd FIS dma handle bind fail"); 3201 /* error.. free the dma handle & free the memory. */ 3202 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3203 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3204 return (AHCI_FAILURE); 3205 } 3206 3207 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 3208 3209 /* Config Port Received FIS Base Address */ 3210 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3211 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 3212 rcvd_fis_dma_cookie.dmac_laddress); 3213 3214 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3215 rcvd_fis_dma_cookie.dmac_laddress); 3216 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3217 rcvd_fis_dma_cookie.dmac_address); 3218 3219 return (AHCI_SUCCESS); 3220 } 3221 3222 /* 3223 * Deallocates the Received FIS Structure 3224 * 3225 * WARNING!!! ahciport_mutex should be acquired before the function 3226 * is called. 3227 */ 3228 static void 3229 ahci_dealloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3230 { 3231 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3232 "ahci_dealloc_rcvd_fis: port %d enter", 3233 ahci_portp->ahciport_port_num); 3234 3235 /* Unbind the cmd list dma handle first. */ 3236 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 3237 3238 /* Then free the underlying memory. */ 3239 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3240 3241 /* Now free the handle itself. */ 3242 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3243 } 3244 3245 /* 3246 * Allocates memory for the Command List, which contains up to 32 entries. 3247 * Each entry contains a command header, which is a 32-byte structure that 3248 * includes the pointer to the command table. 3249 * 3250 * WARNING!!! ahciport_mutex should be acquired before the function 3251 * is called. 3252 */ 3253 static int 3254 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3255 uint8_t port) 3256 { 3257 size_t cmd_list_size; 3258 size_t ret_len; 3259 ddi_dma_cookie_t cmd_list_dma_cookie; 3260 uint_t cookie_count; 3261 uint32_t cap_status; 3262 3263 cmd_list_size = 3264 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 3265 3266 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3267 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3268 3269 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 3270 3271 /* 3272 * If 64-bit addressing is not supported, 3273 * change dma_attr_addr_hi of ahcictl_cmd_list_dma_attr 3274 */ 3275 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3276 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3277 "hba does not support 64-bit addressing"); 3278 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 3279 0xffffffffull; 3280 } 3281 3282 /* allocate cmd list dma handle. */ 3283 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3284 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 3285 DDI_DMA_SLEEP, 3286 NULL, 3287 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 3288 3289 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3290 "cmd list dma handle alloc failed"); 3291 return (AHCI_FAILURE); 3292 } 3293 3294 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 3295 cmd_list_size, 3296 &accattr, 3297 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3298 DDI_DMA_SLEEP, 3299 NULL, 3300 (caddr_t *)&ahci_portp->ahciport_cmd_list, 3301 &ret_len, 3302 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 3303 3304 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3305 "cmd list dma mem alloc fail"); 3306 /* error.. free the dma handle. */ 3307 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3308 return (AHCI_FAILURE); 3309 } 3310 3311 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 3312 NULL, 3313 (caddr_t)ahci_portp->ahciport_cmd_list, 3314 cmd_list_size, 3315 DDI_DMA_CONSISTENT, 3316 DDI_DMA_SLEEP, 3317 NULL, 3318 &cmd_list_dma_cookie, 3319 &cookie_count) != DDI_DMA_MAPPED) { 3320 3321 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3322 "cmd list dma handle bind fail"); 3323 /* error.. free the dma handle & free the memory. */ 3324 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 3325 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3326 return (AHCI_FAILURE); 3327 } 3328 3329 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 3330 3331 /* Config Port Command List Base Address */ 3332 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3333 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 3334 cmd_list_dma_cookie.dmac_laddress); 3335 3336 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3337 cmd_list_dma_cookie.dmac_laddress); 3338 3339 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3340 cmd_list_dma_cookie.dmac_address); 3341 3342 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 3343 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3344 return (AHCI_FAILURE); 3345 } 3346 3347 return (AHCI_SUCCESS); 3348 } 3349 3350 /* 3351 * Deallocates the Command List 3352 * 3353 * WARNING!!! ahciport_mutex should be acquired before the function 3354 * is called. 3355 */ 3356 static void 3357 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3358 { 3359 /* First dealloc command table */ 3360 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 3361 3362 /* Unbind the cmd list dma handle first. */ 3363 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 3364 3365 /* Then free the underlying memory. */ 3366 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 3367 3368 /* Now free the handle itself. */ 3369 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3370 } 3371 3372 /* 3373 * Allocates memory for all Command Tables, which contains Command FIS, 3374 * ATAPI Command and Physical Region Descriptor Table. 3375 * 3376 * WARNING!!! ahciport_mutex should be acquired before the function 3377 * is called. 3378 */ 3379 static int 3380 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3381 { 3382 size_t ret_len; 3383 ddi_dma_cookie_t cmd_table_dma_cookie; 3384 uint_t cookie_count; 3385 uint32_t cap_status; 3386 int slot; 3387 3388 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3389 "ahci_alloc_cmd_tables: port %d enter", 3390 ahci_portp->ahciport_port_num); 3391 3392 /* Check whether the HBA can access 64-bit data structures */ 3393 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3394 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3395 3396 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 3397 3398 /* 3399 * If 64-bit addressing is not supported, 3400 * change dma_attr_addr_hi of ahcictl_cmd_table_dma_attr 3401 */ 3402 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3403 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3404 "hba does not support 64-bit addressing"); 3405 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 3406 0xffffffffull; 3407 } 3408 3409 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 3410 /* Allocate cmd table dma handle. */ 3411 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3412 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 3413 DDI_DMA_SLEEP, 3414 NULL, 3415 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 3416 DDI_SUCCESS) { 3417 3418 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3419 "cmd table dma handle alloc failed"); 3420 3421 goto err_out; 3422 } 3423 3424 if (ddi_dma_mem_alloc( 3425 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3426 ahci_cmd_table_size, 3427 &accattr, 3428 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3429 DDI_DMA_SLEEP, 3430 NULL, 3431 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 3432 &ret_len, 3433 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 3434 NULL) { 3435 3436 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3437 "cmd table dma mem alloc fail"); 3438 3439 /* error.. free the dma handle. */ 3440 ddi_dma_free_handle( 3441 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3442 goto err_out; 3443 } 3444 3445 if (ddi_dma_addr_bind_handle( 3446 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3447 NULL, 3448 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 3449 ahci_cmd_table_size, 3450 DDI_DMA_CONSISTENT, 3451 DDI_DMA_SLEEP, 3452 NULL, 3453 &cmd_table_dma_cookie, 3454 &cookie_count) != DDI_DMA_MAPPED) { 3455 3456 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3457 "cmd table dma handle bind fail"); 3458 /* error.. free the dma handle & free the memory. */ 3459 ddi_dma_mem_free( 3460 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3461 ddi_dma_free_handle( 3462 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3463 goto err_out; 3464 } 3465 3466 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 3467 ahci_cmd_table_size); 3468 3469 /* Config Port Command Table Base Address */ 3470 SET_COMMAND_TABLE_BASE_ADDR( 3471 (&ahci_portp->ahciport_cmd_list[slot]), 3472 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 3473 3474 #ifndef __lock_lint 3475 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 3476 (&ahci_portp->ahciport_cmd_list[slot]), 3477 cmd_table_dma_cookie.dmac_laddress >> 32); 3478 #endif /* __lock_lint */ 3479 } 3480 3481 return (AHCI_SUCCESS); 3482 err_out: 3483 3484 for (slot--; slot >= 0; slot--) { 3485 /* Unbind the cmd table dma handle first */ 3486 (void) ddi_dma_unbind_handle( 3487 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3488 3489 /* Then free the underlying memory */ 3490 ddi_dma_mem_free( 3491 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3492 3493 /* Now free the handle itself */ 3494 ddi_dma_free_handle( 3495 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3496 } 3497 3498 return (AHCI_FAILURE); 3499 } 3500 3501 /* 3502 * Deallocates memory for all Command Tables. 3503 * 3504 * WARNING!!! ahciport_mutex should be acquired before the function 3505 * is called. 3506 */ 3507 static void 3508 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3509 { 3510 int slot; 3511 3512 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3513 "ahci_dealloc_cmd_tables: %d enter", 3514 ahci_portp->ahciport_port_num); 3515 3516 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 3517 /* Unbind the cmd table dma handle first. */ 3518 (void) ddi_dma_unbind_handle( 3519 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3520 3521 /* Then free the underlying memory. */ 3522 ddi_dma_mem_free( 3523 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3524 3525 /* Now free the handle itself. */ 3526 ddi_dma_free_handle( 3527 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3528 } 3529 } 3530 3531 /* 3532 * WARNING!!! ahciport_mutex should be acquired before the function 3533 * is called. 3534 */ 3535 static void 3536 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 3537 sata_device_t *sd) 3538 { 3539 sd->satadev_scr.sstatus = 3540 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3541 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 3542 sd->satadev_scr.serror = 3543 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3544 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 3545 sd->satadev_scr.scontrol = 3546 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3547 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 3548 sd->satadev_scr.sactive = 3549 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3550 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 3551 } 3552 3553 /* 3554 * Set the auto sense data for ATAPI devices. 3555 * 3556 * Note: Currently the sense data is simulated; this code will be enhanced 3557 * in second phase to fetch the real sense data from the atapi device. 3558 */ 3559 static void 3560 ahci_set_sense_data(sata_pkt_t *satapkt, int reason) 3561 { 3562 struct scsi_extended_sense *sense; 3563 3564 sense = (struct scsi_extended_sense *) 3565 satapkt->satapkt_cmd.satacmd_rqsense; 3566 bzero(sense, sizeof (struct scsi_extended_sense)); 3567 sense->es_valid = 1; /* Valid sense */ 3568 sense->es_class = 7; /* Response code 0x70 - current err */ 3569 sense->es_key = 0; 3570 sense->es_info_1 = 0; 3571 sense->es_info_2 = 0; 3572 sense->es_info_3 = 0; 3573 sense->es_info_4 = 0; 3574 sense->es_add_len = 6; /* Additional length */ 3575 sense->es_cmd_info[0] = 0; 3576 sense->es_cmd_info[1] = 0; 3577 sense->es_cmd_info[2] = 0; 3578 sense->es_cmd_info[3] = 0; 3579 sense->es_add_code = 0; 3580 sense->es_qual_code = 0; 3581 3582 if ((reason == SATA_PKT_DEV_ERROR) || (reason == SATA_PKT_TIMEOUT)) { 3583 sense->es_key = KEY_HARDWARE_ERROR; 3584 } 3585 } 3586 3587 /* 3588 * Interrupt service handler 3589 */ 3590 /* ARGSUSED1 */ 3591 static uint_t 3592 ahci_intr(caddr_t arg1, caddr_t arg2) 3593 { 3594 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 3595 ahci_port_t *ahci_portp; 3596 int32_t global_intr_status, port_intr_status; 3597 int32_t port_intr_enable; 3598 uint8_t port; 3599 3600 /* 3601 * global_intr_status indicates that the corresponding port has 3602 * an interrupt pending. 3603 */ 3604 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3605 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 3606 3607 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 3608 "ahci_intr enter: global_intr_status = 0x%x", global_intr_status); 3609 3610 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 3611 /* The interrupt is not ours */ 3612 return (DDI_INTR_UNCLAIMED); 3613 } 3614 3615 /* Loop for all the ports */ 3616 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3617 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3618 continue; 3619 } 3620 3621 if (!((0x1 << port) & global_intr_status)) { 3622 continue; 3623 } 3624 3625 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3626 3627 /* 3628 * port_intr_stats indicates that the corresponding interrupt 3629 * condition is active. 3630 */ 3631 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3632 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3633 3634 /* 3635 * port_intr_enable indicates that the corresponding interrrupt 3636 * reporting is enabled. 3637 */ 3638 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3639 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 3640 3641 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 3642 "ahci_intr: port %d, port_intr_status = 0x%x, " 3643 "port_intr_enable = 0x%x", port, 3644 port_intr_status, port_intr_enable); 3645 3646 port_intr_status &= port_intr_enable; 3647 3648 /* First clear the port interrupts status */ 3649 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3650 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 3651 port_intr_status); 3652 3653 if (port_intr_status & AHCI_INTR_STATUS_DHRS) { 3654 (void) ahci_intr_d2h_register_fis(ahci_ctlp, ahci_portp, 3655 port); 3656 } 3657 3658 if (port_intr_status & AHCI_INTR_STATUS_PSS) { 3659 (void) ahci_intr_pio_setup_fis(ahci_ctlp, ahci_portp, 3660 port); 3661 } 3662 3663 if (port_intr_status & AHCI_INTR_STATUS_DSS) { 3664 (void) ahci_intr_dma_setup_fis(ahci_ctlp, ahci_portp, 3665 port); 3666 } 3667 3668 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 3669 (void) ahci_intr_set_device_bits_fis(ahci_ctlp, 3670 ahci_portp, port); 3671 } 3672 3673 if (port_intr_status & AHCI_INTR_STATUS_UFS) { 3674 (void) ahci_intr_unknown_fis(ahci_ctlp, ahci_portp, 3675 port); 3676 } 3677 3678 if (port_intr_status & AHCI_INTR_STATUS_DPS) { 3679 (void) ahci_intr_descriptor_processed(ahci_ctlp, 3680 ahci_portp, port); 3681 } 3682 3683 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 3684 (void) ahci_intr_port_connect_change(ahci_ctlp, 3685 ahci_portp, port); 3686 } 3687 3688 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 3689 (void) ahci_intr_device_mechanical_presence_status( 3690 ahci_ctlp, ahci_portp, port); 3691 } 3692 3693 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 3694 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 3695 port); 3696 } 3697 3698 if (port_intr_status & AHCI_INTR_STATUS_IPMS) { 3699 (void) ahci_intr_incorrect_port_multiplier(ahci_ctlp, 3700 ahci_portp, port); 3701 } 3702 3703 if (port_intr_status & AHCI_INTR_STATUS_OFS) { 3704 (void) ahci_intr_overflow(ahci_ctlp, ahci_portp, port); 3705 } 3706 3707 if (port_intr_status & AHCI_INTR_STATUS_INFS) { 3708 (void) ahci_intr_interface_non_fatal_error(ahci_ctlp, 3709 ahci_portp, port); 3710 } 3711 3712 if (port_intr_status & AHCI_INTR_STATUS_IFS) { 3713 (void) ahci_intr_interface_fatal_error(ahci_ctlp, 3714 ahci_portp, port); 3715 } 3716 3717 if (port_intr_status & AHCI_INTR_STATUS_HBDS) { 3718 (void) ahci_intr_host_bus_data_error(ahci_ctlp, 3719 ahci_portp, port); 3720 } 3721 3722 if (port_intr_status & AHCI_INTR_STATUS_HBFS) { 3723 (void) ahci_intr_host_bus_fatal_error(ahci_ctlp, 3724 ahci_portp, port); 3725 } 3726 3727 if (port_intr_status & AHCI_INTR_STATUS_TFES) { 3728 (void) ahci_intr_task_file_error(ahci_ctlp, ahci_portp, 3729 port); 3730 } 3731 3732 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 3733 (void) ahci_intr_cold_port_detect(ahci_ctlp, 3734 ahci_portp, port); 3735 } 3736 3737 /* Second clear the corresponding bit in IS.IPS */ 3738 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3739 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 3740 } 3741 3742 return (DDI_INTR_CLAIMED); 3743 } 3744 3745 /* 3746 * A D2H Register FIS has been received with the 'I' bit set. 3747 * 3748 * The following commands will send this FIS upon the successful completion: 3749 * 1. Non-data commands 3750 * 2. DMA data-in command 3751 * 3. DMA data-out command 3752 * 4. PIO data-out command 3753 */ 3754 static int 3755 ahci_intr_d2h_register_fis(ahci_ctl_t *ahci_ctlp, 3756 ahci_port_t *ahci_portp, uint8_t port) 3757 { 3758 uint32_t port_cmd_issue; 3759 uint32_t finished_tags; 3760 int finished_slot, i, num = 0; 3761 sata_pkt_t *satapkt; 3762 ahci_fis_d2h_register_t *rcvd_fisp; 3763 3764 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 3765 "ahci_intr_d2h_register_fis enter, port %d", port); 3766 3767 mutex_enter(&ahci_portp->ahciport_mutex); 3768 3769 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3770 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3771 3772 if (!ahci_portp->ahciport_pending_tags) { 3773 /* 3774 * Spurious interrupt. Nothing to be done. 3775 */ 3776 mutex_exit(&ahci_portp->ahciport_mutex); 3777 return (AHCI_SUCCESS); 3778 } 3779 3780 finished_tags = ahci_portp->ahciport_pending_tags & 3781 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 3782 3783 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 3784 "ahci_intr_d2h_reigster_fis: pending_tags = 0x%x, " 3785 "port_cmd_issue = 0x%x, finished_tags = 0x%x,", 3786 ahci_portp->ahciport_pending_tags, port_cmd_issue, 3787 finished_tags); 3788 3789 for (i = 0; i < ahci_ctlp->ahcictl_num_cmd_slots; i++) { 3790 if ((0x1 << i) & finished_tags) 3791 num++; 3792 } 3793 3794 ASSERT(num <= 1); 3795 3796 finished_slot = ddi_ffs(finished_tags) - 1; 3797 if (finished_slot == -1) { 3798 goto out; 3799 } 3800 3801 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 3802 ASSERT(satapkt != NULL); 3803 3804 /* 3805 * In case the interrupt generates before disabling for poll commands. 3806 */ 3807 if (satapkt->satapkt_op_mode & 3808 (SATA_OPMODE_POLLING | SATA_OPMODE_SYNCH)) { 3809 goto out; 3810 } 3811 3812 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis->ahcirf_d2h_register_fis); 3813 3814 /* Return the status */ 3815 satapkt->satapkt_cmd.satacmd_status_reg = GET_RFIS_STATUS(rcvd_fisp); 3816 3817 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 3818 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 3819 3820 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 3821 "ahci_intr_d2h_register_fis: sending up pkt 0x%p " 3822 "with SATA_PKT_COMPLETED", (void *)satapkt); 3823 3824 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 3825 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 3826 3827 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 3828 out: 3829 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 3830 "ahci_intr_d2h_register_fis pending_tags = 0x%x", 3831 ahci_portp->ahciport_pending_tags); 3832 3833 mutex_exit(&ahci_portp->ahciport_mutex); 3834 3835 return (AHCI_SUCCESS); 3836 } 3837 3838 /* 3839 * A PIO Setup FIS has been received with the 'I' bit set. 3840 * 3841 * The following commands will send this FIS upon the successful completion: 3842 * PIO data-in command 3843 */ 3844 static int 3845 ahci_intr_pio_setup_fis(ahci_ctl_t *ahci_ctlp, 3846 ahci_port_t *ahci_portp, uint8_t port) 3847 { 3848 uint32_t port_cmd_issue; 3849 uint32_t finished_tags; 3850 int finished_slot, i, num = 0; 3851 sata_pkt_t *satapkt; 3852 ahci_fis_d2h_register_t *rcvd_fisp; 3853 3854 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 3855 "ahci_intr_pio_setup_fis enter, port %d", port); 3856 3857 mutex_enter(&ahci_portp->ahciport_mutex); 3858 3859 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3860 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3861 3862 if (!ahci_portp->ahciport_pending_tags) { 3863 /* 3864 * Spurious interrupt. Nothing to be done. 3865 */ 3866 mutex_exit(&ahci_portp->ahciport_mutex); 3867 return (AHCI_SUCCESS); 3868 } 3869 3870 finished_tags = ahci_portp->ahciport_pending_tags & 3871 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 3872 3873 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 3874 "ahci_intr_pio_setup_fis: pending_tags = 0x%x, " 3875 "port_cmd_issue = 0x%x, finished_tags = 0x%x,", 3876 ahci_portp->ahciport_pending_tags, port_cmd_issue, 3877 finished_tags); 3878 3879 for (i = 0; i < ahci_ctlp->ahcictl_num_cmd_slots; i++) { 3880 if ((0x1 << i) & finished_tags) 3881 num++; 3882 } 3883 3884 ASSERT(num <= 1); 3885 3886 finished_slot = ddi_ffs(finished_tags) - 1; 3887 if (finished_slot == -1) { 3888 goto out; 3889 } 3890 3891 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 3892 ASSERT(satapkt != NULL); 3893 3894 /* 3895 * In case the interrupt generates before disabling. 3896 */ 3897 if (satapkt->satapkt_op_mode & 3898 (SATA_OPMODE_POLLING | SATA_OPMODE_SYNCH)) { 3899 goto out; 3900 } 3901 3902 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis->ahcirf_d2h_register_fis); 3903 3904 /* Return the status */ 3905 satapkt->satapkt_cmd.satacmd_status_reg = GET_RFIS_STATUS(rcvd_fisp); 3906 3907 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 3908 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 3909 3910 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 3911 "ahci_intr_pio_setup_fis: sending up pkt 0x%p " 3912 "with SATA_PKT_COMPLETED", (void *)satapkt); 3913 3914 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 3915 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 3916 3917 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 3918 out: 3919 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 3920 "ahci_intr_pio_setup_fis pending_tags = 0x%x", 3921 ahci_portp->ahciport_pending_tags); 3922 3923 mutex_exit(&ahci_portp->ahciport_mutex); 3924 3925 return (AHCI_SUCCESS); 3926 } 3927 3928 /* 3929 * A DMA Setup FIS has been received with the 'I' bit set 3930 * 3931 * DMA Setup FIS will be used during NCQ transfers to activate data 3932 * transfer. 3933 * 3934 * For the first phase, this interrupt is disabled and we just 3935 * log a debug message. 3936 */ 3937 /* ARGSUSED */ 3938 static int 3939 ahci_intr_dma_setup_fis(ahci_ctl_t *ahci_ctlp, 3940 ahci_port_t *ahci_portp, uint8_t port) 3941 { 3942 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 3943 "ahci_intr_dma_setup_fis enter, port %d", port); 3944 3945 return (AHCI_SUCCESS); 3946 } 3947 3948 /* 3949 * A Set Device Bits FIS has been received with the 'I' bit set 3950 * 3951 * Set Device Bits FIS will be sent during NCQ completion. 3952 * 3953 * For the first phase, this interrupt is disabled and we just log 3954 * the debug message. 3955 */ 3956 /* ARGSUSED */ 3957 static int 3958 ahci_intr_set_device_bits_fis(ahci_ctl_t *ahci_ctlp, 3959 ahci_port_t *ahci_portp, uint8_t port) 3960 { 3961 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 3962 "ahci_intr_set_device_bits_fis enter, port %d", port); 3963 3964 return (AHCI_SUCCESS); 3965 } 3966 3967 /* 3968 * An unknown FIS was received and has been copied into system memory. 3969 * 3970 * An unknown FIS is not considered an illegal FIS, unless the length 3971 * received is more than 64 bytes. If an unknown FIS arrives with length 3972 * <= 64 bytes, it is posted and the HBA continues normal operation. 3973 * 3974 * Therefore we just need to clear PxSERR.DIAG.F to clear the intr bit 3975 * and log the debug message. 3976 */ 3977 static int 3978 ahci_intr_unknown_fis(ahci_ctl_t *ahci_ctlp, 3979 ahci_port_t *ahci_portp, uint8_t port) 3980 { 3981 uint32_t port_serror; 3982 3983 mutex_enter(&ahci_portp->ahciport_mutex); 3984 3985 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3986 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 3987 3988 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 3989 "ahci_intr_unknown_fis: port %d, port_serror = 0x%x", 3990 port, port_serror); 3991 3992 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 3993 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3994 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3995 AHCI_SERROR_DIAG_F); 3996 3997 mutex_exit(&ahci_portp->ahciport_mutex); 3998 3999 return (AHCI_SUCCESS); 4000 } 4001 4002 /* 4003 * A PRD with the 'I' bit set has tranfered all of its data. 4004 * 4005 * The PRD Interrupt is an opportunistic interrupt. And it should not 4006 * be used to definitively indicate the end of a transfer since two 4007 * PRD interrupts could happen close in time together such that the 4008 * second interrupt is missed when the first PRD interrupt is being 4009 * cleared. 4010 * 4011 * For the first phase, this interrupt is disabled and we just 4012 * log the debug message. 4013 */ 4014 /* ARGSUSED */ 4015 static int 4016 ahci_intr_descriptor_processed(ahci_ctl_t *ahci_ctlp, 4017 ahci_port_t *ahci_portp, uint8_t port) 4018 { 4019 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4020 "ahci_intr_descriptor_processed enter, port %d", port); 4021 4022 return (AHCI_SUCCESS); 4023 } 4024 4025 /* 4026 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4027 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4028 * when PxSERR.DIAG.X is cleared. 4029 * 4030 * When PxSERR.DIAG.X is set to one, it indicates a COMINIT signal was received. 4031 * 4032 * For the first phase, this interrupt is disabled. 4033 */ 4034 static int 4035 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4036 ahci_port_t *ahci_portp, uint8_t port) 4037 { 4038 uint32_t port_serror, port_cmd_status; 4039 4040 mutex_enter(&ahci_portp->ahciport_mutex); 4041 4042 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4043 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4044 4045 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4046 "ahci_intr_port_connect_change: port %d, " 4047 "port_serror = 0x%x", port, port_serror); 4048 4049 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4050 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4051 4052 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4053 "ahci_intr_port_connect_change: port %d, " 4054 "port_command_status = 0x%x", port, port_cmd_status); 4055 4056 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4057 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4058 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4059 AHCI_SERROR_DIAG_X); 4060 4061 mutex_exit(&ahci_portp->ahciport_mutex); 4062 4063 return (AHCI_SUCCESS); 4064 } 4065 4066 /* 4067 * Hot Plug Operation for platforms that support Mechanical Presence 4068 * Switches. 4069 * 4070 * When set, it indicates that a mechanical presence switch attached to this 4071 * port has been opened or closed, which may lead to a change in the connection 4072 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4073 * are set to '1'. 4074 * 4075 * For the first phase, this interrupt is disabled and we just log 4076 * the debug message. 4077 */ 4078 /* ARGSUSED */ 4079 static int 4080 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4081 ahci_port_t *ahci_portp, uint8_t port) 4082 { 4083 uint32_t cap_status, port_cmd_status; 4084 4085 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4086 "ahci_intr_device_mechanical_presence_status enter, " 4087 "port %d", port); 4088 4089 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4090 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4091 4092 mutex_enter(&ahci_portp->ahciport_mutex); 4093 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4094 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4095 4096 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4097 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4098 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4099 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4100 "the interrupt: cap_status = 0x%x, " 4101 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4102 mutex_exit(&ahci_portp->ahciport_mutex); 4103 4104 return (AHCI_SUCCESS); 4105 } 4106 4107 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4108 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4109 "The mechanical presence switch is open: " 4110 "port %d, port_cmd_status = 0x%x", 4111 port, port_cmd_status); 4112 } else { 4113 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4114 "The mechanical presence switch is close: " 4115 "port %d, port_cmd_status = 0x%x", 4116 port, port_cmd_status); 4117 } 4118 4119 mutex_exit(&ahci_portp->ahciport_mutex); 4120 4121 return (AHCI_SUCCESS); 4122 } 4123 4124 /* 4125 * Native Hot Plug Support. 4126 * 4127 * When set, it indicates that the internal PHYRDY signal changed state. 4128 * This bit reflects the state of PxSERR.DIAG.N. 4129 */ 4130 static int 4131 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4132 ahci_port_t *ahci_portp, uint8_t port) 4133 { 4134 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4135 sata_device_t sdevice; 4136 int dev_exists_now = 0; 4137 int dev_existed_previously = 0; 4138 4139 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4140 "ahci_intr_phyrdy_change enter, port %d", port); 4141 4142 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4143 mutex_enter(&ahci_portp->ahciport_mutex); 4144 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4145 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4146 AHCI_SERROR_DIAG_N); 4147 mutex_exit(&ahci_portp->ahciport_mutex); 4148 4149 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4150 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4151 (ahci_portp == NULL)) { 4152 /* The whole controller setup is not yet done. */ 4153 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4154 return (AHCI_SUCCESS); 4155 } 4156 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4157 4158 mutex_enter(&ahci_portp->ahciport_mutex); 4159 4160 /* SStatus tells the presence of device. */ 4161 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4162 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4163 4164 dev_exists_now = (AHCI_SSTATUS_GET_DET(port_sstatus) == 4165 AHCI_SSTATUS_DET_DEVPRESENT_PHYONLINE); 4166 4167 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4168 dev_existed_previously = 1; 4169 } 4170 4171 bzero((void *)&sdevice, sizeof (sata_device_t)); 4172 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4173 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4174 sdevice.satadev_addr.pmport = 0; 4175 sdevice.satadev_state = SATA_PSTATE_PWRON; 4176 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4177 4178 if (dev_exists_now) { 4179 if (dev_existed_previously) { 4180 /* Things are fine now. The loss was temporary. */ 4181 cmn_err(CE_NOTE, "!ahci phyrdy: port %d " 4182 "device link lost/established", port); 4183 4184 mutex_exit(&ahci_portp->ahciport_mutex); 4185 sata_hba_event_notify( 4186 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4187 &sdevice, 4188 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4189 mutex_enter(&ahci_portp->ahciport_mutex); 4190 4191 } else { 4192 cmn_err(CE_NOTE, "!ahci phyrdy: port %d " 4193 "device link established", port); 4194 4195 /* A new device has been detected. */ 4196 if (ahci_find_dev_signature(ahci_ctlp, ahci_portp, port) 4197 != AHCI_SUCCESS) { 4198 ahci_portp->ahciport_port_state = 4199 SATA_PSTATE_FAILED; 4200 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4201 "phyrdy: port %d failed " 4202 "at find dev signature", port); 4203 } 4204 4205 if ((ahci_portp->ahciport_device_type 4206 == SATA_DTYPE_ATADISK) && 4207 (ahci_start_port(ahci_ctlp, port) 4208 != AHCI_SUCCESS)) { 4209 ahci_portp->ahciport_port_state = 4210 SATA_PSTATE_FAILED; 4211 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4212 "phyrdy: port %d failed " 4213 "at start port", port); 4214 } 4215 4216 mutex_exit(&ahci_portp->ahciport_mutex); 4217 sata_hba_event_notify( 4218 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4219 &sdevice, 4220 SATA_EVNT_LINK_ESTABLISHED); 4221 mutex_enter(&ahci_portp->ahciport_mutex); 4222 4223 } 4224 } else { /* No device exists now */ 4225 4226 if (dev_existed_previously) { 4227 4228 cmn_err(CE_NOTE, "!ahci phyrdy: port %d " 4229 "device link lost", port); 4230 4231 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 4232 (void) ahci_port_into_notrunning_state(ahci_ctlp, 4233 ahci_portp, port); 4234 4235 /* An existing device is lost. */ 4236 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 4237 4238 mutex_exit(&ahci_portp->ahciport_mutex); 4239 sata_hba_event_notify( 4240 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4241 &sdevice, 4242 SATA_EVNT_LINK_LOST); 4243 mutex_enter(&ahci_portp->ahciport_mutex); 4244 4245 } else { 4246 4247 /* Spurious interrupt */ 4248 AHCIDBG0(AHCIDBG_INTR, ahci_ctlp, 4249 "spurious phy ready interrupt"); 4250 } 4251 } 4252 4253 mutex_exit(&ahci_portp->ahciport_mutex); 4254 4255 return (AHCI_SUCCESS); 4256 } 4257 4258 /* 4259 * PxIS.IPMS - Port Multiplier Errors. 4260 * 4261 * Which indicates that the HBA received a FIS from a device whose Port 4262 * Multiplier field did not match what was expected. 4263 * 4264 * For the first phase, this interrupt is disabled, and we just log 4265 * the debug message. 4266 */ 4267 /* ARGSUSED */ 4268 static int 4269 ahci_intr_incorrect_port_multiplier(ahci_ctl_t *ahci_ctlp, 4270 ahci_port_t *ahci_portp, uint8_t port) 4271 { 4272 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4273 "ahci_intr_incorrect_port_multiplier enter, port %d", port); 4274 4275 return (AHCI_SUCCESS); 4276 } 4277 4278 /* 4279 * PxIS.OFS - Fatal Error 4280 * 4281 * Which indicates that the HBA received more bytes from a device than 4282 * was specified in the PRD table for the command. 4283 * 4284 * Overflow is a serious error, thus software should perform a fatal error 4285 * recovery procedure to ensure that the HBA is brought back to a known 4286 * condition before continuing. 4287 */ 4288 static int 4289 ahci_intr_overflow(ahci_ctl_t *ahci_ctlp, 4290 ahci_port_t *ahci_portp, uint8_t port) 4291 { 4292 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4293 "ahci_intr_overflow enter, port %d", port); 4294 4295 mutex_enter(&ahci_portp->ahciport_mutex); 4296 4297 cmn_err(CE_NOTE, "!ahci port %d has overflow error", port); 4298 4299 (void) ahci_recovery_fatal_error(ahci_ctlp, ahci_portp, 4300 port, AHCI_INTR_STATUS_OFS); 4301 4302 mutex_exit(&ahci_portp->ahciport_mutex); 4303 4304 return (AHCI_SUCCESS); 4305 } 4306 4307 /* 4308 * PxIS.IFS and PxIS.INFS are errors that occur due to eletrical issues 4309 * on the interface, or protocol miscommunication between the device 4310 * and HBA. 4311 * 4312 * The conditions that causes PxIS.IFS/PxIS.INFS to be set are 4313 * 1. in PxSERR.ERR, P bit is set to '1' 4314 * 2. in PxSERR.DIAG, C or H bit is set to '1' 4315 * 3. PhyRdy drop unexpectly, N bit is set to '1' 4316 */ 4317 /* 4318 * PxIS.INFS - Interface Error 4319 * 4320 * Which indicates that the HBA encountered an error on the Serial ATA interface 4321 * but was able to continue operation. It's non-fatal error, so we just log 4322 * the debug message. 4323 * 4324 * The error occurred during a non-Data FIS, and the FIS will be 4325 * re-transmitted by HBA automatically. 4326 */ 4327 static int 4328 ahci_intr_interface_non_fatal_error(ahci_ctl_t *ahci_ctlp, 4329 ahci_port_t *ahci_portp, uint8_t port) 4330 { 4331 sata_pkt_t *satapkt; 4332 uint32_t port_serror; 4333 uint32_t port_cmd_status; 4334 int current_slot; 4335 4336 mutex_enter(&ahci_portp->ahciport_mutex); 4337 4338 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4339 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4340 4341 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4342 "ahci_intr_interface_non_fatal_error: port %d, " 4343 "port_serror = 0x%x", port, port_serror); 4344 4345 ahci_log_error_message(ahci_ctlp, port, port_serror); 4346 4347 cmn_err(CE_NOTE, "!ahci port %d has interface non fatal error", port); 4348 4349 /* 4350 * Record the error occurred command's slot. 4351 */ 4352 #if AHCI_DEBUG 4353 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4354 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4355 4356 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 4357 AHCI_CMD_STATUS_CCS_SHIFT; 4358 4359 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 4360 4361 if (satapkt != NULL) { 4362 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4363 "ahci_intr_interface_non_fatal_error: " 4364 "pending_tags= 0x%x ", 4365 ahci_portp->ahciport_pending_tags); 4366 4367 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4368 "ahci_intr_interface_non_fatal_error: cmd= 0x%x ", 4369 satapkt->satapkt_cmd.satacmd_cmd_reg); 4370 4371 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4372 "ahci_intr_interface_non_fatal_error: port %d, " 4373 "satapkt = %p will be re-transmitted", 4374 port, (void *)satapkt); 4375 } 4376 #endif 4377 mutex_exit(&ahci_portp->ahciport_mutex); 4378 4379 return (AHCI_SUCCESS); 4380 } 4381 4382 /* 4383 * PxIS.IFS - Interface Error and Fatal Error 4384 * 4385 * Which indicates that the HBA encountered an error on the Serial ATA interface 4386 * which caused the transfer to stop. 4387 * 4388 * The error occurred during a Data FIS, the transfer shall stop. 4389 */ 4390 static int 4391 ahci_intr_interface_fatal_error(ahci_ctl_t *ahci_ctlp, 4392 ahci_port_t *ahci_portp, uint8_t port) 4393 { 4394 uint32_t port_serror; 4395 4396 mutex_enter(&ahci_portp->ahciport_mutex); 4397 4398 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4399 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4400 4401 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4402 "ahci_intr_interface_fatal_error: port %d, " 4403 "port_serror = 0x%x", port, port_serror); 4404 4405 ahci_log_error_message(ahci_ctlp, port, port_serror); 4406 4407 cmn_err(CE_NOTE, "!ahci port %d has interface fatal error", port); 4408 4409 (void) ahci_recovery_fatal_error(ahci_ctlp, ahci_portp, 4410 port, AHCI_INTR_STATUS_IFS); 4411 4412 mutex_exit(&ahci_portp->ahciport_mutex); 4413 4414 return (AHCI_SUCCESS); 4415 } 4416 4417 /* 4418 * PxIS.HBDS - System Memory Error and Fatal Error 4419 * 4420 * Which indicates that the HBA encountered a data error 4421 * (uncorrectable ECC/parity) when reading from or writing to system memory. 4422 */ 4423 static int 4424 ahci_intr_host_bus_data_error(ahci_ctl_t *ahci_ctlp, 4425 ahci_port_t *ahci_portp, uint8_t port) 4426 { 4427 uint32_t port_serror; 4428 4429 mutex_enter(&ahci_portp->ahciport_mutex); 4430 4431 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4432 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4433 4434 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4435 "ahci_intr_host_bus_data_error: port %d, " 4436 "port_serror = 0x%x", port, port_serror); 4437 4438 ahci_log_error_message(ahci_ctlp, port, port_serror); 4439 4440 cmn_err(CE_NOTE, "!ahci port %d has bus data error", port); 4441 4442 (void) ahci_recovery_fatal_error(ahci_ctlp, ahci_portp, 4443 port, AHCI_INTR_STATUS_HBDS); 4444 4445 mutex_exit(&ahci_portp->ahciport_mutex); 4446 4447 return (AHCI_SUCCESS); 4448 } 4449 4450 /* 4451 * PxIS.HBFS - System Memory Error and Fatal Error 4452 * 4453 * Which indicates that the HBA encountered a host bus error that it cannot 4454 * recover from, such as a bad software pointer. 4455 */ 4456 static int 4457 ahci_intr_host_bus_fatal_error(ahci_ctl_t *ahci_ctlp, 4458 ahci_port_t *ahci_portp, uint8_t port) 4459 { 4460 uint32_t port_serror; 4461 4462 mutex_enter(&ahci_portp->ahciport_mutex); 4463 4464 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4465 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4466 4467 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4468 "ahci_intr_host_bus_fatal_error: port %d, " 4469 "port_serror = 0x%x", port, port_serror); 4470 4471 ahci_log_error_message(ahci_ctlp, port, port_serror); 4472 4473 cmn_err(CE_NOTE, "!ahci port %d has bus fatal error", port); 4474 4475 (void) ahci_recovery_fatal_error(ahci_ctlp, ahci_portp, 4476 port, AHCI_INTR_STATUS_HBFS); 4477 4478 mutex_exit(&ahci_portp->ahciport_mutex); 4479 4480 return (AHCI_SUCCESS); 4481 } 4482 4483 /* 4484 * PxIS.TFES - Device Error and Fatal Error 4485 * 4486 * This bit is set whenever the status register is updated by the device 4487 * and the error bit (bit 0) is set. 4488 */ 4489 static int 4490 ahci_intr_task_file_error(ahci_ctl_t *ahci_ctlp, 4491 ahci_port_t *ahci_portp, uint8_t port) 4492 { 4493 uint32_t task_file_status; 4494 4495 mutex_enter(&ahci_portp->ahciport_mutex); 4496 4497 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4498 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 4499 4500 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4501 "ahci_intr_task_file_error: port %d: " 4502 "task_file_status = 0x%x", port, task_file_status); 4503 4504 cmn_err(CE_NOTE, "!ahci port %d has task file error", port); 4505 4506 (void) ahci_recovery_fatal_error(ahci_ctlp, ahci_portp, 4507 port, AHCI_INTR_STATUS_TFES); 4508 4509 mutex_exit(&ahci_portp->ahciport_mutex); 4510 4511 return (AHCI_SUCCESS); 4512 } 4513 4514 /* 4515 * Hot Plug Operation for platforms that support Cold Presence Detect. 4516 * 4517 * When set, a device status has changed as detected by the cold presence 4518 * detect logic. This bit can either be set due to a non-connected port 4519 * receiving a device, or a connected port having its device removed. 4520 * This bit is only valid if the port supports cold presence detect as 4521 * indicated by PxCMD.CPD set to '1'. 4522 * 4523 * For the first phase, this interrupt is disabled and we just log 4524 * the debug message. 4525 */ 4526 /* ARGSUSED */ 4527 static int 4528 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 4529 ahci_port_t *ahci_portp, uint8_t port) 4530 { 4531 uint32_t port_cmd_status; 4532 sata_device_t sdevice; 4533 4534 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4535 "ahci_intr_cold_port_detect enter, port %d", port); 4536 4537 mutex_enter(&ahci_portp->ahciport_mutex); 4538 4539 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4540 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4541 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 4542 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4543 "port %d does not support cold presence detect, so " 4544 "we just ignore this interrupt", port); 4545 mutex_exit(&ahci_portp->ahciport_mutex); 4546 return (AHCI_SUCCESS); 4547 } 4548 4549 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4550 "port %d device status has changed", port); 4551 4552 bzero((void *)&sdevice, sizeof (sata_device_t)); 4553 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4554 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4555 sdevice.satadev_addr.pmport = 0; 4556 sdevice.satadev_state = SATA_PSTATE_PWRON; 4557 4558 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 4559 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4560 "port %d: a device is hot plugged", port); 4561 mutex_exit(&ahci_portp->ahciport_mutex); 4562 sata_hba_event_notify( 4563 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4564 &sdevice, 4565 SATA_EVNT_DEVICE_ATTACHED); 4566 mutex_enter(&ahci_portp->ahciport_mutex); 4567 4568 } else { 4569 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4570 "port %d: a device is hot unplugged", port); 4571 mutex_exit(&ahci_portp->ahciport_mutex); 4572 sata_hba_event_notify( 4573 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4574 &sdevice, 4575 SATA_EVNT_DEVICE_DETACHED); 4576 mutex_enter(&ahci_portp->ahciport_mutex); 4577 } 4578 4579 mutex_exit(&ahci_portp->ahciport_mutex); 4580 4581 return (AHCI_SUCCESS); 4582 } 4583 4584 /* 4585 * Enable the interrupts for a particular port. 4586 * 4587 * WARNING!!! ahciport_mutex should be acquired before the function 4588 * is called. 4589 */ 4590 /* ARGSUSED */ 4591 static void 4592 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, 4593 ahci_port_t *ahci_portp, uint8_t port) 4594 { 4595 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4596 "ahci_enable_port_intrs enter, port %d", port); 4597 4598 /* 4599 * Clear port interrupt status before enabling interrupt 4600 */ 4601 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4602 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4603 AHCI_PORT_INTR_MASK); 4604 4605 /* 4606 * Clear the pending bit from IS.IPS 4607 */ 4608 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4609 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 4610 4611 /* 4612 * Enable the following interrupts: 4613 * Device to Host Register FIS Interrupt (DHRS) 4614 * PIO Setup FIS Interrupt (PSS) 4615 * Unknown FIS Interrupt (UFS) 4616 * Port Connect Change Status (PCS) 4617 * PhyRdy Change Status (PRCS) 4618 * Overflow Status (OFS) 4619 * Interface Non-fatal Error Status (INFS) 4620 * Interface Fatal Error Status (IFS) 4621 * Host Bus Data Error Status (HBDS) 4622 * Host Bus Fatal Error Status (HBFS) 4623 * Task File Error Status (TFES) 4624 */ 4625 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4626 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 4627 (AHCI_INTR_STATUS_DHRS | 4628 AHCI_INTR_STATUS_PSS | 4629 AHCI_INTR_STATUS_UFS | 4630 AHCI_INTR_STATUS_PCS | 4631 AHCI_INTR_STATUS_PRCS | 4632 AHCI_INTR_STATUS_OFS | 4633 AHCI_INTR_STATUS_INFS | 4634 AHCI_INTR_STATUS_IFS | 4635 AHCI_INTR_STATUS_HBDS | 4636 AHCI_INTR_STATUS_HBFS | 4637 AHCI_INTR_STATUS_TFES)); 4638 } 4639 4640 /* 4641 * Enable interrupts for all the ports. 4642 * 4643 * WARNING!!! ahcictl_mutex should be acquired before the function 4644 * is called. 4645 */ 4646 static void 4647 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 4648 { 4649 uint32_t ghc_control; 4650 4651 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 4652 4653 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4654 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 4655 4656 ghc_control |= AHCI_HBA_GHC_IE; 4657 4658 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4659 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 4660 } 4661 4662 /* 4663 * Disable interrupts for a particular port. 4664 * 4665 * WARNING!!! ahciport_mutex should be acquired before the function 4666 * is called. 4667 */ 4668 /* ARGSUSED */ 4669 static void 4670 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, 4671 ahci_port_t *ahci_portp, uint8_t port) 4672 { 4673 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4674 "ahci_disable_port_intrs enter, port %d", port); 4675 4676 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4677 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 4678 } 4679 4680 /* 4681 * Disable interrupts for the whole HBA. 4682 * 4683 * The global bit is cleared, then all interrupt sources from all 4684 * ports are disabled. 4685 * 4686 * WARNING!!! ahcictl_mutex should be acquired before the function 4687 * is called. 4688 */ 4689 static void 4690 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 4691 { 4692 uint32_t ghc_control; 4693 4694 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 4695 4696 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4697 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 4698 4699 ghc_control &= ~ AHCI_HBA_GHC_IE; 4700 4701 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4702 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 4703 } 4704 4705 /* 4706 * Handle INTx and legacy interrupts. 4707 */ 4708 static int 4709 ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 4710 { 4711 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 4712 int actual, count = 0; 4713 int x, y, rc, inum = 0; 4714 4715 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 4716 "ahci_add_legacy_intrs enter"); 4717 4718 /* get number of interrupts. */ 4719 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 4720 if ((rc != DDI_SUCCESS) || (count == 0)) { 4721 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4722 "ddi_intr_get_nintrs() failed, " 4723 "rc %d count %d\n", rc, count); 4724 return (DDI_FAILURE); 4725 } 4726 4727 /* Allocate an array of interrupt handles. */ 4728 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 4729 ahci_ctlp->ahcictl_intr_htable = 4730 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 4731 4732 /* call ddi_intr_alloc(). */ 4733 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 4734 DDI_INTR_TYPE_FIXED, 4735 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 4736 4737 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4738 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4739 "ddi_intr_alloc() failed, rc %d\n", rc); 4740 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4741 ahci_ctlp->ahcictl_intr_size); 4742 return (DDI_FAILURE); 4743 } 4744 4745 if (actual < count) { 4746 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4747 "Requested: %d, Received: %d", count, actual); 4748 4749 for (x = 0; x < actual; x++) { 4750 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 4751 } 4752 4753 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4754 ahci_ctlp->ahcictl_intr_size); 4755 return (DDI_FAILURE); 4756 } 4757 4758 ahci_ctlp->ahcictl_intr_cnt = actual; 4759 4760 /* Get intr priority. */ 4761 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 4762 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 4763 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4764 "ddi_intr_get_pri() failed"); 4765 4766 for (x = 0; x < actual; x++) { 4767 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 4768 } 4769 4770 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4771 ahci_ctlp->ahcictl_intr_size); 4772 return (DDI_FAILURE); 4773 } 4774 4775 /* Test for high level interrupt. */ 4776 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4777 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4778 "ahci_add_legacy_intrs: Hi level intr not supported"); 4779 4780 for (x = 0; x < actual; x++) { 4781 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 4782 } 4783 4784 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4785 sizeof (ddi_intr_handle_t)); 4786 4787 return (DDI_FAILURE); 4788 } 4789 4790 /* Call ddi_intr_add_handler(). */ 4791 for (x = 0; x < actual; x++) { 4792 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 4793 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 4794 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4795 "ddi_intr_add_handler() failed"); 4796 4797 for (y = 0; y < actual; y++) { 4798 (void) ddi_intr_free( 4799 ahci_ctlp->ahcictl_intr_htable[y]); 4800 } 4801 4802 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4803 ahci_ctlp->ahcictl_intr_size); 4804 return (DDI_FAILURE); 4805 } 4806 } 4807 4808 /* Call ddi_intr_enable() for legacy interrupts. */ 4809 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 4810 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 4811 } 4812 4813 return (DDI_SUCCESS); 4814 } 4815 4816 /* 4817 * Handle MSI interrupts. 4818 */ 4819 static int 4820 ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 4821 { 4822 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 4823 int count, avail, actual; 4824 int x, y, rc, inum = 0; 4825 4826 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 4827 "ahci_add_msi_intrs enter"); 4828 4829 /* get number of interrupts. */ 4830 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 4831 if ((rc != DDI_SUCCESS) || (count == 0)) { 4832 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4833 "ddi_intr_get_nintrs() failed, " 4834 "rc %d count %d\n", rc, count); 4835 return (DDI_FAILURE); 4836 } 4837 4838 /* get number of available interrupts. */ 4839 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 4840 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4841 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4842 "ddi_intr_get_navail() failed, " 4843 "rc %d avail %d\n", rc, avail); 4844 return (DDI_FAILURE); 4845 } 4846 4847 if (avail < count) { 4848 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4849 "ddi_intr_get_nvail returned %d, navail() returned %d", 4850 count, avail); 4851 } 4852 4853 /* Allocate an array of interrupt handles. */ 4854 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 4855 ahci_ctlp->ahcictl_intr_htable = 4856 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 4857 4858 /* call ddi_intr_alloc(). */ 4859 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 4860 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 4861 4862 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4863 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4864 "ddi_intr_alloc() failed, rc %d\n", rc); 4865 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4866 ahci_ctlp->ahcictl_intr_size); 4867 return (DDI_FAILURE); 4868 } 4869 4870 /* use interrupt count returned */ 4871 if (actual < count) { 4872 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4873 "Requested: %d, Received: %d", count, actual); 4874 } 4875 4876 ahci_ctlp->ahcictl_intr_cnt = actual; 4877 4878 /* 4879 * Get priority for first msi, assume remaining are all the same. 4880 */ 4881 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 4882 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 4883 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4884 "ddi_intr_get_pri() failed"); 4885 4886 /* Free already allocated intr. */ 4887 for (y = 0; y < actual; y++) { 4888 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 4889 } 4890 4891 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4892 ahci_ctlp->ahcictl_intr_size); 4893 return (DDI_FAILURE); 4894 } 4895 4896 /* Test for high level interrupt. */ 4897 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4898 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4899 "ahci_add_msi_intrs: Hi level intr not supported"); 4900 4901 /* Free already allocated intr. */ 4902 for (y = 0; y < actual; y++) { 4903 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 4904 } 4905 4906 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4907 sizeof (ddi_intr_handle_t)); 4908 4909 return (DDI_FAILURE); 4910 } 4911 4912 /* Call ddi_intr_add_handler(). */ 4913 for (x = 0; x < actual; x++) { 4914 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 4915 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 4916 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 4917 "ddi_intr_add_handler() failed"); 4918 4919 /* Free already allocated intr. */ 4920 for (y = 0; y < actual; y++) { 4921 (void) ddi_intr_free( 4922 ahci_ctlp->ahcictl_intr_htable[y]); 4923 } 4924 4925 kmem_free(ahci_ctlp->ahcictl_intr_htable, 4926 ahci_ctlp->ahcictl_intr_size); 4927 return (DDI_FAILURE); 4928 } 4929 } 4930 4931 4932 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 4933 &ahci_ctlp->ahcictl_intr_cap); 4934 4935 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 4936 /* Call ddi_intr_block_enable() for MSI. */ 4937 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 4938 ahci_ctlp->ahcictl_intr_cnt); 4939 } else { 4940 /* Call ddi_intr_enable() for MSI non block enable. */ 4941 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 4942 (void) ddi_intr_enable( 4943 ahci_ctlp->ahcictl_intr_htable[x]); 4944 } 4945 } 4946 4947 return (DDI_SUCCESS); 4948 } 4949 4950 /* 4951 * Removes the registered interrupts irrespective of whether they 4952 * were legacy or MSI. 4953 * 4954 * WARNING!!! The controller interrupts must be disabled before calling 4955 * this routine. 4956 */ 4957 static void 4958 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 4959 { 4960 int x; 4961 4962 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 4963 4964 /* Disable all interrupts. */ 4965 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 4966 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 4967 /* Call ddi_intr_block_disable(). */ 4968 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 4969 ahci_ctlp->ahcictl_intr_cnt); 4970 } else { 4971 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 4972 (void) ddi_intr_disable( 4973 ahci_ctlp->ahcictl_intr_htable[x]); 4974 } 4975 } 4976 4977 /* Call ddi_intr_remove_handler(). */ 4978 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 4979 (void) ddi_intr_remove_handler( 4980 ahci_ctlp->ahcictl_intr_htable[x]); 4981 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 4982 } 4983 4984 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 4985 } 4986 4987 /* 4988 * This routine tries to put port into NotRunning state by clearing 4989 * PxCMD.ST and PxCMD.FRE. Remember to clear PxCMD.FRE before clearing 4990 * PxCMD.ST. 4991 * 4992 * WARNING!!! ahciport_mutex should be acquired before the function 4993 * is called. 4994 */ 4995 /* ARGSUSED */ 4996 static int 4997 ahci_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 4998 ahci_port_t *ahci_port, uint8_t port) 4999 { 5000 uint32_t port_cmd_status; 5001 int loop_count; 5002 5003 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5004 "ahci_port_into_notrunning_state enter: port %d", port); 5005 5006 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5007 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5008 5009 if (!(port_cmd_status & AHCI_CMD_STATUS_ST)) 5010 goto clear_fre; 5011 5012 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5013 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5014 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5015 5016 /* Wait until PxCMD.CR is cleared */ 5017 loop_count = 0; 5018 do { 5019 port_cmd_status = 5020 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5021 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5022 5023 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5024 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5025 "clearing port %d CMD.CR timeout, " 5026 "port_cmd_status = 0x%x", port, 5027 port_cmd_status); 5028 /* 5029 * We are effectively timing out after 0.5 sec. 5030 * This value is specified in AHCI spec. 5031 */ 5032 break; 5033 } 5034 5035 /* Wait for 10 millisec */ 5036 #ifndef __lock_lint 5037 delay(AHCI_10MS_TICKS); 5038 #endif /* __lock_lint */ 5039 5040 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5041 5042 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5043 "ahci_port_into_notrunning_state: 1st loop count: %d, " 5044 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5045 5046 clear_fre: 5047 if (port_cmd_status & AHCI_CMD_STATUS_FRE) { 5048 5049 port_cmd_status &= ~AHCI_CMD_STATUS_FRE; 5050 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5051 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 5052 port_cmd_status); 5053 5054 /* Wait until PxCMD.FR is cleared */ 5055 loop_count = 0; 5056 do { 5057 port_cmd_status = 5058 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5059 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5060 5061 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5062 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5063 "clearing port %d CMD.FR " 5064 "timeout, port_cmd_status = 0x%x", 5065 port, port_cmd_status); 5066 /* 5067 * We are effectively timing out after 0.5 sec. 5068 * This value is specified in AHCI spec. 5069 */ 5070 break; 5071 } 5072 5073 /* Wait for 10 millisec */ 5074 #ifndef __lock_lint 5075 delay(AHCI_10MS_TICKS); 5076 #endif /* __lock_lint */ 5077 } while (port_cmd_status & AHCI_CMD_STATUS_FR); 5078 5079 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5080 "ahci_port_into_notrunning_state: 2nd loop count: " 5081 "%d, port_cmd_status = 0x%x", 5082 loop_count, port_cmd_status); 5083 } 5084 5085 if (port_cmd_status & 5086 (AHCI_CMD_STATUS_ST | 5087 AHCI_CMD_STATUS_CR | 5088 AHCI_CMD_STATUS_FRE | 5089 AHCI_CMD_STATUS_FR)) { 5090 5091 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 5092 "port %d cannot be put in NotRunning state", port); 5093 return (AHCI_FAILURE); 5094 5095 } else { 5096 5097 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 5098 "port %d is put in NotRunning state", port); 5099 return (AHCI_SUCCESS); 5100 } 5101 } 5102 5103 /* 5104 * This routine will be called under five scenarios: 5105 * 1. Initialize the port 5106 * 2. To abort the packet(s) 5107 * 3. To reset the port 5108 * 4. Fatal error recovery 5109 * 5. To abort the timeout packet(s) 5110 * 5111 * WARNING!!! ahciport_mutex should be acquired before the function 5112 * is called. 5113 */ 5114 static int 5115 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5116 ahci_port_t *ahci_portp, uint8_t port, int flag) 5117 { 5118 uint32_t task_file_status; 5119 sata_device_t sdevice; 5120 int rval; 5121 5122 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5123 "ahci_restart_port_wait_till_ready: port %d enter", port); 5124 5125 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 5126 5127 rval = ahci_port_into_notrunning_state(ahci_ctlp, ahci_portp, port); 5128 5129 if (rval == AHCI_SUCCESS) { 5130 task_file_status = ddi_get32( 5131 ahci_ctlp->ahcictl_ahci_acc_handle, 5132 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5133 5134 if (task_file_status & AHCI_TFD_STS_BSY || 5135 task_file_status & AHCI_TFD_STS_DRQ) 5136 rval = AHCI_FAILURE; 5137 } 5138 5139 if (!(flag & AHCI_PORT_RESET) && (rval == AHCI_SUCCESS)) 5140 goto out; 5141 5142 /* Set the reset in progress flag */ 5143 if (!(flag & AHCI_RESET_NO_EVENTS_UP)) { 5144 ahci_portp->ahciport_reset_in_progress = 1; 5145 } 5146 5147 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 5148 if (rval != AHCI_SUCCESS) { 5149 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 5150 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5151 "ahci_restart_port_wait_till_ready: port %d failed", 5152 port); 5153 } 5154 5155 /* Indicate to the framework that a reset has happened. */ 5156 if (!(flag & AHCI_RESET_NO_EVENTS_UP)) { 5157 5158 bzero((void *)&sdevice, sizeof (sata_device_t)); 5159 sdevice.satadev_addr.cport = 5160 ahci_ctlp->ahcictl_port_to_cport[port]; 5161 sdevice.satadev_addr.pmport = AHCI_PORTMULT_CONTROL_PORT; 5162 5163 if (ahci_portp->ahciport_device_type == SATA_DTYPE_PMULT) { 5164 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT; 5165 } else { 5166 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5167 } 5168 sdevice.satadev_state = SATA_DSTATE_RESET | 5169 SATA_DSTATE_PWR_ACTIVE; 5170 if (ahci_ctlp->ahcictl_sata_hba_tran) { 5171 mutex_exit(&ahci_portp->ahciport_mutex); 5172 sata_hba_event_notify( 5173 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5174 &sdevice, 5175 SATA_EVNT_DEVICE_RESET); 5176 mutex_enter(&ahci_portp->ahciport_mutex); 5177 } 5178 5179 AHCIDBG0(AHCIDBG_EVENT, ahci_ctlp, 5180 "sending event up: SATA_EVNT_RESET"); 5181 } 5182 out: 5183 if (!(flag & AHCI_PORT_INIT)) { 5184 (void) ahci_start_port(ahci_ctlp, port); 5185 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 5186 } 5187 5188 return (rval); 5189 } 5190 5191 /* 5192 * This routine is called under four scenarios: 5193 * a) some commands failed with errors 5194 * b) or we need to timeout some commands 5195 * c) or we need to abort some commands 5196 * d) or we need reset device/port/controller 5197 * 5198 * In all these scenarios, we need to send any pending unfinished 5199 * commands up to sata framework. 5200 * 5201 * Only one mopping process at a time is allowed; this is achieved 5202 * by checking AHCI_PORT_STATE_MOPPING by the caller. 5203 */ 5204 static void 5205 ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 5206 ahci_port_t *ahci_portp, 5207 uint8_t port, 5208 uint32_t slot_status, 5209 uint32_t failed_tags, 5210 uint32_t timeout_tags, 5211 uint32_t aborted_tags, 5212 uint32_t reset_tags) 5213 { 5214 uint32_t finished_tags, unfinished_tags; 5215 int tmp_slot; 5216 sata_pkt_t *satapkt; 5217 int i, num = 0; 5218 ahci_fis_d2h_register_t *rcvd_fisp; 5219 5220 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 5221 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 5222 port, slot_status); 5223 5224 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 5225 "ahci_mop_commands: failed_tags: 0x%x, " 5226 "timeout_tags: 0x%x aborted_tags: 0x%x, " 5227 "reset_tags: 0x%x", failed_tags, 5228 timeout_tags, aborted_tags, reset_tags); 5229 5230 /* 5231 * We could be here for four reasons: abort, reset, 5232 * timeout or error handling. Only one such mopping 5233 * is allowed at a time. 5234 */ 5235 mutex_enter(&ahci_portp->ahciport_mutex); 5236 5237 finished_tags = ahci_portp->ahciport_pending_tags & 5238 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 5239 5240 unfinished_tags = slot_status & 5241 AHCI_SLOT_MASK(ahci_ctlp) & 5242 ~failed_tags & 5243 ~aborted_tags & 5244 ~reset_tags & 5245 ~timeout_tags; 5246 5247 /* 5248 * Try to check if there are more than one command which have 5249 * been finished. 5250 */ 5251 for (i = 0; i < ahci_ctlp->ahcictl_num_cmd_slots; i++) { 5252 if ((0x1 << i) & finished_tags) 5253 num++; 5254 } 5255 ASSERT(num <= 1); 5256 5257 /* Set finished packets with SATA_PKT_COMPLETED */ 5258 while (finished_tags) { 5259 tmp_slot = ddi_ffs(finished_tags) - 1; 5260 if (tmp_slot == -1) { 5261 break; 5262 } 5263 5264 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5265 ASSERT(satapkt != NULL); 5266 5267 rcvd_fisp = 5268 &(ahci_portp->ahciport_rcvd_fis->ahcirf_d2h_register_fis); 5269 5270 /* Return the status */ 5271 satapkt->satapkt_cmd.satacmd_status_reg = 5272 GET_RFIS_STATUS(rcvd_fisp); 5273 5274 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 5275 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 5276 5277 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 5278 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 5279 (void *)satapkt); 5280 5281 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5282 CLEAR_BIT(finished_tags, tmp_slot); 5283 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5284 5285 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 5286 } 5287 5288 ASSERT(finished_tags == 0); 5289 5290 /* Send up failed_tags with SATA_PKT_DEV_ERROR. */ 5291 while (failed_tags) { 5292 tmp_slot = ddi_ffs(failed_tags) - 1; 5293 if (tmp_slot == -1) { 5294 break; 5295 } 5296 5297 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5298 ASSERT(satapkt != NULL); 5299 5300 if (satapkt->satapkt_device.satadev_type == 5301 SATA_DTYPE_ATAPICD) { 5302 ahci_set_sense_data(satapkt, SATA_PKT_ABORTED); 5303 } 5304 5305 rcvd_fisp = 5306 &(ahci_portp->ahciport_rcvd_fis->ahcirf_d2h_register_fis); 5307 5308 /* Return the status */ 5309 satapkt->satapkt_cmd.satacmd_status_reg = 5310 GET_RFIS_STATUS(rcvd_fisp); 5311 5312 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 5313 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 5314 5315 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5316 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 5317 (void *)satapkt); 5318 5319 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5320 CLEAR_BIT(failed_tags, tmp_slot); 5321 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5322 5323 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 5324 } 5325 5326 ASSERT(failed_tags == 0); 5327 5328 /* Send up timeout_tags with SATA_PKT_TIMEOUT. */ 5329 while (timeout_tags) { 5330 tmp_slot = ddi_ffs(timeout_tags) - 1; 5331 if (tmp_slot == -1) { 5332 break; 5333 } 5334 5335 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5336 ASSERT(satapkt != NULL); 5337 5338 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5339 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 5340 (void *)satapkt); 5341 5342 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5343 CLEAR_BIT(timeout_tags, tmp_slot); 5344 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5345 5346 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 5347 } 5348 5349 ASSERT(timeout_tags == 0); 5350 5351 /* Set aborted packets with SATA_PKT_ABORTED */ 5352 while (aborted_tags) { 5353 tmp_slot = ddi_ffs(aborted_tags) - 1; 5354 if (tmp_slot == -1) { 5355 break; 5356 } 5357 5358 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5359 ASSERT(satapkt != NULL); 5360 5361 if (satapkt->satapkt_device.satadev_type == 5362 SATA_DTYPE_ATAPICD) { 5363 ahci_set_sense_data(satapkt, SATA_PKT_ABORTED); 5364 } 5365 5366 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5367 "sending up pkt 0x%p with SATA_PKT_ABORTED", 5368 (void *)satapkt); 5369 5370 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5371 CLEAR_BIT(aborted_tags, tmp_slot); 5372 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5373 5374 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 5375 } 5376 5377 ASSERT(aborted_tags == 0); 5378 5379 /* Reset tags are sent up to framework with SATA_PKT_RESET. */ 5380 while (reset_tags) { 5381 tmp_slot = ddi_ffs(reset_tags) - 1; 5382 if (tmp_slot == -1) { 5383 break; 5384 } 5385 5386 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5387 ASSERT(satapkt != NULL); 5388 5389 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5390 "sending up pkt 0x%p with SATA_PKT_RESET", 5391 (void *)satapkt); 5392 5393 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5394 CLEAR_BIT(reset_tags, tmp_slot); 5395 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5396 5397 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 5398 } 5399 5400 ASSERT(reset_tags == 0); 5401 5402 /* Set unfinished packets with SATA_PKT_BUSY */ 5403 while (unfinished_tags) { 5404 tmp_slot = ddi_ffs(unfinished_tags) - 1; 5405 if (tmp_slot == -1) { 5406 break; 5407 } 5408 5409 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5410 ASSERT(satapkt != NULL); 5411 5412 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5413 "sending up pkt 0x%p with SATA_PKT_BUSY", 5414 (void *)satapkt); 5415 5416 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5417 CLEAR_BIT(unfinished_tags, tmp_slot); 5418 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5419 5420 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_BUSY); 5421 } 5422 5423 ASSERT(unfinished_tags == 0); 5424 5425 ahci_portp->ahciport_flags &= ~AHCI_PORT_STATE_MOPPING; 5426 5427 mutex_exit(&ahci_portp->ahciport_mutex); 5428 } 5429 5430 /* 5431 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 5432 * the port must be restarted. 5433 * 5434 * Fatal errors include the following: 5435 * PxIS.OFS - Overflow Status 5436 * PxIS.IFS - Interface Fatal Error Status 5437 * PxIS.HBDS - Host Bus Data Error Status 5438 * PxIS.HBFS - Host Bus Fatal Error Status 5439 * PxIS.TFES - Task File Error Status 5440 * 5441 * WARNING!!! ahciport_mutex should be acquired before the function is called. 5442 */ 5443 static int 5444 ahci_recovery_fatal_error(ahci_ctl_t *ahci_ctlp, 5445 ahci_port_t *ahci_portp, uint8_t port, uint32_t error) 5446 { 5447 uint32_t port_cmd_status, slot_status; 5448 uint32_t failed_tags; 5449 int current_slot; 5450 sata_pkt_t *spkt; 5451 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 5452 5453 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5454 "ahci_recovery_fatal_error enter port %d", port); 5455 5456 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5457 /* 5458 * ahci_intr_phyrdy_change() may have rendered it to 5459 * SATA_DTYPE_NONE. 5460 */ 5461 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5462 "ahci_recovery_fatal_error: no device attached, and just " 5463 "return without doing anything", port); 5464 return (SATA_SUCCESS); 5465 } 5466 5467 /* Record the error occurred command slot */ 5468 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5469 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5470 5471 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5472 AHCI_CMD_STATUS_CCS_SHIFT; 5473 5474 spkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5475 if (spkt == NULL) { 5476 /* 5477 * For example, sometimes PxIS.OFS and PxIS.IFS can be set 5478 * concurrently. 5479 */ 5480 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5481 "ahci_recovery_fatal_error: port %d has done " 5482 "fatal error recovery, so return directory", port); 5483 return (SATA_SUCCESS); 5484 } 5485 5486 /* 5487 * To prevent recursive enter to ahci_mop_commands, we need 5488 * check AHCI_PORT_STATE_MOPPING flag. 5489 */ 5490 if (ahci_portp->ahciport_flags & AHCI_PORT_STATE_MOPPING) { 5491 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 5492 "ahci_recovery_fatal_error: port %d is in " 5493 "mopping process, so return directly", port); 5494 return (SATA_SUCCESS); 5495 } 5496 5497 ahci_portp->ahciport_flags |= AHCI_PORT_STATE_MOPPING; 5498 5499 failed_tags = 0x1 << current_slot; 5500 5501 switch (error) { 5502 case AHCI_INTR_STATUS_IFS: 5503 case AHCI_INTR_STATUS_HBFS: 5504 case AHCI_INTR_STATUS_HBDS: 5505 /* 5506 * For PxIS.IFS, PxIS.HBFS and PxIS.HBDS, we need to return 5507 * PxSERR in satapkt. 5508 */ 5509 ahci_update_sata_registers(ahci_ctlp, port, 5510 &spkt->satapkt_device); 5511 break; 5512 5513 case AHCI_INTR_STATUS_TFES: 5514 /* 5515 * For PxIS.TFES, we need to return the status and error 5516 * registers in sata_cmd structure 5517 */ 5518 ahci_rcvd_fisp = 5519 &(ahci_portp->ahciport_rcvd_fis->ahcirf_d2h_register_fis); 5520 5521 spkt->satapkt_cmd.satacmd_status_reg = 5522 GET_RFIS_STATUS(ahci_rcvd_fisp); 5523 5524 spkt->satapkt_cmd.satacmd_error_reg = 5525 GET_RFIS_ERROR(ahci_rcvd_fisp); 5526 break; 5527 5528 case AHCI_INTR_STATUS_OFS: 5529 /* 5530 * For PxIS.OFS, until now have no way to send the error 5531 * to sata framework. 5532 */ 5533 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5534 "ahci_recovery_fatal_error: " 5535 "PxOFS occured for port %d", port); 5536 5537 break; 5538 5539 default: 5540 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5541 "Not supported error 0x%x for port %d", 5542 error, port); 5543 break; 5544 } 5545 5546 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5547 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5548 5549 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 5550 "ahci_recovery_fatal_error: current_slot = 0x%x " 5551 "slot_status = 0x%x", current_slot, slot_status); 5552 5553 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 5554 ahci_portp, port, NULL); 5555 5556 mutex_exit(&ahci_portp->ahciport_mutex); 5557 ahci_mop_commands(ahci_ctlp, 5558 ahci_portp, 5559 port, 5560 slot_status, 5561 failed_tags, /* failed tags */ 5562 0, /* timeout tags */ 5563 0, /* aborted tags */ 5564 0); /* reset tags */ 5565 mutex_enter(&ahci_portp->ahciport_mutex); 5566 5567 return (SATA_SUCCESS); 5568 } 5569 5570 /* 5571 * ahci_watchdog_handler() calls us if it detects that there are some 5572 * commands which timed out. 5573 */ 5574 static void 5575 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5576 uint8_t port, uint32_t tmp_timeout_tags) 5577 { 5578 uint32_t slot_status; 5579 uint32_t finished_tags, timeout_tags; 5580 5581 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 5582 "ahci_timeout_pkts entered"); 5583 5584 mutex_enter(&ahci_portp->ahciport_mutex); 5585 5586 /* 5587 * To prevent recursive enter to ahci_mop_commands, we need 5588 * check AHCI_PORT_STATE_MOPPING flag. 5589 */ 5590 if (ahci_portp->ahciport_flags & AHCI_PORT_STATE_MOPPING) { 5591 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 5592 "ahci_timeout_pkts: port %d is in " 5593 "mopping process, so return directly ", port); 5594 mutex_exit(&ahci_portp->ahciport_mutex); 5595 return; 5596 } 5597 5598 ahci_portp->ahciport_flags |= AHCI_PORT_STATE_MOPPING; 5599 5600 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5601 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5602 5603 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 5604 port, NULL); 5605 /* 5606 * Re-identify timeout tags because some previously checked commands 5607 * could already complete. 5608 */ 5609 finished_tags = ahci_portp->ahciport_pending_tags & 5610 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 5611 5612 timeout_tags = tmp_timeout_tags & ~finished_tags; 5613 5614 AHCIDBG3(AHCIDBG_TIMEOUT, ahci_ctlp, 5615 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 5616 "timeout_tags = 0x%x", port, 5617 finished_tags, timeout_tags); 5618 5619 mutex_exit(&ahci_portp->ahciport_mutex); 5620 ahci_mop_commands(ahci_ctlp, 5621 ahci_portp, 5622 port, 5623 slot_status, 5624 0, /* failed tags */ 5625 timeout_tags, /* timeout tags */ 5626 0, /* aborted tags */ 5627 0); /* reset tags */ 5628 } 5629 5630 /* 5631 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 5632 * for long time. 5633 */ 5634 static void 5635 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 5636 { 5637 ahci_port_t *ahci_portp; 5638 sata_pkt_t *satapkt; 5639 uint32_t pending_tags = 0; 5640 uint32_t timeout_tags = 0; 5641 uint8_t port; 5642 int tmp_slot; 5643 /* max number of cycles this packet should survive */ 5644 int max_life_cycles; 5645 5646 /* how many cycles this packet survived so far */ 5647 int watched_cycles; 5648 5649 mutex_enter(&ahci_ctlp->ahcictl_mutex); 5650 5651 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 5652 "ahci_watchdog_handler entered"); 5653 5654 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 5655 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 5656 continue; 5657 } 5658 5659 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 5660 5661 mutex_enter(&ahci_portp->ahciport_mutex); 5662 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5663 mutex_exit(&ahci_portp->ahciport_mutex); 5664 continue; 5665 } 5666 5667 pending_tags = ahci_portp->ahciport_pending_tags; 5668 timeout_tags = 0; 5669 while (pending_tags) { 5670 tmp_slot = ddi_ffs(pending_tags) - 1; 5671 if (tmp_slot == -1) { 5672 break; 5673 } 5674 5675 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5676 if ((satapkt != NULL) && satapkt->satapkt_time) { 5677 /* 5678 * We are overloading satapkt_hba_driver_private 5679 * with watched_cycle count. 5680 * 5681 * If a packet has survived for more than it's 5682 * max life cycles, it is a candidate for time 5683 * out. 5684 */ 5685 watched_cycles = (int)(intptr_t) 5686 satapkt->satapkt_hba_driver_private; 5687 watched_cycles++; 5688 max_life_cycles = (satapkt->satapkt_time + 5689 ahci_watchdog_timeout - 1) / 5690 ahci_watchdog_timeout; 5691 if (watched_cycles > max_life_cycles) { 5692 timeout_tags |= (0x1 << tmp_slot); 5693 cmn_err(CE_NOTE, "!ahci watchdog: " 5694 "port %d satapkt 0x%p timed out\n", 5695 port, (void *)satapkt); 5696 } 5697 satapkt->satapkt_hba_driver_private = 5698 (void *)(intptr_t)watched_cycles; 5699 } 5700 5701 CLEAR_BIT(pending_tags, tmp_slot); 5702 } 5703 5704 if (timeout_tags) { 5705 mutex_exit(&ahci_portp->ahciport_mutex); 5706 mutex_exit(&ahci_ctlp->ahcictl_mutex); 5707 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 5708 port, timeout_tags); 5709 mutex_enter(&ahci_ctlp->ahcictl_mutex); 5710 mutex_enter(&ahci_portp->ahciport_mutex); 5711 } 5712 5713 mutex_exit(&ahci_portp->ahciport_mutex); 5714 } 5715 5716 /* Re-install the watchdog timeout handler */ 5717 if (ahci_ctlp->ahcictl_timeout_id != 0) { 5718 ahci_ctlp->ahcictl_timeout_id = 5719 timeout((void (*)(void *))ahci_watchdog_handler, 5720 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 5721 } 5722 5723 mutex_exit(&ahci_ctlp->ahcictl_mutex); 5724 } 5725 5726 /* 5727 * Put a copy back to sata_cmd_t. 5728 */ 5729 static void 5730 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 5731 { 5732 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 5733 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 5734 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 5735 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 5736 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 5737 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 5738 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 5739 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 5740 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 5741 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 5742 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 5743 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 5744 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 5745 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 5746 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 5747 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 5748 if (scmd->satacmd_flags.sata_copy_out_device_reg) 5749 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 5750 if (scmd->satacmd_flags.sata_copy_out_error_reg) 5751 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 5752 } 5753 5754 /* 5755 * Dump the serror message to the log. 5756 */ 5757 static void 5758 ahci_log_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 5759 uint32_t port_serror) 5760 { 5761 char *err_str; 5762 5763 if (port_serror & AHCI_SERROR_ERR_I) { 5764 err_str = "Recovered Data Integrity Error (I)"; 5765 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5766 "command error: port: %d, error: %s", 5767 port, err_str); 5768 } 5769 5770 if (port_serror & AHCI_SERROR_ERR_M) { 5771 err_str = "Recovered Communication Error (M)"; 5772 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5773 "command error: port: %d, error: %s", 5774 port, err_str); 5775 } 5776 5777 if (port_serror & AHCI_SERROR_ERR_T) { 5778 err_str = "Transient Data Integrity Error (T)"; 5779 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5780 "command error: port: %d, error: %s", 5781 port, err_str); 5782 } 5783 5784 if (port_serror & AHCI_SERROR_ERR_C) { 5785 err_str = 5786 "Persistent Communication or Data Integrity Error (C)"; 5787 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5788 "command error: port: %d, error: %s", 5789 port, err_str); 5790 } 5791 5792 if (port_serror & AHCI_SERROR_ERR_P) { 5793 err_str = "Protocol Error (P)"; 5794 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5795 "command error: port: %d, error: %s", 5796 port, err_str); 5797 } 5798 5799 if (port_serror & AHCI_SERROR_ERR_E) { 5800 err_str = "Internal Error (E)"; 5801 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5802 "command error: port: %d, error: %s", 5803 port, err_str); 5804 } 5805 5806 if (port_serror & AHCI_SERROR_DIAG_N) { 5807 err_str = "PhyRdy Change (N)"; 5808 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5809 "command error: port: %d, error: %s", 5810 port, err_str); 5811 } 5812 5813 if (port_serror & AHCI_SERROR_DIAG_I) { 5814 err_str = "Phy Internal Error (I)"; 5815 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5816 "command error: port: %d, error: %s", 5817 port, err_str); 5818 } 5819 5820 if (port_serror & AHCI_SERROR_DIAG_W) { 5821 err_str = "Comm Wake (W)"; 5822 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5823 "command error: port: %d, error: %s", 5824 port, err_str); 5825 } 5826 5827 if (port_serror & AHCI_SERROR_DIAG_B) { 5828 err_str = "10B to 8B Decode Error (B)"; 5829 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5830 "command error: port: %d, error: %s", 5831 port, err_str); 5832 } 5833 5834 if (port_serror & AHCI_SERROR_DIAG_D) { 5835 err_str = "Disparity Error (D)"; 5836 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5837 "command error: port: %d, error: %s", 5838 port, err_str); 5839 } 5840 5841 if (port_serror & AHCI_SERROR_DIAG_C) { 5842 err_str = "CRC Error (C)"; 5843 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5844 "command error: port: %d, error: %s", 5845 port, err_str); 5846 } 5847 5848 if (port_serror & AHCI_SERROR_DIAG_H) { 5849 err_str = "Handshake Error (H)"; 5850 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5851 "command error: port: %d, error: %s", 5852 port, err_str); 5853 } 5854 5855 if (port_serror & AHCI_SERROR_DIAG_S) { 5856 err_str = "Link Sequence Error (S)"; 5857 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5858 "command error: port: %d, error: %s", 5859 port, err_str); 5860 } 5861 5862 if (port_serror & AHCI_SERROR_DIAG_T) { 5863 err_str = "Transport state transition error (T)"; 5864 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5865 "command error: port: %d, error: %s", 5866 port, err_str); 5867 } 5868 5869 if (port_serror & AHCI_SERROR_DIAG_F) { 5870 err_str = "Unknown FIS Type (F)"; 5871 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5872 "command error: port: %d, error: %s", 5873 port, err_str); 5874 } 5875 5876 if (port_serror & AHCI_SERROR_DIAG_X) { 5877 err_str = "Exchanged (X)"; 5878 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 5879 "command error: port: %d, error: %s", 5880 port, err_str); 5881 } 5882 } 5883 5884 /* 5885 * This routine is to calculate the total number of ports implemented 5886 * by the HBA. 5887 */ 5888 static int 5889 ahci_get_num_implemented_ports(uint32_t ports_implemented) 5890 { 5891 uint8_t i; 5892 int num = 0; 5893 5894 for (i = 0; i < AHCI_MAX_PORTS; i++) { 5895 if (((uint32_t)0x1 << i) & ports_implemented) 5896 num++; 5897 } 5898 5899 return (num); 5900 } 5901 5902 static void 5903 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 5904 { 5905 va_list ap; 5906 5907 mutex_enter(&ahci_log_mutex); 5908 5909 va_start(ap, fmt); 5910 if (ahci_ctlp) { 5911 (void) sprintf(ahci_log_buf, "%s-[%d]:", 5912 ddi_get_name(ahci_ctlp->ahcictl_dip), 5913 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 5914 } else { 5915 (void) sprintf(ahci_log_buf, "ahci:"); 5916 } 5917 5918 (void) vsprintf(ahci_log_buf, fmt, ap); 5919 va_end(ap); 5920 5921 cmn_err(level, "%s", ahci_log_buf); 5922 5923 mutex_exit(&ahci_log_mutex); 5924 } 5925