1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 31 * 32 * Power Management Support 33 * ------------------------ 34 * 35 * At the moment, the ahci driver only implements suspend/resume to 36 * support Suspend to RAM on X86 feature. Device power management isn't 37 * implemented, link power management is disabled, and hot plug isn't 38 * allowed during the period from suspend to resume. 39 * 40 * For s/r support, the ahci driver only need to implement DDI_SUSPEND 41 * and DDI_RESUME entries, and don't need to take care of new requests 42 * sent down after suspend because the target driver (sd) has already 43 * handled these conditions, and blocked these requests. For the detailed 44 * information, please check with sdopen, sdclose and sdioctl routines. 45 * 46 */ 47 48 #include <sys/scsi/scsi.h> 49 #include <sys/pci.h> 50 #include <sys/sata/sata_hba.h> 51 #include <sys/sata/adapters/ahci/ahcireg.h> 52 #include <sys/sata/adapters/ahci/ahcivar.h> 53 54 /* 55 * Function prototypes for driver entry points 56 */ 57 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 58 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 59 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 60 61 /* 62 * Function prototypes for SATA Framework interfaces 63 */ 64 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 65 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 66 67 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 68 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 69 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 70 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 71 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 72 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 73 #if defined(__lock_lint) 74 static int ahci_selftest(dev_info_t *, sata_device_t *); 75 #endif 76 77 /* 78 * Local function prototypes 79 */ 80 static int ahci_alloc_ports_state(ahci_ctl_t *); 81 static void ahci_dealloc_ports_state(ahci_ctl_t *); 82 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 83 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 84 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 85 static void ahci_dealloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *); 86 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 87 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 88 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 89 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 90 91 static int ahci_initialize_controller(ahci_ctl_t *); 92 static void ahci_uninitialize_controller(ahci_ctl_t *); 93 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 94 static int ahci_config_space_init(ahci_ctl_t *); 95 96 static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 97 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 98 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 99 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 100 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 101 uint8_t, sata_pkt_t *); 102 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 103 uint8_t, sata_pkt_t *); 104 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 105 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 106 static void ahci_copy_ncq_err_page(sata_cmd_t *, 107 struct sata_ncq_error_recovery_page *); 108 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 109 110 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 111 static int ahci_hba_reset(ahci_ctl_t *); 112 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 113 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 114 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 115 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 116 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 117 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 118 uint8_t); 119 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 120 uint8_t, int, int *); 121 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint8_t, 122 uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); 123 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 124 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 125 uint8_t, sata_pkt_t *); 126 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 127 uint8_t, uint32_t); 128 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 129 uint8_t, uint32_t); 130 static void ahci_events_handler(void *); 131 static void ahci_watchdog_handler(ahci_ctl_t *); 132 133 static uint_t ahci_intr(caddr_t, caddr_t); 134 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 135 static int ahci_add_legacy_intrs(ahci_ctl_t *); 136 static int ahci_add_msi_intrs(ahci_ctl_t *); 137 static void ahci_rem_intrs(ahci_ctl_t *); 138 static void ahci_enable_all_intrs(ahci_ctl_t *); 139 static void ahci_disable_all_intrs(ahci_ctl_t *); 140 static void ahci_enable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 141 static void ahci_disable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 142 143 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t, 144 uint32_t); 145 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 146 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 147 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 148 ahci_port_t *, uint8_t); 149 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 150 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 151 uint8_t, uint32_t); 152 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 153 uint8_t, uint32_t); 154 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 155 156 static int ahci_get_num_implemented_ports(uint32_t); 157 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 158 uint32_t); 159 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int); 160 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 161 162 163 /* 164 * DMA attributes for the data buffer 165 * 166 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 167 * does not support 64-bit addressing 168 */ 169 static ddi_dma_attr_t buffer_dma_attr = { 170 DMA_ATTR_V0, /* dma_attr_version */ 171 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 172 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 173 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 174 0x2ull, /* dma_attr_align: word aligned */ 175 1, /* dma_attr_burstsizes */ 176 1, /* dma_attr_minxfer */ 177 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 178 0xffffffffull, /* dma_attr_seg */ 179 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 180 512, /* dma_attr_granular */ 181 0, /* dma_attr_flags */ 182 }; 183 184 /* 185 * DMA attributes for the rcvd FIS 186 * 187 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 188 * does not support 64-bit addressing 189 */ 190 static ddi_dma_attr_t rcvd_fis_dma_attr = { 191 DMA_ATTR_V0, /* dma_attr_version */ 192 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 193 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 194 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 195 0x100ull, /* dma_attr_align: 256-byte aligned */ 196 1, /* dma_attr_burstsizes */ 197 1, /* dma_attr_minxfer */ 198 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 199 0xffffffffull, /* dma_attr_seg */ 200 1, /* dma_attr_sgllen */ 201 1, /* dma_attr_granular */ 202 0, /* dma_attr_flags */ 203 }; 204 205 /* 206 * DMA attributes for the command list 207 * 208 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 209 * does not support 64-bit addressing 210 */ 211 static ddi_dma_attr_t cmd_list_dma_attr = { 212 DMA_ATTR_V0, /* dma_attr_version */ 213 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 214 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 215 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 216 0x400ull, /* dma_attr_align: 1K-byte aligned */ 217 1, /* dma_attr_burstsizes */ 218 1, /* dma_attr_minxfer */ 219 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 220 0xffffffffull, /* dma_attr_seg */ 221 1, /* dma_attr_sgllen */ 222 1, /* dma_attr_granular */ 223 0, /* dma_attr_flags */ 224 }; 225 226 /* 227 * DMA attributes for cmd tables 228 * 229 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 230 * does not support 64-bit addressing 231 */ 232 static ddi_dma_attr_t cmd_table_dma_attr = { 233 DMA_ATTR_V0, /* dma_attr_version */ 234 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 235 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 236 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 237 0x80ull, /* dma_attr_align: 128-byte aligned */ 238 1, /* dma_attr_burstsizes */ 239 1, /* dma_attr_minxfer */ 240 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 241 0xffffffffull, /* dma_attr_seg */ 242 1, /* dma_attr_sgllen */ 243 1, /* dma_attr_granular */ 244 0, /* dma_attr_flags */ 245 }; 246 247 248 /* Device access attributes */ 249 static ddi_device_acc_attr_t accattr = { 250 DDI_DEVICE_ATTR_V0, 251 DDI_STRUCTURE_LE_ACC, 252 DDI_STRICTORDER_ACC 253 }; 254 255 256 static struct dev_ops ahcictl_dev_ops = { 257 DEVO_REV, /* devo_rev */ 258 0, /* refcnt */ 259 ahci_getinfo, /* info */ 260 nulldev, /* identify */ 261 nulldev, /* probe */ 262 ahci_attach, /* attach */ 263 ahci_detach, /* detach */ 264 nodev, /* no reset */ 265 (struct cb_ops *)0, /* driver operations */ 266 NULL, /* bus operations */ 267 NULL /* power */ 268 }; 269 270 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 271 SATA_TRAN_HOTPLUG_OPS_REV_1, 272 ahci_tran_hotplug_port_activate, 273 ahci_tran_hotplug_port_deactivate 274 }; 275 276 extern struct mod_ops mod_driverops; 277 278 static struct modldrv modldrv = { 279 &mod_driverops, /* driverops */ 280 "ahci driver %I%", 281 &ahcictl_dev_ops, /* driver ops */ 282 }; 283 284 static struct modlinkage modlinkage = { 285 MODREV_1, 286 &modldrv, 287 NULL 288 }; 289 290 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 291 static int ahci_watchdog_tick; 292 293 /* The following is needed for ahci_log() */ 294 static kmutex_t ahci_log_mutex; 295 static char ahci_log_buf[512]; 296 297 static size_t ahci_cmd_table_size; 298 299 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 300 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 301 302 /* 303 * AHCI MSI tunable: 304 * 305 * MSI will be enabled in phase 2. 306 */ 307 boolean_t ahci_msi_enabled = B_FALSE; 308 309 #if AHCI_DEBUG 310 uint32_t ahci_debug_flags = 0; 311 #endif 312 313 /* Opaque state pointer initialized by ddi_soft_state_init() */ 314 static void *ahci_statep = NULL; 315 316 /* 317 * ahci module initialization. 318 */ 319 int 320 _init(void) 321 { 322 int ret; 323 324 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 325 if (ret != 0) { 326 goto err_out; 327 } 328 329 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 330 331 if ((ret = sata_hba_init(&modlinkage)) != 0) { 332 mutex_destroy(&ahci_log_mutex); 333 ddi_soft_state_fini(&ahci_statep); 334 goto err_out; 335 } 336 337 ret = mod_install(&modlinkage); 338 if (ret != 0) { 339 sata_hba_fini(&modlinkage); 340 mutex_destroy(&ahci_log_mutex); 341 ddi_soft_state_fini(&ahci_statep); 342 goto err_out; 343 } 344 345 /* watchdog tick */ 346 ahci_watchdog_tick = drv_usectohz( 347 (clock_t)ahci_watchdog_timeout * 1000000); 348 return (ret); 349 350 err_out: 351 cmn_err(CE_WARN, "!ahci: Module init failed"); 352 return (ret); 353 } 354 355 /* 356 * ahci module uninitialize. 357 */ 358 int 359 _fini(void) 360 { 361 int ret; 362 363 ret = mod_remove(&modlinkage); 364 if (ret != 0) { 365 return (ret); 366 } 367 368 /* Remove the resources allocated in _init(). */ 369 sata_hba_fini(&modlinkage); 370 mutex_destroy(&ahci_log_mutex); 371 ddi_soft_state_fini(&ahci_statep); 372 373 return (ret); 374 } 375 376 /* 377 * _info entry point 378 */ 379 int 380 _info(struct modinfo *modinfop) 381 { 382 return (mod_info(&modlinkage, modinfop)); 383 } 384 385 /* 386 * The attach entry point for dev_ops. 387 */ 388 static int 389 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 390 { 391 ahci_ctl_t *ahci_ctlp; 392 int instance = ddi_get_instance(dip); 393 int status; 394 int attach_state; 395 uint32_t cap_status, ahci_version; 396 int intr_types; 397 int i; 398 pci_regspec_t *regs; 399 int regs_length; 400 int rnumber; 401 #if AHCI_DEBUG 402 int speed; 403 #endif 404 405 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 406 407 switch (cmd) { 408 case DDI_ATTACH: 409 break; 410 411 case DDI_RESUME: 412 413 /* 414 * During DDI_RESUME, the hardware state of the device 415 * (power may have been removed from the device) must be 416 * restored, allow pending requests to continue, and 417 * service new requests. 418 */ 419 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 420 mutex_enter(&ahci_ctlp->ahcictl_mutex); 421 422 /* Restart watch thread */ 423 if (ahci_ctlp->ahcictl_timeout_id == 0) 424 ahci_ctlp->ahcictl_timeout_id = timeout( 425 (void (*)(void *))ahci_watchdog_handler, 426 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 427 428 mutex_exit(&ahci_ctlp->ahcictl_mutex); 429 430 /* 431 * Re-initialize the controller and enable the interrupts and 432 * restart all the ports. 433 * 434 * Note that so far we don't support hot-plug during 435 * suspend/resume. 436 */ 437 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 438 AHCIDBG0(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 439 "Failed to initialize the controller " 440 "during DDI_RESUME"); 441 return (DDI_FAILURE); 442 } 443 444 mutex_enter(&ahci_ctlp->ahcictl_mutex); 445 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 446 mutex_exit(&ahci_ctlp->ahcictl_mutex); 447 448 return (DDI_SUCCESS); 449 450 default: 451 return (DDI_FAILURE); 452 } 453 454 attach_state = AHCI_ATTACH_STATE_NONE; 455 456 /* Allocate soft state */ 457 status = ddi_soft_state_zalloc(ahci_statep, instance); 458 if (status != DDI_SUCCESS) { 459 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state", 460 instance); 461 goto err_out; 462 } 463 464 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 465 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 466 ahci_ctlp->ahcictl_dip = dip; 467 468 /* Initialize the cport/port mapping */ 469 for (i = 0; i < AHCI_MAX_PORTS; i++) { 470 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 471 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 472 } 473 474 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 475 476 /* 477 * Now map the AHCI base address; which includes global 478 * registers and port control registers 479 * 480 * According to the spec, the AHCI Base Address is BAR5, 481 * but BAR0-BAR4 are optional, so we need to check which 482 * rnumber is used for BAR5. 483 */ 484 485 /* 486 * search through DDI "reg" property for the AHCI register set 487 */ 488 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 489 DDI_PROP_DONTPASS, "reg", (int **)®s, 490 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 491 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property", 492 instance); 493 goto err_out; 494 } 495 496 /* AHCI Base Address is located at 0x24 offset */ 497 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 498 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 499 == AHCI_PCI_RNUM) 500 break; 501 } 502 503 ddi_prop_free(regs); 504 505 if (rnumber == regs_length) { 506 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set", 507 instance); 508 goto err_out; 509 } 510 511 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 512 513 status = ddi_regs_map_setup(dip, 514 rnumber, 515 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 516 0, 517 0, 518 &accattr, 519 &ahci_ctlp->ahcictl_ahci_acc_handle); 520 if (status != DDI_SUCCESS) { 521 cmn_err(CE_WARN, "!ahci%d: Cannot map register space", 522 instance); 523 goto err_out; 524 } 525 526 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 527 528 /* Get the AHCI version information */ 529 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 530 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 531 532 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance, 533 (ahci_version & 0xffff0000) >> 16, 534 ((ahci_version & 0x0000ff00) >> 4 | 535 (ahci_version & 0x000000ff))); 536 537 /* We don't support controllers whose versions are lower than 1.0 */ 538 if (!(ahci_version & 0xffff0000)) { 539 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower " 540 "than version 1.0", instance); 541 goto err_out; 542 } 543 544 /* Get the HBA capabilities information */ 545 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 546 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 547 548 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 549 cap_status); 550 551 #if AHCI_DEBUG 552 /* Get the interface speed supported by the HBA */ 553 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 554 if (speed == 0x01) { 555 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 556 "hba interface speed support: Gen 1 (1.5Gbps)"); 557 } else if (speed == 0x10) { 558 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 559 "hba interface speed support: Gen 2 (3 Gbps)"); 560 } else if (speed == 0x11) { 561 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 562 "hba interface speed support: Gen 3 (6 Gbps)"); 563 } 564 #endif 565 566 /* Get the number of command slots supported by the HBA */ 567 ahci_ctlp->ahcictl_num_cmd_slots = 568 ((cap_status & AHCI_HBA_CAP_NCS) >> 569 AHCI_HBA_CAP_NCS_SHIFT) + 1; 570 571 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 572 ahci_ctlp->ahcictl_num_cmd_slots); 573 574 /* Get the bit map which indicates ports implemented by the HBA */ 575 ahci_ctlp->ahcictl_ports_implemented = 576 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 577 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 578 579 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 580 ahci_ctlp->ahcictl_ports_implemented); 581 582 /* 583 * According to the AHCI spec, CAP.NP should indicate the maximum 584 * number of ports supported by the HBA silicon, but we found 585 * this value of ICH8 chipset only indicates the number of ports 586 * implemented (exposed) by it. Therefore, the driver should calculate 587 * the potential maximum value by checking PI register, and use 588 * the maximum of this value and CAP.NP. 589 */ 590 ahci_ctlp->ahcictl_num_ports = max( 591 (cap_status & AHCI_HBA_CAP_NP) + 1, 592 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 593 594 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 595 ahci_ctlp->ahcictl_num_ports); 596 597 /* Get the number of implemented ports by the HBA */ 598 ahci_ctlp->ahcictl_num_implemented_ports = 599 ahci_get_num_implemented_ports( 600 ahci_ctlp->ahcictl_ports_implemented); 601 602 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 603 "hba number of implemented ports: %d", 604 ahci_ctlp->ahcictl_num_implemented_ports); 605 606 /* Check whether HBA supports 64bit DMA addressing */ 607 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 608 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 609 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 610 "hba does not support 64-bit addressing"); 611 } 612 613 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 614 != DDI_SUCCESS) { 615 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space", 616 instance); 617 goto err_out; 618 } 619 620 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 621 622 /* Check the pci configuration space, and set caps */ 623 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 624 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed", 625 instance); 626 goto err_out; 627 } 628 629 /* 630 * Disable the whole controller interrupts before adding 631 * interrupt handlers(s). 632 */ 633 ahci_disable_all_intrs(ahci_ctlp); 634 635 /* Get supported interrupt types */ 636 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 637 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed", 638 instance); 639 goto err_out; 640 } 641 642 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 643 "ddi_intr_get_supported_types() returned: 0x%x", 644 intr_types); 645 646 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 647 /* 648 * Try MSI first, but fall back to FIXED if failed 649 */ 650 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 651 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 652 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 653 "Using MSI interrupt type"); 654 goto intr_done; 655 } 656 657 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 658 "MSI registration failed, " 659 "trying FIXED interrupts"); 660 } 661 662 if (intr_types & DDI_INTR_TYPE_FIXED) { 663 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 664 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 665 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 666 "Using FIXED interrupt type"); 667 goto intr_done; 668 } 669 670 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 671 "FIXED interrupt registration failed"); 672 } 673 674 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance); 675 676 goto err_out; 677 678 intr_done: 679 680 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 681 682 /* Initialize the controller mutex */ 683 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 684 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 685 686 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 687 688 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 689 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 690 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 691 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 692 } 693 694 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 695 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 696 sizeof (ahci_prdt_item_t)); 697 698 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 699 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 700 " ahci_cmd_table_size is 0x%x", 701 ahci_dma_prdt_number, ahci_cmd_table_size); 702 703 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 704 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 705 ahci_dma_prdt_number; 706 707 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 708 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 709 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 710 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 711 712 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_32BIT_DMA) { 713 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 714 0xffffffffull; 715 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 716 0xffffffffull; 717 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 718 0xffffffffull; 719 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 720 0xffffffffull; 721 } 722 723 /* Allocate the ports structure */ 724 status = ahci_alloc_ports_state(ahci_ctlp); 725 if (status != AHCI_SUCCESS) { 726 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure", 727 instance); 728 goto err_out; 729 } 730 731 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 732 733 /* 734 * A taskq is created for dealing with events 735 */ 736 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 737 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 738 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event " 739 "handle", instance); 740 goto err_out; 741 } 742 743 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 744 745 /* 746 * Initialize the controller and ports. 747 */ 748 status = ahci_initialize_controller(ahci_ctlp); 749 if (status != AHCI_SUCCESS) { 750 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed", 751 instance); 752 goto err_out; 753 } 754 755 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 756 757 /* Start one thread to check packet timeouts */ 758 ahci_ctlp->ahcictl_timeout_id = timeout( 759 (void (*)(void *))ahci_watchdog_handler, 760 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 761 762 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 763 764 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 765 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed", 766 instance); 767 goto err_out; 768 } 769 770 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 771 772 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 773 774 return (DDI_SUCCESS); 775 776 err_out: 777 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 778 mutex_enter(&ahci_ctlp->ahcictl_mutex); 779 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 780 ahci_ctlp->ahcictl_timeout_id = 0; 781 mutex_exit(&ahci_ctlp->ahcictl_mutex); 782 } 783 784 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 785 ahci_uninitialize_controller(ahci_ctlp); 786 } 787 788 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 789 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 790 } 791 792 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 793 ahci_dealloc_ports_state(ahci_ctlp); 794 } 795 796 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 797 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 798 } 799 800 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 801 ahci_rem_intrs(ahci_ctlp); 802 } 803 804 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 805 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 806 } 807 808 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 809 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 810 } 811 812 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 813 ddi_soft_state_free(ahci_statep, instance); 814 } 815 816 return (DDI_FAILURE); 817 } 818 819 /* 820 * The detach entry point for dev_ops. 821 */ 822 static int 823 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 824 { 825 ahci_ctl_t *ahci_ctlp; 826 int instance; 827 int ret; 828 829 instance = ddi_get_instance(dip); 830 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 831 832 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 833 834 switch (cmd) { 835 case DDI_DETACH: 836 837 /* disable the interrupts for an uninterrupted detach */ 838 mutex_enter(&ahci_ctlp->ahcictl_mutex); 839 ahci_disable_all_intrs(ahci_ctlp); 840 mutex_exit(&ahci_ctlp->ahcictl_mutex); 841 842 /* unregister from the sata framework. */ 843 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 844 if (ret != AHCI_SUCCESS) { 845 mutex_enter(&ahci_ctlp->ahcictl_mutex); 846 ahci_enable_all_intrs(ahci_ctlp); 847 mutex_exit(&ahci_ctlp->ahcictl_mutex); 848 return (DDI_FAILURE); 849 } 850 851 mutex_enter(&ahci_ctlp->ahcictl_mutex); 852 853 /* stop the watchdog handler */ 854 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 855 ahci_ctlp->ahcictl_timeout_id = 0; 856 857 mutex_exit(&ahci_ctlp->ahcictl_mutex); 858 859 /* uninitialize the controller */ 860 ahci_uninitialize_controller(ahci_ctlp); 861 862 /* remove the interrupts */ 863 ahci_rem_intrs(ahci_ctlp); 864 865 /* destroy the taskq */ 866 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 867 868 /* deallocate the ports structures */ 869 ahci_dealloc_ports_state(ahci_ctlp); 870 871 /* destroy mutex */ 872 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 873 874 /* teardown the pci config */ 875 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 876 877 /* remove the reg maps. */ 878 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 879 880 /* free the soft state. */ 881 ddi_soft_state_free(ahci_statep, instance); 882 883 return (DDI_SUCCESS); 884 885 case DDI_SUSPEND: 886 887 /* 888 * The steps associated with suspension must include putting 889 * the underlying device into a quiescent state so that it 890 * will not generate interrupts or modify or access memory. 891 */ 892 mutex_enter(&ahci_ctlp->ahcictl_mutex); 893 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 894 mutex_exit(&ahci_ctlp->ahcictl_mutex); 895 return (DDI_SUCCESS); 896 } 897 898 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 899 900 /* stop the watchdog handler */ 901 if (ahci_ctlp->ahcictl_timeout_id) { 902 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 903 ahci_ctlp->ahcictl_timeout_id = 0; 904 } 905 906 mutex_exit(&ahci_ctlp->ahcictl_mutex); 907 908 /* 909 * drain the taskq 910 */ 911 ddi_taskq_wait(ahci_ctlp->ahcictl_event_taskq); 912 913 /* 914 * Disable the interrupts and stop all the ports. 915 */ 916 ahci_uninitialize_controller(ahci_ctlp); 917 918 return (DDI_SUCCESS); 919 920 default: 921 return (DDI_FAILURE); 922 } 923 } 924 925 /* 926 * The info entry point for dev_ops. 927 * 928 */ 929 static int 930 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 931 void *arg, void **result) 932 { 933 #ifndef __lock_lint 934 _NOTE(ARGUNUSED(dip)) 935 #endif /* __lock_lint */ 936 937 ahci_ctl_t *ahci_ctlp; 938 int instance; 939 dev_t dev; 940 941 dev = (dev_t)arg; 942 instance = getminor(dev); 943 944 switch (infocmd) { 945 case DDI_INFO_DEVT2DEVINFO: 946 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 947 if (ahci_ctlp != NULL) { 948 *result = ahci_ctlp->ahcictl_dip; 949 return (DDI_SUCCESS); 950 } else { 951 *result = NULL; 952 return (DDI_FAILURE); 953 } 954 case DDI_INFO_DEVT2INSTANCE: 955 *(int *)result = instance; 956 break; 957 default: 958 break; 959 } 960 961 return (DDI_SUCCESS); 962 } 963 964 /* 965 * Registers the ahci with sata framework. 966 */ 967 static int 968 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 969 { 970 struct sata_hba_tran *sata_hba_tran; 971 972 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 973 "ahci_register_sata_hba_tran enter"); 974 975 mutex_enter(&ahci_ctlp->ahcictl_mutex); 976 977 /* Allocate memory for the sata_hba_tran */ 978 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 979 980 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 981 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 982 sata_hba_tran->sata_tran_hba_dma_attr = 983 &ahci_ctlp->ahcictl_buffer_dma_attr; 984 985 /* Report the number of implemented ports */ 986 sata_hba_tran->sata_tran_hba_num_cports = 987 ahci_ctlp->ahcictl_num_implemented_ports; 988 989 /* Support ATAPI device */ 990 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 991 992 /* Get the data transfer capability for PIO command by the HBA */ 993 if (cap_status & AHCI_HBA_CAP_PMD) { 994 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 995 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 996 "DRQ block data transfer for PIO command protocol"); 997 } else { 998 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA only supports single " 999 "DRQ block data transfer for PIO command protocol"); 1000 } 1001 1002 /* 1003 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 1004 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 1005 * QUEUED (EXT), and SERVICE commands). Queued operations are 1006 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 1007 * QUEUED commands when the HBA and device support native command 1008 * queuing(NCQ). 1009 * 1010 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 1011 * CAP register of the HBA indicates NCQ is supported. 1012 * 1013 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 1014 * set because the previous register content of PxCI can be re-written 1015 * in the register write. 1016 */ 1017 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 1018 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 1019 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 1020 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 1021 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 1022 "Command Queuing"); 1023 } 1024 1025 /* Report the number of command slots */ 1026 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1027 1028 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1029 sata_hba_tran->sata_tran_start = ahci_tran_start; 1030 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1031 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1032 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1033 #ifdef __lock_lint 1034 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1035 #endif 1036 /* 1037 * When SATA framework adds support for pwrmgt the 1038 * pwrmgt_ops needs to be updated 1039 */ 1040 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1041 sata_hba_tran->sata_tran_ioctl = NULL; 1042 1043 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1044 1045 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1046 1047 /* Attach it to SATA framework */ 1048 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1049 != DDI_SUCCESS) { 1050 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1051 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1052 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1053 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1054 return (AHCI_FAILURE); 1055 } 1056 1057 return (AHCI_SUCCESS); 1058 } 1059 1060 /* 1061 * Unregisters the ahci with sata framework. 1062 */ 1063 static int 1064 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1065 { 1066 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1067 "ahci_unregister_sata_hba_tran enter"); 1068 1069 /* Detach from the SATA framework. */ 1070 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1071 DDI_SUCCESS) { 1072 return (AHCI_FAILURE); 1073 } 1074 1075 /* Deallocate sata_hba_tran. */ 1076 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1077 sizeof (sata_hba_tran_t)); 1078 1079 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1080 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1081 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1082 1083 return (AHCI_SUCCESS); 1084 } 1085 1086 /* 1087 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1088 * port status registers and an attached device type via sata_device 1089 * structure. 1090 * 1091 * We return the cached information from a previous hardware probe. The 1092 * actual hardware probing itself was done either from within 1093 * ahci_initialize_controller() during the driver attach or from a phy 1094 * ready change interrupt handler. 1095 */ 1096 static int 1097 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1098 { 1099 ahci_ctl_t *ahci_ctlp; 1100 ahci_port_t *ahci_portp; 1101 uint8_t cport = sd->satadev_addr.cport; 1102 uint8_t pmport = sd->satadev_addr.pmport; 1103 uint8_t qual = sd->satadev_addr.qual; 1104 uint8_t device_type; 1105 uint32_t port_state; 1106 uint8_t port; 1107 1108 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1109 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1110 1111 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1112 "ahci_tran_probe_port enter: cport: %d, " 1113 "pmport: %d, qual: %d", cport, pmport, qual); 1114 1115 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1116 1117 mutex_enter(&ahci_portp->ahciport_mutex); 1118 1119 port_state = ahci_portp->ahciport_port_state; 1120 switch (port_state) { 1121 1122 case SATA_PSTATE_FAILED: 1123 sd->satadev_state = SATA_PSTATE_FAILED; 1124 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1125 "ahci_tran_probe_port: port %d PORT FAILED", port); 1126 goto out; 1127 1128 case SATA_PSTATE_SHUTDOWN: 1129 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1130 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1131 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1132 goto out; 1133 1134 case SATA_PSTATE_PWROFF: 1135 sd->satadev_state = SATA_PSTATE_PWROFF; 1136 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1137 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1138 goto out; 1139 1140 case SATA_PSTATE_PWRON: 1141 sd->satadev_state = SATA_PSTATE_PWRON; 1142 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1143 "ahci_tran_probe_port: port %d PORT PWRON", port); 1144 break; 1145 1146 default: 1147 sd->satadev_state = port_state; 1148 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1149 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1150 port, port_state); 1151 break; 1152 } 1153 1154 device_type = ahci_portp->ahciport_device_type; 1155 1156 switch (device_type) { 1157 1158 case SATA_DTYPE_ATADISK: 1159 sd->satadev_type = SATA_DTYPE_ATADISK; 1160 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1161 "ahci_tran_probe_port: port %d DISK found", port); 1162 break; 1163 1164 case SATA_DTYPE_ATAPICD: 1165 sd->satadev_type = SATA_DTYPE_ATAPICD; 1166 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1167 "ahci_tran_probe_port: port %d ATAPI found", port); 1168 break; 1169 1170 case SATA_DTYPE_PMULT: 1171 sd->satadev_type = SATA_DTYPE_PMULT; 1172 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1173 "ahci_tran_probe_port: port %d Port Multiplier found", 1174 port); 1175 break; 1176 1177 case SATA_DTYPE_UNKNOWN: 1178 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1179 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1180 "ahci_tran_probe_port: port %d Unknown device found", port); 1181 break; 1182 1183 default: 1184 /* we don't support any other device types */ 1185 sd->satadev_type = SATA_DTYPE_NONE; 1186 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1187 "ahci_tran_probe_port: port %d No device found", port); 1188 break; 1189 } 1190 1191 out: 1192 ahci_update_sata_registers(ahci_ctlp, port, sd); 1193 mutex_exit(&ahci_portp->ahciport_mutex); 1194 1195 return (SATA_SUCCESS); 1196 } 1197 1198 /* 1199 * There are four operation modes in sata framework: 1200 * SATA_OPMODE_INTERRUPTS 1201 * SATA_OPMODE_POLLING 1202 * SATA_OPMODE_ASYNCH 1203 * SATA_OPMODE_SYNCH 1204 * 1205 * Their combined meanings as following: 1206 * 1207 * SATA_OPMODE_SYNCH 1208 * The command has to be completed before sata_tran_start functions returns. 1209 * Either interrupts or polling could be used - it's up to the driver. 1210 * Mode used currently for internal, sata-module initiated operations. 1211 * 1212 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1213 * It is the same as the one above. 1214 * 1215 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1216 * The command has to be completed before sata_tran_start function returns. 1217 * No interrupt used, polling only. This should be the mode used for scsi 1218 * packets with FLAG_NOINTR. 1219 * 1220 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1221 * The command may be queued (callback function specified). Interrupts could 1222 * be used. It's normal operation mode. 1223 */ 1224 /* 1225 * Called by sata framework to transport a sata packet down stream. 1226 */ 1227 static int 1228 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1229 { 1230 ahci_ctl_t *ahci_ctlp; 1231 ahci_port_t *ahci_portp; 1232 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1233 uint8_t port; 1234 1235 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1236 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1237 1238 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1239 "ahci_tran_start enter: cport %d satapkt 0x%p", 1240 cport, (void *)spkt); 1241 1242 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1243 1244 mutex_enter(&ahci_portp->ahciport_mutex); 1245 1246 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1247 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1248 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1249 /* 1250 * In case the targer driver would send the packet before 1251 * sata framework can have the opportunity to process those 1252 * event reports. 1253 */ 1254 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1255 spkt->satapkt_device.satadev_state = 1256 ahci_portp->ahciport_port_state; 1257 ahci_update_sata_registers(ahci_ctlp, port, 1258 &spkt->satapkt_device); 1259 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1260 "ahci_tran_start returning PORT_ERROR while " 1261 "port in FAILED/SHUTDOWN/PWROFF state: " 1262 "port: %d", port); 1263 mutex_exit(&ahci_portp->ahciport_mutex); 1264 return (SATA_TRAN_PORT_ERROR); 1265 } 1266 1267 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1268 /* 1269 * ahci_intr_phyrdy_change() may have rendered it to 1270 * SATA_DTYPE_NONE. 1271 */ 1272 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1273 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1274 spkt->satapkt_device.satadev_state = 1275 ahci_portp->ahciport_port_state; 1276 ahci_update_sata_registers(ahci_ctlp, port, 1277 &spkt->satapkt_device); 1278 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1279 "ahci_tran_start returning PORT_ERROR while " 1280 "no device attached: port: %d", port); 1281 mutex_exit(&ahci_portp->ahciport_mutex); 1282 return (SATA_TRAN_PORT_ERROR); 1283 } 1284 1285 /* 1286 * SATA HBA driver should remember that a device was reset and it 1287 * is supposed to reject any packets which do not specify either 1288 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1289 * 1290 * This is to prevent a race condition when a device was arbitrarily 1291 * reset by the HBA driver (and lost it's setting) and a target 1292 * driver sending some commands to a device before the sata framework 1293 * has a chance to restore the device setting (such as cache enable/ 1294 * disable or other resettable stuff). 1295 */ 1296 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1297 ahci_portp->ahciport_reset_in_progress = 0; 1298 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1299 "ahci_tran_start clearing the " 1300 "reset_in_progress for port: %d", port); 1301 } 1302 1303 if (ahci_portp->ahciport_reset_in_progress && 1304 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1305 ! ddi_in_panic()) { 1306 spkt->satapkt_reason = SATA_PKT_BUSY; 1307 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1308 "ahci_tran_start returning BUSY while " 1309 "reset in progress: port: %d", port); 1310 mutex_exit(&ahci_portp->ahciport_mutex); 1311 return (SATA_TRAN_BUSY); 1312 } 1313 1314 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1315 spkt->satapkt_reason = SATA_PKT_BUSY; 1316 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1317 "ahci_tran_start returning BUSY while " 1318 "mopping in progress: port: %d", port); 1319 mutex_exit(&ahci_portp->ahciport_mutex); 1320 return (SATA_TRAN_BUSY); 1321 } 1322 1323 if (spkt->satapkt_op_mode & 1324 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1325 /* We need to do the sync start now */ 1326 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1327 spkt) == AHCI_FAILURE) { 1328 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1329 "return QUEUE_FULL: port %d", port); 1330 mutex_exit(&ahci_portp->ahciport_mutex); 1331 return (SATA_TRAN_QUEUE_FULL); 1332 } 1333 } else { 1334 /* Async start, using interrupt */ 1335 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1336 == AHCI_FAILURE) { 1337 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1338 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1339 "returning QUEUE_FULL: port %d", port); 1340 mutex_exit(&ahci_portp->ahciport_mutex); 1341 return (SATA_TRAN_QUEUE_FULL); 1342 } 1343 } 1344 1345 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1346 "sata tran accepted: port %d", port); 1347 1348 mutex_exit(&ahci_portp->ahciport_mutex); 1349 return (SATA_TRAN_ACCEPTED); 1350 } 1351 1352 /* 1353 * SATA_OPMODE_SYNCH flag is set 1354 * 1355 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1356 * without interrupt, otherwise we can still use the interrupt. 1357 * 1358 * WARNING!!! ahciport_mutex should be acquired before the function 1359 * is called. 1360 */ 1361 static int 1362 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1363 uint8_t port, sata_pkt_t *spkt) 1364 { 1365 int pkt_timeout_ticks; 1366 uint32_t timeout_tags; 1367 int rval; 1368 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1369 1370 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1371 "port %d spkt 0x%p", port, spkt); 1372 1373 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1374 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1375 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1376 port, spkt)) == AHCI_FAILURE) { 1377 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1378 return (rval); 1379 } 1380 1381 pkt_timeout_ticks = 1382 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1383 1384 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1385 mutex_exit(&ahci_portp->ahciport_mutex); 1386 1387 /* Simulate the interrupt */ 1388 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1389 1390 drv_usecwait(AHCI_1MS_USECS); 1391 1392 mutex_enter(&ahci_portp->ahciport_mutex); 1393 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1394 if (pkt_timeout_ticks < 0) { 1395 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start " 1396 "port %d satapkt 0x%p timed out\n", 1397 instance, port, (void *)spkt); 1398 timeout_tags = (0x1 << rval); 1399 mutex_exit(&ahci_portp->ahciport_mutex); 1400 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1401 port, timeout_tags); 1402 mutex_enter(&ahci_portp->ahciport_mutex); 1403 } 1404 } 1405 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1406 return (AHCI_SUCCESS); 1407 1408 } else { 1409 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1410 port, spkt)) == AHCI_FAILURE) 1411 return (rval); 1412 1413 #if AHCI_DEBUG 1414 /* 1415 * Note that the driver always uses the slot 0 to deliver 1416 * REQUEST SENSE or READ LOG EXT command 1417 */ 1418 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1419 ASSERT(rval == 0); 1420 #endif 1421 1422 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1423 cv_wait(&ahci_portp->ahciport_cv, 1424 &ahci_portp->ahciport_mutex); 1425 1426 return (AHCI_SUCCESS); 1427 } 1428 } 1429 1430 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1431 if (satapkt) { \ 1432 satapkt->satapkt_reason = reason; \ 1433 /* \ 1434 * We set the satapkt_reason in both sync and \ 1435 * non-sync cases. \ 1436 */ \ 1437 } \ 1438 if (satapkt && \ 1439 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1440 satapkt->satapkt_comp) { \ 1441 mutex_exit(&ahci_portp->ahciport_mutex); \ 1442 (*satapkt->satapkt_comp)(satapkt); \ 1443 mutex_enter(&ahci_portp->ahciport_mutex); \ 1444 } else { \ 1445 if (satapkt && \ 1446 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1447 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1448 cv_signal(&ahci_portp->ahciport_cv); \ 1449 } 1450 1451 /* 1452 * Searches for and claims a free command slot. 1453 * 1454 * Returns: 1455 * 1456 * AHCI_FAILURE if failed 1457 * 1. if no empty slot left 1458 * 2. non-queued command requested while queued command(s) is outstanding 1459 * 3. queued command requested whild non-queued command(s) is outstanding 1460 * 4. HBA doesn't support multiple-use of command list while already a 1461 * non-queued command is oustanding 1462 * 1463 * claimed slot number if succeeded 1464 * 1465 * NOTE: it will always return slot 0 during error recovery process for 1466 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1467 * 1468 * WARNING!!! ahciport_mutex should be acquired before the function 1469 * is called. 1470 */ 1471 /*ARGSUSED*/ 1472 static int 1473 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1474 ahci_port_t *ahci_portp, int command_type) 1475 { 1476 uint32_t free_slots; 1477 int slot; 1478 1479 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1480 "ahciport_pending_tags = 0x%x " 1481 "ahciport_pending_ncq_tags = 0x%x", 1482 ahci_portp->ahciport_pending_tags, 1483 ahci_portp->ahciport_pending_ncq_tags); 1484 1485 /* 1486 * According to the AHCI spec, system software is responsible to 1487 * ensure that queued and non-queued commands are not mixed in 1488 * the command list. 1489 */ 1490 if (command_type == AHCI_NON_NCQ_CMD) { 1491 /* Non-NCQ command request */ 1492 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1493 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1494 "ahci_claim_free_slot: there is still pending " 1495 "queued command(s) in the command list, " 1496 "so no available slot for the non-queued " 1497 "command"); 1498 return (AHCI_FAILURE); 1499 } 1500 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1501 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1502 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1503 "ahci_claim_free_slot: HBA cannot support multiple-" 1504 "use of the command list for non-queued commands"); 1505 return (AHCI_FAILURE); 1506 } 1507 free_slots = (~ahci_portp->ahciport_pending_tags) & 1508 AHCI_SLOT_MASK(ahci_ctlp); 1509 } else if (command_type == AHCI_NCQ_CMD) { 1510 /* NCQ command request */ 1511 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1512 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1513 "ahci_claim_free_slot: there is still pending " 1514 "non-queued command(s) in the command list, " 1515 "so no available slot for the queued command"); 1516 return (AHCI_FAILURE); 1517 } 1518 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1519 AHCI_NCQ_SLOT_MASK(ahci_portp); 1520 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1521 /* Error retrieval command request */ 1522 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1523 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1524 "SENSE or READ LOG EXT command"); 1525 slot = 0; 1526 goto out; 1527 } 1528 1529 slot = ddi_ffs(free_slots) - 1; 1530 if (slot == -1) { 1531 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1532 "ahci_claim_free_slot: no empty slots"); 1533 return (AHCI_FAILURE); 1534 } 1535 1536 /* 1537 * According to the AHCI spec, to allow a simple mechanism for the 1538 * HBA to map command list slots to queue entries, software must 1539 * match the tag number it uses to the slot it is placing the command 1540 * in. For example, if a queued command is placed in slot 5, the tag 1541 * for that command must be 5. 1542 */ 1543 if (command_type == AHCI_NCQ_CMD) { 1544 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1545 } 1546 1547 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1548 1549 out: 1550 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1551 "ahci_claim_free_slot: found slot: 0x%x", slot); 1552 1553 return (slot); 1554 } 1555 1556 /* 1557 * Builds the Command Table for the sata packet and delivers it to controller. 1558 * 1559 * Returns: 1560 * slot number if we can obtain a slot successfully 1561 * otherwise, return AHCI_FAILURE 1562 * 1563 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1564 */ 1565 static int 1566 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1567 uint8_t port, sata_pkt_t *spkt) 1568 { 1569 int cmd_slot; 1570 sata_cmd_t *scmd; 1571 ahci_fis_h2d_register_t *h2d_register_fisp; 1572 ahci_cmd_table_t *cmd_table; 1573 ahci_cmd_header_t *cmd_header; 1574 int ncookies; 1575 int i; 1576 int command_type = AHCI_NON_NCQ_CMD; 1577 int ncq_qdepth; 1578 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1579 #if AHCI_DEBUG 1580 uint32_t *ptr; 1581 uint8_t *ptr2; 1582 #endif 1583 1584 spkt->satapkt_reason = SATA_PKT_BUSY; 1585 1586 scmd = &spkt->satapkt_cmd; 1587 1588 /* Check if the command is a NCQ command */ 1589 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1590 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1591 command_type = AHCI_NCQ_CMD; 1592 1593 /* 1594 * When NCQ is support, system software must determine the 1595 * maximum tag allowed by the device and the HBA, and it 1596 * must use a value not beyond of the lower bound of the two. 1597 * 1598 * Sata module is going to calculate the qdepth and send 1599 * down to HBA driver via sata_cmd. 1600 */ 1601 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1602 1603 /* 1604 * At the moment, the driver doesn't support the dynamic 1605 * setting of the maximum ncq depth, and the value can be 1606 * set either during the attach or after hot-plug insertion. 1607 */ 1608 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1609 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1610 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1611 "ahci_deliver_satapkt: port %d the max tags for " 1612 "NCQ command is %d", port, ncq_qdepth); 1613 } else { 1614 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1615 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt" 1616 " port %d the max tag for NCQ command is " 1617 "requested to change from %d to %d, at the" 1618 " moment the driver doesn't support the " 1619 "dynamic change so it's going to " 1620 "still use the previous tag value", 1621 instance, port, 1622 ahci_portp->ahciport_max_ncq_tags, 1623 ncq_qdepth); 1624 } 1625 } 1626 } 1627 1628 /* Check if the command is an error retrieval command */ 1629 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1630 command_type = AHCI_ERR_RETRI_CMD; 1631 1632 /* Check if there is an empty command slot */ 1633 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1634 if (cmd_slot == AHCI_FAILURE) { 1635 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1636 return (AHCI_FAILURE); 1637 } 1638 1639 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1640 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1641 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1642 cmd_slot, port, (void *)spkt); 1643 1644 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1645 bzero((void *)cmd_table, ahci_cmd_table_size); 1646 1647 /* For data transfer operations, it is the H2D Register FIS */ 1648 h2d_register_fisp = 1649 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1650 1651 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1652 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1653 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1654 SET_FIS_PMP(h2d_register_fisp, 1655 spkt->satapkt_device.satadev_addr.pmport); 1656 } 1657 1658 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1659 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1660 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1661 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1662 1663 switch (scmd->satacmd_addr_type) { 1664 1665 case 0: 1666 /* 1667 * satacmd_addr_type will be 0 for the commands below: 1668 * ATAPI command 1669 * SATAC_IDLE_IM 1670 * SATAC_STANDBY_IM 1671 * SATAC_DOWNLOAD_MICROCODE 1672 * SATAC_FLUSH_CACHE 1673 * SATAC_SET_FEATURES 1674 * SATAC_SMART 1675 * SATAC_ID_PACKET_DEVICE 1676 * SATAC_ID_DEVICE 1677 */ 1678 /* fallthrough */ 1679 1680 case ATA_ADDR_LBA: 1681 /* fallthrough */ 1682 1683 case ATA_ADDR_LBA28: 1684 /* LBA[7:0] */ 1685 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1686 1687 /* LBA[15:8] */ 1688 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1689 1690 /* LBA[23:16] */ 1691 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1692 1693 /* LBA [27:24] (also called dev_head) */ 1694 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1695 1696 break; 1697 1698 case ATA_ADDR_LBA48: 1699 /* LBA[7:0] */ 1700 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1701 1702 /* LBA[15:8] */ 1703 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1704 1705 /* LBA[23:16] */ 1706 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1707 1708 /* LBA [31:24] */ 1709 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1710 scmd->satacmd_lba_low_msb); 1711 1712 /* LBA [39:32] */ 1713 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1714 scmd->satacmd_lba_mid_msb); 1715 1716 /* LBA [47:40] */ 1717 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1718 scmd->satacmd_lba_high_msb); 1719 1720 /* Set dev_head */ 1721 SET_FIS_DEV_HEAD(h2d_register_fisp, 1722 scmd->satacmd_device_reg); 1723 1724 /* Set the extended sector count and features */ 1725 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1726 scmd->satacmd_sec_count_msb); 1727 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1728 scmd->satacmd_features_reg_ext); 1729 break; 1730 } 1731 1732 /* 1733 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1734 * filled into features field, and sector count 8:15 is filled into 1735 * features (exp) field. TAG is filled into sector field. 1736 */ 1737 if (command_type == AHCI_NCQ_CMD) { 1738 SET_FIS_FEATURES(h2d_register_fisp, 1739 scmd->satacmd_sec_count_lsb); 1740 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1741 scmd->satacmd_sec_count_msb); 1742 1743 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1744 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1745 } 1746 1747 ncookies = scmd->satacmd_num_dma_cookies; 1748 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1749 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1750 ncookies, ahci_dma_prdt_number); 1751 1752 ASSERT(ncookies <= ahci_dma_prdt_number); 1753 1754 /* *** now fill the scatter gather list ******* */ 1755 for (i = 0; i < ncookies; i++) { 1756 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1757 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1758 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1759 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1760 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1761 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1762 } 1763 1764 /* The ACMD field is filled in for ATAPI command */ 1765 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1766 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1767 SATA_ATAPI_MAX_CDB_LEN); 1768 } 1769 1770 /* Set Command Header in Command List */ 1771 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1772 BZERO_DESCR_INFO(cmd_header); 1773 BZERO_PRD_BYTE_COUNT(cmd_header); 1774 1775 /* Set the number of entries in the PRD table */ 1776 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1777 1778 /* Set the length of the command in the CFIS area */ 1779 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1780 1781 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1782 "sata_data_direction = 0x%x", 1783 scmd->satacmd_flags.sata_data_direction); 1784 1785 /* Set A bit if it is an ATAPI command */ 1786 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1787 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1788 1789 /* Set W bit if data is going to the device */ 1790 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1791 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1792 1793 /* 1794 * Set the prefetchable bit - this bit is only valid if the PRDTL 1795 * field is non-zero or the ATAPI 'A' bit is set in the command 1796 * header. This bit cannot be set when using native command 1797 * queuing commands or when using FIS-based switching with a Port 1798 * multiplier. 1799 */ 1800 if (command_type != AHCI_NCQ_CMD) 1801 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1802 1803 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1804 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1805 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1806 1807 /* 1808 * We are overloading satapkt_hba_driver_private with 1809 * watched_cycle count. 1810 */ 1811 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1812 1813 #if AHCI_DEBUG 1814 /* Dump the command header and table */ 1815 AHCIDBG0(AHCIDBG_COMMAND, ahci_ctlp, "\n"); 1816 AHCIDBG3(AHCIDBG_COMMAND, ahci_ctlp, 1817 "Command header&table for spkt 0x%p cmd_reg 0x%x port %d", 1818 spkt, scmd->satacmd_cmd_reg, port); 1819 ptr = (uint32_t *)cmd_header; 1820 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1821 " Command Header:%8x %8x %8x %8x", 1822 ptr[0], ptr[1], ptr[2], ptr[3]); 1823 1824 /* Dump the H2D register FIS */ 1825 ptr = (uint32_t *)h2d_register_fisp; 1826 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1827 " Command FIS: %8x %8x %8x %8x", 1828 ptr[0], ptr[1], ptr[2], ptr[3]); 1829 1830 /* Dump the ACMD register FIS */ 1831 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1832 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1833 if (ahci_debug_flags & AHCIDBG_COMMAND) 1834 ahci_log(ahci_ctlp, CE_WARN, 1835 " ATAPI command: %2x %2x %2x %2x " 1836 "%2x %2x %2x %2x", 1837 ptr2[8 * i], ptr2[8 * i + 1], 1838 ptr2[8 * i + 2], ptr2[8 * i + 3], 1839 ptr2[8 * i + 4], ptr2[8 * i + 5], 1840 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1841 1842 /* Dump the PRDT */ 1843 for (i = 0; i < ncookies; i++) { 1844 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1845 AHCIDBG5(AHCIDBG_COMMAND, ahci_ctlp, 1846 " Cookie %d: %8x %8x %8x %8x", 1847 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1848 } 1849 #endif 1850 1851 (void) ddi_dma_sync( 1852 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1853 0, 1854 ahci_cmd_table_size, 1855 DDI_DMA_SYNC_FORDEV); 1856 1857 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1858 cmd_slot * sizeof (ahci_cmd_header_t), 1859 sizeof (ahci_cmd_header_t), 1860 DDI_DMA_SYNC_FORDEV); 1861 1862 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1863 if (command_type == AHCI_NCQ_CMD) { 1864 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1865 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1866 (0x1 << cmd_slot)); 1867 } 1868 1869 /* Indicate to the HBA that a command is active. */ 1870 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1871 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1872 (0x1 << cmd_slot)); 1873 1874 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1875 "exit: port %d", port); 1876 1877 return (cmd_slot); 1878 } 1879 1880 /* 1881 * Called by the sata framework to abort the previously sent packet(s). 1882 * 1883 * Reset device to abort commands. 1884 */ 1885 static int 1886 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1887 { 1888 ahci_ctl_t *ahci_ctlp; 1889 ahci_port_t *ahci_portp; 1890 uint32_t slot_status = 0; 1891 uint32_t aborted_tags = 0; 1892 uint32_t finished_tags = 0; 1893 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1894 uint8_t port; 1895 int tmp_slot; 1896 int instance = ddi_get_instance(dip); 1897 1898 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 1899 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1900 1901 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1902 "ahci_tran_abort enter: port %d", port); 1903 1904 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1905 mutex_enter(&ahci_portp->ahciport_mutex); 1906 1907 /* 1908 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1909 * commands are being mopped, therefore there is nothing else to do 1910 */ 1911 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1912 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1913 "ahci_tran_abort: port %d is in " 1914 "mopping process, so just return directly ", port); 1915 mutex_exit(&ahci_portp->ahciport_mutex); 1916 return (SATA_SUCCESS); 1917 } 1918 1919 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1920 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1921 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1922 /* 1923 * In case the targer driver would send the request before 1924 * sata framework can have the opportunity to process those 1925 * event reports. 1926 */ 1927 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1928 spkt->satapkt_device.satadev_state = 1929 ahci_portp->ahciport_port_state; 1930 ahci_update_sata_registers(ahci_ctlp, port, 1931 &spkt->satapkt_device); 1932 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1933 "ahci_tran_abort returning SATA_FAILURE while " 1934 "port in FAILED/SHUTDOWN/PWROFF state: " 1935 "port: %d", port); 1936 mutex_exit(&ahci_portp->ahciport_mutex); 1937 return (SATA_FAILURE); 1938 } 1939 1940 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1941 /* 1942 * ahci_intr_phyrdy_change() may have rendered it to 1943 * AHCI_PORT_TYPE_NODEV. 1944 */ 1945 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1946 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1947 spkt->satapkt_device.satadev_state = 1948 ahci_portp->ahciport_port_state; 1949 ahci_update_sata_registers(ahci_ctlp, port, 1950 &spkt->satapkt_device); 1951 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1952 "ahci_tran_abort returning SATA_FAILURE while " 1953 "no device attached: port: %d", port); 1954 mutex_exit(&ahci_portp->ahciport_mutex); 1955 return (SATA_FAILURE); 1956 } 1957 1958 if (flag == SATA_ABORT_ALL_PACKETS) { 1959 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1960 aborted_tags = ahci_portp->ahciport_pending_tags; 1961 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1962 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 1963 1964 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets", 1965 instance, port); 1966 } else { 1967 aborted_tags = 0xffffffff; 1968 /* 1969 * Aborting one specific packet, first search the 1970 * ahciport_slot_pkts[] list for matching spkt. 1971 */ 1972 for (tmp_slot = 0; 1973 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 1974 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 1975 aborted_tags = (0x1 << tmp_slot); 1976 break; 1977 } 1978 } 1979 1980 if (aborted_tags == 0xffffffff) { 1981 /* request packet is not on the pending list */ 1982 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1983 "Cannot find the aborting pkt 0x%p on the " 1984 "pending list", (void *)spkt); 1985 ahci_update_sata_registers(ahci_ctlp, port, 1986 &spkt->satapkt_device); 1987 mutex_exit(&ahci_portp->ahciport_mutex); 1988 return (SATA_FAILURE); 1989 } 1990 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p", 1991 instance, port, (void *)spkt); 1992 } 1993 1994 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1995 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1996 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1997 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1998 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1999 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2000 2001 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2002 ahci_portp->ahciport_mop_in_progress++; 2003 2004 /* 2005 * To abort the packet(s), first we are trying to clear PxCMD.ST 2006 * to stop the port, and if the port can be stopped 2007 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 2008 * then we just send back the aborted packet(s) with ABORTED flag 2009 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 2010 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 2011 * perform a COMRESET. 2012 */ 2013 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2014 ahci_portp, port, NULL, NULL); 2015 2016 /* 2017 * Compute which have finished and which need to be retried. 2018 * 2019 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 2020 * minus the slot_status. The aborted_tags has to be deducted by 2021 * finished_tags since we can't possibly abort a tag which had finished 2022 * already. 2023 */ 2024 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2025 finished_tags = ahci_portp->ahciport_pending_tags & 2026 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2027 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2028 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2029 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2030 2031 aborted_tags &= ~finished_tags; 2032 2033 ahci_mop_commands(ahci_ctlp, 2034 ahci_portp, 2035 port, 2036 slot_status, 2037 0, /* failed tags */ 2038 0, /* timeout tags */ 2039 aborted_tags, 2040 0); /* reset tags */ 2041 2042 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2043 mutex_exit(&ahci_portp->ahciport_mutex); 2044 2045 return (SATA_SUCCESS); 2046 } 2047 2048 /* 2049 * Used to do device reset and reject all the pending packets on a device 2050 * during the reset operation. 2051 * 2052 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2053 */ 2054 static int 2055 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2056 ahci_port_t *ahci_portp, uint8_t port) 2057 { 2058 uint32_t slot_status = 0; 2059 uint32_t reset_tags = 0; 2060 uint32_t finished_tags = 0; 2061 sata_device_t sdevice; 2062 int ret; 2063 2064 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2065 "ahci_reset_device_reject_pkts on port: %d", port); 2066 2067 /* 2068 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2069 * commands are being mopped, therefore there is nothing else to do 2070 */ 2071 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2072 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2073 "ahci_reset_device_reject_pkts: port %d is in " 2074 "mopping process, so return directly ", port); 2075 return (SATA_SUCCESS); 2076 } 2077 2078 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2079 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2080 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2081 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2082 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2083 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2084 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2085 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2086 } 2087 2088 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2089 != AHCI_SUCCESS) { 2090 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2091 "Try to do a port reset after software " 2092 "reset failed", port); 2093 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2094 if (ret != AHCI_SUCCESS) { 2095 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2096 "ahci_reset_device_reject_pkts: port %d " 2097 "failed", port); 2098 return (SATA_FAILURE); 2099 } 2100 } 2101 /* Set the reset in progress flag */ 2102 ahci_portp->ahciport_reset_in_progress = 1; 2103 2104 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2105 ahci_portp->ahciport_mop_in_progress++; 2106 2107 /* Indicate to the framework that a reset has happened */ 2108 bzero((void *)&sdevice, sizeof (sata_device_t)); 2109 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2110 sdevice.satadev_addr.pmport = 0; 2111 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2112 2113 sdevice.satadev_state = SATA_DSTATE_RESET | 2114 SATA_DSTATE_PWR_ACTIVE; 2115 mutex_exit(&ahci_portp->ahciport_mutex); 2116 sata_hba_event_notify( 2117 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2118 &sdevice, 2119 SATA_EVNT_DEVICE_RESET); 2120 mutex_enter(&ahci_portp->ahciport_mutex); 2121 2122 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2123 "port %d sending event up: SATA_EVNT_RESET", port); 2124 2125 /* Next try to mop the pending commands */ 2126 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2127 finished_tags = ahci_portp->ahciport_pending_tags & 2128 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2129 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2130 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2131 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2132 2133 reset_tags &= ~finished_tags; 2134 2135 ahci_mop_commands(ahci_ctlp, 2136 ahci_portp, 2137 port, 2138 slot_status, 2139 0, /* failed tags */ 2140 0, /* timeout tags */ 2141 0, /* aborted tags */ 2142 reset_tags); /* reset tags */ 2143 2144 return (SATA_SUCCESS); 2145 } 2146 2147 /* 2148 * Used to do port reset and reject all the pending packets on a port during 2149 * the reset operation. 2150 * 2151 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2152 */ 2153 static int 2154 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2155 ahci_port_t *ahci_portp, uint8_t port) 2156 { 2157 uint32_t slot_status = 0; 2158 uint32_t reset_tags = 0; 2159 uint32_t finished_tags = 0; 2160 2161 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2162 "ahci_reset_port_reject_pkts on port: %d", port); 2163 2164 /* 2165 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2166 * commands are being mopped, therefore there is nothing else to do 2167 */ 2168 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2169 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2170 "ahci_reset_port_reject_pkts: port %d is in " 2171 "mopping process, so return directly ", port); 2172 return (SATA_SUCCESS); 2173 } 2174 2175 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2176 ahci_portp->ahciport_mop_in_progress++; 2177 2178 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2179 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2180 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2181 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2182 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2183 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2184 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2185 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2186 } 2187 2188 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2189 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2190 NULL) != AHCI_SUCCESS) 2191 return (SATA_FAILURE); 2192 2193 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2194 finished_tags = ahci_portp->ahciport_pending_tags & 2195 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2196 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2197 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2198 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2199 2200 reset_tags &= ~finished_tags; 2201 2202 ahci_mop_commands(ahci_ctlp, 2203 ahci_portp, 2204 port, 2205 slot_status, 2206 0, /* failed tags */ 2207 0, /* timeout tags */ 2208 0, /* aborted tags */ 2209 reset_tags); /* reset tags */ 2210 2211 return (SATA_SUCCESS); 2212 } 2213 2214 /* 2215 * Used to do hba reset and reject all the pending packets on all ports 2216 * during the reset operation. 2217 */ 2218 static int 2219 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2220 { 2221 ahci_port_t *ahci_portp; 2222 uint32_t slot_status[AHCI_MAX_PORTS]; 2223 uint32_t reset_tags[AHCI_MAX_PORTS]; 2224 uint32_t finished_tags[AHCI_MAX_PORTS]; 2225 uint8_t port; 2226 int ret = SATA_SUCCESS; 2227 2228 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2229 "ahci_reset_hba_reject_pkts enter"); 2230 2231 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2232 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2233 continue; 2234 } 2235 2236 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2237 2238 mutex_enter(&ahci_portp->ahciport_mutex); 2239 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2240 slot_status[port] = ddi_get32( 2241 ahci_ctlp->ahcictl_ahci_acc_handle, 2242 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2243 reset_tags[port] = slot_status[port] & 2244 AHCI_SLOT_MASK(ahci_ctlp); 2245 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2246 slot_status[port] = ddi_get32( 2247 ahci_ctlp->ahcictl_ahci_acc_handle, 2248 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2249 reset_tags[port] = slot_status[port] & 2250 AHCI_NCQ_SLOT_MASK(ahci_portp); 2251 } 2252 mutex_exit(&ahci_portp->ahciport_mutex); 2253 } 2254 2255 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2256 ret = SATA_FAILURE; 2257 goto out; 2258 } 2259 2260 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2261 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2262 continue; 2263 } 2264 2265 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2266 2267 mutex_enter(&ahci_portp->ahciport_mutex); 2268 /* 2269 * To prevent recursive enter to ahci_mop_commands, we need 2270 * check AHCI_PORT_FLAG_MOPPING flag. 2271 */ 2272 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2273 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2274 "ahci_reset_hba_reject_pkts: port %d is in " 2275 "mopping process, so return directly ", port); 2276 mutex_exit(&ahci_portp->ahciport_mutex); 2277 continue; 2278 } 2279 2280 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2281 ahci_portp->ahciport_mop_in_progress++; 2282 2283 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2284 finished_tags[port] = 2285 ahci_portp->ahciport_pending_tags & 2286 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2287 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2288 finished_tags[port] = 2289 ahci_portp->ahciport_pending_ncq_tags & 2290 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2291 2292 reset_tags[port] &= ~finished_tags[port]; 2293 2294 ahci_mop_commands(ahci_ctlp, 2295 ahci_portp, 2296 port, 2297 slot_status[port], 2298 0, /* failed tags */ 2299 0, /* timeout tags */ 2300 0, /* aborted tags */ 2301 reset_tags[port]); /* reset tags */ 2302 mutex_exit(&ahci_portp->ahciport_mutex); 2303 } 2304 out: 2305 return (ret); 2306 } 2307 2308 /* 2309 * Called by sata framework to reset a port(s) or device. 2310 */ 2311 static int 2312 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2313 { 2314 ahci_ctl_t *ahci_ctlp; 2315 ahci_port_t *ahci_portp; 2316 uint8_t cport = sd->satadev_addr.cport; 2317 uint8_t port; 2318 int ret = SATA_SUCCESS; 2319 int instance = ddi_get_instance(dip); 2320 2321 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2322 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2323 2324 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2325 "ahci_tran_reset_port enter: cport: %d", cport); 2326 2327 switch (sd->satadev_addr.qual) { 2328 case SATA_ADDR_CPORT: 2329 /* Port reset */ 2330 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2331 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2332 "reset port", instance, port); 2333 2334 mutex_enter(&ahci_portp->ahciport_mutex); 2335 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2336 mutex_exit(&ahci_portp->ahciport_mutex); 2337 2338 break; 2339 2340 case SATA_ADDR_DCPORT: 2341 /* Device reset */ 2342 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2343 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2344 "reset device", instance, port); 2345 2346 mutex_enter(&ahci_portp->ahciport_mutex); 2347 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2348 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2349 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2350 /* 2351 * In case the targer driver would send the request 2352 * before sata framework can have the opportunity to 2353 * process those event reports. 2354 */ 2355 sd->satadev_state = ahci_portp->ahciport_port_state; 2356 ahci_update_sata_registers(ahci_ctlp, port, sd); 2357 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2358 "ahci_tran_reset_dport returning SATA_FAILURE " 2359 "while port in FAILED/SHUTDOWN/PWROFF state: " 2360 "port: %d", port); 2361 mutex_exit(&ahci_portp->ahciport_mutex); 2362 ret = SATA_FAILURE; 2363 break; 2364 } 2365 2366 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2367 /* 2368 * ahci_intr_phyrdy_change() may have rendered it to 2369 * AHCI_PORT_TYPE_NODEV. 2370 */ 2371 sd->satadev_type = SATA_DTYPE_NONE; 2372 sd->satadev_state = ahci_portp->ahciport_port_state; 2373 ahci_update_sata_registers(ahci_ctlp, port, sd); 2374 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2375 "ahci_tran_reset_dport returning SATA_FAILURE " 2376 "while no device attached: port: %d", port); 2377 mutex_exit(&ahci_portp->ahciport_mutex); 2378 ret = SATA_FAILURE; 2379 break; 2380 } 2381 2382 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2383 ahci_portp, port); 2384 mutex_exit(&ahci_portp->ahciport_mutex); 2385 break; 2386 2387 case SATA_ADDR_CNTRL: 2388 /* Reset the whole controller */ 2389 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2390 "reset the whole hba", instance, port); 2391 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2392 break; 2393 2394 case SATA_ADDR_PMPORT: 2395 case SATA_ADDR_DPMPORT: 2396 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2397 "ahci_tran_reset_dport: port multiplier will be " 2398 "supported later"); 2399 /* FALLSTHROUGH */ 2400 default: 2401 ret = SATA_FAILURE; 2402 } 2403 2404 return (ret); 2405 } 2406 2407 /* 2408 * Called by sata framework to activate a port as part of hotplug. 2409 * (cfgadm -c connect satax/y) 2410 * Note: Not port-mult aware. 2411 */ 2412 static int 2413 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2414 { 2415 ahci_ctl_t *ahci_ctlp; 2416 ahci_port_t *ahci_portp; 2417 uint8_t cport = satadev->satadev_addr.cport; 2418 uint8_t port; 2419 int instance = ddi_get_instance(dip); 2420 2421 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2422 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2423 2424 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2425 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2426 2427 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2428 2429 mutex_enter(&ahci_portp->ahciport_mutex); 2430 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2431 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated", instance, port); 2432 2433 /* 2434 * Reset the port so that the PHY communication would be re-established. 2435 * But this reset is an internal operation and the sata module doesn't 2436 * need to know about it. Moreover, the port with a device attached will 2437 * be started too. 2438 */ 2439 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2440 ahci_portp, port, 2441 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2442 NULL); 2443 2444 /* 2445 * Need to check the link status and device status of the port 2446 * and consider raising power if the port was in D3 state 2447 */ 2448 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2449 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2450 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2451 2452 satadev->satadev_state = ahci_portp->ahciport_port_state; 2453 2454 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2455 2456 mutex_exit(&ahci_portp->ahciport_mutex); 2457 return (SATA_SUCCESS); 2458 } 2459 2460 /* 2461 * Called by sata framework to deactivate a port as part of hotplug. 2462 * (cfgadm -c disconnect satax/y) 2463 * Note: Not port-mult aware. 2464 */ 2465 static int 2466 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2467 { 2468 ahci_ctl_t *ahci_ctlp; 2469 ahci_port_t *ahci_portp; 2470 uint8_t cport = satadev->satadev_addr.cport; 2471 uint8_t port; 2472 uint32_t port_scontrol; 2473 int instance = ddi_get_instance(dip); 2474 2475 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2476 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2477 2478 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2479 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2480 2481 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2482 2483 mutex_enter(&ahci_portp->ahciport_mutex); 2484 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated", 2485 instance, port); 2486 2487 /* Disable the interrupts on the port */ 2488 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2489 2490 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2491 goto phy_offline; 2492 } 2493 2494 /* First to abort all the pending commands */ 2495 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2496 2497 /* Then stop the port */ 2498 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2499 ahci_portp, port); 2500 2501 /* Next put the PHY offline */ 2502 2503 phy_offline: 2504 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2505 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2506 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2507 2508 /* Update ahciport_port_state */ 2509 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2510 satadev->satadev_state = ahci_portp->ahciport_port_state; 2511 2512 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2513 2514 mutex_exit(&ahci_portp->ahciport_mutex); 2515 return (SATA_SUCCESS); 2516 } 2517 2518 /* 2519 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2520 * when a device is unplugged or a port is deactivated. 2521 * 2522 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2523 */ 2524 static void 2525 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2526 ahci_port_t *ahci_portp, uint8_t port) 2527 { 2528 uint32_t slot_status = 0; 2529 uint32_t abort_tags = 0; 2530 2531 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2532 "ahci_reject_all_abort_pkts on port: %d", port); 2533 2534 /* 2535 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2536 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2537 * to get the error data, if yes when the device is removed, the 2538 * command needs to be aborted too. 2539 */ 2540 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2541 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2542 slot_status = 0x1; 2543 abort_tags = 0x1; 2544 goto out; 2545 } else { 2546 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2547 "ahci_reject_all_abort_pkts return directly " 2548 "port %d no needs to reject any outstanding " 2549 "commands", port); 2550 return; 2551 } 2552 } 2553 2554 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2555 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2556 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2557 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2558 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2559 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2560 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2561 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2562 } 2563 2564 out: 2565 /* No need to do mop when there is no outstanding commands */ 2566 if (slot_status != 0) { 2567 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2568 ahci_portp->ahciport_mop_in_progress++; 2569 2570 ahci_mop_commands(ahci_ctlp, 2571 ahci_portp, 2572 port, 2573 slot_status, 2574 0, /* failed tags */ 2575 0, /* timeout tags */ 2576 abort_tags, /* aborting tags */ 2577 0); /* reset tags */ 2578 } 2579 } 2580 2581 #if defined(__lock_lint) 2582 static int 2583 ahci_selftest(dev_info_t *dip, sata_device_t *device) 2584 { 2585 return (SATA_SUCCESS); 2586 } 2587 #endif 2588 2589 /* 2590 * Allocate the ports structure, only called by ahci_attach 2591 */ 2592 static int 2593 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2594 { 2595 int port, cport = 0; 2596 2597 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2598 "ahci_alloc_ports_state enter"); 2599 2600 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2601 2602 /* Allocate structures only for the implemented ports */ 2603 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2604 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2605 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2606 "hba port %d not implemented", port); 2607 continue; 2608 } 2609 2610 #ifndef __lock_lint 2611 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2612 ahci_ctlp->ahcictl_port_to_cport[port] = 2613 (uint8_t)cport++; 2614 #endif /* __lock_lint */ 2615 2616 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2617 goto err_out; 2618 } 2619 } 2620 2621 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2622 return (AHCI_SUCCESS); 2623 2624 err_out: 2625 for (port--; port >= 0; port--) { 2626 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2627 ahci_dealloc_port_state(ahci_ctlp, port); 2628 } 2629 } 2630 2631 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2632 return (AHCI_FAILURE); 2633 } 2634 2635 /* 2636 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2637 */ 2638 static void 2639 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2640 { 2641 int port; 2642 2643 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2644 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2645 /* if this port is implemented by the HBA */ 2646 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2647 ahci_dealloc_port_state(ahci_ctlp, port); 2648 } 2649 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2650 } 2651 2652 /* 2653 * Initialize the controller and all ports. And then try to start the ports 2654 * if there are devices attached. 2655 * 2656 * This routine can be called from three seperate cases: DDI_ATTACH, 2657 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2658 * other two cases; device signature probing are attempted only during 2659 * DDI_ATTACH case. 2660 * 2661 * WARNING!!! Disable the whole controller's interrupts before calling and 2662 * the interrupts will be enabled upon successfully return. 2663 */ 2664 static int 2665 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2666 { 2667 ahci_port_t *ahci_portp; 2668 uint32_t ghc_control; 2669 int port; 2670 2671 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2672 "ahci_initialize_controller enter"); 2673 2674 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2675 2676 /* 2677 * Indicate that system software is AHCI aware by setting 2678 * GHC.AE to 1 2679 */ 2680 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2681 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2682 2683 ghc_control |= AHCI_HBA_GHC_AE; 2684 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2685 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2686 ghc_control); 2687 2688 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2689 2690 /* Initialize the implemented ports and structures */ 2691 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2692 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2693 continue; 2694 } 2695 2696 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2697 mutex_enter(&ahci_portp->ahciport_mutex); 2698 2699 /* 2700 * Ensure that the controller is not in the running state 2701 * by checking every implemented port's PxCMD register 2702 */ 2703 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2704 != AHCI_SUCCESS) { 2705 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2706 "ahci_initialize_controller: failed to " 2707 "initialize port %d", port); 2708 /* 2709 * Set the port state to SATA_PSTATE_FAILED if 2710 * failed to initialize it. 2711 */ 2712 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2713 } 2714 2715 mutex_exit(&ahci_portp->ahciport_mutex); 2716 } 2717 2718 /* Enable the whole controller interrupts */ 2719 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2720 ahci_enable_all_intrs(ahci_ctlp); 2721 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2722 2723 return (AHCI_SUCCESS); 2724 } 2725 2726 /* 2727 * Reverse of ahci_initialize_controller() 2728 * 2729 * We only need to stop the ports and disable the interrupt. 2730 */ 2731 static void 2732 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2733 { 2734 ahci_port_t *ahci_portp; 2735 int port; 2736 2737 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2738 "ahci_uninitialize_controller enter"); 2739 2740 /* disable all the interrupts. */ 2741 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2742 ahci_disable_all_intrs(ahci_ctlp); 2743 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2744 2745 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2746 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2747 continue; 2748 } 2749 2750 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2751 2752 /* Stop the port by clearing PxCMD.ST */ 2753 mutex_enter(&ahci_portp->ahciport_mutex); 2754 2755 /* 2756 * Here we must disable the port interrupt because 2757 * ahci_disable_all_intrs only clear GHC.IE, and IS 2758 * register will be still set if PxIE is enabled. 2759 * When ahci shares one IRQ with other drivers, the 2760 * intr handler may claim the intr mistakenly. 2761 */ 2762 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2763 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2764 ahci_portp, port); 2765 mutex_exit(&ahci_portp->ahciport_mutex); 2766 } 2767 } 2768 2769 /* 2770 * The routine is to initialize the port. First put the port in NOTRunning 2771 * state, then enable port interrupt and clear Serror register. And under 2772 * AHCI_ATTACH case, find device signature and then try to start the port. 2773 * 2774 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2775 */ 2776 static int 2777 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2778 ahci_port_t *ahci_portp, uint8_t port) 2779 { 2780 uint32_t port_cmd_status; 2781 2782 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2783 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2784 2785 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2786 "ahci_initialize_port: port %d " 2787 "port_cmd_status = 0x%x", port, port_cmd_status); 2788 /* 2789 * Check whether the port is in NotRunning state, if not, 2790 * put the port in NotRunning state 2791 */ 2792 if (!(port_cmd_status & 2793 (AHCI_CMD_STATUS_ST | 2794 AHCI_CMD_STATUS_CR | 2795 AHCI_CMD_STATUS_FRE | 2796 AHCI_CMD_STATUS_FR))) { 2797 2798 goto next; 2799 } 2800 2801 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2802 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2803 return (AHCI_FAILURE); 2804 2805 next: 2806 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2807 "port %d is in NotRunning state now", port); 2808 2809 /* 2810 * At the time being, only probe ports/devices and get the types of 2811 * attached devices during DDI_ATTACH. In fact, the device can be 2812 * changed during power state changes, but at the time being, we 2813 * don't support the situation. 2814 */ 2815 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2816 /* Try to get the device signature */ 2817 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2818 } else { 2819 2820 /* 2821 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 2822 * and PxFBU registers in case these registers were cleared 2823 * during the suspend. 2824 */ 2825 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2826 "ahci_initialize_port: port %d " 2827 "reset the port during resume", port); 2828 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 2829 2830 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2831 "ahci_initialize_port: port %d " 2832 "set PxCLB, PxCLBU, PxFB and PxFBU " 2833 "during resume", port); 2834 2835 /* Config Port Received FIS Base Address */ 2836 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2837 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 2838 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 2839 2840 /* Config Port Command List Base Address */ 2841 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2842 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 2843 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 2844 } 2845 2846 /* Disable the interface power management */ 2847 ahci_disable_interface_pm(ahci_ctlp, port); 2848 2849 /* Return directly if no device connected */ 2850 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2851 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2852 "No device connected to port %d", port); 2853 goto out; 2854 } 2855 2856 /* Try to start the port */ 2857 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2858 != AHCI_SUCCESS) { 2859 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2860 "failed to start port %d", port); 2861 return (AHCI_FAILURE); 2862 } 2863 out: 2864 /* Enable port interrupts */ 2865 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2866 2867 return (AHCI_SUCCESS); 2868 } 2869 2870 /* 2871 * Figure out which chip and set flag for VT8251; Also check 2872 * the power management capability. 2873 */ 2874 static int 2875 ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 2876 { 2877 ushort_t venid, devid; 2878 ushort_t caps_ptr, cap_count, cap, pmcap, pmcsr; 2879 uint8_t revision; 2880 2881 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2882 PCI_CONF_VENID); 2883 2884 devid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2885 PCI_CONF_DEVID); 2886 2887 /* 2888 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 2889 * controllers with 0x00 revision id work on 4-byte aligned buffer, 2890 * which is a bug and was fixed after 0x00 revision id controllers. 2891 * 2892 * Moreover, VT8251 cannot use multiple command slots in the command 2893 * list for non-queued commands because the previous register content 2894 * of PxCI can be re-written in the register write, so a flag will be 2895 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 2896 */ 2897 if (venid == VIA_VENID) { 2898 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2899 PCI_CONF_REVID); 2900 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2901 "revision id = 0x%x", revision); 2902 if (revision == 0x00) { 2903 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 2904 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2905 "change ddi_attr_align to 0x4"); 2906 } 2907 2908 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 2909 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2910 "VT8251 cannot use multiple command lists for " 2911 "non-queued commands"); 2912 } 2913 2914 /* 2915 * ATI SB600 (1002,4380) doesn't support 64-bit DMA addressing though it 2916 * declares support, so we need to set AHCI_CAP_32BIT_DMA flag to force 2917 * 32-bit DMA. 2918 */ 2919 if (venid == 0x1002 && devid == 0x4380) { 2920 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2921 "ATI SB600 cannot do 64-bit DMA though CAP indicates " 2922 "support, so force it to use 32-bit DMA"); 2923 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 2924 } 2925 2926 /* 2927 * Check if capabilities list is supported and if so, 2928 * get initial capabilities pointer and clear bits 0,1. 2929 */ 2930 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2931 PCI_CONF_STAT) & PCI_STAT_CAP) { 2932 caps_ptr = P2ALIGN(pci_config_get8( 2933 ahci_ctlp->ahcictl_pci_conf_handle, 2934 PCI_CONF_CAP_PTR), 4); 2935 } else { 2936 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 2937 } 2938 2939 /* 2940 * Walk capabilities if supported. 2941 */ 2942 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 2943 2944 /* 2945 * Check that we haven't exceeded the maximum number of 2946 * capabilities and that the pointer is in a valid range. 2947 */ 2948 if (++cap_count > PCI_CAP_MAX_PTR) { 2949 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2950 "too many device capabilities"); 2951 return (AHCI_FAILURE); 2952 } 2953 if (caps_ptr < PCI_CAP_PTR_OFF) { 2954 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2955 "capabilities pointer 0x%x out of range", 2956 caps_ptr); 2957 return (AHCI_FAILURE); 2958 } 2959 2960 /* 2961 * Get next capability and check that it is valid. 2962 * For now, we only support power management. 2963 */ 2964 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2965 caps_ptr); 2966 switch (cap) { 2967 case PCI_CAP_ID_PM: 2968 2969 /* power management supported */ 2970 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 2971 2972 /* Save PMCSR offset */ 2973 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 2974 2975 pmcap = pci_config_get16( 2976 ahci_ctlp->ahcictl_pci_conf_handle, 2977 caps_ptr + PCI_PMCAP); 2978 pmcsr = pci_config_get16( 2979 ahci_ctlp->ahcictl_pci_conf_handle, 2980 ahci_ctlp->ahcictl_pmcsr_offset); 2981 AHCIDBG2(AHCIDBG_PM, ahci_ctlp, 2982 "Power Management capability found PCI_PMCAP " 2983 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 2984 #if AHCI_DEBUG 2985 if ((pmcap & 0x3) == 0x3) 2986 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2987 "PCI Power Management Interface " 2988 "spec 1.2 compliant"); 2989 #endif 2990 break; 2991 2992 case PCI_CAP_ID_MSI: 2993 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, "MSI capability found"); 2994 break; 2995 2996 case PCI_CAP_ID_PCIX: 2997 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2998 "PCI-X capability found"); 2999 break; 3000 3001 case PCI_CAP_ID_PCI_E: 3002 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3003 "PCI Express capability found"); 3004 break; 3005 3006 case PCI_CAP_ID_MSI_X: 3007 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3008 "MSI-X capability found"); 3009 break; 3010 3011 case PCI_CAP_ID_SATA: 3012 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3013 "SATA capability found"); 3014 break; 3015 3016 case PCI_CAP_ID_VS: 3017 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3018 "Vendor Specific capability found"); 3019 break; 3020 3021 default: 3022 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 3023 "unrecognized capability 0x%x", cap); 3024 break; 3025 } 3026 3027 /* 3028 * Get next capabilities pointer and clear bits 0,1. 3029 */ 3030 caps_ptr = P2ALIGN(pci_config_get8( 3031 ahci_ctlp->ahcictl_pci_conf_handle, 3032 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 3033 } 3034 3035 return (AHCI_SUCCESS); 3036 } 3037 3038 /* 3039 * AHCI device reset ...; a single device on one of the ports is reset, 3040 * but the HBA and physical communication remain intact. This is the 3041 * least intrusive. 3042 * 3043 * When issuing a software reset sequence, there should not be other 3044 * commands in the command list, so we will first clear and then re-set 3045 * PxCMD.ST to clear PxCI. And before issuing the software reset, 3046 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 3047 * cleared. 3048 * 3049 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 3050 * set before the function is called. 3051 */ 3052 static int 3053 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3054 uint8_t port) 3055 { 3056 ahci_fis_h2d_register_t *h2d_register_fisp; 3057 ahci_cmd_table_t *cmd_table; 3058 ahci_cmd_header_t *cmd_header; 3059 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 3060 int slot, loop_count; 3061 3062 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3063 "Port %d device resetting", port); 3064 3065 /* First to clear PxCMD.ST */ 3066 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3067 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3068 3069 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 3070 3071 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3072 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3073 port_cmd_status|AHCI_CMD_STATUS_ST); 3074 3075 /* And then to re-set PxCMD.ST */ 3076 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3077 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3078 3079 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3080 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3081 port_cmd_status|AHCI_CMD_STATUS_ST); 3082 3083 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 3084 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3085 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3086 3087 if (port_task_file & AHCI_TFD_STS_BSY || 3088 port_task_file & AHCI_TFD_STS_DRQ) { 3089 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 3090 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3091 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 3092 "but PxCMD.CLO isn't supported, so a port " 3093 "reset is needed."); 3094 return (AHCI_FAILURE); 3095 } 3096 } 3097 3098 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, AHCI_NON_NCQ_CMD); 3099 if (slot == AHCI_FAILURE) { 3100 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 3101 "ahci_software_reset: no free slot"); 3102 return (AHCI_FAILURE); 3103 } 3104 3105 /* Now send the first R2H FIS with SRST set to 1 */ 3106 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3107 bzero((void *)cmd_table, ahci_cmd_table_size); 3108 3109 h2d_register_fisp = 3110 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3111 3112 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3113 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3114 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 3115 3116 /* Set Command Header in Command List */ 3117 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3118 BZERO_DESCR_INFO(cmd_header); 3119 BZERO_PRD_BYTE_COUNT(cmd_header); 3120 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3121 3122 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 3123 SET_RESET(cmd_header, 1); 3124 SET_WRITE(cmd_header, 1); 3125 3126 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3127 0, 3128 ahci_cmd_table_size, 3129 DDI_DMA_SYNC_FORDEV); 3130 3131 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3132 slot * sizeof (ahci_cmd_header_t), 3133 sizeof (ahci_cmd_header_t), 3134 DDI_DMA_SYNC_FORDEV); 3135 3136 /* Indicate to the HBA that a command is active. */ 3137 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3138 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3139 (0x1 << slot)); 3140 3141 loop_count = 0; 3142 3143 /* Loop till the first command is finished */ 3144 do { 3145 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3146 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3147 3148 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3149 /* We are effectively timing out after 0.1 sec. */ 3150 break; 3151 } 3152 /* Wait for 10 millisec */ 3153 #ifndef __lock_lint 3154 delay(AHCI_10MS_TICKS); 3155 #endif /* __lock_lint */ 3156 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3157 3158 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3159 "ahci_software_reset: 1st loop count: %d, " 3160 "port_cmd_issue = 0x%x, slot = 0x%x", 3161 loop_count, port_cmd_issue, slot); 3162 3163 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3164 ahci_portp->ahciport_slot_pkts[slot] = NULL; 3165 3166 /* Now send the second R2H FIS with SRST cleard to zero */ 3167 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3168 bzero((void *)cmd_table, ahci_cmd_table_size); 3169 3170 h2d_register_fisp = 3171 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3172 3173 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3174 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3175 3176 /* Set Command Header in Command List */ 3177 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3178 BZERO_DESCR_INFO(cmd_header); 3179 BZERO_PRD_BYTE_COUNT(cmd_header); 3180 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3181 3182 SET_WRITE(cmd_header, 1); 3183 3184 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3185 0, 3186 ahci_cmd_table_size, 3187 DDI_DMA_SYNC_FORDEV); 3188 3189 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3190 slot * sizeof (ahci_cmd_header_t), 3191 sizeof (ahci_cmd_header_t), 3192 DDI_DMA_SYNC_FORDEV); 3193 3194 /* Indicate to the HBA that a command is active. */ 3195 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3196 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3197 (0x1 << slot)); 3198 3199 loop_count = 0; 3200 3201 /* Loop till the second command is finished */ 3202 do { 3203 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3204 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3205 3206 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3207 /* We are effectively timing out after 0.1 sec. */ 3208 break; 3209 } 3210 /* Wait for 10 millisec */ 3211 #ifndef __lock_lint 3212 delay(AHCI_10MS_TICKS); 3213 #endif /* __lock_lint */ 3214 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3215 3216 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3217 "ahci_software_reset: 2nd loop count: %d, " 3218 "port_cmd_issue = 0x%x, slot = 0x%x", 3219 loop_count, port_cmd_issue, slot); 3220 3221 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3222 ahci_portp->ahciport_slot_pkts[slot] = NULL; 3223 3224 return (AHCI_SUCCESS); 3225 } 3226 3227 /* 3228 * AHCI port reset ...; the physical communication between the HBA and device 3229 * on a port are disabled. This is more intrusive. 3230 * 3231 * When an HBA or port reset occurs, Phy communication is going to 3232 * be re-established with the device through a COMRESET followed by the 3233 * normal out-of-band communication sequence defined in Serial ATA. AT 3234 * the end of reset, the device, if working properly, will send a D2H 3235 * Register FIS, which contains the device signature. When the HBA receives 3236 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 3237 * the PxSIG register with the signature. 3238 * 3239 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 3240 * to individually spin-up attached devices. Please refer to chapter 10.9 of 3241 * AHCI 1.0 spec. 3242 */ 3243 /* 3244 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 3245 * cleared before the function is called. 3246 */ 3247 static int 3248 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3249 { 3250 uint32_t cap_status, port_cmd_status; 3251 uint32_t port_scontrol, port_sstatus; 3252 uint32_t port_signature, port_intr_status, port_task_file; 3253 int loop_count; 3254 int rval = AHCI_SUCCESS; 3255 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 3256 3257 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3258 "Port %d port resetting...", port); 3259 ahci_portp->ahciport_port_state = 0; 3260 3261 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3262 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3263 3264 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3265 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3266 3267 if (cap_status & AHCI_HBA_CAP_SSS) { 3268 /* 3269 * HBA support staggered spin-up, if the port has 3270 * not spin up yet, then force it to do spin-up 3271 */ 3272 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 3273 if (!(ahci_portp->ahciport_flags 3274 & AHCI_PORT_FLAG_SPINUP)) { 3275 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3276 "Port %d PxCMD.SUD is zero, force " 3277 "it to do spin-up", port); 3278 ahci_portp->ahciport_flags |= 3279 AHCI_PORT_FLAG_SPINUP; 3280 } 3281 } 3282 } else { 3283 /* 3284 * HBA doesn't support stagger spin-up, force it 3285 * to do normal COMRESET 3286 */ 3287 if (ahci_portp->ahciport_flags & 3288 AHCI_PORT_FLAG_SPINUP) { 3289 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3290 "HBA does not support staggered spin-up " 3291 "force it to do normal COMRESET"); 3292 ahci_portp->ahciport_flags &= 3293 ~AHCI_PORT_FLAG_SPINUP; 3294 } 3295 } 3296 3297 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 3298 /* Do normal COMRESET */ 3299 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3300 "ahci_port_reset: do normal COMRESET", port); 3301 3302 /* 3303 * According to the spec, SUD bit should be set here, 3304 * but JMicron JMB363 doesn't follow it, so remove 3305 * the assertion, and just print a debug message. 3306 */ 3307 #if AHCI_DEBUG 3308 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3309 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3310 "port %d SUD bit not set", port) 3311 #endif 3312 3313 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3314 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3315 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3316 3317 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3318 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3319 port_scontrol); 3320 3321 /* Enable PxCMD.FRE to read device */ 3322 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3323 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3324 port_cmd_status|AHCI_CMD_STATUS_FRE); 3325 3326 /* 3327 * Give time for COMRESET to percolate, according to the AHCI 3328 * spec, software shall wait at least 1 millisecond before 3329 * clearing PxSCTL.DET 3330 */ 3331 #ifndef __lock_lint 3332 delay(AHCI_1MS_TICKS*2); 3333 #endif /* __lock_lint */ 3334 3335 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3336 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3337 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3338 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3339 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3340 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3341 port_scontrol); 3342 } else { 3343 /* Do staggered spin-up */ 3344 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3345 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3346 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3347 3348 /* PxSCTL.DET must be 0 */ 3349 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3350 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3351 port_scontrol); 3352 3353 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3354 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3355 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3356 port_cmd_status); 3357 3358 /* 0 -> 1 edge */ 3359 #ifndef __lock_lint 3360 delay(AHCI_1MS_TICKS*2); 3361 #endif /* __lock_lint */ 3362 3363 /* Set PxCMD.SUD to 1 */ 3364 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3365 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3366 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3367 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3368 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3369 port_cmd_status); 3370 3371 /* Enable PxCMD.FRE to read device */ 3372 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3373 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3374 port_cmd_status|AHCI_CMD_STATUS_FRE); 3375 } 3376 3377 /* 3378 * The port enters P:StartComm state, and HBA tells link layer to 3379 * start communication, which involves sending COMRESET to device. 3380 * And the HBA resets PxTFD.STS to 7Fh. 3381 * 3382 * When a COMINIT is received from the device, then the port enters 3383 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3384 * PxSSTS.DET to 1h to indicate a device is detected but communication 3385 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3386 * a COMINIT has been received. 3387 */ 3388 /* 3389 * The DET field is valid only if IPM field indicates 3390 * that the interface is in active state. 3391 */ 3392 loop_count = 0; 3393 do { 3394 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3395 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3396 3397 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3398 /* 3399 * If the interface is not active, the DET field 3400 * is considered not accurate. So we want to 3401 * continue looping. 3402 */ 3403 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3404 } 3405 3406 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3407 /* 3408 * We are effectively timing out after 0.1 sec. 3409 */ 3410 break; 3411 } 3412 3413 /* Wait for 10 millisec */ 3414 #ifndef __lock_lint 3415 delay(AHCI_10MS_TICKS); 3416 #endif /* __lock_lint */ 3417 3418 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3419 3420 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3421 "ahci_port_reset: 1st loop count: %d, " 3422 "port_sstatus = 0x%x port %d", 3423 loop_count, port_sstatus, port); 3424 3425 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3426 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3427 /* 3428 * Either the port is not active or there 3429 * is no device present. 3430 */ 3431 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3432 goto out; 3433 } 3434 3435 /* Now we can make sure there is a device connected to the port */ 3436 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3437 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3438 3439 /* a COMINIT signal is supposed to be received */ 3440 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 3441 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 3442 "COMINIT signal from the device not received", 3443 instance, port); 3444 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3445 rval = AHCI_FAILURE; 3446 goto out; 3447 } 3448 3449 /* 3450 * According to the spec, when PxSCTL.DET is set to 0h, upon 3451 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3452 * shall be set to '1' by the HBA. 3453 * 3454 * However, we found JMicron JMB363 doesn't follow this, so 3455 * remove this check, and just print a debug message. 3456 */ 3457 #if AHCI_DEBUG 3458 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3459 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3460 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3461 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3462 "port %d BSY bit is not set after COMINIT signal " 3463 "is received", port); 3464 } 3465 #endif 3466 3467 /* 3468 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3469 * the D2H FIS received by HBA. 3470 */ 3471 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3472 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3473 SERROR_EXCHANGED_ERR); 3474 3475 /* 3476 * Next check whether COMRESET is completed successfully 3477 */ 3478 loop_count = 0; 3479 do { 3480 port_task_file = 3481 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3482 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3483 3484 /* 3485 * The Error bit '1' means COMRESET is finished successfully 3486 * The device hardware has been initialized and the power-up 3487 * diagnostics successfully completed. 3488 */ 3489 if (((port_task_file & AHCI_TFD_ERR_MASK) 3490 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 3491 3492 port_signature = ddi_get32( 3493 ahci_ctlp->ahcictl_ahci_acc_handle, 3494 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3495 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 3496 "COMRESET success, D2H register FIS " 3497 "post to received FIS structure " 3498 "port %d signature = 0x%x", 3499 port, port_signature); 3500 goto out_check; 3501 } 3502 3503 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3504 /* 3505 * We are effectively timing out after 11 sec. 3506 */ 3507 break; 3508 } 3509 3510 /* Wait for 10 millisec */ 3511 #ifndef __lock_lint 3512 delay(AHCI_10MS_TICKS); 3513 #endif /* __lock_lint */ 3514 3515 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3516 >> AHCI_TFD_ERR_SHIFT) != 0x1); 3517 3518 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 3519 "count: %d, port_task_file = 0x%x port %d", 3520 loop_count, port_task_file, port); 3521 3522 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d the device hardware " 3523 "has been initialized and the power-up diagnostics failed", 3524 instance, port); 3525 3526 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3527 rval = AHCI_FAILURE; 3528 3529 out: 3530 /* Clear port serror register for the port */ 3531 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3532 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3533 AHCI_SERROR_CLEAR_ALL); 3534 3535 return (rval); 3536 3537 out_check: 3538 /* 3539 * Check device status, if keep busy or COMRESET error 3540 * do device reset to patch some SATA disks' issue 3541 * 3542 * For VT8251, sometimes need to do the device reset 3543 */ 3544 if ((port_task_file & AHCI_TFD_STS_BSY) || 3545 (port_task_file & AHCI_TFD_STS_DRQ)) { 3546 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 3547 "need to do device reset", port); 3548 3549 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 3550 3551 port_task_file = 3552 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3553 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3554 3555 if (port_task_file & AHCI_TFD_STS_BSY || 3556 port_task_file & AHCI_TFD_STS_DRQ) { 3557 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset: port %d " 3558 "BSY/DRQ still set after device reset " 3559 "port_task_file = 0x%x", instance, 3560 port, port_task_file); 3561 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3562 rval = AHCI_FAILURE; 3563 } 3564 } 3565 3566 goto out; 3567 } 3568 3569 /* 3570 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3571 * This is the most intrusive. 3572 * 3573 * When an HBA reset occurs, Phy communication will be re-established with 3574 * the device through a COMRESET followed by the normal out-of-band 3575 * communication sequence defined in Serial ATA. AT the end of reset, the 3576 * device, if working properly, will send a D2H Register FIS, which contains 3577 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3578 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3579 * signature. 3580 * 3581 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3582 */ 3583 static int 3584 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3585 { 3586 ahci_port_t *ahci_portp; 3587 uint32_t ghc_control; 3588 uint8_t port; 3589 int loop_count; 3590 int rval = AHCI_SUCCESS; 3591 3592 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3593 3594 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3595 3596 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3597 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3598 3599 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3600 ghc_control |= AHCI_HBA_GHC_HR; 3601 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3602 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3603 3604 /* 3605 * Wait until HBA Reset complete or timeout 3606 */ 3607 loop_count = 0; 3608 do { 3609 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3610 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3611 3612 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3613 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3614 "ahci hba reset is timing out, " 3615 "ghc_control = 0x%x", ghc_control); 3616 /* We are effectively timing out after 1 sec. */ 3617 break; 3618 } 3619 3620 /* Wait for 10 millisec */ 3621 #ifndef __lock_lint 3622 delay(AHCI_10MS_TICKS); 3623 #endif /* __lock_lint */ 3624 3625 } while (ghc_control & AHCI_HBA_GHC_HR); 3626 3627 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3628 "ahci_hba_reset: 1st loop count: %d, " 3629 "ghc_control = 0x%x", loop_count, ghc_control); 3630 3631 if (ghc_control & AHCI_HBA_GHC_HR) { 3632 /* The hba is not reset for some reasons */ 3633 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3634 "hba reset failed: HBA in a hung or locked state"); 3635 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3636 return (AHCI_FAILURE); 3637 } 3638 3639 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3640 /* Only check implemented ports */ 3641 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3642 continue; 3643 } 3644 3645 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3646 mutex_enter(&ahci_portp->ahciport_mutex); 3647 3648 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3649 != AHCI_SUCCESS) { 3650 rval = AHCI_FAILURE; 3651 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3652 "ahci_hba_reset: port %d failed", port); 3653 } 3654 3655 mutex_exit(&ahci_portp->ahciport_mutex); 3656 } 3657 3658 /* 3659 * Indicate that system software is AHCI aware by setting 3660 * GHC.AE to 1 3661 */ 3662 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3663 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3664 3665 ghc_control |= AHCI_HBA_GHC_AE; 3666 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3667 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3668 3669 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3670 3671 return (rval); 3672 } 3673 3674 /* 3675 * This routine is only called from AHCI_ATTACH or phyrdy change 3676 * case. It first calls port reset to initialize port, probe port and probe 3677 * device, then try to read PxSIG register to find the type of device 3678 * attached to the port. 3679 * 3680 * WARNING!!! ahciport_mutex should be acquired before the function 3681 * is called. And the port interrupt is disabled. 3682 */ 3683 static void 3684 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3685 ahci_port_t *ahci_portp, uint8_t port) 3686 { 3687 uint32_t signature; 3688 3689 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3690 "ahci_find_dev_signature enter: port %d", port); 3691 3692 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3693 3694 /* Call port reset to check link status and get device signature */ 3695 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3696 3697 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3698 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3699 "ahci_find_dev_signature: No device is found " 3700 "at port %d", port); 3701 return; 3702 } 3703 3704 /* Check the port state */ 3705 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3706 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3707 "ahci_find_dev_signature: port %d state 0x%x", 3708 port, ahci_portp->ahciport_port_state); 3709 return; 3710 } 3711 3712 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3713 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3714 3715 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3716 "ahci_find_dev_signature: port %d signature = 0x%x", 3717 port, signature); 3718 3719 switch (signature) { 3720 3721 case AHCI_SIGNATURE_DISK: 3722 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3723 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3724 "Disk is found at port: %d", port); 3725 break; 3726 3727 case AHCI_SIGNATURE_ATAPI: 3728 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 3729 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3730 "ATAPI device is found at port: %d", port); 3731 break; 3732 3733 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3734 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3735 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3736 "Port Multiplier is found at port: %d", port); 3737 break; 3738 3739 default: 3740 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3741 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3742 "Unknown device is found at port: %d", port); 3743 } 3744 } 3745 3746 /* 3747 * According to the spec, to reliably detect hot plug removals, software 3748 * must disable interface power management. Software should perform the 3749 * following initialization on a port after a device is attached: 3750 * Set PxSCTL.IPM to 3h to disable interface state transitions 3751 * Set PxCMD.ALPE to '0' to disable aggressive power management 3752 * Disable device initiated interface power management by SET FEATURE 3753 * 3754 * We can ignore the last item because by default the feature is disabled 3755 */ 3756 static void 3757 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 3758 { 3759 uint32_t port_scontrol, port_cmd_status; 3760 3761 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3762 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3763 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 3764 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3765 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3766 3767 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3768 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3769 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 3770 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3771 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 3772 } 3773 3774 /* 3775 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3776 * to 1, then set it firstly. 3777 * 3778 * Each port contains two major DMA engines. One DMA engine walks through 3779 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3780 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3781 * 3782 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3783 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3784 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3785 * 3786 * Software shall not set PxCMD.ST to '1' unless a functional device is 3787 * present on the port(as determined by PxTFD.STS.BSY = '0', 3788 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3789 * 3790 * WARNING!!! ahciport_mutex should be acquired before the function 3791 * is called. 3792 */ 3793 static int 3794 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3795 { 3796 uint32_t port_cmd_status; 3797 3798 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3799 3800 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3801 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3802 "the state for port %d is 0x%x", 3803 port, ahci_portp->ahciport_port_state); 3804 return (AHCI_FAILURE); 3805 } 3806 3807 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3808 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3809 "no device is attached at port %d", port); 3810 return (AHCI_FAILURE); 3811 } 3812 3813 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3814 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3815 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3816 3817 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3818 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3819 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3820 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3821 port_cmd_status); 3822 } 3823 3824 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3825 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3826 3827 port_cmd_status |= AHCI_CMD_STATUS_ST; 3828 3829 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3830 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3831 port_cmd_status); 3832 3833 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3834 3835 return (AHCI_SUCCESS); 3836 } 3837 3838 /* 3839 * Allocate the ahci_port_t including Received FIS and Command List. 3840 * The argument - port is the physical port number, and not logical 3841 * port number seen by the SATA framework. 3842 * 3843 * WARNING!!! ahcictl_mutex should be acquired before the function 3844 * is called. 3845 */ 3846 static int 3847 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3848 { 3849 ahci_port_t *ahci_portp; 3850 3851 ahci_portp = 3852 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3853 3854 #ifndef __lock_lint 3855 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3856 #endif /* __lock_lint */ 3857 3858 ahci_portp->ahciport_port_num = port; 3859 3860 /* Intialize the port condition variable */ 3861 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3862 3863 /* Initialize the port mutex */ 3864 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3865 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3866 3867 mutex_enter(&ahci_portp->ahciport_mutex); 3868 3869 /* 3870 * Allocate memory for received FIS structure and 3871 * command list for this port 3872 */ 3873 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3874 goto err_case1; 3875 } 3876 3877 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3878 goto err_case2; 3879 } 3880 3881 ahci_portp->ahciport_event_args = 3882 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3883 3884 if (ahci_portp->ahciport_event_args == NULL) 3885 goto err_case3; 3886 3887 mutex_exit(&ahci_portp->ahciport_mutex); 3888 3889 return (AHCI_SUCCESS); 3890 3891 err_case3: 3892 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3893 3894 err_case2: 3895 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3896 3897 err_case1: 3898 mutex_exit(&ahci_portp->ahciport_mutex); 3899 mutex_destroy(&ahci_portp->ahciport_mutex); 3900 cv_destroy(&ahci_portp->ahciport_cv); 3901 3902 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3903 3904 return (AHCI_FAILURE); 3905 } 3906 3907 /* 3908 * Reverse of ahci_dealloc_port_state(). 3909 * 3910 * WARNING!!! ahcictl_mutex should be acquired before the function 3911 * is called. 3912 */ 3913 static void 3914 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3915 { 3916 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3917 3918 ASSERT(ahci_portp != NULL); 3919 3920 mutex_enter(&ahci_portp->ahciport_mutex); 3921 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3922 ahci_portp->ahciport_event_args = NULL; 3923 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3924 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3925 mutex_exit(&ahci_portp->ahciport_mutex); 3926 3927 mutex_destroy(&ahci_portp->ahciport_mutex); 3928 cv_destroy(&ahci_portp->ahciport_cv); 3929 3930 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3931 3932 #ifndef __lock_lint 3933 ahci_ctlp->ahcictl_ports[port] = NULL; 3934 #endif /* __lock_lint */ 3935 } 3936 3937 /* 3938 * Allocates memory for the Received FIS Structure 3939 * 3940 * WARNING!!! ahciport_mutex should be acquired before the function 3941 * is called. 3942 */ 3943 static int 3944 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3945 uint8_t port) 3946 { 3947 size_t rcvd_fis_size; 3948 size_t ret_len; 3949 uint_t cookie_count; 3950 3951 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3952 3953 /* allocate rcvd FIS dma handle. */ 3954 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3955 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3956 DDI_DMA_SLEEP, 3957 NULL, 3958 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3959 DDI_SUCCESS) { 3960 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3961 "rcvd FIS dma handle alloc failed"); 3962 3963 return (AHCI_FAILURE); 3964 } 3965 3966 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3967 rcvd_fis_size, 3968 &accattr, 3969 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3970 DDI_DMA_SLEEP, 3971 NULL, 3972 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3973 &ret_len, 3974 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3975 3976 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3977 "rcvd FIS dma mem alloc fail"); 3978 /* error.. free the dma handle. */ 3979 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3980 return (AHCI_FAILURE); 3981 } 3982 3983 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3984 NULL, 3985 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3986 rcvd_fis_size, 3987 DDI_DMA_CONSISTENT, 3988 DDI_DMA_SLEEP, 3989 NULL, 3990 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 3991 &cookie_count) != DDI_DMA_MAPPED) { 3992 3993 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3994 "rcvd FIS dma handle bind fail"); 3995 /* error.. free the dma handle & free the memory. */ 3996 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3997 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3998 return (AHCI_FAILURE); 3999 } 4000 4001 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 4002 4003 /* Config Port Received FIS Base Address */ 4004 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4005 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 4006 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4007 4008 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4009 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4010 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4011 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 4012 4013 return (AHCI_SUCCESS); 4014 } 4015 4016 /* 4017 * Deallocates the Received FIS Structure 4018 * 4019 * WARNING!!! ahciport_mutex should be acquired before the function 4020 * is called. 4021 */ 4022 static void 4023 ahci_dealloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4024 { 4025 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4026 "ahci_dealloc_rcvd_fis: port %d enter", 4027 ahci_portp->ahciport_port_num); 4028 4029 /* Unbind the cmd list dma handle first. */ 4030 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 4031 4032 /* Then free the underlying memory. */ 4033 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4034 4035 /* Now free the handle itself. */ 4036 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4037 } 4038 4039 /* 4040 * Allocates memory for the Command List, which contains up to 32 entries. 4041 * Each entry contains a command header, which is a 32-byte structure that 4042 * includes the pointer to the command table. 4043 * 4044 * WARNING!!! ahciport_mutex should be acquired before the function 4045 * is called. 4046 */ 4047 static int 4048 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4049 uint8_t port) 4050 { 4051 size_t cmd_list_size; 4052 size_t ret_len; 4053 uint_t cookie_count; 4054 4055 cmd_list_size = 4056 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 4057 4058 /* allocate cmd list dma handle. */ 4059 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4060 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 4061 DDI_DMA_SLEEP, 4062 NULL, 4063 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 4064 4065 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4066 "cmd list dma handle alloc failed"); 4067 return (AHCI_FAILURE); 4068 } 4069 4070 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 4071 cmd_list_size, 4072 &accattr, 4073 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4074 DDI_DMA_SLEEP, 4075 NULL, 4076 (caddr_t *)&ahci_portp->ahciport_cmd_list, 4077 &ret_len, 4078 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 4079 4080 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4081 "cmd list dma mem alloc fail"); 4082 /* error.. free the dma handle. */ 4083 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4084 return (AHCI_FAILURE); 4085 } 4086 4087 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 4088 NULL, 4089 (caddr_t)ahci_portp->ahciport_cmd_list, 4090 cmd_list_size, 4091 DDI_DMA_CONSISTENT, 4092 DDI_DMA_SLEEP, 4093 NULL, 4094 &ahci_portp->ahciport_cmd_list_dma_cookie, 4095 &cookie_count) != DDI_DMA_MAPPED) { 4096 4097 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4098 "cmd list dma handle bind fail"); 4099 /* error.. free the dma handle & free the memory. */ 4100 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4101 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4102 return (AHCI_FAILURE); 4103 } 4104 4105 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 4106 4107 /* Config Port Command List Base Address */ 4108 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4109 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 4110 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4111 4112 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4113 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4114 4115 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4116 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 4117 4118 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 4119 goto err_out; 4120 } 4121 4122 return (AHCI_SUCCESS); 4123 4124 err_out: 4125 /* Unbind the cmd list dma handle first. */ 4126 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4127 4128 /* Then free the underlying memory. */ 4129 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4130 4131 /* Now free the handle itself. */ 4132 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4133 4134 return (AHCI_FAILURE); 4135 } 4136 4137 /* 4138 * Deallocates the Command List 4139 * 4140 * WARNING!!! ahciport_mutex should be acquired before the function 4141 * is called. 4142 */ 4143 static void 4144 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4145 { 4146 /* First dealloc command table */ 4147 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 4148 4149 /* Unbind the cmd list dma handle first. */ 4150 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4151 4152 /* Then free the underlying memory. */ 4153 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4154 4155 /* Now free the handle itself. */ 4156 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4157 } 4158 4159 /* 4160 * Allocates memory for all Command Tables, which contains Command FIS, 4161 * ATAPI Command and Physical Region Descriptor Table. 4162 * 4163 * WARNING!!! ahciport_mutex should be acquired before the function 4164 * is called. 4165 */ 4166 static int 4167 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4168 { 4169 size_t ret_len; 4170 ddi_dma_cookie_t cmd_table_dma_cookie; 4171 uint_t cookie_count; 4172 int slot; 4173 4174 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4175 "ahci_alloc_cmd_tables: port %d enter", 4176 ahci_portp->ahciport_port_num); 4177 4178 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4179 /* Allocate cmd table dma handle. */ 4180 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4181 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 4182 DDI_DMA_SLEEP, 4183 NULL, 4184 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 4185 DDI_SUCCESS) { 4186 4187 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4188 "cmd table dma handle alloc failed"); 4189 4190 goto err_out; 4191 } 4192 4193 if (ddi_dma_mem_alloc( 4194 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4195 ahci_cmd_table_size, 4196 &accattr, 4197 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4198 DDI_DMA_SLEEP, 4199 NULL, 4200 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 4201 &ret_len, 4202 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 4203 NULL) { 4204 4205 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4206 "cmd table dma mem alloc fail"); 4207 4208 /* error.. free the dma handle. */ 4209 ddi_dma_free_handle( 4210 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4211 goto err_out; 4212 } 4213 4214 if (ddi_dma_addr_bind_handle( 4215 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4216 NULL, 4217 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 4218 ahci_cmd_table_size, 4219 DDI_DMA_CONSISTENT, 4220 DDI_DMA_SLEEP, 4221 NULL, 4222 &cmd_table_dma_cookie, 4223 &cookie_count) != DDI_DMA_MAPPED) { 4224 4225 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4226 "cmd table dma handle bind fail"); 4227 /* error.. free the dma handle & free the memory. */ 4228 ddi_dma_mem_free( 4229 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4230 ddi_dma_free_handle( 4231 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4232 goto err_out; 4233 } 4234 4235 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 4236 ahci_cmd_table_size); 4237 4238 /* Config Port Command Table Base Address */ 4239 SET_COMMAND_TABLE_BASE_ADDR( 4240 (&ahci_portp->ahciport_cmd_list[slot]), 4241 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 4242 4243 #ifndef __lock_lint 4244 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 4245 (&ahci_portp->ahciport_cmd_list[slot]), 4246 cmd_table_dma_cookie.dmac_laddress >> 32); 4247 #endif /* __lock_lint */ 4248 } 4249 4250 return (AHCI_SUCCESS); 4251 err_out: 4252 4253 for (slot--; slot >= 0; slot--) { 4254 /* Unbind the cmd table dma handle first */ 4255 (void) ddi_dma_unbind_handle( 4256 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4257 4258 /* Then free the underlying memory */ 4259 ddi_dma_mem_free( 4260 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4261 4262 /* Now free the handle itself */ 4263 ddi_dma_free_handle( 4264 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4265 } 4266 4267 return (AHCI_FAILURE); 4268 } 4269 4270 /* 4271 * Deallocates memory for all Command Tables. 4272 * 4273 * WARNING!!! ahciport_mutex should be acquired before the function 4274 * is called. 4275 */ 4276 static void 4277 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4278 { 4279 int slot; 4280 4281 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4282 "ahci_dealloc_cmd_tables: %d enter", 4283 ahci_portp->ahciport_port_num); 4284 4285 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4286 /* Unbind the cmd table dma handle first. */ 4287 (void) ddi_dma_unbind_handle( 4288 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4289 4290 /* Then free the underlying memory. */ 4291 ddi_dma_mem_free( 4292 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4293 4294 /* Now free the handle itself. */ 4295 ddi_dma_free_handle( 4296 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4297 } 4298 } 4299 4300 /* 4301 * WARNING!!! ahciport_mutex should be acquired before the function 4302 * is called. 4303 */ 4304 static void 4305 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4306 sata_device_t *sd) 4307 { 4308 sd->satadev_scr.sstatus = 4309 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4310 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4311 sd->satadev_scr.serror = 4312 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4313 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4314 sd->satadev_scr.scontrol = 4315 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4316 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4317 sd->satadev_scr.sactive = 4318 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4319 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4320 } 4321 4322 /* 4323 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4324 */ 4325 static void 4326 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4327 { 4328 uint32_t port_intr_status; 4329 uint32_t port_intr_enable; 4330 4331 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4332 "ahci_port_intr enter: port %d", port); 4333 4334 mutex_enter(&ahci_portp->ahciport_mutex); 4335 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4336 /* For SATA_OPMODE_POLLING commands */ 4337 port_intr_enable = 4338 (AHCI_INTR_STATUS_DHRS | 4339 AHCI_INTR_STATUS_PSS | 4340 AHCI_INTR_STATUS_SDBS | 4341 AHCI_INTR_STATUS_UFS | 4342 AHCI_INTR_STATUS_PCS | 4343 AHCI_INTR_STATUS_PRCS | 4344 AHCI_INTR_STATUS_OFS | 4345 AHCI_INTR_STATUS_INFS | 4346 AHCI_INTR_STATUS_IFS | 4347 AHCI_INTR_STATUS_HBDS | 4348 AHCI_INTR_STATUS_HBFS | 4349 AHCI_INTR_STATUS_TFES); 4350 mutex_exit(&ahci_portp->ahciport_mutex); 4351 goto next; 4352 } 4353 mutex_exit(&ahci_portp->ahciport_mutex); 4354 4355 /* 4356 * port_intr_enable indicates that the corresponding interrrupt 4357 * reporting is enabled. 4358 */ 4359 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4360 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4361 next: 4362 /* 4363 * port_intr_stats indicates that the corresponding interrupt 4364 * condition is active. 4365 */ 4366 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4367 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4368 4369 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4370 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4371 "port_intr_enable = 0x%x", 4372 port, port_intr_status, port_intr_enable); 4373 4374 port_intr_status &= port_intr_enable; 4375 4376 /* First clear the port interrupts status */ 4377 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4378 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4379 port_intr_status); 4380 4381 /* Check the completed non-queued commands */ 4382 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4383 AHCI_INTR_STATUS_PSS)) { 4384 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4385 ahci_portp, port, port_intr_status); 4386 } 4387 4388 /* Check the completed queued commands */ 4389 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4390 (void) ahci_intr_set_device_bits(ahci_ctlp, 4391 ahci_portp, port); 4392 } 4393 4394 /* Check the port connect change status interrupt bit */ 4395 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4396 (void) ahci_intr_port_connect_change(ahci_ctlp, 4397 ahci_portp, port); 4398 } 4399 4400 /* Check the device mechanical presence status interrupt bit */ 4401 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4402 (void) ahci_intr_device_mechanical_presence_status( 4403 ahci_ctlp, ahci_portp, port); 4404 } 4405 4406 /* Check the PhyRdy change status interrupt bit */ 4407 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4408 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4409 port); 4410 } 4411 4412 /* 4413 * Check the non-fatal error interrupt bits, there are three 4414 * kinds of non-fatal errors at the time being: 4415 * 4416 * PxIS.UFS - Unknown FIS Error 4417 * PxIS.OFS - Overflow Error 4418 * PxIS.INFS - Interface Non-Fatal Error 4419 * 4420 * For these non-fatal errors, the HBA can continue to operate, 4421 * so the driver just log the error messages. 4422 */ 4423 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4424 AHCI_INTR_STATUS_OFS | 4425 AHCI_INTR_STATUS_INFS)) { 4426 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4427 port, port_intr_status); 4428 } 4429 4430 /* 4431 * Check the fatal error interrupt bits, there are four kinds 4432 * of fatal errors for AHCI controllers: 4433 * 4434 * PxIS.HBFS - Host Bus Fatal Error 4435 * PxIS.HBDS - Host Bus Data Error 4436 * PxIS.IFS - Interface Fatal Error 4437 * PxIS.TFES - Task File Error 4438 * 4439 * The fatal error means the HBA can not recover from it by 4440 * itself, and it will try to abort the transfer, and the software 4441 * must intervene to restart the port. 4442 */ 4443 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4444 AHCI_INTR_STATUS_HBDS | 4445 AHCI_INTR_STATUS_HBFS | 4446 AHCI_INTR_STATUS_TFES)) 4447 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4448 port, port_intr_status); 4449 4450 /* Check the cold port detect interrupt bit */ 4451 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4452 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4453 } 4454 4455 /* Second clear the corresponding bit in IS.IPS */ 4456 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4457 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4458 } 4459 4460 /* 4461 * Interrupt service handler 4462 */ 4463 /* ARGSUSED1 */ 4464 static uint_t 4465 ahci_intr(caddr_t arg1, caddr_t arg2) 4466 { 4467 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4468 ahci_port_t *ahci_portp; 4469 int32_t global_intr_status; 4470 uint8_t port; 4471 4472 /* 4473 * global_intr_status indicates that the corresponding port has 4474 * an interrupt pending. 4475 */ 4476 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4477 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4478 4479 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4480 /* The interrupt is not ours */ 4481 return (DDI_INTR_UNCLAIMED); 4482 } 4483 4484 /* Loop for all the ports */ 4485 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4486 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4487 continue; 4488 } 4489 if (!((0x1 << port) & global_intr_status)) { 4490 continue; 4491 } 4492 4493 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4494 4495 /* Call ahci_port_intr */ 4496 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4497 } 4498 4499 return (DDI_INTR_CLAIMED); 4500 } 4501 4502 /* 4503 * For non-queued commands, when the corresponding bit in the PxCI register 4504 * is cleared, it means the command is completed successfully. And according 4505 * to the HBA state machine, there are three conditions which possibly will 4506 * try to clear the PxCI register bit. 4507 * 1. Receive one D2H Register FIS which is with 'I' bit set 4508 * 2. Update PIO Setup FIS 4509 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4510 * 4511 * Process completed non-queued commands when the interrupt status bit - 4512 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4513 * 4514 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4515 * with the 'I' bit set. And the following commands will send thus 4516 * FIS with 'I' bit set upon the successful completion: 4517 * 1. Non-data commands 4518 * 2. DMA data-in command 4519 * 3. DMA data-out command 4520 * 4. PIO data-out command 4521 * 5. PACKET non-data commands 4522 * 6. PACKET PIO data-in command 4523 * 7. PACKET PIO data-out command 4524 * 8. PACKET DMA data-in command 4525 * 9. PACKET DMA data-out command 4526 * 4527 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4528 * with the 'I' bit set. And the following commands will send this 4529 * FIS upon the successful completion: 4530 * 1. PIO data-in command 4531 */ 4532 static int 4533 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4534 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 4535 { 4536 uint32_t port_cmd_issue = 0; 4537 uint32_t finished_tags; 4538 int finished_slot; 4539 sata_pkt_t *satapkt; 4540 ahci_fis_d2h_register_t *rcvd_fisp; 4541 4542 if (intr_status & AHCI_INTR_STATUS_DHRS) 4543 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4544 "ahci_intr_cmd_cmplt enter: port %d " 4545 "a d2h register fis is received", port); 4546 4547 if (intr_status & AHCI_INTR_STATUS_PSS) 4548 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4549 "ahci_intr_cmd_cmplt enter: port %d " 4550 "a pio setup fis is received", port); 4551 4552 mutex_enter(&ahci_portp->ahciport_mutex); 4553 4554 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4555 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4556 /* 4557 * Spurious interrupt. Nothing to be done. 4558 */ 4559 mutex_exit(&ahci_portp->ahciport_mutex); 4560 return (AHCI_SUCCESS); 4561 } 4562 4563 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4564 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4565 4566 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4567 /* Slot 0 is always used during error recovery */ 4568 finished_tags = 0x1 & ~port_cmd_issue; 4569 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4570 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4571 "retrieval is finished, and finished_tags = 0x%x", 4572 port, finished_tags); 4573 } else { 4574 finished_tags = ahci_portp->ahciport_pending_tags & 4575 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4576 } 4577 4578 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4579 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4580 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4581 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4582 finished_tags); 4583 4584 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4585 (finished_tags == 0x1)) { 4586 satapkt = ahci_portp->ahciport_err_retri_pkt; 4587 ASSERT(satapkt != NULL); 4588 4589 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4590 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4591 "with SATA_PKT_COMPLETED", (void *)satapkt); 4592 4593 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4594 goto out; 4595 } 4596 4597 while (finished_tags) { 4598 finished_slot = ddi_ffs(finished_tags) - 1; 4599 if (finished_slot == -1) { 4600 goto out; 4601 } 4602 4603 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4604 ASSERT(satapkt != NULL); 4605 4606 /* 4607 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4608 * feature, sata_special_regs flag will be set, and the 4609 * driver should copy the status and the other corresponding 4610 * register values in the D2H Register FIS received (It's 4611 * working on Non-data protocol) from the device back to 4612 * the sata_cmd. 4613 * 4614 * For every AHCI port, there is only one Received FIS 4615 * structure, which contains the FISes received from the 4616 * device, So we're trying to copy the content of D2H 4617 * Register FIS in the Received FIS structure back to 4618 * the sata_cmd. 4619 */ 4620 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4621 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4622 ahcirf_d2h_register_fis); 4623 satapkt->satapkt_cmd.satacmd_status_reg = 4624 GET_RFIS_STATUS(rcvd_fisp); 4625 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4626 } 4627 4628 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4629 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4630 "with SATA_PKT_COMPLETED", (void *)satapkt); 4631 4632 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4633 CLEAR_BIT(finished_tags, finished_slot); 4634 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4635 4636 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4637 } 4638 out: 4639 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4640 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4641 ahci_portp->ahciport_pending_tags); 4642 4643 mutex_exit(&ahci_portp->ahciport_mutex); 4644 4645 return (AHCI_SUCCESS); 4646 } 4647 4648 /* 4649 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4650 * with the 'I' bit set and has been copied into system memory. It will 4651 * be sent under the following situations: 4652 * 4653 * 1. NCQ command is completed 4654 * 2. Asynchronous notification 4655 * 4656 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4657 * via the Set Device Bits FIS. When such event is generated, the software 4658 * needs to read PxSACT register and compares the current value to the 4659 * list of commands previously issue by software. ahciport_pending_ncq_tags 4660 * keeps the tags of previously issued commands. 4661 * 4662 * Asynchronous Notification is a feature in SATA II, which allows an 4663 * ATAPI device to send a signal to the host when media is inserted or 4664 * removed and avoids polling the device for media changes. The signal 4665 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4666 * set to '1'. At the moment, it's not supported yet. 4667 */ 4668 static int 4669 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4670 ahci_port_t *ahci_portp, uint8_t port) 4671 { 4672 uint32_t port_sactive; 4673 uint32_t port_cmd_issue; 4674 uint32_t issued_tags; 4675 int issued_slot; 4676 uint32_t finished_tags; 4677 int finished_slot; 4678 sata_pkt_t *satapkt; 4679 4680 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4681 "ahci_intr_set_device_bits enter: port %d", port); 4682 4683 mutex_enter(&ahci_portp->ahciport_mutex); 4684 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4685 mutex_exit(&ahci_portp->ahciport_mutex); 4686 return (AHCI_SUCCESS); 4687 } 4688 4689 /* 4690 * First the handler got which commands are finished by checking 4691 * PxSACT register 4692 */ 4693 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4694 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4695 4696 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4697 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4698 4699 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4700 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4701 "port_sactive = 0x%x", port, 4702 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4703 4704 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4705 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4706 4707 /* 4708 * For NCQ commands, the software can determine which command has 4709 * already been transmitted to the device by checking PxCI register. 4710 */ 4711 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4712 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4713 4714 issued_tags = ahci_portp->ahciport_pending_tags & 4715 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4716 4717 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4718 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4719 "port_cmd_issue = 0x%x", port, 4720 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4721 4722 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4723 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4724 4725 /* 4726 * Clear ahciport_pending_tags bit when the corresponding command 4727 * is already sent down to the device. 4728 */ 4729 while (issued_tags) { 4730 issued_slot = ddi_ffs(issued_tags) - 1; 4731 if (issued_slot == -1) { 4732 goto next; 4733 } 4734 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4735 CLEAR_BIT(issued_tags, issued_slot); 4736 } 4737 4738 next: 4739 while (finished_tags) { 4740 finished_slot = ddi_ffs(finished_tags) - 1; 4741 if (finished_slot == -1) { 4742 goto out; 4743 } 4744 4745 /* The command is certainly transmitted to the device */ 4746 ASSERT(!(ahci_portp->ahciport_pending_tags & 4747 (0x1 << finished_slot))); 4748 4749 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4750 ASSERT(satapkt != NULL); 4751 4752 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4753 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4754 "with SATA_PKT_COMPLETED", (void *)satapkt); 4755 4756 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4757 CLEAR_BIT(finished_tags, finished_slot); 4758 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4759 4760 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4761 } 4762 out: 4763 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4764 "ahci_intr_set_device_bits: port %d " 4765 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4766 port, ahci_portp->ahciport_pending_ncq_tags, 4767 ahci_portp->ahciport_pending_tags); 4768 4769 mutex_exit(&ahci_portp->ahciport_mutex); 4770 4771 return (AHCI_SUCCESS); 4772 } 4773 4774 /* 4775 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4776 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4777 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4778 * indicates a COMINIT signal was received. 4779 * 4780 * Hot plug insertion is detected by reception of a COMINIT signal from the 4781 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4782 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4783 * begin the normal communication negotiation sequence as outlined in the 4784 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4785 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4786 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4787 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4788 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4789 * to handle hot plug insertion. In this interrupt handler, just do nothing 4790 * but print some log message and clear the bit. 4791 */ 4792 static int 4793 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4794 ahci_port_t *ahci_portp, uint8_t port) 4795 { 4796 uint32_t port_serror; 4797 4798 mutex_enter(&ahci_portp->ahciport_mutex); 4799 4800 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4801 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4802 4803 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4804 "ahci_intr_port_connect_change: port %d, " 4805 "port_serror = 0x%x", port, port_serror); 4806 4807 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4808 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4809 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4810 SERROR_EXCHANGED_ERR); 4811 4812 mutex_exit(&ahci_portp->ahciport_mutex); 4813 4814 return (AHCI_SUCCESS); 4815 } 4816 4817 /* 4818 * Hot Plug Operation for platforms that support Mechanical Presence 4819 * Switches. 4820 * 4821 * When set, it indicates that a mechanical presence switch attached to this 4822 * port has been opened or closed, which may lead to a change in the connection 4823 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4824 * are set to '1'. 4825 * 4826 * At the moment, this interrupt is not needed and disabled and we just log 4827 * the debug message. 4828 */ 4829 /* ARGSUSED */ 4830 static int 4831 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4832 ahci_port_t *ahci_portp, uint8_t port) 4833 { 4834 uint32_t cap_status, port_cmd_status; 4835 4836 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4837 "ahci_intr_device_mechanical_presence_status enter, " 4838 "port %d", port); 4839 4840 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4841 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4842 4843 mutex_enter(&ahci_portp->ahciport_mutex); 4844 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4845 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4846 4847 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4848 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4849 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4850 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4851 "the interrupt: cap_status = 0x%x, " 4852 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4853 mutex_exit(&ahci_portp->ahciport_mutex); 4854 4855 return (AHCI_SUCCESS); 4856 } 4857 4858 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4859 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4860 "The mechanical presence switch is open: " 4861 "port %d, port_cmd_status = 0x%x", 4862 port, port_cmd_status); 4863 } else { 4864 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4865 "The mechanical presence switch is close: " 4866 "port %d, port_cmd_status = 0x%x", 4867 port, port_cmd_status); 4868 } 4869 4870 mutex_exit(&ahci_portp->ahciport_mutex); 4871 4872 return (AHCI_SUCCESS); 4873 } 4874 4875 /* 4876 * Native Hot Plug Support. 4877 * 4878 * When set, it indicates that the internal PHYRDY signal changed state. 4879 * This bit reflects the state of PxSERR.DIAG.N. 4880 * 4881 * There are three kinds of conditions to generate this interrupt event: 4882 * 1. a device is inserted 4883 * 2. a device is disconnected 4884 * 3. when the link enters/exits a Partial or Slumber interface power 4885 * management state 4886 * 4887 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4888 * bit may be set due to the link entering the Partial or Slumber power 4889 * management state, rather than due to a hot plug insertion or removal 4890 * event. So far, the interface power management is disabled, so the 4891 * driver can reliably get removal detection notification via the 4892 * PxSERR.DIAG.N bit. 4893 */ 4894 static int 4895 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4896 ahci_port_t *ahci_portp, uint8_t port) 4897 { 4898 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4899 sata_device_t sdevice; 4900 int dev_exists_now = 0; 4901 int dev_existed_previously = 0; 4902 4903 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4904 "ahci_intr_phyrdy_change enter, port %d", port); 4905 4906 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4907 mutex_enter(&ahci_portp->ahciport_mutex); 4908 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4909 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4910 SERROR_PHY_RDY_CHG); 4911 mutex_exit(&ahci_portp->ahciport_mutex); 4912 4913 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4914 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4915 (ahci_portp == NULL)) { 4916 /* The whole controller setup is not yet done. */ 4917 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4918 return (AHCI_SUCCESS); 4919 } 4920 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4921 4922 mutex_enter(&ahci_portp->ahciport_mutex); 4923 4924 /* SStatus tells the presence of device. */ 4925 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4926 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4927 4928 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 4929 dev_exists_now = 1; 4930 } 4931 4932 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4933 dev_existed_previously = 1; 4934 } 4935 4936 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 4937 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 4938 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4939 "ahci_intr_phyrdy_change: port %d " 4940 "AHCI_PORT_FLAG_NODEV is cleared", port); 4941 if (dev_exists_now == 0) 4942 dev_existed_previously = 1; 4943 } 4944 4945 bzero((void *)&sdevice, sizeof (sata_device_t)); 4946 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4947 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4948 sdevice.satadev_addr.pmport = 0; 4949 sdevice.satadev_state = SATA_PSTATE_PWRON; 4950 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4951 4952 if (dev_exists_now) { 4953 if (dev_existed_previously) { 4954 /* Things are fine now. The loss was temporary. */ 4955 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4956 "ahci_intr_phyrdy_change port %d " 4957 "device link lost/established", port); 4958 4959 mutex_exit(&ahci_portp->ahciport_mutex); 4960 sata_hba_event_notify( 4961 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4962 &sdevice, 4963 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4964 mutex_enter(&ahci_portp->ahciport_mutex); 4965 4966 } else { 4967 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4968 "ahci_intr_phyrdy_change: port %d " 4969 "device link established", port); 4970 4971 /* A new device has been detected. */ 4972 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 4973 4974 /* Try to start the port */ 4975 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4976 != AHCI_SUCCESS) { 4977 sdevice.satadev_state |= SATA_PSTATE_FAILED; 4978 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4979 "ahci_intr_phyrdy_change: port %d failed " 4980 "at start port", port); 4981 } 4982 4983 /* Clear the max queue depth for inserted device */ 4984 ahci_portp->ahciport_max_ncq_tags = 0; 4985 4986 mutex_exit(&ahci_portp->ahciport_mutex); 4987 sata_hba_event_notify( 4988 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4989 &sdevice, 4990 SATA_EVNT_LINK_ESTABLISHED); 4991 mutex_enter(&ahci_portp->ahciport_mutex); 4992 4993 } 4994 } else { /* No device exists now */ 4995 4996 if (dev_existed_previously) { 4997 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4998 "ahci_intr_phyrdy_change: port %d " 4999 "device link lost", port); 5000 5001 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 5002 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 5003 ahci_portp, port); 5004 5005 /* An existing device is lost. */ 5006 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 5007 5008 mutex_exit(&ahci_portp->ahciport_mutex); 5009 sata_hba_event_notify( 5010 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5011 &sdevice, 5012 SATA_EVNT_LINK_LOST); 5013 mutex_enter(&ahci_portp->ahciport_mutex); 5014 5015 } else { 5016 5017 /* Spurious interrupt */ 5018 AHCIDBG0(AHCIDBG_INTR, ahci_ctlp, 5019 "ahci_intr_phyrdy_change: " 5020 "spurious phy ready interrupt"); 5021 } 5022 } 5023 5024 mutex_exit(&ahci_portp->ahciport_mutex); 5025 5026 return (AHCI_SUCCESS); 5027 } 5028 5029 /* 5030 * PxIS.UFS - Unknown FIS Error 5031 * 5032 * This interrupt event means an unknown FIS was received and has been 5033 * copied into system memory. An unknown FIS is not considered an illegal 5034 * FIS, unless the length received is more than 64 bytes. If an unknown 5035 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 5036 * normal operation. If the unknown FIS is more than 64 bytes, then it 5037 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 5038 * a fatal error. 5039 * 5040 * PxIS.OFS - Overflow Error 5041 * 5042 * Command list overflow is defined as software building a command table 5043 * that has fewer total bytes than the transaction given to the device. 5044 * On device writes, the HBA will run out of data, and on reads, there 5045 * will be no room to put the data. 5046 * 5047 * For an overflow on data read, either PIO or DMA, the HBA will set 5048 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 5049 * non-fatal error when the HBA can continues. Sometimes, it will cause 5050 * a fatal error and need the software to do something. 5051 * 5052 * For an overflow on data write, setting PxIS.OFS is optional for both 5053 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 5054 * software to clean up from this serious error. 5055 * 5056 * PxIS.INFS - Interface Non-Fatal Error 5057 * 5058 * This interrupt event indicates that the HBA encountered an error on 5059 * the Serial ATA interface but was able to continue operation. The kind 5060 * of error usually occurred during a non-Data FIS, and under this condition 5061 * the FIS will be re-transmitted by HBA automatically. 5062 * 5063 * When the FMA is implemented, there should be a stat structure to 5064 * record how many every kind of error happens. 5065 */ 5066 static int 5067 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5068 uint8_t port, uint32_t intr_status) 5069 { 5070 uint32_t port_serror; 5071 #if AHCI_DEBUG 5072 uint32_t port_cmd_status; 5073 uint32_t port_cmd_issue; 5074 uint32_t port_sactive; 5075 int current_slot; 5076 uint32_t current_tags; 5077 sata_pkt_t *satapkt; 5078 #endif 5079 5080 mutex_enter(&ahci_portp->ahciport_mutex); 5081 5082 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5083 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5084 5085 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 5086 "ahci_intr_non_fatal_error: port %d, " 5087 "port_serror = 0x%x", port, port_serror); 5088 5089 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1); 5090 5091 if (intr_status & AHCI_INTR_STATUS_UFS) { 5092 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5093 "ahci port %d has unknown FIS error", port); 5094 5095 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 5096 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5097 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5098 SERROR_FIS_TYPE); 5099 } 5100 5101 #if AHCI_DEBUG 5102 if (intr_status & AHCI_INTR_STATUS_OFS) { 5103 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5104 "ahci port %d has overflow error", port); 5105 } 5106 5107 if (intr_status & AHCI_INTR_STATUS_INFS) { 5108 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5109 "ahci port %d has interface non fatal error", port); 5110 } 5111 5112 /* 5113 * Record the error occurred command's slot. 5114 */ 5115 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 5116 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5117 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5118 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5119 5120 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5121 AHCI_CMD_STATUS_CCS_SHIFT; 5122 5123 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5124 satapkt = ahci_portp->ahciport_err_retri_pkt; 5125 ASSERT(satapkt != NULL); 5126 ASSERT(current_slot == 0); 5127 } else { 5128 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5129 } 5130 5131 if (satapkt != NULL) { 5132 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5133 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 5134 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 5135 satapkt->satapkt_cmd.satacmd_cmd_reg); 5136 5137 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5138 "ahci_intr_non_fatal_error: port %d, " 5139 "satapkt 0x%p is being processed when error occurs", 5140 port, (void *)satapkt); 5141 } 5142 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5143 /* 5144 * For queued command, list those command which have already 5145 * been transmitted to the device and still not completed. 5146 */ 5147 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5148 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 5149 5150 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5151 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5152 5153 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 5154 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 5155 "port_sactive = 0x%x port_cmd_issue = 0x%x", 5156 ahci_portp->ahciport_pending_ncq_tags, 5157 port_sactive, port_cmd_issue); 5158 5159 current_tags = ahci_portp->ahciport_pending_ncq_tags & 5160 port_sactive & ~port_cmd_issue & 5161 AHCI_NCQ_SLOT_MASK(ahci_portp); 5162 5163 while (current_tags) { 5164 current_slot = ddi_ffs(current_tags) - 1; 5165 if (current_slot == -1) { 5166 goto out; 5167 } 5168 5169 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5170 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 5171 ahci_ctlp, "ahci_intr_non_fatal_error: " 5172 "port %d, satapkt 0x%p is outstanding when " 5173 "error occurs", port, (void *)satapkt); 5174 } 5175 } 5176 out: 5177 #endif 5178 mutex_exit(&ahci_portp->ahciport_mutex); 5179 5180 return (AHCI_SUCCESS); 5181 } 5182 5183 /* 5184 * According to the AHCI spec, the error types include system memory 5185 * errors, interface errors, port multiplier errors, device errors, 5186 * command list overflow, command list underflow, native command 5187 * queuing tag errors and pio data transfer errors. 5188 * 5189 * System memory errors such as target abort, master abort, and parity 5190 * may cause the host to stop, and they are serious errors and needed 5191 * to be recovered with software intervention. When system software 5192 * has given a pointer to the HBA that doesn't exist in physical memory, 5193 * a master/target abort error occurs, and PxIS.HBFS will be set. A 5194 * data error such as CRC or parity occurs, the HBA aborts the transfer 5195 * (if necessary) and PxIS.HBDS will be set. 5196 * 5197 * Interface errors are errors that occur due to electrical issues on 5198 * the interface, or protocol miscommunication between the device and 5199 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 5200 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 5201 * causes PxIS.IFS/PxIS.INFS to be set are 5202 * 1. in PxSERR.ERR, P bit is set to '1' 5203 * 2. in PxSERR.DIAG, C or H bit is set to '1' 5204 * 3. PhyRdy drop unexpectly, N bit is set to '1' 5205 * If the error occurred during a non-data FIS, the FIS must be 5206 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 5207 * the error occurred during a data FIS, the transfer will stop, so 5208 * the error is fatal and PxIS.IFS is set. 5209 * 5210 * When a FIS arrives that updates the taskfile, the HBA checks to see 5211 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 5212 * stops processing any more commands. 5213 * 5214 * Command list overflow is defined as software building a command table 5215 * that has fewer total bytes than the transaction given to the device. 5216 * On device writes, the HBA will run out of data, and on reads, there 5217 * will be no room to put the data. For an overflow on data read, either 5218 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 5219 * For an overflow on data write, setting PxIS.OFS is optional for both 5220 * DMA and PIO, and a COMRESET is required by software to clean up from 5221 * this serious error. 5222 * 5223 * Command list underflow is defined as software building a command 5224 * table that has more total bytes than the transaction given to the 5225 * device. For data writes, both PIO and DMA, the device will detect 5226 * an error and end the transfer. And these errors are most likely going 5227 * to be fatal errors that will cause the port to be restarted. For 5228 * data reads, the HBA updates its PRD byte count, and may be 5229 * able to continue normally, but is not required to. And The HBA is 5230 * not required to detect underflow conditions for native command 5231 * queuing command. 5232 * 5233 * The HBA does not actively check incoming DMA Setup FISes to ensure 5234 * that the PxSACT register bit for that slot is set. Existing error 5235 * mechanisms, such as host bus failure, or bad protocol, are used to 5236 * recover from this case. 5237 * 5238 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 5239 * DATA FIS must be an integral number of Dwords. If the HBA receives 5240 * a request which is not an integral number of Dwords, the HBA 5241 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 5242 * software restarts the port. And the HBA ensures that the size 5243 * of the DATA FIS received during a PIO command matches the size in 5244 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 5245 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 5246 * stop running until software restarts the port. 5247 */ 5248 /* 5249 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 5250 * 5251 * PxIS.IFS indicates that the hba encountered an error on the serial ata 5252 * interface which caused the transfer to stop. 5253 * 5254 * PxIS.HBDS indicates that the hba encountered a data error 5255 * (uncorrectable ecc/parity) when reading from or writing to system memory. 5256 * 5257 * PxIS.HBFS indicates that the hba encountered a host bus error that it 5258 * cannot recover from, such as a bad software pointer. 5259 * 5260 * PxIS.TFES is set whenever the status register is updated by the device 5261 * and the error bit (bit 0) is set. 5262 */ 5263 static int 5264 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 5265 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 5266 { 5267 uint32_t port_cmd_status; 5268 uint32_t port_serror; 5269 uint32_t task_file_status; 5270 int failed_slot; 5271 sata_pkt_t *spkt = NULL; 5272 uint8_t err_byte; 5273 ahci_event_arg_t *args; 5274 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 5275 5276 mutex_enter(&ahci_portp->ahciport_mutex); 5277 5278 /* 5279 * ahci_intr_phyrdy_change() may have rendered it to 5280 * SATA_DTYPE_NONE. 5281 */ 5282 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5283 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5284 "ahci_intr_fatal_error: port %d no device attached, " 5285 "and just return without doing anything", port); 5286 goto out0; 5287 } 5288 5289 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5290 /* 5291 * Read PxCMD.CCS to determine the slot that the HBA 5292 * was processing when the error occurred. 5293 */ 5294 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5295 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5296 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5297 AHCI_CMD_STATUS_CCS_SHIFT; 5298 5299 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5300 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5301 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5302 "fatal error occurred for port %d", spkt, port); 5303 5304 if (intr_status & AHCI_INTR_STATUS_TFES) { 5305 task_file_status = ddi_get32( 5306 ahci_ctlp->ahcictl_ahci_acc_handle, 5307 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5308 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5309 "ahci_intr_fatal_error: port %d " 5310 "task_file_status = 0x%x", port, task_file_status); 5311 5312 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5313 >> AHCI_TFD_ERR_SHIFT; 5314 5315 /* 5316 * Won't emit the error message if it is an IDENTIFY 5317 * DEVICE command sent to an ATAPI device. 5318 */ 5319 if ((spkt != NULL) && 5320 (spkt->satapkt_cmd.satacmd_cmd_reg == 5321 SATAC_ID_DEVICE) && 5322 (err_byte == SATA_ERROR_ABORT)) 5323 goto out1; 5324 5325 /* 5326 * Won't emit the error message if it is an ATAPI PACKET 5327 * command 5328 */ 5329 if ((spkt != NULL) && 5330 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5331 goto out1; 5332 } 5333 } 5334 5335 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5336 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5337 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5338 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0); 5339 out1: 5340 /* Prepare the argument for the taskq */ 5341 args = ahci_portp->ahciport_event_args; 5342 args->ahciea_ctlp = (void *)ahci_ctlp; 5343 args->ahciea_portp = (void *)ahci_portp; 5344 args->ahciea_event = intr_status; 5345 5346 /* Start the taskq to handle error recovery */ 5347 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 5348 ahci_events_handler, 5349 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5350 cmn_err(CE_WARN, "!ahci%d: ahci start taskq for event handler " 5351 "failed", instance); 5352 } 5353 out0: 5354 mutex_exit(&ahci_portp->ahciport_mutex); 5355 5356 return (AHCI_SUCCESS); 5357 } 5358 5359 /* 5360 * Hot Plug Operation for platforms that support Cold Presence Detect. 5361 * 5362 * When set, a device status has changed as detected by the cold presence 5363 * detect logic. This bit can either be set due to a non-connected port 5364 * receiving a device, or a connected port having its device removed. 5365 * This bit is only valid if the port supports cold presence detect as 5366 * indicated by PxCMD.CPD set to '1'. 5367 * 5368 * At the moment, this interrupt is not needed and disabled and we just 5369 * log the debug message. 5370 */ 5371 /* ARGSUSED */ 5372 static int 5373 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5374 ahci_port_t *ahci_portp, uint8_t port) 5375 { 5376 uint32_t port_cmd_status; 5377 sata_device_t sdevice; 5378 5379 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5380 "ahci_intr_cold_port_detect enter, port %d", port); 5381 5382 mutex_enter(&ahci_portp->ahciport_mutex); 5383 5384 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5385 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5386 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5387 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5388 "port %d does not support cold presence detect, so " 5389 "we just ignore this interrupt", port); 5390 mutex_exit(&ahci_portp->ahciport_mutex); 5391 return (AHCI_SUCCESS); 5392 } 5393 5394 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5395 "port %d device status has changed", port); 5396 5397 bzero((void *)&sdevice, sizeof (sata_device_t)); 5398 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5399 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5400 sdevice.satadev_addr.pmport = 0; 5401 sdevice.satadev_state = SATA_PSTATE_PWRON; 5402 5403 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5404 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5405 "port %d: a device is hot plugged", port); 5406 mutex_exit(&ahci_portp->ahciport_mutex); 5407 sata_hba_event_notify( 5408 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5409 &sdevice, 5410 SATA_EVNT_DEVICE_ATTACHED); 5411 mutex_enter(&ahci_portp->ahciport_mutex); 5412 5413 } else { 5414 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5415 "port %d: a device is hot unplugged", port); 5416 mutex_exit(&ahci_portp->ahciport_mutex); 5417 sata_hba_event_notify( 5418 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5419 &sdevice, 5420 SATA_EVNT_DEVICE_DETACHED); 5421 mutex_enter(&ahci_portp->ahciport_mutex); 5422 } 5423 5424 mutex_exit(&ahci_portp->ahciport_mutex); 5425 5426 return (AHCI_SUCCESS); 5427 } 5428 5429 /* 5430 * Enable the interrupts for a particular port. 5431 * 5432 * WARNING!!! ahciport_mutex should be acquired before the function 5433 * is called. 5434 */ 5435 /* ARGSUSED */ 5436 static void 5437 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, 5438 ahci_port_t *ahci_portp, uint8_t port) 5439 { 5440 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5441 "ahci_enable_port_intrs enter, port %d", port); 5442 5443 /* 5444 * Clear port interrupt status before enabling interrupt 5445 */ 5446 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5447 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5448 AHCI_PORT_INTR_MASK); 5449 5450 /* 5451 * Clear the pending bit from IS.IPS 5452 */ 5453 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5454 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5455 5456 /* 5457 * Enable the following interrupts: 5458 * Device to Host Register FIS Interrupt (DHRS) 5459 * PIO Setup FIS Interrupt (PSS) 5460 * Set Device Bits Interrupt (SDBS) 5461 * Unknown FIS Interrupt (UFS) 5462 * Port Connect Change Status (PCS) 5463 * PhyRdy Change Status (PRCS) 5464 * Overflow Status (OFS) 5465 * Interface Non-fatal Error Status (INFS) 5466 * Interface Fatal Error Status (IFS) 5467 * Host Bus Data Error Status (HBDS) 5468 * Host Bus Fatal Error Status (HBFS) 5469 * Task File Error Status (TFES) 5470 */ 5471 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5472 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5473 (AHCI_INTR_STATUS_DHRS | 5474 AHCI_INTR_STATUS_PSS | 5475 AHCI_INTR_STATUS_SDBS | 5476 AHCI_INTR_STATUS_UFS | 5477 AHCI_INTR_STATUS_DPS | 5478 AHCI_INTR_STATUS_PCS | 5479 AHCI_INTR_STATUS_PRCS | 5480 AHCI_INTR_STATUS_OFS | 5481 AHCI_INTR_STATUS_INFS | 5482 AHCI_INTR_STATUS_IFS | 5483 AHCI_INTR_STATUS_HBDS | 5484 AHCI_INTR_STATUS_HBFS | 5485 AHCI_INTR_STATUS_TFES)); 5486 } 5487 5488 /* 5489 * Enable interrupts for all the ports. 5490 * 5491 * WARNING!!! ahcictl_mutex should be acquired before the function 5492 * is called. 5493 */ 5494 static void 5495 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5496 { 5497 uint32_t ghc_control; 5498 5499 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5500 5501 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5502 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5503 5504 ghc_control |= AHCI_HBA_GHC_IE; 5505 5506 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5507 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5508 } 5509 5510 /* 5511 * Disable interrupts for a particular port. 5512 * 5513 * WARNING!!! ahciport_mutex should be acquired before the function 5514 * is called. 5515 */ 5516 /* ARGSUSED */ 5517 static void 5518 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, 5519 ahci_port_t *ahci_portp, uint8_t port) 5520 { 5521 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5522 "ahci_disable_port_intrs enter, port %d", port); 5523 5524 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5525 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5526 } 5527 5528 /* 5529 * Disable interrupts for the whole HBA. 5530 * 5531 * The global bit is cleared, then all interrupt sources from all 5532 * ports are disabled. 5533 * 5534 * WARNING!!! ahcictl_mutex should be acquired before the function 5535 * is called. 5536 */ 5537 static void 5538 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5539 { 5540 uint32_t ghc_control; 5541 5542 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5543 5544 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5545 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5546 5547 ghc_control &= ~ AHCI_HBA_GHC_IE; 5548 5549 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5550 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5551 } 5552 5553 /* 5554 * Handle INTx and legacy interrupts. 5555 */ 5556 static int 5557 ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 5558 { 5559 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5560 int actual, count = 0; 5561 int x, y, rc, inum = 0; 5562 5563 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5564 "ahci_add_legacy_intrs enter"); 5565 5566 /* get number of interrupts. */ 5567 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 5568 if ((rc != DDI_SUCCESS) || (count == 0)) { 5569 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5570 "ddi_intr_get_nintrs() failed, " 5571 "rc %d count %d\n", rc, count); 5572 return (DDI_FAILURE); 5573 } 5574 5575 /* Allocate an array of interrupt handles. */ 5576 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5577 ahci_ctlp->ahcictl_intr_htable = 5578 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5579 5580 /* call ddi_intr_alloc(). */ 5581 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5582 DDI_INTR_TYPE_FIXED, 5583 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 5584 5585 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5586 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5587 "ddi_intr_alloc() failed, rc %d\n", rc); 5588 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5589 ahci_ctlp->ahcictl_intr_size); 5590 return (DDI_FAILURE); 5591 } 5592 5593 if (actual < count) { 5594 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5595 "Requested: %d, Received: %d", count, actual); 5596 5597 for (x = 0; x < actual; x++) { 5598 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5599 } 5600 5601 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5602 ahci_ctlp->ahcictl_intr_size); 5603 return (DDI_FAILURE); 5604 } 5605 5606 ahci_ctlp->ahcictl_intr_cnt = actual; 5607 5608 /* Get intr priority. */ 5609 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5610 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5611 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5612 "ddi_intr_get_pri() failed"); 5613 5614 for (x = 0; x < actual; x++) { 5615 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5616 } 5617 5618 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5619 ahci_ctlp->ahcictl_intr_size); 5620 return (DDI_FAILURE); 5621 } 5622 5623 /* Test for high level interrupt. */ 5624 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5625 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5626 "ahci_add_legacy_intrs: Hi level intr not supported"); 5627 5628 for (x = 0; x < actual; x++) { 5629 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5630 } 5631 5632 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5633 sizeof (ddi_intr_handle_t)); 5634 5635 return (DDI_FAILURE); 5636 } 5637 5638 /* Call ddi_intr_add_handler(). */ 5639 for (x = 0; x < actual; x++) { 5640 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5641 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5642 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5643 "ddi_intr_add_handler() failed"); 5644 5645 for (y = 0; y < actual; y++) { 5646 (void) ddi_intr_free( 5647 ahci_ctlp->ahcictl_intr_htable[y]); 5648 } 5649 5650 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5651 ahci_ctlp->ahcictl_intr_size); 5652 return (DDI_FAILURE); 5653 } 5654 } 5655 5656 /* Call ddi_intr_enable() for legacy interrupts. */ 5657 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5658 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 5659 } 5660 5661 return (DDI_SUCCESS); 5662 } 5663 5664 /* 5665 * Handle MSI interrupts. 5666 */ 5667 static int 5668 ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 5669 { 5670 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5671 int count, avail, actual; 5672 int x, y, rc, inum = 0; 5673 5674 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5675 "ahci_add_msi_intrs enter"); 5676 5677 /* get number of interrupts. */ 5678 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 5679 if ((rc != DDI_SUCCESS) || (count == 0)) { 5680 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5681 "ddi_intr_get_nintrs() failed, " 5682 "rc %d count %d\n", rc, count); 5683 return (DDI_FAILURE); 5684 } 5685 5686 /* get number of available interrupts. */ 5687 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 5688 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5689 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5690 "ddi_intr_get_navail() failed, " 5691 "rc %d avail %d\n", rc, avail); 5692 return (DDI_FAILURE); 5693 } 5694 5695 if (avail < count) { 5696 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5697 "ddi_intr_get_nvail returned %d, navail() returned %d", 5698 count, avail); 5699 } 5700 5701 /* Allocate an array of interrupt handles. */ 5702 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5703 ahci_ctlp->ahcictl_intr_htable = 5704 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5705 5706 /* call ddi_intr_alloc(). */ 5707 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5708 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5709 5710 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5711 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5712 "ddi_intr_alloc() failed, rc %d\n", rc); 5713 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5714 ahci_ctlp->ahcictl_intr_size); 5715 return (DDI_FAILURE); 5716 } 5717 5718 /* use interrupt count returned */ 5719 if (actual < count) { 5720 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5721 "Requested: %d, Received: %d", count, actual); 5722 } 5723 5724 ahci_ctlp->ahcictl_intr_cnt = actual; 5725 5726 /* 5727 * Get priority for first msi, assume remaining are all the same. 5728 */ 5729 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5730 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5731 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5732 "ddi_intr_get_pri() failed"); 5733 5734 /* Free already allocated intr. */ 5735 for (y = 0; y < actual; y++) { 5736 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5737 } 5738 5739 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5740 ahci_ctlp->ahcictl_intr_size); 5741 return (DDI_FAILURE); 5742 } 5743 5744 /* Test for high level interrupt. */ 5745 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5746 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5747 "ahci_add_msi_intrs: Hi level intr not supported"); 5748 5749 /* Free already allocated intr. */ 5750 for (y = 0; y < actual; y++) { 5751 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5752 } 5753 5754 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5755 sizeof (ddi_intr_handle_t)); 5756 5757 return (DDI_FAILURE); 5758 } 5759 5760 /* Call ddi_intr_add_handler(). */ 5761 for (x = 0; x < actual; x++) { 5762 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5763 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5764 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5765 "ddi_intr_add_handler() failed"); 5766 5767 /* Free already allocated intr. */ 5768 for (y = 0; y < actual; y++) { 5769 (void) ddi_intr_free( 5770 ahci_ctlp->ahcictl_intr_htable[y]); 5771 } 5772 5773 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5774 ahci_ctlp->ahcictl_intr_size); 5775 return (DDI_FAILURE); 5776 } 5777 } 5778 5779 5780 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5781 &ahci_ctlp->ahcictl_intr_cap); 5782 5783 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5784 /* Call ddi_intr_block_enable() for MSI. */ 5785 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5786 ahci_ctlp->ahcictl_intr_cnt); 5787 } else { 5788 /* Call ddi_intr_enable() for MSI non block enable. */ 5789 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5790 (void) ddi_intr_enable( 5791 ahci_ctlp->ahcictl_intr_htable[x]); 5792 } 5793 } 5794 5795 return (DDI_SUCCESS); 5796 } 5797 5798 /* 5799 * Removes the registered interrupts irrespective of whether they 5800 * were legacy or MSI. 5801 * 5802 * WARNING!!! The controller interrupts must be disabled before calling 5803 * this routine. 5804 */ 5805 static void 5806 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5807 { 5808 int x; 5809 5810 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5811 5812 /* Disable all interrupts. */ 5813 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5814 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5815 /* Call ddi_intr_block_disable(). */ 5816 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5817 ahci_ctlp->ahcictl_intr_cnt); 5818 } else { 5819 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5820 (void) ddi_intr_disable( 5821 ahci_ctlp->ahcictl_intr_htable[x]); 5822 } 5823 } 5824 5825 /* Call ddi_intr_remove_handler(). */ 5826 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5827 (void) ddi_intr_remove_handler( 5828 ahci_ctlp->ahcictl_intr_htable[x]); 5829 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5830 } 5831 5832 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5833 } 5834 5835 /* 5836 * This routine tries to put port into P:NotRunning state by clearing 5837 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5838 * and PxCMD.CR to '0'. 5839 * 5840 * WARNING!!! ahciport_mutex should be acquired before the function 5841 * is called. 5842 */ 5843 /* ARGSUSED */ 5844 static int 5845 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5846 ahci_port_t *ahci_portp, uint8_t port) 5847 { 5848 uint32_t port_cmd_status; 5849 int loop_count; 5850 5851 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5852 "ahci_put_port_into_notrunning_state enter: port %d", port); 5853 5854 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5855 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5856 5857 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5858 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5859 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5860 5861 /* Wait until PxCMD.CR is cleared */ 5862 loop_count = 0; 5863 do { 5864 port_cmd_status = 5865 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5866 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5867 5868 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5869 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5870 "clearing port %d CMD.CR timeout, " 5871 "port_cmd_status = 0x%x", port, 5872 port_cmd_status); 5873 /* 5874 * We are effectively timing out after 0.5 sec. 5875 * This value is specified in AHCI spec. 5876 */ 5877 break; 5878 } 5879 5880 /* Wait for 10 millisec */ 5881 #ifndef __lock_lint 5882 delay(AHCI_10MS_TICKS); 5883 #endif /* __lock_lint */ 5884 5885 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5886 5887 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5888 5889 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5890 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5891 "ahci_put_port_into_notrunning_state: failed to clear " 5892 "PxCMD.CR to '0' after loop count: %d, and " 5893 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5894 return (AHCI_FAILURE); 5895 } else { 5896 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5897 "ahci_put_port_into_notrunning_state: succeeded to clear " 5898 "PxCMD.CR to '0' after loop count: %d, and " 5899 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5900 return (AHCI_SUCCESS); 5901 } 5902 } 5903 5904 /* 5905 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5906 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5907 * stable state, then set PxCMD.ST to '1' to start the port directly. 5908 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5909 * COMRESET to the device to put it in an idle state. 5910 * 5911 * The fifth argument returns whether the port reset is involved during 5912 * the process. 5913 * 5914 * The routine will be called under six scenarios: 5915 * 1. Initialize the port 5916 * 2. To abort the packet(s) 5917 * 3. To reset the port 5918 * 4. To activate the port 5919 * 5. Fatal error recovery 5920 * 6. To abort the timeout packet(s) 5921 * 5922 * WARNING!!! ahciport_mutex should be acquired before the function 5923 * is called. And ahciport_mutex will be released before the reset 5924 * event is reported to sata module by calling sata_hba_event_notify, 5925 * and then be acquired again later. 5926 * 5927 * NOTES!!! During this procedure, PxSERR register will be cleared, and 5928 * according to the spec, the clearance of three bits will also clear 5929 * three interrupt status bits. 5930 * 1. PxSERR.DIAG.F will clear PxIS.UFS 5931 * 2. PxSERR.DIAG.X will clear PxIS.PCS 5932 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 5933 * 5934 * Among these three interrupt events, the driver needs to take care of 5935 * PxIS.PRCS, which is the hot plug event. When the driver found out 5936 * a device was unplugged, it will call the interrupt handler. 5937 */ 5938 static int 5939 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5940 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 5941 { 5942 uint32_t port_sstatus; 5943 uint32_t task_file_status; 5944 sata_device_t sdevice; 5945 int rval; 5946 int dev_exists_begin = 0; 5947 int dev_exists_end = 0; 5948 5949 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5950 "ahci_restart_port_wait_till_ready: port %d enter", port); 5951 5952 if ((flag != AHCI_PORT_INIT) && 5953 (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE)) 5954 dev_exists_begin = 1; 5955 5956 /* First clear PxCMD.ST */ 5957 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 5958 port); 5959 if (rval != AHCI_SUCCESS) 5960 /* 5961 * If PxCMD.CR does not clear within a reasonable time, it 5962 * may assume the interface is in a hung condition and may 5963 * continue with issuing the port reset. 5964 */ 5965 goto reset; 5966 5967 /* Then clear PxSERR */ 5968 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5969 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5970 AHCI_SERROR_CLEAR_ALL); 5971 5972 /* Then get PxTFD */ 5973 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5974 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5975 5976 /* 5977 * Check whether the device is in a stable status, if yes, 5978 * then start the port directly. However for ahci_tran_dport_reset, 5979 * we may have to perform a port reset. 5980 */ 5981 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 5982 !(flag & AHCI_PORT_RESET)) 5983 goto out; 5984 5985 reset: 5986 /* 5987 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 5988 * a COMRESET to the device 5989 */ 5990 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 5991 if (rval != AHCI_SUCCESS) 5992 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5993 "ahci_restart_port_wait_till_ready: port %d failed", 5994 port); 5995 5996 if (reset_flag != NULL) 5997 *reset_flag = 1; 5998 5999 /* Indicate to the framework that a reset has happened. */ 6000 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 6001 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 6002 /* Set the reset in progress flag */ 6003 ahci_portp->ahciport_reset_in_progress = 1; 6004 6005 bzero((void *)&sdevice, sizeof (sata_device_t)); 6006 sdevice.satadev_addr.cport = 6007 ahci_ctlp->ahcictl_port_to_cport[port]; 6008 sdevice.satadev_addr.pmport = 0; 6009 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6010 6011 sdevice.satadev_state = SATA_DSTATE_RESET | 6012 SATA_DSTATE_PWR_ACTIVE; 6013 if (ahci_ctlp->ahcictl_sata_hba_tran) { 6014 mutex_exit(&ahci_portp->ahciport_mutex); 6015 sata_hba_event_notify( 6016 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 6017 &sdevice, 6018 SATA_EVNT_DEVICE_RESET); 6019 mutex_enter(&ahci_portp->ahciport_mutex); 6020 } 6021 6022 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 6023 "port %d sending event up: SATA_EVNT_RESET", port); 6024 } else { 6025 ahci_portp->ahciport_reset_in_progress = 0; 6026 } 6027 6028 out: 6029 /* Start the port if not in initialization phase */ 6030 if (flag & AHCI_PORT_INIT) 6031 return (rval); 6032 6033 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 6034 6035 /* SStatus tells the presence of device. */ 6036 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6037 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 6038 6039 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 6040 dev_exists_end = 1; 6041 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 6042 } 6043 6044 /* Check whether a hot plug event happened */ 6045 if (dev_exists_begin == 1 && dev_exists_end == 0) { 6046 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6047 "ahci_restart_port_wait_till_ready: port %d " 6048 "device is removed", port); 6049 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 6050 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6051 "ahci_restart_port_wait_till_ready: port %d " 6052 "AHCI_PORT_FLAG_NODEV flag is set", port); 6053 mutex_exit(&ahci_portp->ahciport_mutex); 6054 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 6055 mutex_enter(&ahci_portp->ahciport_mutex); 6056 } 6057 6058 return (rval); 6059 } 6060 6061 /* 6062 * This routine may be called under four scenarios: 6063 * a) do the recovery from fatal error 6064 * b) or we need to timeout some commands 6065 * c) or we need to abort some commands 6066 * d) or we need reset device/port/controller 6067 * 6068 * In all these scenarios, we need to send any pending unfinished 6069 * commands up to sata framework. 6070 * 6071 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6072 */ 6073 static void 6074 ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 6075 ahci_port_t *ahci_portp, 6076 uint8_t port, 6077 uint32_t slot_status, 6078 uint32_t failed_tags, 6079 uint32_t timeout_tags, 6080 uint32_t aborted_tags, 6081 uint32_t reset_tags) 6082 { 6083 uint32_t finished_tags = 0; 6084 uint32_t unfinished_tags = 0; 6085 int tmp_slot; 6086 sata_pkt_t *satapkt; 6087 int ncq_cmd_in_progress = 0; 6088 int err_retri_cmd_in_progress = 0; 6089 6090 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6091 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 6092 port, slot_status); 6093 6094 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6095 "ahci_mop_commands: failed_tags: 0x%x, " 6096 "timeout_tags: 0x%x aborted_tags: 0x%x, " 6097 "reset_tags: 0x%x", failed_tags, 6098 timeout_tags, aborted_tags, reset_tags); 6099 6100 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6101 finished_tags = ahci_portp->ahciport_pending_tags & 6102 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6103 6104 unfinished_tags = slot_status & 6105 AHCI_SLOT_MASK(ahci_ctlp) & 6106 ~failed_tags & 6107 ~aborted_tags & 6108 ~reset_tags & 6109 ~timeout_tags; 6110 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6111 ncq_cmd_in_progress = 1; 6112 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6113 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6114 6115 unfinished_tags = slot_status & 6116 AHCI_NCQ_SLOT_MASK(ahci_portp) & 6117 ~failed_tags & 6118 ~aborted_tags & 6119 ~reset_tags & 6120 ~timeout_tags; 6121 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6122 6123 /* 6124 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is 6125 * set, it means REQUEST SENSE or READ LOG EXT command doesn't 6126 * complete successfully due to one of the following three 6127 * conditions: 6128 * 6129 * 1. Fatal error - failed_tags includes its slot 6130 * 2. Timed out - timeout_tags includes its slot 6131 * 3. Aborted when hot unplug - aborted_tags includes its 6132 * slot 6133 * 6134 * Please note that the command is always sent down in Slot 0 6135 */ 6136 err_retri_cmd_in_progress = 1; 6137 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 6138 "ahci_mop_commands is called for port %d while " 6139 "REQUEST SENSE or READ LOG EXT for error retrieval " 6140 "is being executed", port); 6141 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 6142 ASSERT(slot_status == 0x1); 6143 } 6144 6145 /* Send up finished packets with SATA_PKT_COMPLETED */ 6146 while (finished_tags) { 6147 tmp_slot = ddi_ffs(finished_tags) - 1; 6148 if (tmp_slot == -1) { 6149 break; 6150 } 6151 6152 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6153 ASSERT(satapkt != NULL); 6154 6155 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 6156 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 6157 (void *)satapkt); 6158 6159 /* 6160 * Cannot fetch the return register content since the port 6161 * was restarted, so the corresponding tag will be set to 6162 * aborted tags. 6163 */ 6164 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6165 CLEAR_BIT(finished_tags, tmp_slot); 6166 aborted_tags |= tmp_slot; 6167 continue; 6168 } 6169 6170 if (ncq_cmd_in_progress) 6171 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6172 tmp_slot); 6173 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6174 CLEAR_BIT(finished_tags, tmp_slot); 6175 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6176 6177 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6178 } 6179 6180 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 6181 while (failed_tags) { 6182 if (err_retri_cmd_in_progress) { 6183 satapkt = ahci_portp->ahciport_err_retri_pkt; 6184 ASSERT(satapkt != NULL); 6185 ASSERT(failed_tags == 0x1); 6186 6187 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6188 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6189 (void *)satapkt); 6190 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6191 break; 6192 } 6193 6194 tmp_slot = ddi_ffs(failed_tags) - 1; 6195 if (tmp_slot == -1) { 6196 break; 6197 } 6198 6199 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6200 ASSERT(satapkt != NULL); 6201 6202 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6203 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6204 (void *)satapkt); 6205 6206 if (ncq_cmd_in_progress) 6207 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6208 tmp_slot); 6209 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6210 CLEAR_BIT(failed_tags, tmp_slot); 6211 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6212 6213 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6214 } 6215 6216 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 6217 while (timeout_tags) { 6218 if (err_retri_cmd_in_progress) { 6219 satapkt = ahci_portp->ahciport_err_retri_pkt; 6220 ASSERT(satapkt != NULL); 6221 ASSERT(timeout_tags == 0x1); 6222 6223 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6224 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6225 (void *)satapkt); 6226 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6227 break; 6228 } 6229 6230 tmp_slot = ddi_ffs(timeout_tags) - 1; 6231 if (tmp_slot == -1) { 6232 break; 6233 } 6234 6235 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6236 ASSERT(satapkt != NULL); 6237 6238 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6239 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6240 (void *)satapkt); 6241 6242 if (ncq_cmd_in_progress) 6243 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6244 tmp_slot); 6245 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6246 CLEAR_BIT(timeout_tags, tmp_slot); 6247 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6248 6249 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6250 } 6251 6252 /* Send up aborted packets with SATA_PKT_ABORTED */ 6253 while (aborted_tags) { 6254 if (err_retri_cmd_in_progress) { 6255 satapkt = ahci_portp->ahciport_err_retri_pkt; 6256 ASSERT(satapkt != NULL); 6257 ASSERT(aborted_tags == 0x1); 6258 6259 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6260 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6261 (void *)satapkt); 6262 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6263 break; 6264 } 6265 6266 tmp_slot = ddi_ffs(aborted_tags) - 1; 6267 if (tmp_slot == -1) { 6268 break; 6269 } 6270 6271 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6272 ASSERT(satapkt != NULL); 6273 6274 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6275 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6276 (void *)satapkt); 6277 6278 if (ncq_cmd_in_progress) 6279 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6280 tmp_slot); 6281 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6282 CLEAR_BIT(aborted_tags, tmp_slot); 6283 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6284 6285 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6286 } 6287 6288 /* Send up reset packets with SATA_PKT_RESET. */ 6289 while (reset_tags) { 6290 tmp_slot = ddi_ffs(reset_tags) - 1; 6291 if (tmp_slot == -1) { 6292 break; 6293 } 6294 6295 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6296 ASSERT(satapkt != NULL); 6297 6298 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6299 "sending up pkt 0x%p with SATA_PKT_RESET", 6300 (void *)satapkt); 6301 6302 if (ncq_cmd_in_progress) 6303 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6304 tmp_slot); 6305 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6306 CLEAR_BIT(reset_tags, tmp_slot); 6307 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6308 6309 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6310 } 6311 6312 /* Send up unfinished packets with SATA_PKT_RESET */ 6313 while (unfinished_tags) { 6314 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6315 if (tmp_slot == -1) { 6316 break; 6317 } 6318 6319 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6320 ASSERT(satapkt != NULL); 6321 6322 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6323 "sending up pkt 0x%p with SATA_PKT_RESET", 6324 (void *)satapkt); 6325 6326 if (ncq_cmd_in_progress) 6327 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6328 tmp_slot); 6329 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6330 CLEAR_BIT(unfinished_tags, tmp_slot); 6331 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6332 6333 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6334 } 6335 6336 ahci_portp->ahciport_mop_in_progress--; 6337 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6338 6339 if (ahci_portp->ahciport_mop_in_progress == 0) 6340 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6341 } 6342 6343 /* 6344 * This routine is going to first request a READ LOG EXT sata pkt from sata 6345 * module, and then deliver it to the HBA to get the ncq failure context. 6346 * The return value is the exactly failed tags. 6347 */ 6348 static uint32_t 6349 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6350 uint8_t port) 6351 { 6352 sata_device_t sdevice; 6353 sata_pkt_t *rdlog_spkt, *spkt; 6354 ddi_dma_handle_t buf_dma_handle; 6355 int loop_count; 6356 int rval; 6357 int failed_slot; 6358 uint32_t failed_tags = 0; 6359 struct sata_ncq_error_recovery_page *ncq_err_page; 6360 6361 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6362 "ahci_get_rdlogext_data enter: port %d", port); 6363 6364 /* Prepare the sdevice data */ 6365 bzero((void *)&sdevice, sizeof (sata_device_t)); 6366 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6367 6368 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6369 sdevice.satadev_addr.pmport = 0; 6370 6371 /* 6372 * Call the sata hba interface to get a rdlog spkt 6373 */ 6374 loop_count = 0; 6375 loop: 6376 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6377 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6378 if (rdlog_spkt == NULL) { 6379 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6380 /* Sleep for a while */ 6381 delay(AHCI_10MS_TICKS); 6382 goto loop; 6383 } 6384 /* Timed out after 1s */ 6385 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6386 "failed to get rdlog spkt for port %d", port); 6387 return (failed_tags); 6388 } 6389 6390 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6391 6392 /* 6393 * This flag is used to handle the specific error recovery when the 6394 * READ LOG EXT command gets a failure (fatal error or time-out). 6395 */ 6396 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6397 6398 /* 6399 * This start is not supposed to fail because after port is restarted, 6400 * the whole command list is empty. 6401 */ 6402 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6403 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6404 ahci_portp->ahciport_err_retri_pkt = NULL; 6405 6406 /* Remove the flag after READ LOG EXT command is completed */ 6407 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6408 6409 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6410 /* Update the request log data */ 6411 buf_dma_handle = *(ddi_dma_handle_t *) 6412 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6413 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6414 DDI_DMA_SYNC_FORKERNEL); 6415 if (rval == DDI_SUCCESS) { 6416 ncq_err_page = 6417 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6418 satapkt_cmd.satacmd_bp->b_un.b_addr; 6419 6420 /* Get the failed tag */ 6421 failed_slot = ncq_err_page->ncq_tag; 6422 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6423 "ahci_get_rdlogext_data: port %d " 6424 "failed slot %d", port, failed_slot); 6425 if (failed_slot & NQ) { 6426 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6427 "the failed slot is not a valid tag"); 6428 goto out; 6429 } 6430 6431 failed_slot &= NCQ_TAG_MASK; 6432 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6433 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6434 "ahci_get_rdlogext_data: failed spkt 0x%p", 6435 (void *)spkt); 6436 if (spkt == NULL) { 6437 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6438 "the failed slot spkt is NULL") 6439 goto out; 6440 } 6441 6442 failed_tags = 0x1 << failed_slot; 6443 6444 /* Fill out the error context */ 6445 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6446 ncq_err_page); 6447 ahci_update_sata_registers(ahci_ctlp, port, 6448 &spkt->satapkt_device); 6449 } 6450 } else { 6451 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6452 "ahci_get_rdlogext_data: port %d READ LOG EXT command " 6453 "did not successfully complete", port); 6454 } 6455 out: 6456 sata_free_error_retrieval_pkt(rdlog_spkt); 6457 6458 return (failed_tags); 6459 } 6460 6461 /* 6462 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6463 * module, and then deliver it to the HBA to get the sense data and copy 6464 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6465 * SENSE sata pkt later. 6466 */ 6467 static void 6468 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6469 uint8_t port, sata_pkt_t *spkt) 6470 { 6471 sata_device_t sdevice; 6472 sata_pkt_t *rs_spkt; 6473 sata_cmd_t *sata_cmd; 6474 ddi_dma_handle_t buf_dma_handle; 6475 int loop_count; 6476 #if AHCI_DEBUG 6477 struct scsi_extended_sense *rqsense; 6478 #endif 6479 6480 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6481 "ahci_get_rqsense_data enter: port %d", port); 6482 6483 /* Prepare the sdevice data */ 6484 bzero((void *)&sdevice, sizeof (sata_device_t)); 6485 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6486 6487 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6488 sdevice.satadev_addr.pmport = 0; 6489 6490 sata_cmd = &spkt->satapkt_cmd; 6491 6492 /* 6493 * Call the sata hba interface to get a rs spkt 6494 */ 6495 loop_count = 0; 6496 loop: 6497 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6498 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6499 if (rs_spkt == NULL) { 6500 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6501 /* Sleep for a while */ 6502 delay(AHCI_10MS_TICKS); 6503 goto loop; 6504 6505 } 6506 /* Timed out after 1s */ 6507 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6508 "failed to get rs spkt for port %d", port); 6509 return; 6510 } 6511 6512 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6513 6514 /* 6515 * This flag is used to handle the specific error recovery when the 6516 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6517 */ 6518 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6519 6520 /* 6521 * This start is not supposed to fail because after port is restarted, 6522 * the whole command list is empty. 6523 */ 6524 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6525 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6526 ahci_portp->ahciport_err_retri_pkt = NULL; 6527 6528 /* Remove the flag after REQUEST SENSE command is completed */ 6529 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6530 6531 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6532 /* Update the request sense data */ 6533 buf_dma_handle = *(ddi_dma_handle_t *) 6534 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6535 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6536 DDI_DMA_SYNC_FORKERNEL); 6537 /* Copy the request sense data */ 6538 bcopy(rs_spkt-> 6539 satapkt_cmd.satacmd_bp->b_un.b_addr, 6540 &sata_cmd->satacmd_rqsense, 6541 SATA_ATAPI_MIN_RQSENSE_LEN); 6542 #if AHCI_DEBUG 6543 rqsense = (struct scsi_extended_sense *) 6544 sata_cmd->satacmd_rqsense; 6545 6546 /* Dump the sense data */ 6547 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6548 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6549 "Sense data for satapkt %p ATAPI cmd 0x%x", 6550 spkt, sata_cmd->satacmd_acdb[0]); 6551 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6552 " es_code 0x%x es_class 0x%x " 6553 "es_key 0x%x es_add_code 0x%x " 6554 "es_qual_code 0x%x", 6555 rqsense->es_code, rqsense->es_class, 6556 rqsense->es_key, rqsense->es_add_code, 6557 rqsense->es_qual_code); 6558 #endif 6559 } else { 6560 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6561 "ahci_get_rqsense_data: port %d REQUEST SENSE command " 6562 "did not successfully complete", port); 6563 } 6564 6565 sata_free_error_retrieval_pkt(rs_spkt); 6566 } 6567 6568 /* 6569 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6570 * the port must be restarted. When the HBA detects thus error, it may try 6571 * to abort a transfer. And if the transfer was aborted, the device is 6572 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6573 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6574 * that the device is in a stable status and transfers may be restarted without 6575 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6576 * then the software will send the COMRESET to do the port reset. 6577 * 6578 * Software should perform the appropriate error recovery actions based on 6579 * whether non-queued commands were being issued or natived command queuing 6580 * commands were being issued. 6581 * 6582 * And software will complete the command that had the error with error mark 6583 * to higher level software. 6584 * 6585 * Fatal errors include the following: 6586 * PxIS.IFS - Interface Fatal Error Status 6587 * PxIS.HBDS - Host Bus Data Error Status 6588 * PxIS.HBFS - Host Bus Fatal Error Status 6589 * PxIS.TFES - Task File Error Status 6590 * 6591 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6592 */ 6593 static void 6594 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6595 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6596 { 6597 uint32_t port_cmd_status; 6598 uint32_t slot_status = 0; 6599 uint32_t failed_tags = 0; 6600 int failed_slot; 6601 int reset_flag = 0; 6602 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6603 sata_cmd_t *sata_cmd = NULL; 6604 sata_pkt_t *spkt = NULL; 6605 6606 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6607 "ahci_fatal_error_recovery_handler enter: port %d", port); 6608 6609 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6610 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6611 6612 /* Read PxCI to see which commands are still outstanding */ 6613 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6614 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6615 6616 /* 6617 * Read PxCMD.CCS to determine the slot that the HBA 6618 * was processing when the error occurred. 6619 */ 6620 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6621 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6622 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6623 AHCI_CMD_STATUS_CCS_SHIFT; 6624 6625 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6626 spkt = ahci_portp->ahciport_err_retri_pkt; 6627 ASSERT(spkt != NULL); 6628 } else { 6629 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6630 if (spkt == NULL) { 6631 /* May happen when interface errors occur? */ 6632 goto next; 6633 } 6634 } 6635 6636 sata_cmd = &spkt->satapkt_cmd; 6637 6638 /* Fill out the status and error registers for PxIS.TFES */ 6639 if (intr_status & AHCI_INTR_STATUS_TFES) { 6640 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6641 ahcirf_d2h_register_fis); 6642 6643 /* Copy the error context back to the sata_cmd */ 6644 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6645 } 6646 6647 /* The failed command must be one of the outstanding commands */ 6648 failed_tags = 0x1 << failed_slot; 6649 ASSERT(failed_tags & slot_status); 6650 6651 /* Update the sata registers, especially PxSERR register */ 6652 ahci_update_sata_registers(ahci_ctlp, port, 6653 &spkt->satapkt_device); 6654 6655 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6656 /* Read PxSACT to see which commands are still outstanding */ 6657 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6658 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6659 } 6660 next: 6661 6662 #if AHCI_DEBUG 6663 /* 6664 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6665 * set, it means a fatal error happened after REQUEST SENSE command 6666 * or READ LOG EXT command is delivered to the HBA during the error 6667 * recovery process. At this time, the only outstanding command is 6668 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6669 */ 6670 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6671 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6672 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6673 "command or READ LOG EXT command for error data retrieval " 6674 "failed", port); 6675 ASSERT(slot_status == 0x1); 6676 ASSERT(failed_slot == 0x1); 6677 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6678 SCMD_REQUEST_SENSE || 6679 spkt->satapkt_cmd.satacmd_cmd_reg == 6680 SATAC_READ_LOG_EXT); 6681 } 6682 #endif 6683 6684 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6685 ahci_portp->ahciport_mop_in_progress++; 6686 6687 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6688 port, NULL, &reset_flag); 6689 6690 /* 6691 * Won't retrieve error information: 6692 * 1. Port reset was involved to recover 6693 * 2. Device is gone 6694 * 3. IDENTIFY DEVICE command sent to ATAPI device 6695 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6696 */ 6697 if (reset_flag || 6698 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6699 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6700 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6701 goto out; 6702 6703 /* 6704 * Deliver READ LOG EXT to gather information about the error when 6705 * a COMRESET has not been performed as part of the error recovery 6706 * during NCQ command processing. 6707 */ 6708 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6709 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6710 ahci_portp, port); 6711 goto out; 6712 } 6713 6714 /* 6715 * Deliver REQUEST SENSE for ATAPI command to gather information about 6716 * the error when a COMRESET has not been performed as part of the 6717 * error recovery. 6718 */ 6719 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPICD) 6720 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6721 out: 6722 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6723 "ahci_fatal_error_recovery_handler: port %d interface error " 6724 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6725 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6726 port, slot_status, ahci_portp->ahciport_pending_tags, 6727 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6728 6729 ahci_mop_commands(ahci_ctlp, 6730 ahci_portp, 6731 port, 6732 slot_status, 6733 failed_tags, /* failed tags */ 6734 0, /* timeout tags */ 6735 0, /* aborted tags */ 6736 0); /* reset tags */ 6737 } 6738 6739 /* 6740 * Handle events - fatal error recovery 6741 */ 6742 static void 6743 ahci_events_handler(void *args) 6744 { 6745 ahci_event_arg_t *ahci_event_arg; 6746 ahci_ctl_t *ahci_ctlp; 6747 ahci_port_t *ahci_portp; 6748 uint32_t event; 6749 uint8_t port; 6750 6751 ahci_event_arg = (ahci_event_arg_t *)args; 6752 6753 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6754 ahci_portp = ahci_event_arg->ahciea_portp; 6755 event = ahci_event_arg->ahciea_event; 6756 port = ahci_portp->ahciport_port_num; 6757 6758 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6759 "ahci_events_handler enter: port %d intr_status = 0x%x", 6760 port, event); 6761 6762 mutex_enter(&ahci_portp->ahciport_mutex); 6763 6764 /* 6765 * ahci_intr_phyrdy_change() may have rendered it to 6766 * SATA_DTYPE_NONE. 6767 */ 6768 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6769 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6770 "ahci_events_handler: port %d no device attached, " 6771 "and just return without doing anything", port); 6772 goto out; 6773 } 6774 6775 if (event & (AHCI_INTR_STATUS_IFS | 6776 AHCI_INTR_STATUS_HBDS | 6777 AHCI_INTR_STATUS_HBFS | 6778 AHCI_INTR_STATUS_TFES)) 6779 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6780 port, event); 6781 6782 out: 6783 mutex_exit(&ahci_portp->ahciport_mutex); 6784 } 6785 6786 /* 6787 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6788 * detect there are some commands which are timed out. 6789 */ 6790 static void 6791 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6792 uint8_t port, uint32_t tmp_timeout_tags) 6793 { 6794 uint32_t slot_status = 0; 6795 uint32_t finished_tags = 0; 6796 uint32_t timeout_tags = 0; 6797 6798 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6799 "ahci_timeout_pkts enter: port %d", port); 6800 6801 mutex_enter(&ahci_portp->ahciport_mutex); 6802 6803 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6804 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6805 /* Read PxCI to see which commands are still outstanding */ 6806 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6807 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6808 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6809 /* Read PxSACT to see which commands are still outstanding */ 6810 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6811 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6812 } 6813 6814 #if AHCI_DEBUG 6815 /* 6816 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6817 * set, it means a fatal error happened after REQUEST SENSE command 6818 * or READ LOG EXT command is delivered to the HBA during the error 6819 * recovery process. At this time, the only outstanding command is 6820 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6821 */ 6822 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6823 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 6824 "ahci_timeout_pkts called while REQUEST SENSE " 6825 "command or READ LOG EXT command for error recovery " 6826 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 6827 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 6828 tmp_timeout_tags, slot_status, 6829 ahci_portp->ahciport_pending_tags, 6830 ahci_portp->ahciport_pending_ncq_tags); 6831 ASSERT(slot_status == 0x1); 6832 } 6833 #endif 6834 6835 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6836 ahci_portp->ahciport_mop_in_progress++; 6837 6838 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6839 port, NULL, NULL); 6840 6841 /* 6842 * Re-identify timeout tags because some previously checked commands 6843 * could already complete. 6844 */ 6845 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6846 finished_tags = ahci_portp->ahciport_pending_tags & 6847 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6848 timeout_tags = tmp_timeout_tags & ~finished_tags; 6849 6850 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 6851 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6852 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 6853 "pending_tags = 0x%x ", 6854 port, finished_tags, timeout_tags, 6855 slot_status, ahci_portp->ahciport_pending_tags); 6856 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6857 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6858 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6859 timeout_tags = tmp_timeout_tags & ~finished_tags; 6860 6861 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 6862 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6863 "timeout_tags = 0x%x, port_sactive = 0x%x, " 6864 "pending_ncq_tags = 0x%x ", 6865 port, finished_tags, timeout_tags, 6866 slot_status, ahci_portp->ahciport_pending_ncq_tags); 6867 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6868 timeout_tags = tmp_timeout_tags; 6869 } 6870 6871 ahci_mop_commands(ahci_ctlp, 6872 ahci_portp, 6873 port, 6874 slot_status, 6875 0, /* failed tags */ 6876 timeout_tags, /* timeout tags */ 6877 0, /* aborted tags */ 6878 0); /* reset tags */ 6879 6880 mutex_exit(&ahci_portp->ahciport_mutex); 6881 } 6882 6883 /* 6884 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 6885 * for long time. 6886 */ 6887 static void 6888 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 6889 { 6890 ahci_port_t *ahci_portp; 6891 sata_pkt_t *spkt; 6892 uint32_t pending_tags; 6893 uint32_t timeout_tags; 6894 uint32_t port_cmd_status; 6895 uint32_t port_sactive; 6896 uint8_t port; 6897 int tmp_slot; 6898 int current_slot; 6899 uint32_t current_tags; 6900 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 6901 /* max number of cycles this packet should survive */ 6902 int max_life_cycles; 6903 6904 /* how many cycles this packet survived so far */ 6905 int watched_cycles; 6906 6907 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6908 6909 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6910 "ahci_watchdog_handler entered"); 6911 6912 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6913 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6914 continue; 6915 } 6916 6917 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6918 6919 mutex_enter(&ahci_portp->ahciport_mutex); 6920 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6921 mutex_exit(&ahci_portp->ahciport_mutex); 6922 continue; 6923 } 6924 6925 /* Skip the check for those ports in error recovery */ 6926 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 6927 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 6928 mutex_exit(&ahci_portp->ahciport_mutex); 6929 continue; 6930 } 6931 6932 pending_tags = 0; 6933 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6934 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6935 6936 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6937 current_slot = 0; 6938 pending_tags = 0x1; 6939 } else if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6940 current_slot = 6941 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6942 AHCI_CMD_STATUS_CCS_SHIFT; 6943 pending_tags = ahci_portp->ahciport_pending_tags; 6944 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6945 port_sactive = ddi_get32( 6946 ahci_ctlp->ahcictl_ahci_acc_handle, 6947 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6948 current_tags = port_sactive & 6949 ~port_cmd_status & 6950 AHCI_NCQ_SLOT_MASK(ahci_portp); 6951 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 6952 } 6953 6954 timeout_tags = 0; 6955 while (pending_tags) { 6956 tmp_slot = ddi_ffs(pending_tags) - 1; 6957 if (tmp_slot == -1) { 6958 break; 6959 } 6960 6961 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6962 spkt = ahci_portp->ahciport_err_retri_pkt; 6963 else 6964 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6965 6966 if ((spkt != NULL) && spkt->satapkt_time && 6967 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 6968 /* 6969 * We are overloading satapkt_hba_driver_private 6970 * with watched_cycle count. 6971 * 6972 * If a packet has survived for more than it's 6973 * max life cycles, it is a candidate for time 6974 * out. 6975 */ 6976 watched_cycles = (int)(intptr_t) 6977 spkt->satapkt_hba_driver_private; 6978 watched_cycles++; 6979 max_life_cycles = (spkt->satapkt_time + 6980 ahci_watchdog_timeout - 1) / 6981 ahci_watchdog_timeout; 6982 6983 spkt->satapkt_hba_driver_private = 6984 (void *)(intptr_t)watched_cycles; 6985 6986 if (watched_cycles <= max_life_cycles) 6987 goto next; 6988 6989 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6990 "the current slot is %d", current_slot); 6991 /* 6992 * We need to check whether the HBA has 6993 * begun to execute the command, if not, 6994 * then re-set the timer of the command. 6995 */ 6996 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 6997 (tmp_slot != current_slot) || 6998 NCQ_CMD_IN_PROGRESS(ahci_portp) && 6999 ((0x1 << tmp_slot) & current_tags)) { 7000 spkt->satapkt_hba_driver_private = 7001 (void *)(intptr_t)0; 7002 } else { 7003 timeout_tags |= (0x1 << tmp_slot); 7004 cmn_err(CE_WARN, "!ahci%d: watchdog " 7005 "port %d satapkt 0x%p timed out\n", 7006 instance, port, (void *)spkt); 7007 } 7008 } 7009 next: 7010 CLEAR_BIT(pending_tags, tmp_slot); 7011 } 7012 7013 if (timeout_tags) { 7014 mutex_exit(&ahci_portp->ahciport_mutex); 7015 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7016 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 7017 port, timeout_tags); 7018 mutex_enter(&ahci_ctlp->ahcictl_mutex); 7019 mutex_enter(&ahci_portp->ahciport_mutex); 7020 } 7021 7022 mutex_exit(&ahci_portp->ahciport_mutex); 7023 } 7024 7025 /* Re-install the watchdog timeout handler */ 7026 if (ahci_ctlp->ahcictl_timeout_id != 0) { 7027 ahci_ctlp->ahcictl_timeout_id = 7028 timeout((void (*)(void *))ahci_watchdog_handler, 7029 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 7030 } 7031 7032 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7033 } 7034 7035 /* 7036 * Fill the error context into sata_cmd for non-queued command error. 7037 */ 7038 static void 7039 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7040 { 7041 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 7042 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7043 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7044 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7045 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7046 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7047 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7048 7049 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 7050 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7051 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7052 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7053 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7054 } 7055 } 7056 7057 /* 7058 * Fill the ncq error page into sata_cmd for queued command error. 7059 */ 7060 static void 7061 ahci_copy_ncq_err_page(sata_cmd_t *scmd, 7062 struct sata_ncq_error_recovery_page *ncq_err_page) 7063 { 7064 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 7065 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 7066 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 7067 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 7068 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 7069 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 7070 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 7071 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 7072 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 7073 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 7074 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 7075 } 7076 7077 /* 7078 * Put the respective register value to sata_cmd_t for satacmd_flags. 7079 */ 7080 static void 7081 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7082 { 7083 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 7084 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7085 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 7086 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7087 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 7088 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7089 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 7090 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7091 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 7092 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7093 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 7094 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7095 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 7096 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7097 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 7098 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7099 if (scmd->satacmd_flags.sata_copy_out_device_reg) 7100 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7101 if (scmd->satacmd_flags.sata_copy_out_error_reg) 7102 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7103 } 7104 7105 static void 7106 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7107 uint32_t intr_status) 7108 { 7109 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7110 7111 if (intr_status & AHCI_INTR_STATUS_IFS) 7112 cmn_err(CE_WARN, "ahci%d: ahci port %d has interface fatal " 7113 "error", instance, port); 7114 7115 if (intr_status & AHCI_INTR_STATUS_HBDS) 7116 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus data error", 7117 instance, port); 7118 7119 if (intr_status & AHCI_INTR_STATUS_HBFS) 7120 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus fatal error", 7121 instance, port); 7122 7123 if (intr_status & AHCI_INTR_STATUS_TFES) 7124 cmn_err(CE_WARN, "ahci%d: ahci port %d has task file error", 7125 instance, port); 7126 7127 cmn_err(CE_WARN, "ahci%d: ahci port %d is trying to do error " 7128 "recovery", instance, port); 7129 } 7130 7131 /* 7132 * Dump the serror message to the log. 7133 */ 7134 static void 7135 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7136 uint32_t port_serror, int debug_only) 7137 { 7138 static char err_buf[512]; 7139 static char err_msg_header[16]; 7140 char *err_msg = err_buf; 7141 7142 *err_buf = '\0'; 7143 *err_msg_header = '\0'; 7144 7145 if (port_serror & SERROR_DATA_ERR_FIXED) { 7146 err_msg = strcat(err_msg, 7147 "\tRecovered Data Integrity Error (I)\n"); 7148 } 7149 7150 if (port_serror & SERROR_COMM_ERR_FIXED) { 7151 err_msg = strcat(err_msg, 7152 "\tRecovered Communication Error (M)\n"); 7153 } 7154 7155 if (port_serror & SERROR_DATA_ERR) { 7156 err_msg = strcat(err_msg, 7157 "\tTransient Data Integrity Error (T)\n"); 7158 } 7159 7160 if (port_serror & SERROR_PERSISTENT_ERR) { 7161 err_msg = strcat(err_msg, 7162 "\tPersistent Communication or Data Integrity Error (C)\n"); 7163 } 7164 7165 if (port_serror & SERROR_PROTOCOL_ERR) { 7166 err_msg = strcat(err_msg, "\tProtocol Error (P)\n"); 7167 } 7168 7169 if (port_serror & SERROR_INT_ERR) { 7170 err_msg = strcat(err_msg, "\tInternal Error (E)\n"); 7171 } 7172 7173 if (port_serror & SERROR_PHY_RDY_CHG) { 7174 err_msg = strcat(err_msg, "\tPhyRdy Change (N)\n"); 7175 } 7176 7177 if (port_serror & SERROR_PHY_INT_ERR) { 7178 err_msg = strcat(err_msg, "\tPhy Internal Error (I)\n"); 7179 } 7180 7181 if (port_serror & SERROR_COMM_WAKE) { 7182 err_msg = strcat(err_msg, "\tComm Wake (W)\n"); 7183 } 7184 7185 if (port_serror & SERROR_10B_TO_8B_ERR) { 7186 err_msg = strcat(err_msg, "\t10B to 8B Decode Error (B)\n"); 7187 } 7188 7189 if (port_serror & SERROR_DISPARITY_ERR) { 7190 err_msg = strcat(err_msg, "\tDisparity Error (D)\n"); 7191 } 7192 7193 if (port_serror & SERROR_CRC_ERR) { 7194 err_msg = strcat(err_msg, "\tCRC Error (C)\n"); 7195 } 7196 7197 if (port_serror & SERROR_HANDSHAKE_ERR) { 7198 err_msg = strcat(err_msg, "\tHandshake Error (H)\n"); 7199 } 7200 7201 if (port_serror & SERROR_LINK_SEQ_ERR) { 7202 err_msg = strcat(err_msg, "\tLink Sequence Error (S)\n"); 7203 } 7204 7205 if (port_serror & SERROR_TRANS_ERR) { 7206 err_msg = strcat(err_msg, 7207 "\tTransport state transition error (T)\n"); 7208 } 7209 7210 if (port_serror & SERROR_FIS_TYPE) { 7211 err_msg = strcat(err_msg, "\tUnknown FIS Type (F)\n"); 7212 } 7213 7214 if (port_serror & SERROR_EXCHANGED_ERR) { 7215 err_msg = strcat(err_msg, "\tExchanged (X)\n"); 7216 } 7217 7218 if (err_msg == NULL) 7219 return; 7220 7221 if (debug_only) { 7222 (void) sprintf(err_msg_header, "port %d", port); 7223 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg_header); 7224 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg); 7225 } else if (ahci_ctlp) { 7226 cmn_err(CE_WARN, "ahci%d: %s %s", 7227 ddi_get_instance(ahci_ctlp->ahcictl_dip), 7228 err_msg_header, err_msg); 7229 } else { 7230 cmn_err(CE_WARN, "ahci: %s %s", err_msg_header, err_msg); 7231 } 7232 } 7233 7234 /* 7235 * This routine is to calculate the total number of ports implemented 7236 * by the HBA. 7237 */ 7238 static int 7239 ahci_get_num_implemented_ports(uint32_t ports_implemented) 7240 { 7241 uint8_t i; 7242 int num = 0; 7243 7244 for (i = 0; i < AHCI_MAX_PORTS; i++) { 7245 if (((uint32_t)0x1 << i) & ports_implemented) 7246 num++; 7247 } 7248 7249 return (num); 7250 } 7251 7252 static void 7253 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7254 { 7255 static char name[16]; 7256 va_list ap; 7257 7258 mutex_enter(&ahci_log_mutex); 7259 7260 va_start(ap, fmt); 7261 if (ahci_ctlp) { 7262 (void) sprintf(name, "ahci%d: ", 7263 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7264 } else { 7265 (void) sprintf(name, "ahci: "); 7266 } 7267 7268 (void) vsprintf(ahci_log_buf, fmt, ap); 7269 va_end(ap); 7270 7271 cmn_err(level, "%s%s", name, ahci_log_buf); 7272 7273 mutex_exit(&ahci_log_mutex); 7274 } 7275