1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 31 */ 32 33 #include <sys/scsi/scsi.h> 34 #include <sys/pci.h> 35 #include <sys/sata/sata_hba.h> 36 #include <sys/sata/adapters/ahci/ahcireg.h> 37 #include <sys/sata/adapters/ahci/ahcivar.h> 38 39 /* 40 * Function prototypes for driver entry points 41 */ 42 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 43 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 44 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 45 46 /* 47 * Function prototypes for SATA Framework interfaces 48 */ 49 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 50 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 51 52 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 53 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 54 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 55 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 56 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 57 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 58 #if defined(__lock_lint) 59 static int ahci_selftest(dev_info_t *, sata_device_t *); 60 #endif 61 62 /* 63 * Local function prototypes 64 */ 65 static int ahci_alloc_ports_state(ahci_ctl_t *); 66 static void ahci_dealloc_ports_state(ahci_ctl_t *); 67 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 68 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 69 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 70 static void ahci_dealloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *); 71 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 72 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 73 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 74 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 75 76 static int ahci_initialize_controller(ahci_ctl_t *); 77 static void ahci_uninitialize_controller(ahci_ctl_t *); 78 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 79 80 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 81 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 82 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 83 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 84 uint8_t, sata_pkt_t *); 85 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 86 uint8_t, sata_pkt_t *); 87 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 88 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 89 static void ahci_copy_ncq_err_page(sata_cmd_t *, 90 struct sata_ncq_error_recovery_page *); 91 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 92 93 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 94 static int ahci_hba_reset(ahci_ctl_t *); 95 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 96 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 97 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 98 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 99 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 100 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 101 uint8_t); 102 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 103 uint8_t, int, int *); 104 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint8_t, 105 uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); 106 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 107 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 108 uint8_t, sata_pkt_t *); 109 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 110 uint8_t, uint32_t); 111 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 112 uint8_t, uint32_t); 113 static void ahci_events_handler(void *); 114 static void ahci_watchdog_handler(ahci_ctl_t *); 115 116 static uint_t ahci_intr(caddr_t, caddr_t); 117 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 118 static int ahci_add_legacy_intrs(ahci_ctl_t *); 119 static int ahci_add_msi_intrs(ahci_ctl_t *); 120 static void ahci_rem_intrs(ahci_ctl_t *); 121 static void ahci_enable_all_intrs(ahci_ctl_t *); 122 static void ahci_disable_all_intrs(ahci_ctl_t *); 123 static void ahci_enable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 124 static void ahci_disable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 125 126 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t, 127 uint32_t); 128 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 129 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 130 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 131 ahci_port_t *, uint8_t); 132 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 133 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 134 uint8_t, uint32_t); 135 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 136 uint8_t, uint32_t); 137 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 138 139 static int ahci_get_num_implemented_ports(uint32_t); 140 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 141 uint32_t); 142 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t); 143 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 144 145 146 /* 147 * DMA attributes for the data buffer 148 * 149 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 150 * does not support 64-bit addressing 151 */ 152 static ddi_dma_attr_t buffer_dma_attr = { 153 DMA_ATTR_V0, /* dma_attr_version */ 154 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 155 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 156 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 157 0x2ull, /* dma_attr_align: word aligned */ 158 1, /* dma_attr_burstsizes */ 159 1, /* dma_attr_minxfer */ 160 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 161 0xffffffffull, /* dma_attr_seg */ 162 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 163 512, /* dma_attr_granular */ 164 0, /* dma_attr_flags */ 165 }; 166 167 /* 168 * DMA attributes for the rcvd FIS 169 * 170 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 171 * does not support 64-bit addressing 172 */ 173 static ddi_dma_attr_t rcvd_fis_dma_attr = { 174 DMA_ATTR_V0, /* dma_attr_version */ 175 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 176 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 177 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 178 0x100ull, /* dma_attr_align: 256-byte aligned */ 179 1, /* dma_attr_burstsizes */ 180 1, /* dma_attr_minxfer */ 181 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 182 0xffffffffull, /* dma_attr_seg */ 183 1, /* dma_attr_sgllen */ 184 1, /* dma_attr_granular */ 185 0, /* dma_attr_flags */ 186 }; 187 188 /* 189 * DMA attributes for the command list 190 * 191 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 192 * does not support 64-bit addressing 193 */ 194 static ddi_dma_attr_t cmd_list_dma_attr = { 195 DMA_ATTR_V0, /* dma_attr_version */ 196 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 197 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 198 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 199 0x400ull, /* dma_attr_align: 1K-byte aligned */ 200 1, /* dma_attr_burstsizes */ 201 1, /* dma_attr_minxfer */ 202 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 203 0xffffffffull, /* dma_attr_seg */ 204 1, /* dma_attr_sgllen */ 205 1, /* dma_attr_granular */ 206 0, /* dma_attr_flags */ 207 }; 208 209 /* 210 * DMA attributes for cmd tables 211 * 212 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 213 * does not support 64-bit addressing 214 */ 215 static ddi_dma_attr_t cmd_table_dma_attr = { 216 DMA_ATTR_V0, /* dma_attr_version */ 217 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 218 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 219 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 220 0x80ull, /* dma_attr_align: 128-byte aligned */ 221 1, /* dma_attr_burstsizes */ 222 1, /* dma_attr_minxfer */ 223 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 224 0xffffffffull, /* dma_attr_seg */ 225 1, /* dma_attr_sgllen */ 226 1, /* dma_attr_granular */ 227 0, /* dma_attr_flags */ 228 }; 229 230 231 /* Device access attributes */ 232 static ddi_device_acc_attr_t accattr = { 233 DDI_DEVICE_ATTR_V0, 234 DDI_STRUCTURE_LE_ACC, 235 DDI_STRICTORDER_ACC 236 }; 237 238 239 static struct dev_ops ahcictl_dev_ops = { 240 DEVO_REV, /* devo_rev */ 241 0, /* refcnt */ 242 ahci_getinfo, /* info */ 243 nulldev, /* identify */ 244 nulldev, /* probe */ 245 ahci_attach, /* attach */ 246 ahci_detach, /* detach */ 247 nodev, /* no reset */ 248 (struct cb_ops *)0, /* driver operations */ 249 NULL, /* bus operations */ 250 NULL /* power */ 251 }; 252 253 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 254 SATA_TRAN_HOTPLUG_OPS_REV_1, 255 ahci_tran_hotplug_port_activate, 256 ahci_tran_hotplug_port_deactivate 257 }; 258 259 extern struct mod_ops mod_driverops; 260 261 static struct modldrv modldrv = { 262 &mod_driverops, /* driverops */ 263 "ahci driver %I%", 264 &ahcictl_dev_ops, /* driver ops */ 265 }; 266 267 static struct modlinkage modlinkage = { 268 MODREV_1, 269 &modldrv, 270 NULL 271 }; 272 273 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 274 static int ahci_watchdog_tick; 275 276 /* The following is needed for ahci_log() */ 277 static kmutex_t ahci_log_mutex; 278 static char ahci_log_buf[512]; 279 280 static size_t ahci_cmd_table_size; 281 282 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 283 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 284 285 /* 286 * AHCI MSI tunable: 287 * 288 * MSI will be enabled in phase 2. 289 */ 290 boolean_t ahci_msi_enabled = B_FALSE; 291 292 #if AHCI_DEBUG 293 uint32_t ahci_debug_flags = 0; 294 #endif 295 296 /* Opaque state pointer initialized by ddi_soft_state_init() */ 297 static void *ahci_statep = NULL; 298 299 /* 300 * ahci module initialization. 301 */ 302 int 303 _init(void) 304 { 305 int ret; 306 307 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 308 if (ret != 0) { 309 goto err_out; 310 } 311 312 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 313 314 if ((ret = sata_hba_init(&modlinkage)) != 0) { 315 mutex_destroy(&ahci_log_mutex); 316 ddi_soft_state_fini(&ahci_statep); 317 goto err_out; 318 } 319 320 ret = mod_install(&modlinkage); 321 if (ret != 0) { 322 sata_hba_fini(&modlinkage); 323 mutex_destroy(&ahci_log_mutex); 324 ddi_soft_state_fini(&ahci_statep); 325 goto err_out; 326 } 327 328 /* watchdog tick */ 329 ahci_watchdog_tick = drv_usectohz( 330 (clock_t)ahci_watchdog_timeout * 1000000); 331 return (ret); 332 333 err_out: 334 cmn_err(CE_WARN, "!Module init failed"); 335 return (ret); 336 } 337 338 /* 339 * ahci module uninitialize. 340 */ 341 int 342 _fini(void) 343 { 344 int ret; 345 346 ret = mod_remove(&modlinkage); 347 if (ret != 0) { 348 return (ret); 349 } 350 351 /* Remove the resources allocated in _init(). */ 352 sata_hba_fini(&modlinkage); 353 mutex_destroy(&ahci_log_mutex); 354 ddi_soft_state_fini(&ahci_statep); 355 356 return (ret); 357 } 358 359 /* 360 * _info entry point 361 */ 362 int 363 _info(struct modinfo *modinfop) 364 { 365 return (mod_info(&modlinkage, modinfop)); 366 } 367 368 /* 369 * The attach entry point for dev_ops. 370 */ 371 static int 372 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 373 { 374 ahci_ctl_t *ahci_ctlp; 375 int instance = ddi_get_instance(dip); 376 int status; 377 int attach_state; 378 uint32_t cap_status, ahci_version; 379 int intr_types; 380 ushort_t venid; 381 uint8_t revision; 382 int i; 383 pci_regspec_t *regs; 384 int regs_length; 385 int rnumber; 386 #if AHCI_DEBUG 387 int speed; 388 #endif 389 390 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 391 392 switch (cmd) { 393 case DDI_ATTACH: 394 break; 395 396 case DDI_RESUME: 397 /* It will be implemented in Phase 2 */ 398 return (DDI_FAILURE); 399 400 default: 401 return (DDI_FAILURE); 402 } 403 404 attach_state = AHCI_ATTACH_STATE_NONE; 405 406 /* Allocate soft state */ 407 status = ddi_soft_state_zalloc(ahci_statep, instance); 408 if (status != DDI_SUCCESS) { 409 cmn_err(CE_WARN, "!Cannot allocate soft state"); 410 goto err_out; 411 } 412 413 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 414 ahci_ctlp->ahcictl_dip = dip; 415 416 /* Initialize the cport/port mapping */ 417 for (i = 0; i < AHCI_MAX_PORTS; i++) { 418 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 419 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 420 } 421 422 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 423 424 /* 425 * Now map the AHCI base address; which includes global 426 * registers and port control registers 427 * 428 * According to the spec, the AHCI Base Address is BAR5, 429 * but we found JMicron JMB363 PATA-SATA chipset doesn't 430 * follow this, so we need to check which rnumber is used 431 */ 432 433 /* 434 * search through DDI "reg" property for the AHCI register set 435 */ 436 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 437 DDI_PROP_DONTPASS, "reg", (int **)®s, 438 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 439 cmn_err(CE_WARN, "!Cannot lookup reg property"); 440 goto err_out; 441 } 442 443 /* AHCI Base Address is located at 0x24 offset */ 444 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 445 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 446 == AHCI_PCI_RNUM) 447 break; 448 } 449 450 ddi_prop_free(regs); 451 452 if (rnumber == regs_length) { 453 cmn_err(CE_WARN, "!Cannot find AHCI register set"); 454 goto err_out; 455 } 456 457 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 458 459 status = ddi_regs_map_setup(dip, 460 rnumber, 461 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 462 0, 463 0, 464 &accattr, 465 &ahci_ctlp->ahcictl_ahci_acc_handle); 466 if (status != DDI_SUCCESS) { 467 cmn_err(CE_WARN, "!Cannot map register space"); 468 goto err_out; 469 } 470 471 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 472 473 /* Get the AHCI version information */ 474 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 475 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 476 477 cmn_err(CE_NOTE, "!hba AHCI version = %x.%x", 478 (ahci_version & 0xffff0000) >> 16, 479 ((ahci_version & 0x0000ff00) >> 4 | 480 (ahci_version & 0x000000ff))); 481 482 /* We don't support controllers whose versions are lower than 1.0 */ 483 if (!(ahci_version & 0xffff0000)) { 484 cmn_err(CE_WARN, "Don't support AHCI HBA with lower than " 485 "version 1.0"); 486 goto err_out; 487 } 488 489 /* Get the HBA capabilities information */ 490 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 491 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 492 493 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 494 cap_status); 495 496 #if AHCI_DEBUG 497 /* Get the interface speed supported by the HBA */ 498 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 499 if (speed == 0x01) { 500 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 501 "hba interface speed support: Gen 1 (1.5Gbps)"); 502 } else if (speed == 0x10) { 503 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 504 "hba interface speed support: Gen 2 (3 Gbps)"); 505 } else if (speed == 0x11) { 506 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 507 "hba interface speed support: Gen 3 (6 Gbps)"); 508 } 509 #endif 510 511 /* Get the number of command slots supported by the HBA */ 512 ahci_ctlp->ahcictl_num_cmd_slots = 513 ((cap_status & AHCI_HBA_CAP_NCS) >> 514 AHCI_HBA_CAP_NCS_SHIFT) + 1; 515 516 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 517 ahci_ctlp->ahcictl_num_cmd_slots); 518 519 /* Get the bit map which indicates ports implemented by the HBA */ 520 ahci_ctlp->ahcictl_ports_implemented = 521 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 522 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 523 524 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 525 ahci_ctlp->ahcictl_ports_implemented); 526 527 /* 528 * According to the AHCI spec, CAP.NP should indicate the maximum 529 * number of ports supported by the HBA silicon, but we found 530 * this value of ICH8 chipset only indicates the number of ports 531 * implemented (exposed) by it. Therefore, the driver should calculate 532 * the potential maximum value by checking PI register, and use 533 * the maximum of this value and CAP.NP. 534 */ 535 ahci_ctlp->ahcictl_num_ports = max( 536 (cap_status & AHCI_HBA_CAP_NP) + 1, 537 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 538 539 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 540 ahci_ctlp->ahcictl_num_ports); 541 542 /* Get the number of implemented ports by the HBA */ 543 ahci_ctlp->ahcictl_num_implemented_ports = 544 ahci_get_num_implemented_ports( 545 ahci_ctlp->ahcictl_ports_implemented); 546 547 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 548 "hba number of implemented ports: %d", 549 ahci_ctlp->ahcictl_num_implemented_ports); 550 551 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 552 553 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 554 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 555 "hba does not support 64-bit addressing"); 556 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 557 0xffffffffull; 558 } 559 560 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 561 != DDI_SUCCESS) { 562 cmn_err(CE_WARN, "!Cannot set up pci configure space"); 563 goto err_out; 564 } 565 566 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 567 568 /* 569 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 570 * controllers with 0x00 revision id work on 4-byte aligned buffer, 571 * which is a bug and was fixed after 0x00 revision id controllers. 572 * 573 * Moreover, VT8251 cannot use multiple command slots in the command 574 * list for non-queued commands because the previous register content 575 * of PxCI can be re-written in the register write, so a flag will be 576 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 577 */ 578 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 579 PCI_CONF_VENID); 580 581 if (venid == VIA_VENID) { 582 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 583 PCI_CONF_REVID); 584 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 585 "revision id = 0x%x", revision); 586 if (revision == 0x00) { 587 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 588 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 589 "change ddi_attr_align to 0x4"); 590 } 591 592 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 593 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 594 "VT8251 cannot use multiple command lists for " 595 "non-queued commands"); 596 } 597 598 /* 599 * Disable the whole controller interrupts before adding 600 * interrupt handlers(s). 601 */ 602 ahci_disable_all_intrs(ahci_ctlp); 603 604 /* Get supported interrupt types */ 605 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 606 cmn_err(CE_WARN, "!ddi_intr_get_supported_types failed"); 607 goto err_out; 608 } 609 610 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 611 "ddi_intr_get_supported_types() returned: 0x%x", 612 intr_types); 613 614 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 615 /* 616 * Try MSI first, but fall back to FIXED if failed 617 */ 618 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 619 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 620 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 621 "Using MSI interrupt type"); 622 goto intr_done; 623 } 624 625 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 626 "MSI registration failed, " 627 "trying FIXED interrupts"); 628 } 629 630 if (intr_types & DDI_INTR_TYPE_FIXED) { 631 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 632 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 633 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, NULL, 634 "Using FIXED interrupt type"); 635 goto intr_done; 636 } 637 638 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 639 "FIXED interrupt registration failed"); 640 } 641 642 cmn_err(CE_WARN, "!Interrupt registration failed"); 643 644 goto err_out; 645 646 intr_done: 647 648 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 649 650 /* Initialize the controller mutex */ 651 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 652 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 653 654 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 655 656 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 657 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 658 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 659 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 660 } 661 662 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 663 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 664 sizeof (ahci_prdt_item_t)); 665 666 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 667 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 668 " ahci_cmd_table_size is 0x%x", 669 ahci_dma_prdt_number, ahci_cmd_table_size); 670 671 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 672 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 673 ahci_dma_prdt_number; 674 675 /* Allocate the ports structure */ 676 status = ahci_alloc_ports_state(ahci_ctlp); 677 if (status != AHCI_SUCCESS) { 678 cmn_err(CE_WARN, "!Cannot allocate ports structure"); 679 goto err_out; 680 } 681 682 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 683 684 /* 685 * A taskq is created for dealing with events 686 */ 687 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 688 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 689 cmn_err(CE_WARN, "!ddi_taskq_create failed for event handle"); 690 goto err_out; 691 } 692 693 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 694 695 /* 696 * Initialize the controller and ports. 697 */ 698 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 699 status = ahci_initialize_controller(ahci_ctlp); 700 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 701 if (status != AHCI_SUCCESS) { 702 cmn_err(CE_WARN, "!HBA initialization failed"); 703 goto err_out; 704 } 705 706 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 707 708 /* Start one thread to check packet timeouts */ 709 ahci_ctlp->ahcictl_timeout_id = timeout( 710 (void (*)(void *))ahci_watchdog_handler, 711 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 712 713 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 714 715 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 716 cmn_err(CE_WARN, "!sata hba tran registration failed"); 717 goto err_out; 718 } 719 720 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 721 722 return (DDI_SUCCESS); 723 724 err_out: 725 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 726 mutex_enter(&ahci_ctlp->ahcictl_mutex); 727 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 728 ahci_ctlp->ahcictl_timeout_id = 0; 729 mutex_exit(&ahci_ctlp->ahcictl_mutex); 730 } 731 732 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 733 mutex_enter(&ahci_ctlp->ahcictl_mutex); 734 ahci_uninitialize_controller(ahci_ctlp); 735 mutex_exit(&ahci_ctlp->ahcictl_mutex); 736 } 737 738 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 739 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 740 } 741 742 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 743 ahci_dealloc_ports_state(ahci_ctlp); 744 } 745 746 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 747 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 748 } 749 750 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 751 ahci_rem_intrs(ahci_ctlp); 752 } 753 754 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 755 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 756 } 757 758 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 759 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 760 } 761 762 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 763 ddi_soft_state_free(ahci_statep, instance); 764 } 765 766 return (DDI_FAILURE); 767 } 768 769 /* 770 * The detach entry point for dev_ops. 771 */ 772 static int 773 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 774 { 775 ahci_ctl_t *ahci_ctlp; 776 int instance; 777 int ret; 778 779 instance = ddi_get_instance(dip); 780 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 781 782 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 783 784 switch (cmd) { 785 case DDI_DETACH: 786 /* disable the interrupts for an uninterrupted detach */ 787 mutex_enter(&ahci_ctlp->ahcictl_mutex); 788 ahci_disable_all_intrs(ahci_ctlp); 789 mutex_exit(&ahci_ctlp->ahcictl_mutex); 790 791 /* unregister from the sata framework. */ 792 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 793 if (ret != AHCI_SUCCESS) { 794 mutex_enter(&ahci_ctlp->ahcictl_mutex); 795 ahci_enable_all_intrs(ahci_ctlp); 796 mutex_exit(&ahci_ctlp->ahcictl_mutex); 797 return (DDI_FAILURE); 798 } 799 800 mutex_enter(&ahci_ctlp->ahcictl_mutex); 801 802 /* stop the watchdog handler */ 803 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 804 ahci_ctlp->ahcictl_timeout_id = 0; 805 806 mutex_exit(&ahci_ctlp->ahcictl_mutex); 807 808 /* uninitialize the controller */ 809 ahci_ctlp->ahcictl_flags |= AHCI_DETACH; 810 ahci_uninitialize_controller(ahci_ctlp); 811 ahci_ctlp->ahcictl_flags &= ~AHCI_DETACH; 812 813 /* remove the interrupts */ 814 ahci_rem_intrs(ahci_ctlp); 815 816 /* destroy the taskq */ 817 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 818 819 /* deallocate the ports structures */ 820 ahci_dealloc_ports_state(ahci_ctlp); 821 822 /* destroy mutex */ 823 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 824 825 /* teardown the pci config */ 826 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 827 828 /* remove the reg maps. */ 829 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 830 831 /* free the soft state. */ 832 ddi_soft_state_free(ahci_statep, instance); 833 834 return (DDI_SUCCESS); 835 836 case DDI_SUSPEND: 837 /* It will be implemented in Phase 2 */ 838 return (DDI_FAILURE); 839 840 default: 841 return (DDI_FAILURE); 842 } 843 } 844 845 /* 846 * The info entry point for dev_ops. 847 * 848 */ 849 static int 850 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 851 void *arg, void **result) 852 { 853 #ifndef __lock_lint 854 _NOTE(ARGUNUSED(dip)) 855 #endif /* __lock_lint */ 856 857 ahci_ctl_t *ahci_ctlp; 858 int instance; 859 dev_t dev; 860 861 dev = (dev_t)arg; 862 instance = getminor(dev); 863 864 switch (infocmd) { 865 case DDI_INFO_DEVT2DEVINFO: 866 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 867 if (ahci_ctlp != NULL) { 868 *result = ahci_ctlp->ahcictl_dip; 869 return (DDI_SUCCESS); 870 } else { 871 *result = NULL; 872 return (DDI_FAILURE); 873 } 874 case DDI_INFO_DEVT2INSTANCE: 875 *(int *)result = instance; 876 break; 877 default: 878 break; 879 } 880 881 return (DDI_SUCCESS); 882 } 883 884 /* 885 * Registers the ahci with sata framework. 886 */ 887 static int 888 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 889 { 890 struct sata_hba_tran *sata_hba_tran; 891 892 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 893 "ahci_register_sata_hba_tran enter"); 894 895 mutex_enter(&ahci_ctlp->ahcictl_mutex); 896 897 /* Allocate memory for the sata_hba_tran */ 898 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 899 900 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 901 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 902 sata_hba_tran->sata_tran_hba_dma_attr = 903 &ahci_ctlp->ahcictl_buffer_dma_attr; 904 905 /* Report the number of implemented ports */ 906 sata_hba_tran->sata_tran_hba_num_cports = 907 ahci_ctlp->ahcictl_num_implemented_ports; 908 909 /* Support ATAPI device */ 910 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 911 912 /* Get the data transfer capability for PIO command by the HBA */ 913 if (cap_status & AHCI_HBA_CAP_PMD) { 914 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 915 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 916 "DRQ block data transfer for PIO command protocol"); 917 } else { 918 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA only supports single " 919 "DRQ block data transfer for PIO command protocol"); 920 } 921 922 /* 923 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 924 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 925 * QUEUED (EXT), and SERVICE commands). Queued operations are 926 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 927 * QUEUED commands when the HBA and device support native command 928 * queuing(NCQ). 929 * 930 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 931 * CAP register of the HBA indicates NCQ is supported. 932 * 933 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 934 * set because the previous register content of PxCI can be re-written 935 * in the register write. 936 */ 937 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 938 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 939 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 940 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 941 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 942 "Command Queuing"); 943 } 944 945 /* Report the number of command slots */ 946 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 947 948 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 949 sata_hba_tran->sata_tran_start = ahci_tran_start; 950 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 951 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 952 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 953 #ifdef __lock_lint 954 sata_hba_tran->sata_tran_selftest = ahci_selftest; 955 #endif 956 /* 957 * When SATA framework adds support for pwrmgt the 958 * pwrmgt_ops needs to be updated 959 */ 960 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 961 sata_hba_tran->sata_tran_ioctl = NULL; 962 963 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 964 965 mutex_exit(&ahci_ctlp->ahcictl_mutex); 966 967 /* Attach it to SATA framework */ 968 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 969 != DDI_SUCCESS) { 970 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 971 mutex_enter(&ahci_ctlp->ahcictl_mutex); 972 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 973 mutex_exit(&ahci_ctlp->ahcictl_mutex); 974 return (AHCI_FAILURE); 975 } 976 977 return (AHCI_SUCCESS); 978 } 979 980 /* 981 * Unregisters the ahci with sata framework. 982 */ 983 static int 984 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 985 { 986 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 987 "ahci_unregister_sata_hba_tran enter"); 988 989 /* Detach from the SATA framework. */ 990 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 991 DDI_SUCCESS) { 992 return (AHCI_FAILURE); 993 } 994 995 /* Deallocate sata_hba_tran. */ 996 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 997 sizeof (sata_hba_tran_t)); 998 999 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1000 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1001 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1002 1003 return (AHCI_SUCCESS); 1004 } 1005 1006 /* 1007 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1008 * port status registers and an attached device type via sata_device 1009 * structure. 1010 * 1011 * We return the cached information from a previous hardware probe. The 1012 * actual hardware probing itself was done either from within 1013 * ahci_initialize_controller() during the driver attach or from a phy 1014 * ready change interrupt handler. 1015 */ 1016 static int 1017 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1018 { 1019 ahci_ctl_t *ahci_ctlp; 1020 ahci_port_t *ahci_portp; 1021 uint8_t cport = sd->satadev_addr.cport; 1022 uint8_t pmport = sd->satadev_addr.pmport; 1023 uint8_t qual = sd->satadev_addr.qual; 1024 uint8_t device_type; 1025 uint32_t port_state; 1026 uint8_t port; 1027 1028 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1029 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1030 1031 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1032 "ahci_tran_probe_port enter: cport: %d, " 1033 "pmport: %d, qual: %d", cport, pmport, qual); 1034 1035 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1036 1037 mutex_enter(&ahci_portp->ahciport_mutex); 1038 1039 port_state = ahci_portp->ahciport_port_state; 1040 switch (port_state) { 1041 1042 case SATA_PSTATE_FAILED: 1043 sd->satadev_state = SATA_PSTATE_FAILED; 1044 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1045 "ahci_tran_probe_port: port %d PORT FAILED", port); 1046 goto out; 1047 1048 case SATA_PSTATE_SHUTDOWN: 1049 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1050 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1051 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1052 goto out; 1053 1054 case SATA_PSTATE_PWROFF: 1055 sd->satadev_state = SATA_PSTATE_PWROFF; 1056 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1057 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1058 goto out; 1059 1060 case SATA_PSTATE_PWRON: 1061 sd->satadev_state = SATA_PSTATE_PWRON; 1062 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1063 "ahci_tran_probe_port: port %d PORT PWRON", port); 1064 break; 1065 1066 default: 1067 sd->satadev_state = port_state; 1068 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1069 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1070 port, port_state); 1071 break; 1072 } 1073 1074 device_type = ahci_portp->ahciport_device_type; 1075 1076 switch (device_type) { 1077 1078 case SATA_DTYPE_ATADISK: 1079 sd->satadev_type = SATA_DTYPE_ATADISK; 1080 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1081 "ahci_tran_probe_port: port %d DISK found", port); 1082 break; 1083 1084 case SATA_DTYPE_ATAPICD: 1085 sd->satadev_type = SATA_DTYPE_ATAPICD; 1086 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1087 "ahci_tran_probe_port: port %d ATAPI found", port); 1088 break; 1089 1090 case SATA_DTYPE_PMULT: 1091 sd->satadev_type = SATA_DTYPE_PMULT; 1092 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1093 "ahci_tran_probe_port: port %d Port Multiplier found", 1094 port); 1095 break; 1096 1097 case SATA_DTYPE_UNKNOWN: 1098 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1099 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1100 "ahci_tran_probe_port: port %d Unknown device found", port); 1101 break; 1102 1103 default: 1104 /* we don't support any other device types */ 1105 sd->satadev_type = SATA_DTYPE_NONE; 1106 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1107 "ahci_tran_probe_port: port %d No device found", port); 1108 break; 1109 } 1110 1111 out: 1112 ahci_update_sata_registers(ahci_ctlp, port, sd); 1113 mutex_exit(&ahci_portp->ahciport_mutex); 1114 1115 return (SATA_SUCCESS); 1116 } 1117 1118 /* 1119 * There are four operation modes in sata framework: 1120 * SATA_OPMODE_INTERRUPTS 1121 * SATA_OPMODE_POLLING 1122 * SATA_OPMODE_ASYNCH 1123 * SATA_OPMODE_SYNCH 1124 * 1125 * Their combined meanings as following: 1126 * 1127 * SATA_OPMODE_SYNCH 1128 * The command has to be completed before sata_tran_start functions returns. 1129 * Either interrupts or polling could be used - it's up to the driver. 1130 * Mode used currently for internal, sata-module initiated operations. 1131 * 1132 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1133 * It is the same as the one above. 1134 * 1135 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1136 * The command has to be completed before sata_tran_start function returns. 1137 * No interrupt used, polling only. This should be the mode used for scsi 1138 * packets with FLAG_NOINTR. 1139 * 1140 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1141 * The command may be queued (callback function specified). Interrupts could 1142 * be used. It's normal operation mode. 1143 */ 1144 /* 1145 * Called by sata framework to transport a sata packet down stream. 1146 */ 1147 static int 1148 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1149 { 1150 ahci_ctl_t *ahci_ctlp; 1151 ahci_port_t *ahci_portp; 1152 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1153 uint8_t port; 1154 1155 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1156 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1157 1158 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1159 "ahci_tran_start enter: cport %d satapkt 0x%p", 1160 cport, (void *)spkt); 1161 1162 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1163 1164 mutex_enter(&ahci_portp->ahciport_mutex); 1165 1166 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1167 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1168 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1169 /* 1170 * In case the targer driver would send the packet before 1171 * sata framework can have the opportunity to process those 1172 * event reports. 1173 */ 1174 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1175 spkt->satapkt_device.satadev_state = 1176 ahci_portp->ahciport_port_state; 1177 ahci_update_sata_registers(ahci_ctlp, port, 1178 &spkt->satapkt_device); 1179 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1180 "ahci_tran_start returning PORT_ERROR while " 1181 "port in FAILED/SHUTDOWN/PWROFF state: " 1182 "port: %d", port); 1183 mutex_exit(&ahci_portp->ahciport_mutex); 1184 return (SATA_TRAN_PORT_ERROR); 1185 } 1186 1187 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1188 /* 1189 * ahci_intr_phyrdy_change() may have rendered it to 1190 * SATA_DTYPE_NONE. 1191 */ 1192 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1193 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1194 spkt->satapkt_device.satadev_state = 1195 ahci_portp->ahciport_port_state; 1196 ahci_update_sata_registers(ahci_ctlp, port, 1197 &spkt->satapkt_device); 1198 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1199 "ahci_tran_start returning PORT_ERROR while " 1200 "no device attached: port: %d", port); 1201 mutex_exit(&ahci_portp->ahciport_mutex); 1202 return (SATA_TRAN_PORT_ERROR); 1203 } 1204 1205 /* 1206 * SATA HBA driver should remember that a device was reset and it 1207 * is supposed to reject any packets which do not specify either 1208 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1209 * 1210 * This is to prevent a race condition when a device was arbitrarily 1211 * reset by the HBA driver (and lost it's setting) and a target 1212 * driver sending some commands to a device before the sata framework 1213 * has a chance to restore the device setting (such as cache enable/ 1214 * disable or other resettable stuff). 1215 */ 1216 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1217 ahci_portp->ahciport_reset_in_progress = 0; 1218 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1219 "ahci_tran_start clearing the " 1220 "reset_in_progress for port: %d", port); 1221 } 1222 1223 if (ahci_portp->ahciport_reset_in_progress && 1224 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1225 ! ddi_in_panic()) { 1226 spkt->satapkt_reason = SATA_PKT_BUSY; 1227 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1228 "ahci_tran_start returning BUSY while " 1229 "reset in progress: port: %d", port); 1230 mutex_exit(&ahci_portp->ahciport_mutex); 1231 return (SATA_TRAN_BUSY); 1232 } 1233 1234 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1235 spkt->satapkt_reason = SATA_PKT_BUSY; 1236 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1237 "ahci_tran_start returning BUSY while " 1238 "mopping in progress: port: %d", port); 1239 mutex_exit(&ahci_portp->ahciport_mutex); 1240 return (SATA_TRAN_BUSY); 1241 } 1242 1243 if (spkt->satapkt_op_mode & 1244 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1245 /* We need to do the sync start now */ 1246 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1247 spkt) == AHCI_FAILURE) { 1248 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1249 "return QUEUE_FULL: port %d", port); 1250 mutex_exit(&ahci_portp->ahciport_mutex); 1251 return (SATA_TRAN_QUEUE_FULL); 1252 } 1253 } else { 1254 /* Async start, using interrupt */ 1255 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1256 == AHCI_FAILURE) { 1257 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1258 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1259 "returning QUEUE_FULL: port %d", port); 1260 mutex_exit(&ahci_portp->ahciport_mutex); 1261 return (SATA_TRAN_QUEUE_FULL); 1262 } 1263 } 1264 1265 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1266 "sata tran accepted: port %d", port); 1267 1268 mutex_exit(&ahci_portp->ahciport_mutex); 1269 return (SATA_TRAN_ACCEPTED); 1270 } 1271 1272 /* 1273 * SATA_OPMODE_SYNCH flag is set 1274 * 1275 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1276 * without interrupt, otherwise we can still use the interrupt. 1277 * 1278 * WARNING!!! ahciport_mutex should be acquired before the function 1279 * is called. 1280 */ 1281 static int 1282 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1283 uint8_t port, sata_pkt_t *spkt) 1284 { 1285 int pkt_timeout_ticks; 1286 uint32_t timeout_tags; 1287 int rval; 1288 1289 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1290 "port %d spkt 0x%p", port, spkt); 1291 1292 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1293 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1294 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1295 port, spkt)) == AHCI_FAILURE) { 1296 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1297 return (rval); 1298 } 1299 1300 pkt_timeout_ticks = 1301 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1302 1303 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1304 mutex_exit(&ahci_portp->ahciport_mutex); 1305 1306 /* Simulate the interrupt */ 1307 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1308 1309 drv_usecwait(AHCI_1MS_USECS); 1310 1311 mutex_enter(&ahci_portp->ahciport_mutex); 1312 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1313 if (pkt_timeout_ticks < 0) { 1314 cmn_err(CE_NOTE, "!ahci_do_sync_start: " 1315 "port %d satapkt 0x%p timed out\n", 1316 port, (void *)spkt); 1317 timeout_tags = (0x1 << rval); 1318 mutex_exit(&ahci_portp->ahciport_mutex); 1319 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1320 port, timeout_tags); 1321 mutex_enter(&ahci_portp->ahciport_mutex); 1322 } 1323 } 1324 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1325 return (AHCI_SUCCESS); 1326 1327 } else { 1328 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1329 port, spkt)) == AHCI_FAILURE) 1330 return (rval); 1331 1332 #if AHCI_DEBUG 1333 /* 1334 * Note that the driver always uses the slot 0 to deliver 1335 * REQUEST SENSE or READ LOG EXT command 1336 */ 1337 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1338 ASSERT(rval == 0); 1339 #endif 1340 1341 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1342 cv_wait(&ahci_portp->ahciport_cv, 1343 &ahci_portp->ahciport_mutex); 1344 1345 return (AHCI_SUCCESS); 1346 } 1347 } 1348 1349 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1350 if (satapkt) { \ 1351 satapkt->satapkt_reason = reason; \ 1352 /* \ 1353 * We set the satapkt_reason in both sync and \ 1354 * non-sync cases. \ 1355 */ \ 1356 } \ 1357 if (satapkt && \ 1358 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1359 satapkt->satapkt_comp) { \ 1360 mutex_exit(&ahci_portp->ahciport_mutex); \ 1361 (*satapkt->satapkt_comp)(satapkt); \ 1362 mutex_enter(&ahci_portp->ahciport_mutex); \ 1363 } else { \ 1364 if (satapkt && \ 1365 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1366 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1367 cv_signal(&ahci_portp->ahciport_cv); \ 1368 } 1369 1370 /* 1371 * Searches for and claims a free command slot. 1372 * 1373 * Returns: 1374 * 1375 * AHCI_FAILURE if failed 1376 * 1. if no empty slot left 1377 * 2. non-queued command requested while queued command(s) is outstanding 1378 * 3. queued command requested whild non-queued command(s) is outstanding 1379 * 4. HBA doesn't support multiple-use of command list while already a 1380 * non-queued command is oustanding 1381 * 1382 * claimed slot number if succeeded 1383 * 1384 * NOTE: it will always return slot 0 during error recovery process for 1385 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1386 * 1387 * WARNING!!! ahciport_mutex should be acquired before the function 1388 * is called. 1389 */ 1390 /*ARGSUSED*/ 1391 static int 1392 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1393 ahci_port_t *ahci_portp, int command_type) 1394 { 1395 uint32_t free_slots; 1396 int slot; 1397 1398 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1399 "ahciport_pending_tags = 0x%x " 1400 "ahciport_pending_ncq_tags = 0x%x", 1401 ahci_portp->ahciport_pending_tags, 1402 ahci_portp->ahciport_pending_ncq_tags); 1403 1404 /* 1405 * According to the AHCI spec, system software is responsible to 1406 * ensure that queued and non-queued commands are not mixed in 1407 * the command list. 1408 */ 1409 if (command_type == AHCI_NON_NCQ_CMD) { 1410 /* Non-NCQ command request */ 1411 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1412 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1413 "ahci_claim_free_slot: there is still pending " 1414 "queued command(s) in the command list, " 1415 "so no available slot for the non-queued " 1416 "command"); 1417 return (AHCI_FAILURE); 1418 } 1419 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1420 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1421 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1422 "ahci_claim_free_slot: HBA cannot support multiple-" 1423 "use of the command list for non-queued commands"); 1424 return (AHCI_FAILURE); 1425 } 1426 free_slots = (~ahci_portp->ahciport_pending_tags) & 1427 AHCI_SLOT_MASK(ahci_ctlp); 1428 } else if (command_type == AHCI_NCQ_CMD) { 1429 /* NCQ command request */ 1430 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1431 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1432 "ahci_claim_free_slot: there is still pending " 1433 "non-queued command(s) in the command list, " 1434 "so no available slot for the queued command"); 1435 return (AHCI_FAILURE); 1436 } 1437 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1438 AHCI_NCQ_SLOT_MASK(ahci_portp); 1439 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1440 /* Error retrieval command request */ 1441 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1442 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1443 "SENSE or READ LOG EXT command"); 1444 slot = 0; 1445 goto out; 1446 } 1447 1448 slot = ddi_ffs(free_slots) - 1; 1449 if (slot == -1) { 1450 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1451 "ahci_claim_free_slot: no empty slots"); 1452 return (AHCI_FAILURE); 1453 } 1454 1455 /* 1456 * According to the AHCI spec, to allow a simple mechanism for the 1457 * HBA to map command list slots to queue entries, software must 1458 * match the tag number it uses to the slot it is placing the command 1459 * in. For example, if a queued command is placed in slot 5, the tag 1460 * for that command must be 5. 1461 */ 1462 if (command_type == AHCI_NCQ_CMD) { 1463 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1464 } 1465 1466 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1467 1468 out: 1469 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1470 "ahci_claim_free_slot: found slot: 0x%x", slot); 1471 1472 return (slot); 1473 } 1474 1475 /* 1476 * Builds the Command Table for the sata packet and delivers it to controller. 1477 * 1478 * Returns: 1479 * slot number if we can obtain a slot successfully 1480 * otherwise, return AHCI_FAILURE 1481 * 1482 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1483 */ 1484 static int 1485 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1486 uint8_t port, sata_pkt_t *spkt) 1487 { 1488 int cmd_slot; 1489 sata_cmd_t *scmd; 1490 ahci_fis_h2d_register_t *h2d_register_fisp; 1491 ahci_cmd_table_t *cmd_table; 1492 ahci_cmd_header_t *cmd_header; 1493 int ncookies; 1494 int i; 1495 int command_type = AHCI_NON_NCQ_CMD; 1496 int ncq_qdepth; 1497 #if AHCI_DEBUG 1498 uint32_t *ptr; 1499 uint8_t *ptr2; 1500 #endif 1501 1502 spkt->satapkt_reason = SATA_PKT_BUSY; 1503 1504 scmd = &spkt->satapkt_cmd; 1505 1506 /* Check if the command is a NCQ command */ 1507 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1508 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1509 command_type = AHCI_NCQ_CMD; 1510 1511 /* 1512 * When NCQ is support, system software must determine the 1513 * maximum tag allowed by the device and the HBA, and it 1514 * must use a value not beyond of the lower bound of the two. 1515 * 1516 * Sata module is going to calculate the qdepth and send 1517 * down to HBA driver via sata_cmd. 1518 */ 1519 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1520 1521 /* 1522 * At the moment, the driver doesn't support the dynamic 1523 * setting of the maximum ncq depth, and the value can be 1524 * set either during the attach or after hot-plug insertion. 1525 */ 1526 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1527 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1528 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1529 "ahci_deliver_satapkt: port %d the max tags for " 1530 "NCQ command is %d", port, ncq_qdepth); 1531 } else { 1532 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1533 cmn_err(CE_WARN, "ahci_deliver_satapkt: port " 1534 "%d the max tag for NCQ command is " 1535 "requested to change from %d to %d, at the" 1536 " moment the driver doesn't support the " 1537 "dynamic change so it's going to " 1538 "still use the previous tag value", port, 1539 ahci_portp->ahciport_max_ncq_tags, 1540 ncq_qdepth); 1541 } 1542 } 1543 } 1544 1545 /* Check if the command is an error retrieval command */ 1546 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1547 command_type = AHCI_ERR_RETRI_CMD; 1548 1549 /* Check if there is an empty command slot */ 1550 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1551 if (cmd_slot == AHCI_FAILURE) { 1552 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1553 return (AHCI_FAILURE); 1554 } 1555 1556 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1557 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1558 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1559 cmd_slot, port, (void *)spkt); 1560 1561 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1562 bzero((void *)cmd_table, ahci_cmd_table_size); 1563 1564 /* For data transfer operations, it is the H2D Register FIS */ 1565 h2d_register_fisp = 1566 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1567 1568 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1569 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1570 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1571 SET_FIS_PMP(h2d_register_fisp, 1572 spkt->satapkt_device.satadev_addr.pmport); 1573 } 1574 1575 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1576 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1577 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1578 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1579 1580 switch (scmd->satacmd_addr_type) { 1581 1582 case 0: 1583 /* 1584 * satacmd_addr_type will be 0 for the commands below: 1585 * ATAPI command 1586 * SATAC_IDLE_IM 1587 * SATAC_STANDBY_IM 1588 * SATAC_DOWNLOAD_MICROCODE 1589 * SATAC_FLUSH_CACHE 1590 * SATAC_SET_FEATURES 1591 * SATAC_SMART 1592 * SATAC_ID_PACKET_DEVICE 1593 * SATAC_ID_DEVICE 1594 */ 1595 /* fallthrough */ 1596 1597 case ATA_ADDR_LBA: 1598 /* fallthrough */ 1599 1600 case ATA_ADDR_LBA28: 1601 /* LBA[7:0] */ 1602 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1603 1604 /* LBA[15:8] */ 1605 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1606 1607 /* LBA[23:16] */ 1608 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1609 1610 /* LBA [27:24] (also called dev_head) */ 1611 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1612 1613 break; 1614 1615 case ATA_ADDR_LBA48: 1616 /* LBA[7:0] */ 1617 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1618 1619 /* LBA[15:8] */ 1620 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1621 1622 /* LBA[23:16] */ 1623 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1624 1625 /* LBA [31:24] */ 1626 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1627 scmd->satacmd_lba_low_msb); 1628 1629 /* LBA [39:32] */ 1630 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1631 scmd->satacmd_lba_mid_msb); 1632 1633 /* LBA [47:40] */ 1634 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1635 scmd->satacmd_lba_high_msb); 1636 1637 /* Set dev_head */ 1638 SET_FIS_DEV_HEAD(h2d_register_fisp, 1639 scmd->satacmd_device_reg); 1640 1641 /* Set the extended sector count and features */ 1642 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1643 scmd->satacmd_sec_count_msb); 1644 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1645 scmd->satacmd_features_reg_ext); 1646 break; 1647 } 1648 1649 /* 1650 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1651 * filled into features field, and sector count 8:15 is filled into 1652 * features (exp) field. TAG is filled into sector field. 1653 */ 1654 if (command_type == AHCI_NCQ_CMD) { 1655 SET_FIS_FEATURES(h2d_register_fisp, 1656 scmd->satacmd_sec_count_lsb); 1657 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1658 scmd->satacmd_sec_count_msb); 1659 1660 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1661 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1662 } 1663 1664 ncookies = scmd->satacmd_num_dma_cookies; 1665 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1666 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1667 ncookies, ahci_dma_prdt_number); 1668 1669 ASSERT(ncookies <= ahci_dma_prdt_number); 1670 1671 /* *** now fill the scatter gather list ******* */ 1672 for (i = 0; i < ncookies; i++) { 1673 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1674 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1675 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1676 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1677 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1678 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1679 } 1680 1681 /* The ACMD field is filled in for ATAPI command */ 1682 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1683 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1684 SATA_ATAPI_MAX_CDB_LEN); 1685 } 1686 1687 /* Set Command Header in Command List */ 1688 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1689 BZERO_DESCR_INFO(cmd_header); 1690 BZERO_PRD_BYTE_COUNT(cmd_header); 1691 1692 /* Set the number of entries in the PRD table */ 1693 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1694 1695 /* Set the length of the command in the CFIS area */ 1696 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1697 1698 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1699 "sata_data_direction = 0x%x", 1700 scmd->satacmd_flags.sata_data_direction); 1701 1702 /* Set A bit if it is an ATAPI command */ 1703 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1704 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1705 1706 /* Set W bit if data is going to the device */ 1707 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1708 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1709 1710 /* 1711 * Set the prefetchable bit - this bit is only valid if the PRDTL 1712 * field is non-zero or the ATAPI 'A' bit is set in the command 1713 * header. This bit cannot be set when using native command 1714 * queuing commands or when using FIS-based switching with a Port 1715 * multiplier. 1716 */ 1717 if (command_type != AHCI_NCQ_CMD) 1718 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1719 1720 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1721 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1722 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1723 1724 /* 1725 * We are overloading satapkt_hba_driver_private with 1726 * watched_cycle count. 1727 */ 1728 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1729 1730 #if AHCI_DEBUG 1731 /* Dump the command header and table */ 1732 AHCIDBG0(AHCIDBG_COMMAND, ahci_ctlp, "\n"); 1733 AHCIDBG3(AHCIDBG_COMMAND, ahci_ctlp, 1734 "Command header&table for spkt 0x%p cmd_reg 0x%x port %d", 1735 spkt, scmd->satacmd_cmd_reg, port); 1736 ptr = (uint32_t *)cmd_header; 1737 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1738 " Command Header:%8x %8x %8x %8x", 1739 ptr[0], ptr[1], ptr[2], ptr[3]); 1740 1741 /* Dump the H2D register FIS */ 1742 ptr = (uint32_t *)h2d_register_fisp; 1743 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1744 " Command FIS: %8x %8x %8x %8x", 1745 ptr[0], ptr[1], ptr[2], ptr[3]); 1746 1747 /* Dump the ACMD register FIS */ 1748 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1749 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1750 if (ahci_debug_flags & AHCIDBG_COMMAND) 1751 ahci_log(ahci_ctlp, CE_WARN, 1752 " ATAPI command: %2x %2x %2x %2x " 1753 "%2x %2x %2x %2x", 1754 ptr2[8 * i], ptr2[8 * i + 1], 1755 ptr2[8 * i + 2], ptr2[8 * i + 3], 1756 ptr2[8 * i + 4], ptr2[8 * i + 5], 1757 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1758 1759 /* Dump the PRDT */ 1760 for (i = 0; i < ncookies; i++) { 1761 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1762 AHCIDBG5(AHCIDBG_COMMAND, ahci_ctlp, 1763 " Cookie %d: %8x %8x %8x %8x", 1764 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1765 } 1766 #endif 1767 1768 (void) ddi_dma_sync( 1769 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1770 0, 1771 ahci_cmd_table_size, 1772 DDI_DMA_SYNC_FORDEV); 1773 1774 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1775 cmd_slot * sizeof (ahci_cmd_header_t), 1776 sizeof (ahci_cmd_header_t), 1777 DDI_DMA_SYNC_FORDEV); 1778 1779 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1780 if (command_type == AHCI_NCQ_CMD) { 1781 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1782 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1783 (0x1 << cmd_slot)); 1784 } 1785 1786 /* Indicate to the HBA that a command is active. */ 1787 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1788 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1789 (0x1 << cmd_slot)); 1790 1791 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1792 "exit: port %d", port); 1793 1794 return (cmd_slot); 1795 } 1796 1797 /* 1798 * Called by the sata framework to abort the previously sent packet(s). 1799 * 1800 * Reset device to abort commands. 1801 */ 1802 static int 1803 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1804 { 1805 ahci_ctl_t *ahci_ctlp; 1806 ahci_port_t *ahci_portp; 1807 uint32_t slot_status = 0; 1808 uint32_t aborted_tags = 0; 1809 uint32_t finished_tags = 0; 1810 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1811 uint8_t port; 1812 int tmp_slot; 1813 1814 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1815 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1816 1817 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1818 "ahci_tran_abort enter: port %d", port); 1819 1820 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1821 mutex_enter(&ahci_portp->ahciport_mutex); 1822 1823 /* 1824 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1825 * commands are being mopped, therefore there is nothing else to do 1826 */ 1827 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1828 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1829 "ahci_tran_abort: port %d is in " 1830 "mopping process, so just return directly ", port); 1831 mutex_exit(&ahci_portp->ahciport_mutex); 1832 return (SATA_SUCCESS); 1833 } 1834 1835 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1836 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1837 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1838 /* 1839 * In case the targer driver would send the request before 1840 * sata framework can have the opportunity to process those 1841 * event reports. 1842 */ 1843 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1844 spkt->satapkt_device.satadev_state = 1845 ahci_portp->ahciport_port_state; 1846 ahci_update_sata_registers(ahci_ctlp, port, 1847 &spkt->satapkt_device); 1848 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1849 "ahci_tran_abort returning SATA_FAILURE while " 1850 "port in FAILED/SHUTDOWN/PWROFF state: " 1851 "port: %d", port); 1852 mutex_exit(&ahci_portp->ahciport_mutex); 1853 return (SATA_FAILURE); 1854 } 1855 1856 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1857 /* 1858 * ahci_intr_phyrdy_change() may have rendered it to 1859 * AHCI_PORT_TYPE_NODEV. 1860 */ 1861 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1862 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1863 spkt->satapkt_device.satadev_state = 1864 ahci_portp->ahciport_port_state; 1865 ahci_update_sata_registers(ahci_ctlp, port, 1866 &spkt->satapkt_device); 1867 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1868 "ahci_tran_abort returning SATA_FAILURE while " 1869 "no device attached: port: %d", port); 1870 mutex_exit(&ahci_portp->ahciport_mutex); 1871 return (SATA_FAILURE); 1872 } 1873 1874 if (flag == SATA_ABORT_ALL_PACKETS) { 1875 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1876 aborted_tags = ahci_portp->ahciport_pending_tags; 1877 1878 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1879 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 1880 1881 cmn_err(CE_NOTE, "!ahci port %d abort all packets", port); 1882 } else { 1883 aborted_tags = 0xffffffff; 1884 /* 1885 * Aborting one specific packet, first search the 1886 * ahciport_slot_pkts[] list for matching spkt. 1887 */ 1888 for (tmp_slot = 0; 1889 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 1890 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 1891 aborted_tags = (0x1 << tmp_slot); 1892 break; 1893 } 1894 } 1895 1896 if (aborted_tags == 0xffffffff) { 1897 /* request packet is not on the pending list */ 1898 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1899 "Cannot find the aborting pkt 0x%p on the " 1900 "pending list", (void *)spkt); 1901 ahci_update_sata_registers(ahci_ctlp, port, 1902 &spkt->satapkt_device); 1903 mutex_exit(&ahci_portp->ahciport_mutex); 1904 return (SATA_FAILURE); 1905 } 1906 cmn_err(CE_NOTE, "!ahci port %d abort satapkt 0x%p", 1907 port, (void *)spkt); 1908 } 1909 1910 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1911 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1912 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1913 1914 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1915 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1916 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 1917 1918 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 1919 ahci_portp->ahciport_mop_in_progress++; 1920 1921 /* 1922 * To abort the packet(s), first we are trying to clear PxCMD.ST 1923 * to stop the port, and if the port can be stopped 1924 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 1925 * then we just send back the aborted packet(s) with ABORTED flag 1926 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 1927 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 1928 * perform a COMRESET. 1929 */ 1930 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 1931 ahci_portp, port, NULL, NULL); 1932 1933 /* 1934 * Compute which have finished and which need to be retried. 1935 * 1936 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 1937 * minus the slot_status. The aborted_tags has to be deducted by 1938 * finished_tags since we can't possibly abort a tag which had finished 1939 * already. 1940 */ 1941 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1942 finished_tags = ahci_portp->ahciport_pending_tags & 1943 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1944 1945 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1946 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 1947 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 1948 1949 aborted_tags &= ~finished_tags; 1950 1951 ahci_mop_commands(ahci_ctlp, 1952 ahci_portp, 1953 port, 1954 slot_status, 1955 0, /* failed tags */ 1956 0, /* timeout tags */ 1957 aborted_tags, 1958 0); /* reset tags */ 1959 1960 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 1961 mutex_exit(&ahci_portp->ahciport_mutex); 1962 1963 return (SATA_SUCCESS); 1964 } 1965 1966 /* 1967 * Used to do device reset and reject all the pending packets on a device 1968 * during the reset operation. 1969 * 1970 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1971 */ 1972 static int 1973 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 1974 ahci_port_t *ahci_portp, uint8_t port) 1975 { 1976 uint32_t slot_status = 0; 1977 uint32_t reset_tags = 0; 1978 uint32_t finished_tags = 0; 1979 sata_device_t sdevice; 1980 int ret; 1981 1982 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1983 "ahci_reset_device_reject_pkts on port: %d", port); 1984 1985 /* 1986 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1987 * commands are being mopped, therefore there is nothing else to do 1988 */ 1989 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1990 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1991 "ahci_reset_device_reject_pkts: port %d is in " 1992 "mopping process, so return directly ", port); 1993 return (SATA_SUCCESS); 1994 } 1995 1996 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1997 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1998 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1999 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2000 } 2001 2002 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2003 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2004 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2005 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2006 } 2007 2008 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2009 != AHCI_SUCCESS) { 2010 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2011 "Try to do a port reset after software " 2012 "reset failed", port); 2013 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2014 if (ret != AHCI_SUCCESS) { 2015 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2016 "ahci_reset_device_reject_pkts: port %d " 2017 "failed", port); 2018 return (SATA_FAILURE); 2019 } 2020 } 2021 /* Set the reset in progress flag */ 2022 ahci_portp->ahciport_reset_in_progress = 1; 2023 2024 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2025 ahci_portp->ahciport_mop_in_progress++; 2026 2027 /* Indicate to the framework that a reset has happened */ 2028 bzero((void *)&sdevice, sizeof (sata_device_t)); 2029 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2030 sdevice.satadev_addr.pmport = 0; 2031 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2032 2033 sdevice.satadev_state = SATA_DSTATE_RESET | 2034 SATA_DSTATE_PWR_ACTIVE; 2035 mutex_exit(&ahci_portp->ahciport_mutex); 2036 sata_hba_event_notify( 2037 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2038 &sdevice, 2039 SATA_EVNT_DEVICE_RESET); 2040 mutex_enter(&ahci_portp->ahciport_mutex); 2041 2042 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2043 "port %d sending event up: SATA_EVNT_RESET", port); 2044 2045 /* Next try to mop the pending commands */ 2046 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2047 finished_tags = ahci_portp->ahciport_pending_tags & 2048 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2049 2050 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2051 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2052 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2053 2054 reset_tags &= ~finished_tags; 2055 2056 ahci_mop_commands(ahci_ctlp, 2057 ahci_portp, 2058 port, 2059 slot_status, 2060 0, /* failed tags */ 2061 0, /* timeout tags */ 2062 0, /* aborted tags */ 2063 reset_tags); /* reset tags */ 2064 2065 return (SATA_SUCCESS); 2066 } 2067 2068 /* 2069 * Used to do port reset and reject all the pending packets on a port during 2070 * the reset operation. 2071 * 2072 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2073 */ 2074 static int 2075 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2076 ahci_port_t *ahci_portp, uint8_t port) 2077 { 2078 uint32_t slot_status = 0; 2079 uint32_t reset_tags = 0; 2080 uint32_t finished_tags = 0; 2081 2082 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2083 "ahci_reset_port_reject_pkts on port: %d", port); 2084 2085 /* 2086 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2087 * commands are being mopped, therefore there is nothing else to do 2088 */ 2089 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2090 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2091 "ahci_reset_port_reject_pkts: port %d is in " 2092 "mopping process, so return directly ", port); 2093 return (SATA_SUCCESS); 2094 } 2095 2096 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2097 ahci_portp->ahciport_mop_in_progress++; 2098 2099 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2100 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2101 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2102 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2103 } 2104 2105 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2106 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2107 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2108 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2109 } 2110 2111 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2112 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2113 NULL) != AHCI_SUCCESS) 2114 return (SATA_FAILURE); 2115 2116 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2117 finished_tags = ahci_portp->ahciport_pending_tags & 2118 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2119 2120 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2121 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2122 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2123 2124 reset_tags &= ~finished_tags; 2125 2126 ahci_mop_commands(ahci_ctlp, 2127 ahci_portp, 2128 port, 2129 slot_status, 2130 0, /* failed tags */ 2131 0, /* timeout tags */ 2132 0, /* aborted tags */ 2133 reset_tags); /* reset tags */ 2134 2135 return (SATA_SUCCESS); 2136 } 2137 2138 /* 2139 * Used to do hba reset and reject all the pending packets on all ports 2140 * during the reset operation. 2141 */ 2142 static int 2143 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2144 { 2145 ahci_port_t *ahci_portp; 2146 uint32_t slot_status[AHCI_MAX_PORTS]; 2147 uint32_t reset_tags[AHCI_MAX_PORTS]; 2148 uint32_t finished_tags[AHCI_MAX_PORTS]; 2149 uint8_t port; 2150 int ret = SATA_SUCCESS; 2151 2152 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2153 "ahci_reset_hba_reject_pkts enter"); 2154 2155 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2156 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2157 continue; 2158 } 2159 2160 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2161 2162 mutex_enter(&ahci_portp->ahciport_mutex); 2163 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2164 slot_status[port] = ddi_get32( 2165 ahci_ctlp->ahcictl_ahci_acc_handle, 2166 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2167 reset_tags[port] = slot_status[port] & 2168 AHCI_SLOT_MASK(ahci_ctlp); 2169 } 2170 2171 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2172 slot_status[port] = ddi_get32( 2173 ahci_ctlp->ahcictl_ahci_acc_handle, 2174 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2175 reset_tags[port] = slot_status[port] & 2176 AHCI_NCQ_SLOT_MASK(ahci_portp); 2177 } 2178 mutex_exit(&ahci_portp->ahciport_mutex); 2179 } 2180 2181 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2182 ret = SATA_FAILURE; 2183 goto out; 2184 } 2185 2186 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2187 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2188 continue; 2189 } 2190 2191 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2192 2193 mutex_enter(&ahci_portp->ahciport_mutex); 2194 /* 2195 * To prevent recursive enter to ahci_mop_commands, we need 2196 * check AHCI_PORT_FLAG_MOPPING flag. 2197 */ 2198 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2199 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2200 "ahci_reset_hba_reject_pkts: port %d is in " 2201 "mopping process, so return directly ", port); 2202 mutex_exit(&ahci_portp->ahciport_mutex); 2203 continue; 2204 } 2205 2206 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2207 ahci_portp->ahciport_mop_in_progress++; 2208 2209 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2210 finished_tags[port] = 2211 ahci_portp->ahciport_pending_tags & 2212 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2213 2214 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2215 finished_tags[port] = 2216 ahci_portp->ahciport_pending_ncq_tags & 2217 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2218 2219 reset_tags[port] &= ~finished_tags[port]; 2220 2221 ahci_mop_commands(ahci_ctlp, 2222 ahci_portp, 2223 port, 2224 slot_status[port], 2225 0, /* failed tags */ 2226 0, /* timeout tags */ 2227 0, /* aborted tags */ 2228 reset_tags[port]); /* reset tags */ 2229 mutex_exit(&ahci_portp->ahciport_mutex); 2230 } 2231 out: 2232 return (ret); 2233 } 2234 2235 /* 2236 * Called by sata framework to reset a port(s) or device. 2237 */ 2238 static int 2239 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2240 { 2241 ahci_ctl_t *ahci_ctlp; 2242 ahci_port_t *ahci_portp; 2243 uint8_t cport = sd->satadev_addr.cport; 2244 uint8_t port; 2245 int ret = SATA_SUCCESS; 2246 2247 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2248 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2249 2250 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2251 "ahci_tran_reset_port enter: cport: %d", cport); 2252 2253 switch (sd->satadev_addr.qual) { 2254 case SATA_ADDR_CPORT: 2255 /* Port reset */ 2256 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2257 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2258 "reset port", port); 2259 2260 mutex_enter(&ahci_portp->ahciport_mutex); 2261 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2262 mutex_exit(&ahci_portp->ahciport_mutex); 2263 2264 break; 2265 2266 case SATA_ADDR_DCPORT: 2267 /* Device reset */ 2268 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2269 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2270 "reset device", port); 2271 2272 mutex_enter(&ahci_portp->ahciport_mutex); 2273 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2274 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2275 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2276 /* 2277 * In case the targer driver would send the request 2278 * before sata framework can have the opportunity to 2279 * process those event reports. 2280 */ 2281 sd->satadev_state = ahci_portp->ahciport_port_state; 2282 ahci_update_sata_registers(ahci_ctlp, port, sd); 2283 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2284 "ahci_tran_reset_dport returning SATA_FAILURE " 2285 "while port in FAILED/SHUTDOWN/PWROFF state: " 2286 "port: %d", port); 2287 mutex_exit(&ahci_portp->ahciport_mutex); 2288 ret = SATA_FAILURE; 2289 break; 2290 } 2291 2292 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2293 /* 2294 * ahci_intr_phyrdy_change() may have rendered it to 2295 * AHCI_PORT_TYPE_NODEV. 2296 */ 2297 sd->satadev_type = SATA_DTYPE_NONE; 2298 sd->satadev_state = ahci_portp->ahciport_port_state; 2299 ahci_update_sata_registers(ahci_ctlp, port, sd); 2300 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2301 "ahci_tran_reset_dport returning SATA_FAILURE " 2302 "while no device attached: port: %d", port); 2303 mutex_exit(&ahci_portp->ahciport_mutex); 2304 ret = SATA_FAILURE; 2305 break; 2306 } 2307 2308 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2309 ahci_portp, port); 2310 mutex_exit(&ahci_portp->ahciport_mutex); 2311 break; 2312 2313 case SATA_ADDR_CNTRL: 2314 /* Reset the whole controller */ 2315 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2316 "reset the whole hba", port); 2317 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2318 break; 2319 2320 case SATA_ADDR_PMPORT: 2321 case SATA_ADDR_DPMPORT: 2322 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2323 "ahci_tran_reset_dport: port multiplier will be " 2324 "supported later"); 2325 /* FALLSTHROUGH */ 2326 default: 2327 ret = SATA_FAILURE; 2328 } 2329 2330 return (ret); 2331 } 2332 2333 /* 2334 * Called by sata framework to activate a port as part of hotplug. 2335 * (cfgadm -c connect satax/y) 2336 * Note: Not port-mult aware. 2337 */ 2338 static int 2339 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2340 { 2341 ahci_ctl_t *ahci_ctlp; 2342 ahci_port_t *ahci_portp; 2343 uint8_t cport = satadev->satadev_addr.cport; 2344 uint8_t port; 2345 2346 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2347 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2348 2349 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2350 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2351 2352 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2353 2354 mutex_enter(&ahci_portp->ahciport_mutex); 2355 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2356 cmn_err(CE_NOTE, "!ahci port %d is activated", port); 2357 2358 /* 2359 * Reset the port so that the PHY communication would be re-established. 2360 * But this reset is an internal operation and the sata module doesn't 2361 * need to know about it. Moreover, the port with a device attached will 2362 * be started too. 2363 */ 2364 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2365 ahci_portp, port, 2366 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2367 NULL); 2368 2369 /* 2370 * Need to check the link status and device status of the port 2371 * and consider raising power if the port was in D3 state 2372 */ 2373 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2374 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2375 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2376 2377 satadev->satadev_state = ahci_portp->ahciport_port_state; 2378 2379 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2380 2381 mutex_exit(&ahci_portp->ahciport_mutex); 2382 return (SATA_SUCCESS); 2383 } 2384 2385 /* 2386 * Called by sata framework to deactivate a port as part of hotplug. 2387 * (cfgadm -c disconnect satax/y) 2388 * Note: Not port-mult aware. 2389 */ 2390 static int 2391 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2392 { 2393 ahci_ctl_t *ahci_ctlp; 2394 ahci_port_t *ahci_portp; 2395 uint8_t cport = satadev->satadev_addr.cport; 2396 uint8_t port; 2397 uint32_t port_scontrol; 2398 2399 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2400 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2401 2402 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2403 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2404 2405 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2406 2407 mutex_enter(&ahci_portp->ahciport_mutex); 2408 cmn_err(CE_NOTE, "!ahci port %d is deactivated", port); 2409 2410 /* Disable the interrupts on the port */ 2411 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2412 2413 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2414 goto phy_offline; 2415 } 2416 2417 /* First to abort all the pending commands */ 2418 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2419 2420 /* Then stop the port */ 2421 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2422 ahci_portp, port); 2423 2424 /* Next put the PHY offline */ 2425 2426 phy_offline: 2427 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2428 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2429 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2430 2431 /* Update ahciport_port_state */ 2432 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2433 satadev->satadev_state = ahci_portp->ahciport_port_state; 2434 2435 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2436 2437 mutex_exit(&ahci_portp->ahciport_mutex); 2438 return (SATA_SUCCESS); 2439 } 2440 2441 /* 2442 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2443 * when a device is unplugged or a port is deactivated. 2444 * 2445 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2446 */ 2447 static void 2448 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2449 ahci_port_t *ahci_portp, uint8_t port) 2450 { 2451 uint32_t slot_status = 0; 2452 uint32_t abort_tags = 0; 2453 2454 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2455 "ahci_reject_all_abort_pkts on port: %d", port); 2456 2457 /* 2458 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2459 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2460 * to get the error data, if yes when the device is removed, the 2461 * command needs to be aborted too. 2462 */ 2463 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2464 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2465 slot_status = 0x1; 2466 abort_tags = 0x1; 2467 goto out; 2468 } else { 2469 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2470 "ahci_reject_all_abort_pkts return directly " 2471 "port %d no needs to reject any outstanding " 2472 "commands", port); 2473 return; 2474 } 2475 } 2476 2477 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2478 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2479 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2480 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2481 } 2482 2483 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2484 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2485 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2486 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2487 } 2488 2489 out: 2490 /* No need to do mop when there is no outstanding commands */ 2491 if (slot_status != 0) { 2492 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2493 ahci_portp->ahciport_mop_in_progress++; 2494 2495 ahci_mop_commands(ahci_ctlp, 2496 ahci_portp, 2497 port, 2498 slot_status, 2499 0, /* failed tags */ 2500 0, /* timeout tags */ 2501 abort_tags, /* aborting tags */ 2502 0); /* reset tags */ 2503 } 2504 } 2505 2506 #if defined(__lock_lint) 2507 static int 2508 ahci_selftest(dev_info_t *dip, sata_device_t *device) 2509 { 2510 return (SATA_SUCCESS); 2511 } 2512 #endif 2513 2514 /* 2515 * Allocate the ports structure, only called by ahci_attach 2516 */ 2517 static int 2518 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2519 { 2520 int port, cport = 0; 2521 2522 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2523 "ahci_alloc_ports_state enter"); 2524 2525 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2526 2527 /* Allocate structures only for the implemented ports */ 2528 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2529 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2530 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2531 "hba port %d not implemented", port); 2532 continue; 2533 } 2534 2535 #ifndef __lock_lint 2536 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2537 ahci_ctlp->ahcictl_port_to_cport[port] = 2538 (uint8_t)cport++; 2539 #endif /* __lock_lint */ 2540 2541 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2542 goto err_out; 2543 } 2544 } 2545 2546 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2547 return (AHCI_SUCCESS); 2548 2549 err_out: 2550 for (port--; port >= 0; port--) { 2551 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2552 ahci_dealloc_port_state(ahci_ctlp, port); 2553 } 2554 } 2555 2556 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2557 return (AHCI_FAILURE); 2558 } 2559 2560 /* 2561 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2562 */ 2563 static void 2564 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2565 { 2566 int port; 2567 2568 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2569 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2570 /* if this port is implemented by the HBA */ 2571 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2572 ahci_dealloc_port_state(ahci_ctlp, port); 2573 } 2574 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2575 } 2576 2577 /* 2578 * Initialize the controller. 2579 * 2580 * This routine can be called from three seperate cases: DDI_ATTACH, 2581 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2582 * other two cases; device signature probing are attempted only during 2583 * DDI_ATTACH case. 2584 * 2585 * WARNING!!! Disable the whole controller's interrupts before calling and 2586 * the interrupts will be enabled upon successfully return. 2587 */ 2588 static int 2589 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2590 { 2591 ahci_port_t *ahci_portp; 2592 uint32_t ghc_control; 2593 int port; 2594 2595 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2596 "ahci_initialize_controller enter"); 2597 2598 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2599 2600 /* 2601 * Indicate that system software is AHCI aware by setting 2602 * GHC.AE to 1 2603 */ 2604 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2605 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2606 2607 ghc_control |= AHCI_HBA_GHC_AE; 2608 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2609 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2610 ghc_control); 2611 2612 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2613 2614 /* Initialize the implemented ports and structures */ 2615 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2616 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2617 continue; 2618 } 2619 2620 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2621 mutex_enter(&ahci_portp->ahciport_mutex); 2622 2623 /* 2624 * Ensure that the controller is not in the running state 2625 * by checking every implemented port's PxCMD register 2626 */ 2627 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2628 != AHCI_SUCCESS) { 2629 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2630 "ahci_initialize_controller: failed to " 2631 "initialize port %d", port); 2632 /* 2633 * Set the port state to SATA_PSTATE_FAILED if 2634 * failed to initialize it. 2635 */ 2636 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2637 } 2638 2639 mutex_exit(&ahci_portp->ahciport_mutex); 2640 } 2641 2642 /* Enable the whole controller interrupts */ 2643 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2644 ahci_enable_all_intrs(ahci_ctlp); 2645 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2646 2647 return (AHCI_SUCCESS); 2648 } 2649 2650 /* 2651 * Reverse of ahci_initialize_controller() 2652 * 2653 * WARNING!!! ahcictl_mutex should be acquired before the function is called. 2654 */ 2655 static void 2656 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2657 { 2658 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2659 "ahci_uninitialize_controller enter"); 2660 2661 /* disable all the interrupts. */ 2662 ahci_disable_all_intrs(ahci_ctlp); 2663 } 2664 2665 /* 2666 * The routine is to initialize the port. First put the port in NOTRunning 2667 * state, then enable port interrupt and clear Serror register. And under 2668 * AHCI_ATTACH case, find device signature and then try to start the port. 2669 * 2670 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2671 */ 2672 static int 2673 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2674 ahci_port_t *ahci_portp, uint8_t port) 2675 { 2676 uint32_t port_cmd_status; 2677 2678 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2679 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2680 2681 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2682 "ahci_initialize_port: port %d " 2683 "port_cmd_status = 0x%x", port, port_cmd_status); 2684 /* 2685 * Check whether the port is in NotRunning state, if not, 2686 * put the port in NotRunning state 2687 */ 2688 if (!(port_cmd_status & 2689 (AHCI_CMD_STATUS_ST | 2690 AHCI_CMD_STATUS_CR | 2691 AHCI_CMD_STATUS_FRE | 2692 AHCI_CMD_STATUS_FR))) { 2693 2694 goto next; 2695 } 2696 2697 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2698 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2699 return (AHCI_FAILURE); 2700 2701 next: 2702 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2703 "port %d is in NotRunning state now", port); 2704 2705 /* 2706 * At the time being, only probe ports/devices and get the types of 2707 * attached devices during attach. In fact, the device can be changed 2708 * during power state changes, but I would like to postpone this part 2709 * when the power management is supported. 2710 */ 2711 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2712 /* Try to get the device signature */ 2713 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2714 2715 /* Return directly if no device connected */ 2716 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2717 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2718 "No device connected to port %d", port); 2719 goto out; 2720 } 2721 2722 /* Try to start the port */ 2723 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2724 != AHCI_SUCCESS) { 2725 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2726 "failed to start port %d", port); 2727 return (AHCI_FAILURE); 2728 } 2729 } 2730 out: 2731 /* Enable port interrupts */ 2732 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2733 2734 return (AHCI_SUCCESS); 2735 } 2736 2737 /* 2738 * AHCI device reset ...; a single device on one of the ports is reset, 2739 * but the HBA and physical communication remain intact. This is the 2740 * least intrusive. 2741 * 2742 * When issuing a software reset sequence, there should not be other 2743 * commands in the command list, so we will first clear and then re-set 2744 * PxCMD.ST to clear PxCI. And before issuing the software reset, 2745 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 2746 * cleared. 2747 * 2748 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 2749 * set before the function is called. 2750 */ 2751 static int 2752 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 2753 uint8_t port) 2754 { 2755 ahci_fis_h2d_register_t *h2d_register_fisp; 2756 ahci_cmd_table_t *cmd_table; 2757 ahci_cmd_header_t *cmd_header; 2758 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 2759 int slot, loop_count; 2760 2761 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2762 "Port %d device resetting", port); 2763 2764 /* First to clear PxCMD.ST */ 2765 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2766 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2767 2768 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 2769 2770 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2771 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2772 port_cmd_status|AHCI_CMD_STATUS_ST); 2773 2774 /* And then to re-set PxCMD.ST */ 2775 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2776 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2777 2778 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2779 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2780 port_cmd_status|AHCI_CMD_STATUS_ST); 2781 2782 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 2783 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2784 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2785 2786 if (port_task_file & AHCI_TFD_STS_BSY || 2787 port_task_file & AHCI_TFD_STS_DRQ) { 2788 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 2789 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2790 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 2791 "but PxCMD.CLO isn't supported, so a port " 2792 "reset is needed."); 2793 return (AHCI_FAILURE); 2794 } 2795 } 2796 2797 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, AHCI_NON_NCQ_CMD); 2798 if (slot == AHCI_FAILURE) { 2799 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2800 "ahci_software_reset: no free slot"); 2801 return (AHCI_FAILURE); 2802 } 2803 2804 /* Now send the first R2H FIS with SRST set to 1 */ 2805 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 2806 bzero((void *)cmd_table, ahci_cmd_table_size); 2807 2808 h2d_register_fisp = 2809 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 2810 2811 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 2812 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 2813 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 2814 2815 /* Set Command Header in Command List */ 2816 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 2817 BZERO_DESCR_INFO(cmd_header); 2818 BZERO_PRD_BYTE_COUNT(cmd_header); 2819 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 2820 2821 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 2822 SET_RESET(cmd_header, 1); 2823 SET_WRITE(cmd_header, 1); 2824 2825 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 2826 0, 2827 ahci_cmd_table_size, 2828 DDI_DMA_SYNC_FORDEV); 2829 2830 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 2831 slot * sizeof (ahci_cmd_header_t), 2832 sizeof (ahci_cmd_header_t), 2833 DDI_DMA_SYNC_FORDEV); 2834 2835 /* Indicate to the HBA that a command is active. */ 2836 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2837 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 2838 (0x1 << slot)); 2839 2840 loop_count = 0; 2841 2842 /* Loop till the first command is finished */ 2843 do { 2844 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2845 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2846 2847 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 2848 /* We are effectively timing out after 0.1 sec. */ 2849 break; 2850 } 2851 /* Wait for 10 millisec */ 2852 #ifndef __lock_lint 2853 delay(AHCI_10MS_TICKS); 2854 #endif /* __lock_lint */ 2855 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 2856 2857 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 2858 "ahci_software_reset: 1st loop count: %d, " 2859 "port_cmd_issue = 0x%x, slot = 0x%x", 2860 loop_count, port_cmd_issue, slot); 2861 2862 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 2863 ahci_portp->ahciport_slot_pkts[slot] = NULL; 2864 2865 /* Now send the second R2H FIS with SRST cleard to zero */ 2866 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 2867 bzero((void *)cmd_table, ahci_cmd_table_size); 2868 2869 h2d_register_fisp = 2870 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 2871 2872 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 2873 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 2874 2875 /* Set Command Header in Command List */ 2876 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 2877 BZERO_DESCR_INFO(cmd_header); 2878 BZERO_PRD_BYTE_COUNT(cmd_header); 2879 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 2880 2881 SET_WRITE(cmd_header, 1); 2882 2883 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 2884 0, 2885 ahci_cmd_table_size, 2886 DDI_DMA_SYNC_FORDEV); 2887 2888 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 2889 slot * sizeof (ahci_cmd_header_t), 2890 sizeof (ahci_cmd_header_t), 2891 DDI_DMA_SYNC_FORDEV); 2892 2893 /* Indicate to the HBA that a command is active. */ 2894 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2895 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 2896 (0x1 << slot)); 2897 2898 loop_count = 0; 2899 2900 /* Loop till the second command is finished */ 2901 do { 2902 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2903 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2904 2905 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 2906 /* We are effectively timing out after 0.1 sec. */ 2907 break; 2908 } 2909 /* Wait for 10 millisec */ 2910 #ifndef __lock_lint 2911 delay(AHCI_10MS_TICKS); 2912 #endif /* __lock_lint */ 2913 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 2914 2915 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 2916 "ahci_software_reset: 2nd loop count: %d, " 2917 "port_cmd_issue = 0x%x, slot = 0x%x", 2918 loop_count, port_cmd_issue, slot); 2919 2920 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 2921 ahci_portp->ahciport_slot_pkts[slot] = NULL; 2922 2923 return (AHCI_SUCCESS); 2924 } 2925 2926 /* 2927 * AHCI port reset ...; the physical communication between the HBA and device 2928 * on a port are disabled. This is more intrusive. 2929 * 2930 * When an HBA or port reset occurs, Phy communication is going to 2931 * be re-established with the device through a COMRESET followed by the 2932 * normal out-of-band communication sequence defined in Serial ATA. AT 2933 * the end of reset, the device, if working properly, will send a D2H 2934 * Register FIS, which contains the device signature. When the HBA receives 2935 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 2936 * the PxSIG register with the signature. 2937 * 2938 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 2939 * to individually spin-up attached devices. Please refer to chapter 10.9 of 2940 * AHCI 1.0 spec. 2941 */ 2942 /* 2943 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 2944 * cleared before the function is called. 2945 */ 2946 static int 2947 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 2948 { 2949 uint32_t cap_status, port_cmd_status; 2950 uint32_t port_scontrol, port_sstatus; 2951 uint32_t port_signature, port_intr_status, port_task_file; 2952 int loop_count; 2953 int rval = AHCI_SUCCESS; 2954 2955 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2956 "Port %d port resetting...", port); 2957 ahci_portp->ahciport_port_state = 0; 2958 2959 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2960 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 2961 2962 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2963 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2964 2965 if (cap_status & AHCI_HBA_CAP_SSS) { 2966 /* 2967 * HBA support staggered spin-up, if the port has 2968 * not spin up yet, then force it to do spin-up 2969 */ 2970 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 2971 if (!(ahci_portp->ahciport_flags 2972 & AHCI_PORT_FLAG_SPINUP)) { 2973 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2974 "Port %d PxCMD.SUD is zero, force " 2975 "it to do spin-up", port); 2976 ahci_portp->ahciport_flags |= 2977 AHCI_PORT_FLAG_SPINUP; 2978 } 2979 } 2980 } else { 2981 /* 2982 * HBA doesn't support stagger spin-up, force it 2983 * to do normal COMRESET 2984 */ 2985 if (ahci_portp->ahciport_flags & 2986 AHCI_PORT_FLAG_SPINUP) { 2987 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2988 "HBA does not support staggered spin-up " 2989 "force it to do normal COMRESET"); 2990 ahci_portp->ahciport_flags &= 2991 ~AHCI_PORT_FLAG_SPINUP; 2992 } 2993 } 2994 2995 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 2996 /* Do normal COMRESET */ 2997 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2998 "ahci_port_reset: do normal COMRESET", port); 2999 3000 /* 3001 * According to the spec, SUD bit should be set here, 3002 * but JMicron JMB363 doesn't follow it, so remove 3003 * the assertion, and just print a debug message. 3004 */ 3005 #if AHCI_DEBUG 3006 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3007 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3008 "port %d SUD bit not set", port) 3009 #endif 3010 3011 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3012 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3013 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3014 3015 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3016 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3017 port_scontrol); 3018 3019 /* Enable PxCMD.FRE to read device */ 3020 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3021 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3022 port_cmd_status|AHCI_CMD_STATUS_FRE); 3023 3024 /* 3025 * Give time for COMRESET to percolate, according to the AHCI 3026 * spec, software shall wait at least 1 millisecond before 3027 * clearing PxSCTL.DET 3028 */ 3029 #ifndef __lock_lint 3030 delay(AHCI_1MS_TICKS*2); 3031 #endif /* __lock_lint */ 3032 3033 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3034 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3035 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3036 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3037 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3038 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3039 port_scontrol); 3040 } else { 3041 /* Do staggered spin-up */ 3042 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3043 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3044 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3045 3046 /* PxSCTL.DET must be 0 */ 3047 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3048 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3049 port_scontrol); 3050 3051 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3052 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3053 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3054 port_cmd_status); 3055 3056 /* 0 -> 1 edge */ 3057 #ifndef __lock_lint 3058 delay(AHCI_1MS_TICKS*2); 3059 #endif /* __lock_lint */ 3060 3061 /* Set PxCMD.SUD to 1 */ 3062 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3063 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3064 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3065 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3066 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3067 port_cmd_status); 3068 3069 /* Enable PxCMD.FRE to read device */ 3070 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3071 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3072 port_cmd_status|AHCI_CMD_STATUS_FRE); 3073 } 3074 3075 /* 3076 * The port enters P:StartComm state, and HBA tells link layer to 3077 * start communication, which involves sending COMRESET to device. 3078 * And the HBA resets PxTFD.STS to 7Fh. 3079 * 3080 * When a COMINIT is received from the device, then the port enters 3081 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3082 * PxSSTS.DET to 1h to indicate a device is detected but communication 3083 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3084 * a COMINIT has been received. 3085 */ 3086 /* 3087 * The DET field is valid only if IPM field indicates 3088 * that the interface is in active state. 3089 */ 3090 loop_count = 0; 3091 do { 3092 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3093 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3094 3095 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3096 /* 3097 * If the interface is not active, the DET field 3098 * is considered not accurate. So we want to 3099 * continue looping. 3100 */ 3101 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3102 } 3103 3104 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3105 /* 3106 * We are effectively timing out after 0.1 sec. 3107 */ 3108 break; 3109 } 3110 3111 /* Wait for 10 millisec */ 3112 #ifndef __lock_lint 3113 delay(AHCI_10MS_TICKS); 3114 #endif /* __lock_lint */ 3115 3116 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3117 3118 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3119 "ahci_port_reset: 1st loop count: %d, " 3120 "port_sstatus = 0x%x port %d", 3121 loop_count, port_sstatus, port); 3122 3123 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3124 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3125 /* 3126 * Either the port is not active or there 3127 * is no device present. 3128 */ 3129 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3130 goto out; 3131 } 3132 3133 /* Now we can make sure there is a device connected to the port */ 3134 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3135 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3136 3137 /* a COMINIT signal is supposed to be received */ 3138 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 3139 cmn_err(CE_WARN, "ahci_port_reset: port %d COMINIT signal " 3140 "from the device not received", port); 3141 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3142 rval = AHCI_FAILURE; 3143 goto out; 3144 } 3145 3146 /* 3147 * According to the spec, when PxSCTL.DET is set to 0h, upon 3148 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3149 * shall be set to '1' by the HBA. 3150 * 3151 * However, we found JMicron JMB363 doesn't follow this, so 3152 * remove this check, and just print a debug message. 3153 */ 3154 #if AHCI_DEBUG 3155 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3156 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3157 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3158 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3159 "port %d BSY bit is not set after COMINIT signal " 3160 "is received", port); 3161 } 3162 #endif 3163 3164 /* 3165 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3166 * the D2H FIS received by HBA. 3167 */ 3168 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3169 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3170 SERROR_EXCHANGED_ERR); 3171 3172 /* 3173 * Next check whether COMRESET is completed successfully 3174 */ 3175 loop_count = 0; 3176 do { 3177 port_task_file = 3178 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3179 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3180 3181 /* 3182 * The Error bit '1' means COMRESET is finished successfully 3183 * The device hardware has been initialized and the power-up 3184 * diagnostics successfully completed. 3185 */ 3186 if (((port_task_file & AHCI_TFD_ERR_MASK) 3187 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 3188 3189 port_signature = ddi_get32( 3190 ahci_ctlp->ahcictl_ahci_acc_handle, 3191 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3192 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 3193 "COMRESET success, D2H register FIS " 3194 "post to received FIS structure " 3195 "port %d signature = 0x%x", 3196 port, port_signature); 3197 goto out_check; 3198 } 3199 3200 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3201 /* 3202 * We are effectively timing out after 11 sec. 3203 */ 3204 break; 3205 } 3206 3207 /* Wait for 10 millisec */ 3208 #ifndef __lock_lint 3209 delay(AHCI_10MS_TICKS); 3210 #endif /* __lock_lint */ 3211 3212 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3213 >> AHCI_TFD_ERR_SHIFT) != 0x1); 3214 3215 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 3216 "count: %d, port_task_file = 0x%x port %d", 3217 loop_count, port_task_file, port); 3218 3219 cmn_err(CE_WARN, "ahci_port_reset: port %d the device hardware " 3220 "has been initialized and the power-up diagnostics failed", 3221 port); 3222 3223 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3224 rval = AHCI_FAILURE; 3225 3226 out: 3227 /* Clear port serror register for the port */ 3228 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3229 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3230 AHCI_SERROR_CLEAR_ALL); 3231 3232 return (rval); 3233 3234 out_check: 3235 /* 3236 * Check device status, if keep busy or COMRESET error 3237 * do device reset to patch some SATA disks' issue 3238 * 3239 * For VT8251, sometimes need to do the device reset 3240 */ 3241 if ((port_task_file & AHCI_TFD_STS_BSY) || 3242 (port_task_file & AHCI_TFD_STS_DRQ)) { 3243 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 3244 "need to do device reset", port); 3245 3246 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 3247 3248 port_task_file = 3249 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3250 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3251 3252 if (port_task_file & AHCI_TFD_STS_BSY || 3253 port_task_file & AHCI_TFD_STS_DRQ) { 3254 cmn_err(CE_WARN, "ahci_port_reset: port %d " 3255 "BSY/DRQ still set after device reset " 3256 "port_task_file = 0x%x", 3257 port, port_task_file); 3258 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3259 rval = AHCI_FAILURE; 3260 } 3261 } 3262 3263 goto out; 3264 } 3265 3266 /* 3267 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3268 * This is the most intrusive. 3269 * 3270 * When an HBA reset occurs, Phy communication will be re-established with 3271 * the device through a COMRESET followed by the normal out-of-band 3272 * communication sequence defined in Serial ATA. AT the end of reset, the 3273 * device, if working properly, will send a D2H Register FIS, which contains 3274 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3275 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3276 * signature. 3277 * 3278 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3279 */ 3280 static int 3281 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3282 { 3283 ahci_port_t *ahci_portp; 3284 uint32_t ghc_control; 3285 uint8_t port; 3286 int loop_count; 3287 int rval = AHCI_SUCCESS; 3288 3289 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3290 3291 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3292 3293 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3294 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3295 3296 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3297 ghc_control |= AHCI_HBA_GHC_HR; 3298 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3299 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3300 3301 /* 3302 * Wait until HBA Reset complete or timeout 3303 */ 3304 loop_count = 0; 3305 do { 3306 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3307 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3308 3309 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3310 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3311 "ahci hba reset is timing out, " 3312 "ghc_control = 0x%x", ghc_control); 3313 /* We are effectively timing out after 1 sec. */ 3314 break; 3315 } 3316 3317 /* Wait for 10 millisec */ 3318 #ifndef __lock_lint 3319 delay(AHCI_10MS_TICKS); 3320 #endif /* __lock_lint */ 3321 3322 } while (ghc_control & AHCI_HBA_GHC_HR); 3323 3324 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3325 "ahci_hba_reset: 1st loop count: %d, " 3326 "ghc_control = 0x%x", loop_count, ghc_control); 3327 3328 if (ghc_control & AHCI_HBA_GHC_HR) { 3329 /* The hba is not reset for some reasons */ 3330 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3331 "hba reset failed: HBA in a hung or locked state"); 3332 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3333 return (AHCI_FAILURE); 3334 } 3335 3336 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3337 /* Only check implemented ports */ 3338 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3339 continue; 3340 } 3341 3342 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3343 mutex_enter(&ahci_portp->ahciport_mutex); 3344 3345 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3346 != AHCI_SUCCESS) { 3347 rval = AHCI_FAILURE; 3348 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3349 "ahci_hba_reset: port %d failed", port); 3350 } 3351 3352 mutex_exit(&ahci_portp->ahciport_mutex); 3353 } 3354 3355 /* 3356 * Indicate that system software is AHCI aware by setting 3357 * GHC.AE to 1 3358 */ 3359 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3360 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3361 3362 ghc_control |= AHCI_HBA_GHC_AE; 3363 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3364 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3365 3366 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3367 3368 return (rval); 3369 } 3370 3371 /* 3372 * This routine is only called from AHCI_ATTACH or phyrdy change 3373 * case. It first calls port reset to initialize port, probe port and probe 3374 * device, then try to read PxSIG register to find the type of device 3375 * attached to the port. 3376 * 3377 * WARNING!!! ahciport_mutex should be acquired before the function 3378 * is called. And the port interrupt is disabled. 3379 */ 3380 static void 3381 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3382 ahci_port_t *ahci_portp, uint8_t port) 3383 { 3384 uint32_t signature; 3385 3386 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3387 "ahci_find_dev_signature enter: port %d", port); 3388 3389 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3390 3391 /* Call port reset to check link status and get device signature */ 3392 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3393 3394 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3395 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3396 "ahci_find_dev_signature: No device is found " 3397 "at port %d", port); 3398 return; 3399 } 3400 3401 /* Check the port state */ 3402 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3403 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3404 "ahci_find_dev_signature: port %d state 0x%x", 3405 port, ahci_portp->ahciport_port_state); 3406 return; 3407 } 3408 3409 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3410 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3411 3412 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3413 "ahci_find_dev_signature: port %d signature = 0x%x", 3414 port, signature); 3415 3416 switch (signature) { 3417 3418 case AHCI_SIGNATURE_DISK: 3419 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3420 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3421 "Disk is found at port: %d", port); 3422 break; 3423 3424 case AHCI_SIGNATURE_ATAPI: 3425 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 3426 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3427 "ATAPI device is found at port: %d", port); 3428 break; 3429 3430 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3431 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3432 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3433 "Port Multiplier is found at port: %d", port); 3434 break; 3435 3436 default: 3437 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3438 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3439 "Unknown device is found at port: %d", port); 3440 } 3441 } 3442 3443 /* 3444 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3445 * to 1, then set it firstly. 3446 * 3447 * Each port contains two major DMA engines. One DMA engine walks through 3448 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3449 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3450 * 3451 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3452 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3453 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3454 * 3455 * Software shall not set PxCMD.ST to '1' unless a functional device is 3456 * present on the port(as determined by PxTFD.STS.BSY = '0', 3457 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3458 * 3459 * WARNING!!! ahciport_mutex should be acquired before the function 3460 * is called. 3461 */ 3462 static int 3463 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3464 { 3465 uint32_t port_cmd_status; 3466 3467 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3468 3469 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3470 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3471 "the state for port %d is 0x%x", 3472 port, ahci_portp->ahciport_port_state); 3473 return (AHCI_FAILURE); 3474 } 3475 3476 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3477 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3478 "no device is attached at port %d", port); 3479 return (AHCI_FAILURE); 3480 } 3481 3482 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3483 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3484 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3485 3486 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3487 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3488 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3489 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3490 port_cmd_status); 3491 } 3492 3493 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3494 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3495 3496 port_cmd_status |= AHCI_CMD_STATUS_ST; 3497 3498 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3499 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3500 port_cmd_status); 3501 3502 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3503 3504 return (AHCI_SUCCESS); 3505 } 3506 3507 /* 3508 * Allocate the ahci_port_t including Received FIS and Command List. 3509 * The argument - port is the physical port number, and not logical 3510 * port number seen by the SATA framework. 3511 * 3512 * WARNING!!! ahcictl_mutex should be acquired before the function 3513 * is called. 3514 */ 3515 static int 3516 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3517 { 3518 ahci_port_t *ahci_portp; 3519 3520 ahci_portp = 3521 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3522 3523 #ifndef __lock_lint 3524 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3525 #endif /* __lock_lint */ 3526 3527 ahci_portp->ahciport_port_num = port; 3528 3529 /* Intialize the port condition variable */ 3530 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3531 3532 /* Initialize the port mutex */ 3533 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3534 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3535 3536 mutex_enter(&ahci_portp->ahciport_mutex); 3537 3538 /* 3539 * Allocate memory for received FIS structure and 3540 * command list for this port 3541 */ 3542 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3543 goto err_case1; 3544 } 3545 3546 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3547 goto err_case2; 3548 } 3549 3550 ahci_portp->ahciport_event_args = 3551 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3552 3553 if (ahci_portp->ahciport_event_args == NULL) 3554 goto err_case3; 3555 3556 mutex_exit(&ahci_portp->ahciport_mutex); 3557 3558 return (AHCI_SUCCESS); 3559 3560 err_case3: 3561 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3562 3563 err_case2: 3564 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3565 3566 err_case1: 3567 mutex_exit(&ahci_portp->ahciport_mutex); 3568 mutex_destroy(&ahci_portp->ahciport_mutex); 3569 cv_destroy(&ahci_portp->ahciport_cv); 3570 3571 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3572 3573 return (AHCI_FAILURE); 3574 } 3575 3576 /* 3577 * Reverse of ahci_dealloc_port_state(). 3578 * 3579 * WARNING!!! ahcictl_mutex should be acquired before the function 3580 * is called. 3581 */ 3582 static void 3583 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3584 { 3585 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3586 3587 ASSERT(ahci_portp != NULL); 3588 3589 mutex_enter(&ahci_portp->ahciport_mutex); 3590 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3591 ahci_portp->ahciport_event_args = NULL; 3592 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3593 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3594 mutex_exit(&ahci_portp->ahciport_mutex); 3595 3596 mutex_destroy(&ahci_portp->ahciport_mutex); 3597 cv_destroy(&ahci_portp->ahciport_cv); 3598 3599 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3600 3601 #ifndef __lock_lint 3602 ahci_ctlp->ahcictl_ports[port] = NULL; 3603 #endif /* __lock_lint */ 3604 } 3605 3606 /* 3607 * Allocates memory for the Received FIS Structure 3608 * 3609 * WARNING!!! ahciport_mutex should be acquired before the function 3610 * is called. 3611 */ 3612 static int 3613 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3614 uint8_t port) 3615 { 3616 size_t rcvd_fis_size; 3617 size_t ret_len; 3618 ddi_dma_cookie_t rcvd_fis_dma_cookie; 3619 uint_t cookie_count; 3620 uint32_t cap_status; 3621 3622 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3623 3624 /* Check whether the HBA can access 64-bit data structures */ 3625 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3626 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3627 3628 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 3629 3630 /* 3631 * If 64-bit addressing is not supported, 3632 * change dma_attr_addr_hi of ahcictl_rcvd_fis_dma_attr 3633 */ 3634 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3635 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3636 "hba does not support 64-bit addressing"); 3637 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 3638 0xffffffffull; 3639 } 3640 3641 /* allocate rcvd FIS dma handle. */ 3642 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3643 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3644 DDI_DMA_SLEEP, 3645 NULL, 3646 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3647 DDI_SUCCESS) { 3648 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3649 "rcvd FIS dma handle alloc failed"); 3650 3651 return (AHCI_FAILURE); 3652 } 3653 3654 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3655 rcvd_fis_size, 3656 &accattr, 3657 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3658 DDI_DMA_SLEEP, 3659 NULL, 3660 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3661 &ret_len, 3662 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3663 3664 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3665 "rcvd FIS dma mem alloc fail"); 3666 /* error.. free the dma handle. */ 3667 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3668 return (AHCI_FAILURE); 3669 } 3670 3671 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3672 NULL, 3673 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3674 rcvd_fis_size, 3675 DDI_DMA_CONSISTENT, 3676 DDI_DMA_SLEEP, 3677 NULL, 3678 &rcvd_fis_dma_cookie, 3679 &cookie_count) != DDI_DMA_MAPPED) { 3680 3681 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3682 "rcvd FIS dma handle bind fail"); 3683 /* error.. free the dma handle & free the memory. */ 3684 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3685 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3686 return (AHCI_FAILURE); 3687 } 3688 3689 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 3690 3691 /* Config Port Received FIS Base Address */ 3692 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3693 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 3694 rcvd_fis_dma_cookie.dmac_laddress); 3695 3696 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3697 rcvd_fis_dma_cookie.dmac_laddress); 3698 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3699 rcvd_fis_dma_cookie.dmac_address); 3700 3701 return (AHCI_SUCCESS); 3702 } 3703 3704 /* 3705 * Deallocates the Received FIS Structure 3706 * 3707 * WARNING!!! ahciport_mutex should be acquired before the function 3708 * is called. 3709 */ 3710 static void 3711 ahci_dealloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3712 { 3713 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3714 "ahci_dealloc_rcvd_fis: port %d enter", 3715 ahci_portp->ahciport_port_num); 3716 3717 /* Unbind the cmd list dma handle first. */ 3718 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 3719 3720 /* Then free the underlying memory. */ 3721 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3722 3723 /* Now free the handle itself. */ 3724 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3725 } 3726 3727 /* 3728 * Allocates memory for the Command List, which contains up to 32 entries. 3729 * Each entry contains a command header, which is a 32-byte structure that 3730 * includes the pointer to the command table. 3731 * 3732 * WARNING!!! ahciport_mutex should be acquired before the function 3733 * is called. 3734 */ 3735 static int 3736 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3737 uint8_t port) 3738 { 3739 size_t cmd_list_size; 3740 size_t ret_len; 3741 ddi_dma_cookie_t cmd_list_dma_cookie; 3742 uint_t cookie_count; 3743 uint32_t cap_status; 3744 3745 cmd_list_size = 3746 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 3747 3748 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3749 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3750 3751 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 3752 3753 /* 3754 * If 64-bit addressing is not supported, 3755 * change dma_attr_addr_hi of ahcictl_cmd_list_dma_attr 3756 */ 3757 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3758 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3759 "hba does not support 64-bit addressing"); 3760 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 3761 0xffffffffull; 3762 } 3763 3764 /* allocate cmd list dma handle. */ 3765 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3766 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 3767 DDI_DMA_SLEEP, 3768 NULL, 3769 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 3770 3771 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3772 "cmd list dma handle alloc failed"); 3773 return (AHCI_FAILURE); 3774 } 3775 3776 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 3777 cmd_list_size, 3778 &accattr, 3779 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3780 DDI_DMA_SLEEP, 3781 NULL, 3782 (caddr_t *)&ahci_portp->ahciport_cmd_list, 3783 &ret_len, 3784 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 3785 3786 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3787 "cmd list dma mem alloc fail"); 3788 /* error.. free the dma handle. */ 3789 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3790 return (AHCI_FAILURE); 3791 } 3792 3793 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 3794 NULL, 3795 (caddr_t)ahci_portp->ahciport_cmd_list, 3796 cmd_list_size, 3797 DDI_DMA_CONSISTENT, 3798 DDI_DMA_SLEEP, 3799 NULL, 3800 &cmd_list_dma_cookie, 3801 &cookie_count) != DDI_DMA_MAPPED) { 3802 3803 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3804 "cmd list dma handle bind fail"); 3805 /* error.. free the dma handle & free the memory. */ 3806 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 3807 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3808 return (AHCI_FAILURE); 3809 } 3810 3811 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 3812 3813 /* Config Port Command List Base Address */ 3814 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3815 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 3816 cmd_list_dma_cookie.dmac_laddress); 3817 3818 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3819 cmd_list_dma_cookie.dmac_laddress); 3820 3821 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3822 cmd_list_dma_cookie.dmac_address); 3823 3824 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 3825 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3826 return (AHCI_FAILURE); 3827 } 3828 3829 return (AHCI_SUCCESS); 3830 } 3831 3832 /* 3833 * Deallocates the Command List 3834 * 3835 * WARNING!!! ahciport_mutex should be acquired before the function 3836 * is called. 3837 */ 3838 static void 3839 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3840 { 3841 /* First dealloc command table */ 3842 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 3843 3844 /* Unbind the cmd list dma handle first. */ 3845 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 3846 3847 /* Then free the underlying memory. */ 3848 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 3849 3850 /* Now free the handle itself. */ 3851 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3852 } 3853 3854 /* 3855 * Allocates memory for all Command Tables, which contains Command FIS, 3856 * ATAPI Command and Physical Region Descriptor Table. 3857 * 3858 * WARNING!!! ahciport_mutex should be acquired before the function 3859 * is called. 3860 */ 3861 static int 3862 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3863 { 3864 size_t ret_len; 3865 ddi_dma_cookie_t cmd_table_dma_cookie; 3866 uint_t cookie_count; 3867 uint32_t cap_status; 3868 int slot; 3869 3870 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3871 "ahci_alloc_cmd_tables: port %d enter", 3872 ahci_portp->ahciport_port_num); 3873 3874 /* Check whether the HBA can access 64-bit data structures */ 3875 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3876 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3877 3878 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 3879 3880 /* 3881 * If 64-bit addressing is not supported, 3882 * change dma_attr_addr_hi of ahcictl_cmd_table_dma_attr 3883 */ 3884 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3885 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3886 "hba does not support 64-bit addressing"); 3887 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 3888 0xffffffffull; 3889 } 3890 3891 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 3892 /* Allocate cmd table dma handle. */ 3893 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3894 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 3895 DDI_DMA_SLEEP, 3896 NULL, 3897 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 3898 DDI_SUCCESS) { 3899 3900 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3901 "cmd table dma handle alloc failed"); 3902 3903 goto err_out; 3904 } 3905 3906 if (ddi_dma_mem_alloc( 3907 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3908 ahci_cmd_table_size, 3909 &accattr, 3910 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3911 DDI_DMA_SLEEP, 3912 NULL, 3913 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 3914 &ret_len, 3915 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 3916 NULL) { 3917 3918 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3919 "cmd table dma mem alloc fail"); 3920 3921 /* error.. free the dma handle. */ 3922 ddi_dma_free_handle( 3923 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3924 goto err_out; 3925 } 3926 3927 if (ddi_dma_addr_bind_handle( 3928 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3929 NULL, 3930 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 3931 ahci_cmd_table_size, 3932 DDI_DMA_CONSISTENT, 3933 DDI_DMA_SLEEP, 3934 NULL, 3935 &cmd_table_dma_cookie, 3936 &cookie_count) != DDI_DMA_MAPPED) { 3937 3938 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3939 "cmd table dma handle bind fail"); 3940 /* error.. free the dma handle & free the memory. */ 3941 ddi_dma_mem_free( 3942 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3943 ddi_dma_free_handle( 3944 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3945 goto err_out; 3946 } 3947 3948 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 3949 ahci_cmd_table_size); 3950 3951 /* Config Port Command Table Base Address */ 3952 SET_COMMAND_TABLE_BASE_ADDR( 3953 (&ahci_portp->ahciport_cmd_list[slot]), 3954 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 3955 3956 #ifndef __lock_lint 3957 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 3958 (&ahci_portp->ahciport_cmd_list[slot]), 3959 cmd_table_dma_cookie.dmac_laddress >> 32); 3960 #endif /* __lock_lint */ 3961 } 3962 3963 return (AHCI_SUCCESS); 3964 err_out: 3965 3966 for (slot--; slot >= 0; slot--) { 3967 /* Unbind the cmd table dma handle first */ 3968 (void) ddi_dma_unbind_handle( 3969 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3970 3971 /* Then free the underlying memory */ 3972 ddi_dma_mem_free( 3973 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3974 3975 /* Now free the handle itself */ 3976 ddi_dma_free_handle( 3977 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3978 } 3979 3980 return (AHCI_FAILURE); 3981 } 3982 3983 /* 3984 * Deallocates memory for all Command Tables. 3985 * 3986 * WARNING!!! ahciport_mutex should be acquired before the function 3987 * is called. 3988 */ 3989 static void 3990 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3991 { 3992 int slot; 3993 3994 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3995 "ahci_dealloc_cmd_tables: %d enter", 3996 ahci_portp->ahciport_port_num); 3997 3998 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 3999 /* Unbind the cmd table dma handle first. */ 4000 (void) ddi_dma_unbind_handle( 4001 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4002 4003 /* Then free the underlying memory. */ 4004 ddi_dma_mem_free( 4005 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4006 4007 /* Now free the handle itself. */ 4008 ddi_dma_free_handle( 4009 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4010 } 4011 } 4012 4013 /* 4014 * WARNING!!! ahciport_mutex should be acquired before the function 4015 * is called. 4016 */ 4017 static void 4018 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4019 sata_device_t *sd) 4020 { 4021 sd->satadev_scr.sstatus = 4022 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4023 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4024 sd->satadev_scr.serror = 4025 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4026 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4027 sd->satadev_scr.scontrol = 4028 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4029 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4030 sd->satadev_scr.sactive = 4031 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4032 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4033 } 4034 4035 /* 4036 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4037 */ 4038 static void 4039 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4040 { 4041 uint32_t port_intr_status; 4042 uint32_t port_intr_enable; 4043 4044 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4045 "ahci_port_intr enter: port %d", port); 4046 4047 mutex_enter(&ahci_portp->ahciport_mutex); 4048 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4049 /* For SATA_OPMODE_POLLING commands */ 4050 port_intr_enable = 4051 (AHCI_INTR_STATUS_DHRS | 4052 AHCI_INTR_STATUS_PSS | 4053 AHCI_INTR_STATUS_SDBS | 4054 AHCI_INTR_STATUS_UFS | 4055 AHCI_INTR_STATUS_PCS | 4056 AHCI_INTR_STATUS_PRCS | 4057 AHCI_INTR_STATUS_OFS | 4058 AHCI_INTR_STATUS_INFS | 4059 AHCI_INTR_STATUS_IFS | 4060 AHCI_INTR_STATUS_HBDS | 4061 AHCI_INTR_STATUS_HBFS | 4062 AHCI_INTR_STATUS_TFES); 4063 mutex_exit(&ahci_portp->ahciport_mutex); 4064 goto next; 4065 } 4066 mutex_exit(&ahci_portp->ahciport_mutex); 4067 4068 /* 4069 * port_intr_enable indicates that the corresponding interrrupt 4070 * reporting is enabled. 4071 */ 4072 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4073 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4074 next: 4075 /* 4076 * port_intr_stats indicates that the corresponding interrupt 4077 * condition is active. 4078 */ 4079 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4080 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4081 4082 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4083 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4084 "port_intr_enable = 0x%x", 4085 port, port_intr_status, port_intr_enable); 4086 4087 port_intr_status &= port_intr_enable; 4088 4089 /* First clear the port interrupts status */ 4090 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4091 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4092 port_intr_status); 4093 4094 /* Check the completed non-queued commands */ 4095 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4096 AHCI_INTR_STATUS_PSS)) { 4097 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4098 ahci_portp, port, port_intr_status); 4099 } 4100 4101 /* Check the completed queued commands */ 4102 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4103 (void) ahci_intr_set_device_bits(ahci_ctlp, 4104 ahci_portp, port); 4105 } 4106 4107 /* Check the port connect change status interrupt bit */ 4108 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4109 (void) ahci_intr_port_connect_change(ahci_ctlp, 4110 ahci_portp, port); 4111 } 4112 4113 /* Check the device mechanical presence status interrupt bit */ 4114 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4115 (void) ahci_intr_device_mechanical_presence_status( 4116 ahci_ctlp, ahci_portp, port); 4117 } 4118 4119 /* Check the PhyRdy change status interrupt bit */ 4120 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4121 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4122 port); 4123 } 4124 4125 /* 4126 * Check the non-fatal error interrupt bits, there are three 4127 * kinds of non-fatal errors at the time being: 4128 * 4129 * PxIS.UFS - Unknown FIS Error 4130 * PxIS.OFS - Overflow Error 4131 * PxIS.INFS - Interface Non-Fatal Error 4132 * 4133 * For these non-fatal errors, the HBA can continue to operate, 4134 * so the driver just log the error messages. 4135 */ 4136 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4137 AHCI_INTR_STATUS_OFS | 4138 AHCI_INTR_STATUS_INFS)) { 4139 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4140 port, port_intr_status); 4141 } 4142 4143 /* 4144 * Check the fatal error interrupt bits, there are four kinds 4145 * of fatal errors for AHCI controllers: 4146 * 4147 * PxIS.HBFS - Host Bus Fatal Error 4148 * PxIS.HBDS - Host Bus Data Error 4149 * PxIS.IFS - Interface Fatal Error 4150 * PxIS.TFES - Task File Error 4151 * 4152 * The fatal error means the HBA can not recover from it by 4153 * itself, and it will try to abort the transfer, and the software 4154 * must intervene to restart the port. 4155 */ 4156 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4157 AHCI_INTR_STATUS_HBDS | 4158 AHCI_INTR_STATUS_HBFS | 4159 AHCI_INTR_STATUS_TFES)) 4160 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4161 port, port_intr_status); 4162 4163 /* Check the cold port detect interrupt bit */ 4164 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4165 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4166 } 4167 4168 /* Second clear the corresponding bit in IS.IPS */ 4169 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4170 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4171 } 4172 4173 /* 4174 * Interrupt service handler 4175 */ 4176 /* ARGSUSED1 */ 4177 static uint_t 4178 ahci_intr(caddr_t arg1, caddr_t arg2) 4179 { 4180 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4181 ahci_port_t *ahci_portp; 4182 int32_t global_intr_status; 4183 uint8_t port; 4184 4185 /* 4186 * global_intr_status indicates that the corresponding port has 4187 * an interrupt pending. 4188 */ 4189 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4190 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4191 4192 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4193 /* The interrupt is not ours */ 4194 return (DDI_INTR_UNCLAIMED); 4195 } 4196 4197 /* Loop for all the ports */ 4198 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4199 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4200 continue; 4201 } 4202 if (!((0x1 << port) & global_intr_status)) { 4203 continue; 4204 } 4205 4206 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4207 4208 /* Call ahci_port_intr */ 4209 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4210 } 4211 4212 return (DDI_INTR_CLAIMED); 4213 } 4214 4215 /* 4216 * For non-queued commands, when the corresponding bit in the PxCI register 4217 * is cleared, it means the command is completed successfully. And according 4218 * to the HBA state machine, there are three conditions which possibly will 4219 * try to clear the PxCI register bit. 4220 * 1. Receive one D2H Register FIS which is with 'I' bit set 4221 * 2. Update PIO Setup FIS 4222 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4223 * 4224 * Process completed non-queued commands when the interrupt status bit - 4225 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4226 * 4227 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4228 * with the 'I' bit set. And the following commands will send thus 4229 * FIS with 'I' bit set upon the successful completion: 4230 * 1. Non-data commands 4231 * 2. DMA data-in command 4232 * 3. DMA data-out command 4233 * 4. PIO data-out command 4234 * 5. PACKET non-data commands 4235 * 6. PACKET PIO data-in command 4236 * 7. PACKET PIO data-out command 4237 * 8. PACKET DMA data-in command 4238 * 9. PACKET DMA data-out command 4239 * 4240 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4241 * with the 'I' bit set. And the following commands will send this 4242 * FIS upon the successful completion: 4243 * 1. PIO data-in command 4244 */ 4245 static int 4246 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4247 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 4248 { 4249 uint32_t port_cmd_issue = 0; 4250 uint32_t finished_tags; 4251 int finished_slot; 4252 sata_pkt_t *satapkt; 4253 ahci_fis_d2h_register_t *rcvd_fisp; 4254 4255 if (intr_status & AHCI_INTR_STATUS_DHRS) 4256 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4257 "ahci_intr_cmd_cmplt enter: port %d " 4258 "a d2h register fis is received", port); 4259 4260 if (intr_status & AHCI_INTR_STATUS_PSS) 4261 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4262 "ahci_intr_cmd_cmplt enter: port %d " 4263 "a pio setup fis is received", port); 4264 4265 mutex_enter(&ahci_portp->ahciport_mutex); 4266 4267 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4268 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4269 /* 4270 * Spurious interrupt. Nothing to be done. 4271 */ 4272 mutex_exit(&ahci_portp->ahciport_mutex); 4273 return (AHCI_SUCCESS); 4274 } 4275 4276 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4277 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4278 4279 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4280 /* Slot 0 is always used during error recovery */ 4281 finished_tags = 0x1 & ~port_cmd_issue; 4282 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4283 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4284 "retrieval is finished, and finished_tags = 0x%x", 4285 port, finished_tags); 4286 } else { 4287 finished_tags = ahci_portp->ahciport_pending_tags & 4288 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4289 } 4290 4291 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4292 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4293 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4294 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4295 finished_tags); 4296 4297 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4298 (finished_tags == 0x1)) { 4299 satapkt = ahci_portp->ahciport_err_retri_pkt; 4300 ASSERT(satapkt != NULL); 4301 4302 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4303 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4304 "with SATA_PKT_COMPLETED", (void *)satapkt); 4305 4306 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4307 goto out; 4308 } 4309 4310 while (finished_tags) { 4311 finished_slot = ddi_ffs(finished_tags) - 1; 4312 if (finished_slot == -1) { 4313 goto out; 4314 } 4315 4316 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4317 ASSERT(satapkt != NULL); 4318 4319 /* 4320 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4321 * feature, sata_special_regs flag will be set, and the 4322 * driver should copy the status and the other corresponding 4323 * register values in the D2H Register FIS received (It's 4324 * working on Non-data protocol) from the device back to 4325 * the sata_cmd. 4326 * 4327 * For every AHCI port, there is only one Received FIS 4328 * structure, which contains the FISes received from the 4329 * device, So we're trying to copy the content of D2H 4330 * Register FIS in the Received FIS structure back to 4331 * the sata_cmd. 4332 */ 4333 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4334 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4335 ahcirf_d2h_register_fis); 4336 satapkt->satapkt_cmd.satacmd_status_reg = 4337 GET_RFIS_STATUS(rcvd_fisp); 4338 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4339 } 4340 4341 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4342 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4343 "with SATA_PKT_COMPLETED", (void *)satapkt); 4344 4345 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4346 CLEAR_BIT(finished_tags, finished_slot); 4347 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4348 4349 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4350 } 4351 out: 4352 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4353 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4354 ahci_portp->ahciport_pending_tags); 4355 4356 mutex_exit(&ahci_portp->ahciport_mutex); 4357 4358 return (AHCI_SUCCESS); 4359 } 4360 4361 /* 4362 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4363 * with the 'I' bit set and has been copied into system memory. It will 4364 * be sent under the following situations: 4365 * 4366 * 1. NCQ command is completed 4367 * 2. Asynchronous notification 4368 * 4369 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4370 * via the Set Device Bits FIS. When such event is generated, the software 4371 * needs to read PxSACT register and compares the current value to the 4372 * list of commands previously issue by software. ahciport_pending_ncq_tags 4373 * keeps the tags of previously issued commands. 4374 * 4375 * Asynchronous Notification is a feature in SATA II, which allows an 4376 * ATAPI device to send a signal to the host when media is inserted or 4377 * removed and avoids polling the device for media changes. The signal 4378 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4379 * set to '1'. At the moment, it's not supported yet. 4380 */ 4381 static int 4382 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4383 ahci_port_t *ahci_portp, uint8_t port) 4384 { 4385 uint32_t port_sactive; 4386 uint32_t port_cmd_issue; 4387 uint32_t issued_tags; 4388 int issued_slot; 4389 uint32_t finished_tags; 4390 int finished_slot; 4391 sata_pkt_t *satapkt; 4392 4393 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4394 "ahci_intr_set_device_bits enter: port %d", port); 4395 4396 mutex_enter(&ahci_portp->ahciport_mutex); 4397 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4398 mutex_exit(&ahci_portp->ahciport_mutex); 4399 return (AHCI_SUCCESS); 4400 } 4401 4402 /* 4403 * First the handler got which commands are finished by checking 4404 * PxSACT register 4405 */ 4406 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4407 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4408 4409 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4410 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4411 4412 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4413 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4414 "port_sactive = 0x%x", port, 4415 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4416 4417 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4418 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4419 4420 /* 4421 * For NCQ commands, the software can determine which command has 4422 * already been transmitted to the device by checking PxCI register. 4423 */ 4424 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4425 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4426 4427 issued_tags = ahci_portp->ahciport_pending_tags & 4428 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4429 4430 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4431 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4432 "port_cmd_issue = 0x%x", port, 4433 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4434 4435 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4436 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4437 4438 /* 4439 * Clear ahciport_pending_tags bit when the corresponding command 4440 * is already sent down to the device. 4441 */ 4442 while (issued_tags) { 4443 issued_slot = ddi_ffs(issued_tags) - 1; 4444 if (issued_slot == -1) { 4445 goto next; 4446 } 4447 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4448 CLEAR_BIT(issued_tags, issued_slot); 4449 } 4450 4451 next: 4452 while (finished_tags) { 4453 finished_slot = ddi_ffs(finished_tags) - 1; 4454 if (finished_slot == -1) { 4455 goto out; 4456 } 4457 4458 /* The command is certainly transmitted to the device */ 4459 ASSERT(!(ahci_portp->ahciport_pending_tags & 4460 (0x1 << finished_slot))); 4461 4462 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4463 ASSERT(satapkt != NULL); 4464 4465 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4466 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4467 "with SATA_PKT_COMPLETED", (void *)satapkt); 4468 4469 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4470 CLEAR_BIT(finished_tags, finished_slot); 4471 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4472 4473 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4474 } 4475 out: 4476 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4477 "ahci_intr_set_device_bits: port %d " 4478 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4479 port, ahci_portp->ahciport_pending_ncq_tags, 4480 ahci_portp->ahciport_pending_tags); 4481 4482 mutex_exit(&ahci_portp->ahciport_mutex); 4483 4484 return (AHCI_SUCCESS); 4485 } 4486 4487 /* 4488 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4489 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4490 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4491 * indicates a COMINIT signal was received. 4492 * 4493 * Hot plug insertion is detected by reception of a COMINIT signal from the 4494 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4495 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4496 * begin the normal communication negotiation sequence as outlined in the 4497 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4498 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4499 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4500 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4501 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4502 * to handle hot plug insertion. In this interrupt handler, just do nothing 4503 * but print some log message and clear the bit. 4504 */ 4505 static int 4506 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4507 ahci_port_t *ahci_portp, uint8_t port) 4508 { 4509 uint32_t port_serror; 4510 4511 mutex_enter(&ahci_portp->ahciport_mutex); 4512 4513 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4514 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4515 4516 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4517 "ahci_intr_port_connect_change: port %d, " 4518 "port_serror = 0x%x", port, port_serror); 4519 4520 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4521 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4522 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4523 SERROR_EXCHANGED_ERR); 4524 4525 mutex_exit(&ahci_portp->ahciport_mutex); 4526 4527 return (AHCI_SUCCESS); 4528 } 4529 4530 /* 4531 * Hot Plug Operation for platforms that support Mechanical Presence 4532 * Switches. 4533 * 4534 * When set, it indicates that a mechanical presence switch attached to this 4535 * port has been opened or closed, which may lead to a change in the connection 4536 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4537 * are set to '1'. 4538 * 4539 * At the moment, this interrupt is not needed and disabled and we just log 4540 * the debug message. 4541 */ 4542 /* ARGSUSED */ 4543 static int 4544 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4545 ahci_port_t *ahci_portp, uint8_t port) 4546 { 4547 uint32_t cap_status, port_cmd_status; 4548 4549 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4550 "ahci_intr_device_mechanical_presence_status enter, " 4551 "port %d", port); 4552 4553 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4554 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4555 4556 mutex_enter(&ahci_portp->ahciport_mutex); 4557 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4558 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4559 4560 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4561 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4562 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4563 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4564 "the interrupt: cap_status = 0x%x, " 4565 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4566 mutex_exit(&ahci_portp->ahciport_mutex); 4567 4568 return (AHCI_SUCCESS); 4569 } 4570 4571 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4572 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4573 "The mechanical presence switch is open: " 4574 "port %d, port_cmd_status = 0x%x", 4575 port, port_cmd_status); 4576 } else { 4577 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4578 "The mechanical presence switch is close: " 4579 "port %d, port_cmd_status = 0x%x", 4580 port, port_cmd_status); 4581 } 4582 4583 mutex_exit(&ahci_portp->ahciport_mutex); 4584 4585 return (AHCI_SUCCESS); 4586 } 4587 4588 /* 4589 * Native Hot Plug Support. 4590 * 4591 * When set, it indicates that the internal PHYRDY signal changed state. 4592 * This bit reflects the state of PxSERR.DIAG.N. 4593 * 4594 * There are three kinds of conditions to generate this interrupt event: 4595 * 1. a device is inserted 4596 * 2. a device is disconnected 4597 * 3. when the link enters/exits a Partial or Slumber interface power 4598 * management state 4599 * 4600 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4601 * bit may be set due to the link entering the Partial or Slumber power 4602 * management state, rather than due to a hot plug insertion or removal 4603 * event. So far, the power management is disabled, so the driver can 4604 * reliably get removal detection notification via the PxSERR.DIAG.N bit. 4605 */ 4606 static int 4607 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4608 ahci_port_t *ahci_portp, uint8_t port) 4609 { 4610 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4611 sata_device_t sdevice; 4612 int dev_exists_now = 0; 4613 int dev_existed_previously = 0; 4614 4615 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4616 "ahci_intr_phyrdy_change enter, port %d", port); 4617 4618 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4619 mutex_enter(&ahci_portp->ahciport_mutex); 4620 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4621 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4622 SERROR_PHY_RDY_CHG); 4623 mutex_exit(&ahci_portp->ahciport_mutex); 4624 4625 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4626 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4627 (ahci_portp == NULL)) { 4628 /* The whole controller setup is not yet done. */ 4629 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4630 return (AHCI_SUCCESS); 4631 } 4632 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4633 4634 mutex_enter(&ahci_portp->ahciport_mutex); 4635 4636 /* SStatus tells the presence of device. */ 4637 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4638 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4639 4640 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 4641 dev_exists_now = 1; 4642 } 4643 4644 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4645 dev_existed_previously = 1; 4646 } 4647 4648 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 4649 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 4650 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4651 "ahci_intr_phyrdy_change: port %d " 4652 "AHCI_PORT_FLAG_NODEV is cleared", port); 4653 if (dev_exists_now == 0) 4654 dev_existed_previously = 1; 4655 } 4656 4657 bzero((void *)&sdevice, sizeof (sata_device_t)); 4658 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4659 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4660 sdevice.satadev_addr.pmport = 0; 4661 sdevice.satadev_state = SATA_PSTATE_PWRON; 4662 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4663 4664 if (dev_exists_now) { 4665 if (dev_existed_previously) { 4666 /* Things are fine now. The loss was temporary. */ 4667 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4668 "ahci_intr_phyrdy_change port %d " 4669 "device link lost/established", port); 4670 4671 mutex_exit(&ahci_portp->ahciport_mutex); 4672 sata_hba_event_notify( 4673 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4674 &sdevice, 4675 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4676 mutex_enter(&ahci_portp->ahciport_mutex); 4677 4678 } else { 4679 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4680 "ahci_intr_phyrdy_change: port %d " 4681 "device link established", port); 4682 4683 /* A new device has been detected. */ 4684 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 4685 4686 /* Try to start the port */ 4687 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4688 != AHCI_SUCCESS) { 4689 sdevice.satadev_state |= SATA_PSTATE_FAILED; 4690 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4691 "ahci_intr_phyrdy_change: port %d failed " 4692 "at start port", port); 4693 } 4694 4695 /* Clear the max queue depth for inserted device */ 4696 ahci_portp->ahciport_max_ncq_tags = 0; 4697 4698 mutex_exit(&ahci_portp->ahciport_mutex); 4699 sata_hba_event_notify( 4700 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4701 &sdevice, 4702 SATA_EVNT_LINK_ESTABLISHED); 4703 mutex_enter(&ahci_portp->ahciport_mutex); 4704 4705 } 4706 } else { /* No device exists now */ 4707 4708 if (dev_existed_previously) { 4709 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4710 "ahci_intr_phyrdy_change: port %d " 4711 "device link lost", port); 4712 4713 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 4714 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 4715 ahci_portp, port); 4716 4717 /* An existing device is lost. */ 4718 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 4719 4720 mutex_exit(&ahci_portp->ahciport_mutex); 4721 sata_hba_event_notify( 4722 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4723 &sdevice, 4724 SATA_EVNT_LINK_LOST); 4725 mutex_enter(&ahci_portp->ahciport_mutex); 4726 4727 } else { 4728 4729 /* Spurious interrupt */ 4730 AHCIDBG0(AHCIDBG_INTR, ahci_ctlp, 4731 "ahci_intr_phyrdy_change: " 4732 "spurious phy ready interrupt"); 4733 } 4734 } 4735 4736 mutex_exit(&ahci_portp->ahciport_mutex); 4737 4738 return (AHCI_SUCCESS); 4739 } 4740 4741 /* 4742 * PxIS.UFS - Unknown FIS Error 4743 * 4744 * This interrupt event means an unknown FIS was received and has been 4745 * copied into system memory. An unknown FIS is not considered an illegal 4746 * FIS, unless the length received is more than 64 bytes. If an unknown 4747 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 4748 * normal operation. If the unknown FIS is more than 64 bytes, then it 4749 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 4750 * a fatal error. 4751 * 4752 * PxIS.OFS - Overflow Error 4753 * 4754 * Command list overflow is defined as software building a command table 4755 * that has fewer total bytes than the transaction given to the device. 4756 * On device writes, the HBA will run out of data, and on reads, there 4757 * will be no room to put the data. 4758 * 4759 * For an overflow on data read, either PIO or DMA, the HBA will set 4760 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 4761 * non-fatal error when the HBA can continues. Sometimes, it will cause 4762 * a fatal error and need the software to do something. 4763 * 4764 * For an overflow on data write, setting PxIS.OFS is optional for both 4765 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 4766 * software to clean up from this serious error. 4767 * 4768 * PxIS.INFS - Interface Non-Fatal Error 4769 * 4770 * This interrupt event indicates that the HBA encountered an error on 4771 * the Serial ATA interface but was able to continue operation. The kind 4772 * of error usually occurred during a non-Data FIS, and under this condition 4773 * the FIS will be re-transmitted by HBA automatically. 4774 * 4775 * When the FMA is implemented, there should be a stat structure to 4776 * record how many every kind of error happens. 4777 */ 4778 static int 4779 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4780 uint8_t port, uint32_t intr_status) 4781 { 4782 uint32_t port_serror; 4783 #if AHCI_DEBUG 4784 uint32_t port_cmd_status; 4785 uint32_t port_cmd_issue; 4786 uint32_t port_sactive; 4787 int current_slot; 4788 uint32_t current_tags; 4789 sata_pkt_t *satapkt; 4790 #endif 4791 4792 mutex_enter(&ahci_portp->ahciport_mutex); 4793 4794 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4795 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4796 4797 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 4798 "ahci_intr_non_fatal_error: port %d, " 4799 "port_serror = 0x%x", port, port_serror); 4800 4801 ahci_log_serror_message(ahci_ctlp, port, port_serror); 4802 4803 if (intr_status & AHCI_INTR_STATUS_UFS) { 4804 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4805 "ahci port %d has unknown FIS error", port); 4806 4807 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 4808 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4809 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4810 SERROR_FIS_TYPE); 4811 } 4812 4813 #if AHCI_DEBUG 4814 if (intr_status & AHCI_INTR_STATUS_OFS) { 4815 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4816 "ahci port %d has overflow error", port); 4817 } 4818 4819 if (intr_status & AHCI_INTR_STATUS_INFS) { 4820 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4821 "ahci port %d has interface non fatal error", port); 4822 } 4823 4824 /* 4825 * Record the error occurred command's slot. 4826 */ 4827 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 4828 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4829 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4830 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4831 4832 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 4833 AHCI_CMD_STATUS_CCS_SHIFT; 4834 4835 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4836 satapkt = ahci_portp->ahciport_err_retri_pkt; 4837 ASSERT(satapkt != NULL); 4838 ASSERT(current_slot == 0); 4839 } else { 4840 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 4841 } 4842 4843 if (satapkt != NULL) { 4844 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4845 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 4846 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 4847 satapkt->satapkt_cmd.satacmd_cmd_reg); 4848 4849 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4850 "ahci_intr_non_fatal_error: port %d, " 4851 "satapkt 0x%p is being processed when error occurs", 4852 port, (void *)satapkt); 4853 } 4854 } 4855 4856 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4857 /* 4858 * For queued command, list those command which have already 4859 * been transmitted to the device and still not completed. 4860 */ 4861 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4862 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4863 4864 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4865 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4866 4867 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 4868 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 4869 "port_sactive = 0x%x port_cmd_issue = 0x%x", 4870 ahci_portp->ahciport_pending_ncq_tags, 4871 port_sactive, port_cmd_issue); 4872 4873 current_tags = ahci_portp->ahciport_pending_ncq_tags & 4874 port_sactive & ~port_cmd_issue & 4875 AHCI_NCQ_SLOT_MASK(ahci_portp); 4876 4877 while (current_tags) { 4878 current_slot = ddi_ffs(current_tags) - 1; 4879 if (current_slot == -1) { 4880 goto out; 4881 } 4882 4883 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 4884 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 4885 ahci_ctlp, "ahci_intr_non_fatal_error: " 4886 "port %d, satapkt 0x%p is outstanding when " 4887 "error occurs", port, (void *)satapkt); 4888 } 4889 } 4890 out: 4891 #endif 4892 mutex_exit(&ahci_portp->ahciport_mutex); 4893 4894 return (AHCI_SUCCESS); 4895 } 4896 4897 /* 4898 * According to the AHCI spec, the error types include system memory 4899 * errors, interface errors, port multiplier errors, device errors, 4900 * command list overflow, command list underflow, native command 4901 * queuing tag errors and pio data transfer errors. 4902 * 4903 * System memory errors such as target abort, master abort, and parity 4904 * may cause the host to stop, and they are serious errors and needed 4905 * to be recovered with software intervention. When system software 4906 * has given a pointer to the HBA that doesn't exist in physical memory, 4907 * a master/target abort error occurs, and PxIS.HBFS will be set. A 4908 * data error such as CRC or parity occurs, the HBA aborts the transfer 4909 * (if necessary) and PxIS.HBDS will be set. 4910 * 4911 * Interface errors are errors that occur due to electrical issues on 4912 * the interface, or protocol miscommunication between the device and 4913 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 4914 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 4915 * causes PxIS.IFS/PxIS.INFS to be set are 4916 * 1. in PxSERR.ERR, P bit is set to '1' 4917 * 2. in PxSERR.DIAG, C or H bit is set to '1' 4918 * 3. PhyRdy drop unexpectly, N bit is set to '1' 4919 * If the error occurred during a non-data FIS, the FIS must be 4920 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 4921 * the error occurred during a data FIS, the transfer will stop, so 4922 * the error is fatal and PxIS.IFS is set. 4923 * 4924 * When a FIS arrives that updates the taskfile, the HBA checks to see 4925 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 4926 * stops processing any more commands. 4927 * 4928 * Command list overflow is defined as software building a command table 4929 * that has fewer total bytes than the transaction given to the device. 4930 * On device writes, the HBA will run out of data, and on reads, there 4931 * will be no room to put the data. For an overflow on data read, either 4932 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 4933 * For an overflow on data write, setting PxIS.OFS is optional for both 4934 * DMA and PIO, and a COMRESET is required by software to clean up from 4935 * this serious error. 4936 * 4937 * Command list underflow is defined as software building a command 4938 * table that has more total bytes than the transaction given to the 4939 * device. For data writes, both PIO and DMA, the device will detect 4940 * an error and end the transfer. And these errors are most likely going 4941 * to be fatal errors that will cause the port to be restarted. For 4942 * data reads, the HBA updates its PRD byte count, and may be 4943 * able to continue normally, but is not required to. And The HBA is 4944 * not required to detect underflow conditions for native command 4945 * queuing command. 4946 * 4947 * The HBA does not actively check incoming DMA Setup FISes to ensure 4948 * that the PxSACT register bit for that slot is set. Existing error 4949 * mechanisms, such as host bus failure, or bad protocol, are used to 4950 * recover from this case. 4951 * 4952 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 4953 * DATA FIS must be an integral number of Dwords. If the HBA receives 4954 * a request which is not an integral number of Dwords, the HBA 4955 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 4956 * software restarts the port. And the HBA ensures that the size 4957 * of the DATA FIS received during a PIO command matches the size in 4958 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 4959 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 4960 * stop running until software restarts the port. 4961 */ 4962 /* 4963 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 4964 * 4965 * PxIS.IFS indicates that the hba encountered an error on the serial ata 4966 * interface which caused the transfer to stop. 4967 * 4968 * PxIS.HBDS indicates that the hba encountered a data error 4969 * (uncorrectable ecc/parity) when reading from or writing to system memory. 4970 * 4971 * PxIS.HBFS indicates that the hba encountered a host bus error that it 4972 * cannot recover from, such as a bad software pointer. 4973 * 4974 * PxIS.TFES is set whenever the status register is updated by the device 4975 * and the error bit (bit 0) is set. 4976 */ 4977 static int 4978 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 4979 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 4980 { 4981 uint32_t port_cmd_status; 4982 uint32_t port_serror; 4983 uint32_t task_file_status; 4984 int failed_slot; 4985 sata_pkt_t *spkt = NULL; 4986 uint8_t err_byte; 4987 ahci_event_arg_t *args; 4988 4989 mutex_enter(&ahci_portp->ahciport_mutex); 4990 4991 /* 4992 * ahci_intr_phyrdy_change() may have rendered it to 4993 * SATA_DTYPE_NONE. 4994 */ 4995 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 4996 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 4997 "ahci_intr_fatal_error: port %d no device attached, " 4998 "and just return without doing anything", port); 4999 goto out0; 5000 } 5001 5002 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5003 /* 5004 * Read PxCMD.CCS to determine the slot that the HBA 5005 * was processing when the error occurred. 5006 */ 5007 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5008 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5009 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5010 AHCI_CMD_STATUS_CCS_SHIFT; 5011 5012 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5013 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5014 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5015 "fatal error occurred for port %d", spkt, port); 5016 5017 if (intr_status & AHCI_INTR_STATUS_TFES) { 5018 task_file_status = ddi_get32( 5019 ahci_ctlp->ahcictl_ahci_acc_handle, 5020 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5021 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5022 "ahci_intr_fatal_error: port %d " 5023 "task_file_status = 0x%x", port, task_file_status); 5024 5025 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5026 >> AHCI_TFD_ERR_SHIFT; 5027 5028 /* 5029 * Won't emit the error message if it is an IDENTIFY 5030 * DEVICE command sent to an ATAPI device. 5031 */ 5032 if ((spkt != NULL) && 5033 (spkt->satapkt_cmd.satacmd_cmd_reg == 5034 SATAC_ID_DEVICE) && 5035 (err_byte == SATA_ERROR_ABORT)) 5036 goto out1; 5037 5038 /* 5039 * Won't emit the error message if it is an ATAPI PACKET 5040 * command 5041 */ 5042 if ((spkt != NULL) && 5043 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5044 goto out1; 5045 } 5046 } 5047 5048 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5049 5050 out1: 5051 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5052 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5053 ahci_log_serror_message(ahci_ctlp, port, port_serror); 5054 5055 /* Prepare the argument for the taskq */ 5056 args = ahci_portp->ahciport_event_args; 5057 args->ahciea_ctlp = (void *)ahci_ctlp; 5058 args->ahciea_portp = (void *)ahci_portp; 5059 args->ahciea_event = intr_status; 5060 5061 /* Start the taskq to handle error recovery */ 5062 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 5063 ahci_events_handler, 5064 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5065 cmn_err(CE_WARN, "ahci start taskq for event handler failed"); 5066 } 5067 out0: 5068 mutex_exit(&ahci_portp->ahciport_mutex); 5069 5070 return (AHCI_SUCCESS); 5071 } 5072 5073 /* 5074 * Hot Plug Operation for platforms that support Cold Presence Detect. 5075 * 5076 * When set, a device status has changed as detected by the cold presence 5077 * detect logic. This bit can either be set due to a non-connected port 5078 * receiving a device, or a connected port having its device removed. 5079 * This bit is only valid if the port supports cold presence detect as 5080 * indicated by PxCMD.CPD set to '1'. 5081 * 5082 * At the moment, this interrupt is not needed and disabled and we just 5083 * log the debug message. 5084 */ 5085 /* ARGSUSED */ 5086 static int 5087 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5088 ahci_port_t *ahci_portp, uint8_t port) 5089 { 5090 uint32_t port_cmd_status; 5091 sata_device_t sdevice; 5092 5093 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5094 "ahci_intr_cold_port_detect enter, port %d", port); 5095 5096 mutex_enter(&ahci_portp->ahciport_mutex); 5097 5098 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5099 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5100 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5101 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5102 "port %d does not support cold presence detect, so " 5103 "we just ignore this interrupt", port); 5104 mutex_exit(&ahci_portp->ahciport_mutex); 5105 return (AHCI_SUCCESS); 5106 } 5107 5108 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5109 "port %d device status has changed", port); 5110 5111 bzero((void *)&sdevice, sizeof (sata_device_t)); 5112 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5113 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5114 sdevice.satadev_addr.pmport = 0; 5115 sdevice.satadev_state = SATA_PSTATE_PWRON; 5116 5117 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5118 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5119 "port %d: a device is hot plugged", port); 5120 mutex_exit(&ahci_portp->ahciport_mutex); 5121 sata_hba_event_notify( 5122 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5123 &sdevice, 5124 SATA_EVNT_DEVICE_ATTACHED); 5125 mutex_enter(&ahci_portp->ahciport_mutex); 5126 5127 } else { 5128 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5129 "port %d: a device is hot unplugged", port); 5130 mutex_exit(&ahci_portp->ahciport_mutex); 5131 sata_hba_event_notify( 5132 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5133 &sdevice, 5134 SATA_EVNT_DEVICE_DETACHED); 5135 mutex_enter(&ahci_portp->ahciport_mutex); 5136 } 5137 5138 mutex_exit(&ahci_portp->ahciport_mutex); 5139 5140 return (AHCI_SUCCESS); 5141 } 5142 5143 /* 5144 * Enable the interrupts for a particular port. 5145 * 5146 * WARNING!!! ahciport_mutex should be acquired before the function 5147 * is called. 5148 */ 5149 /* ARGSUSED */ 5150 static void 5151 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, 5152 ahci_port_t *ahci_portp, uint8_t port) 5153 { 5154 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5155 "ahci_enable_port_intrs enter, port %d", port); 5156 5157 /* 5158 * Clear port interrupt status before enabling interrupt 5159 */ 5160 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5161 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5162 AHCI_PORT_INTR_MASK); 5163 5164 /* 5165 * Clear the pending bit from IS.IPS 5166 */ 5167 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5168 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5169 5170 /* 5171 * Enable the following interrupts: 5172 * Device to Host Register FIS Interrupt (DHRS) 5173 * PIO Setup FIS Interrupt (PSS) 5174 * Set Device Bits Interrupt (SDBS) 5175 * Unknown FIS Interrupt (UFS) 5176 * Port Connect Change Status (PCS) 5177 * PhyRdy Change Status (PRCS) 5178 * Overflow Status (OFS) 5179 * Interface Non-fatal Error Status (INFS) 5180 * Interface Fatal Error Status (IFS) 5181 * Host Bus Data Error Status (HBDS) 5182 * Host Bus Fatal Error Status (HBFS) 5183 * Task File Error Status (TFES) 5184 */ 5185 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5186 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5187 (AHCI_INTR_STATUS_DHRS | 5188 AHCI_INTR_STATUS_PSS | 5189 AHCI_INTR_STATUS_SDBS | 5190 AHCI_INTR_STATUS_UFS | 5191 AHCI_INTR_STATUS_DPS | 5192 AHCI_INTR_STATUS_PCS | 5193 AHCI_INTR_STATUS_PRCS | 5194 AHCI_INTR_STATUS_OFS | 5195 AHCI_INTR_STATUS_INFS | 5196 AHCI_INTR_STATUS_IFS | 5197 AHCI_INTR_STATUS_HBDS | 5198 AHCI_INTR_STATUS_HBFS | 5199 AHCI_INTR_STATUS_TFES)); 5200 } 5201 5202 /* 5203 * Enable interrupts for all the ports. 5204 * 5205 * WARNING!!! ahcictl_mutex should be acquired before the function 5206 * is called. 5207 */ 5208 static void 5209 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5210 { 5211 uint32_t ghc_control; 5212 5213 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5214 5215 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5216 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5217 5218 ghc_control |= AHCI_HBA_GHC_IE; 5219 5220 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5221 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5222 } 5223 5224 /* 5225 * Disable interrupts for a particular port. 5226 * 5227 * WARNING!!! ahciport_mutex should be acquired before the function 5228 * is called. 5229 */ 5230 /* ARGSUSED */ 5231 static void 5232 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, 5233 ahci_port_t *ahci_portp, uint8_t port) 5234 { 5235 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5236 "ahci_disable_port_intrs enter, port %d", port); 5237 5238 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5239 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5240 } 5241 5242 /* 5243 * Disable interrupts for the whole HBA. 5244 * 5245 * The global bit is cleared, then all interrupt sources from all 5246 * ports are disabled. 5247 * 5248 * WARNING!!! ahcictl_mutex should be acquired before the function 5249 * is called. 5250 */ 5251 static void 5252 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5253 { 5254 uint32_t ghc_control; 5255 5256 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5257 5258 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5259 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5260 5261 ghc_control &= ~ AHCI_HBA_GHC_IE; 5262 5263 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5264 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5265 } 5266 5267 /* 5268 * Handle INTx and legacy interrupts. 5269 */ 5270 static int 5271 ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 5272 { 5273 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5274 int actual, count = 0; 5275 int x, y, rc, inum = 0; 5276 5277 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5278 "ahci_add_legacy_intrs enter"); 5279 5280 /* get number of interrupts. */ 5281 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 5282 if ((rc != DDI_SUCCESS) || (count == 0)) { 5283 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5284 "ddi_intr_get_nintrs() failed, " 5285 "rc %d count %d\n", rc, count); 5286 return (DDI_FAILURE); 5287 } 5288 5289 /* Allocate an array of interrupt handles. */ 5290 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5291 ahci_ctlp->ahcictl_intr_htable = 5292 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5293 5294 /* call ddi_intr_alloc(). */ 5295 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5296 DDI_INTR_TYPE_FIXED, 5297 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 5298 5299 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5300 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5301 "ddi_intr_alloc() failed, rc %d\n", rc); 5302 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5303 ahci_ctlp->ahcictl_intr_size); 5304 return (DDI_FAILURE); 5305 } 5306 5307 if (actual < count) { 5308 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5309 "Requested: %d, Received: %d", count, actual); 5310 5311 for (x = 0; x < actual; x++) { 5312 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5313 } 5314 5315 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5316 ahci_ctlp->ahcictl_intr_size); 5317 return (DDI_FAILURE); 5318 } 5319 5320 ahci_ctlp->ahcictl_intr_cnt = actual; 5321 5322 /* Get intr priority. */ 5323 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5324 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5325 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5326 "ddi_intr_get_pri() failed"); 5327 5328 for (x = 0; x < actual; x++) { 5329 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5330 } 5331 5332 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5333 ahci_ctlp->ahcictl_intr_size); 5334 return (DDI_FAILURE); 5335 } 5336 5337 /* Test for high level interrupt. */ 5338 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5339 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5340 "ahci_add_legacy_intrs: Hi level intr not supported"); 5341 5342 for (x = 0; x < actual; x++) { 5343 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5344 } 5345 5346 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5347 sizeof (ddi_intr_handle_t)); 5348 5349 return (DDI_FAILURE); 5350 } 5351 5352 /* Call ddi_intr_add_handler(). */ 5353 for (x = 0; x < actual; x++) { 5354 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5355 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5356 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5357 "ddi_intr_add_handler() failed"); 5358 5359 for (y = 0; y < actual; y++) { 5360 (void) ddi_intr_free( 5361 ahci_ctlp->ahcictl_intr_htable[y]); 5362 } 5363 5364 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5365 ahci_ctlp->ahcictl_intr_size); 5366 return (DDI_FAILURE); 5367 } 5368 } 5369 5370 /* Call ddi_intr_enable() for legacy interrupts. */ 5371 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5372 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 5373 } 5374 5375 return (DDI_SUCCESS); 5376 } 5377 5378 /* 5379 * Handle MSI interrupts. 5380 */ 5381 static int 5382 ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 5383 { 5384 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5385 int count, avail, actual; 5386 int x, y, rc, inum = 0; 5387 5388 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5389 "ahci_add_msi_intrs enter"); 5390 5391 /* get number of interrupts. */ 5392 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 5393 if ((rc != DDI_SUCCESS) || (count == 0)) { 5394 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5395 "ddi_intr_get_nintrs() failed, " 5396 "rc %d count %d\n", rc, count); 5397 return (DDI_FAILURE); 5398 } 5399 5400 /* get number of available interrupts. */ 5401 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 5402 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5403 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5404 "ddi_intr_get_navail() failed, " 5405 "rc %d avail %d\n", rc, avail); 5406 return (DDI_FAILURE); 5407 } 5408 5409 if (avail < count) { 5410 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5411 "ddi_intr_get_nvail returned %d, navail() returned %d", 5412 count, avail); 5413 } 5414 5415 /* Allocate an array of interrupt handles. */ 5416 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5417 ahci_ctlp->ahcictl_intr_htable = 5418 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5419 5420 /* call ddi_intr_alloc(). */ 5421 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5422 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5423 5424 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5425 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5426 "ddi_intr_alloc() failed, rc %d\n", rc); 5427 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5428 ahci_ctlp->ahcictl_intr_size); 5429 return (DDI_FAILURE); 5430 } 5431 5432 /* use interrupt count returned */ 5433 if (actual < count) { 5434 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5435 "Requested: %d, Received: %d", count, actual); 5436 } 5437 5438 ahci_ctlp->ahcictl_intr_cnt = actual; 5439 5440 /* 5441 * Get priority for first msi, assume remaining are all the same. 5442 */ 5443 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5444 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5445 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5446 "ddi_intr_get_pri() failed"); 5447 5448 /* Free already allocated intr. */ 5449 for (y = 0; y < actual; y++) { 5450 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5451 } 5452 5453 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5454 ahci_ctlp->ahcictl_intr_size); 5455 return (DDI_FAILURE); 5456 } 5457 5458 /* Test for high level interrupt. */ 5459 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5460 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5461 "ahci_add_msi_intrs: Hi level intr not supported"); 5462 5463 /* Free already allocated intr. */ 5464 for (y = 0; y < actual; y++) { 5465 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5466 } 5467 5468 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5469 sizeof (ddi_intr_handle_t)); 5470 5471 return (DDI_FAILURE); 5472 } 5473 5474 /* Call ddi_intr_add_handler(). */ 5475 for (x = 0; x < actual; x++) { 5476 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5477 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5478 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5479 "ddi_intr_add_handler() failed"); 5480 5481 /* Free already allocated intr. */ 5482 for (y = 0; y < actual; y++) { 5483 (void) ddi_intr_free( 5484 ahci_ctlp->ahcictl_intr_htable[y]); 5485 } 5486 5487 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5488 ahci_ctlp->ahcictl_intr_size); 5489 return (DDI_FAILURE); 5490 } 5491 } 5492 5493 5494 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5495 &ahci_ctlp->ahcictl_intr_cap); 5496 5497 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5498 /* Call ddi_intr_block_enable() for MSI. */ 5499 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5500 ahci_ctlp->ahcictl_intr_cnt); 5501 } else { 5502 /* Call ddi_intr_enable() for MSI non block enable. */ 5503 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5504 (void) ddi_intr_enable( 5505 ahci_ctlp->ahcictl_intr_htable[x]); 5506 } 5507 } 5508 5509 return (DDI_SUCCESS); 5510 } 5511 5512 /* 5513 * Removes the registered interrupts irrespective of whether they 5514 * were legacy or MSI. 5515 * 5516 * WARNING!!! The controller interrupts must be disabled before calling 5517 * this routine. 5518 */ 5519 static void 5520 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5521 { 5522 int x; 5523 5524 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5525 5526 /* Disable all interrupts. */ 5527 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5528 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5529 /* Call ddi_intr_block_disable(). */ 5530 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5531 ahci_ctlp->ahcictl_intr_cnt); 5532 } else { 5533 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5534 (void) ddi_intr_disable( 5535 ahci_ctlp->ahcictl_intr_htable[x]); 5536 } 5537 } 5538 5539 /* Call ddi_intr_remove_handler(). */ 5540 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5541 (void) ddi_intr_remove_handler( 5542 ahci_ctlp->ahcictl_intr_htable[x]); 5543 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5544 } 5545 5546 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5547 } 5548 5549 /* 5550 * This routine tries to put port into P:NotRunning state by clearing 5551 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5552 * and PxCMD.CR to '0'. 5553 * 5554 * WARNING!!! ahciport_mutex should be acquired before the function 5555 * is called. 5556 */ 5557 /* ARGSUSED */ 5558 static int 5559 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5560 ahci_port_t *ahci_portp, uint8_t port) 5561 { 5562 uint32_t port_cmd_status; 5563 int loop_count; 5564 5565 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5566 "ahci_put_port_into_notrunning_state enter: port %d", port); 5567 5568 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5569 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5570 5571 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5572 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5573 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5574 5575 /* Wait until PxCMD.CR is cleared */ 5576 loop_count = 0; 5577 do { 5578 port_cmd_status = 5579 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5580 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5581 5582 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5583 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5584 "clearing port %d CMD.CR timeout, " 5585 "port_cmd_status = 0x%x", port, 5586 port_cmd_status); 5587 /* 5588 * We are effectively timing out after 0.5 sec. 5589 * This value is specified in AHCI spec. 5590 */ 5591 break; 5592 } 5593 5594 /* Wait for 10 millisec */ 5595 #ifndef __lock_lint 5596 delay(AHCI_10MS_TICKS); 5597 #endif /* __lock_lint */ 5598 5599 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5600 5601 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5602 5603 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5604 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5605 "ahci_put_port_into_notrunning_state: failed to clear " 5606 "PxCMD.CR to '0' after loop count: %d, and " 5607 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5608 return (AHCI_FAILURE); 5609 } else { 5610 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5611 "ahci_put_port_into_notrunning_state: succeeded to clear " 5612 "PxCMD.CR to '0' after loop count: %d, and " 5613 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5614 return (AHCI_SUCCESS); 5615 } 5616 } 5617 5618 /* 5619 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5620 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5621 * stable state, then set PxCMD.ST to '1' to start the port directly. 5622 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5623 * COMRESET to the device to put it in an idle state. 5624 * 5625 * The fifth argument returns whether the port reset is involved during 5626 * the process. 5627 * 5628 * The routine will be called under six scenarios: 5629 * 1. Initialize the port 5630 * 2. To abort the packet(s) 5631 * 3. To reset the port 5632 * 4. To activate the port 5633 * 5. Fatal error recovery 5634 * 6. To abort the timeout packet(s) 5635 * 5636 * WARNING!!! ahciport_mutex should be acquired before the function 5637 * is called. And ahciport_mutex will be released before the reset 5638 * event is reported to sata module by calling sata_hba_event_notify, 5639 * and then be acquired again later. 5640 * 5641 * NOTES!!! During this procedure, PxSERR register will be cleared, and 5642 * according to the spec, the clearance of three bits will also clear 5643 * three interrupt status bits. 5644 * 1. PxSERR.DIAG.F will clear PxIS.UFS 5645 * 2. PxSERR.DIAG.X will clear PxIS.PCS 5646 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 5647 * 5648 * Among these three interrupt events, the driver needs to take care of 5649 * PxIS.PRCS, which is the hot plug event. When the driver found out 5650 * a device was unplugged, it will call the interrupt handler. 5651 */ 5652 static int 5653 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5654 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 5655 { 5656 uint32_t port_sstatus; 5657 uint32_t task_file_status; 5658 sata_device_t sdevice; 5659 int rval; 5660 int dev_exists_begin = 0; 5661 int dev_exists_end = 0; 5662 5663 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5664 "ahci_restart_port_wait_till_ready: port %d enter", port); 5665 5666 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) 5667 dev_exists_begin = 1; 5668 5669 /* First clear PxCMD.ST */ 5670 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 5671 port); 5672 if (rval != AHCI_SUCCESS) 5673 /* 5674 * If PxCMD.CR does not clear within a reasonable time, it 5675 * may assume the interface is in a hung condition and may 5676 * continue with issuing the port reset. 5677 */ 5678 goto reset; 5679 5680 /* Then clear PxSERR */ 5681 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5682 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5683 AHCI_SERROR_CLEAR_ALL); 5684 5685 /* Then get PxTFD */ 5686 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5687 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5688 5689 /* 5690 * Check whether the device is in a stable status, if yes, 5691 * then start the port directly. However for ahci_tran_dport_reset, 5692 * we may have to perform a port reset. 5693 */ 5694 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 5695 !(flag & AHCI_PORT_RESET)) 5696 goto out; 5697 5698 reset: 5699 /* 5700 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 5701 * a COMRESET to the device 5702 */ 5703 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 5704 if (rval != AHCI_SUCCESS) 5705 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5706 "ahci_restart_port_wait_till_ready: port %d failed", 5707 port); 5708 5709 if (reset_flag != NULL) 5710 *reset_flag = 1; 5711 5712 /* Indicate to the framework that a reset has happened. */ 5713 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 5714 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 5715 /* Set the reset in progress flag */ 5716 ahci_portp->ahciport_reset_in_progress = 1; 5717 5718 bzero((void *)&sdevice, sizeof (sata_device_t)); 5719 sdevice.satadev_addr.cport = 5720 ahci_ctlp->ahcictl_port_to_cport[port]; 5721 sdevice.satadev_addr.pmport = 0; 5722 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5723 5724 sdevice.satadev_state = SATA_DSTATE_RESET | 5725 SATA_DSTATE_PWR_ACTIVE; 5726 if (ahci_ctlp->ahcictl_sata_hba_tran) { 5727 mutex_exit(&ahci_portp->ahciport_mutex); 5728 sata_hba_event_notify( 5729 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5730 &sdevice, 5731 SATA_EVNT_DEVICE_RESET); 5732 mutex_enter(&ahci_portp->ahciport_mutex); 5733 } 5734 5735 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5736 "port %d sending event up: SATA_EVNT_RESET", port); 5737 } else { 5738 ahci_portp->ahciport_reset_in_progress = 0; 5739 } 5740 5741 out: 5742 /* Start the port */ 5743 if (!(flag & AHCI_PORT_INIT)) { 5744 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 5745 } 5746 5747 /* SStatus tells the presence of device. */ 5748 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5749 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 5750 5751 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 5752 dev_exists_end = 1; 5753 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 5754 } 5755 5756 /* Check whether a hot plug event happened */ 5757 if (dev_exists_begin == 1 && dev_exists_end == 0) { 5758 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5759 "ahci_restart_port_wait_till_ready: port %d " 5760 "device is removed", port); 5761 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 5762 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5763 "ahci_restart_port_wait_till_ready: port %d " 5764 "AHCI_PORT_FLAG_NODEV flag is set", port); 5765 mutex_exit(&ahci_portp->ahciport_mutex); 5766 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 5767 mutex_enter(&ahci_portp->ahciport_mutex); 5768 } 5769 5770 return (rval); 5771 } 5772 5773 /* 5774 * This routine may be called under four scenarios: 5775 * a) do the recovery from fatal error 5776 * b) or we need to timeout some commands 5777 * c) or we need to abort some commands 5778 * d) or we need reset device/port/controller 5779 * 5780 * In all these scenarios, we need to send any pending unfinished 5781 * commands up to sata framework. 5782 * 5783 * WARNING!!! ahciport_mutex should be acquired before the function is called. 5784 */ 5785 static void 5786 ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 5787 ahci_port_t *ahci_portp, 5788 uint8_t port, 5789 uint32_t slot_status, 5790 uint32_t failed_tags, 5791 uint32_t timeout_tags, 5792 uint32_t aborted_tags, 5793 uint32_t reset_tags) 5794 { 5795 uint32_t finished_tags = 0; 5796 uint32_t unfinished_tags = 0; 5797 int tmp_slot; 5798 sata_pkt_t *satapkt; 5799 int ncq_cmd_in_progress = 0; 5800 int err_retri_cmd_in_progress = 0; 5801 5802 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 5803 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 5804 port, slot_status); 5805 5806 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 5807 "ahci_mop_commands: failed_tags: 0x%x, " 5808 "timeout_tags: 0x%x aborted_tags: 0x%x, " 5809 "reset_tags: 0x%x", failed_tags, 5810 timeout_tags, aborted_tags, reset_tags); 5811 5812 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5813 finished_tags = ahci_portp->ahciport_pending_tags & 5814 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 5815 5816 unfinished_tags = slot_status & 5817 AHCI_SLOT_MASK(ahci_ctlp) & 5818 ~failed_tags & 5819 ~aborted_tags & 5820 ~reset_tags & 5821 ~timeout_tags; 5822 } 5823 5824 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5825 ncq_cmd_in_progress = 1; 5826 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 5827 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 5828 5829 unfinished_tags = slot_status & 5830 AHCI_NCQ_SLOT_MASK(ahci_portp) & 5831 ~failed_tags & 5832 ~aborted_tags & 5833 ~reset_tags & 5834 ~timeout_tags; 5835 } 5836 5837 /* 5838 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is set, 5839 * it means REQUEST SENSE or READ LOG EXT command doesn't complete 5840 * successfully due to one of the following three conditions: 5841 * 5842 * 1. Fatal error - failed_tags includes its slot 5843 * 2. Timed out - timeout_tags includes its slot 5844 * 3. Aborted when hot unplug - aborted_tags includes its slot 5845 * 5846 * Please note that the command is always sent down in Slot 0 5847 */ 5848 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5849 err_retri_cmd_in_progress = 1; 5850 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 5851 "ahci_mop_commands is called for port %d while " 5852 "REQUEST SENSE or READ LOG EXT for error retrieval " 5853 "is being executed", port); 5854 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 5855 ASSERT(slot_status == 0x1); 5856 } 5857 5858 /* Send up finished packets with SATA_PKT_COMPLETED */ 5859 while (finished_tags) { 5860 tmp_slot = ddi_ffs(finished_tags) - 1; 5861 if (tmp_slot == -1) { 5862 break; 5863 } 5864 5865 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5866 ASSERT(satapkt != NULL); 5867 5868 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 5869 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 5870 (void *)satapkt); 5871 5872 /* 5873 * Cannot fetch the return register content since the port 5874 * was restarted, so the corresponding tag will be set to 5875 * aborted tags. 5876 */ 5877 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 5878 CLEAR_BIT(finished_tags, tmp_slot); 5879 aborted_tags |= tmp_slot; 5880 continue; 5881 } 5882 5883 if (ncq_cmd_in_progress) 5884 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5885 tmp_slot); 5886 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5887 CLEAR_BIT(finished_tags, tmp_slot); 5888 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5889 5890 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 5891 } 5892 5893 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 5894 while (failed_tags) { 5895 if (err_retri_cmd_in_progress) { 5896 satapkt = ahci_portp->ahciport_err_retri_pkt; 5897 ASSERT(satapkt != NULL); 5898 ASSERT(failed_tags == 0x1); 5899 5900 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5901 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 5902 (void *)satapkt); 5903 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 5904 break; 5905 } 5906 5907 tmp_slot = ddi_ffs(failed_tags) - 1; 5908 if (tmp_slot == -1) { 5909 break; 5910 } 5911 5912 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5913 ASSERT(satapkt != NULL); 5914 5915 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5916 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 5917 (void *)satapkt); 5918 5919 if (ncq_cmd_in_progress) 5920 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5921 tmp_slot); 5922 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5923 CLEAR_BIT(failed_tags, tmp_slot); 5924 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5925 5926 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 5927 } 5928 5929 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 5930 while (timeout_tags) { 5931 if (err_retri_cmd_in_progress) { 5932 satapkt = ahci_portp->ahciport_err_retri_pkt; 5933 ASSERT(satapkt != NULL); 5934 ASSERT(timeout_tags == 0x1); 5935 5936 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5937 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 5938 (void *)satapkt); 5939 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 5940 break; 5941 } 5942 5943 tmp_slot = ddi_ffs(timeout_tags) - 1; 5944 if (tmp_slot == -1) { 5945 break; 5946 } 5947 5948 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5949 ASSERT(satapkt != NULL); 5950 5951 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5952 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 5953 (void *)satapkt); 5954 5955 if (ncq_cmd_in_progress) 5956 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5957 tmp_slot); 5958 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5959 CLEAR_BIT(timeout_tags, tmp_slot); 5960 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5961 5962 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 5963 } 5964 5965 /* Send up aborted packets with SATA_PKT_ABORTED */ 5966 while (aborted_tags) { 5967 if (err_retri_cmd_in_progress) { 5968 satapkt = ahci_portp->ahciport_err_retri_pkt; 5969 ASSERT(satapkt != NULL); 5970 ASSERT(aborted_tags == 0x1); 5971 5972 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5973 "sending up pkt 0x%p with SATA_PKT_ABORTED", 5974 (void *)satapkt); 5975 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 5976 break; 5977 } 5978 5979 tmp_slot = ddi_ffs(aborted_tags) - 1; 5980 if (tmp_slot == -1) { 5981 break; 5982 } 5983 5984 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5985 ASSERT(satapkt != NULL); 5986 5987 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5988 "sending up pkt 0x%p with SATA_PKT_ABORTED", 5989 (void *)satapkt); 5990 5991 if (ncq_cmd_in_progress) 5992 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5993 tmp_slot); 5994 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5995 CLEAR_BIT(aborted_tags, tmp_slot); 5996 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5997 5998 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 5999 } 6000 6001 /* Send up reset packets with SATA_PKT_RESET. */ 6002 while (reset_tags) { 6003 tmp_slot = ddi_ffs(reset_tags) - 1; 6004 if (tmp_slot == -1) { 6005 break; 6006 } 6007 6008 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6009 ASSERT(satapkt != NULL); 6010 6011 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6012 "sending up pkt 0x%p with SATA_PKT_RESET", 6013 (void *)satapkt); 6014 6015 if (ncq_cmd_in_progress) 6016 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6017 tmp_slot); 6018 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6019 CLEAR_BIT(reset_tags, tmp_slot); 6020 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6021 6022 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6023 } 6024 6025 /* Send up unfinished packets with SATA_PKT_RESET */ 6026 while (unfinished_tags) { 6027 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6028 if (tmp_slot == -1) { 6029 break; 6030 } 6031 6032 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6033 ASSERT(satapkt != NULL); 6034 6035 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6036 "sending up pkt 0x%p with SATA_PKT_RESET", 6037 (void *)satapkt); 6038 6039 if (ncq_cmd_in_progress) 6040 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6041 tmp_slot); 6042 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6043 CLEAR_BIT(unfinished_tags, tmp_slot); 6044 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6045 6046 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6047 } 6048 6049 ahci_portp->ahciport_mop_in_progress--; 6050 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6051 6052 if (ahci_portp->ahciport_mop_in_progress == 0) 6053 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6054 } 6055 6056 /* 6057 * This routine is going to first request a READ LOG EXT sata pkt from sata 6058 * module, and then deliver it to the HBA to get the ncq failure context. 6059 * The return value is the exactly failed tags. 6060 */ 6061 static uint32_t 6062 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6063 uint8_t port) 6064 { 6065 sata_device_t sdevice; 6066 sata_pkt_t *rdlog_spkt, *spkt; 6067 ddi_dma_handle_t buf_dma_handle; 6068 int loop_count; 6069 int rval; 6070 int failed_slot; 6071 uint32_t failed_tags = 0; 6072 struct sata_ncq_error_recovery_page *ncq_err_page; 6073 6074 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6075 "ahci_get_rdlogext_data enter: port %d", port); 6076 6077 /* Prepare the sdevice data */ 6078 bzero((void *)&sdevice, sizeof (sata_device_t)); 6079 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6080 6081 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6082 sdevice.satadev_addr.pmport = 0; 6083 6084 /* 6085 * Call the sata hba interface to get a rdlog spkt 6086 */ 6087 loop_count = 0; 6088 loop: 6089 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6090 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6091 if (rdlog_spkt == NULL) { 6092 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6093 /* Sleep for a while */ 6094 delay(AHCI_10MS_TICKS); 6095 goto loop; 6096 } 6097 /* Timed out after 1s */ 6098 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6099 "failed to get rdlog spkt for port %d", port); 6100 return (failed_tags); 6101 } 6102 6103 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6104 6105 /* 6106 * This flag is used to handle the specific error recovery when the 6107 * READ LOG EXT command gets a failure (fatal error or time-out). 6108 */ 6109 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6110 6111 /* 6112 * This start is not supposed to fail because after port is restarted, 6113 * the whole command list is empty. 6114 */ 6115 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6116 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6117 ahci_portp->ahciport_err_retri_pkt = NULL; 6118 6119 /* Remove the flag after READ LOG EXT command is completed */ 6120 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6121 6122 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6123 /* Update the request log data */ 6124 buf_dma_handle = *(ddi_dma_handle_t *) 6125 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6126 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6127 DDI_DMA_SYNC_FORKERNEL); 6128 if (rval == DDI_SUCCESS) { 6129 ncq_err_page = 6130 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6131 satapkt_cmd.satacmd_bp->b_un.b_addr; 6132 6133 /* Get the failed tag */ 6134 failed_slot = ncq_err_page->ncq_tag; 6135 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6136 "ahci_get_rdlogext_data: port %d " 6137 "failed slot %d", port, failed_slot); 6138 if (failed_slot & NQ) { 6139 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6140 "the failed slot is not a valid tag"); 6141 goto out; 6142 } 6143 6144 failed_slot &= NCQ_TAG_MASK; 6145 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6146 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6147 "ahci_get_rdlogext_data: failed spkt 0x%p", 6148 (void *)spkt); 6149 if (spkt == NULL) { 6150 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6151 "the failed slot spkt is NULL") 6152 goto out; 6153 } 6154 6155 failed_tags = 0x1 << failed_slot; 6156 6157 /* Fill out the error context */ 6158 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6159 ncq_err_page); 6160 ahci_update_sata_registers(ahci_ctlp, port, 6161 &spkt->satapkt_device); 6162 } 6163 } else { 6164 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6165 "ahci_get_rdlogext_data: port %d READ LOG EXT command " 6166 "did not successfully complete", port); 6167 } 6168 out: 6169 sata_free_error_retrieval_pkt(rdlog_spkt); 6170 6171 return (failed_tags); 6172 } 6173 6174 /* 6175 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6176 * module, and then deliver it to the HBA to get the sense data and copy 6177 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6178 * SENSE sata pkt later. 6179 */ 6180 static void 6181 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6182 uint8_t port, sata_pkt_t *spkt) 6183 { 6184 sata_device_t sdevice; 6185 sata_pkt_t *rs_spkt; 6186 sata_cmd_t *sata_cmd; 6187 ddi_dma_handle_t buf_dma_handle; 6188 int loop_count; 6189 #if AHCI_DEBUG 6190 struct scsi_extended_sense *rqsense; 6191 #endif 6192 6193 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6194 "ahci_get_rqsense_data enter: port %d", port); 6195 6196 /* Prepare the sdevice data */ 6197 bzero((void *)&sdevice, sizeof (sata_device_t)); 6198 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6199 6200 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6201 sdevice.satadev_addr.pmport = 0; 6202 6203 sata_cmd = &spkt->satapkt_cmd; 6204 6205 /* 6206 * Call the sata hba interface to get a rs spkt 6207 */ 6208 loop_count = 0; 6209 loop: 6210 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6211 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6212 if (rs_spkt == NULL) { 6213 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6214 /* Sleep for a while */ 6215 delay(AHCI_10MS_TICKS); 6216 goto loop; 6217 6218 } 6219 /* Timed out after 1s */ 6220 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6221 "failed to get rs spkt for port %d", port); 6222 return; 6223 } 6224 6225 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6226 6227 /* 6228 * This flag is used to handle the specific error recovery when the 6229 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6230 */ 6231 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6232 6233 /* 6234 * This start is not supposed to fail because after port is restarted, 6235 * the whole command list is empty. 6236 */ 6237 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6238 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6239 ahci_portp->ahciport_err_retri_pkt = NULL; 6240 6241 /* Remove the flag after REQUEST SENSE command is completed */ 6242 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6243 6244 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6245 /* Update the request sense data */ 6246 buf_dma_handle = *(ddi_dma_handle_t *) 6247 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6248 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6249 DDI_DMA_SYNC_FORKERNEL); 6250 /* Copy the request sense data */ 6251 bcopy(rs_spkt-> 6252 satapkt_cmd.satacmd_bp->b_un.b_addr, 6253 &sata_cmd->satacmd_rqsense, 6254 SATA_ATAPI_MIN_RQSENSE_LEN); 6255 #if AHCI_DEBUG 6256 rqsense = (struct scsi_extended_sense *) 6257 sata_cmd->satacmd_rqsense; 6258 6259 /* Dump the sense data */ 6260 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6261 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6262 "Sense data for satapkt %p ATAPI cmd 0x%x", 6263 spkt, sata_cmd->satacmd_acdb[0]); 6264 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6265 " es_code 0x%x es_class 0x%x " 6266 "es_key 0x%x es_add_code 0x%x " 6267 "es_qual_code 0x%x", 6268 rqsense->es_code, rqsense->es_class, 6269 rqsense->es_key, rqsense->es_add_code, 6270 rqsense->es_qual_code); 6271 #endif 6272 } else { 6273 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6274 "ahci_get_rqsense_data: port %d REQUEST SENSE command " 6275 "did not successfully complete", port); 6276 } 6277 6278 sata_free_error_retrieval_pkt(rs_spkt); 6279 } 6280 6281 /* 6282 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6283 * the port must be restarted. When the HBA detects thus error, it may try 6284 * to abort a transfer. And if the transfer was aborted, the device is 6285 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6286 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6287 * that the device is in a stable status and transfers may be restarted without 6288 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6289 * then the software will send the COMRESET to do the port reset. 6290 * 6291 * Software should perform the appropriate error recovery actions based on 6292 * whether non-queued commands were being issued or natived command queuing 6293 * commands were being issued. 6294 * 6295 * And software will complete the command that had the error with error mark 6296 * to higher level software. 6297 * 6298 * Fatal errors include the following: 6299 * PxIS.IFS - Interface Fatal Error Status 6300 * PxIS.HBDS - Host Bus Data Error Status 6301 * PxIS.HBFS - Host Bus Fatal Error Status 6302 * PxIS.TFES - Task File Error Status 6303 * 6304 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6305 */ 6306 static void 6307 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6308 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6309 { 6310 uint32_t port_cmd_status; 6311 uint32_t slot_status = 0; 6312 uint32_t failed_tags = 0; 6313 int failed_slot; 6314 int reset_flag = 0; 6315 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6316 sata_cmd_t *sata_cmd = NULL; 6317 sata_pkt_t *spkt = NULL; 6318 6319 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6320 "ahci_fatal_error_recovery_handler enter: port %d", port); 6321 6322 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6323 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6324 6325 /* Read PxCI to see which commands are still outstanding */ 6326 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6327 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6328 6329 /* 6330 * Read PxCMD.CCS to determine the slot that the HBA 6331 * was processing when the error occurred. 6332 */ 6333 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6334 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6335 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6336 AHCI_CMD_STATUS_CCS_SHIFT; 6337 6338 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6339 spkt = ahci_portp->ahciport_err_retri_pkt; 6340 ASSERT(spkt != NULL); 6341 } else { 6342 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6343 if (spkt == NULL) { 6344 /* May happen when interface errors occur? */ 6345 goto next; 6346 } 6347 } 6348 6349 sata_cmd = &spkt->satapkt_cmd; 6350 6351 /* Fill out the status and error registers for PxIS.TFES */ 6352 if (intr_status & AHCI_INTR_STATUS_TFES) { 6353 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6354 ahcirf_d2h_register_fis); 6355 6356 /* Copy the error context back to the sata_cmd */ 6357 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6358 } 6359 6360 /* The failed command must be one of the outstanding commands */ 6361 failed_tags = 0x1 << failed_slot; 6362 ASSERT(failed_tags & slot_status); 6363 6364 /* Update the sata registers, especially PxSERR register */ 6365 ahci_update_sata_registers(ahci_ctlp, port, 6366 &spkt->satapkt_device); 6367 6368 } 6369 6370 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6371 /* Read PxSACT to see which commands are still outstanding */ 6372 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6373 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6374 } 6375 next: 6376 6377 #if AHCI_DEBUG 6378 /* 6379 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6380 * set, it means a fatal error happened after REQUEST SENSE command 6381 * or READ LOG EXT command is delivered to the HBA during the error 6382 * recovery process. At this time, the only outstanding command is 6383 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6384 */ 6385 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6386 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6387 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6388 "command or READ LOG EXT command for error data retrieval " 6389 "failed", port); 6390 ASSERT(slot_status == 0x1); 6391 ASSERT(failed_slot == 0x1); 6392 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6393 SCMD_REQUEST_SENSE || 6394 spkt->satapkt_cmd.satacmd_cmd_reg == 6395 SATAC_READ_LOG_EXT); 6396 } 6397 #endif 6398 6399 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6400 ahci_portp->ahciport_mop_in_progress++; 6401 6402 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6403 port, NULL, &reset_flag); 6404 6405 /* 6406 * Won't retrieve error information: 6407 * 1. Port reset was involved to recover 6408 * 2. Device is gone 6409 * 3. IDENTIFY DEVICE command sent to ATAPI device 6410 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6411 */ 6412 if (reset_flag || 6413 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6414 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6415 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6416 goto out; 6417 6418 /* 6419 * Deliver READ LOG EXT to gather information about the error when 6420 * a COMRESET has not been performed as part of the error recovery 6421 * during NCQ command processing. 6422 */ 6423 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6424 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6425 ahci_portp, port); 6426 goto out; 6427 } 6428 6429 /* 6430 * Deliver REQUEST SENSE for ATAPI command to gather information about 6431 * the error when a COMRESET has not been performed as part of the 6432 * error recovery. 6433 */ 6434 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPICD) 6435 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6436 out: 6437 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6438 "ahci_fatal_error_recovery_handler: port %d interface error " 6439 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6440 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6441 port, slot_status, ahci_portp->ahciport_pending_tags, 6442 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6443 6444 ahci_mop_commands(ahci_ctlp, 6445 ahci_portp, 6446 port, 6447 slot_status, 6448 failed_tags, /* failed tags */ 6449 0, /* timeout tags */ 6450 0, /* aborted tags */ 6451 0); /* reset tags */ 6452 } 6453 6454 /* 6455 * Handle events - fatal error recovery 6456 */ 6457 static void 6458 ahci_events_handler(void *args) 6459 { 6460 ahci_event_arg_t *ahci_event_arg; 6461 ahci_ctl_t *ahci_ctlp; 6462 ahci_port_t *ahci_portp; 6463 uint32_t event; 6464 uint8_t port; 6465 6466 ahci_event_arg = (ahci_event_arg_t *)args; 6467 6468 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6469 ahci_portp = ahci_event_arg->ahciea_portp; 6470 event = ahci_event_arg->ahciea_event; 6471 port = ahci_portp->ahciport_port_num; 6472 6473 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6474 "ahci_events_handler enter: port %d intr_status = 0x%x", 6475 port, event); 6476 6477 mutex_enter(&ahci_portp->ahciport_mutex); 6478 6479 /* 6480 * ahci_intr_phyrdy_change() may have rendered it to 6481 * SATA_DTYPE_NONE. 6482 */ 6483 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6484 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6485 "ahci_events_handler: port %d no device attached, " 6486 "and just return without doing anything", port); 6487 goto out; 6488 } 6489 6490 if (event & (AHCI_INTR_STATUS_IFS | 6491 AHCI_INTR_STATUS_HBDS | 6492 AHCI_INTR_STATUS_HBFS | 6493 AHCI_INTR_STATUS_TFES)) 6494 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6495 port, event); 6496 6497 out: 6498 mutex_exit(&ahci_portp->ahciport_mutex); 6499 } 6500 6501 /* 6502 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6503 * detect there are some commands which are timed out. 6504 */ 6505 static void 6506 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6507 uint8_t port, uint32_t tmp_timeout_tags) 6508 { 6509 uint32_t slot_status = 0; 6510 uint32_t finished_tags = 0; 6511 uint32_t timeout_tags = 0; 6512 6513 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6514 "ahci_timeout_pkts enter: port %d", port); 6515 6516 mutex_enter(&ahci_portp->ahciport_mutex); 6517 6518 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6519 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6520 /* Read PxCI to see which commands are still outstanding */ 6521 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6522 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6523 } 6524 6525 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6526 /* Read PxSACT to see which commands are still outstanding */ 6527 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6528 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6529 } 6530 6531 #if AHCI_DEBUG 6532 /* 6533 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6534 * set, it means a fatal error happened after REQUEST SENSE command 6535 * or READ LOG EXT command is delivered to the HBA during the error 6536 * recovery process. At this time, the only outstanding command is 6537 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6538 */ 6539 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6540 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 6541 "ahci_timeout_pkts called while REQUEST SENSE " 6542 "command or READ LOG EXT command for error recovery " 6543 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 6544 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 6545 tmp_timeout_tags, slot_status, 6546 ahci_portp->ahciport_pending_tags, 6547 ahci_portp->ahciport_pending_ncq_tags); 6548 ASSERT(slot_status == 0x1); 6549 } 6550 #endif 6551 6552 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6553 ahci_portp->ahciport_mop_in_progress++; 6554 6555 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6556 port, NULL, NULL); 6557 6558 /* 6559 * Re-identify timeout tags because some previously checked commands 6560 * could already complete. 6561 */ 6562 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6563 finished_tags = ahci_portp->ahciport_pending_tags & 6564 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6565 timeout_tags = tmp_timeout_tags & ~finished_tags; 6566 6567 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 6568 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6569 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 6570 "pending_tags = 0x%x ", 6571 port, finished_tags, timeout_tags, 6572 slot_status, ahci_portp->ahciport_pending_tags); 6573 } 6574 6575 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6576 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6577 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6578 timeout_tags = tmp_timeout_tags & ~finished_tags; 6579 6580 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 6581 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6582 "timeout_tags = 0x%x, port_sactive = 0x%x, " 6583 "pending_ncq_tags = 0x%x ", 6584 port, finished_tags, timeout_tags, 6585 slot_status, ahci_portp->ahciport_pending_ncq_tags); 6586 } 6587 6588 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6589 timeout_tags = tmp_timeout_tags; 6590 } 6591 6592 ahci_mop_commands(ahci_ctlp, 6593 ahci_portp, 6594 port, 6595 slot_status, 6596 0, /* failed tags */ 6597 timeout_tags, /* timeout tags */ 6598 0, /* aborted tags */ 6599 0); /* reset tags */ 6600 6601 mutex_exit(&ahci_portp->ahciport_mutex); 6602 } 6603 6604 /* 6605 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 6606 * for long time. 6607 */ 6608 static void 6609 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 6610 { 6611 ahci_port_t *ahci_portp; 6612 sata_pkt_t *spkt; 6613 uint32_t pending_tags; 6614 uint32_t timeout_tags; 6615 uint32_t port_cmd_status; 6616 uint32_t port_sactive; 6617 uint8_t port; 6618 int tmp_slot; 6619 int current_slot; 6620 uint32_t current_tags; 6621 /* max number of cycles this packet should survive */ 6622 int max_life_cycles; 6623 6624 /* how many cycles this packet survived so far */ 6625 int watched_cycles; 6626 6627 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6628 6629 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6630 "ahci_watchdog_handler entered"); 6631 6632 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6633 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6634 continue; 6635 } 6636 6637 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6638 6639 mutex_enter(&ahci_portp->ahciport_mutex); 6640 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6641 mutex_exit(&ahci_portp->ahciport_mutex); 6642 continue; 6643 } 6644 6645 /* Skip the check for those ports in error recovery */ 6646 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 6647 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 6648 mutex_exit(&ahci_portp->ahciport_mutex); 6649 continue; 6650 } 6651 6652 pending_tags = 0; 6653 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6654 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6655 6656 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6657 current_slot = 0; 6658 pending_tags = 0x1; 6659 } 6660 6661 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6662 current_slot = 6663 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6664 AHCI_CMD_STATUS_CCS_SHIFT; 6665 pending_tags = ahci_portp->ahciport_pending_tags; 6666 } 6667 6668 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6669 port_sactive = ddi_get32( 6670 ahci_ctlp->ahcictl_ahci_acc_handle, 6671 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6672 current_tags = port_sactive & 6673 ~port_cmd_status & 6674 AHCI_NCQ_SLOT_MASK(ahci_portp); 6675 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 6676 } 6677 6678 timeout_tags = 0; 6679 while (pending_tags) { 6680 tmp_slot = ddi_ffs(pending_tags) - 1; 6681 if (tmp_slot == -1) { 6682 break; 6683 } 6684 6685 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6686 spkt = ahci_portp->ahciport_err_retri_pkt; 6687 else 6688 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6689 6690 if ((spkt != NULL) && spkt->satapkt_time && 6691 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 6692 /* 6693 * We are overloading satapkt_hba_driver_private 6694 * with watched_cycle count. 6695 * 6696 * If a packet has survived for more than it's 6697 * max life cycles, it is a candidate for time 6698 * out. 6699 */ 6700 watched_cycles = (int)(intptr_t) 6701 spkt->satapkt_hba_driver_private; 6702 watched_cycles++; 6703 max_life_cycles = (spkt->satapkt_time + 6704 ahci_watchdog_timeout - 1) / 6705 ahci_watchdog_timeout; 6706 6707 spkt->satapkt_hba_driver_private = 6708 (void *)(intptr_t)watched_cycles; 6709 6710 if (watched_cycles <= max_life_cycles) 6711 goto next; 6712 6713 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6714 "the current slot is %d", current_slot); 6715 /* 6716 * We need to check whether the HBA has 6717 * begun to execute the command, if not, 6718 * then re-set the timer of the command. 6719 */ 6720 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 6721 (tmp_slot != current_slot) || 6722 NCQ_CMD_IN_PROGRESS(ahci_portp) && 6723 ((0x1 << tmp_slot) & current_tags)) { 6724 spkt->satapkt_hba_driver_private = 6725 (void *)(intptr_t)0; 6726 } else { 6727 timeout_tags |= (0x1 << tmp_slot); 6728 cmn_err(CE_NOTE, "!ahci watchdog: " 6729 "port %d satapkt 0x%p timed out\n", 6730 port, (void *)spkt); 6731 } 6732 } 6733 next: 6734 CLEAR_BIT(pending_tags, tmp_slot); 6735 } 6736 6737 if (timeout_tags) { 6738 mutex_exit(&ahci_portp->ahciport_mutex); 6739 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6740 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 6741 port, timeout_tags); 6742 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6743 mutex_enter(&ahci_portp->ahciport_mutex); 6744 } 6745 6746 mutex_exit(&ahci_portp->ahciport_mutex); 6747 } 6748 6749 /* Re-install the watchdog timeout handler */ 6750 if (ahci_ctlp->ahcictl_timeout_id != 0) { 6751 ahci_ctlp->ahcictl_timeout_id = 6752 timeout((void (*)(void *))ahci_watchdog_handler, 6753 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 6754 } 6755 6756 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6757 } 6758 6759 /* 6760 * Fill the error context into sata_cmd for non-queued command error. 6761 */ 6762 static void 6763 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 6764 { 6765 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 6766 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 6767 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 6768 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 6769 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 6770 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 6771 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 6772 6773 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 6774 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 6775 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 6776 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 6777 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 6778 } 6779 } 6780 6781 /* 6782 * Fill the ncq error page into sata_cmd for queued command error. 6783 */ 6784 static void 6785 ahci_copy_ncq_err_page(sata_cmd_t *scmd, 6786 struct sata_ncq_error_recovery_page *ncq_err_page) 6787 { 6788 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 6789 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 6790 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 6791 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 6792 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 6793 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 6794 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 6795 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 6796 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 6797 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 6798 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 6799 } 6800 6801 /* 6802 * Put the respective register value to sata_cmd_t for satacmd_flags. 6803 */ 6804 static void 6805 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 6806 { 6807 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 6808 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 6809 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 6810 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 6811 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 6812 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 6813 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 6814 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 6815 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 6816 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 6817 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 6818 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 6819 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 6820 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 6821 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 6822 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 6823 if (scmd->satacmd_flags.sata_copy_out_device_reg) 6824 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 6825 if (scmd->satacmd_flags.sata_copy_out_error_reg) 6826 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 6827 } 6828 6829 static void 6830 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 6831 uint32_t intr_status) 6832 { 6833 #ifndef __lock_lint 6834 _NOTE(ARGUNUSED(ahci_ctlp)) 6835 #endif 6836 6837 if (intr_status & AHCI_INTR_STATUS_IFS) 6838 cmn_err(CE_NOTE, "!ahci port %d has interface fatal " 6839 "error", port); 6840 6841 if (intr_status & AHCI_INTR_STATUS_HBDS) 6842 cmn_err(CE_NOTE, "!ahci port %d has bus data error", port); 6843 6844 if (intr_status & AHCI_INTR_STATUS_HBFS) 6845 cmn_err(CE_NOTE, "!ahci port %d has bus fatal error", port); 6846 6847 if (intr_status & AHCI_INTR_STATUS_TFES) 6848 cmn_err(CE_NOTE, "!ahci port %d has task file error", port); 6849 6850 cmn_err(CE_NOTE, "!ahci port %d is trying to do error " 6851 "recovery", port); 6852 } 6853 6854 /* 6855 * Dump the serror message to the log. 6856 */ 6857 static void 6858 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 6859 uint32_t port_serror) 6860 { 6861 #ifndef __lock_lint 6862 _NOTE(ARGUNUSED(ahci_ctlp)) 6863 #endif 6864 char *err_str; 6865 6866 if (port_serror & SERROR_DATA_ERR_FIXED) { 6867 err_str = "Recovered Data Integrity Error (I)"; 6868 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6869 "command error: port: %d, error: %s", 6870 port, err_str); 6871 } 6872 6873 if (port_serror & SERROR_COMM_ERR_FIXED) { 6874 err_str = "Recovered Communication Error (M)"; 6875 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6876 "command error: port: %d, error: %s", 6877 port, err_str); 6878 } 6879 6880 if (port_serror & SERROR_DATA_ERR) { 6881 err_str = "Transient Data Integrity Error (T)"; 6882 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6883 "command error: port: %d, error: %s", 6884 port, err_str); 6885 } 6886 6887 if (port_serror & SERROR_PERSISTENT_ERR) { 6888 err_str = 6889 "Persistent Communication or Data Integrity Error (C)"; 6890 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6891 "command error: port: %d, error: %s", 6892 port, err_str); 6893 } 6894 6895 if (port_serror & SERROR_PROTOCOL_ERR) { 6896 err_str = "Protocol Error (P)"; 6897 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6898 "command error: port: %d, error: %s", 6899 port, err_str); 6900 } 6901 6902 if (port_serror & SERROR_INT_ERR) { 6903 err_str = "Internal Error (E)"; 6904 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6905 "command error: port: %d, error: %s", 6906 port, err_str); 6907 } 6908 6909 if (port_serror & SERROR_PHY_RDY_CHG) { 6910 err_str = "PhyRdy Change (N)"; 6911 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6912 "command error: port: %d, error: %s", 6913 port, err_str); 6914 } 6915 6916 if (port_serror & SERROR_PHY_INT_ERR) { 6917 err_str = "Phy Internal Error (I)"; 6918 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6919 "command error: port: %d, error: %s", 6920 port, err_str); 6921 } 6922 6923 if (port_serror & SERROR_COMM_WAKE) { 6924 err_str = "Comm Wake (W)"; 6925 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6926 "command error: port: %d, error: %s", 6927 port, err_str); 6928 } 6929 6930 if (port_serror & SERROR_10B_TO_8B_ERR) { 6931 err_str = "10B to 8B Decode Error (B)"; 6932 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6933 "command error: port: %d, error: %s", 6934 port, err_str); 6935 } 6936 6937 if (port_serror & SERROR_DISPARITY_ERR) { 6938 err_str = "Disparity Error (D)"; 6939 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6940 "command error: port: %d, error: %s", 6941 port, err_str); 6942 } 6943 6944 if (port_serror & SERROR_CRC_ERR) { 6945 err_str = "CRC Error (C)"; 6946 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6947 "command error: port: %d, error: %s", 6948 port, err_str); 6949 } 6950 6951 if (port_serror & SERROR_HANDSHAKE_ERR) { 6952 err_str = "Handshake Error (H)"; 6953 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6954 "command error: port: %d, error: %s", 6955 port, err_str); 6956 } 6957 6958 if (port_serror & SERROR_LINK_SEQ_ERR) { 6959 err_str = "Link Sequence Error (S)"; 6960 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6961 "command error: port: %d, error: %s", 6962 port, err_str); 6963 } 6964 6965 if (port_serror & SERROR_TRANS_ERR) { 6966 err_str = "Transport state transition error (T)"; 6967 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6968 "command error: port: %d, error: %s", 6969 port, err_str); 6970 } 6971 6972 if (port_serror & SERROR_FIS_TYPE) { 6973 err_str = "Unknown FIS Type (F)"; 6974 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6975 "command error: port: %d, error: %s", 6976 port, err_str); 6977 } 6978 6979 if (port_serror & SERROR_EXCHANGED_ERR) { 6980 err_str = "Exchanged (X)"; 6981 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6982 "command error: port: %d, error: %s", 6983 port, err_str); 6984 } 6985 } 6986 6987 /* 6988 * This routine is to calculate the total number of ports implemented 6989 * by the HBA. 6990 */ 6991 static int 6992 ahci_get_num_implemented_ports(uint32_t ports_implemented) 6993 { 6994 uint8_t i; 6995 int num = 0; 6996 6997 for (i = 0; i < AHCI_MAX_PORTS; i++) { 6998 if (((uint32_t)0x1 << i) & ports_implemented) 6999 num++; 7000 } 7001 7002 return (num); 7003 } 7004 7005 static void 7006 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7007 { 7008 va_list ap; 7009 7010 mutex_enter(&ahci_log_mutex); 7011 7012 va_start(ap, fmt); 7013 if (ahci_ctlp) { 7014 (void) sprintf(ahci_log_buf, "%s-[%d]:", 7015 ddi_get_name(ahci_ctlp->ahcictl_dip), 7016 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7017 } else { 7018 (void) sprintf(ahci_log_buf, "ahci:"); 7019 } 7020 7021 (void) vsprintf(ahci_log_buf, fmt, ap); 7022 va_end(ap); 7023 7024 cmn_err(level, "%s", ahci_log_buf); 7025 7026 mutex_exit(&ahci_log_mutex); 7027 } 7028