1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 31 * 32 * Power Management Support 33 * ------------------------ 34 * 35 * At the moment, the ahci driver only implements suspend/resume to 36 * support Suspend to RAM on X86 feature. Device power management isn't 37 * implemented, link power management is disabled, and hot plug isn't 38 * allowed during the period from suspend to resume. 39 * 40 * For s/r support, the ahci driver only need to implement DDI_SUSPEND 41 * and DDI_RESUME entries, and don't need to take care of new requests 42 * sent down after suspend because the target driver (sd) has already 43 * handled these conditions, and blocked these requests. For the detailed 44 * information, please check with sdopen, sdclose and sdioctl routines. 45 * 46 */ 47 48 #include <sys/scsi/scsi.h> 49 #include <sys/pci.h> 50 #include <sys/sata/sata_hba.h> 51 #include <sys/sata/adapters/ahci/ahcireg.h> 52 #include <sys/sata/adapters/ahci/ahcivar.h> 53 54 /* 55 * Function prototypes for driver entry points 56 */ 57 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 58 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 59 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 60 61 /* 62 * Function prototypes for SATA Framework interfaces 63 */ 64 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 65 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 66 67 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 68 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 69 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 70 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 71 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 72 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 73 #if defined(__lock_lint) 74 static int ahci_selftest(dev_info_t *, sata_device_t *); 75 #endif 76 77 /* 78 * Local function prototypes 79 */ 80 static int ahci_alloc_ports_state(ahci_ctl_t *); 81 static void ahci_dealloc_ports_state(ahci_ctl_t *); 82 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 83 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 84 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 85 static void ahci_dealloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *); 86 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 87 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 88 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 89 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 90 91 static int ahci_initialize_controller(ahci_ctl_t *); 92 static void ahci_uninitialize_controller(ahci_ctl_t *); 93 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 94 static int ahci_config_space_init(ahci_ctl_t *); 95 96 static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 97 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 98 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 99 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 100 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 101 uint8_t, sata_pkt_t *); 102 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 103 uint8_t, sata_pkt_t *); 104 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 105 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 106 static void ahci_copy_ncq_err_page(sata_cmd_t *, 107 struct sata_ncq_error_recovery_page *); 108 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 109 110 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 111 static int ahci_hba_reset(ahci_ctl_t *); 112 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 113 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 114 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 115 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 116 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 117 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 118 uint8_t); 119 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 120 uint8_t, int, int *); 121 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint8_t, 122 uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); 123 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 124 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 125 uint8_t, sata_pkt_t *); 126 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 127 uint8_t, uint32_t); 128 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 129 uint8_t, uint32_t); 130 static void ahci_events_handler(void *); 131 static void ahci_watchdog_handler(ahci_ctl_t *); 132 133 static uint_t ahci_intr(caddr_t, caddr_t); 134 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 135 static int ahci_add_legacy_intrs(ahci_ctl_t *); 136 static int ahci_add_msi_intrs(ahci_ctl_t *); 137 static void ahci_rem_intrs(ahci_ctl_t *); 138 static void ahci_enable_all_intrs(ahci_ctl_t *); 139 static void ahci_disable_all_intrs(ahci_ctl_t *); 140 static void ahci_enable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 141 static void ahci_disable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 142 143 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t, 144 uint32_t); 145 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 146 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 147 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 148 ahci_port_t *, uint8_t); 149 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 150 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 151 uint8_t, uint32_t); 152 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 153 uint8_t, uint32_t); 154 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 155 156 static int ahci_get_num_implemented_ports(uint32_t); 157 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 158 uint32_t); 159 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t); 160 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 161 162 163 /* 164 * DMA attributes for the data buffer 165 * 166 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 167 * does not support 64-bit addressing 168 */ 169 static ddi_dma_attr_t buffer_dma_attr = { 170 DMA_ATTR_V0, /* dma_attr_version */ 171 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 172 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 173 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 174 0x2ull, /* dma_attr_align: word aligned */ 175 1, /* dma_attr_burstsizes */ 176 1, /* dma_attr_minxfer */ 177 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 178 0xffffffffull, /* dma_attr_seg */ 179 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 180 512, /* dma_attr_granular */ 181 0, /* dma_attr_flags */ 182 }; 183 184 /* 185 * DMA attributes for the rcvd FIS 186 * 187 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 188 * does not support 64-bit addressing 189 */ 190 static ddi_dma_attr_t rcvd_fis_dma_attr = { 191 DMA_ATTR_V0, /* dma_attr_version */ 192 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 193 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 194 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 195 0x100ull, /* dma_attr_align: 256-byte aligned */ 196 1, /* dma_attr_burstsizes */ 197 1, /* dma_attr_minxfer */ 198 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 199 0xffffffffull, /* dma_attr_seg */ 200 1, /* dma_attr_sgllen */ 201 1, /* dma_attr_granular */ 202 0, /* dma_attr_flags */ 203 }; 204 205 /* 206 * DMA attributes for the command list 207 * 208 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 209 * does not support 64-bit addressing 210 */ 211 static ddi_dma_attr_t cmd_list_dma_attr = { 212 DMA_ATTR_V0, /* dma_attr_version */ 213 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 214 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 215 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 216 0x400ull, /* dma_attr_align: 1K-byte aligned */ 217 1, /* dma_attr_burstsizes */ 218 1, /* dma_attr_minxfer */ 219 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 220 0xffffffffull, /* dma_attr_seg */ 221 1, /* dma_attr_sgllen */ 222 1, /* dma_attr_granular */ 223 0, /* dma_attr_flags */ 224 }; 225 226 /* 227 * DMA attributes for cmd tables 228 * 229 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 230 * does not support 64-bit addressing 231 */ 232 static ddi_dma_attr_t cmd_table_dma_attr = { 233 DMA_ATTR_V0, /* dma_attr_version */ 234 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 235 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 236 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 237 0x80ull, /* dma_attr_align: 128-byte aligned */ 238 1, /* dma_attr_burstsizes */ 239 1, /* dma_attr_minxfer */ 240 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 241 0xffffffffull, /* dma_attr_seg */ 242 1, /* dma_attr_sgllen */ 243 1, /* dma_attr_granular */ 244 0, /* dma_attr_flags */ 245 }; 246 247 248 /* Device access attributes */ 249 static ddi_device_acc_attr_t accattr = { 250 DDI_DEVICE_ATTR_V0, 251 DDI_STRUCTURE_LE_ACC, 252 DDI_STRICTORDER_ACC 253 }; 254 255 256 static struct dev_ops ahcictl_dev_ops = { 257 DEVO_REV, /* devo_rev */ 258 0, /* refcnt */ 259 ahci_getinfo, /* info */ 260 nulldev, /* identify */ 261 nulldev, /* probe */ 262 ahci_attach, /* attach */ 263 ahci_detach, /* detach */ 264 nodev, /* no reset */ 265 (struct cb_ops *)0, /* driver operations */ 266 NULL, /* bus operations */ 267 NULL /* power */ 268 }; 269 270 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 271 SATA_TRAN_HOTPLUG_OPS_REV_1, 272 ahci_tran_hotplug_port_activate, 273 ahci_tran_hotplug_port_deactivate 274 }; 275 276 extern struct mod_ops mod_driverops; 277 278 static struct modldrv modldrv = { 279 &mod_driverops, /* driverops */ 280 "ahci driver %I%", 281 &ahcictl_dev_ops, /* driver ops */ 282 }; 283 284 static struct modlinkage modlinkage = { 285 MODREV_1, 286 &modldrv, 287 NULL 288 }; 289 290 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 291 static int ahci_watchdog_tick; 292 293 /* The following is needed for ahci_log() */ 294 static kmutex_t ahci_log_mutex; 295 static char ahci_log_buf[512]; 296 297 static size_t ahci_cmd_table_size; 298 299 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 300 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 301 302 /* 303 * AHCI MSI tunable: 304 * 305 * MSI will be enabled in phase 2. 306 */ 307 boolean_t ahci_msi_enabled = B_FALSE; 308 309 #if AHCI_DEBUG 310 uint32_t ahci_debug_flags = 0; 311 #endif 312 313 /* Opaque state pointer initialized by ddi_soft_state_init() */ 314 static void *ahci_statep = NULL; 315 316 /* 317 * ahci module initialization. 318 */ 319 int 320 _init(void) 321 { 322 int ret; 323 324 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 325 if (ret != 0) { 326 goto err_out; 327 } 328 329 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 330 331 if ((ret = sata_hba_init(&modlinkage)) != 0) { 332 mutex_destroy(&ahci_log_mutex); 333 ddi_soft_state_fini(&ahci_statep); 334 goto err_out; 335 } 336 337 ret = mod_install(&modlinkage); 338 if (ret != 0) { 339 sata_hba_fini(&modlinkage); 340 mutex_destroy(&ahci_log_mutex); 341 ddi_soft_state_fini(&ahci_statep); 342 goto err_out; 343 } 344 345 /* watchdog tick */ 346 ahci_watchdog_tick = drv_usectohz( 347 (clock_t)ahci_watchdog_timeout * 1000000); 348 return (ret); 349 350 err_out: 351 cmn_err(CE_WARN, "!Module init failed"); 352 return (ret); 353 } 354 355 /* 356 * ahci module uninitialize. 357 */ 358 int 359 _fini(void) 360 { 361 int ret; 362 363 ret = mod_remove(&modlinkage); 364 if (ret != 0) { 365 return (ret); 366 } 367 368 /* Remove the resources allocated in _init(). */ 369 sata_hba_fini(&modlinkage); 370 mutex_destroy(&ahci_log_mutex); 371 ddi_soft_state_fini(&ahci_statep); 372 373 return (ret); 374 } 375 376 /* 377 * _info entry point 378 */ 379 int 380 _info(struct modinfo *modinfop) 381 { 382 return (mod_info(&modlinkage, modinfop)); 383 } 384 385 /* 386 * The attach entry point for dev_ops. 387 */ 388 static int 389 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 390 { 391 ahci_ctl_t *ahci_ctlp; 392 int instance = ddi_get_instance(dip); 393 int status; 394 int attach_state; 395 uint32_t cap_status, ahci_version; 396 int intr_types; 397 int i; 398 pci_regspec_t *regs; 399 int regs_length; 400 int rnumber; 401 #if AHCI_DEBUG 402 int speed; 403 #endif 404 405 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 406 407 switch (cmd) { 408 case DDI_ATTACH: 409 break; 410 411 case DDI_RESUME: 412 413 /* 414 * During DDI_RESUME, the hardware state of the device 415 * (power may have been removed from the device) must be 416 * restored, allow pending requests to continue, and 417 * service new requests. 418 */ 419 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 420 mutex_enter(&ahci_ctlp->ahcictl_mutex); 421 422 /* Restart watch thread */ 423 if (ahci_ctlp->ahcictl_timeout_id == 0) 424 ahci_ctlp->ahcictl_timeout_id = timeout( 425 (void (*)(void *))ahci_watchdog_handler, 426 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 427 428 mutex_exit(&ahci_ctlp->ahcictl_mutex); 429 430 /* 431 * Re-initialize the controller and enable the interrupts and 432 * restart all the ports. 433 * 434 * Note that so far we don't support hot-plug during 435 * suspend/resume. 436 */ 437 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 438 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 439 "ahci%d: Failed to initialize the controller " 440 "during DDI_RESUME", instance); 441 return (DDI_FAILURE); 442 } 443 444 mutex_enter(&ahci_ctlp->ahcictl_mutex); 445 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 446 mutex_exit(&ahci_ctlp->ahcictl_mutex); 447 448 return (DDI_SUCCESS); 449 450 default: 451 return (DDI_FAILURE); 452 } 453 454 attach_state = AHCI_ATTACH_STATE_NONE; 455 456 /* Allocate soft state */ 457 status = ddi_soft_state_zalloc(ahci_statep, instance); 458 if (status != DDI_SUCCESS) { 459 cmn_err(CE_WARN, "!Cannot allocate soft state"); 460 goto err_out; 461 } 462 463 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 464 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 465 ahci_ctlp->ahcictl_dip = dip; 466 467 /* Initialize the cport/port mapping */ 468 for (i = 0; i < AHCI_MAX_PORTS; i++) { 469 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 470 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 471 } 472 473 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 474 475 /* 476 * Now map the AHCI base address; which includes global 477 * registers and port control registers 478 * 479 * According to the spec, the AHCI Base Address is BAR5, 480 * but BAR0-BAR4 are optional, so we need to check which 481 * rnumber is used for BAR5. 482 */ 483 484 /* 485 * search through DDI "reg" property for the AHCI register set 486 */ 487 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 488 DDI_PROP_DONTPASS, "reg", (int **)®s, 489 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 490 cmn_err(CE_WARN, "!Cannot lookup reg property"); 491 goto err_out; 492 } 493 494 /* AHCI Base Address is located at 0x24 offset */ 495 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 496 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 497 == AHCI_PCI_RNUM) 498 break; 499 } 500 501 ddi_prop_free(regs); 502 503 if (rnumber == regs_length) { 504 cmn_err(CE_WARN, "!Cannot find AHCI register set"); 505 goto err_out; 506 } 507 508 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 509 510 status = ddi_regs_map_setup(dip, 511 rnumber, 512 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 513 0, 514 0, 515 &accattr, 516 &ahci_ctlp->ahcictl_ahci_acc_handle); 517 if (status != DDI_SUCCESS) { 518 cmn_err(CE_WARN, "!Cannot map register space"); 519 goto err_out; 520 } 521 522 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 523 524 /* Get the AHCI version information */ 525 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 526 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 527 528 cmn_err(CE_NOTE, "!hba AHCI version = %x.%x", 529 (ahci_version & 0xffff0000) >> 16, 530 ((ahci_version & 0x0000ff00) >> 4 | 531 (ahci_version & 0x000000ff))); 532 533 /* We don't support controllers whose versions are lower than 1.0 */ 534 if (!(ahci_version & 0xffff0000)) { 535 cmn_err(CE_WARN, "Don't support AHCI HBA with lower than " 536 "version 1.0"); 537 goto err_out; 538 } 539 540 /* Get the HBA capabilities information */ 541 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 542 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 543 544 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 545 cap_status); 546 547 #if AHCI_DEBUG 548 /* Get the interface speed supported by the HBA */ 549 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 550 if (speed == 0x01) { 551 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 552 "hba interface speed support: Gen 1 (1.5Gbps)"); 553 } else if (speed == 0x10) { 554 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 555 "hba interface speed support: Gen 2 (3 Gbps)"); 556 } else if (speed == 0x11) { 557 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 558 "hba interface speed support: Gen 3 (6 Gbps)"); 559 } 560 #endif 561 562 /* Get the number of command slots supported by the HBA */ 563 ahci_ctlp->ahcictl_num_cmd_slots = 564 ((cap_status & AHCI_HBA_CAP_NCS) >> 565 AHCI_HBA_CAP_NCS_SHIFT) + 1; 566 567 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 568 ahci_ctlp->ahcictl_num_cmd_slots); 569 570 /* Get the bit map which indicates ports implemented by the HBA */ 571 ahci_ctlp->ahcictl_ports_implemented = 572 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 573 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 574 575 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 576 ahci_ctlp->ahcictl_ports_implemented); 577 578 /* 579 * According to the AHCI spec, CAP.NP should indicate the maximum 580 * number of ports supported by the HBA silicon, but we found 581 * this value of ICH8 chipset only indicates the number of ports 582 * implemented (exposed) by it. Therefore, the driver should calculate 583 * the potential maximum value by checking PI register, and use 584 * the maximum of this value and CAP.NP. 585 */ 586 ahci_ctlp->ahcictl_num_ports = max( 587 (cap_status & AHCI_HBA_CAP_NP) + 1, 588 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 589 590 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 591 ahci_ctlp->ahcictl_num_ports); 592 593 /* Get the number of implemented ports by the HBA */ 594 ahci_ctlp->ahcictl_num_implemented_ports = 595 ahci_get_num_implemented_ports( 596 ahci_ctlp->ahcictl_ports_implemented); 597 598 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 599 "hba number of implemented ports: %d", 600 ahci_ctlp->ahcictl_num_implemented_ports); 601 602 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 603 604 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 605 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 606 "hba does not support 64-bit addressing"); 607 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 608 0xffffffffull; 609 } 610 611 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 612 != DDI_SUCCESS) { 613 cmn_err(CE_WARN, "!Cannot set up pci configure space"); 614 goto err_out; 615 } 616 617 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 618 619 /* Check the pci configuration space, and set caps */ 620 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 621 cmn_err(CE_WARN, "!ahci_config_space_init failed"); 622 goto err_out; 623 } 624 625 /* 626 * Disable the whole controller interrupts before adding 627 * interrupt handlers(s). 628 */ 629 ahci_disable_all_intrs(ahci_ctlp); 630 631 /* Get supported interrupt types */ 632 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 633 cmn_err(CE_WARN, "!ddi_intr_get_supported_types failed"); 634 goto err_out; 635 } 636 637 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 638 "ddi_intr_get_supported_types() returned: 0x%x", 639 intr_types); 640 641 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 642 /* 643 * Try MSI first, but fall back to FIXED if failed 644 */ 645 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 646 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 647 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 648 "Using MSI interrupt type"); 649 goto intr_done; 650 } 651 652 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 653 "MSI registration failed, " 654 "trying FIXED interrupts"); 655 } 656 657 if (intr_types & DDI_INTR_TYPE_FIXED) { 658 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 659 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 660 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, NULL, 661 "Using FIXED interrupt type"); 662 goto intr_done; 663 } 664 665 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 666 "FIXED interrupt registration failed"); 667 } 668 669 cmn_err(CE_WARN, "!Interrupt registration failed"); 670 671 goto err_out; 672 673 intr_done: 674 675 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 676 677 /* Initialize the controller mutex */ 678 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 679 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 680 681 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 682 683 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 684 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 685 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 686 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 687 } 688 689 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 690 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 691 sizeof (ahci_prdt_item_t)); 692 693 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 694 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 695 " ahci_cmd_table_size is 0x%x", 696 ahci_dma_prdt_number, ahci_cmd_table_size); 697 698 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 699 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 700 ahci_dma_prdt_number; 701 702 /* Allocate the ports structure */ 703 status = ahci_alloc_ports_state(ahci_ctlp); 704 if (status != AHCI_SUCCESS) { 705 cmn_err(CE_WARN, "!Cannot allocate ports structure"); 706 goto err_out; 707 } 708 709 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 710 711 /* 712 * A taskq is created for dealing with events 713 */ 714 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 715 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 716 cmn_err(CE_WARN, "!ddi_taskq_create failed for event handle"); 717 goto err_out; 718 } 719 720 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 721 722 /* 723 * Initialize the controller and ports. 724 */ 725 status = ahci_initialize_controller(ahci_ctlp); 726 if (status != AHCI_SUCCESS) { 727 cmn_err(CE_WARN, "!HBA initialization failed"); 728 goto err_out; 729 } 730 731 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 732 733 /* Start one thread to check packet timeouts */ 734 ahci_ctlp->ahcictl_timeout_id = timeout( 735 (void (*)(void *))ahci_watchdog_handler, 736 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 737 738 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 739 740 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 741 cmn_err(CE_WARN, "!sata hba tran registration failed"); 742 goto err_out; 743 } 744 745 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 746 747 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 748 749 return (DDI_SUCCESS); 750 751 err_out: 752 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 753 mutex_enter(&ahci_ctlp->ahcictl_mutex); 754 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 755 ahci_ctlp->ahcictl_timeout_id = 0; 756 mutex_exit(&ahci_ctlp->ahcictl_mutex); 757 } 758 759 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 760 ahci_uninitialize_controller(ahci_ctlp); 761 } 762 763 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 764 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 765 } 766 767 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 768 ahci_dealloc_ports_state(ahci_ctlp); 769 } 770 771 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 772 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 773 } 774 775 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 776 ahci_rem_intrs(ahci_ctlp); 777 } 778 779 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 780 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 781 } 782 783 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 784 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 785 } 786 787 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 788 ddi_soft_state_free(ahci_statep, instance); 789 } 790 791 return (DDI_FAILURE); 792 } 793 794 /* 795 * The detach entry point for dev_ops. 796 */ 797 static int 798 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 799 { 800 ahci_ctl_t *ahci_ctlp; 801 int instance; 802 int ret; 803 804 instance = ddi_get_instance(dip); 805 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 806 807 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 808 809 switch (cmd) { 810 case DDI_DETACH: 811 812 /* disable the interrupts for an uninterrupted detach */ 813 mutex_enter(&ahci_ctlp->ahcictl_mutex); 814 ahci_disable_all_intrs(ahci_ctlp); 815 mutex_exit(&ahci_ctlp->ahcictl_mutex); 816 817 /* unregister from the sata framework. */ 818 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 819 if (ret != AHCI_SUCCESS) { 820 mutex_enter(&ahci_ctlp->ahcictl_mutex); 821 ahci_enable_all_intrs(ahci_ctlp); 822 mutex_exit(&ahci_ctlp->ahcictl_mutex); 823 return (DDI_FAILURE); 824 } 825 826 mutex_enter(&ahci_ctlp->ahcictl_mutex); 827 828 /* stop the watchdog handler */ 829 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 830 ahci_ctlp->ahcictl_timeout_id = 0; 831 832 mutex_exit(&ahci_ctlp->ahcictl_mutex); 833 834 /* uninitialize the controller */ 835 ahci_uninitialize_controller(ahci_ctlp); 836 837 /* remove the interrupts */ 838 ahci_rem_intrs(ahci_ctlp); 839 840 /* destroy the taskq */ 841 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 842 843 /* deallocate the ports structures */ 844 ahci_dealloc_ports_state(ahci_ctlp); 845 846 /* destroy mutex */ 847 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 848 849 /* teardown the pci config */ 850 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 851 852 /* remove the reg maps. */ 853 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 854 855 /* free the soft state. */ 856 ddi_soft_state_free(ahci_statep, instance); 857 858 return (DDI_SUCCESS); 859 860 case DDI_SUSPEND: 861 862 /* 863 * The steps associated with suspension must include putting 864 * the underlying device into a quiescent state so that it 865 * will not generate interrupts or modify or access memory. 866 */ 867 mutex_enter(&ahci_ctlp->ahcictl_mutex); 868 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 869 mutex_exit(&ahci_ctlp->ahcictl_mutex); 870 return (DDI_SUCCESS); 871 } 872 873 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 874 875 /* stop the watchdog handler */ 876 if (ahci_ctlp->ahcictl_timeout_id) { 877 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 878 ahci_ctlp->ahcictl_timeout_id = 0; 879 } 880 881 mutex_exit(&ahci_ctlp->ahcictl_mutex); 882 883 /* 884 * drain the taskq 885 */ 886 ddi_taskq_wait(ahci_ctlp->ahcictl_event_taskq); 887 888 /* 889 * Disable the interrupts and stop all the ports. 890 */ 891 ahci_uninitialize_controller(ahci_ctlp); 892 893 return (DDI_SUCCESS); 894 895 default: 896 return (DDI_FAILURE); 897 } 898 } 899 900 /* 901 * The info entry point for dev_ops. 902 * 903 */ 904 static int 905 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 906 void *arg, void **result) 907 { 908 #ifndef __lock_lint 909 _NOTE(ARGUNUSED(dip)) 910 #endif /* __lock_lint */ 911 912 ahci_ctl_t *ahci_ctlp; 913 int instance; 914 dev_t dev; 915 916 dev = (dev_t)arg; 917 instance = getminor(dev); 918 919 switch (infocmd) { 920 case DDI_INFO_DEVT2DEVINFO: 921 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 922 if (ahci_ctlp != NULL) { 923 *result = ahci_ctlp->ahcictl_dip; 924 return (DDI_SUCCESS); 925 } else { 926 *result = NULL; 927 return (DDI_FAILURE); 928 } 929 case DDI_INFO_DEVT2INSTANCE: 930 *(int *)result = instance; 931 break; 932 default: 933 break; 934 } 935 936 return (DDI_SUCCESS); 937 } 938 939 /* 940 * Registers the ahci with sata framework. 941 */ 942 static int 943 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 944 { 945 struct sata_hba_tran *sata_hba_tran; 946 947 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 948 "ahci_register_sata_hba_tran enter"); 949 950 mutex_enter(&ahci_ctlp->ahcictl_mutex); 951 952 /* Allocate memory for the sata_hba_tran */ 953 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 954 955 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 956 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 957 sata_hba_tran->sata_tran_hba_dma_attr = 958 &ahci_ctlp->ahcictl_buffer_dma_attr; 959 960 /* Report the number of implemented ports */ 961 sata_hba_tran->sata_tran_hba_num_cports = 962 ahci_ctlp->ahcictl_num_implemented_ports; 963 964 /* Support ATAPI device */ 965 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 966 967 /* Get the data transfer capability for PIO command by the HBA */ 968 if (cap_status & AHCI_HBA_CAP_PMD) { 969 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 970 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 971 "DRQ block data transfer for PIO command protocol"); 972 } else { 973 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA only supports single " 974 "DRQ block data transfer for PIO command protocol"); 975 } 976 977 /* 978 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 979 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 980 * QUEUED (EXT), and SERVICE commands). Queued operations are 981 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 982 * QUEUED commands when the HBA and device support native command 983 * queuing(NCQ). 984 * 985 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 986 * CAP register of the HBA indicates NCQ is supported. 987 * 988 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 989 * set because the previous register content of PxCI can be re-written 990 * in the register write. 991 */ 992 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 993 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 994 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 995 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 996 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 997 "Command Queuing"); 998 } 999 1000 /* Report the number of command slots */ 1001 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1002 1003 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1004 sata_hba_tran->sata_tran_start = ahci_tran_start; 1005 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1006 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1007 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1008 #ifdef __lock_lint 1009 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1010 #endif 1011 /* 1012 * When SATA framework adds support for pwrmgt the 1013 * pwrmgt_ops needs to be updated 1014 */ 1015 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1016 sata_hba_tran->sata_tran_ioctl = NULL; 1017 1018 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1019 1020 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1021 1022 /* Attach it to SATA framework */ 1023 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1024 != DDI_SUCCESS) { 1025 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1026 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1027 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1028 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1029 return (AHCI_FAILURE); 1030 } 1031 1032 return (AHCI_SUCCESS); 1033 } 1034 1035 /* 1036 * Unregisters the ahci with sata framework. 1037 */ 1038 static int 1039 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1040 { 1041 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1042 "ahci_unregister_sata_hba_tran enter"); 1043 1044 /* Detach from the SATA framework. */ 1045 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1046 DDI_SUCCESS) { 1047 return (AHCI_FAILURE); 1048 } 1049 1050 /* Deallocate sata_hba_tran. */ 1051 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1052 sizeof (sata_hba_tran_t)); 1053 1054 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1055 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1056 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1057 1058 return (AHCI_SUCCESS); 1059 } 1060 1061 /* 1062 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1063 * port status registers and an attached device type via sata_device 1064 * structure. 1065 * 1066 * We return the cached information from a previous hardware probe. The 1067 * actual hardware probing itself was done either from within 1068 * ahci_initialize_controller() during the driver attach or from a phy 1069 * ready change interrupt handler. 1070 */ 1071 static int 1072 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1073 { 1074 ahci_ctl_t *ahci_ctlp; 1075 ahci_port_t *ahci_portp; 1076 uint8_t cport = sd->satadev_addr.cport; 1077 uint8_t pmport = sd->satadev_addr.pmport; 1078 uint8_t qual = sd->satadev_addr.qual; 1079 uint8_t device_type; 1080 uint32_t port_state; 1081 uint8_t port; 1082 1083 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1084 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1085 1086 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1087 "ahci_tran_probe_port enter: cport: %d, " 1088 "pmport: %d, qual: %d", cport, pmport, qual); 1089 1090 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1091 1092 mutex_enter(&ahci_portp->ahciport_mutex); 1093 1094 port_state = ahci_portp->ahciport_port_state; 1095 switch (port_state) { 1096 1097 case SATA_PSTATE_FAILED: 1098 sd->satadev_state = SATA_PSTATE_FAILED; 1099 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1100 "ahci_tran_probe_port: port %d PORT FAILED", port); 1101 goto out; 1102 1103 case SATA_PSTATE_SHUTDOWN: 1104 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1105 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1106 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1107 goto out; 1108 1109 case SATA_PSTATE_PWROFF: 1110 sd->satadev_state = SATA_PSTATE_PWROFF; 1111 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1112 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1113 goto out; 1114 1115 case SATA_PSTATE_PWRON: 1116 sd->satadev_state = SATA_PSTATE_PWRON; 1117 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1118 "ahci_tran_probe_port: port %d PORT PWRON", port); 1119 break; 1120 1121 default: 1122 sd->satadev_state = port_state; 1123 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1124 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1125 port, port_state); 1126 break; 1127 } 1128 1129 device_type = ahci_portp->ahciport_device_type; 1130 1131 switch (device_type) { 1132 1133 case SATA_DTYPE_ATADISK: 1134 sd->satadev_type = SATA_DTYPE_ATADISK; 1135 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1136 "ahci_tran_probe_port: port %d DISK found", port); 1137 break; 1138 1139 case SATA_DTYPE_ATAPICD: 1140 sd->satadev_type = SATA_DTYPE_ATAPICD; 1141 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1142 "ahci_tran_probe_port: port %d ATAPI found", port); 1143 break; 1144 1145 case SATA_DTYPE_PMULT: 1146 sd->satadev_type = SATA_DTYPE_PMULT; 1147 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1148 "ahci_tran_probe_port: port %d Port Multiplier found", 1149 port); 1150 break; 1151 1152 case SATA_DTYPE_UNKNOWN: 1153 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1154 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1155 "ahci_tran_probe_port: port %d Unknown device found", port); 1156 break; 1157 1158 default: 1159 /* we don't support any other device types */ 1160 sd->satadev_type = SATA_DTYPE_NONE; 1161 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1162 "ahci_tran_probe_port: port %d No device found", port); 1163 break; 1164 } 1165 1166 out: 1167 ahci_update_sata_registers(ahci_ctlp, port, sd); 1168 mutex_exit(&ahci_portp->ahciport_mutex); 1169 1170 return (SATA_SUCCESS); 1171 } 1172 1173 /* 1174 * There are four operation modes in sata framework: 1175 * SATA_OPMODE_INTERRUPTS 1176 * SATA_OPMODE_POLLING 1177 * SATA_OPMODE_ASYNCH 1178 * SATA_OPMODE_SYNCH 1179 * 1180 * Their combined meanings as following: 1181 * 1182 * SATA_OPMODE_SYNCH 1183 * The command has to be completed before sata_tran_start functions returns. 1184 * Either interrupts or polling could be used - it's up to the driver. 1185 * Mode used currently for internal, sata-module initiated operations. 1186 * 1187 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1188 * It is the same as the one above. 1189 * 1190 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1191 * The command has to be completed before sata_tran_start function returns. 1192 * No interrupt used, polling only. This should be the mode used for scsi 1193 * packets with FLAG_NOINTR. 1194 * 1195 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1196 * The command may be queued (callback function specified). Interrupts could 1197 * be used. It's normal operation mode. 1198 */ 1199 /* 1200 * Called by sata framework to transport a sata packet down stream. 1201 */ 1202 static int 1203 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1204 { 1205 ahci_ctl_t *ahci_ctlp; 1206 ahci_port_t *ahci_portp; 1207 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1208 uint8_t port; 1209 1210 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1211 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1212 1213 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1214 "ahci_tran_start enter: cport %d satapkt 0x%p", 1215 cport, (void *)spkt); 1216 1217 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1218 1219 mutex_enter(&ahci_portp->ahciport_mutex); 1220 1221 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1222 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1223 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1224 /* 1225 * In case the targer driver would send the packet before 1226 * sata framework can have the opportunity to process those 1227 * event reports. 1228 */ 1229 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1230 spkt->satapkt_device.satadev_state = 1231 ahci_portp->ahciport_port_state; 1232 ahci_update_sata_registers(ahci_ctlp, port, 1233 &spkt->satapkt_device); 1234 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1235 "ahci_tran_start returning PORT_ERROR while " 1236 "port in FAILED/SHUTDOWN/PWROFF state: " 1237 "port: %d", port); 1238 mutex_exit(&ahci_portp->ahciport_mutex); 1239 return (SATA_TRAN_PORT_ERROR); 1240 } 1241 1242 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1243 /* 1244 * ahci_intr_phyrdy_change() may have rendered it to 1245 * SATA_DTYPE_NONE. 1246 */ 1247 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1248 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1249 spkt->satapkt_device.satadev_state = 1250 ahci_portp->ahciport_port_state; 1251 ahci_update_sata_registers(ahci_ctlp, port, 1252 &spkt->satapkt_device); 1253 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1254 "ahci_tran_start returning PORT_ERROR while " 1255 "no device attached: port: %d", port); 1256 mutex_exit(&ahci_portp->ahciport_mutex); 1257 return (SATA_TRAN_PORT_ERROR); 1258 } 1259 1260 /* 1261 * SATA HBA driver should remember that a device was reset and it 1262 * is supposed to reject any packets which do not specify either 1263 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1264 * 1265 * This is to prevent a race condition when a device was arbitrarily 1266 * reset by the HBA driver (and lost it's setting) and a target 1267 * driver sending some commands to a device before the sata framework 1268 * has a chance to restore the device setting (such as cache enable/ 1269 * disable or other resettable stuff). 1270 */ 1271 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1272 ahci_portp->ahciport_reset_in_progress = 0; 1273 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1274 "ahci_tran_start clearing the " 1275 "reset_in_progress for port: %d", port); 1276 } 1277 1278 if (ahci_portp->ahciport_reset_in_progress && 1279 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1280 ! ddi_in_panic()) { 1281 spkt->satapkt_reason = SATA_PKT_BUSY; 1282 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1283 "ahci_tran_start returning BUSY while " 1284 "reset in progress: port: %d", port); 1285 mutex_exit(&ahci_portp->ahciport_mutex); 1286 return (SATA_TRAN_BUSY); 1287 } 1288 1289 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1290 spkt->satapkt_reason = SATA_PKT_BUSY; 1291 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1292 "ahci_tran_start returning BUSY while " 1293 "mopping in progress: port: %d", port); 1294 mutex_exit(&ahci_portp->ahciport_mutex); 1295 return (SATA_TRAN_BUSY); 1296 } 1297 1298 if (spkt->satapkt_op_mode & 1299 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1300 /* We need to do the sync start now */ 1301 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1302 spkt) == AHCI_FAILURE) { 1303 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1304 "return QUEUE_FULL: port %d", port); 1305 mutex_exit(&ahci_portp->ahciport_mutex); 1306 return (SATA_TRAN_QUEUE_FULL); 1307 } 1308 } else { 1309 /* Async start, using interrupt */ 1310 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1311 == AHCI_FAILURE) { 1312 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1313 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1314 "returning QUEUE_FULL: port %d", port); 1315 mutex_exit(&ahci_portp->ahciport_mutex); 1316 return (SATA_TRAN_QUEUE_FULL); 1317 } 1318 } 1319 1320 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1321 "sata tran accepted: port %d", port); 1322 1323 mutex_exit(&ahci_portp->ahciport_mutex); 1324 return (SATA_TRAN_ACCEPTED); 1325 } 1326 1327 /* 1328 * SATA_OPMODE_SYNCH flag is set 1329 * 1330 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1331 * without interrupt, otherwise we can still use the interrupt. 1332 * 1333 * WARNING!!! ahciport_mutex should be acquired before the function 1334 * is called. 1335 */ 1336 static int 1337 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1338 uint8_t port, sata_pkt_t *spkt) 1339 { 1340 int pkt_timeout_ticks; 1341 uint32_t timeout_tags; 1342 int rval; 1343 1344 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1345 "port %d spkt 0x%p", port, spkt); 1346 1347 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1348 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1349 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1350 port, spkt)) == AHCI_FAILURE) { 1351 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1352 return (rval); 1353 } 1354 1355 pkt_timeout_ticks = 1356 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1357 1358 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1359 mutex_exit(&ahci_portp->ahciport_mutex); 1360 1361 /* Simulate the interrupt */ 1362 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1363 1364 drv_usecwait(AHCI_1MS_USECS); 1365 1366 mutex_enter(&ahci_portp->ahciport_mutex); 1367 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1368 if (pkt_timeout_ticks < 0) { 1369 cmn_err(CE_NOTE, "!ahci_do_sync_start: " 1370 "port %d satapkt 0x%p timed out\n", 1371 port, (void *)spkt); 1372 timeout_tags = (0x1 << rval); 1373 mutex_exit(&ahci_portp->ahciport_mutex); 1374 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1375 port, timeout_tags); 1376 mutex_enter(&ahci_portp->ahciport_mutex); 1377 } 1378 } 1379 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1380 return (AHCI_SUCCESS); 1381 1382 } else { 1383 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1384 port, spkt)) == AHCI_FAILURE) 1385 return (rval); 1386 1387 #if AHCI_DEBUG 1388 /* 1389 * Note that the driver always uses the slot 0 to deliver 1390 * REQUEST SENSE or READ LOG EXT command 1391 */ 1392 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1393 ASSERT(rval == 0); 1394 #endif 1395 1396 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1397 cv_wait(&ahci_portp->ahciport_cv, 1398 &ahci_portp->ahciport_mutex); 1399 1400 return (AHCI_SUCCESS); 1401 } 1402 } 1403 1404 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1405 if (satapkt) { \ 1406 satapkt->satapkt_reason = reason; \ 1407 /* \ 1408 * We set the satapkt_reason in both sync and \ 1409 * non-sync cases. \ 1410 */ \ 1411 } \ 1412 if (satapkt && \ 1413 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1414 satapkt->satapkt_comp) { \ 1415 mutex_exit(&ahci_portp->ahciport_mutex); \ 1416 (*satapkt->satapkt_comp)(satapkt); \ 1417 mutex_enter(&ahci_portp->ahciport_mutex); \ 1418 } else { \ 1419 if (satapkt && \ 1420 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1421 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1422 cv_signal(&ahci_portp->ahciport_cv); \ 1423 } 1424 1425 /* 1426 * Searches for and claims a free command slot. 1427 * 1428 * Returns: 1429 * 1430 * AHCI_FAILURE if failed 1431 * 1. if no empty slot left 1432 * 2. non-queued command requested while queued command(s) is outstanding 1433 * 3. queued command requested whild non-queued command(s) is outstanding 1434 * 4. HBA doesn't support multiple-use of command list while already a 1435 * non-queued command is oustanding 1436 * 1437 * claimed slot number if succeeded 1438 * 1439 * NOTE: it will always return slot 0 during error recovery process for 1440 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1441 * 1442 * WARNING!!! ahciport_mutex should be acquired before the function 1443 * is called. 1444 */ 1445 /*ARGSUSED*/ 1446 static int 1447 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1448 ahci_port_t *ahci_portp, int command_type) 1449 { 1450 uint32_t free_slots; 1451 int slot; 1452 1453 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1454 "ahciport_pending_tags = 0x%x " 1455 "ahciport_pending_ncq_tags = 0x%x", 1456 ahci_portp->ahciport_pending_tags, 1457 ahci_portp->ahciport_pending_ncq_tags); 1458 1459 /* 1460 * According to the AHCI spec, system software is responsible to 1461 * ensure that queued and non-queued commands are not mixed in 1462 * the command list. 1463 */ 1464 if (command_type == AHCI_NON_NCQ_CMD) { 1465 /* Non-NCQ command request */ 1466 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1467 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1468 "ahci_claim_free_slot: there is still pending " 1469 "queued command(s) in the command list, " 1470 "so no available slot for the non-queued " 1471 "command"); 1472 return (AHCI_FAILURE); 1473 } 1474 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1475 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1476 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1477 "ahci_claim_free_slot: HBA cannot support multiple-" 1478 "use of the command list for non-queued commands"); 1479 return (AHCI_FAILURE); 1480 } 1481 free_slots = (~ahci_portp->ahciport_pending_tags) & 1482 AHCI_SLOT_MASK(ahci_ctlp); 1483 } else if (command_type == AHCI_NCQ_CMD) { 1484 /* NCQ command request */ 1485 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1486 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1487 "ahci_claim_free_slot: there is still pending " 1488 "non-queued command(s) in the command list, " 1489 "so no available slot for the queued command"); 1490 return (AHCI_FAILURE); 1491 } 1492 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1493 AHCI_NCQ_SLOT_MASK(ahci_portp); 1494 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1495 /* Error retrieval command request */ 1496 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1497 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1498 "SENSE or READ LOG EXT command"); 1499 slot = 0; 1500 goto out; 1501 } 1502 1503 slot = ddi_ffs(free_slots) - 1; 1504 if (slot == -1) { 1505 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1506 "ahci_claim_free_slot: no empty slots"); 1507 return (AHCI_FAILURE); 1508 } 1509 1510 /* 1511 * According to the AHCI spec, to allow a simple mechanism for the 1512 * HBA to map command list slots to queue entries, software must 1513 * match the tag number it uses to the slot it is placing the command 1514 * in. For example, if a queued command is placed in slot 5, the tag 1515 * for that command must be 5. 1516 */ 1517 if (command_type == AHCI_NCQ_CMD) { 1518 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1519 } 1520 1521 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1522 1523 out: 1524 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1525 "ahci_claim_free_slot: found slot: 0x%x", slot); 1526 1527 return (slot); 1528 } 1529 1530 /* 1531 * Builds the Command Table for the sata packet and delivers it to controller. 1532 * 1533 * Returns: 1534 * slot number if we can obtain a slot successfully 1535 * otherwise, return AHCI_FAILURE 1536 * 1537 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1538 */ 1539 static int 1540 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1541 uint8_t port, sata_pkt_t *spkt) 1542 { 1543 int cmd_slot; 1544 sata_cmd_t *scmd; 1545 ahci_fis_h2d_register_t *h2d_register_fisp; 1546 ahci_cmd_table_t *cmd_table; 1547 ahci_cmd_header_t *cmd_header; 1548 int ncookies; 1549 int i; 1550 int command_type = AHCI_NON_NCQ_CMD; 1551 int ncq_qdepth; 1552 #if AHCI_DEBUG 1553 uint32_t *ptr; 1554 uint8_t *ptr2; 1555 #endif 1556 1557 spkt->satapkt_reason = SATA_PKT_BUSY; 1558 1559 scmd = &spkt->satapkt_cmd; 1560 1561 /* Check if the command is a NCQ command */ 1562 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1563 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1564 command_type = AHCI_NCQ_CMD; 1565 1566 /* 1567 * When NCQ is support, system software must determine the 1568 * maximum tag allowed by the device and the HBA, and it 1569 * must use a value not beyond of the lower bound of the two. 1570 * 1571 * Sata module is going to calculate the qdepth and send 1572 * down to HBA driver via sata_cmd. 1573 */ 1574 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1575 1576 /* 1577 * At the moment, the driver doesn't support the dynamic 1578 * setting of the maximum ncq depth, and the value can be 1579 * set either during the attach or after hot-plug insertion. 1580 */ 1581 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1582 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1583 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1584 "ahci_deliver_satapkt: port %d the max tags for " 1585 "NCQ command is %d", port, ncq_qdepth); 1586 } else { 1587 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1588 cmn_err(CE_WARN, "ahci_deliver_satapkt: port " 1589 "%d the max tag for NCQ command is " 1590 "requested to change from %d to %d, at the" 1591 " moment the driver doesn't support the " 1592 "dynamic change so it's going to " 1593 "still use the previous tag value", port, 1594 ahci_portp->ahciport_max_ncq_tags, 1595 ncq_qdepth); 1596 } 1597 } 1598 } 1599 1600 /* Check if the command is an error retrieval command */ 1601 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1602 command_type = AHCI_ERR_RETRI_CMD; 1603 1604 /* Check if there is an empty command slot */ 1605 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1606 if (cmd_slot == AHCI_FAILURE) { 1607 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1608 return (AHCI_FAILURE); 1609 } 1610 1611 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1612 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1613 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1614 cmd_slot, port, (void *)spkt); 1615 1616 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1617 bzero((void *)cmd_table, ahci_cmd_table_size); 1618 1619 /* For data transfer operations, it is the H2D Register FIS */ 1620 h2d_register_fisp = 1621 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1622 1623 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1624 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1625 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1626 SET_FIS_PMP(h2d_register_fisp, 1627 spkt->satapkt_device.satadev_addr.pmport); 1628 } 1629 1630 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1631 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1632 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1633 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1634 1635 switch (scmd->satacmd_addr_type) { 1636 1637 case 0: 1638 /* 1639 * satacmd_addr_type will be 0 for the commands below: 1640 * ATAPI command 1641 * SATAC_IDLE_IM 1642 * SATAC_STANDBY_IM 1643 * SATAC_DOWNLOAD_MICROCODE 1644 * SATAC_FLUSH_CACHE 1645 * SATAC_SET_FEATURES 1646 * SATAC_SMART 1647 * SATAC_ID_PACKET_DEVICE 1648 * SATAC_ID_DEVICE 1649 */ 1650 /* fallthrough */ 1651 1652 case ATA_ADDR_LBA: 1653 /* fallthrough */ 1654 1655 case ATA_ADDR_LBA28: 1656 /* LBA[7:0] */ 1657 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1658 1659 /* LBA[15:8] */ 1660 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1661 1662 /* LBA[23:16] */ 1663 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1664 1665 /* LBA [27:24] (also called dev_head) */ 1666 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1667 1668 break; 1669 1670 case ATA_ADDR_LBA48: 1671 /* LBA[7:0] */ 1672 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1673 1674 /* LBA[15:8] */ 1675 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1676 1677 /* LBA[23:16] */ 1678 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1679 1680 /* LBA [31:24] */ 1681 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1682 scmd->satacmd_lba_low_msb); 1683 1684 /* LBA [39:32] */ 1685 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1686 scmd->satacmd_lba_mid_msb); 1687 1688 /* LBA [47:40] */ 1689 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1690 scmd->satacmd_lba_high_msb); 1691 1692 /* Set dev_head */ 1693 SET_FIS_DEV_HEAD(h2d_register_fisp, 1694 scmd->satacmd_device_reg); 1695 1696 /* Set the extended sector count and features */ 1697 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1698 scmd->satacmd_sec_count_msb); 1699 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1700 scmd->satacmd_features_reg_ext); 1701 break; 1702 } 1703 1704 /* 1705 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1706 * filled into features field, and sector count 8:15 is filled into 1707 * features (exp) field. TAG is filled into sector field. 1708 */ 1709 if (command_type == AHCI_NCQ_CMD) { 1710 SET_FIS_FEATURES(h2d_register_fisp, 1711 scmd->satacmd_sec_count_lsb); 1712 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1713 scmd->satacmd_sec_count_msb); 1714 1715 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1716 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1717 } 1718 1719 ncookies = scmd->satacmd_num_dma_cookies; 1720 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1721 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1722 ncookies, ahci_dma_prdt_number); 1723 1724 ASSERT(ncookies <= ahci_dma_prdt_number); 1725 1726 /* *** now fill the scatter gather list ******* */ 1727 for (i = 0; i < ncookies; i++) { 1728 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1729 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1730 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1731 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1732 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1733 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1734 } 1735 1736 /* The ACMD field is filled in for ATAPI command */ 1737 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1738 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1739 SATA_ATAPI_MAX_CDB_LEN); 1740 } 1741 1742 /* Set Command Header in Command List */ 1743 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1744 BZERO_DESCR_INFO(cmd_header); 1745 BZERO_PRD_BYTE_COUNT(cmd_header); 1746 1747 /* Set the number of entries in the PRD table */ 1748 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1749 1750 /* Set the length of the command in the CFIS area */ 1751 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1752 1753 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1754 "sata_data_direction = 0x%x", 1755 scmd->satacmd_flags.sata_data_direction); 1756 1757 /* Set A bit if it is an ATAPI command */ 1758 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1759 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1760 1761 /* Set W bit if data is going to the device */ 1762 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1763 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1764 1765 /* 1766 * Set the prefetchable bit - this bit is only valid if the PRDTL 1767 * field is non-zero or the ATAPI 'A' bit is set in the command 1768 * header. This bit cannot be set when using native command 1769 * queuing commands or when using FIS-based switching with a Port 1770 * multiplier. 1771 */ 1772 if (command_type != AHCI_NCQ_CMD) 1773 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1774 1775 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1776 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1777 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1778 1779 /* 1780 * We are overloading satapkt_hba_driver_private with 1781 * watched_cycle count. 1782 */ 1783 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1784 1785 #if AHCI_DEBUG 1786 /* Dump the command header and table */ 1787 AHCIDBG0(AHCIDBG_COMMAND, ahci_ctlp, "\n"); 1788 AHCIDBG3(AHCIDBG_COMMAND, ahci_ctlp, 1789 "Command header&table for spkt 0x%p cmd_reg 0x%x port %d", 1790 spkt, scmd->satacmd_cmd_reg, port); 1791 ptr = (uint32_t *)cmd_header; 1792 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1793 " Command Header:%8x %8x %8x %8x", 1794 ptr[0], ptr[1], ptr[2], ptr[3]); 1795 1796 /* Dump the H2D register FIS */ 1797 ptr = (uint32_t *)h2d_register_fisp; 1798 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1799 " Command FIS: %8x %8x %8x %8x", 1800 ptr[0], ptr[1], ptr[2], ptr[3]); 1801 1802 /* Dump the ACMD register FIS */ 1803 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1804 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1805 if (ahci_debug_flags & AHCIDBG_COMMAND) 1806 ahci_log(ahci_ctlp, CE_WARN, 1807 " ATAPI command: %2x %2x %2x %2x " 1808 "%2x %2x %2x %2x", 1809 ptr2[8 * i], ptr2[8 * i + 1], 1810 ptr2[8 * i + 2], ptr2[8 * i + 3], 1811 ptr2[8 * i + 4], ptr2[8 * i + 5], 1812 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1813 1814 /* Dump the PRDT */ 1815 for (i = 0; i < ncookies; i++) { 1816 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1817 AHCIDBG5(AHCIDBG_COMMAND, ahci_ctlp, 1818 " Cookie %d: %8x %8x %8x %8x", 1819 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1820 } 1821 #endif 1822 1823 (void) ddi_dma_sync( 1824 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1825 0, 1826 ahci_cmd_table_size, 1827 DDI_DMA_SYNC_FORDEV); 1828 1829 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1830 cmd_slot * sizeof (ahci_cmd_header_t), 1831 sizeof (ahci_cmd_header_t), 1832 DDI_DMA_SYNC_FORDEV); 1833 1834 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1835 if (command_type == AHCI_NCQ_CMD) { 1836 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1837 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1838 (0x1 << cmd_slot)); 1839 } 1840 1841 /* Indicate to the HBA that a command is active. */ 1842 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1843 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1844 (0x1 << cmd_slot)); 1845 1846 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1847 "exit: port %d", port); 1848 1849 return (cmd_slot); 1850 } 1851 1852 /* 1853 * Called by the sata framework to abort the previously sent packet(s). 1854 * 1855 * Reset device to abort commands. 1856 */ 1857 static int 1858 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1859 { 1860 ahci_ctl_t *ahci_ctlp; 1861 ahci_port_t *ahci_portp; 1862 uint32_t slot_status = 0; 1863 uint32_t aborted_tags = 0; 1864 uint32_t finished_tags = 0; 1865 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1866 uint8_t port; 1867 int tmp_slot; 1868 1869 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1870 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1871 1872 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1873 "ahci_tran_abort enter: port %d", port); 1874 1875 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1876 mutex_enter(&ahci_portp->ahciport_mutex); 1877 1878 /* 1879 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1880 * commands are being mopped, therefore there is nothing else to do 1881 */ 1882 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1883 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1884 "ahci_tran_abort: port %d is in " 1885 "mopping process, so just return directly ", port); 1886 mutex_exit(&ahci_portp->ahciport_mutex); 1887 return (SATA_SUCCESS); 1888 } 1889 1890 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1891 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1892 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1893 /* 1894 * In case the targer driver would send the request before 1895 * sata framework can have the opportunity to process those 1896 * event reports. 1897 */ 1898 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1899 spkt->satapkt_device.satadev_state = 1900 ahci_portp->ahciport_port_state; 1901 ahci_update_sata_registers(ahci_ctlp, port, 1902 &spkt->satapkt_device); 1903 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1904 "ahci_tran_abort returning SATA_FAILURE while " 1905 "port in FAILED/SHUTDOWN/PWROFF state: " 1906 "port: %d", port); 1907 mutex_exit(&ahci_portp->ahciport_mutex); 1908 return (SATA_FAILURE); 1909 } 1910 1911 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1912 /* 1913 * ahci_intr_phyrdy_change() may have rendered it to 1914 * AHCI_PORT_TYPE_NODEV. 1915 */ 1916 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1917 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1918 spkt->satapkt_device.satadev_state = 1919 ahci_portp->ahciport_port_state; 1920 ahci_update_sata_registers(ahci_ctlp, port, 1921 &spkt->satapkt_device); 1922 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1923 "ahci_tran_abort returning SATA_FAILURE while " 1924 "no device attached: port: %d", port); 1925 mutex_exit(&ahci_portp->ahciport_mutex); 1926 return (SATA_FAILURE); 1927 } 1928 1929 if (flag == SATA_ABORT_ALL_PACKETS) { 1930 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1931 aborted_tags = ahci_portp->ahciport_pending_tags; 1932 1933 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1934 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 1935 1936 cmn_err(CE_NOTE, "!ahci port %d abort all packets", port); 1937 } else { 1938 aborted_tags = 0xffffffff; 1939 /* 1940 * Aborting one specific packet, first search the 1941 * ahciport_slot_pkts[] list for matching spkt. 1942 */ 1943 for (tmp_slot = 0; 1944 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 1945 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 1946 aborted_tags = (0x1 << tmp_slot); 1947 break; 1948 } 1949 } 1950 1951 if (aborted_tags == 0xffffffff) { 1952 /* request packet is not on the pending list */ 1953 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1954 "Cannot find the aborting pkt 0x%p on the " 1955 "pending list", (void *)spkt); 1956 ahci_update_sata_registers(ahci_ctlp, port, 1957 &spkt->satapkt_device); 1958 mutex_exit(&ahci_portp->ahciport_mutex); 1959 return (SATA_FAILURE); 1960 } 1961 cmn_err(CE_NOTE, "!ahci port %d abort satapkt 0x%p", 1962 port, (void *)spkt); 1963 } 1964 1965 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1966 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1967 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1968 1969 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1970 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1971 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 1972 1973 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 1974 ahci_portp->ahciport_mop_in_progress++; 1975 1976 /* 1977 * To abort the packet(s), first we are trying to clear PxCMD.ST 1978 * to stop the port, and if the port can be stopped 1979 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 1980 * then we just send back the aborted packet(s) with ABORTED flag 1981 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 1982 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 1983 * perform a COMRESET. 1984 */ 1985 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 1986 ahci_portp, port, NULL, NULL); 1987 1988 /* 1989 * Compute which have finished and which need to be retried. 1990 * 1991 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 1992 * minus the slot_status. The aborted_tags has to be deducted by 1993 * finished_tags since we can't possibly abort a tag which had finished 1994 * already. 1995 */ 1996 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1997 finished_tags = ahci_portp->ahciport_pending_tags & 1998 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1999 2000 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2001 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2002 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2003 2004 aborted_tags &= ~finished_tags; 2005 2006 ahci_mop_commands(ahci_ctlp, 2007 ahci_portp, 2008 port, 2009 slot_status, 2010 0, /* failed tags */ 2011 0, /* timeout tags */ 2012 aborted_tags, 2013 0); /* reset tags */ 2014 2015 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2016 mutex_exit(&ahci_portp->ahciport_mutex); 2017 2018 return (SATA_SUCCESS); 2019 } 2020 2021 /* 2022 * Used to do device reset and reject all the pending packets on a device 2023 * during the reset operation. 2024 * 2025 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2026 */ 2027 static int 2028 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2029 ahci_port_t *ahci_portp, uint8_t port) 2030 { 2031 uint32_t slot_status = 0; 2032 uint32_t reset_tags = 0; 2033 uint32_t finished_tags = 0; 2034 sata_device_t sdevice; 2035 int ret; 2036 2037 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2038 "ahci_reset_device_reject_pkts on port: %d", port); 2039 2040 /* 2041 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2042 * commands are being mopped, therefore there is nothing else to do 2043 */ 2044 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2045 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2046 "ahci_reset_device_reject_pkts: port %d is in " 2047 "mopping process, so return directly ", port); 2048 return (SATA_SUCCESS); 2049 } 2050 2051 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2052 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2053 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2054 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2055 } 2056 2057 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2058 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2059 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2060 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2061 } 2062 2063 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2064 != AHCI_SUCCESS) { 2065 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2066 "Try to do a port reset after software " 2067 "reset failed", port); 2068 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2069 if (ret != AHCI_SUCCESS) { 2070 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2071 "ahci_reset_device_reject_pkts: port %d " 2072 "failed", port); 2073 return (SATA_FAILURE); 2074 } 2075 } 2076 /* Set the reset in progress flag */ 2077 ahci_portp->ahciport_reset_in_progress = 1; 2078 2079 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2080 ahci_portp->ahciport_mop_in_progress++; 2081 2082 /* Indicate to the framework that a reset has happened */ 2083 bzero((void *)&sdevice, sizeof (sata_device_t)); 2084 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2085 sdevice.satadev_addr.pmport = 0; 2086 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2087 2088 sdevice.satadev_state = SATA_DSTATE_RESET | 2089 SATA_DSTATE_PWR_ACTIVE; 2090 mutex_exit(&ahci_portp->ahciport_mutex); 2091 sata_hba_event_notify( 2092 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2093 &sdevice, 2094 SATA_EVNT_DEVICE_RESET); 2095 mutex_enter(&ahci_portp->ahciport_mutex); 2096 2097 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2098 "port %d sending event up: SATA_EVNT_RESET", port); 2099 2100 /* Next try to mop the pending commands */ 2101 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2102 finished_tags = ahci_portp->ahciport_pending_tags & 2103 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2104 2105 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2106 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2107 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2108 2109 reset_tags &= ~finished_tags; 2110 2111 ahci_mop_commands(ahci_ctlp, 2112 ahci_portp, 2113 port, 2114 slot_status, 2115 0, /* failed tags */ 2116 0, /* timeout tags */ 2117 0, /* aborted tags */ 2118 reset_tags); /* reset tags */ 2119 2120 return (SATA_SUCCESS); 2121 } 2122 2123 /* 2124 * Used to do port reset and reject all the pending packets on a port during 2125 * the reset operation. 2126 * 2127 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2128 */ 2129 static int 2130 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2131 ahci_port_t *ahci_portp, uint8_t port) 2132 { 2133 uint32_t slot_status = 0; 2134 uint32_t reset_tags = 0; 2135 uint32_t finished_tags = 0; 2136 2137 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2138 "ahci_reset_port_reject_pkts on port: %d", port); 2139 2140 /* 2141 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2142 * commands are being mopped, therefore there is nothing else to do 2143 */ 2144 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2145 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2146 "ahci_reset_port_reject_pkts: port %d is in " 2147 "mopping process, so return directly ", port); 2148 return (SATA_SUCCESS); 2149 } 2150 2151 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2152 ahci_portp->ahciport_mop_in_progress++; 2153 2154 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2155 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2156 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2157 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2158 } 2159 2160 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2161 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2162 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2163 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2164 } 2165 2166 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2167 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2168 NULL) != AHCI_SUCCESS) 2169 return (SATA_FAILURE); 2170 2171 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2172 finished_tags = ahci_portp->ahciport_pending_tags & 2173 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2174 2175 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2176 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2177 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2178 2179 reset_tags &= ~finished_tags; 2180 2181 ahci_mop_commands(ahci_ctlp, 2182 ahci_portp, 2183 port, 2184 slot_status, 2185 0, /* failed tags */ 2186 0, /* timeout tags */ 2187 0, /* aborted tags */ 2188 reset_tags); /* reset tags */ 2189 2190 return (SATA_SUCCESS); 2191 } 2192 2193 /* 2194 * Used to do hba reset and reject all the pending packets on all ports 2195 * during the reset operation. 2196 */ 2197 static int 2198 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2199 { 2200 ahci_port_t *ahci_portp; 2201 uint32_t slot_status[AHCI_MAX_PORTS]; 2202 uint32_t reset_tags[AHCI_MAX_PORTS]; 2203 uint32_t finished_tags[AHCI_MAX_PORTS]; 2204 uint8_t port; 2205 int ret = SATA_SUCCESS; 2206 2207 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2208 "ahci_reset_hba_reject_pkts enter"); 2209 2210 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2211 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2212 continue; 2213 } 2214 2215 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2216 2217 mutex_enter(&ahci_portp->ahciport_mutex); 2218 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2219 slot_status[port] = ddi_get32( 2220 ahci_ctlp->ahcictl_ahci_acc_handle, 2221 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2222 reset_tags[port] = slot_status[port] & 2223 AHCI_SLOT_MASK(ahci_ctlp); 2224 } 2225 2226 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2227 slot_status[port] = ddi_get32( 2228 ahci_ctlp->ahcictl_ahci_acc_handle, 2229 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2230 reset_tags[port] = slot_status[port] & 2231 AHCI_NCQ_SLOT_MASK(ahci_portp); 2232 } 2233 mutex_exit(&ahci_portp->ahciport_mutex); 2234 } 2235 2236 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2237 ret = SATA_FAILURE; 2238 goto out; 2239 } 2240 2241 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2242 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2243 continue; 2244 } 2245 2246 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2247 2248 mutex_enter(&ahci_portp->ahciport_mutex); 2249 /* 2250 * To prevent recursive enter to ahci_mop_commands, we need 2251 * check AHCI_PORT_FLAG_MOPPING flag. 2252 */ 2253 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2254 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2255 "ahci_reset_hba_reject_pkts: port %d is in " 2256 "mopping process, so return directly ", port); 2257 mutex_exit(&ahci_portp->ahciport_mutex); 2258 continue; 2259 } 2260 2261 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2262 ahci_portp->ahciport_mop_in_progress++; 2263 2264 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2265 finished_tags[port] = 2266 ahci_portp->ahciport_pending_tags & 2267 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2268 2269 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2270 finished_tags[port] = 2271 ahci_portp->ahciport_pending_ncq_tags & 2272 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2273 2274 reset_tags[port] &= ~finished_tags[port]; 2275 2276 ahci_mop_commands(ahci_ctlp, 2277 ahci_portp, 2278 port, 2279 slot_status[port], 2280 0, /* failed tags */ 2281 0, /* timeout tags */ 2282 0, /* aborted tags */ 2283 reset_tags[port]); /* reset tags */ 2284 mutex_exit(&ahci_portp->ahciport_mutex); 2285 } 2286 out: 2287 return (ret); 2288 } 2289 2290 /* 2291 * Called by sata framework to reset a port(s) or device. 2292 */ 2293 static int 2294 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2295 { 2296 ahci_ctl_t *ahci_ctlp; 2297 ahci_port_t *ahci_portp; 2298 uint8_t cport = sd->satadev_addr.cport; 2299 uint8_t port; 2300 int ret = SATA_SUCCESS; 2301 2302 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2303 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2304 2305 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2306 "ahci_tran_reset_port enter: cport: %d", cport); 2307 2308 switch (sd->satadev_addr.qual) { 2309 case SATA_ADDR_CPORT: 2310 /* Port reset */ 2311 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2312 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2313 "reset port", port); 2314 2315 mutex_enter(&ahci_portp->ahciport_mutex); 2316 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2317 mutex_exit(&ahci_portp->ahciport_mutex); 2318 2319 break; 2320 2321 case SATA_ADDR_DCPORT: 2322 /* Device reset */ 2323 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2324 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2325 "reset device", port); 2326 2327 mutex_enter(&ahci_portp->ahciport_mutex); 2328 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2329 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2330 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2331 /* 2332 * In case the targer driver would send the request 2333 * before sata framework can have the opportunity to 2334 * process those event reports. 2335 */ 2336 sd->satadev_state = ahci_portp->ahciport_port_state; 2337 ahci_update_sata_registers(ahci_ctlp, port, sd); 2338 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2339 "ahci_tran_reset_dport returning SATA_FAILURE " 2340 "while port in FAILED/SHUTDOWN/PWROFF state: " 2341 "port: %d", port); 2342 mutex_exit(&ahci_portp->ahciport_mutex); 2343 ret = SATA_FAILURE; 2344 break; 2345 } 2346 2347 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2348 /* 2349 * ahci_intr_phyrdy_change() may have rendered it to 2350 * AHCI_PORT_TYPE_NODEV. 2351 */ 2352 sd->satadev_type = SATA_DTYPE_NONE; 2353 sd->satadev_state = ahci_portp->ahciport_port_state; 2354 ahci_update_sata_registers(ahci_ctlp, port, sd); 2355 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2356 "ahci_tran_reset_dport returning SATA_FAILURE " 2357 "while no device attached: port: %d", port); 2358 mutex_exit(&ahci_portp->ahciport_mutex); 2359 ret = SATA_FAILURE; 2360 break; 2361 } 2362 2363 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2364 ahci_portp, port); 2365 mutex_exit(&ahci_portp->ahciport_mutex); 2366 break; 2367 2368 case SATA_ADDR_CNTRL: 2369 /* Reset the whole controller */ 2370 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2371 "reset the whole hba", port); 2372 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2373 break; 2374 2375 case SATA_ADDR_PMPORT: 2376 case SATA_ADDR_DPMPORT: 2377 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2378 "ahci_tran_reset_dport: port multiplier will be " 2379 "supported later"); 2380 /* FALLSTHROUGH */ 2381 default: 2382 ret = SATA_FAILURE; 2383 } 2384 2385 return (ret); 2386 } 2387 2388 /* 2389 * Called by sata framework to activate a port as part of hotplug. 2390 * (cfgadm -c connect satax/y) 2391 * Note: Not port-mult aware. 2392 */ 2393 static int 2394 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2395 { 2396 ahci_ctl_t *ahci_ctlp; 2397 ahci_port_t *ahci_portp; 2398 uint8_t cport = satadev->satadev_addr.cport; 2399 uint8_t port; 2400 2401 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2402 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2403 2404 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2405 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2406 2407 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2408 2409 mutex_enter(&ahci_portp->ahciport_mutex); 2410 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2411 cmn_err(CE_NOTE, "!ahci port %d is activated", port); 2412 2413 /* 2414 * Reset the port so that the PHY communication would be re-established. 2415 * But this reset is an internal operation and the sata module doesn't 2416 * need to know about it. Moreover, the port with a device attached will 2417 * be started too. 2418 */ 2419 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2420 ahci_portp, port, 2421 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2422 NULL); 2423 2424 /* 2425 * Need to check the link status and device status of the port 2426 * and consider raising power if the port was in D3 state 2427 */ 2428 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2429 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2430 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2431 2432 satadev->satadev_state = ahci_portp->ahciport_port_state; 2433 2434 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2435 2436 mutex_exit(&ahci_portp->ahciport_mutex); 2437 return (SATA_SUCCESS); 2438 } 2439 2440 /* 2441 * Called by sata framework to deactivate a port as part of hotplug. 2442 * (cfgadm -c disconnect satax/y) 2443 * Note: Not port-mult aware. 2444 */ 2445 static int 2446 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2447 { 2448 ahci_ctl_t *ahci_ctlp; 2449 ahci_port_t *ahci_portp; 2450 uint8_t cport = satadev->satadev_addr.cport; 2451 uint8_t port; 2452 uint32_t port_scontrol; 2453 2454 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2455 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2456 2457 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2458 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2459 2460 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2461 2462 mutex_enter(&ahci_portp->ahciport_mutex); 2463 cmn_err(CE_NOTE, "!ahci port %d is deactivated", port); 2464 2465 /* Disable the interrupts on the port */ 2466 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2467 2468 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2469 goto phy_offline; 2470 } 2471 2472 /* First to abort all the pending commands */ 2473 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2474 2475 /* Then stop the port */ 2476 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2477 ahci_portp, port); 2478 2479 /* Next put the PHY offline */ 2480 2481 phy_offline: 2482 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2483 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2484 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2485 2486 /* Update ahciport_port_state */ 2487 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2488 satadev->satadev_state = ahci_portp->ahciport_port_state; 2489 2490 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2491 2492 mutex_exit(&ahci_portp->ahciport_mutex); 2493 return (SATA_SUCCESS); 2494 } 2495 2496 /* 2497 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2498 * when a device is unplugged or a port is deactivated. 2499 * 2500 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2501 */ 2502 static void 2503 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2504 ahci_port_t *ahci_portp, uint8_t port) 2505 { 2506 uint32_t slot_status = 0; 2507 uint32_t abort_tags = 0; 2508 2509 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2510 "ahci_reject_all_abort_pkts on port: %d", port); 2511 2512 /* 2513 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2514 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2515 * to get the error data, if yes when the device is removed, the 2516 * command needs to be aborted too. 2517 */ 2518 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2519 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2520 slot_status = 0x1; 2521 abort_tags = 0x1; 2522 goto out; 2523 } else { 2524 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2525 "ahci_reject_all_abort_pkts return directly " 2526 "port %d no needs to reject any outstanding " 2527 "commands", port); 2528 return; 2529 } 2530 } 2531 2532 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2533 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2534 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2535 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2536 } 2537 2538 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2539 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2540 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2541 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2542 } 2543 2544 out: 2545 /* No need to do mop when there is no outstanding commands */ 2546 if (slot_status != 0) { 2547 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2548 ahci_portp->ahciport_mop_in_progress++; 2549 2550 ahci_mop_commands(ahci_ctlp, 2551 ahci_portp, 2552 port, 2553 slot_status, 2554 0, /* failed tags */ 2555 0, /* timeout tags */ 2556 abort_tags, /* aborting tags */ 2557 0); /* reset tags */ 2558 } 2559 } 2560 2561 #if defined(__lock_lint) 2562 static int 2563 ahci_selftest(dev_info_t *dip, sata_device_t *device) 2564 { 2565 return (SATA_SUCCESS); 2566 } 2567 #endif 2568 2569 /* 2570 * Allocate the ports structure, only called by ahci_attach 2571 */ 2572 static int 2573 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2574 { 2575 int port, cport = 0; 2576 2577 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2578 "ahci_alloc_ports_state enter"); 2579 2580 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2581 2582 /* Allocate structures only for the implemented ports */ 2583 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2584 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2585 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2586 "hba port %d not implemented", port); 2587 continue; 2588 } 2589 2590 #ifndef __lock_lint 2591 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2592 ahci_ctlp->ahcictl_port_to_cport[port] = 2593 (uint8_t)cport++; 2594 #endif /* __lock_lint */ 2595 2596 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2597 goto err_out; 2598 } 2599 } 2600 2601 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2602 return (AHCI_SUCCESS); 2603 2604 err_out: 2605 for (port--; port >= 0; port--) { 2606 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2607 ahci_dealloc_port_state(ahci_ctlp, port); 2608 } 2609 } 2610 2611 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2612 return (AHCI_FAILURE); 2613 } 2614 2615 /* 2616 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2617 */ 2618 static void 2619 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2620 { 2621 int port; 2622 2623 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2624 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2625 /* if this port is implemented by the HBA */ 2626 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2627 ahci_dealloc_port_state(ahci_ctlp, port); 2628 } 2629 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2630 } 2631 2632 /* 2633 * Initialize the controller and all ports. And then try to start the ports 2634 * if there are devices attached. 2635 * 2636 * This routine can be called from three seperate cases: DDI_ATTACH, 2637 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2638 * other two cases; device signature probing are attempted only during 2639 * DDI_ATTACH case. 2640 * 2641 * WARNING!!! Disable the whole controller's interrupts before calling and 2642 * the interrupts will be enabled upon successfully return. 2643 */ 2644 static int 2645 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2646 { 2647 ahci_port_t *ahci_portp; 2648 uint32_t ghc_control; 2649 int port; 2650 2651 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2652 "ahci_initialize_controller enter"); 2653 2654 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2655 2656 /* 2657 * Indicate that system software is AHCI aware by setting 2658 * GHC.AE to 1 2659 */ 2660 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2661 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2662 2663 ghc_control |= AHCI_HBA_GHC_AE; 2664 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2665 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2666 ghc_control); 2667 2668 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2669 2670 /* Initialize the implemented ports and structures */ 2671 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2672 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2673 continue; 2674 } 2675 2676 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2677 mutex_enter(&ahci_portp->ahciport_mutex); 2678 2679 /* 2680 * Ensure that the controller is not in the running state 2681 * by checking every implemented port's PxCMD register 2682 */ 2683 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2684 != AHCI_SUCCESS) { 2685 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2686 "ahci_initialize_controller: failed to " 2687 "initialize port %d", port); 2688 /* 2689 * Set the port state to SATA_PSTATE_FAILED if 2690 * failed to initialize it. 2691 */ 2692 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2693 } 2694 2695 mutex_exit(&ahci_portp->ahciport_mutex); 2696 } 2697 2698 /* Enable the whole controller interrupts */ 2699 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2700 ahci_enable_all_intrs(ahci_ctlp); 2701 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2702 2703 return (AHCI_SUCCESS); 2704 } 2705 2706 /* 2707 * Reverse of ahci_initialize_controller() 2708 * 2709 * We only need to stop the ports and disable the interrupt. 2710 */ 2711 static void 2712 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2713 { 2714 ahci_port_t *ahci_portp; 2715 int port; 2716 2717 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2718 "ahci_uninitialize_controller enter"); 2719 2720 /* disable all the interrupts. */ 2721 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2722 ahci_disable_all_intrs(ahci_ctlp); 2723 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2724 2725 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2726 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2727 continue; 2728 } 2729 2730 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2731 2732 /* Stop the port by clearing PxCMD.ST */ 2733 mutex_enter(&ahci_portp->ahciport_mutex); 2734 2735 /* 2736 * Here we must disable the port interrupt because 2737 * ahci_disable_all_intrs only clear GHC.IE, and IS 2738 * register will be still set if PxIE is enabled. 2739 * When ahci shares one IRQ with other drivers, the 2740 * intr handler may claim the intr mistakenly. 2741 */ 2742 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2743 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2744 ahci_portp, port); 2745 mutex_exit(&ahci_portp->ahciport_mutex); 2746 } 2747 } 2748 2749 /* 2750 * The routine is to initialize the port. First put the port in NOTRunning 2751 * state, then enable port interrupt and clear Serror register. And under 2752 * AHCI_ATTACH case, find device signature and then try to start the port. 2753 * 2754 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2755 */ 2756 static int 2757 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2758 ahci_port_t *ahci_portp, uint8_t port) 2759 { 2760 uint32_t port_cmd_status; 2761 2762 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2763 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2764 2765 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2766 "ahci_initialize_port: port %d " 2767 "port_cmd_status = 0x%x", port, port_cmd_status); 2768 /* 2769 * Check whether the port is in NotRunning state, if not, 2770 * put the port in NotRunning state 2771 */ 2772 if (!(port_cmd_status & 2773 (AHCI_CMD_STATUS_ST | 2774 AHCI_CMD_STATUS_CR | 2775 AHCI_CMD_STATUS_FRE | 2776 AHCI_CMD_STATUS_FR))) { 2777 2778 goto next; 2779 } 2780 2781 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2782 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2783 return (AHCI_FAILURE); 2784 2785 next: 2786 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2787 "port %d is in NotRunning state now", port); 2788 2789 /* 2790 * At the time being, only probe ports/devices and get the types of 2791 * attached devices during DDI_ATTACH. In fact, the device can be 2792 * changed during power state changes, but at the time being, we 2793 * don't support the situation. 2794 */ 2795 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2796 /* Try to get the device signature */ 2797 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2798 } else { 2799 2800 /* 2801 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 2802 * and PxFBU registers in case these registers were cleared 2803 * during the suspend. 2804 */ 2805 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2806 "ahci_initialize_port: port %d " 2807 "reset the port during resume", port); 2808 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 2809 2810 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2811 "ahci_initialize_port: port %d " 2812 "set PxCLB, PxCLBU, PxFB and PxFBU " 2813 "during resume", port); 2814 2815 /* Config Port Received FIS Base Address */ 2816 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2817 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 2818 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 2819 2820 /* Config Port Command List Base Address */ 2821 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2822 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 2823 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 2824 } 2825 2826 /* Disable the interface power management */ 2827 ahci_disable_interface_pm(ahci_ctlp, port); 2828 2829 /* Return directly if no device connected */ 2830 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2831 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2832 "No device connected to port %d", port); 2833 goto out; 2834 } 2835 2836 /* Try to start the port */ 2837 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2838 != AHCI_SUCCESS) { 2839 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2840 "failed to start port %d", port); 2841 return (AHCI_FAILURE); 2842 } 2843 out: 2844 /* Enable port interrupts */ 2845 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2846 2847 return (AHCI_SUCCESS); 2848 } 2849 2850 /* 2851 * Figure out which chip and set flag for VT8251; Also check 2852 * the power management capability. 2853 */ 2854 static int 2855 ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 2856 { 2857 ushort_t venid, caps_ptr, cap_count, cap, pmcap, pmcsr; 2858 uint8_t revision; 2859 2860 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2861 PCI_CONF_VENID); 2862 2863 /* 2864 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 2865 * controllers with 0x00 revision id work on 4-byte aligned buffer, 2866 * which is a bug and was fixed after 0x00 revision id controllers. 2867 * 2868 * Moreover, VT8251 cannot use multiple command slots in the command 2869 * list for non-queued commands because the previous register content 2870 * of PxCI can be re-written in the register write, so a flag will be 2871 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 2872 */ 2873 if (venid == VIA_VENID) { 2874 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2875 PCI_CONF_REVID); 2876 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2877 "revision id = 0x%x", revision); 2878 if (revision == 0x00) { 2879 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 2880 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2881 "change ddi_attr_align to 0x4"); 2882 } 2883 2884 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 2885 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2886 "VT8251 cannot use multiple command lists for " 2887 "non-queued commands"); 2888 } 2889 2890 /* 2891 * Check if capabilities list is supported and if so, 2892 * get initial capabilities pointer and clear bits 0,1. 2893 */ 2894 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2895 PCI_CONF_STAT) & PCI_STAT_CAP) { 2896 caps_ptr = P2ALIGN(pci_config_get8( 2897 ahci_ctlp->ahcictl_pci_conf_handle, 2898 PCI_CONF_CAP_PTR), 4); 2899 } else { 2900 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 2901 } 2902 2903 /* 2904 * Walk capabilities if supported. 2905 */ 2906 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 2907 2908 /* 2909 * Check that we haven't exceeded the maximum number of 2910 * capabilities and that the pointer is in a valid range. 2911 */ 2912 if (++cap_count > PCI_CAP_MAX_PTR) { 2913 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2914 "too many device capabilities"); 2915 return (AHCI_FAILURE); 2916 } 2917 if (caps_ptr < PCI_CAP_PTR_OFF) { 2918 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2919 "capabilities pointer 0x%x out of range", 2920 caps_ptr); 2921 return (AHCI_FAILURE); 2922 } 2923 2924 /* 2925 * Get next capability and check that it is valid. 2926 * For now, we only support power management. 2927 */ 2928 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2929 caps_ptr); 2930 switch (cap) { 2931 case PCI_CAP_ID_PM: 2932 2933 /* power management supported */ 2934 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 2935 2936 /* Save PMCSR offset */ 2937 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 2938 2939 pmcap = pci_config_get16( 2940 ahci_ctlp->ahcictl_pci_conf_handle, 2941 caps_ptr + PCI_PMCAP); 2942 pmcsr = pci_config_get16( 2943 ahci_ctlp->ahcictl_pci_conf_handle, 2944 ahci_ctlp->ahcictl_pmcsr_offset); 2945 AHCIDBG2(AHCIDBG_PM, ahci_ctlp, 2946 "Power Management capability found PCI_PMCAP " 2947 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 2948 #if AHCI_DEBUG 2949 if ((pmcap & 0x3) == 0x3) 2950 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2951 "PCI Power Management Interface " 2952 "spec 1.2 compliant"); 2953 #endif 2954 break; 2955 2956 case PCI_CAP_ID_MSI: 2957 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, "MSI capability found"); 2958 break; 2959 2960 case PCI_CAP_ID_PCIX: 2961 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2962 "PCI-X capability found"); 2963 break; 2964 2965 case PCI_CAP_ID_PCI_E: 2966 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2967 "PCI Express capability found"); 2968 break; 2969 2970 case PCI_CAP_ID_MSI_X: 2971 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2972 "MSI-X capability found"); 2973 break; 2974 2975 case PCI_CAP_ID_SATA: 2976 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2977 "SATA capability found"); 2978 break; 2979 2980 default: 2981 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2982 "unrecognized capability 0x%x", cap); 2983 break; 2984 } 2985 2986 /* 2987 * Get next capabilities pointer and clear bits 0,1. 2988 */ 2989 caps_ptr = P2ALIGN(pci_config_get8( 2990 ahci_ctlp->ahcictl_pci_conf_handle, 2991 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 2992 } 2993 2994 return (AHCI_SUCCESS); 2995 } 2996 2997 /* 2998 * AHCI device reset ...; a single device on one of the ports is reset, 2999 * but the HBA and physical communication remain intact. This is the 3000 * least intrusive. 3001 * 3002 * When issuing a software reset sequence, there should not be other 3003 * commands in the command list, so we will first clear and then re-set 3004 * PxCMD.ST to clear PxCI. And before issuing the software reset, 3005 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 3006 * cleared. 3007 * 3008 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 3009 * set before the function is called. 3010 */ 3011 static int 3012 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3013 uint8_t port) 3014 { 3015 ahci_fis_h2d_register_t *h2d_register_fisp; 3016 ahci_cmd_table_t *cmd_table; 3017 ahci_cmd_header_t *cmd_header; 3018 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 3019 int slot, loop_count; 3020 3021 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3022 "Port %d device resetting", port); 3023 3024 /* First to clear PxCMD.ST */ 3025 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3026 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3027 3028 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 3029 3030 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3031 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3032 port_cmd_status|AHCI_CMD_STATUS_ST); 3033 3034 /* And then to re-set PxCMD.ST */ 3035 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3036 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3037 3038 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3039 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3040 port_cmd_status|AHCI_CMD_STATUS_ST); 3041 3042 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 3043 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3044 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3045 3046 if (port_task_file & AHCI_TFD_STS_BSY || 3047 port_task_file & AHCI_TFD_STS_DRQ) { 3048 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 3049 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3050 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 3051 "but PxCMD.CLO isn't supported, so a port " 3052 "reset is needed."); 3053 return (AHCI_FAILURE); 3054 } 3055 } 3056 3057 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, AHCI_NON_NCQ_CMD); 3058 if (slot == AHCI_FAILURE) { 3059 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 3060 "ahci_software_reset: no free slot"); 3061 return (AHCI_FAILURE); 3062 } 3063 3064 /* Now send the first R2H FIS with SRST set to 1 */ 3065 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3066 bzero((void *)cmd_table, ahci_cmd_table_size); 3067 3068 h2d_register_fisp = 3069 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3070 3071 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3072 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3073 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 3074 3075 /* Set Command Header in Command List */ 3076 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3077 BZERO_DESCR_INFO(cmd_header); 3078 BZERO_PRD_BYTE_COUNT(cmd_header); 3079 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3080 3081 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 3082 SET_RESET(cmd_header, 1); 3083 SET_WRITE(cmd_header, 1); 3084 3085 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3086 0, 3087 ahci_cmd_table_size, 3088 DDI_DMA_SYNC_FORDEV); 3089 3090 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3091 slot * sizeof (ahci_cmd_header_t), 3092 sizeof (ahci_cmd_header_t), 3093 DDI_DMA_SYNC_FORDEV); 3094 3095 /* Indicate to the HBA that a command is active. */ 3096 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3097 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3098 (0x1 << slot)); 3099 3100 loop_count = 0; 3101 3102 /* Loop till the first command is finished */ 3103 do { 3104 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3105 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3106 3107 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3108 /* We are effectively timing out after 0.1 sec. */ 3109 break; 3110 } 3111 /* Wait for 10 millisec */ 3112 #ifndef __lock_lint 3113 delay(AHCI_10MS_TICKS); 3114 #endif /* __lock_lint */ 3115 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3116 3117 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3118 "ahci_software_reset: 1st loop count: %d, " 3119 "port_cmd_issue = 0x%x, slot = 0x%x", 3120 loop_count, port_cmd_issue, slot); 3121 3122 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3123 ahci_portp->ahciport_slot_pkts[slot] = NULL; 3124 3125 /* Now send the second R2H FIS with SRST cleard to zero */ 3126 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3127 bzero((void *)cmd_table, ahci_cmd_table_size); 3128 3129 h2d_register_fisp = 3130 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3131 3132 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3133 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3134 3135 /* Set Command Header in Command List */ 3136 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3137 BZERO_DESCR_INFO(cmd_header); 3138 BZERO_PRD_BYTE_COUNT(cmd_header); 3139 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3140 3141 SET_WRITE(cmd_header, 1); 3142 3143 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3144 0, 3145 ahci_cmd_table_size, 3146 DDI_DMA_SYNC_FORDEV); 3147 3148 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3149 slot * sizeof (ahci_cmd_header_t), 3150 sizeof (ahci_cmd_header_t), 3151 DDI_DMA_SYNC_FORDEV); 3152 3153 /* Indicate to the HBA that a command is active. */ 3154 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3155 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3156 (0x1 << slot)); 3157 3158 loop_count = 0; 3159 3160 /* Loop till the second command is finished */ 3161 do { 3162 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3163 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3164 3165 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3166 /* We are effectively timing out after 0.1 sec. */ 3167 break; 3168 } 3169 /* Wait for 10 millisec */ 3170 #ifndef __lock_lint 3171 delay(AHCI_10MS_TICKS); 3172 #endif /* __lock_lint */ 3173 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3174 3175 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3176 "ahci_software_reset: 2nd loop count: %d, " 3177 "port_cmd_issue = 0x%x, slot = 0x%x", 3178 loop_count, port_cmd_issue, slot); 3179 3180 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3181 ahci_portp->ahciport_slot_pkts[slot] = NULL; 3182 3183 return (AHCI_SUCCESS); 3184 } 3185 3186 /* 3187 * AHCI port reset ...; the physical communication between the HBA and device 3188 * on a port are disabled. This is more intrusive. 3189 * 3190 * When an HBA or port reset occurs, Phy communication is going to 3191 * be re-established with the device through a COMRESET followed by the 3192 * normal out-of-band communication sequence defined in Serial ATA. AT 3193 * the end of reset, the device, if working properly, will send a D2H 3194 * Register FIS, which contains the device signature. When the HBA receives 3195 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 3196 * the PxSIG register with the signature. 3197 * 3198 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 3199 * to individually spin-up attached devices. Please refer to chapter 10.9 of 3200 * AHCI 1.0 spec. 3201 */ 3202 /* 3203 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 3204 * cleared before the function is called. 3205 */ 3206 static int 3207 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3208 { 3209 uint32_t cap_status, port_cmd_status; 3210 uint32_t port_scontrol, port_sstatus; 3211 uint32_t port_signature, port_intr_status, port_task_file; 3212 int loop_count; 3213 int rval = AHCI_SUCCESS; 3214 3215 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3216 "Port %d port resetting...", port); 3217 ahci_portp->ahciport_port_state = 0; 3218 3219 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3220 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3221 3222 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3223 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3224 3225 if (cap_status & AHCI_HBA_CAP_SSS) { 3226 /* 3227 * HBA support staggered spin-up, if the port has 3228 * not spin up yet, then force it to do spin-up 3229 */ 3230 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 3231 if (!(ahci_portp->ahciport_flags 3232 & AHCI_PORT_FLAG_SPINUP)) { 3233 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3234 "Port %d PxCMD.SUD is zero, force " 3235 "it to do spin-up", port); 3236 ahci_portp->ahciport_flags |= 3237 AHCI_PORT_FLAG_SPINUP; 3238 } 3239 } 3240 } else { 3241 /* 3242 * HBA doesn't support stagger spin-up, force it 3243 * to do normal COMRESET 3244 */ 3245 if (ahci_portp->ahciport_flags & 3246 AHCI_PORT_FLAG_SPINUP) { 3247 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3248 "HBA does not support staggered spin-up " 3249 "force it to do normal COMRESET"); 3250 ahci_portp->ahciport_flags &= 3251 ~AHCI_PORT_FLAG_SPINUP; 3252 } 3253 } 3254 3255 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 3256 /* Do normal COMRESET */ 3257 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3258 "ahci_port_reset: do normal COMRESET", port); 3259 3260 /* 3261 * According to the spec, SUD bit should be set here, 3262 * but JMicron JMB363 doesn't follow it, so remove 3263 * the assertion, and just print a debug message. 3264 */ 3265 #if AHCI_DEBUG 3266 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3267 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3268 "port %d SUD bit not set", port) 3269 #endif 3270 3271 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3272 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3273 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3274 3275 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3276 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3277 port_scontrol); 3278 3279 /* Enable PxCMD.FRE to read device */ 3280 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3281 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3282 port_cmd_status|AHCI_CMD_STATUS_FRE); 3283 3284 /* 3285 * Give time for COMRESET to percolate, according to the AHCI 3286 * spec, software shall wait at least 1 millisecond before 3287 * clearing PxSCTL.DET 3288 */ 3289 #ifndef __lock_lint 3290 delay(AHCI_1MS_TICKS*2); 3291 #endif /* __lock_lint */ 3292 3293 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3294 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3295 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3296 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3297 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3298 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3299 port_scontrol); 3300 } else { 3301 /* Do staggered spin-up */ 3302 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3303 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3304 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3305 3306 /* PxSCTL.DET must be 0 */ 3307 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3308 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3309 port_scontrol); 3310 3311 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3312 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3313 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3314 port_cmd_status); 3315 3316 /* 0 -> 1 edge */ 3317 #ifndef __lock_lint 3318 delay(AHCI_1MS_TICKS*2); 3319 #endif /* __lock_lint */ 3320 3321 /* Set PxCMD.SUD to 1 */ 3322 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3323 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3324 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3325 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3326 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3327 port_cmd_status); 3328 3329 /* Enable PxCMD.FRE to read device */ 3330 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3331 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3332 port_cmd_status|AHCI_CMD_STATUS_FRE); 3333 } 3334 3335 /* 3336 * The port enters P:StartComm state, and HBA tells link layer to 3337 * start communication, which involves sending COMRESET to device. 3338 * And the HBA resets PxTFD.STS to 7Fh. 3339 * 3340 * When a COMINIT is received from the device, then the port enters 3341 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3342 * PxSSTS.DET to 1h to indicate a device is detected but communication 3343 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3344 * a COMINIT has been received. 3345 */ 3346 /* 3347 * The DET field is valid only if IPM field indicates 3348 * that the interface is in active state. 3349 */ 3350 loop_count = 0; 3351 do { 3352 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3353 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3354 3355 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3356 /* 3357 * If the interface is not active, the DET field 3358 * is considered not accurate. So we want to 3359 * continue looping. 3360 */ 3361 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3362 } 3363 3364 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3365 /* 3366 * We are effectively timing out after 0.1 sec. 3367 */ 3368 break; 3369 } 3370 3371 /* Wait for 10 millisec */ 3372 #ifndef __lock_lint 3373 delay(AHCI_10MS_TICKS); 3374 #endif /* __lock_lint */ 3375 3376 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3377 3378 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3379 "ahci_port_reset: 1st loop count: %d, " 3380 "port_sstatus = 0x%x port %d", 3381 loop_count, port_sstatus, port); 3382 3383 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3384 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3385 /* 3386 * Either the port is not active or there 3387 * is no device present. 3388 */ 3389 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3390 goto out; 3391 } 3392 3393 /* Now we can make sure there is a device connected to the port */ 3394 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3395 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3396 3397 /* a COMINIT signal is supposed to be received */ 3398 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 3399 cmn_err(CE_WARN, "ahci_port_reset: port %d COMINIT signal " 3400 "from the device not received", port); 3401 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3402 rval = AHCI_FAILURE; 3403 goto out; 3404 } 3405 3406 /* 3407 * According to the spec, when PxSCTL.DET is set to 0h, upon 3408 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3409 * shall be set to '1' by the HBA. 3410 * 3411 * However, we found JMicron JMB363 doesn't follow this, so 3412 * remove this check, and just print a debug message. 3413 */ 3414 #if AHCI_DEBUG 3415 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3416 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3417 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3418 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3419 "port %d BSY bit is not set after COMINIT signal " 3420 "is received", port); 3421 } 3422 #endif 3423 3424 /* 3425 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3426 * the D2H FIS received by HBA. 3427 */ 3428 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3429 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3430 SERROR_EXCHANGED_ERR); 3431 3432 /* 3433 * Next check whether COMRESET is completed successfully 3434 */ 3435 loop_count = 0; 3436 do { 3437 port_task_file = 3438 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3439 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3440 3441 /* 3442 * The Error bit '1' means COMRESET is finished successfully 3443 * The device hardware has been initialized and the power-up 3444 * diagnostics successfully completed. 3445 */ 3446 if (((port_task_file & AHCI_TFD_ERR_MASK) 3447 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 3448 3449 port_signature = ddi_get32( 3450 ahci_ctlp->ahcictl_ahci_acc_handle, 3451 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3452 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 3453 "COMRESET success, D2H register FIS " 3454 "post to received FIS structure " 3455 "port %d signature = 0x%x", 3456 port, port_signature); 3457 goto out_check; 3458 } 3459 3460 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3461 /* 3462 * We are effectively timing out after 11 sec. 3463 */ 3464 break; 3465 } 3466 3467 /* Wait for 10 millisec */ 3468 #ifndef __lock_lint 3469 delay(AHCI_10MS_TICKS); 3470 #endif /* __lock_lint */ 3471 3472 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3473 >> AHCI_TFD_ERR_SHIFT) != 0x1); 3474 3475 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 3476 "count: %d, port_task_file = 0x%x port %d", 3477 loop_count, port_task_file, port); 3478 3479 cmn_err(CE_WARN, "ahci_port_reset: port %d the device hardware " 3480 "has been initialized and the power-up diagnostics failed", 3481 port); 3482 3483 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3484 rval = AHCI_FAILURE; 3485 3486 out: 3487 /* Clear port serror register for the port */ 3488 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3489 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3490 AHCI_SERROR_CLEAR_ALL); 3491 3492 return (rval); 3493 3494 out_check: 3495 /* 3496 * Check device status, if keep busy or COMRESET error 3497 * do device reset to patch some SATA disks' issue 3498 * 3499 * For VT8251, sometimes need to do the device reset 3500 */ 3501 if ((port_task_file & AHCI_TFD_STS_BSY) || 3502 (port_task_file & AHCI_TFD_STS_DRQ)) { 3503 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 3504 "need to do device reset", port); 3505 3506 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 3507 3508 port_task_file = 3509 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3510 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3511 3512 if (port_task_file & AHCI_TFD_STS_BSY || 3513 port_task_file & AHCI_TFD_STS_DRQ) { 3514 cmn_err(CE_WARN, "ahci_port_reset: port %d " 3515 "BSY/DRQ still set after device reset " 3516 "port_task_file = 0x%x", 3517 port, port_task_file); 3518 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3519 rval = AHCI_FAILURE; 3520 } 3521 } 3522 3523 goto out; 3524 } 3525 3526 /* 3527 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3528 * This is the most intrusive. 3529 * 3530 * When an HBA reset occurs, Phy communication will be re-established with 3531 * the device through a COMRESET followed by the normal out-of-band 3532 * communication sequence defined in Serial ATA. AT the end of reset, the 3533 * device, if working properly, will send a D2H Register FIS, which contains 3534 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3535 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3536 * signature. 3537 * 3538 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3539 */ 3540 static int 3541 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3542 { 3543 ahci_port_t *ahci_portp; 3544 uint32_t ghc_control; 3545 uint8_t port; 3546 int loop_count; 3547 int rval = AHCI_SUCCESS; 3548 3549 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3550 3551 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3552 3553 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3554 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3555 3556 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3557 ghc_control |= AHCI_HBA_GHC_HR; 3558 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3559 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3560 3561 /* 3562 * Wait until HBA Reset complete or timeout 3563 */ 3564 loop_count = 0; 3565 do { 3566 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3567 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3568 3569 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3570 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3571 "ahci hba reset is timing out, " 3572 "ghc_control = 0x%x", ghc_control); 3573 /* We are effectively timing out after 1 sec. */ 3574 break; 3575 } 3576 3577 /* Wait for 10 millisec */ 3578 #ifndef __lock_lint 3579 delay(AHCI_10MS_TICKS); 3580 #endif /* __lock_lint */ 3581 3582 } while (ghc_control & AHCI_HBA_GHC_HR); 3583 3584 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3585 "ahci_hba_reset: 1st loop count: %d, " 3586 "ghc_control = 0x%x", loop_count, ghc_control); 3587 3588 if (ghc_control & AHCI_HBA_GHC_HR) { 3589 /* The hba is not reset for some reasons */ 3590 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3591 "hba reset failed: HBA in a hung or locked state"); 3592 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3593 return (AHCI_FAILURE); 3594 } 3595 3596 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3597 /* Only check implemented ports */ 3598 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3599 continue; 3600 } 3601 3602 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3603 mutex_enter(&ahci_portp->ahciport_mutex); 3604 3605 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3606 != AHCI_SUCCESS) { 3607 rval = AHCI_FAILURE; 3608 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3609 "ahci_hba_reset: port %d failed", port); 3610 } 3611 3612 mutex_exit(&ahci_portp->ahciport_mutex); 3613 } 3614 3615 /* 3616 * Indicate that system software is AHCI aware by setting 3617 * GHC.AE to 1 3618 */ 3619 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3620 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3621 3622 ghc_control |= AHCI_HBA_GHC_AE; 3623 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3624 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3625 3626 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3627 3628 return (rval); 3629 } 3630 3631 /* 3632 * This routine is only called from AHCI_ATTACH or phyrdy change 3633 * case. It first calls port reset to initialize port, probe port and probe 3634 * device, then try to read PxSIG register to find the type of device 3635 * attached to the port. 3636 * 3637 * WARNING!!! ahciport_mutex should be acquired before the function 3638 * is called. And the port interrupt is disabled. 3639 */ 3640 static void 3641 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3642 ahci_port_t *ahci_portp, uint8_t port) 3643 { 3644 uint32_t signature; 3645 3646 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3647 "ahci_find_dev_signature enter: port %d", port); 3648 3649 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3650 3651 /* Call port reset to check link status and get device signature */ 3652 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3653 3654 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3655 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3656 "ahci_find_dev_signature: No device is found " 3657 "at port %d", port); 3658 return; 3659 } 3660 3661 /* Check the port state */ 3662 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3663 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3664 "ahci_find_dev_signature: port %d state 0x%x", 3665 port, ahci_portp->ahciport_port_state); 3666 return; 3667 } 3668 3669 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3670 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3671 3672 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3673 "ahci_find_dev_signature: port %d signature = 0x%x", 3674 port, signature); 3675 3676 switch (signature) { 3677 3678 case AHCI_SIGNATURE_DISK: 3679 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3680 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3681 "Disk is found at port: %d", port); 3682 break; 3683 3684 case AHCI_SIGNATURE_ATAPI: 3685 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 3686 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3687 "ATAPI device is found at port: %d", port); 3688 break; 3689 3690 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3691 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3692 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3693 "Port Multiplier is found at port: %d", port); 3694 break; 3695 3696 default: 3697 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3698 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3699 "Unknown device is found at port: %d", port); 3700 } 3701 } 3702 3703 /* 3704 * According to the spec, to reliably detect hot plug removals, software 3705 * must disable interface power management. Software should perform the 3706 * following initialization on a port after a device is attached: 3707 * Set PxSCTL.IPM to 3h to disable interface state transitions 3708 * Set PxCMD.ALPE to '0' to disable aggressive power management 3709 * Disable device initiated interface power management by SET FEATURE 3710 * 3711 * We can ignore the last item because by default the feature is disabled 3712 */ 3713 static void 3714 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 3715 { 3716 uint32_t port_scontrol, port_cmd_status; 3717 3718 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3719 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3720 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 3721 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3722 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3723 3724 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3725 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3726 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 3727 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3728 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 3729 } 3730 3731 /* 3732 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3733 * to 1, then set it firstly. 3734 * 3735 * Each port contains two major DMA engines. One DMA engine walks through 3736 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3737 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3738 * 3739 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3740 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3741 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3742 * 3743 * Software shall not set PxCMD.ST to '1' unless a functional device is 3744 * present on the port(as determined by PxTFD.STS.BSY = '0', 3745 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3746 * 3747 * WARNING!!! ahciport_mutex should be acquired before the function 3748 * is called. 3749 */ 3750 static int 3751 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3752 { 3753 uint32_t port_cmd_status; 3754 3755 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3756 3757 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3758 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3759 "the state for port %d is 0x%x", 3760 port, ahci_portp->ahciport_port_state); 3761 return (AHCI_FAILURE); 3762 } 3763 3764 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3765 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3766 "no device is attached at port %d", port); 3767 return (AHCI_FAILURE); 3768 } 3769 3770 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3771 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3772 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3773 3774 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3775 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3776 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3777 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3778 port_cmd_status); 3779 } 3780 3781 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3782 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3783 3784 port_cmd_status |= AHCI_CMD_STATUS_ST; 3785 3786 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3787 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3788 port_cmd_status); 3789 3790 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3791 3792 return (AHCI_SUCCESS); 3793 } 3794 3795 /* 3796 * Allocate the ahci_port_t including Received FIS and Command List. 3797 * The argument - port is the physical port number, and not logical 3798 * port number seen by the SATA framework. 3799 * 3800 * WARNING!!! ahcictl_mutex should be acquired before the function 3801 * is called. 3802 */ 3803 static int 3804 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3805 { 3806 ahci_port_t *ahci_portp; 3807 3808 ahci_portp = 3809 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3810 3811 #ifndef __lock_lint 3812 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3813 #endif /* __lock_lint */ 3814 3815 ahci_portp->ahciport_port_num = port; 3816 3817 /* Intialize the port condition variable */ 3818 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3819 3820 /* Initialize the port mutex */ 3821 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3822 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3823 3824 mutex_enter(&ahci_portp->ahciport_mutex); 3825 3826 /* 3827 * Allocate memory for received FIS structure and 3828 * command list for this port 3829 */ 3830 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3831 goto err_case1; 3832 } 3833 3834 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3835 goto err_case2; 3836 } 3837 3838 ahci_portp->ahciport_event_args = 3839 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3840 3841 if (ahci_portp->ahciport_event_args == NULL) 3842 goto err_case3; 3843 3844 mutex_exit(&ahci_portp->ahciport_mutex); 3845 3846 return (AHCI_SUCCESS); 3847 3848 err_case3: 3849 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3850 3851 err_case2: 3852 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3853 3854 err_case1: 3855 mutex_exit(&ahci_portp->ahciport_mutex); 3856 mutex_destroy(&ahci_portp->ahciport_mutex); 3857 cv_destroy(&ahci_portp->ahciport_cv); 3858 3859 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3860 3861 return (AHCI_FAILURE); 3862 } 3863 3864 /* 3865 * Reverse of ahci_dealloc_port_state(). 3866 * 3867 * WARNING!!! ahcictl_mutex should be acquired before the function 3868 * is called. 3869 */ 3870 static void 3871 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3872 { 3873 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3874 3875 ASSERT(ahci_portp != NULL); 3876 3877 mutex_enter(&ahci_portp->ahciport_mutex); 3878 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3879 ahci_portp->ahciport_event_args = NULL; 3880 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3881 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3882 mutex_exit(&ahci_portp->ahciport_mutex); 3883 3884 mutex_destroy(&ahci_portp->ahciport_mutex); 3885 cv_destroy(&ahci_portp->ahciport_cv); 3886 3887 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3888 3889 #ifndef __lock_lint 3890 ahci_ctlp->ahcictl_ports[port] = NULL; 3891 #endif /* __lock_lint */ 3892 } 3893 3894 /* 3895 * Allocates memory for the Received FIS Structure 3896 * 3897 * WARNING!!! ahciport_mutex should be acquired before the function 3898 * is called. 3899 */ 3900 static int 3901 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3902 uint8_t port) 3903 { 3904 size_t rcvd_fis_size; 3905 size_t ret_len; 3906 uint_t cookie_count; 3907 uint32_t cap_status; 3908 3909 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3910 3911 /* Check whether the HBA can access 64-bit data structures */ 3912 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3913 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3914 3915 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 3916 3917 /* 3918 * If 64-bit addressing is not supported, 3919 * change dma_attr_addr_hi of ahcictl_rcvd_fis_dma_attr 3920 */ 3921 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3922 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3923 "hba does not support 64-bit addressing"); 3924 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 3925 0xffffffffull; 3926 } 3927 3928 /* allocate rcvd FIS dma handle. */ 3929 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3930 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3931 DDI_DMA_SLEEP, 3932 NULL, 3933 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3934 DDI_SUCCESS) { 3935 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3936 "rcvd FIS dma handle alloc failed"); 3937 3938 return (AHCI_FAILURE); 3939 } 3940 3941 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3942 rcvd_fis_size, 3943 &accattr, 3944 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3945 DDI_DMA_SLEEP, 3946 NULL, 3947 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3948 &ret_len, 3949 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3950 3951 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3952 "rcvd FIS dma mem alloc fail"); 3953 /* error.. free the dma handle. */ 3954 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3955 return (AHCI_FAILURE); 3956 } 3957 3958 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3959 NULL, 3960 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3961 rcvd_fis_size, 3962 DDI_DMA_CONSISTENT, 3963 DDI_DMA_SLEEP, 3964 NULL, 3965 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 3966 &cookie_count) != DDI_DMA_MAPPED) { 3967 3968 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3969 "rcvd FIS dma handle bind fail"); 3970 /* error.. free the dma handle & free the memory. */ 3971 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3972 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3973 return (AHCI_FAILURE); 3974 } 3975 3976 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 3977 3978 /* Config Port Received FIS Base Address */ 3979 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3980 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 3981 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 3982 3983 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3984 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 3985 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3986 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 3987 3988 return (AHCI_SUCCESS); 3989 } 3990 3991 /* 3992 * Deallocates the Received FIS Structure 3993 * 3994 * WARNING!!! ahciport_mutex should be acquired before the function 3995 * is called. 3996 */ 3997 static void 3998 ahci_dealloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3999 { 4000 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4001 "ahci_dealloc_rcvd_fis: port %d enter", 4002 ahci_portp->ahciport_port_num); 4003 4004 /* Unbind the cmd list dma handle first. */ 4005 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 4006 4007 /* Then free the underlying memory. */ 4008 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4009 4010 /* Now free the handle itself. */ 4011 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4012 } 4013 4014 /* 4015 * Allocates memory for the Command List, which contains up to 32 entries. 4016 * Each entry contains a command header, which is a 32-byte structure that 4017 * includes the pointer to the command table. 4018 * 4019 * WARNING!!! ahciport_mutex should be acquired before the function 4020 * is called. 4021 */ 4022 static int 4023 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4024 uint8_t port) 4025 { 4026 size_t cmd_list_size; 4027 size_t ret_len; 4028 uint_t cookie_count; 4029 uint32_t cap_status; 4030 4031 cmd_list_size = 4032 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 4033 4034 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4035 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4036 4037 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 4038 4039 /* 4040 * If 64-bit addressing is not supported, 4041 * change dma_attr_addr_hi of ahcictl_cmd_list_dma_attr 4042 */ 4043 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 4044 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4045 "hba does not support 64-bit addressing"); 4046 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 4047 0xffffffffull; 4048 } 4049 4050 /* allocate cmd list dma handle. */ 4051 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4052 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 4053 DDI_DMA_SLEEP, 4054 NULL, 4055 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 4056 4057 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4058 "cmd list dma handle alloc failed"); 4059 return (AHCI_FAILURE); 4060 } 4061 4062 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 4063 cmd_list_size, 4064 &accattr, 4065 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4066 DDI_DMA_SLEEP, 4067 NULL, 4068 (caddr_t *)&ahci_portp->ahciport_cmd_list, 4069 &ret_len, 4070 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 4071 4072 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4073 "cmd list dma mem alloc fail"); 4074 /* error.. free the dma handle. */ 4075 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4076 return (AHCI_FAILURE); 4077 } 4078 4079 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 4080 NULL, 4081 (caddr_t)ahci_portp->ahciport_cmd_list, 4082 cmd_list_size, 4083 DDI_DMA_CONSISTENT, 4084 DDI_DMA_SLEEP, 4085 NULL, 4086 &ahci_portp->ahciport_cmd_list_dma_cookie, 4087 &cookie_count) != DDI_DMA_MAPPED) { 4088 4089 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4090 "cmd list dma handle bind fail"); 4091 /* error.. free the dma handle & free the memory. */ 4092 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4093 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4094 return (AHCI_FAILURE); 4095 } 4096 4097 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 4098 4099 /* Config Port Command List Base Address */ 4100 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4101 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 4102 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4103 4104 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4105 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4106 4107 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4108 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 4109 4110 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 4111 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 4112 return (AHCI_FAILURE); 4113 } 4114 4115 return (AHCI_SUCCESS); 4116 } 4117 4118 /* 4119 * Deallocates the Command List 4120 * 4121 * WARNING!!! ahciport_mutex should be acquired before the function 4122 * is called. 4123 */ 4124 static void 4125 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4126 { 4127 /* First dealloc command table */ 4128 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 4129 4130 /* Unbind the cmd list dma handle first. */ 4131 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4132 4133 /* Then free the underlying memory. */ 4134 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4135 4136 /* Now free the handle itself. */ 4137 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4138 } 4139 4140 /* 4141 * Allocates memory for all Command Tables, which contains Command FIS, 4142 * ATAPI Command and Physical Region Descriptor Table. 4143 * 4144 * WARNING!!! ahciport_mutex should be acquired before the function 4145 * is called. 4146 */ 4147 static int 4148 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4149 { 4150 size_t ret_len; 4151 ddi_dma_cookie_t cmd_table_dma_cookie; 4152 uint_t cookie_count; 4153 uint32_t cap_status; 4154 int slot; 4155 4156 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4157 "ahci_alloc_cmd_tables: port %d enter", 4158 ahci_portp->ahciport_port_num); 4159 4160 /* Check whether the HBA can access 64-bit data structures */ 4161 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4162 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4163 4164 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 4165 4166 /* 4167 * If 64-bit addressing is not supported, 4168 * change dma_attr_addr_hi of ahcictl_cmd_table_dma_attr 4169 */ 4170 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 4171 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4172 "hba does not support 64-bit addressing"); 4173 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 4174 0xffffffffull; 4175 } 4176 4177 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4178 /* Allocate cmd table dma handle. */ 4179 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4180 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 4181 DDI_DMA_SLEEP, 4182 NULL, 4183 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 4184 DDI_SUCCESS) { 4185 4186 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4187 "cmd table dma handle alloc failed"); 4188 4189 goto err_out; 4190 } 4191 4192 if (ddi_dma_mem_alloc( 4193 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4194 ahci_cmd_table_size, 4195 &accattr, 4196 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4197 DDI_DMA_SLEEP, 4198 NULL, 4199 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 4200 &ret_len, 4201 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 4202 NULL) { 4203 4204 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4205 "cmd table dma mem alloc fail"); 4206 4207 /* error.. free the dma handle. */ 4208 ddi_dma_free_handle( 4209 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4210 goto err_out; 4211 } 4212 4213 if (ddi_dma_addr_bind_handle( 4214 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4215 NULL, 4216 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 4217 ahci_cmd_table_size, 4218 DDI_DMA_CONSISTENT, 4219 DDI_DMA_SLEEP, 4220 NULL, 4221 &cmd_table_dma_cookie, 4222 &cookie_count) != DDI_DMA_MAPPED) { 4223 4224 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4225 "cmd table dma handle bind fail"); 4226 /* error.. free the dma handle & free the memory. */ 4227 ddi_dma_mem_free( 4228 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4229 ddi_dma_free_handle( 4230 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4231 goto err_out; 4232 } 4233 4234 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 4235 ahci_cmd_table_size); 4236 4237 /* Config Port Command Table Base Address */ 4238 SET_COMMAND_TABLE_BASE_ADDR( 4239 (&ahci_portp->ahciport_cmd_list[slot]), 4240 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 4241 4242 #ifndef __lock_lint 4243 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 4244 (&ahci_portp->ahciport_cmd_list[slot]), 4245 cmd_table_dma_cookie.dmac_laddress >> 32); 4246 #endif /* __lock_lint */ 4247 } 4248 4249 return (AHCI_SUCCESS); 4250 err_out: 4251 4252 for (slot--; slot >= 0; slot--) { 4253 /* Unbind the cmd table dma handle first */ 4254 (void) ddi_dma_unbind_handle( 4255 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4256 4257 /* Then free the underlying memory */ 4258 ddi_dma_mem_free( 4259 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4260 4261 /* Now free the handle itself */ 4262 ddi_dma_free_handle( 4263 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4264 } 4265 4266 return (AHCI_FAILURE); 4267 } 4268 4269 /* 4270 * Deallocates memory for all Command Tables. 4271 * 4272 * WARNING!!! ahciport_mutex should be acquired before the function 4273 * is called. 4274 */ 4275 static void 4276 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4277 { 4278 int slot; 4279 4280 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4281 "ahci_dealloc_cmd_tables: %d enter", 4282 ahci_portp->ahciport_port_num); 4283 4284 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4285 /* Unbind the cmd table dma handle first. */ 4286 (void) ddi_dma_unbind_handle( 4287 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4288 4289 /* Then free the underlying memory. */ 4290 ddi_dma_mem_free( 4291 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4292 4293 /* Now free the handle itself. */ 4294 ddi_dma_free_handle( 4295 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4296 } 4297 } 4298 4299 /* 4300 * WARNING!!! ahciport_mutex should be acquired before the function 4301 * is called. 4302 */ 4303 static void 4304 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4305 sata_device_t *sd) 4306 { 4307 sd->satadev_scr.sstatus = 4308 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4309 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4310 sd->satadev_scr.serror = 4311 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4312 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4313 sd->satadev_scr.scontrol = 4314 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4315 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4316 sd->satadev_scr.sactive = 4317 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4318 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4319 } 4320 4321 /* 4322 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4323 */ 4324 static void 4325 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4326 { 4327 uint32_t port_intr_status; 4328 uint32_t port_intr_enable; 4329 4330 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4331 "ahci_port_intr enter: port %d", port); 4332 4333 mutex_enter(&ahci_portp->ahciport_mutex); 4334 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4335 /* For SATA_OPMODE_POLLING commands */ 4336 port_intr_enable = 4337 (AHCI_INTR_STATUS_DHRS | 4338 AHCI_INTR_STATUS_PSS | 4339 AHCI_INTR_STATUS_SDBS | 4340 AHCI_INTR_STATUS_UFS | 4341 AHCI_INTR_STATUS_PCS | 4342 AHCI_INTR_STATUS_PRCS | 4343 AHCI_INTR_STATUS_OFS | 4344 AHCI_INTR_STATUS_INFS | 4345 AHCI_INTR_STATUS_IFS | 4346 AHCI_INTR_STATUS_HBDS | 4347 AHCI_INTR_STATUS_HBFS | 4348 AHCI_INTR_STATUS_TFES); 4349 mutex_exit(&ahci_portp->ahciport_mutex); 4350 goto next; 4351 } 4352 mutex_exit(&ahci_portp->ahciport_mutex); 4353 4354 /* 4355 * port_intr_enable indicates that the corresponding interrrupt 4356 * reporting is enabled. 4357 */ 4358 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4359 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4360 next: 4361 /* 4362 * port_intr_stats indicates that the corresponding interrupt 4363 * condition is active. 4364 */ 4365 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4366 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4367 4368 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4369 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4370 "port_intr_enable = 0x%x", 4371 port, port_intr_status, port_intr_enable); 4372 4373 port_intr_status &= port_intr_enable; 4374 4375 /* First clear the port interrupts status */ 4376 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4377 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4378 port_intr_status); 4379 4380 /* Check the completed non-queued commands */ 4381 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4382 AHCI_INTR_STATUS_PSS)) { 4383 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4384 ahci_portp, port, port_intr_status); 4385 } 4386 4387 /* Check the completed queued commands */ 4388 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4389 (void) ahci_intr_set_device_bits(ahci_ctlp, 4390 ahci_portp, port); 4391 } 4392 4393 /* Check the port connect change status interrupt bit */ 4394 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4395 (void) ahci_intr_port_connect_change(ahci_ctlp, 4396 ahci_portp, port); 4397 } 4398 4399 /* Check the device mechanical presence status interrupt bit */ 4400 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4401 (void) ahci_intr_device_mechanical_presence_status( 4402 ahci_ctlp, ahci_portp, port); 4403 } 4404 4405 /* Check the PhyRdy change status interrupt bit */ 4406 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4407 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4408 port); 4409 } 4410 4411 /* 4412 * Check the non-fatal error interrupt bits, there are three 4413 * kinds of non-fatal errors at the time being: 4414 * 4415 * PxIS.UFS - Unknown FIS Error 4416 * PxIS.OFS - Overflow Error 4417 * PxIS.INFS - Interface Non-Fatal Error 4418 * 4419 * For these non-fatal errors, the HBA can continue to operate, 4420 * so the driver just log the error messages. 4421 */ 4422 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4423 AHCI_INTR_STATUS_OFS | 4424 AHCI_INTR_STATUS_INFS)) { 4425 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4426 port, port_intr_status); 4427 } 4428 4429 /* 4430 * Check the fatal error interrupt bits, there are four kinds 4431 * of fatal errors for AHCI controllers: 4432 * 4433 * PxIS.HBFS - Host Bus Fatal Error 4434 * PxIS.HBDS - Host Bus Data Error 4435 * PxIS.IFS - Interface Fatal Error 4436 * PxIS.TFES - Task File Error 4437 * 4438 * The fatal error means the HBA can not recover from it by 4439 * itself, and it will try to abort the transfer, and the software 4440 * must intervene to restart the port. 4441 */ 4442 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4443 AHCI_INTR_STATUS_HBDS | 4444 AHCI_INTR_STATUS_HBFS | 4445 AHCI_INTR_STATUS_TFES)) 4446 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4447 port, port_intr_status); 4448 4449 /* Check the cold port detect interrupt bit */ 4450 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4451 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4452 } 4453 4454 /* Second clear the corresponding bit in IS.IPS */ 4455 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4456 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4457 } 4458 4459 /* 4460 * Interrupt service handler 4461 */ 4462 /* ARGSUSED1 */ 4463 static uint_t 4464 ahci_intr(caddr_t arg1, caddr_t arg2) 4465 { 4466 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4467 ahci_port_t *ahci_portp; 4468 int32_t global_intr_status; 4469 uint8_t port; 4470 4471 /* 4472 * global_intr_status indicates that the corresponding port has 4473 * an interrupt pending. 4474 */ 4475 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4476 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4477 4478 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4479 /* The interrupt is not ours */ 4480 return (DDI_INTR_UNCLAIMED); 4481 } 4482 4483 /* Loop for all the ports */ 4484 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4485 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4486 continue; 4487 } 4488 if (!((0x1 << port) & global_intr_status)) { 4489 continue; 4490 } 4491 4492 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4493 4494 /* Call ahci_port_intr */ 4495 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4496 } 4497 4498 return (DDI_INTR_CLAIMED); 4499 } 4500 4501 /* 4502 * For non-queued commands, when the corresponding bit in the PxCI register 4503 * is cleared, it means the command is completed successfully. And according 4504 * to the HBA state machine, there are three conditions which possibly will 4505 * try to clear the PxCI register bit. 4506 * 1. Receive one D2H Register FIS which is with 'I' bit set 4507 * 2. Update PIO Setup FIS 4508 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4509 * 4510 * Process completed non-queued commands when the interrupt status bit - 4511 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4512 * 4513 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4514 * with the 'I' bit set. And the following commands will send thus 4515 * FIS with 'I' bit set upon the successful completion: 4516 * 1. Non-data commands 4517 * 2. DMA data-in command 4518 * 3. DMA data-out command 4519 * 4. PIO data-out command 4520 * 5. PACKET non-data commands 4521 * 6. PACKET PIO data-in command 4522 * 7. PACKET PIO data-out command 4523 * 8. PACKET DMA data-in command 4524 * 9. PACKET DMA data-out command 4525 * 4526 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4527 * with the 'I' bit set. And the following commands will send this 4528 * FIS upon the successful completion: 4529 * 1. PIO data-in command 4530 */ 4531 static int 4532 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4533 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 4534 { 4535 uint32_t port_cmd_issue = 0; 4536 uint32_t finished_tags; 4537 int finished_slot; 4538 sata_pkt_t *satapkt; 4539 ahci_fis_d2h_register_t *rcvd_fisp; 4540 4541 if (intr_status & AHCI_INTR_STATUS_DHRS) 4542 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4543 "ahci_intr_cmd_cmplt enter: port %d " 4544 "a d2h register fis is received", port); 4545 4546 if (intr_status & AHCI_INTR_STATUS_PSS) 4547 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4548 "ahci_intr_cmd_cmplt enter: port %d " 4549 "a pio setup fis is received", port); 4550 4551 mutex_enter(&ahci_portp->ahciport_mutex); 4552 4553 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4554 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4555 /* 4556 * Spurious interrupt. Nothing to be done. 4557 */ 4558 mutex_exit(&ahci_portp->ahciport_mutex); 4559 return (AHCI_SUCCESS); 4560 } 4561 4562 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4563 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4564 4565 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4566 /* Slot 0 is always used during error recovery */ 4567 finished_tags = 0x1 & ~port_cmd_issue; 4568 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4569 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4570 "retrieval is finished, and finished_tags = 0x%x", 4571 port, finished_tags); 4572 } else { 4573 finished_tags = ahci_portp->ahciport_pending_tags & 4574 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4575 } 4576 4577 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4578 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4579 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4580 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4581 finished_tags); 4582 4583 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4584 (finished_tags == 0x1)) { 4585 satapkt = ahci_portp->ahciport_err_retri_pkt; 4586 ASSERT(satapkt != NULL); 4587 4588 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4589 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4590 "with SATA_PKT_COMPLETED", (void *)satapkt); 4591 4592 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4593 goto out; 4594 } 4595 4596 while (finished_tags) { 4597 finished_slot = ddi_ffs(finished_tags) - 1; 4598 if (finished_slot == -1) { 4599 goto out; 4600 } 4601 4602 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4603 ASSERT(satapkt != NULL); 4604 4605 /* 4606 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4607 * feature, sata_special_regs flag will be set, and the 4608 * driver should copy the status and the other corresponding 4609 * register values in the D2H Register FIS received (It's 4610 * working on Non-data protocol) from the device back to 4611 * the sata_cmd. 4612 * 4613 * For every AHCI port, there is only one Received FIS 4614 * structure, which contains the FISes received from the 4615 * device, So we're trying to copy the content of D2H 4616 * Register FIS in the Received FIS structure back to 4617 * the sata_cmd. 4618 */ 4619 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4620 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4621 ahcirf_d2h_register_fis); 4622 satapkt->satapkt_cmd.satacmd_status_reg = 4623 GET_RFIS_STATUS(rcvd_fisp); 4624 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4625 } 4626 4627 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4628 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4629 "with SATA_PKT_COMPLETED", (void *)satapkt); 4630 4631 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4632 CLEAR_BIT(finished_tags, finished_slot); 4633 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4634 4635 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4636 } 4637 out: 4638 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4639 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4640 ahci_portp->ahciport_pending_tags); 4641 4642 mutex_exit(&ahci_portp->ahciport_mutex); 4643 4644 return (AHCI_SUCCESS); 4645 } 4646 4647 /* 4648 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4649 * with the 'I' bit set and has been copied into system memory. It will 4650 * be sent under the following situations: 4651 * 4652 * 1. NCQ command is completed 4653 * 2. Asynchronous notification 4654 * 4655 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4656 * via the Set Device Bits FIS. When such event is generated, the software 4657 * needs to read PxSACT register and compares the current value to the 4658 * list of commands previously issue by software. ahciport_pending_ncq_tags 4659 * keeps the tags of previously issued commands. 4660 * 4661 * Asynchronous Notification is a feature in SATA II, which allows an 4662 * ATAPI device to send a signal to the host when media is inserted or 4663 * removed and avoids polling the device for media changes. The signal 4664 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4665 * set to '1'. At the moment, it's not supported yet. 4666 */ 4667 static int 4668 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4669 ahci_port_t *ahci_portp, uint8_t port) 4670 { 4671 uint32_t port_sactive; 4672 uint32_t port_cmd_issue; 4673 uint32_t issued_tags; 4674 int issued_slot; 4675 uint32_t finished_tags; 4676 int finished_slot; 4677 sata_pkt_t *satapkt; 4678 4679 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4680 "ahci_intr_set_device_bits enter: port %d", port); 4681 4682 mutex_enter(&ahci_portp->ahciport_mutex); 4683 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4684 mutex_exit(&ahci_portp->ahciport_mutex); 4685 return (AHCI_SUCCESS); 4686 } 4687 4688 /* 4689 * First the handler got which commands are finished by checking 4690 * PxSACT register 4691 */ 4692 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4693 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4694 4695 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4696 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4697 4698 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4699 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4700 "port_sactive = 0x%x", port, 4701 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4702 4703 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4704 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4705 4706 /* 4707 * For NCQ commands, the software can determine which command has 4708 * already been transmitted to the device by checking PxCI register. 4709 */ 4710 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4711 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4712 4713 issued_tags = ahci_portp->ahciport_pending_tags & 4714 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4715 4716 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4717 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4718 "port_cmd_issue = 0x%x", port, 4719 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4720 4721 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4722 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4723 4724 /* 4725 * Clear ahciport_pending_tags bit when the corresponding command 4726 * is already sent down to the device. 4727 */ 4728 while (issued_tags) { 4729 issued_slot = ddi_ffs(issued_tags) - 1; 4730 if (issued_slot == -1) { 4731 goto next; 4732 } 4733 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4734 CLEAR_BIT(issued_tags, issued_slot); 4735 } 4736 4737 next: 4738 while (finished_tags) { 4739 finished_slot = ddi_ffs(finished_tags) - 1; 4740 if (finished_slot == -1) { 4741 goto out; 4742 } 4743 4744 /* The command is certainly transmitted to the device */ 4745 ASSERT(!(ahci_portp->ahciport_pending_tags & 4746 (0x1 << finished_slot))); 4747 4748 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4749 ASSERT(satapkt != NULL); 4750 4751 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4752 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4753 "with SATA_PKT_COMPLETED", (void *)satapkt); 4754 4755 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4756 CLEAR_BIT(finished_tags, finished_slot); 4757 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4758 4759 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4760 } 4761 out: 4762 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4763 "ahci_intr_set_device_bits: port %d " 4764 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4765 port, ahci_portp->ahciport_pending_ncq_tags, 4766 ahci_portp->ahciport_pending_tags); 4767 4768 mutex_exit(&ahci_portp->ahciport_mutex); 4769 4770 return (AHCI_SUCCESS); 4771 } 4772 4773 /* 4774 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4775 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4776 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4777 * indicates a COMINIT signal was received. 4778 * 4779 * Hot plug insertion is detected by reception of a COMINIT signal from the 4780 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4781 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4782 * begin the normal communication negotiation sequence as outlined in the 4783 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4784 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4785 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4786 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4787 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4788 * to handle hot plug insertion. In this interrupt handler, just do nothing 4789 * but print some log message and clear the bit. 4790 */ 4791 static int 4792 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4793 ahci_port_t *ahci_portp, uint8_t port) 4794 { 4795 uint32_t port_serror; 4796 4797 mutex_enter(&ahci_portp->ahciport_mutex); 4798 4799 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4800 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4801 4802 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4803 "ahci_intr_port_connect_change: port %d, " 4804 "port_serror = 0x%x", port, port_serror); 4805 4806 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4807 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4808 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4809 SERROR_EXCHANGED_ERR); 4810 4811 mutex_exit(&ahci_portp->ahciport_mutex); 4812 4813 return (AHCI_SUCCESS); 4814 } 4815 4816 /* 4817 * Hot Plug Operation for platforms that support Mechanical Presence 4818 * Switches. 4819 * 4820 * When set, it indicates that a mechanical presence switch attached to this 4821 * port has been opened or closed, which may lead to a change in the connection 4822 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4823 * are set to '1'. 4824 * 4825 * At the moment, this interrupt is not needed and disabled and we just log 4826 * the debug message. 4827 */ 4828 /* ARGSUSED */ 4829 static int 4830 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4831 ahci_port_t *ahci_portp, uint8_t port) 4832 { 4833 uint32_t cap_status, port_cmd_status; 4834 4835 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4836 "ahci_intr_device_mechanical_presence_status enter, " 4837 "port %d", port); 4838 4839 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4840 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4841 4842 mutex_enter(&ahci_portp->ahciport_mutex); 4843 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4844 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4845 4846 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4847 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4848 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4849 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4850 "the interrupt: cap_status = 0x%x, " 4851 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4852 mutex_exit(&ahci_portp->ahciport_mutex); 4853 4854 return (AHCI_SUCCESS); 4855 } 4856 4857 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4858 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4859 "The mechanical presence switch is open: " 4860 "port %d, port_cmd_status = 0x%x", 4861 port, port_cmd_status); 4862 } else { 4863 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4864 "The mechanical presence switch is close: " 4865 "port %d, port_cmd_status = 0x%x", 4866 port, port_cmd_status); 4867 } 4868 4869 mutex_exit(&ahci_portp->ahciport_mutex); 4870 4871 return (AHCI_SUCCESS); 4872 } 4873 4874 /* 4875 * Native Hot Plug Support. 4876 * 4877 * When set, it indicates that the internal PHYRDY signal changed state. 4878 * This bit reflects the state of PxSERR.DIAG.N. 4879 * 4880 * There are three kinds of conditions to generate this interrupt event: 4881 * 1. a device is inserted 4882 * 2. a device is disconnected 4883 * 3. when the link enters/exits a Partial or Slumber interface power 4884 * management state 4885 * 4886 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4887 * bit may be set due to the link entering the Partial or Slumber power 4888 * management state, rather than due to a hot plug insertion or removal 4889 * event. So far, the interface power management is disabled, so the 4890 * driver can reliably get removal detection notification via the 4891 * PxSERR.DIAG.N bit. 4892 */ 4893 static int 4894 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4895 ahci_port_t *ahci_portp, uint8_t port) 4896 { 4897 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4898 sata_device_t sdevice; 4899 int dev_exists_now = 0; 4900 int dev_existed_previously = 0; 4901 4902 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4903 "ahci_intr_phyrdy_change enter, port %d", port); 4904 4905 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4906 mutex_enter(&ahci_portp->ahciport_mutex); 4907 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4908 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4909 SERROR_PHY_RDY_CHG); 4910 mutex_exit(&ahci_portp->ahciport_mutex); 4911 4912 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4913 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4914 (ahci_portp == NULL)) { 4915 /* The whole controller setup is not yet done. */ 4916 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4917 return (AHCI_SUCCESS); 4918 } 4919 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4920 4921 mutex_enter(&ahci_portp->ahciport_mutex); 4922 4923 /* SStatus tells the presence of device. */ 4924 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4925 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4926 4927 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 4928 dev_exists_now = 1; 4929 } 4930 4931 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4932 dev_existed_previously = 1; 4933 } 4934 4935 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 4936 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 4937 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4938 "ahci_intr_phyrdy_change: port %d " 4939 "AHCI_PORT_FLAG_NODEV is cleared", port); 4940 if (dev_exists_now == 0) 4941 dev_existed_previously = 1; 4942 } 4943 4944 bzero((void *)&sdevice, sizeof (sata_device_t)); 4945 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4946 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4947 sdevice.satadev_addr.pmport = 0; 4948 sdevice.satadev_state = SATA_PSTATE_PWRON; 4949 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4950 4951 if (dev_exists_now) { 4952 if (dev_existed_previously) { 4953 /* Things are fine now. The loss was temporary. */ 4954 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4955 "ahci_intr_phyrdy_change port %d " 4956 "device link lost/established", port); 4957 4958 mutex_exit(&ahci_portp->ahciport_mutex); 4959 sata_hba_event_notify( 4960 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4961 &sdevice, 4962 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4963 mutex_enter(&ahci_portp->ahciport_mutex); 4964 4965 } else { 4966 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4967 "ahci_intr_phyrdy_change: port %d " 4968 "device link established", port); 4969 4970 /* A new device has been detected. */ 4971 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 4972 4973 /* Try to start the port */ 4974 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4975 != AHCI_SUCCESS) { 4976 sdevice.satadev_state |= SATA_PSTATE_FAILED; 4977 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4978 "ahci_intr_phyrdy_change: port %d failed " 4979 "at start port", port); 4980 } 4981 4982 /* Clear the max queue depth for inserted device */ 4983 ahci_portp->ahciport_max_ncq_tags = 0; 4984 4985 mutex_exit(&ahci_portp->ahciport_mutex); 4986 sata_hba_event_notify( 4987 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4988 &sdevice, 4989 SATA_EVNT_LINK_ESTABLISHED); 4990 mutex_enter(&ahci_portp->ahciport_mutex); 4991 4992 } 4993 } else { /* No device exists now */ 4994 4995 if (dev_existed_previously) { 4996 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4997 "ahci_intr_phyrdy_change: port %d " 4998 "device link lost", port); 4999 5000 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 5001 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 5002 ahci_portp, port); 5003 5004 /* An existing device is lost. */ 5005 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 5006 5007 mutex_exit(&ahci_portp->ahciport_mutex); 5008 sata_hba_event_notify( 5009 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5010 &sdevice, 5011 SATA_EVNT_LINK_LOST); 5012 mutex_enter(&ahci_portp->ahciport_mutex); 5013 5014 } else { 5015 5016 /* Spurious interrupt */ 5017 AHCIDBG0(AHCIDBG_INTR, ahci_ctlp, 5018 "ahci_intr_phyrdy_change: " 5019 "spurious phy ready interrupt"); 5020 } 5021 } 5022 5023 mutex_exit(&ahci_portp->ahciport_mutex); 5024 5025 return (AHCI_SUCCESS); 5026 } 5027 5028 /* 5029 * PxIS.UFS - Unknown FIS Error 5030 * 5031 * This interrupt event means an unknown FIS was received and has been 5032 * copied into system memory. An unknown FIS is not considered an illegal 5033 * FIS, unless the length received is more than 64 bytes. If an unknown 5034 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 5035 * normal operation. If the unknown FIS is more than 64 bytes, then it 5036 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 5037 * a fatal error. 5038 * 5039 * PxIS.OFS - Overflow Error 5040 * 5041 * Command list overflow is defined as software building a command table 5042 * that has fewer total bytes than the transaction given to the device. 5043 * On device writes, the HBA will run out of data, and on reads, there 5044 * will be no room to put the data. 5045 * 5046 * For an overflow on data read, either PIO or DMA, the HBA will set 5047 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 5048 * non-fatal error when the HBA can continues. Sometimes, it will cause 5049 * a fatal error and need the software to do something. 5050 * 5051 * For an overflow on data write, setting PxIS.OFS is optional for both 5052 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 5053 * software to clean up from this serious error. 5054 * 5055 * PxIS.INFS - Interface Non-Fatal Error 5056 * 5057 * This interrupt event indicates that the HBA encountered an error on 5058 * the Serial ATA interface but was able to continue operation. The kind 5059 * of error usually occurred during a non-Data FIS, and under this condition 5060 * the FIS will be re-transmitted by HBA automatically. 5061 * 5062 * When the FMA is implemented, there should be a stat structure to 5063 * record how many every kind of error happens. 5064 */ 5065 static int 5066 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5067 uint8_t port, uint32_t intr_status) 5068 { 5069 uint32_t port_serror; 5070 #if AHCI_DEBUG 5071 uint32_t port_cmd_status; 5072 uint32_t port_cmd_issue; 5073 uint32_t port_sactive; 5074 int current_slot; 5075 uint32_t current_tags; 5076 sata_pkt_t *satapkt; 5077 #endif 5078 5079 mutex_enter(&ahci_portp->ahciport_mutex); 5080 5081 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5082 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5083 5084 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 5085 "ahci_intr_non_fatal_error: port %d, " 5086 "port_serror = 0x%x", port, port_serror); 5087 5088 ahci_log_serror_message(ahci_ctlp, port, port_serror); 5089 5090 if (intr_status & AHCI_INTR_STATUS_UFS) { 5091 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5092 "ahci port %d has unknown FIS error", port); 5093 5094 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 5095 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5096 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5097 SERROR_FIS_TYPE); 5098 } 5099 5100 #if AHCI_DEBUG 5101 if (intr_status & AHCI_INTR_STATUS_OFS) { 5102 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5103 "ahci port %d has overflow error", port); 5104 } 5105 5106 if (intr_status & AHCI_INTR_STATUS_INFS) { 5107 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5108 "ahci port %d has interface non fatal error", port); 5109 } 5110 5111 /* 5112 * Record the error occurred command's slot. 5113 */ 5114 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 5115 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5116 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5117 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5118 5119 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5120 AHCI_CMD_STATUS_CCS_SHIFT; 5121 5122 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5123 satapkt = ahci_portp->ahciport_err_retri_pkt; 5124 ASSERT(satapkt != NULL); 5125 ASSERT(current_slot == 0); 5126 } else { 5127 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5128 } 5129 5130 if (satapkt != NULL) { 5131 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5132 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 5133 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 5134 satapkt->satapkt_cmd.satacmd_cmd_reg); 5135 5136 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5137 "ahci_intr_non_fatal_error: port %d, " 5138 "satapkt 0x%p is being processed when error occurs", 5139 port, (void *)satapkt); 5140 } 5141 } 5142 5143 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5144 /* 5145 * For queued command, list those command which have already 5146 * been transmitted to the device and still not completed. 5147 */ 5148 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5149 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 5150 5151 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5152 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5153 5154 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 5155 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 5156 "port_sactive = 0x%x port_cmd_issue = 0x%x", 5157 ahci_portp->ahciport_pending_ncq_tags, 5158 port_sactive, port_cmd_issue); 5159 5160 current_tags = ahci_portp->ahciport_pending_ncq_tags & 5161 port_sactive & ~port_cmd_issue & 5162 AHCI_NCQ_SLOT_MASK(ahci_portp); 5163 5164 while (current_tags) { 5165 current_slot = ddi_ffs(current_tags) - 1; 5166 if (current_slot == -1) { 5167 goto out; 5168 } 5169 5170 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5171 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 5172 ahci_ctlp, "ahci_intr_non_fatal_error: " 5173 "port %d, satapkt 0x%p is outstanding when " 5174 "error occurs", port, (void *)satapkt); 5175 } 5176 } 5177 out: 5178 #endif 5179 mutex_exit(&ahci_portp->ahciport_mutex); 5180 5181 return (AHCI_SUCCESS); 5182 } 5183 5184 /* 5185 * According to the AHCI spec, the error types include system memory 5186 * errors, interface errors, port multiplier errors, device errors, 5187 * command list overflow, command list underflow, native command 5188 * queuing tag errors and pio data transfer errors. 5189 * 5190 * System memory errors such as target abort, master abort, and parity 5191 * may cause the host to stop, and they are serious errors and needed 5192 * to be recovered with software intervention. When system software 5193 * has given a pointer to the HBA that doesn't exist in physical memory, 5194 * a master/target abort error occurs, and PxIS.HBFS will be set. A 5195 * data error such as CRC or parity occurs, the HBA aborts the transfer 5196 * (if necessary) and PxIS.HBDS will be set. 5197 * 5198 * Interface errors are errors that occur due to electrical issues on 5199 * the interface, or protocol miscommunication between the device and 5200 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 5201 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 5202 * causes PxIS.IFS/PxIS.INFS to be set are 5203 * 1. in PxSERR.ERR, P bit is set to '1' 5204 * 2. in PxSERR.DIAG, C or H bit is set to '1' 5205 * 3. PhyRdy drop unexpectly, N bit is set to '1' 5206 * If the error occurred during a non-data FIS, the FIS must be 5207 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 5208 * the error occurred during a data FIS, the transfer will stop, so 5209 * the error is fatal and PxIS.IFS is set. 5210 * 5211 * When a FIS arrives that updates the taskfile, the HBA checks to see 5212 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 5213 * stops processing any more commands. 5214 * 5215 * Command list overflow is defined as software building a command table 5216 * that has fewer total bytes than the transaction given to the device. 5217 * On device writes, the HBA will run out of data, and on reads, there 5218 * will be no room to put the data. For an overflow on data read, either 5219 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 5220 * For an overflow on data write, setting PxIS.OFS is optional for both 5221 * DMA and PIO, and a COMRESET is required by software to clean up from 5222 * this serious error. 5223 * 5224 * Command list underflow is defined as software building a command 5225 * table that has more total bytes than the transaction given to the 5226 * device. For data writes, both PIO and DMA, the device will detect 5227 * an error and end the transfer. And these errors are most likely going 5228 * to be fatal errors that will cause the port to be restarted. For 5229 * data reads, the HBA updates its PRD byte count, and may be 5230 * able to continue normally, but is not required to. And The HBA is 5231 * not required to detect underflow conditions for native command 5232 * queuing command. 5233 * 5234 * The HBA does not actively check incoming DMA Setup FISes to ensure 5235 * that the PxSACT register bit for that slot is set. Existing error 5236 * mechanisms, such as host bus failure, or bad protocol, are used to 5237 * recover from this case. 5238 * 5239 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 5240 * DATA FIS must be an integral number of Dwords. If the HBA receives 5241 * a request which is not an integral number of Dwords, the HBA 5242 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 5243 * software restarts the port. And the HBA ensures that the size 5244 * of the DATA FIS received during a PIO command matches the size in 5245 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 5246 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 5247 * stop running until software restarts the port. 5248 */ 5249 /* 5250 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 5251 * 5252 * PxIS.IFS indicates that the hba encountered an error on the serial ata 5253 * interface which caused the transfer to stop. 5254 * 5255 * PxIS.HBDS indicates that the hba encountered a data error 5256 * (uncorrectable ecc/parity) when reading from or writing to system memory. 5257 * 5258 * PxIS.HBFS indicates that the hba encountered a host bus error that it 5259 * cannot recover from, such as a bad software pointer. 5260 * 5261 * PxIS.TFES is set whenever the status register is updated by the device 5262 * and the error bit (bit 0) is set. 5263 */ 5264 static int 5265 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 5266 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 5267 { 5268 uint32_t port_cmd_status; 5269 uint32_t port_serror; 5270 uint32_t task_file_status; 5271 int failed_slot; 5272 sata_pkt_t *spkt = NULL; 5273 uint8_t err_byte; 5274 ahci_event_arg_t *args; 5275 5276 mutex_enter(&ahci_portp->ahciport_mutex); 5277 5278 /* 5279 * ahci_intr_phyrdy_change() may have rendered it to 5280 * SATA_DTYPE_NONE. 5281 */ 5282 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5283 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5284 "ahci_intr_fatal_error: port %d no device attached, " 5285 "and just return without doing anything", port); 5286 goto out0; 5287 } 5288 5289 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5290 /* 5291 * Read PxCMD.CCS to determine the slot that the HBA 5292 * was processing when the error occurred. 5293 */ 5294 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5295 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5296 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5297 AHCI_CMD_STATUS_CCS_SHIFT; 5298 5299 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5300 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5301 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5302 "fatal error occurred for port %d", spkt, port); 5303 5304 if (intr_status & AHCI_INTR_STATUS_TFES) { 5305 task_file_status = ddi_get32( 5306 ahci_ctlp->ahcictl_ahci_acc_handle, 5307 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5308 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5309 "ahci_intr_fatal_error: port %d " 5310 "task_file_status = 0x%x", port, task_file_status); 5311 5312 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5313 >> AHCI_TFD_ERR_SHIFT; 5314 5315 /* 5316 * Won't emit the error message if it is an IDENTIFY 5317 * DEVICE command sent to an ATAPI device. 5318 */ 5319 if ((spkt != NULL) && 5320 (spkt->satapkt_cmd.satacmd_cmd_reg == 5321 SATAC_ID_DEVICE) && 5322 (err_byte == SATA_ERROR_ABORT)) 5323 goto out1; 5324 5325 /* 5326 * Won't emit the error message if it is an ATAPI PACKET 5327 * command 5328 */ 5329 if ((spkt != NULL) && 5330 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5331 goto out1; 5332 } 5333 } 5334 5335 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5336 5337 out1: 5338 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5339 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5340 ahci_log_serror_message(ahci_ctlp, port, port_serror); 5341 5342 /* Prepare the argument for the taskq */ 5343 args = ahci_portp->ahciport_event_args; 5344 args->ahciea_ctlp = (void *)ahci_ctlp; 5345 args->ahciea_portp = (void *)ahci_portp; 5346 args->ahciea_event = intr_status; 5347 5348 /* Start the taskq to handle error recovery */ 5349 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 5350 ahci_events_handler, 5351 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5352 cmn_err(CE_WARN, "ahci start taskq for event handler failed"); 5353 } 5354 out0: 5355 mutex_exit(&ahci_portp->ahciport_mutex); 5356 5357 return (AHCI_SUCCESS); 5358 } 5359 5360 /* 5361 * Hot Plug Operation for platforms that support Cold Presence Detect. 5362 * 5363 * When set, a device status has changed as detected by the cold presence 5364 * detect logic. This bit can either be set due to a non-connected port 5365 * receiving a device, or a connected port having its device removed. 5366 * This bit is only valid if the port supports cold presence detect as 5367 * indicated by PxCMD.CPD set to '1'. 5368 * 5369 * At the moment, this interrupt is not needed and disabled and we just 5370 * log the debug message. 5371 */ 5372 /* ARGSUSED */ 5373 static int 5374 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5375 ahci_port_t *ahci_portp, uint8_t port) 5376 { 5377 uint32_t port_cmd_status; 5378 sata_device_t sdevice; 5379 5380 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5381 "ahci_intr_cold_port_detect enter, port %d", port); 5382 5383 mutex_enter(&ahci_portp->ahciport_mutex); 5384 5385 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5386 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5387 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5388 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5389 "port %d does not support cold presence detect, so " 5390 "we just ignore this interrupt", port); 5391 mutex_exit(&ahci_portp->ahciport_mutex); 5392 return (AHCI_SUCCESS); 5393 } 5394 5395 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5396 "port %d device status has changed", port); 5397 5398 bzero((void *)&sdevice, sizeof (sata_device_t)); 5399 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5400 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5401 sdevice.satadev_addr.pmport = 0; 5402 sdevice.satadev_state = SATA_PSTATE_PWRON; 5403 5404 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5405 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5406 "port %d: a device is hot plugged", port); 5407 mutex_exit(&ahci_portp->ahciport_mutex); 5408 sata_hba_event_notify( 5409 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5410 &sdevice, 5411 SATA_EVNT_DEVICE_ATTACHED); 5412 mutex_enter(&ahci_portp->ahciport_mutex); 5413 5414 } else { 5415 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5416 "port %d: a device is hot unplugged", port); 5417 mutex_exit(&ahci_portp->ahciport_mutex); 5418 sata_hba_event_notify( 5419 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5420 &sdevice, 5421 SATA_EVNT_DEVICE_DETACHED); 5422 mutex_enter(&ahci_portp->ahciport_mutex); 5423 } 5424 5425 mutex_exit(&ahci_portp->ahciport_mutex); 5426 5427 return (AHCI_SUCCESS); 5428 } 5429 5430 /* 5431 * Enable the interrupts for a particular port. 5432 * 5433 * WARNING!!! ahciport_mutex should be acquired before the function 5434 * is called. 5435 */ 5436 /* ARGSUSED */ 5437 static void 5438 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, 5439 ahci_port_t *ahci_portp, uint8_t port) 5440 { 5441 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5442 "ahci_enable_port_intrs enter, port %d", port); 5443 5444 /* 5445 * Clear port interrupt status before enabling interrupt 5446 */ 5447 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5448 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5449 AHCI_PORT_INTR_MASK); 5450 5451 /* 5452 * Clear the pending bit from IS.IPS 5453 */ 5454 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5455 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5456 5457 /* 5458 * Enable the following interrupts: 5459 * Device to Host Register FIS Interrupt (DHRS) 5460 * PIO Setup FIS Interrupt (PSS) 5461 * Set Device Bits Interrupt (SDBS) 5462 * Unknown FIS Interrupt (UFS) 5463 * Port Connect Change Status (PCS) 5464 * PhyRdy Change Status (PRCS) 5465 * Overflow Status (OFS) 5466 * Interface Non-fatal Error Status (INFS) 5467 * Interface Fatal Error Status (IFS) 5468 * Host Bus Data Error Status (HBDS) 5469 * Host Bus Fatal Error Status (HBFS) 5470 * Task File Error Status (TFES) 5471 */ 5472 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5473 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5474 (AHCI_INTR_STATUS_DHRS | 5475 AHCI_INTR_STATUS_PSS | 5476 AHCI_INTR_STATUS_SDBS | 5477 AHCI_INTR_STATUS_UFS | 5478 AHCI_INTR_STATUS_DPS | 5479 AHCI_INTR_STATUS_PCS | 5480 AHCI_INTR_STATUS_PRCS | 5481 AHCI_INTR_STATUS_OFS | 5482 AHCI_INTR_STATUS_INFS | 5483 AHCI_INTR_STATUS_IFS | 5484 AHCI_INTR_STATUS_HBDS | 5485 AHCI_INTR_STATUS_HBFS | 5486 AHCI_INTR_STATUS_TFES)); 5487 } 5488 5489 /* 5490 * Enable interrupts for all the ports. 5491 * 5492 * WARNING!!! ahcictl_mutex should be acquired before the function 5493 * is called. 5494 */ 5495 static void 5496 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5497 { 5498 uint32_t ghc_control; 5499 5500 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5501 5502 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5503 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5504 5505 ghc_control |= AHCI_HBA_GHC_IE; 5506 5507 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5508 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5509 } 5510 5511 /* 5512 * Disable interrupts for a particular port. 5513 * 5514 * WARNING!!! ahciport_mutex should be acquired before the function 5515 * is called. 5516 */ 5517 /* ARGSUSED */ 5518 static void 5519 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, 5520 ahci_port_t *ahci_portp, uint8_t port) 5521 { 5522 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5523 "ahci_disable_port_intrs enter, port %d", port); 5524 5525 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5526 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5527 } 5528 5529 /* 5530 * Disable interrupts for the whole HBA. 5531 * 5532 * The global bit is cleared, then all interrupt sources from all 5533 * ports are disabled. 5534 * 5535 * WARNING!!! ahcictl_mutex should be acquired before the function 5536 * is called. 5537 */ 5538 static void 5539 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5540 { 5541 uint32_t ghc_control; 5542 5543 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5544 5545 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5546 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5547 5548 ghc_control &= ~ AHCI_HBA_GHC_IE; 5549 5550 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5551 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5552 } 5553 5554 /* 5555 * Handle INTx and legacy interrupts. 5556 */ 5557 static int 5558 ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 5559 { 5560 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5561 int actual, count = 0; 5562 int x, y, rc, inum = 0; 5563 5564 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5565 "ahci_add_legacy_intrs enter"); 5566 5567 /* get number of interrupts. */ 5568 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 5569 if ((rc != DDI_SUCCESS) || (count == 0)) { 5570 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5571 "ddi_intr_get_nintrs() failed, " 5572 "rc %d count %d\n", rc, count); 5573 return (DDI_FAILURE); 5574 } 5575 5576 /* Allocate an array of interrupt handles. */ 5577 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5578 ahci_ctlp->ahcictl_intr_htable = 5579 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5580 5581 /* call ddi_intr_alloc(). */ 5582 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5583 DDI_INTR_TYPE_FIXED, 5584 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 5585 5586 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5587 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5588 "ddi_intr_alloc() failed, rc %d\n", rc); 5589 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5590 ahci_ctlp->ahcictl_intr_size); 5591 return (DDI_FAILURE); 5592 } 5593 5594 if (actual < count) { 5595 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5596 "Requested: %d, Received: %d", count, actual); 5597 5598 for (x = 0; x < actual; x++) { 5599 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5600 } 5601 5602 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5603 ahci_ctlp->ahcictl_intr_size); 5604 return (DDI_FAILURE); 5605 } 5606 5607 ahci_ctlp->ahcictl_intr_cnt = actual; 5608 5609 /* Get intr priority. */ 5610 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5611 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5612 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5613 "ddi_intr_get_pri() failed"); 5614 5615 for (x = 0; x < actual; x++) { 5616 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5617 } 5618 5619 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5620 ahci_ctlp->ahcictl_intr_size); 5621 return (DDI_FAILURE); 5622 } 5623 5624 /* Test for high level interrupt. */ 5625 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5626 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5627 "ahci_add_legacy_intrs: Hi level intr not supported"); 5628 5629 for (x = 0; x < actual; x++) { 5630 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5631 } 5632 5633 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5634 sizeof (ddi_intr_handle_t)); 5635 5636 return (DDI_FAILURE); 5637 } 5638 5639 /* Call ddi_intr_add_handler(). */ 5640 for (x = 0; x < actual; x++) { 5641 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5642 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5643 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5644 "ddi_intr_add_handler() failed"); 5645 5646 for (y = 0; y < actual; y++) { 5647 (void) ddi_intr_free( 5648 ahci_ctlp->ahcictl_intr_htable[y]); 5649 } 5650 5651 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5652 ahci_ctlp->ahcictl_intr_size); 5653 return (DDI_FAILURE); 5654 } 5655 } 5656 5657 /* Call ddi_intr_enable() for legacy interrupts. */ 5658 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5659 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 5660 } 5661 5662 return (DDI_SUCCESS); 5663 } 5664 5665 /* 5666 * Handle MSI interrupts. 5667 */ 5668 static int 5669 ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 5670 { 5671 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5672 int count, avail, actual; 5673 int x, y, rc, inum = 0; 5674 5675 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5676 "ahci_add_msi_intrs enter"); 5677 5678 /* get number of interrupts. */ 5679 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 5680 if ((rc != DDI_SUCCESS) || (count == 0)) { 5681 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5682 "ddi_intr_get_nintrs() failed, " 5683 "rc %d count %d\n", rc, count); 5684 return (DDI_FAILURE); 5685 } 5686 5687 /* get number of available interrupts. */ 5688 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 5689 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5690 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5691 "ddi_intr_get_navail() failed, " 5692 "rc %d avail %d\n", rc, avail); 5693 return (DDI_FAILURE); 5694 } 5695 5696 if (avail < count) { 5697 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5698 "ddi_intr_get_nvail returned %d, navail() returned %d", 5699 count, avail); 5700 } 5701 5702 /* Allocate an array of interrupt handles. */ 5703 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5704 ahci_ctlp->ahcictl_intr_htable = 5705 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5706 5707 /* call ddi_intr_alloc(). */ 5708 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5709 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5710 5711 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5712 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5713 "ddi_intr_alloc() failed, rc %d\n", rc); 5714 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5715 ahci_ctlp->ahcictl_intr_size); 5716 return (DDI_FAILURE); 5717 } 5718 5719 /* use interrupt count returned */ 5720 if (actual < count) { 5721 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5722 "Requested: %d, Received: %d", count, actual); 5723 } 5724 5725 ahci_ctlp->ahcictl_intr_cnt = actual; 5726 5727 /* 5728 * Get priority for first msi, assume remaining are all the same. 5729 */ 5730 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5731 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5732 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5733 "ddi_intr_get_pri() failed"); 5734 5735 /* Free already allocated intr. */ 5736 for (y = 0; y < actual; y++) { 5737 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5738 } 5739 5740 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5741 ahci_ctlp->ahcictl_intr_size); 5742 return (DDI_FAILURE); 5743 } 5744 5745 /* Test for high level interrupt. */ 5746 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5747 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5748 "ahci_add_msi_intrs: Hi level intr not supported"); 5749 5750 /* Free already allocated intr. */ 5751 for (y = 0; y < actual; y++) { 5752 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5753 } 5754 5755 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5756 sizeof (ddi_intr_handle_t)); 5757 5758 return (DDI_FAILURE); 5759 } 5760 5761 /* Call ddi_intr_add_handler(). */ 5762 for (x = 0; x < actual; x++) { 5763 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5764 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5765 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5766 "ddi_intr_add_handler() failed"); 5767 5768 /* Free already allocated intr. */ 5769 for (y = 0; y < actual; y++) { 5770 (void) ddi_intr_free( 5771 ahci_ctlp->ahcictl_intr_htable[y]); 5772 } 5773 5774 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5775 ahci_ctlp->ahcictl_intr_size); 5776 return (DDI_FAILURE); 5777 } 5778 } 5779 5780 5781 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5782 &ahci_ctlp->ahcictl_intr_cap); 5783 5784 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5785 /* Call ddi_intr_block_enable() for MSI. */ 5786 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5787 ahci_ctlp->ahcictl_intr_cnt); 5788 } else { 5789 /* Call ddi_intr_enable() for MSI non block enable. */ 5790 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5791 (void) ddi_intr_enable( 5792 ahci_ctlp->ahcictl_intr_htable[x]); 5793 } 5794 } 5795 5796 return (DDI_SUCCESS); 5797 } 5798 5799 /* 5800 * Removes the registered interrupts irrespective of whether they 5801 * were legacy or MSI. 5802 * 5803 * WARNING!!! The controller interrupts must be disabled before calling 5804 * this routine. 5805 */ 5806 static void 5807 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5808 { 5809 int x; 5810 5811 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5812 5813 /* Disable all interrupts. */ 5814 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5815 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5816 /* Call ddi_intr_block_disable(). */ 5817 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5818 ahci_ctlp->ahcictl_intr_cnt); 5819 } else { 5820 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5821 (void) ddi_intr_disable( 5822 ahci_ctlp->ahcictl_intr_htable[x]); 5823 } 5824 } 5825 5826 /* Call ddi_intr_remove_handler(). */ 5827 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5828 (void) ddi_intr_remove_handler( 5829 ahci_ctlp->ahcictl_intr_htable[x]); 5830 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5831 } 5832 5833 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5834 } 5835 5836 /* 5837 * This routine tries to put port into P:NotRunning state by clearing 5838 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5839 * and PxCMD.CR to '0'. 5840 * 5841 * WARNING!!! ahciport_mutex should be acquired before the function 5842 * is called. 5843 */ 5844 /* ARGSUSED */ 5845 static int 5846 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5847 ahci_port_t *ahci_portp, uint8_t port) 5848 { 5849 uint32_t port_cmd_status; 5850 int loop_count; 5851 5852 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5853 "ahci_put_port_into_notrunning_state enter: port %d", port); 5854 5855 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5856 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5857 5858 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5859 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5860 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5861 5862 /* Wait until PxCMD.CR is cleared */ 5863 loop_count = 0; 5864 do { 5865 port_cmd_status = 5866 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5867 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5868 5869 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5870 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5871 "clearing port %d CMD.CR timeout, " 5872 "port_cmd_status = 0x%x", port, 5873 port_cmd_status); 5874 /* 5875 * We are effectively timing out after 0.5 sec. 5876 * This value is specified in AHCI spec. 5877 */ 5878 break; 5879 } 5880 5881 /* Wait for 10 millisec */ 5882 #ifndef __lock_lint 5883 delay(AHCI_10MS_TICKS); 5884 #endif /* __lock_lint */ 5885 5886 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5887 5888 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5889 5890 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5891 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5892 "ahci_put_port_into_notrunning_state: failed to clear " 5893 "PxCMD.CR to '0' after loop count: %d, and " 5894 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5895 return (AHCI_FAILURE); 5896 } else { 5897 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5898 "ahci_put_port_into_notrunning_state: succeeded to clear " 5899 "PxCMD.CR to '0' after loop count: %d, and " 5900 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5901 return (AHCI_SUCCESS); 5902 } 5903 } 5904 5905 /* 5906 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5907 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5908 * stable state, then set PxCMD.ST to '1' to start the port directly. 5909 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5910 * COMRESET to the device to put it in an idle state. 5911 * 5912 * The fifth argument returns whether the port reset is involved during 5913 * the process. 5914 * 5915 * The routine will be called under six scenarios: 5916 * 1. Initialize the port 5917 * 2. To abort the packet(s) 5918 * 3. To reset the port 5919 * 4. To activate the port 5920 * 5. Fatal error recovery 5921 * 6. To abort the timeout packet(s) 5922 * 5923 * WARNING!!! ahciport_mutex should be acquired before the function 5924 * is called. And ahciport_mutex will be released before the reset 5925 * event is reported to sata module by calling sata_hba_event_notify, 5926 * and then be acquired again later. 5927 * 5928 * NOTES!!! During this procedure, PxSERR register will be cleared, and 5929 * according to the spec, the clearance of three bits will also clear 5930 * three interrupt status bits. 5931 * 1. PxSERR.DIAG.F will clear PxIS.UFS 5932 * 2. PxSERR.DIAG.X will clear PxIS.PCS 5933 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 5934 * 5935 * Among these three interrupt events, the driver needs to take care of 5936 * PxIS.PRCS, which is the hot plug event. When the driver found out 5937 * a device was unplugged, it will call the interrupt handler. 5938 */ 5939 static int 5940 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5941 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 5942 { 5943 uint32_t port_sstatus; 5944 uint32_t task_file_status; 5945 sata_device_t sdevice; 5946 int rval; 5947 int dev_exists_begin = 0; 5948 int dev_exists_end = 0; 5949 5950 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5951 "ahci_restart_port_wait_till_ready: port %d enter", port); 5952 5953 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) 5954 dev_exists_begin = 1; 5955 5956 /* First clear PxCMD.ST */ 5957 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 5958 port); 5959 if (rval != AHCI_SUCCESS) 5960 /* 5961 * If PxCMD.CR does not clear within a reasonable time, it 5962 * may assume the interface is in a hung condition and may 5963 * continue with issuing the port reset. 5964 */ 5965 goto reset; 5966 5967 /* Then clear PxSERR */ 5968 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5969 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5970 AHCI_SERROR_CLEAR_ALL); 5971 5972 /* Then get PxTFD */ 5973 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5974 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5975 5976 /* 5977 * Check whether the device is in a stable status, if yes, 5978 * then start the port directly. However for ahci_tran_dport_reset, 5979 * we may have to perform a port reset. 5980 */ 5981 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 5982 !(flag & AHCI_PORT_RESET)) 5983 goto out; 5984 5985 reset: 5986 /* 5987 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 5988 * a COMRESET to the device 5989 */ 5990 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 5991 if (rval != AHCI_SUCCESS) 5992 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5993 "ahci_restart_port_wait_till_ready: port %d failed", 5994 port); 5995 5996 if (reset_flag != NULL) 5997 *reset_flag = 1; 5998 5999 /* Indicate to the framework that a reset has happened. */ 6000 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 6001 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 6002 /* Set the reset in progress flag */ 6003 ahci_portp->ahciport_reset_in_progress = 1; 6004 6005 bzero((void *)&sdevice, sizeof (sata_device_t)); 6006 sdevice.satadev_addr.cport = 6007 ahci_ctlp->ahcictl_port_to_cport[port]; 6008 sdevice.satadev_addr.pmport = 0; 6009 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6010 6011 sdevice.satadev_state = SATA_DSTATE_RESET | 6012 SATA_DSTATE_PWR_ACTIVE; 6013 if (ahci_ctlp->ahcictl_sata_hba_tran) { 6014 mutex_exit(&ahci_portp->ahciport_mutex); 6015 sata_hba_event_notify( 6016 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 6017 &sdevice, 6018 SATA_EVNT_DEVICE_RESET); 6019 mutex_enter(&ahci_portp->ahciport_mutex); 6020 } 6021 6022 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 6023 "port %d sending event up: SATA_EVNT_RESET", port); 6024 } else { 6025 ahci_portp->ahciport_reset_in_progress = 0; 6026 } 6027 6028 out: 6029 /* Start the port */ 6030 if (!(flag & AHCI_PORT_INIT)) { 6031 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 6032 } 6033 6034 /* SStatus tells the presence of device. */ 6035 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6036 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 6037 6038 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 6039 dev_exists_end = 1; 6040 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 6041 } 6042 6043 /* Check whether a hot plug event happened */ 6044 if (dev_exists_begin == 1 && dev_exists_end == 0) { 6045 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6046 "ahci_restart_port_wait_till_ready: port %d " 6047 "device is removed", port); 6048 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 6049 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6050 "ahci_restart_port_wait_till_ready: port %d " 6051 "AHCI_PORT_FLAG_NODEV flag is set", port); 6052 mutex_exit(&ahci_portp->ahciport_mutex); 6053 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 6054 mutex_enter(&ahci_portp->ahciport_mutex); 6055 } 6056 6057 return (rval); 6058 } 6059 6060 /* 6061 * This routine may be called under four scenarios: 6062 * a) do the recovery from fatal error 6063 * b) or we need to timeout some commands 6064 * c) or we need to abort some commands 6065 * d) or we need reset device/port/controller 6066 * 6067 * In all these scenarios, we need to send any pending unfinished 6068 * commands up to sata framework. 6069 * 6070 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6071 */ 6072 static void 6073 ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 6074 ahci_port_t *ahci_portp, 6075 uint8_t port, 6076 uint32_t slot_status, 6077 uint32_t failed_tags, 6078 uint32_t timeout_tags, 6079 uint32_t aborted_tags, 6080 uint32_t reset_tags) 6081 { 6082 uint32_t finished_tags = 0; 6083 uint32_t unfinished_tags = 0; 6084 int tmp_slot; 6085 sata_pkt_t *satapkt; 6086 int ncq_cmd_in_progress = 0; 6087 int err_retri_cmd_in_progress = 0; 6088 6089 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6090 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 6091 port, slot_status); 6092 6093 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6094 "ahci_mop_commands: failed_tags: 0x%x, " 6095 "timeout_tags: 0x%x aborted_tags: 0x%x, " 6096 "reset_tags: 0x%x", failed_tags, 6097 timeout_tags, aborted_tags, reset_tags); 6098 6099 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6100 finished_tags = ahci_portp->ahciport_pending_tags & 6101 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6102 6103 unfinished_tags = slot_status & 6104 AHCI_SLOT_MASK(ahci_ctlp) & 6105 ~failed_tags & 6106 ~aborted_tags & 6107 ~reset_tags & 6108 ~timeout_tags; 6109 } 6110 6111 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6112 ncq_cmd_in_progress = 1; 6113 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6114 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6115 6116 unfinished_tags = slot_status & 6117 AHCI_NCQ_SLOT_MASK(ahci_portp) & 6118 ~failed_tags & 6119 ~aborted_tags & 6120 ~reset_tags & 6121 ~timeout_tags; 6122 } 6123 6124 /* 6125 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is set, 6126 * it means REQUEST SENSE or READ LOG EXT command doesn't complete 6127 * successfully due to one of the following three conditions: 6128 * 6129 * 1. Fatal error - failed_tags includes its slot 6130 * 2. Timed out - timeout_tags includes its slot 6131 * 3. Aborted when hot unplug - aborted_tags includes its slot 6132 * 6133 * Please note that the command is always sent down in Slot 0 6134 */ 6135 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6136 err_retri_cmd_in_progress = 1; 6137 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 6138 "ahci_mop_commands is called for port %d while " 6139 "REQUEST SENSE or READ LOG EXT for error retrieval " 6140 "is being executed", port); 6141 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 6142 ASSERT(slot_status == 0x1); 6143 } 6144 6145 /* Send up finished packets with SATA_PKT_COMPLETED */ 6146 while (finished_tags) { 6147 tmp_slot = ddi_ffs(finished_tags) - 1; 6148 if (tmp_slot == -1) { 6149 break; 6150 } 6151 6152 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6153 ASSERT(satapkt != NULL); 6154 6155 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 6156 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 6157 (void *)satapkt); 6158 6159 /* 6160 * Cannot fetch the return register content since the port 6161 * was restarted, so the corresponding tag will be set to 6162 * aborted tags. 6163 */ 6164 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6165 CLEAR_BIT(finished_tags, tmp_slot); 6166 aborted_tags |= tmp_slot; 6167 continue; 6168 } 6169 6170 if (ncq_cmd_in_progress) 6171 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6172 tmp_slot); 6173 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6174 CLEAR_BIT(finished_tags, tmp_slot); 6175 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6176 6177 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6178 } 6179 6180 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 6181 while (failed_tags) { 6182 if (err_retri_cmd_in_progress) { 6183 satapkt = ahci_portp->ahciport_err_retri_pkt; 6184 ASSERT(satapkt != NULL); 6185 ASSERT(failed_tags == 0x1); 6186 6187 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6188 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6189 (void *)satapkt); 6190 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6191 break; 6192 } 6193 6194 tmp_slot = ddi_ffs(failed_tags) - 1; 6195 if (tmp_slot == -1) { 6196 break; 6197 } 6198 6199 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6200 ASSERT(satapkt != NULL); 6201 6202 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6203 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6204 (void *)satapkt); 6205 6206 if (ncq_cmd_in_progress) 6207 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6208 tmp_slot); 6209 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6210 CLEAR_BIT(failed_tags, tmp_slot); 6211 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6212 6213 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6214 } 6215 6216 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 6217 while (timeout_tags) { 6218 if (err_retri_cmd_in_progress) { 6219 satapkt = ahci_portp->ahciport_err_retri_pkt; 6220 ASSERT(satapkt != NULL); 6221 ASSERT(timeout_tags == 0x1); 6222 6223 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6224 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6225 (void *)satapkt); 6226 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6227 break; 6228 } 6229 6230 tmp_slot = ddi_ffs(timeout_tags) - 1; 6231 if (tmp_slot == -1) { 6232 break; 6233 } 6234 6235 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6236 ASSERT(satapkt != NULL); 6237 6238 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6239 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6240 (void *)satapkt); 6241 6242 if (ncq_cmd_in_progress) 6243 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6244 tmp_slot); 6245 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6246 CLEAR_BIT(timeout_tags, tmp_slot); 6247 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6248 6249 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6250 } 6251 6252 /* Send up aborted packets with SATA_PKT_ABORTED */ 6253 while (aborted_tags) { 6254 if (err_retri_cmd_in_progress) { 6255 satapkt = ahci_portp->ahciport_err_retri_pkt; 6256 ASSERT(satapkt != NULL); 6257 ASSERT(aborted_tags == 0x1); 6258 6259 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6260 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6261 (void *)satapkt); 6262 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6263 break; 6264 } 6265 6266 tmp_slot = ddi_ffs(aborted_tags) - 1; 6267 if (tmp_slot == -1) { 6268 break; 6269 } 6270 6271 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6272 ASSERT(satapkt != NULL); 6273 6274 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6275 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6276 (void *)satapkt); 6277 6278 if (ncq_cmd_in_progress) 6279 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6280 tmp_slot); 6281 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6282 CLEAR_BIT(aborted_tags, tmp_slot); 6283 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6284 6285 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6286 } 6287 6288 /* Send up reset packets with SATA_PKT_RESET. */ 6289 while (reset_tags) { 6290 tmp_slot = ddi_ffs(reset_tags) - 1; 6291 if (tmp_slot == -1) { 6292 break; 6293 } 6294 6295 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6296 ASSERT(satapkt != NULL); 6297 6298 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6299 "sending up pkt 0x%p with SATA_PKT_RESET", 6300 (void *)satapkt); 6301 6302 if (ncq_cmd_in_progress) 6303 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6304 tmp_slot); 6305 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6306 CLEAR_BIT(reset_tags, tmp_slot); 6307 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6308 6309 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6310 } 6311 6312 /* Send up unfinished packets with SATA_PKT_RESET */ 6313 while (unfinished_tags) { 6314 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6315 if (tmp_slot == -1) { 6316 break; 6317 } 6318 6319 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6320 ASSERT(satapkt != NULL); 6321 6322 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6323 "sending up pkt 0x%p with SATA_PKT_RESET", 6324 (void *)satapkt); 6325 6326 if (ncq_cmd_in_progress) 6327 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6328 tmp_slot); 6329 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6330 CLEAR_BIT(unfinished_tags, tmp_slot); 6331 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6332 6333 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6334 } 6335 6336 ahci_portp->ahciport_mop_in_progress--; 6337 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6338 6339 if (ahci_portp->ahciport_mop_in_progress == 0) 6340 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6341 } 6342 6343 /* 6344 * This routine is going to first request a READ LOG EXT sata pkt from sata 6345 * module, and then deliver it to the HBA to get the ncq failure context. 6346 * The return value is the exactly failed tags. 6347 */ 6348 static uint32_t 6349 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6350 uint8_t port) 6351 { 6352 sata_device_t sdevice; 6353 sata_pkt_t *rdlog_spkt, *spkt; 6354 ddi_dma_handle_t buf_dma_handle; 6355 int loop_count; 6356 int rval; 6357 int failed_slot; 6358 uint32_t failed_tags = 0; 6359 struct sata_ncq_error_recovery_page *ncq_err_page; 6360 6361 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6362 "ahci_get_rdlogext_data enter: port %d", port); 6363 6364 /* Prepare the sdevice data */ 6365 bzero((void *)&sdevice, sizeof (sata_device_t)); 6366 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6367 6368 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6369 sdevice.satadev_addr.pmport = 0; 6370 6371 /* 6372 * Call the sata hba interface to get a rdlog spkt 6373 */ 6374 loop_count = 0; 6375 loop: 6376 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6377 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6378 if (rdlog_spkt == NULL) { 6379 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6380 /* Sleep for a while */ 6381 delay(AHCI_10MS_TICKS); 6382 goto loop; 6383 } 6384 /* Timed out after 1s */ 6385 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6386 "failed to get rdlog spkt for port %d", port); 6387 return (failed_tags); 6388 } 6389 6390 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6391 6392 /* 6393 * This flag is used to handle the specific error recovery when the 6394 * READ LOG EXT command gets a failure (fatal error or time-out). 6395 */ 6396 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6397 6398 /* 6399 * This start is not supposed to fail because after port is restarted, 6400 * the whole command list is empty. 6401 */ 6402 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6403 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6404 ahci_portp->ahciport_err_retri_pkt = NULL; 6405 6406 /* Remove the flag after READ LOG EXT command is completed */ 6407 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6408 6409 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6410 /* Update the request log data */ 6411 buf_dma_handle = *(ddi_dma_handle_t *) 6412 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6413 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6414 DDI_DMA_SYNC_FORKERNEL); 6415 if (rval == DDI_SUCCESS) { 6416 ncq_err_page = 6417 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6418 satapkt_cmd.satacmd_bp->b_un.b_addr; 6419 6420 /* Get the failed tag */ 6421 failed_slot = ncq_err_page->ncq_tag; 6422 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6423 "ahci_get_rdlogext_data: port %d " 6424 "failed slot %d", port, failed_slot); 6425 if (failed_slot & NQ) { 6426 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6427 "the failed slot is not a valid tag"); 6428 goto out; 6429 } 6430 6431 failed_slot &= NCQ_TAG_MASK; 6432 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6433 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6434 "ahci_get_rdlogext_data: failed spkt 0x%p", 6435 (void *)spkt); 6436 if (spkt == NULL) { 6437 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6438 "the failed slot spkt is NULL") 6439 goto out; 6440 } 6441 6442 failed_tags = 0x1 << failed_slot; 6443 6444 /* Fill out the error context */ 6445 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6446 ncq_err_page); 6447 ahci_update_sata_registers(ahci_ctlp, port, 6448 &spkt->satapkt_device); 6449 } 6450 } else { 6451 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6452 "ahci_get_rdlogext_data: port %d READ LOG EXT command " 6453 "did not successfully complete", port); 6454 } 6455 out: 6456 sata_free_error_retrieval_pkt(rdlog_spkt); 6457 6458 return (failed_tags); 6459 } 6460 6461 /* 6462 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6463 * module, and then deliver it to the HBA to get the sense data and copy 6464 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6465 * SENSE sata pkt later. 6466 */ 6467 static void 6468 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6469 uint8_t port, sata_pkt_t *spkt) 6470 { 6471 sata_device_t sdevice; 6472 sata_pkt_t *rs_spkt; 6473 sata_cmd_t *sata_cmd; 6474 ddi_dma_handle_t buf_dma_handle; 6475 int loop_count; 6476 #if AHCI_DEBUG 6477 struct scsi_extended_sense *rqsense; 6478 #endif 6479 6480 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6481 "ahci_get_rqsense_data enter: port %d", port); 6482 6483 /* Prepare the sdevice data */ 6484 bzero((void *)&sdevice, sizeof (sata_device_t)); 6485 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6486 6487 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6488 sdevice.satadev_addr.pmport = 0; 6489 6490 sata_cmd = &spkt->satapkt_cmd; 6491 6492 /* 6493 * Call the sata hba interface to get a rs spkt 6494 */ 6495 loop_count = 0; 6496 loop: 6497 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6498 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6499 if (rs_spkt == NULL) { 6500 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6501 /* Sleep for a while */ 6502 delay(AHCI_10MS_TICKS); 6503 goto loop; 6504 6505 } 6506 /* Timed out after 1s */ 6507 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6508 "failed to get rs spkt for port %d", port); 6509 return; 6510 } 6511 6512 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6513 6514 /* 6515 * This flag is used to handle the specific error recovery when the 6516 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6517 */ 6518 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6519 6520 /* 6521 * This start is not supposed to fail because after port is restarted, 6522 * the whole command list is empty. 6523 */ 6524 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6525 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6526 ahci_portp->ahciport_err_retri_pkt = NULL; 6527 6528 /* Remove the flag after REQUEST SENSE command is completed */ 6529 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6530 6531 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6532 /* Update the request sense data */ 6533 buf_dma_handle = *(ddi_dma_handle_t *) 6534 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6535 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6536 DDI_DMA_SYNC_FORKERNEL); 6537 /* Copy the request sense data */ 6538 bcopy(rs_spkt-> 6539 satapkt_cmd.satacmd_bp->b_un.b_addr, 6540 &sata_cmd->satacmd_rqsense, 6541 SATA_ATAPI_MIN_RQSENSE_LEN); 6542 #if AHCI_DEBUG 6543 rqsense = (struct scsi_extended_sense *) 6544 sata_cmd->satacmd_rqsense; 6545 6546 /* Dump the sense data */ 6547 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6548 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6549 "Sense data for satapkt %p ATAPI cmd 0x%x", 6550 spkt, sata_cmd->satacmd_acdb[0]); 6551 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6552 " es_code 0x%x es_class 0x%x " 6553 "es_key 0x%x es_add_code 0x%x " 6554 "es_qual_code 0x%x", 6555 rqsense->es_code, rqsense->es_class, 6556 rqsense->es_key, rqsense->es_add_code, 6557 rqsense->es_qual_code); 6558 #endif 6559 } else { 6560 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6561 "ahci_get_rqsense_data: port %d REQUEST SENSE command " 6562 "did not successfully complete", port); 6563 } 6564 6565 sata_free_error_retrieval_pkt(rs_spkt); 6566 } 6567 6568 /* 6569 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6570 * the port must be restarted. When the HBA detects thus error, it may try 6571 * to abort a transfer. And if the transfer was aborted, the device is 6572 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6573 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6574 * that the device is in a stable status and transfers may be restarted without 6575 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6576 * then the software will send the COMRESET to do the port reset. 6577 * 6578 * Software should perform the appropriate error recovery actions based on 6579 * whether non-queued commands were being issued or natived command queuing 6580 * commands were being issued. 6581 * 6582 * And software will complete the command that had the error with error mark 6583 * to higher level software. 6584 * 6585 * Fatal errors include the following: 6586 * PxIS.IFS - Interface Fatal Error Status 6587 * PxIS.HBDS - Host Bus Data Error Status 6588 * PxIS.HBFS - Host Bus Fatal Error Status 6589 * PxIS.TFES - Task File Error Status 6590 * 6591 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6592 */ 6593 static void 6594 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6595 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6596 { 6597 uint32_t port_cmd_status; 6598 uint32_t slot_status = 0; 6599 uint32_t failed_tags = 0; 6600 int failed_slot; 6601 int reset_flag = 0; 6602 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6603 sata_cmd_t *sata_cmd = NULL; 6604 sata_pkt_t *spkt = NULL; 6605 6606 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6607 "ahci_fatal_error_recovery_handler enter: port %d", port); 6608 6609 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6610 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6611 6612 /* Read PxCI to see which commands are still outstanding */ 6613 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6614 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6615 6616 /* 6617 * Read PxCMD.CCS to determine the slot that the HBA 6618 * was processing when the error occurred. 6619 */ 6620 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6621 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6622 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6623 AHCI_CMD_STATUS_CCS_SHIFT; 6624 6625 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6626 spkt = ahci_portp->ahciport_err_retri_pkt; 6627 ASSERT(spkt != NULL); 6628 } else { 6629 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6630 if (spkt == NULL) { 6631 /* May happen when interface errors occur? */ 6632 goto next; 6633 } 6634 } 6635 6636 sata_cmd = &spkt->satapkt_cmd; 6637 6638 /* Fill out the status and error registers for PxIS.TFES */ 6639 if (intr_status & AHCI_INTR_STATUS_TFES) { 6640 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6641 ahcirf_d2h_register_fis); 6642 6643 /* Copy the error context back to the sata_cmd */ 6644 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6645 } 6646 6647 /* The failed command must be one of the outstanding commands */ 6648 failed_tags = 0x1 << failed_slot; 6649 ASSERT(failed_tags & slot_status); 6650 6651 /* Update the sata registers, especially PxSERR register */ 6652 ahci_update_sata_registers(ahci_ctlp, port, 6653 &spkt->satapkt_device); 6654 6655 } 6656 6657 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6658 /* Read PxSACT to see which commands are still outstanding */ 6659 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6660 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6661 } 6662 next: 6663 6664 #if AHCI_DEBUG 6665 /* 6666 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6667 * set, it means a fatal error happened after REQUEST SENSE command 6668 * or READ LOG EXT command is delivered to the HBA during the error 6669 * recovery process. At this time, the only outstanding command is 6670 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6671 */ 6672 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6673 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6674 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6675 "command or READ LOG EXT command for error data retrieval " 6676 "failed", port); 6677 ASSERT(slot_status == 0x1); 6678 ASSERT(failed_slot == 0x1); 6679 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6680 SCMD_REQUEST_SENSE || 6681 spkt->satapkt_cmd.satacmd_cmd_reg == 6682 SATAC_READ_LOG_EXT); 6683 } 6684 #endif 6685 6686 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6687 ahci_portp->ahciport_mop_in_progress++; 6688 6689 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6690 port, NULL, &reset_flag); 6691 6692 /* 6693 * Won't retrieve error information: 6694 * 1. Port reset was involved to recover 6695 * 2. Device is gone 6696 * 3. IDENTIFY DEVICE command sent to ATAPI device 6697 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6698 */ 6699 if (reset_flag || 6700 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6701 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6702 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6703 goto out; 6704 6705 /* 6706 * Deliver READ LOG EXT to gather information about the error when 6707 * a COMRESET has not been performed as part of the error recovery 6708 * during NCQ command processing. 6709 */ 6710 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6711 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6712 ahci_portp, port); 6713 goto out; 6714 } 6715 6716 /* 6717 * Deliver REQUEST SENSE for ATAPI command to gather information about 6718 * the error when a COMRESET has not been performed as part of the 6719 * error recovery. 6720 */ 6721 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPICD) 6722 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6723 out: 6724 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6725 "ahci_fatal_error_recovery_handler: port %d interface error " 6726 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6727 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6728 port, slot_status, ahci_portp->ahciport_pending_tags, 6729 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6730 6731 ahci_mop_commands(ahci_ctlp, 6732 ahci_portp, 6733 port, 6734 slot_status, 6735 failed_tags, /* failed tags */ 6736 0, /* timeout tags */ 6737 0, /* aborted tags */ 6738 0); /* reset tags */ 6739 } 6740 6741 /* 6742 * Handle events - fatal error recovery 6743 */ 6744 static void 6745 ahci_events_handler(void *args) 6746 { 6747 ahci_event_arg_t *ahci_event_arg; 6748 ahci_ctl_t *ahci_ctlp; 6749 ahci_port_t *ahci_portp; 6750 uint32_t event; 6751 uint8_t port; 6752 6753 ahci_event_arg = (ahci_event_arg_t *)args; 6754 6755 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6756 ahci_portp = ahci_event_arg->ahciea_portp; 6757 event = ahci_event_arg->ahciea_event; 6758 port = ahci_portp->ahciport_port_num; 6759 6760 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6761 "ahci_events_handler enter: port %d intr_status = 0x%x", 6762 port, event); 6763 6764 mutex_enter(&ahci_portp->ahciport_mutex); 6765 6766 /* 6767 * ahci_intr_phyrdy_change() may have rendered it to 6768 * SATA_DTYPE_NONE. 6769 */ 6770 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6771 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6772 "ahci_events_handler: port %d no device attached, " 6773 "and just return without doing anything", port); 6774 goto out; 6775 } 6776 6777 if (event & (AHCI_INTR_STATUS_IFS | 6778 AHCI_INTR_STATUS_HBDS | 6779 AHCI_INTR_STATUS_HBFS | 6780 AHCI_INTR_STATUS_TFES)) 6781 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6782 port, event); 6783 6784 out: 6785 mutex_exit(&ahci_portp->ahciport_mutex); 6786 } 6787 6788 /* 6789 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6790 * detect there are some commands which are timed out. 6791 */ 6792 static void 6793 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6794 uint8_t port, uint32_t tmp_timeout_tags) 6795 { 6796 uint32_t slot_status = 0; 6797 uint32_t finished_tags = 0; 6798 uint32_t timeout_tags = 0; 6799 6800 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6801 "ahci_timeout_pkts enter: port %d", port); 6802 6803 mutex_enter(&ahci_portp->ahciport_mutex); 6804 6805 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6806 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6807 /* Read PxCI to see which commands are still outstanding */ 6808 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6809 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6810 } 6811 6812 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6813 /* Read PxSACT to see which commands are still outstanding */ 6814 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6815 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6816 } 6817 6818 #if AHCI_DEBUG 6819 /* 6820 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6821 * set, it means a fatal error happened after REQUEST SENSE command 6822 * or READ LOG EXT command is delivered to the HBA during the error 6823 * recovery process. At this time, the only outstanding command is 6824 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6825 */ 6826 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6827 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 6828 "ahci_timeout_pkts called while REQUEST SENSE " 6829 "command or READ LOG EXT command for error recovery " 6830 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 6831 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 6832 tmp_timeout_tags, slot_status, 6833 ahci_portp->ahciport_pending_tags, 6834 ahci_portp->ahciport_pending_ncq_tags); 6835 ASSERT(slot_status == 0x1); 6836 } 6837 #endif 6838 6839 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6840 ahci_portp->ahciport_mop_in_progress++; 6841 6842 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6843 port, NULL, NULL); 6844 6845 /* 6846 * Re-identify timeout tags because some previously checked commands 6847 * could already complete. 6848 */ 6849 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6850 finished_tags = ahci_portp->ahciport_pending_tags & 6851 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6852 timeout_tags = tmp_timeout_tags & ~finished_tags; 6853 6854 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 6855 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6856 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 6857 "pending_tags = 0x%x ", 6858 port, finished_tags, timeout_tags, 6859 slot_status, ahci_portp->ahciport_pending_tags); 6860 } 6861 6862 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6863 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6864 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6865 timeout_tags = tmp_timeout_tags & ~finished_tags; 6866 6867 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 6868 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6869 "timeout_tags = 0x%x, port_sactive = 0x%x, " 6870 "pending_ncq_tags = 0x%x ", 6871 port, finished_tags, timeout_tags, 6872 slot_status, ahci_portp->ahciport_pending_ncq_tags); 6873 } 6874 6875 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6876 timeout_tags = tmp_timeout_tags; 6877 } 6878 6879 ahci_mop_commands(ahci_ctlp, 6880 ahci_portp, 6881 port, 6882 slot_status, 6883 0, /* failed tags */ 6884 timeout_tags, /* timeout tags */ 6885 0, /* aborted tags */ 6886 0); /* reset tags */ 6887 6888 mutex_exit(&ahci_portp->ahciport_mutex); 6889 } 6890 6891 /* 6892 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 6893 * for long time. 6894 */ 6895 static void 6896 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 6897 { 6898 ahci_port_t *ahci_portp; 6899 sata_pkt_t *spkt; 6900 uint32_t pending_tags; 6901 uint32_t timeout_tags; 6902 uint32_t port_cmd_status; 6903 uint32_t port_sactive; 6904 uint8_t port; 6905 int tmp_slot; 6906 int current_slot; 6907 uint32_t current_tags; 6908 /* max number of cycles this packet should survive */ 6909 int max_life_cycles; 6910 6911 /* how many cycles this packet survived so far */ 6912 int watched_cycles; 6913 6914 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6915 6916 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6917 "ahci_watchdog_handler entered"); 6918 6919 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6920 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6921 continue; 6922 } 6923 6924 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6925 6926 mutex_enter(&ahci_portp->ahciport_mutex); 6927 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6928 mutex_exit(&ahci_portp->ahciport_mutex); 6929 continue; 6930 } 6931 6932 /* Skip the check for those ports in error recovery */ 6933 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 6934 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 6935 mutex_exit(&ahci_portp->ahciport_mutex); 6936 continue; 6937 } 6938 6939 pending_tags = 0; 6940 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6941 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6942 6943 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6944 current_slot = 0; 6945 pending_tags = 0x1; 6946 } 6947 6948 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6949 current_slot = 6950 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6951 AHCI_CMD_STATUS_CCS_SHIFT; 6952 pending_tags = ahci_portp->ahciport_pending_tags; 6953 } 6954 6955 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6956 port_sactive = ddi_get32( 6957 ahci_ctlp->ahcictl_ahci_acc_handle, 6958 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6959 current_tags = port_sactive & 6960 ~port_cmd_status & 6961 AHCI_NCQ_SLOT_MASK(ahci_portp); 6962 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 6963 } 6964 6965 timeout_tags = 0; 6966 while (pending_tags) { 6967 tmp_slot = ddi_ffs(pending_tags) - 1; 6968 if (tmp_slot == -1) { 6969 break; 6970 } 6971 6972 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6973 spkt = ahci_portp->ahciport_err_retri_pkt; 6974 else 6975 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6976 6977 if ((spkt != NULL) && spkt->satapkt_time && 6978 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 6979 /* 6980 * We are overloading satapkt_hba_driver_private 6981 * with watched_cycle count. 6982 * 6983 * If a packet has survived for more than it's 6984 * max life cycles, it is a candidate for time 6985 * out. 6986 */ 6987 watched_cycles = (int)(intptr_t) 6988 spkt->satapkt_hba_driver_private; 6989 watched_cycles++; 6990 max_life_cycles = (spkt->satapkt_time + 6991 ahci_watchdog_timeout - 1) / 6992 ahci_watchdog_timeout; 6993 6994 spkt->satapkt_hba_driver_private = 6995 (void *)(intptr_t)watched_cycles; 6996 6997 if (watched_cycles <= max_life_cycles) 6998 goto next; 6999 7000 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 7001 "the current slot is %d", current_slot); 7002 /* 7003 * We need to check whether the HBA has 7004 * begun to execute the command, if not, 7005 * then re-set the timer of the command. 7006 */ 7007 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 7008 (tmp_slot != current_slot) || 7009 NCQ_CMD_IN_PROGRESS(ahci_portp) && 7010 ((0x1 << tmp_slot) & current_tags)) { 7011 spkt->satapkt_hba_driver_private = 7012 (void *)(intptr_t)0; 7013 } else { 7014 timeout_tags |= (0x1 << tmp_slot); 7015 cmn_err(CE_NOTE, "!ahci watchdog: " 7016 "port %d satapkt 0x%p timed out\n", 7017 port, (void *)spkt); 7018 } 7019 } 7020 next: 7021 CLEAR_BIT(pending_tags, tmp_slot); 7022 } 7023 7024 if (timeout_tags) { 7025 mutex_exit(&ahci_portp->ahciport_mutex); 7026 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7027 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 7028 port, timeout_tags); 7029 mutex_enter(&ahci_ctlp->ahcictl_mutex); 7030 mutex_enter(&ahci_portp->ahciport_mutex); 7031 } 7032 7033 mutex_exit(&ahci_portp->ahciport_mutex); 7034 } 7035 7036 /* Re-install the watchdog timeout handler */ 7037 if (ahci_ctlp->ahcictl_timeout_id != 0) { 7038 ahci_ctlp->ahcictl_timeout_id = 7039 timeout((void (*)(void *))ahci_watchdog_handler, 7040 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 7041 } 7042 7043 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7044 } 7045 7046 /* 7047 * Fill the error context into sata_cmd for non-queued command error. 7048 */ 7049 static void 7050 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7051 { 7052 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 7053 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7054 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7055 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7056 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7057 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7058 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7059 7060 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 7061 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7062 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7063 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7064 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7065 } 7066 } 7067 7068 /* 7069 * Fill the ncq error page into sata_cmd for queued command error. 7070 */ 7071 static void 7072 ahci_copy_ncq_err_page(sata_cmd_t *scmd, 7073 struct sata_ncq_error_recovery_page *ncq_err_page) 7074 { 7075 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 7076 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 7077 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 7078 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 7079 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 7080 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 7081 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 7082 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 7083 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 7084 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 7085 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 7086 } 7087 7088 /* 7089 * Put the respective register value to sata_cmd_t for satacmd_flags. 7090 */ 7091 static void 7092 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7093 { 7094 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 7095 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7096 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 7097 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7098 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 7099 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7100 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 7101 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7102 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 7103 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7104 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 7105 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7106 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 7107 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7108 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 7109 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7110 if (scmd->satacmd_flags.sata_copy_out_device_reg) 7111 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7112 if (scmd->satacmd_flags.sata_copy_out_error_reg) 7113 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7114 } 7115 7116 static void 7117 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7118 uint32_t intr_status) 7119 { 7120 #ifndef __lock_lint 7121 _NOTE(ARGUNUSED(ahci_ctlp)) 7122 #endif 7123 7124 if (intr_status & AHCI_INTR_STATUS_IFS) 7125 cmn_err(CE_NOTE, "!ahci port %d has interface fatal " 7126 "error", port); 7127 7128 if (intr_status & AHCI_INTR_STATUS_HBDS) 7129 cmn_err(CE_NOTE, "!ahci port %d has bus data error", port); 7130 7131 if (intr_status & AHCI_INTR_STATUS_HBFS) 7132 cmn_err(CE_NOTE, "!ahci port %d has bus fatal error", port); 7133 7134 if (intr_status & AHCI_INTR_STATUS_TFES) 7135 cmn_err(CE_NOTE, "!ahci port %d has task file error", port); 7136 7137 cmn_err(CE_NOTE, "!ahci port %d is trying to do error " 7138 "recovery", port); 7139 } 7140 7141 /* 7142 * Dump the serror message to the log. 7143 */ 7144 static void 7145 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7146 uint32_t port_serror) 7147 { 7148 #ifndef __lock_lint 7149 _NOTE(ARGUNUSED(ahci_ctlp)) 7150 #endif 7151 char *err_str; 7152 7153 if (port_serror & SERROR_DATA_ERR_FIXED) { 7154 err_str = "Recovered Data Integrity Error (I)"; 7155 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7156 "command error: port: %d, error: %s", 7157 port, err_str); 7158 } 7159 7160 if (port_serror & SERROR_COMM_ERR_FIXED) { 7161 err_str = "Recovered Communication Error (M)"; 7162 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7163 "command error: port: %d, error: %s", 7164 port, err_str); 7165 } 7166 7167 if (port_serror & SERROR_DATA_ERR) { 7168 err_str = "Transient Data Integrity Error (T)"; 7169 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7170 "command error: port: %d, error: %s", 7171 port, err_str); 7172 } 7173 7174 if (port_serror & SERROR_PERSISTENT_ERR) { 7175 err_str = 7176 "Persistent Communication or Data Integrity Error (C)"; 7177 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7178 "command error: port: %d, error: %s", 7179 port, err_str); 7180 } 7181 7182 if (port_serror & SERROR_PROTOCOL_ERR) { 7183 err_str = "Protocol Error (P)"; 7184 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7185 "command error: port: %d, error: %s", 7186 port, err_str); 7187 } 7188 7189 if (port_serror & SERROR_INT_ERR) { 7190 err_str = "Internal Error (E)"; 7191 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7192 "command error: port: %d, error: %s", 7193 port, err_str); 7194 } 7195 7196 if (port_serror & SERROR_PHY_RDY_CHG) { 7197 err_str = "PhyRdy Change (N)"; 7198 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7199 "command error: port: %d, error: %s", 7200 port, err_str); 7201 } 7202 7203 if (port_serror & SERROR_PHY_INT_ERR) { 7204 err_str = "Phy Internal Error (I)"; 7205 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7206 "command error: port: %d, error: %s", 7207 port, err_str); 7208 } 7209 7210 if (port_serror & SERROR_COMM_WAKE) { 7211 err_str = "Comm Wake (W)"; 7212 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7213 "command error: port: %d, error: %s", 7214 port, err_str); 7215 } 7216 7217 if (port_serror & SERROR_10B_TO_8B_ERR) { 7218 err_str = "10B to 8B Decode Error (B)"; 7219 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7220 "command error: port: %d, error: %s", 7221 port, err_str); 7222 } 7223 7224 if (port_serror & SERROR_DISPARITY_ERR) { 7225 err_str = "Disparity Error (D)"; 7226 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7227 "command error: port: %d, error: %s", 7228 port, err_str); 7229 } 7230 7231 if (port_serror & SERROR_CRC_ERR) { 7232 err_str = "CRC Error (C)"; 7233 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7234 "command error: port: %d, error: %s", 7235 port, err_str); 7236 } 7237 7238 if (port_serror & SERROR_HANDSHAKE_ERR) { 7239 err_str = "Handshake Error (H)"; 7240 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7241 "command error: port: %d, error: %s", 7242 port, err_str); 7243 } 7244 7245 if (port_serror & SERROR_LINK_SEQ_ERR) { 7246 err_str = "Link Sequence Error (S)"; 7247 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7248 "command error: port: %d, error: %s", 7249 port, err_str); 7250 } 7251 7252 if (port_serror & SERROR_TRANS_ERR) { 7253 err_str = "Transport state transition error (T)"; 7254 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7255 "command error: port: %d, error: %s", 7256 port, err_str); 7257 } 7258 7259 if (port_serror & SERROR_FIS_TYPE) { 7260 err_str = "Unknown FIS Type (F)"; 7261 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7262 "command error: port: %d, error: %s", 7263 port, err_str); 7264 } 7265 7266 if (port_serror & SERROR_EXCHANGED_ERR) { 7267 err_str = "Exchanged (X)"; 7268 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 7269 "command error: port: %d, error: %s", 7270 port, err_str); 7271 } 7272 } 7273 7274 /* 7275 * This routine is to calculate the total number of ports implemented 7276 * by the HBA. 7277 */ 7278 static int 7279 ahci_get_num_implemented_ports(uint32_t ports_implemented) 7280 { 7281 uint8_t i; 7282 int num = 0; 7283 7284 for (i = 0; i < AHCI_MAX_PORTS; i++) { 7285 if (((uint32_t)0x1 << i) & ports_implemented) 7286 num++; 7287 } 7288 7289 return (num); 7290 } 7291 7292 static void 7293 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7294 { 7295 va_list ap; 7296 7297 mutex_enter(&ahci_log_mutex); 7298 7299 va_start(ap, fmt); 7300 if (ahci_ctlp) { 7301 (void) sprintf(ahci_log_buf, "%s-[%d]:", 7302 ddi_get_name(ahci_ctlp->ahcictl_dip), 7303 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7304 } else { 7305 (void) sprintf(ahci_log_buf, "ahci:"); 7306 } 7307 7308 (void) vsprintf(ahci_log_buf, fmt, ap); 7309 va_end(ap); 7310 7311 cmn_err(level, "%s", ahci_log_buf); 7312 7313 mutex_exit(&ahci_log_mutex); 7314 } 7315