1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 29 * 30 * Power Management Support 31 * ------------------------ 32 * 33 * At the moment, the ahci driver only implements suspend/resume to 34 * support Suspend to RAM on X86 feature. Device power management isn't 35 * implemented, link power management is disabled, and hot plug isn't 36 * allowed during the period from suspend to resume. 37 * 38 * For s/r support, the ahci driver only need to implement DDI_SUSPEND 39 * and DDI_RESUME entries, and don't need to take care of new requests 40 * sent down after suspend because the target driver (sd) has already 41 * handled these conditions, and blocked these requests. For the detailed 42 * information, please check with sdopen, sdclose and sdioctl routines. 43 * 44 */ 45 46 #include <sys/note.h> 47 #include <sys/scsi/scsi.h> 48 #include <sys/pci.h> 49 #include <sys/disp.h> 50 #include <sys/sata/sata_hba.h> 51 #include <sys/sata/adapters/ahci/ahcireg.h> 52 #include <sys/sata/adapters/ahci/ahcivar.h> 53 54 /* 55 * This is the string displayed by modinfo, etc. 56 * Make sure you keep the version ID up to date! 57 */ 58 static char ahci_ident[] = "ahci driver"; 59 60 /* 61 * Function prototypes for driver entry points 62 */ 63 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 64 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 65 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 66 static int ahci_quiesce(dev_info_t *); 67 68 /* 69 * Function prototypes for SATA Framework interfaces 70 */ 71 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 72 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 73 74 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 75 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 76 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 77 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 78 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 79 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 80 #if defined(__lock_lint) 81 static int ahci_selftest(dev_info_t *, sata_device_t *); 82 #endif 83 84 /* 85 * Local function prototypes 86 */ 87 static int ahci_alloc_ports_state(ahci_ctl_t *); 88 static void ahci_dealloc_ports_state(ahci_ctl_t *); 89 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 90 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 91 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 92 static void ahci_dealloc_rcvd_fis(ahci_port_t *); 93 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 94 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 95 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 96 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 97 98 static int ahci_initialize_controller(ahci_ctl_t *); 99 static void ahci_uninitialize_controller(ahci_ctl_t *); 100 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 101 static int ahci_config_space_init(ahci_ctl_t *); 102 103 static void ahci_drain_ports_taskq(ahci_ctl_t *); 104 static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 105 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 106 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 107 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 108 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 109 uint8_t, sata_pkt_t *); 110 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 111 uint8_t, sata_pkt_t *); 112 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 113 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 114 static void ahci_copy_ncq_err_page(sata_cmd_t *, 115 struct sata_ncq_error_recovery_page *); 116 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 117 118 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 119 static int ahci_hba_reset(ahci_ctl_t *); 120 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 121 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 122 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 123 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 124 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 125 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 126 uint8_t); 127 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 128 uint8_t, int, int *); 129 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint32_t, 130 uint32_t, uint32_t, uint32_t, uint32_t); 131 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 132 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 133 uint8_t, sata_pkt_t *); 134 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 135 uint8_t, uint32_t); 136 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 137 uint8_t, uint32_t); 138 static void ahci_events_handler(void *); 139 static void ahci_watchdog_handler(ahci_ctl_t *); 140 141 static uint_t ahci_intr(caddr_t, caddr_t); 142 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 143 static int ahci_add_intrs(ahci_ctl_t *, int); 144 static void ahci_rem_intrs(ahci_ctl_t *); 145 static void ahci_enable_all_intrs(ahci_ctl_t *); 146 static void ahci_disable_all_intrs(ahci_ctl_t *); 147 static void ahci_enable_port_intrs(ahci_ctl_t *, uint8_t); 148 static void ahci_disable_port_intrs(ahci_ctl_t *, uint8_t); 149 150 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t); 151 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 152 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 153 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 154 ahci_port_t *, uint8_t); 155 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 156 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 157 uint8_t, uint32_t); 158 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 159 uint8_t, uint32_t); 160 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 161 162 static int ahci_get_num_implemented_ports(uint32_t); 163 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 164 uint32_t); 165 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int); 166 #if AHCI_DEBUG 167 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 168 #endif 169 170 171 /* 172 * DMA attributes for the data buffer 173 * 174 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 175 * does not support 64-bit addressing 176 */ 177 static ddi_dma_attr_t buffer_dma_attr = { 178 DMA_ATTR_V0, /* dma_attr_version */ 179 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 180 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 181 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 182 0x2ull, /* dma_attr_align: word aligned */ 183 1, /* dma_attr_burstsizes */ 184 1, /* dma_attr_minxfer */ 185 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 186 0xffffffffull, /* dma_attr_seg */ 187 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 188 512, /* dma_attr_granular */ 189 0, /* dma_attr_flags */ 190 }; 191 192 /* 193 * DMA attributes for the rcvd FIS 194 * 195 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 196 * does not support 64-bit addressing 197 */ 198 static ddi_dma_attr_t rcvd_fis_dma_attr = { 199 DMA_ATTR_V0, /* dma_attr_version */ 200 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 201 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 202 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 203 0x100ull, /* dma_attr_align: 256-byte aligned */ 204 1, /* dma_attr_burstsizes */ 205 1, /* dma_attr_minxfer */ 206 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 207 0xffffffffull, /* dma_attr_seg */ 208 1, /* dma_attr_sgllen */ 209 1, /* dma_attr_granular */ 210 0, /* dma_attr_flags */ 211 }; 212 213 /* 214 * DMA attributes for the command list 215 * 216 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 217 * does not support 64-bit addressing 218 */ 219 static ddi_dma_attr_t cmd_list_dma_attr = { 220 DMA_ATTR_V0, /* dma_attr_version */ 221 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 222 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 223 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 224 0x400ull, /* dma_attr_align: 1K-byte aligned */ 225 1, /* dma_attr_burstsizes */ 226 1, /* dma_attr_minxfer */ 227 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 228 0xffffffffull, /* dma_attr_seg */ 229 1, /* dma_attr_sgllen */ 230 1, /* dma_attr_granular */ 231 0, /* dma_attr_flags */ 232 }; 233 234 /* 235 * DMA attributes for cmd tables 236 * 237 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 238 * does not support 64-bit addressing 239 */ 240 static ddi_dma_attr_t cmd_table_dma_attr = { 241 DMA_ATTR_V0, /* dma_attr_version */ 242 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 243 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 244 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 245 0x80ull, /* dma_attr_align: 128-byte aligned */ 246 1, /* dma_attr_burstsizes */ 247 1, /* dma_attr_minxfer */ 248 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 249 0xffffffffull, /* dma_attr_seg */ 250 1, /* dma_attr_sgllen */ 251 1, /* dma_attr_granular */ 252 0, /* dma_attr_flags */ 253 }; 254 255 256 /* Device access attributes */ 257 static ddi_device_acc_attr_t accattr = { 258 DDI_DEVICE_ATTR_V0, 259 DDI_STRUCTURE_LE_ACC, 260 DDI_STRICTORDER_ACC 261 }; 262 263 264 static struct dev_ops ahcictl_dev_ops = { 265 DEVO_REV, /* devo_rev */ 266 0, /* refcnt */ 267 ahci_getinfo, /* info */ 268 nulldev, /* identify */ 269 nulldev, /* probe */ 270 ahci_attach, /* attach */ 271 ahci_detach, /* detach */ 272 nodev, /* no reset */ 273 (struct cb_ops *)0, /* driver operations */ 274 NULL, /* bus operations */ 275 NULL, /* power */ 276 ahci_quiesce, /* quiesce */ 277 }; 278 279 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 280 SATA_TRAN_HOTPLUG_OPS_REV_1, 281 ahci_tran_hotplug_port_activate, 282 ahci_tran_hotplug_port_deactivate 283 }; 284 285 extern struct mod_ops mod_driverops; 286 287 static struct modldrv modldrv = { 288 &mod_driverops, /* driverops */ 289 ahci_ident, /* short description */ 290 &ahcictl_dev_ops, /* driver ops */ 291 }; 292 293 static struct modlinkage modlinkage = { 294 MODREV_1, 295 &modldrv, 296 NULL 297 }; 298 299 /* The following variables are watchdog handler related */ 300 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 301 static int ahci_watchdog_tick; 302 303 /* 304 * This static variable indicates the size of command table, 305 * and it's changeable with prdt number, which ahci_dma_prdt_number 306 * indicates. 307 */ 308 static size_t ahci_cmd_table_size; 309 310 /* 311 * The below global variables are tunable via /etc/system 312 * 313 * ahci_dma_prdt_number 314 * ahci_msi_enabled 315 * ahci_buf_64bit_dma 316 * ahci_commu_64bit_dma 317 */ 318 319 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 320 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 321 322 /* AHCI MSI is tunable */ 323 boolean_t ahci_msi_enabled = B_TRUE; 324 325 /* 326 * 64-bit dma addressing for data buffer is tunable 327 * 328 * The variable controls only the below value: 329 * DBAU (upper 32-bits physical address of data block) 330 */ 331 boolean_t ahci_buf_64bit_dma = B_TRUE; 332 333 /* 334 * 64-bit dma addressing for communication system descriptors is tunable 335 * 336 * The variable controls the below three values: 337 * 338 * PxCLBU (upper 32-bits for the command list base physical address) 339 * PxFBU (upper 32-bits for the received FIS base physical address) 340 * CTBAU (upper 32-bits of command table base) 341 */ 342 boolean_t ahci_commu_64bit_dma = B_TRUE; 343 344 /* 345 * End of global tunable variable definition 346 */ 347 348 #if AHCI_DEBUG 349 uint32_t ahci_debug_flags = 0; 350 351 /* The following is needed for ahci_log() */ 352 static kmutex_t ahci_log_mutex; 353 static char ahci_log_buf[512]; 354 #endif 355 356 /* Opaque state pointer initialized by ddi_soft_state_init() */ 357 static void *ahci_statep = NULL; 358 359 /* 360 * ahci module initialization. 361 */ 362 int 363 _init(void) 364 { 365 int ret; 366 367 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 368 if (ret != 0) { 369 goto err_out; 370 } 371 372 #if AHCI_DEBUG 373 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 374 #endif 375 376 if ((ret = sata_hba_init(&modlinkage)) != 0) { 377 #if AHCI_DEBUG 378 mutex_destroy(&ahci_log_mutex); 379 #endif 380 ddi_soft_state_fini(&ahci_statep); 381 goto err_out; 382 } 383 384 ret = mod_install(&modlinkage); 385 if (ret != 0) { 386 sata_hba_fini(&modlinkage); 387 #if AHCI_DEBUG 388 mutex_destroy(&ahci_log_mutex); 389 #endif 390 ddi_soft_state_fini(&ahci_statep); 391 goto err_out; 392 } 393 394 /* watchdog tick */ 395 ahci_watchdog_tick = drv_usectohz( 396 (clock_t)ahci_watchdog_timeout * 1000000); 397 return (ret); 398 399 err_out: 400 cmn_err(CE_WARN, "!ahci: Module init failed"); 401 return (ret); 402 } 403 404 /* 405 * ahci module uninitialize. 406 */ 407 int 408 _fini(void) 409 { 410 int ret; 411 412 ret = mod_remove(&modlinkage); 413 if (ret != 0) { 414 return (ret); 415 } 416 417 /* Remove the resources allocated in _init(). */ 418 sata_hba_fini(&modlinkage); 419 #if AHCI_DEBUG 420 mutex_destroy(&ahci_log_mutex); 421 #endif 422 ddi_soft_state_fini(&ahci_statep); 423 424 return (ret); 425 } 426 427 /* 428 * _info entry point 429 */ 430 int 431 _info(struct modinfo *modinfop) 432 { 433 return (mod_info(&modlinkage, modinfop)); 434 } 435 436 /* 437 * The attach entry point for dev_ops. 438 */ 439 static int 440 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 441 { 442 ahci_ctl_t *ahci_ctlp; 443 int instance = ddi_get_instance(dip); 444 int status; 445 int attach_state; 446 uint32_t cap_status, ahci_version; 447 int intr_types; 448 int i; 449 pci_regspec_t *regs; 450 int regs_length; 451 int rnumber; 452 #if AHCI_DEBUG 453 int speed; 454 #endif 455 456 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 457 458 switch (cmd) { 459 case DDI_ATTACH: 460 break; 461 462 case DDI_RESUME: 463 464 /* 465 * During DDI_RESUME, the hardware state of the device 466 * (power may have been removed from the device) must be 467 * restored, allow pending requests to continue, and 468 * service new requests. 469 */ 470 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 471 mutex_enter(&ahci_ctlp->ahcictl_mutex); 472 473 /* Restart watch thread */ 474 if (ahci_ctlp->ahcictl_timeout_id == 0) 475 ahci_ctlp->ahcictl_timeout_id = timeout( 476 (void (*)(void *))ahci_watchdog_handler, 477 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 478 479 mutex_exit(&ahci_ctlp->ahcictl_mutex); 480 481 /* 482 * Re-initialize the controller and enable the interrupts and 483 * restart all the ports. 484 * 485 * Note that so far we don't support hot-plug during 486 * suspend/resume. 487 */ 488 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 489 AHCIDBG0(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 490 "Failed to initialize the controller " 491 "during DDI_RESUME"); 492 return (DDI_FAILURE); 493 } 494 495 mutex_enter(&ahci_ctlp->ahcictl_mutex); 496 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 497 mutex_exit(&ahci_ctlp->ahcictl_mutex); 498 499 return (DDI_SUCCESS); 500 501 default: 502 return (DDI_FAILURE); 503 } 504 505 attach_state = AHCI_ATTACH_STATE_NONE; 506 507 /* Allocate soft state */ 508 status = ddi_soft_state_zalloc(ahci_statep, instance); 509 if (status != DDI_SUCCESS) { 510 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state", 511 instance); 512 goto err_out; 513 } 514 515 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 516 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 517 ahci_ctlp->ahcictl_dip = dip; 518 519 /* Initialize the cport/port mapping */ 520 for (i = 0; i < AHCI_MAX_PORTS; i++) { 521 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 522 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 523 } 524 525 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 526 527 /* 528 * Now map the AHCI base address; which includes global 529 * registers and port control registers 530 * 531 * According to the spec, the AHCI Base Address is BAR5, 532 * but BAR0-BAR4 are optional, so we need to check which 533 * rnumber is used for BAR5. 534 */ 535 536 /* 537 * search through DDI "reg" property for the AHCI register set 538 */ 539 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 540 DDI_PROP_DONTPASS, "reg", (int **)®s, 541 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 542 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property", 543 instance); 544 goto err_out; 545 } 546 547 /* AHCI Base Address is located at 0x24 offset */ 548 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 549 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 550 == AHCI_PCI_RNUM) 551 break; 552 } 553 554 ddi_prop_free(regs); 555 556 if (rnumber == regs_length) { 557 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set", 558 instance); 559 goto err_out; 560 } 561 562 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 563 564 status = ddi_regs_map_setup(dip, 565 rnumber, 566 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 567 0, 568 0, 569 &accattr, 570 &ahci_ctlp->ahcictl_ahci_acc_handle); 571 if (status != DDI_SUCCESS) { 572 cmn_err(CE_WARN, "!ahci%d: Cannot map register space", 573 instance); 574 goto err_out; 575 } 576 577 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 578 579 /* Get the AHCI version information */ 580 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 581 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 582 583 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance, 584 (ahci_version & 0xffff0000) >> 16, 585 ((ahci_version & 0x0000ff00) >> 4 | 586 (ahci_version & 0x000000ff))); 587 588 /* We don't support controllers whose versions are lower than 1.0 */ 589 if (!(ahci_version & 0xffff0000)) { 590 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower " 591 "than version 1.0", instance); 592 goto err_out; 593 } 594 595 /* Get the HBA capabilities information */ 596 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 597 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 598 599 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 600 cap_status); 601 602 #if AHCI_DEBUG 603 /* Get the interface speed supported by the HBA */ 604 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 605 if (speed == 0x01) { 606 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 607 "hba interface speed support: Gen 1 (1.5Gbps)"); 608 } else if (speed == 0x10) { 609 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 610 "hba interface speed support: Gen 2 (3 Gbps)"); 611 } else if (speed == 0x11) { 612 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 613 "hba interface speed support: Gen 3 (6 Gbps)"); 614 } 615 #endif 616 617 /* Get the number of command slots supported by the HBA */ 618 ahci_ctlp->ahcictl_num_cmd_slots = 619 ((cap_status & AHCI_HBA_CAP_NCS) >> 620 AHCI_HBA_CAP_NCS_SHIFT) + 1; 621 622 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 623 ahci_ctlp->ahcictl_num_cmd_slots); 624 625 /* Get the bit map which indicates ports implemented by the HBA */ 626 ahci_ctlp->ahcictl_ports_implemented = 627 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 628 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 629 630 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 631 ahci_ctlp->ahcictl_ports_implemented); 632 633 /* 634 * According to the AHCI spec, CAP.NP should indicate the maximum 635 * number of ports supported by the HBA silicon, but we found 636 * this value of ICH8 chipset only indicates the number of ports 637 * implemented (exposed) by it. Therefore, the driver should calculate 638 * the potential maximum value by checking PI register, and use 639 * the maximum of this value and CAP.NP. 640 */ 641 ahci_ctlp->ahcictl_num_ports = max( 642 (cap_status & AHCI_HBA_CAP_NP) + 1, 643 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 644 645 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 646 ahci_ctlp->ahcictl_num_ports); 647 648 /* Get the number of implemented ports by the HBA */ 649 ahci_ctlp->ahcictl_num_implemented_ports = 650 ahci_get_num_implemented_ports( 651 ahci_ctlp->ahcictl_ports_implemented); 652 653 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 654 "hba number of implemented ports: %d", 655 ahci_ctlp->ahcictl_num_implemented_ports); 656 657 /* Check whether HBA supports 64bit DMA addressing */ 658 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 659 ahci_ctlp->ahcictl_cap |= AHCI_CAP_BUF_32BIT_DMA; 660 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA; 661 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 662 "hba does not support 64-bit addressing"); 663 } 664 665 /* Checking for Support Command List Override */ 666 if (cap_status & AHCI_HBA_CAP_SCLO) { 667 ahci_ctlp->ahcictl_cap |= AHCI_CAP_SCLO; 668 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 669 "hba supports command list override."); 670 } 671 672 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 673 != DDI_SUCCESS) { 674 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space", 675 instance); 676 goto err_out; 677 } 678 679 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 680 681 /* 682 * Check the pci configuration space, and set caps. We also 683 * handle the hardware defect in this function. 684 * 685 * For example, force ATI SB600 to use 32-bit dma addressing 686 * since it doesn't support 64-bit dma though its CAP register 687 * declares it support. 688 */ 689 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 690 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed", 691 instance); 692 goto err_out; 693 } 694 695 /* 696 * Disable the whole controller interrupts before adding 697 * interrupt handlers(s). 698 */ 699 ahci_disable_all_intrs(ahci_ctlp); 700 701 /* Get supported interrupt types */ 702 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 703 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed", 704 instance); 705 goto err_out; 706 } 707 708 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 709 "ddi_intr_get_supported_types() returned: 0x%x", 710 intr_types); 711 712 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 713 /* 714 * Try MSI first, but fall back to FIXED if failed 715 */ 716 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_MSI) == 717 DDI_SUCCESS) { 718 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 719 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 720 "Using MSI interrupt type"); 721 goto intr_done; 722 } 723 724 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 725 "MSI registration failed, " 726 "trying FIXED interrupts"); 727 } 728 729 if (intr_types & DDI_INTR_TYPE_FIXED) { 730 if (ahci_add_intrs(ahci_ctlp, DDI_INTR_TYPE_FIXED) == 731 DDI_SUCCESS) { 732 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 733 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 734 "Using FIXED interrupt type"); 735 goto intr_done; 736 } 737 738 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 739 "FIXED interrupt registration failed"); 740 } 741 742 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance); 743 744 goto err_out; 745 746 intr_done: 747 748 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 749 750 /* Initialize the controller mutex */ 751 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 752 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 753 754 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 755 756 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 757 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 758 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 759 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 760 } 761 762 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 763 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 764 sizeof (ahci_prdt_item_t)); 765 766 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 767 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 768 " ahci_cmd_table_size is 0x%x", 769 ahci_dma_prdt_number, ahci_cmd_table_size); 770 771 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 772 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 773 ahci_dma_prdt_number; 774 775 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 776 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 777 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 778 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 779 780 if ((ahci_buf_64bit_dma == B_FALSE) || 781 (ahci_ctlp->ahcictl_cap & AHCI_CAP_BUF_32BIT_DMA)) { 782 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 783 0xffffffffull; 784 } 785 786 if ((ahci_commu_64bit_dma == B_FALSE) || 787 (ahci_ctlp->ahcictl_cap & AHCI_CAP_COMMU_32BIT_DMA)) { 788 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 789 0xffffffffull; 790 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 791 0xffffffffull; 792 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 793 0xffffffffull; 794 } 795 796 /* Allocate the ports structure */ 797 status = ahci_alloc_ports_state(ahci_ctlp); 798 if (status != AHCI_SUCCESS) { 799 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure", 800 instance); 801 goto err_out; 802 } 803 804 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 805 806 /* 807 * Initialize the controller and ports. 808 */ 809 status = ahci_initialize_controller(ahci_ctlp); 810 if (status != AHCI_SUCCESS) { 811 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed", 812 instance); 813 goto err_out; 814 } 815 816 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 817 818 /* Start one thread to check packet timeouts */ 819 ahci_ctlp->ahcictl_timeout_id = timeout( 820 (void (*)(void *))ahci_watchdog_handler, 821 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 822 823 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 824 825 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 826 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed", 827 instance); 828 goto err_out; 829 } 830 831 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 832 833 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 834 835 return (DDI_SUCCESS); 836 837 err_out: 838 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 839 mutex_enter(&ahci_ctlp->ahcictl_mutex); 840 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 841 ahci_ctlp->ahcictl_timeout_id = 0; 842 mutex_exit(&ahci_ctlp->ahcictl_mutex); 843 } 844 845 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 846 ahci_uninitialize_controller(ahci_ctlp); 847 } 848 849 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 850 ahci_dealloc_ports_state(ahci_ctlp); 851 } 852 853 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 854 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 855 } 856 857 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 858 ahci_rem_intrs(ahci_ctlp); 859 } 860 861 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 862 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 863 } 864 865 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 866 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 867 } 868 869 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 870 ddi_soft_state_free(ahci_statep, instance); 871 } 872 873 return (DDI_FAILURE); 874 } 875 876 /* 877 * The detach entry point for dev_ops. 878 */ 879 static int 880 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 881 { 882 ahci_ctl_t *ahci_ctlp; 883 int instance; 884 int ret; 885 886 instance = ddi_get_instance(dip); 887 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 888 889 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 890 891 switch (cmd) { 892 case DDI_DETACH: 893 894 /* disable the interrupts for an uninterrupted detach */ 895 mutex_enter(&ahci_ctlp->ahcictl_mutex); 896 ahci_disable_all_intrs(ahci_ctlp); 897 mutex_exit(&ahci_ctlp->ahcictl_mutex); 898 899 /* unregister from the sata framework. */ 900 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 901 if (ret != AHCI_SUCCESS) { 902 mutex_enter(&ahci_ctlp->ahcictl_mutex); 903 ahci_enable_all_intrs(ahci_ctlp); 904 mutex_exit(&ahci_ctlp->ahcictl_mutex); 905 return (DDI_FAILURE); 906 } 907 908 mutex_enter(&ahci_ctlp->ahcictl_mutex); 909 910 /* stop the watchdog handler */ 911 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 912 ahci_ctlp->ahcictl_timeout_id = 0; 913 914 mutex_exit(&ahci_ctlp->ahcictl_mutex); 915 916 /* uninitialize the controller */ 917 ahci_uninitialize_controller(ahci_ctlp); 918 919 /* remove the interrupts */ 920 ahci_rem_intrs(ahci_ctlp); 921 922 /* deallocate the ports structures */ 923 ahci_dealloc_ports_state(ahci_ctlp); 924 925 /* destroy mutex */ 926 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 927 928 /* teardown the pci config */ 929 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 930 931 /* remove the reg maps. */ 932 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 933 934 /* free the soft state. */ 935 ddi_soft_state_free(ahci_statep, instance); 936 937 return (DDI_SUCCESS); 938 939 case DDI_SUSPEND: 940 941 /* 942 * The steps associated with suspension must include putting 943 * the underlying device into a quiescent state so that it 944 * will not generate interrupts or modify or access memory. 945 */ 946 mutex_enter(&ahci_ctlp->ahcictl_mutex); 947 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 948 mutex_exit(&ahci_ctlp->ahcictl_mutex); 949 return (DDI_SUCCESS); 950 } 951 952 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 953 954 /* stop the watchdog handler */ 955 if (ahci_ctlp->ahcictl_timeout_id) { 956 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 957 ahci_ctlp->ahcictl_timeout_id = 0; 958 } 959 960 mutex_exit(&ahci_ctlp->ahcictl_mutex); 961 962 /* 963 * drain the taskq 964 */ 965 ahci_drain_ports_taskq(ahci_ctlp); 966 967 /* 968 * Disable the interrupts and stop all the ports. 969 */ 970 ahci_uninitialize_controller(ahci_ctlp); 971 972 return (DDI_SUCCESS); 973 974 default: 975 return (DDI_FAILURE); 976 } 977 } 978 979 /* 980 * The info entry point for dev_ops. 981 * 982 */ 983 static int 984 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 985 void *arg, void **result) 986 { 987 #ifndef __lock_lint 988 _NOTE(ARGUNUSED(dip)) 989 #endif /* __lock_lint */ 990 991 ahci_ctl_t *ahci_ctlp; 992 int instance; 993 dev_t dev; 994 995 dev = (dev_t)arg; 996 instance = getminor(dev); 997 998 switch (infocmd) { 999 case DDI_INFO_DEVT2DEVINFO: 1000 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 1001 if (ahci_ctlp != NULL) { 1002 *result = ahci_ctlp->ahcictl_dip; 1003 return (DDI_SUCCESS); 1004 } else { 1005 *result = NULL; 1006 return (DDI_FAILURE); 1007 } 1008 case DDI_INFO_DEVT2INSTANCE: 1009 *(int *)result = instance; 1010 break; 1011 default: 1012 break; 1013 } 1014 1015 return (DDI_SUCCESS); 1016 } 1017 1018 /* 1019 * Registers the ahci with sata framework. 1020 */ 1021 static int 1022 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 1023 { 1024 struct sata_hba_tran *sata_hba_tran; 1025 1026 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 1027 "ahci_register_sata_hba_tran enter"); 1028 1029 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1030 1031 /* Allocate memory for the sata_hba_tran */ 1032 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 1033 1034 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 1035 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 1036 sata_hba_tran->sata_tran_hba_dma_attr = 1037 &ahci_ctlp->ahcictl_buffer_dma_attr; 1038 1039 /* Report the number of implemented ports */ 1040 sata_hba_tran->sata_tran_hba_num_cports = 1041 ahci_ctlp->ahcictl_num_implemented_ports; 1042 1043 /* Support ATAPI device */ 1044 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 1045 1046 /* Get the data transfer capability for PIO command by the HBA */ 1047 if (cap_status & AHCI_HBA_CAP_PMD) { 1048 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 1049 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 1050 "DRQ block data transfer for PIO command protocol"); 1051 } 1052 1053 /* 1054 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 1055 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 1056 * QUEUED (EXT), and SERVICE commands). Queued operations are 1057 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 1058 * QUEUED commands when the HBA and device support native command 1059 * queuing(NCQ). 1060 * 1061 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 1062 * CAP register of the HBA indicates NCQ is supported. 1063 * 1064 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 1065 * set because the previous register content of PxCI can be re-written 1066 * in the register write. 1067 */ 1068 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 1069 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 1070 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 1071 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 1072 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 1073 "Command Queuing"); 1074 } 1075 1076 /* Report the number of command slots */ 1077 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1078 1079 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1080 sata_hba_tran->sata_tran_start = ahci_tran_start; 1081 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1082 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1083 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1084 #ifdef __lock_lint 1085 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1086 #endif 1087 /* 1088 * When SATA framework adds support for pwrmgt the 1089 * pwrmgt_ops needs to be updated 1090 */ 1091 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1092 sata_hba_tran->sata_tran_ioctl = NULL; 1093 1094 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1095 1096 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1097 1098 /* Attach it to SATA framework */ 1099 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1100 != DDI_SUCCESS) { 1101 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1102 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1103 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1104 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1105 return (AHCI_FAILURE); 1106 } 1107 1108 return (AHCI_SUCCESS); 1109 } 1110 1111 /* 1112 * Unregisters the ahci with sata framework. 1113 */ 1114 static int 1115 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1116 { 1117 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1118 "ahci_unregister_sata_hba_tran enter"); 1119 1120 /* Detach from the SATA framework. */ 1121 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1122 DDI_SUCCESS) { 1123 return (AHCI_FAILURE); 1124 } 1125 1126 /* Deallocate sata_hba_tran. */ 1127 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1128 sizeof (sata_hba_tran_t)); 1129 1130 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1131 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1132 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1133 1134 return (AHCI_SUCCESS); 1135 } 1136 1137 /* 1138 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1139 * port status registers and an attached device type via sata_device 1140 * structure. 1141 * 1142 * We return the cached information from a previous hardware probe. The 1143 * actual hardware probing itself was done either from within 1144 * ahci_initialize_controller() during the driver attach or from a phy 1145 * ready change interrupt handler. 1146 */ 1147 static int 1148 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1149 { 1150 ahci_ctl_t *ahci_ctlp; 1151 ahci_port_t *ahci_portp; 1152 uint8_t cport = sd->satadev_addr.cport; 1153 #if AHCI_DEBUG 1154 uint8_t pmport = sd->satadev_addr.pmport; 1155 uint8_t qual = sd->satadev_addr.qual; 1156 #endif 1157 uint8_t device_type; 1158 uint32_t port_state; 1159 uint8_t port; 1160 1161 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1162 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1163 1164 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1165 "ahci_tran_probe_port enter: cport: %d, " 1166 "pmport: %d, qual: %d", cport, pmport, qual); 1167 1168 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1169 1170 mutex_enter(&ahci_portp->ahciport_mutex); 1171 1172 port_state = ahci_portp->ahciport_port_state; 1173 switch (port_state) { 1174 1175 case SATA_PSTATE_FAILED: 1176 sd->satadev_state = SATA_PSTATE_FAILED; 1177 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1178 "ahci_tran_probe_port: port %d PORT FAILED", port); 1179 goto out; 1180 1181 case SATA_PSTATE_SHUTDOWN: 1182 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1183 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1184 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1185 goto out; 1186 1187 case SATA_PSTATE_PWROFF: 1188 sd->satadev_state = SATA_PSTATE_PWROFF; 1189 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1190 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1191 goto out; 1192 1193 case SATA_PSTATE_PWRON: 1194 sd->satadev_state = SATA_PSTATE_PWRON; 1195 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1196 "ahci_tran_probe_port: port %d PORT PWRON", port); 1197 break; 1198 1199 default: 1200 sd->satadev_state = port_state; 1201 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1202 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1203 port, port_state); 1204 break; 1205 } 1206 1207 device_type = ahci_portp->ahciport_device_type; 1208 1209 switch (device_type) { 1210 1211 case SATA_DTYPE_ATADISK: 1212 sd->satadev_type = SATA_DTYPE_ATADISK; 1213 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1214 "ahci_tran_probe_port: port %d DISK found", port); 1215 break; 1216 1217 case SATA_DTYPE_ATAPI: 1218 /* 1219 * HBA driver only knows it's an ATAPI device, and don't know 1220 * it's CD/DVD, tape or ATAPI disk because the ATAPI device 1221 * type need to be determined by checking IDENTIFY PACKET 1222 * DEVICE data 1223 */ 1224 sd->satadev_type = SATA_DTYPE_ATAPI; 1225 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1226 "ahci_tran_probe_port: port %d ATAPI found", port); 1227 break; 1228 1229 case SATA_DTYPE_PMULT: 1230 sd->satadev_type = SATA_DTYPE_PMULT; 1231 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1232 "ahci_tran_probe_port: port %d Port Multiplier found", 1233 port); 1234 break; 1235 1236 case SATA_DTYPE_UNKNOWN: 1237 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1238 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1239 "ahci_tran_probe_port: port %d Unknown device found", port); 1240 break; 1241 1242 default: 1243 /* we don't support any other device types */ 1244 sd->satadev_type = SATA_DTYPE_NONE; 1245 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1246 "ahci_tran_probe_port: port %d No device found", port); 1247 break; 1248 } 1249 1250 out: 1251 ahci_update_sata_registers(ahci_ctlp, port, sd); 1252 mutex_exit(&ahci_portp->ahciport_mutex); 1253 1254 return (SATA_SUCCESS); 1255 } 1256 1257 /* 1258 * There are four operation modes in sata framework: 1259 * SATA_OPMODE_INTERRUPTS 1260 * SATA_OPMODE_POLLING 1261 * SATA_OPMODE_ASYNCH 1262 * SATA_OPMODE_SYNCH 1263 * 1264 * Their combined meanings as following: 1265 * 1266 * SATA_OPMODE_SYNCH 1267 * The command has to be completed before sata_tran_start functions returns. 1268 * Either interrupts or polling could be used - it's up to the driver. 1269 * Mode used currently for internal, sata-module initiated operations. 1270 * 1271 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1272 * It is the same as the one above. 1273 * 1274 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1275 * The command has to be completed before sata_tran_start function returns. 1276 * No interrupt used, polling only. This should be the mode used for scsi 1277 * packets with FLAG_NOINTR. 1278 * 1279 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1280 * The command may be queued (callback function specified). Interrupts could 1281 * be used. It's normal operation mode. 1282 */ 1283 /* 1284 * Called by sata framework to transport a sata packet down stream. 1285 */ 1286 static int 1287 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1288 { 1289 ahci_ctl_t *ahci_ctlp; 1290 ahci_port_t *ahci_portp; 1291 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1292 uint8_t port; 1293 1294 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1295 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1296 1297 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1298 "ahci_tran_start enter: cport %d satapkt 0x%p", 1299 cport, (void *)spkt); 1300 1301 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1302 1303 mutex_enter(&ahci_portp->ahciport_mutex); 1304 1305 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1306 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1307 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1308 /* 1309 * In case the targer driver would send the packet before 1310 * sata framework can have the opportunity to process those 1311 * event reports. 1312 */ 1313 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1314 spkt->satapkt_device.satadev_state = 1315 ahci_portp->ahciport_port_state; 1316 ahci_update_sata_registers(ahci_ctlp, port, 1317 &spkt->satapkt_device); 1318 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1319 "ahci_tran_start returning PORT_ERROR while " 1320 "port in FAILED/SHUTDOWN/PWROFF state: " 1321 "port: %d", port); 1322 mutex_exit(&ahci_portp->ahciport_mutex); 1323 return (SATA_TRAN_PORT_ERROR); 1324 } 1325 1326 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1327 /* 1328 * ahci_intr_phyrdy_change() may have rendered it to 1329 * SATA_DTYPE_NONE. 1330 */ 1331 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1332 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1333 spkt->satapkt_device.satadev_state = 1334 ahci_portp->ahciport_port_state; 1335 ahci_update_sata_registers(ahci_ctlp, port, 1336 &spkt->satapkt_device); 1337 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1338 "ahci_tran_start returning PORT_ERROR while " 1339 "no device attached: port: %d", port); 1340 mutex_exit(&ahci_portp->ahciport_mutex); 1341 return (SATA_TRAN_PORT_ERROR); 1342 } 1343 1344 /* 1345 * SATA HBA driver should remember that a device was reset and it 1346 * is supposed to reject any packets which do not specify either 1347 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1348 * 1349 * This is to prevent a race condition when a device was arbitrarily 1350 * reset by the HBA driver (and lost it's setting) and a target 1351 * driver sending some commands to a device before the sata framework 1352 * has a chance to restore the device setting (such as cache enable/ 1353 * disable or other resettable stuff). 1354 */ 1355 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1356 ahci_portp->ahciport_reset_in_progress = 0; 1357 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1358 "ahci_tran_start clearing the " 1359 "reset_in_progress for port: %d", port); 1360 } 1361 1362 if (ahci_portp->ahciport_reset_in_progress && 1363 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1364 ! ddi_in_panic()) { 1365 spkt->satapkt_reason = SATA_PKT_BUSY; 1366 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1367 "ahci_tran_start returning BUSY while " 1368 "reset in progress: port: %d", port); 1369 mutex_exit(&ahci_portp->ahciport_mutex); 1370 return (SATA_TRAN_BUSY); 1371 } 1372 1373 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1374 spkt->satapkt_reason = SATA_PKT_BUSY; 1375 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1376 "ahci_tran_start returning BUSY while " 1377 "mopping in progress: port: %d", port); 1378 mutex_exit(&ahci_portp->ahciport_mutex); 1379 return (SATA_TRAN_BUSY); 1380 } 1381 1382 if (spkt->satapkt_op_mode & 1383 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1384 /* 1385 * If a SYNC command to be executed in interrupt context, 1386 * bounce it back to sata module. 1387 */ 1388 if (!(spkt->satapkt_op_mode & SATA_OPMODE_POLLING) && 1389 servicing_interrupt()) { 1390 spkt->satapkt_reason = SATA_PKT_BUSY; 1391 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1392 "ahci_tran_start returning BUSY while " 1393 "sending SYNC mode under interrupt context: " 1394 "port : %d", port); 1395 mutex_exit(&ahci_portp->ahciport_mutex); 1396 return (SATA_TRAN_BUSY); 1397 } 1398 1399 /* We need to do the sync start now */ 1400 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1401 spkt) == AHCI_FAILURE) { 1402 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1403 "return QUEUE_FULL: port %d", port); 1404 mutex_exit(&ahci_portp->ahciport_mutex); 1405 return (SATA_TRAN_QUEUE_FULL); 1406 } 1407 } else { 1408 /* Async start, using interrupt */ 1409 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1410 == AHCI_FAILURE) { 1411 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1412 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1413 "returning QUEUE_FULL: port %d", port); 1414 mutex_exit(&ahci_portp->ahciport_mutex); 1415 return (SATA_TRAN_QUEUE_FULL); 1416 } 1417 } 1418 1419 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1420 "sata tran accepted: port %d", port); 1421 1422 mutex_exit(&ahci_portp->ahciport_mutex); 1423 return (SATA_TRAN_ACCEPTED); 1424 } 1425 1426 /* 1427 * SATA_OPMODE_SYNCH flag is set 1428 * 1429 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1430 * without interrupt, otherwise we can still use the interrupt. 1431 * 1432 * WARNING!!! ahciport_mutex should be acquired before the function 1433 * is called. 1434 */ 1435 static int 1436 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1437 uint8_t port, sata_pkt_t *spkt) 1438 { 1439 int pkt_timeout_ticks; 1440 uint32_t timeout_tags; 1441 int rval; 1442 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1443 1444 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1445 "port %d spkt 0x%p", port, spkt); 1446 1447 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1448 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1449 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1450 port, spkt)) == AHCI_FAILURE) { 1451 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1452 return (rval); 1453 } 1454 1455 pkt_timeout_ticks = 1456 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1457 1458 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1459 mutex_exit(&ahci_portp->ahciport_mutex); 1460 1461 /* Simulate the interrupt */ 1462 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1463 1464 drv_usecwait(AHCI_1MS_USECS); 1465 1466 mutex_enter(&ahci_portp->ahciport_mutex); 1467 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1468 if (pkt_timeout_ticks < 0) { 1469 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start " 1470 "port %d satapkt 0x%p timed out\n", 1471 instance, port, (void *)spkt); 1472 timeout_tags = (0x1 << rval); 1473 mutex_exit(&ahci_portp->ahciport_mutex); 1474 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1475 port, timeout_tags); 1476 mutex_enter(&ahci_portp->ahciport_mutex); 1477 } 1478 } 1479 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1480 return (AHCI_SUCCESS); 1481 1482 } else { 1483 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1484 port, spkt)) == AHCI_FAILURE) 1485 return (rval); 1486 1487 #if AHCI_DEBUG 1488 /* 1489 * Note that the driver always uses the slot 0 to deliver 1490 * REQUEST SENSE or READ LOG EXT command 1491 */ 1492 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1493 ASSERT(rval == 0); 1494 #endif 1495 1496 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1497 cv_wait(&ahci_portp->ahciport_cv, 1498 &ahci_portp->ahciport_mutex); 1499 1500 return (AHCI_SUCCESS); 1501 } 1502 } 1503 1504 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1505 if (satapkt) { \ 1506 satapkt->satapkt_reason = reason; \ 1507 /* \ 1508 * We set the satapkt_reason in both sync and \ 1509 * non-sync cases. \ 1510 */ \ 1511 } \ 1512 if (satapkt && \ 1513 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1514 satapkt->satapkt_comp) { \ 1515 mutex_exit(&ahci_portp->ahciport_mutex); \ 1516 (*satapkt->satapkt_comp)(satapkt); \ 1517 mutex_enter(&ahci_portp->ahciport_mutex); \ 1518 } else { \ 1519 if (satapkt && \ 1520 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1521 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1522 cv_broadcast(&ahci_portp->ahciport_cv); \ 1523 } 1524 1525 /* 1526 * Searches for and claims a free command slot. 1527 * 1528 * Returns: 1529 * 1530 * AHCI_FAILURE if failed 1531 * 1. if no empty slot left 1532 * 2. non-queued command requested while queued command(s) is outstanding 1533 * 3. queued command requested whild non-queued command(s) is outstanding 1534 * 4. HBA doesn't support multiple-use of command list while already a 1535 * non-queued command is oustanding 1536 * 1537 * claimed slot number if succeeded 1538 * 1539 * NOTE: it will always return slot 0 during error recovery process for 1540 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1541 * 1542 * WARNING!!! ahciport_mutex should be acquired before the function 1543 * is called. 1544 */ 1545 static int 1546 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1547 ahci_port_t *ahci_portp, int command_type) 1548 { 1549 uint32_t free_slots; 1550 int slot; 1551 1552 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1553 "ahciport_pending_tags = 0x%x " 1554 "ahciport_pending_ncq_tags = 0x%x", 1555 ahci_portp->ahciport_pending_tags, 1556 ahci_portp->ahciport_pending_ncq_tags); 1557 1558 /* 1559 * According to the AHCI spec, system software is responsible to 1560 * ensure that queued and non-queued commands are not mixed in 1561 * the command list. 1562 */ 1563 if (command_type == AHCI_NON_NCQ_CMD) { 1564 /* Non-NCQ command request */ 1565 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1566 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1567 "ahci_claim_free_slot: there is still pending " 1568 "queued command(s) in the command list, " 1569 "so no available slot for the non-queued " 1570 "command"); 1571 return (AHCI_FAILURE); 1572 } 1573 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1574 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1575 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1576 "ahci_claim_free_slot: HBA cannot support multiple-" 1577 "use of the command list for non-queued commands"); 1578 return (AHCI_FAILURE); 1579 } 1580 free_slots = (~ahci_portp->ahciport_pending_tags) & 1581 AHCI_SLOT_MASK(ahci_ctlp); 1582 } else if (command_type == AHCI_NCQ_CMD) { 1583 /* NCQ command request */ 1584 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1585 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1586 "ahci_claim_free_slot: there is still pending " 1587 "non-queued command(s) in the command list, " 1588 "so no available slot for the queued command"); 1589 return (AHCI_FAILURE); 1590 } 1591 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1592 AHCI_NCQ_SLOT_MASK(ahci_portp); 1593 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1594 /* Error retrieval command request */ 1595 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1596 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1597 "SENSE or READ LOG EXT command"); 1598 slot = 0; 1599 goto out; 1600 } 1601 1602 slot = ddi_ffs(free_slots) - 1; 1603 if (slot == -1) { 1604 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1605 "ahci_claim_free_slot: no empty slots"); 1606 return (AHCI_FAILURE); 1607 } 1608 1609 /* 1610 * According to the AHCI spec, to allow a simple mechanism for the 1611 * HBA to map command list slots to queue entries, software must 1612 * match the tag number it uses to the slot it is placing the command 1613 * in. For example, if a queued command is placed in slot 5, the tag 1614 * for that command must be 5. 1615 */ 1616 if (command_type == AHCI_NCQ_CMD) { 1617 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1618 } 1619 1620 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1621 1622 out: 1623 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1624 "ahci_claim_free_slot: found slot: 0x%x", slot); 1625 1626 return (slot); 1627 } 1628 1629 /* 1630 * Builds the Command Table for the sata packet and delivers it to controller. 1631 * 1632 * Returns: 1633 * slot number if we can obtain a slot successfully 1634 * otherwise, return AHCI_FAILURE 1635 * 1636 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1637 */ 1638 static int 1639 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1640 uint8_t port, sata_pkt_t *spkt) 1641 { 1642 int cmd_slot; 1643 sata_cmd_t *scmd; 1644 ahci_fis_h2d_register_t *h2d_register_fisp; 1645 ahci_cmd_table_t *cmd_table; 1646 ahci_cmd_header_t *cmd_header; 1647 int ncookies; 1648 int i; 1649 int command_type = AHCI_NON_NCQ_CMD; 1650 int ncq_qdepth; 1651 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1652 #if AHCI_DEBUG 1653 uint32_t *ptr; 1654 uint8_t *ptr2; 1655 #endif 1656 1657 spkt->satapkt_reason = SATA_PKT_BUSY; 1658 1659 scmd = &spkt->satapkt_cmd; 1660 1661 /* Check if the command is a NCQ command */ 1662 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1663 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1664 command_type = AHCI_NCQ_CMD; 1665 1666 /* 1667 * When NCQ is support, system software must determine the 1668 * maximum tag allowed by the device and the HBA, and it 1669 * must use a value not beyond of the lower bound of the two. 1670 * 1671 * Sata module is going to calculate the qdepth and send 1672 * down to HBA driver via sata_cmd. 1673 */ 1674 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1675 1676 /* 1677 * At the moment, the driver doesn't support the dynamic 1678 * setting of the maximum ncq depth, and the value can be 1679 * set either during the attach or after hot-plug insertion. 1680 */ 1681 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1682 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1683 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1684 "ahci_deliver_satapkt: port %d the max tags for " 1685 "NCQ command is %d", port, ncq_qdepth); 1686 } else { 1687 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1688 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt" 1689 " port %d the max tag for NCQ command is " 1690 "requested to change from %d to %d, at the" 1691 " moment the driver doesn't support the " 1692 "dynamic change so it's going to " 1693 "still use the previous tag value", 1694 instance, port, 1695 ahci_portp->ahciport_max_ncq_tags, 1696 ncq_qdepth); 1697 } 1698 } 1699 } 1700 1701 /* Check if the command is an error retrieval command */ 1702 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1703 command_type = AHCI_ERR_RETRI_CMD; 1704 1705 /* Check if there is an empty command slot */ 1706 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1707 if (cmd_slot == AHCI_FAILURE) { 1708 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1709 return (AHCI_FAILURE); 1710 } 1711 1712 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1713 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1714 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1715 cmd_slot, port, (void *)spkt); 1716 1717 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1718 bzero((void *)cmd_table, ahci_cmd_table_size); 1719 1720 /* For data transfer operations, it is the H2D Register FIS */ 1721 h2d_register_fisp = 1722 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1723 1724 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1725 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1726 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1727 SET_FIS_PMP(h2d_register_fisp, 1728 spkt->satapkt_device.satadev_addr.pmport); 1729 } 1730 1731 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1732 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1733 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1734 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1735 1736 switch (scmd->satacmd_addr_type) { 1737 1738 case 0: 1739 /* 1740 * satacmd_addr_type will be 0 for the commands below: 1741 * ATAPI command 1742 * SATAC_IDLE_IM 1743 * SATAC_STANDBY_IM 1744 * SATAC_DOWNLOAD_MICROCODE 1745 * SATAC_FLUSH_CACHE 1746 * SATAC_SET_FEATURES 1747 * SATAC_SMART 1748 * SATAC_ID_PACKET_DEVICE 1749 * SATAC_ID_DEVICE 1750 */ 1751 /* FALLTHRU */ 1752 1753 case ATA_ADDR_LBA: 1754 /* FALLTHRU */ 1755 1756 case ATA_ADDR_LBA28: 1757 /* LBA[7:0] */ 1758 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1759 1760 /* LBA[15:8] */ 1761 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1762 1763 /* LBA[23:16] */ 1764 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1765 1766 /* LBA [27:24] (also called dev_head) */ 1767 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1768 1769 break; 1770 1771 case ATA_ADDR_LBA48: 1772 /* LBA[7:0] */ 1773 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1774 1775 /* LBA[15:8] */ 1776 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1777 1778 /* LBA[23:16] */ 1779 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1780 1781 /* LBA [31:24] */ 1782 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1783 scmd->satacmd_lba_low_msb); 1784 1785 /* LBA [39:32] */ 1786 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1787 scmd->satacmd_lba_mid_msb); 1788 1789 /* LBA [47:40] */ 1790 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1791 scmd->satacmd_lba_high_msb); 1792 1793 /* Set dev_head */ 1794 SET_FIS_DEV_HEAD(h2d_register_fisp, 1795 scmd->satacmd_device_reg); 1796 1797 /* Set the extended sector count and features */ 1798 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1799 scmd->satacmd_sec_count_msb); 1800 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1801 scmd->satacmd_features_reg_ext); 1802 break; 1803 } 1804 1805 /* 1806 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1807 * filled into features field, and sector count 8:15 is filled into 1808 * features (exp) field. TAG is filled into sector field. 1809 */ 1810 if (command_type == AHCI_NCQ_CMD) { 1811 SET_FIS_FEATURES(h2d_register_fisp, 1812 scmd->satacmd_sec_count_lsb); 1813 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1814 scmd->satacmd_sec_count_msb); 1815 1816 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1817 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1818 } 1819 1820 ncookies = scmd->satacmd_num_dma_cookies; 1821 AHCIDBG2(AHCIDBG_PRDT, ahci_ctlp, 1822 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1823 ncookies, ahci_dma_prdt_number); 1824 1825 ASSERT(ncookies <= ahci_dma_prdt_number); 1826 ahci_portp->ahciport_prd_bytecounts[cmd_slot] = 0; 1827 1828 /* *** now fill the scatter gather list ******* */ 1829 for (i = 0; i < ncookies; i++) { 1830 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1831 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1832 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1833 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1834 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1835 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1836 ahci_portp->ahciport_prd_bytecounts[cmd_slot] += 1837 scmd->satacmd_dma_cookie_list[i].dmac_size; 1838 } 1839 1840 AHCIDBG2(AHCIDBG_PRDT, ahci_ctlp, 1841 "ahciport_prd_bytecounts 0x%x for cmd_slot 0x%x", 1842 ahci_portp->ahciport_prd_bytecounts[cmd_slot], cmd_slot); 1843 1844 /* The ACMD field is filled in for ATAPI command */ 1845 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1846 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1847 SATA_ATAPI_MAX_CDB_LEN); 1848 } 1849 1850 /* Set Command Header in Command List */ 1851 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1852 BZERO_DESCR_INFO(cmd_header); 1853 BZERO_PRD_BYTE_COUNT(cmd_header); 1854 1855 /* Set the number of entries in the PRD table */ 1856 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1857 1858 /* Set the length of the command in the CFIS area */ 1859 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1860 1861 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1862 "sata_data_direction = 0x%x", 1863 scmd->satacmd_flags.sata_data_direction); 1864 1865 /* Set A bit if it is an ATAPI command */ 1866 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1867 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1868 1869 /* Set W bit if data is going to the device */ 1870 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1871 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1872 1873 /* 1874 * Set the prefetchable bit - this bit is only valid if the PRDTL 1875 * field is non-zero or the ATAPI 'A' bit is set in the command 1876 * header. This bit cannot be set when using native command 1877 * queuing commands or when using FIS-based switching with a Port 1878 * multiplier. 1879 */ 1880 if (command_type != AHCI_NCQ_CMD) 1881 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1882 1883 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1884 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1885 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1886 1887 /* 1888 * We are overloading satapkt_hba_driver_private with 1889 * watched_cycle count. 1890 */ 1891 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1892 1893 #if AHCI_DEBUG 1894 if (ahci_debug_flags & AHCIDBG_ATACMD && 1895 scmd->satacmd_cmd_reg != SATAC_PACKET || 1896 ahci_debug_flags & AHCIDBG_ATAPICMD && 1897 scmd->satacmd_cmd_reg == SATAC_PACKET) { 1898 1899 /* Dump the command header and table */ 1900 ahci_log(ahci_ctlp, CE_WARN, "\n"); 1901 ahci_log(ahci_ctlp, CE_WARN, "Command header&table for spkt " 1902 "0x%p cmd_reg 0x%x port %d", spkt, 1903 scmd->satacmd_cmd_reg, port); 1904 ptr = (uint32_t *)cmd_header; 1905 ahci_log(ahci_ctlp, CE_WARN, 1906 " Command Header:%8x %8x %8x %8x", 1907 ptr[0], ptr[1], ptr[2], ptr[3]); 1908 1909 /* Dump the H2D register FIS */ 1910 ptr = (uint32_t *)h2d_register_fisp; 1911 ahci_log(ahci_ctlp, CE_WARN, 1912 " Command FIS: %8x %8x %8x %8x", 1913 ptr[0], ptr[1], ptr[2], ptr[3]); 1914 1915 /* Dump the ACMD register FIS */ 1916 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1917 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1918 if (ahci_debug_flags & AHCIDBG_ATAPICMD) 1919 ahci_log(ahci_ctlp, CE_WARN, 1920 " ATAPI command: %2x %2x %2x %2x " 1921 "%2x %2x %2x %2x", 1922 ptr2[8 * i], ptr2[8 * i + 1], 1923 ptr2[8 * i + 2], ptr2[8 * i + 3], 1924 ptr2[8 * i + 4], ptr2[8 * i + 5], 1925 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1926 1927 /* Dump the PRDT */ 1928 for (i = 0; i < ncookies; i++) { 1929 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1930 ahci_log(ahci_ctlp, CE_WARN, 1931 " Cookie %d: %8x %8x %8x %8x", 1932 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1933 } 1934 } 1935 #endif 1936 1937 (void) ddi_dma_sync( 1938 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1939 0, 1940 ahci_cmd_table_size, 1941 DDI_DMA_SYNC_FORDEV); 1942 1943 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1944 cmd_slot * sizeof (ahci_cmd_header_t), 1945 sizeof (ahci_cmd_header_t), 1946 DDI_DMA_SYNC_FORDEV); 1947 1948 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1949 if (command_type == AHCI_NCQ_CMD) { 1950 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1951 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1952 (0x1 << cmd_slot)); 1953 } 1954 1955 /* Indicate to the HBA that a command is active. */ 1956 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1957 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1958 (0x1 << cmd_slot)); 1959 1960 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1961 "exit: port %d", port); 1962 1963 return (cmd_slot); 1964 } 1965 1966 /* 1967 * Called by the sata framework to abort the previously sent packet(s). 1968 * 1969 * Reset device to abort commands. 1970 */ 1971 static int 1972 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1973 { 1974 ahci_ctl_t *ahci_ctlp; 1975 ahci_port_t *ahci_portp; 1976 uint32_t slot_status = 0; 1977 uint32_t aborted_tags = 0; 1978 uint32_t finished_tags = 0; 1979 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1980 uint8_t port; 1981 int tmp_slot; 1982 int instance = ddi_get_instance(dip); 1983 1984 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 1985 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1986 1987 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1988 "ahci_tran_abort enter: port %d", port); 1989 1990 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1991 mutex_enter(&ahci_portp->ahciport_mutex); 1992 1993 /* 1994 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1995 * commands are being mopped, therefore there is nothing else to do 1996 */ 1997 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1998 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1999 "ahci_tran_abort: port %d is in " 2000 "mopping process, so just return directly ", port); 2001 mutex_exit(&ahci_portp->ahciport_mutex); 2002 return (SATA_SUCCESS); 2003 } 2004 2005 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2006 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2007 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2008 /* 2009 * In case the targer driver would send the request before 2010 * sata framework can have the opportunity to process those 2011 * event reports. 2012 */ 2013 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2014 spkt->satapkt_device.satadev_state = 2015 ahci_portp->ahciport_port_state; 2016 ahci_update_sata_registers(ahci_ctlp, port, 2017 &spkt->satapkt_device); 2018 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2019 "ahci_tran_abort returning SATA_FAILURE while " 2020 "port in FAILED/SHUTDOWN/PWROFF state: " 2021 "port: %d", port); 2022 mutex_exit(&ahci_portp->ahciport_mutex); 2023 return (SATA_FAILURE); 2024 } 2025 2026 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2027 /* 2028 * ahci_intr_phyrdy_change() may have rendered it to 2029 * AHCI_PORT_TYPE_NODEV. 2030 */ 2031 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2032 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 2033 spkt->satapkt_device.satadev_state = 2034 ahci_portp->ahciport_port_state; 2035 ahci_update_sata_registers(ahci_ctlp, port, 2036 &spkt->satapkt_device); 2037 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2038 "ahci_tran_abort returning SATA_FAILURE while " 2039 "no device attached: port: %d", port); 2040 mutex_exit(&ahci_portp->ahciport_mutex); 2041 return (SATA_FAILURE); 2042 } 2043 2044 if (flag == SATA_ABORT_ALL_PACKETS) { 2045 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2046 aborted_tags = ahci_portp->ahciport_pending_tags; 2047 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2048 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 2049 2050 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets", 2051 instance, port); 2052 } else { 2053 aborted_tags = 0xffffffff; 2054 /* 2055 * Aborting one specific packet, first search the 2056 * ahciport_slot_pkts[] list for matching spkt. 2057 */ 2058 for (tmp_slot = 0; 2059 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 2060 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 2061 aborted_tags = (0x1 << tmp_slot); 2062 break; 2063 } 2064 } 2065 2066 if (aborted_tags == 0xffffffff) { 2067 /* request packet is not on the pending list */ 2068 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2069 "Cannot find the aborting pkt 0x%p on the " 2070 "pending list", (void *)spkt); 2071 ahci_update_sata_registers(ahci_ctlp, port, 2072 &spkt->satapkt_device); 2073 mutex_exit(&ahci_portp->ahciport_mutex); 2074 return (SATA_FAILURE); 2075 } 2076 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p", 2077 instance, port, (void *)spkt); 2078 } 2079 2080 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2081 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2082 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2083 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2084 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2085 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2086 2087 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2088 ahci_portp->ahciport_mop_in_progress++; 2089 2090 /* 2091 * To abort the packet(s), first we are trying to clear PxCMD.ST 2092 * to stop the port, and if the port can be stopped 2093 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 2094 * then we just send back the aborted packet(s) with ABORTED flag 2095 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 2096 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 2097 * perform a COMRESET. 2098 */ 2099 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2100 ahci_portp, port, NULL, NULL); 2101 2102 /* 2103 * Compute which have finished and which need to be retried. 2104 * 2105 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 2106 * minus the slot_status. The aborted_tags has to be deducted by 2107 * finished_tags since we can't possibly abort a tag which had finished 2108 * already. 2109 */ 2110 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2111 finished_tags = ahci_portp->ahciport_pending_tags & 2112 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2113 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2114 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2115 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2116 2117 aborted_tags &= ~finished_tags; 2118 2119 ahci_mop_commands(ahci_ctlp, 2120 ahci_portp, 2121 slot_status, 2122 0, /* failed tags */ 2123 0, /* timeout tags */ 2124 aborted_tags, 2125 0); /* reset tags */ 2126 2127 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2128 mutex_exit(&ahci_portp->ahciport_mutex); 2129 2130 return (SATA_SUCCESS); 2131 } 2132 2133 /* 2134 * Used to do device reset and reject all the pending packets on a device 2135 * during the reset operation. 2136 * 2137 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2138 */ 2139 static int 2140 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2141 ahci_port_t *ahci_portp, uint8_t port) 2142 { 2143 uint32_t slot_status = 0; 2144 uint32_t reset_tags = 0; 2145 uint32_t finished_tags = 0; 2146 sata_device_t sdevice; 2147 int ret; 2148 2149 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2150 "ahci_reset_device_reject_pkts on port: %d", port); 2151 2152 /* 2153 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2154 * commands are being mopped, therefore there is nothing else to do 2155 */ 2156 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2157 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2158 "ahci_reset_device_reject_pkts: port %d is in " 2159 "mopping process, so return directly ", port); 2160 return (SATA_SUCCESS); 2161 } 2162 2163 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2164 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2165 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2166 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2167 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2168 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2169 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2170 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2171 } 2172 2173 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2174 != AHCI_SUCCESS) { 2175 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2176 "Try to do a port reset after software " 2177 "reset failed", port); 2178 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2179 if (ret != AHCI_SUCCESS) { 2180 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2181 "ahci_reset_device_reject_pkts: port %d " 2182 "failed", port); 2183 return (SATA_FAILURE); 2184 } 2185 } 2186 /* Set the reset in progress flag */ 2187 ahci_portp->ahciport_reset_in_progress = 1; 2188 2189 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2190 ahci_portp->ahciport_mop_in_progress++; 2191 2192 /* Indicate to the framework that a reset has happened */ 2193 bzero((void *)&sdevice, sizeof (sata_device_t)); 2194 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2195 sdevice.satadev_addr.pmport = 0; 2196 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2197 2198 sdevice.satadev_state = SATA_DSTATE_RESET | 2199 SATA_DSTATE_PWR_ACTIVE; 2200 mutex_exit(&ahci_portp->ahciport_mutex); 2201 sata_hba_event_notify( 2202 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2203 &sdevice, 2204 SATA_EVNT_DEVICE_RESET); 2205 mutex_enter(&ahci_portp->ahciport_mutex); 2206 2207 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2208 "port %d sending event up: SATA_EVNT_RESET", port); 2209 2210 /* Next try to mop the pending commands */ 2211 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2212 finished_tags = ahci_portp->ahciport_pending_tags & 2213 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2214 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2215 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2216 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2217 2218 reset_tags &= ~finished_tags; 2219 2220 ahci_mop_commands(ahci_ctlp, 2221 ahci_portp, 2222 slot_status, 2223 0, /* failed tags */ 2224 0, /* timeout tags */ 2225 0, /* aborted tags */ 2226 reset_tags); /* reset tags */ 2227 2228 return (SATA_SUCCESS); 2229 } 2230 2231 /* 2232 * Used to do port reset and reject all the pending packets on a port during 2233 * the reset operation. 2234 * 2235 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2236 */ 2237 static int 2238 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2239 ahci_port_t *ahci_portp, uint8_t port) 2240 { 2241 uint32_t slot_status = 0; 2242 uint32_t reset_tags = 0; 2243 uint32_t finished_tags = 0; 2244 2245 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2246 "ahci_reset_port_reject_pkts on port: %d", port); 2247 2248 /* 2249 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2250 * commands are being mopped, therefore there is nothing else to do 2251 */ 2252 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2253 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2254 "ahci_reset_port_reject_pkts: port %d is in " 2255 "mopping process, so return directly ", port); 2256 return (SATA_SUCCESS); 2257 } 2258 2259 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2260 ahci_portp->ahciport_mop_in_progress++; 2261 2262 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2263 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2264 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2265 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2266 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2267 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2268 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2269 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2270 } 2271 2272 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2273 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2274 NULL) != AHCI_SUCCESS) 2275 return (SATA_FAILURE); 2276 2277 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2278 finished_tags = ahci_portp->ahciport_pending_tags & 2279 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2280 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2281 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2282 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2283 2284 reset_tags &= ~finished_tags; 2285 2286 ahci_mop_commands(ahci_ctlp, 2287 ahci_portp, 2288 slot_status, 2289 0, /* failed tags */ 2290 0, /* timeout tags */ 2291 0, /* aborted tags */ 2292 reset_tags); /* reset tags */ 2293 2294 return (SATA_SUCCESS); 2295 } 2296 2297 /* 2298 * Used to do hba reset and reject all the pending packets on all ports 2299 * during the reset operation. 2300 */ 2301 static int 2302 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2303 { 2304 ahci_port_t *ahci_portp; 2305 uint32_t slot_status[AHCI_MAX_PORTS]; 2306 uint32_t reset_tags[AHCI_MAX_PORTS]; 2307 uint32_t finished_tags[AHCI_MAX_PORTS]; 2308 uint8_t port; 2309 int ret = SATA_SUCCESS; 2310 2311 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2312 "ahci_reset_hba_reject_pkts enter"); 2313 2314 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2315 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2316 continue; 2317 } 2318 2319 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2320 2321 mutex_enter(&ahci_portp->ahciport_mutex); 2322 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2323 slot_status[port] = ddi_get32( 2324 ahci_ctlp->ahcictl_ahci_acc_handle, 2325 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2326 reset_tags[port] = slot_status[port] & 2327 AHCI_SLOT_MASK(ahci_ctlp); 2328 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2329 slot_status[port] = ddi_get32( 2330 ahci_ctlp->ahcictl_ahci_acc_handle, 2331 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2332 reset_tags[port] = slot_status[port] & 2333 AHCI_NCQ_SLOT_MASK(ahci_portp); 2334 } 2335 mutex_exit(&ahci_portp->ahciport_mutex); 2336 } 2337 2338 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2339 ret = SATA_FAILURE; 2340 goto out; 2341 } 2342 2343 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2344 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2345 continue; 2346 } 2347 2348 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2349 2350 mutex_enter(&ahci_portp->ahciport_mutex); 2351 /* 2352 * To prevent recursive enter to ahci_mop_commands, we need 2353 * check AHCI_PORT_FLAG_MOPPING flag. 2354 */ 2355 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2356 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2357 "ahci_reset_hba_reject_pkts: port %d is in " 2358 "mopping process, so return directly ", port); 2359 mutex_exit(&ahci_portp->ahciport_mutex); 2360 continue; 2361 } 2362 2363 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2364 ahci_portp->ahciport_mop_in_progress++; 2365 2366 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2367 finished_tags[port] = 2368 ahci_portp->ahciport_pending_tags & 2369 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2370 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2371 finished_tags[port] = 2372 ahci_portp->ahciport_pending_ncq_tags & 2373 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2374 2375 reset_tags[port] &= ~finished_tags[port]; 2376 2377 ahci_mop_commands(ahci_ctlp, 2378 ahci_portp, 2379 slot_status[port], 2380 0, /* failed tags */ 2381 0, /* timeout tags */ 2382 0, /* aborted tags */ 2383 reset_tags[port]); /* reset tags */ 2384 mutex_exit(&ahci_portp->ahciport_mutex); 2385 } 2386 out: 2387 return (ret); 2388 } 2389 2390 /* 2391 * Called by sata framework to reset a port(s) or device. 2392 */ 2393 static int 2394 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2395 { 2396 ahci_ctl_t *ahci_ctlp; 2397 ahci_port_t *ahci_portp; 2398 uint8_t cport = sd->satadev_addr.cport; 2399 uint8_t port; 2400 int ret = SATA_SUCCESS; 2401 int instance = ddi_get_instance(dip); 2402 2403 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2404 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2405 2406 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2407 "ahci_tran_reset_port enter: cport: %d", cport); 2408 2409 switch (sd->satadev_addr.qual) { 2410 case SATA_ADDR_CPORT: 2411 /* Port reset */ 2412 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2413 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2414 "reset port", instance, port); 2415 2416 mutex_enter(&ahci_portp->ahciport_mutex); 2417 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2418 mutex_exit(&ahci_portp->ahciport_mutex); 2419 2420 break; 2421 2422 case SATA_ADDR_DCPORT: 2423 /* Device reset */ 2424 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2425 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2426 "reset device", instance, port); 2427 2428 mutex_enter(&ahci_portp->ahciport_mutex); 2429 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2430 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2431 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2432 /* 2433 * In case the targer driver would send the request 2434 * before sata framework can have the opportunity to 2435 * process those event reports. 2436 */ 2437 sd->satadev_state = ahci_portp->ahciport_port_state; 2438 ahci_update_sata_registers(ahci_ctlp, port, sd); 2439 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2440 "ahci_tran_reset_dport returning SATA_FAILURE " 2441 "while port in FAILED/SHUTDOWN/PWROFF state: " 2442 "port: %d", port); 2443 mutex_exit(&ahci_portp->ahciport_mutex); 2444 ret = SATA_FAILURE; 2445 break; 2446 } 2447 2448 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2449 /* 2450 * ahci_intr_phyrdy_change() may have rendered it to 2451 * AHCI_PORT_TYPE_NODEV. 2452 */ 2453 sd->satadev_type = SATA_DTYPE_NONE; 2454 sd->satadev_state = ahci_portp->ahciport_port_state; 2455 ahci_update_sata_registers(ahci_ctlp, port, sd); 2456 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2457 "ahci_tran_reset_dport returning SATA_FAILURE " 2458 "while no device attached: port: %d", port); 2459 mutex_exit(&ahci_portp->ahciport_mutex); 2460 ret = SATA_FAILURE; 2461 break; 2462 } 2463 2464 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2465 ahci_portp, port); 2466 mutex_exit(&ahci_portp->ahciport_mutex); 2467 break; 2468 2469 case SATA_ADDR_CNTRL: 2470 /* Reset the whole controller */ 2471 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2472 "reset the whole hba", instance, port); 2473 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2474 break; 2475 2476 case SATA_ADDR_PMPORT: 2477 case SATA_ADDR_DPMPORT: 2478 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2479 "ahci_tran_reset_dport: port multiplier will be " 2480 "supported later"); 2481 /* FALLTHRU */ 2482 default: 2483 ret = SATA_FAILURE; 2484 } 2485 2486 return (ret); 2487 } 2488 2489 /* 2490 * Called by sata framework to activate a port as part of hotplug. 2491 * (cfgadm -c connect satax/y) 2492 * Note: Not port-mult aware. 2493 */ 2494 static int 2495 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2496 { 2497 ahci_ctl_t *ahci_ctlp; 2498 ahci_port_t *ahci_portp; 2499 uint8_t cport = satadev->satadev_addr.cport; 2500 uint8_t port; 2501 int instance = ddi_get_instance(dip); 2502 2503 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2504 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2505 2506 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2507 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2508 2509 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2510 2511 mutex_enter(&ahci_portp->ahciport_mutex); 2512 ahci_enable_port_intrs(ahci_ctlp, port); 2513 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated", instance, port); 2514 2515 /* 2516 * Reset the port so that the PHY communication would be re-established. 2517 * But this reset is an internal operation and the sata module doesn't 2518 * need to know about it. Moreover, the port with a device attached will 2519 * be started too. 2520 */ 2521 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2522 ahci_portp, port, 2523 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2524 NULL); 2525 2526 /* 2527 * Need to check the link status and device status of the port 2528 * and consider raising power if the port was in D3 state 2529 */ 2530 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2531 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2532 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2533 2534 satadev->satadev_state = ahci_portp->ahciport_port_state; 2535 2536 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2537 2538 mutex_exit(&ahci_portp->ahciport_mutex); 2539 return (SATA_SUCCESS); 2540 } 2541 2542 /* 2543 * Called by sata framework to deactivate a port as part of hotplug. 2544 * (cfgadm -c disconnect satax/y) 2545 * Note: Not port-mult aware. 2546 */ 2547 static int 2548 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2549 { 2550 ahci_ctl_t *ahci_ctlp; 2551 ahci_port_t *ahci_portp; 2552 uint8_t cport = satadev->satadev_addr.cport; 2553 uint8_t port; 2554 uint32_t port_scontrol; 2555 int instance = ddi_get_instance(dip); 2556 2557 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2558 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2559 2560 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2561 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2562 2563 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2564 2565 mutex_enter(&ahci_portp->ahciport_mutex); 2566 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated", 2567 instance, port); 2568 2569 /* Disable the interrupts on the port */ 2570 ahci_disable_port_intrs(ahci_ctlp, port); 2571 2572 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2573 goto phy_offline; 2574 } 2575 2576 /* First to abort all the pending commands */ 2577 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2578 2579 /* Then stop the port */ 2580 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2581 ahci_portp, port); 2582 2583 /* Next put the PHY offline */ 2584 2585 phy_offline: 2586 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2587 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2588 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2589 2590 /* Update ahciport_port_state */ 2591 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2592 satadev->satadev_state = ahci_portp->ahciport_port_state; 2593 2594 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2595 2596 mutex_exit(&ahci_portp->ahciport_mutex); 2597 return (SATA_SUCCESS); 2598 } 2599 2600 /* 2601 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2602 * when a device is unplugged or a port is deactivated. 2603 * 2604 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2605 */ 2606 static void 2607 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2608 ahci_port_t *ahci_portp, uint8_t port) 2609 { 2610 uint32_t slot_status = 0; 2611 uint32_t abort_tags = 0; 2612 2613 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2614 "ahci_reject_all_abort_pkts on port: %d", port); 2615 2616 /* 2617 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2618 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2619 * to get the error data, if yes when the device is removed, the 2620 * command needs to be aborted too. 2621 */ 2622 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2623 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2624 slot_status = 0x1; 2625 abort_tags = 0x1; 2626 goto out; 2627 } else { 2628 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2629 "ahci_reject_all_abort_pkts return directly " 2630 "port %d no needs to reject any outstanding " 2631 "commands", port); 2632 return; 2633 } 2634 } 2635 2636 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2637 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2638 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2639 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2640 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2641 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2642 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2643 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2644 } 2645 2646 out: 2647 /* No need to do mop when there is no outstanding commands */ 2648 if (slot_status != 0) { 2649 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2650 ahci_portp->ahciport_mop_in_progress++; 2651 2652 ahci_mop_commands(ahci_ctlp, 2653 ahci_portp, 2654 slot_status, 2655 0, /* failed tags */ 2656 0, /* timeout tags */ 2657 abort_tags, /* aborting tags */ 2658 0); /* reset tags */ 2659 } 2660 } 2661 2662 #if defined(__lock_lint) 2663 static int 2664 ahci_selftest(dev_info_t *dip, sata_device_t *device) 2665 { 2666 return (SATA_SUCCESS); 2667 } 2668 #endif 2669 2670 /* 2671 * Allocate the ports structure, only called by ahci_attach 2672 */ 2673 static int 2674 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2675 { 2676 int port, cport = 0; 2677 2678 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2679 "ahci_alloc_ports_state enter"); 2680 2681 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2682 2683 /* Allocate structures only for the implemented ports */ 2684 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2685 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2686 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2687 "hba port %d not implemented", port); 2688 continue; 2689 } 2690 2691 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2692 ahci_ctlp->ahcictl_port_to_cport[port] = 2693 (uint8_t)cport++; 2694 2695 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2696 goto err_out; 2697 } 2698 } 2699 2700 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2701 return (AHCI_SUCCESS); 2702 2703 err_out: 2704 for (port--; port >= 0; port--) { 2705 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2706 ahci_dealloc_port_state(ahci_ctlp, port); 2707 } 2708 } 2709 2710 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2711 return (AHCI_FAILURE); 2712 } 2713 2714 /* 2715 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2716 */ 2717 static void 2718 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2719 { 2720 int port; 2721 2722 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2723 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2724 /* if this port is implemented by the HBA */ 2725 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2726 ahci_dealloc_port_state(ahci_ctlp, port); 2727 } 2728 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2729 } 2730 2731 /* 2732 * Drain the taskq. 2733 */ 2734 static void 2735 ahci_drain_ports_taskq(ahci_ctl_t *ahci_ctlp) 2736 { 2737 ahci_port_t *ahci_portp; 2738 int port; 2739 2740 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2741 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2742 continue; 2743 } 2744 2745 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2746 2747 mutex_enter(&ahci_portp->ahciport_mutex); 2748 ddi_taskq_wait(ahci_portp->ahciport_event_taskq); 2749 mutex_exit(&ahci_portp->ahciport_mutex); 2750 } 2751 } 2752 2753 /* 2754 * Initialize the controller and all ports. And then try to start the ports 2755 * if there are devices attached. 2756 * 2757 * This routine can be called from three seperate cases: DDI_ATTACH, 2758 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2759 * other two cases; device signature probing are attempted only during 2760 * DDI_ATTACH case. 2761 * 2762 * WARNING!!! Disable the whole controller's interrupts before calling and 2763 * the interrupts will be enabled upon successfully return. 2764 */ 2765 static int 2766 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2767 { 2768 ahci_port_t *ahci_portp; 2769 uint32_t ghc_control; 2770 int port; 2771 2772 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2773 "ahci_initialize_controller enter"); 2774 2775 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2776 2777 /* 2778 * Indicate that system software is AHCI aware by setting 2779 * GHC.AE to 1 2780 */ 2781 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2782 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2783 2784 ghc_control |= AHCI_HBA_GHC_AE; 2785 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2786 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2787 ghc_control); 2788 2789 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2790 2791 /* Initialize the implemented ports and structures */ 2792 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2793 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2794 continue; 2795 } 2796 2797 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2798 mutex_enter(&ahci_portp->ahciport_mutex); 2799 2800 /* 2801 * Ensure that the controller is not in the running state 2802 * by checking every implemented port's PxCMD register 2803 */ 2804 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2805 != AHCI_SUCCESS) { 2806 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2807 "ahci_initialize_controller: failed to " 2808 "initialize port %d", port); 2809 /* 2810 * Set the port state to SATA_PSTATE_FAILED if 2811 * failed to initialize it. 2812 */ 2813 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2814 } 2815 2816 mutex_exit(&ahci_portp->ahciport_mutex); 2817 } 2818 2819 /* Enable the whole controller interrupts */ 2820 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2821 ahci_enable_all_intrs(ahci_ctlp); 2822 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2823 2824 return (AHCI_SUCCESS); 2825 } 2826 2827 /* 2828 * Reverse of ahci_initialize_controller() 2829 * 2830 * We only need to stop the ports and disable the interrupt. 2831 */ 2832 static void 2833 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2834 { 2835 ahci_port_t *ahci_portp; 2836 int port; 2837 2838 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2839 "ahci_uninitialize_controller enter"); 2840 2841 /* disable all the interrupts. */ 2842 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2843 ahci_disable_all_intrs(ahci_ctlp); 2844 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2845 2846 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2847 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2848 continue; 2849 } 2850 2851 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2852 2853 /* Stop the port by clearing PxCMD.ST */ 2854 mutex_enter(&ahci_portp->ahciport_mutex); 2855 2856 /* 2857 * Here we must disable the port interrupt because 2858 * ahci_disable_all_intrs only clear GHC.IE, and IS 2859 * register will be still set if PxIE is enabled. 2860 * When ahci shares one IRQ with other drivers, the 2861 * intr handler may claim the intr mistakenly. 2862 */ 2863 ahci_disable_port_intrs(ahci_ctlp, port); 2864 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2865 ahci_portp, port); 2866 mutex_exit(&ahci_portp->ahciport_mutex); 2867 } 2868 } 2869 2870 /* 2871 * The routine is to initialize the port. First put the port in NOTRunning 2872 * state, then enable port interrupt and clear Serror register. And under 2873 * AHCI_ATTACH case, find device signature and then try to start the port. 2874 * 2875 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2876 */ 2877 static int 2878 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2879 ahci_port_t *ahci_portp, uint8_t port) 2880 { 2881 uint32_t port_sstatus, port_task_file, port_cmd_status; 2882 int ret; 2883 2884 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2885 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2886 2887 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2888 "ahci_initialize_port: port %d " 2889 "port_cmd_status = 0x%x", port, port_cmd_status); 2890 /* 2891 * Check whether the port is in NotRunning state, if not, 2892 * put the port in NotRunning state 2893 */ 2894 if (port_cmd_status & 2895 (AHCI_CMD_STATUS_ST | 2896 AHCI_CMD_STATUS_CR | 2897 AHCI_CMD_STATUS_FRE | 2898 AHCI_CMD_STATUS_FR)) { 2899 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2900 ahci_portp, port); 2901 } 2902 2903 /* Device is unknown at first */ 2904 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 2905 2906 /* Disable the interface power management */ 2907 ahci_disable_interface_pm(ahci_ctlp, port); 2908 2909 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2910 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 2911 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2912 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2913 2914 /* Check physcial link status */ 2915 if (SSTATUS_GET_IPM(port_sstatus) == SSTATUS_IPM_NODEV_NOPHYCOM || 2916 SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_NOPHYCOM || 2917 2918 /* Check interface status */ 2919 port_task_file & AHCI_TFD_STS_BSY || 2920 port_task_file & AHCI_TFD_STS_DRQ) { 2921 2922 /* Incorrect task file state, we need to reset port */ 2923 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2924 2925 /* Does port reset succeed on HBA port? */ 2926 if (ret != AHCI_SUCCESS) { 2927 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp, 2928 "ahci_initialize_port:" 2929 "port reset faild at port %d", port); 2930 return (AHCI_FAILURE); 2931 } 2932 2933 /* Is port failed? */ 2934 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 2935 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ERRS, ahci_ctlp, 2936 "ahci_initialize_port: port %d state 0x%x", 2937 port, ahci_portp->ahciport_port_state); 2938 return (AHCI_FAILURE); 2939 } 2940 } 2941 2942 ahci_portp->ahciport_port_state = SATA_STATE_READY; 2943 2944 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "port %d is ready now.", port); 2945 2946 /* 2947 * At the time being, only probe ports/devices and get the types of 2948 * attached devices during DDI_ATTACH. In fact, the device can be 2949 * changed during power state changes, but at the time being, we 2950 * don't support the situation. 2951 */ 2952 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2953 /* 2954 * Try to get the device signature if the port is 2955 * not empty. 2956 */ 2957 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) 2958 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2959 } else { 2960 2961 /* 2962 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 2963 * and PxFBU registers in case these registers were cleared 2964 * during the suspend. 2965 */ 2966 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2967 "ahci_initialize_port: port %d " 2968 "reset the port during resume", port); 2969 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 2970 2971 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2972 "ahci_initialize_port: port %d " 2973 "set PxCLB, PxCLBU, PxFB and PxFBU " 2974 "during resume", port); 2975 2976 /* Config Port Received FIS Base Address */ 2977 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2978 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 2979 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 2980 2981 /* Config Port Command List Base Address */ 2982 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2983 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 2984 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 2985 } 2986 2987 /* Return directly if no device connected */ 2988 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2989 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2990 "No device connected to port %d", port); 2991 goto out; 2992 } 2993 2994 /* Try to start the port */ 2995 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2996 != AHCI_SUCCESS) { 2997 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2998 "failed to start port %d", port); 2999 return (AHCI_FAILURE); 3000 } 3001 out: 3002 /* Enable port interrupts */ 3003 ahci_enable_port_intrs(ahci_ctlp, port); 3004 3005 return (AHCI_SUCCESS); 3006 } 3007 3008 /* 3009 * Handle hardware defect, and check the capabilities. For example, 3010 * power management capabilty and MSI capability. 3011 */ 3012 static int 3013 ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 3014 { 3015 ushort_t venid, devid; 3016 ushort_t caps_ptr, cap_count, cap; 3017 #if AHCI_DEBUG 3018 ushort_t pmcap, pmcsr; 3019 ushort_t msimc; 3020 #endif 3021 uint8_t revision; 3022 3023 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 3024 PCI_CONF_VENID); 3025 3026 devid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 3027 PCI_CONF_DEVID); 3028 3029 /* 3030 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 3031 * controllers with 0x00 revision id work on 4-byte aligned buffer, 3032 * which is a bug and was fixed after 0x00 revision id controllers. 3033 * 3034 * Moreover, VT8251 cannot use multiple command slots in the command 3035 * list for non-queued commands because the previous register content 3036 * of PxCI can be re-written in the register write, so a flag will be 3037 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 3038 */ 3039 if (venid == VIA_VENID) { 3040 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 3041 PCI_CONF_REVID); 3042 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3043 "revision id = 0x%x", revision); 3044 if (revision == 0x00) { 3045 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 3046 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3047 "change ddi_attr_align to 0x4"); 3048 } 3049 3050 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 3051 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3052 "VT8251 cannot use multiple command lists for " 3053 "non-queued commands"); 3054 } 3055 3056 /* 3057 * AMD/ATI SB600 (1002,4380) AHCI chipset doesn't support 64-bit DMA 3058 * addressing for both data buffer and communication memory descriptors 3059 * though S64A bit of CAP register declares the support. 3060 */ 3061 if (venid == 0x1002 && devid == 0x4380) { 3062 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3063 "ATI SB600 cannot do 64-bit DMA for both data buffer " 3064 "and communication memory descriptors though CAP indicates " 3065 "support, so force it to use 32-bit DMA"); 3066 ahci_ctlp->ahcictl_cap |= AHCI_CAP_BUF_32BIT_DMA; 3067 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA; 3068 } 3069 3070 /* 3071 * AMD/ATI SB700/750 (1002,4391) AHCI chipset doesn't support 64-bit 3072 * DMA addressing for communication memory descriptors though S64A bit 3073 * of CAP register declares the support. However, it does support 3074 * 64-bit DMA for data buffer. 3075 */ 3076 if (venid == 0x1002 && devid == 0x4391) { 3077 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3078 "ATI SB700/750 cannot do 64-bit DMA for communication " 3079 "memory descriptors though CAP indicates support, " 3080 "so force it to use 32-bit DMA"); 3081 ahci_ctlp->ahcictl_cap |= AHCI_CAP_COMMU_32BIT_DMA; 3082 } 3083 3084 /* 3085 * nVidia MCP78 AHCI controller (pci10de,0ad4) will be forced to use 3086 * Fixed interrupt until the known CR 6766472 (MSIs do not function 3087 * on most Nvidia boards) is fixed. 3088 */ 3089 if (venid == 0x10de && devid == 0x0ad4) { 3090 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3091 "Force nVidia MCP78 AHCI controller to use " 3092 "fixed interrupts"); 3093 ahci_msi_enabled = B_FALSE; 3094 } 3095 3096 /* 3097 * Check if capabilities list is supported and if so, 3098 * get initial capabilities pointer and clear bits 0,1. 3099 */ 3100 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 3101 PCI_CONF_STAT) & PCI_STAT_CAP) { 3102 caps_ptr = P2ALIGN(pci_config_get8( 3103 ahci_ctlp->ahcictl_pci_conf_handle, 3104 PCI_CONF_CAP_PTR), 4); 3105 } else { 3106 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 3107 } 3108 3109 /* 3110 * Walk capabilities if supported. 3111 */ 3112 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 3113 3114 /* 3115 * Check that we haven't exceeded the maximum number of 3116 * capabilities and that the pointer is in a valid range. 3117 */ 3118 if (++cap_count > PCI_CAP_MAX_PTR) { 3119 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3120 "too many device capabilities"); 3121 return (AHCI_FAILURE); 3122 } 3123 if (caps_ptr < PCI_CAP_PTR_OFF) { 3124 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3125 "capabilities pointer 0x%x out of range", 3126 caps_ptr); 3127 return (AHCI_FAILURE); 3128 } 3129 3130 /* 3131 * Get next capability and check that it is valid. 3132 * For now, we only support power management. 3133 */ 3134 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 3135 caps_ptr); 3136 switch (cap) { 3137 case PCI_CAP_ID_PM: 3138 3139 /* power management supported */ 3140 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 3141 3142 /* Save PMCSR offset */ 3143 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 3144 3145 #if AHCI_DEBUG 3146 pmcap = pci_config_get16( 3147 ahci_ctlp->ahcictl_pci_conf_handle, 3148 caps_ptr + PCI_PMCAP); 3149 pmcsr = pci_config_get16( 3150 ahci_ctlp->ahcictl_pci_conf_handle, 3151 ahci_ctlp->ahcictl_pmcsr_offset); 3152 AHCIDBG2(AHCIDBG_PM, ahci_ctlp, 3153 "Power Management capability found PCI_PMCAP " 3154 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 3155 if ((pmcap & 0x3) == 0x3) 3156 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3157 "PCI Power Management Interface " 3158 "spec 1.2 compliant"); 3159 #endif 3160 break; 3161 3162 case PCI_CAP_ID_MSI: 3163 #if AHCI_DEBUG 3164 msimc = pci_config_get16( 3165 ahci_ctlp->ahcictl_pci_conf_handle, 3166 caps_ptr + PCI_MSI_CTRL); 3167 AHCIDBG1(AHCIDBG_MSI, ahci_ctlp, 3168 "Message Signaled Interrupt capability found " 3169 "MSICAP_MC.MMC = 0x%x", (msimc & 0xe) >> 1); 3170 #endif 3171 AHCIDBG0(AHCIDBG_MSI, ahci_ctlp, 3172 "MSI capability found"); 3173 break; 3174 3175 case PCI_CAP_ID_PCIX: 3176 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3177 "PCI-X capability found"); 3178 break; 3179 3180 case PCI_CAP_ID_PCI_E: 3181 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3182 "PCI Express capability found"); 3183 break; 3184 3185 case PCI_CAP_ID_MSI_X: 3186 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3187 "MSI-X capability found"); 3188 break; 3189 3190 case PCI_CAP_ID_SATA: 3191 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3192 "SATA capability found"); 3193 break; 3194 3195 case PCI_CAP_ID_VS: 3196 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3197 "Vendor Specific capability found"); 3198 break; 3199 3200 default: 3201 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 3202 "unrecognized capability 0x%x", cap); 3203 break; 3204 } 3205 3206 /* 3207 * Get next capabilities pointer and clear bits 0,1. 3208 */ 3209 caps_ptr = P2ALIGN(pci_config_get8( 3210 ahci_ctlp->ahcictl_pci_conf_handle, 3211 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 3212 } 3213 3214 return (AHCI_SUCCESS); 3215 } 3216 3217 /* 3218 * AHCI device reset ...; a single device on one of the ports is reset, 3219 * but the HBA and physical communication remain intact. This is the 3220 * least intrusive. 3221 * 3222 * When issuing a software reset sequence, there should not be other 3223 * commands in the command list, so we will first clear and then re-set 3224 * PxCMD.ST to clear PxCI. And before issuing the software reset, 3225 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 3226 * cleared unless command list override (PxCMD.CLO) is supported. 3227 * 3228 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 3229 * set before the function is called. 3230 */ 3231 static int 3232 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3233 uint8_t port) 3234 { 3235 ahci_fis_h2d_register_t *h2d_register_fisp; 3236 ahci_cmd_table_t *cmd_table; 3237 ahci_cmd_header_t *cmd_header; 3238 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 3239 int slot, loop_count; 3240 int rval = AHCI_FAILURE; 3241 3242 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3243 "Port %d device resetting", port); 3244 3245 /* First clear PxCMD.ST (AHCI v1.2 10.4.1) */ 3246 if (ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 3247 port) != AHCI_SUCCESS) { 3248 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3249 "ahci_software_reset: cannot stop HBA port %d.", port); 3250 goto out; 3251 } 3252 3253 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 3254 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3255 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3256 3257 if (port_task_file & AHCI_TFD_STS_BSY || 3258 port_task_file & AHCI_TFD_STS_DRQ) { 3259 if (!(ahci_ctlp->ahcictl_cap & AHCI_CAP_SCLO)) { 3260 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3261 "PxTFD.STS.BSY/DRQ is set (PxTFD=0x%x), " 3262 "cannot issue a software reset.", port_task_file); 3263 goto out; 3264 } 3265 3266 /* 3267 * If HBA Support CLO, as Command List Override (CAP.SCLO is 3268 * set), PxCMD.CLO bit should be set before set PxCMD.ST, in 3269 * order to clear PxTFD.STS.BSY and PxTFD.STS.DRQ. 3270 */ 3271 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3272 "PxTFD.STS.BSY/DRQ is set, try SCLO.") 3273 3274 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3275 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3276 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3277 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3278 port_cmd_status|AHCI_CMD_STATUS_CLO); 3279 3280 /* Waiting till PxCMD.SCLO bit is cleared */ 3281 loop_count = 0; 3282 do { 3283 /* Wait for 10 millisec */ 3284 drv_usecwait(AHCI_10MS_USECS); 3285 3286 /* We are effectively timing out after 1 sec. */ 3287 if (loop_count++ > 100) { 3288 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3289 "SCLO time out. port %d is busy.", port); 3290 goto out; 3291 } 3292 3293 port_cmd_status = 3294 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3295 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3296 } while (port_cmd_status & AHCI_CMD_STATUS_CLO); 3297 3298 /* Re-check */ 3299 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3300 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3301 if (port_task_file & AHCI_TFD_STS_BSY || 3302 port_task_file & AHCI_TFD_STS_DRQ) { 3303 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3304 "SCLO cannot clear PxTFD.STS.BSY/DRQ (PxTFD=0x%x)", 3305 port_task_file); 3306 goto out; 3307 } 3308 } 3309 3310 /* Then start port */ 3311 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 3312 != AHCI_SUCCESS) { 3313 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3314 "ahci_software_reset: cannot start AHCI port %d.", port); 3315 goto out; 3316 } 3317 3318 /* 3319 * When ahci_port.ahciport_mop_in_progress is set, A non-zero 3320 * ahci_port.ahciport_pending_ncq_tags may fail 3321 * ahci_claim_free_slot(). Actually according to spec, by clearing 3322 * PxCMD.ST there is no command outstanding while executing software 3323 * reseting. Hence we directly use slot 0 instead of 3324 * ahci_claim_free_slot(). 3325 */ 3326 slot = 0; 3327 3328 /* Now send the first H2D Register FIS with SRST set to 1 */ 3329 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3330 bzero((void *)cmd_table, ahci_cmd_table_size); 3331 3332 h2d_register_fisp = 3333 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3334 3335 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3336 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 3337 3338 /* Set Command Header in Command List */ 3339 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3340 BZERO_DESCR_INFO(cmd_header); 3341 BZERO_PRD_BYTE_COUNT(cmd_header); 3342 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3343 3344 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 3345 SET_RESET(cmd_header, 1); 3346 SET_WRITE(cmd_header, 1); 3347 3348 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3349 0, 3350 ahci_cmd_table_size, 3351 DDI_DMA_SYNC_FORDEV); 3352 3353 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3354 slot * sizeof (ahci_cmd_header_t), 3355 sizeof (ahci_cmd_header_t), 3356 DDI_DMA_SYNC_FORDEV); 3357 3358 /* Indicate to the HBA that a command is active. */ 3359 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3360 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3361 (0x1 << slot)); 3362 3363 loop_count = 0; 3364 3365 /* Loop till the first command is finished */ 3366 do { 3367 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3368 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3369 3370 /* We are effectively timing out after 1 sec. */ 3371 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3372 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3373 "the first SRST FIS is timed out, " 3374 "loop_count = %d", loop_count); 3375 goto out; 3376 } 3377 3378 /* Wait for 10 millisec */ 3379 delay(AHCI_10MS_TICKS); 3380 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3381 3382 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3383 "ahci_software_reset: 1st loop count: %d, " 3384 "port_cmd_issue = 0x%x, slot = 0x%x", 3385 loop_count, port_cmd_issue, slot); 3386 3387 /* According to ATA spec, we need wait at least 5 microsecs here. */ 3388 drv_usecwait(AHCI_1MS_USECS); 3389 3390 /* Now send the second H2D Register FIS with SRST cleard to zero */ 3391 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3392 bzero((void *)cmd_table, ahci_cmd_table_size); 3393 3394 h2d_register_fisp = 3395 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3396 3397 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3398 3399 /* Set Command Header in Command List */ 3400 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3401 BZERO_DESCR_INFO(cmd_header); 3402 BZERO_PRD_BYTE_COUNT(cmd_header); 3403 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3404 3405 SET_WRITE(cmd_header, 1); 3406 3407 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3408 0, 3409 ahci_cmd_table_size, 3410 DDI_DMA_SYNC_FORDEV); 3411 3412 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3413 slot * sizeof (ahci_cmd_header_t), 3414 sizeof (ahci_cmd_header_t), 3415 DDI_DMA_SYNC_FORDEV); 3416 3417 /* Indicate to the HBA that a command is active. */ 3418 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3419 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3420 (0x1 << slot)); 3421 3422 loop_count = 0; 3423 3424 /* Loop till the second command is finished */ 3425 do { 3426 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3427 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3428 3429 /* We are effectively timing out after 1 sec. */ 3430 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3431 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3432 "the second SRST FIS is timed out, " 3433 "loop_count = %d", loop_count); 3434 goto out; 3435 } 3436 3437 /* Wait for 10 millisec */ 3438 delay(AHCI_10MS_TICKS); 3439 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3440 3441 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3442 "ahci_software_reset: 2nd loop count: %d, " 3443 "port_cmd_issue = 0x%x, slot = 0x%x", 3444 loop_count, port_cmd_issue, slot); 3445 3446 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3447 3448 rval = AHCI_SUCCESS; 3449 out: 3450 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3451 "ahci_software_reset: %s at port %d", 3452 rval == AHCI_SUCCESS ? "succeed" : "failed", 3453 port); 3454 3455 return (rval); 3456 } 3457 3458 /* 3459 * AHCI port reset ...; the physical communication between the HBA and device 3460 * on a port are disabled. This is more intrusive. 3461 * 3462 * When an HBA or port reset occurs, Phy communication is going to 3463 * be re-established with the device through a COMRESET followed by the 3464 * normal out-of-band communication sequence defined in Serial ATA. AT 3465 * the end of reset, the device, if working properly, will send a D2H 3466 * Register FIS, which contains the device signature. When the HBA receives 3467 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 3468 * the PxSIG register with the signature. 3469 * 3470 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 3471 * to individually spin-up attached devices. Please refer to chapter 10.9 of 3472 * AHCI 1.0 spec. 3473 */ 3474 /* 3475 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 3476 * cleared before the function is called. 3477 */ 3478 static int 3479 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3480 { 3481 uint32_t cap_status, port_cmd_status; 3482 uint32_t port_scontrol, port_sstatus, port_serror; 3483 uint32_t port_intr_status, port_task_file; 3484 3485 int loop_count; 3486 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 3487 3488 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3489 "Port %d port resetting...", port); 3490 ahci_portp->ahciport_port_state = 0; 3491 3492 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3493 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3494 3495 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3496 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3497 3498 if (cap_status & AHCI_HBA_CAP_SSS) { 3499 /* 3500 * HBA support staggered spin-up, if the port has 3501 * not spin up yet, then force it to do spin-up 3502 */ 3503 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 3504 if (!(ahci_portp->ahciport_flags 3505 & AHCI_PORT_FLAG_SPINUP)) { 3506 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3507 "Port %d PxCMD.SUD is zero, force " 3508 "it to do spin-up", port); 3509 ahci_portp->ahciport_flags |= 3510 AHCI_PORT_FLAG_SPINUP; 3511 } 3512 } 3513 } else { 3514 /* 3515 * HBA doesn't support stagger spin-up, force it 3516 * to do normal COMRESET 3517 */ 3518 if (ahci_portp->ahciport_flags & 3519 AHCI_PORT_FLAG_SPINUP) { 3520 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3521 "HBA does not support staggered spin-up " 3522 "force it to do normal COMRESET"); 3523 ahci_portp->ahciport_flags &= 3524 ~AHCI_PORT_FLAG_SPINUP; 3525 } 3526 } 3527 3528 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 3529 /* Do normal COMRESET */ 3530 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3531 "ahci_port_reset: do normal COMRESET", port); 3532 3533 /* 3534 * According to the spec, SUD bit should be set here, 3535 * but JMicron JMB363 doesn't follow it, so remove 3536 * the assertion, and just print a debug message. 3537 */ 3538 #if AHCI_DEBUG 3539 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3540 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3541 "port %d SUD bit not set", port) 3542 #endif 3543 3544 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3545 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3546 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3547 3548 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3549 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3550 port_scontrol); 3551 3552 /* Enable PxCMD.FRE to read device */ 3553 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3554 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3555 port_cmd_status|AHCI_CMD_STATUS_FRE); 3556 3557 /* 3558 * Give time for COMRESET to percolate, according to the AHCI 3559 * spec, software shall wait at least 1 millisecond before 3560 * clearing PxSCTL.DET 3561 */ 3562 delay(AHCI_1MS_TICKS*2); 3563 3564 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3565 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3566 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3567 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3568 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3569 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3570 port_scontrol); 3571 } else { 3572 /* Do staggered spin-up */ 3573 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3574 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3575 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3576 3577 /* PxSCTL.DET must be 0 */ 3578 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3579 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3580 port_scontrol); 3581 3582 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3583 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3584 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3585 port_cmd_status); 3586 3587 /* 0 -> 1 edge */ 3588 delay(AHCI_1MS_TICKS*2); 3589 3590 /* Set PxCMD.SUD to 1 */ 3591 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3592 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3593 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3594 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3595 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3596 port_cmd_status); 3597 3598 /* Enable PxCMD.FRE to read device */ 3599 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3600 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3601 port_cmd_status|AHCI_CMD_STATUS_FRE); 3602 } 3603 3604 /* 3605 * The port enters P:StartComm state, and HBA tells link layer to 3606 * start communication, which involves sending COMRESET to device. 3607 * And the HBA resets PxTFD.STS to 7Fh. 3608 * 3609 * When a COMINIT is received from the device, then the port enters 3610 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3611 * PxSSTS.DET to 1h to indicate a device is detected but communication 3612 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3613 * a COMINIT has been received. 3614 */ 3615 /* 3616 * The DET field is valid only if IPM field indicates 3617 * that the interface is in active state. 3618 */ 3619 loop_count = 0; 3620 do { 3621 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3622 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3623 3624 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3625 /* 3626 * If the interface is not active, the DET field 3627 * is considered not accurate. So we want to 3628 * continue looping. 3629 */ 3630 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3631 } 3632 3633 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3634 /* 3635 * We are effectively timing out after 0.1 sec. 3636 */ 3637 break; 3638 } 3639 3640 /* Wait for 10 millisec */ 3641 delay(AHCI_10MS_TICKS); 3642 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3643 3644 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3645 "ahci_port_reset: 1st loop count: %d, " 3646 "port_sstatus = 0x%x port %d", 3647 loop_count, port_sstatus, port); 3648 3649 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3650 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3651 /* 3652 * Either the port is not active or there 3653 * is no device present. 3654 */ 3655 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3656 return (AHCI_SUCCESS); 3657 } 3658 3659 /* Now we can make sure there is a device connected to the port */ 3660 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3661 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3662 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3663 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 3664 3665 /* 3666 * A COMINIT signal is supposed to be received 3667 * PxSERR.DIAG.X or PxIS.PCS should be set 3668 */ 3669 if (!(port_intr_status & AHCI_INTR_STATUS_PCS) && 3670 !(port_serror & SERROR_EXCHANGED_ERR)) { 3671 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 3672 "COMINIT signal from the device not received", 3673 instance, port); 3674 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3675 return (AHCI_FAILURE); 3676 } 3677 3678 /* 3679 * According to the spec, when PxSCTL.DET is set to 0h, upon 3680 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3681 * shall be set to '1' by the HBA. 3682 * 3683 * However, we found JMicron JMB363 doesn't follow this, so 3684 * remove this check, and just print a debug message. 3685 */ 3686 #if AHCI_DEBUG 3687 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3688 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3689 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3690 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3691 "port %d BSY bit is not set after COMINIT signal " 3692 "is received", port); 3693 } 3694 #endif 3695 3696 /* 3697 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3698 * the D2H FIS received by HBA. 3699 */ 3700 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3701 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3702 SERROR_EXCHANGED_ERR); 3703 3704 /* 3705 * Devices should return a FIS contains its signature to HBA after 3706 * COMINIT signal. Check whether a D2H FIS is received by polling 3707 * PxTFD.STS.ERR bit. 3708 */ 3709 loop_count = 0; 3710 do { 3711 /* Wait for 10 millisec */ 3712 delay(AHCI_10MS_TICKS); 3713 3714 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3715 /* 3716 * We are effectively timing out after 11 sec. 3717 */ 3718 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 3719 "the device hardware has been initialized and " 3720 "the power-up diagnostics failed", 3721 instance, port); 3722 3723 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3724 "port %d PxTFD.STS.ERR is not set, we need another " 3725 "software reset.", port); 3726 3727 /* Clear port serror register for the port */ 3728 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3729 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3730 AHCI_SERROR_CLEAR_ALL); 3731 3732 /* Try another software reset. */ 3733 if (ahci_software_reset(ahci_ctlp, ahci_portp, 3734 port) != AHCI_SUCCESS) { 3735 ahci_portp->ahciport_port_state |= 3736 SATA_PSTATE_FAILED; 3737 return (AHCI_FAILURE); 3738 } 3739 break; 3740 } 3741 3742 /* 3743 * The Error bit '1' means COMRESET is finished successfully 3744 * The device hardware has been initialized and the power-up 3745 * diagnostics successfully completed. The device requests 3746 * that the Transport layer transmit a Register - D2H FIS to 3747 * the host. (SATA spec 11.5, v2.6) 3748 */ 3749 port_task_file = 3750 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3751 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3752 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3753 >> AHCI_TFD_ERR_SHIFT) != AHCI_TFD_ERR_SGS); 3754 3755 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3756 "ahci_port_reset: 2nd loop count: %d, " 3757 "port_task_file = 0x%x port %d", 3758 loop_count, port_task_file, port); 3759 3760 /* Clear port serror register for the port */ 3761 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3762 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3763 AHCI_SERROR_CLEAR_ALL); 3764 3765 /* Set port as ready */ 3766 ahci_portp->ahciport_port_state |= SATA_STATE_READY; 3767 3768 AHCIDBG1(AHCIDBG_INFO|AHCIDBG_ERRS, ahci_ctlp, 3769 "ahci_port_reset: succeed at port %d.", port); 3770 return (AHCI_SUCCESS); 3771 } 3772 3773 /* 3774 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3775 * This is the most intrusive. 3776 * 3777 * When an HBA reset occurs, Phy communication will be re-established with 3778 * the device through a COMRESET followed by the normal out-of-band 3779 * communication sequence defined in Serial ATA. AT the end of reset, the 3780 * device, if working properly, will send a D2H Register FIS, which contains 3781 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3782 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3783 * signature. 3784 * 3785 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3786 */ 3787 static int 3788 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3789 { 3790 ahci_port_t *ahci_portp; 3791 uint32_t ghc_control; 3792 uint8_t port; 3793 int loop_count; 3794 int rval = AHCI_SUCCESS; 3795 3796 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3797 3798 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3799 3800 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3801 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3802 3803 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3804 ghc_control |= AHCI_HBA_GHC_HR; 3805 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3806 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3807 3808 /* 3809 * Wait until HBA Reset complete or timeout 3810 */ 3811 loop_count = 0; 3812 do { 3813 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3814 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3815 3816 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3817 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3818 "ahci hba reset is timing out, " 3819 "ghc_control = 0x%x", ghc_control); 3820 /* We are effectively timing out after 1 sec. */ 3821 break; 3822 } 3823 3824 /* Wait for 10 millisec */ 3825 delay(AHCI_10MS_TICKS); 3826 } while (ghc_control & AHCI_HBA_GHC_HR); 3827 3828 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3829 "ahci_hba_reset: 1st loop count: %d, " 3830 "ghc_control = 0x%x", loop_count, ghc_control); 3831 3832 if (ghc_control & AHCI_HBA_GHC_HR) { 3833 /* The hba is not reset for some reasons */ 3834 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3835 "hba reset failed: HBA in a hung or locked state"); 3836 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3837 return (AHCI_FAILURE); 3838 } 3839 3840 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3841 /* Only check implemented ports */ 3842 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3843 continue; 3844 } 3845 3846 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3847 mutex_enter(&ahci_portp->ahciport_mutex); 3848 3849 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3850 != AHCI_SUCCESS) { 3851 rval = AHCI_FAILURE; 3852 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3853 "ahci_hba_reset: port %d failed", port); 3854 } 3855 3856 mutex_exit(&ahci_portp->ahciport_mutex); 3857 } 3858 3859 /* 3860 * Indicate that system software is AHCI aware by setting 3861 * GHC.AE to 1 3862 */ 3863 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3864 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3865 3866 ghc_control |= AHCI_HBA_GHC_AE; 3867 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3868 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3869 3870 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3871 3872 return (rval); 3873 } 3874 3875 /* 3876 * This routine is only called from AHCI_ATTACH or phyrdy change 3877 * case. It first calls software reset, then stop the port and try to 3878 * read PxSIG register to find the type of device attached to the port. 3879 * 3880 * The caller should make sure a valid device exists on specified port and 3881 * physical communication has been established so that the signature could 3882 * be retrieved by software reset. 3883 * 3884 * WARNING!!! ahciport_mutex should be acquired before the function 3885 * is called. And the port interrupt is disabled. 3886 */ 3887 static void 3888 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3889 ahci_port_t *ahci_portp, uint8_t port) 3890 { 3891 uint32_t signature; 3892 3893 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3894 "ahci_find_dev_signature enter: port %d", port); 3895 3896 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3897 3898 /* Issue a software reset to get the signature */ 3899 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 3900 != AHCI_SUCCESS) { 3901 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3902 "ahci_find_dev_signature: software reset failed " 3903 "at port %d, cannot get signature.", port); 3904 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 3905 return; 3906 } 3907 3908 /* 3909 * ahci_software_reset has started the port, so we need manually stop 3910 * the port again. 3911 */ 3912 if (ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, port) 3913 != AHCI_SUCCESS) { 3914 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3915 "ahci_find_dev_signature: cannot stop port %d.", port); 3916 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 3917 return; 3918 } 3919 3920 /* Now we can make sure that a valid signature is received. */ 3921 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3922 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3923 3924 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3925 "ahci_find_dev_signature: port %d signature = 0x%x", 3926 port, signature); 3927 3928 switch (signature) { 3929 3930 case AHCI_SIGNATURE_DISK: 3931 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3932 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3933 "Disk is found at port: %d", port); 3934 break; 3935 3936 case AHCI_SIGNATURE_ATAPI: 3937 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPI; 3938 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3939 "ATAPI device is found at port: %d", port); 3940 break; 3941 3942 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3943 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3944 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3945 "Port Multiplier is found at port: %d", port); 3946 break; 3947 3948 default: 3949 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3950 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3951 "Unknown device is found at port: %d", port); 3952 } 3953 } 3954 3955 /* 3956 * According to the spec, to reliably detect hot plug removals, software 3957 * must disable interface power management. Software should perform the 3958 * following initialization on a port after a device is attached: 3959 * Set PxSCTL.IPM to 3h to disable interface state transitions 3960 * Set PxCMD.ALPE to '0' to disable aggressive power management 3961 * Disable device initiated interface power management by SET FEATURE 3962 * 3963 * We can ignore the last item because by default the feature is disabled 3964 */ 3965 static void 3966 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 3967 { 3968 uint32_t port_scontrol, port_cmd_status; 3969 3970 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3971 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3972 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 3973 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3974 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3975 3976 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3977 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3978 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 3979 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3980 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 3981 } 3982 3983 /* 3984 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3985 * to 1, then set it firstly. 3986 * 3987 * Each port contains two major DMA engines. One DMA engine walks through 3988 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3989 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3990 * 3991 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3992 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3993 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3994 * 3995 * Software shall not set PxCMD.ST to '1' unless a functional device is 3996 * present on the port(as determined by PxTFD.STS.BSY = '0', 3997 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3998 * 3999 * WARNING!!! ahciport_mutex should be acquired before the function 4000 * is called. 4001 */ 4002 static int 4003 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4004 { 4005 uint32_t port_cmd_status; 4006 4007 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 4008 4009 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 4010 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 4011 "the state for port %d is 0x%x", 4012 port, ahci_portp->ahciport_port_state); 4013 return (AHCI_FAILURE); 4014 } 4015 4016 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 4017 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 4018 "no device is attached at port %d", port); 4019 return (AHCI_FAILURE); 4020 } 4021 4022 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 4023 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4024 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4025 4026 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 4027 port_cmd_status |= AHCI_CMD_STATUS_FRE; 4028 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4029 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 4030 port_cmd_status); 4031 } 4032 4033 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4034 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4035 4036 port_cmd_status |= AHCI_CMD_STATUS_ST; 4037 4038 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4039 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 4040 port_cmd_status); 4041 4042 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 4043 4044 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port: " 4045 "PxCMD.ST set to '1' at port %d", port); 4046 4047 return (AHCI_SUCCESS); 4048 } 4049 4050 /* 4051 * Allocate the ahci_port_t including Received FIS and Command List. 4052 * The argument - port is the physical port number, and not logical 4053 * port number seen by the SATA framework. 4054 * 4055 * WARNING!!! ahcictl_mutex should be acquired before the function 4056 * is called. 4057 */ 4058 static int 4059 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 4060 { 4061 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 4062 ahci_port_t *ahci_portp; 4063 char taskq_name[64] = "event_handle_taskq"; 4064 4065 ahci_portp = 4066 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 4067 4068 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 4069 ahci_portp->ahciport_port_num = port; 4070 4071 /* Intialize the port condition variable */ 4072 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 4073 4074 /* Initialize the port mutex */ 4075 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 4076 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 4077 4078 mutex_enter(&ahci_portp->ahciport_mutex); 4079 4080 /* 4081 * Allocate memory for received FIS structure and 4082 * command list for this port 4083 */ 4084 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 4085 goto err_case1; 4086 } 4087 4088 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 4089 goto err_case2; 4090 } 4091 4092 (void) snprintf(taskq_name + strlen(taskq_name), 4093 sizeof (taskq_name) - strlen(taskq_name), 4094 "_port%d", port); 4095 4096 /* Create the taskq for the port */ 4097 if ((ahci_portp->ahciport_event_taskq = ddi_taskq_create(dip, 4098 taskq_name, 2, TASKQ_DEFAULTPRI, 0)) == NULL) { 4099 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event " 4100 "handle", ddi_get_instance(ahci_ctlp->ahcictl_dip)); 4101 goto err_case3; 4102 } 4103 4104 /* Allocate the argument for the taskq */ 4105 ahci_portp->ahciport_event_args = 4106 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 4107 4108 if (ahci_portp->ahciport_event_args == NULL) 4109 goto err_case4; 4110 4111 mutex_exit(&ahci_portp->ahciport_mutex); 4112 4113 return (AHCI_SUCCESS); 4114 4115 err_case4: 4116 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq); 4117 4118 err_case3: 4119 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 4120 4121 err_case2: 4122 ahci_dealloc_rcvd_fis(ahci_portp); 4123 4124 err_case1: 4125 mutex_exit(&ahci_portp->ahciport_mutex); 4126 mutex_destroy(&ahci_portp->ahciport_mutex); 4127 cv_destroy(&ahci_portp->ahciport_cv); 4128 4129 kmem_free(ahci_portp, sizeof (ahci_port_t)); 4130 4131 return (AHCI_FAILURE); 4132 } 4133 4134 /* 4135 * Reverse of ahci_dealloc_port_state(). 4136 * 4137 * WARNING!!! ahcictl_mutex should be acquired before the function 4138 * is called. 4139 */ 4140 static void 4141 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 4142 { 4143 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4144 4145 ASSERT(ahci_portp != NULL); 4146 4147 mutex_enter(&ahci_portp->ahciport_mutex); 4148 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 4149 ahci_portp->ahciport_event_args = NULL; 4150 ddi_taskq_destroy(ahci_portp->ahciport_event_taskq); 4151 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 4152 ahci_dealloc_rcvd_fis(ahci_portp); 4153 mutex_exit(&ahci_portp->ahciport_mutex); 4154 4155 mutex_destroy(&ahci_portp->ahciport_mutex); 4156 cv_destroy(&ahci_portp->ahciport_cv); 4157 4158 kmem_free(ahci_portp, sizeof (ahci_port_t)); 4159 4160 ahci_ctlp->ahcictl_ports[port] = NULL; 4161 } 4162 4163 /* 4164 * Allocates memory for the Received FIS Structure 4165 * 4166 * WARNING!!! ahciport_mutex should be acquired before the function 4167 * is called. 4168 */ 4169 static int 4170 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4171 uint8_t port) 4172 { 4173 size_t rcvd_fis_size; 4174 size_t ret_len; 4175 uint_t cookie_count; 4176 4177 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 4178 4179 /* allocate rcvd FIS dma handle. */ 4180 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4181 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 4182 DDI_DMA_SLEEP, 4183 NULL, 4184 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 4185 DDI_SUCCESS) { 4186 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4187 "rcvd FIS dma handle alloc failed"); 4188 4189 return (AHCI_FAILURE); 4190 } 4191 4192 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 4193 rcvd_fis_size, 4194 &accattr, 4195 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4196 DDI_DMA_SLEEP, 4197 NULL, 4198 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 4199 &ret_len, 4200 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 4201 4202 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4203 "rcvd FIS dma mem alloc fail"); 4204 /* error.. free the dma handle. */ 4205 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4206 return (AHCI_FAILURE); 4207 } 4208 4209 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 4210 NULL, 4211 (caddr_t)ahci_portp->ahciport_rcvd_fis, 4212 rcvd_fis_size, 4213 DDI_DMA_CONSISTENT, 4214 DDI_DMA_SLEEP, 4215 NULL, 4216 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 4217 &cookie_count) != DDI_DMA_MAPPED) { 4218 4219 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4220 "rcvd FIS dma handle bind fail"); 4221 /* error.. free the dma handle & free the memory. */ 4222 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4223 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4224 return (AHCI_FAILURE); 4225 } 4226 4227 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 4228 4229 /* Config Port Received FIS Base Address */ 4230 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4231 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 4232 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4233 4234 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4235 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4236 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4237 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 4238 4239 return (AHCI_SUCCESS); 4240 } 4241 4242 /* 4243 * Deallocates the Received FIS Structure 4244 * 4245 * WARNING!!! ahciport_mutex should be acquired before the function 4246 * is called. 4247 */ 4248 static void 4249 ahci_dealloc_rcvd_fis(ahci_port_t *ahci_portp) 4250 { 4251 /* Unbind the cmd list dma handle first. */ 4252 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 4253 4254 /* Then free the underlying memory. */ 4255 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4256 4257 /* Now free the handle itself. */ 4258 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4259 } 4260 4261 /* 4262 * Allocates memory for the Command List, which contains up to 32 entries. 4263 * Each entry contains a command header, which is a 32-byte structure that 4264 * includes the pointer to the command table. 4265 * 4266 * WARNING!!! ahciport_mutex should be acquired before the function 4267 * is called. 4268 */ 4269 static int 4270 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4271 uint8_t port) 4272 { 4273 size_t cmd_list_size; 4274 size_t ret_len; 4275 uint_t cookie_count; 4276 4277 cmd_list_size = 4278 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 4279 4280 /* allocate cmd list dma handle. */ 4281 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4282 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 4283 DDI_DMA_SLEEP, 4284 NULL, 4285 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 4286 4287 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4288 "cmd list dma handle alloc failed"); 4289 return (AHCI_FAILURE); 4290 } 4291 4292 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 4293 cmd_list_size, 4294 &accattr, 4295 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4296 DDI_DMA_SLEEP, 4297 NULL, 4298 (caddr_t *)&ahci_portp->ahciport_cmd_list, 4299 &ret_len, 4300 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 4301 4302 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4303 "cmd list dma mem alloc fail"); 4304 /* error.. free the dma handle. */ 4305 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4306 return (AHCI_FAILURE); 4307 } 4308 4309 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 4310 NULL, 4311 (caddr_t)ahci_portp->ahciport_cmd_list, 4312 cmd_list_size, 4313 DDI_DMA_CONSISTENT, 4314 DDI_DMA_SLEEP, 4315 NULL, 4316 &ahci_portp->ahciport_cmd_list_dma_cookie, 4317 &cookie_count) != DDI_DMA_MAPPED) { 4318 4319 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4320 "cmd list dma handle bind fail"); 4321 /* error.. free the dma handle & free the memory. */ 4322 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4323 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4324 return (AHCI_FAILURE); 4325 } 4326 4327 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 4328 4329 /* Config Port Command List Base Address */ 4330 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4331 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 4332 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4333 4334 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4335 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4336 4337 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4338 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 4339 4340 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 4341 goto err_out; 4342 } 4343 4344 return (AHCI_SUCCESS); 4345 4346 err_out: 4347 /* Unbind the cmd list dma handle first. */ 4348 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4349 4350 /* Then free the underlying memory. */ 4351 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4352 4353 /* Now free the handle itself. */ 4354 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4355 4356 return (AHCI_FAILURE); 4357 } 4358 4359 /* 4360 * Deallocates the Command List 4361 * 4362 * WARNING!!! ahciport_mutex should be acquired before the function 4363 * is called. 4364 */ 4365 static void 4366 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4367 { 4368 /* First dealloc command table */ 4369 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 4370 4371 /* Unbind the cmd list dma handle first. */ 4372 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4373 4374 /* Then free the underlying memory. */ 4375 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4376 4377 /* Now free the handle itself. */ 4378 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4379 } 4380 4381 /* 4382 * Allocates memory for all Command Tables, which contains Command FIS, 4383 * ATAPI Command and Physical Region Descriptor Table. 4384 * 4385 * WARNING!!! ahciport_mutex should be acquired before the function 4386 * is called. 4387 */ 4388 static int 4389 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4390 { 4391 size_t ret_len; 4392 ddi_dma_cookie_t cmd_table_dma_cookie; 4393 uint_t cookie_count; 4394 int slot; 4395 4396 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4397 "ahci_alloc_cmd_tables: port %d enter", 4398 ahci_portp->ahciport_port_num); 4399 4400 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4401 /* Allocate cmd table dma handle. */ 4402 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4403 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 4404 DDI_DMA_SLEEP, 4405 NULL, 4406 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 4407 DDI_SUCCESS) { 4408 4409 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4410 "cmd table dma handle alloc failed"); 4411 4412 goto err_out; 4413 } 4414 4415 if (ddi_dma_mem_alloc( 4416 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4417 ahci_cmd_table_size, 4418 &accattr, 4419 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4420 DDI_DMA_SLEEP, 4421 NULL, 4422 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 4423 &ret_len, 4424 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 4425 NULL) { 4426 4427 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4428 "cmd table dma mem alloc fail"); 4429 4430 /* error.. free the dma handle. */ 4431 ddi_dma_free_handle( 4432 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4433 goto err_out; 4434 } 4435 4436 if (ddi_dma_addr_bind_handle( 4437 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4438 NULL, 4439 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 4440 ahci_cmd_table_size, 4441 DDI_DMA_CONSISTENT, 4442 DDI_DMA_SLEEP, 4443 NULL, 4444 &cmd_table_dma_cookie, 4445 &cookie_count) != DDI_DMA_MAPPED) { 4446 4447 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4448 "cmd table dma handle bind fail"); 4449 /* error.. free the dma handle & free the memory. */ 4450 ddi_dma_mem_free( 4451 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4452 ddi_dma_free_handle( 4453 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4454 goto err_out; 4455 } 4456 4457 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 4458 ahci_cmd_table_size); 4459 4460 /* Config Port Command Table Base Address */ 4461 SET_COMMAND_TABLE_BASE_ADDR( 4462 (&ahci_portp->ahciport_cmd_list[slot]), 4463 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 4464 4465 #ifndef __lock_lint 4466 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 4467 (&ahci_portp->ahciport_cmd_list[slot]), 4468 cmd_table_dma_cookie.dmac_laddress >> 32); 4469 #endif 4470 } 4471 4472 return (AHCI_SUCCESS); 4473 err_out: 4474 4475 for (slot--; slot >= 0; slot--) { 4476 /* Unbind the cmd table dma handle first */ 4477 (void) ddi_dma_unbind_handle( 4478 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4479 4480 /* Then free the underlying memory */ 4481 ddi_dma_mem_free( 4482 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4483 4484 /* Now free the handle itself */ 4485 ddi_dma_free_handle( 4486 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4487 } 4488 4489 return (AHCI_FAILURE); 4490 } 4491 4492 /* 4493 * Deallocates memory for all Command Tables. 4494 * 4495 * WARNING!!! ahciport_mutex should be acquired before the function 4496 * is called. 4497 */ 4498 static void 4499 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4500 { 4501 int slot; 4502 4503 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4504 "ahci_dealloc_cmd_tables: %d enter", 4505 ahci_portp->ahciport_port_num); 4506 4507 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4508 /* Unbind the cmd table dma handle first. */ 4509 (void) ddi_dma_unbind_handle( 4510 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4511 4512 /* Then free the underlying memory. */ 4513 ddi_dma_mem_free( 4514 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4515 4516 /* Now free the handle itself. */ 4517 ddi_dma_free_handle( 4518 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4519 } 4520 } 4521 4522 /* 4523 * WARNING!!! ahciport_mutex should be acquired before the function 4524 * is called. 4525 */ 4526 static void 4527 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4528 sata_device_t *sd) 4529 { 4530 sd->satadev_scr.sstatus = 4531 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4532 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4533 sd->satadev_scr.serror = 4534 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4535 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4536 sd->satadev_scr.scontrol = 4537 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4538 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4539 sd->satadev_scr.sactive = 4540 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4541 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4542 } 4543 4544 /* 4545 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4546 */ 4547 static void 4548 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4549 { 4550 uint32_t port_intr_status; 4551 uint32_t port_intr_enable; 4552 4553 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4554 "ahci_port_intr enter: port %d", port); 4555 4556 mutex_enter(&ahci_portp->ahciport_mutex); 4557 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4558 /* For SATA_OPMODE_POLLING commands */ 4559 port_intr_enable = 4560 (AHCI_INTR_STATUS_DHRS | 4561 AHCI_INTR_STATUS_PSS | 4562 AHCI_INTR_STATUS_SDBS | 4563 AHCI_INTR_STATUS_UFS | 4564 AHCI_INTR_STATUS_PCS | 4565 AHCI_INTR_STATUS_PRCS | 4566 AHCI_INTR_STATUS_OFS | 4567 AHCI_INTR_STATUS_INFS | 4568 AHCI_INTR_STATUS_IFS | 4569 AHCI_INTR_STATUS_HBDS | 4570 AHCI_INTR_STATUS_HBFS | 4571 AHCI_INTR_STATUS_TFES); 4572 mutex_exit(&ahci_portp->ahciport_mutex); 4573 goto next; 4574 } 4575 mutex_exit(&ahci_portp->ahciport_mutex); 4576 4577 /* 4578 * port_intr_enable indicates that the corresponding interrrupt 4579 * reporting is enabled. 4580 */ 4581 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4582 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4583 next: 4584 /* 4585 * port_intr_stats indicates that the corresponding interrupt 4586 * condition is active. 4587 */ 4588 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4589 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4590 4591 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4592 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4593 "port_intr_enable = 0x%x", 4594 port, port_intr_status, port_intr_enable); 4595 4596 port_intr_status &= port_intr_enable; 4597 4598 /* First clear the port interrupts status */ 4599 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4600 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4601 port_intr_status); 4602 4603 /* Check the completed non-queued commands */ 4604 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4605 AHCI_INTR_STATUS_PSS)) { 4606 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4607 ahci_portp, port); 4608 } 4609 4610 /* Check the completed queued commands */ 4611 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4612 (void) ahci_intr_set_device_bits(ahci_ctlp, 4613 ahci_portp, port); 4614 } 4615 4616 /* Check the port connect change status interrupt bit */ 4617 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4618 (void) ahci_intr_port_connect_change(ahci_ctlp, 4619 ahci_portp, port); 4620 } 4621 4622 /* Check the device mechanical presence status interrupt bit */ 4623 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4624 (void) ahci_intr_device_mechanical_presence_status( 4625 ahci_ctlp, ahci_portp, port); 4626 } 4627 4628 /* Check the PhyRdy change status interrupt bit */ 4629 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4630 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4631 port); 4632 } 4633 4634 /* 4635 * Check the non-fatal error interrupt bits, there are three 4636 * kinds of non-fatal errors at the time being: 4637 * 4638 * PxIS.UFS - Unknown FIS Error 4639 * PxIS.OFS - Overflow Error 4640 * PxIS.INFS - Interface Non-Fatal Error 4641 * 4642 * For these non-fatal errors, the HBA can continue to operate, 4643 * so the driver just log the error messages. 4644 */ 4645 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4646 AHCI_INTR_STATUS_OFS | 4647 AHCI_INTR_STATUS_INFS)) { 4648 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4649 port, port_intr_status); 4650 } 4651 4652 /* 4653 * Check the fatal error interrupt bits, there are four kinds 4654 * of fatal errors for AHCI controllers: 4655 * 4656 * PxIS.HBFS - Host Bus Fatal Error 4657 * PxIS.HBDS - Host Bus Data Error 4658 * PxIS.IFS - Interface Fatal Error 4659 * PxIS.TFES - Task File Error 4660 * 4661 * The fatal error means the HBA can not recover from it by 4662 * itself, and it will try to abort the transfer, and the software 4663 * must intervene to restart the port. 4664 */ 4665 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4666 AHCI_INTR_STATUS_HBDS | 4667 AHCI_INTR_STATUS_HBFS | 4668 AHCI_INTR_STATUS_TFES)) 4669 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4670 port, port_intr_status); 4671 4672 /* Check the cold port detect interrupt bit */ 4673 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4674 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4675 } 4676 4677 /* Second clear the corresponding bit in IS.IPS */ 4678 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4679 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4680 } 4681 4682 /* 4683 * Interrupt service handler 4684 */ 4685 static uint_t 4686 ahci_intr(caddr_t arg1, caddr_t arg2) 4687 { 4688 #ifndef __lock_lint 4689 _NOTE(ARGUNUSED(arg2)) 4690 #endif 4691 /* LINTED */ 4692 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4693 ahci_port_t *ahci_portp; 4694 int32_t global_intr_status; 4695 uint8_t port; 4696 4697 /* 4698 * global_intr_status indicates that the corresponding port has 4699 * an interrupt pending. 4700 */ 4701 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4702 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4703 4704 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4705 /* The interrupt is not ours */ 4706 return (DDI_INTR_UNCLAIMED); 4707 } 4708 4709 /* Loop for all the ports */ 4710 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4711 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4712 continue; 4713 } 4714 if (!((0x1 << port) & global_intr_status)) { 4715 continue; 4716 } 4717 4718 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4719 4720 /* Call ahci_port_intr */ 4721 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4722 } 4723 4724 return (DDI_INTR_CLAIMED); 4725 } 4726 4727 /* 4728 * For non-queued commands, when the corresponding bit in the PxCI register 4729 * is cleared, it means the command is completed successfully. And according 4730 * to the HBA state machine, there are three conditions which possibly will 4731 * try to clear the PxCI register bit. 4732 * 1. Receive one D2H Register FIS which is with 'I' bit set 4733 * 2. Update PIO Setup FIS 4734 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4735 * 4736 * Process completed non-queued commands when the interrupt status bit - 4737 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4738 * 4739 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4740 * with the 'I' bit set. And the following commands will send thus 4741 * FIS with 'I' bit set upon the successful completion: 4742 * 1. Non-data commands 4743 * 2. DMA data-in command 4744 * 3. DMA data-out command 4745 * 4. PIO data-out command 4746 * 5. PACKET non-data commands 4747 * 6. PACKET PIO data-in command 4748 * 7. PACKET PIO data-out command 4749 * 8. PACKET DMA data-in command 4750 * 9. PACKET DMA data-out command 4751 * 4752 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4753 * with the 'I' bit set. And the following commands will send this 4754 * FIS upon the successful completion: 4755 * 1. PIO data-in command 4756 */ 4757 static int 4758 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4759 ahci_port_t *ahci_portp, uint8_t port) 4760 { 4761 uint32_t port_cmd_issue = 0; 4762 uint32_t finished_tags; 4763 int finished_slot; 4764 sata_pkt_t *satapkt; 4765 ahci_fis_d2h_register_t *rcvd_fisp; 4766 #if AHCI_DEBUG 4767 ahci_cmd_header_t *cmd_header; 4768 uint32_t cmd_dmacount; 4769 #endif 4770 4771 mutex_enter(&ahci_portp->ahciport_mutex); 4772 4773 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4774 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4775 /* 4776 * Spurious interrupt. Nothing to be done. 4777 */ 4778 mutex_exit(&ahci_portp->ahciport_mutex); 4779 return (AHCI_SUCCESS); 4780 } 4781 4782 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4783 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4784 4785 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4786 /* Slot 0 is always used during error recovery */ 4787 finished_tags = 0x1 & ~port_cmd_issue; 4788 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4789 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4790 "retrieval is finished, and finished_tags = 0x%x", 4791 port, finished_tags); 4792 } else { 4793 finished_tags = ahci_portp->ahciport_pending_tags & 4794 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4795 } 4796 4797 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4798 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4799 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4800 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4801 finished_tags); 4802 4803 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4804 (finished_tags == 0x1)) { 4805 satapkt = ahci_portp->ahciport_err_retri_pkt; 4806 ASSERT(satapkt != NULL); 4807 4808 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4809 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4810 "with SATA_PKT_COMPLETED", (void *)satapkt); 4811 4812 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4813 goto out; 4814 } 4815 4816 while (finished_tags) { 4817 finished_slot = ddi_ffs(finished_tags) - 1; 4818 if (finished_slot == -1) { 4819 goto out; 4820 } 4821 4822 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4823 ASSERT(satapkt != NULL); 4824 #if AHCI_DEBUG 4825 /* 4826 * For non-native queued commands, the PRD byte count field 4827 * shall contain an accurate count of the number of bytes 4828 * transferred for the command before the PxCI bit is cleared 4829 * to '0' for the command. 4830 * 4831 * The purpose of this field is to let software know how many 4832 * bytes transferred for a given operation in order to 4833 * determine if underflow occurred. When issuing native command 4834 * queuing commands, this field should not be used and is not 4835 * required to be valid since in this case underflow is always 4836 * illegal. 4837 * 4838 * For data reads, the HBA will update its PRD byte count with 4839 * the total number of bytes received from the last FIS, and 4840 * may be able to continue normally. For data writes, the 4841 * device will detect an error, and HBA most likely will get 4842 * a fatal error. 4843 * 4844 * Therefore, here just put code to debug part. And please 4845 * refer to the comment above ahci_intr_fatal_error for the 4846 * definition of underflow error. 4847 */ 4848 cmd_dmacount = 4849 ahci_portp->ahciport_prd_bytecounts[finished_slot]; 4850 if (cmd_dmacount) { 4851 cmd_header = 4852 &ahci_portp->ahciport_cmd_list[finished_slot]; 4853 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_PRDT, ahci_ctlp, 4854 "ahci_intr_cmd_cmplt: port %d, " 4855 "PRD Byte Count = 0x%x, " 4856 "ahciport_prd_bytecounts = 0x%x", port, 4857 cmd_header->ahcich_prd_byte_count, 4858 cmd_dmacount); 4859 4860 if (cmd_header->ahcich_prd_byte_count != cmd_dmacount) { 4861 AHCIDBG1(AHCIDBG_UNDERFLOW, ahci_ctlp, 4862 "ahci_intr_cmd_cmplt: port %d, " 4863 "an underflow occurred", port); 4864 } 4865 } 4866 #endif 4867 4868 /* 4869 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4870 * feature, sata_special_regs flag will be set, and the 4871 * driver should copy the status and the other corresponding 4872 * register values in the D2H Register FIS received (It's 4873 * working on Non-data protocol) from the device back to 4874 * the sata_cmd. 4875 * 4876 * For every AHCI port, there is only one Received FIS 4877 * structure, which contains the FISes received from the 4878 * device, So we're trying to copy the content of D2H 4879 * Register FIS in the Received FIS structure back to 4880 * the sata_cmd. 4881 */ 4882 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4883 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4884 ahcirf_d2h_register_fis); 4885 satapkt->satapkt_cmd.satacmd_status_reg = 4886 GET_RFIS_STATUS(rcvd_fisp); 4887 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4888 } 4889 4890 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4891 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4892 "with SATA_PKT_COMPLETED", (void *)satapkt); 4893 4894 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4895 CLEAR_BIT(finished_tags, finished_slot); 4896 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4897 4898 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4899 } 4900 out: 4901 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4902 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4903 ahci_portp->ahciport_pending_tags); 4904 4905 mutex_exit(&ahci_portp->ahciport_mutex); 4906 4907 return (AHCI_SUCCESS); 4908 } 4909 4910 /* 4911 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4912 * with the 'I' bit set and has been copied into system memory. It will 4913 * be sent under the following situations: 4914 * 4915 * 1. NCQ command is completed 4916 * 2. Asynchronous notification 4917 * 4918 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4919 * via the Set Device Bits FIS. When such event is generated, the software 4920 * needs to read PxSACT register and compares the current value to the 4921 * list of commands previously issue by software. ahciport_pending_ncq_tags 4922 * keeps the tags of previously issued commands. 4923 * 4924 * Asynchronous Notification is a feature in SATA II, which allows an 4925 * ATAPI device to send a signal to the host when media is inserted or 4926 * removed and avoids polling the device for media changes. The signal 4927 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4928 * set to '1'. At the moment, it's not supported yet. 4929 */ 4930 static int 4931 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4932 ahci_port_t *ahci_portp, uint8_t port) 4933 { 4934 uint32_t port_sactive; 4935 uint32_t port_cmd_issue; 4936 uint32_t issued_tags; 4937 int issued_slot; 4938 uint32_t finished_tags; 4939 int finished_slot; 4940 sata_pkt_t *satapkt; 4941 4942 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4943 "ahci_intr_set_device_bits enter: port %d", port); 4944 4945 mutex_enter(&ahci_portp->ahciport_mutex); 4946 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4947 mutex_exit(&ahci_portp->ahciport_mutex); 4948 return (AHCI_SUCCESS); 4949 } 4950 4951 /* 4952 * First the handler got which commands are finished by checking 4953 * PxSACT register 4954 */ 4955 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4956 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4957 4958 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4959 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4960 4961 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4962 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4963 "port_sactive = 0x%x", port, 4964 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4965 4966 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4967 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4968 4969 /* 4970 * For NCQ commands, the software can determine which command has 4971 * already been transmitted to the device by checking PxCI register. 4972 */ 4973 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4974 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4975 4976 issued_tags = ahci_portp->ahciport_pending_tags & 4977 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4978 4979 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4980 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4981 "port_cmd_issue = 0x%x", port, 4982 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4983 4984 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4985 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4986 4987 /* 4988 * Clear ahciport_pending_tags bit when the corresponding command 4989 * is already sent down to the device. 4990 */ 4991 while (issued_tags) { 4992 issued_slot = ddi_ffs(issued_tags) - 1; 4993 if (issued_slot == -1) { 4994 goto next; 4995 } 4996 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4997 CLEAR_BIT(issued_tags, issued_slot); 4998 } 4999 5000 next: 5001 while (finished_tags) { 5002 finished_slot = ddi_ffs(finished_tags) - 1; 5003 if (finished_slot == -1) { 5004 goto out; 5005 } 5006 5007 /* The command is certainly transmitted to the device */ 5008 ASSERT(!(ahci_portp->ahciport_pending_tags & 5009 (0x1 << finished_slot))); 5010 5011 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 5012 ASSERT(satapkt != NULL); 5013 5014 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 5015 "ahci_intr_set_device_bits: sending up pkt 0x%p " 5016 "with SATA_PKT_COMPLETED", (void *)satapkt); 5017 5018 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 5019 CLEAR_BIT(finished_tags, finished_slot); 5020 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 5021 5022 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 5023 } 5024 out: 5025 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 5026 "ahci_intr_set_device_bits: port %d " 5027 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 5028 port, ahci_portp->ahciport_pending_ncq_tags, 5029 ahci_portp->ahciport_pending_tags); 5030 5031 mutex_exit(&ahci_portp->ahciport_mutex); 5032 5033 return (AHCI_SUCCESS); 5034 } 5035 5036 /* 5037 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 5038 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 5039 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 5040 * indicates a COMINIT signal was received. 5041 * 5042 * Hot plug insertion is detected by reception of a COMINIT signal from the 5043 * device. On reception of unsolicited COMINIT, the HBA shall generate a 5044 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 5045 * begin the normal communication negotiation sequence as outlined in the 5046 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 5047 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 5048 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 5049 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 5050 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 5051 * to handle hot plug insertion. In this interrupt handler, just do nothing 5052 * but print some log message and clear the bit. 5053 */ 5054 static int 5055 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 5056 ahci_port_t *ahci_portp, uint8_t port) 5057 { 5058 #if AHCI_DEBUG 5059 uint32_t port_serror; 5060 #endif 5061 5062 mutex_enter(&ahci_portp->ahciport_mutex); 5063 5064 #if AHCI_DEBUG 5065 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5066 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5067 5068 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 5069 "ahci_intr_port_connect_change: port %d, " 5070 "port_serror = 0x%x", port, port_serror); 5071 #endif 5072 5073 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 5074 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5075 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5076 SERROR_EXCHANGED_ERR); 5077 5078 mutex_exit(&ahci_portp->ahciport_mutex); 5079 5080 return (AHCI_SUCCESS); 5081 } 5082 5083 /* 5084 * Hot Plug Operation for platforms that support Mechanical Presence 5085 * Switches. 5086 * 5087 * When set, it indicates that a mechanical presence switch attached to this 5088 * port has been opened or closed, which may lead to a change in the connection 5089 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 5090 * are set to '1'. 5091 * 5092 * At the moment, this interrupt is not needed and disabled and we just log 5093 * the debug message. 5094 */ 5095 static int 5096 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 5097 ahci_port_t *ahci_portp, uint8_t port) 5098 { 5099 uint32_t cap_status, port_cmd_status; 5100 5101 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 5102 "ahci_intr_device_mechanical_presence_status enter, " 5103 "port %d", port); 5104 5105 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5106 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 5107 5108 mutex_enter(&ahci_portp->ahciport_mutex); 5109 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5110 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5111 5112 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 5113 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 5114 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 5115 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 5116 "the interrupt: cap_status = 0x%x, " 5117 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 5118 mutex_exit(&ahci_portp->ahciport_mutex); 5119 5120 return (AHCI_SUCCESS); 5121 } 5122 5123 #if AHCI_DEBUG 5124 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 5125 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 5126 "The mechanical presence switch is open: " 5127 "port %d, port_cmd_status = 0x%x", 5128 port, port_cmd_status); 5129 } else { 5130 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 5131 "The mechanical presence switch is close: " 5132 "port %d, port_cmd_status = 0x%x", 5133 port, port_cmd_status); 5134 } 5135 #endif 5136 5137 mutex_exit(&ahci_portp->ahciport_mutex); 5138 5139 return (AHCI_SUCCESS); 5140 } 5141 5142 /* 5143 * Native Hot Plug Support. 5144 * 5145 * When set, it indicates that the internal PHYRDY signal changed state. 5146 * This bit reflects the state of PxSERR.DIAG.N. 5147 * 5148 * There are three kinds of conditions to generate this interrupt event: 5149 * 1. a device is inserted 5150 * 2. a device is disconnected 5151 * 3. when the link enters/exits a Partial or Slumber interface power 5152 * management state 5153 * 5154 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 5155 * bit may be set due to the link entering the Partial or Slumber power 5156 * management state, rather than due to a hot plug insertion or removal 5157 * event. So far, the interface power management is disabled, so the 5158 * driver can reliably get removal detection notification via the 5159 * PxSERR.DIAG.N bit. 5160 */ 5161 static int 5162 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 5163 ahci_port_t *ahci_portp, uint8_t port) 5164 { 5165 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 5166 sata_device_t sdevice; 5167 int dev_exists_now = 0; 5168 int dev_existed_previously = 0; 5169 5170 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 5171 "ahci_intr_phyrdy_change enter, port %d", port); 5172 5173 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 5174 mutex_enter(&ahci_portp->ahciport_mutex); 5175 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5176 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5177 SERROR_PHY_RDY_CHG); 5178 mutex_exit(&ahci_portp->ahciport_mutex); 5179 5180 mutex_enter(&ahci_ctlp->ahcictl_mutex); 5181 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 5182 (ahci_portp == NULL)) { 5183 /* The whole controller setup is not yet done. */ 5184 mutex_exit(&ahci_ctlp->ahcictl_mutex); 5185 return (AHCI_SUCCESS); 5186 } 5187 mutex_exit(&ahci_ctlp->ahcictl_mutex); 5188 5189 mutex_enter(&ahci_portp->ahciport_mutex); 5190 5191 /* SStatus tells the presence of device. */ 5192 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5193 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 5194 5195 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 5196 dev_exists_now = 1; 5197 } 5198 5199 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 5200 dev_existed_previously = 1; 5201 } 5202 5203 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 5204 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 5205 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5206 "ahci_intr_phyrdy_change: port %d " 5207 "AHCI_PORT_FLAG_NODEV is cleared", port); 5208 if (dev_exists_now == 0) 5209 dev_existed_previously = 1; 5210 } 5211 5212 bzero((void *)&sdevice, sizeof (sata_device_t)); 5213 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5214 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5215 sdevice.satadev_addr.pmport = 0; 5216 sdevice.satadev_state = SATA_PSTATE_PWRON; 5217 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 5218 5219 if (dev_exists_now) { 5220 if (dev_existed_previously) { 5221 /* Things are fine now. The loss was temporary. */ 5222 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5223 "ahci_intr_phyrdy_change port %d " 5224 "device link lost/established", port); 5225 5226 mutex_exit(&ahci_portp->ahciport_mutex); 5227 sata_hba_event_notify( 5228 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5229 &sdevice, 5230 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 5231 mutex_enter(&ahci_portp->ahciport_mutex); 5232 5233 } else { 5234 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5235 "ahci_intr_phyrdy_change: port %d " 5236 "device link established", port); 5237 5238 /* A new device has been detected. */ 5239 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 5240 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 5241 5242 /* Try to start the port */ 5243 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 5244 != AHCI_SUCCESS) { 5245 sdevice.satadev_state |= SATA_PSTATE_FAILED; 5246 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5247 "ahci_intr_phyrdy_change: port %d failed " 5248 "at start port", port); 5249 } 5250 5251 /* Clear the max queue depth for inserted device */ 5252 ahci_portp->ahciport_max_ncq_tags = 0; 5253 5254 mutex_exit(&ahci_portp->ahciport_mutex); 5255 sata_hba_event_notify( 5256 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5257 &sdevice, 5258 SATA_EVNT_LINK_ESTABLISHED); 5259 mutex_enter(&ahci_portp->ahciport_mutex); 5260 5261 } 5262 } else { /* No device exists now */ 5263 5264 if (dev_existed_previously) { 5265 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5266 "ahci_intr_phyrdy_change: port %d " 5267 "device link lost", port); 5268 5269 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 5270 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 5271 ahci_portp, port); 5272 5273 /* An existing device is lost. */ 5274 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 5275 5276 mutex_exit(&ahci_portp->ahciport_mutex); 5277 sata_hba_event_notify( 5278 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5279 &sdevice, 5280 SATA_EVNT_LINK_LOST); 5281 mutex_enter(&ahci_portp->ahciport_mutex); 5282 } 5283 } 5284 5285 mutex_exit(&ahci_portp->ahciport_mutex); 5286 5287 return (AHCI_SUCCESS); 5288 } 5289 5290 /* 5291 * PxIS.UFS - Unknown FIS Error 5292 * 5293 * This interrupt event means an unknown FIS was received and has been 5294 * copied into system memory. An unknown FIS is not considered an illegal 5295 * FIS, unless the length received is more than 64 bytes. If an unknown 5296 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 5297 * normal operation. If the unknown FIS is more than 64 bytes, then it 5298 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 5299 * a fatal error. 5300 * 5301 * PxIS.OFS - Overflow Error 5302 * 5303 * Command list overflow is defined as software building a command table 5304 * that has fewer total bytes than the transaction given to the device. 5305 * On device writes, the HBA will run out of data, and on reads, there 5306 * will be no room to put the data. 5307 * 5308 * For an overflow on data read, either PIO or DMA, the HBA will set 5309 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 5310 * non-fatal error when the HBA can continues. Sometimes, it will cause 5311 * a fatal error and need the software to do something. 5312 * 5313 * For an overflow on data write, setting PxIS.OFS is optional for both 5314 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 5315 * software to clean up from this serious error. 5316 * 5317 * PxIS.INFS - Interface Non-Fatal Error 5318 * 5319 * This interrupt event indicates that the HBA encountered an error on 5320 * the Serial ATA interface but was able to continue operation. The kind 5321 * of error usually occurred during a non-Data FIS, and under this condition 5322 * the FIS will be re-transmitted by HBA automatically. 5323 * 5324 * When the FMA is implemented, there should be a stat structure to 5325 * record how many every kind of error happens. 5326 */ 5327 static int 5328 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5329 uint8_t port, uint32_t intr_status) 5330 { 5331 uint32_t port_serror; 5332 #if AHCI_DEBUG 5333 uint32_t port_cmd_status; 5334 uint32_t port_cmd_issue; 5335 uint32_t port_sactive; 5336 int current_slot; 5337 uint32_t current_tags; 5338 sata_pkt_t *satapkt; 5339 ahci_cmd_header_t *cmd_header; 5340 uint32_t cmd_dmacount; 5341 #endif 5342 5343 mutex_enter(&ahci_portp->ahciport_mutex); 5344 5345 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5346 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5347 5348 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 5349 "ahci_intr_non_fatal_error: port %d, " 5350 "port_serror = 0x%x", port, port_serror); 5351 5352 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1); 5353 5354 if (intr_status & AHCI_INTR_STATUS_UFS) { 5355 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5356 "ahci port %d has unknown FIS error", port); 5357 5358 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 5359 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5360 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5361 SERROR_FIS_TYPE); 5362 } 5363 5364 #if AHCI_DEBUG 5365 if (intr_status & AHCI_INTR_STATUS_OFS) { 5366 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5367 "ahci port %d has overflow error", port); 5368 } 5369 5370 if (intr_status & AHCI_INTR_STATUS_INFS) { 5371 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5372 "ahci port %d has interface non fatal error", port); 5373 } 5374 5375 /* 5376 * Record the error occurred command's slot. 5377 */ 5378 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 5379 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5380 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5381 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5382 5383 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5384 AHCI_CMD_STATUS_CCS_SHIFT; 5385 5386 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5387 satapkt = ahci_portp->ahciport_err_retri_pkt; 5388 ASSERT(satapkt != NULL); 5389 ASSERT(current_slot == 0); 5390 } else { 5391 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5392 } 5393 5394 if (satapkt != NULL) { 5395 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5396 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 5397 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 5398 satapkt->satapkt_cmd.satacmd_cmd_reg); 5399 5400 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5401 "ahci_intr_non_fatal_error: port %d, " 5402 "satapkt 0x%p is being processed when error occurs", 5403 port, (void *)satapkt); 5404 5405 /* 5406 * PRD Byte Count field of command header is not 5407 * required to reflect the total number of bytes 5408 * transferred when an overflow occurs, so here 5409 * just log the value. 5410 */ 5411 cmd_dmacount = 5412 ahci_portp->ahciport_prd_bytecounts[current_slot]; 5413 if (cmd_dmacount) { 5414 cmd_header = &ahci_portp-> 5415 ahciport_cmd_list[current_slot]; 5416 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5417 "ahci_intr_non_fatal_error: port %d, " 5418 "PRD Byte Count = 0x%x, " 5419 "ahciport_prd_bytecounts = 0x%x", port, 5420 cmd_header->ahcich_prd_byte_count, 5421 cmd_dmacount); 5422 } 5423 } 5424 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5425 /* 5426 * For queued command, list those command which have already 5427 * been transmitted to the device and still not completed. 5428 */ 5429 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5430 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 5431 5432 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5433 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5434 5435 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 5436 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 5437 "port_sactive = 0x%x port_cmd_issue = 0x%x", 5438 ahci_portp->ahciport_pending_ncq_tags, 5439 port_sactive, port_cmd_issue); 5440 5441 current_tags = ahci_portp->ahciport_pending_ncq_tags & 5442 port_sactive & ~port_cmd_issue & 5443 AHCI_NCQ_SLOT_MASK(ahci_portp); 5444 5445 while (current_tags) { 5446 current_slot = ddi_ffs(current_tags) - 1; 5447 if (current_slot == -1) { 5448 goto out; 5449 } 5450 5451 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5452 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 5453 ahci_ctlp, "ahci_intr_non_fatal_error: " 5454 "port %d, satapkt 0x%p is outstanding when " 5455 "error occurs", port, (void *)satapkt); 5456 5457 CLEAR_BIT(current_tags, current_slot); 5458 } 5459 } 5460 out: 5461 #endif 5462 mutex_exit(&ahci_portp->ahciport_mutex); 5463 5464 return (AHCI_SUCCESS); 5465 } 5466 5467 /* 5468 * According to the AHCI spec, the error types include system memory 5469 * errors, interface errors, port multiplier errors, device errors, 5470 * command list overflow, command list underflow, native command 5471 * queuing tag errors and pio data transfer errors. 5472 * 5473 * System memory errors such as target abort, master abort, and parity 5474 * may cause the host to stop, and they are serious errors and needed 5475 * to be recovered with software intervention. When system software 5476 * has given a pointer to the HBA that doesn't exist in physical memory, 5477 * a master/target abort error occurs, and PxIS.HBFS will be set. A 5478 * data error such as CRC or parity occurs, the HBA aborts the transfer 5479 * (if necessary) and PxIS.HBDS will be set. 5480 * 5481 * Interface errors are errors that occur due to electrical issues on 5482 * the interface, or protocol miscommunication between the device and 5483 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 5484 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 5485 * causes PxIS.IFS/PxIS.INFS to be set are 5486 * 1. in PxSERR.ERR, P bit is set to '1' 5487 * 2. in PxSERR.DIAG, C or H bit is set to '1' 5488 * 3. PhyRdy drop unexpectly, N bit is set to '1' 5489 * If the error occurred during a non-data FIS, the FIS must be 5490 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 5491 * the error occurred during a data FIS, the transfer will stop, so 5492 * the error is fatal and PxIS.IFS is set. 5493 * 5494 * When a FIS arrives that updates the taskfile, the HBA checks to see 5495 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 5496 * stops processing any more commands. 5497 * 5498 * Command list overflow is defined as software building a command table 5499 * that has fewer total bytes than the transaction given to the device. 5500 * On device writes, the HBA will run out of data, and on reads, there 5501 * will be no room to put the data. For an overflow on data read, either 5502 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 5503 * For an overflow on data write, setting PxIS.OFS is optional for both 5504 * DMA and PIO, and a COMRESET is required by software to clean up from 5505 * this serious error. 5506 * 5507 * Command list underflow is defined as software building a command 5508 * table that has more total bytes than the transaction given to the 5509 * device. For data writes, both PIO and DMA, the device will detect 5510 * an error and end the transfer. And these errors are most likely going 5511 * to be fatal errors that will cause the port to be restarted. For 5512 * data reads, the HBA updates its PRD byte count, and may be 5513 * able to continue normally, but is not required to. And The HBA is 5514 * not required to detect underflow conditions for native command 5515 * queuing command. 5516 * 5517 * The HBA does not actively check incoming DMA Setup FISes to ensure 5518 * that the PxSACT register bit for that slot is set. Existing error 5519 * mechanisms, such as host bus failure, or bad protocol, are used to 5520 * recover from this case. 5521 * 5522 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 5523 * DATA FIS must be an integral number of Dwords. If the HBA receives 5524 * a request which is not an integral number of Dwords, the HBA 5525 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 5526 * software restarts the port. And the HBA ensures that the size 5527 * of the DATA FIS received during a PIO command matches the size in 5528 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 5529 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 5530 * stop running until software restarts the port. 5531 */ 5532 /* 5533 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 5534 * 5535 * PxIS.IFS indicates that the hba encountered an error on the serial ata 5536 * interface which caused the transfer to stop. 5537 * 5538 * PxIS.HBDS indicates that the hba encountered a data error 5539 * (uncorrectable ecc/parity) when reading from or writing to system memory. 5540 * 5541 * PxIS.HBFS indicates that the hba encountered a host bus error that it 5542 * cannot recover from, such as a bad software pointer. 5543 * 5544 * PxIS.TFES is set whenever the status register is updated by the device 5545 * and the error bit (bit 0) is set. 5546 */ 5547 static int 5548 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 5549 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 5550 { 5551 uint32_t port_cmd_status; 5552 uint32_t port_serror; 5553 uint32_t task_file_status; 5554 int failed_slot; 5555 sata_pkt_t *spkt = NULL; 5556 uint8_t err_byte; 5557 ahci_event_arg_t *args; 5558 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 5559 5560 mutex_enter(&ahci_portp->ahciport_mutex); 5561 5562 /* 5563 * ahci_intr_phyrdy_change() may have rendered it to 5564 * SATA_DTYPE_NONE. 5565 */ 5566 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5567 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5568 "ahci_intr_fatal_error: port %d no device attached, " 5569 "and just return without doing anything", port); 5570 goto out0; 5571 } 5572 5573 if (intr_status & AHCI_INTR_STATUS_TFES) { 5574 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5575 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5576 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5577 "ahci_intr_fatal_error: port %d " 5578 "task_file_status = 0x%x", port, task_file_status); 5579 } 5580 5581 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5582 /* 5583 * Read PxCMD.CCS to determine the slot that the HBA 5584 * was processing when the error occurred. 5585 */ 5586 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5587 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5588 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5589 AHCI_CMD_STATUS_CCS_SHIFT; 5590 5591 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5592 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5593 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5594 "fatal error occurred for port %d", spkt, port); 5595 5596 if (intr_status & AHCI_INTR_STATUS_TFES) { 5597 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5598 >> AHCI_TFD_ERR_SHIFT; 5599 5600 /* 5601 * Won't emit the error message if it is an IDENTIFY 5602 * DEVICE command sent to an ATAPI device. 5603 */ 5604 if ((spkt != NULL) && 5605 (spkt->satapkt_cmd.satacmd_cmd_reg == 5606 SATAC_ID_DEVICE) && 5607 (err_byte == SATA_ERROR_ABORT)) 5608 goto out1; 5609 5610 /* 5611 * Won't emit the error message if it is an ATAPI PACKET 5612 * command 5613 */ 5614 if ((spkt != NULL) && 5615 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5616 goto out1; 5617 } 5618 } 5619 5620 /* print the fatal error type */ 5621 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5622 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5623 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5624 5625 /* print PxSERR related error message */ 5626 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0); 5627 5628 /* print task file register value */ 5629 if (intr_status & AHCI_INTR_STATUS_TFES) { 5630 cmn_err(CE_WARN, "!ahci%d: ahci port %d task_file_status " 5631 "= 0x%x", instance, port, task_file_status); 5632 } 5633 5634 out1: 5635 /* Prepare the argument for the taskq */ 5636 args = ahci_portp->ahciport_event_args; 5637 args->ahciea_ctlp = (void *)ahci_ctlp; 5638 args->ahciea_portp = (void *)ahci_portp; 5639 args->ahciea_event = intr_status; 5640 5641 /* Start the taskq to handle error recovery */ 5642 if ((ddi_taskq_dispatch(ahci_portp->ahciport_event_taskq, 5643 ahci_events_handler, 5644 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5645 cmn_err(CE_WARN, "!ahci%d: ahci start taskq for event handler " 5646 "failed", instance); 5647 } 5648 out0: 5649 mutex_exit(&ahci_portp->ahciport_mutex); 5650 5651 return (AHCI_SUCCESS); 5652 } 5653 5654 /* 5655 * Hot Plug Operation for platforms that support Cold Presence Detect. 5656 * 5657 * When set, a device status has changed as detected by the cold presence 5658 * detect logic. This bit can either be set due to a non-connected port 5659 * receiving a device, or a connected port having its device removed. 5660 * This bit is only valid if the port supports cold presence detect as 5661 * indicated by PxCMD.CPD set to '1'. 5662 * 5663 * At the moment, this interrupt is not needed and disabled and we just 5664 * log the debug message. 5665 */ 5666 static int 5667 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5668 ahci_port_t *ahci_portp, uint8_t port) 5669 { 5670 uint32_t port_cmd_status; 5671 sata_device_t sdevice; 5672 5673 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5674 "ahci_intr_cold_port_detect enter, port %d", port); 5675 5676 mutex_enter(&ahci_portp->ahciport_mutex); 5677 5678 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5679 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5680 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5681 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5682 "port %d does not support cold presence detect, so " 5683 "we just ignore this interrupt", port); 5684 mutex_exit(&ahci_portp->ahciport_mutex); 5685 return (AHCI_SUCCESS); 5686 } 5687 5688 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5689 "port %d device status has changed", port); 5690 5691 bzero((void *)&sdevice, sizeof (sata_device_t)); 5692 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5693 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5694 sdevice.satadev_addr.pmport = 0; 5695 sdevice.satadev_state = SATA_PSTATE_PWRON; 5696 5697 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5698 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5699 "port %d: a device is hot plugged", port); 5700 mutex_exit(&ahci_portp->ahciport_mutex); 5701 sata_hba_event_notify( 5702 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5703 &sdevice, 5704 SATA_EVNT_DEVICE_ATTACHED); 5705 mutex_enter(&ahci_portp->ahciport_mutex); 5706 5707 } else { 5708 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5709 "port %d: a device is hot unplugged", port); 5710 mutex_exit(&ahci_portp->ahciport_mutex); 5711 sata_hba_event_notify( 5712 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5713 &sdevice, 5714 SATA_EVNT_DEVICE_DETACHED); 5715 mutex_enter(&ahci_portp->ahciport_mutex); 5716 } 5717 5718 mutex_exit(&ahci_portp->ahciport_mutex); 5719 5720 return (AHCI_SUCCESS); 5721 } 5722 5723 /* 5724 * Enable the interrupts for a particular port. 5725 * 5726 * WARNING!!! ahciport_mutex should be acquired before the function 5727 * is called. 5728 */ 5729 static void 5730 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5731 { 5732 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5733 "ahci_enable_port_intrs enter, port %d", port); 5734 5735 /* 5736 * Clear port interrupt status before enabling interrupt 5737 */ 5738 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5739 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5740 AHCI_PORT_INTR_MASK); 5741 5742 /* 5743 * Clear the pending bit from IS.IPS 5744 */ 5745 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5746 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5747 5748 /* 5749 * Enable the following interrupts: 5750 * Device to Host Register FIS Interrupt (DHRS) 5751 * PIO Setup FIS Interrupt (PSS) 5752 * Set Device Bits Interrupt (SDBS) 5753 * Unknown FIS Interrupt (UFS) 5754 * Port Connect Change Status (PCS) 5755 * PhyRdy Change Status (PRCS) 5756 * Overflow Status (OFS) 5757 * Interface Non-fatal Error Status (INFS) 5758 * Interface Fatal Error Status (IFS) 5759 * Host Bus Data Error Status (HBDS) 5760 * Host Bus Fatal Error Status (HBFS) 5761 * Task File Error Status (TFES) 5762 */ 5763 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5764 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5765 (AHCI_INTR_STATUS_DHRS | 5766 AHCI_INTR_STATUS_PSS | 5767 AHCI_INTR_STATUS_SDBS | 5768 AHCI_INTR_STATUS_UFS | 5769 AHCI_INTR_STATUS_DPS | 5770 AHCI_INTR_STATUS_PCS | 5771 AHCI_INTR_STATUS_PRCS | 5772 AHCI_INTR_STATUS_OFS | 5773 AHCI_INTR_STATUS_INFS | 5774 AHCI_INTR_STATUS_IFS | 5775 AHCI_INTR_STATUS_HBDS | 5776 AHCI_INTR_STATUS_HBFS | 5777 AHCI_INTR_STATUS_TFES)); 5778 } 5779 5780 /* 5781 * Enable interrupts for all the ports. 5782 * 5783 * WARNING!!! ahcictl_mutex should be acquired before the function 5784 * is called. 5785 */ 5786 static void 5787 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5788 { 5789 uint32_t ghc_control; 5790 5791 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5792 5793 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5794 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5795 5796 ghc_control |= AHCI_HBA_GHC_IE; 5797 5798 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5799 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5800 } 5801 5802 /* 5803 * Disable interrupts for a particular port. 5804 * 5805 * WARNING!!! ahciport_mutex should be acquired before the function 5806 * is called. 5807 */ 5808 static void 5809 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5810 { 5811 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5812 "ahci_disable_port_intrs enter, port %d", port); 5813 5814 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5815 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5816 } 5817 5818 /* 5819 * Disable interrupts for the whole HBA. 5820 * 5821 * The global bit is cleared, then all interrupt sources from all 5822 * ports are disabled. 5823 * 5824 * WARNING!!! ahcictl_mutex should be acquired before the function 5825 * is called. 5826 */ 5827 static void 5828 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5829 { 5830 uint32_t ghc_control; 5831 5832 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5833 5834 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5835 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5836 5837 ghc_control &= ~ AHCI_HBA_GHC_IE; 5838 5839 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5840 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5841 } 5842 5843 /* 5844 * Handle FIXED or MSI interrupts. 5845 */ 5846 /* 5847 * According to AHCI spec, the HBA may support several interrupt modes: 5848 * * pin based interrupts (FIXED) 5849 * * single MSI message interrupts 5850 * * multiple MSI based message interrupts 5851 * 5852 * For pin based interrupts, the software interrupt handler need to check IS 5853 * register to find out which port has pending interrupts. And then check 5854 * PxIS register to find out which interrupt events happened on that port. 5855 * 5856 * For single MSI message interrupts, MSICAP.MC.MSIE is set with '1', and 5857 * MSICAP.MC.MME is set with '0'. This mode is similar to pin based interrupts 5858 * in that software interrupt handler need to check IS register to determine 5859 * which port triggered the interrupts since it uses a single message for all 5860 * port interrupts. 5861 * 5862 * HBA may optionally support multiple MSI message for better performance. In 5863 * this mode, each port may have its own interrupt message, and thus generation 5864 * of interrupts is no longer controlled through the IS register. MSICAP.MC.MMC 5865 * represents a power-of-2 wrapper on the number of implemented ports, and 5866 * the mapping of ports to interrupts is done in a 1-1 relationship, up to the 5867 * maximum number of assigned interrupts. When the number of MSI messages 5868 * allocated is less than the number requested, then hardware may have two 5869 * implementation behaviors: 5870 * * assign each ports its own interrupt and then force all additional 5871 * ports to share the last interrupt message, and this condition is 5872 * indicated by clearing GHC.MRSM to '0' 5873 * * revert to single MSI mode, indicated by setting GHC.MRSM to '1' 5874 * When multiple-message MSI is enabled, hardware will still set IS register 5875 * as single message case. And this IS register may be used by software when 5876 * fewer than the requested number of messages is granted in order to determine 5877 * which port had the interrupt. 5878 * 5879 * Note: The current ahci driver only supports the first two interrupt modes: 5880 * pin based interrupts and single MSI message interrupts, and the reason 5881 * is indicated in below code. 5882 */ 5883 static int 5884 ahci_add_intrs(ahci_ctl_t *ahci_ctlp, int intr_type) 5885 { 5886 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5887 int count, avail, actual; 5888 int i, rc; 5889 5890 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 5891 "ahci_add_intrs enter interrupt type 0x%x", intr_type); 5892 5893 /* get number of interrupts. */ 5894 rc = ddi_intr_get_nintrs(dip, intr_type, &count); 5895 if ((rc != DDI_SUCCESS) || (count == 0)) { 5896 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5897 "ddi_intr_get_nintrs() failed, " 5898 "rc %d count %d\n", rc, count); 5899 return (DDI_FAILURE); 5900 } 5901 5902 /* get number of available interrupts. */ 5903 rc = ddi_intr_get_navail(dip, intr_type, &avail); 5904 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5905 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5906 "ddi_intr_get_navail() failed, " 5907 "rc %d avail %d\n", rc, avail); 5908 return (DDI_FAILURE); 5909 } 5910 5911 #if AHCI_DEBUG 5912 if (avail < count) { 5913 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5914 "ddi_intr_get_nintrs returned %d, navail() returned %d", 5915 count, avail); 5916 } 5917 #endif 5918 5919 /* 5920 * Note: So far Solaris restricts the maximum number of messages for 5921 * x86 to 2, that is avail is 2, so here we set the count with 1 to 5922 * force the driver to use single MSI message interrupt. In future if 5923 * Solaris remove the restriction, then we need to delete the below 5924 * code and try to use multiple interrupt routine to gain better 5925 * performance. 5926 */ 5927 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 5928 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5929 "force to use one interrupt routine though the " 5930 "HBA supports %d interrupt", count); 5931 count = 1; 5932 } 5933 5934 /* Allocate an array of interrupt handles. */ 5935 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5936 ahci_ctlp->ahcictl_intr_htable = 5937 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5938 5939 /* call ddi_intr_alloc(). */ 5940 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5941 intr_type, 0, count, &actual, DDI_INTR_ALLOC_NORMAL); 5942 5943 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5944 AHCIDBG4(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5945 "ddi_intr_alloc() failed, rc %d count %d actual %d " 5946 "avail %d\n", rc, count, actual, avail); 5947 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5948 ahci_ctlp->ahcictl_intr_size); 5949 return (DDI_FAILURE); 5950 } 5951 5952 /* use interrupt count returned */ 5953 #if AHCI_DEBUG 5954 if (actual < count) { 5955 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5956 "Requested: %d, Received: %d", count, actual); 5957 } 5958 #endif 5959 5960 ahci_ctlp->ahcictl_intr_cnt = actual; 5961 5962 /* 5963 * Get priority for first, assume remaining are all the same. 5964 */ 5965 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5966 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5967 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5968 "ddi_intr_get_pri() failed"); 5969 5970 /* Free already allocated intr. */ 5971 for (i = 0; i < actual; i++) { 5972 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]); 5973 } 5974 5975 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5976 ahci_ctlp->ahcictl_intr_size); 5977 return (DDI_FAILURE); 5978 } 5979 5980 /* Test for high level interrupt. */ 5981 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5982 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5983 "ahci_add_intrs: Hi level intr not supported"); 5984 5985 /* Free already allocated intr. */ 5986 for (i = 0; i < actual; i++) { 5987 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[i]); 5988 } 5989 5990 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5991 sizeof (ddi_intr_handle_t)); 5992 5993 return (DDI_FAILURE); 5994 } 5995 5996 /* Call ddi_intr_add_handler(). */ 5997 for (i = 0; i < actual; i++) { 5998 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[i], 5999 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 6000 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 6001 "ddi_intr_add_handler() failed"); 6002 6003 /* Free already allocated intr. */ 6004 for (i = 0; i < actual; i++) { 6005 (void) ddi_intr_free( 6006 ahci_ctlp->ahcictl_intr_htable[i]); 6007 } 6008 6009 kmem_free(ahci_ctlp->ahcictl_intr_htable, 6010 ahci_ctlp->ahcictl_intr_size); 6011 return (DDI_FAILURE); 6012 } 6013 } 6014 6015 if (ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 6016 &ahci_ctlp->ahcictl_intr_cap) != DDI_SUCCESS) { 6017 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 6018 "ddi_intr_get_cap() failed"); 6019 6020 /* Free already allocated intr. */ 6021 for (i = 0; i < actual; i++) { 6022 (void) ddi_intr_free( 6023 ahci_ctlp->ahcictl_intr_htable[i]); 6024 } 6025 6026 kmem_free(ahci_ctlp->ahcictl_intr_htable, 6027 ahci_ctlp->ahcictl_intr_size); 6028 return (DDI_FAILURE); 6029 } 6030 6031 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 6032 /* Call ddi_intr_block_enable() for MSI. */ 6033 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 6034 ahci_ctlp->ahcictl_intr_cnt); 6035 } else { 6036 /* Call ddi_intr_enable() for FIXED or MSI non block enable. */ 6037 for (i = 0; i < ahci_ctlp->ahcictl_intr_cnt; i++) { 6038 (void) ddi_intr_enable( 6039 ahci_ctlp->ahcictl_intr_htable[i]); 6040 } 6041 } 6042 6043 return (DDI_SUCCESS); 6044 } 6045 6046 /* 6047 * Removes the registered interrupts irrespective of whether they 6048 * were legacy or MSI. 6049 * 6050 * WARNING!!! The controller interrupts must be disabled before calling 6051 * this routine. 6052 */ 6053 static void 6054 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 6055 { 6056 int x; 6057 6058 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 6059 6060 /* Disable all interrupts. */ 6061 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 6062 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 6063 /* Call ddi_intr_block_disable(). */ 6064 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 6065 ahci_ctlp->ahcictl_intr_cnt); 6066 } else { 6067 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 6068 (void) ddi_intr_disable( 6069 ahci_ctlp->ahcictl_intr_htable[x]); 6070 } 6071 } 6072 6073 /* Call ddi_intr_remove_handler(). */ 6074 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 6075 (void) ddi_intr_remove_handler( 6076 ahci_ctlp->ahcictl_intr_htable[x]); 6077 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 6078 } 6079 6080 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 6081 } 6082 6083 /* 6084 * This routine tries to put port into P:NotRunning state by clearing 6085 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 6086 * and PxCMD.CR to '0'. 6087 * 6088 * WARNING!!! ahciport_mutex should be acquired before the function 6089 * is called. 6090 */ 6091 static int 6092 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 6093 ahci_port_t *ahci_portp, uint8_t port) 6094 { 6095 uint32_t port_cmd_status; 6096 int loop_count; 6097 6098 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6099 "ahci_put_port_into_notrunning_state enter: port %d", port); 6100 6101 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6102 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6103 6104 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 6105 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6106 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 6107 6108 /* Wait until PxCMD.CR is cleared */ 6109 loop_count = 0; 6110 do { 6111 port_cmd_status = 6112 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6113 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6114 6115 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 6116 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 6117 "clearing port %d CMD.CR timeout, " 6118 "port_cmd_status = 0x%x", port, 6119 port_cmd_status); 6120 /* 6121 * We are effectively timing out after 0.5 sec. 6122 * This value is specified in AHCI spec. 6123 */ 6124 break; 6125 } 6126 6127 /* Wait for 10 millisec */ 6128 drv_usecwait(10000); 6129 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 6130 6131 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 6132 6133 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 6134 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 6135 "ahci_put_port_into_notrunning_state: failed to clear " 6136 "PxCMD.CR to '0' after loop count: %d, and " 6137 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 6138 return (AHCI_FAILURE); 6139 } else { 6140 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 6141 "ahci_put_port_into_notrunning_state: succeeded to clear " 6142 "PxCMD.CR to '0' after loop count: %d, and " 6143 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 6144 return (AHCI_SUCCESS); 6145 } 6146 } 6147 6148 /* 6149 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 6150 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 6151 * stable state, then set PxCMD.ST to '1' to start the port directly. 6152 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 6153 * COMRESET to the device to put it in an idle state. 6154 * 6155 * The fifth argument returns whether the port reset is involved during 6156 * the process. 6157 * 6158 * The routine will be called under following scenarios: 6159 * + To abort the packet(s) 6160 * + To reset the port 6161 * + To activate the port 6162 * + Fatal error recovery 6163 * + To abort the timeout packet(s) 6164 * 6165 * WARNING!!! ahciport_mutex should be acquired before the function 6166 * is called. And ahciport_mutex will be released before the reset 6167 * event is reported to sata module by calling sata_hba_event_notify, 6168 * and then be acquired again later. 6169 * 6170 * NOTES!!! During this procedure, PxSERR register will be cleared, and 6171 * according to the spec, the clearance of three bits will also clear 6172 * three interrupt status bits. 6173 * 1. PxSERR.DIAG.F will clear PxIS.UFS 6174 * 2. PxSERR.DIAG.X will clear PxIS.PCS 6175 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 6176 * 6177 * Among these three interrupt events, the driver needs to take care of 6178 * PxIS.PRCS, which is the hot plug event. When the driver found out 6179 * a device was unplugged, it will call the interrupt handler. 6180 */ 6181 static int 6182 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 6183 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 6184 { 6185 uint32_t port_sstatus; 6186 uint32_t task_file_status; 6187 sata_device_t sdevice; 6188 int rval; 6189 int dev_exists_begin = 0; 6190 int dev_exists_end = 0; 6191 6192 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6193 "ahci_restart_port_wait_till_ready: port %d enter", port); 6194 6195 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) 6196 dev_exists_begin = 1; 6197 6198 /* First clear PxCMD.ST */ 6199 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 6200 port); 6201 if (rval != AHCI_SUCCESS) 6202 /* 6203 * If PxCMD.CR does not clear within a reasonable time, it 6204 * may assume the interface is in a hung condition and may 6205 * continue with issuing the port reset. 6206 */ 6207 goto reset; 6208 6209 /* Then clear PxSERR */ 6210 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6211 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 6212 AHCI_SERROR_CLEAR_ALL); 6213 6214 /* Then get PxTFD */ 6215 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6216 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 6217 6218 /* 6219 * Check whether the device is in a stable status, if yes, 6220 * then start the port directly. However for ahci_tran_dport_reset, 6221 * we may have to perform a port reset. 6222 */ 6223 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 6224 !(flag & AHCI_PORT_RESET)) 6225 goto out; 6226 6227 reset: 6228 /* 6229 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 6230 * a COMRESET to the device 6231 */ 6232 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 6233 6234 if (reset_flag != NULL) 6235 *reset_flag = 1; 6236 6237 /* Indicate to the framework that a reset has happened. */ 6238 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 6239 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 6240 /* Set the reset in progress flag */ 6241 ahci_portp->ahciport_reset_in_progress = 1; 6242 6243 bzero((void *)&sdevice, sizeof (sata_device_t)); 6244 sdevice.satadev_addr.cport = 6245 ahci_ctlp->ahcictl_port_to_cport[port]; 6246 sdevice.satadev_addr.pmport = 0; 6247 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6248 6249 sdevice.satadev_state = SATA_DSTATE_RESET | 6250 SATA_DSTATE_PWR_ACTIVE; 6251 if (ahci_ctlp->ahcictl_sata_hba_tran) { 6252 mutex_exit(&ahci_portp->ahciport_mutex); 6253 sata_hba_event_notify( 6254 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 6255 &sdevice, 6256 SATA_EVNT_DEVICE_RESET); 6257 mutex_enter(&ahci_portp->ahciport_mutex); 6258 } 6259 6260 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 6261 "port %d sending event up: SATA_EVNT_RESET", port); 6262 } else { 6263 ahci_portp->ahciport_reset_in_progress = 0; 6264 } 6265 6266 out: 6267 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 6268 6269 /* SStatus tells the presence of device. */ 6270 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6271 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 6272 6273 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 6274 dev_exists_end = 1; 6275 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 6276 } 6277 6278 /* Check whether a hot plug event happened */ 6279 if (dev_exists_begin == 1 && dev_exists_end == 0) { 6280 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6281 "ahci_restart_port_wait_till_ready: port %d " 6282 "device is removed", port); 6283 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 6284 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6285 "ahci_restart_port_wait_till_ready: port %d " 6286 "AHCI_PORT_FLAG_NODEV flag is set", port); 6287 mutex_exit(&ahci_portp->ahciport_mutex); 6288 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 6289 mutex_enter(&ahci_portp->ahciport_mutex); 6290 } 6291 6292 return (rval); 6293 } 6294 6295 /* 6296 * This routine may be called under four scenarios: 6297 * a) do the recovery from fatal error 6298 * b) or we need to timeout some commands 6299 * c) or we need to abort some commands 6300 * d) or we need reset device/port/controller 6301 * 6302 * In all these scenarios, we need to send any pending unfinished 6303 * commands up to sata framework. 6304 * 6305 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6306 */ 6307 static void 6308 ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 6309 ahci_port_t *ahci_portp, 6310 uint32_t slot_status, 6311 uint32_t failed_tags, 6312 uint32_t timeout_tags, 6313 uint32_t aborted_tags, 6314 uint32_t reset_tags) 6315 { 6316 uint32_t finished_tags = 0; 6317 uint32_t unfinished_tags = 0; 6318 int tmp_slot; 6319 sata_pkt_t *satapkt; 6320 int ncq_cmd_in_progress = 0; 6321 int err_retri_cmd_in_progress = 0; 6322 6323 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6324 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 6325 ahci_portp->ahciport_port_num, slot_status); 6326 6327 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6328 "ahci_mop_commands: failed_tags: 0x%x, " 6329 "timeout_tags: 0x%x aborted_tags: 0x%x, " 6330 "reset_tags: 0x%x", failed_tags, 6331 timeout_tags, aborted_tags, reset_tags); 6332 6333 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6334 finished_tags = ahci_portp->ahciport_pending_tags & 6335 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6336 6337 unfinished_tags = slot_status & 6338 AHCI_SLOT_MASK(ahci_ctlp) & 6339 ~failed_tags & 6340 ~aborted_tags & 6341 ~reset_tags & 6342 ~timeout_tags; 6343 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6344 ncq_cmd_in_progress = 1; 6345 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6346 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6347 6348 unfinished_tags = slot_status & 6349 AHCI_NCQ_SLOT_MASK(ahci_portp) & 6350 ~failed_tags & 6351 ~aborted_tags & 6352 ~reset_tags & 6353 ~timeout_tags; 6354 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6355 6356 /* 6357 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is 6358 * set, it means REQUEST SENSE or READ LOG EXT command doesn't 6359 * complete successfully due to one of the following three 6360 * conditions: 6361 * 6362 * 1. Fatal error - failed_tags includes its slot 6363 * 2. Timed out - timeout_tags includes its slot 6364 * 3. Aborted when hot unplug - aborted_tags includes its 6365 * slot 6366 * 6367 * Please note that the command is always sent down in Slot 0 6368 */ 6369 err_retri_cmd_in_progress = 1; 6370 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 6371 "ahci_mop_commands is called for port %d while " 6372 "REQUEST SENSE or READ LOG EXT for error retrieval " 6373 "is being executed slot_status = 0x%x", 6374 ahci_portp->ahciport_port_num, slot_status); 6375 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 6376 ASSERT(slot_status == 0x1); 6377 } 6378 6379 /* Send up finished packets with SATA_PKT_COMPLETED */ 6380 while (finished_tags) { 6381 tmp_slot = ddi_ffs(finished_tags) - 1; 6382 if (tmp_slot == -1) { 6383 break; 6384 } 6385 6386 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6387 ASSERT(satapkt != NULL); 6388 6389 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 6390 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 6391 (void *)satapkt); 6392 6393 /* 6394 * Cannot fetch the return register content since the port 6395 * was restarted, so the corresponding tag will be set to 6396 * aborted tags. 6397 */ 6398 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6399 CLEAR_BIT(finished_tags, tmp_slot); 6400 aborted_tags |= tmp_slot; 6401 continue; 6402 } 6403 6404 if (ncq_cmd_in_progress) 6405 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6406 tmp_slot); 6407 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6408 CLEAR_BIT(finished_tags, tmp_slot); 6409 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6410 6411 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6412 } 6413 6414 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 6415 while (failed_tags) { 6416 if (err_retri_cmd_in_progress) { 6417 satapkt = ahci_portp->ahciport_err_retri_pkt; 6418 ASSERT(satapkt != NULL); 6419 ASSERT(failed_tags == 0x1); 6420 6421 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6422 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6423 (void *)satapkt); 6424 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6425 break; 6426 } 6427 6428 tmp_slot = ddi_ffs(failed_tags) - 1; 6429 if (tmp_slot == -1) { 6430 break; 6431 } 6432 6433 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6434 ASSERT(satapkt != NULL); 6435 6436 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6437 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6438 (void *)satapkt); 6439 6440 if (ncq_cmd_in_progress) 6441 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6442 tmp_slot); 6443 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6444 CLEAR_BIT(failed_tags, tmp_slot); 6445 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6446 6447 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6448 } 6449 6450 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 6451 while (timeout_tags) { 6452 if (err_retri_cmd_in_progress) { 6453 satapkt = ahci_portp->ahciport_err_retri_pkt; 6454 ASSERT(satapkt != NULL); 6455 ASSERT(timeout_tags == 0x1); 6456 6457 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6458 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6459 (void *)satapkt); 6460 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6461 break; 6462 } 6463 6464 tmp_slot = ddi_ffs(timeout_tags) - 1; 6465 if (tmp_slot == -1) { 6466 break; 6467 } 6468 6469 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6470 ASSERT(satapkt != NULL); 6471 6472 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6473 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6474 (void *)satapkt); 6475 6476 if (ncq_cmd_in_progress) 6477 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6478 tmp_slot); 6479 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6480 CLEAR_BIT(timeout_tags, tmp_slot); 6481 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6482 6483 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6484 } 6485 6486 /* Send up aborted packets with SATA_PKT_ABORTED */ 6487 while (aborted_tags) { 6488 if (err_retri_cmd_in_progress) { 6489 satapkt = ahci_portp->ahciport_err_retri_pkt; 6490 ASSERT(satapkt != NULL); 6491 ASSERT(aborted_tags == 0x1); 6492 6493 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6494 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6495 (void *)satapkt); 6496 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6497 break; 6498 } 6499 6500 tmp_slot = ddi_ffs(aborted_tags) - 1; 6501 if (tmp_slot == -1) { 6502 break; 6503 } 6504 6505 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6506 ASSERT(satapkt != NULL); 6507 6508 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6509 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6510 (void *)satapkt); 6511 6512 if (ncq_cmd_in_progress) 6513 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6514 tmp_slot); 6515 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6516 CLEAR_BIT(aborted_tags, tmp_slot); 6517 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6518 6519 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6520 } 6521 6522 /* Send up reset packets with SATA_PKT_RESET. */ 6523 while (reset_tags) { 6524 tmp_slot = ddi_ffs(reset_tags) - 1; 6525 if (tmp_slot == -1) { 6526 break; 6527 } 6528 6529 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6530 ASSERT(satapkt != NULL); 6531 6532 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6533 "sending up pkt 0x%p with SATA_PKT_RESET", 6534 (void *)satapkt); 6535 6536 if (ncq_cmd_in_progress) 6537 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6538 tmp_slot); 6539 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6540 CLEAR_BIT(reset_tags, tmp_slot); 6541 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6542 6543 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6544 } 6545 6546 /* Send up unfinished packets with SATA_PKT_RESET */ 6547 while (unfinished_tags) { 6548 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6549 if (tmp_slot == -1) { 6550 break; 6551 } 6552 6553 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6554 ASSERT(satapkt != NULL); 6555 6556 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6557 "sending up pkt 0x%p with SATA_PKT_RESET", 6558 (void *)satapkt); 6559 6560 if (ncq_cmd_in_progress) 6561 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6562 tmp_slot); 6563 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6564 CLEAR_BIT(unfinished_tags, tmp_slot); 6565 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6566 6567 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6568 } 6569 6570 ahci_portp->ahciport_mop_in_progress--; 6571 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6572 6573 if (ahci_portp->ahciport_mop_in_progress == 0) 6574 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6575 } 6576 6577 /* 6578 * This routine is going to first request a READ LOG EXT sata pkt from sata 6579 * module, and then deliver it to the HBA to get the ncq failure context. 6580 * The return value is the exactly failed tags. 6581 */ 6582 static uint32_t 6583 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6584 uint8_t port) 6585 { 6586 sata_device_t sdevice; 6587 sata_pkt_t *rdlog_spkt, *spkt; 6588 ddi_dma_handle_t buf_dma_handle; 6589 int loop_count; 6590 int rval; 6591 int failed_slot; 6592 uint32_t failed_tags = 0; 6593 struct sata_ncq_error_recovery_page *ncq_err_page; 6594 6595 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6596 "ahci_get_rdlogext_data enter: port %d", port); 6597 6598 /* Prepare the sdevice data */ 6599 bzero((void *)&sdevice, sizeof (sata_device_t)); 6600 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6601 6602 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6603 sdevice.satadev_addr.pmport = 0; 6604 6605 /* 6606 * Call the sata hba interface to get a rdlog spkt 6607 */ 6608 loop_count = 0; 6609 loop: 6610 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6611 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6612 if (rdlog_spkt == NULL) { 6613 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6614 /* Sleep for a while */ 6615 delay(AHCI_10MS_TICKS); 6616 goto loop; 6617 } 6618 /* Timed out after 1s */ 6619 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6620 "failed to get rdlog spkt for port %d", port); 6621 return (failed_tags); 6622 } 6623 6624 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6625 6626 /* 6627 * This flag is used to handle the specific error recovery when the 6628 * READ LOG EXT command gets a failure (fatal error or time-out). 6629 */ 6630 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6631 6632 /* 6633 * This start is not supposed to fail because after port is restarted, 6634 * the whole command list is empty. 6635 */ 6636 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6637 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6638 ahci_portp->ahciport_err_retri_pkt = NULL; 6639 6640 /* Remove the flag after READ LOG EXT command is completed */ 6641 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6642 6643 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6644 /* Update the request log data */ 6645 buf_dma_handle = *(ddi_dma_handle_t *) 6646 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6647 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6648 DDI_DMA_SYNC_FORKERNEL); 6649 if (rval == DDI_SUCCESS) { 6650 ncq_err_page = 6651 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6652 satapkt_cmd.satacmd_bp->b_un.b_addr; 6653 6654 /* Get the failed tag */ 6655 failed_slot = ncq_err_page->ncq_tag; 6656 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6657 "ahci_get_rdlogext_data: port %d " 6658 "failed slot %d", port, failed_slot); 6659 if (failed_slot & NQ) { 6660 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6661 "the failed slot is not a valid tag"); 6662 goto out; 6663 } 6664 6665 failed_slot &= NCQ_TAG_MASK; 6666 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6667 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6668 "ahci_get_rdlogext_data: failed spkt 0x%p", 6669 (void *)spkt); 6670 if (spkt == NULL) { 6671 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6672 "the failed slot spkt is NULL") 6673 goto out; 6674 } 6675 6676 failed_tags = 0x1 << failed_slot; 6677 6678 /* Fill out the error context */ 6679 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6680 ncq_err_page); 6681 ahci_update_sata_registers(ahci_ctlp, port, 6682 &spkt->satapkt_device); 6683 } 6684 } 6685 out: 6686 sata_free_error_retrieval_pkt(rdlog_spkt); 6687 6688 return (failed_tags); 6689 } 6690 6691 /* 6692 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6693 * module, and then deliver it to the HBA to get the sense data and copy 6694 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6695 * SENSE sata pkt later. 6696 */ 6697 static void 6698 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6699 uint8_t port, sata_pkt_t *spkt) 6700 { 6701 sata_device_t sdevice; 6702 sata_pkt_t *rs_spkt; 6703 sata_cmd_t *sata_cmd; 6704 ddi_dma_handle_t buf_dma_handle; 6705 int loop_count; 6706 #if AHCI_DEBUG 6707 struct scsi_extended_sense *rqsense; 6708 #endif 6709 6710 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6711 "ahci_get_rqsense_data enter: port %d", port); 6712 6713 /* Prepare the sdevice data */ 6714 bzero((void *)&sdevice, sizeof (sata_device_t)); 6715 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6716 6717 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6718 sdevice.satadev_addr.pmport = 0; 6719 6720 sata_cmd = &spkt->satapkt_cmd; 6721 6722 /* 6723 * Call the sata hba interface to get a rs spkt 6724 */ 6725 loop_count = 0; 6726 loop: 6727 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6728 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6729 if (rs_spkt == NULL) { 6730 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6731 /* Sleep for a while */ 6732 delay(AHCI_10MS_TICKS); 6733 goto loop; 6734 6735 } 6736 /* Timed out after 1s */ 6737 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6738 "failed to get rs spkt for port %d", port); 6739 return; 6740 } 6741 6742 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6743 6744 /* 6745 * This flag is used to handle the specific error recovery when the 6746 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6747 */ 6748 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6749 6750 /* 6751 * This start is not supposed to fail because after port is restarted, 6752 * the whole command list is empty. 6753 */ 6754 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6755 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6756 ahci_portp->ahciport_err_retri_pkt = NULL; 6757 6758 /* Remove the flag after REQUEST SENSE command is completed */ 6759 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6760 6761 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6762 /* Update the request sense data */ 6763 buf_dma_handle = *(ddi_dma_handle_t *) 6764 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6765 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6766 DDI_DMA_SYNC_FORKERNEL); 6767 /* Copy the request sense data */ 6768 bcopy(rs_spkt-> 6769 satapkt_cmd.satacmd_bp->b_un.b_addr, 6770 &sata_cmd->satacmd_rqsense, 6771 SATA_ATAPI_MIN_RQSENSE_LEN); 6772 #if AHCI_DEBUG 6773 rqsense = (struct scsi_extended_sense *) 6774 sata_cmd->satacmd_rqsense; 6775 6776 /* Dump the sense data */ 6777 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6778 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6779 "Sense data for satapkt %p ATAPI cmd 0x%x", 6780 spkt, sata_cmd->satacmd_acdb[0]); 6781 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6782 " es_code 0x%x es_class 0x%x " 6783 "es_key 0x%x es_add_code 0x%x " 6784 "es_qual_code 0x%x", 6785 rqsense->es_code, rqsense->es_class, 6786 rqsense->es_key, rqsense->es_add_code, 6787 rqsense->es_qual_code); 6788 #endif 6789 } 6790 6791 sata_free_error_retrieval_pkt(rs_spkt); 6792 } 6793 6794 /* 6795 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6796 * the port must be restarted. When the HBA detects thus error, it may try 6797 * to abort a transfer. And if the transfer was aborted, the device is 6798 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6799 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6800 * that the device is in a stable status and transfers may be restarted without 6801 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6802 * then the software will send the COMRESET to do the port reset. 6803 * 6804 * Software should perform the appropriate error recovery actions based on 6805 * whether non-queued commands were being issued or natived command queuing 6806 * commands were being issued. 6807 * 6808 * And software will complete the command that had the error with error mark 6809 * to higher level software. 6810 * 6811 * Fatal errors include the following: 6812 * PxIS.IFS - Interface Fatal Error Status 6813 * PxIS.HBDS - Host Bus Data Error Status 6814 * PxIS.HBFS - Host Bus Fatal Error Status 6815 * PxIS.TFES - Task File Error Status 6816 * 6817 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6818 */ 6819 static void 6820 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6821 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6822 { 6823 uint32_t port_cmd_status; 6824 uint32_t slot_status = 0; 6825 uint32_t failed_tags = 0; 6826 int failed_slot; 6827 int reset_flag = 0; 6828 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6829 sata_cmd_t *sata_cmd = NULL; 6830 sata_pkt_t *spkt = NULL; 6831 #if AHCI_DEBUG 6832 ahci_cmd_header_t *cmd_header; 6833 #endif 6834 6835 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6836 "ahci_fatal_error_recovery_handler enter: port %d", port); 6837 6838 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6839 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6840 6841 /* Read PxCI to see which commands are still outstanding */ 6842 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6843 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6844 6845 /* 6846 * Read PxCMD.CCS to determine the slot that the HBA 6847 * was processing when the error occurred. 6848 */ 6849 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6850 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6851 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6852 AHCI_CMD_STATUS_CCS_SHIFT; 6853 6854 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6855 spkt = ahci_portp->ahciport_err_retri_pkt; 6856 ASSERT(spkt != NULL); 6857 } else { 6858 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6859 if (spkt == NULL) { 6860 /* May happen when interface errors occur? */ 6861 goto next; 6862 } 6863 } 6864 6865 #if AHCI_DEBUG 6866 /* 6867 * Debugging purpose... 6868 */ 6869 if (ahci_portp->ahciport_prd_bytecounts[failed_slot]) { 6870 cmd_header = 6871 &ahci_portp->ahciport_cmd_list[failed_slot]; 6872 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 6873 "ahci_fatal_error_recovery_handler: port %d, " 6874 "PRD Byte Count = 0x%x, " 6875 "ahciport_prd_bytecounts = 0x%x", port, 6876 cmd_header->ahcich_prd_byte_count, 6877 ahci_portp->ahciport_prd_bytecounts[failed_slot]); 6878 } 6879 #endif 6880 6881 sata_cmd = &spkt->satapkt_cmd; 6882 6883 /* Fill out the status and error registers for PxIS.TFES */ 6884 if (intr_status & AHCI_INTR_STATUS_TFES) { 6885 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6886 ahcirf_d2h_register_fis); 6887 6888 /* Copy the error context back to the sata_cmd */ 6889 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6890 } 6891 6892 /* The failed command must be one of the outstanding commands */ 6893 failed_tags = 0x1 << failed_slot; 6894 ASSERT(failed_tags & slot_status); 6895 6896 /* Update the sata registers, especially PxSERR register */ 6897 ahci_update_sata_registers(ahci_ctlp, port, 6898 &spkt->satapkt_device); 6899 6900 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6901 /* Read PxSACT to see which commands are still outstanding */ 6902 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6903 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6904 } 6905 next: 6906 6907 #if AHCI_DEBUG 6908 /* 6909 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6910 * set, it means a fatal error happened after REQUEST SENSE command 6911 * or READ LOG EXT command is delivered to the HBA during the error 6912 * recovery process. At this time, the only outstanding command is 6913 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6914 */ 6915 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6916 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6917 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6918 "command or READ LOG EXT command for error data retrieval " 6919 "failed", port); 6920 ASSERT(slot_status == 0x1); 6921 ASSERT(failed_slot == 0); 6922 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6923 SCMD_REQUEST_SENSE || 6924 spkt->satapkt_cmd.satacmd_cmd_reg == 6925 SATAC_READ_LOG_EXT); 6926 } 6927 #endif 6928 6929 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6930 ahci_portp->ahciport_mop_in_progress++; 6931 6932 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6933 port, NULL, &reset_flag); 6934 6935 /* 6936 * Won't retrieve error information: 6937 * 1. Port reset was involved to recover 6938 * 2. Device is gone 6939 * 3. IDENTIFY DEVICE command sent to ATAPI device 6940 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6941 */ 6942 if (reset_flag || 6943 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6944 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6945 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6946 goto out; 6947 6948 /* 6949 * Deliver READ LOG EXT to gather information about the error when 6950 * a COMRESET has not been performed as part of the error recovery 6951 * during NCQ command processing. 6952 */ 6953 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6954 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6955 ahci_portp, port); 6956 goto out; 6957 } 6958 6959 /* 6960 * Deliver REQUEST SENSE for ATAPI command to gather information about 6961 * the error when a COMRESET has not been performed as part of the 6962 * error recovery. 6963 */ 6964 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPI) 6965 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6966 out: 6967 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6968 "ahci_fatal_error_recovery_handler: port %d fatal error " 6969 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6970 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6971 port, slot_status, ahci_portp->ahciport_pending_tags, 6972 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6973 6974 ahci_mop_commands(ahci_ctlp, 6975 ahci_portp, 6976 slot_status, 6977 failed_tags, /* failed tags */ 6978 0, /* timeout tags */ 6979 0, /* aborted tags */ 6980 0); /* reset tags */ 6981 } 6982 6983 /* 6984 * Handle events - fatal error recovery 6985 */ 6986 static void 6987 ahci_events_handler(void *args) 6988 { 6989 ahci_event_arg_t *ahci_event_arg; 6990 ahci_ctl_t *ahci_ctlp; 6991 ahci_port_t *ahci_portp; 6992 uint32_t event; 6993 uint8_t port; 6994 6995 ahci_event_arg = (ahci_event_arg_t *)args; 6996 6997 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6998 ahci_portp = ahci_event_arg->ahciea_portp; 6999 event = ahci_event_arg->ahciea_event; 7000 port = ahci_portp->ahciport_port_num; 7001 7002 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 7003 "ahci_events_handler enter: port %d intr_status = 0x%x", 7004 port, event); 7005 7006 mutex_enter(&ahci_portp->ahciport_mutex); 7007 7008 /* 7009 * ahci_intr_phyrdy_change() may have rendered it to 7010 * SATA_DTYPE_NONE. 7011 */ 7012 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 7013 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 7014 "ahci_events_handler: port %d no device attached, " 7015 "and just return without doing anything", port); 7016 goto out; 7017 } 7018 7019 if (event & (AHCI_INTR_STATUS_IFS | 7020 AHCI_INTR_STATUS_HBDS | 7021 AHCI_INTR_STATUS_HBFS | 7022 AHCI_INTR_STATUS_TFES)) 7023 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 7024 port, event); 7025 7026 out: 7027 mutex_exit(&ahci_portp->ahciport_mutex); 7028 } 7029 7030 /* 7031 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 7032 * detect there are some commands which are timed out. 7033 */ 7034 static void 7035 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 7036 uint8_t port, uint32_t tmp_timeout_tags) 7037 { 7038 uint32_t slot_status = 0; 7039 uint32_t finished_tags = 0; 7040 uint32_t timeout_tags = 0; 7041 7042 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 7043 "ahci_timeout_pkts enter: port %d", port); 7044 7045 mutex_enter(&ahci_portp->ahciport_mutex); 7046 7047 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 7048 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7049 /* Read PxCI to see which commands are still outstanding */ 7050 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7051 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 7052 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7053 /* Read PxSACT to see which commands are still outstanding */ 7054 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7055 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 7056 } 7057 7058 #if AHCI_DEBUG 7059 /* 7060 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 7061 * set, it means a fatal error happened after REQUEST SENSE command 7062 * or READ LOG EXT command is delivered to the HBA during the error 7063 * recovery process. At this time, the only outstanding command is 7064 * supposed to be REQUEST SENSE command or READ LOG EXT command. 7065 */ 7066 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7067 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 7068 "ahci_timeout_pkts called while REQUEST SENSE " 7069 "command or READ LOG EXT command for error recovery " 7070 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 7071 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 7072 tmp_timeout_tags, slot_status, 7073 ahci_portp->ahciport_pending_tags, 7074 ahci_portp->ahciport_pending_ncq_tags); 7075 ASSERT(slot_status == 0x1); 7076 } 7077 #endif 7078 7079 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 7080 ahci_portp->ahciport_mop_in_progress++; 7081 7082 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 7083 port, NULL, NULL); 7084 7085 /* 7086 * Re-identify timeout tags because some previously checked commands 7087 * could already complete. 7088 */ 7089 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7090 finished_tags = ahci_portp->ahciport_pending_tags & 7091 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 7092 timeout_tags = tmp_timeout_tags & ~finished_tags; 7093 7094 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 7095 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 7096 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 7097 "pending_tags = 0x%x ", 7098 port, finished_tags, timeout_tags, 7099 slot_status, ahci_portp->ahciport_pending_tags); 7100 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7101 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 7102 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 7103 timeout_tags = tmp_timeout_tags & ~finished_tags; 7104 7105 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 7106 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 7107 "timeout_tags = 0x%x, port_sactive = 0x%x, " 7108 "pending_ncq_tags = 0x%x ", 7109 port, finished_tags, timeout_tags, 7110 slot_status, ahci_portp->ahciport_pending_ncq_tags); 7111 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7112 timeout_tags = tmp_timeout_tags; 7113 } 7114 7115 ahci_mop_commands(ahci_ctlp, 7116 ahci_portp, 7117 slot_status, 7118 0, /* failed tags */ 7119 timeout_tags, /* timeout tags */ 7120 0, /* aborted tags */ 7121 0); /* reset tags */ 7122 7123 mutex_exit(&ahci_portp->ahciport_mutex); 7124 } 7125 7126 /* 7127 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 7128 * for long time. 7129 */ 7130 static void 7131 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 7132 { 7133 ahci_port_t *ahci_portp; 7134 sata_pkt_t *spkt; 7135 uint32_t pending_tags; 7136 uint32_t timeout_tags; 7137 uint32_t port_cmd_status; 7138 uint32_t port_sactive; 7139 uint8_t port; 7140 int tmp_slot; 7141 int current_slot; 7142 uint32_t current_tags; 7143 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7144 /* max number of cycles this packet should survive */ 7145 int max_life_cycles; 7146 7147 /* how many cycles this packet survived so far */ 7148 int watched_cycles; 7149 7150 mutex_enter(&ahci_ctlp->ahcictl_mutex); 7151 7152 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 7153 "ahci_watchdog_handler entered"); 7154 7155 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 7156 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 7157 continue; 7158 } 7159 7160 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 7161 7162 mutex_enter(&ahci_portp->ahciport_mutex); 7163 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 7164 mutex_exit(&ahci_portp->ahciport_mutex); 7165 continue; 7166 } 7167 7168 /* Skip the check for those ports in error recovery */ 7169 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 7170 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 7171 mutex_exit(&ahci_portp->ahciport_mutex); 7172 continue; 7173 } 7174 7175 pending_tags = 0; 7176 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7177 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 7178 7179 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7180 current_slot = 0; 7181 pending_tags = 0x1; 7182 } else if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7183 current_slot = 7184 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 7185 AHCI_CMD_STATUS_CCS_SHIFT; 7186 pending_tags = ahci_portp->ahciport_pending_tags; 7187 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7188 port_sactive = ddi_get32( 7189 ahci_ctlp->ahcictl_ahci_acc_handle, 7190 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 7191 current_tags = port_sactive & 7192 ~port_cmd_status & 7193 AHCI_NCQ_SLOT_MASK(ahci_portp); 7194 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 7195 } 7196 7197 timeout_tags = 0; 7198 while (pending_tags) { 7199 tmp_slot = ddi_ffs(pending_tags) - 1; 7200 if (tmp_slot == -1) { 7201 break; 7202 } 7203 7204 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 7205 spkt = ahci_portp->ahciport_err_retri_pkt; 7206 else 7207 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 7208 7209 if ((spkt != NULL) && spkt->satapkt_time && 7210 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 7211 /* 7212 * We are overloading satapkt_hba_driver_private 7213 * with watched_cycle count. 7214 * 7215 * If a packet has survived for more than it's 7216 * max life cycles, it is a candidate for time 7217 * out. 7218 */ 7219 watched_cycles = (int)(intptr_t) 7220 spkt->satapkt_hba_driver_private; 7221 watched_cycles++; 7222 max_life_cycles = (spkt->satapkt_time + 7223 ahci_watchdog_timeout - 1) / 7224 ahci_watchdog_timeout; 7225 7226 spkt->satapkt_hba_driver_private = 7227 (void *)(intptr_t)watched_cycles; 7228 7229 if (watched_cycles <= max_life_cycles) 7230 goto next; 7231 7232 #if AHCI_DEBUG 7233 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7234 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, 7235 ahci_ctlp, "watchdog: the current " 7236 "tags is 0x%x", current_tags); 7237 } else { 7238 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, 7239 ahci_ctlp, "watchdog: the current " 7240 "slot is %d", current_slot); 7241 } 7242 #endif 7243 7244 /* 7245 * We need to check whether the HBA has 7246 * begun to execute the command, if not, 7247 * then re-set the timer of the command. 7248 */ 7249 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 7250 (tmp_slot != current_slot) || 7251 NCQ_CMD_IN_PROGRESS(ahci_portp) && 7252 ((0x1 << tmp_slot) & current_tags)) { 7253 spkt->satapkt_hba_driver_private = 7254 (void *)(intptr_t)0; 7255 } else { 7256 timeout_tags |= (0x1 << tmp_slot); 7257 cmn_err(CE_WARN, "!ahci%d: watchdog " 7258 "port %d satapkt 0x%p timed out\n", 7259 instance, port, (void *)spkt); 7260 } 7261 } 7262 next: 7263 CLEAR_BIT(pending_tags, tmp_slot); 7264 } 7265 7266 if (timeout_tags) { 7267 mutex_exit(&ahci_portp->ahciport_mutex); 7268 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7269 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 7270 port, timeout_tags); 7271 mutex_enter(&ahci_ctlp->ahcictl_mutex); 7272 mutex_enter(&ahci_portp->ahciport_mutex); 7273 } 7274 7275 mutex_exit(&ahci_portp->ahciport_mutex); 7276 } 7277 7278 /* Re-install the watchdog timeout handler */ 7279 if (ahci_ctlp->ahcictl_timeout_id != 0) { 7280 ahci_ctlp->ahcictl_timeout_id = 7281 timeout((void (*)(void *))ahci_watchdog_handler, 7282 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 7283 } 7284 7285 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7286 } 7287 7288 /* 7289 * Fill the error context into sata_cmd for non-queued command error. 7290 */ 7291 static void 7292 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7293 { 7294 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 7295 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7296 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7297 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7298 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7299 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7300 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7301 7302 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 7303 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7304 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7305 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7306 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7307 } 7308 } 7309 7310 /* 7311 * Fill the ncq error page into sata_cmd for queued command error. 7312 */ 7313 static void 7314 ahci_copy_ncq_err_page(sata_cmd_t *scmd, 7315 struct sata_ncq_error_recovery_page *ncq_err_page) 7316 { 7317 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 7318 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 7319 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 7320 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 7321 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 7322 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 7323 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 7324 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 7325 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 7326 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 7327 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 7328 } 7329 7330 /* 7331 * Put the respective register value to sata_cmd_t for satacmd_flags. 7332 */ 7333 static void 7334 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7335 { 7336 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 7337 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7338 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 7339 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7340 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 7341 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7342 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 7343 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7344 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 7345 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7346 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 7347 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7348 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 7349 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7350 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 7351 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7352 if (scmd->satacmd_flags.sata_copy_out_device_reg) 7353 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7354 if (scmd->satacmd_flags.sata_copy_out_error_reg) 7355 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7356 } 7357 7358 static void 7359 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7360 uint32_t intr_status) 7361 { 7362 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7363 7364 if (intr_status & AHCI_INTR_STATUS_IFS) 7365 cmn_err(CE_WARN, "!ahci%d: ahci port %d has interface fatal " 7366 "error", instance, port); 7367 7368 if (intr_status & AHCI_INTR_STATUS_HBDS) 7369 cmn_err(CE_WARN, "!ahci%d: ahci port %d has bus data error", 7370 instance, port); 7371 7372 if (intr_status & AHCI_INTR_STATUS_HBFS) 7373 cmn_err(CE_WARN, "!ahci%d: ahci port %d has bus fatal error", 7374 instance, port); 7375 7376 if (intr_status & AHCI_INTR_STATUS_TFES) 7377 cmn_err(CE_WARN, "!ahci%d: ahci port %d has task file error", 7378 instance, port); 7379 7380 cmn_err(CE_WARN, "!ahci%d: ahci port %d is trying to do error " 7381 "recovery", instance, port); 7382 } 7383 7384 /* 7385 * Dump the serror message to the log. 7386 */ 7387 static void 7388 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7389 uint32_t port_serror, int debug_only) 7390 { 7391 static char err_buf[512]; 7392 static char err_msg_header[16]; 7393 char *err_msg = err_buf; 7394 7395 *err_buf = '\0'; 7396 *err_msg_header = '\0'; 7397 7398 if (port_serror & SERROR_DATA_ERR_FIXED) { 7399 err_msg = strcat(err_msg, 7400 "\tRecovered Data Integrity Error (I)\n"); 7401 } 7402 7403 if (port_serror & SERROR_COMM_ERR_FIXED) { 7404 err_msg = strcat(err_msg, 7405 "\tRecovered Communication Error (M)\n"); 7406 } 7407 7408 if (port_serror & SERROR_DATA_ERR) { 7409 err_msg = strcat(err_msg, 7410 "\tTransient Data Integrity Error (T)\n"); 7411 } 7412 7413 if (port_serror & SERROR_PERSISTENT_ERR) { 7414 err_msg = strcat(err_msg, 7415 "\tPersistent Communication or Data Integrity Error (C)\n"); 7416 } 7417 7418 if (port_serror & SERROR_PROTOCOL_ERR) { 7419 err_msg = strcat(err_msg, "\tProtocol Error (P)\n"); 7420 } 7421 7422 if (port_serror & SERROR_INT_ERR) { 7423 err_msg = strcat(err_msg, "\tInternal Error (E)\n"); 7424 } 7425 7426 if (port_serror & SERROR_PHY_RDY_CHG) { 7427 err_msg = strcat(err_msg, "\tPhyRdy Change (N)\n"); 7428 } 7429 7430 if (port_serror & SERROR_PHY_INT_ERR) { 7431 err_msg = strcat(err_msg, "\tPhy Internal Error (I)\n"); 7432 } 7433 7434 if (port_serror & SERROR_COMM_WAKE) { 7435 err_msg = strcat(err_msg, "\tComm Wake (W)\n"); 7436 } 7437 7438 if (port_serror & SERROR_10B_TO_8B_ERR) { 7439 err_msg = strcat(err_msg, "\t10B to 8B Decode Error (B)\n"); 7440 } 7441 7442 if (port_serror & SERROR_DISPARITY_ERR) { 7443 err_msg = strcat(err_msg, "\tDisparity Error (D)\n"); 7444 } 7445 7446 if (port_serror & SERROR_CRC_ERR) { 7447 err_msg = strcat(err_msg, "\tCRC Error (C)\n"); 7448 } 7449 7450 if (port_serror & SERROR_HANDSHAKE_ERR) { 7451 err_msg = strcat(err_msg, "\tHandshake Error (H)\n"); 7452 } 7453 7454 if (port_serror & SERROR_LINK_SEQ_ERR) { 7455 err_msg = strcat(err_msg, "\tLink Sequence Error (S)\n"); 7456 } 7457 7458 if (port_serror & SERROR_TRANS_ERR) { 7459 err_msg = strcat(err_msg, 7460 "\tTransport state transition error (T)\n"); 7461 } 7462 7463 if (port_serror & SERROR_FIS_TYPE) { 7464 err_msg = strcat(err_msg, "\tUnknown FIS Type (F)\n"); 7465 } 7466 7467 if (port_serror & SERROR_EXCHANGED_ERR) { 7468 err_msg = strcat(err_msg, "\tExchanged (X)\n"); 7469 } 7470 7471 if (err_msg == NULL) 7472 return; 7473 7474 if (debug_only) { 7475 (void) sprintf(err_msg_header, "port %d", port); 7476 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg_header); 7477 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg); 7478 } else if (ahci_ctlp) { 7479 cmn_err(CE_WARN, "!ahci%d: %s %s", 7480 ddi_get_instance(ahci_ctlp->ahcictl_dip), 7481 err_msg_header, err_msg); 7482 } else { 7483 cmn_err(CE_WARN, "!ahci: %s %s", err_msg_header, err_msg); 7484 } 7485 } 7486 7487 /* 7488 * This routine is to calculate the total number of ports implemented 7489 * by the HBA. 7490 */ 7491 static int 7492 ahci_get_num_implemented_ports(uint32_t ports_implemented) 7493 { 7494 uint8_t i; 7495 int num = 0; 7496 7497 for (i = 0; i < AHCI_MAX_PORTS; i++) { 7498 if (((uint32_t)0x1 << i) & ports_implemented) 7499 num++; 7500 } 7501 7502 return (num); 7503 } 7504 7505 #if AHCI_DEBUG 7506 static void 7507 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7508 { 7509 static char name[16]; 7510 va_list ap; 7511 7512 mutex_enter(&ahci_log_mutex); 7513 7514 va_start(ap, fmt); 7515 if (ahci_ctlp) { 7516 (void) sprintf(name, "ahci%d: ", 7517 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7518 } else { 7519 (void) sprintf(name, "ahci: "); 7520 } 7521 7522 (void) vsprintf(ahci_log_buf, fmt, ap); 7523 va_end(ap); 7524 7525 cmn_err(level, "%s%s", name, ahci_log_buf); 7526 7527 mutex_exit(&ahci_log_mutex); 7528 } 7529 #endif 7530 7531 /* 7532 * quiesce(9E) entry point. 7533 * 7534 * This function is called when the system is single-threaded at high 7535 * PIL with preemption disabled. Therefore, this function must not be 7536 * blocked. 7537 * 7538 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 7539 * DDI_FAILURE indicates an error condition and should almost never happen. 7540 */ 7541 static int 7542 ahci_quiesce(dev_info_t *dip) 7543 { 7544 ahci_ctl_t *ahci_ctlp; 7545 ahci_port_t *ahci_portp; 7546 int instance, port; 7547 7548 instance = ddi_get_instance(dip); 7549 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 7550 7551 if (ahci_ctlp == NULL) 7552 return (DDI_FAILURE); 7553 7554 #if AHCI_DEBUG 7555 ahci_debug_flags = 0; 7556 #endif 7557 7558 /* disable all the interrupts. */ 7559 ahci_disable_all_intrs(ahci_ctlp); 7560 7561 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 7562 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 7563 continue; 7564 } 7565 7566 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 7567 7568 /* 7569 * Stop the port by clearing PxCMD.ST 7570 * 7571 * Here we must disable the port interrupt because 7572 * ahci_disable_all_intrs only clear GHC.IE, and IS 7573 * register will be still set if PxIE is enabled. 7574 * When ahci shares one IRQ with other drivers, the 7575 * intr handler may claim the intr mistakenly. 7576 */ 7577 ahci_disable_port_intrs(ahci_ctlp, port); 7578 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 7579 ahci_portp, port); 7580 } 7581 7582 return (DDI_SUCCESS); 7583 } 7584