1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 29 * 30 * Power Management Support 31 * ------------------------ 32 * 33 * At the moment, the ahci driver only implements suspend/resume to 34 * support Suspend to RAM on X86 feature. Device power management isn't 35 * implemented, link power management is disabled, and hot plug isn't 36 * allowed during the period from suspend to resume. 37 * 38 * For s/r support, the ahci driver only need to implement DDI_SUSPEND 39 * and DDI_RESUME entries, and don't need to take care of new requests 40 * sent down after suspend because the target driver (sd) has already 41 * handled these conditions, and blocked these requests. For the detailed 42 * information, please check with sdopen, sdclose and sdioctl routines. 43 * 44 */ 45 46 #include <sys/note.h> 47 #include <sys/scsi/scsi.h> 48 #include <sys/pci.h> 49 #include <sys/disp.h> 50 #include <sys/sata/sata_hba.h> 51 #include <sys/sata/adapters/ahci/ahcireg.h> 52 #include <sys/sata/adapters/ahci/ahcivar.h> 53 54 /* 55 * This is the string displayed by modinfo, etc. 56 * Make sure you keep the version ID up to date! 57 */ 58 static char ahci_ident[] = "ahci driver"; 59 60 /* 61 * Function prototypes for driver entry points 62 */ 63 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 64 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 65 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 66 static int ahci_quiesce(dev_info_t *); 67 68 /* 69 * Function prototypes for SATA Framework interfaces 70 */ 71 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 72 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 73 74 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 75 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 76 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 77 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 78 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 79 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 80 #if defined(__lock_lint) 81 static int ahci_selftest(dev_info_t *, sata_device_t *); 82 #endif 83 84 /* 85 * Local function prototypes 86 */ 87 static int ahci_alloc_ports_state(ahci_ctl_t *); 88 static void ahci_dealloc_ports_state(ahci_ctl_t *); 89 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 90 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 91 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 92 static void ahci_dealloc_rcvd_fis(ahci_port_t *); 93 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 94 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 95 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 96 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 97 98 static int ahci_initialize_controller(ahci_ctl_t *); 99 static void ahci_uninitialize_controller(ahci_ctl_t *); 100 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 101 static int ahci_config_space_init(ahci_ctl_t *); 102 103 static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 104 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 105 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 106 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 107 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 108 uint8_t, sata_pkt_t *); 109 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 110 uint8_t, sata_pkt_t *); 111 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 112 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 113 static void ahci_copy_ncq_err_page(sata_cmd_t *, 114 struct sata_ncq_error_recovery_page *); 115 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 116 117 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 118 static int ahci_hba_reset(ahci_ctl_t *); 119 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 120 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 121 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 122 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 123 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 124 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 125 uint8_t); 126 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 127 uint8_t, int, int *); 128 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint32_t, 129 uint32_t, uint32_t, uint32_t, uint32_t); 130 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 131 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 132 uint8_t, sata_pkt_t *); 133 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 134 uint8_t, uint32_t); 135 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 136 uint8_t, uint32_t); 137 static void ahci_events_handler(void *); 138 static void ahci_watchdog_handler(ahci_ctl_t *); 139 140 static uint_t ahci_intr(caddr_t, caddr_t); 141 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 142 static int ahci_add_legacy_intrs(ahci_ctl_t *); 143 static int ahci_add_msi_intrs(ahci_ctl_t *); 144 static void ahci_rem_intrs(ahci_ctl_t *); 145 static void ahci_enable_all_intrs(ahci_ctl_t *); 146 static void ahci_disable_all_intrs(ahci_ctl_t *); 147 static void ahci_enable_port_intrs(ahci_ctl_t *, uint8_t); 148 static void ahci_disable_port_intrs(ahci_ctl_t *, uint8_t); 149 150 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t); 151 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 152 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 153 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 154 ahci_port_t *, uint8_t); 155 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 156 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 157 uint8_t, uint32_t); 158 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 159 uint8_t, uint32_t); 160 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 161 162 static int ahci_get_num_implemented_ports(uint32_t); 163 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 164 uint32_t); 165 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int); 166 #if AHCI_DEBUG 167 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 168 #endif 169 170 171 /* 172 * DMA attributes for the data buffer 173 * 174 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 175 * does not support 64-bit addressing 176 */ 177 static ddi_dma_attr_t buffer_dma_attr = { 178 DMA_ATTR_V0, /* dma_attr_version */ 179 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 180 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 181 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 182 0x2ull, /* dma_attr_align: word aligned */ 183 1, /* dma_attr_burstsizes */ 184 1, /* dma_attr_minxfer */ 185 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 186 0xffffffffull, /* dma_attr_seg */ 187 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 188 512, /* dma_attr_granular */ 189 0, /* dma_attr_flags */ 190 }; 191 192 /* 193 * DMA attributes for the rcvd FIS 194 * 195 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 196 * does not support 64-bit addressing 197 */ 198 static ddi_dma_attr_t rcvd_fis_dma_attr = { 199 DMA_ATTR_V0, /* dma_attr_version */ 200 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 201 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 202 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 203 0x100ull, /* dma_attr_align: 256-byte aligned */ 204 1, /* dma_attr_burstsizes */ 205 1, /* dma_attr_minxfer */ 206 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 207 0xffffffffull, /* dma_attr_seg */ 208 1, /* dma_attr_sgllen */ 209 1, /* dma_attr_granular */ 210 0, /* dma_attr_flags */ 211 }; 212 213 /* 214 * DMA attributes for the command list 215 * 216 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 217 * does not support 64-bit addressing 218 */ 219 static ddi_dma_attr_t cmd_list_dma_attr = { 220 DMA_ATTR_V0, /* dma_attr_version */ 221 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 222 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 223 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 224 0x400ull, /* dma_attr_align: 1K-byte aligned */ 225 1, /* dma_attr_burstsizes */ 226 1, /* dma_attr_minxfer */ 227 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 228 0xffffffffull, /* dma_attr_seg */ 229 1, /* dma_attr_sgllen */ 230 1, /* dma_attr_granular */ 231 0, /* dma_attr_flags */ 232 }; 233 234 /* 235 * DMA attributes for cmd tables 236 * 237 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 238 * does not support 64-bit addressing 239 */ 240 static ddi_dma_attr_t cmd_table_dma_attr = { 241 DMA_ATTR_V0, /* dma_attr_version */ 242 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 243 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 244 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 245 0x80ull, /* dma_attr_align: 128-byte aligned */ 246 1, /* dma_attr_burstsizes */ 247 1, /* dma_attr_minxfer */ 248 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 249 0xffffffffull, /* dma_attr_seg */ 250 1, /* dma_attr_sgllen */ 251 1, /* dma_attr_granular */ 252 0, /* dma_attr_flags */ 253 }; 254 255 256 /* Device access attributes */ 257 static ddi_device_acc_attr_t accattr = { 258 DDI_DEVICE_ATTR_V0, 259 DDI_STRUCTURE_LE_ACC, 260 DDI_STRICTORDER_ACC 261 }; 262 263 264 static struct dev_ops ahcictl_dev_ops = { 265 DEVO_REV, /* devo_rev */ 266 0, /* refcnt */ 267 ahci_getinfo, /* info */ 268 nulldev, /* identify */ 269 nulldev, /* probe */ 270 ahci_attach, /* attach */ 271 ahci_detach, /* detach */ 272 nodev, /* no reset */ 273 (struct cb_ops *)0, /* driver operations */ 274 NULL, /* bus operations */ 275 NULL, /* power */ 276 ahci_quiesce, /* quiesce */ 277 }; 278 279 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 280 SATA_TRAN_HOTPLUG_OPS_REV_1, 281 ahci_tran_hotplug_port_activate, 282 ahci_tran_hotplug_port_deactivate 283 }; 284 285 extern struct mod_ops mod_driverops; 286 287 static struct modldrv modldrv = { 288 &mod_driverops, /* driverops */ 289 ahci_ident, /* short description */ 290 &ahcictl_dev_ops, /* driver ops */ 291 }; 292 293 static struct modlinkage modlinkage = { 294 MODREV_1, 295 &modldrv, 296 NULL 297 }; 298 299 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 300 static int ahci_watchdog_tick; 301 302 static size_t ahci_cmd_table_size; 303 304 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 305 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 306 307 /* 308 * AHCI MSI tunable: 309 * 310 * MSI will be enabled in phase 2. 311 */ 312 boolean_t ahci_msi_enabled = B_FALSE; 313 314 #if AHCI_DEBUG 315 uint32_t ahci_debug_flags = 0; 316 317 /* The following is needed for ahci_log() */ 318 static kmutex_t ahci_log_mutex; 319 static char ahci_log_buf[512]; 320 #endif 321 322 /* Opaque state pointer initialized by ddi_soft_state_init() */ 323 static void *ahci_statep = NULL; 324 325 /* 326 * ahci module initialization. 327 */ 328 int 329 _init(void) 330 { 331 int ret; 332 333 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 334 if (ret != 0) { 335 goto err_out; 336 } 337 338 #if AHCI_DEBUG 339 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 340 #endif 341 342 if ((ret = sata_hba_init(&modlinkage)) != 0) { 343 #if AHCI_DEBUG 344 mutex_destroy(&ahci_log_mutex); 345 #endif 346 ddi_soft_state_fini(&ahci_statep); 347 goto err_out; 348 } 349 350 ret = mod_install(&modlinkage); 351 if (ret != 0) { 352 sata_hba_fini(&modlinkage); 353 #if AHCI_DEBUG 354 mutex_destroy(&ahci_log_mutex); 355 #endif 356 ddi_soft_state_fini(&ahci_statep); 357 goto err_out; 358 } 359 360 /* watchdog tick */ 361 ahci_watchdog_tick = drv_usectohz( 362 (clock_t)ahci_watchdog_timeout * 1000000); 363 return (ret); 364 365 err_out: 366 cmn_err(CE_WARN, "!ahci: Module init failed"); 367 return (ret); 368 } 369 370 /* 371 * ahci module uninitialize. 372 */ 373 int 374 _fini(void) 375 { 376 int ret; 377 378 ret = mod_remove(&modlinkage); 379 if (ret != 0) { 380 return (ret); 381 } 382 383 /* Remove the resources allocated in _init(). */ 384 sata_hba_fini(&modlinkage); 385 #if AHCI_DEBUG 386 mutex_destroy(&ahci_log_mutex); 387 #endif 388 ddi_soft_state_fini(&ahci_statep); 389 390 return (ret); 391 } 392 393 /* 394 * _info entry point 395 */ 396 int 397 _info(struct modinfo *modinfop) 398 { 399 return (mod_info(&modlinkage, modinfop)); 400 } 401 402 /* 403 * The attach entry point for dev_ops. 404 */ 405 static int 406 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 407 { 408 ahci_ctl_t *ahci_ctlp; 409 int instance = ddi_get_instance(dip); 410 int status; 411 int attach_state; 412 uint32_t cap_status, ahci_version; 413 int intr_types; 414 int i; 415 pci_regspec_t *regs; 416 int regs_length; 417 int rnumber; 418 #if AHCI_DEBUG 419 int speed; 420 #endif 421 422 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 423 424 switch (cmd) { 425 case DDI_ATTACH: 426 break; 427 428 case DDI_RESUME: 429 430 /* 431 * During DDI_RESUME, the hardware state of the device 432 * (power may have been removed from the device) must be 433 * restored, allow pending requests to continue, and 434 * service new requests. 435 */ 436 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 437 mutex_enter(&ahci_ctlp->ahcictl_mutex); 438 439 /* Restart watch thread */ 440 if (ahci_ctlp->ahcictl_timeout_id == 0) 441 ahci_ctlp->ahcictl_timeout_id = timeout( 442 (void (*)(void *))ahci_watchdog_handler, 443 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 444 445 mutex_exit(&ahci_ctlp->ahcictl_mutex); 446 447 /* 448 * Re-initialize the controller and enable the interrupts and 449 * restart all the ports. 450 * 451 * Note that so far we don't support hot-plug during 452 * suspend/resume. 453 */ 454 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 455 AHCIDBG0(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 456 "Failed to initialize the controller " 457 "during DDI_RESUME"); 458 return (DDI_FAILURE); 459 } 460 461 mutex_enter(&ahci_ctlp->ahcictl_mutex); 462 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 463 mutex_exit(&ahci_ctlp->ahcictl_mutex); 464 465 return (DDI_SUCCESS); 466 467 default: 468 return (DDI_FAILURE); 469 } 470 471 attach_state = AHCI_ATTACH_STATE_NONE; 472 473 /* Allocate soft state */ 474 status = ddi_soft_state_zalloc(ahci_statep, instance); 475 if (status != DDI_SUCCESS) { 476 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state", 477 instance); 478 goto err_out; 479 } 480 481 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 482 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 483 ahci_ctlp->ahcictl_dip = dip; 484 485 /* Initialize the cport/port mapping */ 486 for (i = 0; i < AHCI_MAX_PORTS; i++) { 487 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 488 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 489 } 490 491 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 492 493 /* 494 * Now map the AHCI base address; which includes global 495 * registers and port control registers 496 * 497 * According to the spec, the AHCI Base Address is BAR5, 498 * but BAR0-BAR4 are optional, so we need to check which 499 * rnumber is used for BAR5. 500 */ 501 502 /* 503 * search through DDI "reg" property for the AHCI register set 504 */ 505 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 506 DDI_PROP_DONTPASS, "reg", (int **)®s, 507 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 508 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property", 509 instance); 510 goto err_out; 511 } 512 513 /* AHCI Base Address is located at 0x24 offset */ 514 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 515 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 516 == AHCI_PCI_RNUM) 517 break; 518 } 519 520 ddi_prop_free(regs); 521 522 if (rnumber == regs_length) { 523 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set", 524 instance); 525 goto err_out; 526 } 527 528 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 529 530 status = ddi_regs_map_setup(dip, 531 rnumber, 532 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 533 0, 534 0, 535 &accattr, 536 &ahci_ctlp->ahcictl_ahci_acc_handle); 537 if (status != DDI_SUCCESS) { 538 cmn_err(CE_WARN, "!ahci%d: Cannot map register space", 539 instance); 540 goto err_out; 541 } 542 543 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 544 545 /* Get the AHCI version information */ 546 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 547 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 548 549 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance, 550 (ahci_version & 0xffff0000) >> 16, 551 ((ahci_version & 0x0000ff00) >> 4 | 552 (ahci_version & 0x000000ff))); 553 554 /* We don't support controllers whose versions are lower than 1.0 */ 555 if (!(ahci_version & 0xffff0000)) { 556 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower " 557 "than version 1.0", instance); 558 goto err_out; 559 } 560 561 /* Get the HBA capabilities information */ 562 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 563 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 564 565 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 566 cap_status); 567 568 #if AHCI_DEBUG 569 /* Get the interface speed supported by the HBA */ 570 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 571 if (speed == 0x01) { 572 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 573 "hba interface speed support: Gen 1 (1.5Gbps)"); 574 } else if (speed == 0x10) { 575 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 576 "hba interface speed support: Gen 2 (3 Gbps)"); 577 } else if (speed == 0x11) { 578 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 579 "hba interface speed support: Gen 3 (6 Gbps)"); 580 } 581 #endif 582 583 /* Get the number of command slots supported by the HBA */ 584 ahci_ctlp->ahcictl_num_cmd_slots = 585 ((cap_status & AHCI_HBA_CAP_NCS) >> 586 AHCI_HBA_CAP_NCS_SHIFT) + 1; 587 588 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 589 ahci_ctlp->ahcictl_num_cmd_slots); 590 591 /* Get the bit map which indicates ports implemented by the HBA */ 592 ahci_ctlp->ahcictl_ports_implemented = 593 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 594 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 595 596 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 597 ahci_ctlp->ahcictl_ports_implemented); 598 599 /* 600 * According to the AHCI spec, CAP.NP should indicate the maximum 601 * number of ports supported by the HBA silicon, but we found 602 * this value of ICH8 chipset only indicates the number of ports 603 * implemented (exposed) by it. Therefore, the driver should calculate 604 * the potential maximum value by checking PI register, and use 605 * the maximum of this value and CAP.NP. 606 */ 607 ahci_ctlp->ahcictl_num_ports = max( 608 (cap_status & AHCI_HBA_CAP_NP) + 1, 609 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 610 611 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 612 ahci_ctlp->ahcictl_num_ports); 613 614 /* Get the number of implemented ports by the HBA */ 615 ahci_ctlp->ahcictl_num_implemented_ports = 616 ahci_get_num_implemented_ports( 617 ahci_ctlp->ahcictl_ports_implemented); 618 619 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 620 "hba number of implemented ports: %d", 621 ahci_ctlp->ahcictl_num_implemented_ports); 622 623 /* Check whether HBA supports 64bit DMA addressing */ 624 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 625 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 626 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 627 "hba does not support 64-bit addressing"); 628 } 629 630 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 631 != DDI_SUCCESS) { 632 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space", 633 instance); 634 goto err_out; 635 } 636 637 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 638 639 /* Check the pci configuration space, and set caps */ 640 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 641 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed", 642 instance); 643 goto err_out; 644 } 645 646 /* 647 * Disable the whole controller interrupts before adding 648 * interrupt handlers(s). 649 */ 650 ahci_disable_all_intrs(ahci_ctlp); 651 652 /* Get supported interrupt types */ 653 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 654 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed", 655 instance); 656 goto err_out; 657 } 658 659 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 660 "ddi_intr_get_supported_types() returned: 0x%x", 661 intr_types); 662 663 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 664 /* 665 * Try MSI first, but fall back to FIXED if failed 666 */ 667 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 668 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 669 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 670 "Using MSI interrupt type"); 671 goto intr_done; 672 } 673 674 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 675 "MSI registration failed, " 676 "trying FIXED interrupts"); 677 } 678 679 if (intr_types & DDI_INTR_TYPE_FIXED) { 680 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 681 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 682 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 683 "Using FIXED interrupt type"); 684 goto intr_done; 685 } 686 687 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 688 "FIXED interrupt registration failed"); 689 } 690 691 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance); 692 693 goto err_out; 694 695 intr_done: 696 697 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 698 699 /* Initialize the controller mutex */ 700 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 701 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 702 703 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 704 705 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 706 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 707 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 708 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 709 } 710 711 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 712 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 713 sizeof (ahci_prdt_item_t)); 714 715 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 716 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 717 " ahci_cmd_table_size is 0x%x", 718 ahci_dma_prdt_number, ahci_cmd_table_size); 719 720 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 721 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 722 ahci_dma_prdt_number; 723 724 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 725 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 726 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 727 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 728 729 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_32BIT_DMA) { 730 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 731 0xffffffffull; 732 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 733 0xffffffffull; 734 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 735 0xffffffffull; 736 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 737 0xffffffffull; 738 } 739 740 /* Allocate the ports structure */ 741 status = ahci_alloc_ports_state(ahci_ctlp); 742 if (status != AHCI_SUCCESS) { 743 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure", 744 instance); 745 goto err_out; 746 } 747 748 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 749 750 /* 751 * A taskq is created for dealing with events 752 */ 753 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 754 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 755 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event " 756 "handle", instance); 757 goto err_out; 758 } 759 760 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 761 762 /* 763 * Initialize the controller and ports. 764 */ 765 status = ahci_initialize_controller(ahci_ctlp); 766 if (status != AHCI_SUCCESS) { 767 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed", 768 instance); 769 goto err_out; 770 } 771 772 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 773 774 /* Start one thread to check packet timeouts */ 775 ahci_ctlp->ahcictl_timeout_id = timeout( 776 (void (*)(void *))ahci_watchdog_handler, 777 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 778 779 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 780 781 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 782 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed", 783 instance); 784 goto err_out; 785 } 786 787 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 788 789 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 790 791 return (DDI_SUCCESS); 792 793 err_out: 794 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 795 mutex_enter(&ahci_ctlp->ahcictl_mutex); 796 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 797 ahci_ctlp->ahcictl_timeout_id = 0; 798 mutex_exit(&ahci_ctlp->ahcictl_mutex); 799 } 800 801 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 802 ahci_uninitialize_controller(ahci_ctlp); 803 } 804 805 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 806 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 807 } 808 809 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 810 ahci_dealloc_ports_state(ahci_ctlp); 811 } 812 813 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 814 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 815 } 816 817 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 818 ahci_rem_intrs(ahci_ctlp); 819 } 820 821 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 822 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 823 } 824 825 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 826 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 827 } 828 829 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 830 ddi_soft_state_free(ahci_statep, instance); 831 } 832 833 return (DDI_FAILURE); 834 } 835 836 /* 837 * The detach entry point for dev_ops. 838 */ 839 static int 840 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 841 { 842 ahci_ctl_t *ahci_ctlp; 843 int instance; 844 int ret; 845 846 instance = ddi_get_instance(dip); 847 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 848 849 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 850 851 switch (cmd) { 852 case DDI_DETACH: 853 854 /* disable the interrupts for an uninterrupted detach */ 855 mutex_enter(&ahci_ctlp->ahcictl_mutex); 856 ahci_disable_all_intrs(ahci_ctlp); 857 mutex_exit(&ahci_ctlp->ahcictl_mutex); 858 859 /* unregister from the sata framework. */ 860 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 861 if (ret != AHCI_SUCCESS) { 862 mutex_enter(&ahci_ctlp->ahcictl_mutex); 863 ahci_enable_all_intrs(ahci_ctlp); 864 mutex_exit(&ahci_ctlp->ahcictl_mutex); 865 return (DDI_FAILURE); 866 } 867 868 mutex_enter(&ahci_ctlp->ahcictl_mutex); 869 870 /* stop the watchdog handler */ 871 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 872 ahci_ctlp->ahcictl_timeout_id = 0; 873 874 mutex_exit(&ahci_ctlp->ahcictl_mutex); 875 876 /* uninitialize the controller */ 877 ahci_uninitialize_controller(ahci_ctlp); 878 879 /* remove the interrupts */ 880 ahci_rem_intrs(ahci_ctlp); 881 882 /* destroy the taskq */ 883 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 884 885 /* deallocate the ports structures */ 886 ahci_dealloc_ports_state(ahci_ctlp); 887 888 /* destroy mutex */ 889 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 890 891 /* teardown the pci config */ 892 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 893 894 /* remove the reg maps. */ 895 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 896 897 /* free the soft state. */ 898 ddi_soft_state_free(ahci_statep, instance); 899 900 return (DDI_SUCCESS); 901 902 case DDI_SUSPEND: 903 904 /* 905 * The steps associated with suspension must include putting 906 * the underlying device into a quiescent state so that it 907 * will not generate interrupts or modify or access memory. 908 */ 909 mutex_enter(&ahci_ctlp->ahcictl_mutex); 910 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 911 mutex_exit(&ahci_ctlp->ahcictl_mutex); 912 return (DDI_SUCCESS); 913 } 914 915 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 916 917 /* stop the watchdog handler */ 918 if (ahci_ctlp->ahcictl_timeout_id) { 919 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 920 ahci_ctlp->ahcictl_timeout_id = 0; 921 } 922 923 mutex_exit(&ahci_ctlp->ahcictl_mutex); 924 925 /* 926 * drain the taskq 927 */ 928 ddi_taskq_wait(ahci_ctlp->ahcictl_event_taskq); 929 930 /* 931 * Disable the interrupts and stop all the ports. 932 */ 933 ahci_uninitialize_controller(ahci_ctlp); 934 935 return (DDI_SUCCESS); 936 937 default: 938 return (DDI_FAILURE); 939 } 940 } 941 942 /* 943 * The info entry point for dev_ops. 944 * 945 */ 946 static int 947 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 948 void *arg, void **result) 949 { 950 #ifndef __lock_lint 951 _NOTE(ARGUNUSED(dip)) 952 #endif /* __lock_lint */ 953 954 ahci_ctl_t *ahci_ctlp; 955 int instance; 956 dev_t dev; 957 958 dev = (dev_t)arg; 959 instance = getminor(dev); 960 961 switch (infocmd) { 962 case DDI_INFO_DEVT2DEVINFO: 963 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 964 if (ahci_ctlp != NULL) { 965 *result = ahci_ctlp->ahcictl_dip; 966 return (DDI_SUCCESS); 967 } else { 968 *result = NULL; 969 return (DDI_FAILURE); 970 } 971 case DDI_INFO_DEVT2INSTANCE: 972 *(int *)result = instance; 973 break; 974 default: 975 break; 976 } 977 978 return (DDI_SUCCESS); 979 } 980 981 /* 982 * Registers the ahci with sata framework. 983 */ 984 static int 985 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 986 { 987 struct sata_hba_tran *sata_hba_tran; 988 989 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 990 "ahci_register_sata_hba_tran enter"); 991 992 mutex_enter(&ahci_ctlp->ahcictl_mutex); 993 994 /* Allocate memory for the sata_hba_tran */ 995 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 996 997 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 998 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 999 sata_hba_tran->sata_tran_hba_dma_attr = 1000 &ahci_ctlp->ahcictl_buffer_dma_attr; 1001 1002 /* Report the number of implemented ports */ 1003 sata_hba_tran->sata_tran_hba_num_cports = 1004 ahci_ctlp->ahcictl_num_implemented_ports; 1005 1006 /* Support ATAPI device */ 1007 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 1008 1009 /* Get the data transfer capability for PIO command by the HBA */ 1010 if (cap_status & AHCI_HBA_CAP_PMD) { 1011 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 1012 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 1013 "DRQ block data transfer for PIO command protocol"); 1014 } 1015 1016 /* 1017 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 1018 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 1019 * QUEUED (EXT), and SERVICE commands). Queued operations are 1020 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 1021 * QUEUED commands when the HBA and device support native command 1022 * queuing(NCQ). 1023 * 1024 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 1025 * CAP register of the HBA indicates NCQ is supported. 1026 * 1027 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 1028 * set because the previous register content of PxCI can be re-written 1029 * in the register write. 1030 */ 1031 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 1032 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 1033 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 1034 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 1035 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 1036 "Command Queuing"); 1037 } 1038 1039 /* Report the number of command slots */ 1040 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1041 1042 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1043 sata_hba_tran->sata_tran_start = ahci_tran_start; 1044 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1045 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1046 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1047 #ifdef __lock_lint 1048 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1049 #endif 1050 /* 1051 * When SATA framework adds support for pwrmgt the 1052 * pwrmgt_ops needs to be updated 1053 */ 1054 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1055 sata_hba_tran->sata_tran_ioctl = NULL; 1056 1057 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1058 1059 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1060 1061 /* Attach it to SATA framework */ 1062 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1063 != DDI_SUCCESS) { 1064 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1065 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1066 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1067 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1068 return (AHCI_FAILURE); 1069 } 1070 1071 return (AHCI_SUCCESS); 1072 } 1073 1074 /* 1075 * Unregisters the ahci with sata framework. 1076 */ 1077 static int 1078 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1079 { 1080 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1081 "ahci_unregister_sata_hba_tran enter"); 1082 1083 /* Detach from the SATA framework. */ 1084 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1085 DDI_SUCCESS) { 1086 return (AHCI_FAILURE); 1087 } 1088 1089 /* Deallocate sata_hba_tran. */ 1090 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1091 sizeof (sata_hba_tran_t)); 1092 1093 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1094 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1095 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1096 1097 return (AHCI_SUCCESS); 1098 } 1099 1100 /* 1101 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1102 * port status registers and an attached device type via sata_device 1103 * structure. 1104 * 1105 * We return the cached information from a previous hardware probe. The 1106 * actual hardware probing itself was done either from within 1107 * ahci_initialize_controller() during the driver attach or from a phy 1108 * ready change interrupt handler. 1109 */ 1110 static int 1111 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1112 { 1113 ahci_ctl_t *ahci_ctlp; 1114 ahci_port_t *ahci_portp; 1115 uint8_t cport = sd->satadev_addr.cport; 1116 #if AHCI_DEBUG 1117 uint8_t pmport = sd->satadev_addr.pmport; 1118 uint8_t qual = sd->satadev_addr.qual; 1119 #endif 1120 uint8_t device_type; 1121 uint32_t port_state; 1122 uint8_t port; 1123 1124 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1125 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1126 1127 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1128 "ahci_tran_probe_port enter: cport: %d, " 1129 "pmport: %d, qual: %d", cport, pmport, qual); 1130 1131 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1132 1133 mutex_enter(&ahci_portp->ahciport_mutex); 1134 1135 port_state = ahci_portp->ahciport_port_state; 1136 switch (port_state) { 1137 1138 case SATA_PSTATE_FAILED: 1139 sd->satadev_state = SATA_PSTATE_FAILED; 1140 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1141 "ahci_tran_probe_port: port %d PORT FAILED", port); 1142 goto out; 1143 1144 case SATA_PSTATE_SHUTDOWN: 1145 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1146 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1147 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1148 goto out; 1149 1150 case SATA_PSTATE_PWROFF: 1151 sd->satadev_state = SATA_PSTATE_PWROFF; 1152 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1153 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1154 goto out; 1155 1156 case SATA_PSTATE_PWRON: 1157 sd->satadev_state = SATA_PSTATE_PWRON; 1158 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1159 "ahci_tran_probe_port: port %d PORT PWRON", port); 1160 break; 1161 1162 default: 1163 sd->satadev_state = port_state; 1164 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1165 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1166 port, port_state); 1167 break; 1168 } 1169 1170 device_type = ahci_portp->ahciport_device_type; 1171 1172 switch (device_type) { 1173 1174 case SATA_DTYPE_ATADISK: 1175 sd->satadev_type = SATA_DTYPE_ATADISK; 1176 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1177 "ahci_tran_probe_port: port %d DISK found", port); 1178 break; 1179 1180 case SATA_DTYPE_ATAPI: 1181 /* 1182 * HBA driver only knows it's an ATAPI device, and don't know 1183 * it's CD/DVD or tape because the ATAPI device type need to 1184 * be determined by checking IDENTIFY PACKET DEVICE data 1185 */ 1186 sd->satadev_type = SATA_DTYPE_ATAPI; 1187 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1188 "ahci_tran_probe_port: port %d ATAPI found", port); 1189 break; 1190 1191 case SATA_DTYPE_PMULT: 1192 sd->satadev_type = SATA_DTYPE_PMULT; 1193 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1194 "ahci_tran_probe_port: port %d Port Multiplier found", 1195 port); 1196 break; 1197 1198 case SATA_DTYPE_UNKNOWN: 1199 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1200 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1201 "ahci_tran_probe_port: port %d Unknown device found", port); 1202 break; 1203 1204 default: 1205 /* we don't support any other device types */ 1206 sd->satadev_type = SATA_DTYPE_NONE; 1207 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1208 "ahci_tran_probe_port: port %d No device found", port); 1209 break; 1210 } 1211 1212 out: 1213 ahci_update_sata_registers(ahci_ctlp, port, sd); 1214 mutex_exit(&ahci_portp->ahciport_mutex); 1215 1216 return (SATA_SUCCESS); 1217 } 1218 1219 /* 1220 * There are four operation modes in sata framework: 1221 * SATA_OPMODE_INTERRUPTS 1222 * SATA_OPMODE_POLLING 1223 * SATA_OPMODE_ASYNCH 1224 * SATA_OPMODE_SYNCH 1225 * 1226 * Their combined meanings as following: 1227 * 1228 * SATA_OPMODE_SYNCH 1229 * The command has to be completed before sata_tran_start functions returns. 1230 * Either interrupts or polling could be used - it's up to the driver. 1231 * Mode used currently for internal, sata-module initiated operations. 1232 * 1233 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1234 * It is the same as the one above. 1235 * 1236 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1237 * The command has to be completed before sata_tran_start function returns. 1238 * No interrupt used, polling only. This should be the mode used for scsi 1239 * packets with FLAG_NOINTR. 1240 * 1241 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1242 * The command may be queued (callback function specified). Interrupts could 1243 * be used. It's normal operation mode. 1244 */ 1245 /* 1246 * Called by sata framework to transport a sata packet down stream. 1247 */ 1248 static int 1249 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1250 { 1251 ahci_ctl_t *ahci_ctlp; 1252 ahci_port_t *ahci_portp; 1253 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1254 uint8_t port; 1255 1256 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1257 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1258 1259 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1260 "ahci_tran_start enter: cport %d satapkt 0x%p", 1261 cport, (void *)spkt); 1262 1263 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1264 1265 mutex_enter(&ahci_portp->ahciport_mutex); 1266 1267 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1268 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1269 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1270 /* 1271 * In case the targer driver would send the packet before 1272 * sata framework can have the opportunity to process those 1273 * event reports. 1274 */ 1275 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1276 spkt->satapkt_device.satadev_state = 1277 ahci_portp->ahciport_port_state; 1278 ahci_update_sata_registers(ahci_ctlp, port, 1279 &spkt->satapkt_device); 1280 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1281 "ahci_tran_start returning PORT_ERROR while " 1282 "port in FAILED/SHUTDOWN/PWROFF state: " 1283 "port: %d", port); 1284 mutex_exit(&ahci_portp->ahciport_mutex); 1285 return (SATA_TRAN_PORT_ERROR); 1286 } 1287 1288 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1289 /* 1290 * ahci_intr_phyrdy_change() may have rendered it to 1291 * SATA_DTYPE_NONE. 1292 */ 1293 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1294 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1295 spkt->satapkt_device.satadev_state = 1296 ahci_portp->ahciport_port_state; 1297 ahci_update_sata_registers(ahci_ctlp, port, 1298 &spkt->satapkt_device); 1299 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1300 "ahci_tran_start returning PORT_ERROR while " 1301 "no device attached: port: %d", port); 1302 mutex_exit(&ahci_portp->ahciport_mutex); 1303 return (SATA_TRAN_PORT_ERROR); 1304 } 1305 1306 /* 1307 * SATA HBA driver should remember that a device was reset and it 1308 * is supposed to reject any packets which do not specify either 1309 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1310 * 1311 * This is to prevent a race condition when a device was arbitrarily 1312 * reset by the HBA driver (and lost it's setting) and a target 1313 * driver sending some commands to a device before the sata framework 1314 * has a chance to restore the device setting (such as cache enable/ 1315 * disable or other resettable stuff). 1316 */ 1317 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1318 ahci_portp->ahciport_reset_in_progress = 0; 1319 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1320 "ahci_tran_start clearing the " 1321 "reset_in_progress for port: %d", port); 1322 } 1323 1324 if (ahci_portp->ahciport_reset_in_progress && 1325 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1326 ! ddi_in_panic()) { 1327 spkt->satapkt_reason = SATA_PKT_BUSY; 1328 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1329 "ahci_tran_start returning BUSY while " 1330 "reset in progress: port: %d", port); 1331 mutex_exit(&ahci_portp->ahciport_mutex); 1332 return (SATA_TRAN_BUSY); 1333 } 1334 1335 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1336 spkt->satapkt_reason = SATA_PKT_BUSY; 1337 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1338 "ahci_tran_start returning BUSY while " 1339 "mopping in progress: port: %d", port); 1340 mutex_exit(&ahci_portp->ahciport_mutex); 1341 return (SATA_TRAN_BUSY); 1342 } 1343 1344 if (spkt->satapkt_op_mode & 1345 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1346 /* 1347 * If a SYNC command to be executed in interrupt context, 1348 * bounce it back to sata module. 1349 */ 1350 if (!(spkt->satapkt_op_mode & SATA_OPMODE_POLLING) && 1351 servicing_interrupt()) { 1352 spkt->satapkt_reason = SATA_PKT_BUSY; 1353 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1354 "ahci_tran_start returning BUSY while " 1355 "sending SYNC mode under interrupt context: " 1356 "port : %d", port); 1357 mutex_exit(&ahci_portp->ahciport_mutex); 1358 return (SATA_TRAN_BUSY); 1359 } 1360 1361 /* We need to do the sync start now */ 1362 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1363 spkt) == AHCI_FAILURE) { 1364 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1365 "return QUEUE_FULL: port %d", port); 1366 mutex_exit(&ahci_portp->ahciport_mutex); 1367 return (SATA_TRAN_QUEUE_FULL); 1368 } 1369 } else { 1370 /* Async start, using interrupt */ 1371 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1372 == AHCI_FAILURE) { 1373 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1374 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1375 "returning QUEUE_FULL: port %d", port); 1376 mutex_exit(&ahci_portp->ahciport_mutex); 1377 return (SATA_TRAN_QUEUE_FULL); 1378 } 1379 } 1380 1381 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1382 "sata tran accepted: port %d", port); 1383 1384 mutex_exit(&ahci_portp->ahciport_mutex); 1385 return (SATA_TRAN_ACCEPTED); 1386 } 1387 1388 /* 1389 * SATA_OPMODE_SYNCH flag is set 1390 * 1391 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1392 * without interrupt, otherwise we can still use the interrupt. 1393 * 1394 * WARNING!!! ahciport_mutex should be acquired before the function 1395 * is called. 1396 */ 1397 static int 1398 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1399 uint8_t port, sata_pkt_t *spkt) 1400 { 1401 int pkt_timeout_ticks; 1402 uint32_t timeout_tags; 1403 int rval; 1404 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1405 1406 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1407 "port %d spkt 0x%p", port, spkt); 1408 1409 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1410 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1411 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1412 port, spkt)) == AHCI_FAILURE) { 1413 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1414 return (rval); 1415 } 1416 1417 pkt_timeout_ticks = 1418 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1419 1420 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1421 mutex_exit(&ahci_portp->ahciport_mutex); 1422 1423 /* Simulate the interrupt */ 1424 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1425 1426 drv_usecwait(AHCI_1MS_USECS); 1427 1428 mutex_enter(&ahci_portp->ahciport_mutex); 1429 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1430 if (pkt_timeout_ticks < 0) { 1431 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start " 1432 "port %d satapkt 0x%p timed out\n", 1433 instance, port, (void *)spkt); 1434 timeout_tags = (0x1 << rval); 1435 mutex_exit(&ahci_portp->ahciport_mutex); 1436 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1437 port, timeout_tags); 1438 mutex_enter(&ahci_portp->ahciport_mutex); 1439 } 1440 } 1441 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1442 return (AHCI_SUCCESS); 1443 1444 } else { 1445 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1446 port, spkt)) == AHCI_FAILURE) 1447 return (rval); 1448 1449 #if AHCI_DEBUG 1450 /* 1451 * Note that the driver always uses the slot 0 to deliver 1452 * REQUEST SENSE or READ LOG EXT command 1453 */ 1454 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1455 ASSERT(rval == 0); 1456 #endif 1457 1458 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1459 cv_wait(&ahci_portp->ahciport_cv, 1460 &ahci_portp->ahciport_mutex); 1461 1462 return (AHCI_SUCCESS); 1463 } 1464 } 1465 1466 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1467 if (satapkt) { \ 1468 satapkt->satapkt_reason = reason; \ 1469 /* \ 1470 * We set the satapkt_reason in both sync and \ 1471 * non-sync cases. \ 1472 */ \ 1473 } \ 1474 if (satapkt && \ 1475 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1476 satapkt->satapkt_comp) { \ 1477 mutex_exit(&ahci_portp->ahciport_mutex); \ 1478 (*satapkt->satapkt_comp)(satapkt); \ 1479 mutex_enter(&ahci_portp->ahciport_mutex); \ 1480 } else { \ 1481 if (satapkt && \ 1482 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1483 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1484 cv_signal(&ahci_portp->ahciport_cv); \ 1485 } 1486 1487 /* 1488 * Searches for and claims a free command slot. 1489 * 1490 * Returns: 1491 * 1492 * AHCI_FAILURE if failed 1493 * 1. if no empty slot left 1494 * 2. non-queued command requested while queued command(s) is outstanding 1495 * 3. queued command requested whild non-queued command(s) is outstanding 1496 * 4. HBA doesn't support multiple-use of command list while already a 1497 * non-queued command is oustanding 1498 * 1499 * claimed slot number if succeeded 1500 * 1501 * NOTE: it will always return slot 0 during error recovery process for 1502 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1503 * 1504 * WARNING!!! ahciport_mutex should be acquired before the function 1505 * is called. 1506 */ 1507 static int 1508 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1509 ahci_port_t *ahci_portp, int command_type) 1510 { 1511 uint32_t free_slots; 1512 int slot; 1513 1514 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1515 "ahciport_pending_tags = 0x%x " 1516 "ahciport_pending_ncq_tags = 0x%x", 1517 ahci_portp->ahciport_pending_tags, 1518 ahci_portp->ahciport_pending_ncq_tags); 1519 1520 /* 1521 * According to the AHCI spec, system software is responsible to 1522 * ensure that queued and non-queued commands are not mixed in 1523 * the command list. 1524 */ 1525 if (command_type == AHCI_NON_NCQ_CMD) { 1526 /* Non-NCQ command request */ 1527 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1528 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1529 "ahci_claim_free_slot: there is still pending " 1530 "queued command(s) in the command list, " 1531 "so no available slot for the non-queued " 1532 "command"); 1533 return (AHCI_FAILURE); 1534 } 1535 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1536 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1537 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1538 "ahci_claim_free_slot: HBA cannot support multiple-" 1539 "use of the command list for non-queued commands"); 1540 return (AHCI_FAILURE); 1541 } 1542 free_slots = (~ahci_portp->ahciport_pending_tags) & 1543 AHCI_SLOT_MASK(ahci_ctlp); 1544 } else if (command_type == AHCI_NCQ_CMD) { 1545 /* NCQ command request */ 1546 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1547 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1548 "ahci_claim_free_slot: there is still pending " 1549 "non-queued command(s) in the command list, " 1550 "so no available slot for the queued command"); 1551 return (AHCI_FAILURE); 1552 } 1553 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1554 AHCI_NCQ_SLOT_MASK(ahci_portp); 1555 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1556 /* Error retrieval command request */ 1557 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1558 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1559 "SENSE or READ LOG EXT command"); 1560 slot = 0; 1561 goto out; 1562 } 1563 1564 slot = ddi_ffs(free_slots) - 1; 1565 if (slot == -1) { 1566 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1567 "ahci_claim_free_slot: no empty slots"); 1568 return (AHCI_FAILURE); 1569 } 1570 1571 /* 1572 * According to the AHCI spec, to allow a simple mechanism for the 1573 * HBA to map command list slots to queue entries, software must 1574 * match the tag number it uses to the slot it is placing the command 1575 * in. For example, if a queued command is placed in slot 5, the tag 1576 * for that command must be 5. 1577 */ 1578 if (command_type == AHCI_NCQ_CMD) { 1579 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1580 } 1581 1582 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1583 1584 out: 1585 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1586 "ahci_claim_free_slot: found slot: 0x%x", slot); 1587 1588 return (slot); 1589 } 1590 1591 /* 1592 * Builds the Command Table for the sata packet and delivers it to controller. 1593 * 1594 * Returns: 1595 * slot number if we can obtain a slot successfully 1596 * otherwise, return AHCI_FAILURE 1597 * 1598 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1599 */ 1600 static int 1601 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1602 uint8_t port, sata_pkt_t *spkt) 1603 { 1604 int cmd_slot; 1605 sata_cmd_t *scmd; 1606 ahci_fis_h2d_register_t *h2d_register_fisp; 1607 ahci_cmd_table_t *cmd_table; 1608 ahci_cmd_header_t *cmd_header; 1609 int ncookies; 1610 int i; 1611 int command_type = AHCI_NON_NCQ_CMD; 1612 int ncq_qdepth; 1613 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1614 #if AHCI_DEBUG 1615 uint32_t *ptr; 1616 uint8_t *ptr2; 1617 #endif 1618 1619 spkt->satapkt_reason = SATA_PKT_BUSY; 1620 1621 scmd = &spkt->satapkt_cmd; 1622 1623 /* Check if the command is a NCQ command */ 1624 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1625 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1626 command_type = AHCI_NCQ_CMD; 1627 1628 /* 1629 * When NCQ is support, system software must determine the 1630 * maximum tag allowed by the device and the HBA, and it 1631 * must use a value not beyond of the lower bound of the two. 1632 * 1633 * Sata module is going to calculate the qdepth and send 1634 * down to HBA driver via sata_cmd. 1635 */ 1636 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1637 1638 /* 1639 * At the moment, the driver doesn't support the dynamic 1640 * setting of the maximum ncq depth, and the value can be 1641 * set either during the attach or after hot-plug insertion. 1642 */ 1643 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1644 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1645 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1646 "ahci_deliver_satapkt: port %d the max tags for " 1647 "NCQ command is %d", port, ncq_qdepth); 1648 } else { 1649 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1650 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt" 1651 " port %d the max tag for NCQ command is " 1652 "requested to change from %d to %d, at the" 1653 " moment the driver doesn't support the " 1654 "dynamic change so it's going to " 1655 "still use the previous tag value", 1656 instance, port, 1657 ahci_portp->ahciport_max_ncq_tags, 1658 ncq_qdepth); 1659 } 1660 } 1661 } 1662 1663 /* Check if the command is an error retrieval command */ 1664 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1665 command_type = AHCI_ERR_RETRI_CMD; 1666 1667 /* Check if there is an empty command slot */ 1668 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1669 if (cmd_slot == AHCI_FAILURE) { 1670 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1671 return (AHCI_FAILURE); 1672 } 1673 1674 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1675 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1676 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1677 cmd_slot, port, (void *)spkt); 1678 1679 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1680 bzero((void *)cmd_table, ahci_cmd_table_size); 1681 1682 /* For data transfer operations, it is the H2D Register FIS */ 1683 h2d_register_fisp = 1684 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1685 1686 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1687 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1688 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1689 SET_FIS_PMP(h2d_register_fisp, 1690 spkt->satapkt_device.satadev_addr.pmport); 1691 } 1692 1693 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1694 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1695 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1696 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1697 1698 switch (scmd->satacmd_addr_type) { 1699 1700 case 0: 1701 /* 1702 * satacmd_addr_type will be 0 for the commands below: 1703 * ATAPI command 1704 * SATAC_IDLE_IM 1705 * SATAC_STANDBY_IM 1706 * SATAC_DOWNLOAD_MICROCODE 1707 * SATAC_FLUSH_CACHE 1708 * SATAC_SET_FEATURES 1709 * SATAC_SMART 1710 * SATAC_ID_PACKET_DEVICE 1711 * SATAC_ID_DEVICE 1712 */ 1713 /* FALLTHRU */ 1714 1715 case ATA_ADDR_LBA: 1716 /* FALLTHRU */ 1717 1718 case ATA_ADDR_LBA28: 1719 /* LBA[7:0] */ 1720 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1721 1722 /* LBA[15:8] */ 1723 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1724 1725 /* LBA[23:16] */ 1726 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1727 1728 /* LBA [27:24] (also called dev_head) */ 1729 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1730 1731 break; 1732 1733 case ATA_ADDR_LBA48: 1734 /* LBA[7:0] */ 1735 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1736 1737 /* LBA[15:8] */ 1738 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1739 1740 /* LBA[23:16] */ 1741 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1742 1743 /* LBA [31:24] */ 1744 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1745 scmd->satacmd_lba_low_msb); 1746 1747 /* LBA [39:32] */ 1748 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1749 scmd->satacmd_lba_mid_msb); 1750 1751 /* LBA [47:40] */ 1752 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1753 scmd->satacmd_lba_high_msb); 1754 1755 /* Set dev_head */ 1756 SET_FIS_DEV_HEAD(h2d_register_fisp, 1757 scmd->satacmd_device_reg); 1758 1759 /* Set the extended sector count and features */ 1760 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1761 scmd->satacmd_sec_count_msb); 1762 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1763 scmd->satacmd_features_reg_ext); 1764 break; 1765 } 1766 1767 /* 1768 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1769 * filled into features field, and sector count 8:15 is filled into 1770 * features (exp) field. TAG is filled into sector field. 1771 */ 1772 if (command_type == AHCI_NCQ_CMD) { 1773 SET_FIS_FEATURES(h2d_register_fisp, 1774 scmd->satacmd_sec_count_lsb); 1775 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1776 scmd->satacmd_sec_count_msb); 1777 1778 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1779 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1780 } 1781 1782 ncookies = scmd->satacmd_num_dma_cookies; 1783 AHCIDBG2(AHCIDBG_PRDT, ahci_ctlp, 1784 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1785 ncookies, ahci_dma_prdt_number); 1786 1787 ASSERT(ncookies <= ahci_dma_prdt_number); 1788 ahci_portp->ahciport_prd_bytecounts[cmd_slot] = 0; 1789 1790 /* *** now fill the scatter gather list ******* */ 1791 for (i = 0; i < ncookies; i++) { 1792 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1793 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1794 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1795 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1796 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1797 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1798 ahci_portp->ahciport_prd_bytecounts[cmd_slot] += 1799 scmd->satacmd_dma_cookie_list[i].dmac_size; 1800 } 1801 1802 AHCIDBG2(AHCIDBG_PRDT, ahci_ctlp, 1803 "ahciport_prd_bytecounts 0x%x for cmd_slot 0x%x", 1804 ahci_portp->ahciport_prd_bytecounts[cmd_slot], cmd_slot); 1805 1806 /* The ACMD field is filled in for ATAPI command */ 1807 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1808 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1809 SATA_ATAPI_MAX_CDB_LEN); 1810 } 1811 1812 /* Set Command Header in Command List */ 1813 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1814 BZERO_DESCR_INFO(cmd_header); 1815 BZERO_PRD_BYTE_COUNT(cmd_header); 1816 1817 /* Set the number of entries in the PRD table */ 1818 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1819 1820 /* Set the length of the command in the CFIS area */ 1821 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1822 1823 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1824 "sata_data_direction = 0x%x", 1825 scmd->satacmd_flags.sata_data_direction); 1826 1827 /* Set A bit if it is an ATAPI command */ 1828 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1829 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1830 1831 /* Set W bit if data is going to the device */ 1832 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1833 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1834 1835 /* 1836 * Set the prefetchable bit - this bit is only valid if the PRDTL 1837 * field is non-zero or the ATAPI 'A' bit is set in the command 1838 * header. This bit cannot be set when using native command 1839 * queuing commands or when using FIS-based switching with a Port 1840 * multiplier. 1841 */ 1842 if (command_type != AHCI_NCQ_CMD) 1843 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1844 1845 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1846 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1847 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1848 1849 /* 1850 * We are overloading satapkt_hba_driver_private with 1851 * watched_cycle count. 1852 */ 1853 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1854 1855 #if AHCI_DEBUG 1856 if (ahci_debug_flags & AHCIDBG_ATACMD && 1857 scmd->satacmd_cmd_reg != SATAC_PACKET || 1858 ahci_debug_flags & AHCIDBG_ATAPICMD && 1859 scmd->satacmd_cmd_reg == SATAC_PACKET) { 1860 1861 /* Dump the command header and table */ 1862 ahci_log(ahci_ctlp, CE_WARN, "\n"); 1863 ahci_log(ahci_ctlp, CE_WARN, "Command header&table for spkt " 1864 "0x%p cmd_reg 0x%x port %d", spkt, 1865 scmd->satacmd_cmd_reg, port); 1866 ptr = (uint32_t *)cmd_header; 1867 ahci_log(ahci_ctlp, CE_WARN, 1868 " Command Header:%8x %8x %8x %8x", 1869 ptr[0], ptr[1], ptr[2], ptr[3]); 1870 1871 /* Dump the H2D register FIS */ 1872 ptr = (uint32_t *)h2d_register_fisp; 1873 ahci_log(ahci_ctlp, CE_WARN, 1874 " Command FIS: %8x %8x %8x %8x", 1875 ptr[0], ptr[1], ptr[2], ptr[3]); 1876 1877 /* Dump the ACMD register FIS */ 1878 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1879 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1880 if (ahci_debug_flags & AHCIDBG_ATAPICMD) 1881 ahci_log(ahci_ctlp, CE_WARN, 1882 " ATAPI command: %2x %2x %2x %2x " 1883 "%2x %2x %2x %2x", 1884 ptr2[8 * i], ptr2[8 * i + 1], 1885 ptr2[8 * i + 2], ptr2[8 * i + 3], 1886 ptr2[8 * i + 4], ptr2[8 * i + 5], 1887 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1888 1889 /* Dump the PRDT */ 1890 for (i = 0; i < ncookies; i++) { 1891 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1892 ahci_log(ahci_ctlp, CE_WARN, 1893 " Cookie %d: %8x %8x %8x %8x", 1894 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1895 } 1896 } 1897 #endif 1898 1899 (void) ddi_dma_sync( 1900 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1901 0, 1902 ahci_cmd_table_size, 1903 DDI_DMA_SYNC_FORDEV); 1904 1905 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1906 cmd_slot * sizeof (ahci_cmd_header_t), 1907 sizeof (ahci_cmd_header_t), 1908 DDI_DMA_SYNC_FORDEV); 1909 1910 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1911 if (command_type == AHCI_NCQ_CMD) { 1912 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1913 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1914 (0x1 << cmd_slot)); 1915 } 1916 1917 /* Indicate to the HBA that a command is active. */ 1918 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1919 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1920 (0x1 << cmd_slot)); 1921 1922 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1923 "exit: port %d", port); 1924 1925 return (cmd_slot); 1926 } 1927 1928 /* 1929 * Called by the sata framework to abort the previously sent packet(s). 1930 * 1931 * Reset device to abort commands. 1932 */ 1933 static int 1934 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1935 { 1936 ahci_ctl_t *ahci_ctlp; 1937 ahci_port_t *ahci_portp; 1938 uint32_t slot_status = 0; 1939 uint32_t aborted_tags = 0; 1940 uint32_t finished_tags = 0; 1941 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1942 uint8_t port; 1943 int tmp_slot; 1944 int instance = ddi_get_instance(dip); 1945 1946 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 1947 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1948 1949 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1950 "ahci_tran_abort enter: port %d", port); 1951 1952 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1953 mutex_enter(&ahci_portp->ahciport_mutex); 1954 1955 /* 1956 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1957 * commands are being mopped, therefore there is nothing else to do 1958 */ 1959 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1960 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1961 "ahci_tran_abort: port %d is in " 1962 "mopping process, so just return directly ", port); 1963 mutex_exit(&ahci_portp->ahciport_mutex); 1964 return (SATA_SUCCESS); 1965 } 1966 1967 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1968 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1969 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1970 /* 1971 * In case the targer driver would send the request before 1972 * sata framework can have the opportunity to process those 1973 * event reports. 1974 */ 1975 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1976 spkt->satapkt_device.satadev_state = 1977 ahci_portp->ahciport_port_state; 1978 ahci_update_sata_registers(ahci_ctlp, port, 1979 &spkt->satapkt_device); 1980 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1981 "ahci_tran_abort returning SATA_FAILURE while " 1982 "port in FAILED/SHUTDOWN/PWROFF state: " 1983 "port: %d", port); 1984 mutex_exit(&ahci_portp->ahciport_mutex); 1985 return (SATA_FAILURE); 1986 } 1987 1988 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1989 /* 1990 * ahci_intr_phyrdy_change() may have rendered it to 1991 * AHCI_PORT_TYPE_NODEV. 1992 */ 1993 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1994 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1995 spkt->satapkt_device.satadev_state = 1996 ahci_portp->ahciport_port_state; 1997 ahci_update_sata_registers(ahci_ctlp, port, 1998 &spkt->satapkt_device); 1999 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2000 "ahci_tran_abort returning SATA_FAILURE while " 2001 "no device attached: port: %d", port); 2002 mutex_exit(&ahci_portp->ahciport_mutex); 2003 return (SATA_FAILURE); 2004 } 2005 2006 if (flag == SATA_ABORT_ALL_PACKETS) { 2007 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2008 aborted_tags = ahci_portp->ahciport_pending_tags; 2009 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2010 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 2011 2012 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets", 2013 instance, port); 2014 } else { 2015 aborted_tags = 0xffffffff; 2016 /* 2017 * Aborting one specific packet, first search the 2018 * ahciport_slot_pkts[] list for matching spkt. 2019 */ 2020 for (tmp_slot = 0; 2021 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 2022 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 2023 aborted_tags = (0x1 << tmp_slot); 2024 break; 2025 } 2026 } 2027 2028 if (aborted_tags == 0xffffffff) { 2029 /* request packet is not on the pending list */ 2030 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2031 "Cannot find the aborting pkt 0x%p on the " 2032 "pending list", (void *)spkt); 2033 ahci_update_sata_registers(ahci_ctlp, port, 2034 &spkt->satapkt_device); 2035 mutex_exit(&ahci_portp->ahciport_mutex); 2036 return (SATA_FAILURE); 2037 } 2038 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p", 2039 instance, port, (void *)spkt); 2040 } 2041 2042 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2043 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2044 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2045 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2046 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2047 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2048 2049 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2050 ahci_portp->ahciport_mop_in_progress++; 2051 2052 /* 2053 * To abort the packet(s), first we are trying to clear PxCMD.ST 2054 * to stop the port, and if the port can be stopped 2055 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 2056 * then we just send back the aborted packet(s) with ABORTED flag 2057 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 2058 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 2059 * perform a COMRESET. 2060 */ 2061 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2062 ahci_portp, port, NULL, NULL); 2063 2064 /* 2065 * Compute which have finished and which need to be retried. 2066 * 2067 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 2068 * minus the slot_status. The aborted_tags has to be deducted by 2069 * finished_tags since we can't possibly abort a tag which had finished 2070 * already. 2071 */ 2072 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2073 finished_tags = ahci_portp->ahciport_pending_tags & 2074 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2075 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2076 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2077 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2078 2079 aborted_tags &= ~finished_tags; 2080 2081 ahci_mop_commands(ahci_ctlp, 2082 ahci_portp, 2083 slot_status, 2084 0, /* failed tags */ 2085 0, /* timeout tags */ 2086 aborted_tags, 2087 0); /* reset tags */ 2088 2089 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2090 mutex_exit(&ahci_portp->ahciport_mutex); 2091 2092 return (SATA_SUCCESS); 2093 } 2094 2095 /* 2096 * Used to do device reset and reject all the pending packets on a device 2097 * during the reset operation. 2098 * 2099 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2100 */ 2101 static int 2102 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2103 ahci_port_t *ahci_portp, uint8_t port) 2104 { 2105 uint32_t slot_status = 0; 2106 uint32_t reset_tags = 0; 2107 uint32_t finished_tags = 0; 2108 sata_device_t sdevice; 2109 int ret; 2110 2111 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2112 "ahci_reset_device_reject_pkts on port: %d", port); 2113 2114 /* 2115 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2116 * commands are being mopped, therefore there is nothing else to do 2117 */ 2118 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2119 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2120 "ahci_reset_device_reject_pkts: port %d is in " 2121 "mopping process, so return directly ", port); 2122 return (SATA_SUCCESS); 2123 } 2124 2125 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2126 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2127 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2128 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2129 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2130 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2131 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2132 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2133 } 2134 2135 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2136 != AHCI_SUCCESS) { 2137 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2138 "Try to do a port reset after software " 2139 "reset failed", port); 2140 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2141 if (ret != AHCI_SUCCESS) { 2142 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2143 "ahci_reset_device_reject_pkts: port %d " 2144 "failed", port); 2145 return (SATA_FAILURE); 2146 } 2147 } 2148 /* Set the reset in progress flag */ 2149 ahci_portp->ahciport_reset_in_progress = 1; 2150 2151 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2152 ahci_portp->ahciport_mop_in_progress++; 2153 2154 /* Indicate to the framework that a reset has happened */ 2155 bzero((void *)&sdevice, sizeof (sata_device_t)); 2156 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2157 sdevice.satadev_addr.pmport = 0; 2158 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2159 2160 sdevice.satadev_state = SATA_DSTATE_RESET | 2161 SATA_DSTATE_PWR_ACTIVE; 2162 mutex_exit(&ahci_portp->ahciport_mutex); 2163 sata_hba_event_notify( 2164 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2165 &sdevice, 2166 SATA_EVNT_DEVICE_RESET); 2167 mutex_enter(&ahci_portp->ahciport_mutex); 2168 2169 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2170 "port %d sending event up: SATA_EVNT_RESET", port); 2171 2172 /* Next try to mop the pending commands */ 2173 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2174 finished_tags = ahci_portp->ahciport_pending_tags & 2175 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2176 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2177 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2178 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2179 2180 reset_tags &= ~finished_tags; 2181 2182 ahci_mop_commands(ahci_ctlp, 2183 ahci_portp, 2184 slot_status, 2185 0, /* failed tags */ 2186 0, /* timeout tags */ 2187 0, /* aborted tags */ 2188 reset_tags); /* reset tags */ 2189 2190 return (SATA_SUCCESS); 2191 } 2192 2193 /* 2194 * Used to do port reset and reject all the pending packets on a port during 2195 * the reset operation. 2196 * 2197 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2198 */ 2199 static int 2200 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2201 ahci_port_t *ahci_portp, uint8_t port) 2202 { 2203 uint32_t slot_status = 0; 2204 uint32_t reset_tags = 0; 2205 uint32_t finished_tags = 0; 2206 2207 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2208 "ahci_reset_port_reject_pkts on port: %d", port); 2209 2210 /* 2211 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2212 * commands are being mopped, therefore there is nothing else to do 2213 */ 2214 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2215 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2216 "ahci_reset_port_reject_pkts: port %d is in " 2217 "mopping process, so return directly ", port); 2218 return (SATA_SUCCESS); 2219 } 2220 2221 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2222 ahci_portp->ahciport_mop_in_progress++; 2223 2224 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2225 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2226 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2227 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2228 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2229 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2230 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2231 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2232 } 2233 2234 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2235 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2236 NULL) != AHCI_SUCCESS) 2237 return (SATA_FAILURE); 2238 2239 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2240 finished_tags = ahci_portp->ahciport_pending_tags & 2241 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2242 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2243 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2244 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2245 2246 reset_tags &= ~finished_tags; 2247 2248 ahci_mop_commands(ahci_ctlp, 2249 ahci_portp, 2250 slot_status, 2251 0, /* failed tags */ 2252 0, /* timeout tags */ 2253 0, /* aborted tags */ 2254 reset_tags); /* reset tags */ 2255 2256 return (SATA_SUCCESS); 2257 } 2258 2259 /* 2260 * Used to do hba reset and reject all the pending packets on all ports 2261 * during the reset operation. 2262 */ 2263 static int 2264 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2265 { 2266 ahci_port_t *ahci_portp; 2267 uint32_t slot_status[AHCI_MAX_PORTS]; 2268 uint32_t reset_tags[AHCI_MAX_PORTS]; 2269 uint32_t finished_tags[AHCI_MAX_PORTS]; 2270 uint8_t port; 2271 int ret = SATA_SUCCESS; 2272 2273 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2274 "ahci_reset_hba_reject_pkts enter"); 2275 2276 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2277 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2278 continue; 2279 } 2280 2281 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2282 2283 mutex_enter(&ahci_portp->ahciport_mutex); 2284 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2285 slot_status[port] = ddi_get32( 2286 ahci_ctlp->ahcictl_ahci_acc_handle, 2287 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2288 reset_tags[port] = slot_status[port] & 2289 AHCI_SLOT_MASK(ahci_ctlp); 2290 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2291 slot_status[port] = ddi_get32( 2292 ahci_ctlp->ahcictl_ahci_acc_handle, 2293 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2294 reset_tags[port] = slot_status[port] & 2295 AHCI_NCQ_SLOT_MASK(ahci_portp); 2296 } 2297 mutex_exit(&ahci_portp->ahciport_mutex); 2298 } 2299 2300 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2301 ret = SATA_FAILURE; 2302 goto out; 2303 } 2304 2305 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2306 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2307 continue; 2308 } 2309 2310 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2311 2312 mutex_enter(&ahci_portp->ahciport_mutex); 2313 /* 2314 * To prevent recursive enter to ahci_mop_commands, we need 2315 * check AHCI_PORT_FLAG_MOPPING flag. 2316 */ 2317 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2318 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2319 "ahci_reset_hba_reject_pkts: port %d is in " 2320 "mopping process, so return directly ", port); 2321 mutex_exit(&ahci_portp->ahciport_mutex); 2322 continue; 2323 } 2324 2325 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2326 ahci_portp->ahciport_mop_in_progress++; 2327 2328 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2329 finished_tags[port] = 2330 ahci_portp->ahciport_pending_tags & 2331 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2332 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2333 finished_tags[port] = 2334 ahci_portp->ahciport_pending_ncq_tags & 2335 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2336 2337 reset_tags[port] &= ~finished_tags[port]; 2338 2339 ahci_mop_commands(ahci_ctlp, 2340 ahci_portp, 2341 slot_status[port], 2342 0, /* failed tags */ 2343 0, /* timeout tags */ 2344 0, /* aborted tags */ 2345 reset_tags[port]); /* reset tags */ 2346 mutex_exit(&ahci_portp->ahciport_mutex); 2347 } 2348 out: 2349 return (ret); 2350 } 2351 2352 /* 2353 * Called by sata framework to reset a port(s) or device. 2354 */ 2355 static int 2356 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2357 { 2358 ahci_ctl_t *ahci_ctlp; 2359 ahci_port_t *ahci_portp; 2360 uint8_t cport = sd->satadev_addr.cport; 2361 uint8_t port; 2362 int ret = SATA_SUCCESS; 2363 int instance = ddi_get_instance(dip); 2364 2365 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2366 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2367 2368 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2369 "ahci_tran_reset_port enter: cport: %d", cport); 2370 2371 switch (sd->satadev_addr.qual) { 2372 case SATA_ADDR_CPORT: 2373 /* Port reset */ 2374 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2375 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2376 "reset port", instance, port); 2377 2378 mutex_enter(&ahci_portp->ahciport_mutex); 2379 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2380 mutex_exit(&ahci_portp->ahciport_mutex); 2381 2382 break; 2383 2384 case SATA_ADDR_DCPORT: 2385 /* Device reset */ 2386 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2387 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2388 "reset device", instance, port); 2389 2390 mutex_enter(&ahci_portp->ahciport_mutex); 2391 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2392 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2393 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2394 /* 2395 * In case the targer driver would send the request 2396 * before sata framework can have the opportunity to 2397 * process those event reports. 2398 */ 2399 sd->satadev_state = ahci_portp->ahciport_port_state; 2400 ahci_update_sata_registers(ahci_ctlp, port, sd); 2401 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2402 "ahci_tran_reset_dport returning SATA_FAILURE " 2403 "while port in FAILED/SHUTDOWN/PWROFF state: " 2404 "port: %d", port); 2405 mutex_exit(&ahci_portp->ahciport_mutex); 2406 ret = SATA_FAILURE; 2407 break; 2408 } 2409 2410 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2411 /* 2412 * ahci_intr_phyrdy_change() may have rendered it to 2413 * AHCI_PORT_TYPE_NODEV. 2414 */ 2415 sd->satadev_type = SATA_DTYPE_NONE; 2416 sd->satadev_state = ahci_portp->ahciport_port_state; 2417 ahci_update_sata_registers(ahci_ctlp, port, sd); 2418 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2419 "ahci_tran_reset_dport returning SATA_FAILURE " 2420 "while no device attached: port: %d", port); 2421 mutex_exit(&ahci_portp->ahciport_mutex); 2422 ret = SATA_FAILURE; 2423 break; 2424 } 2425 2426 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2427 ahci_portp, port); 2428 mutex_exit(&ahci_portp->ahciport_mutex); 2429 break; 2430 2431 case SATA_ADDR_CNTRL: 2432 /* Reset the whole controller */ 2433 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2434 "reset the whole hba", instance, port); 2435 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2436 break; 2437 2438 case SATA_ADDR_PMPORT: 2439 case SATA_ADDR_DPMPORT: 2440 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2441 "ahci_tran_reset_dport: port multiplier will be " 2442 "supported later"); 2443 /* FALLTHRU */ 2444 default: 2445 ret = SATA_FAILURE; 2446 } 2447 2448 return (ret); 2449 } 2450 2451 /* 2452 * Called by sata framework to activate a port as part of hotplug. 2453 * (cfgadm -c connect satax/y) 2454 * Note: Not port-mult aware. 2455 */ 2456 static int 2457 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2458 { 2459 ahci_ctl_t *ahci_ctlp; 2460 ahci_port_t *ahci_portp; 2461 uint8_t cport = satadev->satadev_addr.cport; 2462 uint8_t port; 2463 int instance = ddi_get_instance(dip); 2464 2465 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2466 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2467 2468 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2469 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2470 2471 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2472 2473 mutex_enter(&ahci_portp->ahciport_mutex); 2474 ahci_enable_port_intrs(ahci_ctlp, port); 2475 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated", instance, port); 2476 2477 /* 2478 * Reset the port so that the PHY communication would be re-established. 2479 * But this reset is an internal operation and the sata module doesn't 2480 * need to know about it. Moreover, the port with a device attached will 2481 * be started too. 2482 */ 2483 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2484 ahci_portp, port, 2485 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2486 NULL); 2487 2488 /* 2489 * Need to check the link status and device status of the port 2490 * and consider raising power if the port was in D3 state 2491 */ 2492 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2493 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2494 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2495 2496 satadev->satadev_state = ahci_portp->ahciport_port_state; 2497 2498 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2499 2500 mutex_exit(&ahci_portp->ahciport_mutex); 2501 return (SATA_SUCCESS); 2502 } 2503 2504 /* 2505 * Called by sata framework to deactivate a port as part of hotplug. 2506 * (cfgadm -c disconnect satax/y) 2507 * Note: Not port-mult aware. 2508 */ 2509 static int 2510 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2511 { 2512 ahci_ctl_t *ahci_ctlp; 2513 ahci_port_t *ahci_portp; 2514 uint8_t cport = satadev->satadev_addr.cport; 2515 uint8_t port; 2516 uint32_t port_scontrol; 2517 int instance = ddi_get_instance(dip); 2518 2519 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2520 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2521 2522 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2523 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2524 2525 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2526 2527 mutex_enter(&ahci_portp->ahciport_mutex); 2528 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated", 2529 instance, port); 2530 2531 /* Disable the interrupts on the port */ 2532 ahci_disable_port_intrs(ahci_ctlp, port); 2533 2534 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2535 goto phy_offline; 2536 } 2537 2538 /* First to abort all the pending commands */ 2539 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2540 2541 /* Then stop the port */ 2542 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2543 ahci_portp, port); 2544 2545 /* Next put the PHY offline */ 2546 2547 phy_offline: 2548 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2549 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2550 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2551 2552 /* Update ahciport_port_state */ 2553 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2554 satadev->satadev_state = ahci_portp->ahciport_port_state; 2555 2556 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2557 2558 mutex_exit(&ahci_portp->ahciport_mutex); 2559 return (SATA_SUCCESS); 2560 } 2561 2562 /* 2563 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2564 * when a device is unplugged or a port is deactivated. 2565 * 2566 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2567 */ 2568 static void 2569 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2570 ahci_port_t *ahci_portp, uint8_t port) 2571 { 2572 uint32_t slot_status = 0; 2573 uint32_t abort_tags = 0; 2574 2575 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2576 "ahci_reject_all_abort_pkts on port: %d", port); 2577 2578 /* 2579 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2580 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2581 * to get the error data, if yes when the device is removed, the 2582 * command needs to be aborted too. 2583 */ 2584 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2585 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2586 slot_status = 0x1; 2587 abort_tags = 0x1; 2588 goto out; 2589 } else { 2590 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2591 "ahci_reject_all_abort_pkts return directly " 2592 "port %d no needs to reject any outstanding " 2593 "commands", port); 2594 return; 2595 } 2596 } 2597 2598 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2599 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2600 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2601 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2602 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2603 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2604 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2605 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2606 } 2607 2608 out: 2609 /* No need to do mop when there is no outstanding commands */ 2610 if (slot_status != 0) { 2611 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2612 ahci_portp->ahciport_mop_in_progress++; 2613 2614 ahci_mop_commands(ahci_ctlp, 2615 ahci_portp, 2616 slot_status, 2617 0, /* failed tags */ 2618 0, /* timeout tags */ 2619 abort_tags, /* aborting tags */ 2620 0); /* reset tags */ 2621 } 2622 } 2623 2624 #if defined(__lock_lint) 2625 static int 2626 ahci_selftest(dev_info_t *dip, sata_device_t *device) 2627 { 2628 return (SATA_SUCCESS); 2629 } 2630 #endif 2631 2632 /* 2633 * Allocate the ports structure, only called by ahci_attach 2634 */ 2635 static int 2636 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2637 { 2638 int port, cport = 0; 2639 2640 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2641 "ahci_alloc_ports_state enter"); 2642 2643 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2644 2645 /* Allocate structures only for the implemented ports */ 2646 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2647 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2648 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2649 "hba port %d not implemented", port); 2650 continue; 2651 } 2652 2653 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2654 ahci_ctlp->ahcictl_port_to_cport[port] = 2655 (uint8_t)cport++; 2656 2657 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2658 goto err_out; 2659 } 2660 } 2661 2662 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2663 return (AHCI_SUCCESS); 2664 2665 err_out: 2666 for (port--; port >= 0; port--) { 2667 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2668 ahci_dealloc_port_state(ahci_ctlp, port); 2669 } 2670 } 2671 2672 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2673 return (AHCI_FAILURE); 2674 } 2675 2676 /* 2677 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2678 */ 2679 static void 2680 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2681 { 2682 int port; 2683 2684 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2685 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2686 /* if this port is implemented by the HBA */ 2687 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2688 ahci_dealloc_port_state(ahci_ctlp, port); 2689 } 2690 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2691 } 2692 2693 /* 2694 * Initialize the controller and all ports. And then try to start the ports 2695 * if there are devices attached. 2696 * 2697 * This routine can be called from three seperate cases: DDI_ATTACH, 2698 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2699 * other two cases; device signature probing are attempted only during 2700 * DDI_ATTACH case. 2701 * 2702 * WARNING!!! Disable the whole controller's interrupts before calling and 2703 * the interrupts will be enabled upon successfully return. 2704 */ 2705 static int 2706 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2707 { 2708 ahci_port_t *ahci_portp; 2709 uint32_t ghc_control; 2710 int port; 2711 2712 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2713 "ahci_initialize_controller enter"); 2714 2715 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2716 2717 /* 2718 * Indicate that system software is AHCI aware by setting 2719 * GHC.AE to 1 2720 */ 2721 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2722 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2723 2724 ghc_control |= AHCI_HBA_GHC_AE; 2725 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2726 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2727 ghc_control); 2728 2729 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2730 2731 /* Initialize the implemented ports and structures */ 2732 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2733 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2734 continue; 2735 } 2736 2737 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2738 mutex_enter(&ahci_portp->ahciport_mutex); 2739 2740 /* 2741 * Ensure that the controller is not in the running state 2742 * by checking every implemented port's PxCMD register 2743 */ 2744 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2745 != AHCI_SUCCESS) { 2746 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2747 "ahci_initialize_controller: failed to " 2748 "initialize port %d", port); 2749 /* 2750 * Set the port state to SATA_PSTATE_FAILED if 2751 * failed to initialize it. 2752 */ 2753 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2754 } 2755 2756 mutex_exit(&ahci_portp->ahciport_mutex); 2757 } 2758 2759 /* Enable the whole controller interrupts */ 2760 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2761 ahci_enable_all_intrs(ahci_ctlp); 2762 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2763 2764 return (AHCI_SUCCESS); 2765 } 2766 2767 /* 2768 * Reverse of ahci_initialize_controller() 2769 * 2770 * We only need to stop the ports and disable the interrupt. 2771 */ 2772 static void 2773 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2774 { 2775 ahci_port_t *ahci_portp; 2776 int port; 2777 2778 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2779 "ahci_uninitialize_controller enter"); 2780 2781 /* disable all the interrupts. */ 2782 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2783 ahci_disable_all_intrs(ahci_ctlp); 2784 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2785 2786 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2787 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2788 continue; 2789 } 2790 2791 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2792 2793 /* Stop the port by clearing PxCMD.ST */ 2794 mutex_enter(&ahci_portp->ahciport_mutex); 2795 2796 /* 2797 * Here we must disable the port interrupt because 2798 * ahci_disable_all_intrs only clear GHC.IE, and IS 2799 * register will be still set if PxIE is enabled. 2800 * When ahci shares one IRQ with other drivers, the 2801 * intr handler may claim the intr mistakenly. 2802 */ 2803 ahci_disable_port_intrs(ahci_ctlp, port); 2804 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2805 ahci_portp, port); 2806 mutex_exit(&ahci_portp->ahciport_mutex); 2807 } 2808 } 2809 2810 /* 2811 * The routine is to initialize the port. First put the port in NOTRunning 2812 * state, then enable port interrupt and clear Serror register. And under 2813 * AHCI_ATTACH case, find device signature and then try to start the port. 2814 * 2815 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2816 */ 2817 static int 2818 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2819 ahci_port_t *ahci_portp, uint8_t port) 2820 { 2821 uint32_t port_cmd_status; 2822 2823 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2824 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2825 2826 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2827 "ahci_initialize_port: port %d " 2828 "port_cmd_status = 0x%x", port, port_cmd_status); 2829 /* 2830 * Check whether the port is in NotRunning state, if not, 2831 * put the port in NotRunning state 2832 */ 2833 if (!(port_cmd_status & 2834 (AHCI_CMD_STATUS_ST | 2835 AHCI_CMD_STATUS_CR | 2836 AHCI_CMD_STATUS_FRE | 2837 AHCI_CMD_STATUS_FR))) { 2838 2839 goto next; 2840 } 2841 2842 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2843 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2844 return (AHCI_FAILURE); 2845 2846 next: 2847 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2848 "port %d is in NotRunning state now", port); 2849 2850 /* 2851 * At the time being, only probe ports/devices and get the types of 2852 * attached devices during DDI_ATTACH. In fact, the device can be 2853 * changed during power state changes, but at the time being, we 2854 * don't support the situation. 2855 */ 2856 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2857 /* Try to get the device signature */ 2858 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2859 } else { 2860 2861 /* 2862 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 2863 * and PxFBU registers in case these registers were cleared 2864 * during the suspend. 2865 */ 2866 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2867 "ahci_initialize_port: port %d " 2868 "reset the port during resume", port); 2869 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 2870 2871 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2872 "ahci_initialize_port: port %d " 2873 "set PxCLB, PxCLBU, PxFB and PxFBU " 2874 "during resume", port); 2875 2876 /* Config Port Received FIS Base Address */ 2877 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2878 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 2879 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 2880 2881 /* Config Port Command List Base Address */ 2882 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2883 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 2884 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 2885 } 2886 2887 /* Disable the interface power management */ 2888 ahci_disable_interface_pm(ahci_ctlp, port); 2889 2890 /* Return directly if no device connected */ 2891 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2892 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2893 "No device connected to port %d", port); 2894 goto out; 2895 } 2896 2897 /* Try to start the port */ 2898 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2899 != AHCI_SUCCESS) { 2900 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2901 "failed to start port %d", port); 2902 return (AHCI_FAILURE); 2903 } 2904 out: 2905 /* Enable port interrupts */ 2906 ahci_enable_port_intrs(ahci_ctlp, port); 2907 2908 return (AHCI_SUCCESS); 2909 } 2910 2911 /* 2912 * Figure out which chip and set flag for VT8251; Also check 2913 * the power management capability. 2914 */ 2915 static int 2916 ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 2917 { 2918 ushort_t venid, devid; 2919 ushort_t caps_ptr, cap_count, cap; 2920 #if AHCI_DEBUG 2921 ushort_t pmcap, pmcsr; 2922 #endif 2923 uint8_t revision; 2924 2925 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2926 PCI_CONF_VENID); 2927 2928 devid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2929 PCI_CONF_DEVID); 2930 2931 /* 2932 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 2933 * controllers with 0x00 revision id work on 4-byte aligned buffer, 2934 * which is a bug and was fixed after 0x00 revision id controllers. 2935 * 2936 * Moreover, VT8251 cannot use multiple command slots in the command 2937 * list for non-queued commands because the previous register content 2938 * of PxCI can be re-written in the register write, so a flag will be 2939 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 2940 */ 2941 if (venid == VIA_VENID) { 2942 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2943 PCI_CONF_REVID); 2944 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2945 "revision id = 0x%x", revision); 2946 if (revision == 0x00) { 2947 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 2948 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2949 "change ddi_attr_align to 0x4"); 2950 } 2951 2952 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 2953 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2954 "VT8251 cannot use multiple command lists for " 2955 "non-queued commands"); 2956 } 2957 2958 /* 2959 * ATI SB600 (1002,4380) doesn't support 64-bit DMA addressing though it 2960 * declares support, so we need to set AHCI_CAP_32BIT_DMA flag to force 2961 * 32-bit DMA. 2962 */ 2963 if (venid == 0x1002 && devid == 0x4380) { 2964 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2965 "ATI SB600 cannot do 64-bit DMA though CAP indicates " 2966 "support, so force it to use 32-bit DMA"); 2967 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 2968 } 2969 2970 /* 2971 * Check if capabilities list is supported and if so, 2972 * get initial capabilities pointer and clear bits 0,1. 2973 */ 2974 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2975 PCI_CONF_STAT) & PCI_STAT_CAP) { 2976 caps_ptr = P2ALIGN(pci_config_get8( 2977 ahci_ctlp->ahcictl_pci_conf_handle, 2978 PCI_CONF_CAP_PTR), 4); 2979 } else { 2980 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 2981 } 2982 2983 /* 2984 * Walk capabilities if supported. 2985 */ 2986 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 2987 2988 /* 2989 * Check that we haven't exceeded the maximum number of 2990 * capabilities and that the pointer is in a valid range. 2991 */ 2992 if (++cap_count > PCI_CAP_MAX_PTR) { 2993 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2994 "too many device capabilities"); 2995 return (AHCI_FAILURE); 2996 } 2997 if (caps_ptr < PCI_CAP_PTR_OFF) { 2998 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2999 "capabilities pointer 0x%x out of range", 3000 caps_ptr); 3001 return (AHCI_FAILURE); 3002 } 3003 3004 /* 3005 * Get next capability and check that it is valid. 3006 * For now, we only support power management. 3007 */ 3008 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 3009 caps_ptr); 3010 switch (cap) { 3011 case PCI_CAP_ID_PM: 3012 3013 /* power management supported */ 3014 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 3015 3016 /* Save PMCSR offset */ 3017 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 3018 3019 #if AHCI_DEBUG 3020 pmcap = pci_config_get16( 3021 ahci_ctlp->ahcictl_pci_conf_handle, 3022 caps_ptr + PCI_PMCAP); 3023 pmcsr = pci_config_get16( 3024 ahci_ctlp->ahcictl_pci_conf_handle, 3025 ahci_ctlp->ahcictl_pmcsr_offset); 3026 AHCIDBG2(AHCIDBG_PM, ahci_ctlp, 3027 "Power Management capability found PCI_PMCAP " 3028 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 3029 if ((pmcap & 0x3) == 0x3) 3030 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3031 "PCI Power Management Interface " 3032 "spec 1.2 compliant"); 3033 #endif 3034 break; 3035 3036 case PCI_CAP_ID_MSI: 3037 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, "MSI capability found"); 3038 break; 3039 3040 case PCI_CAP_ID_PCIX: 3041 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3042 "PCI-X capability found"); 3043 break; 3044 3045 case PCI_CAP_ID_PCI_E: 3046 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3047 "PCI Express capability found"); 3048 break; 3049 3050 case PCI_CAP_ID_MSI_X: 3051 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3052 "MSI-X capability found"); 3053 break; 3054 3055 case PCI_CAP_ID_SATA: 3056 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3057 "SATA capability found"); 3058 break; 3059 3060 case PCI_CAP_ID_VS: 3061 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3062 "Vendor Specific capability found"); 3063 break; 3064 3065 default: 3066 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 3067 "unrecognized capability 0x%x", cap); 3068 break; 3069 } 3070 3071 /* 3072 * Get next capabilities pointer and clear bits 0,1. 3073 */ 3074 caps_ptr = P2ALIGN(pci_config_get8( 3075 ahci_ctlp->ahcictl_pci_conf_handle, 3076 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 3077 } 3078 3079 return (AHCI_SUCCESS); 3080 } 3081 3082 /* 3083 * AHCI device reset ...; a single device on one of the ports is reset, 3084 * but the HBA and physical communication remain intact. This is the 3085 * least intrusive. 3086 * 3087 * When issuing a software reset sequence, there should not be other 3088 * commands in the command list, so we will first clear and then re-set 3089 * PxCMD.ST to clear PxCI. And before issuing the software reset, 3090 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 3091 * cleared unless command list override (PxCMD.CLO) is supported. 3092 * 3093 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 3094 * set before the function is called. 3095 */ 3096 static int 3097 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3098 uint8_t port) 3099 { 3100 ahci_fis_h2d_register_t *h2d_register_fisp; 3101 ahci_cmd_table_t *cmd_table; 3102 ahci_cmd_header_t *cmd_header; 3103 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 3104 int slot, loop_count; 3105 3106 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3107 "Port %d device resetting", port); 3108 3109 /* First clear PxCMD.ST */ 3110 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 3111 ahci_portp, port); 3112 3113 /* Then re-set PxCMD.ST */ 3114 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 3115 3116 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 3117 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3118 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3119 3120 if (port_task_file & AHCI_TFD_STS_BSY || 3121 port_task_file & AHCI_TFD_STS_DRQ) { 3122 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3123 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3124 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 3125 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3126 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 3127 "but PxCMD.CLO isn't supported, so a port " 3128 "reset is needed."); 3129 return (AHCI_FAILURE); 3130 } 3131 } 3132 3133 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, AHCI_NON_NCQ_CMD); 3134 if (slot == AHCI_FAILURE) { 3135 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 3136 "ahci_software_reset: no free slot"); 3137 return (AHCI_FAILURE); 3138 } 3139 3140 /* Now send the first H2D Register FIS with SRST set to 1 */ 3141 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3142 bzero((void *)cmd_table, ahci_cmd_table_size); 3143 3144 h2d_register_fisp = 3145 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3146 3147 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3148 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3149 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 3150 3151 /* Set Command Header in Command List */ 3152 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3153 BZERO_DESCR_INFO(cmd_header); 3154 BZERO_PRD_BYTE_COUNT(cmd_header); 3155 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3156 3157 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 3158 SET_RESET(cmd_header, 1); 3159 SET_WRITE(cmd_header, 1); 3160 3161 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3162 0, 3163 ahci_cmd_table_size, 3164 DDI_DMA_SYNC_FORDEV); 3165 3166 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3167 slot * sizeof (ahci_cmd_header_t), 3168 sizeof (ahci_cmd_header_t), 3169 DDI_DMA_SYNC_FORDEV); 3170 3171 /* Indicate to the HBA that a command is active. */ 3172 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3173 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3174 (0x1 << slot)); 3175 3176 loop_count = 0; 3177 3178 /* Loop till the first command is finished */ 3179 do { 3180 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3181 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3182 3183 /* We are effectively timing out after 1 sec. */ 3184 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3185 break; 3186 } 3187 /* Wait for 10 millisec */ 3188 delay(AHCI_10MS_TICKS); 3189 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3190 3191 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3192 "ahci_software_reset: 1st loop count: %d, " 3193 "port_cmd_issue = 0x%x, slot = 0x%x", 3194 loop_count, port_cmd_issue, slot); 3195 3196 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3197 3198 /* Now send the second H2D Register FIS with SRST cleard to zero */ 3199 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3200 bzero((void *)cmd_table, ahci_cmd_table_size); 3201 3202 h2d_register_fisp = 3203 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3204 3205 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3206 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3207 3208 /* Set Command Header in Command List */ 3209 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3210 BZERO_DESCR_INFO(cmd_header); 3211 BZERO_PRD_BYTE_COUNT(cmd_header); 3212 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3213 3214 SET_WRITE(cmd_header, 1); 3215 3216 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3217 0, 3218 ahci_cmd_table_size, 3219 DDI_DMA_SYNC_FORDEV); 3220 3221 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3222 slot * sizeof (ahci_cmd_header_t), 3223 sizeof (ahci_cmd_header_t), 3224 DDI_DMA_SYNC_FORDEV); 3225 3226 /* Indicate to the HBA that a command is active. */ 3227 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3228 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3229 (0x1 << slot)); 3230 3231 loop_count = 0; 3232 3233 /* Loop till the second command is finished */ 3234 do { 3235 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3236 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3237 3238 /* We are effectively timing out after 1 sec. */ 3239 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3240 break; 3241 } 3242 /* Wait for 10 millisec */ 3243 delay(AHCI_10MS_TICKS); 3244 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3245 3246 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3247 "ahci_software_reset: 2nd loop count: %d, " 3248 "port_cmd_issue = 0x%x, slot = 0x%x", 3249 loop_count, port_cmd_issue, slot); 3250 3251 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3252 3253 return (AHCI_SUCCESS); 3254 } 3255 3256 /* 3257 * AHCI port reset ...; the physical communication between the HBA and device 3258 * on a port are disabled. This is more intrusive. 3259 * 3260 * When an HBA or port reset occurs, Phy communication is going to 3261 * be re-established with the device through a COMRESET followed by the 3262 * normal out-of-band communication sequence defined in Serial ATA. AT 3263 * the end of reset, the device, if working properly, will send a D2H 3264 * Register FIS, which contains the device signature. When the HBA receives 3265 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 3266 * the PxSIG register with the signature. 3267 * 3268 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 3269 * to individually spin-up attached devices. Please refer to chapter 10.9 of 3270 * AHCI 1.0 spec. 3271 */ 3272 /* 3273 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 3274 * cleared before the function is called. 3275 */ 3276 static int 3277 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3278 { 3279 uint32_t cap_status, port_cmd_status; 3280 uint32_t port_scontrol, port_sstatus; 3281 uint32_t port_intr_status, port_task_file; 3282 #if AHCI_DEBUG 3283 uint32_t port_signature; 3284 #endif 3285 int loop_count; 3286 int rval = AHCI_SUCCESS; 3287 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 3288 3289 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3290 "Port %d port resetting...", port); 3291 ahci_portp->ahciport_port_state = 0; 3292 3293 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3294 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3295 3296 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3297 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3298 3299 if (cap_status & AHCI_HBA_CAP_SSS) { 3300 /* 3301 * HBA support staggered spin-up, if the port has 3302 * not spin up yet, then force it to do spin-up 3303 */ 3304 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 3305 if (!(ahci_portp->ahciport_flags 3306 & AHCI_PORT_FLAG_SPINUP)) { 3307 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3308 "Port %d PxCMD.SUD is zero, force " 3309 "it to do spin-up", port); 3310 ahci_portp->ahciport_flags |= 3311 AHCI_PORT_FLAG_SPINUP; 3312 } 3313 } 3314 } else { 3315 /* 3316 * HBA doesn't support stagger spin-up, force it 3317 * to do normal COMRESET 3318 */ 3319 if (ahci_portp->ahciport_flags & 3320 AHCI_PORT_FLAG_SPINUP) { 3321 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3322 "HBA does not support staggered spin-up " 3323 "force it to do normal COMRESET"); 3324 ahci_portp->ahciport_flags &= 3325 ~AHCI_PORT_FLAG_SPINUP; 3326 } 3327 } 3328 3329 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 3330 /* Do normal COMRESET */ 3331 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3332 "ahci_port_reset: do normal COMRESET", port); 3333 3334 /* 3335 * According to the spec, SUD bit should be set here, 3336 * but JMicron JMB363 doesn't follow it, so remove 3337 * the assertion, and just print a debug message. 3338 */ 3339 #if AHCI_DEBUG 3340 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3341 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3342 "port %d SUD bit not set", port) 3343 #endif 3344 3345 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3346 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3347 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3348 3349 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3350 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3351 port_scontrol); 3352 3353 /* Enable PxCMD.FRE to read device */ 3354 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3355 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3356 port_cmd_status|AHCI_CMD_STATUS_FRE); 3357 3358 /* 3359 * Give time for COMRESET to percolate, according to the AHCI 3360 * spec, software shall wait at least 1 millisecond before 3361 * clearing PxSCTL.DET 3362 */ 3363 delay(AHCI_1MS_TICKS*2); 3364 3365 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3366 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3367 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3368 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3369 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3370 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3371 port_scontrol); 3372 } else { 3373 /* Do staggered spin-up */ 3374 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3375 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3376 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3377 3378 /* PxSCTL.DET must be 0 */ 3379 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3380 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3381 port_scontrol); 3382 3383 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3384 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3385 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3386 port_cmd_status); 3387 3388 /* 0 -> 1 edge */ 3389 delay(AHCI_1MS_TICKS*2); 3390 3391 /* Set PxCMD.SUD to 1 */ 3392 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3393 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3394 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3395 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3396 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3397 port_cmd_status); 3398 3399 /* Enable PxCMD.FRE to read device */ 3400 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3401 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3402 port_cmd_status|AHCI_CMD_STATUS_FRE); 3403 } 3404 3405 /* 3406 * The port enters P:StartComm state, and HBA tells link layer to 3407 * start communication, which involves sending COMRESET to device. 3408 * And the HBA resets PxTFD.STS to 7Fh. 3409 * 3410 * When a COMINIT is received from the device, then the port enters 3411 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3412 * PxSSTS.DET to 1h to indicate a device is detected but communication 3413 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3414 * a COMINIT has been received. 3415 */ 3416 /* 3417 * The DET field is valid only if IPM field indicates 3418 * that the interface is in active state. 3419 */ 3420 loop_count = 0; 3421 do { 3422 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3423 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3424 3425 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3426 /* 3427 * If the interface is not active, the DET field 3428 * is considered not accurate. So we want to 3429 * continue looping. 3430 */ 3431 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3432 } 3433 3434 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3435 /* 3436 * We are effectively timing out after 0.1 sec. 3437 */ 3438 break; 3439 } 3440 3441 /* Wait for 10 millisec */ 3442 delay(AHCI_10MS_TICKS); 3443 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3444 3445 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3446 "ahci_port_reset: 1st loop count: %d, " 3447 "port_sstatus = 0x%x port %d", 3448 loop_count, port_sstatus, port); 3449 3450 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3451 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3452 /* 3453 * Either the port is not active or there 3454 * is no device present. 3455 */ 3456 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3457 goto out; 3458 } 3459 3460 /* Now we can make sure there is a device connected to the port */ 3461 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3462 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3463 3464 /* a COMINIT signal is supposed to be received */ 3465 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 3466 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 3467 "COMINIT signal from the device not received", 3468 instance, port); 3469 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3470 rval = AHCI_FAILURE; 3471 goto out; 3472 } 3473 3474 /* 3475 * According to the spec, when PxSCTL.DET is set to 0h, upon 3476 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3477 * shall be set to '1' by the HBA. 3478 * 3479 * However, we found JMicron JMB363 doesn't follow this, so 3480 * remove this check, and just print a debug message. 3481 */ 3482 #if AHCI_DEBUG 3483 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3484 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3485 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3486 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3487 "port %d BSY bit is not set after COMINIT signal " 3488 "is received", port); 3489 } 3490 #endif 3491 3492 /* 3493 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3494 * the D2H FIS received by HBA. 3495 */ 3496 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3497 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3498 SERROR_EXCHANGED_ERR); 3499 3500 /* 3501 * Next check whether COMRESET is completed successfully 3502 */ 3503 loop_count = 0; 3504 do { 3505 port_task_file = 3506 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3507 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3508 3509 /* 3510 * The Error bit '1' means COMRESET is finished successfully 3511 * The device hardware has been initialized and the power-up 3512 * diagnostics successfully completed. 3513 */ 3514 if (((port_task_file & AHCI_TFD_ERR_MASK) 3515 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 3516 #if AHCI_DEBUG 3517 port_signature = ddi_get32( 3518 ahci_ctlp->ahcictl_ahci_acc_handle, 3519 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3520 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 3521 "COMRESET success, D2H register FIS " 3522 "post to received FIS structure " 3523 "port %d signature = 0x%x", 3524 port, port_signature); 3525 #endif 3526 goto out_check; 3527 } 3528 3529 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3530 /* 3531 * We are effectively timing out after 11 sec. 3532 */ 3533 break; 3534 } 3535 3536 /* Wait for 10 millisec */ 3537 delay(AHCI_10MS_TICKS); 3538 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3539 >> AHCI_TFD_ERR_SHIFT) != 0x1); 3540 3541 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 3542 "count: %d, port_task_file = 0x%x port %d", 3543 loop_count, port_task_file, port); 3544 3545 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d the device hardware " 3546 "has been initialized and the power-up diagnostics failed", 3547 instance, port); 3548 3549 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3550 rval = AHCI_FAILURE; 3551 3552 out: 3553 /* Clear port serror register for the port */ 3554 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3555 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3556 AHCI_SERROR_CLEAR_ALL); 3557 3558 return (rval); 3559 3560 out_check: 3561 /* 3562 * Check device status, if keep busy or COMRESET error 3563 * do device reset to patch some SATA disks' issue 3564 * 3565 * For VT8251, sometimes need to do the device reset 3566 */ 3567 if ((port_task_file & AHCI_TFD_STS_BSY) || 3568 (port_task_file & AHCI_TFD_STS_DRQ)) { 3569 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 3570 "need to do device reset", port); 3571 3572 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 3573 3574 port_task_file = 3575 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3576 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3577 3578 if (port_task_file & AHCI_TFD_STS_BSY || 3579 port_task_file & AHCI_TFD_STS_DRQ) { 3580 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset: port %d " 3581 "BSY/DRQ still set after device reset " 3582 "port_task_file = 0x%x", instance, 3583 port, port_task_file); 3584 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3585 rval = AHCI_FAILURE; 3586 } 3587 } 3588 3589 goto out; 3590 } 3591 3592 /* 3593 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3594 * This is the most intrusive. 3595 * 3596 * When an HBA reset occurs, Phy communication will be re-established with 3597 * the device through a COMRESET followed by the normal out-of-band 3598 * communication sequence defined in Serial ATA. AT the end of reset, the 3599 * device, if working properly, will send a D2H Register FIS, which contains 3600 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3601 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3602 * signature. 3603 * 3604 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3605 */ 3606 static int 3607 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3608 { 3609 ahci_port_t *ahci_portp; 3610 uint32_t ghc_control; 3611 uint8_t port; 3612 int loop_count; 3613 int rval = AHCI_SUCCESS; 3614 3615 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3616 3617 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3618 3619 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3620 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3621 3622 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3623 ghc_control |= AHCI_HBA_GHC_HR; 3624 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3625 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3626 3627 /* 3628 * Wait until HBA Reset complete or timeout 3629 */ 3630 loop_count = 0; 3631 do { 3632 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3633 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3634 3635 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3636 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3637 "ahci hba reset is timing out, " 3638 "ghc_control = 0x%x", ghc_control); 3639 /* We are effectively timing out after 1 sec. */ 3640 break; 3641 } 3642 3643 /* Wait for 10 millisec */ 3644 delay(AHCI_10MS_TICKS); 3645 } while (ghc_control & AHCI_HBA_GHC_HR); 3646 3647 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3648 "ahci_hba_reset: 1st loop count: %d, " 3649 "ghc_control = 0x%x", loop_count, ghc_control); 3650 3651 if (ghc_control & AHCI_HBA_GHC_HR) { 3652 /* The hba is not reset for some reasons */ 3653 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3654 "hba reset failed: HBA in a hung or locked state"); 3655 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3656 return (AHCI_FAILURE); 3657 } 3658 3659 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3660 /* Only check implemented ports */ 3661 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3662 continue; 3663 } 3664 3665 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3666 mutex_enter(&ahci_portp->ahciport_mutex); 3667 3668 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3669 != AHCI_SUCCESS) { 3670 rval = AHCI_FAILURE; 3671 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3672 "ahci_hba_reset: port %d failed", port); 3673 } 3674 3675 mutex_exit(&ahci_portp->ahciport_mutex); 3676 } 3677 3678 /* 3679 * Indicate that system software is AHCI aware by setting 3680 * GHC.AE to 1 3681 */ 3682 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3683 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3684 3685 ghc_control |= AHCI_HBA_GHC_AE; 3686 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3687 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3688 3689 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3690 3691 return (rval); 3692 } 3693 3694 /* 3695 * This routine is only called from AHCI_ATTACH or phyrdy change 3696 * case. It first calls port reset to initialize port, probe port and probe 3697 * device, then try to read PxSIG register to find the type of device 3698 * attached to the port. 3699 * 3700 * WARNING!!! ahciport_mutex should be acquired before the function 3701 * is called. And the port interrupt is disabled. 3702 */ 3703 static void 3704 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3705 ahci_port_t *ahci_portp, uint8_t port) 3706 { 3707 uint32_t signature; 3708 3709 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3710 "ahci_find_dev_signature enter: port %d", port); 3711 3712 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3713 3714 /* Call port reset to check link status and get device signature */ 3715 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3716 3717 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3718 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3719 "ahci_find_dev_signature: No device is found " 3720 "at port %d", port); 3721 return; 3722 } 3723 3724 /* Check the port state */ 3725 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3726 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3727 "ahci_find_dev_signature: port %d state 0x%x", 3728 port, ahci_portp->ahciport_port_state); 3729 return; 3730 } 3731 3732 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3733 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3734 3735 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3736 "ahci_find_dev_signature: port %d signature = 0x%x", 3737 port, signature); 3738 3739 switch (signature) { 3740 3741 case AHCI_SIGNATURE_DISK: 3742 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3743 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3744 "Disk is found at port: %d", port); 3745 break; 3746 3747 case AHCI_SIGNATURE_ATAPI: 3748 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPI; 3749 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3750 "ATAPI device is found at port: %d", port); 3751 break; 3752 3753 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3754 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3755 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3756 "Port Multiplier is found at port: %d", port); 3757 break; 3758 3759 default: 3760 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3761 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3762 "Unknown device is found at port: %d", port); 3763 } 3764 } 3765 3766 /* 3767 * According to the spec, to reliably detect hot plug removals, software 3768 * must disable interface power management. Software should perform the 3769 * following initialization on a port after a device is attached: 3770 * Set PxSCTL.IPM to 3h to disable interface state transitions 3771 * Set PxCMD.ALPE to '0' to disable aggressive power management 3772 * Disable device initiated interface power management by SET FEATURE 3773 * 3774 * We can ignore the last item because by default the feature is disabled 3775 */ 3776 static void 3777 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 3778 { 3779 uint32_t port_scontrol, port_cmd_status; 3780 3781 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3782 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3783 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 3784 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3785 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3786 3787 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3788 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3789 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 3790 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3791 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 3792 } 3793 3794 /* 3795 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3796 * to 1, then set it firstly. 3797 * 3798 * Each port contains two major DMA engines. One DMA engine walks through 3799 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3800 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3801 * 3802 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3803 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3804 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3805 * 3806 * Software shall not set PxCMD.ST to '1' unless a functional device is 3807 * present on the port(as determined by PxTFD.STS.BSY = '0', 3808 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3809 * 3810 * WARNING!!! ahciport_mutex should be acquired before the function 3811 * is called. 3812 */ 3813 static int 3814 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3815 { 3816 uint32_t port_cmd_status; 3817 3818 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3819 3820 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3821 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3822 "the state for port %d is 0x%x", 3823 port, ahci_portp->ahciport_port_state); 3824 return (AHCI_FAILURE); 3825 } 3826 3827 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3828 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3829 "no device is attached at port %d", port); 3830 return (AHCI_FAILURE); 3831 } 3832 3833 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3834 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3835 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3836 3837 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3838 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3839 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3840 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3841 port_cmd_status); 3842 } 3843 3844 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3845 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3846 3847 port_cmd_status |= AHCI_CMD_STATUS_ST; 3848 3849 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3850 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3851 port_cmd_status); 3852 3853 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3854 3855 return (AHCI_SUCCESS); 3856 } 3857 3858 /* 3859 * Allocate the ahci_port_t including Received FIS and Command List. 3860 * The argument - port is the physical port number, and not logical 3861 * port number seen by the SATA framework. 3862 * 3863 * WARNING!!! ahcictl_mutex should be acquired before the function 3864 * is called. 3865 */ 3866 static int 3867 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3868 { 3869 ahci_port_t *ahci_portp; 3870 3871 ahci_portp = 3872 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3873 3874 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3875 ahci_portp->ahciport_port_num = port; 3876 3877 /* Intialize the port condition variable */ 3878 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3879 3880 /* Initialize the port mutex */ 3881 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3882 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3883 3884 mutex_enter(&ahci_portp->ahciport_mutex); 3885 3886 /* 3887 * Allocate memory for received FIS structure and 3888 * command list for this port 3889 */ 3890 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3891 goto err_case1; 3892 } 3893 3894 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3895 goto err_case2; 3896 } 3897 3898 ahci_portp->ahciport_event_args = 3899 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3900 3901 if (ahci_portp->ahciport_event_args == NULL) 3902 goto err_case3; 3903 3904 mutex_exit(&ahci_portp->ahciport_mutex); 3905 3906 return (AHCI_SUCCESS); 3907 3908 err_case3: 3909 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3910 3911 err_case2: 3912 ahci_dealloc_rcvd_fis(ahci_portp); 3913 3914 err_case1: 3915 mutex_exit(&ahci_portp->ahciport_mutex); 3916 mutex_destroy(&ahci_portp->ahciport_mutex); 3917 cv_destroy(&ahci_portp->ahciport_cv); 3918 3919 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3920 3921 return (AHCI_FAILURE); 3922 } 3923 3924 /* 3925 * Reverse of ahci_dealloc_port_state(). 3926 * 3927 * WARNING!!! ahcictl_mutex should be acquired before the function 3928 * is called. 3929 */ 3930 static void 3931 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3932 { 3933 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3934 3935 ASSERT(ahci_portp != NULL); 3936 3937 mutex_enter(&ahci_portp->ahciport_mutex); 3938 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3939 ahci_portp->ahciport_event_args = NULL; 3940 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3941 ahci_dealloc_rcvd_fis(ahci_portp); 3942 mutex_exit(&ahci_portp->ahciport_mutex); 3943 3944 mutex_destroy(&ahci_portp->ahciport_mutex); 3945 cv_destroy(&ahci_portp->ahciport_cv); 3946 3947 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3948 3949 ahci_ctlp->ahcictl_ports[port] = NULL; 3950 } 3951 3952 /* 3953 * Allocates memory for the Received FIS Structure 3954 * 3955 * WARNING!!! ahciport_mutex should be acquired before the function 3956 * is called. 3957 */ 3958 static int 3959 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3960 uint8_t port) 3961 { 3962 size_t rcvd_fis_size; 3963 size_t ret_len; 3964 uint_t cookie_count; 3965 3966 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3967 3968 /* allocate rcvd FIS dma handle. */ 3969 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3970 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3971 DDI_DMA_SLEEP, 3972 NULL, 3973 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3974 DDI_SUCCESS) { 3975 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3976 "rcvd FIS dma handle alloc failed"); 3977 3978 return (AHCI_FAILURE); 3979 } 3980 3981 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3982 rcvd_fis_size, 3983 &accattr, 3984 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3985 DDI_DMA_SLEEP, 3986 NULL, 3987 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3988 &ret_len, 3989 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3990 3991 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3992 "rcvd FIS dma mem alloc fail"); 3993 /* error.. free the dma handle. */ 3994 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3995 return (AHCI_FAILURE); 3996 } 3997 3998 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3999 NULL, 4000 (caddr_t)ahci_portp->ahciport_rcvd_fis, 4001 rcvd_fis_size, 4002 DDI_DMA_CONSISTENT, 4003 DDI_DMA_SLEEP, 4004 NULL, 4005 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 4006 &cookie_count) != DDI_DMA_MAPPED) { 4007 4008 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4009 "rcvd FIS dma handle bind fail"); 4010 /* error.. free the dma handle & free the memory. */ 4011 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4012 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4013 return (AHCI_FAILURE); 4014 } 4015 4016 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 4017 4018 /* Config Port Received FIS Base Address */ 4019 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4020 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 4021 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4022 4023 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4024 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4025 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4026 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 4027 4028 return (AHCI_SUCCESS); 4029 } 4030 4031 /* 4032 * Deallocates the Received FIS Structure 4033 * 4034 * WARNING!!! ahciport_mutex should be acquired before the function 4035 * is called. 4036 */ 4037 static void 4038 ahci_dealloc_rcvd_fis(ahci_port_t *ahci_portp) 4039 { 4040 /* Unbind the cmd list dma handle first. */ 4041 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 4042 4043 /* Then free the underlying memory. */ 4044 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4045 4046 /* Now free the handle itself. */ 4047 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4048 } 4049 4050 /* 4051 * Allocates memory for the Command List, which contains up to 32 entries. 4052 * Each entry contains a command header, which is a 32-byte structure that 4053 * includes the pointer to the command table. 4054 * 4055 * WARNING!!! ahciport_mutex should be acquired before the function 4056 * is called. 4057 */ 4058 static int 4059 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4060 uint8_t port) 4061 { 4062 size_t cmd_list_size; 4063 size_t ret_len; 4064 uint_t cookie_count; 4065 4066 cmd_list_size = 4067 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 4068 4069 /* allocate cmd list dma handle. */ 4070 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4071 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 4072 DDI_DMA_SLEEP, 4073 NULL, 4074 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 4075 4076 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4077 "cmd list dma handle alloc failed"); 4078 return (AHCI_FAILURE); 4079 } 4080 4081 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 4082 cmd_list_size, 4083 &accattr, 4084 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4085 DDI_DMA_SLEEP, 4086 NULL, 4087 (caddr_t *)&ahci_portp->ahciport_cmd_list, 4088 &ret_len, 4089 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 4090 4091 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4092 "cmd list dma mem alloc fail"); 4093 /* error.. free the dma handle. */ 4094 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4095 return (AHCI_FAILURE); 4096 } 4097 4098 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 4099 NULL, 4100 (caddr_t)ahci_portp->ahciport_cmd_list, 4101 cmd_list_size, 4102 DDI_DMA_CONSISTENT, 4103 DDI_DMA_SLEEP, 4104 NULL, 4105 &ahci_portp->ahciport_cmd_list_dma_cookie, 4106 &cookie_count) != DDI_DMA_MAPPED) { 4107 4108 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4109 "cmd list dma handle bind fail"); 4110 /* error.. free the dma handle & free the memory. */ 4111 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4112 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4113 return (AHCI_FAILURE); 4114 } 4115 4116 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 4117 4118 /* Config Port Command List Base Address */ 4119 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4120 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 4121 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4122 4123 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4124 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4125 4126 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4127 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 4128 4129 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 4130 goto err_out; 4131 } 4132 4133 return (AHCI_SUCCESS); 4134 4135 err_out: 4136 /* Unbind the cmd list dma handle first. */ 4137 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4138 4139 /* Then free the underlying memory. */ 4140 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4141 4142 /* Now free the handle itself. */ 4143 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4144 4145 return (AHCI_FAILURE); 4146 } 4147 4148 /* 4149 * Deallocates the Command List 4150 * 4151 * WARNING!!! ahciport_mutex should be acquired before the function 4152 * is called. 4153 */ 4154 static void 4155 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4156 { 4157 /* First dealloc command table */ 4158 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 4159 4160 /* Unbind the cmd list dma handle first. */ 4161 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4162 4163 /* Then free the underlying memory. */ 4164 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4165 4166 /* Now free the handle itself. */ 4167 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4168 } 4169 4170 /* 4171 * Allocates memory for all Command Tables, which contains Command FIS, 4172 * ATAPI Command and Physical Region Descriptor Table. 4173 * 4174 * WARNING!!! ahciport_mutex should be acquired before the function 4175 * is called. 4176 */ 4177 static int 4178 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4179 { 4180 size_t ret_len; 4181 ddi_dma_cookie_t cmd_table_dma_cookie; 4182 uint_t cookie_count; 4183 int slot; 4184 4185 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4186 "ahci_alloc_cmd_tables: port %d enter", 4187 ahci_portp->ahciport_port_num); 4188 4189 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4190 /* Allocate cmd table dma handle. */ 4191 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4192 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 4193 DDI_DMA_SLEEP, 4194 NULL, 4195 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 4196 DDI_SUCCESS) { 4197 4198 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4199 "cmd table dma handle alloc failed"); 4200 4201 goto err_out; 4202 } 4203 4204 if (ddi_dma_mem_alloc( 4205 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4206 ahci_cmd_table_size, 4207 &accattr, 4208 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4209 DDI_DMA_SLEEP, 4210 NULL, 4211 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 4212 &ret_len, 4213 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 4214 NULL) { 4215 4216 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4217 "cmd table dma mem alloc fail"); 4218 4219 /* error.. free the dma handle. */ 4220 ddi_dma_free_handle( 4221 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4222 goto err_out; 4223 } 4224 4225 if (ddi_dma_addr_bind_handle( 4226 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4227 NULL, 4228 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 4229 ahci_cmd_table_size, 4230 DDI_DMA_CONSISTENT, 4231 DDI_DMA_SLEEP, 4232 NULL, 4233 &cmd_table_dma_cookie, 4234 &cookie_count) != DDI_DMA_MAPPED) { 4235 4236 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4237 "cmd table dma handle bind fail"); 4238 /* error.. free the dma handle & free the memory. */ 4239 ddi_dma_mem_free( 4240 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4241 ddi_dma_free_handle( 4242 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4243 goto err_out; 4244 } 4245 4246 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 4247 ahci_cmd_table_size); 4248 4249 /* Config Port Command Table Base Address */ 4250 SET_COMMAND_TABLE_BASE_ADDR( 4251 (&ahci_portp->ahciport_cmd_list[slot]), 4252 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 4253 4254 #ifndef __lock_lint 4255 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 4256 (&ahci_portp->ahciport_cmd_list[slot]), 4257 cmd_table_dma_cookie.dmac_laddress >> 32); 4258 #endif 4259 } 4260 4261 return (AHCI_SUCCESS); 4262 err_out: 4263 4264 for (slot--; slot >= 0; slot--) { 4265 /* Unbind the cmd table dma handle first */ 4266 (void) ddi_dma_unbind_handle( 4267 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4268 4269 /* Then free the underlying memory */ 4270 ddi_dma_mem_free( 4271 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4272 4273 /* Now free the handle itself */ 4274 ddi_dma_free_handle( 4275 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4276 } 4277 4278 return (AHCI_FAILURE); 4279 } 4280 4281 /* 4282 * Deallocates memory for all Command Tables. 4283 * 4284 * WARNING!!! ahciport_mutex should be acquired before the function 4285 * is called. 4286 */ 4287 static void 4288 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4289 { 4290 int slot; 4291 4292 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4293 "ahci_dealloc_cmd_tables: %d enter", 4294 ahci_portp->ahciport_port_num); 4295 4296 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4297 /* Unbind the cmd table dma handle first. */ 4298 (void) ddi_dma_unbind_handle( 4299 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4300 4301 /* Then free the underlying memory. */ 4302 ddi_dma_mem_free( 4303 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4304 4305 /* Now free the handle itself. */ 4306 ddi_dma_free_handle( 4307 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4308 } 4309 } 4310 4311 /* 4312 * WARNING!!! ahciport_mutex should be acquired before the function 4313 * is called. 4314 */ 4315 static void 4316 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4317 sata_device_t *sd) 4318 { 4319 sd->satadev_scr.sstatus = 4320 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4321 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4322 sd->satadev_scr.serror = 4323 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4324 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4325 sd->satadev_scr.scontrol = 4326 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4327 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4328 sd->satadev_scr.sactive = 4329 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4330 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4331 } 4332 4333 /* 4334 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4335 */ 4336 static void 4337 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4338 { 4339 uint32_t port_intr_status; 4340 uint32_t port_intr_enable; 4341 4342 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4343 "ahci_port_intr enter: port %d", port); 4344 4345 mutex_enter(&ahci_portp->ahciport_mutex); 4346 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4347 /* For SATA_OPMODE_POLLING commands */ 4348 port_intr_enable = 4349 (AHCI_INTR_STATUS_DHRS | 4350 AHCI_INTR_STATUS_PSS | 4351 AHCI_INTR_STATUS_SDBS | 4352 AHCI_INTR_STATUS_UFS | 4353 AHCI_INTR_STATUS_PCS | 4354 AHCI_INTR_STATUS_PRCS | 4355 AHCI_INTR_STATUS_OFS | 4356 AHCI_INTR_STATUS_INFS | 4357 AHCI_INTR_STATUS_IFS | 4358 AHCI_INTR_STATUS_HBDS | 4359 AHCI_INTR_STATUS_HBFS | 4360 AHCI_INTR_STATUS_TFES); 4361 mutex_exit(&ahci_portp->ahciport_mutex); 4362 goto next; 4363 } 4364 mutex_exit(&ahci_portp->ahciport_mutex); 4365 4366 /* 4367 * port_intr_enable indicates that the corresponding interrrupt 4368 * reporting is enabled. 4369 */ 4370 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4371 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4372 next: 4373 /* 4374 * port_intr_stats indicates that the corresponding interrupt 4375 * condition is active. 4376 */ 4377 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4378 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4379 4380 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4381 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4382 "port_intr_enable = 0x%x", 4383 port, port_intr_status, port_intr_enable); 4384 4385 port_intr_status &= port_intr_enable; 4386 4387 /* First clear the port interrupts status */ 4388 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4389 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4390 port_intr_status); 4391 4392 /* Check the completed non-queued commands */ 4393 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4394 AHCI_INTR_STATUS_PSS)) { 4395 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4396 ahci_portp, port); 4397 } 4398 4399 /* Check the completed queued commands */ 4400 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4401 (void) ahci_intr_set_device_bits(ahci_ctlp, 4402 ahci_portp, port); 4403 } 4404 4405 /* Check the port connect change status interrupt bit */ 4406 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4407 (void) ahci_intr_port_connect_change(ahci_ctlp, 4408 ahci_portp, port); 4409 } 4410 4411 /* Check the device mechanical presence status interrupt bit */ 4412 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4413 (void) ahci_intr_device_mechanical_presence_status( 4414 ahci_ctlp, ahci_portp, port); 4415 } 4416 4417 /* Check the PhyRdy change status interrupt bit */ 4418 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4419 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4420 port); 4421 } 4422 4423 /* 4424 * Check the non-fatal error interrupt bits, there are three 4425 * kinds of non-fatal errors at the time being: 4426 * 4427 * PxIS.UFS - Unknown FIS Error 4428 * PxIS.OFS - Overflow Error 4429 * PxIS.INFS - Interface Non-Fatal Error 4430 * 4431 * For these non-fatal errors, the HBA can continue to operate, 4432 * so the driver just log the error messages. 4433 */ 4434 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4435 AHCI_INTR_STATUS_OFS | 4436 AHCI_INTR_STATUS_INFS)) { 4437 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4438 port, port_intr_status); 4439 } 4440 4441 /* 4442 * Check the fatal error interrupt bits, there are four kinds 4443 * of fatal errors for AHCI controllers: 4444 * 4445 * PxIS.HBFS - Host Bus Fatal Error 4446 * PxIS.HBDS - Host Bus Data Error 4447 * PxIS.IFS - Interface Fatal Error 4448 * PxIS.TFES - Task File Error 4449 * 4450 * The fatal error means the HBA can not recover from it by 4451 * itself, and it will try to abort the transfer, and the software 4452 * must intervene to restart the port. 4453 */ 4454 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4455 AHCI_INTR_STATUS_HBDS | 4456 AHCI_INTR_STATUS_HBFS | 4457 AHCI_INTR_STATUS_TFES)) 4458 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4459 port, port_intr_status); 4460 4461 /* Check the cold port detect interrupt bit */ 4462 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4463 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4464 } 4465 4466 /* Second clear the corresponding bit in IS.IPS */ 4467 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4468 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4469 } 4470 4471 /* 4472 * Interrupt service handler 4473 */ 4474 static uint_t 4475 ahci_intr(caddr_t arg1, caddr_t arg2) 4476 { 4477 #ifndef __lock_lint 4478 _NOTE(ARGUNUSED(arg2)) 4479 #endif 4480 /* LINTED */ 4481 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4482 ahci_port_t *ahci_portp; 4483 int32_t global_intr_status; 4484 uint8_t port; 4485 4486 /* 4487 * global_intr_status indicates that the corresponding port has 4488 * an interrupt pending. 4489 */ 4490 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4491 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4492 4493 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4494 /* The interrupt is not ours */ 4495 return (DDI_INTR_UNCLAIMED); 4496 } 4497 4498 /* Loop for all the ports */ 4499 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4500 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4501 continue; 4502 } 4503 if (!((0x1 << port) & global_intr_status)) { 4504 continue; 4505 } 4506 4507 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4508 4509 /* Call ahci_port_intr */ 4510 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4511 } 4512 4513 return (DDI_INTR_CLAIMED); 4514 } 4515 4516 /* 4517 * For non-queued commands, when the corresponding bit in the PxCI register 4518 * is cleared, it means the command is completed successfully. And according 4519 * to the HBA state machine, there are three conditions which possibly will 4520 * try to clear the PxCI register bit. 4521 * 1. Receive one D2H Register FIS which is with 'I' bit set 4522 * 2. Update PIO Setup FIS 4523 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4524 * 4525 * Process completed non-queued commands when the interrupt status bit - 4526 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4527 * 4528 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4529 * with the 'I' bit set. And the following commands will send thus 4530 * FIS with 'I' bit set upon the successful completion: 4531 * 1. Non-data commands 4532 * 2. DMA data-in command 4533 * 3. DMA data-out command 4534 * 4. PIO data-out command 4535 * 5. PACKET non-data commands 4536 * 6. PACKET PIO data-in command 4537 * 7. PACKET PIO data-out command 4538 * 8. PACKET DMA data-in command 4539 * 9. PACKET DMA data-out command 4540 * 4541 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4542 * with the 'I' bit set. And the following commands will send this 4543 * FIS upon the successful completion: 4544 * 1. PIO data-in command 4545 */ 4546 static int 4547 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4548 ahci_port_t *ahci_portp, uint8_t port) 4549 { 4550 uint32_t port_cmd_issue = 0; 4551 uint32_t finished_tags; 4552 int finished_slot; 4553 sata_pkt_t *satapkt; 4554 ahci_fis_d2h_register_t *rcvd_fisp; 4555 #if AHCI_DEBUG 4556 ahci_cmd_header_t *cmd_header; 4557 uint32_t cmd_dmacount; 4558 #endif 4559 4560 mutex_enter(&ahci_portp->ahciport_mutex); 4561 4562 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4563 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4564 /* 4565 * Spurious interrupt. Nothing to be done. 4566 */ 4567 mutex_exit(&ahci_portp->ahciport_mutex); 4568 return (AHCI_SUCCESS); 4569 } 4570 4571 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4572 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4573 4574 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4575 /* Slot 0 is always used during error recovery */ 4576 finished_tags = 0x1 & ~port_cmd_issue; 4577 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4578 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4579 "retrieval is finished, and finished_tags = 0x%x", 4580 port, finished_tags); 4581 } else { 4582 finished_tags = ahci_portp->ahciport_pending_tags & 4583 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4584 } 4585 4586 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4587 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4588 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4589 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4590 finished_tags); 4591 4592 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4593 (finished_tags == 0x1)) { 4594 satapkt = ahci_portp->ahciport_err_retri_pkt; 4595 ASSERT(satapkt != NULL); 4596 4597 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4598 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4599 "with SATA_PKT_COMPLETED", (void *)satapkt); 4600 4601 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4602 goto out; 4603 } 4604 4605 while (finished_tags) { 4606 finished_slot = ddi_ffs(finished_tags) - 1; 4607 if (finished_slot == -1) { 4608 goto out; 4609 } 4610 4611 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4612 ASSERT(satapkt != NULL); 4613 #if AHCI_DEBUG 4614 /* 4615 * For non-native queued commands, the PRD byte count field 4616 * shall contain an accurate count of the number of bytes 4617 * transferred for the command before the PxCI bit is cleared 4618 * to '0' for the command. 4619 * 4620 * The purpose of this field is to let software know how many 4621 * bytes transferred for a given operation in order to 4622 * determine if underflow occurred. When issuing native command 4623 * queuing commands, this field should not be used and is not 4624 * required to be valid since in this case underflow is always 4625 * illegal. 4626 * 4627 * For data reads, the HBA will update its PRD byte count with 4628 * the total number of bytes received from the last FIS, and 4629 * may be able to continue normally. For data writes, the 4630 * device will detect an error, and HBA most likely will get 4631 * a fatal error. 4632 * 4633 * Therefore, here just put code to debug part. And please 4634 * refer to the comment above ahci_intr_fatal_error for the 4635 * definition of underflow error. 4636 */ 4637 cmd_dmacount = 4638 ahci_portp->ahciport_prd_bytecounts[finished_slot]; 4639 if (cmd_dmacount) { 4640 cmd_header = 4641 &ahci_portp->ahciport_cmd_list[finished_slot]; 4642 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_PRDT, ahci_ctlp, 4643 "ahci_intr_cmd_cmplt: port %d, " 4644 "PRD Byte Count = 0x%x, " 4645 "ahciport_prd_bytecounts = 0x%x", port, 4646 cmd_header->ahcich_prd_byte_count, 4647 cmd_dmacount); 4648 4649 if (cmd_header->ahcich_prd_byte_count != cmd_dmacount) { 4650 AHCIDBG1(AHCIDBG_UNDERFLOW, ahci_ctlp, 4651 "ahci_intr_cmd_cmplt: port %d, " 4652 "an underflow occurred", port); 4653 } 4654 } 4655 #endif 4656 4657 /* 4658 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4659 * feature, sata_special_regs flag will be set, and the 4660 * driver should copy the status and the other corresponding 4661 * register values in the D2H Register FIS received (It's 4662 * working on Non-data protocol) from the device back to 4663 * the sata_cmd. 4664 * 4665 * For every AHCI port, there is only one Received FIS 4666 * structure, which contains the FISes received from the 4667 * device, So we're trying to copy the content of D2H 4668 * Register FIS in the Received FIS structure back to 4669 * the sata_cmd. 4670 */ 4671 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4672 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4673 ahcirf_d2h_register_fis); 4674 satapkt->satapkt_cmd.satacmd_status_reg = 4675 GET_RFIS_STATUS(rcvd_fisp); 4676 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4677 } 4678 4679 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4680 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4681 "with SATA_PKT_COMPLETED", (void *)satapkt); 4682 4683 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4684 CLEAR_BIT(finished_tags, finished_slot); 4685 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4686 4687 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4688 } 4689 out: 4690 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4691 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4692 ahci_portp->ahciport_pending_tags); 4693 4694 mutex_exit(&ahci_portp->ahciport_mutex); 4695 4696 return (AHCI_SUCCESS); 4697 } 4698 4699 /* 4700 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4701 * with the 'I' bit set and has been copied into system memory. It will 4702 * be sent under the following situations: 4703 * 4704 * 1. NCQ command is completed 4705 * 2. Asynchronous notification 4706 * 4707 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4708 * via the Set Device Bits FIS. When such event is generated, the software 4709 * needs to read PxSACT register and compares the current value to the 4710 * list of commands previously issue by software. ahciport_pending_ncq_tags 4711 * keeps the tags of previously issued commands. 4712 * 4713 * Asynchronous Notification is a feature in SATA II, which allows an 4714 * ATAPI device to send a signal to the host when media is inserted or 4715 * removed and avoids polling the device for media changes. The signal 4716 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4717 * set to '1'. At the moment, it's not supported yet. 4718 */ 4719 static int 4720 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4721 ahci_port_t *ahci_portp, uint8_t port) 4722 { 4723 uint32_t port_sactive; 4724 uint32_t port_cmd_issue; 4725 uint32_t issued_tags; 4726 int issued_slot; 4727 uint32_t finished_tags; 4728 int finished_slot; 4729 sata_pkt_t *satapkt; 4730 4731 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4732 "ahci_intr_set_device_bits enter: port %d", port); 4733 4734 mutex_enter(&ahci_portp->ahciport_mutex); 4735 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4736 mutex_exit(&ahci_portp->ahciport_mutex); 4737 return (AHCI_SUCCESS); 4738 } 4739 4740 /* 4741 * First the handler got which commands are finished by checking 4742 * PxSACT register 4743 */ 4744 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4745 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4746 4747 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4748 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4749 4750 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4751 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4752 "port_sactive = 0x%x", port, 4753 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4754 4755 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4756 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4757 4758 /* 4759 * For NCQ commands, the software can determine which command has 4760 * already been transmitted to the device by checking PxCI register. 4761 */ 4762 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4763 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4764 4765 issued_tags = ahci_portp->ahciport_pending_tags & 4766 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4767 4768 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4769 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4770 "port_cmd_issue = 0x%x", port, 4771 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4772 4773 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4774 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4775 4776 /* 4777 * Clear ahciport_pending_tags bit when the corresponding command 4778 * is already sent down to the device. 4779 */ 4780 while (issued_tags) { 4781 issued_slot = ddi_ffs(issued_tags) - 1; 4782 if (issued_slot == -1) { 4783 goto next; 4784 } 4785 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4786 CLEAR_BIT(issued_tags, issued_slot); 4787 } 4788 4789 next: 4790 while (finished_tags) { 4791 finished_slot = ddi_ffs(finished_tags) - 1; 4792 if (finished_slot == -1) { 4793 goto out; 4794 } 4795 4796 /* The command is certainly transmitted to the device */ 4797 ASSERT(!(ahci_portp->ahciport_pending_tags & 4798 (0x1 << finished_slot))); 4799 4800 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4801 ASSERT(satapkt != NULL); 4802 4803 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4804 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4805 "with SATA_PKT_COMPLETED", (void *)satapkt); 4806 4807 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4808 CLEAR_BIT(finished_tags, finished_slot); 4809 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4810 4811 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4812 } 4813 out: 4814 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4815 "ahci_intr_set_device_bits: port %d " 4816 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4817 port, ahci_portp->ahciport_pending_ncq_tags, 4818 ahci_portp->ahciport_pending_tags); 4819 4820 mutex_exit(&ahci_portp->ahciport_mutex); 4821 4822 return (AHCI_SUCCESS); 4823 } 4824 4825 /* 4826 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4827 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4828 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4829 * indicates a COMINIT signal was received. 4830 * 4831 * Hot plug insertion is detected by reception of a COMINIT signal from the 4832 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4833 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4834 * begin the normal communication negotiation sequence as outlined in the 4835 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4836 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4837 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4838 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4839 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4840 * to handle hot plug insertion. In this interrupt handler, just do nothing 4841 * but print some log message and clear the bit. 4842 */ 4843 static int 4844 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4845 ahci_port_t *ahci_portp, uint8_t port) 4846 { 4847 #if AHCI_DEBUG 4848 uint32_t port_serror; 4849 #endif 4850 4851 mutex_enter(&ahci_portp->ahciport_mutex); 4852 4853 #if AHCI_DEBUG 4854 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4855 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4856 4857 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4858 "ahci_intr_port_connect_change: port %d, " 4859 "port_serror = 0x%x", port, port_serror); 4860 #endif 4861 4862 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4863 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4864 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4865 SERROR_EXCHANGED_ERR); 4866 4867 mutex_exit(&ahci_portp->ahciport_mutex); 4868 4869 return (AHCI_SUCCESS); 4870 } 4871 4872 /* 4873 * Hot Plug Operation for platforms that support Mechanical Presence 4874 * Switches. 4875 * 4876 * When set, it indicates that a mechanical presence switch attached to this 4877 * port has been opened or closed, which may lead to a change in the connection 4878 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4879 * are set to '1'. 4880 * 4881 * At the moment, this interrupt is not needed and disabled and we just log 4882 * the debug message. 4883 */ 4884 static int 4885 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4886 ahci_port_t *ahci_portp, uint8_t port) 4887 { 4888 uint32_t cap_status, port_cmd_status; 4889 4890 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4891 "ahci_intr_device_mechanical_presence_status enter, " 4892 "port %d", port); 4893 4894 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4895 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4896 4897 mutex_enter(&ahci_portp->ahciport_mutex); 4898 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4899 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4900 4901 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4902 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4903 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4904 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4905 "the interrupt: cap_status = 0x%x, " 4906 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4907 mutex_exit(&ahci_portp->ahciport_mutex); 4908 4909 return (AHCI_SUCCESS); 4910 } 4911 4912 #if AHCI_DEBUG 4913 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4914 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4915 "The mechanical presence switch is open: " 4916 "port %d, port_cmd_status = 0x%x", 4917 port, port_cmd_status); 4918 } else { 4919 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4920 "The mechanical presence switch is close: " 4921 "port %d, port_cmd_status = 0x%x", 4922 port, port_cmd_status); 4923 } 4924 #endif 4925 4926 mutex_exit(&ahci_portp->ahciport_mutex); 4927 4928 return (AHCI_SUCCESS); 4929 } 4930 4931 /* 4932 * Native Hot Plug Support. 4933 * 4934 * When set, it indicates that the internal PHYRDY signal changed state. 4935 * This bit reflects the state of PxSERR.DIAG.N. 4936 * 4937 * There are three kinds of conditions to generate this interrupt event: 4938 * 1. a device is inserted 4939 * 2. a device is disconnected 4940 * 3. when the link enters/exits a Partial or Slumber interface power 4941 * management state 4942 * 4943 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4944 * bit may be set due to the link entering the Partial or Slumber power 4945 * management state, rather than due to a hot plug insertion or removal 4946 * event. So far, the interface power management is disabled, so the 4947 * driver can reliably get removal detection notification via the 4948 * PxSERR.DIAG.N bit. 4949 */ 4950 static int 4951 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4952 ahci_port_t *ahci_portp, uint8_t port) 4953 { 4954 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4955 sata_device_t sdevice; 4956 int dev_exists_now = 0; 4957 int dev_existed_previously = 0; 4958 4959 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4960 "ahci_intr_phyrdy_change enter, port %d", port); 4961 4962 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4963 mutex_enter(&ahci_portp->ahciport_mutex); 4964 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4965 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4966 SERROR_PHY_RDY_CHG); 4967 mutex_exit(&ahci_portp->ahciport_mutex); 4968 4969 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4970 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4971 (ahci_portp == NULL)) { 4972 /* The whole controller setup is not yet done. */ 4973 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4974 return (AHCI_SUCCESS); 4975 } 4976 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4977 4978 mutex_enter(&ahci_portp->ahciport_mutex); 4979 4980 /* SStatus tells the presence of device. */ 4981 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4982 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4983 4984 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 4985 dev_exists_now = 1; 4986 } 4987 4988 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4989 dev_existed_previously = 1; 4990 } 4991 4992 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 4993 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 4994 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4995 "ahci_intr_phyrdy_change: port %d " 4996 "AHCI_PORT_FLAG_NODEV is cleared", port); 4997 if (dev_exists_now == 0) 4998 dev_existed_previously = 1; 4999 } 5000 5001 bzero((void *)&sdevice, sizeof (sata_device_t)); 5002 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5003 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5004 sdevice.satadev_addr.pmport = 0; 5005 sdevice.satadev_state = SATA_PSTATE_PWRON; 5006 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 5007 5008 if (dev_exists_now) { 5009 if (dev_existed_previously) { 5010 /* Things are fine now. The loss was temporary. */ 5011 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5012 "ahci_intr_phyrdy_change port %d " 5013 "device link lost/established", port); 5014 5015 mutex_exit(&ahci_portp->ahciport_mutex); 5016 sata_hba_event_notify( 5017 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5018 &sdevice, 5019 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 5020 mutex_enter(&ahci_portp->ahciport_mutex); 5021 5022 } else { 5023 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5024 "ahci_intr_phyrdy_change: port %d " 5025 "device link established", port); 5026 5027 /* A new device has been detected. */ 5028 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 5029 5030 /* Try to start the port */ 5031 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 5032 != AHCI_SUCCESS) { 5033 sdevice.satadev_state |= SATA_PSTATE_FAILED; 5034 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5035 "ahci_intr_phyrdy_change: port %d failed " 5036 "at start port", port); 5037 } 5038 5039 /* Clear the max queue depth for inserted device */ 5040 ahci_portp->ahciport_max_ncq_tags = 0; 5041 5042 mutex_exit(&ahci_portp->ahciport_mutex); 5043 sata_hba_event_notify( 5044 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5045 &sdevice, 5046 SATA_EVNT_LINK_ESTABLISHED); 5047 mutex_enter(&ahci_portp->ahciport_mutex); 5048 5049 } 5050 } else { /* No device exists now */ 5051 5052 if (dev_existed_previously) { 5053 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5054 "ahci_intr_phyrdy_change: port %d " 5055 "device link lost", port); 5056 5057 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 5058 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 5059 ahci_portp, port); 5060 5061 /* An existing device is lost. */ 5062 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 5063 5064 mutex_exit(&ahci_portp->ahciport_mutex); 5065 sata_hba_event_notify( 5066 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5067 &sdevice, 5068 SATA_EVNT_LINK_LOST); 5069 mutex_enter(&ahci_portp->ahciport_mutex); 5070 } 5071 } 5072 5073 mutex_exit(&ahci_portp->ahciport_mutex); 5074 5075 return (AHCI_SUCCESS); 5076 } 5077 5078 /* 5079 * PxIS.UFS - Unknown FIS Error 5080 * 5081 * This interrupt event means an unknown FIS was received and has been 5082 * copied into system memory. An unknown FIS is not considered an illegal 5083 * FIS, unless the length received is more than 64 bytes. If an unknown 5084 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 5085 * normal operation. If the unknown FIS is more than 64 bytes, then it 5086 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 5087 * a fatal error. 5088 * 5089 * PxIS.OFS - Overflow Error 5090 * 5091 * Command list overflow is defined as software building a command table 5092 * that has fewer total bytes than the transaction given to the device. 5093 * On device writes, the HBA will run out of data, and on reads, there 5094 * will be no room to put the data. 5095 * 5096 * For an overflow on data read, either PIO or DMA, the HBA will set 5097 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 5098 * non-fatal error when the HBA can continues. Sometimes, it will cause 5099 * a fatal error and need the software to do something. 5100 * 5101 * For an overflow on data write, setting PxIS.OFS is optional for both 5102 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 5103 * software to clean up from this serious error. 5104 * 5105 * PxIS.INFS - Interface Non-Fatal Error 5106 * 5107 * This interrupt event indicates that the HBA encountered an error on 5108 * the Serial ATA interface but was able to continue operation. The kind 5109 * of error usually occurred during a non-Data FIS, and under this condition 5110 * the FIS will be re-transmitted by HBA automatically. 5111 * 5112 * When the FMA is implemented, there should be a stat structure to 5113 * record how many every kind of error happens. 5114 */ 5115 static int 5116 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5117 uint8_t port, uint32_t intr_status) 5118 { 5119 uint32_t port_serror; 5120 #if AHCI_DEBUG 5121 uint32_t port_cmd_status; 5122 uint32_t port_cmd_issue; 5123 uint32_t port_sactive; 5124 int current_slot; 5125 uint32_t current_tags; 5126 sata_pkt_t *satapkt; 5127 ahci_cmd_header_t *cmd_header; 5128 uint32_t cmd_dmacount; 5129 #endif 5130 5131 mutex_enter(&ahci_portp->ahciport_mutex); 5132 5133 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5134 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5135 5136 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 5137 "ahci_intr_non_fatal_error: port %d, " 5138 "port_serror = 0x%x", port, port_serror); 5139 5140 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1); 5141 5142 if (intr_status & AHCI_INTR_STATUS_UFS) { 5143 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5144 "ahci port %d has unknown FIS error", port); 5145 5146 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 5147 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5148 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5149 SERROR_FIS_TYPE); 5150 } 5151 5152 #if AHCI_DEBUG 5153 if (intr_status & AHCI_INTR_STATUS_OFS) { 5154 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5155 "ahci port %d has overflow error", port); 5156 } 5157 5158 if (intr_status & AHCI_INTR_STATUS_INFS) { 5159 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5160 "ahci port %d has interface non fatal error", port); 5161 } 5162 5163 /* 5164 * Record the error occurred command's slot. 5165 */ 5166 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 5167 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5168 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5169 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5170 5171 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5172 AHCI_CMD_STATUS_CCS_SHIFT; 5173 5174 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5175 satapkt = ahci_portp->ahciport_err_retri_pkt; 5176 ASSERT(satapkt != NULL); 5177 ASSERT(current_slot == 0); 5178 } else { 5179 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5180 } 5181 5182 if (satapkt != NULL) { 5183 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5184 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 5185 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 5186 satapkt->satapkt_cmd.satacmd_cmd_reg); 5187 5188 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5189 "ahci_intr_non_fatal_error: port %d, " 5190 "satapkt 0x%p is being processed when error occurs", 5191 port, (void *)satapkt); 5192 5193 /* 5194 * PRD Byte Count field of command header is not 5195 * required to reflect the total number of bytes 5196 * transferred when an overflow occurs, so here 5197 * just log the value. 5198 */ 5199 cmd_dmacount = 5200 ahci_portp->ahciport_prd_bytecounts[current_slot]; 5201 if (cmd_dmacount) { 5202 cmd_header = &ahci_portp-> 5203 ahciport_cmd_list[current_slot]; 5204 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5205 "ahci_intr_non_fatal_error: port %d, " 5206 "PRD Byte Count = 0x%x, " 5207 "ahciport_prd_bytecounts = 0x%x", port, 5208 cmd_header->ahcich_prd_byte_count, 5209 cmd_dmacount); 5210 } 5211 } 5212 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5213 /* 5214 * For queued command, list those command which have already 5215 * been transmitted to the device and still not completed. 5216 */ 5217 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5218 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 5219 5220 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5221 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5222 5223 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 5224 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 5225 "port_sactive = 0x%x port_cmd_issue = 0x%x", 5226 ahci_portp->ahciport_pending_ncq_tags, 5227 port_sactive, port_cmd_issue); 5228 5229 current_tags = ahci_portp->ahciport_pending_ncq_tags & 5230 port_sactive & ~port_cmd_issue & 5231 AHCI_NCQ_SLOT_MASK(ahci_portp); 5232 5233 while (current_tags) { 5234 current_slot = ddi_ffs(current_tags) - 1; 5235 if (current_slot == -1) { 5236 goto out; 5237 } 5238 5239 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5240 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 5241 ahci_ctlp, "ahci_intr_non_fatal_error: " 5242 "port %d, satapkt 0x%p is outstanding when " 5243 "error occurs", port, (void *)satapkt); 5244 } 5245 } 5246 out: 5247 #endif 5248 mutex_exit(&ahci_portp->ahciport_mutex); 5249 5250 return (AHCI_SUCCESS); 5251 } 5252 5253 /* 5254 * According to the AHCI spec, the error types include system memory 5255 * errors, interface errors, port multiplier errors, device errors, 5256 * command list overflow, command list underflow, native command 5257 * queuing tag errors and pio data transfer errors. 5258 * 5259 * System memory errors such as target abort, master abort, and parity 5260 * may cause the host to stop, and they are serious errors and needed 5261 * to be recovered with software intervention. When system software 5262 * has given a pointer to the HBA that doesn't exist in physical memory, 5263 * a master/target abort error occurs, and PxIS.HBFS will be set. A 5264 * data error such as CRC or parity occurs, the HBA aborts the transfer 5265 * (if necessary) and PxIS.HBDS will be set. 5266 * 5267 * Interface errors are errors that occur due to electrical issues on 5268 * the interface, or protocol miscommunication between the device and 5269 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 5270 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 5271 * causes PxIS.IFS/PxIS.INFS to be set are 5272 * 1. in PxSERR.ERR, P bit is set to '1' 5273 * 2. in PxSERR.DIAG, C or H bit is set to '1' 5274 * 3. PhyRdy drop unexpectly, N bit is set to '1' 5275 * If the error occurred during a non-data FIS, the FIS must be 5276 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 5277 * the error occurred during a data FIS, the transfer will stop, so 5278 * the error is fatal and PxIS.IFS is set. 5279 * 5280 * When a FIS arrives that updates the taskfile, the HBA checks to see 5281 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 5282 * stops processing any more commands. 5283 * 5284 * Command list overflow is defined as software building a command table 5285 * that has fewer total bytes than the transaction given to the device. 5286 * On device writes, the HBA will run out of data, and on reads, there 5287 * will be no room to put the data. For an overflow on data read, either 5288 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 5289 * For an overflow on data write, setting PxIS.OFS is optional for both 5290 * DMA and PIO, and a COMRESET is required by software to clean up from 5291 * this serious error. 5292 * 5293 * Command list underflow is defined as software building a command 5294 * table that has more total bytes than the transaction given to the 5295 * device. For data writes, both PIO and DMA, the device will detect 5296 * an error and end the transfer. And these errors are most likely going 5297 * to be fatal errors that will cause the port to be restarted. For 5298 * data reads, the HBA updates its PRD byte count, and may be 5299 * able to continue normally, but is not required to. And The HBA is 5300 * not required to detect underflow conditions for native command 5301 * queuing command. 5302 * 5303 * The HBA does not actively check incoming DMA Setup FISes to ensure 5304 * that the PxSACT register bit for that slot is set. Existing error 5305 * mechanisms, such as host bus failure, or bad protocol, are used to 5306 * recover from this case. 5307 * 5308 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 5309 * DATA FIS must be an integral number of Dwords. If the HBA receives 5310 * a request which is not an integral number of Dwords, the HBA 5311 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 5312 * software restarts the port. And the HBA ensures that the size 5313 * of the DATA FIS received during a PIO command matches the size in 5314 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 5315 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 5316 * stop running until software restarts the port. 5317 */ 5318 /* 5319 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 5320 * 5321 * PxIS.IFS indicates that the hba encountered an error on the serial ata 5322 * interface which caused the transfer to stop. 5323 * 5324 * PxIS.HBDS indicates that the hba encountered a data error 5325 * (uncorrectable ecc/parity) when reading from or writing to system memory. 5326 * 5327 * PxIS.HBFS indicates that the hba encountered a host bus error that it 5328 * cannot recover from, such as a bad software pointer. 5329 * 5330 * PxIS.TFES is set whenever the status register is updated by the device 5331 * and the error bit (bit 0) is set. 5332 */ 5333 static int 5334 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 5335 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 5336 { 5337 uint32_t port_cmd_status; 5338 uint32_t port_serror; 5339 uint32_t task_file_status; 5340 int failed_slot; 5341 sata_pkt_t *spkt = NULL; 5342 uint8_t err_byte; 5343 ahci_event_arg_t *args; 5344 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 5345 5346 mutex_enter(&ahci_portp->ahciport_mutex); 5347 5348 /* 5349 * ahci_intr_phyrdy_change() may have rendered it to 5350 * SATA_DTYPE_NONE. 5351 */ 5352 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5353 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5354 "ahci_intr_fatal_error: port %d no device attached, " 5355 "and just return without doing anything", port); 5356 goto out0; 5357 } 5358 5359 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5360 /* 5361 * Read PxCMD.CCS to determine the slot that the HBA 5362 * was processing when the error occurred. 5363 */ 5364 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5365 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5366 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5367 AHCI_CMD_STATUS_CCS_SHIFT; 5368 5369 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5370 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5371 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5372 "fatal error occurred for port %d", spkt, port); 5373 5374 if (intr_status & AHCI_INTR_STATUS_TFES) { 5375 task_file_status = ddi_get32( 5376 ahci_ctlp->ahcictl_ahci_acc_handle, 5377 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5378 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5379 "ahci_intr_fatal_error: port %d " 5380 "task_file_status = 0x%x", port, task_file_status); 5381 5382 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5383 >> AHCI_TFD_ERR_SHIFT; 5384 5385 /* 5386 * Won't emit the error message if it is an IDENTIFY 5387 * DEVICE command sent to an ATAPI device. 5388 */ 5389 if ((spkt != NULL) && 5390 (spkt->satapkt_cmd.satacmd_cmd_reg == 5391 SATAC_ID_DEVICE) && 5392 (err_byte == SATA_ERROR_ABORT)) 5393 goto out1; 5394 5395 /* 5396 * Won't emit the error message if it is an ATAPI PACKET 5397 * command 5398 */ 5399 if ((spkt != NULL) && 5400 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5401 goto out1; 5402 } 5403 } 5404 5405 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5406 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5407 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5408 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0); 5409 out1: 5410 /* Prepare the argument for the taskq */ 5411 args = ahci_portp->ahciport_event_args; 5412 args->ahciea_ctlp = (void *)ahci_ctlp; 5413 args->ahciea_portp = (void *)ahci_portp; 5414 args->ahciea_event = intr_status; 5415 5416 /* Start the taskq to handle error recovery */ 5417 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 5418 ahci_events_handler, 5419 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5420 cmn_err(CE_WARN, "!ahci%d: ahci start taskq for event handler " 5421 "failed", instance); 5422 } 5423 out0: 5424 mutex_exit(&ahci_portp->ahciport_mutex); 5425 5426 return (AHCI_SUCCESS); 5427 } 5428 5429 /* 5430 * Hot Plug Operation for platforms that support Cold Presence Detect. 5431 * 5432 * When set, a device status has changed as detected by the cold presence 5433 * detect logic. This bit can either be set due to a non-connected port 5434 * receiving a device, or a connected port having its device removed. 5435 * This bit is only valid if the port supports cold presence detect as 5436 * indicated by PxCMD.CPD set to '1'. 5437 * 5438 * At the moment, this interrupt is not needed and disabled and we just 5439 * log the debug message. 5440 */ 5441 static int 5442 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5443 ahci_port_t *ahci_portp, uint8_t port) 5444 { 5445 uint32_t port_cmd_status; 5446 sata_device_t sdevice; 5447 5448 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5449 "ahci_intr_cold_port_detect enter, port %d", port); 5450 5451 mutex_enter(&ahci_portp->ahciport_mutex); 5452 5453 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5454 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5455 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5456 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5457 "port %d does not support cold presence detect, so " 5458 "we just ignore this interrupt", port); 5459 mutex_exit(&ahci_portp->ahciport_mutex); 5460 return (AHCI_SUCCESS); 5461 } 5462 5463 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5464 "port %d device status has changed", port); 5465 5466 bzero((void *)&sdevice, sizeof (sata_device_t)); 5467 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5468 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5469 sdevice.satadev_addr.pmport = 0; 5470 sdevice.satadev_state = SATA_PSTATE_PWRON; 5471 5472 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5473 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5474 "port %d: a device is hot plugged", port); 5475 mutex_exit(&ahci_portp->ahciport_mutex); 5476 sata_hba_event_notify( 5477 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5478 &sdevice, 5479 SATA_EVNT_DEVICE_ATTACHED); 5480 mutex_enter(&ahci_portp->ahciport_mutex); 5481 5482 } else { 5483 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5484 "port %d: a device is hot unplugged", port); 5485 mutex_exit(&ahci_portp->ahciport_mutex); 5486 sata_hba_event_notify( 5487 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5488 &sdevice, 5489 SATA_EVNT_DEVICE_DETACHED); 5490 mutex_enter(&ahci_portp->ahciport_mutex); 5491 } 5492 5493 mutex_exit(&ahci_portp->ahciport_mutex); 5494 5495 return (AHCI_SUCCESS); 5496 } 5497 5498 /* 5499 * Enable the interrupts for a particular port. 5500 * 5501 * WARNING!!! ahciport_mutex should be acquired before the function 5502 * is called. 5503 */ 5504 static void 5505 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5506 { 5507 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5508 "ahci_enable_port_intrs enter, port %d", port); 5509 5510 /* 5511 * Clear port interrupt status before enabling interrupt 5512 */ 5513 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5514 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5515 AHCI_PORT_INTR_MASK); 5516 5517 /* 5518 * Clear the pending bit from IS.IPS 5519 */ 5520 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5521 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5522 5523 /* 5524 * Enable the following interrupts: 5525 * Device to Host Register FIS Interrupt (DHRS) 5526 * PIO Setup FIS Interrupt (PSS) 5527 * Set Device Bits Interrupt (SDBS) 5528 * Unknown FIS Interrupt (UFS) 5529 * Port Connect Change Status (PCS) 5530 * PhyRdy Change Status (PRCS) 5531 * Overflow Status (OFS) 5532 * Interface Non-fatal Error Status (INFS) 5533 * Interface Fatal Error Status (IFS) 5534 * Host Bus Data Error Status (HBDS) 5535 * Host Bus Fatal Error Status (HBFS) 5536 * Task File Error Status (TFES) 5537 */ 5538 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5539 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5540 (AHCI_INTR_STATUS_DHRS | 5541 AHCI_INTR_STATUS_PSS | 5542 AHCI_INTR_STATUS_SDBS | 5543 AHCI_INTR_STATUS_UFS | 5544 AHCI_INTR_STATUS_DPS | 5545 AHCI_INTR_STATUS_PCS | 5546 AHCI_INTR_STATUS_PRCS | 5547 AHCI_INTR_STATUS_OFS | 5548 AHCI_INTR_STATUS_INFS | 5549 AHCI_INTR_STATUS_IFS | 5550 AHCI_INTR_STATUS_HBDS | 5551 AHCI_INTR_STATUS_HBFS | 5552 AHCI_INTR_STATUS_TFES)); 5553 } 5554 5555 /* 5556 * Enable interrupts for all the ports. 5557 * 5558 * WARNING!!! ahcictl_mutex should be acquired before the function 5559 * is called. 5560 */ 5561 static void 5562 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5563 { 5564 uint32_t ghc_control; 5565 5566 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5567 5568 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5569 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5570 5571 ghc_control |= AHCI_HBA_GHC_IE; 5572 5573 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5574 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5575 } 5576 5577 /* 5578 * Disable interrupts for a particular port. 5579 * 5580 * WARNING!!! ahciport_mutex should be acquired before the function 5581 * is called. 5582 */ 5583 static void 5584 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5585 { 5586 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5587 "ahci_disable_port_intrs enter, port %d", port); 5588 5589 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5590 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5591 } 5592 5593 /* 5594 * Disable interrupts for the whole HBA. 5595 * 5596 * The global bit is cleared, then all interrupt sources from all 5597 * ports are disabled. 5598 * 5599 * WARNING!!! ahcictl_mutex should be acquired before the function 5600 * is called. 5601 */ 5602 static void 5603 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5604 { 5605 uint32_t ghc_control; 5606 5607 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5608 5609 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5610 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5611 5612 ghc_control &= ~ AHCI_HBA_GHC_IE; 5613 5614 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5615 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5616 } 5617 5618 /* 5619 * Handle INTx and legacy interrupts. 5620 */ 5621 static int 5622 ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 5623 { 5624 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5625 int actual, count = 0; 5626 int x, y, rc, inum = 0; 5627 5628 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5629 "ahci_add_legacy_intrs enter"); 5630 5631 /* get number of interrupts. */ 5632 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 5633 if ((rc != DDI_SUCCESS) || (count == 0)) { 5634 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5635 "ddi_intr_get_nintrs() failed, " 5636 "rc %d count %d\n", rc, count); 5637 return (DDI_FAILURE); 5638 } 5639 5640 /* Allocate an array of interrupt handles. */ 5641 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5642 ahci_ctlp->ahcictl_intr_htable = 5643 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5644 5645 /* call ddi_intr_alloc(). */ 5646 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5647 DDI_INTR_TYPE_FIXED, 5648 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 5649 5650 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5651 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5652 "ddi_intr_alloc() failed, rc %d\n", rc); 5653 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5654 ahci_ctlp->ahcictl_intr_size); 5655 return (DDI_FAILURE); 5656 } 5657 5658 if (actual < count) { 5659 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5660 "Requested: %d, Received: %d", count, actual); 5661 5662 for (x = 0; x < actual; x++) { 5663 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5664 } 5665 5666 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5667 ahci_ctlp->ahcictl_intr_size); 5668 return (DDI_FAILURE); 5669 } 5670 5671 ahci_ctlp->ahcictl_intr_cnt = actual; 5672 5673 /* Get intr priority. */ 5674 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5675 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5676 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5677 "ddi_intr_get_pri() failed"); 5678 5679 for (x = 0; x < actual; x++) { 5680 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5681 } 5682 5683 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5684 ahci_ctlp->ahcictl_intr_size); 5685 return (DDI_FAILURE); 5686 } 5687 5688 /* Test for high level interrupt. */ 5689 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5690 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5691 "ahci_add_legacy_intrs: Hi level intr not supported"); 5692 5693 for (x = 0; x < actual; x++) { 5694 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5695 } 5696 5697 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5698 sizeof (ddi_intr_handle_t)); 5699 5700 return (DDI_FAILURE); 5701 } 5702 5703 /* Call ddi_intr_add_handler(). */ 5704 for (x = 0; x < actual; x++) { 5705 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5706 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5707 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5708 "ddi_intr_add_handler() failed"); 5709 5710 for (y = 0; y < actual; y++) { 5711 (void) ddi_intr_free( 5712 ahci_ctlp->ahcictl_intr_htable[y]); 5713 } 5714 5715 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5716 ahci_ctlp->ahcictl_intr_size); 5717 return (DDI_FAILURE); 5718 } 5719 } 5720 5721 /* Call ddi_intr_enable() for legacy interrupts. */ 5722 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5723 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 5724 } 5725 5726 return (DDI_SUCCESS); 5727 } 5728 5729 /* 5730 * Handle MSI interrupts. 5731 */ 5732 static int 5733 ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 5734 { 5735 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5736 int count, avail, actual; 5737 int x, y, rc, inum = 0; 5738 5739 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5740 "ahci_add_msi_intrs enter"); 5741 5742 /* get number of interrupts. */ 5743 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 5744 if ((rc != DDI_SUCCESS) || (count == 0)) { 5745 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5746 "ddi_intr_get_nintrs() failed, " 5747 "rc %d count %d\n", rc, count); 5748 return (DDI_FAILURE); 5749 } 5750 5751 /* get number of available interrupts. */ 5752 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 5753 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5754 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5755 "ddi_intr_get_navail() failed, " 5756 "rc %d avail %d\n", rc, avail); 5757 return (DDI_FAILURE); 5758 } 5759 5760 #if AHCI_DEBUG 5761 if (avail < count) { 5762 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5763 "ddi_intr_get_nvail returned %d, navail() returned %d", 5764 count, avail); 5765 } 5766 #endif 5767 5768 /* Allocate an array of interrupt handles. */ 5769 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5770 ahci_ctlp->ahcictl_intr_htable = 5771 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5772 5773 /* call ddi_intr_alloc(). */ 5774 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5775 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5776 5777 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5778 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5779 "ddi_intr_alloc() failed, rc %d\n", rc); 5780 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5781 ahci_ctlp->ahcictl_intr_size); 5782 return (DDI_FAILURE); 5783 } 5784 5785 /* use interrupt count returned */ 5786 #if AHCI_DEBUG 5787 if (actual < count) { 5788 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5789 "Requested: %d, Received: %d", count, actual); 5790 } 5791 #endif 5792 5793 ahci_ctlp->ahcictl_intr_cnt = actual; 5794 5795 /* 5796 * Get priority for first msi, assume remaining are all the same. 5797 */ 5798 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5799 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5800 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5801 "ddi_intr_get_pri() failed"); 5802 5803 /* Free already allocated intr. */ 5804 for (y = 0; y < actual; y++) { 5805 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5806 } 5807 5808 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5809 ahci_ctlp->ahcictl_intr_size); 5810 return (DDI_FAILURE); 5811 } 5812 5813 /* Test for high level interrupt. */ 5814 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5815 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5816 "ahci_add_msi_intrs: Hi level intr not supported"); 5817 5818 /* Free already allocated intr. */ 5819 for (y = 0; y < actual; y++) { 5820 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5821 } 5822 5823 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5824 sizeof (ddi_intr_handle_t)); 5825 5826 return (DDI_FAILURE); 5827 } 5828 5829 /* Call ddi_intr_add_handler(). */ 5830 for (x = 0; x < actual; x++) { 5831 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5832 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5833 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5834 "ddi_intr_add_handler() failed"); 5835 5836 /* Free already allocated intr. */ 5837 for (y = 0; y < actual; y++) { 5838 (void) ddi_intr_free( 5839 ahci_ctlp->ahcictl_intr_htable[y]); 5840 } 5841 5842 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5843 ahci_ctlp->ahcictl_intr_size); 5844 return (DDI_FAILURE); 5845 } 5846 } 5847 5848 5849 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5850 &ahci_ctlp->ahcictl_intr_cap); 5851 5852 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5853 /* Call ddi_intr_block_enable() for MSI. */ 5854 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5855 ahci_ctlp->ahcictl_intr_cnt); 5856 } else { 5857 /* Call ddi_intr_enable() for MSI non block enable. */ 5858 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5859 (void) ddi_intr_enable( 5860 ahci_ctlp->ahcictl_intr_htable[x]); 5861 } 5862 } 5863 5864 return (DDI_SUCCESS); 5865 } 5866 5867 /* 5868 * Removes the registered interrupts irrespective of whether they 5869 * were legacy or MSI. 5870 * 5871 * WARNING!!! The controller interrupts must be disabled before calling 5872 * this routine. 5873 */ 5874 static void 5875 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5876 { 5877 int x; 5878 5879 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5880 5881 /* Disable all interrupts. */ 5882 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5883 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5884 /* Call ddi_intr_block_disable(). */ 5885 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5886 ahci_ctlp->ahcictl_intr_cnt); 5887 } else { 5888 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5889 (void) ddi_intr_disable( 5890 ahci_ctlp->ahcictl_intr_htable[x]); 5891 } 5892 } 5893 5894 /* Call ddi_intr_remove_handler(). */ 5895 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5896 (void) ddi_intr_remove_handler( 5897 ahci_ctlp->ahcictl_intr_htable[x]); 5898 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5899 } 5900 5901 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5902 } 5903 5904 /* 5905 * This routine tries to put port into P:NotRunning state by clearing 5906 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5907 * and PxCMD.CR to '0'. 5908 * 5909 * WARNING!!! ahciport_mutex should be acquired before the function 5910 * is called. 5911 */ 5912 static int 5913 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5914 ahci_port_t *ahci_portp, uint8_t port) 5915 { 5916 uint32_t port_cmd_status; 5917 int loop_count; 5918 5919 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5920 "ahci_put_port_into_notrunning_state enter: port %d", port); 5921 5922 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5923 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5924 5925 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5926 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5927 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5928 5929 /* Wait until PxCMD.CR is cleared */ 5930 loop_count = 0; 5931 do { 5932 port_cmd_status = 5933 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5934 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5935 5936 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5937 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5938 "clearing port %d CMD.CR timeout, " 5939 "port_cmd_status = 0x%x", port, 5940 port_cmd_status); 5941 /* 5942 * We are effectively timing out after 0.5 sec. 5943 * This value is specified in AHCI spec. 5944 */ 5945 break; 5946 } 5947 5948 /* Wait for 10 millisec */ 5949 drv_usecwait(10000); 5950 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5951 5952 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5953 5954 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5955 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5956 "ahci_put_port_into_notrunning_state: failed to clear " 5957 "PxCMD.CR to '0' after loop count: %d, and " 5958 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5959 return (AHCI_FAILURE); 5960 } else { 5961 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5962 "ahci_put_port_into_notrunning_state: succeeded to clear " 5963 "PxCMD.CR to '0' after loop count: %d, and " 5964 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5965 return (AHCI_SUCCESS); 5966 } 5967 } 5968 5969 /* 5970 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5971 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5972 * stable state, then set PxCMD.ST to '1' to start the port directly. 5973 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5974 * COMRESET to the device to put it in an idle state. 5975 * 5976 * The fifth argument returns whether the port reset is involved during 5977 * the process. 5978 * 5979 * The routine will be called under six scenarios: 5980 * 1. Initialize the port 5981 * 2. To abort the packet(s) 5982 * 3. To reset the port 5983 * 4. To activate the port 5984 * 5. Fatal error recovery 5985 * 6. To abort the timeout packet(s) 5986 * 5987 * WARNING!!! ahciport_mutex should be acquired before the function 5988 * is called. And ahciport_mutex will be released before the reset 5989 * event is reported to sata module by calling sata_hba_event_notify, 5990 * and then be acquired again later. 5991 * 5992 * NOTES!!! During this procedure, PxSERR register will be cleared, and 5993 * according to the spec, the clearance of three bits will also clear 5994 * three interrupt status bits. 5995 * 1. PxSERR.DIAG.F will clear PxIS.UFS 5996 * 2. PxSERR.DIAG.X will clear PxIS.PCS 5997 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 5998 * 5999 * Among these three interrupt events, the driver needs to take care of 6000 * PxIS.PRCS, which is the hot plug event. When the driver found out 6001 * a device was unplugged, it will call the interrupt handler. 6002 */ 6003 static int 6004 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 6005 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 6006 { 6007 uint32_t port_sstatus; 6008 uint32_t task_file_status; 6009 sata_device_t sdevice; 6010 int rval; 6011 int dev_exists_begin = 0; 6012 int dev_exists_end = 0; 6013 6014 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6015 "ahci_restart_port_wait_till_ready: port %d enter", port); 6016 6017 if ((flag != AHCI_PORT_INIT) && 6018 (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE)) 6019 dev_exists_begin = 1; 6020 6021 /* First clear PxCMD.ST */ 6022 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 6023 port); 6024 if (rval != AHCI_SUCCESS) 6025 /* 6026 * If PxCMD.CR does not clear within a reasonable time, it 6027 * may assume the interface is in a hung condition and may 6028 * continue with issuing the port reset. 6029 */ 6030 goto reset; 6031 6032 /* Then clear PxSERR */ 6033 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 6034 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 6035 AHCI_SERROR_CLEAR_ALL); 6036 6037 /* Then get PxTFD */ 6038 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6039 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 6040 6041 /* 6042 * Check whether the device is in a stable status, if yes, 6043 * then start the port directly. However for ahci_tran_dport_reset, 6044 * we may have to perform a port reset. 6045 */ 6046 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 6047 !(flag & AHCI_PORT_RESET)) 6048 goto out; 6049 6050 reset: 6051 /* 6052 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 6053 * a COMRESET to the device 6054 */ 6055 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 6056 6057 if (reset_flag != NULL) 6058 *reset_flag = 1; 6059 6060 /* Indicate to the framework that a reset has happened. */ 6061 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 6062 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 6063 /* Set the reset in progress flag */ 6064 ahci_portp->ahciport_reset_in_progress = 1; 6065 6066 bzero((void *)&sdevice, sizeof (sata_device_t)); 6067 sdevice.satadev_addr.cport = 6068 ahci_ctlp->ahcictl_port_to_cport[port]; 6069 sdevice.satadev_addr.pmport = 0; 6070 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6071 6072 sdevice.satadev_state = SATA_DSTATE_RESET | 6073 SATA_DSTATE_PWR_ACTIVE; 6074 if (ahci_ctlp->ahcictl_sata_hba_tran) { 6075 mutex_exit(&ahci_portp->ahciport_mutex); 6076 sata_hba_event_notify( 6077 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 6078 &sdevice, 6079 SATA_EVNT_DEVICE_RESET); 6080 mutex_enter(&ahci_portp->ahciport_mutex); 6081 } 6082 6083 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 6084 "port %d sending event up: SATA_EVNT_RESET", port); 6085 } else { 6086 ahci_portp->ahciport_reset_in_progress = 0; 6087 } 6088 6089 out: 6090 /* Start the port if not in initialization phase */ 6091 if (flag & AHCI_PORT_INIT) 6092 return (rval); 6093 6094 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 6095 6096 /* SStatus tells the presence of device. */ 6097 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6098 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 6099 6100 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 6101 dev_exists_end = 1; 6102 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 6103 } 6104 6105 /* Check whether a hot plug event happened */ 6106 if (dev_exists_begin == 1 && dev_exists_end == 0) { 6107 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6108 "ahci_restart_port_wait_till_ready: port %d " 6109 "device is removed", port); 6110 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 6111 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6112 "ahci_restart_port_wait_till_ready: port %d " 6113 "AHCI_PORT_FLAG_NODEV flag is set", port); 6114 mutex_exit(&ahci_portp->ahciport_mutex); 6115 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 6116 mutex_enter(&ahci_portp->ahciport_mutex); 6117 } 6118 6119 return (rval); 6120 } 6121 6122 /* 6123 * This routine may be called under four scenarios: 6124 * a) do the recovery from fatal error 6125 * b) or we need to timeout some commands 6126 * c) or we need to abort some commands 6127 * d) or we need reset device/port/controller 6128 * 6129 * In all these scenarios, we need to send any pending unfinished 6130 * commands up to sata framework. 6131 * 6132 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6133 */ 6134 static void 6135 ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 6136 ahci_port_t *ahci_portp, 6137 uint32_t slot_status, 6138 uint32_t failed_tags, 6139 uint32_t timeout_tags, 6140 uint32_t aborted_tags, 6141 uint32_t reset_tags) 6142 { 6143 uint32_t finished_tags = 0; 6144 uint32_t unfinished_tags = 0; 6145 int tmp_slot; 6146 sata_pkt_t *satapkt; 6147 int ncq_cmd_in_progress = 0; 6148 int err_retri_cmd_in_progress = 0; 6149 6150 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6151 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 6152 ahci_portp->ahciport_port_num, slot_status); 6153 6154 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6155 "ahci_mop_commands: failed_tags: 0x%x, " 6156 "timeout_tags: 0x%x aborted_tags: 0x%x, " 6157 "reset_tags: 0x%x", failed_tags, 6158 timeout_tags, aborted_tags, reset_tags); 6159 6160 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6161 finished_tags = ahci_portp->ahciport_pending_tags & 6162 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6163 6164 unfinished_tags = slot_status & 6165 AHCI_SLOT_MASK(ahci_ctlp) & 6166 ~failed_tags & 6167 ~aborted_tags & 6168 ~reset_tags & 6169 ~timeout_tags; 6170 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6171 ncq_cmd_in_progress = 1; 6172 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6173 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6174 6175 unfinished_tags = slot_status & 6176 AHCI_NCQ_SLOT_MASK(ahci_portp) & 6177 ~failed_tags & 6178 ~aborted_tags & 6179 ~reset_tags & 6180 ~timeout_tags; 6181 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6182 6183 /* 6184 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is 6185 * set, it means REQUEST SENSE or READ LOG EXT command doesn't 6186 * complete successfully due to one of the following three 6187 * conditions: 6188 * 6189 * 1. Fatal error - failed_tags includes its slot 6190 * 2. Timed out - timeout_tags includes its slot 6191 * 3. Aborted when hot unplug - aborted_tags includes its 6192 * slot 6193 * 6194 * Please note that the command is always sent down in Slot 0 6195 */ 6196 err_retri_cmd_in_progress = 1; 6197 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 6198 "ahci_mop_commands is called for port %d while " 6199 "REQUEST SENSE or READ LOG EXT for error retrieval " 6200 "is being executed", ahci_portp->ahciport_port_num); 6201 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 6202 ASSERT(slot_status == 0x1); 6203 } 6204 6205 /* Send up finished packets with SATA_PKT_COMPLETED */ 6206 while (finished_tags) { 6207 tmp_slot = ddi_ffs(finished_tags) - 1; 6208 if (tmp_slot == -1) { 6209 break; 6210 } 6211 6212 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6213 ASSERT(satapkt != NULL); 6214 6215 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 6216 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 6217 (void *)satapkt); 6218 6219 /* 6220 * Cannot fetch the return register content since the port 6221 * was restarted, so the corresponding tag will be set to 6222 * aborted tags. 6223 */ 6224 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6225 CLEAR_BIT(finished_tags, tmp_slot); 6226 aborted_tags |= tmp_slot; 6227 continue; 6228 } 6229 6230 if (ncq_cmd_in_progress) 6231 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6232 tmp_slot); 6233 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6234 CLEAR_BIT(finished_tags, tmp_slot); 6235 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6236 6237 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6238 } 6239 6240 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 6241 while (failed_tags) { 6242 if (err_retri_cmd_in_progress) { 6243 satapkt = ahci_portp->ahciport_err_retri_pkt; 6244 ASSERT(satapkt != NULL); 6245 ASSERT(failed_tags == 0x1); 6246 6247 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6248 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6249 (void *)satapkt); 6250 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6251 break; 6252 } 6253 6254 tmp_slot = ddi_ffs(failed_tags) - 1; 6255 if (tmp_slot == -1) { 6256 break; 6257 } 6258 6259 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6260 ASSERT(satapkt != NULL); 6261 6262 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6263 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6264 (void *)satapkt); 6265 6266 if (ncq_cmd_in_progress) 6267 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6268 tmp_slot); 6269 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6270 CLEAR_BIT(failed_tags, tmp_slot); 6271 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6272 6273 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6274 } 6275 6276 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 6277 while (timeout_tags) { 6278 if (err_retri_cmd_in_progress) { 6279 satapkt = ahci_portp->ahciport_err_retri_pkt; 6280 ASSERT(satapkt != NULL); 6281 ASSERT(timeout_tags == 0x1); 6282 6283 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6284 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6285 (void *)satapkt); 6286 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6287 break; 6288 } 6289 6290 tmp_slot = ddi_ffs(timeout_tags) - 1; 6291 if (tmp_slot == -1) { 6292 break; 6293 } 6294 6295 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6296 ASSERT(satapkt != NULL); 6297 6298 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6299 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6300 (void *)satapkt); 6301 6302 if (ncq_cmd_in_progress) 6303 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6304 tmp_slot); 6305 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6306 CLEAR_BIT(timeout_tags, tmp_slot); 6307 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6308 6309 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6310 } 6311 6312 /* Send up aborted packets with SATA_PKT_ABORTED */ 6313 while (aborted_tags) { 6314 if (err_retri_cmd_in_progress) { 6315 satapkt = ahci_portp->ahciport_err_retri_pkt; 6316 ASSERT(satapkt != NULL); 6317 ASSERT(aborted_tags == 0x1); 6318 6319 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6320 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6321 (void *)satapkt); 6322 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6323 break; 6324 } 6325 6326 tmp_slot = ddi_ffs(aborted_tags) - 1; 6327 if (tmp_slot == -1) { 6328 break; 6329 } 6330 6331 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6332 ASSERT(satapkt != NULL); 6333 6334 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6335 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6336 (void *)satapkt); 6337 6338 if (ncq_cmd_in_progress) 6339 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6340 tmp_slot); 6341 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6342 CLEAR_BIT(aborted_tags, tmp_slot); 6343 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6344 6345 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6346 } 6347 6348 /* Send up reset packets with SATA_PKT_RESET. */ 6349 while (reset_tags) { 6350 tmp_slot = ddi_ffs(reset_tags) - 1; 6351 if (tmp_slot == -1) { 6352 break; 6353 } 6354 6355 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6356 ASSERT(satapkt != NULL); 6357 6358 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6359 "sending up pkt 0x%p with SATA_PKT_RESET", 6360 (void *)satapkt); 6361 6362 if (ncq_cmd_in_progress) 6363 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6364 tmp_slot); 6365 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6366 CLEAR_BIT(reset_tags, tmp_slot); 6367 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6368 6369 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6370 } 6371 6372 /* Send up unfinished packets with SATA_PKT_RESET */ 6373 while (unfinished_tags) { 6374 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6375 if (tmp_slot == -1) { 6376 break; 6377 } 6378 6379 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6380 ASSERT(satapkt != NULL); 6381 6382 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6383 "sending up pkt 0x%p with SATA_PKT_RESET", 6384 (void *)satapkt); 6385 6386 if (ncq_cmd_in_progress) 6387 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6388 tmp_slot); 6389 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6390 CLEAR_BIT(unfinished_tags, tmp_slot); 6391 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6392 6393 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6394 } 6395 6396 ahci_portp->ahciport_mop_in_progress--; 6397 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6398 6399 if (ahci_portp->ahciport_mop_in_progress == 0) 6400 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6401 } 6402 6403 /* 6404 * This routine is going to first request a READ LOG EXT sata pkt from sata 6405 * module, and then deliver it to the HBA to get the ncq failure context. 6406 * The return value is the exactly failed tags. 6407 */ 6408 static uint32_t 6409 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6410 uint8_t port) 6411 { 6412 sata_device_t sdevice; 6413 sata_pkt_t *rdlog_spkt, *spkt; 6414 ddi_dma_handle_t buf_dma_handle; 6415 int loop_count; 6416 int rval; 6417 int failed_slot; 6418 uint32_t failed_tags = 0; 6419 struct sata_ncq_error_recovery_page *ncq_err_page; 6420 6421 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6422 "ahci_get_rdlogext_data enter: port %d", port); 6423 6424 /* Prepare the sdevice data */ 6425 bzero((void *)&sdevice, sizeof (sata_device_t)); 6426 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6427 6428 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6429 sdevice.satadev_addr.pmport = 0; 6430 6431 /* 6432 * Call the sata hba interface to get a rdlog spkt 6433 */ 6434 loop_count = 0; 6435 loop: 6436 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6437 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6438 if (rdlog_spkt == NULL) { 6439 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6440 /* Sleep for a while */ 6441 delay(AHCI_10MS_TICKS); 6442 goto loop; 6443 } 6444 /* Timed out after 1s */ 6445 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6446 "failed to get rdlog spkt for port %d", port); 6447 return (failed_tags); 6448 } 6449 6450 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6451 6452 /* 6453 * This flag is used to handle the specific error recovery when the 6454 * READ LOG EXT command gets a failure (fatal error or time-out). 6455 */ 6456 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6457 6458 /* 6459 * This start is not supposed to fail because after port is restarted, 6460 * the whole command list is empty. 6461 */ 6462 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6463 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6464 ahci_portp->ahciport_err_retri_pkt = NULL; 6465 6466 /* Remove the flag after READ LOG EXT command is completed */ 6467 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6468 6469 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6470 /* Update the request log data */ 6471 buf_dma_handle = *(ddi_dma_handle_t *) 6472 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6473 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6474 DDI_DMA_SYNC_FORKERNEL); 6475 if (rval == DDI_SUCCESS) { 6476 ncq_err_page = 6477 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6478 satapkt_cmd.satacmd_bp->b_un.b_addr; 6479 6480 /* Get the failed tag */ 6481 failed_slot = ncq_err_page->ncq_tag; 6482 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6483 "ahci_get_rdlogext_data: port %d " 6484 "failed slot %d", port, failed_slot); 6485 if (failed_slot & NQ) { 6486 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6487 "the failed slot is not a valid tag"); 6488 goto out; 6489 } 6490 6491 failed_slot &= NCQ_TAG_MASK; 6492 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6493 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6494 "ahci_get_rdlogext_data: failed spkt 0x%p", 6495 (void *)spkt); 6496 if (spkt == NULL) { 6497 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6498 "the failed slot spkt is NULL") 6499 goto out; 6500 } 6501 6502 failed_tags = 0x1 << failed_slot; 6503 6504 /* Fill out the error context */ 6505 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6506 ncq_err_page); 6507 ahci_update_sata_registers(ahci_ctlp, port, 6508 &spkt->satapkt_device); 6509 } 6510 } 6511 out: 6512 sata_free_error_retrieval_pkt(rdlog_spkt); 6513 6514 return (failed_tags); 6515 } 6516 6517 /* 6518 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6519 * module, and then deliver it to the HBA to get the sense data and copy 6520 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6521 * SENSE sata pkt later. 6522 */ 6523 static void 6524 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6525 uint8_t port, sata_pkt_t *spkt) 6526 { 6527 sata_device_t sdevice; 6528 sata_pkt_t *rs_spkt; 6529 sata_cmd_t *sata_cmd; 6530 ddi_dma_handle_t buf_dma_handle; 6531 int loop_count; 6532 #if AHCI_DEBUG 6533 struct scsi_extended_sense *rqsense; 6534 #endif 6535 6536 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6537 "ahci_get_rqsense_data enter: port %d", port); 6538 6539 /* Prepare the sdevice data */ 6540 bzero((void *)&sdevice, sizeof (sata_device_t)); 6541 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6542 6543 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6544 sdevice.satadev_addr.pmport = 0; 6545 6546 sata_cmd = &spkt->satapkt_cmd; 6547 6548 /* 6549 * Call the sata hba interface to get a rs spkt 6550 */ 6551 loop_count = 0; 6552 loop: 6553 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6554 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6555 if (rs_spkt == NULL) { 6556 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6557 /* Sleep for a while */ 6558 delay(AHCI_10MS_TICKS); 6559 goto loop; 6560 6561 } 6562 /* Timed out after 1s */ 6563 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6564 "failed to get rs spkt for port %d", port); 6565 return; 6566 } 6567 6568 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6569 6570 /* 6571 * This flag is used to handle the specific error recovery when the 6572 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6573 */ 6574 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6575 6576 /* 6577 * This start is not supposed to fail because after port is restarted, 6578 * the whole command list is empty. 6579 */ 6580 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6581 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6582 ahci_portp->ahciport_err_retri_pkt = NULL; 6583 6584 /* Remove the flag after REQUEST SENSE command is completed */ 6585 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6586 6587 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6588 /* Update the request sense data */ 6589 buf_dma_handle = *(ddi_dma_handle_t *) 6590 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6591 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6592 DDI_DMA_SYNC_FORKERNEL); 6593 /* Copy the request sense data */ 6594 bcopy(rs_spkt-> 6595 satapkt_cmd.satacmd_bp->b_un.b_addr, 6596 &sata_cmd->satacmd_rqsense, 6597 SATA_ATAPI_MIN_RQSENSE_LEN); 6598 #if AHCI_DEBUG 6599 rqsense = (struct scsi_extended_sense *) 6600 sata_cmd->satacmd_rqsense; 6601 6602 /* Dump the sense data */ 6603 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6604 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6605 "Sense data for satapkt %p ATAPI cmd 0x%x", 6606 spkt, sata_cmd->satacmd_acdb[0]); 6607 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6608 " es_code 0x%x es_class 0x%x " 6609 "es_key 0x%x es_add_code 0x%x " 6610 "es_qual_code 0x%x", 6611 rqsense->es_code, rqsense->es_class, 6612 rqsense->es_key, rqsense->es_add_code, 6613 rqsense->es_qual_code); 6614 #endif 6615 } 6616 6617 sata_free_error_retrieval_pkt(rs_spkt); 6618 } 6619 6620 /* 6621 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6622 * the port must be restarted. When the HBA detects thus error, it may try 6623 * to abort a transfer. And if the transfer was aborted, the device is 6624 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6625 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6626 * that the device is in a stable status and transfers may be restarted without 6627 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6628 * then the software will send the COMRESET to do the port reset. 6629 * 6630 * Software should perform the appropriate error recovery actions based on 6631 * whether non-queued commands were being issued or natived command queuing 6632 * commands were being issued. 6633 * 6634 * And software will complete the command that had the error with error mark 6635 * to higher level software. 6636 * 6637 * Fatal errors include the following: 6638 * PxIS.IFS - Interface Fatal Error Status 6639 * PxIS.HBDS - Host Bus Data Error Status 6640 * PxIS.HBFS - Host Bus Fatal Error Status 6641 * PxIS.TFES - Task File Error Status 6642 * 6643 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6644 */ 6645 static void 6646 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6647 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6648 { 6649 uint32_t port_cmd_status; 6650 uint32_t slot_status = 0; 6651 uint32_t failed_tags = 0; 6652 int failed_slot; 6653 int reset_flag = 0; 6654 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6655 sata_cmd_t *sata_cmd = NULL; 6656 sata_pkt_t *spkt = NULL; 6657 #if AHCI_DEBUG 6658 ahci_cmd_header_t *cmd_header; 6659 #endif 6660 6661 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6662 "ahci_fatal_error_recovery_handler enter: port %d", port); 6663 6664 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6665 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6666 6667 /* Read PxCI to see which commands are still outstanding */ 6668 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6669 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6670 6671 /* 6672 * Read PxCMD.CCS to determine the slot that the HBA 6673 * was processing when the error occurred. 6674 */ 6675 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6676 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6677 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6678 AHCI_CMD_STATUS_CCS_SHIFT; 6679 6680 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6681 spkt = ahci_portp->ahciport_err_retri_pkt; 6682 ASSERT(spkt != NULL); 6683 } else { 6684 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6685 if (spkt == NULL) { 6686 /* May happen when interface errors occur? */ 6687 goto next; 6688 } 6689 } 6690 6691 #if AHCI_DEBUG 6692 /* 6693 * Debugging purpose... 6694 */ 6695 if (ahci_portp->ahciport_prd_bytecounts[failed_slot]) { 6696 cmd_header = 6697 &ahci_portp->ahciport_cmd_list[failed_slot]; 6698 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 6699 "ahci_fatal_error_recovery_handler: port %d, " 6700 "PRD Byte Count = 0x%x, " 6701 "ahciport_prd_bytecounts = 0x%x", port, 6702 cmd_header->ahcich_prd_byte_count, 6703 ahci_portp->ahciport_prd_bytecounts[failed_slot]); 6704 } 6705 #endif 6706 6707 sata_cmd = &spkt->satapkt_cmd; 6708 6709 /* Fill out the status and error registers for PxIS.TFES */ 6710 if (intr_status & AHCI_INTR_STATUS_TFES) { 6711 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6712 ahcirf_d2h_register_fis); 6713 6714 /* Copy the error context back to the sata_cmd */ 6715 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6716 } 6717 6718 /* The failed command must be one of the outstanding commands */ 6719 failed_tags = 0x1 << failed_slot; 6720 ASSERT(failed_tags & slot_status); 6721 6722 /* Update the sata registers, especially PxSERR register */ 6723 ahci_update_sata_registers(ahci_ctlp, port, 6724 &spkt->satapkt_device); 6725 6726 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6727 /* Read PxSACT to see which commands are still outstanding */ 6728 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6729 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6730 } 6731 next: 6732 6733 #if AHCI_DEBUG 6734 /* 6735 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6736 * set, it means a fatal error happened after REQUEST SENSE command 6737 * or READ LOG EXT command is delivered to the HBA during the error 6738 * recovery process. At this time, the only outstanding command is 6739 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6740 */ 6741 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6742 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6743 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6744 "command or READ LOG EXT command for error data retrieval " 6745 "failed", port); 6746 ASSERT(slot_status == 0x1); 6747 ASSERT(failed_slot == 0x1); 6748 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6749 SCMD_REQUEST_SENSE || 6750 spkt->satapkt_cmd.satacmd_cmd_reg == 6751 SATAC_READ_LOG_EXT); 6752 } 6753 #endif 6754 6755 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6756 ahci_portp->ahciport_mop_in_progress++; 6757 6758 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6759 port, NULL, &reset_flag); 6760 6761 /* 6762 * Won't retrieve error information: 6763 * 1. Port reset was involved to recover 6764 * 2. Device is gone 6765 * 3. IDENTIFY DEVICE command sent to ATAPI device 6766 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6767 */ 6768 if (reset_flag || 6769 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6770 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6771 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6772 goto out; 6773 6774 /* 6775 * Deliver READ LOG EXT to gather information about the error when 6776 * a COMRESET has not been performed as part of the error recovery 6777 * during NCQ command processing. 6778 */ 6779 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6780 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6781 ahci_portp, port); 6782 goto out; 6783 } 6784 6785 /* 6786 * Deliver REQUEST SENSE for ATAPI command to gather information about 6787 * the error when a COMRESET has not been performed as part of the 6788 * error recovery. 6789 */ 6790 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPI) 6791 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6792 out: 6793 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6794 "ahci_fatal_error_recovery_handler: port %d fatal error " 6795 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6796 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6797 port, slot_status, ahci_portp->ahciport_pending_tags, 6798 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6799 6800 ahci_mop_commands(ahci_ctlp, 6801 ahci_portp, 6802 slot_status, 6803 failed_tags, /* failed tags */ 6804 0, /* timeout tags */ 6805 0, /* aborted tags */ 6806 0); /* reset tags */ 6807 } 6808 6809 /* 6810 * Handle events - fatal error recovery 6811 */ 6812 static void 6813 ahci_events_handler(void *args) 6814 { 6815 ahci_event_arg_t *ahci_event_arg; 6816 ahci_ctl_t *ahci_ctlp; 6817 ahci_port_t *ahci_portp; 6818 uint32_t event; 6819 uint8_t port; 6820 6821 ahci_event_arg = (ahci_event_arg_t *)args; 6822 6823 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6824 ahci_portp = ahci_event_arg->ahciea_portp; 6825 event = ahci_event_arg->ahciea_event; 6826 port = ahci_portp->ahciport_port_num; 6827 6828 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6829 "ahci_events_handler enter: port %d intr_status = 0x%x", 6830 port, event); 6831 6832 mutex_enter(&ahci_portp->ahciport_mutex); 6833 6834 /* 6835 * ahci_intr_phyrdy_change() may have rendered it to 6836 * SATA_DTYPE_NONE. 6837 */ 6838 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6839 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6840 "ahci_events_handler: port %d no device attached, " 6841 "and just return without doing anything", port); 6842 goto out; 6843 } 6844 6845 if (event & (AHCI_INTR_STATUS_IFS | 6846 AHCI_INTR_STATUS_HBDS | 6847 AHCI_INTR_STATUS_HBFS | 6848 AHCI_INTR_STATUS_TFES)) 6849 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6850 port, event); 6851 6852 out: 6853 mutex_exit(&ahci_portp->ahciport_mutex); 6854 } 6855 6856 /* 6857 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6858 * detect there are some commands which are timed out. 6859 */ 6860 static void 6861 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6862 uint8_t port, uint32_t tmp_timeout_tags) 6863 { 6864 uint32_t slot_status = 0; 6865 uint32_t finished_tags = 0; 6866 uint32_t timeout_tags = 0; 6867 6868 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6869 "ahci_timeout_pkts enter: port %d", port); 6870 6871 mutex_enter(&ahci_portp->ahciport_mutex); 6872 6873 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6874 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6875 /* Read PxCI to see which commands are still outstanding */ 6876 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6877 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6878 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6879 /* Read PxSACT to see which commands are still outstanding */ 6880 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6881 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6882 } 6883 6884 #if AHCI_DEBUG 6885 /* 6886 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6887 * set, it means a fatal error happened after REQUEST SENSE command 6888 * or READ LOG EXT command is delivered to the HBA during the error 6889 * recovery process. At this time, the only outstanding command is 6890 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6891 */ 6892 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6893 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 6894 "ahci_timeout_pkts called while REQUEST SENSE " 6895 "command or READ LOG EXT command for error recovery " 6896 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 6897 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 6898 tmp_timeout_tags, slot_status, 6899 ahci_portp->ahciport_pending_tags, 6900 ahci_portp->ahciport_pending_ncq_tags); 6901 ASSERT(slot_status == 0x1); 6902 } 6903 #endif 6904 6905 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6906 ahci_portp->ahciport_mop_in_progress++; 6907 6908 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6909 port, NULL, NULL); 6910 6911 /* 6912 * Re-identify timeout tags because some previously checked commands 6913 * could already complete. 6914 */ 6915 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6916 finished_tags = ahci_portp->ahciport_pending_tags & 6917 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6918 timeout_tags = tmp_timeout_tags & ~finished_tags; 6919 6920 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 6921 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6922 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 6923 "pending_tags = 0x%x ", 6924 port, finished_tags, timeout_tags, 6925 slot_status, ahci_portp->ahciport_pending_tags); 6926 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6927 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6928 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6929 timeout_tags = tmp_timeout_tags & ~finished_tags; 6930 6931 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 6932 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6933 "timeout_tags = 0x%x, port_sactive = 0x%x, " 6934 "pending_ncq_tags = 0x%x ", 6935 port, finished_tags, timeout_tags, 6936 slot_status, ahci_portp->ahciport_pending_ncq_tags); 6937 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6938 timeout_tags = tmp_timeout_tags; 6939 } 6940 6941 ahci_mop_commands(ahci_ctlp, 6942 ahci_portp, 6943 slot_status, 6944 0, /* failed tags */ 6945 timeout_tags, /* timeout tags */ 6946 0, /* aborted tags */ 6947 0); /* reset tags */ 6948 6949 mutex_exit(&ahci_portp->ahciport_mutex); 6950 } 6951 6952 /* 6953 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 6954 * for long time. 6955 */ 6956 static void 6957 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 6958 { 6959 ahci_port_t *ahci_portp; 6960 sata_pkt_t *spkt; 6961 uint32_t pending_tags; 6962 uint32_t timeout_tags; 6963 uint32_t port_cmd_status; 6964 uint32_t port_sactive; 6965 uint8_t port; 6966 int tmp_slot; 6967 int current_slot; 6968 uint32_t current_tags; 6969 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 6970 /* max number of cycles this packet should survive */ 6971 int max_life_cycles; 6972 6973 /* how many cycles this packet survived so far */ 6974 int watched_cycles; 6975 6976 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6977 6978 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6979 "ahci_watchdog_handler entered"); 6980 6981 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6982 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6983 continue; 6984 } 6985 6986 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6987 6988 mutex_enter(&ahci_portp->ahciport_mutex); 6989 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6990 mutex_exit(&ahci_portp->ahciport_mutex); 6991 continue; 6992 } 6993 6994 /* Skip the check for those ports in error recovery */ 6995 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 6996 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 6997 mutex_exit(&ahci_portp->ahciport_mutex); 6998 continue; 6999 } 7000 7001 pending_tags = 0; 7002 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 7003 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 7004 7005 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 7006 current_slot = 0; 7007 pending_tags = 0x1; 7008 } else if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7009 current_slot = 7010 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 7011 AHCI_CMD_STATUS_CCS_SHIFT; 7012 pending_tags = ahci_portp->ahciport_pending_tags; 7013 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 7014 port_sactive = ddi_get32( 7015 ahci_ctlp->ahcictl_ahci_acc_handle, 7016 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 7017 current_tags = port_sactive & 7018 ~port_cmd_status & 7019 AHCI_NCQ_SLOT_MASK(ahci_portp); 7020 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 7021 } 7022 7023 timeout_tags = 0; 7024 while (pending_tags) { 7025 tmp_slot = ddi_ffs(pending_tags) - 1; 7026 if (tmp_slot == -1) { 7027 break; 7028 } 7029 7030 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 7031 spkt = ahci_portp->ahciport_err_retri_pkt; 7032 else 7033 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 7034 7035 if ((spkt != NULL) && spkt->satapkt_time && 7036 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 7037 /* 7038 * We are overloading satapkt_hba_driver_private 7039 * with watched_cycle count. 7040 * 7041 * If a packet has survived for more than it's 7042 * max life cycles, it is a candidate for time 7043 * out. 7044 */ 7045 watched_cycles = (int)(intptr_t) 7046 spkt->satapkt_hba_driver_private; 7047 watched_cycles++; 7048 max_life_cycles = (spkt->satapkt_time + 7049 ahci_watchdog_timeout - 1) / 7050 ahci_watchdog_timeout; 7051 7052 spkt->satapkt_hba_driver_private = 7053 (void *)(intptr_t)watched_cycles; 7054 7055 if (watched_cycles <= max_life_cycles) 7056 goto next; 7057 7058 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 7059 "the current slot is %d", current_slot); 7060 /* 7061 * We need to check whether the HBA has 7062 * begun to execute the command, if not, 7063 * then re-set the timer of the command. 7064 */ 7065 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 7066 (tmp_slot != current_slot) || 7067 NCQ_CMD_IN_PROGRESS(ahci_portp) && 7068 ((0x1 << tmp_slot) & current_tags)) { 7069 spkt->satapkt_hba_driver_private = 7070 (void *)(intptr_t)0; 7071 } else { 7072 timeout_tags |= (0x1 << tmp_slot); 7073 cmn_err(CE_WARN, "!ahci%d: watchdog " 7074 "port %d satapkt 0x%p timed out\n", 7075 instance, port, (void *)spkt); 7076 } 7077 } 7078 next: 7079 CLEAR_BIT(pending_tags, tmp_slot); 7080 } 7081 7082 if (timeout_tags) { 7083 mutex_exit(&ahci_portp->ahciport_mutex); 7084 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7085 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 7086 port, timeout_tags); 7087 mutex_enter(&ahci_ctlp->ahcictl_mutex); 7088 mutex_enter(&ahci_portp->ahciport_mutex); 7089 } 7090 7091 mutex_exit(&ahci_portp->ahciport_mutex); 7092 } 7093 7094 /* Re-install the watchdog timeout handler */ 7095 if (ahci_ctlp->ahcictl_timeout_id != 0) { 7096 ahci_ctlp->ahcictl_timeout_id = 7097 timeout((void (*)(void *))ahci_watchdog_handler, 7098 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 7099 } 7100 7101 mutex_exit(&ahci_ctlp->ahcictl_mutex); 7102 } 7103 7104 /* 7105 * Fill the error context into sata_cmd for non-queued command error. 7106 */ 7107 static void 7108 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7109 { 7110 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 7111 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7112 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7113 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7114 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7115 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7116 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7117 7118 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 7119 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7120 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7121 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7122 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7123 } 7124 } 7125 7126 /* 7127 * Fill the ncq error page into sata_cmd for queued command error. 7128 */ 7129 static void 7130 ahci_copy_ncq_err_page(sata_cmd_t *scmd, 7131 struct sata_ncq_error_recovery_page *ncq_err_page) 7132 { 7133 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 7134 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 7135 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 7136 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 7137 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 7138 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 7139 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 7140 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 7141 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 7142 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 7143 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 7144 } 7145 7146 /* 7147 * Put the respective register value to sata_cmd_t for satacmd_flags. 7148 */ 7149 static void 7150 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7151 { 7152 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 7153 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7154 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 7155 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7156 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 7157 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7158 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 7159 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7160 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 7161 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7162 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 7163 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7164 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 7165 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7166 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 7167 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7168 if (scmd->satacmd_flags.sata_copy_out_device_reg) 7169 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7170 if (scmd->satacmd_flags.sata_copy_out_error_reg) 7171 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7172 } 7173 7174 static void 7175 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7176 uint32_t intr_status) 7177 { 7178 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7179 7180 if (intr_status & AHCI_INTR_STATUS_IFS) 7181 cmn_err(CE_WARN, "ahci%d: ahci port %d has interface fatal " 7182 "error", instance, port); 7183 7184 if (intr_status & AHCI_INTR_STATUS_HBDS) 7185 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus data error", 7186 instance, port); 7187 7188 if (intr_status & AHCI_INTR_STATUS_HBFS) 7189 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus fatal error", 7190 instance, port); 7191 7192 if (intr_status & AHCI_INTR_STATUS_TFES) 7193 cmn_err(CE_WARN, "ahci%d: ahci port %d has task file error", 7194 instance, port); 7195 7196 cmn_err(CE_WARN, "ahci%d: ahci port %d is trying to do error " 7197 "recovery", instance, port); 7198 } 7199 7200 /* 7201 * Dump the serror message to the log. 7202 */ 7203 static void 7204 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7205 uint32_t port_serror, int debug_only) 7206 { 7207 static char err_buf[512]; 7208 static char err_msg_header[16]; 7209 char *err_msg = err_buf; 7210 7211 *err_buf = '\0'; 7212 *err_msg_header = '\0'; 7213 7214 if (port_serror & SERROR_DATA_ERR_FIXED) { 7215 err_msg = strcat(err_msg, 7216 "\tRecovered Data Integrity Error (I)\n"); 7217 } 7218 7219 if (port_serror & SERROR_COMM_ERR_FIXED) { 7220 err_msg = strcat(err_msg, 7221 "\tRecovered Communication Error (M)\n"); 7222 } 7223 7224 if (port_serror & SERROR_DATA_ERR) { 7225 err_msg = strcat(err_msg, 7226 "\tTransient Data Integrity Error (T)\n"); 7227 } 7228 7229 if (port_serror & SERROR_PERSISTENT_ERR) { 7230 err_msg = strcat(err_msg, 7231 "\tPersistent Communication or Data Integrity Error (C)\n"); 7232 } 7233 7234 if (port_serror & SERROR_PROTOCOL_ERR) { 7235 err_msg = strcat(err_msg, "\tProtocol Error (P)\n"); 7236 } 7237 7238 if (port_serror & SERROR_INT_ERR) { 7239 err_msg = strcat(err_msg, "\tInternal Error (E)\n"); 7240 } 7241 7242 if (port_serror & SERROR_PHY_RDY_CHG) { 7243 err_msg = strcat(err_msg, "\tPhyRdy Change (N)\n"); 7244 } 7245 7246 if (port_serror & SERROR_PHY_INT_ERR) { 7247 err_msg = strcat(err_msg, "\tPhy Internal Error (I)\n"); 7248 } 7249 7250 if (port_serror & SERROR_COMM_WAKE) { 7251 err_msg = strcat(err_msg, "\tComm Wake (W)\n"); 7252 } 7253 7254 if (port_serror & SERROR_10B_TO_8B_ERR) { 7255 err_msg = strcat(err_msg, "\t10B to 8B Decode Error (B)\n"); 7256 } 7257 7258 if (port_serror & SERROR_DISPARITY_ERR) { 7259 err_msg = strcat(err_msg, "\tDisparity Error (D)\n"); 7260 } 7261 7262 if (port_serror & SERROR_CRC_ERR) { 7263 err_msg = strcat(err_msg, "\tCRC Error (C)\n"); 7264 } 7265 7266 if (port_serror & SERROR_HANDSHAKE_ERR) { 7267 err_msg = strcat(err_msg, "\tHandshake Error (H)\n"); 7268 } 7269 7270 if (port_serror & SERROR_LINK_SEQ_ERR) { 7271 err_msg = strcat(err_msg, "\tLink Sequence Error (S)\n"); 7272 } 7273 7274 if (port_serror & SERROR_TRANS_ERR) { 7275 err_msg = strcat(err_msg, 7276 "\tTransport state transition error (T)\n"); 7277 } 7278 7279 if (port_serror & SERROR_FIS_TYPE) { 7280 err_msg = strcat(err_msg, "\tUnknown FIS Type (F)\n"); 7281 } 7282 7283 if (port_serror & SERROR_EXCHANGED_ERR) { 7284 err_msg = strcat(err_msg, "\tExchanged (X)\n"); 7285 } 7286 7287 if (err_msg == NULL) 7288 return; 7289 7290 if (debug_only) { 7291 (void) sprintf(err_msg_header, "port %d", port); 7292 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg_header); 7293 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg); 7294 } else if (ahci_ctlp) { 7295 cmn_err(CE_WARN, "ahci%d: %s %s", 7296 ddi_get_instance(ahci_ctlp->ahcictl_dip), 7297 err_msg_header, err_msg); 7298 } else { 7299 cmn_err(CE_WARN, "ahci: %s %s", err_msg_header, err_msg); 7300 } 7301 } 7302 7303 /* 7304 * This routine is to calculate the total number of ports implemented 7305 * by the HBA. 7306 */ 7307 static int 7308 ahci_get_num_implemented_ports(uint32_t ports_implemented) 7309 { 7310 uint8_t i; 7311 int num = 0; 7312 7313 for (i = 0; i < AHCI_MAX_PORTS; i++) { 7314 if (((uint32_t)0x1 << i) & ports_implemented) 7315 num++; 7316 } 7317 7318 return (num); 7319 } 7320 7321 #if AHCI_DEBUG 7322 static void 7323 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7324 { 7325 static char name[16]; 7326 va_list ap; 7327 7328 mutex_enter(&ahci_log_mutex); 7329 7330 va_start(ap, fmt); 7331 if (ahci_ctlp) { 7332 (void) sprintf(name, "ahci%d: ", 7333 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7334 } else { 7335 (void) sprintf(name, "ahci: "); 7336 } 7337 7338 (void) vsprintf(ahci_log_buf, fmt, ap); 7339 va_end(ap); 7340 7341 cmn_err(level, "%s%s", name, ahci_log_buf); 7342 7343 mutex_exit(&ahci_log_mutex); 7344 } 7345 #endif 7346 7347 /* 7348 * quiesce(9E) entry point. 7349 * 7350 * This function is called when the system is single-threaded at high 7351 * PIL with preemption disabled. Therefore, this function must not be 7352 * blocked. 7353 * 7354 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 7355 * DDI_FAILURE indicates an error condition and should almost never happen. 7356 */ 7357 static int 7358 ahci_quiesce(dev_info_t *dip) 7359 { 7360 ahci_ctl_t *ahci_ctlp; 7361 ahci_port_t *ahci_portp; 7362 int instance, port; 7363 7364 instance = ddi_get_instance(dip); 7365 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 7366 7367 if (ahci_ctlp == NULL) 7368 return (DDI_FAILURE); 7369 7370 #if AHCI_DEBUG 7371 ahci_debug_flags = 0; 7372 #endif 7373 7374 /* disable all the interrupts. */ 7375 ahci_disable_all_intrs(ahci_ctlp); 7376 7377 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 7378 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 7379 continue; 7380 } 7381 7382 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 7383 7384 /* 7385 * Stop the port by clearing PxCMD.ST 7386 * 7387 * Here we must disable the port interrupt because 7388 * ahci_disable_all_intrs only clear GHC.IE, and IS 7389 * register will be still set if PxIE is enabled. 7390 * When ahci shares one IRQ with other drivers, the 7391 * intr handler may claim the intr mistakenly. 7392 */ 7393 ahci_disable_port_intrs(ahci_ctlp, port); 7394 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 7395 ahci_portp, port); 7396 } 7397 7398 return (DDI_SUCCESS); 7399 } 7400