1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 31 */ 32 33 #include <sys/scsi/scsi.h> 34 #include <sys/pci.h> 35 #include <sys/sata/sata_hba.h> 36 #include <sys/sata/adapters/ahci/ahcireg.h> 37 #include <sys/sata/adapters/ahci/ahcivar.h> 38 39 /* 40 * Function prototypes for driver entry points 41 */ 42 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 43 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 44 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 45 46 /* 47 * Function prototypes for SATA Framework interfaces 48 */ 49 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 50 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 51 52 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 53 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 54 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 55 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 56 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 57 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 58 #if defined(__lock_lint) 59 static int ahci_selftest(dev_info_t *, sata_device_t *); 60 #endif 61 62 /* 63 * Local function prototypes 64 */ 65 static int ahci_alloc_ports_state(ahci_ctl_t *); 66 static void ahci_dealloc_ports_state(ahci_ctl_t *); 67 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 68 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 69 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 70 static void ahci_dealloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *); 71 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 72 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 73 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 74 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 75 76 static int ahci_initialize_controller(ahci_ctl_t *); 77 static void ahci_uninitialize_controller(ahci_ctl_t *); 78 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 79 80 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 81 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 82 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 83 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 84 uint8_t, sata_pkt_t *); 85 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 86 uint8_t, sata_pkt_t *); 87 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 88 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 89 static void ahci_copy_ncq_err_page(sata_cmd_t *, 90 struct sata_ncq_error_recovery_page *); 91 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 92 93 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 94 static int ahci_hba_reset(ahci_ctl_t *); 95 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 96 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 97 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 98 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 99 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 100 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 101 uint8_t); 102 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 103 uint8_t, int, int *); 104 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint8_t, 105 uint32_t, uint32_t, uint32_t, uint32_t, uint32_t); 106 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 107 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 108 uint8_t, sata_pkt_t *); 109 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 110 uint8_t, uint32_t); 111 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 112 uint8_t, uint32_t); 113 static void ahci_events_handler(void *); 114 static void ahci_watchdog_handler(ahci_ctl_t *); 115 116 static uint_t ahci_intr(caddr_t, caddr_t); 117 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 118 static int ahci_add_legacy_intrs(ahci_ctl_t *); 119 static int ahci_add_msi_intrs(ahci_ctl_t *); 120 static void ahci_rem_intrs(ahci_ctl_t *); 121 static void ahci_enable_all_intrs(ahci_ctl_t *); 122 static void ahci_disable_all_intrs(ahci_ctl_t *); 123 static void ahci_enable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 124 static void ahci_disable_port_intrs(ahci_ctl_t *, ahci_port_t *, uint8_t); 125 126 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t, 127 uint32_t); 128 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 129 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 130 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 131 ahci_port_t *, uint8_t); 132 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 133 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 134 uint8_t, uint32_t); 135 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 136 uint8_t, uint32_t); 137 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 138 139 static int ahci_get_num_implemented_ports(uint32_t); 140 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 141 uint32_t); 142 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t); 143 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 144 145 146 /* 147 * DMA attributes for the data buffer 148 * 149 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 150 * does not support 64-bit addressing 151 */ 152 static ddi_dma_attr_t buffer_dma_attr = { 153 DMA_ATTR_V0, /* dma_attr_version */ 154 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 155 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 156 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 157 0x2ull, /* dma_attr_align: word aligned */ 158 1, /* dma_attr_burstsizes */ 159 1, /* dma_attr_minxfer */ 160 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 161 0xffffffffull, /* dma_attr_seg */ 162 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 163 512, /* dma_attr_granular */ 164 0, /* dma_attr_flags */ 165 }; 166 167 /* 168 * DMA attributes for the rcvd FIS 169 * 170 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 171 * does not support 64-bit addressing 172 */ 173 static ddi_dma_attr_t rcvd_fis_dma_attr = { 174 DMA_ATTR_V0, /* dma_attr_version */ 175 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 176 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 177 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 178 0x100ull, /* dma_attr_align: 256-byte aligned */ 179 1, /* dma_attr_burstsizes */ 180 1, /* dma_attr_minxfer */ 181 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 182 0xffffffffull, /* dma_attr_seg */ 183 1, /* dma_attr_sgllen */ 184 1, /* dma_attr_granular */ 185 0, /* dma_attr_flags */ 186 }; 187 188 /* 189 * DMA attributes for the command list 190 * 191 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 192 * does not support 64-bit addressing 193 */ 194 static ddi_dma_attr_t cmd_list_dma_attr = { 195 DMA_ATTR_V0, /* dma_attr_version */ 196 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 197 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 198 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 199 0x400ull, /* dma_attr_align: 1K-byte aligned */ 200 1, /* dma_attr_burstsizes */ 201 1, /* dma_attr_minxfer */ 202 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 203 0xffffffffull, /* dma_attr_seg */ 204 1, /* dma_attr_sgllen */ 205 1, /* dma_attr_granular */ 206 0, /* dma_attr_flags */ 207 }; 208 209 /* 210 * DMA attributes for cmd tables 211 * 212 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 213 * does not support 64-bit addressing 214 */ 215 static ddi_dma_attr_t cmd_table_dma_attr = { 216 DMA_ATTR_V0, /* dma_attr_version */ 217 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 218 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 219 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 220 0x80ull, /* dma_attr_align: 128-byte aligned */ 221 1, /* dma_attr_burstsizes */ 222 1, /* dma_attr_minxfer */ 223 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 224 0xffffffffull, /* dma_attr_seg */ 225 1, /* dma_attr_sgllen */ 226 1, /* dma_attr_granular */ 227 0, /* dma_attr_flags */ 228 }; 229 230 231 /* Device access attributes */ 232 static ddi_device_acc_attr_t accattr = { 233 DDI_DEVICE_ATTR_V0, 234 DDI_STRUCTURE_LE_ACC, 235 DDI_STRICTORDER_ACC 236 }; 237 238 239 static struct dev_ops ahcictl_dev_ops = { 240 DEVO_REV, /* devo_rev */ 241 0, /* refcnt */ 242 ahci_getinfo, /* info */ 243 nulldev, /* identify */ 244 nulldev, /* probe */ 245 ahci_attach, /* attach */ 246 ahci_detach, /* detach */ 247 nodev, /* no reset */ 248 (struct cb_ops *)0, /* driver operations */ 249 NULL, /* bus operations */ 250 NULL /* power */ 251 }; 252 253 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 254 SATA_TRAN_HOTPLUG_OPS_REV_1, 255 ahci_tran_hotplug_port_activate, 256 ahci_tran_hotplug_port_deactivate 257 }; 258 259 extern struct mod_ops mod_driverops; 260 261 static struct modldrv modldrv = { 262 &mod_driverops, /* driverops */ 263 "ahci driver %I%", 264 &ahcictl_dev_ops, /* driver ops */ 265 }; 266 267 static struct modlinkage modlinkage = { 268 MODREV_1, 269 &modldrv, 270 NULL 271 }; 272 273 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 274 static int ahci_watchdog_tick; 275 276 /* The following is needed for ahci_log() */ 277 static kmutex_t ahci_log_mutex; 278 static char ahci_log_buf[512]; 279 280 static size_t ahci_cmd_table_size; 281 282 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 283 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 284 285 /* 286 * AHCI MSI tunable: 287 * 288 * MSI will be enabled in phase 2. 289 */ 290 boolean_t ahci_msi_enabled = B_FALSE; 291 292 #if AHCI_DEBUG 293 uint32_t ahci_debug_flags = 0; 294 #endif 295 296 /* Opaque state pointer initialized by ddi_soft_state_init() */ 297 static void *ahci_statep = NULL; 298 299 /* 300 * ahci module initialization. 301 */ 302 int 303 _init(void) 304 { 305 int ret; 306 307 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 308 if (ret != 0) { 309 goto err_out; 310 } 311 312 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 313 314 if ((ret = sata_hba_init(&modlinkage)) != 0) { 315 mutex_destroy(&ahci_log_mutex); 316 ddi_soft_state_fini(&ahci_statep); 317 goto err_out; 318 } 319 320 ret = mod_install(&modlinkage); 321 if (ret != 0) { 322 sata_hba_fini(&modlinkage); 323 mutex_destroy(&ahci_log_mutex); 324 ddi_soft_state_fini(&ahci_statep); 325 goto err_out; 326 } 327 328 /* watchdog tick */ 329 ahci_watchdog_tick = drv_usectohz( 330 (clock_t)ahci_watchdog_timeout * 1000000); 331 return (ret); 332 333 err_out: 334 cmn_err(CE_WARN, "!Module init failed"); 335 return (ret); 336 } 337 338 /* 339 * ahci module uninitialize. 340 */ 341 int 342 _fini(void) 343 { 344 int ret; 345 346 ret = mod_remove(&modlinkage); 347 if (ret != 0) { 348 return (ret); 349 } 350 351 /* Remove the resources allocated in _init(). */ 352 sata_hba_fini(&modlinkage); 353 mutex_destroy(&ahci_log_mutex); 354 ddi_soft_state_fini(&ahci_statep); 355 356 return (ret); 357 } 358 359 /* 360 * _info entry point 361 */ 362 int 363 _info(struct modinfo *modinfop) 364 { 365 return (mod_info(&modlinkage, modinfop)); 366 } 367 368 /* 369 * The attach entry point for dev_ops. 370 */ 371 static int 372 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 373 { 374 ahci_ctl_t *ahci_ctlp; 375 int instance = ddi_get_instance(dip); 376 int status; 377 int attach_state; 378 uint32_t cap_status, ahci_version; 379 int intr_types; 380 ushort_t venid; 381 uint8_t revision; 382 int i; 383 #if AHCI_DEBUG 384 int speed; 385 #endif 386 387 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 388 389 switch (cmd) { 390 case DDI_ATTACH: 391 break; 392 393 case DDI_RESUME: 394 /* It will be implemented in Phase 2 */ 395 return (DDI_FAILURE); 396 397 default: 398 return (DDI_FAILURE); 399 } 400 401 attach_state = AHCI_ATTACH_STATE_NONE; 402 403 /* Allocate soft state */ 404 status = ddi_soft_state_zalloc(ahci_statep, instance); 405 if (status != DDI_SUCCESS) { 406 cmn_err(CE_WARN, "!Cannot allocate soft state"); 407 goto err_out; 408 } 409 410 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 411 ahci_ctlp->ahcictl_dip = dip; 412 413 /* Initialize the cport/port mapping */ 414 for (i = 0; i < AHCI_MAX_PORTS; i++) { 415 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 416 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 417 } 418 419 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 420 421 /* 422 * Now map the AHCI base address; which includes global 423 * registers and port control registers 424 */ 425 status = ddi_regs_map_setup(dip, 426 AHCI_BASE_REG, 427 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 428 0, 429 0, 430 &accattr, 431 &ahci_ctlp->ahcictl_ahci_acc_handle); 432 if (status != DDI_SUCCESS) { 433 cmn_err(CE_WARN, "!Cannot map register space"); 434 goto err_out; 435 } 436 437 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 438 439 /* Get the AHCI version information */ 440 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 441 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 442 443 cmn_err(CE_NOTE, "!hba AHCI version = %x.%x", 444 (ahci_version & 0xffff0000) >> 16, 445 ((ahci_version & 0x0000ff00) >> 4 | 446 (ahci_version & 0x000000ff))); 447 448 /* We don't support controllers whose versions are lower than 1.0 */ 449 if (!(ahci_version & 0xffff0000)) { 450 cmn_err(CE_WARN, "Don't support AHCI HBA with lower than " 451 "version 1.0"); 452 goto err_out; 453 } 454 455 /* Get the HBA capabilities information */ 456 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 457 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 458 459 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 460 cap_status); 461 462 #if AHCI_DEBUG 463 /* Get the interface speed supported by the HBA */ 464 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 465 if (speed == 0x01) { 466 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 467 "hba interface speed support: Gen 1 (1.5Gbps)"); 468 } else if (speed == 0x10) { 469 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 470 "hba interface speed support: Gen 2 (3 Gbps)"); 471 } else if (speed == 0x11) { 472 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 473 "hba interface speed support: Gen 3 (6 Gbps)"); 474 } 475 #endif 476 477 /* Get the number of command slots supported by the HBA */ 478 ahci_ctlp->ahcictl_num_cmd_slots = 479 ((cap_status & AHCI_HBA_CAP_NCS) >> 480 AHCI_HBA_CAP_NCS_SHIFT) + 1; 481 482 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 483 ahci_ctlp->ahcictl_num_cmd_slots); 484 485 /* Get the bit map which indicates ports implemented by the HBA */ 486 ahci_ctlp->ahcictl_ports_implemented = 487 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 488 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 489 490 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 491 ahci_ctlp->ahcictl_ports_implemented); 492 493 /* 494 * According to the AHCI spec, CAP.NP should indicate the maximum 495 * number of ports supported by the HBA silicon, but we found 496 * this value of ICH8 chipset only indicates the number of ports 497 * implemented (exposed) by it. Therefore, the driver should calculate 498 * the potential maximum value by checking PI register, and use 499 * the maximum of this value and CAP.NP. 500 */ 501 ahci_ctlp->ahcictl_num_ports = max( 502 (cap_status & AHCI_HBA_CAP_NP) + 1, 503 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 504 505 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 506 ahci_ctlp->ahcictl_num_ports); 507 508 /* Get the number of implemented ports by the HBA */ 509 ahci_ctlp->ahcictl_num_implemented_ports = 510 ahci_get_num_implemented_ports( 511 ahci_ctlp->ahcictl_ports_implemented); 512 513 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 514 "hba number of implemented ports: %d", 515 ahci_ctlp->ahcictl_num_implemented_ports); 516 517 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 518 519 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 520 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 521 "hba does not support 64-bit addressing"); 522 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 523 0xffffffffull; 524 } 525 526 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 527 != DDI_SUCCESS) { 528 cmn_err(CE_WARN, "!Cannot set up pci configure space"); 529 goto err_out; 530 } 531 532 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 533 534 /* 535 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 536 * controllers with 0x00 revision id work on 4-byte aligned buffer, 537 * which is a bug and was fixed after 0x00 revision id controllers. 538 * 539 * Moreover, VT8251 cannot use multiple command slots in the command 540 * list for non-queued commands because the previous register content 541 * of PxCI can be re-written in the register write, so a flag will be 542 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 543 */ 544 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 545 PCI_CONF_VENID); 546 547 if (venid == VIA_VENID) { 548 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 549 PCI_CONF_REVID); 550 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 551 "revision id = 0x%x", revision); 552 if (revision == 0x00) { 553 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 554 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 555 "change ddi_attr_align to 0x4"); 556 } 557 558 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 559 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 560 "VT8251 cannot use multiple command lists for " 561 "non-queued commands"); 562 } 563 564 /* 565 * Disable the whole controller interrupts before adding 566 * interrupt handlers(s). 567 */ 568 ahci_disable_all_intrs(ahci_ctlp); 569 570 /* Get supported interrupt types */ 571 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 572 cmn_err(CE_WARN, "!ddi_intr_get_supported_types failed"); 573 goto err_out; 574 } 575 576 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 577 "ddi_intr_get_supported_types() returned: 0x%x", 578 intr_types); 579 580 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 581 /* 582 * Try MSI first, but fall back to FIXED if failed 583 */ 584 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 585 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 586 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 587 "Using MSI interrupt type"); 588 goto intr_done; 589 } 590 591 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 592 "MSI registration failed, " 593 "trying FIXED interrupts"); 594 } 595 596 if (intr_types & DDI_INTR_TYPE_FIXED) { 597 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 598 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 599 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, NULL, 600 "Using FIXED interrupt type"); 601 goto intr_done; 602 } 603 604 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 605 "FIXED interrupt registration failed"); 606 } 607 608 cmn_err(CE_WARN, "!Interrupt registration failed"); 609 610 goto err_out; 611 612 intr_done: 613 614 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 615 616 /* Initialize the controller mutex */ 617 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 618 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 619 620 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 621 622 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 623 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 624 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 625 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 626 } 627 628 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 629 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 630 sizeof (ahci_prdt_item_t)); 631 632 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 633 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 634 " ahci_cmd_table_size is 0x%x", 635 ahci_dma_prdt_number, ahci_cmd_table_size); 636 637 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 638 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 639 ahci_dma_prdt_number; 640 641 /* Allocate the ports structure */ 642 status = ahci_alloc_ports_state(ahci_ctlp); 643 if (status != AHCI_SUCCESS) { 644 cmn_err(CE_WARN, "!Cannot allocate ports structure"); 645 goto err_out; 646 } 647 648 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 649 650 /* 651 * A taskq is created for dealing with events 652 */ 653 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 654 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 655 cmn_err(CE_WARN, "!ddi_taskq_create failed for event handle"); 656 goto err_out; 657 } 658 659 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 660 661 /* 662 * Initialize the controller and ports. 663 */ 664 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 665 status = ahci_initialize_controller(ahci_ctlp); 666 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 667 if (status != AHCI_SUCCESS) { 668 cmn_err(CE_WARN, "!HBA initialization failed"); 669 goto err_out; 670 } 671 672 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 673 674 /* Start one thread to check packet timeouts */ 675 ahci_ctlp->ahcictl_timeout_id = timeout( 676 (void (*)(void *))ahci_watchdog_handler, 677 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 678 679 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 680 681 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 682 cmn_err(CE_WARN, "!sata hba tran registration failed"); 683 goto err_out; 684 } 685 686 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 687 688 return (DDI_SUCCESS); 689 690 err_out: 691 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 692 mutex_enter(&ahci_ctlp->ahcictl_mutex); 693 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 694 ahci_ctlp->ahcictl_timeout_id = 0; 695 mutex_exit(&ahci_ctlp->ahcictl_mutex); 696 } 697 698 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 699 mutex_enter(&ahci_ctlp->ahcictl_mutex); 700 ahci_uninitialize_controller(ahci_ctlp); 701 mutex_exit(&ahci_ctlp->ahcictl_mutex); 702 } 703 704 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 705 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 706 } 707 708 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 709 ahci_dealloc_ports_state(ahci_ctlp); 710 } 711 712 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 713 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 714 } 715 716 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 717 ahci_rem_intrs(ahci_ctlp); 718 } 719 720 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 721 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 722 } 723 724 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 725 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 726 } 727 728 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 729 ddi_soft_state_free(ahci_statep, instance); 730 } 731 732 return (DDI_FAILURE); 733 } 734 735 /* 736 * The detach entry point for dev_ops. 737 */ 738 static int 739 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 740 { 741 ahci_ctl_t *ahci_ctlp; 742 int instance; 743 int ret; 744 745 instance = ddi_get_instance(dip); 746 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 747 748 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 749 750 switch (cmd) { 751 case DDI_DETACH: 752 /* disable the interrupts for an uninterrupted detach */ 753 mutex_enter(&ahci_ctlp->ahcictl_mutex); 754 ahci_disable_all_intrs(ahci_ctlp); 755 mutex_exit(&ahci_ctlp->ahcictl_mutex); 756 757 /* unregister from the sata framework. */ 758 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 759 if (ret != AHCI_SUCCESS) { 760 mutex_enter(&ahci_ctlp->ahcictl_mutex); 761 ahci_enable_all_intrs(ahci_ctlp); 762 mutex_exit(&ahci_ctlp->ahcictl_mutex); 763 return (DDI_FAILURE); 764 } 765 766 mutex_enter(&ahci_ctlp->ahcictl_mutex); 767 768 /* stop the watchdog handler */ 769 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 770 ahci_ctlp->ahcictl_timeout_id = 0; 771 772 mutex_exit(&ahci_ctlp->ahcictl_mutex); 773 774 /* uninitialize the controller */ 775 ahci_ctlp->ahcictl_flags |= AHCI_DETACH; 776 ahci_uninitialize_controller(ahci_ctlp); 777 ahci_ctlp->ahcictl_flags &= ~AHCI_DETACH; 778 779 /* remove the interrupts */ 780 ahci_rem_intrs(ahci_ctlp); 781 782 /* destroy the taskq */ 783 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 784 785 /* deallocate the ports structures */ 786 ahci_dealloc_ports_state(ahci_ctlp); 787 788 /* destroy mutex */ 789 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 790 791 /* teardown the pci config */ 792 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 793 794 /* remove the reg maps. */ 795 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 796 797 /* free the soft state. */ 798 ddi_soft_state_free(ahci_statep, instance); 799 800 return (DDI_SUCCESS); 801 802 case DDI_SUSPEND: 803 /* It will be implemented in Phase 2 */ 804 return (DDI_FAILURE); 805 806 default: 807 return (DDI_FAILURE); 808 } 809 } 810 811 /* 812 * The info entry point for dev_ops. 813 * 814 */ 815 static int 816 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 817 void *arg, void **result) 818 { 819 #ifndef __lock_lint 820 _NOTE(ARGUNUSED(dip)) 821 #endif /* __lock_lint */ 822 823 ahci_ctl_t *ahci_ctlp; 824 int instance; 825 dev_t dev; 826 827 dev = (dev_t)arg; 828 instance = getminor(dev); 829 830 switch (infocmd) { 831 case DDI_INFO_DEVT2DEVINFO: 832 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 833 if (ahci_ctlp != NULL) { 834 *result = ahci_ctlp->ahcictl_dip; 835 return (DDI_SUCCESS); 836 } else { 837 *result = NULL; 838 return (DDI_FAILURE); 839 } 840 case DDI_INFO_DEVT2INSTANCE: 841 *(int *)result = instance; 842 break; 843 default: 844 break; 845 } 846 847 return (DDI_SUCCESS); 848 } 849 850 /* 851 * Registers the ahci with sata framework. 852 */ 853 static int 854 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 855 { 856 struct sata_hba_tran *sata_hba_tran; 857 858 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 859 "ahci_register_sata_hba_tran enter"); 860 861 mutex_enter(&ahci_ctlp->ahcictl_mutex); 862 863 /* Allocate memory for the sata_hba_tran */ 864 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 865 866 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 867 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 868 sata_hba_tran->sata_tran_hba_dma_attr = 869 &ahci_ctlp->ahcictl_buffer_dma_attr; 870 871 /* Report the number of implemented ports */ 872 sata_hba_tran->sata_tran_hba_num_cports = 873 ahci_ctlp->ahcictl_num_implemented_ports; 874 875 /* Support ATAPI device */ 876 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 877 878 /* Get the data transfer capability for PIO command by the HBA */ 879 if (cap_status & AHCI_HBA_CAP_PMD) { 880 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 881 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 882 "DRQ block data transfer for PIO command protocol"); 883 } else { 884 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA only supports single " 885 "DRQ block data transfer for PIO command protocol"); 886 } 887 888 /* 889 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 890 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 891 * QUEUED (EXT), and SERVICE commands). Queued operations are 892 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 893 * QUEUED commands when the HBA and device support native command 894 * queuing(NCQ). 895 * 896 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 897 * CAP register of the HBA indicates NCQ is supported. 898 * 899 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 900 * set because the previous register content of PxCI can be re-written 901 * in the register write. 902 */ 903 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 904 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 905 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 906 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 907 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 908 "Command Queuing"); 909 } 910 911 /* Report the number of command slots */ 912 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 913 914 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 915 sata_hba_tran->sata_tran_start = ahci_tran_start; 916 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 917 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 918 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 919 #ifdef __lock_lint 920 sata_hba_tran->sata_tran_selftest = ahci_selftest; 921 #endif 922 /* 923 * When SATA framework adds support for pwrmgt the 924 * pwrmgt_ops needs to be updated 925 */ 926 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 927 sata_hba_tran->sata_tran_ioctl = NULL; 928 929 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 930 931 mutex_exit(&ahci_ctlp->ahcictl_mutex); 932 933 /* Attach it to SATA framework */ 934 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 935 != DDI_SUCCESS) { 936 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 937 mutex_enter(&ahci_ctlp->ahcictl_mutex); 938 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 939 mutex_exit(&ahci_ctlp->ahcictl_mutex); 940 return (AHCI_FAILURE); 941 } 942 943 return (AHCI_SUCCESS); 944 } 945 946 /* 947 * Unregisters the ahci with sata framework. 948 */ 949 static int 950 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 951 { 952 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 953 "ahci_unregister_sata_hba_tran enter"); 954 955 /* Detach from the SATA framework. */ 956 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 957 DDI_SUCCESS) { 958 return (AHCI_FAILURE); 959 } 960 961 /* Deallocate sata_hba_tran. */ 962 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 963 sizeof (sata_hba_tran_t)); 964 965 mutex_enter(&ahci_ctlp->ahcictl_mutex); 966 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 967 mutex_exit(&ahci_ctlp->ahcictl_mutex); 968 969 return (AHCI_SUCCESS); 970 } 971 972 /* 973 * ahci_tran_probe_port is called by SATA framework. It returns port state, 974 * port status registers and an attached device type via sata_device 975 * structure. 976 * 977 * We return the cached information from a previous hardware probe. The 978 * actual hardware probing itself was done either from within 979 * ahci_initialize_controller() during the driver attach or from a phy 980 * ready change interrupt handler. 981 */ 982 static int 983 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 984 { 985 ahci_ctl_t *ahci_ctlp; 986 ahci_port_t *ahci_portp; 987 uint8_t cport = sd->satadev_addr.cport; 988 uint8_t pmport = sd->satadev_addr.pmport; 989 uint8_t qual = sd->satadev_addr.qual; 990 uint8_t device_type; 991 uint32_t port_state; 992 uint8_t port; 993 994 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 995 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 996 997 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 998 "ahci_tran_probe_port enter: cport: %d, " 999 "pmport: %d, qual: %d", cport, pmport, qual); 1000 1001 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1002 1003 mutex_enter(&ahci_portp->ahciport_mutex); 1004 1005 port_state = ahci_portp->ahciport_port_state; 1006 switch (port_state) { 1007 1008 case SATA_PSTATE_FAILED: 1009 sd->satadev_state = SATA_PSTATE_FAILED; 1010 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1011 "ahci_tran_probe_port: port %d PORT FAILED", port); 1012 goto out; 1013 1014 case SATA_PSTATE_SHUTDOWN: 1015 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1016 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1017 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1018 goto out; 1019 1020 case SATA_PSTATE_PWROFF: 1021 sd->satadev_state = SATA_PSTATE_PWROFF; 1022 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1023 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1024 goto out; 1025 1026 case SATA_PSTATE_PWRON: 1027 sd->satadev_state = SATA_PSTATE_PWRON; 1028 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1029 "ahci_tran_probe_port: port %d PORT PWRON", port); 1030 break; 1031 1032 default: 1033 sd->satadev_state = port_state; 1034 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1035 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1036 port, port_state); 1037 break; 1038 } 1039 1040 device_type = ahci_portp->ahciport_device_type; 1041 1042 switch (device_type) { 1043 1044 case SATA_DTYPE_ATADISK: 1045 sd->satadev_type = SATA_DTYPE_ATADISK; 1046 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1047 "ahci_tran_probe_port: port %d DISK found", port); 1048 break; 1049 1050 case SATA_DTYPE_ATAPICD: 1051 sd->satadev_type = SATA_DTYPE_ATAPICD; 1052 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1053 "ahci_tran_probe_port: port %d ATAPI found", port); 1054 break; 1055 1056 case SATA_DTYPE_PMULT: 1057 sd->satadev_type = SATA_DTYPE_PMULT; 1058 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1059 "ahci_tran_probe_port: port %d Port Multiplier found", 1060 port); 1061 break; 1062 1063 case SATA_DTYPE_UNKNOWN: 1064 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1065 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1066 "ahci_tran_probe_port: port %d Unknown device found", port); 1067 break; 1068 1069 default: 1070 /* we don't support any other device types */ 1071 sd->satadev_type = SATA_DTYPE_NONE; 1072 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1073 "ahci_tran_probe_port: port %d No device found", port); 1074 break; 1075 } 1076 1077 out: 1078 ahci_update_sata_registers(ahci_ctlp, port, sd); 1079 mutex_exit(&ahci_portp->ahciport_mutex); 1080 1081 return (SATA_SUCCESS); 1082 } 1083 1084 /* 1085 * There are four operation modes in sata framework: 1086 * SATA_OPMODE_INTERRUPTS 1087 * SATA_OPMODE_POLLING 1088 * SATA_OPMODE_ASYNCH 1089 * SATA_OPMODE_SYNCH 1090 * 1091 * Their combined meanings as following: 1092 * 1093 * SATA_OPMODE_SYNCH 1094 * The command has to be completed before sata_tran_start functions returns. 1095 * Either interrupts or polling could be used - it's up to the driver. 1096 * Mode used currently for internal, sata-module initiated operations. 1097 * 1098 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1099 * It is the same as the one above. 1100 * 1101 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1102 * The command has to be completed before sata_tran_start function returns. 1103 * No interrupt used, polling only. This should be the mode used for scsi 1104 * packets with FLAG_NOINTR. 1105 * 1106 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1107 * The command may be queued (callback function specified). Interrupts could 1108 * be used. It's normal operation mode. 1109 */ 1110 /* 1111 * Called by sata framework to transport a sata packet down stream. 1112 */ 1113 static int 1114 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1115 { 1116 ahci_ctl_t *ahci_ctlp; 1117 ahci_port_t *ahci_portp; 1118 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1119 uint8_t port; 1120 1121 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1122 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1123 1124 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1125 "ahci_tran_start enter: cport %d satapkt 0x%p", 1126 cport, (void *)spkt); 1127 1128 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1129 1130 mutex_enter(&ahci_portp->ahciport_mutex); 1131 1132 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1133 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1134 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1135 /* 1136 * In case the targer driver would send the packet before 1137 * sata framework can have the opportunity to process those 1138 * event reports. 1139 */ 1140 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1141 spkt->satapkt_device.satadev_state = 1142 ahci_portp->ahciport_port_state; 1143 ahci_update_sata_registers(ahci_ctlp, port, 1144 &spkt->satapkt_device); 1145 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1146 "ahci_tran_start returning PORT_ERROR while " 1147 "port in FAILED/SHUTDOWN/PWROFF state: " 1148 "port: %d", port); 1149 mutex_exit(&ahci_portp->ahciport_mutex); 1150 return (SATA_TRAN_PORT_ERROR); 1151 } 1152 1153 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1154 /* 1155 * ahci_intr_phyrdy_change() may have rendered it to 1156 * SATA_DTYPE_NONE. 1157 */ 1158 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1159 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1160 spkt->satapkt_device.satadev_state = 1161 ahci_portp->ahciport_port_state; 1162 ahci_update_sata_registers(ahci_ctlp, port, 1163 &spkt->satapkt_device); 1164 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1165 "ahci_tran_start returning PORT_ERROR while " 1166 "no device attached: port: %d", port); 1167 mutex_exit(&ahci_portp->ahciport_mutex); 1168 return (SATA_TRAN_PORT_ERROR); 1169 } 1170 1171 /* 1172 * SATA HBA driver should remember that a device was reset and it 1173 * is supposed to reject any packets which do not specify either 1174 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1175 * 1176 * This is to prevent a race condition when a device was arbitrarily 1177 * reset by the HBA driver (and lost it's setting) and a target 1178 * driver sending some commands to a device before the sata framework 1179 * has a chance to restore the device setting (such as cache enable/ 1180 * disable or other resettable stuff). 1181 */ 1182 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1183 ahci_portp->ahciport_reset_in_progress = 0; 1184 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1185 "ahci_tran_start clearing the " 1186 "reset_in_progress for port: %d", port); 1187 } 1188 1189 if (ahci_portp->ahciport_reset_in_progress && 1190 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1191 ! ddi_in_panic()) { 1192 spkt->satapkt_reason = SATA_PKT_BUSY; 1193 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1194 "ahci_tran_start returning BUSY while " 1195 "reset in progress: port: %d", port); 1196 mutex_exit(&ahci_portp->ahciport_mutex); 1197 return (SATA_TRAN_BUSY); 1198 } 1199 1200 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1201 spkt->satapkt_reason = SATA_PKT_BUSY; 1202 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1203 "ahci_tran_start returning BUSY while " 1204 "mopping in progress: port: %d", port); 1205 mutex_exit(&ahci_portp->ahciport_mutex); 1206 return (SATA_TRAN_BUSY); 1207 } 1208 1209 if (spkt->satapkt_op_mode & 1210 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1211 /* We need to do the sync start now */ 1212 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1213 spkt) == AHCI_FAILURE) { 1214 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1215 "return QUEUE_FULL: port %d", port); 1216 mutex_exit(&ahci_portp->ahciport_mutex); 1217 return (SATA_TRAN_QUEUE_FULL); 1218 } 1219 } else { 1220 /* Async start, using interrupt */ 1221 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1222 == AHCI_FAILURE) { 1223 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1224 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1225 "returning QUEUE_FULL: port %d", port); 1226 mutex_exit(&ahci_portp->ahciport_mutex); 1227 return (SATA_TRAN_QUEUE_FULL); 1228 } 1229 } 1230 1231 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1232 "sata tran accepted: port %d", port); 1233 1234 mutex_exit(&ahci_portp->ahciport_mutex); 1235 return (SATA_TRAN_ACCEPTED); 1236 } 1237 1238 /* 1239 * SATA_OPMODE_SYNCH flag is set 1240 * 1241 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1242 * without interrupt, otherwise we can still use the interrupt. 1243 * 1244 * WARNING!!! ahciport_mutex should be acquired before the function 1245 * is called. 1246 */ 1247 static int 1248 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1249 uint8_t port, sata_pkt_t *spkt) 1250 { 1251 int pkt_timeout_ticks; 1252 uint32_t timeout_tags; 1253 int rval; 1254 1255 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1256 "port %d spkt 0x%p", port, spkt); 1257 1258 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1259 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1260 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1261 port, spkt)) == AHCI_FAILURE) { 1262 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1263 return (rval); 1264 } 1265 1266 pkt_timeout_ticks = 1267 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1268 1269 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1270 mutex_exit(&ahci_portp->ahciport_mutex); 1271 1272 /* Simulate the interrupt */ 1273 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1274 1275 drv_usecwait(AHCI_1MS_USECS); 1276 1277 mutex_enter(&ahci_portp->ahciport_mutex); 1278 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1279 if (pkt_timeout_ticks < 0) { 1280 cmn_err(CE_NOTE, "!ahci_do_sync_start: " 1281 "port %d satapkt 0x%p timed out\n", 1282 port, (void *)spkt); 1283 timeout_tags = (0x1 << rval); 1284 mutex_exit(&ahci_portp->ahciport_mutex); 1285 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1286 port, timeout_tags); 1287 mutex_enter(&ahci_portp->ahciport_mutex); 1288 } 1289 } 1290 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1291 return (AHCI_SUCCESS); 1292 1293 } else { 1294 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1295 port, spkt)) == AHCI_FAILURE) 1296 return (rval); 1297 1298 #if AHCI_DEBUG 1299 /* 1300 * Note that the driver always uses the slot 0 to deliver 1301 * REQUEST SENSE or READ LOG EXT command 1302 */ 1303 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1304 ASSERT(rval == 0); 1305 #endif 1306 1307 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1308 cv_wait(&ahci_portp->ahciport_cv, 1309 &ahci_portp->ahciport_mutex); 1310 1311 return (AHCI_SUCCESS); 1312 } 1313 } 1314 1315 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1316 if (satapkt) { \ 1317 satapkt->satapkt_reason = reason; \ 1318 /* \ 1319 * We set the satapkt_reason in both sync and \ 1320 * non-sync cases. \ 1321 */ \ 1322 } \ 1323 if (satapkt && \ 1324 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1325 satapkt->satapkt_comp) { \ 1326 mutex_exit(&ahci_portp->ahciport_mutex); \ 1327 (*satapkt->satapkt_comp)(satapkt); \ 1328 mutex_enter(&ahci_portp->ahciport_mutex); \ 1329 } else { \ 1330 if (satapkt && \ 1331 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1332 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1333 cv_signal(&ahci_portp->ahciport_cv); \ 1334 } 1335 1336 /* 1337 * Searches for and claims a free command slot. 1338 * 1339 * Returns: 1340 * 1341 * AHCI_FAILURE if failed 1342 * 1. if no empty slot left 1343 * 2. non-queued command requested while queued command(s) is outstanding 1344 * 3. queued command requested whild non-queued command(s) is outstanding 1345 * 4. HBA doesn't support multiple-use of command list while already a 1346 * non-queued command is oustanding 1347 * 1348 * claimed slot number if succeeded 1349 * 1350 * NOTE: it will always return slot 0 during error recovery process for 1351 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1352 * 1353 * WARNING!!! ahciport_mutex should be acquired before the function 1354 * is called. 1355 */ 1356 /*ARGSUSED*/ 1357 static int 1358 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1359 ahci_port_t *ahci_portp, int command_type) 1360 { 1361 uint32_t free_slots; 1362 int slot; 1363 1364 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1365 "ahciport_pending_tags = 0x%x " 1366 "ahciport_pending_ncq_tags = 0x%x", 1367 ahci_portp->ahciport_pending_tags, 1368 ahci_portp->ahciport_pending_ncq_tags); 1369 1370 /* 1371 * According to the AHCI spec, system software is responsible to 1372 * ensure that queued and non-queued commands are not mixed in 1373 * the command list. 1374 */ 1375 if (command_type == AHCI_NON_NCQ_CMD) { 1376 /* Non-NCQ command request */ 1377 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1378 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1379 "ahci_claim_free_slot: there is still pending " 1380 "queued command(s) in the command list, " 1381 "so no available slot for the non-queued " 1382 "command"); 1383 return (AHCI_FAILURE); 1384 } 1385 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1386 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1387 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1388 "ahci_claim_free_slot: HBA cannot support multiple-" 1389 "use of the command list for non-queued commands"); 1390 return (AHCI_FAILURE); 1391 } 1392 free_slots = (~ahci_portp->ahciport_pending_tags) & 1393 AHCI_SLOT_MASK(ahci_ctlp); 1394 } else if (command_type == AHCI_NCQ_CMD) { 1395 /* NCQ command request */ 1396 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1397 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1398 "ahci_claim_free_slot: there is still pending " 1399 "non-queued command(s) in the command list, " 1400 "so no available slot for the queued command"); 1401 return (AHCI_FAILURE); 1402 } 1403 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1404 AHCI_NCQ_SLOT_MASK(ahci_portp); 1405 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1406 /* Error retrieval command request */ 1407 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1408 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1409 "SENSE or READ LOG EXT command"); 1410 slot = 0; 1411 goto out; 1412 } 1413 1414 slot = ddi_ffs(free_slots) - 1; 1415 if (slot == -1) { 1416 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1417 "ahci_claim_free_slot: no empty slots"); 1418 return (AHCI_FAILURE); 1419 } 1420 1421 /* 1422 * According to the AHCI spec, to allow a simple mechanism for the 1423 * HBA to map command list slots to queue entries, software must 1424 * match the tag number it uses to the slot it is placing the command 1425 * in. For example, if a queued command is placed in slot 5, the tag 1426 * for that command must be 5. 1427 */ 1428 if (command_type == AHCI_NCQ_CMD) { 1429 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1430 } 1431 1432 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1433 1434 out: 1435 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1436 "ahci_claim_free_slot: found slot: 0x%x", slot); 1437 1438 return (slot); 1439 } 1440 1441 /* 1442 * Builds the Command Table for the sata packet and delivers it to controller. 1443 * 1444 * Returns: 1445 * slot number if we can obtain a slot successfully 1446 * otherwise, return AHCI_FAILURE 1447 * 1448 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1449 */ 1450 static int 1451 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1452 uint8_t port, sata_pkt_t *spkt) 1453 { 1454 int cmd_slot; 1455 sata_cmd_t *scmd; 1456 ahci_fis_h2d_register_t *h2d_register_fisp; 1457 ahci_cmd_table_t *cmd_table; 1458 ahci_cmd_header_t *cmd_header; 1459 int ncookies; 1460 int i; 1461 int command_type = AHCI_NON_NCQ_CMD; 1462 int ncq_qdepth; 1463 #if AHCI_DEBUG 1464 uint32_t *ptr; 1465 uint8_t *ptr2; 1466 #endif 1467 1468 spkt->satapkt_reason = SATA_PKT_BUSY; 1469 1470 scmd = &spkt->satapkt_cmd; 1471 1472 /* Check if the command is a NCQ command */ 1473 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1474 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1475 command_type = AHCI_NCQ_CMD; 1476 1477 /* 1478 * When NCQ is support, system software must determine the 1479 * maximum tag allowed by the device and the HBA, and it 1480 * must use a value not beyond of the lower bound of the two. 1481 * 1482 * Sata module is going to calculate the qdepth and send 1483 * down to HBA driver via sata_cmd. 1484 */ 1485 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1486 1487 /* 1488 * At the moment, the driver doesn't support the dynamic 1489 * setting of the maximum ncq depth, and the value can be 1490 * set either during the attach or after hot-plug insertion. 1491 */ 1492 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1493 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1494 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1495 "ahci_deliver_satapkt: port %d the max tags for " 1496 "NCQ command is %d", port, ncq_qdepth); 1497 } else { 1498 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1499 cmn_err(CE_WARN, "ahci_deliver_satapkt: port " 1500 "%d the max tag for NCQ command is " 1501 "requested to change from %d to %d, at the" 1502 " moment the driver doesn't support the " 1503 "dynamic change so it's going to " 1504 "still use the previous tag value", port, 1505 ahci_portp->ahciport_max_ncq_tags, 1506 ncq_qdepth); 1507 } 1508 } 1509 } 1510 1511 /* Check if the command is an error retrieval command */ 1512 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1513 command_type = AHCI_ERR_RETRI_CMD; 1514 1515 /* Check if there is an empty command slot */ 1516 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1517 if (cmd_slot == AHCI_FAILURE) { 1518 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1519 return (AHCI_FAILURE); 1520 } 1521 1522 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1523 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1524 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1525 cmd_slot, port, (void *)spkt); 1526 1527 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1528 bzero((void *)cmd_table, ahci_cmd_table_size); 1529 1530 /* For data transfer operations, it is the H2D Register FIS */ 1531 h2d_register_fisp = 1532 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1533 1534 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1535 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1536 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1537 SET_FIS_PMP(h2d_register_fisp, 1538 spkt->satapkt_device.satadev_addr.pmport); 1539 } 1540 1541 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1542 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1543 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1544 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1545 1546 switch (scmd->satacmd_addr_type) { 1547 1548 case 0: 1549 /* 1550 * satacmd_addr_type will be 0 for the commands below: 1551 * ATAPI command 1552 * SATAC_IDLE_IM 1553 * SATAC_STANDBY_IM 1554 * SATAC_DOWNLOAD_MICROCODE 1555 * SATAC_FLUSH_CACHE 1556 * SATAC_SET_FEATURES 1557 * SATAC_SMART 1558 * SATAC_ID_PACKET_DEVICE 1559 * SATAC_ID_DEVICE 1560 */ 1561 /* fallthrough */ 1562 1563 case ATA_ADDR_LBA: 1564 /* fallthrough */ 1565 1566 case ATA_ADDR_LBA28: 1567 /* LBA[7:0] */ 1568 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1569 1570 /* LBA[15:8] */ 1571 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1572 1573 /* LBA[23:16] */ 1574 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1575 1576 /* LBA [27:24] (also called dev_head) */ 1577 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1578 1579 break; 1580 1581 case ATA_ADDR_LBA48: 1582 /* LBA[7:0] */ 1583 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1584 1585 /* LBA[15:8] */ 1586 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1587 1588 /* LBA[23:16] */ 1589 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1590 1591 /* LBA [31:24] */ 1592 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1593 scmd->satacmd_lba_low_msb); 1594 1595 /* LBA [39:32] */ 1596 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1597 scmd->satacmd_lba_mid_msb); 1598 1599 /* LBA [47:40] */ 1600 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1601 scmd->satacmd_lba_high_msb); 1602 1603 /* Set dev_head */ 1604 SET_FIS_DEV_HEAD(h2d_register_fisp, 1605 scmd->satacmd_device_reg); 1606 1607 /* Set the extended sector count and features */ 1608 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1609 scmd->satacmd_sec_count_msb); 1610 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1611 scmd->satacmd_features_reg_ext); 1612 break; 1613 } 1614 1615 /* 1616 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1617 * filled into features field, and sector count 8:15 is filled into 1618 * features (exp) field. TAG is filled into sector field. 1619 */ 1620 if (command_type == AHCI_NCQ_CMD) { 1621 SET_FIS_FEATURES(h2d_register_fisp, 1622 scmd->satacmd_sec_count_lsb); 1623 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1624 scmd->satacmd_sec_count_msb); 1625 1626 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1627 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1628 } 1629 1630 ncookies = scmd->satacmd_num_dma_cookies; 1631 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1632 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1633 ncookies, ahci_dma_prdt_number); 1634 1635 ASSERT(ncookies <= ahci_dma_prdt_number); 1636 1637 /* *** now fill the scatter gather list ******* */ 1638 for (i = 0; i < ncookies; i++) { 1639 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1640 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1641 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1642 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1643 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1644 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1645 } 1646 1647 /* The ACMD field is filled in for ATAPI command */ 1648 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1649 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1650 SATA_ATAPI_MAX_CDB_LEN); 1651 } 1652 1653 /* Set Command Header in Command List */ 1654 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1655 BZERO_DESCR_INFO(cmd_header); 1656 BZERO_PRD_BYTE_COUNT(cmd_header); 1657 1658 /* Set the number of entries in the PRD table */ 1659 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1660 1661 /* Set the length of the command in the CFIS area */ 1662 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1663 1664 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1665 "sata_data_direction = 0x%x", 1666 scmd->satacmd_flags.sata_data_direction); 1667 1668 /* Set A bit if it is an ATAPI command */ 1669 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1670 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1671 1672 /* Set W bit if data is going to the device */ 1673 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1674 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1675 1676 /* 1677 * Set the prefetchable bit - this bit is only valid if the PRDTL 1678 * field is non-zero or the ATAPI 'A' bit is set in the command 1679 * header. This bit cannot be set when using native command 1680 * queuing commands or when using FIS-based switching with a Port 1681 * multiplier. 1682 */ 1683 if (command_type != AHCI_NCQ_CMD) 1684 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1685 1686 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1687 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1688 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1689 1690 /* 1691 * We are overloading satapkt_hba_driver_private with 1692 * watched_cycle count. 1693 */ 1694 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1695 1696 #if AHCI_DEBUG 1697 /* Dump the command header and table */ 1698 AHCIDBG0(AHCIDBG_COMMAND, ahci_ctlp, "\n"); 1699 AHCIDBG3(AHCIDBG_COMMAND, ahci_ctlp, 1700 "Command header&table for spkt 0x%p cmd_reg 0x%x port %d", 1701 spkt, scmd->satacmd_cmd_reg, port); 1702 ptr = (uint32_t *)cmd_header; 1703 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1704 " Command Header:%8x %8x %8x %8x", 1705 ptr[0], ptr[1], ptr[2], ptr[3]); 1706 1707 /* Dump the H2D register FIS */ 1708 ptr = (uint32_t *)h2d_register_fisp; 1709 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1710 " Command FIS: %8x %8x %8x %8x", 1711 ptr[0], ptr[1], ptr[2], ptr[3]); 1712 1713 /* Dump the ACMD register FIS */ 1714 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1715 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1716 if (ahci_debug_flags & AHCIDBG_COMMAND) 1717 ahci_log(ahci_ctlp, CE_WARN, 1718 " ATAPI command: %2x %2x %2x %2x " 1719 "%2x %2x %2x %2x", 1720 ptr2[8 * i], ptr2[8 * i + 1], 1721 ptr2[8 * i + 2], ptr2[8 * i + 3], 1722 ptr2[8 * i + 4], ptr2[8 * i + 5], 1723 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1724 1725 /* Dump the PRDT */ 1726 for (i = 0; i < ncookies; i++) { 1727 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1728 AHCIDBG5(AHCIDBG_COMMAND, ahci_ctlp, 1729 " Cookie %d: %8x %8x %8x %8x", 1730 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1731 } 1732 #endif 1733 1734 (void) ddi_dma_sync( 1735 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1736 0, 1737 ahci_cmd_table_size, 1738 DDI_DMA_SYNC_FORDEV); 1739 1740 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1741 cmd_slot * sizeof (ahci_cmd_header_t), 1742 sizeof (ahci_cmd_header_t), 1743 DDI_DMA_SYNC_FORDEV); 1744 1745 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1746 if (command_type == AHCI_NCQ_CMD) { 1747 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1748 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1749 (0x1 << cmd_slot)); 1750 } 1751 1752 /* Indicate to the HBA that a command is active. */ 1753 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1754 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1755 (0x1 << cmd_slot)); 1756 1757 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1758 "exit: port %d", port); 1759 1760 return (cmd_slot); 1761 } 1762 1763 /* 1764 * Called by the sata framework to abort the previously sent packet(s). 1765 * 1766 * Reset device to abort commands. 1767 */ 1768 static int 1769 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1770 { 1771 ahci_ctl_t *ahci_ctlp; 1772 ahci_port_t *ahci_portp; 1773 uint32_t slot_status = 0; 1774 uint32_t aborted_tags = 0; 1775 uint32_t finished_tags = 0; 1776 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1777 uint8_t port; 1778 int tmp_slot; 1779 1780 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1781 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1782 1783 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1784 "ahci_tran_abort enter: port %d", port); 1785 1786 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1787 mutex_enter(&ahci_portp->ahciport_mutex); 1788 1789 /* 1790 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1791 * commands are being mopped, therefore there is nothing else to do 1792 */ 1793 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1794 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1795 "ahci_tran_abort: port %d is in " 1796 "mopping process, so just return directly ", port); 1797 mutex_exit(&ahci_portp->ahciport_mutex); 1798 return (SATA_SUCCESS); 1799 } 1800 1801 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1802 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1803 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1804 /* 1805 * In case the targer driver would send the request before 1806 * sata framework can have the opportunity to process those 1807 * event reports. 1808 */ 1809 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1810 spkt->satapkt_device.satadev_state = 1811 ahci_portp->ahciport_port_state; 1812 ahci_update_sata_registers(ahci_ctlp, port, 1813 &spkt->satapkt_device); 1814 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1815 "ahci_tran_abort returning SATA_FAILURE while " 1816 "port in FAILED/SHUTDOWN/PWROFF state: " 1817 "port: %d", port); 1818 mutex_exit(&ahci_portp->ahciport_mutex); 1819 return (SATA_FAILURE); 1820 } 1821 1822 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1823 /* 1824 * ahci_intr_phyrdy_change() may have rendered it to 1825 * AHCI_PORT_TYPE_NODEV. 1826 */ 1827 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1828 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1829 spkt->satapkt_device.satadev_state = 1830 ahci_portp->ahciport_port_state; 1831 ahci_update_sata_registers(ahci_ctlp, port, 1832 &spkt->satapkt_device); 1833 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1834 "ahci_tran_abort returning SATA_FAILURE while " 1835 "no device attached: port: %d", port); 1836 mutex_exit(&ahci_portp->ahciport_mutex); 1837 return (SATA_FAILURE); 1838 } 1839 1840 if (flag == SATA_ABORT_ALL_PACKETS) { 1841 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1842 aborted_tags = ahci_portp->ahciport_pending_tags; 1843 1844 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1845 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 1846 1847 cmn_err(CE_NOTE, "!ahci port %d abort all packets", port); 1848 } else { 1849 aborted_tags = 0xffffffff; 1850 /* 1851 * Aborting one specific packet, first search the 1852 * ahciport_slot_pkts[] list for matching spkt. 1853 */ 1854 for (tmp_slot = 0; 1855 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 1856 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 1857 aborted_tags = (0x1 << tmp_slot); 1858 break; 1859 } 1860 } 1861 1862 if (aborted_tags == 0xffffffff) { 1863 /* request packet is not on the pending list */ 1864 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1865 "Cannot find the aborting pkt 0x%p on the " 1866 "pending list", (void *)spkt); 1867 ahci_update_sata_registers(ahci_ctlp, port, 1868 &spkt->satapkt_device); 1869 mutex_exit(&ahci_portp->ahciport_mutex); 1870 return (SATA_FAILURE); 1871 } 1872 cmn_err(CE_NOTE, "!ahci port %d abort satapkt 0x%p", 1873 port, (void *)spkt); 1874 } 1875 1876 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1877 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1878 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1879 1880 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1881 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1882 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 1883 1884 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 1885 ahci_portp->ahciport_mop_in_progress++; 1886 1887 /* 1888 * To abort the packet(s), first we are trying to clear PxCMD.ST 1889 * to stop the port, and if the port can be stopped 1890 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 1891 * then we just send back the aborted packet(s) with ABORTED flag 1892 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 1893 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 1894 * perform a COMRESET. 1895 */ 1896 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 1897 ahci_portp, port, NULL, NULL); 1898 1899 /* 1900 * Compute which have finished and which need to be retried. 1901 * 1902 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 1903 * minus the slot_status. The aborted_tags has to be deducted by 1904 * finished_tags since we can't possibly abort a tag which had finished 1905 * already. 1906 */ 1907 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1908 finished_tags = ahci_portp->ahciport_pending_tags & 1909 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1910 1911 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1912 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 1913 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 1914 1915 aborted_tags &= ~finished_tags; 1916 1917 ahci_mop_commands(ahci_ctlp, 1918 ahci_portp, 1919 port, 1920 slot_status, 1921 0, /* failed tags */ 1922 0, /* timeout tags */ 1923 aborted_tags, 1924 0); /* reset tags */ 1925 1926 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 1927 mutex_exit(&ahci_portp->ahciport_mutex); 1928 1929 return (SATA_SUCCESS); 1930 } 1931 1932 /* 1933 * Used to do device reset and reject all the pending packets on a device 1934 * during the reset operation. 1935 * 1936 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1937 */ 1938 static int 1939 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 1940 ahci_port_t *ahci_portp, uint8_t port) 1941 { 1942 uint32_t slot_status = 0; 1943 uint32_t reset_tags = 0; 1944 uint32_t finished_tags = 0; 1945 sata_device_t sdevice; 1946 int ret; 1947 1948 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1949 "ahci_reset_device_reject_pkts on port: %d", port); 1950 1951 /* 1952 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1953 * commands are being mopped, therefore there is nothing else to do 1954 */ 1955 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1956 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1957 "ahci_reset_device_reject_pkts: port %d is in " 1958 "mopping process, so return directly ", port); 1959 return (SATA_SUCCESS); 1960 } 1961 1962 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1963 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1964 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 1965 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 1966 } 1967 1968 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1969 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 1970 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 1971 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 1972 } 1973 1974 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 1975 != AHCI_SUCCESS) { 1976 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1977 "Try to do a port reset after software " 1978 "reset failed", port); 1979 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 1980 if (ret != AHCI_SUCCESS) { 1981 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1982 "ahci_reset_device_reject_pkts: port %d " 1983 "failed", port); 1984 return (SATA_FAILURE); 1985 } 1986 } 1987 /* Set the reset in progress flag */ 1988 ahci_portp->ahciport_reset_in_progress = 1; 1989 1990 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 1991 ahci_portp->ahciport_mop_in_progress++; 1992 1993 /* Indicate to the framework that a reset has happened */ 1994 bzero((void *)&sdevice, sizeof (sata_device_t)); 1995 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 1996 sdevice.satadev_addr.pmport = 0; 1997 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 1998 1999 sdevice.satadev_state = SATA_DSTATE_RESET | 2000 SATA_DSTATE_PWR_ACTIVE; 2001 mutex_exit(&ahci_portp->ahciport_mutex); 2002 sata_hba_event_notify( 2003 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2004 &sdevice, 2005 SATA_EVNT_DEVICE_RESET); 2006 mutex_enter(&ahci_portp->ahciport_mutex); 2007 2008 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2009 "port %d sending event up: SATA_EVNT_RESET", port); 2010 2011 /* Next try to mop the pending commands */ 2012 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2013 finished_tags = ahci_portp->ahciport_pending_tags & 2014 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2015 2016 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2017 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2018 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2019 2020 reset_tags &= ~finished_tags; 2021 2022 ahci_mop_commands(ahci_ctlp, 2023 ahci_portp, 2024 port, 2025 slot_status, 2026 0, /* failed tags */ 2027 0, /* timeout tags */ 2028 0, /* aborted tags */ 2029 reset_tags); /* reset tags */ 2030 2031 return (SATA_SUCCESS); 2032 } 2033 2034 /* 2035 * Used to do port reset and reject all the pending packets on a port during 2036 * the reset operation. 2037 * 2038 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2039 */ 2040 static int 2041 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2042 ahci_port_t *ahci_portp, uint8_t port) 2043 { 2044 uint32_t slot_status = 0; 2045 uint32_t reset_tags = 0; 2046 uint32_t finished_tags = 0; 2047 2048 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2049 "ahci_reset_port_reject_pkts on port: %d", port); 2050 2051 /* 2052 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2053 * commands are being mopped, therefore there is nothing else to do 2054 */ 2055 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2056 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2057 "ahci_reset_port_reject_pkts: port %d is in " 2058 "mopping process, so return directly ", port); 2059 return (SATA_SUCCESS); 2060 } 2061 2062 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2063 ahci_portp->ahciport_mop_in_progress++; 2064 2065 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2066 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2067 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2068 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2069 } 2070 2071 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2072 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2073 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2074 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2075 } 2076 2077 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2078 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2079 NULL) != AHCI_SUCCESS) 2080 return (SATA_FAILURE); 2081 2082 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2083 finished_tags = ahci_portp->ahciport_pending_tags & 2084 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2085 2086 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2087 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2088 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2089 2090 reset_tags &= ~finished_tags; 2091 2092 ahci_mop_commands(ahci_ctlp, 2093 ahci_portp, 2094 port, 2095 slot_status, 2096 0, /* failed tags */ 2097 0, /* timeout tags */ 2098 0, /* aborted tags */ 2099 reset_tags); /* reset tags */ 2100 2101 return (SATA_SUCCESS); 2102 } 2103 2104 /* 2105 * Used to do hba reset and reject all the pending packets on all ports 2106 * during the reset operation. 2107 */ 2108 static int 2109 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2110 { 2111 ahci_port_t *ahci_portp; 2112 uint32_t slot_status[AHCI_MAX_PORTS]; 2113 uint32_t reset_tags[AHCI_MAX_PORTS]; 2114 uint32_t finished_tags[AHCI_MAX_PORTS]; 2115 uint8_t port; 2116 int ret = SATA_SUCCESS; 2117 2118 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2119 "ahci_reset_hba_reject_pkts enter"); 2120 2121 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2122 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2123 continue; 2124 } 2125 2126 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2127 2128 mutex_enter(&ahci_portp->ahciport_mutex); 2129 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2130 slot_status[port] = ddi_get32( 2131 ahci_ctlp->ahcictl_ahci_acc_handle, 2132 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2133 reset_tags[port] = slot_status[port] & 2134 AHCI_SLOT_MASK(ahci_ctlp); 2135 } 2136 2137 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2138 slot_status[port] = ddi_get32( 2139 ahci_ctlp->ahcictl_ahci_acc_handle, 2140 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2141 reset_tags[port] = slot_status[port] & 2142 AHCI_NCQ_SLOT_MASK(ahci_portp); 2143 } 2144 mutex_exit(&ahci_portp->ahciport_mutex); 2145 } 2146 2147 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2148 ret = SATA_FAILURE; 2149 goto out; 2150 } 2151 2152 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2153 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2154 continue; 2155 } 2156 2157 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2158 2159 mutex_enter(&ahci_portp->ahciport_mutex); 2160 /* 2161 * To prevent recursive enter to ahci_mop_commands, we need 2162 * check AHCI_PORT_FLAG_MOPPING flag. 2163 */ 2164 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2165 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2166 "ahci_reset_hba_reject_pkts: port %d is in " 2167 "mopping process, so return directly ", port); 2168 mutex_exit(&ahci_portp->ahciport_mutex); 2169 continue; 2170 } 2171 2172 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2173 ahci_portp->ahciport_mop_in_progress++; 2174 2175 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2176 finished_tags[port] = 2177 ahci_portp->ahciport_pending_tags & 2178 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2179 2180 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2181 finished_tags[port] = 2182 ahci_portp->ahciport_pending_ncq_tags & 2183 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2184 2185 reset_tags[port] &= ~finished_tags[port]; 2186 2187 ahci_mop_commands(ahci_ctlp, 2188 ahci_portp, 2189 port, 2190 slot_status[port], 2191 0, /* failed tags */ 2192 0, /* timeout tags */ 2193 0, /* aborted tags */ 2194 reset_tags[port]); /* reset tags */ 2195 mutex_exit(&ahci_portp->ahciport_mutex); 2196 } 2197 out: 2198 return (ret); 2199 } 2200 2201 /* 2202 * Called by sata framework to reset a port(s) or device. 2203 */ 2204 static int 2205 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2206 { 2207 ahci_ctl_t *ahci_ctlp; 2208 ahci_port_t *ahci_portp; 2209 uint8_t cport = sd->satadev_addr.cport; 2210 uint8_t port; 2211 int ret = SATA_SUCCESS; 2212 2213 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2214 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2215 2216 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2217 "ahci_tran_reset_port enter: cport: %d", cport); 2218 2219 switch (sd->satadev_addr.qual) { 2220 case SATA_ADDR_CPORT: 2221 /* Port reset */ 2222 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2223 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2224 "reset port", port); 2225 2226 mutex_enter(&ahci_portp->ahciport_mutex); 2227 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2228 mutex_exit(&ahci_portp->ahciport_mutex); 2229 2230 break; 2231 2232 case SATA_ADDR_DCPORT: 2233 /* Device reset */ 2234 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2235 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2236 "reset device", port); 2237 2238 mutex_enter(&ahci_portp->ahciport_mutex); 2239 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2240 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2241 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2242 /* 2243 * In case the targer driver would send the request 2244 * before sata framework can have the opportunity to 2245 * process those event reports. 2246 */ 2247 sd->satadev_state = ahci_portp->ahciport_port_state; 2248 ahci_update_sata_registers(ahci_ctlp, port, sd); 2249 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2250 "ahci_tran_reset_dport returning SATA_FAILURE " 2251 "while port in FAILED/SHUTDOWN/PWROFF state: " 2252 "port: %d", port); 2253 mutex_exit(&ahci_portp->ahciport_mutex); 2254 ret = SATA_FAILURE; 2255 break; 2256 } 2257 2258 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2259 /* 2260 * ahci_intr_phyrdy_change() may have rendered it to 2261 * AHCI_PORT_TYPE_NODEV. 2262 */ 2263 sd->satadev_type = SATA_DTYPE_NONE; 2264 sd->satadev_state = ahci_portp->ahciport_port_state; 2265 ahci_update_sata_registers(ahci_ctlp, port, sd); 2266 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2267 "ahci_tran_reset_dport returning SATA_FAILURE " 2268 "while no device attached: port: %d", port); 2269 mutex_exit(&ahci_portp->ahciport_mutex); 2270 ret = SATA_FAILURE; 2271 break; 2272 } 2273 2274 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2275 ahci_portp, port); 2276 mutex_exit(&ahci_portp->ahciport_mutex); 2277 break; 2278 2279 case SATA_ADDR_CNTRL: 2280 /* Reset the whole controller */ 2281 cmn_err(CE_NOTE, "!ahci_tran_reset_dport: port %d " 2282 "reset the whole hba", port); 2283 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2284 break; 2285 2286 case SATA_ADDR_PMPORT: 2287 case SATA_ADDR_DPMPORT: 2288 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2289 "ahci_tran_reset_dport: port multiplier will be " 2290 "supported later"); 2291 /* FALLSTHROUGH */ 2292 default: 2293 ret = SATA_FAILURE; 2294 } 2295 2296 return (ret); 2297 } 2298 2299 /* 2300 * Called by sata framework to activate a port as part of hotplug. 2301 * (cfgadm -c connect satax/y) 2302 * Note: Not port-mult aware. 2303 */ 2304 static int 2305 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2306 { 2307 ahci_ctl_t *ahci_ctlp; 2308 ahci_port_t *ahci_portp; 2309 uint8_t cport = satadev->satadev_addr.cport; 2310 uint8_t port; 2311 2312 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2313 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2314 2315 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2316 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2317 2318 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2319 2320 mutex_enter(&ahci_portp->ahciport_mutex); 2321 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2322 cmn_err(CE_NOTE, "!ahci port %d is activated", port); 2323 2324 /* 2325 * Reset the port so that the PHY communication would be re-established. 2326 * But this reset is an internal operation and the sata module doesn't 2327 * need to know about it. Moreover, the port with a device attached will 2328 * be started too. 2329 */ 2330 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2331 ahci_portp, port, 2332 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2333 NULL); 2334 2335 /* 2336 * Need to check the link status and device status of the port 2337 * and consider raising power if the port was in D3 state 2338 */ 2339 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2340 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2341 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2342 2343 satadev->satadev_state = ahci_portp->ahciport_port_state; 2344 2345 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2346 2347 mutex_exit(&ahci_portp->ahciport_mutex); 2348 return (SATA_SUCCESS); 2349 } 2350 2351 /* 2352 * Called by sata framework to deactivate a port as part of hotplug. 2353 * (cfgadm -c disconnect satax/y) 2354 * Note: Not port-mult aware. 2355 */ 2356 static int 2357 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2358 { 2359 ahci_ctl_t *ahci_ctlp; 2360 ahci_port_t *ahci_portp; 2361 uint8_t cport = satadev->satadev_addr.cport; 2362 uint8_t port; 2363 uint32_t port_scontrol; 2364 2365 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 2366 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2367 2368 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2369 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2370 2371 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2372 2373 mutex_enter(&ahci_portp->ahciport_mutex); 2374 cmn_err(CE_NOTE, "!ahci port %d is deactivated", port); 2375 2376 /* Disable the interrupts on the port */ 2377 ahci_disable_port_intrs(ahci_ctlp, ahci_portp, port); 2378 2379 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2380 goto phy_offline; 2381 } 2382 2383 /* First to abort all the pending commands */ 2384 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2385 2386 /* Then stop the port */ 2387 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2388 ahci_portp, port); 2389 2390 /* Next put the PHY offline */ 2391 2392 phy_offline: 2393 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2394 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2395 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2396 2397 /* Update ahciport_port_state */ 2398 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2399 satadev->satadev_state = ahci_portp->ahciport_port_state; 2400 2401 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2402 2403 mutex_exit(&ahci_portp->ahciport_mutex); 2404 return (SATA_SUCCESS); 2405 } 2406 2407 /* 2408 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2409 * when a device is unplugged or a port is deactivated. 2410 * 2411 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2412 */ 2413 static void 2414 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2415 ahci_port_t *ahci_portp, uint8_t port) 2416 { 2417 uint32_t slot_status = 0; 2418 uint32_t abort_tags = 0; 2419 2420 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2421 "ahci_reject_all_abort_pkts on port: %d", port); 2422 2423 /* 2424 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2425 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2426 * to get the error data, if yes when the device is removed, the 2427 * command needs to be aborted too. 2428 */ 2429 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2430 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2431 slot_status = 0x1; 2432 abort_tags = 0x1; 2433 goto out; 2434 } else { 2435 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2436 "ahci_reject_all_abort_pkts return directly " 2437 "port %d no needs to reject any outstanding " 2438 "commands", port); 2439 return; 2440 } 2441 } 2442 2443 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2444 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2445 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2446 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2447 } 2448 2449 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2450 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2451 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2452 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2453 } 2454 2455 out: 2456 /* No need to do mop when there is no outstanding commands */ 2457 if (slot_status != 0) { 2458 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2459 ahci_portp->ahciport_mop_in_progress++; 2460 2461 ahci_mop_commands(ahci_ctlp, 2462 ahci_portp, 2463 port, 2464 slot_status, 2465 0, /* failed tags */ 2466 0, /* timeout tags */ 2467 abort_tags, /* aborting tags */ 2468 0); /* reset tags */ 2469 } 2470 } 2471 2472 #if defined(__lock_lint) 2473 static int 2474 ahci_selftest(dev_info_t *dip, sata_device_t *device) 2475 { 2476 return (SATA_SUCCESS); 2477 } 2478 #endif 2479 2480 /* 2481 * Allocate the ports structure, only called by ahci_attach 2482 */ 2483 static int 2484 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2485 { 2486 int port, cport = 0; 2487 2488 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2489 "ahci_alloc_ports_state enter"); 2490 2491 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2492 2493 /* Allocate structures only for the implemented ports */ 2494 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2495 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2496 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2497 "hba port %d not implemented", port); 2498 continue; 2499 } 2500 2501 #ifndef __lock_lint 2502 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2503 ahci_ctlp->ahcictl_port_to_cport[port] = 2504 (uint8_t)cport++; 2505 #endif /* __lock_lint */ 2506 2507 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2508 goto err_out; 2509 } 2510 } 2511 2512 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2513 return (AHCI_SUCCESS); 2514 2515 err_out: 2516 for (port--; port >= 0; port--) { 2517 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2518 ahci_dealloc_port_state(ahci_ctlp, port); 2519 } 2520 } 2521 2522 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2523 return (AHCI_FAILURE); 2524 } 2525 2526 /* 2527 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2528 */ 2529 static void 2530 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2531 { 2532 int port; 2533 2534 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2535 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2536 /* if this port is implemented by the HBA */ 2537 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2538 ahci_dealloc_port_state(ahci_ctlp, port); 2539 } 2540 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2541 } 2542 2543 /* 2544 * Initialize the controller. 2545 * 2546 * This routine can be called from three seperate cases: DDI_ATTACH, 2547 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2548 * other two cases; device signature probing are attempted only during 2549 * DDI_ATTACH case. 2550 * 2551 * WARNING!!! Disable the whole controller's interrupts before calling and 2552 * the interrupts will be enabled upon successfully return. 2553 */ 2554 static int 2555 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2556 { 2557 ahci_port_t *ahci_portp; 2558 uint32_t ghc_control; 2559 int port; 2560 2561 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2562 "ahci_initialize_controller enter"); 2563 2564 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2565 2566 /* 2567 * Indicate that system software is AHCI aware by setting 2568 * GHC.AE to 1 2569 */ 2570 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2571 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2572 2573 ghc_control |= AHCI_HBA_GHC_AE; 2574 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2575 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2576 ghc_control); 2577 2578 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2579 2580 /* Initialize the implemented ports and structures */ 2581 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2582 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2583 continue; 2584 } 2585 2586 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2587 mutex_enter(&ahci_portp->ahciport_mutex); 2588 2589 /* 2590 * Ensure that the controller is not in the running state 2591 * by checking every implemented port's PxCMD register 2592 */ 2593 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2594 != AHCI_SUCCESS) { 2595 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2596 "ahci_initialize_controller: failed to " 2597 "initialize port %d", port); 2598 /* 2599 * Set the port state to SATA_PSTATE_FAILED if 2600 * failed to initialize it. 2601 */ 2602 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2603 } 2604 2605 mutex_exit(&ahci_portp->ahciport_mutex); 2606 } 2607 2608 /* Enable the whole controller interrupts */ 2609 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2610 ahci_enable_all_intrs(ahci_ctlp); 2611 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2612 2613 return (AHCI_SUCCESS); 2614 } 2615 2616 /* 2617 * Reverse of ahci_initialize_controller() 2618 * 2619 * WARNING!!! ahcictl_mutex should be acquired before the function is called. 2620 */ 2621 static void 2622 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2623 { 2624 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2625 "ahci_uninitialize_controller enter"); 2626 2627 /* disable all the interrupts. */ 2628 ahci_disable_all_intrs(ahci_ctlp); 2629 } 2630 2631 /* 2632 * The routine is to initialize the port. First put the port in NOTRunning 2633 * state, then enable port interrupt and clear Serror register. And under 2634 * AHCI_ATTACH case, find device signature and then try to start the port. 2635 * 2636 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2637 */ 2638 static int 2639 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2640 ahci_port_t *ahci_portp, uint8_t port) 2641 { 2642 uint32_t port_cmd_status; 2643 2644 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2645 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2646 2647 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2648 "ahci_initialize_port: port %d " 2649 "port_cmd_status = 0x%x", port, port_cmd_status); 2650 /* 2651 * Check whether the port is in NotRunning state, if not, 2652 * put the port in NotRunning state 2653 */ 2654 if (!(port_cmd_status & 2655 (AHCI_CMD_STATUS_ST | 2656 AHCI_CMD_STATUS_CR | 2657 AHCI_CMD_STATUS_FRE | 2658 AHCI_CMD_STATUS_FR))) { 2659 2660 goto next; 2661 } 2662 2663 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2664 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2665 return (AHCI_FAILURE); 2666 2667 next: 2668 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2669 "port %d is in NotRunning state now", port); 2670 2671 /* 2672 * At the time being, only probe ports/devices and get the types of 2673 * attached devices during attach. In fact, the device can be changed 2674 * during power state changes, but I would like to postpone this part 2675 * when the power management is supported. 2676 */ 2677 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2678 /* Try to get the device signature */ 2679 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2680 2681 /* Return directly if no device connected */ 2682 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2683 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2684 "No device connected to port %d", port); 2685 goto out; 2686 } 2687 2688 /* Try to start the port */ 2689 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2690 != AHCI_SUCCESS) { 2691 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2692 "failed to start port %d", port); 2693 return (AHCI_FAILURE); 2694 } 2695 } 2696 out: 2697 /* Enable port interrupts */ 2698 ahci_enable_port_intrs(ahci_ctlp, ahci_portp, port); 2699 2700 return (AHCI_SUCCESS); 2701 } 2702 2703 /* 2704 * AHCI device reset ...; a single device on one of the ports is reset, 2705 * but the HBA and physical communication remain intact. This is the 2706 * least intrusive. 2707 * 2708 * When issuing a software reset sequence, there should not be other 2709 * commands in the command list, so we will first clear and then re-set 2710 * PxCMD.ST to clear PxCI. And before issuing the software reset, 2711 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 2712 * cleared. 2713 * 2714 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 2715 * set before the function is called. 2716 */ 2717 static int 2718 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 2719 uint8_t port) 2720 { 2721 ahci_fis_h2d_register_t *h2d_register_fisp; 2722 ahci_cmd_table_t *cmd_table; 2723 ahci_cmd_header_t *cmd_header; 2724 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 2725 int slot, loop_count; 2726 2727 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2728 "Port %d device resetting", port); 2729 2730 /* First to clear PxCMD.ST */ 2731 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2732 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2733 2734 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 2735 2736 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2737 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2738 port_cmd_status|AHCI_CMD_STATUS_ST); 2739 2740 /* And then to re-set PxCMD.ST */ 2741 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2742 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2743 2744 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2745 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2746 port_cmd_status|AHCI_CMD_STATUS_ST); 2747 2748 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 2749 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2750 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 2751 2752 if (port_task_file & AHCI_TFD_STS_BSY || 2753 port_task_file & AHCI_TFD_STS_DRQ) { 2754 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 2755 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2756 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 2757 "but PxCMD.CLO isn't supported, so a port " 2758 "reset is needed."); 2759 return (AHCI_FAILURE); 2760 } 2761 } 2762 2763 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, AHCI_NON_NCQ_CMD); 2764 if (slot == AHCI_FAILURE) { 2765 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2766 "ahci_software_reset: no free slot"); 2767 return (AHCI_FAILURE); 2768 } 2769 2770 /* Now send the first R2H FIS with SRST set to 1 */ 2771 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 2772 bzero((void *)cmd_table, ahci_cmd_table_size); 2773 2774 h2d_register_fisp = 2775 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 2776 2777 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 2778 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 2779 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 2780 2781 /* Set Command Header in Command List */ 2782 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 2783 BZERO_DESCR_INFO(cmd_header); 2784 BZERO_PRD_BYTE_COUNT(cmd_header); 2785 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 2786 2787 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 2788 SET_RESET(cmd_header, 1); 2789 SET_WRITE(cmd_header, 1); 2790 2791 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 2792 0, 2793 ahci_cmd_table_size, 2794 DDI_DMA_SYNC_FORDEV); 2795 2796 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 2797 slot * sizeof (ahci_cmd_header_t), 2798 sizeof (ahci_cmd_header_t), 2799 DDI_DMA_SYNC_FORDEV); 2800 2801 /* Indicate to the HBA that a command is active. */ 2802 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2803 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 2804 (0x1 << slot)); 2805 2806 loop_count = 0; 2807 2808 /* Loop till the first command is finished */ 2809 do { 2810 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2811 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2812 2813 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 2814 /* We are effectively timing out after 0.1 sec. */ 2815 break; 2816 } 2817 /* Wait for 10 millisec */ 2818 #ifndef __lock_lint 2819 delay(AHCI_10MS_TICKS); 2820 #endif /* __lock_lint */ 2821 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 2822 2823 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 2824 "ahci_software_reset: 1st loop count: %d, " 2825 "port_cmd_issue = 0x%x, slot = 0x%x", 2826 loop_count, port_cmd_issue, slot); 2827 2828 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 2829 ahci_portp->ahciport_slot_pkts[slot] = NULL; 2830 2831 /* Now send the second R2H FIS with SRST cleard to zero */ 2832 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 2833 bzero((void *)cmd_table, ahci_cmd_table_size); 2834 2835 h2d_register_fisp = 2836 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 2837 2838 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 2839 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 2840 2841 /* Set Command Header in Command List */ 2842 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 2843 BZERO_DESCR_INFO(cmd_header); 2844 BZERO_PRD_BYTE_COUNT(cmd_header); 2845 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 2846 2847 SET_WRITE(cmd_header, 1); 2848 2849 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 2850 0, 2851 ahci_cmd_table_size, 2852 DDI_DMA_SYNC_FORDEV); 2853 2854 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 2855 slot * sizeof (ahci_cmd_header_t), 2856 sizeof (ahci_cmd_header_t), 2857 DDI_DMA_SYNC_FORDEV); 2858 2859 /* Indicate to the HBA that a command is active. */ 2860 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2861 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 2862 (0x1 << slot)); 2863 2864 loop_count = 0; 2865 2866 /* Loop till the second command is finished */ 2867 do { 2868 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2869 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2870 2871 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 2872 /* We are effectively timing out after 0.1 sec. */ 2873 break; 2874 } 2875 /* Wait for 10 millisec */ 2876 #ifndef __lock_lint 2877 delay(AHCI_10MS_TICKS); 2878 #endif /* __lock_lint */ 2879 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 2880 2881 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 2882 "ahci_software_reset: 2nd loop count: %d, " 2883 "port_cmd_issue = 0x%x, slot = 0x%x", 2884 loop_count, port_cmd_issue, slot); 2885 2886 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 2887 ahci_portp->ahciport_slot_pkts[slot] = NULL; 2888 2889 return (AHCI_SUCCESS); 2890 } 2891 2892 /* 2893 * AHCI port reset ...; the physical communication between the HBA and device 2894 * on a port are disabled. This is more intrusive. 2895 * 2896 * When an HBA or port reset occurs, Phy communication is going to 2897 * be re-established with the device through a COMRESET followed by the 2898 * normal out-of-band communication sequence defined in Serial ATA. AT 2899 * the end of reset, the device, if working properly, will send a D2H 2900 * Register FIS, which contains the device signature. When the HBA receives 2901 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 2902 * the PxSIG register with the signature. 2903 * 2904 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 2905 * to individually spin-up attached devices. Please refer to chapter 10.9 of 2906 * AHCI 1.0 spec. 2907 */ 2908 /* 2909 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 2910 * cleared before the function is called. 2911 */ 2912 static int 2913 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 2914 { 2915 uint32_t cap_status, port_cmd_status; 2916 uint32_t port_scontrol, port_sstatus; 2917 uint32_t port_signature, port_intr_status, port_task_file; 2918 int loop_count; 2919 int rval = AHCI_SUCCESS; 2920 2921 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2922 "Port %d port resetting...", port); 2923 ahci_portp->ahciport_port_state = 0; 2924 2925 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2926 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 2927 2928 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2929 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2930 2931 if (cap_status & AHCI_HBA_CAP_SSS) { 2932 /* 2933 * HBA support staggered spin-up, if the port has 2934 * not spin up yet, then force it to do spin-up 2935 */ 2936 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 2937 if (!(ahci_portp->ahciport_flags 2938 & AHCI_PORT_FLAG_SPINUP)) { 2939 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2940 "Port %d PxCMD.SUD is zero, force " 2941 "it to do spin-up", port); 2942 ahci_portp->ahciport_flags |= 2943 AHCI_PORT_FLAG_SPINUP; 2944 } 2945 } 2946 } else { 2947 /* 2948 * HBA doesn't support stagger spin-up, force it 2949 * to do normal COMRESET 2950 */ 2951 ASSERT(port_cmd_status & AHCI_CMD_STATUS_SUD); 2952 if (ahci_portp->ahciport_flags & 2953 AHCI_PORT_FLAG_SPINUP) { 2954 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2955 "HBA does not support staggered spin-up " 2956 "force it to do normal COMRESET"); 2957 ahci_portp->ahciport_flags &= 2958 ~AHCI_PORT_FLAG_SPINUP; 2959 } 2960 } 2961 2962 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 2963 /* Do normal COMRESET */ 2964 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2965 "ahci_port_reset: do normal COMRESET", port); 2966 2967 ASSERT(port_cmd_status & AHCI_CMD_STATUS_SUD); 2968 2969 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2970 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2971 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 2972 2973 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2974 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 2975 port_scontrol); 2976 2977 /* Enable PxCMD.FRE to read device */ 2978 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2979 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 2980 port_cmd_status|AHCI_CMD_STATUS_FRE); 2981 2982 /* 2983 * Give time for COMRESET to percolate, according to the AHCI 2984 * spec, software shall wait at least 1 millisecond before 2985 * clearing PxSCTL.DET 2986 */ 2987 #ifndef __lock_lint 2988 delay(AHCI_1MS_TICKS*2); 2989 #endif /* __lock_lint */ 2990 2991 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 2992 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2993 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2994 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 2995 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2996 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 2997 port_scontrol); 2998 } else { 2999 /* Do staggered spin-up */ 3000 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3001 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3002 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3003 3004 /* PxSCTL.DET must be 0 */ 3005 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3006 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3007 port_scontrol); 3008 3009 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3010 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3011 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3012 port_cmd_status); 3013 3014 /* 0 -> 1 edge */ 3015 #ifndef __lock_lint 3016 delay(AHCI_1MS_TICKS*2); 3017 #endif /* __lock_lint */ 3018 3019 /* Set PxCMD.SUD to 1 */ 3020 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3021 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3022 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3023 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3024 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3025 port_cmd_status); 3026 3027 /* Enable PxCMD.FRE to read device */ 3028 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3029 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3030 port_cmd_status|AHCI_CMD_STATUS_FRE); 3031 } 3032 3033 /* 3034 * The port enters P:StartComm state, and HBA tells link layer to 3035 * start communication, which involves sending COMRESET to device. 3036 * And the HBA resets PxTFD.STS to 7Fh. 3037 * 3038 * When a COMINIT is received from the device, then the port enters 3039 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3040 * PxSSTS.DET to 1h to indicate a device is detected but communication 3041 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3042 * a COMINIT has been received. 3043 */ 3044 /* 3045 * The DET field is valid only if IPM field indicates 3046 * that the interface is in active state. 3047 */ 3048 loop_count = 0; 3049 do { 3050 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3051 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3052 3053 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3054 /* 3055 * If the interface is not active, the DET field 3056 * is considered not accurate. So we want to 3057 * continue looping. 3058 */ 3059 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3060 } 3061 3062 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3063 /* 3064 * We are effectively timing out after 0.1 sec. 3065 */ 3066 break; 3067 } 3068 3069 /* Wait for 10 millisec */ 3070 #ifndef __lock_lint 3071 delay(AHCI_10MS_TICKS); 3072 #endif /* __lock_lint */ 3073 3074 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3075 3076 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3077 "ahci_port_reset: 1st loop count: %d, " 3078 "port_sstatus = 0x%x port %d", 3079 loop_count, port_sstatus, port); 3080 3081 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3082 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3083 /* 3084 * Either the port is not active or there 3085 * is no device present. 3086 */ 3087 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3088 goto out; 3089 } 3090 3091 /* Now we can make sure there is a device connected to the port */ 3092 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3093 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3094 3095 /* a COMINIT signal is supposed to be received */ 3096 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 3097 cmn_err(CE_WARN, "ahci_port_reset: port %d COMINIT signal " 3098 "from the device not received", port); 3099 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3100 rval = AHCI_FAILURE; 3101 goto out; 3102 } 3103 3104 /* PxTFD.STS.BSY is supposed to be set */ 3105 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3106 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3107 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3108 cmn_err(CE_WARN, "ahci_port_reset: port %d BSY bit " 3109 "is not set after COMINIT signal is received", port); 3110 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3111 rval = AHCI_FAILURE; 3112 goto out; 3113 } 3114 3115 /* 3116 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3117 * the D2H FIS received by HBA. 3118 */ 3119 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3120 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3121 SERROR_EXCHANGED_ERR); 3122 3123 /* 3124 * Next check whether COMRESET is completed successfully 3125 */ 3126 loop_count = 0; 3127 do { 3128 port_task_file = 3129 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3130 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3131 3132 /* 3133 * The Error bit '1' means COMRESET is finished successfully 3134 * The device hardware has been initialized and the power-up 3135 * diagnostics successfully completed. 3136 */ 3137 if (((port_task_file & AHCI_TFD_ERR_MASK) 3138 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 3139 3140 port_signature = ddi_get32( 3141 ahci_ctlp->ahcictl_ahci_acc_handle, 3142 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3143 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 3144 "COMRESET success, D2H register FIS " 3145 "post to received FIS structure " 3146 "port %d signature = 0x%x", 3147 port, port_signature); 3148 goto out_check; 3149 } 3150 3151 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3152 /* 3153 * We are effectively timing out after 11 sec. 3154 */ 3155 break; 3156 } 3157 3158 /* Wait for 10 millisec */ 3159 #ifndef __lock_lint 3160 delay(AHCI_10MS_TICKS); 3161 #endif /* __lock_lint */ 3162 3163 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3164 >> AHCI_TFD_ERR_SHIFT) != 0x1); 3165 3166 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 3167 "count: %d, port_task_file = 0x%x port %d", 3168 loop_count, port_task_file, port); 3169 3170 cmn_err(CE_WARN, "ahci_port_reset: port %d the device hardware " 3171 "has been initialized and the power-up diagnostics failed", 3172 port); 3173 3174 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3175 rval = AHCI_FAILURE; 3176 3177 out: 3178 /* Clear port serror register for the port */ 3179 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3180 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3181 AHCI_SERROR_CLEAR_ALL); 3182 3183 return (rval); 3184 3185 out_check: 3186 /* 3187 * Check device status, if keep busy or COMRESET error 3188 * do device reset to patch some SATA disks' issue 3189 * 3190 * For VT8251, sometimes need to do the device reset 3191 */ 3192 if ((port_task_file & AHCI_TFD_STS_BSY) || 3193 (port_task_file & AHCI_TFD_STS_DRQ)) { 3194 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 3195 "need to do device reset", port); 3196 3197 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 3198 3199 port_task_file = 3200 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3201 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3202 3203 if (port_task_file & AHCI_TFD_STS_BSY || 3204 port_task_file & AHCI_TFD_STS_DRQ) { 3205 cmn_err(CE_WARN, "ahci_port_reset: port %d " 3206 "BSY/DRQ still set after device reset " 3207 "port_task_file = 0x%x", 3208 port, port_task_file); 3209 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3210 rval = AHCI_FAILURE; 3211 } 3212 } 3213 3214 goto out; 3215 } 3216 3217 /* 3218 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3219 * This is the most intrusive. 3220 * 3221 * When an HBA reset occurs, Phy communication will be re-established with 3222 * the device through a COMRESET followed by the normal out-of-band 3223 * communication sequence defined in Serial ATA. AT the end of reset, the 3224 * device, if working properly, will send a D2H Register FIS, which contains 3225 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3226 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3227 * signature. 3228 * 3229 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3230 */ 3231 static int 3232 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3233 { 3234 ahci_port_t *ahci_portp; 3235 uint32_t ghc_control; 3236 uint8_t port; 3237 int loop_count; 3238 int rval = AHCI_SUCCESS; 3239 3240 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3241 3242 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3243 3244 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3245 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3246 3247 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3248 ghc_control |= AHCI_HBA_GHC_HR; 3249 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3250 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3251 3252 /* 3253 * Wait until HBA Reset complete or timeout 3254 */ 3255 loop_count = 0; 3256 do { 3257 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3258 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3259 3260 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3261 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3262 "ahci hba reset is timing out, " 3263 "ghc_control = 0x%x", ghc_control); 3264 /* We are effectively timing out after 1 sec. */ 3265 break; 3266 } 3267 3268 /* Wait for 10 millisec */ 3269 #ifndef __lock_lint 3270 delay(AHCI_10MS_TICKS); 3271 #endif /* __lock_lint */ 3272 3273 } while (ghc_control & AHCI_HBA_GHC_HR); 3274 3275 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3276 "ahci_hba_reset: 1st loop count: %d, " 3277 "ghc_control = 0x%x", loop_count, ghc_control); 3278 3279 if (ghc_control & AHCI_HBA_GHC_HR) { 3280 /* The hba is not reset for some reasons */ 3281 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3282 "hba reset failed: HBA in a hung or locked state"); 3283 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3284 return (AHCI_FAILURE); 3285 } 3286 3287 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3288 /* Only check implemented ports */ 3289 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3290 continue; 3291 } 3292 3293 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3294 mutex_enter(&ahci_portp->ahciport_mutex); 3295 3296 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3297 != AHCI_SUCCESS) { 3298 rval = AHCI_FAILURE; 3299 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3300 "ahci_hba_reset: port %d failed", port); 3301 } 3302 3303 mutex_exit(&ahci_portp->ahciport_mutex); 3304 } 3305 3306 /* 3307 * Indicate that system software is AHCI aware by setting 3308 * GHC.AE to 1 3309 */ 3310 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3311 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3312 3313 ghc_control |= AHCI_HBA_GHC_AE; 3314 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3315 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3316 3317 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3318 3319 return (rval); 3320 } 3321 3322 /* 3323 * This routine is only called from AHCI_ATTACH or phyrdy change 3324 * case. It first calls port reset to initialize port, probe port and probe 3325 * device, then try to read PxSIG register to find the type of device 3326 * attached to the port. 3327 * 3328 * WARNING!!! ahciport_mutex should be acquired before the function 3329 * is called. And the port interrupt is disabled. 3330 */ 3331 static void 3332 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3333 ahci_port_t *ahci_portp, uint8_t port) 3334 { 3335 uint32_t signature; 3336 3337 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3338 "ahci_find_dev_signature enter: port %d", port); 3339 3340 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3341 3342 /* Call port reset to check link status and get device signature */ 3343 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3344 3345 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3346 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3347 "ahci_find_dev_signature: No device is found " 3348 "at port %d", port); 3349 return; 3350 } 3351 3352 /* Check the port state */ 3353 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3354 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3355 "ahci_find_dev_signature: port %d state 0x%x", 3356 port, ahci_portp->ahciport_port_state); 3357 return; 3358 } 3359 3360 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3361 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3362 3363 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3364 "ahci_find_dev_signature: port %d signature = 0x%x", 3365 port, signature); 3366 3367 switch (signature) { 3368 3369 case AHCI_SIGNATURE_DISK: 3370 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3371 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3372 "Disk is found at port: %d", port); 3373 break; 3374 3375 case AHCI_SIGNATURE_ATAPI: 3376 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 3377 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3378 "ATAPI device is found at port: %d", port); 3379 break; 3380 3381 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3382 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3383 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3384 "Port Multiplier is found at port: %d", port); 3385 break; 3386 3387 default: 3388 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3389 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3390 "Unknown device is found at port: %d", port); 3391 } 3392 } 3393 3394 /* 3395 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3396 * to 1, then set it firstly. 3397 * 3398 * Each port contains two major DMA engines. One DMA engine walks through 3399 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3400 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3401 * 3402 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3403 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3404 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3405 * 3406 * Software shall not set PxCMD.ST to '1' unless a functional device is 3407 * present on the port(as determined by PxTFD.STS.BSY = '0', 3408 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3409 * 3410 * WARNING!!! ahciport_mutex should be acquired before the function 3411 * is called. 3412 */ 3413 static int 3414 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3415 { 3416 uint32_t port_cmd_status; 3417 3418 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3419 3420 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3421 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3422 "the state for port %d is 0x%x", 3423 port, ahci_portp->ahciport_port_state); 3424 return (AHCI_FAILURE); 3425 } 3426 3427 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3428 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3429 "no device is attached at port %d", port); 3430 return (AHCI_FAILURE); 3431 } 3432 3433 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3434 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3435 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3436 3437 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3438 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3439 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3440 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3441 port_cmd_status); 3442 } 3443 3444 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3445 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3446 3447 port_cmd_status |= AHCI_CMD_STATUS_ST; 3448 3449 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3450 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3451 port_cmd_status); 3452 3453 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3454 3455 return (AHCI_SUCCESS); 3456 } 3457 3458 /* 3459 * Allocate the ahci_port_t including Received FIS and Command List. 3460 * The argument - port is the physical port number, and not logical 3461 * port number seen by the SATA framework. 3462 * 3463 * WARNING!!! ahcictl_mutex should be acquired before the function 3464 * is called. 3465 */ 3466 static int 3467 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3468 { 3469 ahci_port_t *ahci_portp; 3470 3471 ahci_portp = 3472 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3473 3474 #ifndef __lock_lint 3475 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3476 #endif /* __lock_lint */ 3477 3478 ahci_portp->ahciport_port_num = port; 3479 3480 /* Intialize the port condition variable */ 3481 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3482 3483 /* Initialize the port mutex */ 3484 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3485 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3486 3487 mutex_enter(&ahci_portp->ahciport_mutex); 3488 3489 /* 3490 * Allocate memory for received FIS structure and 3491 * command list for this port 3492 */ 3493 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3494 goto err_case1; 3495 } 3496 3497 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3498 goto err_case2; 3499 } 3500 3501 ahci_portp->ahciport_event_args = 3502 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3503 3504 if (ahci_portp->ahciport_event_args == NULL) 3505 goto err_case3; 3506 3507 mutex_exit(&ahci_portp->ahciport_mutex); 3508 3509 return (AHCI_SUCCESS); 3510 3511 err_case3: 3512 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3513 3514 err_case2: 3515 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3516 3517 err_case1: 3518 mutex_exit(&ahci_portp->ahciport_mutex); 3519 mutex_destroy(&ahci_portp->ahciport_mutex); 3520 cv_destroy(&ahci_portp->ahciport_cv); 3521 3522 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3523 3524 return (AHCI_FAILURE); 3525 } 3526 3527 /* 3528 * Reverse of ahci_dealloc_port_state(). 3529 * 3530 * WARNING!!! ahcictl_mutex should be acquired before the function 3531 * is called. 3532 */ 3533 static void 3534 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3535 { 3536 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3537 3538 ASSERT(ahci_portp != NULL); 3539 3540 mutex_enter(&ahci_portp->ahciport_mutex); 3541 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3542 ahci_portp->ahciport_event_args = NULL; 3543 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3544 ahci_dealloc_rcvd_fis(ahci_ctlp, ahci_portp); 3545 mutex_exit(&ahci_portp->ahciport_mutex); 3546 3547 mutex_destroy(&ahci_portp->ahciport_mutex); 3548 cv_destroy(&ahci_portp->ahciport_cv); 3549 3550 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3551 3552 #ifndef __lock_lint 3553 ahci_ctlp->ahcictl_ports[port] = NULL; 3554 #endif /* __lock_lint */ 3555 } 3556 3557 /* 3558 * Allocates memory for the Received FIS Structure 3559 * 3560 * WARNING!!! ahciport_mutex should be acquired before the function 3561 * is called. 3562 */ 3563 static int 3564 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3565 uint8_t port) 3566 { 3567 size_t rcvd_fis_size; 3568 size_t ret_len; 3569 ddi_dma_cookie_t rcvd_fis_dma_cookie; 3570 uint_t cookie_count; 3571 uint32_t cap_status; 3572 3573 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3574 3575 /* Check whether the HBA can access 64-bit data structures */ 3576 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3577 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3578 3579 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 3580 3581 /* 3582 * If 64-bit addressing is not supported, 3583 * change dma_attr_addr_hi of ahcictl_rcvd_fis_dma_attr 3584 */ 3585 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3586 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3587 "hba does not support 64-bit addressing"); 3588 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 3589 0xffffffffull; 3590 } 3591 3592 /* allocate rcvd FIS dma handle. */ 3593 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3594 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3595 DDI_DMA_SLEEP, 3596 NULL, 3597 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3598 DDI_SUCCESS) { 3599 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3600 "rcvd FIS dma handle alloc failed"); 3601 3602 return (AHCI_FAILURE); 3603 } 3604 3605 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3606 rcvd_fis_size, 3607 &accattr, 3608 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3609 DDI_DMA_SLEEP, 3610 NULL, 3611 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3612 &ret_len, 3613 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3614 3615 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3616 "rcvd FIS dma mem alloc fail"); 3617 /* error.. free the dma handle. */ 3618 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3619 return (AHCI_FAILURE); 3620 } 3621 3622 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3623 NULL, 3624 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3625 rcvd_fis_size, 3626 DDI_DMA_CONSISTENT, 3627 DDI_DMA_SLEEP, 3628 NULL, 3629 &rcvd_fis_dma_cookie, 3630 &cookie_count) != DDI_DMA_MAPPED) { 3631 3632 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3633 "rcvd FIS dma handle bind fail"); 3634 /* error.. free the dma handle & free the memory. */ 3635 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3636 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3637 return (AHCI_FAILURE); 3638 } 3639 3640 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 3641 3642 /* Config Port Received FIS Base Address */ 3643 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3644 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 3645 rcvd_fis_dma_cookie.dmac_laddress); 3646 3647 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3648 rcvd_fis_dma_cookie.dmac_laddress); 3649 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3650 rcvd_fis_dma_cookie.dmac_address); 3651 3652 return (AHCI_SUCCESS); 3653 } 3654 3655 /* 3656 * Deallocates the Received FIS Structure 3657 * 3658 * WARNING!!! ahciport_mutex should be acquired before the function 3659 * is called. 3660 */ 3661 static void 3662 ahci_dealloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3663 { 3664 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3665 "ahci_dealloc_rcvd_fis: port %d enter", 3666 ahci_portp->ahciport_port_num); 3667 3668 /* Unbind the cmd list dma handle first. */ 3669 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 3670 3671 /* Then free the underlying memory. */ 3672 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3673 3674 /* Now free the handle itself. */ 3675 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3676 } 3677 3678 /* 3679 * Allocates memory for the Command List, which contains up to 32 entries. 3680 * Each entry contains a command header, which is a 32-byte structure that 3681 * includes the pointer to the command table. 3682 * 3683 * WARNING!!! ahciport_mutex should be acquired before the function 3684 * is called. 3685 */ 3686 static int 3687 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3688 uint8_t port) 3689 { 3690 size_t cmd_list_size; 3691 size_t ret_len; 3692 ddi_dma_cookie_t cmd_list_dma_cookie; 3693 uint_t cookie_count; 3694 uint32_t cap_status; 3695 3696 cmd_list_size = 3697 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 3698 3699 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3700 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3701 3702 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 3703 3704 /* 3705 * If 64-bit addressing is not supported, 3706 * change dma_attr_addr_hi of ahcictl_cmd_list_dma_attr 3707 */ 3708 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3709 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3710 "hba does not support 64-bit addressing"); 3711 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 3712 0xffffffffull; 3713 } 3714 3715 /* allocate cmd list dma handle. */ 3716 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3717 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 3718 DDI_DMA_SLEEP, 3719 NULL, 3720 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 3721 3722 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3723 "cmd list dma handle alloc failed"); 3724 return (AHCI_FAILURE); 3725 } 3726 3727 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 3728 cmd_list_size, 3729 &accattr, 3730 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3731 DDI_DMA_SLEEP, 3732 NULL, 3733 (caddr_t *)&ahci_portp->ahciport_cmd_list, 3734 &ret_len, 3735 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 3736 3737 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3738 "cmd list dma mem alloc fail"); 3739 /* error.. free the dma handle. */ 3740 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3741 return (AHCI_FAILURE); 3742 } 3743 3744 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 3745 NULL, 3746 (caddr_t)ahci_portp->ahciport_cmd_list, 3747 cmd_list_size, 3748 DDI_DMA_CONSISTENT, 3749 DDI_DMA_SLEEP, 3750 NULL, 3751 &cmd_list_dma_cookie, 3752 &cookie_count) != DDI_DMA_MAPPED) { 3753 3754 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3755 "cmd list dma handle bind fail"); 3756 /* error.. free the dma handle & free the memory. */ 3757 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 3758 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3759 return (AHCI_FAILURE); 3760 } 3761 3762 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 3763 3764 /* Config Port Command List Base Address */ 3765 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3766 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 3767 cmd_list_dma_cookie.dmac_laddress); 3768 3769 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3770 cmd_list_dma_cookie.dmac_laddress); 3771 3772 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3773 cmd_list_dma_cookie.dmac_address); 3774 3775 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 3776 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3777 return (AHCI_FAILURE); 3778 } 3779 3780 return (AHCI_SUCCESS); 3781 } 3782 3783 /* 3784 * Deallocates the Command List 3785 * 3786 * WARNING!!! ahciport_mutex should be acquired before the function 3787 * is called. 3788 */ 3789 static void 3790 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3791 { 3792 /* First dealloc command table */ 3793 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 3794 3795 /* Unbind the cmd list dma handle first. */ 3796 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 3797 3798 /* Then free the underlying memory. */ 3799 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 3800 3801 /* Now free the handle itself. */ 3802 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 3803 } 3804 3805 /* 3806 * Allocates memory for all Command Tables, which contains Command FIS, 3807 * ATAPI Command and Physical Region Descriptor Table. 3808 * 3809 * WARNING!!! ahciport_mutex should be acquired before the function 3810 * is called. 3811 */ 3812 static int 3813 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3814 { 3815 size_t ret_len; 3816 ddi_dma_cookie_t cmd_table_dma_cookie; 3817 uint_t cookie_count; 3818 uint32_t cap_status; 3819 int slot; 3820 3821 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3822 "ahci_alloc_cmd_tables: port %d enter", 3823 ahci_portp->ahciport_port_num); 3824 3825 /* Check whether the HBA can access 64-bit data structures */ 3826 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3827 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3828 3829 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 3830 3831 /* 3832 * If 64-bit addressing is not supported, 3833 * change dma_attr_addr_hi of ahcictl_cmd_table_dma_attr 3834 */ 3835 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 3836 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3837 "hba does not support 64-bit addressing"); 3838 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 3839 0xffffffffull; 3840 } 3841 3842 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 3843 /* Allocate cmd table dma handle. */ 3844 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3845 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 3846 DDI_DMA_SLEEP, 3847 NULL, 3848 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 3849 DDI_SUCCESS) { 3850 3851 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3852 "cmd table dma handle alloc failed"); 3853 3854 goto err_out; 3855 } 3856 3857 if (ddi_dma_mem_alloc( 3858 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3859 ahci_cmd_table_size, 3860 &accattr, 3861 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3862 DDI_DMA_SLEEP, 3863 NULL, 3864 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 3865 &ret_len, 3866 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 3867 NULL) { 3868 3869 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3870 "cmd table dma mem alloc fail"); 3871 3872 /* error.. free the dma handle. */ 3873 ddi_dma_free_handle( 3874 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3875 goto err_out; 3876 } 3877 3878 if (ddi_dma_addr_bind_handle( 3879 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3880 NULL, 3881 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 3882 ahci_cmd_table_size, 3883 DDI_DMA_CONSISTENT, 3884 DDI_DMA_SLEEP, 3885 NULL, 3886 &cmd_table_dma_cookie, 3887 &cookie_count) != DDI_DMA_MAPPED) { 3888 3889 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3890 "cmd table dma handle bind fail"); 3891 /* error.. free the dma handle & free the memory. */ 3892 ddi_dma_mem_free( 3893 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3894 ddi_dma_free_handle( 3895 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3896 goto err_out; 3897 } 3898 3899 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 3900 ahci_cmd_table_size); 3901 3902 /* Config Port Command Table Base Address */ 3903 SET_COMMAND_TABLE_BASE_ADDR( 3904 (&ahci_portp->ahciport_cmd_list[slot]), 3905 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 3906 3907 #ifndef __lock_lint 3908 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 3909 (&ahci_portp->ahciport_cmd_list[slot]), 3910 cmd_table_dma_cookie.dmac_laddress >> 32); 3911 #endif /* __lock_lint */ 3912 } 3913 3914 return (AHCI_SUCCESS); 3915 err_out: 3916 3917 for (slot--; slot >= 0; slot--) { 3918 /* Unbind the cmd table dma handle first */ 3919 (void) ddi_dma_unbind_handle( 3920 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3921 3922 /* Then free the underlying memory */ 3923 ddi_dma_mem_free( 3924 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3925 3926 /* Now free the handle itself */ 3927 ddi_dma_free_handle( 3928 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3929 } 3930 3931 return (AHCI_FAILURE); 3932 } 3933 3934 /* 3935 * Deallocates memory for all Command Tables. 3936 * 3937 * WARNING!!! ahciport_mutex should be acquired before the function 3938 * is called. 3939 */ 3940 static void 3941 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 3942 { 3943 int slot; 3944 3945 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3946 "ahci_dealloc_cmd_tables: %d enter", 3947 ahci_portp->ahciport_port_num); 3948 3949 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 3950 /* Unbind the cmd table dma handle first. */ 3951 (void) ddi_dma_unbind_handle( 3952 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3953 3954 /* Then free the underlying memory. */ 3955 ddi_dma_mem_free( 3956 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 3957 3958 /* Now free the handle itself. */ 3959 ddi_dma_free_handle( 3960 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 3961 } 3962 } 3963 3964 /* 3965 * WARNING!!! ahciport_mutex should be acquired before the function 3966 * is called. 3967 */ 3968 static void 3969 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 3970 sata_device_t *sd) 3971 { 3972 sd->satadev_scr.sstatus = 3973 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3974 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 3975 sd->satadev_scr.serror = 3976 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3977 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 3978 sd->satadev_scr.scontrol = 3979 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3980 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 3981 sd->satadev_scr.sactive = 3982 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3983 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 3984 } 3985 3986 /* 3987 * For poll mode, ahci_port_intr will be called to emulate the interrupt 3988 */ 3989 static void 3990 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3991 { 3992 uint32_t port_intr_status; 3993 uint32_t port_intr_enable; 3994 3995 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 3996 "ahci_port_intr enter: port %d", port); 3997 3998 mutex_enter(&ahci_portp->ahciport_mutex); 3999 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4000 /* For SATA_OPMODE_POLLING commands */ 4001 port_intr_enable = 4002 (AHCI_INTR_STATUS_DHRS | 4003 AHCI_INTR_STATUS_PSS | 4004 AHCI_INTR_STATUS_SDBS | 4005 AHCI_INTR_STATUS_UFS | 4006 AHCI_INTR_STATUS_PCS | 4007 AHCI_INTR_STATUS_PRCS | 4008 AHCI_INTR_STATUS_OFS | 4009 AHCI_INTR_STATUS_INFS | 4010 AHCI_INTR_STATUS_IFS | 4011 AHCI_INTR_STATUS_HBDS | 4012 AHCI_INTR_STATUS_HBFS | 4013 AHCI_INTR_STATUS_TFES); 4014 mutex_exit(&ahci_portp->ahciport_mutex); 4015 goto next; 4016 } 4017 mutex_exit(&ahci_portp->ahciport_mutex); 4018 4019 /* 4020 * port_intr_enable indicates that the corresponding interrrupt 4021 * reporting is enabled. 4022 */ 4023 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4024 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4025 next: 4026 /* 4027 * port_intr_stats indicates that the corresponding interrupt 4028 * condition is active. 4029 */ 4030 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4031 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4032 4033 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4034 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4035 "port_intr_enable = 0x%x", 4036 port, port_intr_status, port_intr_enable); 4037 4038 port_intr_status &= port_intr_enable; 4039 4040 /* First clear the port interrupts status */ 4041 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4042 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4043 port_intr_status); 4044 4045 /* Check the completed non-queued commands */ 4046 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4047 AHCI_INTR_STATUS_PSS)) { 4048 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4049 ahci_portp, port, port_intr_status); 4050 } 4051 4052 /* Check the completed queued commands */ 4053 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4054 (void) ahci_intr_set_device_bits(ahci_ctlp, 4055 ahci_portp, port); 4056 } 4057 4058 /* Check the port connect change status interrupt bit */ 4059 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4060 (void) ahci_intr_port_connect_change(ahci_ctlp, 4061 ahci_portp, port); 4062 } 4063 4064 /* Check the device mechanical presence status interrupt bit */ 4065 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4066 (void) ahci_intr_device_mechanical_presence_status( 4067 ahci_ctlp, ahci_portp, port); 4068 } 4069 4070 /* Check the PhyRdy change status interrupt bit */ 4071 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4072 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4073 port); 4074 } 4075 4076 /* 4077 * Check the non-fatal error interrupt bits, there are three 4078 * kinds of non-fatal errors at the time being: 4079 * 4080 * PxIS.UFS - Unknown FIS Error 4081 * PxIS.OFS - Overflow Error 4082 * PxIS.INFS - Interface Non-Fatal Error 4083 * 4084 * For these non-fatal errors, the HBA can continue to operate, 4085 * so the driver just log the error messages. 4086 */ 4087 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4088 AHCI_INTR_STATUS_OFS | 4089 AHCI_INTR_STATUS_INFS)) { 4090 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4091 port, port_intr_status); 4092 } 4093 4094 /* 4095 * Check the fatal error interrupt bits, there are four kinds 4096 * of fatal errors for AHCI controllers: 4097 * 4098 * PxIS.HBFS - Host Bus Fatal Error 4099 * PxIS.HBDS - Host Bus Data Error 4100 * PxIS.IFS - Interface Fatal Error 4101 * PxIS.TFES - Task File Error 4102 * 4103 * The fatal error means the HBA can not recover from it by 4104 * itself, and it will try to abort the transfer, and the software 4105 * must intervene to restart the port. 4106 */ 4107 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4108 AHCI_INTR_STATUS_HBDS | 4109 AHCI_INTR_STATUS_HBFS | 4110 AHCI_INTR_STATUS_TFES)) 4111 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4112 port, port_intr_status); 4113 4114 /* Check the cold port detect interrupt bit */ 4115 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4116 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4117 } 4118 4119 /* Second clear the corresponding bit in IS.IPS */ 4120 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4121 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4122 } 4123 4124 /* 4125 * Interrupt service handler 4126 */ 4127 /* ARGSUSED1 */ 4128 static uint_t 4129 ahci_intr(caddr_t arg1, caddr_t arg2) 4130 { 4131 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4132 ahci_port_t *ahci_portp; 4133 int32_t global_intr_status; 4134 uint8_t port; 4135 4136 /* 4137 * global_intr_status indicates that the corresponding port has 4138 * an interrupt pending. 4139 */ 4140 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4141 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4142 4143 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4144 /* The interrupt is not ours */ 4145 return (DDI_INTR_UNCLAIMED); 4146 } 4147 4148 /* Loop for all the ports */ 4149 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4150 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4151 continue; 4152 } 4153 if (!((0x1 << port) & global_intr_status)) { 4154 continue; 4155 } 4156 4157 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4158 4159 /* Call ahci_port_intr */ 4160 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4161 } 4162 4163 return (DDI_INTR_CLAIMED); 4164 } 4165 4166 /* 4167 * For non-queued commands, when the corresponding bit in the PxCI register 4168 * is cleared, it means the command is completed successfully. And according 4169 * to the HBA state machine, there are three conditions which possibly will 4170 * try to clear the PxCI register bit. 4171 * 1. Receive one D2H Register FIS which is with 'I' bit set 4172 * 2. Update PIO Setup FIS 4173 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4174 * 4175 * Process completed non-queued commands when the interrupt status bit - 4176 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4177 * 4178 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4179 * with the 'I' bit set. And the following commands will send thus 4180 * FIS with 'I' bit set upon the successful completion: 4181 * 1. Non-data commands 4182 * 2. DMA data-in command 4183 * 3. DMA data-out command 4184 * 4. PIO data-out command 4185 * 5. PACKET non-data commands 4186 * 6. PACKET PIO data-in command 4187 * 7. PACKET PIO data-out command 4188 * 8. PACKET DMA data-in command 4189 * 9. PACKET DMA data-out command 4190 * 4191 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4192 * with the 'I' bit set. And the following commands will send this 4193 * FIS upon the successful completion: 4194 * 1. PIO data-in command 4195 */ 4196 static int 4197 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4198 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 4199 { 4200 uint32_t port_cmd_issue = 0; 4201 uint32_t finished_tags; 4202 int finished_slot; 4203 sata_pkt_t *satapkt; 4204 ahci_fis_d2h_register_t *rcvd_fisp; 4205 4206 if (intr_status & AHCI_INTR_STATUS_DHRS) 4207 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4208 "ahci_intr_cmd_cmplt enter: port %d " 4209 "a d2h register fis is received", port); 4210 4211 if (intr_status & AHCI_INTR_STATUS_PSS) 4212 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4213 "ahci_intr_cmd_cmplt enter: port %d " 4214 "a pio setup fis is received", port); 4215 4216 mutex_enter(&ahci_portp->ahciport_mutex); 4217 4218 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4219 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4220 /* 4221 * Spurious interrupt. Nothing to be done. 4222 */ 4223 mutex_exit(&ahci_portp->ahciport_mutex); 4224 return (AHCI_SUCCESS); 4225 } 4226 4227 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4228 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4229 4230 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4231 /* Slot 0 is always used during error recovery */ 4232 finished_tags = 0x1 & ~port_cmd_issue; 4233 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4234 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4235 "retrieval is finished, and finished_tags = 0x%x", 4236 port, finished_tags); 4237 } else { 4238 finished_tags = ahci_portp->ahciport_pending_tags & 4239 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4240 } 4241 4242 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4243 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4244 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4245 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4246 finished_tags); 4247 4248 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4249 (finished_tags == 0x1)) { 4250 satapkt = ahci_portp->ahciport_err_retri_pkt; 4251 ASSERT(satapkt != NULL); 4252 4253 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4254 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4255 "with SATA_PKT_COMPLETED", (void *)satapkt); 4256 4257 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4258 goto out; 4259 } 4260 4261 while (finished_tags) { 4262 finished_slot = ddi_ffs(finished_tags) - 1; 4263 if (finished_slot == -1) { 4264 goto out; 4265 } 4266 4267 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4268 ASSERT(satapkt != NULL); 4269 4270 /* 4271 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4272 * feature, sata_special_regs flag will be set, and the 4273 * driver should copy the status and the other corresponding 4274 * register values in the D2H Register FIS received (It's 4275 * working on Non-data protocol) from the device back to 4276 * the sata_cmd. 4277 * 4278 * For every AHCI port, there is only one Received FIS 4279 * structure, which contains the FISes received from the 4280 * device, So we're trying to copy the content of D2H 4281 * Register FIS in the Received FIS structure back to 4282 * the sata_cmd. 4283 */ 4284 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4285 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4286 ahcirf_d2h_register_fis); 4287 satapkt->satapkt_cmd.satacmd_status_reg = 4288 GET_RFIS_STATUS(rcvd_fisp); 4289 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4290 } 4291 4292 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4293 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4294 "with SATA_PKT_COMPLETED", (void *)satapkt); 4295 4296 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4297 CLEAR_BIT(finished_tags, finished_slot); 4298 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4299 4300 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4301 } 4302 out: 4303 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4304 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4305 ahci_portp->ahciport_pending_tags); 4306 4307 mutex_exit(&ahci_portp->ahciport_mutex); 4308 4309 return (AHCI_SUCCESS); 4310 } 4311 4312 /* 4313 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4314 * with the 'I' bit set and has been copied into system memory. It will 4315 * be sent under the following situations: 4316 * 4317 * 1. NCQ command is completed 4318 * 2. Asynchronous notification 4319 * 4320 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4321 * via the Set Device Bits FIS. When such event is generated, the software 4322 * needs to read PxSACT register and compares the current value to the 4323 * list of commands previously issue by software. ahciport_pending_ncq_tags 4324 * keeps the tags of previously issued commands. 4325 * 4326 * Asynchronous Notification is a feature in SATA II, which allows an 4327 * ATAPI device to send a signal to the host when media is inserted or 4328 * removed and avoids polling the device for media changes. The signal 4329 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4330 * set to '1'. At the moment, it's not supported yet. 4331 */ 4332 static int 4333 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4334 ahci_port_t *ahci_portp, uint8_t port) 4335 { 4336 uint32_t port_sactive; 4337 uint32_t port_cmd_issue; 4338 uint32_t issued_tags; 4339 int issued_slot; 4340 uint32_t finished_tags; 4341 int finished_slot; 4342 sata_pkt_t *satapkt; 4343 4344 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4345 "ahci_intr_set_device_bits enter: port %d", port); 4346 4347 mutex_enter(&ahci_portp->ahciport_mutex); 4348 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4349 mutex_exit(&ahci_portp->ahciport_mutex); 4350 return (AHCI_SUCCESS); 4351 } 4352 4353 /* 4354 * First the handler got which commands are finished by checking 4355 * PxSACT register 4356 */ 4357 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4358 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4359 4360 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4361 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4362 4363 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4364 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4365 "port_sactive = 0x%x", port, 4366 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4367 4368 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4369 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4370 4371 /* 4372 * For NCQ commands, the software can determine which command has 4373 * already been transmitted to the device by checking PxCI register. 4374 */ 4375 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4376 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4377 4378 issued_tags = ahci_portp->ahciport_pending_tags & 4379 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4380 4381 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4382 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4383 "port_cmd_issue = 0x%x", port, 4384 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4385 4386 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4387 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4388 4389 /* 4390 * Clear ahciport_pending_tags bit when the corresponding command 4391 * is already sent down to the device. 4392 */ 4393 while (issued_tags) { 4394 issued_slot = ddi_ffs(issued_tags) - 1; 4395 if (issued_slot == -1) { 4396 goto next; 4397 } 4398 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4399 CLEAR_BIT(issued_tags, issued_slot); 4400 } 4401 4402 next: 4403 while (finished_tags) { 4404 finished_slot = ddi_ffs(finished_tags) - 1; 4405 if (finished_slot == -1) { 4406 goto out; 4407 } 4408 4409 /* The command is certainly transmitted to the device */ 4410 ASSERT(!(ahci_portp->ahciport_pending_tags & 4411 (0x1 << finished_slot))); 4412 4413 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4414 ASSERT(satapkt != NULL); 4415 4416 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4417 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4418 "with SATA_PKT_COMPLETED", (void *)satapkt); 4419 4420 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4421 CLEAR_BIT(finished_tags, finished_slot); 4422 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4423 4424 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4425 } 4426 out: 4427 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4428 "ahci_intr_set_device_bits: port %d " 4429 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4430 port, ahci_portp->ahciport_pending_ncq_tags, 4431 ahci_portp->ahciport_pending_tags); 4432 4433 mutex_exit(&ahci_portp->ahciport_mutex); 4434 4435 return (AHCI_SUCCESS); 4436 } 4437 4438 /* 4439 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4440 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4441 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4442 * indicates a COMINIT signal was received. 4443 * 4444 * Hot plug insertion is detected by reception of a COMINIT signal from the 4445 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4446 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4447 * begin the normal communication negotiation sequence as outlined in the 4448 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4449 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4450 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4451 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4452 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4453 * to handle hot plug insertion. In this interrupt handler, just do nothing 4454 * but print some log message and clear the bit. 4455 */ 4456 static int 4457 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4458 ahci_port_t *ahci_portp, uint8_t port) 4459 { 4460 uint32_t port_serror; 4461 4462 mutex_enter(&ahci_portp->ahciport_mutex); 4463 4464 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4465 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4466 4467 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4468 "ahci_intr_port_connect_change: port %d, " 4469 "port_serror = 0x%x", port, port_serror); 4470 4471 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4472 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4473 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4474 SERROR_EXCHANGED_ERR); 4475 4476 mutex_exit(&ahci_portp->ahciport_mutex); 4477 4478 return (AHCI_SUCCESS); 4479 } 4480 4481 /* 4482 * Hot Plug Operation for platforms that support Mechanical Presence 4483 * Switches. 4484 * 4485 * When set, it indicates that a mechanical presence switch attached to this 4486 * port has been opened or closed, which may lead to a change in the connection 4487 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4488 * are set to '1'. 4489 * 4490 * At the moment, this interrupt is not needed and disabled and we just log 4491 * the debug message. 4492 */ 4493 /* ARGSUSED */ 4494 static int 4495 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4496 ahci_port_t *ahci_portp, uint8_t port) 4497 { 4498 uint32_t cap_status, port_cmd_status; 4499 4500 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4501 "ahci_intr_device_mechanical_presence_status enter, " 4502 "port %d", port); 4503 4504 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4505 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4506 4507 mutex_enter(&ahci_portp->ahciport_mutex); 4508 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4509 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4510 4511 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4512 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4513 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4514 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4515 "the interrupt: cap_status = 0x%x, " 4516 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4517 mutex_exit(&ahci_portp->ahciport_mutex); 4518 4519 return (AHCI_SUCCESS); 4520 } 4521 4522 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4523 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4524 "The mechanical presence switch is open: " 4525 "port %d, port_cmd_status = 0x%x", 4526 port, port_cmd_status); 4527 } else { 4528 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4529 "The mechanical presence switch is close: " 4530 "port %d, port_cmd_status = 0x%x", 4531 port, port_cmd_status); 4532 } 4533 4534 mutex_exit(&ahci_portp->ahciport_mutex); 4535 4536 return (AHCI_SUCCESS); 4537 } 4538 4539 /* 4540 * Native Hot Plug Support. 4541 * 4542 * When set, it indicates that the internal PHYRDY signal changed state. 4543 * This bit reflects the state of PxSERR.DIAG.N. 4544 * 4545 * There are three kinds of conditions to generate this interrupt event: 4546 * 1. a device is inserted 4547 * 2. a device is disconnected 4548 * 3. when the link enters/exits a Partial or Slumber interface power 4549 * management state 4550 * 4551 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4552 * bit may be set due to the link entering the Partial or Slumber power 4553 * management state, rather than due to a hot plug insertion or removal 4554 * event. So far, the power management is disabled, so the driver can 4555 * reliably get removal detection notification via the PxSERR.DIAG.N bit. 4556 */ 4557 static int 4558 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4559 ahci_port_t *ahci_portp, uint8_t port) 4560 { 4561 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4562 sata_device_t sdevice; 4563 int dev_exists_now = 0; 4564 int dev_existed_previously = 0; 4565 4566 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4567 "ahci_intr_phyrdy_change enter, port %d", port); 4568 4569 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4570 mutex_enter(&ahci_portp->ahciport_mutex); 4571 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4572 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4573 SERROR_PHY_RDY_CHG); 4574 mutex_exit(&ahci_portp->ahciport_mutex); 4575 4576 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4577 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4578 (ahci_portp == NULL)) { 4579 /* The whole controller setup is not yet done. */ 4580 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4581 return (AHCI_SUCCESS); 4582 } 4583 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4584 4585 mutex_enter(&ahci_portp->ahciport_mutex); 4586 4587 /* SStatus tells the presence of device. */ 4588 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4589 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4590 4591 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 4592 dev_exists_now = 1; 4593 } 4594 4595 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4596 dev_existed_previously = 1; 4597 } 4598 4599 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 4600 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 4601 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4602 "ahci_intr_phyrdy_change: port %d " 4603 "AHCI_PORT_FLAG_NODEV is cleared", port); 4604 if (dev_exists_now == 0) 4605 dev_existed_previously = 1; 4606 } 4607 4608 bzero((void *)&sdevice, sizeof (sata_device_t)); 4609 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4610 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4611 sdevice.satadev_addr.pmport = 0; 4612 sdevice.satadev_state = SATA_PSTATE_PWRON; 4613 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4614 4615 if (dev_exists_now) { 4616 if (dev_existed_previously) { 4617 /* Things are fine now. The loss was temporary. */ 4618 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4619 "ahci_intr_phyrdy_change port %d " 4620 "device link lost/established", port); 4621 4622 mutex_exit(&ahci_portp->ahciport_mutex); 4623 sata_hba_event_notify( 4624 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4625 &sdevice, 4626 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4627 mutex_enter(&ahci_portp->ahciport_mutex); 4628 4629 } else { 4630 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4631 "ahci_intr_phyrdy_change: port %d " 4632 "device link established", port); 4633 4634 /* A new device has been detected. */ 4635 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 4636 4637 /* Try to start the port */ 4638 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4639 != AHCI_SUCCESS) { 4640 sdevice.satadev_state |= SATA_PSTATE_FAILED; 4641 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4642 "ahci_intr_phyrdy_change: port %d failed " 4643 "at start port", port); 4644 } 4645 4646 /* Clear the max queue depth for inserted device */ 4647 ahci_portp->ahciport_max_ncq_tags = 0; 4648 4649 mutex_exit(&ahci_portp->ahciport_mutex); 4650 sata_hba_event_notify( 4651 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4652 &sdevice, 4653 SATA_EVNT_LINK_ESTABLISHED); 4654 mutex_enter(&ahci_portp->ahciport_mutex); 4655 4656 } 4657 } else { /* No device exists now */ 4658 4659 if (dev_existed_previously) { 4660 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4661 "ahci_intr_phyrdy_change: port %d " 4662 "device link lost", port); 4663 4664 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 4665 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 4666 ahci_portp, port); 4667 4668 /* An existing device is lost. */ 4669 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 4670 4671 mutex_exit(&ahci_portp->ahciport_mutex); 4672 sata_hba_event_notify( 4673 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4674 &sdevice, 4675 SATA_EVNT_LINK_LOST); 4676 mutex_enter(&ahci_portp->ahciport_mutex); 4677 4678 } else { 4679 4680 /* Spurious interrupt */ 4681 AHCIDBG0(AHCIDBG_INTR, ahci_ctlp, 4682 "ahci_intr_phyrdy_change: " 4683 "spurious phy ready interrupt"); 4684 } 4685 } 4686 4687 mutex_exit(&ahci_portp->ahciport_mutex); 4688 4689 return (AHCI_SUCCESS); 4690 } 4691 4692 /* 4693 * PxIS.UFS - Unknown FIS Error 4694 * 4695 * This interrupt event means an unknown FIS was received and has been 4696 * copied into system memory. An unknown FIS is not considered an illegal 4697 * FIS, unless the length received is more than 64 bytes. If an unknown 4698 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 4699 * normal operation. If the unknown FIS is more than 64 bytes, then it 4700 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 4701 * a fatal error. 4702 * 4703 * PxIS.OFS - Overflow Error 4704 * 4705 * Command list overflow is defined as software building a command table 4706 * that has fewer total bytes than the transaction given to the device. 4707 * On device writes, the HBA will run out of data, and on reads, there 4708 * will be no room to put the data. 4709 * 4710 * For an overflow on data read, either PIO or DMA, the HBA will set 4711 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 4712 * non-fatal error when the HBA can continues. Sometimes, it will cause 4713 * a fatal error and need the software to do something. 4714 * 4715 * For an overflow on data write, setting PxIS.OFS is optional for both 4716 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 4717 * software to clean up from this serious error. 4718 * 4719 * PxIS.INFS - Interface Non-Fatal Error 4720 * 4721 * This interrupt event indicates that the HBA encountered an error on 4722 * the Serial ATA interface but was able to continue operation. The kind 4723 * of error usually occurred during a non-Data FIS, and under this condition 4724 * the FIS will be re-transmitted by HBA automatically. 4725 * 4726 * When the FMA is implemented, there should be a stat structure to 4727 * record how many every kind of error happens. 4728 */ 4729 static int 4730 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4731 uint8_t port, uint32_t intr_status) 4732 { 4733 uint32_t port_serror; 4734 #if AHCI_DEBUG 4735 uint32_t port_cmd_status; 4736 uint32_t port_cmd_issue; 4737 uint32_t port_sactive; 4738 int current_slot; 4739 uint32_t current_tags; 4740 sata_pkt_t *satapkt; 4741 #endif 4742 4743 mutex_enter(&ahci_portp->ahciport_mutex); 4744 4745 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4746 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4747 4748 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 4749 "ahci_intr_non_fatal_error: port %d, " 4750 "port_serror = 0x%x", port, port_serror); 4751 4752 ahci_log_serror_message(ahci_ctlp, port, port_serror); 4753 4754 if (intr_status & AHCI_INTR_STATUS_UFS) { 4755 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4756 "ahci port %d has unknown FIS error", port); 4757 4758 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 4759 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4760 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4761 SERROR_FIS_TYPE); 4762 } 4763 4764 #if AHCI_DEBUG 4765 if (intr_status & AHCI_INTR_STATUS_OFS) { 4766 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4767 "ahci port %d has overflow error", port); 4768 } 4769 4770 if (intr_status & AHCI_INTR_STATUS_INFS) { 4771 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4772 "ahci port %d has interface non fatal error", port); 4773 } 4774 4775 /* 4776 * Record the error occurred command's slot. 4777 */ 4778 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 4779 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4780 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4781 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4782 4783 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 4784 AHCI_CMD_STATUS_CCS_SHIFT; 4785 4786 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4787 satapkt = ahci_portp->ahciport_err_retri_pkt; 4788 ASSERT(satapkt != NULL); 4789 ASSERT(current_slot == 0); 4790 } else { 4791 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 4792 } 4793 4794 if (satapkt != NULL) { 4795 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4796 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 4797 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 4798 satapkt->satapkt_cmd.satacmd_cmd_reg); 4799 4800 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4801 "ahci_intr_non_fatal_error: port %d, " 4802 "satapkt 0x%p is being processed when error occurs", 4803 port, (void *)satapkt); 4804 } 4805 } 4806 4807 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4808 /* 4809 * For queued command, list those command which have already 4810 * been transmitted to the device and still not completed. 4811 */ 4812 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4813 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4814 4815 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4816 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4817 4818 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 4819 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 4820 "port_sactive = 0x%x port_cmd_issue = 0x%x", 4821 ahci_portp->ahciport_pending_ncq_tags, 4822 port_sactive, port_cmd_issue); 4823 4824 current_tags = ahci_portp->ahciport_pending_ncq_tags & 4825 port_sactive & ~port_cmd_issue & 4826 AHCI_NCQ_SLOT_MASK(ahci_portp); 4827 4828 while (current_tags) { 4829 current_slot = ddi_ffs(current_tags) - 1; 4830 if (current_slot == -1) { 4831 goto out; 4832 } 4833 4834 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 4835 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 4836 ahci_ctlp, "ahci_intr_non_fatal_error: " 4837 "port %d, satapkt 0x%p is outstanding when " 4838 "error occurs", port, (void *)satapkt); 4839 } 4840 } 4841 out: 4842 #endif 4843 mutex_exit(&ahci_portp->ahciport_mutex); 4844 4845 return (AHCI_SUCCESS); 4846 } 4847 4848 /* 4849 * According to the AHCI spec, the error types include system memory 4850 * errors, interface errors, port multiplier errors, device errors, 4851 * command list overflow, command list underflow, native command 4852 * queuing tag errors and pio data transfer errors. 4853 * 4854 * System memory errors such as target abort, master abort, and parity 4855 * may cause the host to stop, and they are serious errors and needed 4856 * to be recovered with software intervention. When system software 4857 * has given a pointer to the HBA that doesn't exist in physical memory, 4858 * a master/target abort error occurs, and PxIS.HBFS will be set. A 4859 * data error such as CRC or parity occurs, the HBA aborts the transfer 4860 * (if necessary) and PxIS.HBDS will be set. 4861 * 4862 * Interface errors are errors that occur due to electrical issues on 4863 * the interface, or protocol miscommunication between the device and 4864 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 4865 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 4866 * causes PxIS.IFS/PxIS.INFS to be set are 4867 * 1. in PxSERR.ERR, P bit is set to '1' 4868 * 2. in PxSERR.DIAG, C or H bit is set to '1' 4869 * 3. PhyRdy drop unexpectly, N bit is set to '1' 4870 * If the error occurred during a non-data FIS, the FIS must be 4871 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 4872 * the error occurred during a data FIS, the transfer will stop, so 4873 * the error is fatal and PxIS.IFS is set. 4874 * 4875 * When a FIS arrives that updates the taskfile, the HBA checks to see 4876 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 4877 * stops processing any more commands. 4878 * 4879 * Command list overflow is defined as software building a command table 4880 * that has fewer total bytes than the transaction given to the device. 4881 * On device writes, the HBA will run out of data, and on reads, there 4882 * will be no room to put the data. For an overflow on data read, either 4883 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 4884 * For an overflow on data write, setting PxIS.OFS is optional for both 4885 * DMA and PIO, and a COMRESET is required by software to clean up from 4886 * this serious error. 4887 * 4888 * Command list underflow is defined as software building a command 4889 * table that has more total bytes than the transaction given to the 4890 * device. For data writes, both PIO and DMA, the device will detect 4891 * an error and end the transfer. And these errors are most likely going 4892 * to be fatal errors that will cause the port to be restarted. For 4893 * data reads, the HBA updates its PRD byte count, and may be 4894 * able to continue normally, but is not required to. And The HBA is 4895 * not required to detect underflow conditions for native command 4896 * queuing command. 4897 * 4898 * The HBA does not actively check incoming DMA Setup FISes to ensure 4899 * that the PxSACT register bit for that slot is set. Existing error 4900 * mechanisms, such as host bus failure, or bad protocol, are used to 4901 * recover from this case. 4902 * 4903 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 4904 * DATA FIS must be an integral number of Dwords. If the HBA receives 4905 * a request which is not an integral number of Dwords, the HBA 4906 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 4907 * software restarts the port. And the HBA ensures that the size 4908 * of the DATA FIS received during a PIO command matches the size in 4909 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 4910 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 4911 * stop running until software restarts the port. 4912 */ 4913 /* 4914 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 4915 * 4916 * PxIS.IFS indicates that the hba encountered an error on the serial ata 4917 * interface which caused the transfer to stop. 4918 * 4919 * PxIS.HBDS indicates that the hba encountered a data error 4920 * (uncorrectable ecc/parity) when reading from or writing to system memory. 4921 * 4922 * PxIS.HBFS indicates that the hba encountered a host bus error that it 4923 * cannot recover from, such as a bad software pointer. 4924 * 4925 * PxIS.TFES is set whenever the status register is updated by the device 4926 * and the error bit (bit 0) is set. 4927 */ 4928 static int 4929 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 4930 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 4931 { 4932 uint32_t port_cmd_status; 4933 uint32_t port_serror; 4934 uint32_t task_file_status; 4935 int failed_slot; 4936 sata_pkt_t *spkt = NULL; 4937 uint8_t err_byte; 4938 ahci_event_arg_t *args; 4939 4940 mutex_enter(&ahci_portp->ahciport_mutex); 4941 4942 /* 4943 * ahci_intr_phyrdy_change() may have rendered it to 4944 * SATA_DTYPE_NONE. 4945 */ 4946 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 4947 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 4948 "ahci_intr_fatal_error: port %d no device attached, " 4949 "and just return without doing anything", port); 4950 goto out0; 4951 } 4952 4953 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4954 /* 4955 * Read PxCMD.CCS to determine the slot that the HBA 4956 * was processing when the error occurred. 4957 */ 4958 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4959 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4960 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 4961 AHCI_CMD_STATUS_CCS_SHIFT; 4962 4963 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 4964 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4965 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 4966 "fatal error occurred for port %d", spkt, port); 4967 4968 if (intr_status & AHCI_INTR_STATUS_TFES) { 4969 task_file_status = ddi_get32( 4970 ahci_ctlp->ahcictl_ahci_acc_handle, 4971 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 4972 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 4973 "ahci_intr_fatal_error: port %d " 4974 "task_file_status = 0x%x", port, task_file_status); 4975 4976 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 4977 >> AHCI_TFD_ERR_SHIFT; 4978 4979 /* 4980 * Won't emit the error message if it is an IDENTIFY 4981 * DEVICE command sent to an ATAPI device. 4982 */ 4983 if ((spkt != NULL) && 4984 (spkt->satapkt_cmd.satacmd_cmd_reg == 4985 SATAC_ID_DEVICE) && 4986 (err_byte == SATA_ERROR_ABORT)) 4987 goto out1; 4988 4989 /* 4990 * Won't emit the error message if it is an ATAPI PACKET 4991 * command 4992 */ 4993 if ((spkt != NULL) && 4994 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 4995 goto out1; 4996 } 4997 } 4998 4999 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5000 5001 out1: 5002 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5003 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5004 ahci_log_serror_message(ahci_ctlp, port, port_serror); 5005 5006 /* Prepare the argument for the taskq */ 5007 args = ahci_portp->ahciport_event_args; 5008 args->ahciea_ctlp = (void *)ahci_ctlp; 5009 args->ahciea_portp = (void *)ahci_portp; 5010 args->ahciea_event = intr_status; 5011 5012 /* Start the taskq to handle error recovery */ 5013 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 5014 ahci_events_handler, 5015 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5016 cmn_err(CE_WARN, "ahci start taskq for event handler failed"); 5017 } 5018 out0: 5019 mutex_exit(&ahci_portp->ahciport_mutex); 5020 5021 return (AHCI_SUCCESS); 5022 } 5023 5024 /* 5025 * Hot Plug Operation for platforms that support Cold Presence Detect. 5026 * 5027 * When set, a device status has changed as detected by the cold presence 5028 * detect logic. This bit can either be set due to a non-connected port 5029 * receiving a device, or a connected port having its device removed. 5030 * This bit is only valid if the port supports cold presence detect as 5031 * indicated by PxCMD.CPD set to '1'. 5032 * 5033 * At the moment, this interrupt is not needed and disabled and we just 5034 * log the debug message. 5035 */ 5036 /* ARGSUSED */ 5037 static int 5038 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5039 ahci_port_t *ahci_portp, uint8_t port) 5040 { 5041 uint32_t port_cmd_status; 5042 sata_device_t sdevice; 5043 5044 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5045 "ahci_intr_cold_port_detect enter, port %d", port); 5046 5047 mutex_enter(&ahci_portp->ahciport_mutex); 5048 5049 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5050 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5051 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5052 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5053 "port %d does not support cold presence detect, so " 5054 "we just ignore this interrupt", port); 5055 mutex_exit(&ahci_portp->ahciport_mutex); 5056 return (AHCI_SUCCESS); 5057 } 5058 5059 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5060 "port %d device status has changed", port); 5061 5062 bzero((void *)&sdevice, sizeof (sata_device_t)); 5063 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5064 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5065 sdevice.satadev_addr.pmport = 0; 5066 sdevice.satadev_state = SATA_PSTATE_PWRON; 5067 5068 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5069 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5070 "port %d: a device is hot plugged", port); 5071 mutex_exit(&ahci_portp->ahciport_mutex); 5072 sata_hba_event_notify( 5073 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5074 &sdevice, 5075 SATA_EVNT_DEVICE_ATTACHED); 5076 mutex_enter(&ahci_portp->ahciport_mutex); 5077 5078 } else { 5079 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5080 "port %d: a device is hot unplugged", port); 5081 mutex_exit(&ahci_portp->ahciport_mutex); 5082 sata_hba_event_notify( 5083 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5084 &sdevice, 5085 SATA_EVNT_DEVICE_DETACHED); 5086 mutex_enter(&ahci_portp->ahciport_mutex); 5087 } 5088 5089 mutex_exit(&ahci_portp->ahciport_mutex); 5090 5091 return (AHCI_SUCCESS); 5092 } 5093 5094 /* 5095 * Enable the interrupts for a particular port. 5096 * 5097 * WARNING!!! ahciport_mutex should be acquired before the function 5098 * is called. 5099 */ 5100 /* ARGSUSED */ 5101 static void 5102 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, 5103 ahci_port_t *ahci_portp, uint8_t port) 5104 { 5105 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5106 "ahci_enable_port_intrs enter, port %d", port); 5107 5108 /* 5109 * Clear port interrupt status before enabling interrupt 5110 */ 5111 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5112 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5113 AHCI_PORT_INTR_MASK); 5114 5115 /* 5116 * Clear the pending bit from IS.IPS 5117 */ 5118 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5119 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5120 5121 /* 5122 * Enable the following interrupts: 5123 * Device to Host Register FIS Interrupt (DHRS) 5124 * PIO Setup FIS Interrupt (PSS) 5125 * Set Device Bits Interrupt (SDBS) 5126 * Unknown FIS Interrupt (UFS) 5127 * Port Connect Change Status (PCS) 5128 * PhyRdy Change Status (PRCS) 5129 * Overflow Status (OFS) 5130 * Interface Non-fatal Error Status (INFS) 5131 * Interface Fatal Error Status (IFS) 5132 * Host Bus Data Error Status (HBDS) 5133 * Host Bus Fatal Error Status (HBFS) 5134 * Task File Error Status (TFES) 5135 */ 5136 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5137 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5138 (AHCI_INTR_STATUS_DHRS | 5139 AHCI_INTR_STATUS_PSS | 5140 AHCI_INTR_STATUS_SDBS | 5141 AHCI_INTR_STATUS_UFS | 5142 AHCI_INTR_STATUS_DPS | 5143 AHCI_INTR_STATUS_PCS | 5144 AHCI_INTR_STATUS_PRCS | 5145 AHCI_INTR_STATUS_OFS | 5146 AHCI_INTR_STATUS_INFS | 5147 AHCI_INTR_STATUS_IFS | 5148 AHCI_INTR_STATUS_HBDS | 5149 AHCI_INTR_STATUS_HBFS | 5150 AHCI_INTR_STATUS_TFES)); 5151 } 5152 5153 /* 5154 * Enable interrupts for all the ports. 5155 * 5156 * WARNING!!! ahcictl_mutex should be acquired before the function 5157 * is called. 5158 */ 5159 static void 5160 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5161 { 5162 uint32_t ghc_control; 5163 5164 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5165 5166 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5167 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5168 5169 ghc_control |= AHCI_HBA_GHC_IE; 5170 5171 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5172 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5173 } 5174 5175 /* 5176 * Disable interrupts for a particular port. 5177 * 5178 * WARNING!!! ahciport_mutex should be acquired before the function 5179 * is called. 5180 */ 5181 /* ARGSUSED */ 5182 static void 5183 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, 5184 ahci_port_t *ahci_portp, uint8_t port) 5185 { 5186 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5187 "ahci_disable_port_intrs enter, port %d", port); 5188 5189 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5190 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5191 } 5192 5193 /* 5194 * Disable interrupts for the whole HBA. 5195 * 5196 * The global bit is cleared, then all interrupt sources from all 5197 * ports are disabled. 5198 * 5199 * WARNING!!! ahcictl_mutex should be acquired before the function 5200 * is called. 5201 */ 5202 static void 5203 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5204 { 5205 uint32_t ghc_control; 5206 5207 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5208 5209 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5210 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5211 5212 ghc_control &= ~ AHCI_HBA_GHC_IE; 5213 5214 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5215 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5216 } 5217 5218 /* 5219 * Handle INTx and legacy interrupts. 5220 */ 5221 static int 5222 ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 5223 { 5224 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5225 int actual, count = 0; 5226 int x, y, rc, inum = 0; 5227 5228 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5229 "ahci_add_legacy_intrs enter"); 5230 5231 /* get number of interrupts. */ 5232 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 5233 if ((rc != DDI_SUCCESS) || (count == 0)) { 5234 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5235 "ddi_intr_get_nintrs() failed, " 5236 "rc %d count %d\n", rc, count); 5237 return (DDI_FAILURE); 5238 } 5239 5240 /* Allocate an array of interrupt handles. */ 5241 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5242 ahci_ctlp->ahcictl_intr_htable = 5243 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5244 5245 /* call ddi_intr_alloc(). */ 5246 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5247 DDI_INTR_TYPE_FIXED, 5248 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 5249 5250 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5251 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5252 "ddi_intr_alloc() failed, rc %d\n", rc); 5253 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5254 ahci_ctlp->ahcictl_intr_size); 5255 return (DDI_FAILURE); 5256 } 5257 5258 if (actual < count) { 5259 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5260 "Requested: %d, Received: %d", count, actual); 5261 5262 for (x = 0; x < actual; x++) { 5263 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5264 } 5265 5266 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5267 ahci_ctlp->ahcictl_intr_size); 5268 return (DDI_FAILURE); 5269 } 5270 5271 ahci_ctlp->ahcictl_intr_cnt = actual; 5272 5273 /* Get intr priority. */ 5274 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5275 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5276 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5277 "ddi_intr_get_pri() failed"); 5278 5279 for (x = 0; x < actual; x++) { 5280 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5281 } 5282 5283 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5284 ahci_ctlp->ahcictl_intr_size); 5285 return (DDI_FAILURE); 5286 } 5287 5288 /* Test for high level interrupt. */ 5289 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5290 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5291 "ahci_add_legacy_intrs: Hi level intr not supported"); 5292 5293 for (x = 0; x < actual; x++) { 5294 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5295 } 5296 5297 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5298 sizeof (ddi_intr_handle_t)); 5299 5300 return (DDI_FAILURE); 5301 } 5302 5303 /* Call ddi_intr_add_handler(). */ 5304 for (x = 0; x < actual; x++) { 5305 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5306 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5307 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5308 "ddi_intr_add_handler() failed"); 5309 5310 for (y = 0; y < actual; y++) { 5311 (void) ddi_intr_free( 5312 ahci_ctlp->ahcictl_intr_htable[y]); 5313 } 5314 5315 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5316 ahci_ctlp->ahcictl_intr_size); 5317 return (DDI_FAILURE); 5318 } 5319 } 5320 5321 /* Call ddi_intr_enable() for legacy interrupts. */ 5322 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5323 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 5324 } 5325 5326 return (DDI_SUCCESS); 5327 } 5328 5329 /* 5330 * Handle MSI interrupts. 5331 */ 5332 static int 5333 ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 5334 { 5335 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5336 int count, avail, actual; 5337 int x, y, rc, inum = 0; 5338 5339 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5340 "ahci_add_msi_intrs enter"); 5341 5342 /* get number of interrupts. */ 5343 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 5344 if ((rc != DDI_SUCCESS) || (count == 0)) { 5345 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5346 "ddi_intr_get_nintrs() failed, " 5347 "rc %d count %d\n", rc, count); 5348 return (DDI_FAILURE); 5349 } 5350 5351 /* get number of available interrupts. */ 5352 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 5353 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5354 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5355 "ddi_intr_get_navail() failed, " 5356 "rc %d avail %d\n", rc, avail); 5357 return (DDI_FAILURE); 5358 } 5359 5360 if (avail < count) { 5361 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5362 "ddi_intr_get_nvail returned %d, navail() returned %d", 5363 count, avail); 5364 } 5365 5366 /* Allocate an array of interrupt handles. */ 5367 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5368 ahci_ctlp->ahcictl_intr_htable = 5369 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5370 5371 /* call ddi_intr_alloc(). */ 5372 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5373 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5374 5375 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5376 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5377 "ddi_intr_alloc() failed, rc %d\n", rc); 5378 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5379 ahci_ctlp->ahcictl_intr_size); 5380 return (DDI_FAILURE); 5381 } 5382 5383 /* use interrupt count returned */ 5384 if (actual < count) { 5385 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5386 "Requested: %d, Received: %d", count, actual); 5387 } 5388 5389 ahci_ctlp->ahcictl_intr_cnt = actual; 5390 5391 /* 5392 * Get priority for first msi, assume remaining are all the same. 5393 */ 5394 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5395 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5396 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5397 "ddi_intr_get_pri() failed"); 5398 5399 /* Free already allocated intr. */ 5400 for (y = 0; y < actual; y++) { 5401 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5402 } 5403 5404 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5405 ahci_ctlp->ahcictl_intr_size); 5406 return (DDI_FAILURE); 5407 } 5408 5409 /* Test for high level interrupt. */ 5410 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5411 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5412 "ahci_add_msi_intrs: Hi level intr not supported"); 5413 5414 /* Free already allocated intr. */ 5415 for (y = 0; y < actual; y++) { 5416 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5417 } 5418 5419 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5420 sizeof (ddi_intr_handle_t)); 5421 5422 return (DDI_FAILURE); 5423 } 5424 5425 /* Call ddi_intr_add_handler(). */ 5426 for (x = 0; x < actual; x++) { 5427 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5428 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5429 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5430 "ddi_intr_add_handler() failed"); 5431 5432 /* Free already allocated intr. */ 5433 for (y = 0; y < actual; y++) { 5434 (void) ddi_intr_free( 5435 ahci_ctlp->ahcictl_intr_htable[y]); 5436 } 5437 5438 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5439 ahci_ctlp->ahcictl_intr_size); 5440 return (DDI_FAILURE); 5441 } 5442 } 5443 5444 5445 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5446 &ahci_ctlp->ahcictl_intr_cap); 5447 5448 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5449 /* Call ddi_intr_block_enable() for MSI. */ 5450 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5451 ahci_ctlp->ahcictl_intr_cnt); 5452 } else { 5453 /* Call ddi_intr_enable() for MSI non block enable. */ 5454 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5455 (void) ddi_intr_enable( 5456 ahci_ctlp->ahcictl_intr_htable[x]); 5457 } 5458 } 5459 5460 return (DDI_SUCCESS); 5461 } 5462 5463 /* 5464 * Removes the registered interrupts irrespective of whether they 5465 * were legacy or MSI. 5466 * 5467 * WARNING!!! The controller interrupts must be disabled before calling 5468 * this routine. 5469 */ 5470 static void 5471 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5472 { 5473 int x; 5474 5475 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5476 5477 /* Disable all interrupts. */ 5478 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5479 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5480 /* Call ddi_intr_block_disable(). */ 5481 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5482 ahci_ctlp->ahcictl_intr_cnt); 5483 } else { 5484 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5485 (void) ddi_intr_disable( 5486 ahci_ctlp->ahcictl_intr_htable[x]); 5487 } 5488 } 5489 5490 /* Call ddi_intr_remove_handler(). */ 5491 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5492 (void) ddi_intr_remove_handler( 5493 ahci_ctlp->ahcictl_intr_htable[x]); 5494 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5495 } 5496 5497 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5498 } 5499 5500 /* 5501 * This routine tries to put port into P:NotRunning state by clearing 5502 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5503 * and PxCMD.CR to '0'. 5504 * 5505 * WARNING!!! ahciport_mutex should be acquired before the function 5506 * is called. 5507 */ 5508 /* ARGSUSED */ 5509 static int 5510 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5511 ahci_port_t *ahci_portp, uint8_t port) 5512 { 5513 uint32_t port_cmd_status; 5514 int loop_count; 5515 5516 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5517 "ahci_put_port_into_notrunning_state enter: port %d", port); 5518 5519 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5520 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5521 5522 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5523 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5524 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5525 5526 /* Wait until PxCMD.CR is cleared */ 5527 loop_count = 0; 5528 do { 5529 port_cmd_status = 5530 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5531 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5532 5533 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5534 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5535 "clearing port %d CMD.CR timeout, " 5536 "port_cmd_status = 0x%x", port, 5537 port_cmd_status); 5538 /* 5539 * We are effectively timing out after 0.5 sec. 5540 * This value is specified in AHCI spec. 5541 */ 5542 break; 5543 } 5544 5545 /* Wait for 10 millisec */ 5546 #ifndef __lock_lint 5547 delay(AHCI_10MS_TICKS); 5548 #endif /* __lock_lint */ 5549 5550 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5551 5552 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5553 5554 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5555 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5556 "ahci_put_port_into_notrunning_state: failed to clear " 5557 "PxCMD.CR to '0' after loop count: %d, and " 5558 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5559 return (AHCI_FAILURE); 5560 } else { 5561 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5562 "ahci_put_port_into_notrunning_state: succeeded to clear " 5563 "PxCMD.CR to '0' after loop count: %d, and " 5564 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5565 return (AHCI_SUCCESS); 5566 } 5567 } 5568 5569 /* 5570 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5571 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5572 * stable state, then set PxCMD.ST to '1' to start the port directly. 5573 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5574 * COMRESET to the device to put it in an idle state. 5575 * 5576 * The fifth argument returns whether the port reset is involved during 5577 * the process. 5578 * 5579 * The routine will be called under six scenarios: 5580 * 1. Initialize the port 5581 * 2. To abort the packet(s) 5582 * 3. To reset the port 5583 * 4. To activate the port 5584 * 5. Fatal error recovery 5585 * 6. To abort the timeout packet(s) 5586 * 5587 * WARNING!!! ahciport_mutex should be acquired before the function 5588 * is called. And ahciport_mutex will be released before the reset 5589 * event is reported to sata module by calling sata_hba_event_notify, 5590 * and then be acquired again later. 5591 * 5592 * NOTES!!! During this procedure, PxSERR register will be cleared, and 5593 * according to the spec, the clearance of three bits will also clear 5594 * three interrupt status bits. 5595 * 1. PxSERR.DIAG.F will clear PxIS.UFS 5596 * 2. PxSERR.DIAG.X will clear PxIS.PCS 5597 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 5598 * 5599 * Among these three interrupt events, the driver needs to take care of 5600 * PxIS.PRCS, which is the hot plug event. When the driver found out 5601 * a device was unplugged, it will call the interrupt handler. 5602 */ 5603 static int 5604 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5605 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 5606 { 5607 uint32_t port_sstatus; 5608 uint32_t task_file_status; 5609 sata_device_t sdevice; 5610 int rval; 5611 int dev_exists_begin = 0; 5612 int dev_exists_end = 0; 5613 5614 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5615 "ahci_restart_port_wait_till_ready: port %d enter", port); 5616 5617 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) 5618 dev_exists_begin = 1; 5619 5620 /* First clear PxCMD.ST */ 5621 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 5622 port); 5623 if (rval != AHCI_SUCCESS) 5624 /* 5625 * If PxCMD.CR does not clear within a reasonable time, it 5626 * may assume the interface is in a hung condition and may 5627 * continue with issuing the port reset. 5628 */ 5629 goto reset; 5630 5631 /* Then clear PxSERR */ 5632 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5633 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5634 AHCI_SERROR_CLEAR_ALL); 5635 5636 /* Then get PxTFD */ 5637 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5638 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5639 5640 /* 5641 * Check whether the device is in a stable status, if yes, 5642 * then start the port directly. However for ahci_tran_dport_reset, 5643 * we may have to perform a port reset. 5644 */ 5645 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 5646 !(flag & AHCI_PORT_RESET)) 5647 goto out; 5648 5649 reset: 5650 /* 5651 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 5652 * a COMRESET to the device 5653 */ 5654 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 5655 if (rval != AHCI_SUCCESS) 5656 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5657 "ahci_restart_port_wait_till_ready: port %d failed", 5658 port); 5659 5660 if (reset_flag != NULL) 5661 *reset_flag = 1; 5662 5663 /* Indicate to the framework that a reset has happened. */ 5664 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 5665 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 5666 /* Set the reset in progress flag */ 5667 ahci_portp->ahciport_reset_in_progress = 1; 5668 5669 bzero((void *)&sdevice, sizeof (sata_device_t)); 5670 sdevice.satadev_addr.cport = 5671 ahci_ctlp->ahcictl_port_to_cport[port]; 5672 sdevice.satadev_addr.pmport = 0; 5673 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5674 5675 sdevice.satadev_state = SATA_DSTATE_RESET | 5676 SATA_DSTATE_PWR_ACTIVE; 5677 if (ahci_ctlp->ahcictl_sata_hba_tran) { 5678 mutex_exit(&ahci_portp->ahciport_mutex); 5679 sata_hba_event_notify( 5680 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5681 &sdevice, 5682 SATA_EVNT_DEVICE_RESET); 5683 mutex_enter(&ahci_portp->ahciport_mutex); 5684 } 5685 5686 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5687 "port %d sending event up: SATA_EVNT_RESET", port); 5688 } else { 5689 ahci_portp->ahciport_reset_in_progress = 0; 5690 } 5691 5692 out: 5693 /* Start the port */ 5694 if (!(flag & AHCI_PORT_INIT)) { 5695 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 5696 } 5697 5698 /* SStatus tells the presence of device. */ 5699 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5700 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 5701 5702 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 5703 dev_exists_end = 1; 5704 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 5705 } 5706 5707 /* Check whether a hot plug event happened */ 5708 if (dev_exists_begin == 1 && dev_exists_end == 0) { 5709 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5710 "ahci_restart_port_wait_till_ready: port %d " 5711 "device is removed", port); 5712 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 5713 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5714 "ahci_restart_port_wait_till_ready: port %d " 5715 "AHCI_PORT_FLAG_NODEV flag is set", port); 5716 mutex_exit(&ahci_portp->ahciport_mutex); 5717 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 5718 mutex_enter(&ahci_portp->ahciport_mutex); 5719 } 5720 5721 return (rval); 5722 } 5723 5724 /* 5725 * This routine may be called under four scenarios: 5726 * a) do the recovery from fatal error 5727 * b) or we need to timeout some commands 5728 * c) or we need to abort some commands 5729 * d) or we need reset device/port/controller 5730 * 5731 * In all these scenarios, we need to send any pending unfinished 5732 * commands up to sata framework. 5733 * 5734 * WARNING!!! ahciport_mutex should be acquired before the function is called. 5735 */ 5736 static void 5737 ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 5738 ahci_port_t *ahci_portp, 5739 uint8_t port, 5740 uint32_t slot_status, 5741 uint32_t failed_tags, 5742 uint32_t timeout_tags, 5743 uint32_t aborted_tags, 5744 uint32_t reset_tags) 5745 { 5746 uint32_t finished_tags = 0; 5747 uint32_t unfinished_tags = 0; 5748 int tmp_slot; 5749 sata_pkt_t *satapkt; 5750 int ncq_cmd_in_progress = 0; 5751 int err_retri_cmd_in_progress = 0; 5752 5753 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 5754 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 5755 port, slot_status); 5756 5757 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 5758 "ahci_mop_commands: failed_tags: 0x%x, " 5759 "timeout_tags: 0x%x aborted_tags: 0x%x, " 5760 "reset_tags: 0x%x", failed_tags, 5761 timeout_tags, aborted_tags, reset_tags); 5762 5763 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5764 finished_tags = ahci_portp->ahciport_pending_tags & 5765 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 5766 5767 unfinished_tags = slot_status & 5768 AHCI_SLOT_MASK(ahci_ctlp) & 5769 ~failed_tags & 5770 ~aborted_tags & 5771 ~reset_tags & 5772 ~timeout_tags; 5773 } 5774 5775 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5776 ncq_cmd_in_progress = 1; 5777 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 5778 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 5779 5780 unfinished_tags = slot_status & 5781 AHCI_NCQ_SLOT_MASK(ahci_portp) & 5782 ~failed_tags & 5783 ~aborted_tags & 5784 ~reset_tags & 5785 ~timeout_tags; 5786 } 5787 5788 /* 5789 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is set, 5790 * it means REQUEST SENSE or READ LOG EXT command doesn't complete 5791 * successfully due to one of the following three conditions: 5792 * 5793 * 1. Fatal error - failed_tags includes its slot 5794 * 2. Timed out - timeout_tags includes its slot 5795 * 3. Aborted when hot unplug - aborted_tags includes its slot 5796 * 5797 * Please note that the command is always sent down in Slot 0 5798 */ 5799 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5800 err_retri_cmd_in_progress = 1; 5801 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 5802 "ahci_mop_commands is called for port %d while " 5803 "REQUEST SENSE or READ LOG EXT for error retrieval " 5804 "is being executed", port); 5805 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 5806 ASSERT(slot_status == 0x1); 5807 } 5808 5809 /* Send up finished packets with SATA_PKT_COMPLETED */ 5810 while (finished_tags) { 5811 tmp_slot = ddi_ffs(finished_tags) - 1; 5812 if (tmp_slot == -1) { 5813 break; 5814 } 5815 5816 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5817 ASSERT(satapkt != NULL); 5818 5819 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 5820 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 5821 (void *)satapkt); 5822 5823 /* 5824 * Cannot fetch the return register content since the port 5825 * was restarted, so the corresponding tag will be set to 5826 * aborted tags. 5827 */ 5828 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 5829 CLEAR_BIT(finished_tags, tmp_slot); 5830 aborted_tags |= tmp_slot; 5831 continue; 5832 } 5833 5834 if (ncq_cmd_in_progress) 5835 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5836 tmp_slot); 5837 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5838 CLEAR_BIT(finished_tags, tmp_slot); 5839 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5840 5841 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 5842 } 5843 5844 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 5845 while (failed_tags) { 5846 if (err_retri_cmd_in_progress) { 5847 satapkt = ahci_portp->ahciport_err_retri_pkt; 5848 ASSERT(satapkt != NULL); 5849 ASSERT(failed_tags == 0x1); 5850 5851 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5852 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 5853 (void *)satapkt); 5854 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 5855 break; 5856 } 5857 5858 tmp_slot = ddi_ffs(failed_tags) - 1; 5859 if (tmp_slot == -1) { 5860 break; 5861 } 5862 5863 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5864 ASSERT(satapkt != NULL); 5865 5866 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5867 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 5868 (void *)satapkt); 5869 5870 if (ncq_cmd_in_progress) 5871 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5872 tmp_slot); 5873 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5874 CLEAR_BIT(failed_tags, tmp_slot); 5875 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5876 5877 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 5878 } 5879 5880 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 5881 while (timeout_tags) { 5882 if (err_retri_cmd_in_progress) { 5883 satapkt = ahci_portp->ahciport_err_retri_pkt; 5884 ASSERT(satapkt != NULL); 5885 ASSERT(timeout_tags == 0x1); 5886 5887 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5888 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 5889 (void *)satapkt); 5890 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 5891 break; 5892 } 5893 5894 tmp_slot = ddi_ffs(timeout_tags) - 1; 5895 if (tmp_slot == -1) { 5896 break; 5897 } 5898 5899 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5900 ASSERT(satapkt != NULL); 5901 5902 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5903 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 5904 (void *)satapkt); 5905 5906 if (ncq_cmd_in_progress) 5907 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5908 tmp_slot); 5909 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5910 CLEAR_BIT(timeout_tags, tmp_slot); 5911 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5912 5913 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 5914 } 5915 5916 /* Send up aborted packets with SATA_PKT_ABORTED */ 5917 while (aborted_tags) { 5918 if (err_retri_cmd_in_progress) { 5919 satapkt = ahci_portp->ahciport_err_retri_pkt; 5920 ASSERT(satapkt != NULL); 5921 ASSERT(aborted_tags == 0x1); 5922 5923 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5924 "sending up pkt 0x%p with SATA_PKT_ABORTED", 5925 (void *)satapkt); 5926 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 5927 break; 5928 } 5929 5930 tmp_slot = ddi_ffs(aborted_tags) - 1; 5931 if (tmp_slot == -1) { 5932 break; 5933 } 5934 5935 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5936 ASSERT(satapkt != NULL); 5937 5938 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5939 "sending up pkt 0x%p with SATA_PKT_ABORTED", 5940 (void *)satapkt); 5941 5942 if (ncq_cmd_in_progress) 5943 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5944 tmp_slot); 5945 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5946 CLEAR_BIT(aborted_tags, tmp_slot); 5947 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5948 5949 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 5950 } 5951 5952 /* Send up reset packets with SATA_PKT_RESET. */ 5953 while (reset_tags) { 5954 tmp_slot = ddi_ffs(reset_tags) - 1; 5955 if (tmp_slot == -1) { 5956 break; 5957 } 5958 5959 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5960 ASSERT(satapkt != NULL); 5961 5962 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5963 "sending up pkt 0x%p with SATA_PKT_RESET", 5964 (void *)satapkt); 5965 5966 if (ncq_cmd_in_progress) 5967 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5968 tmp_slot); 5969 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5970 CLEAR_BIT(reset_tags, tmp_slot); 5971 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5972 5973 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 5974 } 5975 5976 /* Send up unfinished packets with SATA_PKT_RESET */ 5977 while (unfinished_tags) { 5978 tmp_slot = ddi_ffs(unfinished_tags) - 1; 5979 if (tmp_slot == -1) { 5980 break; 5981 } 5982 5983 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 5984 ASSERT(satapkt != NULL); 5985 5986 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 5987 "sending up pkt 0x%p with SATA_PKT_RESET", 5988 (void *)satapkt); 5989 5990 if (ncq_cmd_in_progress) 5991 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 5992 tmp_slot); 5993 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 5994 CLEAR_BIT(unfinished_tags, tmp_slot); 5995 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 5996 5997 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 5998 } 5999 6000 ahci_portp->ahciport_mop_in_progress--; 6001 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6002 6003 if (ahci_portp->ahciport_mop_in_progress == 0) 6004 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6005 } 6006 6007 /* 6008 * This routine is going to first request a READ LOG EXT sata pkt from sata 6009 * module, and then deliver it to the HBA to get the ncq failure context. 6010 * The return value is the exactly failed tags. 6011 */ 6012 static uint32_t 6013 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6014 uint8_t port) 6015 { 6016 sata_device_t sdevice; 6017 sata_pkt_t *rdlog_spkt, *spkt; 6018 ddi_dma_handle_t buf_dma_handle; 6019 int loop_count; 6020 int rval; 6021 int failed_slot; 6022 uint32_t failed_tags = 0; 6023 struct sata_ncq_error_recovery_page *ncq_err_page; 6024 6025 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6026 "ahci_get_rdlogext_data enter: port %d", port); 6027 6028 /* Prepare the sdevice data */ 6029 bzero((void *)&sdevice, sizeof (sata_device_t)); 6030 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6031 6032 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6033 sdevice.satadev_addr.pmport = 0; 6034 6035 /* 6036 * Call the sata hba interface to get a rdlog spkt 6037 */ 6038 loop_count = 0; 6039 loop: 6040 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6041 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6042 if (rdlog_spkt == NULL) { 6043 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6044 /* Sleep for a while */ 6045 delay(AHCI_10MS_TICKS); 6046 goto loop; 6047 } 6048 /* Timed out after 1s */ 6049 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6050 "failed to get rdlog spkt for port %d", port); 6051 return (failed_tags); 6052 } 6053 6054 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6055 6056 /* 6057 * This flag is used to handle the specific error recovery when the 6058 * READ LOG EXT command gets a failure (fatal error or time-out). 6059 */ 6060 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6061 6062 /* 6063 * This start is not supposed to fail because after port is restarted, 6064 * the whole command list is empty. 6065 */ 6066 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6067 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6068 ahci_portp->ahciport_err_retri_pkt = NULL; 6069 6070 /* Remove the flag after READ LOG EXT command is completed */ 6071 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6072 6073 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6074 /* Update the request log data */ 6075 buf_dma_handle = *(ddi_dma_handle_t *) 6076 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6077 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6078 DDI_DMA_SYNC_FORKERNEL); 6079 if (rval == DDI_SUCCESS) { 6080 ncq_err_page = 6081 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6082 satapkt_cmd.satacmd_bp->b_un.b_addr; 6083 6084 /* Get the failed tag */ 6085 failed_slot = ncq_err_page->ncq_tag; 6086 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6087 "ahci_get_rdlogext_data: port %d " 6088 "failed slot %d", port, failed_slot); 6089 if (failed_slot & NQ) { 6090 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6091 "the failed slot is not a valid tag"); 6092 goto out; 6093 } 6094 6095 failed_slot &= NCQ_TAG_MASK; 6096 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6097 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6098 "ahci_get_rdlogext_data: failed spkt 0x%p", 6099 (void *)spkt); 6100 if (spkt == NULL) { 6101 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6102 "the failed slot spkt is NULL") 6103 goto out; 6104 } 6105 6106 failed_tags = 0x1 << failed_slot; 6107 6108 /* Fill out the error context */ 6109 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6110 ncq_err_page); 6111 ahci_update_sata_registers(ahci_ctlp, port, 6112 &spkt->satapkt_device); 6113 } 6114 } else { 6115 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6116 "ahci_get_rdlogext_data: port %d READ LOG EXT command " 6117 "did not successfully complete", port); 6118 } 6119 out: 6120 sata_free_error_retrieval_pkt(rdlog_spkt); 6121 6122 return (failed_tags); 6123 } 6124 6125 /* 6126 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6127 * module, and then deliver it to the HBA to get the sense data and copy 6128 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6129 * SENSE sata pkt later. 6130 */ 6131 static void 6132 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6133 uint8_t port, sata_pkt_t *spkt) 6134 { 6135 sata_device_t sdevice; 6136 sata_pkt_t *rs_spkt; 6137 sata_cmd_t *sata_cmd; 6138 ddi_dma_handle_t buf_dma_handle; 6139 int loop_count; 6140 #if AHCI_DEBUG 6141 struct scsi_extended_sense *rqsense; 6142 #endif 6143 6144 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6145 "ahci_get_rqsense_data enter: port %d", port); 6146 6147 /* Prepare the sdevice data */ 6148 bzero((void *)&sdevice, sizeof (sata_device_t)); 6149 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6150 6151 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6152 sdevice.satadev_addr.pmport = 0; 6153 6154 sata_cmd = &spkt->satapkt_cmd; 6155 6156 /* 6157 * Call the sata hba interface to get a rs spkt 6158 */ 6159 loop_count = 0; 6160 loop: 6161 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6162 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6163 if (rs_spkt == NULL) { 6164 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6165 /* Sleep for a while */ 6166 delay(AHCI_10MS_TICKS); 6167 goto loop; 6168 6169 } 6170 /* Timed out after 1s */ 6171 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6172 "failed to get rs spkt for port %d", port); 6173 return; 6174 } 6175 6176 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6177 6178 /* 6179 * This flag is used to handle the specific error recovery when the 6180 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6181 */ 6182 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6183 6184 /* 6185 * This start is not supposed to fail because after port is restarted, 6186 * the whole command list is empty. 6187 */ 6188 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6189 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6190 ahci_portp->ahciport_err_retri_pkt = NULL; 6191 6192 /* Remove the flag after REQUEST SENSE command is completed */ 6193 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6194 6195 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6196 /* Update the request sense data */ 6197 buf_dma_handle = *(ddi_dma_handle_t *) 6198 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6199 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6200 DDI_DMA_SYNC_FORKERNEL); 6201 /* Copy the request sense data */ 6202 bcopy(rs_spkt-> 6203 satapkt_cmd.satacmd_bp->b_un.b_addr, 6204 &sata_cmd->satacmd_rqsense, 6205 SATA_ATAPI_MIN_RQSENSE_LEN); 6206 #if AHCI_DEBUG 6207 rqsense = (struct scsi_extended_sense *) 6208 sata_cmd->satacmd_rqsense; 6209 6210 /* Dump the sense data */ 6211 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6212 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6213 "Sense data for satapkt %p ATAPI cmd 0x%x", 6214 spkt, sata_cmd->satacmd_acdb[0]); 6215 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6216 " es_code 0x%x es_class 0x%x " 6217 "es_key 0x%x es_add_code 0x%x " 6218 "es_qual_code 0x%x", 6219 rqsense->es_code, rqsense->es_class, 6220 rqsense->es_key, rqsense->es_add_code, 6221 rqsense->es_qual_code); 6222 #endif 6223 } else { 6224 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6225 "ahci_get_rqsense_data: port %d REQUEST SENSE command " 6226 "did not successfully complete", port); 6227 } 6228 6229 sata_free_error_retrieval_pkt(rs_spkt); 6230 } 6231 6232 /* 6233 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6234 * the port must be restarted. When the HBA detects thus error, it may try 6235 * to abort a transfer. And if the transfer was aborted, the device is 6236 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6237 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6238 * that the device is in a stable status and transfers may be restarted without 6239 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6240 * then the software will send the COMRESET to do the port reset. 6241 * 6242 * Software should perform the appropriate error recovery actions based on 6243 * whether non-queued commands were being issued or natived command queuing 6244 * commands were being issued. 6245 * 6246 * And software will complete the command that had the error with error mark 6247 * to higher level software. 6248 * 6249 * Fatal errors include the following: 6250 * PxIS.IFS - Interface Fatal Error Status 6251 * PxIS.HBDS - Host Bus Data Error Status 6252 * PxIS.HBFS - Host Bus Fatal Error Status 6253 * PxIS.TFES - Task File Error Status 6254 * 6255 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6256 */ 6257 static void 6258 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6259 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6260 { 6261 uint32_t port_cmd_status; 6262 uint32_t slot_status = 0; 6263 uint32_t failed_tags = 0; 6264 int failed_slot; 6265 int reset_flag = 0; 6266 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6267 sata_cmd_t *sata_cmd = NULL; 6268 sata_pkt_t *spkt = NULL; 6269 6270 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6271 "ahci_fatal_error_recovery_handler enter: port %d", port); 6272 6273 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6274 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6275 6276 /* Read PxCI to see which commands are still outstanding */ 6277 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6278 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6279 6280 /* 6281 * Read PxCMD.CCS to determine the slot that the HBA 6282 * was processing when the error occurred. 6283 */ 6284 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6285 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6286 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6287 AHCI_CMD_STATUS_CCS_SHIFT; 6288 6289 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6290 spkt = ahci_portp->ahciport_err_retri_pkt; 6291 ASSERT(spkt != NULL); 6292 } else { 6293 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6294 if (spkt == NULL) { 6295 /* May happen when interface errors occur? */ 6296 goto next; 6297 } 6298 } 6299 6300 sata_cmd = &spkt->satapkt_cmd; 6301 6302 /* Fill out the status and error registers for PxIS.TFES */ 6303 if (intr_status & AHCI_INTR_STATUS_TFES) { 6304 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6305 ahcirf_d2h_register_fis); 6306 6307 /* Copy the error context back to the sata_cmd */ 6308 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6309 } 6310 6311 /* The failed command must be one of the outstanding commands */ 6312 failed_tags = 0x1 << failed_slot; 6313 ASSERT(failed_tags & slot_status); 6314 6315 /* Update the sata registers, especially PxSERR register */ 6316 ahci_update_sata_registers(ahci_ctlp, port, 6317 &spkt->satapkt_device); 6318 6319 } 6320 6321 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6322 /* Read PxSACT to see which commands are still outstanding */ 6323 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6324 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6325 } 6326 next: 6327 6328 #if AHCI_DEBUG 6329 /* 6330 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6331 * set, it means a fatal error happened after REQUEST SENSE command 6332 * or READ LOG EXT command is delivered to the HBA during the error 6333 * recovery process. At this time, the only outstanding command is 6334 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6335 */ 6336 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6337 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6338 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6339 "command or READ LOG EXT command for error data retrieval " 6340 "failed", port); 6341 ASSERT(slot_status == 0x1); 6342 ASSERT(failed_slot == 0x1); 6343 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6344 SCMD_REQUEST_SENSE || 6345 spkt->satapkt_cmd.satacmd_cmd_reg == 6346 SATAC_READ_LOG_EXT); 6347 } 6348 #endif 6349 6350 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6351 ahci_portp->ahciport_mop_in_progress++; 6352 6353 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6354 port, NULL, &reset_flag); 6355 6356 /* 6357 * Won't retrieve error information: 6358 * 1. Port reset was involved to recover 6359 * 2. Device is gone 6360 * 3. IDENTIFY DEVICE command sent to ATAPI device 6361 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6362 */ 6363 if (reset_flag || 6364 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6365 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6366 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6367 goto out; 6368 6369 /* 6370 * Deliver READ LOG EXT to gather information about the error when 6371 * a COMRESET has not been performed as part of the error recovery 6372 * during NCQ command processing. 6373 */ 6374 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6375 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6376 ahci_portp, port); 6377 goto out; 6378 } 6379 6380 /* 6381 * Deliver REQUEST SENSE for ATAPI command to gather information about 6382 * the error when a COMRESET has not been performed as part of the 6383 * error recovery. 6384 */ 6385 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPICD) 6386 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6387 out: 6388 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6389 "ahci_fatal_error_recovery_handler: port %d interface error " 6390 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6391 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6392 port, slot_status, ahci_portp->ahciport_pending_tags, 6393 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6394 6395 ahci_mop_commands(ahci_ctlp, 6396 ahci_portp, 6397 port, 6398 slot_status, 6399 failed_tags, /* failed tags */ 6400 0, /* timeout tags */ 6401 0, /* aborted tags */ 6402 0); /* reset tags */ 6403 } 6404 6405 /* 6406 * Handle events - fatal error recovery 6407 */ 6408 static void 6409 ahci_events_handler(void *args) 6410 { 6411 ahci_event_arg_t *ahci_event_arg; 6412 ahci_ctl_t *ahci_ctlp; 6413 ahci_port_t *ahci_portp; 6414 uint32_t event; 6415 uint8_t port; 6416 6417 ahci_event_arg = (ahci_event_arg_t *)args; 6418 6419 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6420 ahci_portp = ahci_event_arg->ahciea_portp; 6421 event = ahci_event_arg->ahciea_event; 6422 port = ahci_portp->ahciport_port_num; 6423 6424 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6425 "ahci_events_handler enter: port %d intr_status = 0x%x", 6426 port, event); 6427 6428 mutex_enter(&ahci_portp->ahciport_mutex); 6429 6430 /* 6431 * ahci_intr_phyrdy_change() may have rendered it to 6432 * SATA_DTYPE_NONE. 6433 */ 6434 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6435 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6436 "ahci_events_handler: port %d no device attached, " 6437 "and just return without doing anything", port); 6438 goto out; 6439 } 6440 6441 if (event & (AHCI_INTR_STATUS_IFS | 6442 AHCI_INTR_STATUS_HBDS | 6443 AHCI_INTR_STATUS_HBFS | 6444 AHCI_INTR_STATUS_TFES)) 6445 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6446 port, event); 6447 6448 out: 6449 mutex_exit(&ahci_portp->ahciport_mutex); 6450 } 6451 6452 /* 6453 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6454 * detect there are some commands which are timed out. 6455 */ 6456 static void 6457 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6458 uint8_t port, uint32_t tmp_timeout_tags) 6459 { 6460 uint32_t slot_status = 0; 6461 uint32_t finished_tags = 0; 6462 uint32_t timeout_tags = 0; 6463 6464 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6465 "ahci_timeout_pkts enter: port %d", port); 6466 6467 mutex_enter(&ahci_portp->ahciport_mutex); 6468 6469 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6470 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6471 /* Read PxCI to see which commands are still outstanding */ 6472 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6473 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6474 } 6475 6476 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6477 /* Read PxSACT to see which commands are still outstanding */ 6478 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6479 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6480 } 6481 6482 #if AHCI_DEBUG 6483 /* 6484 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6485 * set, it means a fatal error happened after REQUEST SENSE command 6486 * or READ LOG EXT command is delivered to the HBA during the error 6487 * recovery process. At this time, the only outstanding command is 6488 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6489 */ 6490 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6491 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 6492 "ahci_timeout_pkts called while REQUEST SENSE " 6493 "command or READ LOG EXT command for error recovery " 6494 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 6495 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 6496 tmp_timeout_tags, slot_status, 6497 ahci_portp->ahciport_pending_tags, 6498 ahci_portp->ahciport_pending_ncq_tags); 6499 ASSERT(slot_status == 0x1); 6500 } 6501 #endif 6502 6503 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6504 ahci_portp->ahciport_mop_in_progress++; 6505 6506 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6507 port, NULL, NULL); 6508 6509 /* 6510 * Re-identify timeout tags because some previously checked commands 6511 * could already complete. 6512 */ 6513 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6514 finished_tags = ahci_portp->ahciport_pending_tags & 6515 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6516 timeout_tags = tmp_timeout_tags & ~finished_tags; 6517 6518 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 6519 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6520 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 6521 "pending_tags = 0x%x ", 6522 port, finished_tags, timeout_tags, 6523 slot_status, ahci_portp->ahciport_pending_tags); 6524 } 6525 6526 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6527 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6528 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6529 timeout_tags = tmp_timeout_tags & ~finished_tags; 6530 6531 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 6532 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6533 "timeout_tags = 0x%x, port_sactive = 0x%x, " 6534 "pending_ncq_tags = 0x%x ", 6535 port, finished_tags, timeout_tags, 6536 slot_status, ahci_portp->ahciport_pending_ncq_tags); 6537 } 6538 6539 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6540 timeout_tags = tmp_timeout_tags; 6541 } 6542 6543 ahci_mop_commands(ahci_ctlp, 6544 ahci_portp, 6545 port, 6546 slot_status, 6547 0, /* failed tags */ 6548 timeout_tags, /* timeout tags */ 6549 0, /* aborted tags */ 6550 0); /* reset tags */ 6551 6552 mutex_exit(&ahci_portp->ahciport_mutex); 6553 } 6554 6555 /* 6556 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 6557 * for long time. 6558 */ 6559 static void 6560 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 6561 { 6562 ahci_port_t *ahci_portp; 6563 sata_pkt_t *spkt; 6564 uint32_t pending_tags; 6565 uint32_t timeout_tags; 6566 uint32_t port_cmd_status; 6567 uint32_t port_sactive; 6568 uint8_t port; 6569 int tmp_slot; 6570 int current_slot; 6571 uint32_t current_tags; 6572 /* max number of cycles this packet should survive */ 6573 int max_life_cycles; 6574 6575 /* how many cycles this packet survived so far */ 6576 int watched_cycles; 6577 6578 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6579 6580 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6581 "ahci_watchdog_handler entered"); 6582 6583 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6584 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6585 continue; 6586 } 6587 6588 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6589 6590 mutex_enter(&ahci_portp->ahciport_mutex); 6591 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6592 mutex_exit(&ahci_portp->ahciport_mutex); 6593 continue; 6594 } 6595 6596 /* Skip the check for those ports in error recovery */ 6597 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 6598 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 6599 mutex_exit(&ahci_portp->ahciport_mutex); 6600 continue; 6601 } 6602 6603 pending_tags = 0; 6604 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6605 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6606 6607 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6608 current_slot = 0; 6609 pending_tags = 0x1; 6610 } 6611 6612 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6613 current_slot = 6614 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6615 AHCI_CMD_STATUS_CCS_SHIFT; 6616 pending_tags = ahci_portp->ahciport_pending_tags; 6617 } 6618 6619 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6620 port_sactive = ddi_get32( 6621 ahci_ctlp->ahcictl_ahci_acc_handle, 6622 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6623 current_tags = port_sactive & 6624 ~port_cmd_status & 6625 AHCI_NCQ_SLOT_MASK(ahci_portp); 6626 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 6627 } 6628 6629 timeout_tags = 0; 6630 while (pending_tags) { 6631 tmp_slot = ddi_ffs(pending_tags) - 1; 6632 if (tmp_slot == -1) { 6633 break; 6634 } 6635 6636 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6637 spkt = ahci_portp->ahciport_err_retri_pkt; 6638 else 6639 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6640 6641 if ((spkt != NULL) && spkt->satapkt_time && 6642 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 6643 /* 6644 * We are overloading satapkt_hba_driver_private 6645 * with watched_cycle count. 6646 * 6647 * If a packet has survived for more than it's 6648 * max life cycles, it is a candidate for time 6649 * out. 6650 */ 6651 watched_cycles = (int)(intptr_t) 6652 spkt->satapkt_hba_driver_private; 6653 watched_cycles++; 6654 max_life_cycles = (spkt->satapkt_time + 6655 ahci_watchdog_timeout - 1) / 6656 ahci_watchdog_timeout; 6657 6658 spkt->satapkt_hba_driver_private = 6659 (void *)(intptr_t)watched_cycles; 6660 6661 if (watched_cycles <= max_life_cycles) 6662 goto next; 6663 6664 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6665 "the current slot is %d", current_slot); 6666 /* 6667 * We need to check whether the HBA has 6668 * begun to execute the command, if not, 6669 * then re-set the timer of the command. 6670 */ 6671 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 6672 (tmp_slot != current_slot) || 6673 NCQ_CMD_IN_PROGRESS(ahci_portp) && 6674 ((0x1 << tmp_slot) & current_tags)) { 6675 spkt->satapkt_hba_driver_private = 6676 (void *)(intptr_t)0; 6677 } else { 6678 timeout_tags |= (0x1 << tmp_slot); 6679 cmn_err(CE_NOTE, "!ahci watchdog: " 6680 "port %d satapkt 0x%p timed out\n", 6681 port, (void *)spkt); 6682 } 6683 } 6684 next: 6685 CLEAR_BIT(pending_tags, tmp_slot); 6686 } 6687 6688 if (timeout_tags) { 6689 mutex_exit(&ahci_portp->ahciport_mutex); 6690 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6691 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 6692 port, timeout_tags); 6693 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6694 mutex_enter(&ahci_portp->ahciport_mutex); 6695 } 6696 6697 mutex_exit(&ahci_portp->ahciport_mutex); 6698 } 6699 6700 /* Re-install the watchdog timeout handler */ 6701 if (ahci_ctlp->ahcictl_timeout_id != 0) { 6702 ahci_ctlp->ahcictl_timeout_id = 6703 timeout((void (*)(void *))ahci_watchdog_handler, 6704 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 6705 } 6706 6707 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6708 } 6709 6710 /* 6711 * Fill the error context into sata_cmd for non-queued command error. 6712 */ 6713 static void 6714 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 6715 { 6716 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 6717 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 6718 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 6719 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 6720 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 6721 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 6722 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 6723 6724 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 6725 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 6726 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 6727 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 6728 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 6729 } 6730 } 6731 6732 /* 6733 * Fill the ncq error page into sata_cmd for queued command error. 6734 */ 6735 static void 6736 ahci_copy_ncq_err_page(sata_cmd_t *scmd, 6737 struct sata_ncq_error_recovery_page *ncq_err_page) 6738 { 6739 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 6740 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 6741 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 6742 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 6743 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 6744 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 6745 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 6746 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 6747 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 6748 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 6749 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 6750 } 6751 6752 /* 6753 * Put the respective register value to sata_cmd_t for satacmd_flags. 6754 */ 6755 static void 6756 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 6757 { 6758 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 6759 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 6760 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 6761 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 6762 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 6763 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 6764 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 6765 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 6766 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 6767 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 6768 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 6769 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 6770 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 6771 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 6772 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 6773 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 6774 if (scmd->satacmd_flags.sata_copy_out_device_reg) 6775 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 6776 if (scmd->satacmd_flags.sata_copy_out_error_reg) 6777 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 6778 } 6779 6780 static void 6781 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 6782 uint32_t intr_status) 6783 { 6784 #ifndef __lock_lint 6785 _NOTE(ARGUNUSED(ahci_ctlp)) 6786 #endif 6787 6788 if (intr_status & AHCI_INTR_STATUS_IFS) 6789 cmn_err(CE_NOTE, "!ahci port %d has interface fatal " 6790 "error", port); 6791 6792 if (intr_status & AHCI_INTR_STATUS_HBDS) 6793 cmn_err(CE_NOTE, "!ahci port %d has bus data error", port); 6794 6795 if (intr_status & AHCI_INTR_STATUS_HBFS) 6796 cmn_err(CE_NOTE, "!ahci port %d has bus fatal error", port); 6797 6798 if (intr_status & AHCI_INTR_STATUS_TFES) 6799 cmn_err(CE_NOTE, "!ahci port %d has task file error", port); 6800 6801 cmn_err(CE_NOTE, "!ahci port %d is trying to do error " 6802 "recovery", port); 6803 } 6804 6805 /* 6806 * Dump the serror message to the log. 6807 */ 6808 static void 6809 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 6810 uint32_t port_serror) 6811 { 6812 #ifndef __lock_lint 6813 _NOTE(ARGUNUSED(ahci_ctlp)) 6814 #endif 6815 char *err_str; 6816 6817 if (port_serror & SERROR_DATA_ERR_FIXED) { 6818 err_str = "Recovered Data Integrity Error (I)"; 6819 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6820 "command error: port: %d, error: %s", 6821 port, err_str); 6822 } 6823 6824 if (port_serror & SERROR_COMM_ERR_FIXED) { 6825 err_str = "Recovered Communication Error (M)"; 6826 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6827 "command error: port: %d, error: %s", 6828 port, err_str); 6829 } 6830 6831 if (port_serror & SERROR_DATA_ERR) { 6832 err_str = "Transient Data Integrity Error (T)"; 6833 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6834 "command error: port: %d, error: %s", 6835 port, err_str); 6836 } 6837 6838 if (port_serror & SERROR_PERSISTENT_ERR) { 6839 err_str = 6840 "Persistent Communication or Data Integrity Error (C)"; 6841 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6842 "command error: port: %d, error: %s", 6843 port, err_str); 6844 } 6845 6846 if (port_serror & SERROR_PROTOCOL_ERR) { 6847 err_str = "Protocol Error (P)"; 6848 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6849 "command error: port: %d, error: %s", 6850 port, err_str); 6851 } 6852 6853 if (port_serror & SERROR_INT_ERR) { 6854 err_str = "Internal Error (E)"; 6855 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6856 "command error: port: %d, error: %s", 6857 port, err_str); 6858 } 6859 6860 if (port_serror & SERROR_PHY_RDY_CHG) { 6861 err_str = "PhyRdy Change (N)"; 6862 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6863 "command error: port: %d, error: %s", 6864 port, err_str); 6865 } 6866 6867 if (port_serror & SERROR_PHY_INT_ERR) { 6868 err_str = "Phy Internal Error (I)"; 6869 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6870 "command error: port: %d, error: %s", 6871 port, err_str); 6872 } 6873 6874 if (port_serror & SERROR_COMM_WAKE) { 6875 err_str = "Comm Wake (W)"; 6876 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6877 "command error: port: %d, error: %s", 6878 port, err_str); 6879 } 6880 6881 if (port_serror & SERROR_10B_TO_8B_ERR) { 6882 err_str = "10B to 8B Decode Error (B)"; 6883 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6884 "command error: port: %d, error: %s", 6885 port, err_str); 6886 } 6887 6888 if (port_serror & SERROR_DISPARITY_ERR) { 6889 err_str = "Disparity Error (D)"; 6890 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6891 "command error: port: %d, error: %s", 6892 port, err_str); 6893 } 6894 6895 if (port_serror & SERROR_CRC_ERR) { 6896 err_str = "CRC Error (C)"; 6897 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6898 "command error: port: %d, error: %s", 6899 port, err_str); 6900 } 6901 6902 if (port_serror & SERROR_HANDSHAKE_ERR) { 6903 err_str = "Handshake Error (H)"; 6904 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6905 "command error: port: %d, error: %s", 6906 port, err_str); 6907 } 6908 6909 if (port_serror & SERROR_LINK_SEQ_ERR) { 6910 err_str = "Link Sequence Error (S)"; 6911 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6912 "command error: port: %d, error: %s", 6913 port, err_str); 6914 } 6915 6916 if (port_serror & SERROR_TRANS_ERR) { 6917 err_str = "Transport state transition error (T)"; 6918 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6919 "command error: port: %d, error: %s", 6920 port, err_str); 6921 } 6922 6923 if (port_serror & SERROR_FIS_TYPE) { 6924 err_str = "Unknown FIS Type (F)"; 6925 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6926 "command error: port: %d, error: %s", 6927 port, err_str); 6928 } 6929 6930 if (port_serror & SERROR_EXCHANGED_ERR) { 6931 err_str = "Exchanged (X)"; 6932 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6933 "command error: port: %d, error: %s", 6934 port, err_str); 6935 } 6936 } 6937 6938 /* 6939 * This routine is to calculate the total number of ports implemented 6940 * by the HBA. 6941 */ 6942 static int 6943 ahci_get_num_implemented_ports(uint32_t ports_implemented) 6944 { 6945 uint8_t i; 6946 int num = 0; 6947 6948 for (i = 0; i < AHCI_MAX_PORTS; i++) { 6949 if (((uint32_t)0x1 << i) & ports_implemented) 6950 num++; 6951 } 6952 6953 return (num); 6954 } 6955 6956 static void 6957 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 6958 { 6959 va_list ap; 6960 6961 mutex_enter(&ahci_log_mutex); 6962 6963 va_start(ap, fmt); 6964 if (ahci_ctlp) { 6965 (void) sprintf(ahci_log_buf, "%s-[%d]:", 6966 ddi_get_name(ahci_ctlp->ahcictl_dip), 6967 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 6968 } else { 6969 (void) sprintf(ahci_log_buf, "ahci:"); 6970 } 6971 6972 (void) vsprintf(ahci_log_buf, fmt, ap); 6973 va_end(ap); 6974 6975 cmn_err(level, "%s", ahci_log_buf); 6976 6977 mutex_exit(&ahci_log_mutex); 6978 } 6979