1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 25 */ 26 27 /* 28 * rtls -- REALTEK 8139-serials PCI Fast Ethernet Driver, Depends on the 29 * Generic LAN Driver utility functions in /kernel/misc/mac 30 * 31 * This product is covered by one or more of the following patents: 32 * US5,307,459, US5,434,872, US5,732,094, US6,570,884, US6,115,776, and 33 * US6,327,625. 34 * 35 * Currently supports: 36 * RTL8139 37 */ 38 39 #include <sys/types.h> 40 #include <sys/debug.h> 41 #include <sys/errno.h> 42 43 #include <sys/stropts.h> 44 #include <sys/stream.h> 45 #include <sys/kmem.h> 46 #include <sys/conf.h> 47 #include <sys/ddi.h> 48 #include <sys/devops.h> 49 #include <sys/ksynch.h> 50 #include <sys/stat.h> 51 #include <sys/conf.h> 52 #include <sys/modctl.h> 53 #include <sys/dlpi.h> 54 #include <sys/ethernet.h> 55 #include <sys/vlan.h> 56 #include <sys/strsun.h> 57 #include <sys/pci.h> 58 #include <sys/sunddi.h> 59 #include <sys/mii.h> 60 #include <sys/miiregs.h> 61 #include <sys/mac_provider.h> 62 #include <sys/mac_ether.h> 63 64 #include "rtls.h" 65 66 /* 67 * Declarations and Module Linkage 68 */ 69 70 /* 71 * This is the string displayed by modinfo, etc. 72 */ 73 static char rtls_ident[] = "RealTek 8139 Ethernet driver"; 74 75 #ifdef RTLS_DEBUG 76 int rtls_debug = 0; 77 #endif 78 79 /* 80 * Required system entry points 81 */ 82 static int rtls_attach(dev_info_t *, ddi_attach_cmd_t); 83 static int rtls_detach(dev_info_t *, ddi_detach_cmd_t); 84 static int rtls_quiesce(dev_info_t *); 85 86 /* 87 * Required driver entry points for MAC 88 */ 89 static int rtls_m_start(void *); 90 static void rtls_m_stop(void *); 91 static int rtls_m_unicst(void *, const uint8_t *); 92 static int rtls_m_multicst(void *, boolean_t, const uint8_t *); 93 static int rtls_m_promisc(void *, boolean_t); 94 static mblk_t *rtls_m_tx(void *, mblk_t *); 95 static int rtls_m_getprop(void *, const char *, mac_prop_id_t, uint_t, 96 void *); 97 static int rtls_m_setprop(void *, const char *, mac_prop_id_t, uint_t, 98 const void *); 99 static void rtls_m_propinfo(void *, const char *, mac_prop_id_t, 100 mac_prop_info_handle_t); 101 static int rtls_m_stat(void *, uint_t, uint64_t *); 102 103 static uint_t rtls_intr(caddr_t); 104 105 /* 106 * MII entry points 107 */ 108 static uint16_t rtls_mii_read(void *, uint8_t, uint8_t); 109 static void rtls_mii_write(void *, uint8_t, uint8_t, uint16_t); 110 static void rtls_mii_notify(void *, link_state_t); 111 112 /* 113 * Internal functions used by the above entry points 114 */ 115 static int rtls_chip_reset(rtls_t *, boolean_t); 116 static void rtls_chip_init(rtls_t *); 117 static void rtls_chip_stop(rtls_t *rtlsp); 118 static void rtls_chip_start(rtls_t *rtlsp); 119 static void rtls_chip_restart(rtls_t *rtlsp); 120 static void rtls_get_mac_addr(rtls_t *, uint8_t *); 121 static void rtls_set_mac_addr(rtls_t *, const uint8_t *); 122 static uint_t rtls_hash_index(const uint8_t *); 123 static boolean_t rtls_send(rtls_t *, mblk_t *); 124 static void rtls_receive(rtls_t *); 125 126 /* 127 * Buffer Management Routines 128 */ 129 static int rtls_alloc_bufs(rtls_t *); 130 static void rtls_free_bufs(rtls_t *); 131 static int rtls_alloc_dma_mem(rtls_t *, size_t, ddi_device_acc_attr_t *, 132 uint_t, dma_area_t *); 133 static void rtls_free_dma_mem(dma_area_t *); 134 135 #ifdef RTLS_DEBUG 136 static void rtls_reg_print(rtls_t *); /* debug routine */ 137 #endif 138 139 #define RTLS_DRIVER_NAME "rtls" 140 141 /* 142 * Used for buffers allocated by ddi_dma_mem_alloc() 143 */ 144 static ddi_dma_attr_t dma_attr = { 145 DMA_ATTR_V0, /* dma_attr version */ 146 0, /* dma_attr_addr_lo */ 147 (uint_t)0xFFFFFFFF, /* dma_attr_addr_hi */ 148 0x7FFFFFFF, /* dma_attr_count_max */ 149 4, /* dma_attr_align */ 150 0x3F, /* dma_attr_burstsizes */ 151 1, /* dma_attr_minxfer */ 152 (uint_t)0xFFFFFFFF, /* dma_attr_maxxfer */ 153 (uint_t)0xFFFFFFFF, /* dma_attr_seg */ 154 1, /* dma_attr_sgllen */ 155 1, /* dma_attr_granular */ 156 0, /* dma_attr_flags */ 157 }; 158 159 /* 160 * PIO access attributes for registers 161 */ 162 static ddi_device_acc_attr_t rtls_reg_accattr = { 163 DDI_DEVICE_ATTR_V0, 164 DDI_STRUCTURE_LE_ACC, 165 DDI_STRICTORDER_ACC 166 }; 167 168 /* 169 * DMA access attributes for data 170 */ 171 static ddi_device_acc_attr_t rtls_buf_accattr = { 172 DDI_DEVICE_ATTR_V0, 173 DDI_NEVERSWAP_ACC, 174 DDI_STRICTORDER_ACC 175 }; 176 177 uchar_t rtls_broadcastaddr[] = { 178 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 179 }; 180 181 static mac_callbacks_t rtls_m_callbacks = { 182 MC_PROPERTIES, 183 rtls_m_stat, 184 rtls_m_start, 185 rtls_m_stop, 186 rtls_m_promisc, 187 rtls_m_multicst, 188 rtls_m_unicst, 189 rtls_m_tx, 190 NULL, 191 NULL, /* mc_ioctl */ 192 NULL, /* mc_getcapab */ 193 NULL, /* mc_open */ 194 NULL, /* mc_close */ 195 rtls_m_setprop, 196 rtls_m_getprop, 197 rtls_m_propinfo 198 }; 199 200 static mii_ops_t rtls_mii_ops = { 201 MII_OPS_VERSION, 202 rtls_mii_read, 203 rtls_mii_write, 204 rtls_mii_notify, /* notify */ 205 NULL, /* reset */ 206 }; 207 208 DDI_DEFINE_STREAM_OPS(rtls_dev_ops, nulldev, nulldev, rtls_attach, rtls_detach, 209 nodev, NULL, D_MP, NULL, rtls_quiesce); 210 211 /* 212 * Standard module linkage initialization for a MAC driver 213 */ 214 static struct modldrv rtls_modldrv = { 215 &mod_driverops, /* type of module. This one is a driver */ 216 rtls_ident, /* short description */ 217 &rtls_dev_ops /* driver specific ops */ 218 }; 219 220 static struct modlinkage modlinkage = { 221 MODREV_1, { (void *)&rtls_modldrv, NULL } 222 }; 223 224 /* 225 * ========== RealTek chip register access Routines ========== 226 */ 227 static uint8_t 228 rtls_reg_get8(rtls_t *rtlsp, uint32_t reg) 229 { 230 uint8_t *addr; 231 232 addr = REG8(rtlsp->io_reg, reg); 233 return (ddi_get8(rtlsp->io_handle, addr)); 234 } 235 236 static uint16_t 237 rtls_reg_get16(rtls_t *rtlsp, uint32_t reg) 238 { 239 uint16_t *addr; 240 241 addr = REG16(rtlsp->io_reg, reg); 242 return (ddi_get16(rtlsp->io_handle, addr)); 243 } 244 245 static uint32_t 246 rtls_reg_get32(rtls_t *rtlsp, uint32_t reg) 247 { 248 uint32_t *addr; 249 250 addr = REG32(rtlsp->io_reg, reg); 251 return (ddi_get32(rtlsp->io_handle, addr)); 252 } 253 254 static void 255 rtls_reg_set8(rtls_t *rtlsp, uint32_t reg, uint8_t value) 256 { 257 uint8_t *addr; 258 259 addr = REG8(rtlsp->io_reg, reg); 260 ddi_put8(rtlsp->io_handle, addr, value); 261 } 262 263 static void 264 rtls_reg_set16(rtls_t *rtlsp, uint32_t reg, uint16_t value) 265 { 266 uint16_t *addr; 267 268 addr = REG16(rtlsp->io_reg, reg); 269 ddi_put16(rtlsp->io_handle, addr, value); 270 } 271 272 static void 273 rtls_reg_set32(rtls_t *rtlsp, uint32_t reg, uint32_t value) 274 { 275 uint32_t *addr; 276 277 addr = REG32(rtlsp->io_reg, reg); 278 ddi_put32(rtlsp->io_handle, addr, value); 279 } 280 281 /* 282 * ========== Module Loading Entry Points ========== 283 */ 284 int 285 _init(void) 286 { 287 int rv; 288 289 mac_init_ops(&rtls_dev_ops, RTLS_DRIVER_NAME); 290 if ((rv = mod_install(&modlinkage)) != DDI_SUCCESS) { 291 mac_fini_ops(&rtls_dev_ops); 292 } 293 return (rv); 294 } 295 296 int 297 _fini(void) 298 { 299 int rv; 300 301 if ((rv = mod_remove(&modlinkage)) == DDI_SUCCESS) { 302 mac_fini_ops(&rtls_dev_ops); 303 } 304 return (rv); 305 } 306 307 int 308 _info(struct modinfo *modinfop) 309 { 310 return (mod_info(&modlinkage, modinfop)); 311 } 312 313 314 /* 315 * ========== DDI Entry Points ========== 316 */ 317 318 /* 319 * attach(9E) -- Attach a device to the system 320 * 321 * Called once for each board successfully probed. 322 */ 323 static int 324 rtls_attach(dev_info_t *devinfo, ddi_attach_cmd_t cmd) 325 { 326 rtls_t *rtlsp; /* Our private device info */ 327 ddi_acc_handle_t pci_handle; 328 uint16_t pci_commond; 329 uint16_t vendorid; 330 uint16_t deviceid; 331 uint32_t device; 332 mac_register_t *macp; 333 int err; 334 335 switch (cmd) { 336 case DDI_ATTACH: 337 break; 338 case DDI_RESUME: 339 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 340 return (DDI_FAILURE); 341 } 342 mutex_enter(&rtlsp->rtls_io_lock); 343 mutex_enter(&rtlsp->rtls_rx_lock); 344 mutex_enter(&rtlsp->rtls_tx_lock); 345 /* 346 * Turn on Master Enable (DMA) and IO Enable bits. 347 * Enable PCI Memory Space accesses 348 * Disable Memory Write/Invalidate 349 */ 350 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 351 mutex_exit(&rtlsp->rtls_tx_lock); 352 mutex_exit(&rtlsp->rtls_rx_lock); 353 mutex_exit(&rtlsp->rtls_io_lock); 354 return (DDI_FAILURE); 355 } 356 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 357 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 358 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 359 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 360 pci_config_teardown(&pci_handle); 361 362 rtls_chip_restart(rtlsp); 363 rtlsp->chip_error = B_FALSE; 364 rtlsp->tx_retry = 0; 365 rtlsp->rtls_suspended = B_FALSE; 366 mutex_exit(&rtlsp->rtls_tx_lock); 367 mutex_exit(&rtlsp->rtls_rx_lock); 368 mutex_exit(&rtlsp->rtls_io_lock); 369 370 mii_resume(rtlsp->mii); 371 372 mac_tx_update(rtlsp->mh); 373 return (DDI_SUCCESS); 374 default: 375 return (DDI_FAILURE); 376 } 377 378 /* 379 * we don't support high level interrupts in the driver 380 */ 381 if (ddi_intr_hilevel(devinfo, 0) != 0) { 382 cmn_err(CE_WARN, "unsupported high level interrupt"); 383 return (DDI_FAILURE); 384 } 385 386 /* 387 * Get handle to access pci configuration space 388 */ 389 if (pci_config_setup(devinfo, &pci_handle) != DDI_SUCCESS) { 390 cmn_err(CE_WARN, "pci_config_setup fail."); 391 return (DDI_FAILURE); 392 } 393 394 /* 395 * Make sure we support this particular vendor/device 396 */ 397 vendorid = pci_config_get16(pci_handle, PCI_CONF_VENID); 398 deviceid = pci_config_get16(pci_handle, PCI_CONF_DEVID); 399 device = vendorid; 400 device = (device << 16) | deviceid; /* combine two id together */ 401 402 /* 403 * See if we support this device 404 * We do not return for wrong device id. It's user risk. 405 */ 406 switch (device) { 407 default: 408 cmn_err(CE_WARN, 409 "RTLS doesn't support this device: " 410 "vendorID = 0x%x, deviceID = 0x%x", 411 vendorid, deviceid); 412 break; 413 case RTLS_SUPPORT_DEVICE_1: 414 case RTLS_SUPPORT_DEVICE_2: 415 case RTLS_SUPPORT_DEVICE_3: 416 case RTLS_SUPPORT_DEVICE_4: 417 break; 418 } 419 420 /* 421 * Turn on Master Enable (DMA) and IO Enable bits. 422 * Enable PCI Memory Space accesses 423 * Disable Memory Write/Invalidate 424 */ 425 pci_commond = pci_config_get16(pci_handle, PCI_CONF_COMM); 426 pci_commond &= ~PCI_COMM_MEMWR_INVAL; 427 pci_commond |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 428 pci_config_put32(pci_handle, PCI_CONF_COMM, pci_commond); 429 430 /* 431 * Free handle to access pci configuration space 432 */ 433 pci_config_teardown(&pci_handle); 434 435 rtlsp = kmem_zalloc(sizeof (rtls_t), KM_SLEEP); 436 437 ddi_set_driver_private(devinfo, rtlsp); 438 rtlsp->devinfo = devinfo; 439 rtlsp->instance = ddi_get_instance(devinfo); 440 441 /* 442 * Map operating register 443 */ 444 err = ddi_regs_map_setup(devinfo, 1, &rtlsp->io_reg, 445 (offset_t)0, 0, &rtls_reg_accattr, &rtlsp->io_handle); 446 if (err != DDI_SUCCESS) { 447 kmem_free((caddr_t)rtlsp, sizeof (rtls_t)); 448 cmn_err(CE_WARN, "ddi_regs_map_setup fail."); 449 return (DDI_FAILURE); 450 } 451 452 /* 453 * Allocate the TX and RX descriptors/buffers 454 */ 455 if (rtls_alloc_bufs(rtlsp) == DDI_FAILURE) { 456 cmn_err(CE_WARN, "DMA buffer allocation fail."); 457 goto fail; 458 } 459 460 /* 461 * Reset the chip 462 */ 463 err = rtls_chip_reset(rtlsp, B_FALSE); 464 if (err != DDI_SUCCESS) 465 goto fail; 466 467 /* 468 * Init rtls_t structure 469 */ 470 rtls_get_mac_addr(rtlsp, rtlsp->netaddr); 471 472 /* 473 * Add the interrupt handler 474 * 475 * This will prevent receiving interrupts before device is ready, as 476 * we are initializing device after setting the interrupts. So we 477 * will not get our interrupt handler invoked by OS while our device 478 * is still coming up or timer routines will not start till we are 479 * all set to process... 480 */ 481 482 if (ddi_add_intr(devinfo, 0, &rtlsp->iblk, NULL, rtls_intr, 483 (caddr_t)rtlsp) != DDI_SUCCESS) { 484 cmn_err(CE_WARN, "ddi_add_intr fail."); 485 goto late_fail; 486 } 487 488 if ((rtlsp->mii = mii_alloc(rtlsp, devinfo, &rtls_mii_ops)) == NULL) { 489 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 490 goto late_fail; 491 } 492 /* 493 * Note: Some models of 8139 can support pause, but we have 494 * not implemented support for it at this time. This might be 495 * an interesting feature to add later. 496 */ 497 mii_set_pauseable(rtlsp->mii, B_FALSE, B_FALSE); 498 499 if ((macp = mac_alloc(MAC_VERSION)) == NULL) { 500 cmn_err(CE_WARN, "mac_alloc fail."); 501 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 502 goto late_fail; 503 } 504 505 /* 506 * Init mutex 507 */ 508 mutex_init(&rtlsp->rtls_io_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 509 mutex_init(&rtlsp->rtls_tx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 510 mutex_init(&rtlsp->rtls_rx_lock, NULL, MUTEX_DRIVER, rtlsp->iblk); 511 512 /* 513 * Initialize pointers to device specific functions which will be 514 * used by the generic layer. 515 */ 516 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 517 macp->m_driver = rtlsp; 518 macp->m_dip = devinfo; 519 macp->m_src_addr = rtlsp->netaddr; 520 macp->m_callbacks = &rtls_m_callbacks; 521 macp->m_min_sdu = 0; 522 macp->m_max_sdu = ETHERMTU; 523 macp->m_margin = VLAN_TAGSZ; 524 525 if (mac_register(macp, &rtlsp->mh) != 0) { 526 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 527 mutex_destroy(&rtlsp->rtls_io_lock); 528 mutex_destroy(&rtlsp->rtls_tx_lock); 529 mutex_destroy(&rtlsp->rtls_rx_lock); 530 goto late_fail; 531 } 532 533 mac_free(macp); 534 535 return (DDI_SUCCESS); 536 537 late_fail: 538 if (macp) 539 mac_free(macp); 540 if (rtlsp->mii) 541 mii_free(rtlsp->mii); 542 543 fail: 544 ddi_regs_map_free(&rtlsp->io_handle); 545 rtls_free_bufs(rtlsp); 546 kmem_free(rtlsp, sizeof (rtls_t)); 547 548 return (DDI_FAILURE); 549 } 550 551 /* 552 * detach(9E) -- Detach a device from the system 553 */ 554 static int 555 rtls_detach(dev_info_t *devinfo, ddi_detach_cmd_t cmd) 556 { 557 rtls_t *rtlsp; /* our private device info */ 558 559 /* 560 * Get the driver private structure 561 */ 562 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 563 return (DDI_FAILURE); 564 } 565 566 switch (cmd) { 567 case DDI_DETACH: 568 break; 569 570 case DDI_SUSPEND: 571 mii_suspend(rtlsp->mii); 572 573 mutex_enter(&rtlsp->rtls_io_lock); 574 mutex_enter(&rtlsp->rtls_rx_lock); 575 mutex_enter(&rtlsp->rtls_tx_lock); 576 577 rtlsp->rtls_suspended = B_TRUE; 578 rtls_chip_stop(rtlsp); 579 580 mutex_exit(&rtlsp->rtls_tx_lock); 581 mutex_exit(&rtlsp->rtls_rx_lock); 582 mutex_exit(&rtlsp->rtls_io_lock); 583 return (DDI_SUCCESS); 584 585 default: 586 return (DDI_FAILURE); 587 } 588 589 if (mac_unregister(rtlsp->mh) != 0) { 590 /* device busy */ 591 return (DDI_FAILURE); 592 } 593 594 ddi_remove_intr(devinfo, 0, rtlsp->iblk); 595 596 mii_free(rtlsp->mii); 597 598 mutex_destroy(&rtlsp->rtls_io_lock); 599 mutex_destroy(&rtlsp->rtls_tx_lock); 600 mutex_destroy(&rtlsp->rtls_rx_lock); 601 602 ddi_regs_map_free(&rtlsp->io_handle); 603 rtls_free_bufs(rtlsp); 604 kmem_free(rtlsp, sizeof (rtls_t)); 605 606 return (DDI_SUCCESS); 607 } 608 609 /* 610 * quiesce(9E) entry point. 611 * 612 * This function is called when the system is single-threaded at high 613 * PIL with preemption disabled. Therefore, this function must not be 614 * blocked. 615 * 616 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 617 * DDI_FAILURE indicates an error condition and should almost never happen. 618 */ 619 static int 620 rtls_quiesce(dev_info_t *devinfo) 621 { 622 rtls_t *rtlsp; /* our private device info */ 623 624 /* 625 * Get the driver private structure 626 */ 627 if ((rtlsp = ddi_get_driver_private(devinfo)) == NULL) { 628 return (DDI_FAILURE); 629 } 630 return (rtls_chip_reset(rtlsp, B_TRUE)); 631 } 632 633 /* 634 * ========== MAC Entry Points ========== 635 */ 636 637 /* 638 * rtls_m_start() -- start the board receiving and allow transmits 639 */ 640 static int 641 rtls_m_start(void *arg) 642 { 643 rtls_t *rtlsp = (rtls_t *)arg; 644 645 mutex_enter(&rtlsp->rtls_io_lock); 646 mutex_enter(&rtlsp->rtls_rx_lock); 647 mutex_enter(&rtlsp->rtls_tx_lock); 648 649 if (!rtlsp->rtls_suspended) 650 rtls_chip_restart(rtlsp); 651 652 rtlsp->rtls_running = B_TRUE; 653 654 mutex_exit(&rtlsp->rtls_tx_lock); 655 mutex_exit(&rtlsp->rtls_rx_lock); 656 mutex_exit(&rtlsp->rtls_io_lock); 657 658 drv_usecwait(100); 659 660 mii_start(rtlsp->mii); 661 662 return (0); 663 } 664 665 /* 666 * rtls_m_stop() -- stop board receiving and transmits 667 */ 668 static void 669 rtls_m_stop(void *arg) 670 { 671 rtls_t *rtlsp = (rtls_t *)arg; 672 673 mii_stop(rtlsp->mii); 674 675 mutex_enter(&rtlsp->rtls_io_lock); 676 677 if (!rtlsp->rtls_suspended) 678 rtls_chip_stop(rtlsp); 679 rtlsp->rtls_running = B_FALSE; 680 681 mutex_exit(&rtlsp->rtls_io_lock); 682 } 683 684 /* 685 * rtls_m_unicst() -- set the physical network address 686 * on the board 687 */ 688 static int 689 rtls_m_unicst(void *arg, const uint8_t *macaddr) 690 { 691 rtls_t *rtlsp = arg; 692 693 mutex_enter(&rtlsp->rtls_io_lock); 694 bcopy(macaddr, rtlsp->netaddr, ETHERADDRL); 695 if (!rtlsp->rtls_suspended) 696 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 697 mutex_exit(&rtlsp->rtls_io_lock); 698 return (0); 699 } 700 701 /* 702 * rtls_m_multicst() -- set(enable) or disable a multicast address 703 * 704 * Program the hardware to enable/disable the multicast address in "mcast". 705 */ 706 static int 707 rtls_m_multicst(void *arg, boolean_t enable, const uint8_t *mcast) 708 { 709 rtls_t *rtlsp = (rtls_t *)arg; 710 uint_t index; 711 uint32_t *hashp; 712 713 mutex_enter(&rtlsp->rtls_io_lock); 714 hashp = rtlsp->multi_hash; 715 index = rtls_hash_index(mcast); 716 /* index value is between 0 and 63 */ 717 718 if (enable) { 719 if (rtlsp->multicast_cnt[index]++) { 720 mutex_exit(&rtlsp->rtls_io_lock); 721 return (0); 722 } 723 hashp[index/32] |= 1<< (index % 32); 724 } else { 725 if (--rtlsp->multicast_cnt[index]) { 726 mutex_exit(&rtlsp->rtls_io_lock); 727 return (0); 728 } 729 hashp[index/32] &= ~(1<< (index % 32)); 730 } 731 732 /* 733 * Set multicast register 734 */ 735 if (!rtlsp->rtls_suspended) { 736 rtls_reg_set32(rtlsp, MULTICAST_0_REG, hashp[0]); 737 rtls_reg_set32(rtlsp, MULTICAST_4_REG, hashp[1]); 738 } 739 740 mutex_exit(&rtlsp->rtls_io_lock); 741 742 return (0); 743 } 744 745 /* 746 * rtls_hash_index() -- a hashing function used for setting the 747 * node address or a multicast address 748 */ 749 static uint_t 750 rtls_hash_index(const uint8_t *address) 751 { 752 uint32_t crc = (ulong_t)RTLS_HASH_CRC; 753 uint32_t const POLY = RTLS_HASH_POLY; 754 uint32_t msb; 755 int bytes; 756 uchar_t currentbyte; 757 uint_t index; 758 int bit; 759 760 for (bytes = 0; bytes < ETHERADDRL; bytes++) { 761 currentbyte = address[bytes]; 762 for (bit = 0; bit < 8; bit++) { 763 msb = crc >> 31; 764 crc <<= 1; 765 if (msb ^ (currentbyte & 1)) { 766 crc ^= POLY; 767 crc |= 0x00000001; 768 } 769 currentbyte >>= 1; 770 } 771 } 772 773 index = crc >> 26; 774 775 return (index); 776 } 777 778 /* 779 * rtls_m_promisc() -- set or reset promiscuous mode on the board 780 */ 781 static int 782 rtls_m_promisc(void *arg, boolean_t on) 783 { 784 rtls_t *rtlsp = arg; 785 786 mutex_enter(&rtlsp->rtls_io_lock); 787 788 rtlsp->promisc = on; 789 if (!rtlsp->rtls_suspended) { 790 uint32_t val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 791 if (on) { 792 val32 |= RX_ACCEPT_ALL_PACKET; 793 } else { 794 val32 &= ~RX_ACCEPT_ALL_PACKET; 795 } 796 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32); 797 } 798 mutex_exit(&rtlsp->rtls_io_lock); 799 800 return (0); 801 } 802 803 /* 804 * rtls_m_stat() -- retrieve statistic 805 * 806 * MAC calls this routine just before it reads the driver's statistics 807 * structure. If your board maintains statistics, this is the time to 808 * read them in and update the values in the structure. If the driver 809 * maintains statistics continuously, this routine need do nothing. 810 */ 811 static int 812 rtls_m_stat(void *arg, uint_t stat, uint64_t *val) 813 { 814 rtls_t *rtlsp = arg; 815 816 if (mii_m_getstat(rtlsp->mii, stat, val) == 0) { 817 return (0); 818 } 819 820 switch (stat) { 821 case MAC_STAT_IPACKETS: 822 *val = rtlsp->stats.ipackets; 823 break; 824 case MAC_STAT_RBYTES: 825 *val = rtlsp->stats.rbytes; 826 break; 827 case MAC_STAT_OPACKETS: 828 *val = rtlsp->stats.opackets; 829 break; 830 case MAC_STAT_OBYTES: 831 *val = rtlsp->stats.obytes; 832 break; 833 case MAC_STAT_IERRORS: 834 *val = rtlsp->stats.rcv_err; 835 break; 836 case MAC_STAT_OERRORS: 837 *val = rtlsp->stats.xmt_err; 838 break; 839 case MAC_STAT_MULTIRCV: 840 *val = rtlsp->stats.multi_rcv; 841 break; 842 case MAC_STAT_BRDCSTRCV: 843 *val = rtlsp->stats.brdcst_rcv; 844 break; 845 case MAC_STAT_MULTIXMT: 846 *val = rtlsp->stats.multi_xmt; 847 break; 848 case MAC_STAT_BRDCSTXMT: 849 *val = rtlsp->stats.brdcst_xmt; 850 break; 851 case MAC_STAT_UNDERFLOWS: 852 *val = rtlsp->stats.underflow; 853 break; 854 case MAC_STAT_OVERFLOWS: 855 *val = rtlsp->stats.overflow; 856 break; 857 case MAC_STAT_NORCVBUF: 858 *val = rtlsp->stats.no_rcvbuf; 859 break; 860 case MAC_STAT_COLLISIONS: 861 *val = rtlsp->stats.collisions; 862 break; 863 case ETHER_STAT_FCS_ERRORS: 864 *val = rtlsp->stats.crc_err; 865 break; 866 case ETHER_STAT_ALIGN_ERRORS: 867 *val = rtlsp->stats.frame_err; 868 break; 869 case ETHER_STAT_DEFER_XMTS: 870 *val = rtlsp->stats.defer; 871 break; 872 case ETHER_STAT_TX_LATE_COLLISIONS: 873 *val = rtlsp->stats.xmt_latecoll; 874 break; 875 case ETHER_STAT_TOOLONG_ERRORS: 876 *val = rtlsp->stats.too_long; 877 break; 878 case ETHER_STAT_TOOSHORT_ERRORS: 879 *val = rtlsp->stats.in_short; 880 break; 881 case ETHER_STAT_CARRIER_ERRORS: 882 *val = rtlsp->stats.no_carrier; 883 break; 884 case ETHER_STAT_FIRST_COLLISIONS: 885 *val = rtlsp->stats.firstcol; 886 break; 887 case ETHER_STAT_MULTI_COLLISIONS: 888 *val = rtlsp->stats.multicol; 889 break; 890 default: 891 return (ENOTSUP); 892 } 893 894 /* 895 * RTL8139 don't support MII statistics, 896 * these values are maintained by the driver software. 897 */ 898 899 #ifdef RTLS_DEBUG 900 if (rtls_debug & RTLS_TRACE) 901 rtls_reg_print(rtlsp); 902 #endif 903 904 return (0); 905 } 906 907 int 908 rtls_m_getprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz, 909 void *val) 910 { 911 rtls_t *rtlsp = arg; 912 913 return (mii_m_getprop(rtlsp->mii, name, num, sz, val)); 914 } 915 916 int 917 rtls_m_setprop(void *arg, const char *name, mac_prop_id_t num, uint_t sz, 918 const void *val) 919 { 920 rtls_t *rtlsp = arg; 921 922 return (mii_m_setprop(rtlsp->mii, name, num, sz, val)); 923 } 924 925 static void 926 rtls_m_propinfo(void *arg, const char *name, mac_prop_id_t num, 927 mac_prop_info_handle_t prh) 928 { 929 rtls_t *rtlsp = arg; 930 931 mii_m_propinfo(rtlsp->mii, name, num, prh); 932 } 933 934 /* 935 * rtls_send() -- send a packet 936 * 937 * Called when a packet is ready to be transmitted. A pointer to an 938 * M_DATA message that contains the packet is passed to this routine. 939 * The complete LLC header is contained in the message's first message 940 * block, and the remainder of the packet is contained within 941 * additional M_DATA message blocks linked to the first message block. 942 * 943 * Returns B_TRUE if the packet was properly disposed of, or B_FALSE if 944 * if the packet is being deferred and should be tried again later. 945 */ 946 947 static boolean_t 948 rtls_send(rtls_t *rtlsp, mblk_t *mp) 949 { 950 int totlen; 951 int ncc; 952 uint16_t cur_desc; 953 uint32_t tx_status; 954 955 ASSERT(mp != NULL); 956 ASSERT(rtlsp->rtls_running); 957 958 mutex_enter(&rtlsp->rtls_tx_lock); 959 960 if (rtlsp->rtls_suspended) { 961 mutex_exit(&rtlsp->rtls_tx_lock); 962 return (B_FALSE); 963 } 964 965 /* 966 * If chip error ... 967 */ 968 if (rtlsp->chip_error) { 969 #ifdef RTLS_DEBUG 970 cmn_err(CE_WARN, 971 "%s: send fail--CHIP ERROR!", 972 mac_name(rtlsp->mh)); 973 #endif 974 mutex_exit(&rtlsp->rtls_tx_lock); 975 freemsg(mp); 976 return (B_TRUE); 977 } 978 979 /* 980 * If chip link down ... Note that experimentation shows that 981 * the device seems not to care about whether or not we have 982 * this check, but if we don't add the check here, it might 983 * not be properly reported as a carrier error. 984 */ 985 if (rtls_reg_get8(rtlsp, MEDIA_STATUS_REG) & MEDIA_STATUS_LINK) { 986 #ifdef RTLS_DEBUG 987 cmn_err(CE_WARN, 988 "%s: send fail--LINK DOWN!", 989 mac_name(rtlsp->mh)); 990 #endif 991 rtlsp->stats.no_carrier++; 992 mutex_exit(&rtlsp->rtls_tx_lock); 993 freemsg(mp); 994 return (B_TRUE); 995 } 996 997 /* 998 * Current transmit descriptor 999 */ 1000 cur_desc = rtlsp->tx_current_desc; 1001 ASSERT(cur_desc < RTLS_MAX_TX_DESC); 1002 1003 /* 1004 * RealTek 8139 has 4 tx descriptor for transmit. In the first tx loop 1005 * of transmit,we needn't judge transmit status. 1006 */ 1007 if (rtlsp->tx_first_loop < RTLS_MAX_TX_DESC) { 1008 rtlsp->tx_first_loop++; 1009 goto tx_ready; 1010 } 1011 1012 /* 1013 * If it's not the first tx loop, we need judge whether the chip is 1014 * busy or not. Otherwise, we have to reschedule send and wait... 1015 */ 1016 tx_status = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc); 1017 1018 /* 1019 * H/W doesn't complete packet transmit 1020 */ 1021 if (!(tx_status & TX_COMPLETE_FLAG)) { 1022 #ifdef RTLS_DEBUG 1023 if (rtls_debug & RTLS_SEND) { 1024 cmn_err(CE_NOTE, 1025 "%s: rtls_send: need_sched", mac_name(rtlsp->mh)); 1026 } 1027 #endif 1028 /* 1029 * Through test, we find RTL8139 tx status might be 1030 * not-completing all along. We have to reset chip 1031 * to make RTL8139 tansmit re-work. 1032 */ 1033 if (rtlsp->tx_retry++ > RTLS_TX_RETRY_NUM) { 1034 1035 /* 1036 * Wait transmit h/w more time... 1037 */ 1038 RTLS_TX_WAIT_TIMEOUT; /* 100 ms */ 1039 1040 /* 1041 * Judge tx status again, if it remains not-completing, 1042 * we can confirm RTL8139 is in chip error state 1043 * and must reset it. 1044 */ 1045 tx_status = rtls_reg_get32(rtlsp, 1046 TX_STATUS_DESC0_REG + 4 * cur_desc); 1047 if (!(tx_status & TX_COMPLETE_FLAG)) { 1048 #ifdef RTLS_DEBUG 1049 cmn_err(CE_NOTE, "%s: tx chip_error = 0x%x", 1050 mac_name(rtlsp->mh), tx_status); 1051 #endif 1052 rtlsp->tx_retry = 0; 1053 rtlsp->chip_error = B_TRUE; 1054 rtlsp->stats.xmt_err++; 1055 rtlsp->stats.mac_xmt_err++; 1056 mutex_exit(&rtlsp->rtls_tx_lock); 1057 freemsg(mp); 1058 return (B_TRUE); 1059 } 1060 } else { 1061 rtlsp->stats.defer++; 1062 rtlsp->need_sched = B_TRUE; 1063 mutex_exit(&rtlsp->rtls_tx_lock); 1064 return (B_FALSE); 1065 } 1066 } 1067 1068 /* 1069 * Transmit error? 1070 */ 1071 if (tx_status & TX_ERR_FLAG) { 1072 #ifdef RTLS_DEBUG 1073 if (rtls_debug & RTLS_SEND) { 1074 cmn_err(CE_NOTE, "%s: transmit error, status = 0x%x", 1075 mac_name(rtlsp->mh), tx_status); 1076 } 1077 #endif 1078 rtlsp->stats.xmt_err++; 1079 if (tx_status & TX_STATUS_TX_UNDERRUN) 1080 rtlsp->stats.underflow++; 1081 if (tx_status & TX_STATUS_CS_LOST) 1082 rtlsp->stats.no_carrier++; 1083 if (tx_status & TX_STATUS_OWC) 1084 rtlsp->stats.xmt_latecoll++; 1085 } 1086 ncc = ((tx_status & TX_STATUS_NCC) >> TX_STATUS_NCC_SHIFT); 1087 if (ncc != 0) { 1088 rtlsp->stats.collisions += ncc; 1089 rtlsp->stats.firstcol++; 1090 rtlsp->stats.multicol += ncc - 1; 1091 } 1092 1093 tx_ready: 1094 /* 1095 * Initialize variable 1096 */ 1097 rtlsp->tx_retry = 0; 1098 totlen = 0; 1099 1100 /* 1101 * Copy packet to tx descriptor buffer 1102 */ 1103 totlen = msgsize(mp); 1104 if (totlen > (ETHERMAX + 4)) { /* 4 bytes for VLAN header */ 1105 cmn_err(CE_NOTE, 1106 "%s: rtls_send: try to send large %d packet", 1107 mac_name(rtlsp->mh), totlen); 1108 rtlsp->stats.mac_xmt_err++; 1109 rtlsp->stats.xmt_err++; 1110 freemsg(mp); 1111 mutex_exit(&rtlsp->rtls_tx_lock); 1112 return (B_TRUE); 1113 } 1114 1115 /* this will free the mblk */ 1116 mcopymsg(mp, rtlsp->tx_buf[cur_desc]); 1117 1118 /* update stats */ 1119 if (*rtlsp->tx_buf[cur_desc] & 0x1) { 1120 uint16_t *ptr = (void *)rtlsp->tx_buf[cur_desc]; 1121 if ((ptr[0] == 0xffff) && 1122 (ptr[1] == 0xffff) && 1123 (ptr[2] == 0xffff)) { 1124 rtlsp->stats.brdcst_xmt++; 1125 } else { 1126 rtlsp->stats.multi_xmt++; 1127 } 1128 } 1129 rtlsp->stats.opackets++; 1130 rtlsp->stats.obytes += totlen; 1131 1132 if (totlen < ETHERMIN) { 1133 bzero(rtlsp->tx_buf[cur_desc] + totlen, ETHERMIN - totlen); 1134 totlen = ETHERMIN; 1135 } 1136 1137 /* make sure caches are flushed */ 1138 (void) ddi_dma_sync(rtlsp->dma_area_tx[cur_desc].dma_hdl, 0, totlen, 1139 DDI_DMA_SYNC_FORDEV); 1140 1141 /* 1142 * Start transmit 1143 * set transmit FIFO threshhold to 0x30*32 = 1536 bytes 1144 * to avoid tx underrun. 1145 */ 1146 rtls_reg_set32(rtlsp, TX_STATUS_DESC0_REG + 4 * cur_desc, 1147 totlen | (0x30 << TX_STATUS_TX_THRESHOLD_SHIFT)); 1148 1149 /* 1150 * Update the value of current tx descriptor 1151 */ 1152 cur_desc++; 1153 cur_desc %= RTLS_MAX_TX_DESC; 1154 rtlsp->tx_current_desc = cur_desc; 1155 1156 mutex_exit(&rtlsp->rtls_tx_lock); 1157 1158 return (B_TRUE); 1159 } 1160 1161 /* 1162 * rtls_m_tx() -- send a chain of packets, linked by mp->b_next. 1163 */ 1164 static mblk_t * 1165 rtls_m_tx(void *arg, mblk_t *mp) 1166 { 1167 rtls_t *rtlsp = arg; 1168 mblk_t *next; 1169 1170 while (mp != NULL) { 1171 next = mp->b_next; 1172 mp->b_next = NULL; 1173 if (!rtls_send(rtlsp, mp)) { 1174 mp->b_next = next; 1175 break; 1176 } 1177 mp = next; 1178 } 1179 return (mp); 1180 } 1181 1182 /* 1183 * rtls_receive() -- receive packets 1184 * 1185 * Called when receive interrupts detected 1186 */ 1187 static void 1188 rtls_receive(rtls_t *rtlsp) 1189 { 1190 mblk_t *head = NULL; 1191 mblk_t **mpp; 1192 mblk_t *mp; 1193 uint16_t rx_status; 1194 uint16_t packet_len; 1195 int wrap_size; 1196 uint32_t cur_rx; 1197 uint8_t *rx_ptr; 1198 1199 mpp = &head; 1200 1201 mutex_enter(&rtlsp->rtls_rx_lock); 1202 1203 if (rtlsp->rtls_suspended) { 1204 mutex_exit(&rtlsp->rtls_rx_lock); 1205 return; 1206 } 1207 1208 while ((rtls_reg_get8(rtlsp, RT_COMMAND_REG) 1209 & RT_COMMAND_BUFF_EMPTY) == 0) { 1210 1211 /* 1212 * Chip error state 1213 */ 1214 if (rtlsp->chip_error) { 1215 #ifdef RTLS_DEBUG 1216 cmn_err(CE_WARN, 1217 "%s: receive fail--CHIP ERROR!", 1218 mac_name(rtlsp->mh)); 1219 #endif 1220 break; 1221 } 1222 1223 cur_rx = rtlsp->cur_rx; 1224 rx_ptr = rtlsp->rx_ring + cur_rx; 1225 packet_len = (rx_ptr[3] << 8) | (rx_ptr[2]); 1226 rx_status = rx_ptr[0]; 1227 1228 /* 1229 * DMA still in progress 1230 */ 1231 if (packet_len == RX_STATUS_DMA_BUSY) { 1232 cmn_err(CE_NOTE, "%s: Rx DMA still in progress", 1233 mac_name(rtlsp->mh)); 1234 break; 1235 } 1236 1237 /* 1238 * Check receive status 1239 */ 1240 if ((rx_status & RX_ERR_FLAGS) || 1241 (!(rx_status & RX_HEADER_STATUS_ROK)) || 1242 (packet_len < (ETHERMIN + ETHERFCSL)) || 1243 (packet_len > (ETHERMAX + ETHERFCSL + 4))) { 1244 #ifdef RTLS_DEBUG 1245 cmn_err(CE_NOTE, 1246 "%s: receive error, status = 0x%x, length = %d", 1247 mac_name(rtlsp->mh), rx_status, packet_len); 1248 #endif 1249 /* 1250 * Rx error statistics 1251 */ 1252 if ((rx_status & RX_HEADER_STATUS_RUNT) || 1253 (packet_len < (ETHERMIN + ETHERFCSL))) 1254 rtlsp->stats.in_short++; 1255 else if (packet_len > (ETHERMAX + ETHERFCSL + 4)) 1256 rtlsp->stats.too_long++; 1257 else if (rx_status & RX_HEADER_STATUS_CRC) 1258 rtlsp->stats.crc_err++; 1259 else if (rx_status & RX_HEADER_STATUS_FAE) 1260 rtlsp->stats.frame_err++; 1261 1262 /* 1263 * Set chip_error flag to reset chip: 1264 * (suggested in RealTek programming guide.) 1265 */ 1266 rtlsp->chip_error = B_TRUE; 1267 mutex_exit(&rtlsp->rtls_rx_lock); 1268 return; 1269 } 1270 1271 /* 1272 * We need not up-send ETHERFCSL bytes of receive packet 1273 */ 1274 packet_len -= ETHERFCSL; 1275 1276 /* 1277 * Allocate buffer to receive this good packet 1278 */ 1279 mp = allocb(packet_len, 0); 1280 1281 /* 1282 * Copy the data found into the new cluster, we have (+4) 1283 * to get us past the packet head data that the rtl chip 1284 * places at the start of the message 1285 */ 1286 if ((cur_rx + packet_len + RX_HEADER_SIZE) 1287 > RTLS_RX_BUF_RING) { 1288 wrap_size = cur_rx + packet_len + RX_HEADER_SIZE 1289 - RTLS_RX_BUF_RING; 1290 #ifdef RTLS_DEBUG 1291 if (rtls_debug & RTLS_RECV) { 1292 cmn_err(CE_NOTE, 1293 "%s: Rx: packet_len = %d, wrap_size = %d", 1294 mac_name(rtlsp->mh), packet_len, wrap_size); 1295 } 1296 #endif 1297 1298 if (mp != NULL) { 1299 /* Flush caches */ 1300 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1301 cur_rx + RX_HEADER_SIZE, 1302 packet_len - wrap_size, 1303 DDI_DMA_SYNC_FORKERNEL); 1304 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1305 0, wrap_size, 1306 DDI_DMA_SYNC_FORKERNEL); 1307 1308 /* 1309 * Copy in first section of message as stored 1310 * at the end of the ring buffer 1311 */ 1312 bcopy(rx_ptr + RX_HEADER_SIZE, 1313 mp->b_wptr, packet_len - wrap_size); 1314 mp->b_wptr += packet_len - wrap_size; 1315 bcopy(rtlsp->rx_ring, mp->b_wptr, wrap_size); 1316 mp->b_wptr += wrap_size; 1317 *mpp = mp; 1318 mpp = &mp->b_next; 1319 1320 rtlsp->stats.ipackets++; 1321 if (rx_status & RX_HEADER_STATUS_BCAST) 1322 rtlsp->stats.brdcst_rcv++; 1323 if (rx_status & RX_HEADER_STATUS_MULTI) 1324 rtlsp->stats.multi_rcv++; 1325 rtlsp->stats.rbytes += packet_len; 1326 } else { 1327 rtlsp->stats.no_rcvbuf++; 1328 } 1329 1330 cur_rx = RTLS_RX_ADDR_ALIGNED(wrap_size + ETHERFCSL); 1331 /* 4-byte aligned */ 1332 } else { 1333 1334 if (mp != NULL) { 1335 /* Flush caches */ 1336 (void) ddi_dma_sync(rtlsp->dma_area_rx.dma_hdl, 1337 cur_rx + RX_HEADER_SIZE, packet_len, 1338 DDI_DMA_SYNC_FORKERNEL); 1339 bcopy(rx_ptr + RX_HEADER_SIZE, mp->b_wptr, 1340 packet_len); 1341 mp->b_wptr += packet_len; 1342 *mpp = mp; 1343 mpp = &mp->b_next; 1344 1345 rtlsp->stats.ipackets++; 1346 if (rx_status & RX_HEADER_STATUS_BCAST) 1347 rtlsp->stats.brdcst_rcv++; 1348 if (rx_status & RX_HEADER_STATUS_MULTI) 1349 rtlsp->stats.multi_rcv++; 1350 rtlsp->stats.rbytes += packet_len; 1351 } else { 1352 rtlsp->stats.no_rcvbuf++; 1353 } 1354 cur_rx += packet_len + RX_HEADER_SIZE + ETHERFCSL; 1355 1356 cur_rx = RTLS_RX_ADDR_ALIGNED(cur_rx); 1357 /* 4-byte aligned */ 1358 } 1359 1360 /* 1361 * Update rx buffer ring read pointer: 1362 * give us a little leeway to ensure no overflow 1363 */ 1364 rtlsp->cur_rx = cur_rx; 1365 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, 1366 cur_rx - READ_ADDR_GAP); 1367 } 1368 mutex_exit(&rtlsp->rtls_rx_lock); 1369 1370 /* 1371 * Upsend packet 1372 */ 1373 if (head) { 1374 mac_rx(rtlsp->mh, NULL, head); 1375 } 1376 } 1377 1378 /* 1379 * rtls_intr() -- interrupt from board to inform us that a receive or 1380 * link change. 1381 */ 1382 static uint_t 1383 rtls_intr(caddr_t arg) 1384 { 1385 rtls_t *rtlsp = (void *)arg; 1386 uint32_t int_status; 1387 uint32_t val32; 1388 boolean_t resched = B_FALSE; 1389 1390 mutex_enter(&rtlsp->rtls_io_lock); 1391 if (rtlsp->rtls_suspended) { 1392 mutex_exit(&rtlsp->rtls_io_lock); 1393 return (DDI_INTR_UNCLAIMED); 1394 } 1395 1396 /* 1397 * Was this interrupt caused by our device... 1398 */ 1399 int_status = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1400 if (!(int_status & rtlsp->int_mask)) { 1401 mutex_exit(&rtlsp->rtls_io_lock); 1402 return (DDI_INTR_UNCLAIMED); 1403 /* indicate it wasn't our interrupt */ 1404 } 1405 1406 /* 1407 * Clear interrupt 1408 */ 1409 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, int_status); 1410 1411 /* 1412 * If chip error, restart chip... 1413 */ 1414 if (rtlsp->chip_error) { 1415 mutex_enter(&rtlsp->rtls_rx_lock); 1416 mutex_enter(&rtlsp->rtls_tx_lock); 1417 rtls_chip_restart(rtlsp); 1418 rtlsp->chip_error = B_FALSE; 1419 rtlsp->tx_retry = 0; 1420 mutex_exit(&rtlsp->rtls_tx_lock); 1421 mutex_exit(&rtlsp->rtls_rx_lock); 1422 mutex_exit(&rtlsp->rtls_io_lock); 1423 return (DDI_INTR_CLAIMED); 1424 /* no need to hand other interrupts */ 1425 } 1426 1427 /* 1428 * Transmit error interrupt 1429 */ 1430 if (int_status & TX_ERR_INT) { 1431 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1432 val32 |= TX_CLEAR_ABORT; 1433 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32); 1434 cmn_err(CE_WARN, "%s: transmit abort!!!", mac_name(rtlsp->mh)); 1435 } 1436 1437 /* 1438 * Trigger mac_tx_update 1439 */ 1440 if (rtlsp->need_sched) { 1441 rtlsp->need_sched = B_FALSE; 1442 resched = B_TRUE; 1443 } 1444 1445 mutex_exit(&rtlsp->rtls_io_lock); 1446 1447 /* 1448 * Receive interrupt 1449 */ 1450 if (int_status & RTLS_RX_INT) { 1451 if (int_status & RX_OVERFLOW_INT) { 1452 rtlsp->stats.overflow++; 1453 rtlsp->stats.rcv_err++; 1454 } 1455 rtls_receive(rtlsp); 1456 } 1457 1458 /* 1459 * Link change interrupt. 1460 */ 1461 if (int_status & LINK_CHANGE_INT) { 1462 mii_check(rtlsp->mii); 1463 } 1464 1465 if (resched) { 1466 mac_tx_update(rtlsp->mh); 1467 } 1468 1469 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1470 } 1471 1472 /* 1473 * ========== Buffer Management Routines ========== 1474 */ 1475 1476 /* 1477 * rtls_alloc_dma_mem() -- allocate an area of memory and a DMA handle 1478 * for accessing it 1479 */ 1480 static int 1481 rtls_alloc_dma_mem(rtls_t *rtlsp, size_t memsize, 1482 ddi_device_acc_attr_t *attr_p, uint_t dma_flags, dma_area_t *dma_p) 1483 { 1484 caddr_t vaddr; 1485 int err; 1486 1487 /* 1488 * Allocate handle 1489 */ 1490 err = ddi_dma_alloc_handle(rtlsp->devinfo, &dma_attr, 1491 DDI_DMA_SLEEP, NULL, &dma_p->dma_hdl); 1492 if (err != DDI_SUCCESS) { 1493 cmn_err(CE_WARN, 1494 "%s: rtls_alloc_dma_mem: ddi_dma_alloc_handle failed: %d", 1495 mac_name(rtlsp->mh), err); 1496 dma_p->dma_hdl = NULL; 1497 return (DDI_FAILURE); 1498 } 1499 1500 /* 1501 * Allocate memory 1502 */ 1503 err = ddi_dma_mem_alloc(dma_p->dma_hdl, memsize, attr_p, 1504 dma_flags & (DDI_DMA_CONSISTENT | DDI_DMA_STREAMING), 1505 DDI_DMA_SLEEP, NULL, &vaddr, &dma_p->alength, &dma_p->acc_hdl); 1506 if (err != DDI_SUCCESS) { 1507 cmn_err(CE_WARN, 1508 "%s: rtls_alloc_dma_mem: ddi_dma_mem_alloc failed: %d", 1509 mac_name(rtlsp->mh), err); 1510 ddi_dma_free_handle(&dma_p->dma_hdl); 1511 dma_p->dma_hdl = NULL; 1512 dma_p->acc_hdl = NULL; 1513 return (DDI_FAILURE); 1514 } 1515 1516 /* 1517 * Bind the two together 1518 */ 1519 dma_p->mem_va = vaddr; 1520 err = ddi_dma_addr_bind_handle(dma_p->dma_hdl, NULL, 1521 vaddr, dma_p->alength, dma_flags, DDI_DMA_SLEEP, NULL, 1522 &dma_p->cookie, &dma_p->ncookies); 1523 if (err != DDI_DMA_MAPPED || dma_p->ncookies != 1) { 1524 cmn_err(CE_WARN, 1525 "%s: rtls_alloc_dma_mem: " 1526 "ddi_dma_addr_bind_handle failed: %d", 1527 mac_name(rtlsp->mh), err); 1528 ddi_dma_mem_free(&dma_p->acc_hdl); 1529 ddi_dma_free_handle(&dma_p->dma_hdl); 1530 dma_p->acc_hdl = NULL; 1531 dma_p->dma_hdl = NULL; 1532 return (DDI_FAILURE); 1533 } 1534 1535 return (DDI_SUCCESS); 1536 } 1537 1538 /* 1539 * rtls_free_dma_mem() -- free one allocated area of DMAable memory 1540 */ 1541 static void 1542 rtls_free_dma_mem(dma_area_t *dma_p) 1543 { 1544 if (dma_p->dma_hdl != NULL) { 1545 if (dma_p->ncookies) { 1546 (void) ddi_dma_unbind_handle(dma_p->dma_hdl); 1547 dma_p->ncookies = 0; 1548 } 1549 ddi_dma_free_handle(&dma_p->dma_hdl); 1550 dma_p->dma_hdl = NULL; 1551 } 1552 1553 if (dma_p->acc_hdl != NULL) { 1554 ddi_dma_mem_free(&dma_p->acc_hdl); 1555 dma_p->acc_hdl = NULL; 1556 } 1557 } 1558 1559 /* 1560 * rtls_alloc_bufs() -- allocate descriptors/buffers for this device instance 1561 */ 1562 static int 1563 rtls_alloc_bufs(rtls_t *rtlsp) 1564 { 1565 int i; 1566 int err; 1567 1568 /* 1569 * Allocate memory & handle for Tx buffers 1570 */ 1571 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1572 err = rtls_alloc_dma_mem(rtlsp, 1573 RTLS_TX_BUF_SIZE, 1574 &rtls_buf_accattr, 1575 DDI_DMA_WRITE | DDI_DMA_STREAMING, 1576 &rtlsp->dma_area_tx[i]); 1577 1578 if (err != DDI_SUCCESS) 1579 return (DDI_FAILURE); 1580 1581 rtlsp->tx_buf[i] = (uint8_t *)rtlsp->dma_area_tx[i].mem_va; 1582 } 1583 1584 /* 1585 * Allocate memory & handle for Rx buffers 1586 */ 1587 err = rtls_alloc_dma_mem(rtlsp, 1588 RTLS_RX_BUF_SIZE, 1589 &rtls_buf_accattr, 1590 DDI_DMA_READ | DDI_DMA_STREAMING, 1591 &rtlsp->dma_area_rx); 1592 1593 if (err != DDI_SUCCESS) 1594 return (DDI_FAILURE); 1595 1596 rtlsp->rx_ring = (uint8_t *)rtlsp->dma_area_rx.mem_va; 1597 1598 return (DDI_SUCCESS); 1599 } 1600 1601 /* 1602 * rtls_free_bufs() -- free descriptors/buffers allocated for this 1603 * device instance. 1604 */ 1605 static void 1606 rtls_free_bufs(rtls_t *rtlsp) 1607 { 1608 int i; 1609 1610 for (i = 0; i < RTLS_MAX_TX_DESC; i++) { 1611 rtls_free_dma_mem(&rtlsp->dma_area_tx[i]); 1612 rtlsp->tx_buf[i] = NULL; 1613 } 1614 1615 rtls_free_dma_mem(&rtlsp->dma_area_rx); 1616 rtlsp->rx_ring = NULL; 1617 } 1618 1619 /* 1620 * ========== Chip H/W Operation Routines ========== 1621 */ 1622 1623 /* 1624 * rtls_chip_reset() -- reset chip 1625 */ 1626 static int 1627 rtls_chip_reset(rtls_t *rtlsp, boolean_t quiesce) 1628 { 1629 int i; 1630 uint16_t val16; 1631 uint8_t val8; 1632 1633 /* 1634 * Chip should be in STOP state 1635 */ 1636 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1637 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1638 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 1639 1640 /* 1641 * Disable interrupt 1642 */ 1643 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1644 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 1645 rtlsp->int_mask = RTLS_INT_MASK_NONE; 1646 1647 /* 1648 * Clear pended interrupt 1649 */ 1650 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1651 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 1652 1653 /* 1654 * Reset chip 1655 */ 1656 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1657 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8 | RT_COMMAND_RESET); 1658 1659 /* 1660 * Wait for reset success 1661 */ 1662 i = 0; 1663 while (rtls_reg_get8(rtlsp, RT_COMMAND_REG) & RT_COMMAND_RESET) { 1664 if (++i > RTLS_RESET_WAIT_NUM) { 1665 /* 1666 * At quiesce path we can't call cmn_err(), as 1667 * it might block 1668 */ 1669 if (!quiesce) 1670 cmn_err(CE_WARN, 1671 "%s: chip reset fail.", 1672 mac_name(rtlsp->mh)); 1673 return (DDI_FAILURE); 1674 } 1675 RTLS_RESET_WAIT_INTERVAL; 1676 } 1677 1678 return (DDI_SUCCESS); 1679 } 1680 1681 /* 1682 * rtls_chip_init() -- initialize the specified network board short of 1683 * actually starting the board. Call after rtls_chip_reset(). 1684 */ 1685 static void 1686 rtls_chip_init(rtls_t *rtlsp) 1687 { 1688 uint32_t val32; 1689 uint16_t val16; 1690 uint8_t val8; 1691 1692 /* 1693 * Initialize internal data structures 1694 */ 1695 rtlsp->cur_rx = 0; 1696 rtlsp->tx_current_desc = 0; 1697 rtlsp->tx_first_loop = 0; 1698 1699 /* 1700 * Set DMA physical rx/tx buffer address to register 1701 */ 1702 rtls_reg_set32(rtlsp, RX_BUFF_ADDR_REG, 1703 (ulong_t)rtlsp->dma_area_rx.cookie.dmac_address); 1704 rtls_reg_set32(rtlsp, TX_ADDR_DESC0_REG, 1705 (ulong_t)rtlsp->dma_area_tx[0].cookie.dmac_address); 1706 rtls_reg_set32(rtlsp, TX_ADDR_DESC1_REG, 1707 (ulong_t)rtlsp->dma_area_tx[1].cookie.dmac_address); 1708 rtls_reg_set32(rtlsp, TX_ADDR_DESC2_REG, 1709 (ulong_t)rtlsp->dma_area_tx[2].cookie.dmac_address); 1710 rtls_reg_set32(rtlsp, TX_ADDR_DESC3_REG, 1711 (ulong_t)rtlsp->dma_area_tx[3].cookie.dmac_address); 1712 1713 /* 1714 * Start transmit/receive before set tx/rx configuration register 1715 */ 1716 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1717 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 1718 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1719 1720 /* 1721 * Set transmit configuration register 1722 */ 1723 val32 = rtls_reg_get32(rtlsp, TX_CONFIG_REG); 1724 val32 &= TX_CONSIG_REG_RESERVE; 1725 rtls_reg_set32(rtlsp, TX_CONFIG_REG, val32 | TX_CONFIG_DEFAULT); 1726 1727 /* 1728 * Set receive configuration register 1729 */ 1730 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 1731 val32 &= RX_CONSIG_REG_RESERVE; 1732 if (rtlsp->promisc) 1733 val32 |= RX_ACCEPT_ALL_PACKET; 1734 rtls_reg_set32(rtlsp, RX_CONFIG_REG, val32 | RX_CONFIG_DEFAULT); 1735 1736 /* 1737 * Set multicast register 1738 */ 1739 rtls_reg_set32(rtlsp, MULTICAST_0_REG, rtlsp->multi_hash[0]); 1740 rtls_reg_set32(rtlsp, MULTICAST_4_REG, rtlsp->multi_hash[1]); 1741 1742 /* 1743 * Set unicast address 1744 */ 1745 rtls_set_mac_addr(rtlsp, rtlsp->netaddr); 1746 1747 /* 1748 * Set current address of packet read 1749 */ 1750 rtls_reg_set16(rtlsp, RX_CURRENT_READ_ADDR_REG, RX_READ_RESET_VAL); 1751 1752 /* 1753 * No early-rx interrupts 1754 */ 1755 val16 = rtls_reg_get16(rtlsp, RT_MUL_INTSEL_REG); 1756 val16 &= ~RT_MUL_INTSEL_BITS; 1757 rtls_reg_set16(rtlsp, RT_MUL_INTSEL_REG, val16); 1758 } 1759 1760 /* 1761 * rtls_chip_start() -- start chip 1762 */ 1763 static void 1764 rtls_chip_start(rtls_t *rtlsp) 1765 { 1766 uint16_t val16; 1767 uint8_t val8; 1768 1769 /* 1770 * Start transmit/receive 1771 */ 1772 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1773 rtls_reg_set8(rtlsp, RT_COMMAND_REG, 1774 val8 | RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1775 1776 /* 1777 * Enable interrupt 1778 */ 1779 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1780 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 | RTLS_INT_MASK); 1781 rtlsp->int_mask = RTLS_INT_MASK; 1782 } 1783 1784 /* 1785 * rtls_chip_restart() -- restart chip 1786 */ 1787 static void 1788 rtls_chip_restart(rtls_t *rtlsp) 1789 { 1790 (void) rtls_chip_reset(rtlsp, B_FALSE); 1791 rtls_chip_init(rtlsp); 1792 rtls_chip_start(rtlsp); 1793 } 1794 1795 /* 1796 * rtls_chip_stop() -- stop board receiving 1797 */ 1798 static void 1799 rtls_chip_stop(rtls_t *rtlsp) 1800 { 1801 uint16_t val16; 1802 uint8_t val8; 1803 1804 /* 1805 * Disable interrupt 1806 */ 1807 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 1808 rtls_reg_set16(rtlsp, RT_INT_MASK_REG, val16 & (~RTLS_INT_MASK_ALL)); 1809 rtlsp->int_mask = RTLS_INT_MASK_NONE; 1810 1811 /* 1812 * Clear pended interrupt 1813 */ 1814 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 1815 rtls_reg_set16(rtlsp, RT_INT_STATUS_REG, val16); 1816 1817 /* 1818 * Stop the board and disable transmit/receive 1819 */ 1820 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 1821 val8 &= ~(RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1822 rtls_reg_set8(rtlsp, RT_COMMAND_REG, val8); 1823 } 1824 1825 /* 1826 * rtls_get_mac_addr() -- get the physical network address on the board 1827 */ 1828 static void 1829 rtls_get_mac_addr(rtls_t *rtlsp, uint8_t *macaddr) 1830 { 1831 uint32_t val32; 1832 1833 /* 1834 * Read first 4-byte of mac address 1835 */ 1836 val32 = rtls_reg_get32(rtlsp, ID_0_REG); 1837 macaddr[0] = val32 & 0xff; 1838 val32 = val32 >> 8; 1839 macaddr[1] = val32 & 0xff; 1840 val32 = val32 >> 8; 1841 macaddr[2] = val32 & 0xff; 1842 val32 = val32 >> 8; 1843 macaddr[3] = val32 & 0xff; 1844 1845 /* 1846 * Read last 2-byte of mac address 1847 */ 1848 val32 = rtls_reg_get32(rtlsp, ID_4_REG); 1849 macaddr[4] = val32 & 0xff; 1850 val32 = val32 >> 8; 1851 macaddr[5] = val32 & 0xff; 1852 } 1853 1854 static void 1855 rtls_set_mac_addr(rtls_t *rtlsp, const uint8_t *macaddr) 1856 { 1857 uint32_t val32; 1858 uint8_t val8; 1859 1860 /* 1861 * Change to config register write enable mode 1862 */ 1863 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG); 1864 val8 |= RT_93c46_MODE_CONFIG; 1865 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1866 1867 /* 1868 * Get first 4 bytes of mac address 1869 */ 1870 val32 = macaddr[3]; 1871 val32 = val32 << 8; 1872 val32 |= macaddr[2]; 1873 val32 = val32 << 8; 1874 val32 |= macaddr[1]; 1875 val32 = val32 << 8; 1876 val32 |= macaddr[0]; 1877 1878 /* 1879 * Set first 4 bytes of mac address 1880 */ 1881 rtls_reg_set32(rtlsp, ID_0_REG, val32); 1882 1883 /* 1884 * Get last 2 bytes of mac address 1885 */ 1886 val32 = macaddr[5]; 1887 val32 = val32 << 8; 1888 val32 |= macaddr[4]; 1889 1890 /* 1891 * Set last 2 bytes of mac address 1892 */ 1893 val32 |= rtls_reg_get32(rtlsp, ID_4_REG) & ~0xffff; 1894 rtls_reg_set32(rtlsp, ID_4_REG, val32); 1895 1896 /* 1897 * Return to normal network/host communication mode 1898 */ 1899 val8 &= ~RT_93c46_MODE_CONFIG; 1900 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1901 } 1902 1903 static uint16_t 1904 rtls_mii_read(void *arg, uint8_t phy, uint8_t reg) 1905 { 1906 rtls_t *rtlsp = arg; 1907 uint16_t val; 1908 1909 if (phy != 1) { 1910 return (0xffff); 1911 } 1912 switch (reg) { 1913 case MII_CONTROL: 1914 val = rtls_reg_get16(rtlsp, BASIC_MODE_CONTROL_REG); 1915 break; 1916 case MII_STATUS: 1917 val = rtls_reg_get16(rtlsp, BASIC_MODE_STATUS_REG); 1918 break; 1919 case MII_AN_ADVERT: 1920 val = rtls_reg_get16(rtlsp, AUTO_NEGO_AD_REG); 1921 break; 1922 case MII_AN_LPABLE: 1923 val = rtls_reg_get16(rtlsp, AUTO_NEGO_LP_REG); 1924 break; 1925 case MII_AN_EXPANSION: 1926 val = rtls_reg_get16(rtlsp, AUTO_NEGO_EXP_REG); 1927 break; 1928 case MII_VENDOR(0): 1929 /* 1930 * We "simulate" a vendor private register so that the 1931 * PHY layer can access it to determine detected link 1932 * speed/duplex. 1933 */ 1934 val = rtls_reg_get8(rtlsp, MEDIA_STATUS_REG); 1935 break; 1936 case MII_PHYIDH: 1937 case MII_PHYIDL: 1938 default: 1939 val = 0; 1940 break; 1941 } 1942 return (val); 1943 } 1944 1945 void 1946 rtls_mii_write(void *arg, uint8_t phy, uint8_t reg, uint16_t val) 1947 { 1948 rtls_t *rtlsp = arg; 1949 uint8_t val8; 1950 1951 if (phy != 1) { 1952 return; 1953 } 1954 switch (reg) { 1955 case MII_CONTROL: 1956 /* Enable writes to all bits of BMCR */ 1957 val8 = rtls_reg_get8(rtlsp, RT_93c46_COMMAND_REG); 1958 val8 |= RT_93c46_MODE_CONFIG; 1959 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1960 /* write out the value */ 1961 rtls_reg_set16(rtlsp, BASIC_MODE_CONTROL_REG, val); 1962 1963 /* Return to normal network/host communication mode */ 1964 val8 &= ~RT_93c46_MODE_CONFIG; 1965 rtls_reg_set8(rtlsp, RT_93c46_COMMAND_REG, val8); 1966 return; 1967 1968 case MII_STATUS: 1969 rtls_reg_set16(rtlsp, BASIC_MODE_STATUS_REG, val); 1970 break; 1971 case MII_AN_ADVERT: 1972 rtls_reg_set16(rtlsp, AUTO_NEGO_AD_REG, val); 1973 break; 1974 case MII_AN_LPABLE: 1975 rtls_reg_set16(rtlsp, AUTO_NEGO_LP_REG, val); 1976 break; 1977 case MII_AN_EXPANSION: 1978 rtls_reg_set16(rtlsp, AUTO_NEGO_EXP_REG, val); 1979 break; 1980 case MII_PHYIDH: 1981 case MII_PHYIDL: 1982 default: 1983 /* these are not writable */ 1984 break; 1985 } 1986 } 1987 1988 void 1989 rtls_mii_notify(void *arg, link_state_t link) 1990 { 1991 rtls_t *rtlsp = arg; 1992 1993 mac_link_update(rtlsp->mh, link); 1994 } 1995 1996 #ifdef RTLS_DEBUG 1997 /* 1998 * rtls_reg_print() -- print out reg value(for debug use only) 1999 */ 2000 static void 2001 rtls_reg_print(rtls_t *rtlsp) 2002 { 2003 uint8_t val8; 2004 uint16_t val16; 2005 uint32_t val32; 2006 2007 val8 = rtls_reg_get8(rtlsp, RT_COMMAND_REG); 2008 cmn_err(CE_NOTE, "%s: RT_COMMAND_REG = 0x%x", 2009 mac_name(rtlsp->mh), val8); 2010 delay(drv_usectohz(1000)); 2011 2012 val16 = rtls_reg_get16(rtlsp, RT_INT_STATUS_REG); 2013 cmn_err(CE_NOTE, "%s: RT_INT_STATUS_REG = 0x%x", 2014 mac_name(rtlsp->mh), val16); 2015 delay(drv_usectohz(1000)); 2016 2017 val16 = rtls_reg_get16(rtlsp, RT_INT_MASK_REG); 2018 cmn_err(CE_NOTE, "%s: RT_INT_MASK_REG = 0x%x", 2019 mac_name(rtlsp->mh), val16); 2020 delay(drv_usectohz(1000)); 2021 2022 val32 = rtls_reg_get32(rtlsp, RX_CONFIG_REG); 2023 cmn_err(CE_NOTE, "%s: RX_CONFIG_REG = 0x%x", 2024 mac_name(rtlsp->mh), val32); 2025 delay(drv_usectohz(1000)); 2026 2027 val16 = rtls_reg_get16(rtlsp, TX_DESC_STAUS_REG); 2028 cmn_err(CE_NOTE, "%s: TX_DESC_STAUS_REG = 0x%x, cur_desc = %d", 2029 mac_name(rtlsp->mh), val16, rtlsp->tx_current_desc); 2030 delay(drv_usectohz(1000)); 2031 2032 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC0_REG); 2033 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC0_REG = 0x%x", 2034 mac_name(rtlsp->mh), val32); 2035 delay(drv_usectohz(1000)); 2036 2037 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC1_REG); 2038 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC1_REG = 0x%x", 2039 mac_name(rtlsp->mh), val32); 2040 delay(drv_usectohz(1000)); 2041 2042 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC2_REG); 2043 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC2_REG = 0x%x", 2044 mac_name(rtlsp->mh), val32); 2045 delay(drv_usectohz(1000)); 2046 2047 val32 = rtls_reg_get32(rtlsp, TX_STATUS_DESC3_REG); 2048 cmn_err(CE_NOTE, "%s: TX_STATUS_DESC3_REG = 0x%x", 2049 mac_name(rtlsp->mh), val32); 2050 delay(drv_usectohz(1000)); 2051 2052 cmn_err(CE_NOTE, "%s: in = %llu, multicast = %llu, broadcast = %llu", 2053 mac_name(rtlsp->mh), 2054 (unsigned long long)rtlsp->stats.ipackets, 2055 (unsigned long long)rtlsp->stats.multi_rcv, 2056 (unsigned long long)rtlsp->stats.brdcst_rcv); 2057 delay(drv_usectohz(1000)); 2058 } 2059 #endif 2060