1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include "rge.h" 27 28 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 29 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 30 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 31 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 32 33 /* 34 * Patchable globals: 35 * 36 * rge_autorecover 37 * Enables/disables automatic recovery after fault detection 38 */ 39 static uint32_t rge_autorecover = 1; 40 41 /* 42 * globals: 43 */ 44 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 45 static uint32_t rge_watchdog_count = 1 << 16; 46 47 /* 48 * Operating register get/set access routines 49 */ 50 51 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 52 #pragma inline(rge_reg_get32) 53 54 static uint32_t 55 rge_reg_get32(rge_t *rgep, uintptr_t regno) 56 { 57 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 58 (void *)rgep, regno)); 59 60 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 61 } 62 63 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 64 #pragma inline(rge_reg_put32) 65 66 static void 67 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 68 { 69 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 70 (void *)rgep, regno, data)); 71 72 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 73 } 74 75 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 76 #pragma inline(rge_reg_set32) 77 78 static void 79 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 80 { 81 uint32_t regval; 82 83 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 84 (void *)rgep, regno, bits)); 85 86 regval = rge_reg_get32(rgep, regno); 87 regval |= bits; 88 rge_reg_put32(rgep, regno, regval); 89 } 90 91 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 92 #pragma inline(rge_reg_clr32) 93 94 static void 95 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 96 { 97 uint32_t regval; 98 99 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 100 (void *)rgep, regno, bits)); 101 102 regval = rge_reg_get32(rgep, regno); 103 regval &= ~bits; 104 rge_reg_put32(rgep, regno, regval); 105 } 106 107 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 108 #pragma inline(rge_reg_get16) 109 110 static uint16_t 111 rge_reg_get16(rge_t *rgep, uintptr_t regno) 112 { 113 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 114 (void *)rgep, regno)); 115 116 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 117 } 118 119 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 120 #pragma inline(rge_reg_put16) 121 122 static void 123 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 124 { 125 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 126 (void *)rgep, regno, data)); 127 128 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 129 } 130 131 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 132 #pragma inline(rge_reg_get8) 133 134 static uint8_t 135 rge_reg_get8(rge_t *rgep, uintptr_t regno) 136 { 137 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 138 (void *)rgep, regno)); 139 140 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 141 } 142 143 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 144 #pragma inline(rge_reg_put8) 145 146 static void 147 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 148 { 149 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 150 (void *)rgep, regno, data)); 151 152 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 153 } 154 155 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 156 #pragma inline(rge_reg_set8) 157 158 static void 159 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 160 { 161 uint8_t regval; 162 163 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 164 (void *)rgep, regno, bits)); 165 166 regval = rge_reg_get8(rgep, regno); 167 regval |= bits; 168 rge_reg_put8(rgep, regno, regval); 169 } 170 171 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 172 #pragma inline(rge_reg_clr8) 173 174 static void 175 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 176 { 177 uint8_t regval; 178 179 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 180 (void *)rgep, regno, bits)); 181 182 regval = rge_reg_get8(rgep, regno); 183 regval &= ~bits; 184 rge_reg_put8(rgep, regno, regval); 185 } 186 187 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 188 #pragma no_inline(rge_mii_get16) 189 190 uint16_t 191 rge_mii_get16(rge_t *rgep, uintptr_t mii) 192 { 193 uint32_t regval; 194 uint32_t val32; 195 uint32_t i; 196 197 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 198 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 199 200 /* 201 * Waiting for PHY reading OK 202 */ 203 for (i = 0; i < PHY_RESET_LOOP; i++) { 204 drv_usecwait(1000); 205 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 206 if (val32 & PHY_ACCESS_WR_FLAG) 207 return ((uint16_t)(val32 & 0xffff)); 208 } 209 210 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 211 return ((uint16_t)~0u); 212 } 213 214 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 215 #pragma no_inline(rge_mii_put16) 216 217 void 218 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 219 { 220 uint32_t regval; 221 uint32_t val32; 222 uint32_t i; 223 224 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 225 regval |= data & PHY_DATA_MASK; 226 regval |= PHY_ACCESS_WR_FLAG; 227 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 228 229 /* 230 * Waiting for PHY writing OK 231 */ 232 for (i = 0; i < PHY_RESET_LOOP; i++) { 233 drv_usecwait(1000); 234 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 235 if (!(val32 & PHY_ACCESS_WR_FLAG)) 236 return; 237 } 238 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 239 mii, data)); 240 } 241 242 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 243 #pragma no_inline(rge_ephy_put16) 244 245 void 246 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 247 { 248 uint32_t regval; 249 uint32_t val32; 250 uint32_t i; 251 252 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 253 regval |= data & EPHY_DATA_MASK; 254 regval |= EPHY_ACCESS_WR_FLAG; 255 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 256 257 /* 258 * Waiting for PHY writing OK 259 */ 260 for (i = 0; i < PHY_RESET_LOOP; i++) { 261 drv_usecwait(1000); 262 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 263 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 264 return; 265 } 266 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 267 emii, data)); 268 } 269 270 /* 271 * Atomically shift a 32-bit word left, returning 272 * the value it had *before* the shift was applied 273 */ 274 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 275 #pragma inline(rge_mii_put16) 276 277 static uint32_t 278 rge_atomic_shl32(uint32_t *sp, uint_t count) 279 { 280 uint32_t oldval; 281 uint32_t newval; 282 283 /* ATOMICALLY */ 284 do { 285 oldval = *sp; 286 newval = oldval << count; 287 } while (cas32(sp, oldval, newval) != oldval); 288 289 return (oldval); 290 } 291 292 /* 293 * PHY operation routines 294 */ 295 #if RGE_DEBUGGING 296 297 void 298 rge_phydump(rge_t *rgep) 299 { 300 uint16_t regs[32]; 301 int i; 302 303 ASSERT(mutex_owned(rgep->genlock)); 304 305 for (i = 0; i < 32; ++i) { 306 regs[i] = rge_mii_get16(rgep, i); 307 } 308 309 for (i = 0; i < 32; i += 8) 310 RGE_DEBUG(("rge_phydump: " 311 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 312 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 313 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 314 } 315 316 #endif /* RGE_DEBUGGING */ 317 318 static void 319 rge_phy_check(rge_t *rgep) 320 { 321 uint16_t gig_ctl; 322 323 if (rgep->param_link_up == LINK_STATE_DOWN) { 324 /* 325 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 326 * every 15 seconds whin link down & advertise is 1000. 327 */ 328 if (rgep->chipid.phy_ver == PHY_VER_S) { 329 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 330 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 331 rgep->link_down_count++; 332 if (rgep->link_down_count > 15) { 333 (void) rge_phy_reset(rgep); 334 rgep->stats.phy_reset++; 335 rgep->link_down_count = 0; 336 } 337 } 338 } 339 } else { 340 rgep->link_down_count = 0; 341 } 342 } 343 344 /* 345 * Basic low-level function to reset the PHY. 346 * Doesn't incorporate any special-case workarounds. 347 * 348 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 349 */ 350 boolean_t 351 rge_phy_reset(rge_t *rgep) 352 { 353 uint16_t control; 354 uint_t count; 355 356 /* 357 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 358 */ 359 control = rge_mii_get16(rgep, MII_CONTROL); 360 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 361 for (count = 0; count < 5; count++) { 362 drv_usecwait(100); 363 control = rge_mii_get16(rgep, MII_CONTROL); 364 if (BIC(control, MII_CONTROL_RESET)) 365 return (B_TRUE); 366 } 367 368 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 369 return (B_FALSE); 370 } 371 372 /* 373 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 374 * and advertisements with the required settings as specified by the various 375 * param_* variables that can be poked via the NDD interface. 376 * 377 * We always reset the PHY and reprogram *all* the relevant registers, 378 * not just those changed. This should cause the link to go down, and then 379 * back up again once the link is stable and autonegotiation (if enabled) 380 * is complete. We should get a link state change interrupt somewhere along 381 * the way ... 382 * 383 * NOTE: <genlock> must already be held by the caller 384 */ 385 void 386 rge_phy_update(rge_t *rgep) 387 { 388 boolean_t adv_autoneg; 389 boolean_t adv_pause; 390 boolean_t adv_asym_pause; 391 boolean_t adv_1000fdx; 392 boolean_t adv_1000hdx; 393 boolean_t adv_100fdx; 394 boolean_t adv_100hdx; 395 boolean_t adv_10fdx; 396 boolean_t adv_10hdx; 397 398 uint16_t control; 399 uint16_t gigctrl; 400 uint16_t anar; 401 402 ASSERT(mutex_owned(rgep->genlock)); 403 404 RGE_DEBUG(("rge_phy_update: autoneg %d " 405 "pause %d asym_pause %d " 406 "1000fdx %d 1000hdx %d " 407 "100fdx %d 100hdx %d " 408 "10fdx %d 10hdx %d ", 409 rgep->param_adv_autoneg, 410 rgep->param_adv_pause, rgep->param_adv_asym_pause, 411 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 412 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 413 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 414 415 control = gigctrl = anar = 0; 416 417 /* 418 * PHY settings are normally based on the param_* variables, 419 * but if any loopback mode is in effect, that takes precedence. 420 * 421 * RGE supports MAC-internal loopback, PHY-internal loopback, 422 * and External loopback at a variety of speeds (with a special 423 * cable). In all cases, autoneg is turned OFF, full-duplex 424 * is turned ON, and the speed/mastership is forced. 425 */ 426 switch (rgep->param_loop_mode) { 427 case RGE_LOOP_NONE: 428 default: 429 adv_autoneg = rgep->param_adv_autoneg; 430 adv_pause = rgep->param_adv_pause; 431 adv_asym_pause = rgep->param_adv_asym_pause; 432 adv_1000fdx = rgep->param_adv_1000fdx; 433 adv_1000hdx = rgep->param_adv_1000hdx; 434 adv_100fdx = rgep->param_adv_100fdx; 435 adv_100hdx = rgep->param_adv_100hdx; 436 adv_10fdx = rgep->param_adv_10fdx; 437 adv_10hdx = rgep->param_adv_10hdx; 438 break; 439 440 case RGE_LOOP_INTERNAL_PHY: 441 case RGE_LOOP_INTERNAL_MAC: 442 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 443 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 444 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 445 rgep->param_link_duplex = LINK_DUPLEX_FULL; 446 447 switch (rgep->param_loop_mode) { 448 case RGE_LOOP_INTERNAL_PHY: 449 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 450 rgep->param_link_speed = 1000; 451 adv_1000fdx = B_TRUE; 452 } else { 453 rgep->param_link_speed = 100; 454 adv_100fdx = B_TRUE; 455 } 456 control = MII_CONTROL_LOOPBACK; 457 break; 458 459 case RGE_LOOP_INTERNAL_MAC: 460 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 461 rgep->param_link_speed = 1000; 462 adv_1000fdx = B_TRUE; 463 } else { 464 rgep->param_link_speed = 100; 465 adv_100fdx = B_TRUE; 466 break; 467 } 468 } 469 470 RGE_DEBUG(("rge_phy_update: autoneg %d " 471 "pause %d asym_pause %d " 472 "1000fdx %d 1000hdx %d " 473 "100fdx %d 100hdx %d " 474 "10fdx %d 10hdx %d ", 475 adv_autoneg, 476 adv_pause, adv_asym_pause, 477 adv_1000fdx, adv_1000hdx, 478 adv_100fdx, adv_100hdx, 479 adv_10fdx, adv_10hdx)); 480 481 /* 482 * We should have at least one technology capability set; 483 * if not, we select a default of 1000Mb/s full-duplex 484 */ 485 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 486 !adv_1000hdx && !adv_100hdx && !adv_10hdx) { 487 if (rgep->chipid.mac_ver != MAC_VER_8101E) 488 adv_1000fdx = B_TRUE; 489 } else { 490 adv_1000fdx = B_FALSE; 491 adv_100fdx = B_TRUE; 492 } 493 } 494 495 /* 496 * Now transform the adv_* variables into the proper settings 497 * of the PHY registers ... 498 * 499 * If autonegotiation is (now) enabled, we want to trigger 500 * a new autonegotiation cycle once the PHY has been 501 * programmed with the capabilities to be advertised. 502 * 503 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 504 */ 505 if (adv_autoneg) 506 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 507 508 if (adv_1000fdx) 509 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 510 else if (adv_1000hdx) 511 control |= MII_CONTROL_1000MB; 512 else if (adv_100fdx) 513 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 514 else if (adv_100hdx) 515 control |= MII_CONTROL_100MB; 516 else if (adv_10fdx) 517 control |= MII_CONTROL_FDUPLEX; 518 else if (adv_10hdx) 519 control |= 0; 520 else 521 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 522 523 if (adv_1000fdx) { 524 gigctrl |= MII_1000BT_CTL_ADV_FDX; 525 /* 526 * Chipset limitation: need set other capabilities to true 527 */ 528 if (rgep->chipid.is_pcie) 529 adv_1000hdx = B_TRUE; 530 adv_100fdx = B_TRUE; 531 adv_100hdx = B_TRUE; 532 adv_10fdx = B_TRUE; 533 adv_10hdx = B_TRUE; 534 } 535 536 if (adv_1000hdx) 537 gigctrl |= MII_1000BT_CTL_ADV_HDX; 538 539 if (adv_100fdx) 540 anar |= MII_ABILITY_100BASE_TX_FD; 541 if (adv_100hdx) 542 anar |= MII_ABILITY_100BASE_TX; 543 if (adv_10fdx) 544 anar |= MII_ABILITY_10BASE_T_FD; 545 if (adv_10hdx) 546 anar |= MII_ABILITY_10BASE_T; 547 548 if (adv_pause) 549 anar |= MII_ABILITY_PAUSE; 550 if (adv_asym_pause) 551 anar |= MII_ABILITY_ASYM_PAUSE; 552 553 /* 554 * Munge in any other fixed bits we require ... 555 */ 556 anar |= MII_AN_SELECTOR_8023; 557 558 /* 559 * Restart the PHY and write the new values. Note the 560 * time, so that we can say whether subsequent link state 561 * changes can be attributed to our reprogramming the PHY 562 */ 563 rge_phy_init(rgep); 564 if (rgep->chipid.mac_ver == MAC_VER_8168B_B || 565 rgep->chipid.mac_ver == MAC_VER_8168B_C) { 566 /* power up PHY for RTL8168B chipset */ 567 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 568 rge_mii_put16(rgep, PHY_0E_REG, 0x0000); 569 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 570 } 571 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 572 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 573 rge_mii_put16(rgep, MII_CONTROL, control); 574 575 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 576 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 577 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 578 } 579 580 void rge_phy_init(rge_t *rgep); 581 #pragma no_inline(rge_phy_init) 582 583 void 584 rge_phy_init(rge_t *rgep) 585 { 586 rgep->phy_mii_addr = 1; 587 588 /* 589 * Below phy config steps are copied from the Programming Guide 590 * (there's no detail comments for these steps.) 591 */ 592 switch (rgep->chipid.mac_ver) { 593 case MAC_VER_8169S_D: 594 case MAC_VER_8169S_E : 595 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 596 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 597 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 598 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 599 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 600 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 601 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 602 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 603 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 604 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 605 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 606 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 607 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 608 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 609 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 610 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 611 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 612 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 613 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 614 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 615 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 616 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 617 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 618 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 619 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 620 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 621 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 622 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 623 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 624 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 625 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 626 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 627 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 628 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 629 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 630 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 631 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 632 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 633 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 634 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 635 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 636 break; 637 638 case MAC_VER_8169SB: 639 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 640 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 641 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 642 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 643 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 644 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 645 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 646 break; 647 648 case MAC_VER_8169SC: 649 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 650 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); 651 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); 652 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); 653 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); 654 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); 655 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); 656 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); 657 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); 658 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); 659 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 660 rge_mii_put16(rgep, PHY_13_REG, 0x0600); 661 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 662 break; 663 664 case MAC_VER_8168: 665 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 666 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 667 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 668 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 669 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 670 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 671 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 672 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 673 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 674 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 675 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 676 break; 677 678 case MAC_VER_8168B_B: 679 case MAC_VER_8168B_C: 680 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 681 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 682 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 683 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 684 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 685 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 686 break; 687 } 688 } 689 690 void rge_chip_ident(rge_t *rgep); 691 #pragma no_inline(rge_chip_ident) 692 693 void 694 rge_chip_ident(rge_t *rgep) 695 { 696 chip_id_t *chip = &rgep->chipid; 697 uint32_t val32; 698 uint16_t val16; 699 700 /* 701 * Read and record MAC version 702 */ 703 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 704 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 705 chip->mac_ver = val32; 706 switch (chip->mac_ver) { 707 case MAC_VER_8168: 708 case MAC_VER_8168B_B: 709 case MAC_VER_8168B_C: 710 case MAC_VER_8101E: 711 case MAC_VER_8101E_B: 712 chip->is_pcie = B_TRUE; 713 break; 714 715 default: 716 chip->is_pcie = B_FALSE; 717 break; 718 } 719 720 /* 721 * Read and record PHY version 722 */ 723 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 724 val16 &= PHY_VER_MASK; 725 chip->phy_ver = val16; 726 727 /* set pci latency timer */ 728 if (chip->mac_ver == MAC_VER_8169 || 729 chip->mac_ver == MAC_VER_8169S_D || 730 chip->mac_ver == MAC_VER_8169SC) 731 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 732 733 if (chip->mac_ver == MAC_VER_8169SC) { 734 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); 735 val16 &= 0x0300; 736 if (val16 == 0x1) /* 66Mhz PCI */ 737 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff); 738 else if (val16 == 0x0) /* 33Mhz PCI */ 739 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00); 740 } 741 742 /* 743 * PCIE chipset require the Rx buffer start address must be 744 * 8-byte alignment and the Rx buffer size must be multiple of 8. 745 * We'll just use bcopy in receive procedure for the PCIE chipset. 746 */ 747 if (chip->is_pcie) { 748 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 749 if (rgep->default_mtu > ETHERMTU) { 750 rge_notice(rgep, "Jumbo packets not supported " 751 "for this PCIE chipset"); 752 rgep->default_mtu = ETHERMTU; 753 } 754 } 755 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 756 rgep->head_room = 0; 757 else 758 rgep->head_room = RGE_HEADROOM; 759 760 /* 761 * Initialize other variables. 762 */ 763 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 764 rgep->default_mtu = ETHERMTU; 765 if (rgep->default_mtu > ETHERMTU) { 766 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 767 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 768 rgep->ethmax_size = RGE_JUMBO_SIZE; 769 } else { 770 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 771 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 772 rgep->ethmax_size = ETHERMAX; 773 } 774 chip->rxconfig = RX_CONFIG_DEFAULT; 775 chip->txconfig = TX_CONFIG_DEFAULT; 776 777 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 778 rgep->ifname, chip->mac_ver, chip->phy_ver)); 779 } 780 781 /* 782 * Perform first-stage chip (re-)initialisation, using only config-space 783 * accesses: 784 * 785 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 786 * returning the data in the structure pointed to by <idp>. 787 * + Enable Memory Space accesses. 788 * + Enable Bus Mastering according. 789 */ 790 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 791 #pragma no_inline(rge_chip_cfg_init) 792 793 void 794 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 795 { 796 ddi_acc_handle_t handle; 797 uint16_t commd; 798 799 handle = rgep->cfg_handle; 800 801 /* 802 * Save PCI cache line size and subsystem vendor ID 803 */ 804 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 805 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 806 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 807 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 808 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 809 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 810 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 811 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 812 813 /* 814 * Turn on Master Enable (DMA) and IO Enable bits. 815 * Enable PCI Memory Space accesses 816 */ 817 commd = cidp->command; 818 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 819 pci_config_put16(handle, PCI_CONF_COMM, commd); 820 821 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 822 cidp->vendor, cidp->device, cidp->revision)); 823 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 824 cidp->subven, cidp->subdev)); 825 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 826 cidp->clsize, cidp->latency, cidp->command)); 827 } 828 829 int rge_chip_reset(rge_t *rgep); 830 #pragma no_inline(rge_chip_reset) 831 832 int 833 rge_chip_reset(rge_t *rgep) 834 { 835 int i; 836 uint8_t val8; 837 838 /* 839 * Chip should be in STOP state 840 */ 841 rge_reg_clr8(rgep, RT_COMMAND_REG, 842 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 843 844 /* 845 * Disable interrupt 846 */ 847 rgep->int_mask = INT_MASK_NONE; 848 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 849 850 /* 851 * Clear pended interrupt 852 */ 853 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 854 855 /* 856 * Reset chip 857 */ 858 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 859 860 /* 861 * Wait for reset success 862 */ 863 for (i = 0; i < CHIP_RESET_LOOP; i++) { 864 drv_usecwait(10); 865 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 866 if (!(val8 & RT_COMMAND_RESET)) { 867 rgep->rge_chip_state = RGE_CHIP_RESET; 868 return (0); 869 } 870 } 871 RGE_REPORT((rgep, "rge_chip_reset fail.")); 872 return (-1); 873 } 874 875 void rge_chip_init(rge_t *rgep); 876 #pragma no_inline(rge_chip_init) 877 878 void 879 rge_chip_init(rge_t *rgep) 880 { 881 uint32_t val32; 882 uint32_t val16; 883 uint32_t *hashp; 884 chip_id_t *chip = &rgep->chipid; 885 886 if (chip->is_pcie) { 887 /* 888 * Increase the threshold voltage of RX sensitivity 889 */ 890 if (chip->mac_ver != MAC_VER_8168 && 891 chip->mac_ver != MAC_VER_8101E_B) 892 rge_ephy_put16(rgep, 0x01, 0x1bd3); 893 894 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 895 val16 = 0x12<<8 | val16; 896 if (rgep->chipid.mac_ver != MAC_VER_8101E && 897 rgep->chipid.mac_ver != MAC_VER_8101E_B && 898 rgep->chipid.mac_ver != MAC_VER_8101E_C && 899 rgep->chipid.mac_ver != MAC_VER_8168B_C) { 900 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 901 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 902 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 903 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 904 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 905 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 906 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 907 val32 |= 0x7000; 908 val32 &= 0xffff5fff; 909 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 910 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 911 } 912 } 913 914 /* 915 * Config MII register 916 */ 917 rgep->param_link_up = LINK_STATE_DOWN; 918 rge_phy_update(rgep); 919 920 /* 921 * Enable Rx checksum offload. 922 * Then for vlan support, we must enable receive vlan de-tagging. 923 * Otherwise, there'll be checksum error. 924 */ 925 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 926 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 927 if (chip->mac_ver == MAC_VER_8169S_D) { 928 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 929 rge_reg_put8(rgep, RESV_82_REG, 0x01); 930 } 931 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 932 933 /* 934 * Start transmit/receive before set tx/rx configuration register 935 */ 936 if (!chip->is_pcie) 937 rge_reg_set8(rgep, RT_COMMAND_REG, 938 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 939 940 /* 941 * Set dump tally counter register 942 */ 943 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 944 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 945 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 946 val32 &= DUMP_COUNTER_REG_RESV; 947 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 948 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 949 950 /* 951 * Change to config register write enable mode 952 */ 953 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 954 955 /* 956 * Set Tx/Rx maximum packet size 957 */ 958 if (rgep->default_mtu > ETHERMTU) { 959 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 960 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 961 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) { 962 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 963 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 964 } else { 965 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E); 966 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E); 967 } 968 969 /* 970 * Set receive configuration register 971 */ 972 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 973 val32 &= RX_CONFIG_REG_RESV; 974 if (rgep->promisc) 975 val32 |= RX_ACCEPT_ALL_PKT; 976 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 977 978 /* 979 * Set transmit configuration register 980 */ 981 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 982 val32 &= TX_CONFIG_REG_RESV; 983 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 984 985 /* 986 * Set Tx/Rx descriptor register 987 */ 988 val32 = rgep->tx_desc.cookie.dmac_laddress; 989 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 990 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 991 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 992 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 993 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 994 val32 = rgep->rx_desc.cookie.dmac_laddress; 995 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 996 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 997 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 998 999 /* 1000 * Suggested setting from Realtek 1001 */ 1002 if (rgep->chipid.mac_ver != MAC_VER_8101E) 1003 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 1004 else 1005 rge_reg_put16(rgep, RESV_E2_REG, 0x0000); 1006 1007 /* 1008 * Set multicast register 1009 */ 1010 hashp = (uint32_t *)rgep->mcast_hash; 1011 rge_reg_put32(rgep, MULTICAST_0_REG, hashp[0]); 1012 rge_reg_put32(rgep, MULTICAST_4_REG, hashp[1]); 1013 1014 /* 1015 * Msic register setting: 1016 * -- Missed packet counter: clear it 1017 * -- TimerInt Register 1018 * -- Timer count register 1019 */ 1020 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1021 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1022 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1023 1024 /* 1025 * disable the Unicast Wakeup Frame capability 1026 */ 1027 rge_reg_clr8(rgep, RT_CONFIG_5_REG, RT_UNI_WAKE_FRAME); 1028 1029 /* 1030 * Return to normal network/host communication mode 1031 */ 1032 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1033 drv_usecwait(20); 1034 } 1035 1036 /* 1037 * rge_chip_start() -- start the chip transmitting and/or receiving, 1038 * including enabling interrupts 1039 */ 1040 void rge_chip_start(rge_t *rgep); 1041 #pragma no_inline(rge_chip_start) 1042 1043 void 1044 rge_chip_start(rge_t *rgep) 1045 { 1046 /* 1047 * Clear statistics 1048 */ 1049 bzero(&rgep->stats, sizeof (rge_stats_t)); 1050 DMA_ZERO(rgep->dma_area_stats); 1051 1052 /* 1053 * Start transmit/receive 1054 */ 1055 rge_reg_set8(rgep, RT_COMMAND_REG, 1056 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1057 1058 /* 1059 * Enable interrupt 1060 */ 1061 rgep->int_mask = RGE_INT_MASK; 1062 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1063 1064 /* 1065 * All done! 1066 */ 1067 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1068 } 1069 1070 /* 1071 * rge_chip_stop() -- stop board receiving 1072 * 1073 * Since this function is also invoked by rge_quiesce(), it 1074 * must not block; also, no tracing or logging takes place 1075 * when invoked by rge_quiesce(). 1076 */ 1077 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1078 #pragma no_inline(rge_chip_stop) 1079 1080 void 1081 rge_chip_stop(rge_t *rgep, boolean_t fault) 1082 { 1083 /* 1084 * Disable interrupt 1085 */ 1086 rgep->int_mask = INT_MASK_NONE; 1087 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1088 1089 /* 1090 * Clear pended interrupt 1091 */ 1092 if (!rgep->suspended) { 1093 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1094 } 1095 1096 /* 1097 * Stop the board and disable transmit/receive 1098 */ 1099 rge_reg_clr8(rgep, RT_COMMAND_REG, 1100 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1101 1102 if (fault) 1103 rgep->rge_chip_state = RGE_CHIP_FAULT; 1104 else 1105 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1106 } 1107 1108 /* 1109 * rge_get_mac_addr() -- get the MAC address on NIC 1110 */ 1111 static void rge_get_mac_addr(rge_t *rgep); 1112 #pragma inline(rge_get_mac_addr) 1113 1114 static void 1115 rge_get_mac_addr(rge_t *rgep) 1116 { 1117 uint8_t *macaddr = rgep->netaddr; 1118 uint32_t val32; 1119 1120 /* 1121 * Read first 4-byte of mac address 1122 */ 1123 val32 = rge_reg_get32(rgep, ID_0_REG); 1124 macaddr[0] = val32 & 0xff; 1125 val32 = val32 >> 8; 1126 macaddr[1] = val32 & 0xff; 1127 val32 = val32 >> 8; 1128 macaddr[2] = val32 & 0xff; 1129 val32 = val32 >> 8; 1130 macaddr[3] = val32 & 0xff; 1131 1132 /* 1133 * Read last 2-byte of mac address 1134 */ 1135 val32 = rge_reg_get32(rgep, ID_4_REG); 1136 macaddr[4] = val32 & 0xff; 1137 val32 = val32 >> 8; 1138 macaddr[5] = val32 & 0xff; 1139 } 1140 1141 static void rge_set_mac_addr(rge_t *rgep); 1142 #pragma inline(rge_set_mac_addr) 1143 1144 static void 1145 rge_set_mac_addr(rge_t *rgep) 1146 { 1147 uint8_t *p = rgep->netaddr; 1148 uint32_t val32; 1149 1150 /* 1151 * Change to config register write enable mode 1152 */ 1153 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1154 1155 /* 1156 * Get first 4 bytes of mac address 1157 */ 1158 val32 = p[3]; 1159 val32 = val32 << 8; 1160 val32 |= p[2]; 1161 val32 = val32 << 8; 1162 val32 |= p[1]; 1163 val32 = val32 << 8; 1164 val32 |= p[0]; 1165 1166 /* 1167 * Set first 4 bytes of mac address 1168 */ 1169 rge_reg_put32(rgep, ID_0_REG, val32); 1170 1171 /* 1172 * Get last 2 bytes of mac address 1173 */ 1174 val32 = p[5]; 1175 val32 = val32 << 8; 1176 val32 |= p[4]; 1177 1178 /* 1179 * Set last 2 bytes of mac address 1180 */ 1181 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1182 rge_reg_put32(rgep, ID_4_REG, val32); 1183 1184 /* 1185 * Return to normal network/host communication mode 1186 */ 1187 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1188 } 1189 1190 static void rge_set_multi_addr(rge_t *rgep); 1191 #pragma inline(rge_set_multi_addr) 1192 1193 static void 1194 rge_set_multi_addr(rge_t *rgep) 1195 { 1196 uint32_t *hashp; 1197 1198 hashp = (uint32_t *)rgep->mcast_hash; 1199 1200 /* 1201 * Change to config register write enable mode 1202 */ 1203 if (rgep->chipid.mac_ver == MAC_VER_8169SC) { 1204 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1205 } 1206 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1207 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1208 1209 /* 1210 * Return to normal network/host communication mode 1211 */ 1212 if (rgep->chipid.mac_ver == MAC_VER_8169SC) { 1213 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1214 } 1215 } 1216 1217 static void rge_set_promisc(rge_t *rgep); 1218 #pragma inline(rge_set_promisc) 1219 1220 static void 1221 rge_set_promisc(rge_t *rgep) 1222 { 1223 if (rgep->promisc) 1224 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1225 else 1226 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1227 } 1228 1229 /* 1230 * rge_chip_sync() -- program the chip with the unicast MAC address, 1231 * the multicast hash table, the required level of promiscuity, and 1232 * the current loopback mode ... 1233 */ 1234 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1235 #pragma no_inline(rge_chip_sync) 1236 1237 void 1238 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1239 { 1240 switch (todo) { 1241 case RGE_GET_MAC: 1242 rge_get_mac_addr(rgep); 1243 break; 1244 case RGE_SET_MAC: 1245 /* Reprogram the unicast MAC address(es) ... */ 1246 rge_set_mac_addr(rgep); 1247 break; 1248 case RGE_SET_MUL: 1249 /* Reprogram the hashed multicast address table ... */ 1250 rge_set_multi_addr(rgep); 1251 break; 1252 case RGE_SET_PROMISC: 1253 /* Set or clear the PROMISCUOUS mode bit */ 1254 rge_set_promisc(rgep); 1255 break; 1256 default: 1257 break; 1258 } 1259 } 1260 1261 void rge_chip_blank(void *arg, time_t ticks, uint_t count); 1262 #pragma no_inline(rge_chip_blank) 1263 1264 void 1265 rge_chip_blank(void *arg, time_t ticks, uint_t count) 1266 { 1267 _NOTE(ARGUNUSED(arg, ticks, count)); 1268 } 1269 1270 void rge_tx_trigger(rge_t *rgep); 1271 #pragma no_inline(rge_tx_trigger) 1272 1273 void 1274 rge_tx_trigger(rge_t *rgep) 1275 { 1276 rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1277 } 1278 1279 void rge_hw_stats_dump(rge_t *rgep); 1280 #pragma no_inline(rge_tx_trigger) 1281 1282 void 1283 rge_hw_stats_dump(rge_t *rgep) 1284 { 1285 int i = 0; 1286 1287 while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) { 1288 drv_usecwait(100); 1289 if (++i > STATS_DUMP_LOOP) { 1290 RGE_DEBUG(("rge h/w statistics dump fail!")); 1291 rgep->rge_chip_state = RGE_CHIP_ERROR; 1292 return; 1293 } 1294 } 1295 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1296 1297 /* 1298 * Start H/W statistics dump for RTL8169 chip 1299 */ 1300 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1301 } 1302 1303 /* 1304 * ========== Hardware interrupt handler ========== 1305 */ 1306 1307 #undef RGE_DBG 1308 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1309 1310 static void rge_wake_factotum(rge_t *rgep); 1311 #pragma inline(rge_wake_factotum) 1312 1313 static void 1314 rge_wake_factotum(rge_t *rgep) 1315 { 1316 if (rgep->factotum_flag == 0) { 1317 rgep->factotum_flag = 1; 1318 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1319 } 1320 } 1321 1322 /* 1323 * rge_intr() -- handle chip interrupts 1324 */ 1325 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1326 #pragma no_inline(rge_intr) 1327 1328 uint_t 1329 rge_intr(caddr_t arg1, caddr_t arg2) 1330 { 1331 rge_t *rgep = (rge_t *)arg1; 1332 uint16_t int_status; 1333 1334 _NOTE(ARGUNUSED(arg2)) 1335 1336 mutex_enter(rgep->genlock); 1337 1338 if (rgep->suspended) { 1339 mutex_exit(rgep->genlock); 1340 return (DDI_INTR_UNCLAIMED); 1341 } 1342 1343 /* 1344 * Was this interrupt caused by our device... 1345 */ 1346 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1347 if (!(int_status & rgep->int_mask)) { 1348 mutex_exit(rgep->genlock); 1349 return (DDI_INTR_UNCLAIMED); 1350 /* indicate it wasn't our interrupt */ 1351 } 1352 rgep->stats.intr++; 1353 1354 /* 1355 * Clear interrupt 1356 * For PCIE chipset, we need disable interrupt first. 1357 */ 1358 if (rgep->chipid.is_pcie) 1359 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1360 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1361 1362 /* 1363 * Cable link change interrupt 1364 */ 1365 if (int_status & LINK_CHANGE_INT) { 1366 rge_chip_cyclic(rgep); 1367 } 1368 1369 mutex_exit(rgep->genlock); 1370 1371 /* 1372 * Receive interrupt 1373 */ 1374 if (int_status & RGE_RX_INT) 1375 rge_receive(rgep); 1376 1377 /* 1378 * Re-enable interrupt for PCIE chipset 1379 */ 1380 if (rgep->chipid.is_pcie) 1381 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1382 1383 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1384 } 1385 1386 /* 1387 * ========== Factotum, implemented as a softint handler ========== 1388 */ 1389 1390 #undef RGE_DBG 1391 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1392 1393 static boolean_t rge_factotum_link_check(rge_t *rgep); 1394 #pragma no_inline(rge_factotum_link_check) 1395 1396 static boolean_t 1397 rge_factotum_link_check(rge_t *rgep) 1398 { 1399 uint8_t media_status; 1400 int32_t link; 1401 1402 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1403 link = (media_status & PHY_STATUS_LINK_UP) ? 1404 LINK_STATE_UP : LINK_STATE_DOWN; 1405 if (rgep->param_link_up != link) { 1406 /* 1407 * Link change. 1408 */ 1409 rgep->param_link_up = link; 1410 1411 if (link == LINK_STATE_UP) { 1412 if (media_status & PHY_STATUS_1000MF) { 1413 rgep->param_link_speed = RGE_SPEED_1000M; 1414 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1415 } else { 1416 rgep->param_link_speed = 1417 (media_status & PHY_STATUS_100M) ? 1418 RGE_SPEED_100M : RGE_SPEED_10M; 1419 rgep->param_link_duplex = 1420 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1421 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1422 } 1423 } 1424 return (B_TRUE); 1425 } 1426 return (B_FALSE); 1427 } 1428 1429 /* 1430 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1431 */ 1432 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1433 #pragma no_inline(rge_factotum_stall_check) 1434 1435 static boolean_t 1436 rge_factotum_stall_check(rge_t *rgep) 1437 { 1438 uint32_t dogval; 1439 1440 ASSERT(mutex_owned(rgep->genlock)); 1441 1442 /* 1443 * Specific check for Tx stall ... 1444 * 1445 * The 'watchdog' counter is incremented whenever a packet 1446 * is queued, reset to 1 when some (but not all) buffers 1447 * are reclaimed, reset to 0 (disabled) when all buffers 1448 * are reclaimed, and shifted left here. If it exceeds the 1449 * threshold value, the chip is assumed to have stalled and 1450 * is put into the ERROR state. The factotum will then reset 1451 * it on the next pass. 1452 * 1453 * All of which should ensure that we don't get into a state 1454 * where packets are left pending indefinitely! 1455 */ 1456 if (rgep->resched_needed) 1457 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1458 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1459 if (dogval < rge_watchdog_count) 1460 return (B_FALSE); 1461 1462 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1463 return (B_TRUE); 1464 1465 } 1466 1467 /* 1468 * The factotum is woken up when there's something to do that we'd rather 1469 * not do from inside a hardware interrupt handler or high-level cyclic. 1470 * Its two main tasks are: 1471 * reset & restart the chip after an error 1472 * check the link status whenever necessary 1473 */ 1474 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1475 #pragma no_inline(rge_chip_factotum) 1476 1477 uint_t 1478 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1479 { 1480 rge_t *rgep; 1481 uint_t result; 1482 boolean_t error; 1483 boolean_t linkchg; 1484 1485 rgep = (rge_t *)arg1; 1486 _NOTE(ARGUNUSED(arg2)) 1487 1488 if (rgep->factotum_flag == 0) 1489 return (DDI_INTR_UNCLAIMED); 1490 1491 rgep->factotum_flag = 0; 1492 result = DDI_INTR_CLAIMED; 1493 error = B_FALSE; 1494 linkchg = B_FALSE; 1495 1496 mutex_enter(rgep->genlock); 1497 switch (rgep->rge_chip_state) { 1498 default: 1499 break; 1500 1501 case RGE_CHIP_RUNNING: 1502 linkchg = rge_factotum_link_check(rgep); 1503 error = rge_factotum_stall_check(rgep); 1504 break; 1505 1506 case RGE_CHIP_ERROR: 1507 error = B_TRUE; 1508 break; 1509 1510 case RGE_CHIP_FAULT: 1511 /* 1512 * Fault detected, time to reset ... 1513 */ 1514 if (rge_autorecover) { 1515 RGE_REPORT((rgep, "automatic recovery activated")); 1516 rge_restart(rgep); 1517 } 1518 break; 1519 } 1520 1521 /* 1522 * If an error is detected, stop the chip now, marking it as 1523 * faulty, so that it will be reset next time through ... 1524 */ 1525 if (error) 1526 rge_chip_stop(rgep, B_TRUE); 1527 mutex_exit(rgep->genlock); 1528 1529 /* 1530 * If the link state changed, tell the world about it. 1531 * Note: can't do this while still holding the mutex. 1532 */ 1533 if (linkchg) 1534 mac_link_update(rgep->mh, rgep->param_link_up); 1535 1536 return (result); 1537 } 1538 1539 /* 1540 * High-level cyclic handler 1541 * 1542 * This routine schedules a (low-level) softint callback to the 1543 * factotum, and prods the chip to update the status block (which 1544 * will cause a hardware interrupt when complete). 1545 */ 1546 void rge_chip_cyclic(void *arg); 1547 #pragma no_inline(rge_chip_cyclic) 1548 1549 void 1550 rge_chip_cyclic(void *arg) 1551 { 1552 rge_t *rgep; 1553 1554 rgep = arg; 1555 1556 switch (rgep->rge_chip_state) { 1557 default: 1558 return; 1559 1560 case RGE_CHIP_RUNNING: 1561 rge_phy_check(rgep); 1562 break; 1563 1564 case RGE_CHIP_FAULT: 1565 case RGE_CHIP_ERROR: 1566 break; 1567 } 1568 1569 rge_wake_factotum(rgep); 1570 } 1571 1572 1573 /* 1574 * ========== Ioctl subfunctions ========== 1575 */ 1576 1577 #undef RGE_DBG 1578 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1579 1580 #if RGE_DEBUGGING || RGE_DO_PPIO 1581 1582 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1583 #pragma no_inline(rge_chip_peek_cfg) 1584 1585 static void 1586 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1587 { 1588 uint64_t regval; 1589 uint64_t regno; 1590 1591 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1592 (void *)rgep, (void *)ppd)); 1593 1594 regno = ppd->pp_acc_offset; 1595 1596 switch (ppd->pp_acc_size) { 1597 case 1: 1598 regval = pci_config_get8(rgep->cfg_handle, regno); 1599 break; 1600 1601 case 2: 1602 regval = pci_config_get16(rgep->cfg_handle, regno); 1603 break; 1604 1605 case 4: 1606 regval = pci_config_get32(rgep->cfg_handle, regno); 1607 break; 1608 1609 case 8: 1610 regval = pci_config_get64(rgep->cfg_handle, regno); 1611 break; 1612 } 1613 1614 ppd->pp_acc_data = regval; 1615 } 1616 1617 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1618 #pragma no_inline(rge_chip_poke_cfg) 1619 1620 static void 1621 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1622 { 1623 uint64_t regval; 1624 uint64_t regno; 1625 1626 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1627 (void *)rgep, (void *)ppd)); 1628 1629 regno = ppd->pp_acc_offset; 1630 regval = ppd->pp_acc_data; 1631 1632 switch (ppd->pp_acc_size) { 1633 case 1: 1634 pci_config_put8(rgep->cfg_handle, regno, regval); 1635 break; 1636 1637 case 2: 1638 pci_config_put16(rgep->cfg_handle, regno, regval); 1639 break; 1640 1641 case 4: 1642 pci_config_put32(rgep->cfg_handle, regno, regval); 1643 break; 1644 1645 case 8: 1646 pci_config_put64(rgep->cfg_handle, regno, regval); 1647 break; 1648 } 1649 } 1650 1651 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1652 #pragma no_inline(rge_chip_peek_reg) 1653 1654 static void 1655 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1656 { 1657 uint64_t regval; 1658 void *regaddr; 1659 1660 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1661 (void *)rgep, (void *)ppd)); 1662 1663 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1664 1665 switch (ppd->pp_acc_size) { 1666 case 1: 1667 regval = ddi_get8(rgep->io_handle, regaddr); 1668 break; 1669 1670 case 2: 1671 regval = ddi_get16(rgep->io_handle, regaddr); 1672 break; 1673 1674 case 4: 1675 regval = ddi_get32(rgep->io_handle, regaddr); 1676 break; 1677 1678 case 8: 1679 regval = ddi_get64(rgep->io_handle, regaddr); 1680 break; 1681 } 1682 1683 ppd->pp_acc_data = regval; 1684 } 1685 1686 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1687 #pragma no_inline(rge_chip_peek_reg) 1688 1689 static void 1690 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1691 { 1692 uint64_t regval; 1693 void *regaddr; 1694 1695 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1696 (void *)rgep, (void *)ppd)); 1697 1698 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1699 regval = ppd->pp_acc_data; 1700 1701 switch (ppd->pp_acc_size) { 1702 case 1: 1703 ddi_put8(rgep->io_handle, regaddr, regval); 1704 break; 1705 1706 case 2: 1707 ddi_put16(rgep->io_handle, regaddr, regval); 1708 break; 1709 1710 case 4: 1711 ddi_put32(rgep->io_handle, regaddr, regval); 1712 break; 1713 1714 case 8: 1715 ddi_put64(rgep->io_handle, regaddr, regval); 1716 break; 1717 } 1718 } 1719 1720 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1721 #pragma no_inline(rge_chip_peek_mii) 1722 1723 static void 1724 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1725 { 1726 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1727 (void *)rgep, (void *)ppd)); 1728 1729 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1730 } 1731 1732 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1733 #pragma no_inline(rge_chip_poke_mii) 1734 1735 static void 1736 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1737 { 1738 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1739 (void *)rgep, (void *)ppd)); 1740 1741 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1742 } 1743 1744 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1745 #pragma no_inline(rge_chip_peek_mem) 1746 1747 static void 1748 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1749 { 1750 uint64_t regval; 1751 void *vaddr; 1752 1753 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1754 (void *)rgep, (void *)ppd)); 1755 1756 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1757 1758 switch (ppd->pp_acc_size) { 1759 case 1: 1760 regval = *(uint8_t *)vaddr; 1761 break; 1762 1763 case 2: 1764 regval = *(uint16_t *)vaddr; 1765 break; 1766 1767 case 4: 1768 regval = *(uint32_t *)vaddr; 1769 break; 1770 1771 case 8: 1772 regval = *(uint64_t *)vaddr; 1773 break; 1774 } 1775 1776 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1777 (void *)rgep, (void *)ppd, regval, vaddr)); 1778 1779 ppd->pp_acc_data = regval; 1780 } 1781 1782 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1783 #pragma no_inline(rge_chip_poke_mem) 1784 1785 static void 1786 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1787 { 1788 uint64_t regval; 1789 void *vaddr; 1790 1791 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1792 (void *)rgep, (void *)ppd)); 1793 1794 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1795 regval = ppd->pp_acc_data; 1796 1797 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1798 (void *)rgep, (void *)ppd, regval, vaddr)); 1799 1800 switch (ppd->pp_acc_size) { 1801 case 1: 1802 *(uint8_t *)vaddr = (uint8_t)regval; 1803 break; 1804 1805 case 2: 1806 *(uint16_t *)vaddr = (uint16_t)regval; 1807 break; 1808 1809 case 4: 1810 *(uint32_t *)vaddr = (uint32_t)regval; 1811 break; 1812 1813 case 8: 1814 *(uint64_t *)vaddr = (uint64_t)regval; 1815 break; 1816 } 1817 } 1818 1819 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1820 struct iocblk *iocp); 1821 #pragma no_inline(rge_pp_ioctl) 1822 1823 static enum ioc_reply 1824 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1825 { 1826 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1827 rge_peekpoke_t *ppd; 1828 dma_area_t *areap; 1829 uint64_t sizemask; 1830 uint64_t mem_va; 1831 uint64_t maxoff; 1832 boolean_t peek; 1833 1834 switch (cmd) { 1835 default: 1836 /* NOTREACHED */ 1837 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 1838 return (IOC_INVAL); 1839 1840 case RGE_PEEK: 1841 peek = B_TRUE; 1842 break; 1843 1844 case RGE_POKE: 1845 peek = B_FALSE; 1846 break; 1847 } 1848 1849 /* 1850 * Validate format of ioctl 1851 */ 1852 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 1853 return (IOC_INVAL); 1854 if (mp->b_cont == NULL) 1855 return (IOC_INVAL); 1856 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 1857 1858 /* 1859 * Validate request parameters 1860 */ 1861 switch (ppd->pp_acc_space) { 1862 default: 1863 return (IOC_INVAL); 1864 1865 case RGE_PP_SPACE_CFG: 1866 /* 1867 * Config space 1868 */ 1869 sizemask = 8|4|2|1; 1870 mem_va = 0; 1871 maxoff = PCI_CONF_HDR_SIZE; 1872 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 1873 break; 1874 1875 case RGE_PP_SPACE_REG: 1876 /* 1877 * Memory-mapped I/O space 1878 */ 1879 sizemask = 8|4|2|1; 1880 mem_va = 0; 1881 maxoff = RGE_REGISTER_MAX; 1882 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 1883 break; 1884 1885 case RGE_PP_SPACE_MII: 1886 /* 1887 * PHY's MII registers 1888 * NB: all PHY registers are two bytes, but the 1889 * addresses increment in ones (word addressing). 1890 * So we scale the address here, then undo the 1891 * transformation inside the peek/poke functions. 1892 */ 1893 ppd->pp_acc_offset *= 2; 1894 sizemask = 2; 1895 mem_va = 0; 1896 maxoff = (MII_MAXREG+1)*2; 1897 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 1898 break; 1899 1900 case RGE_PP_SPACE_RGE: 1901 /* 1902 * RGE data structure! 1903 */ 1904 sizemask = 8|4|2|1; 1905 mem_va = (uintptr_t)rgep; 1906 maxoff = sizeof (*rgep); 1907 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1908 break; 1909 1910 case RGE_PP_SPACE_STATISTICS: 1911 case RGE_PP_SPACE_TXDESC: 1912 case RGE_PP_SPACE_TXBUFF: 1913 case RGE_PP_SPACE_RXDESC: 1914 case RGE_PP_SPACE_RXBUFF: 1915 /* 1916 * Various DMA_AREAs 1917 */ 1918 switch (ppd->pp_acc_space) { 1919 case RGE_PP_SPACE_TXDESC: 1920 areap = &rgep->dma_area_txdesc; 1921 break; 1922 case RGE_PP_SPACE_RXDESC: 1923 areap = &rgep->dma_area_rxdesc; 1924 break; 1925 case RGE_PP_SPACE_STATISTICS: 1926 areap = &rgep->dma_area_stats; 1927 break; 1928 } 1929 1930 sizemask = 8|4|2|1; 1931 mem_va = (uintptr_t)areap->mem_va; 1932 maxoff = areap->alength; 1933 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1934 break; 1935 } 1936 1937 switch (ppd->pp_acc_size) { 1938 default: 1939 return (IOC_INVAL); 1940 1941 case 8: 1942 case 4: 1943 case 2: 1944 case 1: 1945 if ((ppd->pp_acc_size & sizemask) == 0) 1946 return (IOC_INVAL); 1947 break; 1948 } 1949 1950 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1951 return (IOC_INVAL); 1952 1953 if (ppd->pp_acc_offset >= maxoff) 1954 return (IOC_INVAL); 1955 1956 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1957 return (IOC_INVAL); 1958 1959 /* 1960 * All OK - go do it! 1961 */ 1962 ppd->pp_acc_offset += mem_va; 1963 (*ppfn)(rgep, ppd); 1964 return (peek ? IOC_REPLY : IOC_ACK); 1965 } 1966 1967 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1968 struct iocblk *iocp); 1969 #pragma no_inline(rge_diag_ioctl) 1970 1971 static enum ioc_reply 1972 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1973 { 1974 ASSERT(mutex_owned(rgep->genlock)); 1975 1976 switch (cmd) { 1977 default: 1978 /* NOTREACHED */ 1979 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 1980 return (IOC_INVAL); 1981 1982 case RGE_DIAG: 1983 /* 1984 * Currently a no-op 1985 */ 1986 return (IOC_ACK); 1987 1988 case RGE_PEEK: 1989 case RGE_POKE: 1990 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 1991 1992 case RGE_PHY_RESET: 1993 return (IOC_RESTART_ACK); 1994 1995 case RGE_SOFT_RESET: 1996 case RGE_HARD_RESET: 1997 /* 1998 * Reset and reinitialise the 570x hardware 1999 */ 2000 rge_restart(rgep); 2001 return (IOC_ACK); 2002 } 2003 2004 /* NOTREACHED */ 2005 } 2006 2007 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2008 2009 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2010 struct iocblk *iocp); 2011 #pragma no_inline(rge_mii_ioctl) 2012 2013 static enum ioc_reply 2014 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2015 { 2016 struct rge_mii_rw *miirwp; 2017 2018 /* 2019 * Validate format of ioctl 2020 */ 2021 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2022 return (IOC_INVAL); 2023 if (mp->b_cont == NULL) 2024 return (IOC_INVAL); 2025 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2026 2027 /* 2028 * Validate request parameters ... 2029 */ 2030 if (miirwp->mii_reg > MII_MAXREG) 2031 return (IOC_INVAL); 2032 2033 switch (cmd) { 2034 default: 2035 /* NOTREACHED */ 2036 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2037 return (IOC_INVAL); 2038 2039 case RGE_MII_READ: 2040 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2041 return (IOC_REPLY); 2042 2043 case RGE_MII_WRITE: 2044 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2045 return (IOC_ACK); 2046 } 2047 2048 /* NOTREACHED */ 2049 } 2050 2051 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2052 struct iocblk *iocp); 2053 #pragma no_inline(rge_chip_ioctl) 2054 2055 enum ioc_reply 2056 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2057 { 2058 int cmd; 2059 2060 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2061 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2062 2063 ASSERT(mutex_owned(rgep->genlock)); 2064 2065 cmd = iocp->ioc_cmd; 2066 switch (cmd) { 2067 default: 2068 /* NOTREACHED */ 2069 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2070 return (IOC_INVAL); 2071 2072 case RGE_DIAG: 2073 case RGE_PEEK: 2074 case RGE_POKE: 2075 case RGE_PHY_RESET: 2076 case RGE_SOFT_RESET: 2077 case RGE_HARD_RESET: 2078 #if RGE_DEBUGGING || RGE_DO_PPIO 2079 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2080 #else 2081 return (IOC_INVAL); 2082 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2083 2084 case RGE_MII_READ: 2085 case RGE_MII_WRITE: 2086 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2087 2088 } 2089 2090 /* NOTREACHED */ 2091 } 2092