1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include "rge.h" 27 28 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 29 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 30 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 31 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 32 33 /* 34 * Patchable globals: 35 * 36 * rge_autorecover 37 * Enables/disables automatic recovery after fault detection 38 */ 39 static uint32_t rge_autorecover = 1; 40 41 /* 42 * globals: 43 */ 44 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 45 static uint32_t rge_watchdog_count = 1 << 16; 46 47 /* 48 * Operating register get/set access routines 49 */ 50 51 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 52 #pragma inline(rge_reg_get32) 53 54 static uint32_t 55 rge_reg_get32(rge_t *rgep, uintptr_t regno) 56 { 57 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 58 (void *)rgep, regno)); 59 60 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 61 } 62 63 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 64 #pragma inline(rge_reg_put32) 65 66 static void 67 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 68 { 69 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 70 (void *)rgep, regno, data)); 71 72 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 73 } 74 75 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 76 #pragma inline(rge_reg_set32) 77 78 static void 79 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 80 { 81 uint32_t regval; 82 83 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 84 (void *)rgep, regno, bits)); 85 86 regval = rge_reg_get32(rgep, regno); 87 regval |= bits; 88 rge_reg_put32(rgep, regno, regval); 89 } 90 91 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 92 #pragma inline(rge_reg_clr32) 93 94 static void 95 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 96 { 97 uint32_t regval; 98 99 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 100 (void *)rgep, regno, bits)); 101 102 regval = rge_reg_get32(rgep, regno); 103 regval &= ~bits; 104 rge_reg_put32(rgep, regno, regval); 105 } 106 107 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 108 #pragma inline(rge_reg_get16) 109 110 static uint16_t 111 rge_reg_get16(rge_t *rgep, uintptr_t regno) 112 { 113 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 114 (void *)rgep, regno)); 115 116 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 117 } 118 119 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 120 #pragma inline(rge_reg_put16) 121 122 static void 123 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 124 { 125 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 126 (void *)rgep, regno, data)); 127 128 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 129 } 130 131 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 132 #pragma inline(rge_reg_get8) 133 134 static uint8_t 135 rge_reg_get8(rge_t *rgep, uintptr_t regno) 136 { 137 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 138 (void *)rgep, regno)); 139 140 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 141 } 142 143 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 144 #pragma inline(rge_reg_put8) 145 146 static void 147 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 148 { 149 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 150 (void *)rgep, regno, data)); 151 152 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 153 } 154 155 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 156 #pragma inline(rge_reg_set8) 157 158 static void 159 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 160 { 161 uint8_t regval; 162 163 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 164 (void *)rgep, regno, bits)); 165 166 regval = rge_reg_get8(rgep, regno); 167 regval |= bits; 168 rge_reg_put8(rgep, regno, regval); 169 } 170 171 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 172 #pragma inline(rge_reg_clr8) 173 174 static void 175 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 176 { 177 uint8_t regval; 178 179 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 180 (void *)rgep, regno, bits)); 181 182 regval = rge_reg_get8(rgep, regno); 183 regval &= ~bits; 184 rge_reg_put8(rgep, regno, regval); 185 } 186 187 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 188 #pragma no_inline(rge_mii_get16) 189 190 uint16_t 191 rge_mii_get16(rge_t *rgep, uintptr_t mii) 192 { 193 uint32_t regval; 194 uint32_t val32; 195 uint32_t i; 196 197 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 198 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 199 200 /* 201 * Waiting for PHY reading OK 202 */ 203 for (i = 0; i < PHY_RESET_LOOP; i++) { 204 drv_usecwait(1000); 205 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 206 if (val32 & PHY_ACCESS_WR_FLAG) 207 return ((uint16_t)(val32 & 0xffff)); 208 } 209 210 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 211 return ((uint16_t)~0u); 212 } 213 214 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 215 #pragma no_inline(rge_mii_put16) 216 217 void 218 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 219 { 220 uint32_t regval; 221 uint32_t val32; 222 uint32_t i; 223 224 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 225 regval |= data & PHY_DATA_MASK; 226 regval |= PHY_ACCESS_WR_FLAG; 227 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 228 229 /* 230 * Waiting for PHY writing OK 231 */ 232 for (i = 0; i < PHY_RESET_LOOP; i++) { 233 drv_usecwait(1000); 234 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 235 if (!(val32 & PHY_ACCESS_WR_FLAG)) 236 return; 237 } 238 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 239 mii, data)); 240 } 241 242 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 243 #pragma no_inline(rge_ephy_put16) 244 245 void 246 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 247 { 248 uint32_t regval; 249 uint32_t val32; 250 uint32_t i; 251 252 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 253 regval |= data & EPHY_DATA_MASK; 254 regval |= EPHY_ACCESS_WR_FLAG; 255 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 256 257 /* 258 * Waiting for PHY writing OK 259 */ 260 for (i = 0; i < PHY_RESET_LOOP; i++) { 261 drv_usecwait(1000); 262 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 263 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 264 return; 265 } 266 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 267 emii, data)); 268 } 269 270 /* 271 * Atomically shift a 32-bit word left, returning 272 * the value it had *before* the shift was applied 273 */ 274 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 275 #pragma inline(rge_mii_put16) 276 277 static uint32_t 278 rge_atomic_shl32(uint32_t *sp, uint_t count) 279 { 280 uint32_t oldval; 281 uint32_t newval; 282 283 /* ATOMICALLY */ 284 do { 285 oldval = *sp; 286 newval = oldval << count; 287 } while (cas32(sp, oldval, newval) != oldval); 288 289 return (oldval); 290 } 291 292 /* 293 * PHY operation routines 294 */ 295 #if RGE_DEBUGGING 296 297 void 298 rge_phydump(rge_t *rgep) 299 { 300 uint16_t regs[32]; 301 int i; 302 303 ASSERT(mutex_owned(rgep->genlock)); 304 305 for (i = 0; i < 32; ++i) { 306 regs[i] = rge_mii_get16(rgep, i); 307 } 308 309 for (i = 0; i < 32; i += 8) 310 RGE_DEBUG(("rge_phydump: " 311 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 312 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 313 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 314 } 315 316 #endif /* RGE_DEBUGGING */ 317 318 static void 319 rge_phy_check(rge_t *rgep) 320 { 321 uint16_t gig_ctl; 322 323 if (rgep->param_link_up == LINK_STATE_DOWN) { 324 /* 325 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 326 * every 15 seconds whin link down & advertise is 1000. 327 */ 328 if (rgep->chipid.phy_ver == PHY_VER_S) { 329 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 330 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 331 rgep->link_down_count++; 332 if (rgep->link_down_count > 15) { 333 (void) rge_phy_reset(rgep); 334 rgep->stats.phy_reset++; 335 rgep->link_down_count = 0; 336 } 337 } 338 } 339 } else { 340 rgep->link_down_count = 0; 341 } 342 } 343 344 /* 345 * Basic low-level function to reset the PHY. 346 * Doesn't incorporate any special-case workarounds. 347 * 348 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 349 */ 350 boolean_t 351 rge_phy_reset(rge_t *rgep) 352 { 353 uint16_t control; 354 uint_t count; 355 356 /* 357 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 358 */ 359 control = rge_mii_get16(rgep, MII_CONTROL); 360 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 361 for (count = 0; count < 5; count++) { 362 drv_usecwait(100); 363 control = rge_mii_get16(rgep, MII_CONTROL); 364 if (BIC(control, MII_CONTROL_RESET)) 365 return (B_TRUE); 366 } 367 368 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 369 return (B_FALSE); 370 } 371 372 /* 373 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 374 * and advertisements with the required settings as specified by the various 375 * param_* variables that can be poked via the NDD interface. 376 * 377 * We always reset the PHY and reprogram *all* the relevant registers, 378 * not just those changed. This should cause the link to go down, and then 379 * back up again once the link is stable and autonegotiation (if enabled) 380 * is complete. We should get a link state change interrupt somewhere along 381 * the way ... 382 * 383 * NOTE: <genlock> must already be held by the caller 384 */ 385 void 386 rge_phy_update(rge_t *rgep) 387 { 388 boolean_t adv_autoneg; 389 boolean_t adv_pause; 390 boolean_t adv_asym_pause; 391 boolean_t adv_1000fdx; 392 boolean_t adv_1000hdx; 393 boolean_t adv_100fdx; 394 boolean_t adv_100hdx; 395 boolean_t adv_10fdx; 396 boolean_t adv_10hdx; 397 398 uint16_t control; 399 uint16_t gigctrl; 400 uint16_t anar; 401 402 ASSERT(mutex_owned(rgep->genlock)); 403 404 RGE_DEBUG(("rge_phy_update: autoneg %d " 405 "pause %d asym_pause %d " 406 "1000fdx %d 1000hdx %d " 407 "100fdx %d 100hdx %d " 408 "10fdx %d 10hdx %d ", 409 rgep->param_adv_autoneg, 410 rgep->param_adv_pause, rgep->param_adv_asym_pause, 411 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 412 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 413 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 414 415 control = gigctrl = anar = 0; 416 417 /* 418 * PHY settings are normally based on the param_* variables, 419 * but if any loopback mode is in effect, that takes precedence. 420 * 421 * RGE supports MAC-internal loopback, PHY-internal loopback, 422 * and External loopback at a variety of speeds (with a special 423 * cable). In all cases, autoneg is turned OFF, full-duplex 424 * is turned ON, and the speed/mastership is forced. 425 */ 426 switch (rgep->param_loop_mode) { 427 case RGE_LOOP_NONE: 428 default: 429 adv_autoneg = rgep->param_adv_autoneg; 430 adv_pause = rgep->param_adv_pause; 431 adv_asym_pause = rgep->param_adv_asym_pause; 432 adv_1000fdx = rgep->param_adv_1000fdx; 433 adv_1000hdx = rgep->param_adv_1000hdx; 434 adv_100fdx = rgep->param_adv_100fdx; 435 adv_100hdx = rgep->param_adv_100hdx; 436 adv_10fdx = rgep->param_adv_10fdx; 437 adv_10hdx = rgep->param_adv_10hdx; 438 break; 439 440 case RGE_LOOP_INTERNAL_PHY: 441 case RGE_LOOP_INTERNAL_MAC: 442 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 443 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 444 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 445 rgep->param_link_duplex = LINK_DUPLEX_FULL; 446 447 switch (rgep->param_loop_mode) { 448 case RGE_LOOP_INTERNAL_PHY: 449 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 450 rgep->param_link_speed = 1000; 451 adv_1000fdx = B_TRUE; 452 } else { 453 rgep->param_link_speed = 100; 454 adv_100fdx = B_TRUE; 455 } 456 control = MII_CONTROL_LOOPBACK; 457 break; 458 459 case RGE_LOOP_INTERNAL_MAC: 460 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 461 rgep->param_link_speed = 1000; 462 adv_1000fdx = B_TRUE; 463 } else { 464 rgep->param_link_speed = 100; 465 adv_100fdx = B_TRUE; 466 break; 467 } 468 } 469 470 RGE_DEBUG(("rge_phy_update: autoneg %d " 471 "pause %d asym_pause %d " 472 "1000fdx %d 1000hdx %d " 473 "100fdx %d 100hdx %d " 474 "10fdx %d 10hdx %d ", 475 adv_autoneg, 476 adv_pause, adv_asym_pause, 477 adv_1000fdx, adv_1000hdx, 478 adv_100fdx, adv_100hdx, 479 adv_10fdx, adv_10hdx)); 480 481 /* 482 * We should have at least one technology capability set; 483 * if not, we select a default of 1000Mb/s full-duplex 484 */ 485 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 486 !adv_1000hdx && !adv_100hdx && !adv_10hdx) { 487 if (rgep->chipid.mac_ver != MAC_VER_8101E) 488 adv_1000fdx = B_TRUE; 489 } else { 490 adv_1000fdx = B_FALSE; 491 adv_100fdx = B_TRUE; 492 } 493 } 494 495 /* 496 * Now transform the adv_* variables into the proper settings 497 * of the PHY registers ... 498 * 499 * If autonegotiation is (now) enabled, we want to trigger 500 * a new autonegotiation cycle once the PHY has been 501 * programmed with the capabilities to be advertised. 502 * 503 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 504 */ 505 if (adv_autoneg) 506 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 507 508 if (adv_1000fdx) 509 control |= MII_CONTROL_1000MB|MII_CONTROL_FDUPLEX; 510 else if (adv_1000hdx) 511 control |= MII_CONTROL_1000MB; 512 else if (adv_100fdx) 513 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 514 else if (adv_100hdx) 515 control |= MII_CONTROL_100MB; 516 else if (adv_10fdx) 517 control |= MII_CONTROL_FDUPLEX; 518 else if (adv_10hdx) 519 control |= 0; 520 else 521 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 522 523 if (adv_1000fdx) { 524 gigctrl |= MII_1000BT_CTL_ADV_FDX; 525 /* 526 * Chipset limitation: need set other capabilities to true 527 */ 528 if (rgep->chipid.is_pcie) 529 adv_1000hdx = B_TRUE; 530 adv_100fdx = B_TRUE; 531 adv_100hdx = B_TRUE; 532 adv_10fdx = B_TRUE; 533 adv_10hdx = B_TRUE; 534 } 535 536 if (adv_1000hdx) 537 gigctrl |= MII_1000BT_CTL_ADV_HDX; 538 539 if (adv_100fdx) 540 anar |= MII_ABILITY_100BASE_TX_FD; 541 if (adv_100hdx) 542 anar |= MII_ABILITY_100BASE_TX; 543 if (adv_10fdx) 544 anar |= MII_ABILITY_10BASE_T_FD; 545 if (adv_10hdx) 546 anar |= MII_ABILITY_10BASE_T; 547 548 if (adv_pause) 549 anar |= MII_ABILITY_PAUSE; 550 if (adv_asym_pause) 551 anar |= MII_ABILITY_ASYM_PAUSE; 552 553 /* 554 * Munge in any other fixed bits we require ... 555 */ 556 anar |= MII_AN_SELECTOR_8023; 557 558 /* 559 * Restart the PHY and write the new values. Note the 560 * time, so that we can say whether subsequent link state 561 * changes can be attributed to our reprogramming the PHY 562 */ 563 rge_phy_init(rgep); 564 if (rgep->chipid.mac_ver == MAC_VER_8168B_B || 565 rgep->chipid.mac_ver == MAC_VER_8168B_C) { 566 /* power up PHY for RTL8168B chipset */ 567 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 568 rge_mii_put16(rgep, PHY_0E_REG, 0x0000); 569 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 570 } 571 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 572 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 573 rge_mii_put16(rgep, MII_CONTROL, control); 574 575 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 576 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 577 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 578 } 579 580 void rge_phy_init(rge_t *rgep); 581 #pragma no_inline(rge_phy_init) 582 583 void 584 rge_phy_init(rge_t *rgep) 585 { 586 rgep->phy_mii_addr = 1; 587 588 /* 589 * Below phy config steps are copied from the Programming Guide 590 * (there's no detail comments for these steps.) 591 */ 592 switch (rgep->chipid.mac_ver) { 593 case MAC_VER_8169S_D: 594 case MAC_VER_8169S_E : 595 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 596 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 597 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 598 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 599 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 600 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 601 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 602 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 603 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 604 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 605 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 606 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 607 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 608 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 609 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 610 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 611 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 612 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 613 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 614 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 615 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 616 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 617 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 618 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 619 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 620 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 621 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 622 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 623 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 624 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 625 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 626 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 627 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 628 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 629 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 630 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 631 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 632 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 633 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 634 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 635 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 636 break; 637 638 case MAC_VER_8169SB: 639 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 640 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 641 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 642 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 643 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 644 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 645 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 646 break; 647 648 case MAC_VER_8169SC: 649 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 650 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); 651 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); 652 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); 653 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); 654 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); 655 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); 656 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); 657 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); 658 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); 659 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 660 rge_mii_put16(rgep, PHY_13_REG, 0x0600); 661 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 662 break; 663 664 case MAC_VER_8168: 665 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 666 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 667 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 668 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 669 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 670 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 671 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 672 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 673 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 674 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 675 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 676 break; 677 678 case MAC_VER_8168B_B: 679 case MAC_VER_8168B_C: 680 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 681 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 682 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 683 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 684 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 685 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 686 break; 687 } 688 } 689 690 void rge_chip_ident(rge_t *rgep); 691 #pragma no_inline(rge_chip_ident) 692 693 void 694 rge_chip_ident(rge_t *rgep) 695 { 696 chip_id_t *chip = &rgep->chipid; 697 uint32_t val32; 698 uint16_t val16; 699 700 /* 701 * Read and record MAC version 702 */ 703 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 704 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 705 chip->mac_ver = val32; 706 switch (chip->mac_ver) { 707 case MAC_VER_8168: 708 case MAC_VER_8168B_B: 709 case MAC_VER_8168B_C: 710 case MAC_VER_8101E: 711 case MAC_VER_8101E_B: 712 chip->is_pcie = B_TRUE; 713 break; 714 715 default: 716 chip->is_pcie = B_FALSE; 717 break; 718 } 719 720 /* 721 * Read and record PHY version 722 */ 723 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 724 val16 &= PHY_VER_MASK; 725 chip->phy_ver = val16; 726 727 /* set pci latency timer */ 728 if (chip->mac_ver == MAC_VER_8169 || 729 chip->mac_ver == MAC_VER_8169S_D || 730 chip->mac_ver == MAC_VER_8169SC) 731 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 732 733 if (chip->mac_ver == MAC_VER_8169SC) { 734 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); 735 val16 &= 0x0300; 736 if (val16 == 0x1) /* 66Mhz PCI */ 737 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ff00ff); 738 else if (val16 == 0x0) /* 33Mhz PCI */ 739 pci_config_put32(rgep->cfg_handle, 0x7c, 0x00ffff00); 740 } 741 742 /* 743 * PCIE chipset require the Rx buffer start address must be 744 * 8-byte alignment and the Rx buffer size must be multiple of 8. 745 * We'll just use bcopy in receive procedure for the PCIE chipset. 746 */ 747 if (chip->is_pcie) { 748 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 749 if (rgep->default_mtu > ETHERMTU) { 750 rge_notice(rgep, "Jumbo packets not supported " 751 "for this PCIE chipset"); 752 rgep->default_mtu = ETHERMTU; 753 } 754 } 755 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 756 rgep->head_room = 0; 757 else 758 rgep->head_room = RGE_HEADROOM; 759 760 /* 761 * Initialize other variables. 762 */ 763 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 764 rgep->default_mtu = ETHERMTU; 765 if (rgep->default_mtu > ETHERMTU) { 766 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 767 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 768 rgep->ethmax_size = RGE_JUMBO_SIZE; 769 } else { 770 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 771 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 772 rgep->ethmax_size = ETHERMAX; 773 } 774 chip->rxconfig = RX_CONFIG_DEFAULT; 775 chip->txconfig = TX_CONFIG_DEFAULT; 776 777 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 778 rgep->ifname, chip->mac_ver, chip->phy_ver)); 779 } 780 781 /* 782 * Perform first-stage chip (re-)initialisation, using only config-space 783 * accesses: 784 * 785 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 786 * returning the data in the structure pointed to by <idp>. 787 * + Enable Memory Space accesses. 788 * + Enable Bus Mastering according. 789 */ 790 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 791 #pragma no_inline(rge_chip_cfg_init) 792 793 void 794 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 795 { 796 ddi_acc_handle_t handle; 797 uint16_t commd; 798 799 handle = rgep->cfg_handle; 800 801 /* 802 * Save PCI cache line size and subsystem vendor ID 803 */ 804 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 805 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 806 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 807 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 808 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 809 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 810 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 811 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 812 813 /* 814 * Turn on Master Enable (DMA) and IO Enable bits. 815 * Enable PCI Memory Space accesses 816 */ 817 commd = cidp->command; 818 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 819 pci_config_put16(handle, PCI_CONF_COMM, commd); 820 821 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 822 cidp->vendor, cidp->device, cidp->revision)); 823 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 824 cidp->subven, cidp->subdev)); 825 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 826 cidp->clsize, cidp->latency, cidp->command)); 827 } 828 829 int rge_chip_reset(rge_t *rgep); 830 #pragma no_inline(rge_chip_reset) 831 832 int 833 rge_chip_reset(rge_t *rgep) 834 { 835 int i; 836 uint8_t val8; 837 838 /* 839 * Chip should be in STOP state 840 */ 841 rge_reg_clr8(rgep, RT_COMMAND_REG, 842 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 843 844 /* 845 * Disable interrupt 846 */ 847 rgep->int_mask = INT_MASK_NONE; 848 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 849 850 /* 851 * Clear pended interrupt 852 */ 853 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 854 855 /* 856 * Reset chip 857 */ 858 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 859 860 /* 861 * Wait for reset success 862 */ 863 for (i = 0; i < CHIP_RESET_LOOP; i++) { 864 drv_usecwait(10); 865 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 866 if (!(val8 & RT_COMMAND_RESET)) { 867 rgep->rge_chip_state = RGE_CHIP_RESET; 868 return (0); 869 } 870 } 871 RGE_REPORT((rgep, "rge_chip_reset fail.")); 872 return (-1); 873 } 874 875 void rge_chip_init(rge_t *rgep); 876 #pragma no_inline(rge_chip_init) 877 878 void 879 rge_chip_init(rge_t *rgep) 880 { 881 uint32_t val32; 882 uint32_t val16; 883 uint32_t *hashp; 884 chip_id_t *chip = &rgep->chipid; 885 886 if (chip->is_pcie) { 887 /* 888 * Increase the threshold voltage of RX sensitivity 889 */ 890 if (chip->mac_ver != MAC_VER_8168 && 891 chip->mac_ver != MAC_VER_8101E_B) 892 rge_ephy_put16(rgep, 0x01, 0x1bd3); 893 894 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 895 val16 = 0x12<<8 | val16; 896 if (rgep->chipid.mac_ver != MAC_VER_8101E && 897 rgep->chipid.mac_ver != MAC_VER_8101E_B && 898 rgep->chipid.mac_ver != MAC_VER_8101E_C && 899 rgep->chipid.mac_ver != MAC_VER_8168B_C) { 900 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 901 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 902 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 903 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 904 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 905 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 906 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 907 val32 |= 0x7000; 908 val32 &= 0xffff5fff; 909 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 910 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 911 } 912 } 913 914 /* 915 * Config MII register 916 */ 917 rgep->param_link_up = LINK_STATE_DOWN; 918 rge_phy_update(rgep); 919 920 /* 921 * Enable Rx checksum offload. 922 * Then for vlan support, we must enable receive vlan de-tagging. 923 * Otherwise, there'll be checksum error. 924 */ 925 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 926 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 927 if (chip->mac_ver == MAC_VER_8169S_D) { 928 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 929 rge_reg_put8(rgep, RESV_82_REG, 0x01); 930 } 931 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 932 933 /* 934 * Start transmit/receive before set tx/rx configuration register 935 */ 936 if (!chip->is_pcie) 937 rge_reg_set8(rgep, RT_COMMAND_REG, 938 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 939 940 /* 941 * Set dump tally counter register 942 */ 943 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 944 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 945 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 946 val32 &= DUMP_COUNTER_REG_RESV; 947 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 948 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 949 950 /* 951 * Change to config register write enable mode 952 */ 953 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 954 955 /* 956 * Set Tx/Rx maximum packet size 957 */ 958 if (rgep->default_mtu > ETHERMTU) { 959 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 960 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 961 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) { 962 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 963 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 964 } else { 965 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E); 966 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E); 967 } 968 969 /* 970 * Set receive configuration register 971 */ 972 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 973 val32 &= RX_CONFIG_REG_RESV; 974 if (rgep->promisc) 975 val32 |= RX_ACCEPT_ALL_PKT; 976 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 977 978 /* 979 * Set transmit configuration register 980 */ 981 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 982 val32 &= TX_CONFIG_REG_RESV; 983 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 984 985 /* 986 * Set Tx/Rx descriptor register 987 */ 988 val32 = rgep->tx_desc.cookie.dmac_laddress; 989 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 990 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 991 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 992 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 993 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 994 val32 = rgep->rx_desc.cookie.dmac_laddress; 995 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 996 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 997 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 998 999 /* 1000 * Suggested setting from Realtek 1001 */ 1002 if (rgep->chipid.mac_ver != MAC_VER_8101E) 1003 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 1004 else 1005 rge_reg_put16(rgep, RESV_E2_REG, 0x0000); 1006 1007 /* 1008 * Set multicast register 1009 */ 1010 hashp = (uint32_t *)rgep->mcast_hash; 1011 rge_reg_put32(rgep, MULTICAST_0_REG, hashp[0]); 1012 rge_reg_put32(rgep, MULTICAST_4_REG, hashp[1]); 1013 1014 /* 1015 * Msic register setting: 1016 * -- Missed packet counter: clear it 1017 * -- TimerInt Register 1018 * -- Timer count register 1019 */ 1020 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1021 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1022 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1023 1024 /* 1025 * Return to normal network/host communication mode 1026 */ 1027 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1028 drv_usecwait(20); 1029 } 1030 1031 /* 1032 * rge_chip_start() -- start the chip transmitting and/or receiving, 1033 * including enabling interrupts 1034 */ 1035 void rge_chip_start(rge_t *rgep); 1036 #pragma no_inline(rge_chip_start) 1037 1038 void 1039 rge_chip_start(rge_t *rgep) 1040 { 1041 /* 1042 * Clear statistics 1043 */ 1044 bzero(&rgep->stats, sizeof (rge_stats_t)); 1045 DMA_ZERO(rgep->dma_area_stats); 1046 1047 /* 1048 * Start transmit/receive 1049 */ 1050 rge_reg_set8(rgep, RT_COMMAND_REG, 1051 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1052 1053 /* 1054 * Enable interrupt 1055 */ 1056 rgep->int_mask = RGE_INT_MASK; 1057 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1058 1059 /* 1060 * All done! 1061 */ 1062 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1063 } 1064 1065 /* 1066 * rge_chip_stop() -- stop board receiving 1067 */ 1068 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1069 #pragma no_inline(rge_chip_stop) 1070 1071 void 1072 rge_chip_stop(rge_t *rgep, boolean_t fault) 1073 { 1074 /* 1075 * Disable interrupt 1076 */ 1077 rgep->int_mask = INT_MASK_NONE; 1078 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1079 1080 /* 1081 * Clear pended interrupt 1082 */ 1083 if (!rgep->suspended) { 1084 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1085 } 1086 1087 /* 1088 * Stop the board and disable transmit/receive 1089 */ 1090 rge_reg_clr8(rgep, RT_COMMAND_REG, 1091 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1092 1093 if (fault) 1094 rgep->rge_chip_state = RGE_CHIP_FAULT; 1095 else 1096 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1097 } 1098 1099 /* 1100 * rge_get_mac_addr() -- get the MAC address on NIC 1101 */ 1102 static void rge_get_mac_addr(rge_t *rgep); 1103 #pragma inline(rge_get_mac_addr) 1104 1105 static void 1106 rge_get_mac_addr(rge_t *rgep) 1107 { 1108 uint8_t *macaddr = rgep->netaddr; 1109 uint32_t val32; 1110 1111 /* 1112 * Read first 4-byte of mac address 1113 */ 1114 val32 = rge_reg_get32(rgep, ID_0_REG); 1115 macaddr[0] = val32 & 0xff; 1116 val32 = val32 >> 8; 1117 macaddr[1] = val32 & 0xff; 1118 val32 = val32 >> 8; 1119 macaddr[2] = val32 & 0xff; 1120 val32 = val32 >> 8; 1121 macaddr[3] = val32 & 0xff; 1122 1123 /* 1124 * Read last 2-byte of mac address 1125 */ 1126 val32 = rge_reg_get32(rgep, ID_4_REG); 1127 macaddr[4] = val32 & 0xff; 1128 val32 = val32 >> 8; 1129 macaddr[5] = val32 & 0xff; 1130 } 1131 1132 static void rge_set_mac_addr(rge_t *rgep); 1133 #pragma inline(rge_set_mac_addr) 1134 1135 static void 1136 rge_set_mac_addr(rge_t *rgep) 1137 { 1138 uint8_t *p = rgep->netaddr; 1139 uint32_t val32; 1140 1141 /* 1142 * Change to config register write enable mode 1143 */ 1144 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1145 1146 /* 1147 * Get first 4 bytes of mac address 1148 */ 1149 val32 = p[3]; 1150 val32 = val32 << 8; 1151 val32 |= p[2]; 1152 val32 = val32 << 8; 1153 val32 |= p[1]; 1154 val32 = val32 << 8; 1155 val32 |= p[0]; 1156 1157 /* 1158 * Set first 4 bytes of mac address 1159 */ 1160 rge_reg_put32(rgep, ID_0_REG, val32); 1161 1162 /* 1163 * Get last 2 bytes of mac address 1164 */ 1165 val32 = p[5]; 1166 val32 = val32 << 8; 1167 val32 |= p[4]; 1168 1169 /* 1170 * Set last 2 bytes of mac address 1171 */ 1172 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1173 rge_reg_put32(rgep, ID_4_REG, val32); 1174 1175 /* 1176 * Return to normal network/host communication mode 1177 */ 1178 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1179 } 1180 1181 static void rge_set_multi_addr(rge_t *rgep); 1182 #pragma inline(rge_set_multi_addr) 1183 1184 static void 1185 rge_set_multi_addr(rge_t *rgep) 1186 { 1187 uint32_t *hashp; 1188 1189 hashp = (uint32_t *)rgep->mcast_hash; 1190 1191 /* 1192 * Change to config register write enable mode 1193 */ 1194 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1195 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1196 1197 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1198 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1199 1200 /* 1201 * Return to normal network/host communication mode 1202 */ 1203 if (rgep->chipid.mac_ver == MAC_VER_8169SC) 1204 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1205 } 1206 1207 static void rge_set_promisc(rge_t *rgep); 1208 #pragma inline(rge_set_promisc) 1209 1210 static void 1211 rge_set_promisc(rge_t *rgep) 1212 { 1213 if (rgep->promisc) 1214 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1215 else 1216 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1217 } 1218 1219 /* 1220 * rge_chip_sync() -- program the chip with the unicast MAC address, 1221 * the multicast hash table, the required level of promiscuity, and 1222 * the current loopback mode ... 1223 */ 1224 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1225 #pragma no_inline(rge_chip_sync) 1226 1227 void 1228 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1229 { 1230 switch (todo) { 1231 case RGE_GET_MAC: 1232 rge_get_mac_addr(rgep); 1233 break; 1234 case RGE_SET_MAC: 1235 /* Reprogram the unicast MAC address(es) ... */ 1236 rge_set_mac_addr(rgep); 1237 break; 1238 case RGE_SET_MUL: 1239 /* Reprogram the hashed multicast address table ... */ 1240 rge_set_multi_addr(rgep); 1241 break; 1242 case RGE_SET_PROMISC: 1243 /* Set or clear the PROMISCUOUS mode bit */ 1244 rge_set_promisc(rgep); 1245 break; 1246 default: 1247 break; 1248 } 1249 } 1250 1251 void rge_chip_blank(void *arg, time_t ticks, uint_t count); 1252 #pragma no_inline(rge_chip_blank) 1253 1254 void 1255 rge_chip_blank(void *arg, time_t ticks, uint_t count) 1256 { 1257 _NOTE(ARGUNUSED(arg, ticks, count)); 1258 } 1259 1260 void rge_tx_trigger(rge_t *rgep); 1261 #pragma no_inline(rge_tx_trigger) 1262 1263 void 1264 rge_tx_trigger(rge_t *rgep) 1265 { 1266 rge_reg_set8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1267 } 1268 1269 void rge_hw_stats_dump(rge_t *rgep); 1270 #pragma no_inline(rge_tx_trigger) 1271 1272 void 1273 rge_hw_stats_dump(rge_t *rgep) 1274 { 1275 int i = 0; 1276 1277 while (rge_reg_get32(rgep, DUMP_COUNTER_REG_0) & DUMP_START) { 1278 drv_usecwait(100); 1279 if (++i > STATS_DUMP_LOOP) { 1280 RGE_DEBUG(("rge h/w statistics dump fail!")); 1281 rgep->rge_chip_state = RGE_CHIP_ERROR; 1282 return; 1283 } 1284 } 1285 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1286 1287 /* 1288 * Start H/W statistics dump for RTL8169 chip 1289 */ 1290 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1291 } 1292 1293 /* 1294 * ========== Hardware interrupt handler ========== 1295 */ 1296 1297 #undef RGE_DBG 1298 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1299 1300 static void rge_wake_factotum(rge_t *rgep); 1301 #pragma inline(rge_wake_factotum) 1302 1303 static void 1304 rge_wake_factotum(rge_t *rgep) 1305 { 1306 if (rgep->factotum_flag == 0) { 1307 rgep->factotum_flag = 1; 1308 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1309 } 1310 } 1311 1312 /* 1313 * rge_intr() -- handle chip interrupts 1314 */ 1315 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1316 #pragma no_inline(rge_intr) 1317 1318 uint_t 1319 rge_intr(caddr_t arg1, caddr_t arg2) 1320 { 1321 rge_t *rgep = (rge_t *)arg1; 1322 uint16_t int_status; 1323 1324 _NOTE(ARGUNUSED(arg2)) 1325 1326 mutex_enter(rgep->genlock); 1327 1328 if (rgep->suspended) { 1329 mutex_exit(rgep->genlock); 1330 return (DDI_INTR_UNCLAIMED); 1331 } 1332 1333 /* 1334 * Was this interrupt caused by our device... 1335 */ 1336 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1337 if (!(int_status & rgep->int_mask)) { 1338 mutex_exit(rgep->genlock); 1339 return (DDI_INTR_UNCLAIMED); 1340 /* indicate it wasn't our interrupt */ 1341 } 1342 rgep->stats.intr++; 1343 1344 /* 1345 * Clear interrupt 1346 * For PCIE chipset, we need disable interrupt first. 1347 */ 1348 if (rgep->chipid.is_pcie) 1349 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1350 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1351 1352 /* 1353 * Cable link change interrupt 1354 */ 1355 if (int_status & LINK_CHANGE_INT) { 1356 rge_chip_cyclic(rgep); 1357 } 1358 1359 mutex_exit(rgep->genlock); 1360 1361 /* 1362 * Receive interrupt 1363 */ 1364 if (int_status & RGE_RX_INT) 1365 rge_receive(rgep); 1366 1367 /* 1368 * Re-enable interrupt for PCIE chipset 1369 */ 1370 if (rgep->chipid.is_pcie) 1371 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1372 1373 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1374 } 1375 1376 /* 1377 * ========== Factotum, implemented as a softint handler ========== 1378 */ 1379 1380 #undef RGE_DBG 1381 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1382 1383 static boolean_t rge_factotum_link_check(rge_t *rgep); 1384 #pragma no_inline(rge_factotum_link_check) 1385 1386 static boolean_t 1387 rge_factotum_link_check(rge_t *rgep) 1388 { 1389 uint8_t media_status; 1390 int32_t link; 1391 1392 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1393 link = (media_status & PHY_STATUS_LINK_UP) ? 1394 LINK_STATE_UP : LINK_STATE_DOWN; 1395 if (rgep->param_link_up != link) { 1396 /* 1397 * Link change. 1398 */ 1399 rgep->param_link_up = link; 1400 1401 if (link == LINK_STATE_UP) { 1402 if (media_status & PHY_STATUS_1000MF) { 1403 rgep->param_link_speed = RGE_SPEED_1000M; 1404 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1405 } else { 1406 rgep->param_link_speed = 1407 (media_status & PHY_STATUS_100M) ? 1408 RGE_SPEED_100M : RGE_SPEED_10M; 1409 rgep->param_link_duplex = 1410 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1411 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1412 } 1413 } 1414 return (B_TRUE); 1415 } 1416 return (B_FALSE); 1417 } 1418 1419 /* 1420 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1421 */ 1422 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1423 #pragma no_inline(rge_factotum_stall_check) 1424 1425 static boolean_t 1426 rge_factotum_stall_check(rge_t *rgep) 1427 { 1428 uint32_t dogval; 1429 1430 ASSERT(mutex_owned(rgep->genlock)); 1431 1432 /* 1433 * Specific check for Tx stall ... 1434 * 1435 * The 'watchdog' counter is incremented whenever a packet 1436 * is queued, reset to 1 when some (but not all) buffers 1437 * are reclaimed, reset to 0 (disabled) when all buffers 1438 * are reclaimed, and shifted left here. If it exceeds the 1439 * threshold value, the chip is assumed to have stalled and 1440 * is put into the ERROR state. The factotum will then reset 1441 * it on the next pass. 1442 * 1443 * All of which should ensure that we don't get into a state 1444 * where packets are left pending indefinitely! 1445 */ 1446 if (rgep->resched_needed) 1447 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1448 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1449 if (dogval < rge_watchdog_count) 1450 return (B_FALSE); 1451 1452 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1453 return (B_TRUE); 1454 1455 } 1456 1457 /* 1458 * The factotum is woken up when there's something to do that we'd rather 1459 * not do from inside a hardware interrupt handler or high-level cyclic. 1460 * Its two main tasks are: 1461 * reset & restart the chip after an error 1462 * check the link status whenever necessary 1463 */ 1464 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1465 #pragma no_inline(rge_chip_factotum) 1466 1467 uint_t 1468 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1469 { 1470 rge_t *rgep; 1471 uint_t result; 1472 boolean_t error; 1473 boolean_t linkchg; 1474 1475 rgep = (rge_t *)arg1; 1476 _NOTE(ARGUNUSED(arg2)) 1477 1478 if (rgep->factotum_flag == 0) 1479 return (DDI_INTR_UNCLAIMED); 1480 1481 rgep->factotum_flag = 0; 1482 result = DDI_INTR_CLAIMED; 1483 error = B_FALSE; 1484 linkchg = B_FALSE; 1485 1486 mutex_enter(rgep->genlock); 1487 switch (rgep->rge_chip_state) { 1488 default: 1489 break; 1490 1491 case RGE_CHIP_RUNNING: 1492 linkchg = rge_factotum_link_check(rgep); 1493 error = rge_factotum_stall_check(rgep); 1494 break; 1495 1496 case RGE_CHIP_ERROR: 1497 error = B_TRUE; 1498 break; 1499 1500 case RGE_CHIP_FAULT: 1501 /* 1502 * Fault detected, time to reset ... 1503 */ 1504 if (rge_autorecover) { 1505 RGE_REPORT((rgep, "automatic recovery activated")); 1506 rge_restart(rgep); 1507 } 1508 break; 1509 } 1510 1511 /* 1512 * If an error is detected, stop the chip now, marking it as 1513 * faulty, so that it will be reset next time through ... 1514 */ 1515 if (error) 1516 rge_chip_stop(rgep, B_TRUE); 1517 mutex_exit(rgep->genlock); 1518 1519 /* 1520 * If the link state changed, tell the world about it. 1521 * Note: can't do this while still holding the mutex. 1522 */ 1523 if (linkchg) 1524 mac_link_update(rgep->mh, rgep->param_link_up); 1525 1526 return (result); 1527 } 1528 1529 /* 1530 * High-level cyclic handler 1531 * 1532 * This routine schedules a (low-level) softint callback to the 1533 * factotum, and prods the chip to update the status block (which 1534 * will cause a hardware interrupt when complete). 1535 */ 1536 void rge_chip_cyclic(void *arg); 1537 #pragma no_inline(rge_chip_cyclic) 1538 1539 void 1540 rge_chip_cyclic(void *arg) 1541 { 1542 rge_t *rgep; 1543 1544 rgep = arg; 1545 1546 switch (rgep->rge_chip_state) { 1547 default: 1548 return; 1549 1550 case RGE_CHIP_RUNNING: 1551 rge_phy_check(rgep); 1552 break; 1553 1554 case RGE_CHIP_FAULT: 1555 case RGE_CHIP_ERROR: 1556 break; 1557 } 1558 1559 rge_wake_factotum(rgep); 1560 } 1561 1562 1563 /* 1564 * ========== Ioctl subfunctions ========== 1565 */ 1566 1567 #undef RGE_DBG 1568 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1569 1570 #if RGE_DEBUGGING || RGE_DO_PPIO 1571 1572 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1573 #pragma no_inline(rge_chip_peek_cfg) 1574 1575 static void 1576 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1577 { 1578 uint64_t regval; 1579 uint64_t regno; 1580 1581 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1582 (void *)rgep, (void *)ppd)); 1583 1584 regno = ppd->pp_acc_offset; 1585 1586 switch (ppd->pp_acc_size) { 1587 case 1: 1588 regval = pci_config_get8(rgep->cfg_handle, regno); 1589 break; 1590 1591 case 2: 1592 regval = pci_config_get16(rgep->cfg_handle, regno); 1593 break; 1594 1595 case 4: 1596 regval = pci_config_get32(rgep->cfg_handle, regno); 1597 break; 1598 1599 case 8: 1600 regval = pci_config_get64(rgep->cfg_handle, regno); 1601 break; 1602 } 1603 1604 ppd->pp_acc_data = regval; 1605 } 1606 1607 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1608 #pragma no_inline(rge_chip_poke_cfg) 1609 1610 static void 1611 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1612 { 1613 uint64_t regval; 1614 uint64_t regno; 1615 1616 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1617 (void *)rgep, (void *)ppd)); 1618 1619 regno = ppd->pp_acc_offset; 1620 regval = ppd->pp_acc_data; 1621 1622 switch (ppd->pp_acc_size) { 1623 case 1: 1624 pci_config_put8(rgep->cfg_handle, regno, regval); 1625 break; 1626 1627 case 2: 1628 pci_config_put16(rgep->cfg_handle, regno, regval); 1629 break; 1630 1631 case 4: 1632 pci_config_put32(rgep->cfg_handle, regno, regval); 1633 break; 1634 1635 case 8: 1636 pci_config_put64(rgep->cfg_handle, regno, regval); 1637 break; 1638 } 1639 } 1640 1641 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1642 #pragma no_inline(rge_chip_peek_reg) 1643 1644 static void 1645 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1646 { 1647 uint64_t regval; 1648 void *regaddr; 1649 1650 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1651 (void *)rgep, (void *)ppd)); 1652 1653 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1654 1655 switch (ppd->pp_acc_size) { 1656 case 1: 1657 regval = ddi_get8(rgep->io_handle, regaddr); 1658 break; 1659 1660 case 2: 1661 regval = ddi_get16(rgep->io_handle, regaddr); 1662 break; 1663 1664 case 4: 1665 regval = ddi_get32(rgep->io_handle, regaddr); 1666 break; 1667 1668 case 8: 1669 regval = ddi_get64(rgep->io_handle, regaddr); 1670 break; 1671 } 1672 1673 ppd->pp_acc_data = regval; 1674 } 1675 1676 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1677 #pragma no_inline(rge_chip_peek_reg) 1678 1679 static void 1680 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1681 { 1682 uint64_t regval; 1683 void *regaddr; 1684 1685 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1686 (void *)rgep, (void *)ppd)); 1687 1688 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1689 regval = ppd->pp_acc_data; 1690 1691 switch (ppd->pp_acc_size) { 1692 case 1: 1693 ddi_put8(rgep->io_handle, regaddr, regval); 1694 break; 1695 1696 case 2: 1697 ddi_put16(rgep->io_handle, regaddr, regval); 1698 break; 1699 1700 case 4: 1701 ddi_put32(rgep->io_handle, regaddr, regval); 1702 break; 1703 1704 case 8: 1705 ddi_put64(rgep->io_handle, regaddr, regval); 1706 break; 1707 } 1708 } 1709 1710 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1711 #pragma no_inline(rge_chip_peek_mii) 1712 1713 static void 1714 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1715 { 1716 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1717 (void *)rgep, (void *)ppd)); 1718 1719 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1720 } 1721 1722 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1723 #pragma no_inline(rge_chip_poke_mii) 1724 1725 static void 1726 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1727 { 1728 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1729 (void *)rgep, (void *)ppd)); 1730 1731 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1732 } 1733 1734 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1735 #pragma no_inline(rge_chip_peek_mem) 1736 1737 static void 1738 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1739 { 1740 uint64_t regval; 1741 void *vaddr; 1742 1743 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1744 (void *)rgep, (void *)ppd)); 1745 1746 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1747 1748 switch (ppd->pp_acc_size) { 1749 case 1: 1750 regval = *(uint8_t *)vaddr; 1751 break; 1752 1753 case 2: 1754 regval = *(uint16_t *)vaddr; 1755 break; 1756 1757 case 4: 1758 regval = *(uint32_t *)vaddr; 1759 break; 1760 1761 case 8: 1762 regval = *(uint64_t *)vaddr; 1763 break; 1764 } 1765 1766 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1767 (void *)rgep, (void *)ppd, regval, vaddr)); 1768 1769 ppd->pp_acc_data = regval; 1770 } 1771 1772 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1773 #pragma no_inline(rge_chip_poke_mem) 1774 1775 static void 1776 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1777 { 1778 uint64_t regval; 1779 void *vaddr; 1780 1781 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1782 (void *)rgep, (void *)ppd)); 1783 1784 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1785 regval = ppd->pp_acc_data; 1786 1787 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1788 (void *)rgep, (void *)ppd, regval, vaddr)); 1789 1790 switch (ppd->pp_acc_size) { 1791 case 1: 1792 *(uint8_t *)vaddr = (uint8_t)regval; 1793 break; 1794 1795 case 2: 1796 *(uint16_t *)vaddr = (uint16_t)regval; 1797 break; 1798 1799 case 4: 1800 *(uint32_t *)vaddr = (uint32_t)regval; 1801 break; 1802 1803 case 8: 1804 *(uint64_t *)vaddr = (uint64_t)regval; 1805 break; 1806 } 1807 } 1808 1809 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1810 struct iocblk *iocp); 1811 #pragma no_inline(rge_pp_ioctl) 1812 1813 static enum ioc_reply 1814 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1815 { 1816 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1817 rge_peekpoke_t *ppd; 1818 dma_area_t *areap; 1819 uint64_t sizemask; 1820 uint64_t mem_va; 1821 uint64_t maxoff; 1822 boolean_t peek; 1823 1824 switch (cmd) { 1825 default: 1826 /* NOTREACHED */ 1827 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 1828 return (IOC_INVAL); 1829 1830 case RGE_PEEK: 1831 peek = B_TRUE; 1832 break; 1833 1834 case RGE_POKE: 1835 peek = B_FALSE; 1836 break; 1837 } 1838 1839 /* 1840 * Validate format of ioctl 1841 */ 1842 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 1843 return (IOC_INVAL); 1844 if (mp->b_cont == NULL) 1845 return (IOC_INVAL); 1846 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 1847 1848 /* 1849 * Validate request parameters 1850 */ 1851 switch (ppd->pp_acc_space) { 1852 default: 1853 return (IOC_INVAL); 1854 1855 case RGE_PP_SPACE_CFG: 1856 /* 1857 * Config space 1858 */ 1859 sizemask = 8|4|2|1; 1860 mem_va = 0; 1861 maxoff = PCI_CONF_HDR_SIZE; 1862 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 1863 break; 1864 1865 case RGE_PP_SPACE_REG: 1866 /* 1867 * Memory-mapped I/O space 1868 */ 1869 sizemask = 8|4|2|1; 1870 mem_va = 0; 1871 maxoff = RGE_REGISTER_MAX; 1872 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 1873 break; 1874 1875 case RGE_PP_SPACE_MII: 1876 /* 1877 * PHY's MII registers 1878 * NB: all PHY registers are two bytes, but the 1879 * addresses increment in ones (word addressing). 1880 * So we scale the address here, then undo the 1881 * transformation inside the peek/poke functions. 1882 */ 1883 ppd->pp_acc_offset *= 2; 1884 sizemask = 2; 1885 mem_va = 0; 1886 maxoff = (MII_MAXREG+1)*2; 1887 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 1888 break; 1889 1890 case RGE_PP_SPACE_RGE: 1891 /* 1892 * RGE data structure! 1893 */ 1894 sizemask = 8|4|2|1; 1895 mem_va = (uintptr_t)rgep; 1896 maxoff = sizeof (*rgep); 1897 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1898 break; 1899 1900 case RGE_PP_SPACE_STATISTICS: 1901 case RGE_PP_SPACE_TXDESC: 1902 case RGE_PP_SPACE_TXBUFF: 1903 case RGE_PP_SPACE_RXDESC: 1904 case RGE_PP_SPACE_RXBUFF: 1905 /* 1906 * Various DMA_AREAs 1907 */ 1908 switch (ppd->pp_acc_space) { 1909 case RGE_PP_SPACE_TXDESC: 1910 areap = &rgep->dma_area_txdesc; 1911 break; 1912 case RGE_PP_SPACE_RXDESC: 1913 areap = &rgep->dma_area_rxdesc; 1914 break; 1915 case RGE_PP_SPACE_STATISTICS: 1916 areap = &rgep->dma_area_stats; 1917 break; 1918 } 1919 1920 sizemask = 8|4|2|1; 1921 mem_va = (uintptr_t)areap->mem_va; 1922 maxoff = areap->alength; 1923 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 1924 break; 1925 } 1926 1927 switch (ppd->pp_acc_size) { 1928 default: 1929 return (IOC_INVAL); 1930 1931 case 8: 1932 case 4: 1933 case 2: 1934 case 1: 1935 if ((ppd->pp_acc_size & sizemask) == 0) 1936 return (IOC_INVAL); 1937 break; 1938 } 1939 1940 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 1941 return (IOC_INVAL); 1942 1943 if (ppd->pp_acc_offset >= maxoff) 1944 return (IOC_INVAL); 1945 1946 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 1947 return (IOC_INVAL); 1948 1949 /* 1950 * All OK - go do it! 1951 */ 1952 ppd->pp_acc_offset += mem_va; 1953 (*ppfn)(rgep, ppd); 1954 return (peek ? IOC_REPLY : IOC_ACK); 1955 } 1956 1957 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1958 struct iocblk *iocp); 1959 #pragma no_inline(rge_diag_ioctl) 1960 1961 static enum ioc_reply 1962 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1963 { 1964 ASSERT(mutex_owned(rgep->genlock)); 1965 1966 switch (cmd) { 1967 default: 1968 /* NOTREACHED */ 1969 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 1970 return (IOC_INVAL); 1971 1972 case RGE_DIAG: 1973 /* 1974 * Currently a no-op 1975 */ 1976 return (IOC_ACK); 1977 1978 case RGE_PEEK: 1979 case RGE_POKE: 1980 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 1981 1982 case RGE_PHY_RESET: 1983 return (IOC_RESTART_ACK); 1984 1985 case RGE_SOFT_RESET: 1986 case RGE_HARD_RESET: 1987 /* 1988 * Reset and reinitialise the 570x hardware 1989 */ 1990 rge_restart(rgep); 1991 return (IOC_ACK); 1992 } 1993 1994 /* NOTREACHED */ 1995 } 1996 1997 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 1998 1999 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2000 struct iocblk *iocp); 2001 #pragma no_inline(rge_mii_ioctl) 2002 2003 static enum ioc_reply 2004 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2005 { 2006 struct rge_mii_rw *miirwp; 2007 2008 /* 2009 * Validate format of ioctl 2010 */ 2011 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2012 return (IOC_INVAL); 2013 if (mp->b_cont == NULL) 2014 return (IOC_INVAL); 2015 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2016 2017 /* 2018 * Validate request parameters ... 2019 */ 2020 if (miirwp->mii_reg > MII_MAXREG) 2021 return (IOC_INVAL); 2022 2023 switch (cmd) { 2024 default: 2025 /* NOTREACHED */ 2026 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2027 return (IOC_INVAL); 2028 2029 case RGE_MII_READ: 2030 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2031 return (IOC_REPLY); 2032 2033 case RGE_MII_WRITE: 2034 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2035 return (IOC_ACK); 2036 } 2037 2038 /* NOTREACHED */ 2039 } 2040 2041 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2042 struct iocblk *iocp); 2043 #pragma no_inline(rge_chip_ioctl) 2044 2045 enum ioc_reply 2046 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2047 { 2048 int cmd; 2049 2050 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2051 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2052 2053 ASSERT(mutex_owned(rgep->genlock)); 2054 2055 cmd = iocp->ioc_cmd; 2056 switch (cmd) { 2057 default: 2058 /* NOTREACHED */ 2059 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2060 return (IOC_INVAL); 2061 2062 case RGE_DIAG: 2063 case RGE_PEEK: 2064 case RGE_POKE: 2065 case RGE_PHY_RESET: 2066 case RGE_SOFT_RESET: 2067 case RGE_HARD_RESET: 2068 #if RGE_DEBUGGING || RGE_DO_PPIO 2069 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2070 #else 2071 return (IOC_INVAL); 2072 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2073 2074 case RGE_MII_READ: 2075 case RGE_MII_WRITE: 2076 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2077 2078 } 2079 2080 /* NOTREACHED */ 2081 } 2082