1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef _QEDE_H 37 #define _QEDE_H 38 39 #include <sys/stream.h> 40 41 #include <sys/ddi.h> 42 #include <sys/ddifm.h> 43 #include <sys/dditypes.h> 44 #include <sys/sunddi.h> 45 #include <sys/fm/io/ddi.h> 46 #include <sys/mac_provider.h> 47 #include <sys/mac_ether.h> 48 #include <sys/kobj.h> 49 #include <sys/mac.h> 50 #include <sys/dlpi.h> 51 #include <sys/pattr.h> 52 #include <sys/gld.h> 53 #include <inet/ip.h> 54 #include <inet/tcp.h> 55 #include <netinet/udp.h> 56 #include <sys/ethernet.h> 57 #include <sys/pci.h> 58 #include <sys/netlb.h> 59 #include <sys/strsun.h> 60 #include <sys/strsubr.h> 61 #include <sys/policy.h> 62 63 #include "qede_version.h" 64 #include "bcm_osal.h" 65 #include "qede_fp.h" 66 67 #if 1 68 #include "ecore.h" 69 #include "ecore_status.h" 70 #include "ecore_utils.h" 71 #include "ecore_chain.h" 72 #include "ecore_hsi_common.h" 73 #include "ecore_hsi_eth.h" 74 #include "ecore_proto_if.h" 75 #include "ecore_iov_api.h" 76 #include "ecore_int_api.h" 77 #include "ecore_dev_api.h" 78 #include "ecore_l2_api.h" 79 #include "ecore_hw.h" 80 #include "nvm_cfg.h" 81 #include "ecore_mcp.h" 82 #include "ecore_dbg_fw_funcs.h" 83 #include <sys/pcie.h> 84 #include <sys/time.h> 85 #else 86 #include <ecore.h> 87 #include <ecore_status.h> 88 #include <ecore_utils.h> 89 #include <ecore_hsi_common.h> 90 #include <ecore_hsi_eth.h> 91 #include <ecore_proto_if.h> 92 #include <ecore_chain.h> 93 #include <ecore_iov_api.h> 94 #include <ecore_int_api.h> 95 #include <ecore_dev_api.h> 96 #include <ecore_ll2_api.h> 97 #include <ecore_l2_api.h> 98 #include <ecore_mcp.h> 99 #endif 100 101 102 103 #ifndef STRINGIFY 104 #define XSTRINGIFY(x) #x 105 #define STRINGIFY(x) XSTRINGIFY(x) 106 #endif 107 #define QEDE_STR_SIZE 32 108 /* Product Identification Banner */ 109 #define QEDE_PRODUCT_INFO\ 110 "QLogic FastLinQ QL45xxx " STRINGIFY(MAJVERSION) \ 111 "." STRINGIFY(MINVERSION) "." STRINGIFY(REVVERSION) 112 113 /* 114 * Debug Infrastructure 115 */ 116 #define DEBUG_NONE 0x0 117 #define DEBUG_ATTACH 0x1 118 119 #ifndef DEBUG_LEVEL 120 #define DEBUG_LEVEL DEBUG_NONE 121 #endif 122 123 #define qede_dbg(MASK, ptr, fmt, ...) \ 124 do { \ 125 if (DEBUG_LEVEL & (MASK)) { \ 126 qede_print("!%s(%d) STRINGIFY(MASK):" fmt, __func__, \ 127 (ptr)->instance, \ 128 ##__VA_ARGS__);\ 129 } \ 130 } while (0); 131 132 #define qede_info(ptr, fmt, ...) \ 133 do { \ 134 qede_print("!%s(%d):" fmt, __func__, (ptr)->instance, \ 135 ##__VA_ARGS__); \ 136 } while (0); 137 138 #define qede_warn(ptr, fmt, ...) \ 139 do { \ 140 qede_print_err("!%s(%d):" fmt, __func__, (ptr)->instance, \ 141 ##__VA_ARGS__); \ 142 } while (0); 143 144 #ifdef __sparc 145 #define QEDE_PAGE_ALIGNMENT 0x0000000000002000ull 146 #define QEDE_PAGE_SIZE 0x0000000000002000ull 147 #else 148 #define QEDE_PAGE_ALIGNMENT 0x0000000000001000ull 149 #define QEDE_PAGE_SIZE 0x0000000000001000ull 150 #endif 151 152 #define LE_TO_HOST_64 LE_64 153 #define HOST_TO_LE_64 LE_64 154 #define HOST_TO_LE_32 LE_32 155 #define LE_TO_HOST_32 LE_32 156 #define HOST_TO_LE_16 LE_16 157 #define LE_TO_HOST_16 LE_16 158 159 160 161 #define QEDE_LSO_MAXLEN 65535 162 163 #define BUF_2K_SIZE 2048 164 #define BUF_2K_ALIGNMENT BUF_2K_SIZE 165 166 #define MIN_TX_RING_COUNT 1 167 #define MAX_TX_RING_COUNT 1 168 #define DEFAULT_TX_RING_COUNT 1 169 #define MAX_TC_COUNT 1 170 #define DEFAULT_TRFK_CLASS_COUNT 1 171 172 #define MIN_TX_RING_SIZE 1024 173 #define DEFAULT_TX_RING_SIZE 8192 174 175 #define DEFAULT_TX_COPY_THRESHOLD 256 176 #define DEFAULT_TX_RECYCLE_THRESHOLD 128 177 178 #define TX_RING_MASK (tx_ring->tx_ring_size - 1) 179 180 #define IP_ALIGNMENT_BYTES 2 181 #define QEDE_MAX_ETHER_HDR 18 182 183 #define MIN_FASTPATH_COUNT 1 184 #define MAX_FASTPATH_COUNT 6 185 #define DEFAULT_FASTPATH_COUNT 4 186 187 #define MIN_RX_RING_SIZE 1024 188 #define DEFAULT_RX_RING_SIZE 8192 189 #define MAX_RX_RING_SIZE DEFAULT_RX_RING_SIZE 190 191 #define MIN_RX_BUF_SIZE 2048 192 #define MAX_RX_BUF_SIZE 2048 193 #define DEFAULT_RX_BUF_SIZE 2048 194 195 #define DEFAULT_RX_COPY_THRESHOLD 128 196 #define RX_RING_MASK (rx_ring->rx_buf_count - 1) 197 #define MIN_RX_BUF_COUNT MIN_RX_RING_SIZE 198 #define MAX_RX_BUF_COUNT MAX_RX_RING_SIZE 199 #define DEFAULT_RX_BUF_COUNT DEFAULT_RX_RING_SIZE 200 #define RX_LOW_BUFFER_THRESHOLD 128 201 202 #define USER_OPTION_CKSUM_NONE 0x0 203 #define USER_OPTION_CKSUM_L3 0x1 204 #define USER_OPTION_CKSUM_L3_L4 0x2 205 #define DEFAULT_CKSUM_OFFLOAD USER_OPTION_CKSUM_L3_L4 206 207 #define QEDE_OFFLOAD_NONE 0x00000000 208 #define QEDE_OFFLOAD_TX_IP_CKSUM 0x00000001 209 #define QEDE_OFFLOAD_RX_IP_CKSUM 0x00000002 210 #define QEDE_OFFLOAD_TX_TCP_CKSUM 0x00000004 211 #define QEDE_OFFLOAD_RX_TCP_CKSUM 0x00000008 212 #define QEDE_OFFLOAD_TX_UDP_CKSUM 0x00000010 213 #define QEDE_OFFLOAD_RX_UDP_CKSUM 0x00000020 214 215 #define DEFAULT_JUMBO_MTU 9000 216 #define MIN_MTU ETHERMTU 217 #define MAX_MTU DEFAULT_JUMBO_MTU 218 #define DEFAULT_MTU ETHERMTU 219 220 #define DEFAULT_ECORE_DEBUG_LEVEL ECORE_LEVEL_VERBOSE 221 222 223 #define DEFAULT_ECORE_DEBUG_MODULE ECORE_MSG_DRV 224 225 #define VLAN_TAGSZ 0x4 226 227 #define MAX_TC 1 228 229 #define DUPLEX_HALF 0 230 #define DUPLEX_FULL 1 231 232 #define ETH_ALLEN 6 233 234 #define MAC_STRING "%2x:%2x:%2x:%2x:%2x:%2x" 235 #define MACTOSTR(a) a[0], a[1], a[2], a[3], a[4], a[5] 236 237 #define MAX_MC_SOFT_LIMIT 1024 238 239 #define qede_delay(_msecs_) delay(drv_usectohz(_msecs_ * 1000)) 240 241 #define QEDE_CMD 73 242 243 244 typedef struct _KstatRingMap 245 { 246 uint32_t idx; /* ring index */ 247 void * qede; /* reference back to qede_t */ 248 } KstatRingMap; 249 250 #define IS_ETH_MULTICAST(eth_addr) \ 251 (((unsigned char *) (eth_addr))[0] & ((unsigned char) 0x01)) 252 253 #define IS_ETH_ADDRESS_EQUAL(eth_addr1, eth_addr2) \ 254 ((((unsigned char *) (eth_addr1))[0] == \ 255 ((unsigned char *) (eth_addr2))[0]) && \ 256 (((unsigned char *) (eth_addr1))[1] == \ 257 ((unsigned char *) (eth_addr2))[1]) && \ 258 (((unsigned char *) (eth_addr1))[2] == \ 259 ((unsigned char *) (eth_addr2))[2]) && \ 260 (((unsigned char *) (eth_addr1))[3] == \ 261 ((unsigned char *) (eth_addr2))[3]) && \ 262 (((unsigned char *) (eth_addr1))[4] == \ 263 ((unsigned char *) (eth_addr2))[4]) && \ 264 (((unsigned char *) (eth_addr1))[5] == \ 265 ((unsigned char *) (eth_addr2))[5])) 266 267 #define COPY_ETH_ADDRESS(src, dst) \ 268 ((unsigned char *) (dst))[0] = ((unsigned char *) (src))[0]; \ 269 ((unsigned char *) (dst))[1] = ((unsigned char *) (src))[1]; \ 270 ((unsigned char *) (dst))[2] = ((unsigned char *) (src))[2]; \ 271 ((unsigned char *) (dst))[3] = ((unsigned char *) (src))[3]; \ 272 ((unsigned char *) (dst))[4] = ((unsigned char *) (src))[4]; \ 273 ((unsigned char *) (dst))[5] = ((unsigned char *) (src))[5]; 274 275 276 union db_prod { 277 struct eth_db_data data; 278 uint32_t raw; 279 }; 280 281 struct qede; 282 struct qede_fastpath; 283 struct qede_rx_ring; 284 struct qede_tx_pktinfo_s; 285 286 typedef struct qede_tx_ring { 287 struct qede_fastpath *fp; 288 struct qede *qede; 289 uint32_t tx_queue_index; 290 uint16_t *hw_cons_ptr; 291 292 /* pointer to driver ring control */ 293 struct ecore_chain tx_bd_ring; 294 u16 sw_tx_cons; 295 u16 sw_tx_prod; 296 u16 bd_ring_size; 297 298 /* From ecore_sp_tx_queue_start() */ 299 void __iomem *doorbell_addr; 300 ddi_acc_handle_t doorbell_handle; 301 302 /* Saved copy of doorbell data for this tx queue */ 303 union db_prod tx_db; 304 305 uint32_t fp_idx; 306 kmutex_t tx_lock; 307 int tx_buf_size; 308 uint32_t tx_ring_size; 309 bool queue_started; 310 mac_ring_handle_t mac_ring_handle; 311 312 /* pre-allocated bcopy packets */ 313 qede_tx_bcopy_list_t bcopy_list; 314 /* pre-allocated dma handles */ 315 qede_dma_handles_list_t dmah_list; 316 /* List of recycle entires for tx packets */ 317 qede_tx_recycle_list_t *tx_recycle_list; 318 319 #ifdef DBLK_DMA_PREMAP 320 pm_handle_t pm_handle; 321 #endif 322 /* dma_handle for tx bd ring */ 323 ddi_dma_handle_t tx_bd_dmah; 324 ddi_dma_handle_t tx_pbl_dmah; 325 326 bool tx_q_sleeping; 327 328 uint64_t tx_pkt_count; 329 uint64_t tx_byte_count; 330 uint64_t tx_pkt_dropped; 331 uint64_t tx_copy_count; 332 uint64_t tx_bind_count; 333 uint64_t tx_bind_fail; 334 uint64_t tx_premap_count; 335 uint64_t tx_premap_fail; 336 uint64_t tx_pullup_count; 337 uint64_t tx_too_many_cookies; 338 uint64_t tx_lso_pkt_count; 339 uint64_t tx_ring_pause; 340 uint64_t tx_too_many_mblks; 341 uint64_t tx_mapped_pkts; 342 uint64_t tx_jumbo_pkt_count; 343 struct ecore_queue_cid *p_cid; 344 } qede_tx_ring_t; 345 346 347 typedef struct qede_vector_info { 348 /* 349 * Pointer to a fastpath structure, 350 * or to a hwfnc. 351 */ 352 void *fp; 353 struct qede *qede; 354 uint32_t vect_index; 355 bool handler_added; 356 /* set and cleared by ISR, checked by stop path 357 * when waiting for quiesce 358 */ 359 bool in_isr; 360 } qede_vector_info_t; 361 362 363 typedef struct qede_fastpath { 364 qede_vector_info_t *vect_info; 365 366 /* Status block associated with this fp */ 367 ddi_dma_handle_t sb_dma_handle; 368 ddi_acc_handle_t sb_acc_handle; 369 struct status_block *sb_virt; 370 uint64_t sb_phys; 371 372 struct ecore_sb_info *sb_info; 373 struct qede_rx_ring *rx_ring; 374 qede_tx_ring_t *tx_ring[MAX_TC]; 375 struct qede *qede; 376 377 uint32_t fp_index; 378 uint32_t fp_hw_eng_index; 379 uint32_t vport_id; /* */ 380 uint32_t stats_id; /* vport id to hold stats */ 381 uint32_t rx_queue_index; 382 uint32_t rss_id; 383 kmutex_t fp_lock; 384 uint32_t disabled_by_poll; 385 } qede_fastpath_t; 386 387 enum qede_agg_state { 388 QEDE_AGG_STATE_NONE = 0, 389 QEDE_AGG_STATE_START = 1, 390 QEDE_AGG_STATE_ERROR = 2 391 }; 392 393 #define QEDE_MAX_BD_PER_AGG 16 394 struct qede_rx_buffer_s; 395 typedef struct qede_lro_info { 396 uint16_t pars_flags; 397 uint16_t pad; 398 uint16_t vlan_tag; 399 uint16_t bd_count; 400 uint32_t rss_hash; 401 uint32_t header_len; 402 uint32_t free_buffer_count; 403 struct qede_rx_buffer_s *rx_buffer[QEDE_MAX_BD_PER_AGG]; 404 enum qede_agg_state agg_state; 405 } qede_lro_info_t; 406 407 typedef struct qede_dma_info_s { 408 ddi_acc_handle_t acc_handle; 409 ddi_dma_handle_t dma_handle; 410 u32 ncookies; 411 u32 offset; 412 u64 phys_addr; 413 void *virt_addr; 414 u32 pad; 415 } qede_dma_info_t; 416 417 enum rx_buf_state { 418 RX_BUF_STATE_FREE, 419 RX_BUF_STATE_WITH_FW, 420 RX_BUF_STATE_WITH_OS, 421 RX_BUF_STATE_WITH_DRV, 422 }; 423 424 struct qede_rx_buf_area; 425 426 typedef struct qede_rx_buffer_s { 427 qede_dma_info_t dma_info; 428 mblk_t *mp; 429 u32 index; 430 struct qede_rx_ring *rx_ring; 431 432 /* Recycle function */ 433 frtn_t recycle; 434 u32 ref_cnt; 435 enum rx_buf_state buf_state; 436 struct qede_rx_buf_area *rx_buf_area; 437 } qede_rx_buffer_t; 438 439 typedef struct qede_rx_buf_list_s { 440 kmutex_t lock; 441 u16 head, tail; 442 u32 num_entries; 443 qede_rx_buffer_t *buf_list[DEFAULT_RX_RING_SIZE]; 444 } qede_rx_buf_list_t; 445 446 typedef struct qede_rx_buf_area { 447 //kmutex_t rx_buf_area_lock; 448 qede_rx_buffer_t rx_buf_pool[DEFAULT_RX_RING_SIZE]; 449 450 qede_rx_buf_list_t active_buf_list; 451 qede_rx_buf_list_t passive_buf_list; 452 453 u32 bufs_per_page; 454 struct qede_rx_ring *rx_ring; 455 u32 inactive; 456 u32 buf_upstream; 457 } qede_rx_buf_area_t; 458 459 typedef struct qede_rx_ring { 460 uint32_t rx_buf_count; 461 uint32_t rx_buf_size; 462 /* 463 * Pointer to an array of producer indicies. 464 * Returned in call to ecore_sp_eth_rx_queue_start() 465 * during qede_start(). Driver uses address 466 * to update producer indicies for 467 * CQE and RX buffer chains. 468 */ 469 void __iomem *hw_rxq_prod_addr; 470 471 /* Pointer to hw cqe consumer index. 472 * Taken from sb_virt->pi_array after 473 * rx_ring has been started by calling 474 * ecore_sp_eth_rx_queue_start(). 475 * This value is little endian and requires 476 * swapping on big endian platforms. 477 * It is updated by ecore and read by 478 * the driver while processing rings. 479 */ 480 uint16_t *hw_cons_ptr; 481 482 u16 sw_rx_cons; 483 u16 sw_rx_prod; 484 u16 last_cqe_consumer; 485 486 /* 487 * Driver buffer descriptor ring defining 488 * buffers on a one-to-one releationship 489 * to ecore_chain rx_bd_ring. 490 */ 491 qede_rx_buffer_t *rx_buffers; 492 qede_rx_buf_area_t *rx_buf_area; 493 /* 494 * Descriptor rings returned from 495 * ecore_chain_alloc() 496 */ 497 struct ecore_chain rx_bd_ring; 498 struct ecore_chain rx_cqe_ring; 499 500 uint32_t rss_id; 501 bool queue_started; 502 bool mac_ring_started; 503 kmutex_t rx_lock; 504 kmutex_t rx_replen_lock; 505 mac_ring_handle_t mac_ring_handle; 506 u64 mr_gen_num; /* Mac rings generation number */ 507 uint32_t group_index; 508 qede_fastpath_t *fp; 509 struct qede *qede; 510 511 /* dma_handles for rx dma mem */ 512 ddi_dma_handle_t rx_bd_dmah; 513 ddi_dma_handle_t rx_cqe_dmah; 514 ddi_dma_handle_t rx_cqe_pbl_dmah; 515 uint32_t rx_copy_threshold; 516 uint32_t rx_low_buffer_threshold; 517 struct qede_lro_info lro_info[ETH_TPA_MAX_AGGS_NUM]; 518 uint32_t lro_active_count; 519 520 uint64_t rx_copy_cnt; 521 uint64_t rx_drop_cnt; 522 uint64_t rx_low_water_cnt; 523 uint64_t rx_poll_cnt; 524 uint64_t rx_reg_pkt_cnt; 525 uint64_t rx_jumbo_pkt_cnt; 526 uint64_t rx_lro_pkt_cnt; 527 uint64_t rx_byte_cnt; 528 uint64_t rx_pkt_cnt; 529 uint8_t intrEnableCnt; 530 uint8_t intrDisableCnt; 531 struct ecore_queue_cid *p_cid; 532 } qede_rx_ring_t; 533 534 typedef uint32_t qede_offload_t; 535 typedef struct qede_params { 536 qede_offload_t enabled_offloads; 537 boolean_t multi_promisc_fl; 538 boolean_t promisc_fl; 539 uint32_t link_state; 540 u32 loopback_mode; 541 } qede_params_t; 542 543 typedef struct qede_intr_context { 544 /* bit field indicating enable/disable state of vector */ 545 volatile uint32_t intr_state; 546 qede_vector_info_t *intr_vect_info; 547 int intr_vect_info_array_size; /* based on hw max vectors */ 548 ddi_intr_handle_t *intr_hdl_array; /* handle array from ddi_intr_alloc() */ 549 int intr_hdl_array_size; /* based on hw max vectors */ 550 int intr_types_available; /* from ddi_intr_get_supported_types */ 551 int intr_type_forced; /* from qede.conf */ 552 int intr_type_in_use; /* interrupt type currently used */ 553 int intr_vect_supported; /* from ddi_intr_get_nintrs */ 554 int intr_vect_available; /* from ddi_intr_get_navail */ 555 int intr_vect_to_request; /* intr count requested */ 556 int intr_vect_allocated; /* intr count taken */ 557 uint32_t intr_pri; 558 int intr_cap; 559 uint32_t intr_fp_vector_count; 560 enum ecore_int_mode intr_mode; 561 } qede_intr_context_t; 562 563 #define QEDE_LINK_PAUSE_AUTONEG_ENABLE (1 << 0) 564 #define QEDE_LINK_PAUSE_RX_ENABLE (1 << 1) 565 #define QEDE_LINK_PAUSE_TX_ENABLE (1 << 2) 566 567 typedef struct qede_props { 568 uint32_t link_speed; 569 boolean_t link_duplex; 570 boolean_t tx_pause; 571 boolean_t rx_pause; 572 time_t uptime; 573 } qede_props_t; 574 575 typedef struct qede_link_props { 576 uint8_t port_type; 577 boolean_t autoneg; 578 boolean_t asym_pause; 579 boolean_t pause; 580 boolean_t param_100000fdx; 581 boolean_t param_50000fdx; 582 boolean_t param_40000fdx; 583 boolean_t param_25000fdx; 584 boolean_t param_10000fdx; 585 boolean_t param_1000fdx; 586 boolean_t param_1000hdx; 587 } qede_link_props_t; 588 589 typedef struct qede_link_cfg { 590 boolean_t link_up; 591 uint32_t speed; 592 uint8_t duplex; 593 uint8_t port; 594 boolean_t autoneg; 595 uint32_t pause_cfg; 596 qede_link_props_t supp_capab; 597 qede_link_props_t adv_capab; 598 qede_link_props_t rem_capab; 599 } qede_link_cfg_t; 600 601 enum qede_filter_type { 602 QEDE_FILTER_UCAST, 603 QEDE_FILTER_MCAST, 604 QEDE_FILTER_RX_MODE, 605 QEDE_MAX_FILTER_TYPES, 606 607 }; 608 609 enum qede_filter_rx_mode_type { 610 QEDE_FILTER_RX_MODE_REGULAR, 611 QEDE_FILTER_RX_MODE_MULTI_PROMISC, 612 QEDE_FILTER_RX_MODE_PROMISC, 613 }; 614 615 616 617 struct qede_mcast_filter_params { 618 enum qede_filter_rx_mode_type acc_flg; 619 struct ecore_filter_mcast mcast; 620 }; 621 622 #define QEDE_MAX_UCST_CNT 8 623 typedef struct qede_mac_addr { 624 struct ether_addr mac_addr; 625 boolean_t set; 626 } qede_mac_addr_t; 627 628 629 630 enum qede_state { 631 QEDE_STATE_UNKNOWN, 632 QEDE_STATE_ATTACHED, 633 QEDE_STATE_STARTING, /* Transitioning State */ 634 QEDE_STATE_STARTED, 635 QEDE_STATE_STOPPING, /* Transitioning State */ 636 QEDE_STATE_STOPPED, 637 QEDE_STATE_SUSPENDING, /* Transitioning State */ 638 QEDE_STATE_SUSPENDED, 639 QEDE_STATE_RESUMING, /* Transitioning State */ 640 QEDE_STATE_FAILED, 641 }; 642 643 enum qede_attach_resources { 644 QEDE_STRUCT_ALLOC = (1 << 0), 645 QEDE_FM = (1 << 1), 646 QEDE_PCI = (1 << 2), 647 QEDE_ECORE_HW_PREP = (1 << 3), 648 QEDE_SET_PARAMS = (1 << 4), 649 QEDE_CALLBACK = (1 << 5), 650 QEDE_IO_STRUCT_ALLOC = (1 << 6), 651 QEDE_INIT_LOCKS = (1 << 7), 652 QEDE_INTR_ALLOC = (1 << 8), 653 QEDE_INTR_CONFIG = (1 << 9), 654 QEDE_EDEV_CONFIG = (1 << 10), 655 QEDE_KSTAT_INIT = (1 << 11), 656 QEDE_GLD_INIT = (1 << 12), 657 QEDE_SP_INTR_ENBL = (1 << 13), 658 QEDE_ECORE_HW_INIT = (1 << 14), 659 /* 660 = (1 << 15), 661 = (1 << 16), 662 = (1 << 17), 663 = (1 << 18), 664 = (1 << 19), 665 = (1 << 20), 666 */ 667 }; 668 669 enum qede_vport_state { 670 QEDE_VPORT_UNKNOWN, 671 QEDE_VPORT_STARTED, 672 QEDE_VPORT_ON, 673 QEDE_VPORT_OFF, 674 QEDE_VPORT_STOPPED 675 }; 676 677 #define QEDE_MAX_GROUPS 1 678 typedef struct qede_mac_group { 679 int group_index; 680 mac_group_handle_t group_handle; 681 struct qede *qede; 682 } qede_mac_group_t; 683 684 typedef struct qede_link_input_params { 685 struct ecore_mcp_link_params default_link_params; 686 u32 loopback_mode; 687 }qede_link_input_params_t; 688 689 typedef struct qede { 690 struct ecore_dev edev; /* keep this at the beginning of the structure */ 691 dev_info_t *dip; 692 int instance; 693 enum qede_state qede_state; 694 #define MAX_QEDE_NAME_LEN 8 695 char name[MAX_QEDE_NAME_LEN]; 696 697 /* PCI access handle */ 698 ddi_acc_handle_t pci_cfg_handle; 699 700 /* BAR 0 - registers */ 701 ddi_acc_handle_t regs_handle; 702 off_t regview_size; 703 caddr_t regview; 704 uint64_t pci_bar0_base; 705 706 /* BAR 2 - doorbell */ 707 ddi_acc_handle_t doorbell_handle; 708 off_t doorbell_size; 709 caddr_t doorbell; 710 uint64_t pci_bar2_base; 711 712 /* Vport params */ 713 struct ecore_sp_vport_update_params vport_params[MAX_HWFNS_PER_DEVICE]; 714 struct ecore_rss_params rss_params[MAX_HWFNS_PER_DEVICE]; 715 enum qede_vport_state vport_state[MAX_HWFNS_PER_DEVICE]; 716 717 /* mac Layer related vars */ 718 mac_handle_t mac_handle; 719 qede_mac_group_t rx_groups[QEDE_MAX_GROUPS]; 720 qede_mac_group_t tx_groups[QEDE_MAX_GROUPS]; 721 722 u8 *sp_dpc; 723 /* 724 * pre-mapped buffer cache handle for TX 725 * used for getting sglist for mbkls 726 * that were already mapped in mac layer 727 */ 728 #ifdef DBLK_DMA_PREMAP 729 pm_handle_t pm_handle; 730 #endif 731 732 /* current operating paramters */ 733 uint32_t mtu; 734 uint32_t num_fp; 735 uint32_t mc_cnt; 736 737 uint32_t tx_ring_size; 738 uint32_t tx_buf_size; 739 uint16_t tx_recycle_threshold; 740 u16 pad; // remove later 741 742 int checksum; 743 qede_offload_t enabled_offloads; 744 uint32_t rx_ring_size; 745 uint32_t rx_buf_count; 746 uint32_t rx_buf_size; 747 uint32_t rx_copy_threshold; 748 uint32_t rx_low_buffer_threshold; 749 boolean_t lso_enable; 750 boolean_t lro_enable; 751 boolean_t jumbo_enable; 752 boolean_t log_enable; 753 uint32_t ecore_debug_level; 754 uint32_t ecore_debug_module; 755 boolean_t intr_coalesce; 756 uint32_t intr_rx_coal_usec; 757 uint32_t intr_tx_coal_usec; 758 759 /* From ecore_hw_init */ 760 uint32_t num_hwfns; 761 unsigned char ether_addr[ETHERADDRL]; 762 uint32_t num_tc; 763 764 qede_mac_addr_t ucst_mac[QEDE_MAX_UCST_CNT]; 765 uint32_t ucst_total; 766 uint32_t ucst_avail; 767 qede_mac_addr_t suspnd_mac_list[QEDE_MAX_UCST_CNT]; 768 769 770 /* software data structures for tx/rx */ 771 qede_intr_context_t intr_ctx; 772 qede_fastpath_t fp_array[MAX_FASTPATH_COUNT]; 773 struct ecore_sb_info sb_array[MAX_FASTPATH_COUNT]; 774 qede_rx_ring_t rx_array[MAX_FASTPATH_COUNT]; 775 qede_tx_ring_t tx_array[MAX_TC_COUNT][MAX_FASTPATH_COUNT]; 776 777 uint16_t tx_bcopy_threshold; 778 uint16_t pad1; /* remove later */ 779 780 /* status_block phys mem */ 781 bool sb_phy_mem_alloc; 782 783 kmutex_t drv_lock; 784 kmutex_t watch_lock; 785 uint32_t callback_flags; 786 enum qede_attach_resources attach_resources; 787 788 /* 789 * qede osal mem management queues 790 */ 791 qede_phys_mem_list_t phys_mem_list; 792 qede_mem_list_t mem_list; 793 794 qede_props_t props; 795 qede_link_cfg_t hwinit; 796 qede_link_cfg_t curcfg; 797 qede_params_t params; 798 volatile uint32_t plumbed; 799 qede_mcast_list_t mclist; 800 801 uint32_t mfw_ver; 802 803 char devName[QEDE_STR_SIZE]; 804 char version[QEDE_STR_SIZE]; 805 char versionFW[QEDE_STR_SIZE]; 806 char versionMFW[QEDE_STR_SIZE]; 807 char chip_name[QEDE_STR_SIZE]; 808 char chipID[QEDE_STR_SIZE]; 809 char intrAlloc[QEDE_STR_SIZE]; 810 char bus_dev_func[QEDE_STR_SIZE]; 811 char vendor_device[QEDE_STR_SIZE]; 812 813 uint64_t txTotalPkts; 814 uint64_t txTotalBytes; 815 uint64_t txTotalDiscards; 816 uint64_t rxTotalPkts; 817 uint64_t rxTotalBytes; 818 uint64_t rxTotalDiscards; 819 820 uint64_t intrFired; 821 kmutex_t kstat_lock; 822 kmutex_t gld_lock; 823 uint64_t intrSbCnt[MAX_FASTPATH_COUNT + 1]; 824 uint64_t intrSbNoChangeCnt[MAX_FASTPATH_COUNT + 1]; 825 uint64_t intrSbPollCnt[MAX_FASTPATH_COUNT + 1]; 826 uint64_t intrSbPollNoChangeCnt[MAX_FASTPATH_COUNT + 1]; 827 828 kstat_t *kstats; 829 kstat_t *kstats_link; 830 kstat_t *kstats_intr; 831 kstat_t *kstats_vport; 832 kstat_t *kstats_rxq[MAX_FASTPATH_COUNT]; 833 KstatRingMap kstats_rxq_map[MAX_FASTPATH_COUNT]; 834 kstat_t *kstats_txq[MAX_FASTPATH_COUNT]; 835 KstatRingMap kstats_txq_map[MAX_FASTPATH_COUNT]; 836 struct ecore_eth_stats save_stats; 837 838 mblk_t *stored_mp; 839 int mp_index; 840 qede_link_input_params_t link_input_params; /*(test) */ 841 uint32_t loop_back_mode; /*(test) */ 842 bool lb_linkup; /*(test) */ 843 uint32_t forced_speed_10G; 844 uint8_t pci_func; 845 void *nvm_buf; 846 void *nvm_buf_start; 847 uint32_t nvm_buf_size; 848 uint32_t copy_len; 849 uint8_t *reserved_buf; 850 int fm_cap; 851 uint64_t allocbFailures; 852 volatile uint32_t detach_unsafe; 853 854 } qede_t; 855 856 /* 857 * ioctl commands 858 */ 859 860 typedef enum { 861 QEDE_DRV_INFO = 2, 862 QEDE_RD_PCICFG, 863 QEDE_WR_PCICFG, 864 QEDE_RW_REG, 865 QEDE_RW_NVRAM, 866 QEDE_FUNC_INFO, 867 QEDE_MAC_ADDR 868 } qede_ioctl_cmd_t; 869 870 871 872 /* 873 * ioctl message structure for FW update utility 874 */ 875 876 /* regiser read/write commands */ 877 #define QEDE_REG_READ 0 878 #define QEDE_REG_WRITE 1 879 880 /* nvram read/write commands */ 881 #define QEDE_NVRAM_CMD_READ 0 882 #define QEDE_NVRAM_CMD_WRITE 1 883 #define QEDE_NVRAM_CMD_PUT_FILE_DATA 2 884 #define QEDE_NVRAM_CMD_SET_SECURE_MODE 3 885 #define QEDE_NVRAM_CMD_DEL_FILE 4 886 #define QEDE_NVRAM_CMD_PUT_FILE_BEGIN 5 887 #define QEDE_NVRAM_CMD_GET_NVRAM_RESP 6 888 889 typedef struct { 890 uint32_t cmd; 891 uint32_t unused1; 892 uint64_t off; 893 uint32_t size; 894 uint32_t rv; 895 char uabc[2048]; 896 uint64_t address; 897 void *ptr; 898 } qede_ioctl_data_t; 899 900 typedef struct { 901 uint32_t cmd; 902 uint32_t unused1; 903 uint64_t off; 904 uint32_t size; 905 uint32_t buf_size; 906 char uabc[2048]; 907 uint64_t cmd2; 908 #define START_NVM_WRITE 1 909 #define ACCUMULATE_NVM_BUF 2 910 #define STOP_NVM_WRITE 3 911 #define READ_BUF 4 912 void *ptr; 913 }qede_nvram_data_t; 914 915 typedef struct { 916 char drv_name[MAX_QEDE_NAME_LEN]; 917 char drv_version[QEDE_STR_SIZE]; 918 char mfw_version[QEDE_STR_SIZE]; 919 char stormfw_version[QEDE_STR_SIZE]; 920 uint32_t eeprom_dump_len; /* in bytes */ 921 uint32_t reg_dump_len; /* in bytes */ 922 char bus_info[QEDE_STR_SIZE]; 923 } qede_driver_info_t; 924 925 typedef struct { 926 uint32_t supported; /* Features this interface supports */ 927 uint32_t advertising; /* Features this interface advertises */ 928 uint32_t speed; /* The forced speed, 10Mb, 100Mb, gigabit */ 929 uint32_t duplex; /* Duplex, half or full */ 930 uint32_t port; /* Which connector port */ 931 uint32_t phy_address; /* port number*/ 932 uint32_t autoneg; /* Enable or disable autonegotiation */ 933 } qede_func_info_t; 934 935 936 typedef struct { 937 bool link_up; 938 u32 supported_caps; /* In SUPPORTED defs */ 939 u32 advertised_caps; /* In ADVERTISED defs */ 940 u32 lp_caps; /* In ADVERTISED defs */ 941 u32 speed; /* In Mb/s */ 942 u8 duplex; /* In DUPLEX defs */ 943 u8 port; /* In PORT defs */ 944 bool autoneg; 945 } qede_link_output_t; 946 947 #define PORT_FIBRE (1) 948 #define SUPPORTED_FIBRE (1 << 15) 949 #define SUPPORTED_Autoneg (1 << 16) 950 #define SUPPORTED_Pause (1 << 17) 951 #define SUPPORTED_Asym_Pause (1 << 18) 952 #define SUPPORTED_1000baseT_Half (1 << 19) 953 #define SUPPORTED_1000baseT_Full (1 << 20) 954 #define SUPPORTED_10000baseKR_Full (1 << 21) 955 #define SUPPORTED_20000baseKR2_Full (1 << 22) 956 #define SUPPORTED_40000baseKR4_Full (1 << 23) 957 #define SUPPORTED_40000baseCR4_Full (1 << 24) 958 #define SUPPORTED_40000baseSR4_Full (1 << 25) 959 #define SUPPORTED_40000baseLR4_Full (1 << 26) 960 961 962 963 typedef struct { 964 uint32_t cmd; 965 #define QEDE_PCICFG_READ 0x01 966 #define QEDE_PCICFG_WRITE 0x02 967 uint32_t reg; 968 uint32_t val; 969 uint32_t width; 970 } qede_pcicfg_rdw_t; 971 /* 972 * (Internal) return values from ioctl subroutines 973 * 974 */ 975 enum ioc_reply { 976 IOC_INVAL = -1, /* bad, NAK with EINVAL */ 977 IOC_DONE, /* OK, reply sent */ 978 IOC_ACK, /* OK, just send ACK */ 979 IOC_REPLY, /* OK, just send reply */ 980 IOC_RESTART_ACK, /* OK, restart & ACK */ 981 IOC_RESTART_REPLY /* OK, restart & reply */ 982 }; 983 984 /* 985 * Loop Back Modes 986 */ 987 enum { 988 QEDE_LOOP_NONE, 989 QEDE_LOOP_INTERNAL, 990 QEDE_LOOP_EXTERNAL, 991 }; 992 993 /* Loopback test return values */ 994 enum { 995 QEDE_LB_TEST_OK, 996 QEDE_LB_SEND_WAIT_QUEUE_ERR, 997 QEDE_LB_NORCV_ERR, 998 QEDE_LB_NOMEM_ERR, 999 QEDE_LB_TX_QUEUE_ERR, 1000 QEDE_LB_SHORT_DATA_ERR, 1001 QEDE_LB_SEQUENCE_ERR, 1002 QEDE_LB_DATA_ERR, 1003 QEDE_LB_ERRCNT, 1004 QEDE_LB_NOT_SUPPORTED, 1005 QEDE_LB_TEST_CHECK_CABLE, 1006 QEDE_LB_TEST_IN_PROGRESS 1007 }; 1008 1009 extern qede_link_props_t qede_def_link_props; 1010 /* Functions exported by qede_cfg.c */ 1011 void qede_cfg_reset(qede_t *qede); 1012 void qede_cfg_init(qede_t *qede); 1013 1014 /* Functions exported by qede_gld.c */ 1015 boolean_t qede_gld_init(qede_t *qede); 1016 int qede_multicast(qede_t * qede, boolean_t flag, const uint8_t *ptr_mcaddr); 1017 int qede_set_filter_rx_mode(qede_t *qede, enum qede_filter_rx_mode_type type); 1018 int qede_set_rx_mac_mcast(qede_t *qede, enum ecore_filter_opcode opcode, 1019 uint8_t *mac, int mc_cnt); 1020 int qede_ucst_find(qede_t *qede, const uint8_t *mac_addr); 1021 int qede_clear_filters(qede_t *qede); 1022 /* Functions exported by qede_main.c */ 1023 int 1024 qede_stop(qede_t *); 1025 int 1026 qede_start(qede_t *); 1027 1028 #define QEDE_DOORBELL_WR qede_bar2_write32_tx_doorbell 1029 void 1030 qede_bar2_write32_tx_doorbell(qede_tx_ring_t *tx_ring, u32 val); 1031 void 1032 qede_enable_hw_intr(qede_fastpath_t *); 1033 void 1034 qede_disable_hw_intr(qede_fastpath_t *); 1035 1036 /* Functions exported by qede_dbg.c */ 1037 extern void 1038 qede_stacktrace(qede_t *); 1039 extern void 1040 qede_print_vport_params(qede_t *, 1041 struct ecore_sp_vport_update_params *); 1042 void 1043 qede_dump_single_mblk(qede_t *qede, mblk_t *mp); 1044 void 1045 qede_dump_mblk_chain_bnext_ptr(qede_t *qede, mblk_t *mp); 1046 void 1047 qede_dump_mblk_chain_bcont_ptr(qede_t *qede, mblk_t *mp); 1048 void 1049 qede_dump_bytes(char *, int); 1050 void qede_dump_reg_cqe(struct eth_fast_path_rx_reg_cqe *cqe); 1051 void qede_dump_start_lro_cqe(struct eth_fast_path_rx_tpa_start_cqe *); 1052 void qede_dump_cont_lro_cqe(struct eth_fast_path_rx_tpa_cont_cqe *); 1053 void qede_dump_end_lro_cqe(struct eth_fast_path_rx_tpa_end_cqe *); 1054 void qede_dump_mblk_chain_bcont_ptr(qede_t *, mblk_t *); 1055 1056 /* Functions exported by qede_fp.c */ 1057 mblk_t *qede_fp_poll(void *arg, int poll_bytes, int poll_pkts); 1058 int qede_fp_stat(mac_ring_driver_t rh, uint_t stat, u64 *val); 1059 mblk_t * 1060 qede_process_fastpath(qede_fastpath_t *fp, 1061 int nbytes, int npkts, int *work_done); 1062 void 1063 qede_desc_dma_mem_sync(ddi_dma_handle_t *dma_handle, 1064 uint_t start, uint_t count, uint_t range, 1065 uint_t unit_size, uint_t direction); 1066 1067 /* Functions exported by qede_osal.c */ 1068 u32 qede_osal_cleanup(qede_t *qede); 1069 int 1070 qede_osal_find_dma_handle_for_block(qede_t *qede, void *addr, 1071 ddi_dma_handle_t *dma_handle); 1072 1073 /* Functions exported by qede_main.c */ 1074 int 1075 qede_get_mag_elem(qede_rx_ring_t *, qede_rx_buffer_t *); 1076 void 1077 qede_update_rx_q_producer(qede_rx_ring_t *rx_ring); 1078 void qede_get_link_info(struct ecore_hwfn *hwfn,struct qede_link_cfg *lnkcfg); 1079 int 1080 qede_put_to_passive_list(qede_rx_ring_t *rx_ring, qede_rx_buffer_t *rx_buffer); 1081 qede_rx_buffer_t * 1082 qede_get_from_active_list(qede_rx_ring_t *, uint32_t *); 1083 void 1084 qede_replenish_rx_buffers(qede_rx_ring_t *); 1085 void 1086 qede_recycle_copied_rx_buffer(qede_rx_buffer_t *rx_buffer); 1087 boolean_t qede_kstat_init(qede_t *qede); 1088 void qede_kstat_fini(qede_t *qede); 1089 /*void qede_get_current_link(qede_t *qede, struct qede_link_cfg *lnkcfg);*/ 1090 #endif /* _QEDE_H */ 1091