1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __ECORE_HSI_TOOLS__ 37 #define __ECORE_HSI_TOOLS__ 38 39 /**********************************/ 40 /* Tools HSI constants and macros */ 41 /**********************************/ 42 43 /* Width of GRC address in bits (addresses are specified in dwords) */ 44 #define GRC_ADDR_BITS 23 45 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1) 46 47 /* indicates an init that should be applied to any phase ID */ 48 #define ANY_PHASE_ID 0xffff 49 50 /* init pattern size in bytes */ 51 #define INIT_PATTERN_SIZE_BITS 4 52 #define MAX_INIT_PATTERN_SIZE (1 << INIT_PATTERN_SIZE_BITS) 53 54 /* Max size in dwords of a zipped array */ 55 #define MAX_ZIPPED_SIZE 8192 56 57 /* Global PXP window */ 58 #define NUM_OF_PXP_WIN 19 59 #define PXP_WIN_DWORD_SIZE_BITS 10 60 #define PXP_WIN_DWORD_SIZE (1 << PXP_WIN_DWORD_SIZE_BITS) 61 #define PXP_WIN_BYTE_SIZE_BITS (PXP_WIN_DWORD_SIZE_BITS + 2) 62 #define PXP_WIN_BYTE_SIZE (PXP_WIN_DWORD_SIZE * 4) 63 64 65 /* 66 * Binary buffer header 67 */ 68 struct bin_buffer_hdr 69 { 70 __le32 offset /* buffer offset in bytes from the beginning of the binary file */; 71 __le32 length /* buffer length in bytes */; 72 }; 73 74 75 /* 76 * binary buffer types 77 */ 78 enum bin_buffer_type 79 { 80 BIN_BUF_FW_VER_INFO /* fw_ver_info struct */, 81 BIN_BUF_INIT_CMD /* init commands */, 82 BIN_BUF_INIT_VAL /* init data */, 83 BIN_BUF_INIT_MODE_TREE /* init modes tree */, 84 BIN_BUF_IRO /* internal RAM offsets array */, 85 MAX_BIN_BUFFER_TYPE 86 }; 87 88 89 /* 90 * init array header: raw 91 */ 92 struct init_array_raw_hdr 93 { 94 __le32 data; 95 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 96 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 97 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */ 98 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 99 }; 100 101 102 /* 103 * init array header: standard 104 */ 105 struct init_array_standard_hdr 106 { 107 __le32 data; 108 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 109 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 110 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */ 111 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 112 }; 113 114 115 /* 116 * init array header: zipped 117 */ 118 struct init_array_zipped_hdr 119 { 120 __le32 data; 121 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 122 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 123 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */ 124 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 125 }; 126 127 128 /* 129 * init array header: pattern 130 */ 131 struct init_array_pattern_hdr 132 { 133 __le32 data; 134 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 135 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 136 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */ 137 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 138 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */ 139 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 140 }; 141 142 143 /* 144 * init array header union 145 */ 146 union init_array_hdr 147 { 148 struct init_array_raw_hdr raw /* raw init array header */; 149 struct init_array_standard_hdr standard /* standard init array header */; 150 struct init_array_zipped_hdr zipped /* zipped init array header */; 151 struct init_array_pattern_hdr pattern /* pattern init array header */; 152 }; 153 154 155 /* 156 * init array types 157 */ 158 enum init_array_types 159 { 160 INIT_ARR_STANDARD /* standard init array */, 161 INIT_ARR_ZIPPED /* zipped init array */, 162 INIT_ARR_PATTERN /* a repeated pattern */, 163 MAX_INIT_ARRAY_TYPES 164 }; 165 166 167 /* 168 * init operation: callback 169 */ 170 struct init_callback_op 171 { 172 __le32 op_data; 173 #define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 174 #define INIT_CALLBACK_OP_OP_SHIFT 0 175 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 176 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 177 __le16 callback_id /* Callback ID */; 178 __le16 block_id /* Blocks ID */; 179 }; 180 181 182 /* 183 * init operation: delay 184 */ 185 struct init_delay_op 186 { 187 __le32 op_data; 188 #define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 189 #define INIT_DELAY_OP_OP_SHIFT 0 190 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 191 #define INIT_DELAY_OP_RESERVED_SHIFT 4 192 __le32 delay /* delay in us */; 193 }; 194 195 196 /* 197 * init operation: if_mode 198 */ 199 struct init_if_mode_op 200 { 201 __le32 op_data; 202 #define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 203 #define INIT_IF_MODE_OP_OP_SHIFT 0 204 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 205 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 206 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */ 207 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 208 __le16 reserved2; 209 __le16 modes_buf_offset /* offset (in bytes) in modes expression buffer */; 210 }; 211 212 213 /* 214 * init operation: if_phase 215 */ 216 struct init_if_phase_op 217 { 218 __le32 op_data; 219 #define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 220 #define INIT_IF_PHASE_OP_OP_SHIFT 0 221 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */ 222 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 223 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF 224 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 225 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */ 226 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 227 __le32 phase_data; 228 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */ 229 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 230 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 231 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 232 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */ 233 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 234 }; 235 236 237 /* 238 * init mode operators 239 */ 240 enum init_mode_ops 241 { 242 INIT_MODE_OP_NOT /* init mode not operator */, 243 INIT_MODE_OP_OR /* init mode or operator */, 244 INIT_MODE_OP_AND /* init mode and operator */, 245 MAX_INIT_MODE_OPS 246 }; 247 248 249 /* 250 * init operation: raw 251 */ 252 struct init_raw_op 253 { 254 __le32 op_data; 255 #define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 256 #define INIT_RAW_OP_OP_SHIFT 0 257 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */ 258 #define INIT_RAW_OP_PARAM1_SHIFT 4 259 __le32 param2 /* Init param 2 */; 260 }; 261 262 263 /* 264 * init array params 265 */ 266 struct init_op_array_params 267 { 268 __le16 size /* array size in dwords */; 269 __le16 offset /* array start offset in dwords */; 270 }; 271 272 273 /* 274 * Write init operation arguments 275 */ 276 union init_write_args 277 { 278 __le32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */; 279 __le32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */; 280 __le32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */; 281 struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */; 282 }; 283 284 285 /* 286 * init operation: write 287 */ 288 struct init_write_op 289 { 290 __le32 data; 291 #define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 292 #define INIT_WRITE_OP_OP_SHIFT 0 293 #define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */ 294 #define INIT_WRITE_OP_SOURCE_SHIFT 4 295 #define INIT_WRITE_OP_RESERVED_MASK 0x1 296 #define INIT_WRITE_OP_RESERVED_SHIFT 7 297 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 298 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 299 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 300 #define INIT_WRITE_OP_ADDRESS_SHIFT 9 301 union init_write_args args /* Write init operation arguments */; 302 }; 303 304 305 /* 306 * init operation: read 307 */ 308 struct init_read_op 309 { 310 __le32 op_data; 311 #define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 312 #define INIT_READ_OP_OP_SHIFT 0 313 #define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */ 314 #define INIT_READ_OP_POLL_TYPE_SHIFT 4 315 #define INIT_READ_OP_RESERVED_MASK 0x1 316 #define INIT_READ_OP_RESERVED_SHIFT 8 317 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 318 #define INIT_READ_OP_ADDRESS_SHIFT 9 319 __le32 expected_val /* expected polling value, used only when polling is done */; 320 }; 321 322 323 /* 324 * Init operations union 325 */ 326 union init_op 327 { 328 struct init_raw_op raw /* raw init operation */; 329 struct init_write_op write /* write init operation */; 330 struct init_read_op read /* read init operation */; 331 struct init_if_mode_op if_mode /* if_mode init operation */; 332 struct init_if_phase_op if_phase /* if_phase init operation */; 333 struct init_callback_op callback /* callback init operation */; 334 struct init_delay_op delay /* delay init operation */; 335 }; 336 337 338 /* 339 * Init command operation types 340 */ 341 enum init_op_types 342 { 343 INIT_OP_READ /* GRC read init command */, 344 INIT_OP_WRITE /* GRC write init command */, 345 INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */, 346 INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */, 347 INIT_OP_DELAY /* delay init command */, 348 INIT_OP_CALLBACK /* callback init command */, 349 MAX_INIT_OP_TYPES 350 }; 351 352 353 /* 354 * init polling types 355 */ 356 enum init_poll_types 357 { 358 INIT_POLL_NONE /* No polling */, 359 INIT_POLL_EQ /* init value is included in the init command */, 360 INIT_POLL_OR /* init value is all zeros */, 361 INIT_POLL_AND /* init value is an array of values */, 362 MAX_INIT_POLL_TYPES 363 }; 364 365 366 /* 367 * init source types 368 */ 369 enum init_source_types 370 { 371 INIT_SRC_INLINE /* init value is included in the init command */, 372 INIT_SRC_ZEROS /* init value is all zeros */, 373 INIT_SRC_ARRAY /* init value is an array of values */, 374 INIT_SRC_RUNTIME /* init value is provided during runtime */, 375 MAX_INIT_SOURCE_TYPES 376 }; 377 378 379 struct fw_ver_num 380 { 381 u8 major /* Firmware major version number */; 382 u8 minor /* Firmware minor version number */; 383 u8 rev /* Firmware revision version number */; 384 u8 eng /* Firmware engineering version number (for bootleg verisons) */; 385 }; 386 387 388 struct fw_ver_params 389 { 390 u8 image_id /* Firmware image ID */; 391 u8 storm_id /* Storm ID */; 392 u8 chip_ver /* Chip version number */; 393 u8 reserved; 394 }; 395 396 397 struct fw_ver_info 398 { 399 __le16 tools_ver /* Tools version number */; 400 __le16 reserved; 401 struct fw_ver_num num; 402 struct fw_ver_params params; 403 __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */; 404 }; 405 406 407 enum init_modes 408 { 409 MODE_BB_A0, 410 MODE_BB_B0, 411 MODE_K2, 412 MODE_ASIC, 413 MODE_EMUL_REDUCED, 414 MODE_EMUL_FULL, 415 MODE_FPGA, 416 MODE_CHIPSIM, 417 MODE_SF, 418 MODE_MF_SD, 419 MODE_MF_SI, 420 MODE_PORTS_PER_ENG_1, 421 MODE_PORTS_PER_ENG_2, 422 MODE_PORTS_PER_ENG_4, 423 MODE_100G, 424 MODE_EAGLE_ENG1_WORKAROUND, 425 MAX_INIT_MODES 426 }; 427 428 429 enum init_phases 430 { 431 PHASE_ENGINE, 432 PHASE_PORT, 433 PHASE_PF, 434 PHASE_VF, 435 PHASE_QM_PF, 436 MAX_INIT_PHASES 437 }; 438 439 440 #endif /* __ECORE_HSI_TOOLS__ */ 441