1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __ECORE_HSI_COMMON__ 37 #define __ECORE_HSI_COMMON__ 38 /********************************/ 39 /* Add include to common target */ 40 /********************************/ 41 #include "common_hsi.h" 42 43 44 /* 45 * opcodes for the event ring 46 */ 47 enum common_event_opcode 48 { 49 COMMON_EVENT_PF_START, 50 COMMON_EVENT_PF_STOP, 51 COMMON_EVENT_VF_START, 52 COMMON_EVENT_VF_STOP, 53 COMMON_EVENT_VF_PF_CHANNEL, 54 COMMON_EVENT_VF_FLR, 55 COMMON_EVENT_PF_UPDATE, 56 COMMON_EVENT_MALICIOUS_VF, 57 COMMON_EVENT_RL_UPDATE, 58 COMMON_EVENT_EMPTY, 59 MAX_COMMON_EVENT_OPCODE 60 }; 61 62 63 /* 64 * Common Ramrod Command IDs 65 */ 66 enum common_ramrod_cmd_id 67 { 68 COMMON_RAMROD_UNUSED, 69 COMMON_RAMROD_PF_START /* PF Function Start Ramrod */, 70 COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */, 71 COMMON_RAMROD_VF_START /* VF Function Start */, 72 COMMON_RAMROD_VF_STOP /* VF Function Stop Ramrod */, 73 COMMON_RAMROD_PF_UPDATE /* PF update Ramrod */, 74 COMMON_RAMROD_RL_UPDATE /* QCN/DCQCN RL update Ramrod */, 75 COMMON_RAMROD_EMPTY /* Empty Ramrod */, 76 MAX_COMMON_RAMROD_CMD_ID 77 }; 78 79 80 /* 81 * The core storm context for the Ystorm 82 */ 83 struct ystorm_core_conn_st_ctx 84 { 85 __le32 reserved[4]; 86 }; 87 88 /* 89 * The core storm context for the Pstorm 90 */ 91 struct pstorm_core_conn_st_ctx 92 { 93 __le32 reserved[4]; 94 }; 95 96 /* 97 * Core Slowpath Connection storm context of Xstorm 98 */ 99 struct xstorm_core_conn_st_ctx 100 { 101 __le32 spq_base_lo /* SPQ Ring Base Address low dword */; 102 __le32 spq_base_hi /* SPQ Ring Base Address high dword */; 103 struct regpair consolid_base_addr /* Consolidation Ring Base Address */; 104 __le16 spq_cons /* SPQ Ring Consumer */; 105 __le16 consolid_cons /* Consolidation Ring Consumer */; 106 __le32 reserved0[55] /* Pad to 15 cycles */; 107 }; 108 109 struct e4_xstorm_core_conn_ag_ctx 110 { 111 u8 reserved0 /* cdu_validation */; 112 u8 core_state /* state */; 113 u8 flags0; 114 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 115 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 116 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 117 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 118 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 119 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 120 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 121 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 122 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 123 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 124 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 125 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 126 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 127 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 128 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 129 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 130 u8 flags1; 131 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 132 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 133 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 134 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 135 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 136 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 137 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 138 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 139 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 140 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 141 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 142 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 143 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 144 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 145 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 146 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 147 u8 flags2; 148 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 149 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 150 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 151 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 152 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 153 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 154 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 155 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 156 u8 flags3; 157 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 158 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 159 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 160 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 161 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 162 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 163 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 164 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 165 u8 flags4; 166 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 167 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 168 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 169 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 170 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 171 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 172 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 173 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 174 u8 flags5; 175 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 176 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 177 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 178 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 179 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 180 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 181 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 182 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 183 u8 flags6; 184 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */ 185 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 186 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 187 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 188 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 189 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 190 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 191 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 192 u8 flags7; 193 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 194 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 195 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 196 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 197 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 198 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 199 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 200 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 201 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 202 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 203 u8 flags8; 204 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 205 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 206 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 207 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 208 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 209 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 210 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 211 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 212 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 213 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 214 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 215 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 216 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 217 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 218 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 219 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 220 u8 flags9; 221 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 222 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 223 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 224 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 225 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 226 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 227 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 228 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 229 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 230 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 231 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 232 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 233 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */ 234 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 235 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 236 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 237 u8 flags10; 238 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 239 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 240 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 241 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 242 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 243 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 244 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 245 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 246 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 247 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 248 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 249 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 250 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 251 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 252 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 253 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 254 u8 flags11; 255 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 256 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 257 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 258 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 259 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 260 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 261 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 262 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 263 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 264 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 265 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 266 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 267 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 268 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 269 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 270 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 271 u8 flags12; 272 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 273 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 274 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 275 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 276 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 277 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 278 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 279 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 280 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 281 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 282 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 283 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 284 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 285 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 286 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 287 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 288 u8 flags13; 289 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 290 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 291 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 292 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 293 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 294 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 295 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 296 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 297 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 298 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 299 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 300 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 301 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 302 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 303 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 304 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 305 u8 flags14; 306 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 307 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 308 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 309 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 310 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 311 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 312 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 313 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 314 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 315 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 316 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 317 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 318 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 319 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 320 u8 byte2 /* byte2 */; 321 __le16 physical_q0 /* physical_q0 */; 322 __le16 consolid_prod /* physical_q1 */; 323 __le16 reserved16 /* physical_q2 */; 324 __le16 tx_bd_cons /* word3 */; 325 __le16 tx_bd_or_spq_prod /* word4 */; 326 __le16 word5 /* word5 */; 327 __le16 conn_dpi /* conn_dpi */; 328 u8 byte3 /* byte3 */; 329 u8 byte4 /* byte4 */; 330 u8 byte5 /* byte5 */; 331 u8 byte6 /* byte6 */; 332 __le32 reg0 /* reg0 */; 333 __le32 reg1 /* reg1 */; 334 __le32 reg2 /* reg2 */; 335 __le32 reg3 /* reg3 */; 336 __le32 reg4 /* reg4 */; 337 __le32 reg5 /* cf_array0 */; 338 __le32 reg6 /* cf_array1 */; 339 __le16 word7 /* word7 */; 340 __le16 word8 /* word8 */; 341 __le16 word9 /* word9 */; 342 __le16 word10 /* word10 */; 343 __le32 reg7 /* reg7 */; 344 __le32 reg8 /* reg8 */; 345 __le32 reg9 /* reg9 */; 346 u8 byte7 /* byte7 */; 347 u8 byte8 /* byte8 */; 348 u8 byte9 /* byte9 */; 349 u8 byte10 /* byte10 */; 350 u8 byte11 /* byte11 */; 351 u8 byte12 /* byte12 */; 352 u8 byte13 /* byte13 */; 353 u8 byte14 /* byte14 */; 354 u8 byte15 /* byte15 */; 355 u8 e5_reserved /* e5_reserved */; 356 __le16 word11 /* word11 */; 357 __le32 reg10 /* reg10 */; 358 __le32 reg11 /* reg11 */; 359 __le32 reg12 /* reg12 */; 360 __le32 reg13 /* reg13 */; 361 __le32 reg14 /* reg14 */; 362 __le32 reg15 /* reg15 */; 363 __le32 reg16 /* reg16 */; 364 __le32 reg17 /* reg17 */; 365 __le32 reg18 /* reg18 */; 366 __le32 reg19 /* reg19 */; 367 __le16 word12 /* word12 */; 368 __le16 word13 /* word13 */; 369 __le16 word14 /* word14 */; 370 __le16 word15 /* word15 */; 371 }; 372 373 struct e4_tstorm_core_conn_ag_ctx 374 { 375 u8 byte0 /* cdu_validation */; 376 u8 byte1 /* state */; 377 u8 flags0; 378 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 379 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 380 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 381 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 382 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 383 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 384 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 385 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 386 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 387 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 388 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 389 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 390 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 391 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 392 u8 flags1; 393 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 394 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 395 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 396 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 397 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 398 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 399 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 400 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 401 u8 flags2; 402 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 403 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 404 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 405 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 406 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 407 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 408 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 409 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 410 u8 flags3; 411 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 412 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 413 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 414 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 415 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 416 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 417 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 418 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 419 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 420 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 421 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 422 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 423 u8 flags4; 424 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 425 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 426 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 427 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 428 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 429 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 430 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 431 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 432 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 433 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 434 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 435 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 436 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 437 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 438 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 439 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 440 u8 flags5; 441 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 442 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 443 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 444 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 445 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 446 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 447 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 448 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 449 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 450 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 451 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 452 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 453 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 454 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 455 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 456 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 457 __le32 reg0 /* reg0 */; 458 __le32 reg1 /* reg1 */; 459 __le32 reg2 /* reg2 */; 460 __le32 reg3 /* reg3 */; 461 __le32 reg4 /* reg4 */; 462 __le32 reg5 /* reg5 */; 463 __le32 reg6 /* reg6 */; 464 __le32 reg7 /* reg7 */; 465 __le32 reg8 /* reg8 */; 466 u8 byte2 /* byte2 */; 467 u8 byte3 /* byte3 */; 468 __le16 word0 /* word0 */; 469 u8 byte4 /* byte4 */; 470 u8 byte5 /* byte5 */; 471 __le16 word1 /* word1 */; 472 __le16 word2 /* conn_dpi */; 473 __le16 word3 /* word3 */; 474 __le32 reg9 /* reg9 */; 475 __le32 reg10 /* reg10 */; 476 }; 477 478 struct e4_ustorm_core_conn_ag_ctx 479 { 480 u8 reserved /* cdu_validation */; 481 u8 byte1 /* state */; 482 u8 flags0; 483 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 484 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 485 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 486 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 487 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 488 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 489 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 490 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 491 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 492 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 493 u8 flags1; 494 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 495 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 496 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 497 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 498 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 499 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 500 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 501 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 502 u8 flags2; 503 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 504 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 505 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 506 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 507 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 508 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 509 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 510 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 511 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 512 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 513 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 514 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 515 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 516 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 517 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 518 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 519 u8 flags3; 520 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 521 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 522 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 523 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 524 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 525 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 526 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 527 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 528 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 529 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 530 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 531 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 532 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 533 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 534 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 535 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 536 u8 byte2 /* byte2 */; 537 u8 byte3 /* byte3 */; 538 __le16 word0 /* conn_dpi */; 539 __le16 word1 /* word1 */; 540 __le32 rx_producers /* reg0 */; 541 __le32 reg1 /* reg1 */; 542 __le32 reg2 /* reg2 */; 543 __le32 reg3 /* reg3 */; 544 __le16 word2 /* word2 */; 545 __le16 word3 /* word3 */; 546 }; 547 548 /* 549 * The core storm context for the Mstorm 550 */ 551 struct mstorm_core_conn_st_ctx 552 { 553 __le32 reserved[24]; 554 }; 555 556 /* 557 * The core storm context for the Ustorm 558 */ 559 struct ustorm_core_conn_st_ctx 560 { 561 __le32 reserved[4]; 562 }; 563 564 /* 565 * core connection context 566 */ 567 struct core_conn_context 568 { 569 struct ystorm_core_conn_st_ctx ystorm_st_context /* ystorm storm context */; 570 struct regpair ystorm_st_padding[2] /* padding */; 571 struct pstorm_core_conn_st_ctx pstorm_st_context /* pstorm storm context */; 572 struct regpair pstorm_st_padding[2] /* padding */; 573 struct xstorm_core_conn_st_ctx xstorm_st_context /* xstorm storm context */; 574 struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 575 struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 576 struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 577 struct mstorm_core_conn_st_ctx mstorm_st_context /* mstorm storm context */; 578 struct ustorm_core_conn_st_ctx ustorm_st_context /* ustorm storm context */; 579 struct regpair ustorm_st_padding[2] /* padding */; 580 }; 581 582 583 /* 584 * How ll2 should deal with packet upon errors 585 */ 586 enum core_error_handle 587 { 588 LL2_DROP_PACKET /* If error occurs drop packet */, 589 LL2_DO_NOTHING /* If error occurs do nothing */, 590 LL2_ASSERT /* If error occurs assert */, 591 MAX_CORE_ERROR_HANDLE 592 }; 593 594 595 /* 596 * opcodes for the event ring 597 */ 598 enum core_event_opcode 599 { 600 CORE_EVENT_TX_QUEUE_START, 601 CORE_EVENT_TX_QUEUE_STOP, 602 CORE_EVENT_RX_QUEUE_START, 603 CORE_EVENT_RX_QUEUE_STOP, 604 CORE_EVENT_RX_QUEUE_FLUSH, 605 MAX_CORE_EVENT_OPCODE 606 }; 607 608 609 /* 610 * The L4 pseudo checksum mode for Core 611 */ 612 enum core_l4_pseudo_checksum_mode 613 { 614 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH /* Pseudo Checksum on packet is calculated with the correct packet length. */, 615 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH /* Pseudo Checksum on packet is calculated with zero length. */, 616 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE 617 }; 618 619 620 /* 621 * Light-L2 RX Producers in Tstorm RAM 622 */ 623 struct core_ll2_port_stats 624 { 625 struct regpair gsi_invalid_hdr; 626 struct regpair gsi_invalid_pkt_length; 627 struct regpair gsi_unsupported_pkt_typ; 628 struct regpair gsi_crcchksm_error; 629 }; 630 631 632 /* 633 * Ethernet TX Per Queue Stats 634 */ 635 struct core_ll2_pstorm_per_queue_stat 636 { 637 struct regpair sent_ucast_bytes /* number of total bytes sent without errors */; 638 struct regpair sent_mcast_bytes /* number of total bytes sent without errors */; 639 struct regpair sent_bcast_bytes /* number of total bytes sent without errors */; 640 struct regpair sent_ucast_pkts /* number of total packets sent without errors */; 641 struct regpair sent_mcast_pkts /* number of total packets sent without errors */; 642 struct regpair sent_bcast_pkts /* number of total packets sent without errors */; 643 }; 644 645 646 /* 647 * Light-L2 RX Producers in Tstorm RAM 648 */ 649 struct core_ll2_rx_prod 650 { 651 __le16 bd_prod /* BD Producer */; 652 __le16 cqe_prod /* CQE Producer */; 653 __le32 reserved; 654 }; 655 656 657 struct core_ll2_tstorm_per_queue_stat 658 { 659 struct regpair packet_too_big_discard /* Number of packets discarded because they are bigger than MTU */; 660 struct regpair no_buff_discard /* Number of packets discarded due to lack of host buffers */; 661 }; 662 663 664 struct core_ll2_ustorm_per_queue_stat 665 { 666 struct regpair rcv_ucast_bytes; 667 struct regpair rcv_mcast_bytes; 668 struct regpair rcv_bcast_bytes; 669 struct regpair rcv_ucast_pkts; 670 struct regpair rcv_mcast_pkts; 671 struct regpair rcv_bcast_pkts; 672 }; 673 674 675 /* 676 * Core Ramrod Command IDs (light L2) 677 */ 678 enum core_ramrod_cmd_id 679 { 680 CORE_RAMROD_UNUSED, 681 CORE_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, 682 CORE_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, 683 CORE_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, 684 CORE_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, 685 CORE_RAMROD_RX_QUEUE_FLUSH /* RX Flush queue Ramrod */, 686 MAX_CORE_RAMROD_CMD_ID 687 }; 688 689 690 /* 691 * Core RX CQE Type for Light L2 692 */ 693 enum core_roce_flavor_type 694 { 695 CORE_ROCE, 696 CORE_RROCE, 697 MAX_CORE_ROCE_FLAVOR_TYPE 698 }; 699 700 701 /* 702 * Specifies how ll2 should deal with packets errors: packet_too_big and no_buff 703 */ 704 struct core_rx_action_on_error 705 { 706 u8 error_type; 707 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 /* ll2 how to handle error packet_too_big (use enum core_error_handle) */ 708 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 709 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 /* ll2 how to handle error with no_buff (use enum core_error_handle) */ 710 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 711 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF 712 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4 713 }; 714 715 716 /* 717 * Core RX BD for Light L2 718 */ 719 struct core_rx_bd 720 { 721 struct regpair addr; 722 __le16 reserved[4]; 723 }; 724 725 726 /* 727 * Core RX CM offload BD for Light L2 728 */ 729 struct core_rx_bd_with_buff_len 730 { 731 struct regpair addr; 732 __le16 buff_length; 733 __le16 reserved[3]; 734 }; 735 736 /* 737 * Core RX CM offload BD for Light L2 738 */ 739 union core_rx_bd_union 740 { 741 struct core_rx_bd rx_bd /* Core Rx Bd static buffer size */; 742 struct core_rx_bd_with_buff_len rx_bd_with_len /* Core Rx Bd with dynamic buffer length */; 743 }; 744 745 746 747 /* 748 * Opaque Data for Light L2 RX CQE . 749 */ 750 struct core_rx_cqe_opaque_data 751 { 752 __le32 data[2] /* Opaque CQE Data */; 753 }; 754 755 756 /* 757 * Core RX CQE Type for Light L2 758 */ 759 enum core_rx_cqe_type 760 { 761 CORE_RX_CQE_ILLIGAL_TYPE /* Bad RX Cqe type */, 762 CORE_RX_CQE_TYPE_REGULAR /* Regular Core RX CQE */, 763 CORE_RX_CQE_TYPE_GSI_OFFLOAD /* Fp Gsi offload RX CQE */, 764 CORE_RX_CQE_TYPE_SLOW_PATH /* Slow path Core RX CQE */, 765 MAX_CORE_RX_CQE_TYPE 766 }; 767 768 769 /* 770 * Core RX CQE for Light L2 . 771 */ 772 struct core_rx_fast_path_cqe 773 { 774 u8 type /* CQE type */; 775 u8 placement_offset /* Offset (in bytes) of the packet from start of the buffer */; 776 struct parsing_and_err_flags parse_flags /* Parsing and error flags from the parser */; 777 __le16 packet_length /* Total packet length (from the parser) */; 778 __le16 vlan /* 802.1q VLAN tag */; 779 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */; 780 struct parsing_err_flags err_flags /* bit- map: each bit represents a specific error. errors indications are provided by the cracker. see spec for detailed description */; 781 __le16 reserved0; 782 __le32 reserved1[3]; 783 }; 784 785 /* 786 * Core Rx CM offload CQE . 787 */ 788 struct core_rx_gsi_offload_cqe 789 { 790 u8 type /* CQE type */; 791 u8 data_length_error /* set if gsi data is bigger than buff */; 792 struct parsing_and_err_flags parse_flags /* Parsing and error flags from the parser */; 793 __le16 data_length /* Total packet length (from the parser) */; 794 __le16 vlan /* 802.1q VLAN tag */; 795 __le32 src_mac_addrhi /* hi 4 bytes source mac address */; 796 __le16 src_mac_addrlo /* lo 2 bytes of source mac address */; 797 __le16 qp_id /* These are the lower 16 bit of QP id in RoCE BTH header */; 798 __le32 gid_dst[4] /* Gid destination address */; 799 }; 800 801 /* 802 * Core RX CQE for Light L2 . 803 */ 804 struct core_rx_slow_path_cqe 805 { 806 u8 type /* CQE type */; 807 u8 ramrod_cmd_id; 808 __le16 echo; 809 struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */; 810 __le32 reserved1[5]; 811 }; 812 813 /* 814 * Core RX CM offload BD for Light L2 815 */ 816 union core_rx_cqe_union 817 { 818 struct core_rx_fast_path_cqe rx_cqe_fp /* Fast path CQE */; 819 struct core_rx_gsi_offload_cqe rx_cqe_gsi /* GSI offload CQE */; 820 struct core_rx_slow_path_cqe rx_cqe_sp /* Slow path CQE */; 821 }; 822 823 824 825 826 827 /* 828 * Ramrod data for rx queue start ramrod 829 */ 830 struct core_rx_start_ramrod_data 831 { 832 struct regpair bd_base /* bd address of the first bd page */; 833 struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */; 834 __le16 mtu /* Maximum transmission unit */; 835 __le16 sb_id /* Status block ID */; 836 u8 sb_index /* index of the protocol index */; 837 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 838 u8 complete_event_flg /* post completion to the event ring if set */; 839 u8 drop_ttl0_flg /* drop packet with ttl0 if set */; 840 __le16 num_of_pbl_pages /* Num of pages in CQE PBL */; 841 u8 inner_vlan_removal_en /* if set, 802.1q tags will be removed and copied to CQE */; 842 u8 queue_id /* Light L2 RX Queue ID */; 843 u8 main_func_queue /* Is this the main queue for the PF */; 844 u8 mf_si_bcast_accept_all /* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if main_func_queue is set. */; 845 u8 mf_si_mcast_accept_all /* Duplicate multicast packets to LL2 main queue in mf_si mode. Valid if main_func_queue is set. */; 846 struct core_rx_action_on_error action_on_error /* Specifies how ll2 should deal with packets errors: packet_too_big and no_buff */; 847 u8 gsi_offload_flag /* set when in GSI offload mode on ROCE connection */; 848 u8 reserved[7]; 849 }; 850 851 852 /* 853 * Ramrod data for rx queue stop ramrod 854 */ 855 struct core_rx_stop_ramrod_data 856 { 857 u8 complete_cqe_flg /* post completion to the CQE ring if set */; 858 u8 complete_event_flg /* post completion to the event ring if set */; 859 u8 queue_id /* Light L2 RX Queue ID */; 860 u8 reserved1; 861 __le16 reserved2[2]; 862 }; 863 864 865 /* 866 * Flags for Core TX BD 867 */ 868 struct core_tx_bd_data 869 { 870 __le16 as_bitfield; 871 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1 /* Do not allow additional VLAN manipulations on this packet (DCB) */ 872 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0 873 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1 /* Insert VLAN into packet */ 874 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1 875 #define CORE_TX_BD_DATA_START_BD_MASK 0x1 /* This is the first BD of the packet (for debug) */ 876 #define CORE_TX_BD_DATA_START_BD_SHIFT 2 877 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1 /* Calculate the IP checksum for the packet */ 878 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3 879 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1 /* Calculate the L4 checksum for the packet */ 880 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4 881 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1 /* Packet is IPv6 with extensions */ 882 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5 883 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1 /* If IPv6+ext, and if l4_csum is 1, than this field indicates L4 protocol: 0-TCP, 1-UDP */ 884 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6 885 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1 /* The pseudo checksum mode to place in the L4 checksum field. Required only when IPv6+ext and l4_csum is set. (use enum core_l4_pseudo_checksum_mode) */ 886 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7 887 #define CORE_TX_BD_DATA_NBDS_MASK 0xF /* Number of BDs that make up one packet - width wide enough to present CORE_LL2_TX_MAX_BDS_PER_PACKET */ 888 #define CORE_TX_BD_DATA_NBDS_SHIFT 8 889 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1 /* Use roce_flavor enum - Differentiate between Roce flavors is valid when connType is ROCE (use enum core_roce_flavor_type) */ 890 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12 891 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1 /* Calculate ip length */ 892 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13 893 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x3 894 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 14 895 }; 896 897 /* 898 * Core TX BD for Light L2 899 */ 900 struct core_tx_bd 901 { 902 struct regpair addr /* Buffer Address */; 903 __le16 nbytes /* Number of Bytes in Buffer */; 904 __le16 nw_vlan_or_lb_echo /* Network packets: VLAN to insert to packet (if insertion flag set) LoopBack packets: echo data to pass to Rx */; 905 struct core_tx_bd_data bd_data /* BD Flags */; 906 __le16 bitfield1; 907 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF /* L4 Header Offset from start of packet (in Words). This is needed if both l4_csum and ipv6_ext are set */ 908 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 909 #define CORE_TX_BD_TX_DST_MASK 0x3 /* Packet destination - Network, Loopback or Drop (use enum core_tx_dest) */ 910 #define CORE_TX_BD_TX_DST_SHIFT 14 911 }; 912 913 914 915 /* 916 * Light L2 TX Destination 917 */ 918 enum core_tx_dest 919 { 920 CORE_TX_DEST_NW /* TX Destination to the Network */, 921 CORE_TX_DEST_LB /* TX Destination to the Loopback */, 922 CORE_TX_DEST_RESERVED, 923 CORE_TX_DEST_DROP /* TX Drop */, 924 MAX_CORE_TX_DEST 925 }; 926 927 928 /* 929 * Ramrod data for tx queue start ramrod 930 */ 931 struct core_tx_start_ramrod_data 932 { 933 struct regpair pbl_base_addr /* Address of the pbl page */; 934 __le16 mtu /* Maximum transmission unit */; 935 __le16 sb_id /* Status block ID */; 936 u8 sb_index /* Status block protocol index */; 937 u8 stats_en /* Statistics Enable */; 938 u8 stats_id /* Statistics Counter ID */; 939 u8 conn_type /* connection type that loaded ll2 */; 940 __le16 pbl_size /* Number of BD pages pointed by PBL */; 941 __le16 qm_pq_id /* QM PQ ID */; 942 u8 gsi_offload_flag /* set when in GSI offload mode on ROCE connection */; 943 u8 resrved[3]; 944 }; 945 946 947 /* 948 * Ramrod data for tx queue stop ramrod 949 */ 950 struct core_tx_stop_ramrod_data 951 { 952 __le32 reserved0[2]; 953 }; 954 955 956 /* 957 * Enum flag for what type of dcb data to update 958 */ 959 enum dcb_dscp_update_mode 960 { 961 DONT_UPDATE_DCB_DSCP /* use when no change should be done to dcb data */, 962 UPDATE_DCB /* use to update only l2 (vlan) priority */, 963 UPDATE_DSCP /* use to update only l3 dscp */, 964 UPDATE_DCB_DSCP /* update vlan pri and dscp */, 965 MAX_DCB_DSCP_UPDATE_MODE 966 }; 967 968 969 struct eth_mstorm_per_pf_stat 970 { 971 struct regpair gre_discard_pkts /* Dropped GRE RX packets */; 972 struct regpair vxlan_discard_pkts /* Dropped VXLAN RX packets */; 973 struct regpair geneve_discard_pkts /* Dropped GENEVE RX packets */; 974 struct regpair lb_discard_pkts /* Dropped Tx switched packets */; 975 }; 976 977 978 struct eth_mstorm_per_queue_stat 979 { 980 struct regpair ttl0_discard /* Number of packets discarded because TTL=0 (in IPv4) or hopLimit=0 (in IPv6) */; 981 struct regpair packet_too_big_discard /* Number of packets discarded because they are bigger than MTU */; 982 struct regpair no_buff_discard /* Number of packets discarded due to lack of host buffers (BDs/SGEs/CQEs) */; 983 struct regpair not_active_discard /* Number of packets discarded because of no active Rx connection */; 984 struct regpair tpa_coalesced_pkts /* number of coalesced packets in all TPA aggregations */; 985 struct regpair tpa_coalesced_events /* total number of TPA aggregations */; 986 struct regpair tpa_aborts_num /* number of aggregations, which abnormally ended */; 987 struct regpair tpa_coalesced_bytes /* total TCP payload length in all TPA aggregations */; 988 }; 989 990 991 /* 992 * Ethernet TX Per PF 993 */ 994 struct eth_pstorm_per_pf_stat 995 { 996 struct regpair sent_lb_ucast_bytes /* number of total ucast bytes sent on loopback port without errors */; 997 struct regpair sent_lb_mcast_bytes /* number of total mcast bytes sent on loopback port without errors */; 998 struct regpair sent_lb_bcast_bytes /* number of total bcast bytes sent on loopback port without errors */; 999 struct regpair sent_lb_ucast_pkts /* number of total ucast packets sent on loopback port without errors */; 1000 struct regpair sent_lb_mcast_pkts /* number of total mcast packets sent on loopback port without errors */; 1001 struct regpair sent_lb_bcast_pkts /* number of total bcast packets sent on loopback port without errors */; 1002 struct regpair sent_gre_bytes /* Sent GRE bytes */; 1003 struct regpair sent_vxlan_bytes /* Sent VXLAN bytes */; 1004 struct regpair sent_geneve_bytes /* Sent GENEVE bytes */; 1005 struct regpair sent_gre_pkts /* Sent GRE packets */; 1006 struct regpair sent_vxlan_pkts /* Sent VXLAN packets */; 1007 struct regpair sent_geneve_pkts /* Sent GENEVE packets */; 1008 struct regpair gre_drop_pkts /* Dropped GRE TX packets */; 1009 struct regpair vxlan_drop_pkts /* Dropped VXLAN TX packets */; 1010 struct regpair geneve_drop_pkts /* Dropped GENEVE TX packets */; 1011 }; 1012 1013 1014 /* 1015 * Ethernet TX Per Queue Stats 1016 */ 1017 struct eth_pstorm_per_queue_stat 1018 { 1019 struct regpair sent_ucast_bytes /* number of total bytes sent without errors */; 1020 struct regpair sent_mcast_bytes /* number of total bytes sent without errors */; 1021 struct regpair sent_bcast_bytes /* number of total bytes sent without errors */; 1022 struct regpair sent_ucast_pkts /* number of total packets sent without errors */; 1023 struct regpair sent_mcast_pkts /* number of total packets sent without errors */; 1024 struct regpair sent_bcast_pkts /* number of total packets sent without errors */; 1025 struct regpair error_drop_pkts /* number of total packets dropped due to errors */; 1026 }; 1027 1028 1029 /* 1030 * ETH Rx producers data 1031 */ 1032 struct eth_rx_rate_limit 1033 { 1034 __le16 mult /* Rate Limit Multiplier - (Storm Clock (MHz) * 8 / Desired Bandwidth (MB/s)) */; 1035 __le16 cnst /* Constant term to add (or subtract from number of cycles) */; 1036 u8 add_sub_cnst /* Add (1) or subtract (0) constant term */; 1037 u8 reserved0; 1038 __le16 reserved1; 1039 }; 1040 1041 1042 struct eth_ustorm_per_pf_stat 1043 { 1044 struct regpair rcv_lb_ucast_bytes /* number of total ucast bytes received on loopback port without errors */; 1045 struct regpair rcv_lb_mcast_bytes /* number of total mcast bytes received on loopback port without errors */; 1046 struct regpair rcv_lb_bcast_bytes /* number of total bcast bytes received on loopback port without errors */; 1047 struct regpair rcv_lb_ucast_pkts /* number of total ucast packets received on loopback port without errors */; 1048 struct regpair rcv_lb_mcast_pkts /* number of total mcast packets received on loopback port without errors */; 1049 struct regpair rcv_lb_bcast_pkts /* number of total bcast packets received on loopback port without errors */; 1050 struct regpair rcv_gre_bytes /* Received GRE bytes */; 1051 struct regpair rcv_vxlan_bytes /* Received VXLAN bytes */; 1052 struct regpair rcv_geneve_bytes /* Received GENEVE bytes */; 1053 struct regpair rcv_gre_pkts /* Received GRE packets */; 1054 struct regpair rcv_vxlan_pkts /* Received VXLAN packets */; 1055 struct regpair rcv_geneve_pkts /* Received GENEVE packets */; 1056 }; 1057 1058 1059 struct eth_ustorm_per_queue_stat 1060 { 1061 struct regpair rcv_ucast_bytes; 1062 struct regpair rcv_mcast_bytes; 1063 struct regpair rcv_bcast_bytes; 1064 struct regpair rcv_ucast_pkts; 1065 struct regpair rcv_mcast_pkts; 1066 struct regpair rcv_bcast_pkts; 1067 }; 1068 1069 1070 /* 1071 * Event Ring Next Page Address 1072 */ 1073 struct event_ring_next_addr 1074 { 1075 struct regpair addr /* Next Page Address */; 1076 __le32 reserved[2] /* Reserved */; 1077 }; 1078 1079 /* 1080 * Event Ring Element 1081 */ 1082 union event_ring_element 1083 { 1084 struct event_ring_entry entry /* Event Ring Entry */; 1085 struct event_ring_next_addr next_addr /* Event Ring Next Page Address */; 1086 }; 1087 1088 1089 1090 /* 1091 * Ports mode 1092 */ 1093 enum fw_flow_ctrl_mode 1094 { 1095 flow_ctrl_pause, 1096 flow_ctrl_pfc, 1097 MAX_FW_FLOW_CTRL_MODE 1098 }; 1099 1100 1101 /* 1102 * Major and Minor hsi Versions 1103 */ 1104 struct hsi_fp_ver_struct 1105 { 1106 u8 minor_ver_arr[2] /* Minor Version of hsi loading pf */; 1107 u8 major_ver_arr[2] /* Major Version of driver loading pf */; 1108 }; 1109 1110 1111 /* 1112 * Integration Phase 1113 */ 1114 enum integ_phase 1115 { 1116 INTEG_PHASE_BB_A0_LATEST=3 /* BB A0 latest integration phase */, 1117 INTEG_PHASE_BB_B0_NO_MCP=10 /* BB B0 without MCP */, 1118 INTEG_PHASE_BB_B0_WITH_MCP=11 /* BB B0 with MCP */, 1119 MAX_INTEG_PHASE 1120 }; 1121 1122 1123 /* 1124 * Ports mode 1125 */ 1126 enum iwarp_ll2_tx_queues 1127 { 1128 IWARP_LL2_IN_ORDER_TX_QUEUE=1 /* LL2 queue for OOO packets sent in-order by the driver */, 1129 IWARP_LL2_ALIGNED_TX_QUEUE /* LL2 queue for unaligned packets sent aligned by the driver */, 1130 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE /* LL2 queue for unaligned packets sent aligned and was right-trimmed by the driver */, 1131 IWARP_LL2_ERROR /* Error indication */, 1132 MAX_IWARP_LL2_TX_QUEUES 1133 }; 1134 1135 1136 /* 1137 * Malicious VF error ID 1138 */ 1139 enum malicious_vf_error_id 1140 { 1141 MALICIOUS_VF_NO_ERROR /* Zero placeholder value */, 1142 VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */, 1143 VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */, 1144 VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */, 1145 ETH_PACKET_TOO_SMALL /* TX packet is shorter then reported on BDs or from minimal size */, 1146 ETH_ILLEGAL_VLAN_MODE /* Tx packet with marked as insert VLAN when its illegal */, 1147 ETH_MTU_VIOLATION /* TX packet is greater then MTU */, 1148 ETH_ILLEGAL_INBAND_TAGS /* TX packet has illegal inband tags marked */, 1149 ETH_VLAN_INSERT_AND_INBAND_VLAN /* Vlan cant be added to inband tag */, 1150 ETH_ILLEGAL_NBDS /* indicated number of BDs for the packet is illegal */, 1151 ETH_FIRST_BD_WO_SOP /* 1st BD must have start_bd flag set */, 1152 ETH_INSUFFICIENT_BDS /* There are not enough BDs for transmission of even one packet */, 1153 ETH_ILLEGAL_LSO_HDR_NBDS /* Header NBDs value is illegal */, 1154 ETH_ILLEGAL_LSO_MSS /* LSO MSS value is more than allowed */, 1155 ETH_ZERO_SIZE_BD /* empty BD (which not contains control flags) is illegal */, 1156 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header size is above the limit */, 1157 ETH_INSUFFICIENT_PAYLOAD /* In LSO its expected that on the local BD ring there will be at least MSS bytes of data */, 1158 ETH_EDPM_OUT_OF_SYNC /* Valid BDs on local ring after EDPM L2 sync */, 1159 ETH_TUNN_IPV6_EXT_NBD_ERR /* Tunneled packet with IPv6+Ext without a proper number of BDs */, 1160 ETH_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */, 1161 ETH_ANTI_SPOOFING_ERR /* Anti-Spoofing verification failure */, 1162 MAX_MALICIOUS_VF_ERROR_ID 1163 }; 1164 1165 1166 1167 /* 1168 * Mstorm non-triggering VF zone 1169 */ 1170 struct mstorm_non_trigger_vf_zone 1171 { 1172 struct eth_mstorm_per_queue_stat eth_queue_stat /* VF statistic bucket */; 1173 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD] /* VF RX queues producers */; 1174 }; 1175 1176 1177 /* 1178 * Mstorm VF zone 1179 */ 1180 struct mstorm_vf_zone 1181 { 1182 struct mstorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 1183 }; 1184 1185 1186 /* 1187 * personality per PF 1188 */ 1189 enum personality_type 1190 { 1191 BAD_PERSONALITY_TYP, 1192 PERSONALITY_ISCSI /* iSCSI and LL2 */, 1193 PERSONALITY_FCOE /* Fcoe and LL2 */, 1194 PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp, Eth and LL2 */, 1195 PERSONALITY_RDMA /* Roce and LL2 */, 1196 PERSONALITY_CORE /* CORE(LL2) */, 1197 PERSONALITY_ETH /* Ethernet */, 1198 PERSONALITY_TOE /* Toe and LL2 */, 1199 MAX_PERSONALITY_TYPE 1200 }; 1201 1202 1203 /* 1204 * tunnel configuration 1205 */ 1206 struct pf_start_tunnel_config 1207 { 1208 u8 set_vxlan_udp_port_flg /* Set VXLAN tunnel UDP destination port to vxlan_udp_port. If not set - FW will use a default port */; 1209 u8 set_geneve_udp_port_flg /* Set GENEVE tunnel UDP destination port to geneve_udp_port. If not set - FW will use a default port */; 1210 u8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. */; 1211 u8 tunnel_clss_l2geneve /* Rx classification scheme for l2 GENEVE tunnel. */; 1212 u8 tunnel_clss_ipgeneve /* Rx classification scheme for ip GENEVE tunnel. */; 1213 u8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. */; 1214 u8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. */; 1215 u8 reserved; 1216 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */; 1217 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */; 1218 }; 1219 1220 /* 1221 * Ramrod data for PF start ramrod 1222 */ 1223 struct pf_start_ramrod_data 1224 { 1225 struct regpair event_ring_pbl_addr /* Address of event ring PBL */; 1226 struct regpair consolid_q_pbl_addr /* PBL address of consolidation queue */; 1227 struct pf_start_tunnel_config tunnel_config /* tunnel configuration. */; 1228 __le32 reserved; 1229 __le16 event_ring_sb_id /* Status block ID */; 1230 u8 base_vf_id /* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */; 1231 u8 num_vfs /* Amount of vfs owned by PF */; 1232 u8 event_ring_num_pages /* Number of PBL pages in event ring */; 1233 u8 event_ring_sb_index /* Status block index */; 1234 u8 path_id /* HW path ID (engine ID) */; 1235 u8 warning_as_error /* In FW asserts, treat warning as error */; 1236 u8 dont_log_ramrods /* If not set - throw a warning for each ramrod (for debug) */; 1237 u8 personality /* define what type of personality is new PF */; 1238 __le16 log_type_mask /* Log type mask. Each bit set enables a corresponding event type logging. Event types are defined as ASSERT_LOG_TYPE_xxx */; 1239 u8 mf_mode /* Multi function mode */; 1240 u8 integ_phase /* Integration phase */; 1241 u8 allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode */; 1242 u8 inner_to_outer_pri_map[8] /* Map from inner to outer priority. Set pri_map_valid when init map */; 1243 u8 pri_map_valid /* If inner_to_outer_pri_map is initialize then set pri_map_valid */; 1244 __le32 outer_tag /* In case mf_mode is MF_OVLAN, this field specifies the outer vlan (lower 16 bits) and ethType to use (higher 16 bits) */; 1245 struct hsi_fp_ver_struct hsi_fp_ver /* FP HSI version to be used by FW */; 1246 }; 1247 1248 1249 1250 /* 1251 * Data for port update ramrod 1252 */ 1253 struct protocol_dcb_data 1254 { 1255 u8 dcb_enable_flag /* dcbEnable flag value */; 1256 u8 dscp_enable_flag /* If set use dscp value */; 1257 u8 dcb_priority /* dcbPri flag value */; 1258 u8 dcb_tc /* dcb TC value */; 1259 u8 dscp_val /* dscp value to write if dscp_enable_flag is set */; 1260 u8 reserved0; 1261 }; 1262 1263 /* 1264 * Update tunnel configuration 1265 */ 1266 struct pf_update_tunnel_config 1267 { 1268 u8 update_rx_pf_clss /* Update RX per PF tunnel classification scheme. */; 1269 u8 update_rx_def_ucast_clss /* Update per PORT default tunnel RX classification scheme for traffic with unknown unicast outer MAC in NPAR mode. */; 1270 u8 update_rx_def_non_ucast_clss /* Update per PORT default tunnel RX classification scheme for traffic with non unicast outer MAC in NPAR mode. */; 1271 u8 set_vxlan_udp_port_flg /* Update VXLAN tunnel UDP destination port. */; 1272 u8 set_geneve_udp_port_flg /* Update GENEVE tunnel UDP destination port. */; 1273 u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. */; 1274 u8 tunnel_clss_l2geneve /* Classification scheme for l2 GENEVE tunnel. */; 1275 u8 tunnel_clss_ipgeneve /* Classification scheme for ip GENEVE tunnel. */; 1276 u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. */; 1277 u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. */; 1278 __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */; 1279 __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */; 1280 __le16 reserved; 1281 }; 1282 1283 /* 1284 * Data for port update ramrod 1285 */ 1286 struct pf_update_ramrod_data 1287 { 1288 u8 pf_id; 1289 u8 update_eth_dcb_data_mode /* Update Eth DCB data indication */; 1290 u8 update_fcoe_dcb_data_mode /* Update FCOE DCB data indication */; 1291 u8 update_iscsi_dcb_data_mode /* Update iSCSI DCB data indication */; 1292 u8 update_roce_dcb_data_mode /* Update ROCE DCB data indication */; 1293 u8 update_rroce_dcb_data_mode /* Update RROCE (RoceV2) DCB data indication */; 1294 u8 update_iwarp_dcb_data_mode /* Update IWARP DCB data indication */; 1295 u8 update_mf_vlan_flag /* Update MF outer vlan Id */; 1296 struct protocol_dcb_data eth_dcb_data /* core eth related fields */; 1297 struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */; 1298 struct protocol_dcb_data iscsi_dcb_data /* core iscsi related fields */; 1299 struct protocol_dcb_data roce_dcb_data /* core roce related fields */; 1300 struct protocol_dcb_data rroce_dcb_data /* core roce related fields */; 1301 struct protocol_dcb_data iwarp_dcb_data /* core iwarp related fields */; 1302 __le16 mf_vlan /* new outer vlan id value */; 1303 __le16 reserved; 1304 struct pf_update_tunnel_config tunnel_config /* tunnel configuration. */; 1305 }; 1306 1307 1308 1309 /* 1310 * Ports mode 1311 */ 1312 enum ports_mode 1313 { 1314 ENGX2_PORTX1 /* 2 engines x 1 port */, 1315 ENGX2_PORTX2 /* 2 engines x 2 ports */, 1316 ENGX1_PORTX1 /* 1 engine x 1 port */, 1317 ENGX1_PORTX2 /* 1 engine x 2 ports */, 1318 ENGX1_PORTX4 /* 1 engine x 4 ports */, 1319 MAX_PORTS_MODE 1320 }; 1321 1322 1323 1324 /* 1325 * use to index in hsi_fp_[major|minor]_ver_arr per protocol 1326 */ 1327 enum protocol_version_array_key 1328 { 1329 ETH_VER_KEY=0, 1330 ROCE_VER_KEY, 1331 MAX_PROTOCOL_VERSION_ARRAY_KEY 1332 }; 1333 1334 1335 1336 /* 1337 * RDMA TX Stats 1338 */ 1339 struct rdma_sent_stats 1340 { 1341 struct regpair sent_bytes /* number of total RDMA bytes sent */; 1342 struct regpair sent_pkts /* number of total RDMA packets sent */; 1343 }; 1344 1345 /* 1346 * Pstorm non-triggering VF zone 1347 */ 1348 struct pstorm_non_trigger_vf_zone 1349 { 1350 struct eth_pstorm_per_queue_stat eth_queue_stat /* VF statistic bucket */; 1351 struct rdma_sent_stats rdma_stats /* RoCE sent statistics */; 1352 }; 1353 1354 1355 /* 1356 * Pstorm VF zone 1357 */ 1358 struct pstorm_vf_zone 1359 { 1360 struct pstorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 1361 struct regpair reserved[7] /* vf_zone size mus be power of 2 */; 1362 }; 1363 1364 1365 /* 1366 * Ramrod Header of SPQE 1367 */ 1368 struct ramrod_header 1369 { 1370 __le32 cid /* Slowpath Connection CID */; 1371 u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */; 1372 u8 protocol_id /* Ramrod Protocol ID */; 1373 __le16 echo /* Ramrod echo */; 1374 }; 1375 1376 1377 /* 1378 * RDMA RX Stats 1379 */ 1380 struct rdma_rcv_stats 1381 { 1382 struct regpair rcv_bytes /* number of total RDMA bytes received */; 1383 struct regpair rcv_pkts /* number of total RDMA packets received */; 1384 }; 1385 1386 1387 1388 /* 1389 * Data for update QCN/DCQCN RL ramrod 1390 */ 1391 struct rl_update_ramrod_data 1392 { 1393 u8 qcn_update_param_flg /* Update QCN global params: timeout. */; 1394 u8 dcqcn_update_param_flg /* Update DCQCN global params: timeout, g, k. */; 1395 u8 rl_init_flg /* Init RL parameters, when RL disabled. */; 1396 u8 rl_start_flg /* Start RL in IDLE state. Set rate to maximum. */; 1397 u8 rl_stop_flg /* Stop RL. */; 1398 u8 rl_id_first /* ID of first or single RL, that will be updated. */; 1399 u8 rl_id_last /* ID of last RL, that will be updated. If clear, single RL will updated. */; 1400 u8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */; 1401 __le32 rl_bc_rate /* Byte Counter Limit. */; 1402 __le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */; 1403 __le16 rl_r_ai /* Active increase rate. */; 1404 __le16 rl_r_hai /* Hyper active increase rate. */; 1405 __le16 dcqcn_g /* DCQCN Alpha update gain in 1/64K resolution . */; 1406 __le32 dcqcn_k_us /* DCQCN Alpha update interval. */; 1407 __le32 dcqcn_timeuot_us /* DCQCN timeout. */; 1408 __le32 qcn_timeuot_us /* QCN timeout. */; 1409 __le32 reserved[2]; 1410 }; 1411 1412 1413 /* 1414 * Slowpath Element (SPQE) 1415 */ 1416 struct slow_path_element 1417 { 1418 struct ramrod_header hdr /* Ramrod Header */; 1419 struct regpair data_ptr /* Pointer to the Ramrod Data on the Host */; 1420 }; 1421 1422 1423 /* 1424 * Tstorm non-triggering VF zone 1425 */ 1426 struct tstorm_non_trigger_vf_zone 1427 { 1428 struct rdma_rcv_stats rdma_stats /* RoCE received statistics */; 1429 }; 1430 1431 1432 struct tstorm_per_port_stat 1433 { 1434 struct regpair trunc_error_discard /* packet is dropped because it was truncated in NIG */; 1435 struct regpair mac_error_discard /* packet is dropped because of Ethernet FCS error */; 1436 struct regpair mftag_filter_discard /* packet is dropped because classification was unsuccessful */; 1437 struct regpair eth_mac_filter_discard /* packet was passed to Ethernet and dropped because of no mac filter match */; 1438 struct regpair ll2_mac_filter_discard /* packet passed to Light L2 and dropped because Light L2 is not configured for this PF */; 1439 struct regpair ll2_conn_disabled_discard /* packet passed to Light L2 and dropped because Light L2 is not configured for this PF */; 1440 struct regpair iscsi_irregular_pkt /* packet is an ISCSI irregular packet */; 1441 struct regpair fcoe_irregular_pkt /* packet is an FCOE irregular packet */; 1442 struct regpair roce_irregular_pkt /* packet is an ROCE irregular packet */; 1443 struct regpair iwarp_irregular_pkt /* packet is an IWARP irregular packet */; 1444 struct regpair eth_irregular_pkt /* packet is an ETH irregular packet */; 1445 struct regpair toe_irregular_pkt /* packet is an TOE irregular packet */; 1446 struct regpair preroce_irregular_pkt /* packet is an PREROCE irregular packet */; 1447 struct regpair eth_gre_tunn_filter_discard /* GRE dropped packets */; 1448 struct regpair eth_vxlan_tunn_filter_discard /* VXLAN dropped packets */; 1449 struct regpair eth_geneve_tunn_filter_discard /* GENEVE dropped packets */; 1450 }; 1451 1452 1453 /* 1454 * Tstorm VF zone 1455 */ 1456 struct tstorm_vf_zone 1457 { 1458 struct tstorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 1459 }; 1460 1461 1462 /* 1463 * Tunnel classification scheme 1464 */ 1465 enum tunnel_clss 1466 { 1467 TUNNEL_CLSS_MAC_VLAN=0 /* Use MAC and VLAN from first L2 header for vport classification. */, 1468 TUNNEL_CLSS_MAC_VNI /* Use MAC from first L2 header and VNI from tunnel header for vport classification */, 1469 TUNNEL_CLSS_INNER_MAC_VLAN /* Use MAC and VLAN from last L2 header for vport classification */, 1470 TUNNEL_CLSS_INNER_MAC_VNI /* Use MAC from last L2 header and VNI from tunnel header for vport classification */, 1471 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE /* Use MAC and VLAN from last L2 header for vport classification. If no exact match, use MAC and VLAN from first L2 header for classification. */, 1472 MAX_TUNNEL_CLSS 1473 }; 1474 1475 1476 1477 /* 1478 * Ustorm non-triggering VF zone 1479 */ 1480 struct ustorm_non_trigger_vf_zone 1481 { 1482 struct eth_ustorm_per_queue_stat eth_queue_stat /* VF statistic bucket */; 1483 struct regpair vf_pf_msg_addr /* VF-PF message address */; 1484 }; 1485 1486 1487 /* 1488 * Ustorm triggering VF zone 1489 */ 1490 struct ustorm_trigger_vf_zone 1491 { 1492 u8 vf_pf_msg_valid /* VF-PF message valid flag */; 1493 u8 reserved[7]; 1494 }; 1495 1496 1497 /* 1498 * Ustorm VF zone 1499 */ 1500 struct ustorm_vf_zone 1501 { 1502 struct ustorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 1503 struct ustorm_trigger_vf_zone trigger /* interrupt triggering zone */; 1504 }; 1505 1506 1507 /* 1508 * VF-PF channel data 1509 */ 1510 struct vf_pf_channel_data 1511 { 1512 __le32 ready /* 0: VF-PF Channel NOT ready. Waiting for ack from PF driver. 1: VF-PF Channel is ready for a new transaction. */; 1513 u8 valid /* 0: VF-PF Channel is invalid because of malicious VF. 1: VF-PF Channel is valid. */; 1514 u8 reserved0; 1515 __le16 reserved1; 1516 }; 1517 1518 1519 /* 1520 * Ramrod data for VF start ramrod 1521 */ 1522 struct vf_start_ramrod_data 1523 { 1524 u8 vf_id /* VF ID */; 1525 u8 enable_flr_ack /* If set, initial cleanup ack will be sent to parent PF SP event queue */; 1526 __le16 opaque_fid /* VF opaque FID */; 1527 u8 personality /* define what type of personality is new VF */; 1528 u8 reserved[7]; 1529 struct hsi_fp_ver_struct hsi_fp_ver /* FP HSI version to be used by FW */; 1530 }; 1531 1532 1533 /* 1534 * Ramrod data for VF start ramrod 1535 */ 1536 struct vf_stop_ramrod_data 1537 { 1538 u8 vf_id /* VF ID */; 1539 u8 reserved0; 1540 __le16 reserved1; 1541 __le32 reserved2; 1542 }; 1543 1544 1545 /* 1546 * VF zone size mode. 1547 */ 1548 enum vf_zone_size_mode 1549 { 1550 VF_ZONE_SIZE_MODE_DEFAULT /* Default VF zone size. Up to 192 VF supported. */, 1551 VF_ZONE_SIZE_MODE_DOUBLE /* Doubled VF zone size. Up to 96 VF supported. */, 1552 VF_ZONE_SIZE_MODE_QUAD /* Quad VF zone size. Up to 48 VF supported. */, 1553 MAX_VF_ZONE_SIZE_MODE 1554 }; 1555 1556 1557 1558 1559 /* 1560 * Attentions status block 1561 */ 1562 struct atten_status_block 1563 { 1564 __le32 atten_bits; 1565 __le32 atten_ack; 1566 __le16 reserved0; 1567 __le16 sb_index /* status block running index */; 1568 __le32 reserved1; 1569 }; 1570 1571 1572 /* 1573 * Igu cleanup bit values to distinguish between clean or producer consumer update. 1574 */ 1575 enum command_type_bit 1576 { 1577 IGU_COMMAND_TYPE_NOP=0, 1578 IGU_COMMAND_TYPE_SET=1, 1579 MAX_COMMAND_TYPE_BIT 1580 }; 1581 1582 1583 /* 1584 * DMAE command 1585 */ 1586 struct dmae_cmd 1587 { 1588 __le32 opcode; 1589 #define DMAE_CMD_SRC_MASK 0x1 /* DMA Source. 0 - PCIe, 1 - GRC (use enum dmae_cmd_src_enum) */ 1590 #define DMAE_CMD_SRC_SHIFT 0 1591 #define DMAE_CMD_DST_MASK 0x3 /* DMA destination. 0 - None, 1 - PCIe, 2 - GRC, 3 - None (use enum dmae_cmd_dst_enum) */ 1592 #define DMAE_CMD_DST_SHIFT 1 1593 #define DMAE_CMD_C_DST_MASK 0x1 /* Completion destination. 0 - PCie, 1 - GRC (use enum dmae_cmd_c_dst_enum) */ 1594 #define DMAE_CMD_C_DST_SHIFT 3 1595 #define DMAE_CMD_CRC_RESET_MASK 0x1 /* Reset the CRC result (do not use the previous result as the seed) */ 1596 #define DMAE_CMD_CRC_RESET_SHIFT 4 1597 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1 /* Reset the source address in the next go to the same source address of the previous go */ 1598 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5 1599 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1 /* Reset the destination address in the next go to the same destination address of the previous go */ 1600 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6 1601 #define DMAE_CMD_COMP_FUNC_MASK 0x1 /* 0 completion function is the same as src function, 1 - 0 completion function is the same as dst function (use enum dmae_cmd_comp_func_enum) */ 1602 #define DMAE_CMD_COMP_FUNC_SHIFT 7 1603 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1 /* 0 - Do not write a completion word, 1 - Write a completion word (use enum dmae_cmd_comp_word_en_enum) */ 1604 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8 1605 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1 /* 0 - Do not write a CRC word, 1 - Write a CRC word (use enum dmae_cmd_comp_crc_en_enum) */ 1606 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9 1607 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7 /* The CRC word should be taken from the DMAE address space from address 9+X, where X is the value in these bits. */ 1608 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10 1609 #define DMAE_CMD_RESERVED1_MASK 0x1 1610 #define DMAE_CMD_RESERVED1_SHIFT 13 1611 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3 1612 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14 1613 #define DMAE_CMD_ERR_HANDLING_MASK 0x3 /* The field specifies how the completion word is affected by PCIe read error. 0 Send a regular completion, 1 - Send a completion with an error indication, 2 do not send a completion (use enum dmae_cmd_error_handling_enum) */ 1614 #define DMAE_CMD_ERR_HANDLING_SHIFT 16 1615 #define DMAE_CMD_PORT_ID_MASK 0x3 /* The port ID to be placed on the RF FID field of the GRC bus. this field is used both when GRC is the destination and when it is the source of the DMAE transaction. */ 1616 #define DMAE_CMD_PORT_ID_SHIFT 18 1617 #define DMAE_CMD_SRC_PF_ID_MASK 0xF /* Source PCI function number [3:0] */ 1618 #define DMAE_CMD_SRC_PF_ID_SHIFT 20 1619 #define DMAE_CMD_DST_PF_ID_MASK 0xF /* Destination PCI function number [3:0] */ 1620 #define DMAE_CMD_DST_PF_ID_SHIFT 24 1621 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 /* Source VFID valid */ 1622 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28 1623 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 /* Destination VFID valid */ 1624 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29 1625 #define DMAE_CMD_RESERVED2_MASK 0x3 1626 #define DMAE_CMD_RESERVED2_SHIFT 30 1627 __le32 src_addr_lo /* PCIe source address low in bytes or GRC source address in DW */; 1628 __le32 src_addr_hi /* PCIe source address high in bytes or reserved (if source is GRC) */; 1629 __le32 dst_addr_lo /* PCIe destination address low in bytes or GRC destination address in DW */; 1630 __le32 dst_addr_hi /* PCIe destination address high in bytes or reserved (if destination is GRC) */; 1631 __le16 length_dw /* Length in DW */; 1632 __le16 opcode_b; 1633 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */ 1634 #define DMAE_CMD_SRC_VF_ID_SHIFT 0 1635 #define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */ 1636 #define DMAE_CMD_DST_VF_ID_SHIFT 8 1637 __le32 comp_addr_lo /* PCIe completion address low in bytes or GRC completion address in DW */; 1638 __le32 comp_addr_hi /* PCIe completion address high in bytes or reserved (if completion address is GRC) */; 1639 __le32 comp_val /* Value to write to completion address */; 1640 __le32 crc32 /* crc16 result */; 1641 __le32 crc_32_c /* crc32_c result */; 1642 __le16 crc16 /* crc16 result */; 1643 __le16 crc16_c /* crc16_c result */; 1644 __le16 crc10 /* crc_t10 result */; 1645 __le16 reserved; 1646 __le16 xsum16 /* checksum16 result */; 1647 __le16 xsum8 /* checksum8 result */; 1648 }; 1649 1650 1651 enum dmae_cmd_comp_crc_en_enum 1652 { 1653 dmae_cmd_comp_crc_disabled /* Do not write a CRC word */, 1654 dmae_cmd_comp_crc_enabled /* Write a CRC word */, 1655 MAX_DMAE_CMD_COMP_CRC_EN_ENUM 1656 }; 1657 1658 1659 enum dmae_cmd_comp_func_enum 1660 { 1661 dmae_cmd_comp_func_to_src /* completion word and/or CRC will be sent to SRC-PCI function/SRC VFID */, 1662 dmae_cmd_comp_func_to_dst /* completion word and/or CRC will be sent to DST-PCI function/DST VFID */, 1663 MAX_DMAE_CMD_COMP_FUNC_ENUM 1664 }; 1665 1666 1667 enum dmae_cmd_comp_word_en_enum 1668 { 1669 dmae_cmd_comp_word_disabled /* Do not write a completion word */, 1670 dmae_cmd_comp_word_enabled /* Write the completion word */, 1671 MAX_DMAE_CMD_COMP_WORD_EN_ENUM 1672 }; 1673 1674 1675 enum dmae_cmd_c_dst_enum 1676 { 1677 dmae_cmd_c_dst_pcie, 1678 dmae_cmd_c_dst_grc, 1679 MAX_DMAE_CMD_C_DST_ENUM 1680 }; 1681 1682 1683 enum dmae_cmd_dst_enum 1684 { 1685 dmae_cmd_dst_none_0, 1686 dmae_cmd_dst_pcie, 1687 dmae_cmd_dst_grc, 1688 dmae_cmd_dst_none_3, 1689 MAX_DMAE_CMD_DST_ENUM 1690 }; 1691 1692 1693 enum dmae_cmd_error_handling_enum 1694 { 1695 dmae_cmd_error_handling_send_regular_comp /* Send a regular completion (with no error indication) */, 1696 dmae_cmd_error_handling_send_comp_with_err /* Send a completion with an error indication (i.e. set bit 31 of the completion word) */, 1697 dmae_cmd_error_handling_dont_send_comp /* Do not send a completion */, 1698 MAX_DMAE_CMD_ERROR_HANDLING_ENUM 1699 }; 1700 1701 1702 enum dmae_cmd_src_enum 1703 { 1704 dmae_cmd_src_pcie /* The source is the PCIe */, 1705 dmae_cmd_src_grc /* The source is the GRC */, 1706 MAX_DMAE_CMD_SRC_ENUM 1707 }; 1708 1709 1710 struct e4_mstorm_core_conn_ag_ctx 1711 { 1712 u8 byte0 /* cdu_validation */; 1713 u8 byte1 /* state */; 1714 u8 flags0; 1715 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1716 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1717 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1718 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1719 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1720 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1721 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1722 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1723 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1724 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1725 u8 flags1; 1726 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1727 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1728 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1729 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1730 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1731 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1732 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1733 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1734 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1735 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1736 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1737 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1738 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1739 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1740 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1741 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 1742 __le16 word0 /* word0 */; 1743 __le16 word1 /* word1 */; 1744 __le32 reg0 /* reg0 */; 1745 __le32 reg1 /* reg1 */; 1746 }; 1747 1748 1749 1750 1751 1752 struct e4_ystorm_core_conn_ag_ctx 1753 { 1754 u8 byte0 /* cdu_validation */; 1755 u8 byte1 /* state */; 1756 u8 flags0; 1757 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1758 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1759 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1760 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1761 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1762 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1763 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1764 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1765 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1766 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1767 u8 flags1; 1768 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1769 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1770 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1771 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1772 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1773 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1774 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1775 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1776 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1777 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1778 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1779 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1780 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1781 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1782 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1783 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 1784 u8 byte2 /* byte2 */; 1785 u8 byte3 /* byte3 */; 1786 __le16 word0 /* word0 */; 1787 __le32 reg0 /* reg0 */; 1788 __le32 reg1 /* reg1 */; 1789 __le16 word1 /* word1 */; 1790 __le16 word2 /* word2 */; 1791 __le16 word3 /* word3 */; 1792 __le16 word4 /* word4 */; 1793 __le32 reg2 /* reg2 */; 1794 __le32 reg3 /* reg3 */; 1795 }; 1796 1797 1798 struct e5_mstorm_core_conn_ag_ctx 1799 { 1800 u8 byte0 /* cdu_validation */; 1801 u8 byte1 /* state_and_core_id */; 1802 u8 flags0; 1803 #define E5_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1804 #define E5_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1805 #define E5_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1806 #define E5_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1807 #define E5_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1808 #define E5_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1809 #define E5_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1810 #define E5_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1811 #define E5_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1812 #define E5_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1813 u8 flags1; 1814 #define E5_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1815 #define E5_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1816 #define E5_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1817 #define E5_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1818 #define E5_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1819 #define E5_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1820 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1821 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1822 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1823 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1824 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1825 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1826 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1827 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1828 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1829 #define E5_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 1830 __le16 word0 /* word0 */; 1831 __le16 word1 /* word1 */; 1832 __le32 reg0 /* reg0 */; 1833 __le32 reg1 /* reg1 */; 1834 }; 1835 1836 1837 struct e5_tstorm_core_conn_ag_ctx 1838 { 1839 u8 byte0 /* cdu_validation */; 1840 u8 byte1 /* state_and_core_id */; 1841 u8 flags0; 1842 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1843 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1844 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1845 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1846 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1847 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 1848 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1849 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 1850 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1851 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 1852 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1853 #define E5_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 1854 #define E5_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1855 #define E5_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 1856 u8 flags1; 1857 #define E5_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1858 #define E5_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 1859 #define E5_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1860 #define E5_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 1861 #define E5_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1862 #define E5_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 1863 #define E5_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1864 #define E5_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 1865 u8 flags2; 1866 #define E5_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1867 #define E5_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 1868 #define E5_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1869 #define E5_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 1870 #define E5_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1871 #define E5_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 1872 #define E5_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1873 #define E5_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 1874 u8 flags3; 1875 #define E5_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1876 #define E5_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 1877 #define E5_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1878 #define E5_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 1879 #define E5_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1880 #define E5_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 1881 #define E5_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1882 #define E5_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 1883 #define E5_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1884 #define E5_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 1885 #define E5_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1886 #define E5_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 1887 u8 flags4; 1888 #define E5_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1889 #define E5_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 1890 #define E5_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1891 #define E5_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 1892 #define E5_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1893 #define E5_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 1894 #define E5_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1895 #define E5_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 1896 #define E5_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1897 #define E5_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 1898 #define E5_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1899 #define E5_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 1900 #define E5_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1901 #define E5_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 1902 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1903 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 1904 u8 flags5; 1905 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1906 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 1907 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1908 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 1909 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1910 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 1911 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1912 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 1913 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1914 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 1915 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1916 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 1917 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1918 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 1919 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1920 #define E5_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 1921 u8 flags6; 1922 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1923 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1924 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1925 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1926 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1927 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1928 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1929 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1930 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1931 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1932 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1933 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1934 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1935 #define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1936 u8 byte2 /* byte2 */; 1937 __le16 word0 /* word0 */; 1938 __le32 reg0 /* reg0 */; 1939 __le32 reg1 /* reg1 */; 1940 __le32 reg2 /* reg2 */; 1941 __le32 reg3 /* reg3 */; 1942 __le32 reg4 /* reg4 */; 1943 __le32 reg5 /* reg5 */; 1944 __le32 reg6 /* reg6 */; 1945 __le32 reg7 /* reg7 */; 1946 __le32 reg8 /* reg8 */; 1947 u8 byte3 /* byte3 */; 1948 u8 byte4 /* byte4 */; 1949 u8 byte5 /* byte5 */; 1950 u8 e4_reserved8 /* byte6 */; 1951 __le16 word1 /* word1 */; 1952 __le16 word2 /* conn_dpi */; 1953 __le32 reg9 /* reg9 */; 1954 __le16 word3 /* word3 */; 1955 __le16 e4_reserved9 /* word4 */; 1956 }; 1957 1958 1959 struct e5_ustorm_core_conn_ag_ctx 1960 { 1961 u8 reserved /* cdu_validation */; 1962 u8 byte1 /* state_and_core_id */; 1963 u8 flags0; 1964 #define E5_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1965 #define E5_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1966 #define E5_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1967 #define E5_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1968 #define E5_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1969 #define E5_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1970 #define E5_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1971 #define E5_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1972 #define E5_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1973 #define E5_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1974 u8 flags1; 1975 #define E5_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1976 #define E5_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 1977 #define E5_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1978 #define E5_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 1979 #define E5_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1980 #define E5_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 1981 #define E5_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1982 #define E5_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 1983 u8 flags2; 1984 #define E5_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1985 #define E5_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1986 #define E5_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1987 #define E5_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1988 #define E5_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1989 #define E5_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1990 #define E5_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1991 #define E5_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 1992 #define E5_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1993 #define E5_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 1994 #define E5_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1995 #define E5_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 1996 #define E5_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1997 #define E5_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 1998 #define E5_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1999 #define E5_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 2000 u8 flags3; 2001 #define E5_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2002 #define E5_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 2003 #define E5_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2004 #define E5_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 2005 #define E5_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2006 #define E5_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 2007 #define E5_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2008 #define E5_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 2009 #define E5_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2010 #define E5_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 2011 #define E5_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2012 #define E5_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 2013 #define E5_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2014 #define E5_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 2015 #define E5_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 2016 #define E5_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 2017 u8 flags4; 2018 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 2019 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2020 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 2021 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2022 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 2023 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2024 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 2025 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 2026 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 2027 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 2028 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 2029 #define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 2030 u8 byte2 /* byte2 */; 2031 __le16 word0 /* conn_dpi */; 2032 __le16 word1 /* word1 */; 2033 __le32 rx_producers /* reg0 */; 2034 __le32 reg1 /* reg1 */; 2035 __le32 reg2 /* reg2 */; 2036 __le32 reg3 /* reg3 */; 2037 __le16 word2 /* word2 */; 2038 __le16 word3 /* word3 */; 2039 }; 2040 2041 2042 struct e5_xstorm_core_conn_ag_ctx 2043 { 2044 u8 reserved0 /* cdu_validation */; 2045 u8 state_and_core_id /* state_and_core_id */; 2046 u8 flags0; 2047 #define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2048 #define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 2049 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 2050 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 2051 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 2052 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 2053 #define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 2054 #define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 2055 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 2056 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 2057 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 2058 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 2059 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 2060 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 2061 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 2062 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 2063 u8 flags1; 2064 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 2065 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 2066 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 2067 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 2068 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 2069 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 2070 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 2071 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 2072 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 2073 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 2074 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 2075 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 2076 #define E5_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 2077 #define E5_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 2078 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 2079 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 2080 u8 flags2; 2081 #define E5_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 2082 #define E5_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 2083 #define E5_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 2084 #define E5_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 2085 #define E5_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 2086 #define E5_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 2087 #define E5_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 2088 #define E5_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 2089 u8 flags3; 2090 #define E5_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 2091 #define E5_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 2092 #define E5_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 2093 #define E5_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 2094 #define E5_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 2095 #define E5_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 2096 #define E5_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 2097 #define E5_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 2098 u8 flags4; 2099 #define E5_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2100 #define E5_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 2101 #define E5_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2102 #define E5_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 2103 #define E5_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2104 #define E5_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 2105 #define E5_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2106 #define E5_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 2107 u8 flags5; 2108 #define E5_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2109 #define E5_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 2110 #define E5_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2111 #define E5_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 2112 #define E5_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2113 #define E5_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 2114 #define E5_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2115 #define E5_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 2116 u8 flags6; 2117 #define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */ 2118 #define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 2119 #define E5_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2120 #define E5_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 2121 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 2122 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 2123 #define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 2124 #define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 2125 u8 flags7; 2126 #define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 2127 #define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 2128 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 2129 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 2130 #define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2131 #define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2132 #define E5_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2133 #define E5_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 2134 #define E5_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2135 #define E5_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 2136 u8 flags8; 2137 #define E5_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2138 #define E5_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 2139 #define E5_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2140 #define E5_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 2141 #define E5_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2142 #define E5_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 2143 #define E5_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2144 #define E5_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 2145 #define E5_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2146 #define E5_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 2147 #define E5_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 2148 #define E5_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 2149 #define E5_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2150 #define E5_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 2151 #define E5_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2152 #define E5_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 2153 u8 flags9; 2154 #define E5_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2155 #define E5_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 2156 #define E5_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2157 #define E5_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 2158 #define E5_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2159 #define E5_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 2160 #define E5_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2161 #define E5_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 2162 #define E5_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2163 #define E5_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 2164 #define E5_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2165 #define E5_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 2166 #define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */ 2167 #define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 2168 #define E5_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2169 #define E5_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 2170 u8 flags10; 2171 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 2172 #define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 2173 #define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 2174 #define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 2175 #define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 2176 #define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 2177 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 2178 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 2179 #define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2180 #define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2181 #define E5_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2182 #define E5_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 2183 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 2184 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 2185 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 2186 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 2187 u8 flags11; 2188 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 2189 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 2190 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 2191 #define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 2192 #define E5_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 2193 #define E5_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 2194 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2195 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 2196 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2197 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 2198 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2199 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 2200 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2201 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2202 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2203 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 2204 u8 flags12; 2205 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2206 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 2207 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2208 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 2209 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2210 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2211 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2212 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2213 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2214 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 2215 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2216 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 2217 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2218 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 2219 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2220 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 2221 u8 flags13; 2222 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2223 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 2224 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2225 #define E5_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 2226 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2227 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2228 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2229 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2230 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2231 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2232 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2233 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2234 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2235 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2236 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2237 #define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2238 u8 flags14; 2239 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 2240 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 2241 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2242 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 2243 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 2244 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 2245 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 2246 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 2247 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 2248 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 2249 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 2250 #define E5_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 2251 #define E5_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2252 #define E5_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 2253 u8 byte2 /* byte2 */; 2254 __le16 physical_q0 /* physical_q0 */; 2255 __le16 consolid_prod /* physical_q1 */; 2256 __le16 reserved16 /* physical_q2 */; 2257 __le16 tx_bd_cons /* word3 */; 2258 __le16 tx_bd_or_spq_prod /* word4 */; 2259 __le16 word5 /* word5 */; 2260 __le16 conn_dpi /* conn_dpi */; 2261 u8 byte3 /* byte3 */; 2262 u8 byte4 /* byte4 */; 2263 u8 byte5 /* byte5 */; 2264 u8 byte6 /* byte6 */; 2265 __le32 reg0 /* reg0 */; 2266 __le32 reg1 /* reg1 */; 2267 __le32 reg2 /* reg2 */; 2268 __le32 reg3 /* reg3 */; 2269 __le32 reg4 /* reg4 */; 2270 __le32 reg5 /* cf_array0 */; 2271 __le32 reg6 /* cf_array1 */; 2272 u8 flags15; 2273 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 2274 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 2275 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 2276 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 2277 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 2278 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 2279 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 2280 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 2281 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 2282 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 2283 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 2284 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 2285 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 2286 #define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 2287 u8 byte7 /* byte7 */; 2288 __le16 word7 /* word7 */; 2289 __le16 word8 /* word8 */; 2290 __le16 word9 /* word9 */; 2291 __le16 word10 /* word10 */; 2292 __le16 word11 /* word11 */; 2293 __le32 reg7 /* reg7 */; 2294 __le32 reg8 /* reg8 */; 2295 __le32 reg9 /* reg9 */; 2296 u8 byte8 /* byte8 */; 2297 u8 byte9 /* byte9 */; 2298 u8 byte10 /* byte10 */; 2299 u8 byte11 /* byte11 */; 2300 u8 byte12 /* byte12 */; 2301 u8 byte13 /* byte13 */; 2302 u8 byte14 /* byte14 */; 2303 u8 byte15 /* byte15 */; 2304 __le32 reg10 /* reg10 */; 2305 __le32 reg11 /* reg11 */; 2306 __le32 reg12 /* reg12 */; 2307 __le32 reg13 /* reg13 */; 2308 __le32 reg14 /* reg14 */; 2309 __le32 reg15 /* reg15 */; 2310 __le32 reg16 /* reg16 */; 2311 __le32 reg17 /* reg17 */; 2312 __le32 reg18 /* reg18 */; 2313 __le32 reg19 /* reg19 */; 2314 __le16 word12 /* word12 */; 2315 __le16 word13 /* word13 */; 2316 __le16 word14 /* word14 */; 2317 __le16 word15 /* word15 */; 2318 }; 2319 2320 2321 struct e5_ystorm_core_conn_ag_ctx 2322 { 2323 u8 byte0 /* cdu_validation */; 2324 u8 byte1 /* state_and_core_id */; 2325 u8 flags0; 2326 #define E5_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2327 #define E5_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 2328 #define E5_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2329 #define E5_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 2330 #define E5_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2331 #define E5_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 2332 #define E5_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2333 #define E5_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 2334 #define E5_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2335 #define E5_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 2336 u8 flags1; 2337 #define E5_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2338 #define E5_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 2339 #define E5_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2340 #define E5_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 2341 #define E5_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2342 #define E5_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 2343 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2344 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 2345 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2346 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 2347 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2348 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 2349 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2350 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 2351 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2352 #define E5_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 2353 u8 byte2 /* byte2 */; 2354 u8 byte3 /* byte3 */; 2355 __le16 word0 /* word0 */; 2356 __le32 reg0 /* reg0 */; 2357 __le32 reg1 /* reg1 */; 2358 __le16 word1 /* word1 */; 2359 __le16 word2 /* word2 */; 2360 __le16 word3 /* word3 */; 2361 __le16 word4 /* word4 */; 2362 __le32 reg2 /* reg2 */; 2363 __le32 reg3 /* reg3 */; 2364 }; 2365 2366 2367 /* 2368 * IGU cleanup command 2369 */ 2370 struct igu_cleanup 2371 { 2372 __le32 sb_id_and_flags; 2373 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF 2374 #define IGU_CLEANUP_RESERVED0_SHIFT 0 2375 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 /* cleanup clear - 0, set - 1 */ 2376 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27 2377 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 2378 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 2379 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 /* must always be set (use enum command_type_bit) */ 2380 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 2381 __le32 reserved1; 2382 }; 2383 2384 2385 /* 2386 * IGU firmware driver command 2387 */ 2388 union igu_command 2389 { 2390 struct igu_prod_cons_update prod_cons_update; 2391 struct igu_cleanup cleanup; 2392 }; 2393 2394 2395 /* 2396 * IGU firmware driver command 2397 */ 2398 struct igu_command_reg_ctrl 2399 { 2400 __le16 opaque_fid; 2401 __le16 igu_command_reg_ctrl_fields; 2402 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF 2403 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0 2404 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7 2405 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12 2406 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1 /* command typ: 0 - read, 1 - write */ 2407 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15 2408 }; 2409 2410 2411 /* 2412 * IGU mapping line structure 2413 */ 2414 struct igu_mapping_line 2415 { 2416 __le32 igu_mapping_line_fields; 2417 #define IGU_MAPPING_LINE_VALID_MASK 0x1 2418 #define IGU_MAPPING_LINE_VALID_SHIFT 0 2419 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF 2420 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1 2421 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF /* In BB: VF-0-120, PF-0-7; In K2: VF-0-191, PF-0-15 */ 2422 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9 2423 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */ 2424 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17 2425 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F 2426 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18 2427 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF 2428 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24 2429 }; 2430 2431 2432 /* 2433 * IGU MSIX line structure 2434 */ 2435 struct igu_msix_vector 2436 { 2437 struct regpair address; 2438 __le32 data; 2439 __le32 msix_vector_fields; 2440 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1 2441 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0 2442 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF 2443 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1 2444 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF 2445 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16 2446 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF 2447 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24 2448 }; 2449 2450 2451 /* 2452 * per encapsulation type enabling flags 2453 */ 2454 struct prs_reg_encapsulation_type_en 2455 { 2456 u8 flags; 2457 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1 /* Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. */ 2458 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0 2459 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1 /* Enable bit for IP-over-GRE (IP GRE) encapsulation. */ 2460 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1 2461 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1 /* Enable bit for VXLAN encapsulation. */ 2462 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2 2463 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1 /* Enable bit for T-Tag encapsulation. */ 2464 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3 2465 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1 /* Enable bit for Ethernet-over-GENEVE (L2 GENEVE) encapsulation. */ 2466 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4 2467 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1 /* Enable bit for IP-over-GENEVE (IP GENEVE) encapsulation. */ 2468 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5 2469 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3 2470 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6 2471 }; 2472 2473 2474 enum pxp_tph_st_hint 2475 { 2476 TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */, 2477 TPH_ST_HINT_REQUESTER /* Read/Write access by Device */, 2478 TPH_ST_HINT_TARGET /* Device Write and Host Read, or Host Write and Device Read */, 2479 TPH_ST_HINT_TARGET_PRIO /* Device Write and Host Read, or Host Write and Device Read - with temporal reuse */, 2480 MAX_PXP_TPH_ST_HINT 2481 }; 2482 2483 2484 /* 2485 * QM hardware structure of enable bypass credit mask 2486 */ 2487 struct qm_rf_bypass_mask 2488 { 2489 u8 flags; 2490 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1 2491 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0 2492 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1 2493 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1 2494 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1 2495 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2 2496 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1 2497 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3 2498 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1 2499 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4 2500 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1 2501 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5 2502 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1 2503 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6 2504 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1 2505 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7 2506 }; 2507 2508 2509 /* 2510 * QM hardware structure of opportunistic credit mask 2511 */ 2512 struct qm_rf_opportunistic_mask 2513 { 2514 __le16 flags; 2515 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1 2516 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0 2517 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1 2518 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1 2519 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1 2520 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2 2521 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1 2522 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3 2523 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1 2524 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4 2525 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1 2526 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5 2527 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1 2528 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6 2529 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1 2530 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7 2531 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1 2532 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8 2533 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F 2534 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9 2535 }; 2536 2537 2538 /* 2539 * QM hardware structure of QM map memory 2540 */ 2541 struct qm_rf_pq_map 2542 { 2543 __le32 reg; 2544 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 /* PQ active */ 2545 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0 2546 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF /* RL ID */ 2547 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1 2548 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF /* the first PQ associated with the VPORT and VOQ of this PQ */ 2549 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9 2550 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F /* VOQ */ 2551 #define QM_RF_PQ_MAP_VOQ_SHIFT 18 2552 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */ 2553 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23 2554 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 /* RL active */ 2555 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25 2556 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F 2557 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26 2558 }; 2559 2560 2561 /* 2562 * Completion params for aggregated interrupt completion 2563 */ 2564 struct sdm_agg_int_comp_params 2565 { 2566 __le16 params; 2567 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F /* the number of aggregated interrupt, 0-31 */ 2568 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0 2569 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1 /* 1 - set a bit in aggregated vector, 0 - dont set */ 2570 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6 2571 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF /* Number of bit in the aggregated vector, 0-279 (TBD) */ 2572 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7 2573 }; 2574 2575 2576 /* 2577 * SDM operation gen command (generate aggregative interrupt) 2578 */ 2579 struct sdm_op_gen 2580 { 2581 __le32 command; 2582 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF /* completion parameters 0-15 */ 2583 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 2584 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */ 2585 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16 2586 #define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */ 2587 #define SDM_OP_GEN_RESERVED_SHIFT 20 2588 }; 2589 2590 #endif /* __ECORE_HSI_COMMON__ */ 2591