1e7a617a7SRobert Mustacchi /* 2e7a617a7SRobert Mustacchi * This file and its contents are supplied under the terms of the 3e7a617a7SRobert Mustacchi * Common Development and Distribution License ("CDDL"), version 1.0. 4e7a617a7SRobert Mustacchi * You may only use this file in accordance with the terms of version 5e7a617a7SRobert Mustacchi * 1.0 of the CDDL. 6e7a617a7SRobert Mustacchi * 7e7a617a7SRobert Mustacchi * A full copy of the text of the CDDL should have accompanied this 8e7a617a7SRobert Mustacchi * source. A copy of the CDDL is also available via the Internet at 9e7a617a7SRobert Mustacchi * http://www.illumos.org/license/CDDL. 10e7a617a7SRobert Mustacchi */ 11e7a617a7SRobert Mustacchi 12e7a617a7SRobert Mustacchi /* 13e7a617a7SRobert Mustacchi * Copyright 2019 Joyent, Inc. 14*89427192SRobert Mustacchi * Copyright 2022 Oxide Computer Company 15e7a617a7SRobert Mustacchi */ 16e7a617a7SRobert Mustacchi 17e7a617a7SRobert Mustacchi #ifndef _IO_PCIE_PCIEB_IOCTL_H 18e7a617a7SRobert Mustacchi #define _IO_PCIE_PCIEB_IOCTL_H 19e7a617a7SRobert Mustacchi 20e7a617a7SRobert Mustacchi /* 21e7a617a7SRobert Mustacchi * These are private ioctls for PCIe bridges that are currently consumed by the 22e7a617a7SRobert Mustacchi * 'pcieb' command. These should be used until we figure out how best to 23e7a617a7SRobert Mustacchi * represent PCIe links in the traditional cfgadm and devctl frameworks. 24e7a617a7SRobert Mustacchi */ 25e7a617a7SRobert Mustacchi 26e7a617a7SRobert Mustacchi #include <sys/stdint.h> 27e7a617a7SRobert Mustacchi 28e7a617a7SRobert Mustacchi #ifdef __cplusplus 29e7a617a7SRobert Mustacchi extern "C" { 30e7a617a7SRobert Mustacchi #endif 31e7a617a7SRobert Mustacchi 32e7a617a7SRobert Mustacchi #define PCIEB_IOCTL (('p' << 24) | ('c' << 16) | ('b' << 8)) 33e7a617a7SRobert Mustacchi 34e7a617a7SRobert Mustacchi /* 35e7a617a7SRobert Mustacchi * This requests that we retrain the link that the PCIe bridge has to its 36e7a617a7SRobert Mustacchi * downstream component. 37e7a617a7SRobert Mustacchi */ 38e7a617a7SRobert Mustacchi #define PCIEB_IOCTL_RETRAIN (PCIEB_IOCTL | 0x01) 39e7a617a7SRobert Mustacchi 40e7a617a7SRobert Mustacchi /* 41e7a617a7SRobert Mustacchi * Get and set the current target speed for a bridge. The target speed of the 42e7a617a7SRobert Mustacchi * bridge will have an impact on the values that end up being used by its 43e7a617a7SRobert Mustacchi * downstream components. 44e7a617a7SRobert Mustacchi */ 45e7a617a7SRobert Mustacchi #define PCIEB_IOCTL_GET_TARGET_SPEED (PCIEB_IOCTL | 0x02) 46e7a617a7SRobert Mustacchi #define PCIEB_IOCTL_SET_TARGET_SPEED (PCIEB_IOCTL | 0x03) 47e7a617a7SRobert Mustacchi 48e7a617a7SRobert Mustacchi typedef struct pcieb_ioctl_target_speed { 49e7a617a7SRobert Mustacchi uint32_t pits_flags; 50e7a617a7SRobert Mustacchi uint32_t pits_speed; 51e7a617a7SRobert Mustacchi } pcieb_ioctl_target_speed_t; 52e7a617a7SRobert Mustacchi 53e7a617a7SRobert Mustacchi #define PCIEB_FLAGS_ADMIN_SET 0x01 54e7a617a7SRobert Mustacchi 55e7a617a7SRobert Mustacchi #define PCIEB_LINK_SPEED_UNKNOWN 0x00 56e7a617a7SRobert Mustacchi #define PCIEB_LINK_SPEED_GEN1 0x01 57e7a617a7SRobert Mustacchi #define PCIEB_LINK_SPEED_GEN2 0x02 58e7a617a7SRobert Mustacchi #define PCIEB_LINK_SPEED_GEN3 0x03 59e7a617a7SRobert Mustacchi #define PCIEB_LINK_SPEED_GEN4 0x04 60*89427192SRobert Mustacchi #define PCIEB_LINK_SPEED_GEN5 0x05 61*89427192SRobert Mustacchi #define PCIEB_LINK_SPEED_GEN6 0x06 62e7a617a7SRobert Mustacchi 63e7a617a7SRobert Mustacchi #ifdef __cplusplus 64e7a617a7SRobert Mustacchi } 65e7a617a7SRobert Mustacchi #endif 66e7a617a7SRobert Mustacchi 67e7a617a7SRobert Mustacchi #endif /* _IO_PCIE_PCIEB_IOCTL_H */ 68