xref: /illumos-gate/usr/src/uts/common/io/pciex/pcieb.c (revision b24ab6762772a3f6a89393947930c7fa61306783)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /*
27  * Common x86 and SPARC PCI-E to PCI bus bridge nexus driver
28  */
29 
30 #include <sys/sysmacros.h>
31 #include <sys/conf.h>
32 #include <sys/kmem.h>
33 #include <sys/debug.h>
34 #include <sys/modctl.h>
35 #include <sys/autoconf.h>
36 #include <sys/ddi_impldefs.h>
37 #include <sys/pci.h>
38 #include <sys/ddi.h>
39 #include <sys/sunddi.h>
40 #include <sys/sunndi.h>
41 #include <sys/fm/util.h>
42 #include <sys/pcie.h>
43 #include <sys/pci_cap.h>
44 #include <sys/pcie_impl.h>
45 #include <sys/hotplug/pci/pcihp.h>
46 #include <sys/hotplug/pci/pciehpc.h>
47 #include <sys/hotplug/pci/pcishpc.h>
48 #include <sys/open.h>
49 #include <sys/stat.h>
50 #include <sys/file.h>
51 #include <sys/promif.h>		/* prom_printf */
52 #include <sys/disp.h>
53 #include <sys/pcie_pwr.h>
54 #include "pcieb.h"
55 #ifdef PX_PLX
56 #include <io/pciex/pcieb_plx.h>
57 #endif /* PX_PLX */
58 
59 /*LINTLIBRARY*/
60 
61 /* panic flag */
62 int pcieb_die = PF_ERR_FATAL_FLAGS;
63 
64 /* flag to turn on MSI support */
65 int pcieb_enable_msi = 1;
66 
67 #if defined(DEBUG)
68 uint_t pcieb_dbg_print = 0;
69 
70 static char *pcieb_debug_sym [] = {	/* same sequence as pcieb_debug_bit */
71 	/*  0 */ "attach",
72 	/*  1 */ "pwr",
73 	/*  2 */ "intr"
74 };
75 #endif /* DEBUG */
76 
77 static int pcieb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, off_t,
78 	off_t, caddr_t *);
79 static int pcieb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, void *,
80 	void *);
81 static int pcieb_fm_init(pcieb_devstate_t *pcieb_p);
82 static void pcieb_fm_fini(pcieb_devstate_t *pcieb_p);
83 static int pcieb_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap,
84     ddi_iblock_cookie_t *ibc_p);
85 static int pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
86 	ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg,
87 	ddi_dma_handle_t *handlep);
88 static int pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip,
89 	ddi_dma_handle_t handle, enum ddi_dma_ctlops cmd, off_t *offp,
90 	size_t *lenp, caddr_t *objp, uint_t cache_flags);
91 static int pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip,
92 	ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result);
93 
94 static struct bus_ops pcieb_bus_ops = {
95 	BUSO_REV,
96 	pcieb_bus_map,
97 	0,
98 	0,
99 	0,
100 	i_ddi_map_fault,
101 	ddi_dma_map,
102 	pcieb_dma_allochdl,
103 	ddi_dma_freehdl,
104 	ddi_dma_bindhdl,
105 	ddi_dma_unbindhdl,
106 	ddi_dma_flush,
107 	ddi_dma_win,
108 	pcieb_dma_mctl,
109 	pcieb_ctlops,
110 	ddi_bus_prop_op,
111 	ndi_busop_get_eventcookie,	/* (*bus_get_eventcookie)();	*/
112 	ndi_busop_add_eventcall,	/* (*bus_add_eventcall)();	*/
113 	ndi_busop_remove_eventcall,	/* (*bus_remove_eventcall)();	*/
114 	ndi_post_event,			/* (*bus_post_event)();		*/
115 	NULL,				/* (*bus_intr_ctl)();		*/
116 	NULL,				/* (*bus_config)(); 		*/
117 	NULL,				/* (*bus_unconfig)(); 		*/
118 	pcieb_fm_init_child,		/* (*bus_fm_init)(); 		*/
119 	NULL,				/* (*bus_fm_fini)(); 		*/
120 	i_ndi_busop_access_enter,	/* (*bus_fm_access_enter)(); 	*/
121 	i_ndi_busop_access_exit,	/* (*bus_fm_access_exit)(); 	*/
122 	pcie_bus_power,			/* (*bus_power)(); 	*/
123 	pcieb_intr_ops			/* (*bus_intr_op)(); 		*/
124 };
125 
126 static int	pcieb_open(dev_t *, int, int, cred_t *);
127 static int	pcieb_close(dev_t, int, int, cred_t *);
128 static int	pcieb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
129 static int	pcieb_prop_op(dev_t, dev_info_t *, ddi_prop_op_t, int, char *,
130 		    caddr_t, int *);
131 static int	pcieb_info(dev_info_t *, ddi_info_cmd_t, void *, void **);
132 static uint_t 	pcieb_intr_handler(caddr_t arg1, caddr_t arg2);
133 
134 /* PM related functions */
135 static int	pcieb_pwr_setup(dev_info_t *dip);
136 static int	pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p);
137 static void	pcieb_pwr_teardown(dev_info_t *dip);
138 static int	pcieb_pwr_disable(dev_info_t *dip);
139 
140 /* Hotplug related functions */
141 static int pcieb_pciehpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle);
142 static int pcieb_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle);
143 static int pcieb_init_hotplug(pcieb_devstate_t *pcieb);
144 static void pcieb_id_props(pcieb_devstate_t *pcieb);
145 
146 /*
147  * soft state pointer
148  */
149 void *pcieb_state;
150 
151 static struct cb_ops pcieb_cb_ops = {
152 	pcieb_open,			/* open */
153 	pcieb_close,			/* close */
154 	nodev,				/* strategy */
155 	nodev,				/* print */
156 	nodev,				/* dump */
157 	nodev,				/* read */
158 	nodev,				/* write */
159 	pcieb_ioctl,			/* ioctl */
160 	nodev,				/* devmap */
161 	nodev,				/* mmap */
162 	nodev,				/* segmap */
163 	nochpoll,			/* poll */
164 	pcieb_prop_op,			/* cb_prop_op */
165 	NULL,				/* streamtab */
166 	D_NEW | D_MP | D_HOTPLUG,	/* Driver compatibility flag */
167 	CB_REV,				/* rev */
168 	nodev,				/* int (*cb_aread)() */
169 	nodev				/* int (*cb_awrite)() */
170 };
171 
172 static int	pcieb_probe(dev_info_t *);
173 static int	pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd);
174 static int	pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
175 
176 static struct dev_ops pcieb_ops = {
177 	DEVO_REV,		/* devo_rev */
178 	0,			/* refcnt  */
179 	pcieb_info,		/* info */
180 	nulldev,		/* identify */
181 	pcieb_probe,		/* probe */
182 	pcieb_attach,		/* attach */
183 	pcieb_detach,		/* detach */
184 	nulldev,		/* reset */
185 	&pcieb_cb_ops,		/* driver operations */
186 	&pcieb_bus_ops,		/* bus operations */
187 	pcie_power,		/* power */
188 	ddi_quiesce_not_needed,		/* quiesce */
189 };
190 
191 /*
192  * Module linkage information for the kernel.
193  */
194 
195 static struct modldrv modldrv = {
196 	&mod_driverops, /* Type of module */
197 	"PCIe to PCI nexus driver",
198 	&pcieb_ops,	/* driver ops */
199 };
200 
201 static struct modlinkage modlinkage = {
202 	MODREV_1,
203 	(void *)&modldrv,
204 	NULL
205 };
206 
207 /*
208  * forward function declarations:
209  */
210 static void	pcieb_uninitchild(dev_info_t *);
211 static int 	pcieb_initchild(dev_info_t *child);
212 static void	pcieb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t);
213 static boolean_t pcieb_is_pcie_device_type(dev_info_t *dip);
214 
215 /* interrupt related declarations */
216 static int	pcieb_msi_supported(dev_info_t *);
217 static int	pcieb_intr_attach(pcieb_devstate_t *pcieb);
218 static int	pcieb_intr_init(pcieb_devstate_t *pcieb_p, int intr_type);
219 static void	pcieb_intr_fini(pcieb_devstate_t *pcieb_p);
220 
221 int
222 _init(void)
223 {
224 	int e;
225 
226 	if ((e = ddi_soft_state_init(&pcieb_state, sizeof (pcieb_devstate_t),
227 	    1)) == 0 && (e = mod_install(&modlinkage)) != 0)
228 		ddi_soft_state_fini(&pcieb_state);
229 	return (e);
230 }
231 
232 int
233 _fini(void)
234 {
235 	int e;
236 
237 	if ((e = mod_remove(&modlinkage)) == 0) {
238 		ddi_soft_state_fini(&pcieb_state);
239 	}
240 	return (e);
241 }
242 
243 int
244 _info(struct modinfo *modinfop)
245 {
246 	return (mod_info(&modlinkage, modinfop));
247 }
248 
249 /*ARGSUSED*/
250 static int
251 pcieb_probe(dev_info_t *devi)
252 {
253 	return (DDI_PROBE_SUCCESS);
254 }
255 
256 static int
257 pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
258 {
259 	int			instance;
260 	char			device_type[8];
261 	pcieb_devstate_t	*pcieb;
262 	pcie_bus_t		*bus_p = PCIE_DIP2UPBUS(devi);
263 	ddi_acc_handle_t	config_handle = bus_p->bus_cfg_hdl;
264 	uint8_t			dev_type = bus_p->bus_dev_type;
265 
266 	switch (cmd) {
267 	case DDI_RESUME:
268 		(void) pcie_pwr_resume(devi);
269 		return (DDI_SUCCESS);
270 
271 	default:
272 		return (DDI_FAILURE);
273 
274 	case DDI_ATTACH:
275 		break;
276 	}
277 
278 	if (!(PCIE_IS_BDG(bus_p))) {
279 		PCIEB_DEBUG(DBG_ATTACH, devi, "This is not a switch or"
280 		" bridge\n");
281 		return (DDI_FAILURE);
282 	}
283 
284 	/*
285 	 * If PCIE_LINKCTL_LINK_DISABLE bit in the PCIe Config
286 	 * Space (PCIe Capability Link Control Register) is set,
287 	 * then do not bind the driver.
288 	 */
289 	if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & PCIE_LINKCTL_LINK_DISABLE)
290 		return (DDI_FAILURE);
291 
292 	/*
293 	 * Allocate and get soft state structure.
294 	 */
295 	instance = ddi_get_instance(devi);
296 	if (ddi_soft_state_zalloc(pcieb_state, instance) != DDI_SUCCESS)
297 		return (DDI_FAILURE);
298 	pcieb = ddi_get_soft_state(pcieb_state, instance);
299 	pcieb->pcieb_dip = devi;
300 	pcieb->pcieb_soft_state = PCIEB_SOFT_STATE_CLOSED;
301 
302 	if ((pcieb_fm_init(pcieb)) != DDI_SUCCESS) {
303 		PCIEB_DEBUG(DBG_ATTACH, devi, "Failed in pcieb_fm_init\n");
304 		goto fail;
305 	}
306 	pcieb->pcieb_init_flags |= PCIEB_INIT_FM;
307 
308 	mutex_init(&pcieb->pcieb_mutex, NULL, MUTEX_DRIVER, NULL);
309 	mutex_init(&pcieb->pcieb_err_mutex, NULL, MUTEX_DRIVER,
310 	    (void *)pcieb->pcieb_fm_ibc);
311 	mutex_init(&pcieb->pcieb_peek_poke_mutex, NULL, MUTEX_DRIVER,
312 	    (void *)pcieb->pcieb_fm_ibc);
313 
314 	/* create special properties for device identification */
315 	pcieb_id_props(pcieb);
316 
317 	/*
318 	 * Power management setup. This also makes sure that switch/bridge
319 	 * is at D0 during attach.
320 	 */
321 	if (pwr_common_setup(devi) != DDI_SUCCESS) {
322 		PCIEB_DEBUG(DBG_PWR, devi, "pwr_common_setup failed\n");
323 		goto fail;
324 	}
325 
326 	if (pcieb_pwr_setup(devi) != DDI_SUCCESS) {
327 		PCIEB_DEBUG(DBG_PWR, devi, "pxb_pwr_setup failed \n");
328 		goto fail;
329 	}
330 
331 	/*
332 	 * Make sure the "device_type" property exists.
333 	 */
334 	if (pcieb_is_pcie_device_type(devi))
335 		(void) strcpy(device_type, "pciex");
336 	else
337 		(void) strcpy(device_type, "pci");
338 
339 	(void) ddi_prop_update_string(DDI_DEV_T_NONE, devi,
340 	    "device_type", device_type);
341 
342 	/*
343 	 * Check whether the "ranges" property is present.
344 	 * Otherwise create the ranges property by reading
345 	 * the configuration registers
346 	 */
347 	if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS,
348 	    "ranges") == 0) {
349 		pcieb_create_ranges_prop(devi, config_handle);
350 	}
351 
352 	if (PCIE_IS_PCI_BDG(bus_p))
353 		pcieb_set_pci_perf_parameters(devi, config_handle);
354 
355 #ifdef PX_PLX
356 	pcieb_attach_plx_workarounds(pcieb);
357 #endif /* PX_PLX */
358 
359 	/* Initialize hotplug */
360 	pcieb->pcieb_hotplug_capable = B_FALSE;
361 
362 	if ((dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) ||
363 	    (dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) ||
364 	    (dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ||
365 	    (dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) {
366 		(void) pcieb_init_hotplug(pcieb);
367 	}
368 
369 	/*
370 	 * Initialize interrupt handlers. Ignore return value.
371 	 */
372 	(void) pcieb_intr_attach(pcieb);
373 
374 	if (pcieb->pcieb_hotplug_capable == B_FALSE) {
375 		/*
376 		 * (for non hotplug bus) this would create ":devctl" minor
377 		 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls
378 		 * to this bus.
379 		 */
380 		if (ddi_create_minor_node(devi, "devctl", S_IFCHR,
381 		    PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR),
382 		    DDI_NT_NEXUS, 0) != DDI_SUCCESS)
383 			goto fail;
384 	}
385 
386 	PCIEB_DEBUG(DBG_ATTACH, devi,
387 	    "pcieb_attach: this nexus %s hotplug slots\n",
388 	    pcieb->pcieb_hotplug_capable == B_TRUE ? "has":"has no");
389 
390 	/* Do any platform specific workarounds needed at this time */
391 	pcieb_plat_attach_workaround(devi);
392 
393 	/*
394 	 * If this is a root port, determine and set the max payload size.
395 	 * Since this will involve scanning the fabric, all error enabling
396 	 * and sw workarounds should be in place before doing this.
397 	 */
398 	if (PCIE_IS_RP(bus_p))
399 		pcie_init_root_port_mps(devi);
400 
401 	ddi_report_dev(devi);
402 	return (DDI_SUCCESS);
403 
404 fail:
405 	(void) pcieb_detach(devi, DDI_DETACH);
406 	return (DDI_FAILURE);
407 }
408 
409 static int
410 pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
411 {
412 	pcieb_devstate_t *pcieb;
413 	int error = DDI_SUCCESS;
414 
415 	switch (cmd) {
416 	case DDI_SUSPEND:
417 		error = pcie_pwr_suspend(devi);
418 		return (error);
419 
420 	case DDI_DETACH:
421 		break;
422 
423 	default:
424 		return (DDI_FAILURE);
425 	}
426 
427 	pcieb = ddi_get_soft_state(pcieb_state, ddi_get_instance(devi));
428 
429 	/* remove interrupt handlers */
430 	pcieb_intr_fini(pcieb);
431 
432 	if (pcieb->pcieb_hotplug_capable == B_TRUE) {
433 		if (pcihp_uninit(devi) == DDI_FAILURE)
434 			error = DDI_FAILURE;
435 
436 		if (pcieb->pcieb_hpc_type == HPC_PCIE)
437 			(void) pciehpc_uninit(devi);
438 		else if (pcieb->pcieb_hpc_type == HPC_SHPC)
439 			(void) pcishpc_uninit(devi);
440 
441 		(void) ndi_prop_remove(DDI_DEV_T_NONE, devi, "hotplug-capable");
442 	} else {
443 		ddi_remove_minor_node(devi, "devctl");
444 	}
445 
446 	(void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type");
447 
448 	(void) ndi_prop_remove(DDI_DEV_T_NONE, pcieb->pcieb_dip,
449 	    "pcie_ce_mask");
450 
451 	if (pcieb->pcieb_init_flags & PCIEB_INIT_FM)
452 		pcieb_fm_fini(pcieb);
453 
454 	pcieb_pwr_teardown(devi);
455 	pwr_common_teardown(devi);
456 
457 	mutex_destroy(&pcieb->pcieb_peek_poke_mutex);
458 	mutex_destroy(&pcieb->pcieb_err_mutex);
459 	mutex_destroy(&pcieb->pcieb_mutex);
460 
461 	/*
462 	 * And finally free the per-pci soft state.
463 	 */
464 	ddi_soft_state_free(pcieb_state, ddi_get_instance(devi));
465 
466 	return (DDI_SUCCESS);
467 }
468 
469 static int
470 pcieb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
471     off_t offset, off_t len, caddr_t *vaddrp)
472 {
473 	dev_info_t *pdip;
474 
475 	pdip = (dev_info_t *)DEVI(dip)->devi_parent;
476 	return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip, rdip, mp,
477 	    offset, len, vaddrp));
478 }
479 
480 static int
481 pcieb_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop,
482     void *arg, void *result)
483 {
484 	pci_regspec_t *drv_regp;
485 	int	reglen;
486 	int	rn;
487 	int	totreg;
488 	pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state,
489 	    ddi_get_instance(dip));
490 	struct detachspec *ds;
491 	struct attachspec *as;
492 
493 	switch (ctlop) {
494 	case DDI_CTLOPS_REPORTDEV:
495 		if (rdip == (dev_info_t *)0)
496 			return (DDI_FAILURE);
497 		cmn_err(CE_CONT, "?PCIE-device: %s@%s, %s%d\n",
498 		    ddi_node_name(rdip), ddi_get_name_addr(rdip),
499 		    ddi_driver_name(rdip),
500 		    ddi_get_instance(rdip));
501 		return (DDI_SUCCESS);
502 
503 	case DDI_CTLOPS_INITCHILD:
504 		return (pcieb_initchild((dev_info_t *)arg));
505 
506 	case DDI_CTLOPS_UNINITCHILD:
507 		pcieb_uninitchild((dev_info_t *)arg);
508 		return (DDI_SUCCESS);
509 
510 	case DDI_CTLOPS_SIDDEV:
511 		return (DDI_SUCCESS);
512 
513 	case DDI_CTLOPS_REGSIZE:
514 	case DDI_CTLOPS_NREGS:
515 		if (rdip == (dev_info_t *)0)
516 			return (DDI_FAILURE);
517 		break;
518 
519 	case DDI_CTLOPS_PEEK:
520 	case DDI_CTLOPS_POKE:
521 		return (pcieb_plat_peekpoke(dip, rdip, ctlop, arg, result));
522 	case DDI_CTLOPS_ATTACH:
523 		if (!pcie_is_child(dip, rdip))
524 			return (DDI_SUCCESS);
525 
526 		as = (struct attachspec *)arg;
527 		switch (as->when) {
528 		case DDI_PRE:
529 			if (as->cmd == DDI_RESUME) {
530 				pcie_clear_errors(rdip);
531 				if (pcieb_plat_ctlops(rdip, ctlop, arg) !=
532 				    DDI_SUCCESS)
533 					return (DDI_FAILURE);
534 			}
535 
536 			if (as->cmd == DDI_ATTACH)
537 				return (pcie_pm_hold(dip));
538 
539 			return (DDI_SUCCESS);
540 
541 		case DDI_POST:
542 			if (as->cmd == DDI_ATTACH &&
543 			    as->result != DDI_SUCCESS) {
544 				/*
545 				 * Attach failed for the child device. The child
546 				 * driver may have made PM calls before the
547 				 * attach failed. pcie_pm_remove_child() should
548 				 * cleanup PM state and holds (if any)
549 				 * associated with the child device.
550 				 */
551 				return (pcie_pm_remove_child(dip, rdip));
552 			}
553 
554 			if (as->result == DDI_SUCCESS) {
555 				pf_init(rdip, (void *)pcieb->pcieb_fm_ibc,
556 				    as->cmd);
557 
558 				(void) pcieb_plat_ctlops(rdip, ctlop, arg);
559 			}
560 
561 			/*
562 			 * For empty hotplug-capable slots, we should explicitly
563 			 * disable the errors, so that we won't panic upon
564 			 * unsupported hotplug messages.
565 			 */
566 			if ((!ddi_prop_exists(DDI_DEV_T_ANY, rdip,
567 			    DDI_PROP_DONTPASS, "hotplug-capable")) ||
568 			    ddi_get_child(rdip)) {
569 				(void) pcie_postattach_child(rdip);
570 				return (DDI_SUCCESS);
571 			}
572 
573 			pcie_disable_errors(rdip);
574 
575 			return (DDI_SUCCESS);
576 		default:
577 			break;
578 		}
579 		return (DDI_SUCCESS);
580 
581 	case DDI_CTLOPS_DETACH:
582 		if (!pcie_is_child(dip, rdip))
583 			return (DDI_SUCCESS);
584 
585 		ds = (struct detachspec *)arg;
586 		switch (ds->when) {
587 		case DDI_PRE:
588 			pf_fini(rdip, ds->cmd);
589 			return (DDI_SUCCESS);
590 
591 		case DDI_POST:
592 			if (pcieb_plat_ctlops(rdip, ctlop, arg) != DDI_SUCCESS)
593 				return (DDI_FAILURE);
594 			if (ds->cmd == DDI_DETACH &&
595 			    ds->result == DDI_SUCCESS) {
596 				return (pcie_pm_remove_child(dip, rdip));
597 			}
598 			return (DDI_SUCCESS);
599 		default:
600 			break;
601 		}
602 		return (DDI_SUCCESS);
603 	default:
604 		return (ddi_ctlops(dip, rdip, ctlop, arg, result));
605 	}
606 
607 	*(int *)result = 0;
608 	if (ddi_getlongprop(DDI_DEV_T_ANY, rdip,
609 	    DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", (caddr_t)&drv_regp,
610 	    &reglen) != DDI_SUCCESS)
611 		return (DDI_FAILURE);
612 
613 	totreg = reglen / sizeof (pci_regspec_t);
614 	if (ctlop == DDI_CTLOPS_NREGS)
615 		*(int *)result = totreg;
616 	else if (ctlop == DDI_CTLOPS_REGSIZE) {
617 		rn = *(int *)arg;
618 		if (rn >= totreg) {
619 			kmem_free(drv_regp, reglen);
620 			return (DDI_FAILURE);
621 		}
622 
623 		*(off_t *)result = drv_regp[rn].pci_size_low |
624 		    ((uint64_t)drv_regp[rn].pci_size_hi << 32);
625 	}
626 
627 	kmem_free(drv_regp, reglen);
628 	return (DDI_SUCCESS);
629 }
630 
631 /*
632  * name_child
633  *
634  * This function is called from init_child to name a node. It is
635  * also passed as a callback for node merging functions.
636  *
637  * return value: DDI_SUCCESS, DDI_FAILURE
638  */
639 static int
640 pcieb_name_child(dev_info_t *child, char *name, int namelen)
641 {
642 	pci_regspec_t *pci_rp;
643 	uint_t slot, func;
644 	char **unit_addr;
645 	uint_t n;
646 
647 	/*
648 	 * For .conf nodes, use unit-address property as name
649 	 */
650 	if (ndi_dev_is_persistent_node(child) == 0) {
651 		if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child,
652 		    DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) !=
653 		    DDI_PROP_SUCCESS) {
654 			cmn_err(CE_WARN,
655 			    "cannot find unit-address in %s.conf",
656 			    ddi_driver_name(child));
657 			return (DDI_FAILURE);
658 		}
659 		if (n != 1 || *unit_addr == NULL || **unit_addr == 0) {
660 			cmn_err(CE_WARN, "unit-address property in %s.conf"
661 			    " not well-formed", ddi_driver_name(child));
662 			ddi_prop_free(unit_addr);
663 			return (DDI_FAILURE);
664 		}
665 		(void) snprintf(name, namelen, "%s", *unit_addr);
666 		ddi_prop_free(unit_addr);
667 		return (DDI_SUCCESS);
668 	}
669 
670 	/*
671 	 * Get the address portion of the node name based on
672 	 * the function and device number.
673 	 */
674 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child,
675 	    DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) {
676 		return (DDI_FAILURE);
677 	}
678 
679 	/* copy the device identifications */
680 	slot = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi);
681 	func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi);
682 
683 	if (func != 0)
684 		(void) snprintf(name, namelen, "%x,%x", slot, func);
685 	else
686 		(void) snprintf(name, namelen, "%x", slot);
687 
688 	ddi_prop_free(pci_rp);
689 	return (DDI_SUCCESS);
690 }
691 
692 static int
693 pcieb_initchild(dev_info_t *child)
694 {
695 	char name[MAXNAMELEN];
696 	int result = DDI_FAILURE;
697 	pcieb_devstate_t *pcieb =
698 	    (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state,
699 	    ddi_get_instance(ddi_get_parent(child)));
700 
701 	/*
702 	 * Name the child
703 	 */
704 	if (pcieb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) {
705 		result = DDI_FAILURE;
706 		goto done;
707 	}
708 	ddi_set_name_addr(child, name);
709 
710 	/*
711 	 * Pseudo nodes indicate a prototype node with per-instance
712 	 * properties to be merged into the real h/w device node.
713 	 * The interpretation of the unit-address is DD[,F]
714 	 * where DD is the device id and F is the function.
715 	 */
716 	if (ndi_dev_is_persistent_node(child) == 0) {
717 		extern int pci_allow_pseudo_children;
718 
719 		/*
720 		 * Try to merge the properties from this prototype
721 		 * node into real h/w nodes.
722 		 */
723 		if (ndi_merge_node(child, pcieb_name_child) != DDI_SUCCESS) {
724 			/*
725 			 * Merged ok - return failure to remove the node.
726 			 */
727 			ddi_set_name_addr(child, NULL);
728 			result = DDI_FAILURE;
729 			goto done;
730 		}
731 
732 		/* workaround for ddivs to run under PCI-E */
733 		if (pci_allow_pseudo_children) {
734 			result = DDI_SUCCESS;
735 			goto done;
736 		}
737 
738 		/*
739 		 * The child was not merged into a h/w node,
740 		 * but there's not much we can do with it other
741 		 * than return failure to cause the node to be removed.
742 		 */
743 		cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged",
744 		    ddi_driver_name(child), ddi_get_name_addr(child),
745 		    ddi_driver_name(child));
746 		ddi_set_name_addr(child, NULL);
747 		result = DDI_NOT_WELL_FORMED;
748 		goto done;
749 	}
750 
751 	/* platform specific initchild */
752 	pcieb_plat_initchild(child);
753 
754 	if (pcie_pm_hold(pcieb->pcieb_dip) != DDI_SUCCESS) {
755 		PCIEB_DEBUG(DBG_PWR, pcieb->pcieb_dip,
756 		    "INITCHILD: px_pm_hold failed\n");
757 		result = DDI_FAILURE;
758 		goto done;
759 	}
760 	/* Any return from here must call pcie_pm_release */
761 
762 	/*
763 	 * If configuration registers were previously saved by
764 	 * child (before it entered D3), then let the child do the
765 	 * restore to set up the config regs as it'll first need to
766 	 * power the device out of D3.
767 	 */
768 	if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
769 	    "config-regs-saved-by-child") == 1) {
770 		PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child),
771 		    "INITCHILD: config regs to be restored by child"
772 		    " for %s@%s\n", ddi_node_name(child),
773 		    ddi_get_name_addr(child));
774 
775 		result = DDI_SUCCESS;
776 		goto cleanup;
777 	}
778 
779 	PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child),
780 	    "INITCHILD: config regs setup for %s@%s\n",
781 	    ddi_node_name(child), ddi_get_name_addr(child));
782 
783 	if (!pcie_init_bus(child) || pcie_initchild(child) != DDI_SUCCESS) {
784 		result = DDI_FAILURE;
785 		goto cleanup;
786 	}
787 
788 #ifdef PX_PLX
789 	if (pcieb_init_plx_workarounds(pcieb, child) == DDI_FAILURE) {
790 		result = DDI_FAILURE;
791 		goto cleanup;
792 	}
793 #endif /* PX_PLX */
794 
795 	result = DDI_SUCCESS;
796 cleanup:
797 	pcie_pm_release(pcieb->pcieb_dip);
798 done:
799 	return (result);
800 }
801 
802 static void
803 pcieb_uninitchild(dev_info_t *dip)
804 {
805 
806 	pcie_uninitchild(dip);
807 
808 	pcieb_plat_uninitchild(dip);
809 
810 	ddi_set_name_addr(dip, NULL);
811 
812 	/*
813 	 * Strip the node to properly convert it back to prototype form
814 	 */
815 	ddi_remove_minor_node(dip, NULL);
816 
817 	ddi_prop_remove_all(dip);
818 }
819 
820 static boolean_t
821 pcieb_is_pcie_device_type(dev_info_t *dip)
822 {
823 	pcie_bus_t	*bus_p = PCIE_DIP2BUS(dip);
824 
825 	if (PCIE_IS_SW(bus_p) || PCIE_IS_RP(bus_p) || PCIE_IS_PCI2PCIE(bus_p))
826 		return (B_TRUE);
827 
828 	return (B_FALSE);
829 }
830 
831 static int
832 pcieb_intr_attach(pcieb_devstate_t *pcieb)
833 {
834 	int			intr_types;
835 	dev_info_t		*dip = pcieb->pcieb_dip;
836 
837 	/* Allow platform specific code to do any initialization first */
838 	pcieb_plat_intr_attach(pcieb);
839 
840 	/*
841 	 * Initialize interrupt handlers.
842 	 * If both MSI and FIXED are supported, try to attach MSI first.
843 	 * If MSI fails for any reason, then try FIXED, but only allow one
844 	 * type to be attached.
845 	 */
846 	if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
847 		PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_supported_types"
848 		    " failed\n");
849 		goto FAIL;
850 	}
851 
852 	if ((intr_types & DDI_INTR_TYPE_MSI) &&
853 	    (pcieb_msi_supported(dip) == DDI_SUCCESS)) {
854 		if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_MSI) == DDI_SUCCESS)
855 			intr_types = DDI_INTR_TYPE_MSI;
856 		else {
857 			PCIEB_DEBUG(DBG_ATTACH, dip, "Unable to attach MSI"
858 			    " handler\n");
859 		}
860 	}
861 
862 	if (intr_types != DDI_INTR_TYPE_MSI) {
863 		/*
864 		 * MSIs are not supported or MSI initialization failed. For Root
865 		 * Ports mark this so error handling might try to fallback to
866 		 * some other mechanism if available (machinecheck etc.).
867 		 */
868 		if (PCIE_IS_RP(PCIE_DIP2UPBUS(dip)))
869 			pcieb->pcieb_no_aer_msi = B_TRUE;
870 	}
871 
872 	if (intr_types & DDI_INTR_TYPE_FIXED) {
873 		if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_FIXED) !=
874 		    DDI_SUCCESS) {
875 			PCIEB_DEBUG(DBG_ATTACH, dip,
876 			    "Unable to attach INTx handler\n");
877 			goto FAIL;
878 		}
879 	}
880 	return (DDI_SUCCESS);
881 
882 FAIL:
883 	return (DDI_FAILURE);
884 }
885 
886 /*
887  * This function initializes internally generated interrupts only.
888  * It does not affect any interrupts generated by downstream devices
889  * or the forwarding of them.
890  *
891  * Enable Device Specific Interrupts or Hotplug features here.
892  * Enabling features may change how many interrupts are requested
893  * by the device.  If features are not enabled first, the
894  * device might not ask for any interrupts.
895  */
896 
897 static int
898 pcieb_intr_init(pcieb_devstate_t *pcieb, int intr_type)
899 {
900 	dev_info_t	*dip = pcieb->pcieb_dip;
901 	int		nintrs, request, count, x;
902 	int		intr_cap = 0;
903 	int		inum = 0;
904 	int		ret, hp_msi_off;
905 	pcie_bus_t	*bus_p = PCIE_DIP2UPBUS(dip);
906 	uint16_t	vendorid = bus_p->bus_dev_ven_id & 0xFFFF;
907 	boolean_t	is_hp = B_FALSE;
908 	boolean_t	is_pme = B_FALSE;
909 
910 	PCIEB_DEBUG(DBG_ATTACH, dip, "pcieb_intr_init: Attaching %s handler\n",
911 	    (intr_type == DDI_INTR_TYPE_MSI) ? "MSI" : "INTx");
912 
913 	request = 0;
914 	if (pcieb->pcieb_hotplug_capable) {
915 		request++;
916 		is_hp = B_TRUE;
917 	}
918 
919 	/*
920 	 * Hotplug and PME share the same MSI vector. If hotplug is not
921 	 * supported check if MSI is needed for PME.
922 	 */
923 	if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p) &&
924 	    (vendorid == NVIDIA_VENDOR_ID)) {
925 		is_pme = B_TRUE;
926 		if (!is_hp)
927 			request++;
928 	}
929 
930 	/*
931 	 * Setup MSI if this device is a Rootport and has AER. Currently no
932 	 * SPARC Root Port supports fabric errors being reported through it.
933 	 */
934 	if (intr_type == DDI_INTR_TYPE_MSI) {
935 		if (PCIE_IS_RP(bus_p) && PCIE_HAS_AER(bus_p))
936 			request++;
937 	}
938 
939 	if (request == 0)
940 		return (DDI_SUCCESS);
941 
942 	/*
943 	 * Get number of supported interrupts.
944 	 *
945 	 * Several Bridges/Switches will not have this property set, resulting
946 	 * in a FAILURE, if the device is not configured in a way that
947 	 * interrupts are needed. (eg. hotplugging)
948 	 */
949 	ret = ddi_intr_get_nintrs(dip, intr_type, &nintrs);
950 	if ((ret != DDI_SUCCESS) || (nintrs == 0)) {
951 		PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_nintrs ret:%d"
952 		    " req:%d\n", ret, nintrs);
953 		return (DDI_FAILURE);
954 	}
955 
956 	PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0x%x: ddi_intr_get_nintrs: nintrs %d",
957 	    " request %d\n", bus_p->bus_bdf, nintrs, request);
958 
959 	if (request > nintrs)
960 		request = nintrs;
961 
962 	/* Allocate an array of interrupt handlers */
963 	pcieb->pcieb_htable_size = sizeof (ddi_intr_handle_t) * request;
964 	pcieb->pcieb_htable = kmem_zalloc(pcieb->pcieb_htable_size,
965 	    KM_SLEEP);
966 	pcieb->pcieb_init_flags |= PCIEB_INIT_HTABLE;
967 
968 	ret = ddi_intr_alloc(dip, pcieb->pcieb_htable, intr_type, inum,
969 	    request, &count, DDI_INTR_ALLOC_NORMAL);
970 	if ((ret != DDI_SUCCESS) || (count == 0)) {
971 		PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_alloc() ret: %d ask: %d"
972 		    " actual: %d\n", ret, request, count);
973 		goto FAIL;
974 	}
975 	pcieb->pcieb_init_flags |= PCIEB_INIT_ALLOC;
976 
977 	/* Save the actual number of interrupts allocated */
978 	pcieb->pcieb_intr_count = count;
979 	if (count < request) {
980 		PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0%x: Requested Intr: %d"
981 		    " Received: %d\n", bus_p->bus_bdf, request, count);
982 	}
983 
984 	/*
985 	 * NVidia (MCP55 and other) chipsets have a errata that if the number
986 	 * of requested MSI intrs is not allocated we have to fall back to INTx.
987 	 */
988 	if (intr_type == DDI_INTR_TYPE_MSI) {
989 		if (PCIE_IS_RP(bus_p) && (vendorid == NVIDIA_VENDOR_ID)) {
990 			if (request != count)
991 				goto FAIL;
992 		}
993 	}
994 
995 	/* Get interrupt priority */
996 	ret = ddi_intr_get_pri(pcieb->pcieb_htable[0],
997 	    &pcieb->pcieb_intr_priority);
998 	if (ret != DDI_SUCCESS) {
999 		PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_pri() ret: %d\n",
1000 		    ret);
1001 		goto FAIL;
1002 	}
1003 
1004 	if (pcieb->pcieb_intr_priority >= LOCK_LEVEL) {
1005 		pcieb->pcieb_intr_priority = LOCK_LEVEL - 1;
1006 		ret = ddi_intr_set_pri(pcieb->pcieb_htable[0],
1007 		    pcieb->pcieb_intr_priority);
1008 		if (ret != DDI_SUCCESS) {
1009 			PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_set_pri() ret:"
1010 			" %d\n", ret);
1011 
1012 			goto FAIL;
1013 		}
1014 	}
1015 
1016 	mutex_init(&pcieb->pcieb_intr_mutex, NULL, MUTEX_DRIVER, NULL);
1017 
1018 	pcieb->pcieb_init_flags |= PCIEB_INIT_MUTEX;
1019 
1020 	for (count = 0; count < pcieb->pcieb_intr_count; count++) {
1021 		ret = ddi_intr_add_handler(pcieb->pcieb_htable[count],
1022 		    pcieb_intr_handler, (caddr_t)pcieb,
1023 		    (caddr_t)(uintptr_t)(inum + count));
1024 
1025 		if (ret != DDI_SUCCESS) {
1026 			PCIEB_DEBUG(DBG_ATTACH, dip, "Cannot add "
1027 			    "interrupt(%d)\n", ret);
1028 			break;
1029 		}
1030 	}
1031 
1032 	/* If unsucessful, remove the added handlers */
1033 	if (ret != DDI_SUCCESS) {
1034 		for (x = 0; x < count; x++) {
1035 			(void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]);
1036 		}
1037 		goto FAIL;
1038 	}
1039 
1040 	pcieb->pcieb_init_flags |= PCIEB_INIT_HANDLER;
1041 
1042 	(void) ddi_intr_get_cap(pcieb->pcieb_htable[0], &intr_cap);
1043 
1044 	/*
1045 	 * Get this intr lock because we are not quite ready to handle
1046 	 * interrupts immediately after enabling it. The MSI multi register
1047 	 * gets programmed in ddi_intr_enable after which we need to get the
1048 	 * MSI offsets for Hotplug/AER.
1049 	 */
1050 	mutex_enter(&pcieb->pcieb_intr_mutex);
1051 
1052 	if (intr_cap & DDI_INTR_FLAG_BLOCK) {
1053 		(void) ddi_intr_block_enable(pcieb->pcieb_htable,
1054 		    pcieb->pcieb_intr_count);
1055 		pcieb->pcieb_init_flags |= PCIEB_INIT_BLOCK;
1056 	} else {
1057 		for (count = 0; count < pcieb->pcieb_intr_count; count++) {
1058 			(void) ddi_intr_enable(pcieb->pcieb_htable[count]);
1059 		}
1060 	}
1061 	pcieb->pcieb_init_flags |= PCIEB_INIT_ENABLE;
1062 
1063 	/* Save the interrupt type */
1064 	pcieb->pcieb_intr_type = intr_type;
1065 
1066 	/* Get the MSI offset for hotplug/PME from the PCIe cap reg */
1067 	if (intr_type == DDI_INTR_TYPE_MSI) {
1068 		hp_msi_off = PCI_CAP_GET16(bus_p->bus_cfg_hdl, NULL,
1069 		    bus_p->bus_pcie_off, PCIE_PCIECAP) &
1070 		    PCIE_PCIECAP_INT_MSG_NUM;
1071 
1072 		if (hp_msi_off >= count) {
1073 			PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in PCIe "
1074 			    "cap > max allocated %d\n", hp_msi_off, count);
1075 			mutex_exit(&pcieb->pcieb_intr_mutex);
1076 			goto FAIL;
1077 		}
1078 
1079 		if (is_hp)
1080 			pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_HP;
1081 
1082 		if (is_pme)
1083 			pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_PME;
1084 	} else {
1085 		/* INTx handles only Hotplug interrupts */
1086 		if (is_hp)
1087 			pcieb->pcieb_isr_tab[0] |= PCIEB_INTR_SRC_HP;
1088 	}
1089 
1090 
1091 	/*
1092 	 * Get the MSI offset for errors from the AER Root Error status
1093 	 * register.
1094 	 */
1095 	if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p)) {
1096 		if (PCIE_HAS_AER(bus_p)) {
1097 			int aer_msi_off;
1098 			aer_msi_off = (PCI_XCAP_GET32(bus_p->bus_cfg_hdl, NULL,
1099 			    bus_p->bus_aer_off, PCIE_AER_RE_STS) >>
1100 			    PCIE_AER_RE_STS_MSG_NUM_SHIFT) &
1101 			    PCIE_AER_RE_STS_MSG_NUM_MASK;
1102 
1103 			if (aer_msi_off >= count) {
1104 				PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in"
1105 				    " AER cap > max allocated %d\n",
1106 				    aer_msi_off, count);
1107 				mutex_exit(&pcieb->pcieb_intr_mutex);
1108 				goto FAIL;
1109 			}
1110 			pcieb->pcieb_isr_tab[aer_msi_off] |= PCIEB_INTR_SRC_AER;
1111 		} else {
1112 			/*
1113 			 * This RP does not have AER. Fallback to the
1114 			 * SERR+Machinecheck approach if available.
1115 			 */
1116 			pcieb->pcieb_no_aer_msi = B_TRUE;
1117 		}
1118 	}
1119 
1120 	mutex_exit(&pcieb->pcieb_intr_mutex);
1121 	return (DDI_SUCCESS);
1122 
1123 FAIL:
1124 	pcieb_intr_fini(pcieb);
1125 	return (DDI_FAILURE);
1126 }
1127 
1128 static void
1129 pcieb_intr_fini(pcieb_devstate_t *pcieb)
1130 {
1131 	int x;
1132 	int count = pcieb->pcieb_intr_count;
1133 	int flags = pcieb->pcieb_init_flags;
1134 
1135 	if ((flags & PCIEB_INIT_ENABLE) &&
1136 	    (flags & PCIEB_INIT_BLOCK)) {
1137 		(void) ddi_intr_block_disable(pcieb->pcieb_htable, count);
1138 		flags &= ~(PCIEB_INIT_ENABLE |
1139 		    PCIEB_INIT_BLOCK);
1140 	}
1141 
1142 	if (flags & PCIEB_INIT_MUTEX)
1143 		mutex_destroy(&pcieb->pcieb_intr_mutex);
1144 
1145 	for (x = 0; x < count; x++) {
1146 		if (flags & PCIEB_INIT_ENABLE)
1147 			(void) ddi_intr_disable(pcieb->pcieb_htable[x]);
1148 
1149 		if (flags & PCIEB_INIT_HANDLER)
1150 			(void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]);
1151 
1152 		if (flags & PCIEB_INIT_ALLOC)
1153 			(void) ddi_intr_free(pcieb->pcieb_htable[x]);
1154 	}
1155 
1156 	flags &= ~(PCIEB_INIT_ENABLE | PCIEB_INIT_HANDLER | PCIEB_INIT_ALLOC |
1157 	    PCIEB_INIT_MUTEX);
1158 
1159 	if (flags & PCIEB_INIT_HTABLE)
1160 		kmem_free(pcieb->pcieb_htable, pcieb->pcieb_htable_size);
1161 
1162 	flags &= ~PCIEB_INIT_HTABLE;
1163 
1164 	pcieb->pcieb_init_flags &= flags;
1165 }
1166 
1167 /*
1168  * Checks if this device needs MSIs enabled or not.
1169  */
1170 /*ARGSUSED*/
1171 static int
1172 pcieb_msi_supported(dev_info_t *dip)
1173 {
1174 	return ((pcieb_enable_msi && pcieb_plat_msi_supported(dip)) ?
1175 	    DDI_SUCCESS: DDI_FAILURE);
1176 }
1177 
1178 /*ARGSUSED*/
1179 static int
1180 pcieb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
1181     ddi_iblock_cookie_t *ibc)
1182 {
1183 	pcieb_devstate_t  *pcieb = ddi_get_soft_state(pcieb_state,
1184 	    ddi_get_instance(dip));
1185 
1186 	ASSERT(ibc != NULL);
1187 	*ibc = pcieb->pcieb_fm_ibc;
1188 
1189 	return (DEVI(dip)->devi_fmhdl->fh_cap | DDI_FM_ACCCHK_CAPABLE |
1190 	    DDI_FM_DMACHK_CAPABLE);
1191 }
1192 
1193 static int
1194 pcieb_fm_init(pcieb_devstate_t *pcieb_p)
1195 {
1196 	dev_info_t	*dip = pcieb_p->pcieb_dip;
1197 	int		fm_cap = DDI_FM_EREPORT_CAPABLE;
1198 
1199 	/*
1200 	 * Request our capability level and get our parents capability
1201 	 * and ibc.
1202 	 */
1203 	ddi_fm_init(dip, &fm_cap, &pcieb_p->pcieb_fm_ibc);
1204 
1205 	return (DDI_SUCCESS);
1206 }
1207 
1208 /*
1209  * Breakdown our FMA resources
1210  */
1211 static void
1212 pcieb_fm_fini(pcieb_devstate_t *pcieb_p)
1213 {
1214 	/*
1215 	 * Clean up allocated fm structures
1216 	 */
1217 	ddi_fm_fini(pcieb_p->pcieb_dip);
1218 }
1219 
1220 static int
1221 pcieb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
1222 {
1223 	pcieb_devstate_t *pcieb_p;
1224 	minor_t		minor = getminor(*devp);
1225 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1226 
1227 	/*
1228 	 * Make sure the open is for the right file type.
1229 	 */
1230 	if (otyp != OTYP_CHR)
1231 		return (EINVAL);
1232 
1233 	/*
1234 	 * Get the soft state structure for the device.
1235 	 */
1236 	pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state,
1237 	    instance);
1238 
1239 	if (pcieb_p == NULL)
1240 		return (ENXIO);
1241 
1242 	if (pcieb_p->pcieb_hotplug_capable == B_TRUE)
1243 		return ((pcihp_get_cb_ops())->cb_open(devp, flags,
1244 		    otyp, credp));
1245 
1246 	/*
1247 	 * Handle the open by tracking the device state.
1248 	 */
1249 	mutex_enter(&pcieb_p->pcieb_mutex);
1250 	if (flags & FEXCL) {
1251 		if (pcieb_p->pcieb_soft_state != PCIEB_SOFT_STATE_CLOSED) {
1252 			mutex_exit(&pcieb_p->pcieb_mutex);
1253 			return (EBUSY);
1254 		}
1255 		pcieb_p->pcieb_soft_state = PCIEB_SOFT_STATE_OPEN_EXCL;
1256 	} else {
1257 		if (pcieb_p->pcieb_soft_state == PCIEB_SOFT_STATE_OPEN_EXCL) {
1258 			mutex_exit(&pcieb_p->pcieb_mutex);
1259 			return (EBUSY);
1260 		}
1261 		pcieb_p->pcieb_soft_state = PCIEB_SOFT_STATE_OPEN;
1262 	}
1263 	mutex_exit(&pcieb_p->pcieb_mutex);
1264 	return (0);
1265 }
1266 
1267 static int
1268 pcieb_close(dev_t dev, int flags, int otyp, cred_t *credp)
1269 {
1270 	pcieb_devstate_t *pcieb_p;
1271 	minor_t		minor = getminor(dev);
1272 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1273 
1274 	if (otyp != OTYP_CHR)
1275 		return (EINVAL);
1276 
1277 	pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state,
1278 	    instance);
1279 
1280 	if (pcieb_p == NULL)
1281 		return (ENXIO);
1282 
1283 	if (pcieb_p->pcieb_hotplug_capable == B_TRUE)
1284 		return ((pcihp_get_cb_ops())->cb_close(dev, flags,
1285 		    otyp, credp));
1286 
1287 	mutex_enter(&pcieb_p->pcieb_mutex);
1288 	pcieb_p->pcieb_soft_state = PCIEB_SOFT_STATE_CLOSED;
1289 	mutex_exit(&pcieb_p->pcieb_mutex);
1290 	return (0);
1291 }
1292 
1293 static int
1294 pcieb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
1295 	int *rvalp)
1296 {
1297 	pcieb_devstate_t *pcieb_p;
1298 	dev_info_t *self;
1299 	struct devctl_iocdata *dcp;
1300 	uint_t bus_state;
1301 	int rv = 0;
1302 	minor_t		minor = getminor(dev);
1303 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1304 
1305 	pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state,
1306 	    instance);
1307 
1308 	if (pcieb_p == NULL)
1309 		return (ENXIO);
1310 
1311 	self = pcieb_p->pcieb_dip;
1312 	if (pcieb_p->pcieb_hotplug_capable == B_TRUE) {
1313 		rv = ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd,
1314 		    arg, mode, credp, rvalp));
1315 
1316 		pcieb_plat_ioctl_hotplug(self, rv, cmd);
1317 		return (rv);
1318 	}
1319 
1320 	/*
1321 	 * We can use the generic implementation for these ioctls
1322 	 */
1323 	switch (cmd) {
1324 	case DEVCTL_DEVICE_GETSTATE:
1325 	case DEVCTL_DEVICE_ONLINE:
1326 	case DEVCTL_DEVICE_OFFLINE:
1327 	case DEVCTL_BUS_GETSTATE:
1328 		return (ndi_devctl_ioctl(self, cmd, arg, mode, 0));
1329 	}
1330 
1331 	/*
1332 	 * read devctl ioctl data
1333 	 */
1334 	if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS)
1335 		return (EFAULT);
1336 
1337 	switch (cmd) {
1338 
1339 	case DEVCTL_DEVICE_RESET:
1340 		rv = ENOTSUP;
1341 		break;
1342 
1343 	case DEVCTL_BUS_QUIESCE:
1344 		if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS)
1345 			if (bus_state == BUS_QUIESCED)
1346 				break;
1347 		(void) ndi_set_bus_state(self, BUS_QUIESCED);
1348 		break;
1349 
1350 	case DEVCTL_BUS_UNQUIESCE:
1351 		if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS)
1352 			if (bus_state == BUS_ACTIVE)
1353 				break;
1354 		(void) ndi_set_bus_state(self, BUS_ACTIVE);
1355 		break;
1356 
1357 	case DEVCTL_BUS_RESET:
1358 		rv = ENOTSUP;
1359 		break;
1360 
1361 	case DEVCTL_BUS_RESETALL:
1362 		rv = ENOTSUP;
1363 		break;
1364 
1365 	default:
1366 		rv = ENOTTY;
1367 	}
1368 
1369 	ndi_dc_freehdl(dcp);
1370 	return (rv);
1371 }
1372 
1373 static int
1374 pcieb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op,
1375 	int flags, char *name, caddr_t valuep, int *lengthp)
1376 {
1377 	pcieb_devstate_t *pcieb_p;
1378 	minor_t		minor = getminor(dev);
1379 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1380 
1381 	pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state,
1382 	    instance);
1383 
1384 	if (pcieb_p == NULL)
1385 		return (ENXIO);
1386 
1387 	if (pcieb_p->pcieb_hotplug_capable == B_TRUE)
1388 		return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op,
1389 		    flags, name, valuep, lengthp));
1390 
1391 	return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp));
1392 }
1393 
1394 /*ARGSUSED*/
1395 static int
1396 pcieb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
1397 {
1398 	pcieb_devstate_t *pcieb_p;	/* per pcieb state pointer */
1399 	minor_t		minor = getminor((dev_t)arg);
1400 	int		instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor);
1401 
1402 	pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state,
1403 	    instance);
1404 
1405 	switch (infocmd) {
1406 	default:
1407 		return (DDI_FAILURE);
1408 
1409 	case DDI_INFO_DEVT2INSTANCE:
1410 		*result = (void *)(intptr_t)instance;
1411 		return (DDI_SUCCESS);
1412 
1413 	case DDI_INFO_DEVT2DEVINFO:
1414 		if (pcieb_p == NULL)
1415 			return (DDI_FAILURE);
1416 		*result = (void *)pcieb_p->pcieb_dip;
1417 		return (DDI_SUCCESS);
1418 	}
1419 }
1420 
1421 /*
1422  * Common interrupt handler for hotplug, PME and errors.
1423  */
1424 static uint_t
1425 pcieb_intr_handler(caddr_t arg1, caddr_t arg2)
1426 {
1427 	pcieb_devstate_t *pcieb_p = (pcieb_devstate_t *)arg1;
1428 	dev_info_t	*dip = pcieb_p->pcieb_dip;
1429 	ddi_fm_error_t	derr;
1430 	int		sts = 0;
1431 	int		ret = DDI_INTR_UNCLAIMED;
1432 	int		isrc;
1433 
1434 	if (!(pcieb_p->pcieb_init_flags & PCIEB_INIT_ENABLE))
1435 		goto FAIL;
1436 
1437 	mutex_enter(&pcieb_p->pcieb_intr_mutex);
1438 	isrc = pcieb_p->pcieb_isr_tab[(int)(uintptr_t)arg2];
1439 	mutex_exit(&pcieb_p->pcieb_intr_mutex);
1440 
1441 	PCIEB_DEBUG(DBG_INTR, dip, "Received intr number %d\n",
1442 	    (int)(uintptr_t)arg2);
1443 
1444 	if (isrc == PCIEB_INTR_SRC_UNKNOWN)
1445 		goto FAIL;
1446 
1447 	if (isrc & PCIEB_INTR_SRC_HP) {
1448 		if (pcieb_p->pcieb_hpc_type == HPC_PCIE)
1449 			ret = pciehpc_intr(dip);
1450 		else if (pcieb_p->pcieb_hpc_type == HPC_SHPC)
1451 			ret = pcishpc_intr(dip);
1452 	}
1453 
1454 	if (isrc & PCIEB_INTR_SRC_PME)
1455 		ret = DDI_INTR_CLAIMED;
1456 
1457 	/* AER Error */
1458 	if (isrc & PCIEB_INTR_SRC_AER) {
1459 		/*
1460 		 *  If MSI is shared with PME/hotplug then check Root Error
1461 		 *  Status Reg before claiming it. For now it's ok since
1462 		 *  we know we get 2 MSIs.
1463 		 */
1464 		ret = DDI_INTR_CLAIMED;
1465 		bzero(&derr, sizeof (ddi_fm_error_t));
1466 		derr.fme_version = DDI_FME_VERSION;
1467 		mutex_enter(&pcieb_p->pcieb_peek_poke_mutex);
1468 		mutex_enter(&pcieb_p->pcieb_err_mutex);
1469 
1470 		if ((DEVI(dip)->devi_fmhdl->fh_cap) & DDI_FM_EREPORT_CAPABLE)
1471 			sts = pf_scan_fabric(dip, &derr, NULL);
1472 
1473 		mutex_exit(&pcieb_p->pcieb_err_mutex);
1474 		mutex_exit(&pcieb_p->pcieb_peek_poke_mutex);
1475 		if (pcieb_die & sts)
1476 			fm_panic("%s-%d: PCI(-X) Express Fatal Error. (0x%x)",
1477 			    ddi_driver_name(dip), ddi_get_instance(dip), sts);
1478 	}
1479 FAIL:
1480 	return (ret);
1481 }
1482 
1483 /*
1484  * Some PCI-X to PCI-E bridges do not support full 64-bit addressing on the
1485  * PCI-X side of the bridge.  We build a special version of this driver for
1486  * those bridges, which uses PCIEB_ADDR_LIMIT_LO and/or PCIEB_ADDR_LIMIT_HI
1487  * to define the range of values which the chip can handle.  The code below
1488  * then clamps the DMA address range supplied by the driver, preventing the
1489  * PCI-E nexus driver from allocating any memory the bridge can't deal
1490  * with.
1491  */
1492 static int
1493 pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
1494 	ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg,
1495 	ddi_dma_handle_t *handlep)
1496 {
1497 	int		ret;
1498 #ifdef	BCM_SW_WORKAROUNDS
1499 	uint64_t	lim;
1500 
1501 	/*
1502 	 * If the leaf device's limits are outside than what the Broadcom
1503 	 * bridge can handle, we need to clip the values passed up the chain.
1504 	 */
1505 	lim = attr_p->dma_attr_addr_lo;
1506 	attr_p->dma_attr_addr_lo = MAX(lim, PCIEB_ADDR_LIMIT_LO);
1507 
1508 	lim = attr_p->dma_attr_addr_hi;
1509 	attr_p->dma_attr_addr_hi = MIN(lim, PCIEB_ADDR_LIMIT_HI);
1510 
1511 #endif	/* BCM_SW_WORKAROUNDS */
1512 
1513 	/*
1514 	 * This is a software workaround to fix the Broadcom 5714/5715 PCIe-PCI
1515 	 * bridge prefetch bug. Intercept the DMA alloc handle request and set
1516 	 * PX_DMAI_FLAGS_MAP_BUFZONE flag in the handle. If this flag is set,
1517 	 * the px nexus driver will allocate an extra page & make it valid one,
1518 	 * for any DVMA request that comes from any of the Broadcom bridge child
1519 	 * devices.
1520 	 */
1521 	if ((ret = ddi_dma_allochdl(dip, rdip, attr_p, waitfp, arg,
1522 	    handlep)) == DDI_SUCCESS) {
1523 		ddi_dma_impl_t	*mp = (ddi_dma_impl_t *)*handlep;
1524 #ifdef	BCM_SW_WORKAROUNDS
1525 		mp->dmai_inuse |= PX_DMAI_FLAGS_MAP_BUFZONE;
1526 #endif	/* BCM_SW_WORKAROUNDS */
1527 		/*
1528 		 * For a given rdip, update mp->dmai_bdf with the bdf value
1529 		 * of pcieb's immediate child or secondary bus-id of the
1530 		 * PCIe2PCI bridge.
1531 		 */
1532 		mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip);
1533 	}
1534 
1535 	return (ret);
1536 }
1537 
1538 /*
1539  * FDVMA feature is not supported for any child device of Broadcom 5714/5715
1540  * PCIe-PCI bridge due to prefetch bug. Return failure immediately, so that
1541  * these drivers will switch to regular DVMA path.
1542  */
1543 /*ARGSUSED*/
1544 static int
1545 pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
1546 	enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
1547 	uint_t cache_flags)
1548 {
1549 	int	ret;
1550 
1551 #ifdef	BCM_SW_WORKAROUNDS
1552 	if (cmd == DDI_DMA_RESERVE)
1553 		return (DDI_FAILURE);
1554 #endif	/* BCM_SW_WORKAROUNDS */
1555 
1556 	if (((ret = ddi_dma_mctl(dip, rdip, handle, cmd, offp, lenp, objp,
1557 	    cache_flags)) == DDI_SUCCESS) && (cmd == DDI_DMA_RESERVE)) {
1558 		ddi_dma_impl_t	*mp = (ddi_dma_impl_t *)*objp;
1559 
1560 		/*
1561 		 * For a given rdip, update mp->dmai_bdf with the bdf value
1562 		 * of pcieb's immediate child or secondary bus-id of the
1563 		 * PCIe2PCI bridge.
1564 		 */
1565 		mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip);
1566 	}
1567 
1568 	return (ret);
1569 }
1570 
1571 static int
1572 pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
1573     ddi_intr_handle_impl_t *hdlp, void *result)
1574 {
1575 	return (pcieb_plat_intr_ops(dip, rdip, intr_op, hdlp, result));
1576 
1577 }
1578 
1579 /*ARGSUSED*/
1580 static int pcieb_pciehpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle)
1581 {
1582 	uint16_t cap_ptr;
1583 
1584 	if ((PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_E, &cap_ptr)) !=
1585 	    DDI_FAILURE) {
1586 		uint16_t slotimpl = PCI_CAP_GET16(config_handle, NULL, cap_ptr,
1587 		    PCIE_PCIECAP) & PCIE_PCIECAP_SLOT_IMPL;
1588 		if (slotimpl)
1589 			if (PCI_CAP_GET32(config_handle, NULL, cap_ptr,
1590 			    PCIE_SLOTCAP) & PCIE_SLOTCAP_HP_CAPABLE)
1591 				return (DDI_SUCCESS);
1592 	}
1593 
1594 	return (DDI_FAILURE);
1595 }
1596 
1597 static int pcieb_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle)
1598 {
1599 	return (pcieb_plat_pcishpc_probe(dip, config_handle));
1600 }
1601 
1602 /*
1603  * Initialize hotplug framework if we are hotpluggable.
1604  * Sets flag in the soft state if Hot Plug is supported and initialized
1605  * properly.
1606  */
1607 /*ARGSUSED*/
1608 static int
1609 pcieb_init_hotplug(pcieb_devstate_t *pcieb)
1610 {
1611 	int rv = DDI_FAILURE;
1612 	pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip);
1613 	ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl;
1614 	uint8_t dev_type = bus_p->bus_dev_type;
1615 
1616 #ifdef PX_PLX
1617 	uint16_t vid = bus_p->bus_dev_ven_id & 0xFFFF;
1618 	uint16_t did = bus_p->bus_dev_ven_id >> 16;
1619 	if ((vid == PXB_VENDOR_PLX) && (did == PXB_DEVICE_PLX_8532) &&
1620 	    (bus_p->bus_rev_id <= PXB_DEVICE_PLX_AA_REV))
1621 		return (DDI_SUCCESS);
1622 #endif /* PX_PLX */
1623 
1624 	if (((dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) ||
1625 	    (dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE) ||
1626 	    (dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT)) &&
1627 	    (pcieb_pciehpc_probe(pcieb->pcieb_dip,
1628 	    config_handle) == DDI_SUCCESS)) {
1629 		pcieb->pcieb_hpc_type = HPC_PCIE;
1630 	} else if ((dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) &&
1631 	    (pcieb_pcishpc_probe(pcieb->pcieb_dip,
1632 	    config_handle) == DDI_SUCCESS)) {
1633 		pcieb->pcieb_hpc_type = HPC_SHPC;
1634 	} else {
1635 		pcieb->pcieb_hpc_type = HPC_NONE;
1636 		return (DDI_SUCCESS);
1637 	}
1638 
1639 	pcieb->pcieb_hotplug_capable = B_TRUE;
1640 
1641 	if (pcieb->pcieb_hpc_type == HPC_PCIE)
1642 		rv = pciehpc_init(pcieb->pcieb_dip, NULL);
1643 	else if (pcieb->pcieb_hpc_type == HPC_SHPC)
1644 		rv = pcishpc_init(pcieb->pcieb_dip);
1645 
1646 	if (rv != DDI_SUCCESS)
1647 		goto fail;
1648 
1649 	if (pcihp_init(pcieb->pcieb_dip) != DDI_SUCCESS) {
1650 		if (pcieb->pcieb_hpc_type == HPC_PCIE)
1651 			(void) pciehpc_uninit(pcieb->pcieb_dip);
1652 		else if (pcieb->pcieb_hpc_type == HPC_SHPC)
1653 			(void) pcishpc_uninit(pcieb->pcieb_dip);
1654 
1655 		goto fail;
1656 	}
1657 
1658 	(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip,
1659 	    "hotplug-capable");
1660 
1661 	return (DDI_SUCCESS);
1662 
1663 fail:
1664 	pcieb->pcieb_hpc_type = HPC_NONE;
1665 	pcieb->pcieb_hotplug_capable = B_FALSE;
1666 	PCIEB_DEBUG(DBG_ATTACH, pcieb->pcieb_dip, "Failed setting hotplug"
1667 	    " framework\n");
1668 
1669 	return (DDI_FAILURE);
1670 }
1671 
1672 /*
1673  * Power management related initialization specific to pcieb.
1674  * Called by pcieb_attach()
1675  */
1676 static int
1677 pcieb_pwr_setup(dev_info_t *dip)
1678 {
1679 	char *comp_array[5];
1680 	int i;
1681 	ddi_acc_handle_t conf_hdl;
1682 	uint16_t pmcap, cap_ptr;
1683 	pcie_pwr_t *pwr_p;
1684 
1685 	/* Some platforms/devices may choose to disable PM */
1686 	if (pcieb_plat_pwr_disable(dip)) {
1687 		(void) pcieb_pwr_disable(dip);
1688 		return (DDI_SUCCESS);
1689 	}
1690 
1691 	ASSERT(PCIE_PMINFO(dip));
1692 	pwr_p = PCIE_NEXUS_PMINFO(dip);
1693 	ASSERT(pwr_p);
1694 
1695 	/* Code taken from pci_pci driver */
1696 	if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) {
1697 		PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: pci_config_setup "
1698 		    "failed\n");
1699 		return (DDI_FAILURE);
1700 	}
1701 	conf_hdl = pwr_p->pwr_conf_hdl;
1702 
1703 	/*
1704 	 * Walk the capabilities searching for a PM entry.
1705 	 */
1706 	if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &cap_ptr)) ==
1707 	    DDI_FAILURE) {
1708 		PCIEB_DEBUG(DBG_PWR, dip, "switch/bridge does not support PM. "
1709 		    " PCI PM data structure not found in config header\n");
1710 		pci_config_teardown(&conf_hdl);
1711 		return (DDI_SUCCESS);
1712 	}
1713 	/*
1714 	 * Save offset to pmcsr for future references.
1715 	 */
1716 	pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR;
1717 	pmcap = PCI_CAP_GET16(conf_hdl, NULL, cap_ptr, PCI_PMCAP);
1718 	if (pmcap & PCI_PMCAP_D1) {
1719 		PCIEB_DEBUG(DBG_PWR, dip, "D1 state supported\n");
1720 		pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1;
1721 	}
1722 	if (pmcap & PCI_PMCAP_D2) {
1723 		PCIEB_DEBUG(DBG_PWR, dip, "D2 state supported\n");
1724 		pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2;
1725 	}
1726 
1727 	i = 0;
1728 	comp_array[i++] = "NAME=PCIe switch/bridge PM";
1729 	comp_array[i++] = "0=Power Off (D3)";
1730 	if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D2)
1731 		comp_array[i++] = "1=D2";
1732 	if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D1)
1733 		comp_array[i++] = "2=D1";
1734 	comp_array[i++] = "3=Full Power D0";
1735 
1736 	/*
1737 	 * Create pm-components property, if it does not exist already.
1738 	 */
1739 	if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip,
1740 	    "pm-components", comp_array, i) != DDI_PROP_SUCCESS) {
1741 		PCIEB_DEBUG(DBG_PWR, dip, "could not create pm-components "
1742 		    " prop\n");
1743 		pci_config_teardown(&conf_hdl);
1744 		return (DDI_FAILURE);
1745 	}
1746 	return (pcieb_pwr_init_and_raise(dip, pwr_p));
1747 }
1748 
1749 /*
1750  * undo whatever is done in pcieb_pwr_setup. called by pcieb_detach()
1751  */
1752 static void
1753 pcieb_pwr_teardown(dev_info_t *dip)
1754 {
1755 	pcie_pwr_t	*pwr_p;
1756 
1757 	if (!PCIE_PMINFO(dip) || !(pwr_p = PCIE_NEXUS_PMINFO(dip)))
1758 		return;
1759 
1760 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components");
1761 	if (pwr_p->pwr_conf_hdl)
1762 		pci_config_teardown(&pwr_p->pwr_conf_hdl);
1763 }
1764 
1765 /*
1766  * Initializes the power level and raise the power to D0, if it is
1767  * not at D0.
1768  */
1769 static int
1770 pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p)
1771 {
1772 	uint16_t pmcsr;
1773 	int ret = DDI_SUCCESS;
1774 
1775 	/*
1776 	 * Intialize our power level from PMCSR. The common code initializes
1777 	 * this to UNKNOWN. There is no guarantee that we will be at full
1778 	 * power at attach. If we are not at D0, raise the power.
1779 	 */
1780 	pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, pwr_p->pwr_pmcsr_offset);
1781 	pmcsr &= PCI_PMCSR_STATE_MASK;
1782 	switch (pmcsr) {
1783 	case PCI_PMCSR_D0:
1784 		pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1785 		break;
1786 
1787 	case PCI_PMCSR_D1:
1788 		pwr_p->pwr_func_lvl = PM_LEVEL_D1;
1789 		break;
1790 
1791 	case PCI_PMCSR_D2:
1792 		pwr_p->pwr_func_lvl = PM_LEVEL_D2;
1793 		break;
1794 
1795 	case PCI_PMCSR_D3HOT:
1796 		pwr_p->pwr_func_lvl = PM_LEVEL_D3;
1797 		break;
1798 
1799 	default:
1800 		break;
1801 	}
1802 
1803 	/* Raise the power to D0. */
1804 	if (pwr_p->pwr_func_lvl != PM_LEVEL_D0 &&
1805 	    ((ret = pm_raise_power(dip, 0, PM_LEVEL_D0)) != DDI_SUCCESS)) {
1806 		/*
1807 		 * Read PMCSR again. If it is at D0, ignore the return
1808 		 * value from pm_raise_power.
1809 		 */
1810 		pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl,
1811 		    pwr_p->pwr_pmcsr_offset);
1812 		if ((pmcsr & PCI_PMCSR_STATE_MASK) == PCI_PMCSR_D0)
1813 			ret = DDI_SUCCESS;
1814 		else {
1815 			PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: could not "
1816 			    "raise power to D0 \n");
1817 		}
1818 	}
1819 	if (ret == DDI_SUCCESS)
1820 		pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1821 	return (ret);
1822 }
1823 
1824 /*
1825  * Disable PM for x86 and PLX 8532 switch.
1826  * For PLX Transitioning one port on this switch to low power causes links
1827  * on other ports on the same station to die. Due to PLX erratum #34, we
1828  * can't allow the downstream device go to non-D0 state.
1829  */
1830 static int
1831 pcieb_pwr_disable(dev_info_t *dip)
1832 {
1833 	pcie_pwr_t *pwr_p;
1834 
1835 	ASSERT(PCIE_PMINFO(dip));
1836 	pwr_p = PCIE_NEXUS_PMINFO(dip);
1837 	ASSERT(pwr_p);
1838 	PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_disable: disabling PM\n");
1839 	pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1840 	pwr_p->pwr_flags = PCIE_NO_CHILD_PM;
1841 	return (DDI_SUCCESS);
1842 }
1843 
1844 #ifdef DEBUG
1845 int pcieb_dbg_intr_print = 0;
1846 void
1847 pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...)
1848 {
1849 	va_list ap;
1850 
1851 	if (!pcieb_dbg_print)
1852 		return;
1853 
1854 	if (dip)
1855 		prom_printf("%s(%d): %s", ddi_driver_name(dip),
1856 		    ddi_get_instance(dip), pcieb_debug_sym[bit]);
1857 
1858 	va_start(ap, fmt);
1859 	if (servicing_interrupt()) {
1860 		if (pcieb_dbg_intr_print)
1861 			prom_vprintf(fmt, ap);
1862 	} else {
1863 		prom_vprintf(fmt, ap);
1864 	}
1865 
1866 	va_end(ap);
1867 }
1868 #endif
1869 
1870 static void
1871 pcieb_id_props(pcieb_devstate_t *pcieb)
1872 {
1873 	uint64_t serialid = 0;	/* 40b field of EUI-64 serial no. register */
1874 	uint16_t cap_ptr;
1875 	uint8_t fic = 0;	/* 1 = first in chassis device */
1876 	pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip);
1877 	ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl;
1878 
1879 	/*
1880 	 * Identify first in chassis.  In the special case of a Sun branded
1881 	 * PLX device, it obviously is first in chassis.  Otherwise, in the
1882 	 * general case, look for an Expansion Slot Register and check its
1883 	 * first-in-chassis bit.
1884 	 */
1885 #ifdef	PX_PLX
1886 	uint16_t vendor_id = bus_p->bus_dev_ven_id & 0xFFFF;
1887 	uint16_t device_id = bus_p->bus_dev_ven_id >> 16;
1888 	if ((vendor_id == PXB_VENDOR_SUN) &&
1889 	    ((device_id == PXB_DEVICE_PLX_PCIX) ||
1890 	    (device_id == PXB_DEVICE_PLX_PCIE))) {
1891 		fic = 1;
1892 	}
1893 #endif	/* PX_PLX */
1894 	if ((fic == 0) && ((PCI_CAP_LOCATE(config_handle,
1895 	    PCI_CAP_ID_SLOT_ID, &cap_ptr)) != DDI_FAILURE)) {
1896 		uint8_t esr = PCI_CAP_GET8(config_handle, NULL,
1897 		    cap_ptr, PCI_CAP_ID_REGS_OFF);
1898 		if (PCI_CAPSLOT_FIC(esr))
1899 			fic = 1;
1900 	}
1901 
1902 	if ((PCI_CAP_LOCATE(config_handle,
1903 	    PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_SER), &cap_ptr)) != DDI_FAILURE) {
1904 		/* Serialid can be 0 thru a full 40b number */
1905 		serialid = PCI_XCAP_GET32(config_handle, NULL,
1906 		    cap_ptr, PCIE_SER_SID_UPPER_DW);
1907 		serialid <<= 32;
1908 		serialid |= PCI_XCAP_GET32(config_handle, NULL,
1909 		    cap_ptr, PCIE_SER_SID_LOWER_DW);
1910 	}
1911 
1912 	if (fic)
1913 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip,
1914 		    "first-in-chassis");
1915 	if (serialid)
1916 		(void) ddi_prop_update_int64(DDI_DEV_T_NONE, pcieb->pcieb_dip,
1917 		    "serialid#", serialid);
1918 }
1919 
1920 static void
1921 pcieb_create_ranges_prop(dev_info_t *dip,
1922 	ddi_acc_handle_t config_handle)
1923 {
1924 	uint32_t base, limit;
1925 	pcieb_ranges_t	ranges[PCIEB_RANGE_LEN];
1926 	uint8_t io_base_lo, io_limit_lo;
1927 	uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit;
1928 	int i = 0, rangelen = sizeof (pcieb_ranges_t)/sizeof (int);
1929 
1930 	io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW);
1931 	io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW);
1932 	io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI);
1933 	io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI);
1934 	mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE);
1935 	mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT);
1936 
1937 	/*
1938 	 * Create ranges for IO space
1939 	 */
1940 	ranges[i].size_low = ranges[i].size_high = 0;
1941 	ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0;
1942 	ranges[i].child_high = ranges[i].parent_high |=
1943 	    (PCI_REG_REL_M | PCI_ADDR_IO);
1944 	base = PCIEB_16bit_IOADDR(io_base_lo);
1945 	limit = PCIEB_16bit_IOADDR(io_limit_lo);
1946 
1947 	if ((io_base_lo & 0xf) == PCIEB_32BIT_IO) {
1948 		base = PCIEB_LADDR(base, io_base_hi);
1949 	}
1950 	if ((io_limit_lo & 0xf) == PCIEB_32BIT_IO) {
1951 		limit = PCIEB_LADDR(limit, io_limit_hi);
1952 	}
1953 
1954 	if ((io_base_lo & PCIEB_32BIT_IO) && (io_limit_hi > 0)) {
1955 		base = PCIEB_LADDR(base, io_base_hi);
1956 		limit = PCIEB_LADDR(limit, io_limit_hi);
1957 	}
1958 
1959 	/*
1960 	 * Create ranges for 32bit memory space
1961 	 */
1962 	base = PCIEB_32bit_MEMADDR(mem_base);
1963 	limit = PCIEB_32bit_MEMADDR(mem_limit);
1964 	ranges[i].size_low = ranges[i].size_high = 0;
1965 	ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0;
1966 	ranges[i].child_high = ranges[i].parent_high |=
1967 	    (PCI_REG_REL_M | PCI_ADDR_MEM32);
1968 	ranges[i].child_low = ranges[i].parent_low = base;
1969 	if (limit >= base) {
1970 		ranges[i].size_low = limit - base + PCIEB_MEMGRAIN;
1971 		i++;
1972 	}
1973 
1974 	if (i) {
1975 		(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges",
1976 		    (int *)ranges, i * rangelen);
1977 	}
1978 }
1979 
1980 /*
1981  * For PCI and PCI-X devices including PCIe2PCI bridge, initialize
1982  * cache-line-size and latency timer configuration registers.
1983  */
1984 void
1985 pcieb_set_pci_perf_parameters(dev_info_t *dip, ddi_acc_handle_t cfg_hdl)
1986 {
1987 	uint_t	n;
1988 
1989 	/* Initialize cache-line-size configuration register if needed */
1990 	if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1991 	    "cache-line-size", 0) == 0) {
1992 		pci_config_put8(cfg_hdl, PCI_CONF_CACHE_LINESZ,
1993 		    PCIEB_CACHE_LINE_SIZE);
1994 		n = pci_config_get8(cfg_hdl, PCI_CONF_CACHE_LINESZ);
1995 		if (n != 0) {
1996 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1997 			    "cache-line-size", n);
1998 		}
1999 	}
2000 
2001 	/* Initialize latency timer configuration registers if needed */
2002 	if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
2003 	    "latency-timer", 0) == 0) {
2004 		uchar_t	min_gnt, latency_timer;
2005 		uchar_t header_type;
2006 
2007 		/* Determine the configuration header type */
2008 		header_type = pci_config_get8(cfg_hdl, PCI_CONF_HEADER);
2009 
2010 		if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) {
2011 			latency_timer = PCIEB_LATENCY_TIMER;
2012 			pci_config_put8(cfg_hdl, PCI_BCNF_LATENCY_TIMER,
2013 			    latency_timer);
2014 		} else {
2015 			min_gnt = pci_config_get8(cfg_hdl, PCI_CONF_MIN_G);
2016 			latency_timer = min_gnt * 8;
2017 		}
2018 
2019 		pci_config_put8(cfg_hdl, PCI_CONF_LATENCY_TIMER,
2020 		    latency_timer);
2021 		n = pci_config_get8(cfg_hdl, PCI_CONF_LATENCY_TIMER);
2022 		if (n != 0) {
2023 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
2024 			    "latency-timer", n);
2025 		}
2026 	}
2027 }
2028