1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Common x86 and SPARC PCI-E to PCI bus bridge nexus driver 28 */ 29 30 #include <sys/sysmacros.h> 31 #include <sys/conf.h> 32 #include <sys/kmem.h> 33 #include <sys/debug.h> 34 #include <sys/modctl.h> 35 #include <sys/autoconf.h> 36 #include <sys/ddi_impldefs.h> 37 #include <sys/pci.h> 38 #include <sys/ddi.h> 39 #include <sys/sunddi.h> 40 #include <sys/sunndi.h> 41 #include <sys/fm/util.h> 42 #include <sys/pcie.h> 43 #include <sys/pci_cap.h> 44 #include <sys/pcie_impl.h> 45 #include <sys/hotplug/pci/pcihp.h> 46 #include <sys/hotplug/pci/pciehpc.h> 47 #include <sys/hotplug/pci/pcishpc.h> 48 #include <sys/open.h> 49 #include <sys/stat.h> 50 #include <sys/file.h> 51 #include <sys/promif.h> /* prom_printf */ 52 #include <sys/disp.h> 53 #include <sys/pcie_pwr.h> 54 #include "pcieb.h" 55 #ifdef PX_PLX 56 #include <io/pciex/pcieb_plx.h> 57 #endif /* PX_PLX */ 58 59 /*LINTLIBRARY*/ 60 61 /* panic flag */ 62 int pcieb_die = PF_ERR_FATAL_FLAGS; 63 64 /* flag to turn on MSI support */ 65 int pcieb_enable_msi = 1; 66 67 #if defined(DEBUG) 68 uint_t pcieb_dbg_print = 0; 69 70 static char *pcieb_debug_sym [] = { /* same sequence as pcieb_debug_bit */ 71 /* 0 */ "attach", 72 /* 1 */ "pwr", 73 /* 2 */ "intr" 74 }; 75 #endif /* DEBUG */ 76 77 static int pcieb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, off_t, 78 off_t, caddr_t *); 79 static int pcieb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, void *, 80 void *); 81 static int pcieb_fm_init(pcieb_devstate_t *pcieb_p); 82 static void pcieb_fm_fini(pcieb_devstate_t *pcieb_p); 83 static int pcieb_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap, 84 ddi_iblock_cookie_t *ibc_p); 85 static int pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 86 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg, 87 ddi_dma_handle_t *handlep); 88 static int pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, 89 ddi_dma_handle_t handle, enum ddi_dma_ctlops cmd, off_t *offp, 90 size_t *lenp, caddr_t *objp, uint_t cache_flags); 91 static int pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, 92 ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result); 93 94 static struct bus_ops pcieb_bus_ops = { 95 BUSO_REV, 96 pcieb_bus_map, 97 0, 98 0, 99 0, 100 i_ddi_map_fault, 101 ddi_dma_map, 102 pcieb_dma_allochdl, 103 ddi_dma_freehdl, 104 ddi_dma_bindhdl, 105 ddi_dma_unbindhdl, 106 ddi_dma_flush, 107 ddi_dma_win, 108 pcieb_dma_mctl, 109 pcieb_ctlops, 110 ddi_bus_prop_op, 111 ndi_busop_get_eventcookie, /* (*bus_get_eventcookie)(); */ 112 ndi_busop_add_eventcall, /* (*bus_add_eventcall)(); */ 113 ndi_busop_remove_eventcall, /* (*bus_remove_eventcall)(); */ 114 ndi_post_event, /* (*bus_post_event)(); */ 115 NULL, /* (*bus_intr_ctl)(); */ 116 NULL, /* (*bus_config)(); */ 117 NULL, /* (*bus_unconfig)(); */ 118 pcieb_fm_init_child, /* (*bus_fm_init)(); */ 119 NULL, /* (*bus_fm_fini)(); */ 120 i_ndi_busop_access_enter, /* (*bus_fm_access_enter)(); */ 121 i_ndi_busop_access_exit, /* (*bus_fm_access_exit)(); */ 122 pcie_bus_power, /* (*bus_power)(); */ 123 pcieb_intr_ops /* (*bus_intr_op)(); */ 124 }; 125 126 static int pcieb_open(dev_t *, int, int, cred_t *); 127 static int pcieb_close(dev_t, int, int, cred_t *); 128 static int pcieb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 129 static int pcieb_prop_op(dev_t, dev_info_t *, ddi_prop_op_t, int, char *, 130 caddr_t, int *); 131 static int pcieb_info(dev_info_t *, ddi_info_cmd_t, void *, void **); 132 static uint_t pcieb_intr_handler(caddr_t arg1, caddr_t arg2); 133 134 /* PM related functions */ 135 static int pcieb_pwr_setup(dev_info_t *dip); 136 static int pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p); 137 static void pcieb_pwr_teardown(dev_info_t *dip); 138 static int pcieb_pwr_disable(dev_info_t *dip); 139 140 /* Hotplug related functions */ 141 static int pcieb_pciehpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle); 142 static int pcieb_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle); 143 static int pcieb_init_hotplug(pcieb_devstate_t *pcieb); 144 static void pcieb_id_props(pcieb_devstate_t *pcieb); 145 146 /* 147 * soft state pointer 148 */ 149 void *pcieb_state; 150 151 static struct cb_ops pcieb_cb_ops = { 152 pcieb_open, /* open */ 153 pcieb_close, /* close */ 154 nodev, /* strategy */ 155 nodev, /* print */ 156 nodev, /* dump */ 157 nodev, /* read */ 158 nodev, /* write */ 159 pcieb_ioctl, /* ioctl */ 160 nodev, /* devmap */ 161 nodev, /* mmap */ 162 nodev, /* segmap */ 163 nochpoll, /* poll */ 164 pcieb_prop_op, /* cb_prop_op */ 165 NULL, /* streamtab */ 166 D_NEW | D_MP | D_HOTPLUG, /* Driver compatibility flag */ 167 CB_REV, /* rev */ 168 nodev, /* int (*cb_aread)() */ 169 nodev /* int (*cb_awrite)() */ 170 }; 171 172 static int pcieb_probe(dev_info_t *); 173 static int pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd); 174 static int pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 175 176 static struct dev_ops pcieb_ops = { 177 DEVO_REV, /* devo_rev */ 178 0, /* refcnt */ 179 pcieb_info, /* info */ 180 nulldev, /* identify */ 181 pcieb_probe, /* probe */ 182 pcieb_attach, /* attach */ 183 pcieb_detach, /* detach */ 184 nulldev, /* reset */ 185 &pcieb_cb_ops, /* driver operations */ 186 &pcieb_bus_ops, /* bus operations */ 187 pcie_power, /* power */ 188 ddi_quiesce_not_needed, /* quiesce */ 189 }; 190 191 /* 192 * Module linkage information for the kernel. 193 */ 194 195 static struct modldrv modldrv = { 196 &mod_driverops, /* Type of module */ 197 "PCIe to PCI nexus driver", 198 &pcieb_ops, /* driver ops */ 199 }; 200 201 static struct modlinkage modlinkage = { 202 MODREV_1, 203 (void *)&modldrv, 204 NULL 205 }; 206 207 /* 208 * forward function declarations: 209 */ 210 static void pcieb_uninitchild(dev_info_t *); 211 static int pcieb_initchild(dev_info_t *child); 212 static void pcieb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t); 213 static boolean_t pcieb_is_pcie_device_type(dev_info_t *dip); 214 215 /* interrupt related declarations */ 216 static int pcieb_msi_supported(dev_info_t *); 217 static int pcieb_intr_attach(pcieb_devstate_t *pcieb); 218 static int pcieb_intr_init(pcieb_devstate_t *pcieb_p, int intr_type); 219 static void pcieb_intr_fini(pcieb_devstate_t *pcieb_p); 220 221 int 222 _init(void) 223 { 224 int e; 225 226 if ((e = ddi_soft_state_init(&pcieb_state, sizeof (pcieb_devstate_t), 227 1)) == 0 && (e = mod_install(&modlinkage)) != 0) 228 ddi_soft_state_fini(&pcieb_state); 229 return (e); 230 } 231 232 int 233 _fini(void) 234 { 235 int e; 236 237 if ((e = mod_remove(&modlinkage)) == 0) { 238 ddi_soft_state_fini(&pcieb_state); 239 } 240 return (e); 241 } 242 243 int 244 _info(struct modinfo *modinfop) 245 { 246 return (mod_info(&modlinkage, modinfop)); 247 } 248 249 /*ARGSUSED*/ 250 static int 251 pcieb_probe(dev_info_t *devi) 252 { 253 return (DDI_PROBE_SUCCESS); 254 } 255 256 static int 257 pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 258 { 259 int instance; 260 char device_type[8]; 261 pcieb_devstate_t *pcieb; 262 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(devi); 263 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 264 uint8_t dev_type = bus_p->bus_dev_type; 265 266 switch (cmd) { 267 case DDI_RESUME: 268 (void) pcie_pwr_resume(devi); 269 return (DDI_SUCCESS); 270 271 default: 272 return (DDI_FAILURE); 273 274 case DDI_ATTACH: 275 break; 276 } 277 278 if (!(PCIE_IS_BDG(bus_p))) { 279 PCIEB_DEBUG(DBG_ATTACH, devi, "This is not a switch or" 280 " bridge\n"); 281 return (DDI_FAILURE); 282 } 283 284 /* 285 * If PCIE_LINKCTL_LINK_DISABLE bit in the PCIe Config 286 * Space (PCIe Capability Link Control Register) is set, 287 * then do not bind the driver. 288 */ 289 if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & PCIE_LINKCTL_LINK_DISABLE) 290 return (DDI_FAILURE); 291 292 /* 293 * Allocate and get soft state structure. 294 */ 295 instance = ddi_get_instance(devi); 296 if (ddi_soft_state_zalloc(pcieb_state, instance) != DDI_SUCCESS) 297 return (DDI_FAILURE); 298 pcieb = ddi_get_soft_state(pcieb_state, instance); 299 pcieb->pcieb_dip = devi; 300 pcieb->pcieb_soft_state = PCIEB_SOFT_STATE_CLOSED; 301 302 if ((pcieb_fm_init(pcieb)) != DDI_SUCCESS) { 303 PCIEB_DEBUG(DBG_ATTACH, devi, "Failed in pcieb_fm_init\n"); 304 goto fail; 305 } 306 pcieb->pcieb_init_flags |= PCIEB_INIT_FM; 307 308 mutex_init(&pcieb->pcieb_mutex, NULL, MUTEX_DRIVER, NULL); 309 mutex_init(&pcieb->pcieb_err_mutex, NULL, MUTEX_DRIVER, 310 (void *)pcieb->pcieb_fm_ibc); 311 mutex_init(&pcieb->pcieb_peek_poke_mutex, NULL, MUTEX_DRIVER, 312 (void *)pcieb->pcieb_fm_ibc); 313 314 /* create special properties for device identification */ 315 pcieb_id_props(pcieb); 316 317 /* 318 * Power management setup. This also makes sure that switch/bridge 319 * is at D0 during attach. 320 */ 321 if (pwr_common_setup(devi) != DDI_SUCCESS) { 322 PCIEB_DEBUG(DBG_PWR, devi, "pwr_common_setup failed\n"); 323 goto fail; 324 } 325 326 if (pcieb_pwr_setup(devi) != DDI_SUCCESS) { 327 PCIEB_DEBUG(DBG_PWR, devi, "pxb_pwr_setup failed \n"); 328 goto fail; 329 } 330 331 /* 332 * Make sure the "device_type" property exists. 333 */ 334 if (pcieb_is_pcie_device_type(devi)) 335 (void) strcpy(device_type, "pciex"); 336 else 337 (void) strcpy(device_type, "pci"); 338 339 (void) ddi_prop_update_string(DDI_DEV_T_NONE, devi, 340 "device_type", device_type); 341 342 /* 343 * Check whether the "ranges" property is present. 344 * Otherwise create the ranges property by reading 345 * the configuration registers 346 */ 347 if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS, 348 "ranges") == 0) { 349 pcieb_create_ranges_prop(devi, config_handle); 350 } 351 352 if (PCIE_IS_PCI_BDG(bus_p)) 353 pcieb_set_pci_perf_parameters(devi, config_handle); 354 355 #ifdef PX_PLX 356 pcieb_attach_plx_workarounds(pcieb); 357 #endif /* PX_PLX */ 358 359 /* Initialize hotplug */ 360 pcieb->pcieb_hotplug_capable = B_FALSE; 361 362 if ((dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) || 363 (dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT) || 364 (dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) || 365 (dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) { 366 (void) pcieb_init_hotplug(pcieb); 367 } 368 369 /* 370 * Initialize interrupt handlers. Ignore return value. 371 */ 372 (void) pcieb_intr_attach(pcieb); 373 374 if (pcieb->pcieb_hotplug_capable == B_FALSE) { 375 /* 376 * (for non hotplug bus) this would create ":devctl" minor 377 * node to support DEVCTL_DEVICE_* and DEVCTL_BUS_* ioctls 378 * to this bus. 379 */ 380 if (ddi_create_minor_node(devi, "devctl", S_IFCHR, 381 PCIHP_AP_MINOR_NUM(instance, PCIHP_DEVCTL_MINOR), 382 DDI_NT_NEXUS, 0) != DDI_SUCCESS) 383 goto fail; 384 } 385 386 PCIEB_DEBUG(DBG_ATTACH, devi, 387 "pcieb_attach: this nexus %s hotplug slots\n", 388 pcieb->pcieb_hotplug_capable == B_TRUE ? "has":"has no"); 389 390 /* Do any platform specific workarounds needed at this time */ 391 pcieb_plat_attach_workaround(devi); 392 393 /* 394 * If this is a root port, determine and set the max payload size. 395 * Since this will involve scanning the fabric, all error enabling 396 * and sw workarounds should be in place before doing this. 397 */ 398 if (PCIE_IS_RP(bus_p)) 399 pcie_init_root_port_mps(devi); 400 401 ddi_report_dev(devi); 402 return (DDI_SUCCESS); 403 404 fail: 405 (void) pcieb_detach(devi, DDI_DETACH); 406 return (DDI_FAILURE); 407 } 408 409 static int 410 pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 411 { 412 pcieb_devstate_t *pcieb; 413 int error = DDI_SUCCESS; 414 415 switch (cmd) { 416 case DDI_SUSPEND: 417 error = pcie_pwr_suspend(devi); 418 return (error); 419 420 case DDI_DETACH: 421 break; 422 423 default: 424 return (DDI_FAILURE); 425 } 426 427 pcieb = ddi_get_soft_state(pcieb_state, ddi_get_instance(devi)); 428 429 /* remove interrupt handlers */ 430 pcieb_intr_fini(pcieb); 431 432 if (pcieb->pcieb_hotplug_capable == B_TRUE) { 433 if (pcihp_uninit(devi) == DDI_FAILURE) 434 error = DDI_FAILURE; 435 436 if (pcieb->pcieb_hpc_type == HPC_PCIE) 437 (void) pciehpc_uninit(devi); 438 else if (pcieb->pcieb_hpc_type == HPC_SHPC) 439 (void) pcishpc_uninit(devi); 440 } else { 441 ddi_remove_minor_node(devi, "devctl"); 442 } 443 444 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type"); 445 446 (void) ndi_prop_remove(DDI_DEV_T_NONE, pcieb->pcieb_dip, 447 "pcie_ce_mask"); 448 449 if (pcieb->pcieb_init_flags & PCIEB_INIT_FM) 450 pcieb_fm_fini(pcieb); 451 452 pcieb_pwr_teardown(devi); 453 pwr_common_teardown(devi); 454 455 mutex_destroy(&pcieb->pcieb_peek_poke_mutex); 456 mutex_destroy(&pcieb->pcieb_err_mutex); 457 mutex_destroy(&pcieb->pcieb_mutex); 458 459 /* 460 * And finally free the per-pci soft state. 461 */ 462 ddi_soft_state_free(pcieb_state, ddi_get_instance(devi)); 463 464 return (DDI_SUCCESS); 465 } 466 467 static int 468 pcieb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 469 off_t offset, off_t len, caddr_t *vaddrp) 470 { 471 dev_info_t *pdip; 472 473 pdip = (dev_info_t *)DEVI(dip)->devi_parent; 474 return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip, rdip, mp, 475 offset, len, vaddrp)); 476 } 477 478 static int 479 pcieb_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop, 480 void *arg, void *result) 481 { 482 pci_regspec_t *drv_regp; 483 int reglen; 484 int rn; 485 int totreg; 486 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, 487 ddi_get_instance(dip)); 488 struct detachspec *ds; 489 struct attachspec *as; 490 491 switch (ctlop) { 492 case DDI_CTLOPS_REPORTDEV: 493 if (rdip == (dev_info_t *)0) 494 return (DDI_FAILURE); 495 cmn_err(CE_CONT, "?PCIE-device: %s@%s, %s%d\n", 496 ddi_node_name(rdip), ddi_get_name_addr(rdip), 497 ddi_driver_name(rdip), 498 ddi_get_instance(rdip)); 499 return (DDI_SUCCESS); 500 501 case DDI_CTLOPS_INITCHILD: 502 return (pcieb_initchild((dev_info_t *)arg)); 503 504 case DDI_CTLOPS_UNINITCHILD: 505 pcieb_uninitchild((dev_info_t *)arg); 506 return (DDI_SUCCESS); 507 508 case DDI_CTLOPS_SIDDEV: 509 return (DDI_SUCCESS); 510 511 case DDI_CTLOPS_REGSIZE: 512 case DDI_CTLOPS_NREGS: 513 if (rdip == (dev_info_t *)0) 514 return (DDI_FAILURE); 515 break; 516 517 case DDI_CTLOPS_PEEK: 518 case DDI_CTLOPS_POKE: 519 return (pcieb_plat_peekpoke(dip, rdip, ctlop, arg, result)); 520 case DDI_CTLOPS_ATTACH: 521 if (!pcie_is_child(dip, rdip)) 522 return (DDI_SUCCESS); 523 524 as = (struct attachspec *)arg; 525 switch (as->when) { 526 case DDI_PRE: 527 if (as->cmd == DDI_RESUME) { 528 pcie_clear_errors(rdip); 529 if (pcieb_plat_ctlops(rdip, ctlop, arg) != 530 DDI_SUCCESS) 531 return (DDI_FAILURE); 532 } 533 534 if (as->cmd == DDI_ATTACH) 535 return (pcie_pm_hold(dip)); 536 537 return (DDI_SUCCESS); 538 539 case DDI_POST: 540 if (as->cmd == DDI_ATTACH && as->result != DDI_SUCCESS) 541 pcie_pm_release(dip); 542 543 if (as->result == DDI_SUCCESS) { 544 pf_init(rdip, (void *)pcieb->pcieb_fm_ibc, 545 as->cmd); 546 547 (void) pcieb_plat_ctlops(rdip, ctlop, arg); 548 } 549 550 /* 551 * For empty hotplug-capable slots, we should explicitly 552 * disable the errors, so that we won't panic upon 553 * unsupported hotplug messages. 554 */ 555 if ((!ddi_prop_exists(DDI_DEV_T_ANY, rdip, 556 DDI_PROP_DONTPASS, "hotplug-capable")) || 557 ddi_get_child(rdip)) { 558 (void) pcie_postattach_child(rdip); 559 return (DDI_SUCCESS); 560 } 561 562 pcie_disable_errors(rdip); 563 564 return (DDI_SUCCESS); 565 default: 566 break; 567 } 568 return (DDI_SUCCESS); 569 570 case DDI_CTLOPS_DETACH: 571 if (!pcie_is_child(dip, rdip)) 572 return (DDI_SUCCESS); 573 574 ds = (struct detachspec *)arg; 575 switch (ds->when) { 576 case DDI_PRE: 577 pf_fini(rdip, ds->cmd); 578 return (DDI_SUCCESS); 579 580 case DDI_POST: 581 if (pcieb_plat_ctlops(rdip, ctlop, arg) != DDI_SUCCESS) 582 return (DDI_FAILURE); 583 if (ds->cmd == DDI_DETACH && 584 ds->result == DDI_SUCCESS) { 585 return (pcie_pm_remove_child(dip, rdip)); 586 } 587 return (DDI_SUCCESS); 588 default: 589 break; 590 } 591 return (DDI_SUCCESS); 592 default: 593 return (ddi_ctlops(dip, rdip, ctlop, arg, result)); 594 } 595 596 *(int *)result = 0; 597 if (ddi_getlongprop(DDI_DEV_T_ANY, rdip, 598 DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", (caddr_t)&drv_regp, 599 ®len) != DDI_SUCCESS) 600 return (DDI_FAILURE); 601 602 totreg = reglen / sizeof (pci_regspec_t); 603 if (ctlop == DDI_CTLOPS_NREGS) 604 *(int *)result = totreg; 605 else if (ctlop == DDI_CTLOPS_REGSIZE) { 606 rn = *(int *)arg; 607 if (rn >= totreg) { 608 kmem_free(drv_regp, reglen); 609 return (DDI_FAILURE); 610 } 611 612 *(off_t *)result = drv_regp[rn].pci_size_low | 613 ((uint64_t)drv_regp[rn].pci_size_hi << 32); 614 } 615 616 kmem_free(drv_regp, reglen); 617 return (DDI_SUCCESS); 618 } 619 620 /* 621 * name_child 622 * 623 * This function is called from init_child to name a node. It is 624 * also passed as a callback for node merging functions. 625 * 626 * return value: DDI_SUCCESS, DDI_FAILURE 627 */ 628 static int 629 pcieb_name_child(dev_info_t *child, char *name, int namelen) 630 { 631 pci_regspec_t *pci_rp; 632 uint_t slot, func; 633 char **unit_addr; 634 uint_t n; 635 636 /* 637 * For .conf nodes, use unit-address property as name 638 */ 639 if (ndi_dev_is_persistent_node(child) == 0) { 640 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child, 641 DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) != 642 DDI_PROP_SUCCESS) { 643 cmn_err(CE_WARN, 644 "cannot find unit-address in %s.conf", 645 ddi_driver_name(child)); 646 return (DDI_FAILURE); 647 } 648 if (n != 1 || *unit_addr == NULL || **unit_addr == 0) { 649 cmn_err(CE_WARN, "unit-address property in %s.conf" 650 " not well-formed", ddi_driver_name(child)); 651 ddi_prop_free(unit_addr); 652 return (DDI_FAILURE); 653 } 654 (void) snprintf(name, namelen, "%s", *unit_addr); 655 ddi_prop_free(unit_addr); 656 return (DDI_SUCCESS); 657 } 658 659 /* 660 * Get the address portion of the node name based on 661 * the function and device number. 662 */ 663 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child, 664 DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) { 665 return (DDI_FAILURE); 666 } 667 668 /* copy the device identifications */ 669 slot = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi); 670 func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi); 671 672 if (func != 0) 673 (void) snprintf(name, namelen, "%x,%x", slot, func); 674 else 675 (void) snprintf(name, namelen, "%x", slot); 676 677 ddi_prop_free(pci_rp); 678 return (DDI_SUCCESS); 679 } 680 681 static int 682 pcieb_initchild(dev_info_t *child) 683 { 684 char name[MAXNAMELEN]; 685 int result = DDI_FAILURE; 686 pcieb_devstate_t *pcieb = 687 (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 688 ddi_get_instance(ddi_get_parent(child))); 689 690 /* 691 * Name the child 692 */ 693 if (pcieb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) { 694 result = DDI_FAILURE; 695 goto done; 696 } 697 ddi_set_name_addr(child, name); 698 699 /* 700 * Pseudo nodes indicate a prototype node with per-instance 701 * properties to be merged into the real h/w device node. 702 * The interpretation of the unit-address is DD[,F] 703 * where DD is the device id and F is the function. 704 */ 705 if (ndi_dev_is_persistent_node(child) == 0) { 706 extern int pci_allow_pseudo_children; 707 708 /* 709 * Try to merge the properties from this prototype 710 * node into real h/w nodes. 711 */ 712 if (ndi_merge_node(child, pcieb_name_child) != DDI_SUCCESS) { 713 /* 714 * Merged ok - return failure to remove the node. 715 */ 716 ddi_set_name_addr(child, NULL); 717 result = DDI_FAILURE; 718 goto done; 719 } 720 721 /* workaround for ddivs to run under PCI-E */ 722 if (pci_allow_pseudo_children) { 723 result = DDI_SUCCESS; 724 goto done; 725 } 726 727 /* 728 * The child was not merged into a h/w node, 729 * but there's not much we can do with it other 730 * than return failure to cause the node to be removed. 731 */ 732 cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged", 733 ddi_driver_name(child), ddi_get_name_addr(child), 734 ddi_driver_name(child)); 735 ddi_set_name_addr(child, NULL); 736 result = DDI_NOT_WELL_FORMED; 737 goto done; 738 } 739 740 /* platform specific initchild */ 741 pcieb_plat_initchild(child); 742 743 if (pcie_pm_hold(pcieb->pcieb_dip) != DDI_SUCCESS) { 744 PCIEB_DEBUG(DBG_PWR, pcieb->pcieb_dip, 745 "INITCHILD: px_pm_hold failed\n"); 746 result = DDI_FAILURE; 747 goto done; 748 } 749 /* Any return from here must call pcie_pm_release */ 750 751 /* 752 * If configuration registers were previously saved by 753 * child (before it entered D3), then let the child do the 754 * restore to set up the config regs as it'll first need to 755 * power the device out of D3. 756 */ 757 if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 758 "config-regs-saved-by-child") == 1) { 759 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 760 "INITCHILD: config regs to be restored by child" 761 " for %s@%s\n", ddi_node_name(child), 762 ddi_get_name_addr(child)); 763 764 result = DDI_SUCCESS; 765 goto cleanup; 766 } 767 768 PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child), 769 "INITCHILD: config regs setup for %s@%s\n", 770 ddi_node_name(child), ddi_get_name_addr(child)); 771 772 if (!pcie_init_bus(child) || pcie_initchild(child) != DDI_SUCCESS) { 773 result = DDI_FAILURE; 774 goto cleanup; 775 } 776 777 #ifdef PX_PLX 778 if (pcieb_init_plx_workarounds(pcieb, child) == DDI_FAILURE) { 779 result = DDI_FAILURE; 780 goto cleanup; 781 } 782 #endif /* PX_PLX */ 783 784 result = DDI_SUCCESS; 785 cleanup: 786 pcie_pm_release(pcieb->pcieb_dip); 787 done: 788 return (result); 789 } 790 791 static void 792 pcieb_uninitchild(dev_info_t *dip) 793 { 794 795 pcie_uninitchild(dip); 796 797 pcieb_plat_uninitchild(dip); 798 799 ddi_set_name_addr(dip, NULL); 800 801 /* 802 * Strip the node to properly convert it back to prototype form 803 */ 804 ddi_remove_minor_node(dip, NULL); 805 806 ddi_prop_remove_all(dip); 807 } 808 809 static boolean_t 810 pcieb_is_pcie_device_type(dev_info_t *dip) 811 { 812 pcie_bus_t *bus_p = PCIE_DIP2BUS(dip); 813 814 if (PCIE_IS_SW(bus_p) || PCIE_IS_RP(bus_p) || PCIE_IS_PCI2PCIE(bus_p)) 815 return (B_TRUE); 816 817 return (B_FALSE); 818 } 819 820 static int 821 pcieb_intr_attach(pcieb_devstate_t *pcieb) 822 { 823 int intr_types; 824 dev_info_t *dip = pcieb->pcieb_dip; 825 826 /* Allow platform specific code to do any initialization first */ 827 pcieb_plat_intr_attach(pcieb); 828 829 /* 830 * Initialize interrupt handlers. 831 * If both MSI and FIXED are supported, try to attach MSI first. 832 * If MSI fails for any reason, then try FIXED, but only allow one 833 * type to be attached. 834 */ 835 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 836 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_supported_types" 837 " failed\n"); 838 goto FAIL; 839 } 840 841 if ((intr_types & DDI_INTR_TYPE_MSI) && 842 (pcieb_msi_supported(dip) == DDI_SUCCESS)) { 843 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) 844 intr_types = DDI_INTR_TYPE_MSI; 845 else { 846 PCIEB_DEBUG(DBG_ATTACH, dip, "Unable to attach MSI" 847 " handler\n"); 848 } 849 } 850 851 if (intr_types != DDI_INTR_TYPE_MSI) { 852 /* 853 * MSIs are not supported or MSI initialization failed. For Root 854 * Ports mark this so error handling might try to fallback to 855 * some other mechanism if available (machinecheck etc.). 856 */ 857 if (PCIE_IS_RP(PCIE_DIP2UPBUS(dip))) 858 pcieb->pcieb_no_aer_msi = B_TRUE; 859 } 860 861 if (intr_types & DDI_INTR_TYPE_FIXED) { 862 if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_FIXED) != 863 DDI_SUCCESS) { 864 PCIEB_DEBUG(DBG_ATTACH, dip, 865 "Unable to attach INTx handler\n"); 866 goto FAIL; 867 } 868 } 869 return (DDI_SUCCESS); 870 871 FAIL: 872 return (DDI_FAILURE); 873 } 874 875 /* 876 * This function initializes internally generated interrupts only. 877 * It does not affect any interrupts generated by downstream devices 878 * or the forwarding of them. 879 * 880 * Enable Device Specific Interrupts or Hotplug features here. 881 * Enabling features may change how many interrupts are requested 882 * by the device. If features are not enabled first, the 883 * device might not ask for any interrupts. 884 */ 885 static int 886 pcieb_intr_init(pcieb_devstate_t *pcieb, int intr_type) 887 { 888 dev_info_t *dip = pcieb->pcieb_dip; 889 int nintrs, request, count, x; 890 int intr_cap = 0; 891 int inum = 0; 892 int ret, hp_msi_off; 893 pcie_bus_t *bus_p = PCIE_DIP2UPBUS(dip); 894 uint16_t vendorid = bus_p->bus_dev_ven_id & 0xFFFF; 895 boolean_t is_hp = B_FALSE; 896 boolean_t is_pme = B_FALSE; 897 898 PCIEB_DEBUG(DBG_ATTACH, dip, "pcieb_intr_init: Attaching %s handler\n", 899 (intr_type == DDI_INTR_TYPE_MSI) ? "MSI" : "INTx"); 900 901 request = 0; 902 if (pcieb->pcieb_hotplug_capable) { 903 request++; 904 is_hp = B_TRUE; 905 } 906 907 /* 908 * Hotplug and PME share the same MSI vector. If hotplug is not 909 * supported check if MSI is needed for PME. 910 */ 911 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p) && 912 (vendorid == NVIDIA_VENDOR_ID)) { 913 is_pme = B_TRUE; 914 if (!is_hp) 915 request++; 916 } 917 918 /* 919 * Setup MSI if this device is a Rootport and has AER. Currently no 920 * SPARC Root Port supports fabric errors being reported through it. 921 */ 922 if (intr_type == DDI_INTR_TYPE_MSI) { 923 if (PCIE_IS_RP(bus_p) && PCIE_HAS_AER(bus_p)) 924 request++; 925 } 926 927 if (request == 0) 928 return (DDI_SUCCESS); 929 930 /* 931 * Get number of supported interrupts. 932 * 933 * Several Bridges/Switches will not have this property set, resulting 934 * in a FAILURE, if the device is not configured in a way that 935 * interrupts are needed. (eg. hotplugging) 936 */ 937 ret = ddi_intr_get_nintrs(dip, intr_type, &nintrs); 938 if ((ret != DDI_SUCCESS) || (nintrs == 0)) { 939 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_nintrs ret:%d" 940 " req:%d\n", ret, nintrs); 941 return (DDI_FAILURE); 942 } 943 944 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0x%x: ddi_intr_get_nintrs: nintrs %d", 945 " request %d\n", bus_p->bus_bdf, nintrs, request); 946 947 if (request > nintrs) 948 request = nintrs; 949 950 /* Allocate an array of interrupt handlers */ 951 pcieb->pcieb_htable_size = sizeof (ddi_intr_handle_t) * request; 952 pcieb->pcieb_htable = kmem_zalloc(pcieb->pcieb_htable_size, 953 KM_SLEEP); 954 pcieb->pcieb_init_flags |= PCIEB_INIT_HTABLE; 955 956 ret = ddi_intr_alloc(dip, pcieb->pcieb_htable, intr_type, inum, 957 request, &count, DDI_INTR_ALLOC_NORMAL); 958 if ((ret != DDI_SUCCESS) || (count == 0)) { 959 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_alloc() ret: %d ask: %d" 960 " actual: %d\n", ret, request, count); 961 goto FAIL; 962 } 963 pcieb->pcieb_init_flags |= PCIEB_INIT_ALLOC; 964 965 /* Save the actual number of interrupts allocated */ 966 pcieb->pcieb_intr_count = count; 967 if (count < request) { 968 PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0%x: Requested Intr: %d" 969 " Received: %d\n", bus_p->bus_bdf, request, count); 970 } 971 972 /* 973 * NVidia (MCP55 and other) chipsets have a errata that if the number 974 * of requested MSI intrs is not allocated we have to fall back to INTx. 975 */ 976 if (intr_type == DDI_INTR_TYPE_MSI) { 977 if (PCIE_IS_RP(bus_p) && (vendorid == NVIDIA_VENDOR_ID)) { 978 if (request != count) 979 goto FAIL; 980 } 981 } 982 983 /* Get interrupt priority */ 984 ret = ddi_intr_get_pri(pcieb->pcieb_htable[0], 985 &pcieb->pcieb_intr_priority); 986 if (ret != DDI_SUCCESS) { 987 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_pri() ret: %d\n", 988 ret); 989 goto FAIL; 990 } 991 992 if (pcieb->pcieb_intr_priority >= LOCK_LEVEL) { 993 pcieb->pcieb_intr_priority = LOCK_LEVEL - 1; 994 ret = ddi_intr_set_pri(pcieb->pcieb_htable[0], 995 pcieb->pcieb_intr_priority); 996 if (ret != DDI_SUCCESS) { 997 PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_set_pri() ret:" 998 " %d\n", ret); 999 1000 goto FAIL; 1001 } 1002 } 1003 1004 mutex_init(&pcieb->pcieb_intr_mutex, NULL, MUTEX_DRIVER, NULL); 1005 1006 pcieb->pcieb_init_flags |= PCIEB_INIT_MUTEX; 1007 1008 for (count = 0; count < pcieb->pcieb_intr_count; count++) { 1009 ret = ddi_intr_add_handler(pcieb->pcieb_htable[count], 1010 pcieb_intr_handler, (caddr_t)pcieb, 1011 (caddr_t)(uintptr_t)(inum + count)); 1012 1013 if (ret != DDI_SUCCESS) { 1014 PCIEB_DEBUG(DBG_ATTACH, dip, "Cannot add " 1015 "interrupt(%d)\n", ret); 1016 break; 1017 } 1018 } 1019 1020 /* If unsucessful, remove the added handlers */ 1021 if (ret != DDI_SUCCESS) { 1022 for (x = 0; x < count; x++) { 1023 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]); 1024 } 1025 goto FAIL; 1026 } 1027 1028 pcieb->pcieb_init_flags |= PCIEB_INIT_HANDLER; 1029 1030 (void) ddi_intr_get_cap(pcieb->pcieb_htable[0], &intr_cap); 1031 1032 /* 1033 * Get this intr lock because we are not quite ready to handle 1034 * interrupts immediately after enabling it. The MSI multi register 1035 * gets programmed in ddi_intr_enable after which we need to get the 1036 * MSI offsets for Hotplug/AER. 1037 */ 1038 mutex_enter(&pcieb->pcieb_intr_mutex); 1039 1040 if (intr_cap & DDI_INTR_FLAG_BLOCK) { 1041 (void) ddi_intr_block_enable(pcieb->pcieb_htable, 1042 pcieb->pcieb_intr_count); 1043 pcieb->pcieb_init_flags |= PCIEB_INIT_BLOCK; 1044 } else { 1045 for (count = 0; count < pcieb->pcieb_intr_count; count++) { 1046 (void) ddi_intr_enable(pcieb->pcieb_htable[count]); 1047 } 1048 } 1049 pcieb->pcieb_init_flags |= PCIEB_INIT_ENABLE; 1050 1051 /* Save the interrupt type */ 1052 pcieb->pcieb_intr_type = intr_type; 1053 1054 /* Get the MSI offset for hotplug/PME from the PCIe cap reg */ 1055 if (intr_type == DDI_INTR_TYPE_MSI) { 1056 hp_msi_off = PCI_CAP_GET16(bus_p->bus_cfg_hdl, NULL, 1057 bus_p->bus_pcie_off, PCIE_PCIECAP) & 1058 PCIE_PCIECAP_INT_MSG_NUM; 1059 1060 if (hp_msi_off >= count) { 1061 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in PCIe " 1062 "cap > max allocated %d\n", hp_msi_off, count); 1063 mutex_exit(&pcieb->pcieb_intr_mutex); 1064 goto FAIL; 1065 } 1066 1067 if (is_hp) 1068 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_HP; 1069 1070 if (is_pme) 1071 pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_PME; 1072 } else { 1073 /* INTx handles only Hotplug interrupts */ 1074 if (is_hp) 1075 pcieb->pcieb_isr_tab[0] |= PCIEB_INTR_SRC_HP; 1076 } 1077 1078 1079 /* 1080 * Get the MSI offset for errors from the AER Root Error status 1081 * register. 1082 */ 1083 if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p)) { 1084 if (PCIE_HAS_AER(bus_p)) { 1085 int aer_msi_off; 1086 aer_msi_off = (PCI_XCAP_GET32(bus_p->bus_cfg_hdl, NULL, 1087 bus_p->bus_aer_off, PCIE_AER_RE_STS) >> 1088 PCIE_AER_RE_STS_MSG_NUM_SHIFT) & 1089 PCIE_AER_RE_STS_MSG_NUM_MASK; 1090 1091 if (aer_msi_off >= count) { 1092 PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in" 1093 " AER cap > max allocated %d\n", 1094 aer_msi_off, count); 1095 mutex_exit(&pcieb->pcieb_intr_mutex); 1096 goto FAIL; 1097 } 1098 pcieb->pcieb_isr_tab[aer_msi_off] |= PCIEB_INTR_SRC_AER; 1099 } else { 1100 /* 1101 * This RP does not have AER. Fallback to the 1102 * SERR+Machinecheck approach if available. 1103 */ 1104 pcieb->pcieb_no_aer_msi = B_TRUE; 1105 } 1106 } 1107 1108 mutex_exit(&pcieb->pcieb_intr_mutex); 1109 1110 return (DDI_SUCCESS); 1111 1112 FAIL: 1113 return (DDI_FAILURE); 1114 } 1115 1116 static void 1117 pcieb_intr_fini(pcieb_devstate_t *pcieb) 1118 { 1119 int x; 1120 int count = pcieb->pcieb_intr_count; 1121 int flags = pcieb->pcieb_init_flags; 1122 1123 if ((flags & PCIEB_INIT_ENABLE) && 1124 (flags & PCIEB_INIT_BLOCK)) { 1125 (void) ddi_intr_block_disable(pcieb->pcieb_htable, count); 1126 flags &= ~(PCIEB_INIT_ENABLE | 1127 PCIEB_INIT_BLOCK); 1128 } 1129 1130 if (flags & PCIEB_INIT_MUTEX) 1131 mutex_destroy(&pcieb->pcieb_intr_mutex); 1132 1133 for (x = 0; x < count; x++) { 1134 if (flags & PCIEB_INIT_ENABLE) 1135 (void) ddi_intr_disable(pcieb->pcieb_htable[x]); 1136 1137 if (flags & PCIEB_INIT_HANDLER) 1138 (void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]); 1139 1140 if (flags & PCIEB_INIT_ALLOC) 1141 (void) ddi_intr_free(pcieb->pcieb_htable[x]); 1142 } 1143 1144 flags &= ~(PCIEB_INIT_ENABLE | PCIEB_INIT_HANDLER | PCIEB_INIT_ALLOC | 1145 PCIEB_INIT_MUTEX); 1146 1147 if (flags & PCIEB_INIT_HTABLE) 1148 kmem_free(pcieb->pcieb_htable, pcieb->pcieb_htable_size); 1149 1150 flags &= ~PCIEB_INIT_HTABLE; 1151 1152 pcieb->pcieb_init_flags &= flags; 1153 } 1154 1155 /* 1156 * Checks if this device needs MSIs enabled or not. 1157 */ 1158 /*ARGSUSED*/ 1159 static int 1160 pcieb_msi_supported(dev_info_t *dip) 1161 { 1162 return ((pcieb_enable_msi && pcieb_plat_msi_supported(dip)) ? 1163 DDI_SUCCESS: DDI_FAILURE); 1164 } 1165 1166 /*ARGSUSED*/ 1167 int 1168 pcieb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap, 1169 ddi_iblock_cookie_t *ibc) 1170 { 1171 pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, 1172 ddi_get_instance(dip)); 1173 1174 ASSERT(ibc != NULL); 1175 *ibc = pcieb->pcieb_fm_ibc; 1176 1177 return (DEVI(dip)->devi_fmhdl->fh_cap | DDI_FM_ACCCHK_CAPABLE | 1178 DDI_FM_DMACHK_CAPABLE); 1179 } 1180 1181 static int 1182 pcieb_fm_init(pcieb_devstate_t *pcieb_p) 1183 { 1184 dev_info_t *dip = pcieb_p->pcieb_dip; 1185 int fm_cap = DDI_FM_EREPORT_CAPABLE; 1186 1187 /* 1188 * Request our capability level and get our parents capability 1189 * and ibc. 1190 */ 1191 ddi_fm_init(dip, &fm_cap, &pcieb_p->pcieb_fm_ibc); 1192 1193 return (DDI_SUCCESS); 1194 } 1195 1196 /* 1197 * Breakdown our FMA resources 1198 */ 1199 static void 1200 pcieb_fm_fini(pcieb_devstate_t *pcieb_p) 1201 { 1202 /* 1203 * Clean up allocated fm structures 1204 */ 1205 ddi_fm_fini(pcieb_p->pcieb_dip); 1206 } 1207 1208 static int 1209 pcieb_open(dev_t *devp, int flags, int otyp, cred_t *credp) 1210 { 1211 pcieb_devstate_t *pcieb_p; 1212 minor_t minor = getminor(*devp); 1213 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1214 1215 /* 1216 * Make sure the open is for the right file type. 1217 */ 1218 if (otyp != OTYP_CHR) 1219 return (EINVAL); 1220 1221 /* 1222 * Get the soft state structure for the device. 1223 */ 1224 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1225 instance); 1226 1227 if (pcieb_p == NULL) 1228 return (ENXIO); 1229 1230 if (pcieb_p->pcieb_hotplug_capable == B_TRUE) 1231 return ((pcihp_get_cb_ops())->cb_open(devp, flags, 1232 otyp, credp)); 1233 1234 /* 1235 * Handle the open by tracking the device state. 1236 */ 1237 mutex_enter(&pcieb_p->pcieb_mutex); 1238 if (flags & FEXCL) { 1239 if (pcieb_p->pcieb_soft_state != PCIEB_SOFT_STATE_CLOSED) { 1240 mutex_exit(&pcieb_p->pcieb_mutex); 1241 return (EBUSY); 1242 } 1243 pcieb_p->pcieb_soft_state = PCIEB_SOFT_STATE_OPEN_EXCL; 1244 } else { 1245 if (pcieb_p->pcieb_soft_state == PCIEB_SOFT_STATE_OPEN_EXCL) { 1246 mutex_exit(&pcieb_p->pcieb_mutex); 1247 return (EBUSY); 1248 } 1249 pcieb_p->pcieb_soft_state = PCIEB_SOFT_STATE_OPEN; 1250 } 1251 mutex_exit(&pcieb_p->pcieb_mutex); 1252 return (0); 1253 } 1254 1255 static int 1256 pcieb_close(dev_t dev, int flags, int otyp, cred_t *credp) 1257 { 1258 pcieb_devstate_t *pcieb_p; 1259 minor_t minor = getminor(dev); 1260 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1261 1262 if (otyp != OTYP_CHR) 1263 return (EINVAL); 1264 1265 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1266 instance); 1267 1268 if (pcieb_p == NULL) 1269 return (ENXIO); 1270 1271 if (pcieb_p->pcieb_hotplug_capable == B_TRUE) 1272 return ((pcihp_get_cb_ops())->cb_close(dev, flags, 1273 otyp, credp)); 1274 1275 mutex_enter(&pcieb_p->pcieb_mutex); 1276 pcieb_p->pcieb_soft_state = PCIEB_SOFT_STATE_CLOSED; 1277 mutex_exit(&pcieb_p->pcieb_mutex); 1278 return (0); 1279 } 1280 1281 static int 1282 pcieb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 1283 int *rvalp) 1284 { 1285 pcieb_devstate_t *pcieb_p; 1286 dev_info_t *self; 1287 struct devctl_iocdata *dcp; 1288 uint_t bus_state; 1289 int rv = 0; 1290 minor_t minor = getminor(dev); 1291 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1292 1293 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1294 instance); 1295 1296 if (pcieb_p == NULL) 1297 return (ENXIO); 1298 1299 self = pcieb_p->pcieb_dip; 1300 if (pcieb_p->pcieb_hotplug_capable == B_TRUE) { 1301 rv = ((pcihp_get_cb_ops())->cb_ioctl(dev, cmd, 1302 arg, mode, credp, rvalp)); 1303 1304 pcieb_plat_ioctl_hotplug(self, rv, cmd); 1305 return (rv); 1306 } 1307 1308 /* 1309 * We can use the generic implementation for these ioctls 1310 */ 1311 switch (cmd) { 1312 case DEVCTL_DEVICE_GETSTATE: 1313 case DEVCTL_DEVICE_ONLINE: 1314 case DEVCTL_DEVICE_OFFLINE: 1315 case DEVCTL_BUS_GETSTATE: 1316 return (ndi_devctl_ioctl(self, cmd, arg, mode, 0)); 1317 } 1318 1319 /* 1320 * read devctl ioctl data 1321 */ 1322 if (ndi_dc_allochdl((void *)arg, &dcp) != NDI_SUCCESS) 1323 return (EFAULT); 1324 1325 switch (cmd) { 1326 1327 case DEVCTL_DEVICE_RESET: 1328 rv = ENOTSUP; 1329 break; 1330 1331 case DEVCTL_BUS_QUIESCE: 1332 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1333 if (bus_state == BUS_QUIESCED) 1334 break; 1335 (void) ndi_set_bus_state(self, BUS_QUIESCED); 1336 break; 1337 1338 case DEVCTL_BUS_UNQUIESCE: 1339 if (ndi_get_bus_state(self, &bus_state) == NDI_SUCCESS) 1340 if (bus_state == BUS_ACTIVE) 1341 break; 1342 (void) ndi_set_bus_state(self, BUS_ACTIVE); 1343 break; 1344 1345 case DEVCTL_BUS_RESET: 1346 rv = ENOTSUP; 1347 break; 1348 1349 case DEVCTL_BUS_RESETALL: 1350 rv = ENOTSUP; 1351 break; 1352 1353 default: 1354 rv = ENOTTY; 1355 } 1356 1357 ndi_dc_freehdl(dcp); 1358 return (rv); 1359 } 1360 1361 static int 1362 pcieb_prop_op(dev_t dev, dev_info_t *dip, ddi_prop_op_t prop_op, 1363 int flags, char *name, caddr_t valuep, int *lengthp) 1364 { 1365 pcieb_devstate_t *pcieb_p; 1366 minor_t minor = getminor(dev); 1367 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1368 1369 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1370 instance); 1371 1372 if (pcieb_p == NULL) 1373 return (ENXIO); 1374 1375 if (pcieb_p->pcieb_hotplug_capable == B_TRUE) 1376 return ((pcihp_get_cb_ops())->cb_prop_op(dev, dip, prop_op, 1377 flags, name, valuep, lengthp)); 1378 1379 return (ddi_prop_op(dev, dip, prop_op, flags, name, valuep, lengthp)); 1380 } 1381 1382 /*ARGSUSED*/ 1383 static int 1384 pcieb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result) 1385 { 1386 pcieb_devstate_t *pcieb_p; /* per pcieb state pointer */ 1387 minor_t minor = getminor((dev_t)arg); 1388 int instance = PCIHP_AP_MINOR_NUM_TO_INSTANCE(minor); 1389 1390 pcieb_p = (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state, 1391 instance); 1392 1393 switch (infocmd) { 1394 default: 1395 return (DDI_FAILURE); 1396 1397 case DDI_INFO_DEVT2INSTANCE: 1398 *result = (void *)(intptr_t)instance; 1399 return (DDI_SUCCESS); 1400 1401 case DDI_INFO_DEVT2DEVINFO: 1402 if (pcieb_p == NULL) 1403 return (DDI_FAILURE); 1404 *result = (void *)pcieb_p->pcieb_dip; 1405 return (DDI_SUCCESS); 1406 } 1407 } 1408 1409 /* 1410 * Common interrupt handler for hotplug, PME and errors. 1411 */ 1412 static uint_t 1413 pcieb_intr_handler(caddr_t arg1, caddr_t arg2) 1414 { 1415 pcieb_devstate_t *pcieb_p = (pcieb_devstate_t *)arg1; 1416 dev_info_t *dip = pcieb_p->pcieb_dip; 1417 ddi_fm_error_t derr; 1418 int sts = 0; 1419 int ret = DDI_INTR_UNCLAIMED; 1420 int isrc; 1421 1422 if (!(pcieb_p->pcieb_init_flags & PCIEB_INIT_ENABLE)) 1423 goto FAIL; 1424 1425 mutex_enter(&pcieb_p->pcieb_intr_mutex); 1426 isrc = pcieb_p->pcieb_isr_tab[(int)(uintptr_t)arg2]; 1427 mutex_exit(&pcieb_p->pcieb_intr_mutex); 1428 1429 PCIEB_DEBUG(DBG_INTR, dip, "Received intr number %d\n", 1430 (int)(uintptr_t)arg2); 1431 1432 if (isrc == PCIEB_INTR_SRC_UNKNOWN) 1433 goto FAIL; 1434 1435 if (isrc & PCIEB_INTR_SRC_HP) { 1436 if (pcieb_p->pcieb_hpc_type == HPC_PCIE) 1437 ret = pciehpc_intr(dip); 1438 else if (pcieb_p->pcieb_hpc_type == HPC_SHPC) 1439 ret = pcishpc_intr(dip); 1440 } 1441 1442 if (isrc & PCIEB_INTR_SRC_PME) 1443 ret = DDI_INTR_CLAIMED; 1444 1445 /* AER Error */ 1446 if (isrc & PCIEB_INTR_SRC_AER) { 1447 /* 1448 * If MSI is shared with PME/hotplug then check Root Error 1449 * Status Reg before claiming it. For now it's ok since 1450 * we know we get 2 MSIs. 1451 */ 1452 ret = DDI_INTR_CLAIMED; 1453 bzero(&derr, sizeof (ddi_fm_error_t)); 1454 derr.fme_version = DDI_FME_VERSION; 1455 mutex_enter(&pcieb_p->pcieb_peek_poke_mutex); 1456 mutex_enter(&pcieb_p->pcieb_err_mutex); 1457 1458 if ((DEVI(dip)->devi_fmhdl->fh_cap) & DDI_FM_EREPORT_CAPABLE) 1459 sts = pf_scan_fabric(dip, &derr, NULL); 1460 1461 mutex_exit(&pcieb_p->pcieb_err_mutex); 1462 mutex_exit(&pcieb_p->pcieb_peek_poke_mutex); 1463 if (pcieb_die & sts) 1464 fm_panic("%s-%d: PCI(-X) Express Fatal Error. (0x%x)", 1465 ddi_driver_name(dip), ddi_get_instance(dip), sts); 1466 } 1467 FAIL: 1468 return (ret); 1469 } 1470 1471 /* 1472 * Some PCI-X to PCI-E bridges do not support full 64-bit addressing on the 1473 * PCI-X side of the bridge. We build a special version of this driver for 1474 * those bridges, which uses PCIEB_ADDR_LIMIT_LO and/or PCIEB_ADDR_LIMIT_HI 1475 * to define the range of values which the chip can handle. The code below 1476 * then clamps the DMA address range supplied by the driver, preventing the 1477 * PCI-E nexus driver from allocating any memory the bridge can't deal 1478 * with. 1479 */ 1480 static int 1481 pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, 1482 ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg, 1483 ddi_dma_handle_t *handlep) 1484 { 1485 int ret; 1486 #ifdef BCM_SW_WORKAROUNDS 1487 uint64_t lim; 1488 1489 /* 1490 * If the leaf device's limits are outside than what the Broadcom 1491 * bridge can handle, we need to clip the values passed up the chain. 1492 */ 1493 lim = attr_p->dma_attr_addr_lo; 1494 attr_p->dma_attr_addr_lo = MAX(lim, PCIEB_ADDR_LIMIT_LO); 1495 1496 lim = attr_p->dma_attr_addr_hi; 1497 attr_p->dma_attr_addr_hi = MIN(lim, PCIEB_ADDR_LIMIT_HI); 1498 1499 #endif /* BCM_SW_WORKAROUNDS */ 1500 1501 /* 1502 * This is a software workaround to fix the Broadcom 5714/5715 PCIe-PCI 1503 * bridge prefetch bug. Intercept the DMA alloc handle request and set 1504 * PX_DMAI_FLAGS_MAP_BUFZONE flag in the handle. If this flag is set, 1505 * the px nexus driver will allocate an extra page & make it valid one, 1506 * for any DVMA request that comes from any of the Broadcom bridge child 1507 * devices. 1508 */ 1509 if ((ret = ddi_dma_allochdl(dip, rdip, attr_p, waitfp, arg, 1510 handlep)) == DDI_SUCCESS) { 1511 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*handlep; 1512 #ifdef BCM_SW_WORKAROUNDS 1513 mp->dmai_inuse |= PX_DMAI_FLAGS_MAP_BUFZONE; 1514 #endif /* BCM_SW_WORKAROUNDS */ 1515 /* 1516 * For a given rdip, update mp->dmai_bdf with the bdf value 1517 * of pcieb's immediate child or secondary bus-id of the 1518 * PCIe2PCI bridge. 1519 */ 1520 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip); 1521 } 1522 1523 return (ret); 1524 } 1525 1526 /* 1527 * FDVMA feature is not supported for any child device of Broadcom 5714/5715 1528 * PCIe-PCI bridge due to prefetch bug. Return failure immediately, so that 1529 * these drivers will switch to regular DVMA path. 1530 */ 1531 /*ARGSUSED*/ 1532 static int 1533 pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 1534 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 1535 uint_t cache_flags) 1536 { 1537 int ret; 1538 1539 #ifdef BCM_SW_WORKAROUNDS 1540 if (cmd == DDI_DMA_RESERVE) 1541 return (DDI_FAILURE); 1542 #endif /* BCM_SW_WORKAROUNDS */ 1543 1544 if (((ret = ddi_dma_mctl(dip, rdip, handle, cmd, offp, lenp, objp, 1545 cache_flags)) == DDI_SUCCESS) && (cmd == DDI_DMA_RESERVE)) { 1546 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)*objp; 1547 1548 /* 1549 * For a given rdip, update mp->dmai_bdf with the bdf value 1550 * of pcieb's immediate child or secondary bus-id of the 1551 * PCIe2PCI bridge. 1552 */ 1553 mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip); 1554 } 1555 1556 return (ret); 1557 } 1558 1559 static int 1560 pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 1561 ddi_intr_handle_impl_t *hdlp, void *result) 1562 { 1563 return (pcieb_plat_intr_ops(dip, rdip, intr_op, hdlp, result)); 1564 1565 } 1566 1567 /*ARGSUSED*/ 1568 static int pcieb_pciehpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle) 1569 { 1570 uint16_t cap_ptr; 1571 1572 if ((PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_E, &cap_ptr)) != 1573 DDI_FAILURE) { 1574 uint16_t slotimpl = PCI_CAP_GET16(config_handle, NULL, cap_ptr, 1575 PCIE_PCIECAP) & PCIE_PCIECAP_SLOT_IMPL; 1576 if (slotimpl) 1577 if (PCI_CAP_GET32(config_handle, NULL, cap_ptr, 1578 PCIE_SLOTCAP) & PCIE_SLOTCAP_HP_CAPABLE) 1579 return (DDI_SUCCESS); 1580 } 1581 1582 return (DDI_FAILURE); 1583 } 1584 1585 static int pcieb_pcishpc_probe(dev_info_t *dip, ddi_acc_handle_t config_handle) 1586 { 1587 return (pcieb_plat_pcishpc_probe(dip, config_handle)); 1588 } 1589 1590 /* 1591 * Initialize hotplug framework if we are hotpluggable. 1592 * Sets flag in the soft state if Hot Plug is supported and initialized 1593 * properly. 1594 */ 1595 /*ARGSUSED*/ 1596 static int 1597 pcieb_init_hotplug(pcieb_devstate_t *pcieb) 1598 { 1599 int rv = DDI_FAILURE; 1600 pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip); 1601 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 1602 uint8_t dev_type = bus_p->bus_dev_type; 1603 1604 #ifdef PX_PLX 1605 uint16_t vid = bus_p->bus_dev_ven_id & 0xFFFF; 1606 uint16_t did = bus_p->bus_dev_ven_id >> 16; 1607 if ((vid == PXB_VENDOR_PLX) && (did == PXB_DEVICE_PLX_8532) && 1608 (bus_p->bus_rev_id <= PXB_DEVICE_PLX_AA_REV)) 1609 return (DDI_SUCCESS); 1610 #endif /* PX_PLX */ 1611 1612 if (((dev_type == PCIE_PCIECAP_DEV_TYPE_DOWN) || 1613 (dev_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE) || 1614 (dev_type == PCIE_PCIECAP_DEV_TYPE_ROOT)) && 1615 (pcieb_pciehpc_probe(pcieb->pcieb_dip, 1616 config_handle) == DDI_SUCCESS)) { 1617 pcieb->pcieb_hpc_type = HPC_PCIE; 1618 } else if ((dev_type == PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) && 1619 (pcieb_pcishpc_probe(pcieb->pcieb_dip, 1620 config_handle) == DDI_SUCCESS)) { 1621 pcieb->pcieb_hpc_type = HPC_SHPC; 1622 } else { 1623 pcieb->pcieb_hpc_type = HPC_NONE; 1624 return (DDI_SUCCESS); 1625 } 1626 1627 pcieb->pcieb_hotplug_capable = B_TRUE; 1628 1629 if (pcieb->pcieb_hpc_type == HPC_PCIE) 1630 rv = pciehpc_init(pcieb->pcieb_dip, NULL); 1631 else if (pcieb->pcieb_hpc_type == HPC_SHPC) 1632 rv = pcishpc_init(pcieb->pcieb_dip); 1633 1634 if (rv != DDI_SUCCESS) 1635 goto fail; 1636 1637 if (pcihp_init(pcieb->pcieb_dip) != DDI_SUCCESS) { 1638 if (pcieb->pcieb_hpc_type == HPC_PCIE) 1639 (void) pciehpc_uninit(pcieb->pcieb_dip); 1640 else if (pcieb->pcieb_hpc_type == HPC_SHPC) 1641 (void) pcishpc_uninit(pcieb->pcieb_dip); 1642 1643 goto fail; 1644 } 1645 1646 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1647 "hotplug-capable"); 1648 1649 return (DDI_SUCCESS); 1650 1651 fail: 1652 pcieb->pcieb_hpc_type = HPC_NONE; 1653 pcieb->pcieb_hotplug_capable = B_FALSE; 1654 PCIEB_DEBUG(DBG_ATTACH, pcieb->pcieb_dip, "Failed setting hotplug" 1655 " framework\n"); 1656 1657 return (DDI_FAILURE); 1658 } 1659 1660 /* 1661 * Power management related initialization specific to pcieb. 1662 * Called by pcieb_attach() 1663 */ 1664 static int 1665 pcieb_pwr_setup(dev_info_t *dip) 1666 { 1667 char *comp_array[5]; 1668 int i; 1669 ddi_acc_handle_t conf_hdl; 1670 uint16_t pmcap, cap_ptr; 1671 pcie_pwr_t *pwr_p; 1672 1673 /* Some platforms/devices may choose to disable PM */ 1674 if (pcieb_plat_pwr_disable(dip)) { 1675 (void) pcieb_pwr_disable(dip); 1676 return (DDI_SUCCESS); 1677 } 1678 1679 ASSERT(PCIE_PMINFO(dip)); 1680 pwr_p = PCIE_NEXUS_PMINFO(dip); 1681 ASSERT(pwr_p); 1682 1683 /* Code taken from pci_pci driver */ 1684 if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) { 1685 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: pci_config_setup " 1686 "failed\n"); 1687 return (DDI_FAILURE); 1688 } 1689 conf_hdl = pwr_p->pwr_conf_hdl; 1690 1691 /* 1692 * Walk the capabilities searching for a PM entry. 1693 */ 1694 if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &cap_ptr)) == 1695 DDI_FAILURE) { 1696 PCIEB_DEBUG(DBG_PWR, dip, "switch/bridge does not support PM. " 1697 " PCI PM data structure not found in config header\n"); 1698 pci_config_teardown(&conf_hdl); 1699 return (DDI_SUCCESS); 1700 } 1701 /* 1702 * Save offset to pmcsr for future references. 1703 */ 1704 pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR; 1705 pmcap = PCI_CAP_GET16(conf_hdl, NULL, cap_ptr, PCI_PMCAP); 1706 if (pmcap & PCI_PMCAP_D1) { 1707 PCIEB_DEBUG(DBG_PWR, dip, "D1 state supported\n"); 1708 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1; 1709 } 1710 if (pmcap & PCI_PMCAP_D2) { 1711 PCIEB_DEBUG(DBG_PWR, dip, "D2 state supported\n"); 1712 pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2; 1713 } 1714 1715 i = 0; 1716 comp_array[i++] = "NAME=PCIe switch/bridge PM"; 1717 comp_array[i++] = "0=Power Off (D3)"; 1718 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D2) 1719 comp_array[i++] = "1=D2"; 1720 if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D1) 1721 comp_array[i++] = "2=D1"; 1722 comp_array[i++] = "3=Full Power D0"; 1723 1724 /* 1725 * Create pm-components property, if it does not exist already. 1726 */ 1727 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 1728 "pm-components", comp_array, i) != DDI_PROP_SUCCESS) { 1729 PCIEB_DEBUG(DBG_PWR, dip, "could not create pm-components " 1730 " prop\n"); 1731 pci_config_teardown(&conf_hdl); 1732 return (DDI_FAILURE); 1733 } 1734 return (pcieb_pwr_init_and_raise(dip, pwr_p)); 1735 } 1736 1737 /* 1738 * undo whatever is done in pcieb_pwr_setup. called by pcieb_detach() 1739 */ 1740 static void 1741 pcieb_pwr_teardown(dev_info_t *dip) 1742 { 1743 pcie_pwr_t *pwr_p; 1744 1745 if (!PCIE_PMINFO(dip) || !(pwr_p = PCIE_NEXUS_PMINFO(dip))) 1746 return; 1747 1748 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 1749 if (pwr_p->pwr_conf_hdl) 1750 pci_config_teardown(&pwr_p->pwr_conf_hdl); 1751 } 1752 1753 /* 1754 * Initializes the power level and raise the power to D0, if it is 1755 * not at D0. 1756 */ 1757 static int 1758 pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p) 1759 { 1760 uint16_t pmcsr; 1761 int ret = DDI_SUCCESS; 1762 1763 /* 1764 * Intialize our power level from PMCSR. The common code initializes 1765 * this to UNKNOWN. There is no guarantee that we will be at full 1766 * power at attach. If we are not at D0, raise the power. 1767 */ 1768 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, pwr_p->pwr_pmcsr_offset); 1769 pmcsr &= PCI_PMCSR_STATE_MASK; 1770 switch (pmcsr) { 1771 case PCI_PMCSR_D0: 1772 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1773 break; 1774 1775 case PCI_PMCSR_D1: 1776 pwr_p->pwr_func_lvl = PM_LEVEL_D1; 1777 break; 1778 1779 case PCI_PMCSR_D2: 1780 pwr_p->pwr_func_lvl = PM_LEVEL_D2; 1781 break; 1782 1783 case PCI_PMCSR_D3HOT: 1784 pwr_p->pwr_func_lvl = PM_LEVEL_D3; 1785 break; 1786 1787 default: 1788 break; 1789 } 1790 1791 /* Raise the power to D0. */ 1792 if (pwr_p->pwr_func_lvl != PM_LEVEL_D0 && 1793 ((ret = pm_raise_power(dip, 0, PM_LEVEL_D0)) != DDI_SUCCESS)) { 1794 /* 1795 * Read PMCSR again. If it is at D0, ignore the return 1796 * value from pm_raise_power. 1797 */ 1798 pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, 1799 pwr_p->pwr_pmcsr_offset); 1800 if ((pmcsr & PCI_PMCSR_STATE_MASK) == PCI_PMCSR_D0) 1801 ret = DDI_SUCCESS; 1802 else { 1803 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: could not " 1804 "raise power to D0 \n"); 1805 } 1806 } 1807 if (ret == DDI_SUCCESS) 1808 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1809 return (ret); 1810 } 1811 1812 /* 1813 * Disable PM for x86 and PLX 8532 switch. 1814 * For PLX Transitioning one port on this switch to low power causes links 1815 * on other ports on the same station to die. Due to PLX erratum #34, we 1816 * can't allow the downstream device go to non-D0 state. 1817 */ 1818 static int 1819 pcieb_pwr_disable(dev_info_t *dip) 1820 { 1821 pcie_pwr_t *pwr_p; 1822 1823 ASSERT(PCIE_PMINFO(dip)); 1824 pwr_p = PCIE_NEXUS_PMINFO(dip); 1825 ASSERT(pwr_p); 1826 PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_disable: disabling PM\n"); 1827 pwr_p->pwr_func_lvl = PM_LEVEL_D0; 1828 pwr_p->pwr_flags = PCIE_NO_CHILD_PM; 1829 return (DDI_SUCCESS); 1830 } 1831 1832 #ifdef DEBUG 1833 int pcieb_dbg_intr_print = 0; 1834 void 1835 pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...) 1836 { 1837 va_list ap; 1838 1839 if (!pcieb_dbg_print) 1840 return; 1841 1842 if (dip) 1843 prom_printf("%s(%d): %s", ddi_driver_name(dip), 1844 ddi_get_instance(dip), pcieb_debug_sym[bit]); 1845 1846 va_start(ap, fmt); 1847 if (servicing_interrupt()) { 1848 if (pcieb_dbg_intr_print) 1849 prom_vprintf(fmt, ap); 1850 } else { 1851 prom_vprintf(fmt, ap); 1852 } 1853 1854 va_end(ap); 1855 } 1856 #endif 1857 1858 static void 1859 pcieb_id_props(pcieb_devstate_t *pcieb) 1860 { 1861 uint64_t serialid = 0; /* 40b field of EUI-64 serial no. register */ 1862 uint16_t cap_ptr; 1863 uint8_t fic = 0; /* 1 = first in chassis device */ 1864 pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip); 1865 ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl; 1866 1867 /* 1868 * Identify first in chassis. In the special case of a Sun branded 1869 * PLX device, it obviously is first in chassis. Otherwise, in the 1870 * general case, look for an Expansion Slot Register and check its 1871 * first-in-chassis bit. 1872 */ 1873 #ifdef PX_PLX 1874 uint16_t vendor_id = bus_p->bus_dev_ven_id & 0xFFFF; 1875 uint16_t device_id = bus_p->bus_dev_ven_id >> 16; 1876 if ((vendor_id == PXB_VENDOR_SUN) && 1877 ((device_id == PXB_DEVICE_PLX_PCIX) || 1878 (device_id == PXB_DEVICE_PLX_PCIE))) { 1879 fic = 1; 1880 } 1881 #endif /* PX_PLX */ 1882 if ((fic == 0) && ((PCI_CAP_LOCATE(config_handle, 1883 PCI_CAP_ID_SLOT_ID, &cap_ptr)) != DDI_FAILURE)) { 1884 uint8_t esr = PCI_CAP_GET8(config_handle, NULL, 1885 cap_ptr, PCI_CAP_ID_REGS_OFF); 1886 if (PCI_CAPSLOT_FIC(esr)) 1887 fic = 1; 1888 } 1889 1890 if ((PCI_CAP_LOCATE(config_handle, 1891 PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_SER), &cap_ptr)) != DDI_FAILURE) { 1892 /* Serialid can be 0 thru a full 40b number */ 1893 serialid = PCI_XCAP_GET32(config_handle, NULL, 1894 cap_ptr, PCIE_SER_SID_UPPER_DW); 1895 serialid <<= 32; 1896 serialid |= PCI_XCAP_GET32(config_handle, NULL, 1897 cap_ptr, PCIE_SER_SID_LOWER_DW); 1898 } 1899 1900 if (fic) 1901 (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1902 "first-in-chassis"); 1903 if (serialid) 1904 (void) ddi_prop_update_int64(DDI_DEV_T_NONE, pcieb->pcieb_dip, 1905 "serialid#", serialid); 1906 } 1907 1908 static void 1909 pcieb_create_ranges_prop(dev_info_t *dip, 1910 ddi_acc_handle_t config_handle) 1911 { 1912 uint32_t base, limit; 1913 pcieb_ranges_t ranges[PCIEB_RANGE_LEN]; 1914 uint8_t io_base_lo, io_limit_lo; 1915 uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit; 1916 int i = 0, rangelen = sizeof (pcieb_ranges_t)/sizeof (int); 1917 1918 io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW); 1919 io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW); 1920 io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI); 1921 io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI); 1922 mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE); 1923 mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT); 1924 1925 /* 1926 * Create ranges for IO space 1927 */ 1928 ranges[i].size_low = ranges[i].size_high = 0; 1929 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0; 1930 ranges[i].child_high = ranges[i].parent_high |= 1931 (PCI_REG_REL_M | PCI_ADDR_IO); 1932 base = PCIEB_16bit_IOADDR(io_base_lo); 1933 limit = PCIEB_16bit_IOADDR(io_limit_lo); 1934 1935 if ((io_base_lo & 0xf) == PCIEB_32BIT_IO) { 1936 base = PCIEB_LADDR(base, io_base_hi); 1937 } 1938 if ((io_limit_lo & 0xf) == PCIEB_32BIT_IO) { 1939 limit = PCIEB_LADDR(limit, io_limit_hi); 1940 } 1941 1942 if ((io_base_lo & PCIEB_32BIT_IO) && (io_limit_hi > 0)) { 1943 base = PCIEB_LADDR(base, io_base_hi); 1944 limit = PCIEB_LADDR(limit, io_limit_hi); 1945 } 1946 1947 /* 1948 * Create ranges for 32bit memory space 1949 */ 1950 base = PCIEB_32bit_MEMADDR(mem_base); 1951 limit = PCIEB_32bit_MEMADDR(mem_limit); 1952 ranges[i].size_low = ranges[i].size_high = 0; 1953 ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0; 1954 ranges[i].child_high = ranges[i].parent_high |= 1955 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1956 ranges[i].child_low = ranges[i].parent_low = base; 1957 if (limit >= base) { 1958 ranges[i].size_low = limit - base + PCIEB_MEMGRAIN; 1959 i++; 1960 } 1961 1962 if (i) { 1963 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 1964 (int *)ranges, i * rangelen); 1965 } 1966 } 1967 1968 /* 1969 * For PCI and PCI-X devices including PCIe2PCI bridge, initialize 1970 * cache-line-size and latency timer configuration registers. 1971 */ 1972 void 1973 pcieb_set_pci_perf_parameters(dev_info_t *dip, ddi_acc_handle_t cfg_hdl) 1974 { 1975 uint_t n; 1976 1977 /* Initialize cache-line-size configuration register if needed */ 1978 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1979 "cache-line-size", 0) == 0) { 1980 pci_config_put8(cfg_hdl, PCI_CONF_CACHE_LINESZ, 1981 PCIEB_CACHE_LINE_SIZE); 1982 n = pci_config_get8(cfg_hdl, PCI_CONF_CACHE_LINESZ); 1983 if (n != 0) { 1984 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 1985 "cache-line-size", n); 1986 } 1987 } 1988 1989 /* Initialize latency timer configuration registers if needed */ 1990 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1991 "latency-timer", 0) == 0) { 1992 uchar_t min_gnt, latency_timer; 1993 uchar_t header_type; 1994 1995 /* Determine the configuration header type */ 1996 header_type = pci_config_get8(cfg_hdl, PCI_CONF_HEADER); 1997 1998 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) { 1999 latency_timer = PCIEB_LATENCY_TIMER; 2000 pci_config_put8(cfg_hdl, PCI_BCNF_LATENCY_TIMER, 2001 latency_timer); 2002 } else { 2003 min_gnt = pci_config_get8(cfg_hdl, PCI_CONF_MIN_G); 2004 latency_timer = min_gnt * 8; 2005 } 2006 2007 pci_config_put8(cfg_hdl, PCI_CONF_LATENCY_TIMER, 2008 latency_timer); 2009 n = pci_config_get8(cfg_hdl, PCI_CONF_LATENCY_TIMER); 2010 if (n != 0) { 2011 (void) ndi_prop_update_int(DDI_DEV_T_NONE, dip, 2012 "latency-timer", n); 2013 } 2014 } 2015 } 2016