1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * PCIC device/interrupt handler 29 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 30 * and Toshiba (and possibly other clones) PCMCIA adapter chip 31 * sets. It implements a subset of Socket Services as defined 32 * in the Solaris PCMCIA design documents 33 */ 34 35 /* 36 * currently defined "properties" 37 * 38 * clock-frequency bus clock frequency 39 * smi system management interrupt override 40 * need-mult-irq need status IRQ for each pair of sockets 41 * disable-audio don't route audio signal to speaker 42 */ 43 44 45 #include <sys/types.h> 46 #include <sys/inttypes.h> 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/user.h> 50 #include <sys/buf.h> 51 #include <sys/file.h> 52 #include <sys/uio.h> 53 #include <sys/conf.h> 54 #include <sys/stat.h> 55 #include <sys/autoconf.h> 56 #include <sys/vtoc.h> 57 #include <sys/dkio.h> 58 #include <sys/ddi.h> 59 #include <sys/sunddi.h> 60 #include <sys/sunndi.h> 61 #include <sys/var.h> 62 #include <sys/callb.h> 63 #include <sys/open.h> 64 #include <sys/ddidmareq.h> 65 #include <sys/dma_engine.h> 66 #include <sys/kstat.h> 67 #include <sys/kmem.h> 68 #include <sys/modctl.h> 69 #include <sys/pci.h> 70 #include <sys/pci_impl.h> 71 72 #include <sys/pctypes.h> 73 #include <sys/pcmcia.h> 74 #include <sys/sservice.h> 75 76 #include <sys/note.h> 77 78 #include <sys/pcic_reg.h> 79 #include <sys/pcic_var.h> 80 81 #if defined(__i386) || defined(__amd64) 82 #include <sys/pci_cfgspace.h> 83 #endif 84 85 #if defined(__sparc) 86 #include <sys/pci/pci_nexus.h> 87 #endif 88 89 #include <sys/hotplug/hpcsvc.h> 90 #include "cardbus/cardbus.h" 91 92 #define SOFTC_SIZE (sizeof (anp_t)) 93 94 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 95 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 96 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 97 static uint_t pcic_intr(caddr_t, caddr_t); 98 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 99 static int pcic_probe(dev_info_t *); 100 101 static int pcic_open(dev_t *, int, int, cred_t *); 102 static int pcic_close(dev_t, int, int, cred_t *); 103 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 104 105 typedef struct pcm_regs pcm_regs_t; 106 107 static void pcic_init_assigned(dev_info_t *); 108 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 109 pci_regspec_t *, int); 110 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 111 112 /* 113 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 114 * are xlated into DMA ctlops. To make this nexus work on x86, we 115 * need to have the default ddi_dma_mctl ctlops in the bus_ops 116 * structure, just to pass the request to the parent. The correct 117 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 118 */ 119 static 120 struct bus_ops pcmciabus_ops = { 121 BUSO_REV, 122 pcmcia_bus_map, 123 NULL, 124 NULL, 125 NULL, 126 i_ddi_map_fault, 127 ddi_no_dma_map, 128 ddi_no_dma_allochdl, 129 ddi_no_dma_freehdl, 130 ddi_no_dma_bindhdl, 131 ddi_no_dma_unbindhdl, 132 ddi_no_dma_flush, 133 ddi_no_dma_win, 134 ddi_dma_mctl, 135 pcmcia_ctlops, 136 pcmcia_prop_op, 137 NULL, /* (*bus_get_eventcookie)(); */ 138 NULL, /* (*bus_add_eventcall)(); */ 139 NULL, /* (*bus_remove_eventcall)(); */ 140 NULL, /* (*bus_post_event)(); */ 141 NULL, /* (*bus_intr_ctl)(); */ 142 NULL, /* (*bus_config)(); */ 143 NULL, /* (*bus_unconfig)(); */ 144 NULL, /* (*bus_fm_init)(); */ 145 NULL, /* (*bus_fm_fini)(); */ 146 NULL, /* (*bus_enter)() */ 147 NULL, /* (*bus_exit)() */ 148 NULL, /* (*bus_power)() */ 149 pcmcia_intr_ops /* (*bus_intr_op)(); */ 150 }; 151 152 static struct cb_ops pcic_cbops = { 153 pcic_open, 154 pcic_close, 155 nodev, 156 nodev, 157 nodev, 158 nodev, 159 nodev, 160 pcic_ioctl, 161 nodev, 162 nodev, 163 nodev, 164 nochpoll, 165 ddi_prop_op, 166 NULL, 167 #ifdef CARDBUS 168 D_NEW | D_MP | D_HOTPLUG 169 #else 170 D_NEW | D_MP 171 #endif 172 }; 173 174 static struct dev_ops pcic_devops = { 175 DEVO_REV, 176 0, 177 pcic_getinfo, 178 nulldev, 179 pcic_probe, 180 pcic_attach, 181 pcic_detach, 182 nulldev, 183 &pcic_cbops, 184 &pcmciabus_ops, 185 NULL 186 }; 187 188 void *pcic_soft_state_p = NULL; 189 static int pcic_maxinst = -1; 190 191 int pcic_do_insertion = 1; 192 int pcic_do_removal = 1; 193 194 struct irqmap { 195 int irq; 196 int count; 197 } pcic_irq_map[16]; 198 199 200 int pcic_debug = 0x0; 201 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 202 extern void cardbus_dump_pci_config(dev_info_t *dip); 203 extern void cardbus_dump_socket(dev_info_t *dip); 204 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 205 static void pcic_dump_debqueue(char *msg); 206 207 #if defined(PCIC_DEBUG) 208 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 209 210 #define pcic_mutex_enter(a) \ 211 { \ 212 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 213 mutex_enter(a); \ 214 }; 215 216 #define pcic_mutex_exit(a) \ 217 { \ 218 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 219 mutex_exit(a); \ 220 }; 221 222 #else 223 #define pcic_mutex_enter(a) mutex_enter(a) 224 #define pcic_mutex_exit(a) mutex_exit(a) 225 #endif 226 227 #define PCIC_VCC_3VLEVEL 1 228 #define PCIC_VCC_5VLEVEL 2 229 #define PCIC_VCC_12LEVEL 3 230 231 /* bit patterns to select voltage levels */ 232 int pcic_vpp_levels[13] = { 233 0, 0, 0, 234 1, /* 3.3V */ 235 0, 236 1, /* 5V */ 237 0, 0, 0, 0, 0, 0, 238 2 /* 12V */ 239 }; 240 241 uint8_t pcic_cbv_levels[13] = { 242 0, 0, 0, 243 3, /* 3.3V */ 244 0, 245 2, /* 5V */ 246 0, 0, 0, 0, 0, 0, 247 1 /* 12V */ 248 }; 249 250 struct power_entry pcic_power[4] = { 251 { 252 0, VCC|VPP1|VPP2 253 }, 254 { 255 33, /* 3.3Volt */ 256 VCC|VPP1|VPP2 257 }, 258 { 259 5*10, /* 5Volt */ 260 VCC|VPP1|VPP2 /* currently only know about this */ 261 }, 262 { 263 12*10, /* 12Volt */ 264 VPP1|VPP2 265 } 266 }; 267 268 /* 269 * Base used to allocate ranges of PCI memory on x86 systems 270 * Each instance gets a chunk above the base that is used to map 271 * in the memory and I/O windows for that device. 272 * Pages below the base are also allocated for the EXCA registers, 273 * one per instance. 274 */ 275 #define PCIC_PCI_MEMCHUNK 0x1000000 276 277 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 278 static int pcic_debounce_time = 200000; /* In micro-seconds */ 279 280 struct debounce { 281 pcic_socket_t *pcs; 282 clock_t expire; 283 struct debounce *next; 284 }; 285 286 static struct debounce *pcic_deb_queue = NULL; 287 static kmutex_t pcic_deb_mtx; 288 static kcondvar_t pcic_deb_cv; 289 static kthread_t *pcic_deb_threadid; 290 291 static inthandler_t *pcic_handlers; 292 293 static void pcic_setup_adapter(pcicdev_t *); 294 static int pcic_change(pcicdev_t *, int); 295 static int pcic_ll_reset(pcicdev_t *, int); 296 static void pcic_mswait(pcicdev_t *, int, int); 297 static boolean_t pcic_check_ready(pcicdev_t *, int); 298 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 299 static void pcic_ready_wait(pcicdev_t *, int); 300 extern int pcmcia_get_intr(dev_info_t *, int); 301 extern int pcmcia_return_intr(dev_info_t *, int); 302 extern void pcmcia_cb_suspended(int); 303 extern void pcmcia_cb_resumed(int); 304 305 static int pcic_callback(dev_info_t *, int (*)(), int); 306 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 307 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 308 static int pcic_get_page(dev_info_t *, get_page_t *); 309 static int pcic_get_socket(dev_info_t *, get_socket_t *); 310 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 311 static int pcic_get_window(dev_info_t *, get_window_t *); 312 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 313 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 314 static int pcic_reset_socket(dev_info_t *, int, int); 315 static int pcic_set_page(dev_info_t *, set_page_t *); 316 static int pcic_set_window(dev_info_t *, set_window_t *); 317 static int pcic_set_socket(dev_info_t *, set_socket_t *); 318 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 319 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 320 static void pcic_pm_detection(void *); 321 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 322 static int clext_reg_read(pcicdev_t *, int, uchar_t); 323 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 324 static int pcic_calc_speed(pcicdev_t *, uint32_t); 325 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 326 static int pcic_find_pci_type(pcicdev_t *); 327 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 328 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 329 static uint_t pcic_cd_softint(caddr_t, caddr_t); 330 static uint8_t pcic_getb(pcicdev_t *, int, int); 331 static void pcic_putb(pcicdev_t *, int, int, int8_t); 332 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 333 static uint_t pcic_softintr(caddr_t, caddr_t); 334 335 static void pcic_debounce(pcic_socket_t *); 336 static void pcic_do_resume(pcicdev_t *); 337 static void *pcic_add_debqueue(pcic_socket_t *, int); 338 static void pcic_rm_debqueue(void *); 339 static void pcic_deb_thread(); 340 341 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 342 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 343 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 344 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 345 static void pcic_cb_enable_intr(dev_info_t *); 346 static void pcic_cb_disable_intr(dev_info_t *); 347 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 348 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 349 350 static cb_nexus_cb_t pcic_cbnexus_ops = { 351 pcic_cb_enable_intr, 352 pcic_cb_disable_intr 353 }; 354 355 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 356 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 357 358 #if defined(__sparc) 359 static int pcic_fault(enum pci_fault_ops op, void *arg); 360 #endif 361 362 363 /* 364 * pcmcia interface operations structure 365 * this is the private interface that is exported to the nexus 366 */ 367 pcmcia_if_t pcic_if_ops = { 368 PCIF_MAGIC, 369 PCIF_VERSION, 370 pcic_callback, 371 pcic_get_adapter, 372 pcic_get_page, 373 pcic_get_socket, 374 pcic_get_status, 375 pcic_get_window, 376 pcic_inquire_adapter, 377 pcic_inquire_socket, 378 pcic_inquire_window, 379 pcic_reset_socket, 380 pcic_set_page, 381 pcic_set_window, 382 pcic_set_socket, 383 pcic_set_interrupt, 384 pcic_clear_interrupt, 385 NULL, 386 }; 387 388 /* 389 * chip type identification routines 390 * this list of functions is searched until one of them succeeds 391 * or all fail. i82365SL is assumed if failed. 392 */ 393 static int pcic_ci_cirrus(pcicdev_t *); 394 static int pcic_ci_vadem(pcicdev_t *); 395 static int pcic_ci_ricoh(pcicdev_t *); 396 397 int (*pcic_ci_funcs[])(pcicdev_t *) = { 398 pcic_ci_cirrus, 399 pcic_ci_vadem, 400 pcic_ci_ricoh, 401 NULL 402 }; 403 404 static struct modldrv modldrv = { 405 &mod_driverops, /* Type of module. This one is a driver */ 406 "PCIC PCMCIA adapter driver", /* Name of the module. */ 407 &pcic_devops, /* driver ops */ 408 }; 409 410 static struct modlinkage modlinkage = { 411 MODREV_1, (void *)&modldrv, NULL 412 }; 413 414 int 415 _init() 416 { 417 int stat; 418 419 /* Allocate soft state */ 420 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 421 SOFTC_SIZE, 2)) != DDI_SUCCESS) 422 return (stat); 423 424 if ((stat = mod_install(&modlinkage)) != 0) 425 ddi_soft_state_fini(&pcic_soft_state_p); 426 427 return (stat); 428 } 429 430 int 431 _fini() 432 { 433 int stat = 0; 434 435 if ((stat = mod_remove(&modlinkage)) != 0) 436 return (stat); 437 438 if (pcic_deb_threadid) { 439 mutex_enter(&pcic_deb_mtx); 440 pcic_deb_threadid = 0; 441 while (!pcic_deb_threadid) 442 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 443 pcic_deb_threadid = 0; 444 mutex_exit(&pcic_deb_mtx); 445 446 mutex_destroy(&pcic_deb_mtx); 447 cv_destroy(&pcic_deb_cv); 448 } 449 450 ddi_soft_state_fini(&pcic_soft_state_p); 451 452 return (stat); 453 } 454 455 int 456 _info(struct modinfo *modinfop) 457 { 458 return (mod_info(&modlinkage, modinfop)); 459 } 460 461 /* 462 * pcic_getinfo() 463 * provide instance/device information about driver 464 */ 465 /*ARGSUSED*/ 466 static int 467 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 468 { 469 anp_t *anp; 470 int error = DDI_SUCCESS; 471 minor_t minor; 472 473 switch (cmd) { 474 case DDI_INFO_DEVT2DEVINFO: 475 minor = getminor((dev_t)arg); 476 minor &= 0x7f; 477 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 478 *result = NULL; 479 else 480 *result = anp->an_dip; 481 break; 482 case DDI_INFO_DEVT2INSTANCE: 483 minor = getminor((dev_t)arg); 484 minor &= 0x7f; 485 *result = (void *)((long)minor); 486 break; 487 default: 488 error = DDI_FAILURE; 489 break; 490 } 491 return (error); 492 } 493 494 static int 495 pcic_probe(dev_info_t *dip) 496 { 497 int value; 498 ddi_device_acc_attr_t attr; 499 ddi_acc_handle_t handle; 500 uchar_t *index, *data; 501 502 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 503 return (DDI_PROBE_DONTCARE); 504 505 /* 506 * find a PCIC device (any vendor) 507 * while there can be up to 4 such devices in 508 * a system, we currently only look for 1 509 * per probe. There will be up to 2 chips per 510 * instance since they share I/O space 511 */ 512 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 513 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 514 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 515 516 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 517 (caddr_t *)&index, 518 PCIC_ISA_CONTROL_REG_OFFSET, 519 PCIC_ISA_CONTROL_REG_LENGTH, 520 &attr, &handle) != DDI_SUCCESS) 521 return (DDI_PROBE_FAILURE); 522 523 data = index + 1; 524 525 #if defined(PCIC_DEBUG) 526 if (pcic_debug) 527 cmn_err(CE_CONT, "pcic_probe: entered\n"); 528 if (pcic_debug) 529 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 530 #endif 531 ddi_put8(handle, index, PCIC_CHIP_REVISION); 532 ddi_put8(handle, data, 0); 533 value = ddi_get8(handle, data); 534 #if defined(PCIC_DEBUG) 535 if (pcic_debug) 536 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 537 #endif 538 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 539 (value & 0x30) == 0) { 540 /* 541 * we probably have a PCIC chip in the system 542 * do a little more checking. If we find one, 543 * reset everything in case of softboot 544 */ 545 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 546 ddi_put8(handle, data, 0); 547 value = ddi_get8(handle, data); 548 #if defined(PCIC_DEBUG) 549 if (pcic_debug) 550 cmn_err(CE_CONT, "\tzero test = %x\n", value); 551 #endif 552 /* should read back as zero */ 553 if (value == 0) { 554 /* 555 * we do have one and it is off the bus 556 */ 557 #if defined(PCIC_DEBUG) 558 if (pcic_debug) 559 cmn_err(CE_CONT, "pcic_probe: success\n"); 560 #endif 561 ddi_regs_map_free(&handle); 562 return (DDI_PROBE_SUCCESS); 563 } 564 } 565 #if defined(PCIC_DEBUG) 566 if (pcic_debug) 567 cmn_err(CE_CONT, "pcic_probe: failed\n"); 568 #endif 569 ddi_regs_map_free(&handle); 570 return (DDI_PROBE_FAILURE); 571 } 572 573 /* 574 * These are just defaults they can also be changed via a property in the 575 * conf file. 576 */ 577 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 578 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 579 static int pcic_do_pcmcia_sr = 1; 580 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 581 582 /* 583 * enable insertion/removal interrupt for 32bit cards 584 */ 585 static int 586 cardbus_enable_cd_intr(dev_info_t *dip) 587 { 588 ddi_acc_handle_t iohandle; 589 caddr_t ioaddr; 590 ddi_device_acc_attr_t attr; 591 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 592 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 593 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 594 (void) ddi_regs_map_setup(dip, 1, 595 (caddr_t *)&ioaddr, 596 0, 597 4096, 598 &attr, &iohandle); 599 600 /* CSC Interrupt: Card detect interrupt on */ 601 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 602 ddi_get32(iohandle, 603 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 604 605 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 606 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 607 608 ddi_regs_map_free(&iohandle); 609 return (1); 610 } 611 612 /* 613 * pcic_attach() 614 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 615 * to the system. This is a child of "sysbus" since that is where 616 * the hardware lives, but it provides services to the "pcmcia" 617 * nexus driver. It gives a pointer back via its private data 618 * structure which contains both the dip and socket services entry 619 * points 620 */ 621 static int 622 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 623 { 624 anp_t *pcic_nexus; 625 pcicdev_t *pcic; 626 int irqlevel, value; 627 int pci_cfrn, pci_ctrn; 628 int i, j, smi, actual; 629 char *typename; 630 char bus_type[16] = "(unknown)"; 631 int len = sizeof (bus_type); 632 ddi_device_acc_attr_t attr; 633 anp_t *anp = ddi_get_driver_private(dip); 634 uint_t pri; 635 636 #if defined(PCIC_DEBUG) 637 if (pcic_debug) { 638 cmn_err(CE_CONT, "pcic_attach: entered\n"); 639 } 640 #endif 641 switch (cmd) { 642 case DDI_ATTACH: 643 break; 644 case DDI_RESUME: 645 pcic = anp->an_private; 646 /* 647 * for now, this is a simulated resume. 648 * a real one may need different things. 649 */ 650 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 651 mutex_enter(&pcic->pc_lock); 652 /* should probe for new sockets showing up */ 653 pcic_setup_adapter(pcic); 654 pcic->pc_flags &= ~PCF_SUSPENDED; 655 mutex_exit(&pcic->pc_lock); 656 (void) pcmcia_begin_resume(dip); 657 658 pcic_do_resume(pcic); 659 #ifdef CARDBUS 660 cardbus_restore_children(ddi_get_child(dip)); 661 #endif 662 663 /* 664 * for complete implementation need END_RESUME (later) 665 */ 666 return (DDI_SUCCESS); 667 668 } 669 return (DDI_SUCCESS); 670 default: 671 return (DDI_FAILURE); 672 } 673 674 /* 675 * Allocate soft state associated with this instance. 676 */ 677 if (ddi_soft_state_zalloc(pcic_soft_state_p, 678 ddi_get_instance(dip)) != DDI_SUCCESS) { 679 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 680 ddi_get_instance(dip)); 681 return (DDI_FAILURE); 682 } 683 684 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 685 ddi_get_instance(dip)); 686 687 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 688 689 pcic->dip = dip; 690 pcic_nexus->an_dip = dip; 691 pcic_nexus->an_if = &pcic_if_ops; 692 pcic_nexus->an_private = pcic; 693 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 694 pcic->pc_power = pcic_power; 695 696 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 697 "pci-control-reg-number", pci_control_reg_num); 698 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 699 "pci-config-reg-number", pci_config_reg_num); 700 701 ddi_set_driver_private(dip, pcic_nexus); 702 703 /* 704 * pcic->pc_irq is really the IPL level we want to run at 705 * set the default values here and override from intr spec 706 */ 707 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 708 "interrupt-priorities", -1); 709 710 if (pcic->pc_irq == -1) { 711 int actual; 712 uint_t pri; 713 ddi_intr_handle_t hdl; 714 715 /* see if intrspec tells us different */ 716 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 717 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 718 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 719 pcic->pc_irq = pri; 720 else 721 pcic->pc_irq = LOCK_LEVEL + 1; 722 (void) ddi_intr_free(hdl); 723 } 724 } 725 pcic_nexus->an_ipl = pcic->pc_irq; 726 727 /* 728 * Check our parent bus type. We do different things based on which 729 * bus we're on. 730 */ 731 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 732 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 733 "device_type", (caddr_t)&bus_type[0], &len) != 734 DDI_PROP_SUCCESS) { 735 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 736 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 737 "bus-type", (caddr_t)&bus_type[0], &len) != 738 DDI_PROP_SUCCESS) { 739 740 cmn_err(CE_CONT, 741 "pcic%d: can't find parent bus type\n", 742 ddi_get_instance(dip)); 743 744 kmem_free(pcic, sizeof (pcicdev_t)); 745 ddi_soft_state_free(pcic_soft_state_p, 746 ddi_get_instance(dip)); 747 return (DDI_FAILURE); 748 } 749 } /* ddi_prop_op("device_type") */ 750 751 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 752 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0) { 753 pcic->pc_flags = PCF_PCIBUS; 754 } else { 755 cmn_err(CE_WARN, "!pcic%d: non-pci mode (%s) not supported, " 756 "set BIOS to yenta mode if applicable\n", 757 ddi_get_instance(dip), bus_type); 758 kmem_free(pcic, sizeof (pcicdev_t)); 759 ddi_soft_state_free(pcic_soft_state_p, 760 ddi_get_instance(dip)); 761 return (DDI_FAILURE); 762 } 763 764 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 765 DDI_PROP_CANSLEEP, 766 "clock-frequency", 0)) == 0) { 767 if (pcic->pc_flags & PCF_PCIBUS) 768 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 769 else 770 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 771 } else { 772 /* 773 * OBP can declare the speed in Hz... 774 */ 775 if (pcic->bus_speed > 1000000) 776 pcic->bus_speed /= 1000000; 777 } /* ddi_prop_op("clock-frequency") */ 778 779 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 780 781 #ifdef PCIC_DEBUG 782 if (pcic_debug) { 783 cmn_err(CE_CONT, 784 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 785 ddi_get_instance(dip), 786 bus_type, pcic->bus_speed); 787 } 788 #endif 789 790 /* 791 * The reg properties on a PCI node are different than those 792 * on a non-PCI node. Handle that difference here. 793 * If it turns out to be a CardBus chip, we have even more 794 * differences. 795 */ 796 if (pcic->pc_flags & PCF_PCIBUS) { 797 int class_code; 798 #if defined(__i386) || defined(__amd64) 799 pcic->pc_base = 0x1000000; 800 pcic->pc_bound = (uint32_t)~0; 801 pcic->pc_iobase = 0x1000; 802 pcic->pc_iobound = 0xefff; 803 #elif defined(__sparc) 804 pcic->pc_base = 0x0; 805 pcic->pc_bound = (uint32_t)~0; 806 pcic->pc_iobase = 0x00000; 807 pcic->pc_iobound = 0xffff; 808 #endif 809 810 /* usually need to get at config space so map first */ 811 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 812 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 813 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 814 815 if (ddi_regs_map_setup(dip, pci_cfrn, 816 (caddr_t *)&pcic->cfgaddr, 817 PCIC_PCI_CONFIG_REG_OFFSET, 818 PCIC_PCI_CONFIG_REG_LENGTH, 819 &attr, 820 &pcic->cfg_handle) != 821 DDI_SUCCESS) { 822 cmn_err(CE_CONT, 823 "pcic%d: unable to map config space" 824 "regs\n", 825 ddi_get_instance(dip)); 826 827 kmem_free(pcic, sizeof (pcicdev_t)); 828 return (DDI_FAILURE); 829 } /* ddi_regs_map_setup */ 830 831 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 832 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 833 "class-code", -1); 834 #ifdef PCIC_DEBUG 835 if (pcic_debug) { 836 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 837 class_code); 838 } 839 #endif 840 841 switch (class_code) { 842 case PCIC_PCI_CARDBUS: 843 pcic->pc_flags |= PCF_CARDBUS; 844 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 845 /* 846 * Get access to the adapter registers on the 847 * PCI bus. A 4K memory page 848 */ 849 #if defined(PCIC_DEBUG) 850 pcic_err(dip, 8, "Is Cardbus device\n"); 851 if (pcic_debug) { 852 int nr; 853 long rs; 854 (void) ddi_dev_nregs(dip, &nr); 855 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 856 "cfghndl 0x%p nregs %d", 857 (void *)pcic->cfgaddr, 858 (void *)pcic->cfg_handle, nr); 859 860 (void) ddi_dev_regsize(dip, 861 PCIC_PCI_CONTROL_REG_NUM, &rs); 862 863 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 864 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 865 } 866 #endif 867 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 868 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 869 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 870 871 if (ddi_regs_map_setup(dip, pci_ctrn, 872 (caddr_t *)&pcic->ioaddr, 873 PCIC_PCI_CONTROL_REG_OFFSET, 874 PCIC_CB_CONTROL_REG_LENGTH, 875 &attr, &pcic->handle) != 876 DDI_SUCCESS) { 877 cmn_err(CE_CONT, 878 "pcic%d: unable to map PCI regs\n", 879 ddi_get_instance(dip)); 880 ddi_regs_map_free(&pcic->cfg_handle); 881 kmem_free(pcic, sizeof (pcicdev_t)); 882 return (DDI_FAILURE); 883 } /* ddi_regs_map_setup */ 884 885 /* 886 * Find out the chip type - If we're on a PCI bus, 887 * the adapter has that information in the PCI 888 * config space. 889 * Note that we call pcic_find_pci_type here since 890 * it needs a valid mapped pcic->handle to 891 * access some of the adapter registers in 892 * some cases. 893 */ 894 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 895 ddi_regs_map_free(&pcic->handle); 896 ddi_regs_map_free(&pcic->cfg_handle); 897 kmem_free(pcic, sizeof (pcicdev_t)); 898 cmn_err(CE_WARN, "pcic: %s: unsupported " 899 "bridge\n", 900 ddi_get_name_addr(dip)); 901 return (DDI_FAILURE); 902 } 903 break; 904 905 default: 906 case PCIC_PCI_PCMCIA: 907 /* 908 * Get access to the adapter IO registers on the 909 * PCI bus config space. 910 */ 911 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 912 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 913 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 914 915 /* 916 * We need a default mapping to the adapter's IO 917 * control register space. For most adapters 918 * that are of class PCIC_PCI_PCMCIA (or of 919 * a default class) the control registers 920 * will be using the 82365-type control/data 921 * format. 922 */ 923 if (ddi_regs_map_setup(dip, pci_ctrn, 924 (caddr_t *)&pcic->ioaddr, 925 PCIC_PCI_CONTROL_REG_OFFSET, 926 PCIC_PCI_CONTROL_REG_LENGTH, 927 &attr, 928 &pcic->handle) != DDI_SUCCESS) { 929 cmn_err(CE_CONT, 930 "pcic%d: unable to map PCI regs\n", 931 ddi_get_instance(dip)); 932 ddi_regs_map_free(&pcic->cfg_handle); 933 kmem_free(pcic, sizeof (pcicdev_t)); 934 return (DDI_FAILURE); 935 } /* ddi_regs_map_setup */ 936 937 /* 938 * Find out the chip type - If we're on a PCI bus, 939 * the adapter has that information in the PCI 940 * config space. 941 * Note that we call pcic_find_pci_type here since 942 * it needs a valid mapped pcic->handle to 943 * access some of the adapter registers in 944 * some cases. 945 */ 946 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 947 ddi_regs_map_free(&pcic->handle); 948 ddi_regs_map_free(&pcic->cfg_handle); 949 kmem_free(pcic, sizeof (pcicdev_t)); 950 cmn_err(CE_WARN, "pcic: %s: unsupported " 951 "bridge\n", 952 ddi_get_name_addr(dip)); 953 return (DDI_FAILURE); 954 } 955 956 /* 957 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 958 * for extended registers even though they are 959 * not CardBus adapters. For those adapters, 960 * re-map pcic->handle to be large enough to 961 * encompass the Yenta registers. 962 */ 963 switch (pcic->pc_type) { 964 case PCIC_TI_PCI1031: 965 ddi_regs_map_free(&pcic->handle); 966 967 if (ddi_regs_map_setup(dip, 968 PCIC_PCI_CONTROL_REG_NUM, 969 (caddr_t *)&pcic->ioaddr, 970 PCIC_PCI_CONTROL_REG_OFFSET, 971 PCIC_CB_CONTROL_REG_LENGTH, 972 &attr, 973 &pcic->handle) != DDI_SUCCESS) { 974 cmn_err(CE_CONT, 975 "pcic%d: unable to map " 976 "PCI regs\n", 977 ddi_get_instance(dip)); 978 ddi_regs_map_free(&pcic->cfg_handle); 979 kmem_free(pcic, sizeof (pcicdev_t)); 980 return (DDI_FAILURE); 981 } /* ddi_regs_map_setup */ 982 break; 983 default: 984 break; 985 } /* switch (pcic->pc_type) */ 986 break; 987 } /* switch (class_code) */ 988 } else { 989 /* 990 * We're not on a PCI bus, so assume an ISA bus type 991 * register property. Get access to the adapter IO 992 * registers on a non-PCI bus. 993 */ 994 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 995 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 996 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 997 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 998 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 999 1000 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 1001 (caddr_t *)&pcic->ioaddr, 1002 PCIC_ISA_CONTROL_REG_OFFSET, 1003 PCIC_ISA_CONTROL_REG_LENGTH, 1004 &attr, 1005 &pcic->handle) != DDI_SUCCESS) { 1006 cmn_err(CE_CONT, 1007 "pcic%d: unable to map ISA registers\n", 1008 ddi_get_instance(dip)); 1009 1010 kmem_free(pcic, sizeof (pcicdev_t)); 1011 return (DDI_FAILURE); 1012 } /* ddi_regs_map_setup */ 1013 1014 /* ISA bus is limited to 24-bits, but not first 640K */ 1015 pcic->pc_base = 0xd0000; 1016 pcic->pc_bound = (uint32_t)~0; 1017 pcic->pc_iobase = 0x1000; 1018 pcic->pc_iobound = 0xefff; 1019 } /* !PCF_PCIBUS */ 1020 1021 #ifdef PCIC_DEBUG 1022 if (pcic_debug) { 1023 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1024 pcic->pc_flags, pcic->pc_type); 1025 } 1026 #endif 1027 1028 /* 1029 * Setup various adapter registers for the PCI case. For the 1030 * non-PCI case, find out the chip type. 1031 */ 1032 if (pcic->pc_flags & PCF_PCIBUS) { 1033 int iline; 1034 #if defined(__sparc) 1035 iline = 0; 1036 #else 1037 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1038 #endif 1039 1040 /* set flags and socket counts based on chip type */ 1041 switch (pcic->pc_type) { 1042 uint32_t cfg; 1043 case PCIC_INTEL_i82092: 1044 cfg = ddi_get8(pcic->cfg_handle, 1045 pcic->cfgaddr + PCIC_82092_PCICON); 1046 /* we can only support 4 Socket version */ 1047 if (cfg & PCIC_82092_4_SOCKETS) { 1048 pcic->pc_numsockets = 4; 1049 pcic->pc_type = PCIC_INTEL_i82092; 1050 if (iline != 0xFF) 1051 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1052 else 1053 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1054 } else { 1055 cmn_err(CE_CONT, 1056 "pcic%d: Intel 82092 adapter " 1057 "in unsupported configuration: 0x%x", 1058 ddi_get_instance(pcic->dip), cfg); 1059 pcic->pc_numsockets = 0; 1060 } /* PCIC_82092_4_SOCKETS */ 1061 break; 1062 case PCIC_CL_PD6730: 1063 case PCIC_CL_PD6729: 1064 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1065 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1066 DDI_PROP_CANSLEEP, 1067 "interrupts", 0); 1068 /* if not interrupt pin then must use ISA style IRQs */ 1069 if (cfg == 0 || iline == 0xFF) 1070 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1071 else { 1072 /* 1073 * we have the option to use PCI interrupts. 1074 * this might not be optimal but in some cases 1075 * is the only thing possible (sparc case). 1076 * we now deterine what is possible. 1077 */ 1078 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1079 } 1080 pcic->pc_numsockets = 2; 1081 pcic->pc_flags |= PCF_IO_REMAP; 1082 break; 1083 case PCIC_TI_PCI1031: 1084 /* this chip doesn't do CardBus but looks like one */ 1085 pcic->pc_flags &= ~PCF_CARDBUS; 1086 /* FALLTHROUGH */ 1087 default: 1088 pcic->pc_flags |= PCF_IO_REMAP; 1089 /* FALLTHROUGH */ 1090 /* indicate feature even if not supported */ 1091 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1092 /* Not sure if these apply to all these chips */ 1093 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1094 pcic->pc_flags |= pcic_use_cbpwrctl; 1095 1096 pcic->pc_numsockets = 1; /* one per function */ 1097 if (iline != 0xFF) { 1098 uint8_t cfg; 1099 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1100 1101 cfg = ddi_get8(pcic->cfg_handle, 1102 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1103 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1104 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1105 PCIC_BRIDGE_CTL_REG), cfg); 1106 } 1107 else 1108 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1109 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1110 break; 1111 } 1112 } else { 1113 /* 1114 * We're not on a PCI bus so do some more 1115 * checking for adapter type here. 1116 * For the non-PCI bus case: 1117 * It could be any one of a number of different chips 1118 * If we can't determine anything else, it is assumed 1119 * to be an Intel 82365SL. The Cirrus Logic PD6710 1120 * has an extension register that provides unique 1121 * identification. Toshiba chip isn't detailed as yet. 1122 */ 1123 1124 /* Init the CL id mode */ 1125 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1126 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1127 1128 /* default to Intel i82365SL and then refine */ 1129 pcic->pc_type = PCIC_I82365SL; 1130 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1131 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1132 /* go until one succeeds or none left */ 1133 if (pcic_ci_funcs[value](pcic)) 1134 break; 1135 } 1136 1137 /* any chip specific flags get set here */ 1138 switch (pcic->pc_type) { 1139 case PCIC_CL_PD6722: 1140 pcic->pc_flags |= PCF_DMA; 1141 } 1142 1143 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1144 /* 1145 * look for total number of sockets. 1146 * basically check each possible socket for 1147 * presence like in probe 1148 */ 1149 1150 /* turn all windows off */ 1151 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1152 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1153 1154 /* 1155 * if a zero is read back, then this socket 1156 * might be present. It would be except for 1157 * some systems that map the secondary PCIC 1158 * chip space back to the first. 1159 */ 1160 if (value != 0) { 1161 /* definitely not so skip */ 1162 /* note: this is for Compaq support */ 1163 continue; 1164 } 1165 1166 /* further tests */ 1167 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1168 PCIC_REV_MASK; 1169 if (!(value >= PCIC_REV_LEVEL_LOW && 1170 value <= PCIC_REV_LEVEL_HI)) 1171 break; 1172 1173 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1174 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1175 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1176 1177 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1178 if (value != 0xaa || j != 0x55) 1179 break; 1180 1181 /* 1182 * at this point we know if we have hardware 1183 * of some type and not just the bus holding 1184 * a pattern for us. We still have to determine 1185 * the case where more than 2 sockets are 1186 * really the same due to peculiar mappings of 1187 * hardware. 1188 */ 1189 j = pcic->pc_numsockets++; 1190 pcic->pc_sockets[j].pcs_flags = 0; 1191 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1192 pcic->pc_sockets[j].pcs_socket = i; 1193 1194 /* put PC Card into RESET, just in case */ 1195 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1196 pcic_putb(pcic, i, PCIC_INTERRUPT, 1197 value & ~PCIC_RESET); 1198 } 1199 1200 #if defined(PCIC_DEBUG) 1201 if (pcic_debug) 1202 cmn_err(CE_CONT, "num sockets = %d\n", 1203 pcic->pc_numsockets); 1204 #endif 1205 if (pcic->pc_numsockets == 0) { 1206 ddi_regs_map_free(&pcic->handle); 1207 kmem_free(pcic, sizeof (pcicdev_t)); 1208 return (DDI_FAILURE); 1209 } 1210 1211 /* 1212 * need to think this through again in light of 1213 * Compaq not following the model that all the 1214 * chip vendors recommend. IBM 755 seems to be 1215 * afflicted as well. Basically, if the vendor 1216 * wired things wrong, socket 0 responds for socket 2 1217 * accesses, etc. 1218 */ 1219 if (pcic->pc_numsockets > 2) { 1220 int count = pcic->pc_numsockets / 4; 1221 for (i = 0; i < count; i++) { 1222 /* put pattern into socket 0 */ 1223 pcic_putb(pcic, i, 1224 PCIC_SYSMEM_0_STARTLOW, 0x11); 1225 1226 /* put pattern into socket 2 */ 1227 pcic_putb(pcic, i + 2, 1228 PCIC_SYSMEM_0_STARTLOW, 0x33); 1229 1230 /* read back socket 0 */ 1231 value = pcic_getb(pcic, i, 1232 PCIC_SYSMEM_0_STARTLOW); 1233 1234 /* read back chip 1 socket 0 */ 1235 j = pcic_getb(pcic, i + 2, 1236 PCIC_SYSMEM_0_STARTLOW); 1237 if (j == value) { 1238 pcic->pc_numsockets -= 2; 1239 } 1240 } 1241 } 1242 1243 smi = 0xff; /* no more override */ 1244 1245 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1246 DDI_PROP_DONTPASS, "need-mult-irq", 1247 0xffff) != 0xffff) 1248 pcic->pc_flags |= PCF_MULT_IRQ; 1249 1250 } /* !PCF_PCIBUS */ 1251 1252 /* 1253 * some platforms/busses need to have resources setup 1254 * this is temporary until a real resource allocator is 1255 * implemented. 1256 */ 1257 1258 pcic_init_assigned(dip); 1259 1260 typename = pcic->pc_chipname; 1261 1262 #ifdef PCIC_DEBUG 1263 if (pcic_debug) { 1264 int nregs, nintrs; 1265 1266 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1267 nregs = 0; 1268 1269 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1270 nintrs = 0; 1271 1272 cmn_err(CE_CONT, 1273 "pcic%d: %d register sets, %d interrupts\n", 1274 ddi_get_instance(dip), nregs, nintrs); 1275 1276 nintrs = 0; 1277 while (nregs--) { 1278 off_t size; 1279 1280 if (ddi_dev_regsize(dip, nintrs, &size) == 1281 DDI_SUCCESS) { 1282 cmn_err(CE_CONT, 1283 "\tregnum %d size %ld (0x%lx)" 1284 "bytes", 1285 nintrs, size, size); 1286 if (nintrs == 1287 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1288 PCIC_ISA_CONTROL_REG_NUM : 1289 PCIC_PCI_CONTROL_REG_NUM)) 1290 cmn_err(CE_CONT, 1291 " mapped at: 0x%p\n", 1292 (void *)pcic->ioaddr); 1293 else 1294 cmn_err(CE_CONT, "\n"); 1295 } else { 1296 cmn_err(CE_CONT, 1297 "\tddi_dev_regsize(rnumber" 1298 "= %d) returns DDI_FAILURE\n", 1299 nintrs); 1300 } 1301 nintrs++; 1302 } /* while */ 1303 } /* if (pcic_debug) */ 1304 #endif 1305 1306 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1307 1308 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1309 "disable-audio", 0)) 1310 pcic->pc_flags |= PCF_AUDIO; 1311 1312 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1313 "disable-cardbus", 0)) 1314 pcic->pc_flags &= ~PCF_CARDBUS; 1315 1316 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1317 typename); 1318 1319 /* 1320 * Init all socket SMI levels to 0 (no SMI) 1321 */ 1322 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1323 pcic->pc_sockets[i].pcs_smi = 0; 1324 pcic->pc_sockets[i].pcs_debounce_id = 0; 1325 pcic->pc_sockets[i].pcs_pcic = pcic; 1326 } 1327 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1328 1329 /* 1330 * Setup the IRQ handler(s) 1331 */ 1332 switch (pcic->pc_intr_mode) { 1333 int xx; 1334 case PCIC_INTR_MODE_ISA: 1335 /* 1336 * On a non-PCI bus, we just use whatever SMI IRQ level was 1337 * specified above, and the IO IRQ levels are allocated 1338 * dynamically. 1339 */ 1340 for (xx = 15, smi = 0; xx >= 0; xx--) { 1341 if (PCIC_IRQ(xx) & 1342 PCIC_AVAIL_IRQS) { 1343 smi = pcmcia_get_intr(dip, xx); 1344 if (smi >= 0) 1345 break; 1346 } 1347 } 1348 #if defined(PCIC_DEBUG) 1349 if (pcic_debug) 1350 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1351 #endif 1352 /* init to same so share is easy */ 1353 for (i = 0; i < pcic->pc_numsockets; i++) 1354 pcic->pc_sockets[i].pcs_smi = smi; 1355 /* any special handling of IRQ levels */ 1356 if (pcic->pc_flags & PCF_MULT_IRQ) { 1357 for (i = 2; i < pcic->pc_numsockets; i++) { 1358 if ((i & 1) == 0) { 1359 int xx; 1360 for (xx = 15, smi = 0; xx >= 0; xx--) { 1361 if (PCIC_IRQ(xx) & 1362 PCIC_AVAIL_IRQS) { 1363 smi = 1364 pcmcia_get_intr(dip, 1365 xx); 1366 if (smi >= 0) 1367 break; 1368 } 1369 } 1370 } 1371 if (smi >= 0) 1372 pcic->pc_sockets[i].pcs_smi = smi; 1373 } 1374 } 1375 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1376 sizeof (ddi_intr_handle_t), KM_SLEEP); 1377 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1378 struct intrspec *ispecp; 1379 struct ddi_parent_private_data *pdp; 1380 1381 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1382 continue; 1383 else { 1384 irqlevel = pcic->pc_sockets[i].pcs_smi; 1385 } 1386 /* 1387 * now convert the allocated IRQ into an intrspec 1388 * and ask our parent to add it. Don't use 1389 * the ddi_add_intr since we don't have a 1390 * default intrspec in all cases. 1391 * 1392 * note: this sort of violates DDI but we don't 1393 * get hardware intrspecs for many of the devices. 1394 * at the same time, we know how to allocate them 1395 * so we do the right thing. 1396 */ 1397 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1398 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1399 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1400 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1401 ddi_get_name(dip)); 1402 goto isa_exit1; 1403 } 1404 1405 /* 1406 * See earlier note: 1407 * Since some devices don't have 'intrspec' 1408 * we make one up in rootnex. 1409 * 1410 * However, it is not properly initialized as 1411 * the data it needs is present in this driver 1412 * and there is no interface to pass that up. 1413 * Specially 'irqlevel' is very important and 1414 * it is part of pcic struct. 1415 * 1416 * Set 'intrspec' up here; otherwise adding the 1417 * interrupt will fail. 1418 */ 1419 pdp = ddi_get_parent_data(dip); 1420 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1421 ispecp->intrspec_vec = irqlevel; 1422 ispecp->intrspec_pri = pcic->pc_irq; 1423 1424 /* Stay compatible w/ PCMCIA */ 1425 pcic->pc_pri = (ddi_iblock_cookie_t) 1426 (uintptr_t)pcic->pc_irq; 1427 pcic->pc_dcookie.idev_priority = 1428 (uintptr_t)pcic->pc_pri; 1429 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1430 1431 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1432 pcic->pc_irq); 1433 1434 if (i == 0) { 1435 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1436 DDI_INTR_PRI(pcic->pc_irq)); 1437 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1438 NULL); 1439 } 1440 1441 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1442 pcic_intr, (caddr_t)pcic, NULL)) { 1443 cmn_err(CE_WARN, 1444 "%s: ddi_intr_add_handler failed", 1445 ddi_get_name(dip)); 1446 goto isa_exit2; 1447 } 1448 1449 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1450 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1451 ddi_get_name(dip)); 1452 for (j = i; j < 0; j--) 1453 (void) ddi_intr_remove_handler( 1454 pcic->pc_intr_htblp[j]); 1455 goto isa_exit2; 1456 } 1457 } 1458 break; 1459 case PCIC_INTR_MODE_PCI_1: 1460 case PCIC_INTR_MODE_PCI: 1461 /* 1462 * If we're on a PCI bus, we route all interrupts, both SMI 1463 * and IO interrupts, through a single interrupt line. 1464 * Assign the SMI IRQ level to the IO IRQ level here. 1465 */ 1466 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1467 KM_SLEEP); 1468 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1469 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1470 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1471 goto pci_exit1; 1472 1473 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1474 &pri) != DDI_SUCCESS) { 1475 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1476 goto pci_exit1; 1477 } 1478 1479 pcic->pc_pri = (void *)(uintptr_t)pri; 1480 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1481 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1482 1483 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1484 pcic_intr, (caddr_t)pcic, NULL)) 1485 goto pci_exit2; 1486 1487 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1488 (void) ddi_intr_remove_handler( 1489 pcic->pc_pci_intr_hdlp[0]); 1490 goto pci_exit2; 1491 } 1492 1493 /* Stay compatible w/ PCMCIA */ 1494 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1495 1496 /* init to same (PCI) so share is easy */ 1497 for (i = 0; i < pcic->pc_numsockets; i++) 1498 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1499 break; 1500 } 1501 1502 /* 1503 * Setup the adapter hardware to some reasonable defaults. 1504 */ 1505 mutex_enter(&pcic->pc_lock); 1506 /* mark the driver state as attached */ 1507 pcic->pc_flags |= PCF_ATTACHED; 1508 pcic_setup_adapter(pcic); 1509 1510 for (j = 0; j < pcic->pc_numsockets; j++) 1511 if (ddi_intr_add_softint(dip, 1512 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1513 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1514 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1515 goto pci_exit2; 1516 1517 #if defined(PCIC_DEBUG) 1518 if (pcic_debug) 1519 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1520 pcic->pc_numsockets); 1521 #endif 1522 1523 pcic_nexus->an_iblock = &pcic->pc_pri; 1524 pcic_nexus->an_idev = &pcic->pc_dcookie; 1525 1526 mutex_exit(&pcic->pc_lock); 1527 1528 #ifdef CARDBUS 1529 (void) cardbus_enable_cd_intr(dip); 1530 if (pcic_debug) { 1531 1532 cardbus_dump_pci_config(dip); 1533 cardbus_dump_socket(dip); 1534 } 1535 1536 /* 1537 * Give the Cardbus misc module a chance to do it's per-adapter 1538 * instance setup. Note that there is no corresponding detach() 1539 * call. 1540 */ 1541 if (pcic->pc_flags & PCF_CARDBUS) 1542 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1543 cmn_err(CE_CONT, 1544 "pcic_attach: cardbus_attach failed\n"); 1545 goto pci_exit2; 1546 } 1547 #endif 1548 1549 /* 1550 * Give the PCMCIA misc module a chance to do it's per-adapter 1551 * instance setup. 1552 */ 1553 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1554 goto pci_exit2; 1555 1556 if (pcic_maxinst == -1) { 1557 /* This assumes that all instances run at the same IPL. */ 1558 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1559 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1560 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1561 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1562 v.v_maxsyspri - 2); 1563 } 1564 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1565 /* 1566 * Setup a debounce timeout to do an initial card detect 1567 * and enable interrupts. 1568 */ 1569 for (j = 0; j < pcic->pc_numsockets; j++) { 1570 pcic->pc_sockets[j].pcs_debounce_id = 1571 pcic_add_debqueue(&pcic->pc_sockets[j], 1572 drv_usectohz(pcic_debounce_time)); 1573 } 1574 1575 return (i); 1576 1577 isa_exit2: 1578 mutex_destroy(&pcic->intr_lock); 1579 mutex_destroy(&pcic->pc_lock); 1580 for (j = i; j < 0; j--) 1581 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1582 isa_exit1: 1583 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1584 ddi_regs_map_free(&pcic->handle); 1585 if (pcic->pc_flags & PCF_PCIBUS) 1586 ddi_regs_map_free(&pcic->cfg_handle); 1587 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1588 sizeof (ddi_intr_handle_t)); 1589 kmem_free(pcic, sizeof (pcicdev_t)); 1590 return (DDI_FAILURE); 1591 1592 pci_exit2: 1593 mutex_destroy(&pcic->intr_lock); 1594 mutex_destroy(&pcic->pc_lock); 1595 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1596 pci_exit1: 1597 ddi_regs_map_free(&pcic->handle); 1598 if (pcic->pc_flags & PCF_PCIBUS) 1599 ddi_regs_map_free(&pcic->cfg_handle); 1600 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1601 kmem_free(pcic, sizeof (pcicdev_t)); 1602 return (DDI_FAILURE); 1603 } 1604 1605 /* 1606 * pcic_detach() 1607 * request to detach from the system 1608 */ 1609 static int 1610 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1611 { 1612 anp_t *anp = ddi_get_driver_private(dip); 1613 pcicdev_t *pcic = anp->an_private; 1614 int i; 1615 1616 switch (cmd) { 1617 case DDI_DETACH: 1618 /* don't detach if the nexus still talks to us */ 1619 if (pcic->pc_callback != NULL) 1620 return (DDI_FAILURE); 1621 1622 /* kill off the pm simulation */ 1623 if (pcic->pc_pmtimer) 1624 (void) untimeout(pcic->pc_pmtimer); 1625 1626 /* turn everything off for all sockets and chips */ 1627 for (i = 0; i < pcic->pc_numsockets; i++) { 1628 if (pcic->pc_sockets[i].pcs_debounce_id) 1629 pcic_rm_debqueue( 1630 pcic->pc_sockets[i].pcs_debounce_id); 1631 pcic->pc_sockets[i].pcs_debounce_id = 0; 1632 1633 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1634 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1635 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1636 /* disable interrupts and put card into RESET */ 1637 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1638 } 1639 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1640 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1641 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1642 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1643 pcic->pc_flags = 0; 1644 mutex_destroy(&pcic->pc_lock); 1645 mutex_destroy(&pcic->intr_lock); 1646 cv_destroy(&pcic->pm_cv); 1647 if (pcic->pc_flags & PCF_PCIBUS) 1648 ddi_regs_map_free(&pcic->cfg_handle); 1649 if (pcic->handle) 1650 ddi_regs_map_free(&pcic->handle); 1651 kmem_free(pcic, sizeof (pcicdev_t)); 1652 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1653 return (DDI_SUCCESS); 1654 1655 case DDI_SUSPEND: 1656 case DDI_PM_SUSPEND: 1657 /* 1658 * we got a suspend event (either real or imagined) 1659 * so notify the nexus proper that all existing cards 1660 * should go away. 1661 */ 1662 mutex_enter(&pcic->pc_lock); 1663 #ifdef CARDBUS 1664 if (pcic->pc_flags & PCF_CARDBUS) { 1665 for (i = 0; i < pcic->pc_numsockets; i++) { 1666 if ((pcic->pc_sockets[i].pcs_flags & 1667 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1668 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) { 1669 1670 pcmcia_cb_suspended( 1671 pcic->pc_sockets[i].pcs_socket); 1672 } 1673 } 1674 1675 cardbus_save_children(ddi_get_child(dip)); 1676 } 1677 #endif 1678 /* turn everything off for all sockets and chips */ 1679 for (i = 0; i < pcic->pc_numsockets; i++) { 1680 if (pcic->pc_sockets[i].pcs_debounce_id) 1681 pcic_rm_debqueue( 1682 pcic->pc_sockets[i].pcs_debounce_id); 1683 pcic->pc_sockets[i].pcs_debounce_id = 0; 1684 1685 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1686 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1687 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1688 /* disable interrupts and put card into RESET */ 1689 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1690 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1691 if (pcic->pc_flags & PCF_CBPWRCTL) 1692 pcic_putcb(pcic, CB_CONTROL, 0); 1693 1694 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1695 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1696 /* 1697 * Because we are half way through a save 1698 * all this does is schedule a removal event 1699 * to cs for when the system comes back. 1700 * This doesn't actually matter. 1701 */ 1702 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1703 pcic->pc_callback) { 1704 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1705 PCE_CARD_REMOVAL, 1706 pcic->pc_sockets[i].pcs_socket); 1707 } 1708 } 1709 } 1710 1711 pcic->pc_flags |= PCF_SUSPENDED; 1712 mutex_exit(&pcic->pc_lock); 1713 1714 /* 1715 * when true power management exists, save the adapter 1716 * state here to enable a recovery. For the emulation 1717 * condition, the state is gone 1718 */ 1719 return (DDI_SUCCESS); 1720 1721 default: 1722 return (EINVAL); 1723 } 1724 } 1725 1726 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1727 static uint32_t pcic_tisysctl_offbits = 0; 1728 static uint32_t pcic_default_latency = 0x40; 1729 1730 static void 1731 pcic_setup_adapter(pcicdev_t *pcic) 1732 { 1733 int i; 1734 int value, flags; 1735 1736 #if defined(__i386) || defined(__amd64) 1737 pci_regspec_t *reg; 1738 uchar_t bus, dev, func; 1739 uint_t classcode; 1740 int length; 1741 #endif 1742 1743 if (pcic->pc_flags & PCF_PCIBUS) { 1744 /* 1745 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1746 */ 1747 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1748 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1749 } 1750 /* enable each socket */ 1751 for (i = 0; i < pcic->pc_numsockets; i++) { 1752 pcic->pc_sockets[i].pcs_flags = 0; 1753 /* find out the socket capabilities (I/O vs memory) */ 1754 value = pcic_getb(pcic, i, 1755 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1756 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1757 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1758 1759 /* disable all windows just in case */ 1760 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1761 1762 switch (pcic->pc_type) { 1763 uint32_t cfg32; 1764 uint16_t cfg16; 1765 uint8_t cfg; 1766 1767 /* enable extended registers for Vadem */ 1768 case PCIC_VADEM_VG469: 1769 case PCIC_VADEM: 1770 1771 /* enable card status change interrupt for socket */ 1772 break; 1773 1774 case PCIC_I82365SL: 1775 break; 1776 1777 case PCIC_CL_PD6710: 1778 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1779 break; 1780 1781 /* 1782 * On the CL_6730, we need to set up the interrupt 1783 * signalling mode (PCI mode) and set the SMI and 1784 * IRQ interrupt lines to PCI/level-mode. 1785 */ 1786 case PCIC_CL_PD6730: 1787 switch (pcic->pc_intr_mode) { 1788 case PCIC_INTR_MODE_PCI_1: 1789 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1790 ((clext_reg_read(pcic, i, 1791 PCIC_CLEXT_MISC_CTL_3) & 1792 ~PCIC_CLEXT_INT_PCI) | 1793 PCIC_CLEXT_INT_PCI)); 1794 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1795 (PCIC_CLEXT_IRQ_LVL_MODE | 1796 PCIC_CLEXT_SMI_LVL_MODE)); 1797 cfg = PCIC_CL_LP_DYN_MODE; 1798 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1799 break; 1800 case PCIC_INTR_MODE_ISA: 1801 break; 1802 } 1803 break; 1804 /* 1805 * On the CL_6729, we set the SMI and IRQ interrupt 1806 * lines to PCI/level-mode. as well as program the 1807 * correct clock speed divider bit. 1808 */ 1809 case PCIC_CL_PD6729: 1810 switch (pcic->pc_intr_mode) { 1811 case PCIC_INTR_MODE_PCI_1: 1812 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1813 (PCIC_CLEXT_IRQ_LVL_MODE | 1814 PCIC_CLEXT_SMI_LVL_MODE)); 1815 1816 break; 1817 case PCIC_INTR_MODE_ISA: 1818 break; 1819 } 1820 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1821 cfg = 0; 1822 cfg |= PCIC_CL_TIMER_CLK_DIV; 1823 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1824 } 1825 break; 1826 case PCIC_INTEL_i82092: 1827 cfg = PCIC_82092_EN_TIMING; 1828 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1829 cfg |= PCIC_82092_PCICLK_25MHZ; 1830 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1831 PCIC_82092_PCICON, cfg); 1832 break; 1833 case PCIC_TI_PCI1130: 1834 case PCIC_TI_PCI1131: 1835 case PCIC_TI_PCI1250: 1836 case PCIC_TI_PCI1031: 1837 cfg = ddi_get8(pcic->cfg_handle, 1838 pcic->cfgaddr + PCIC_DEVCTL_REG); 1839 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1840 switch (pcic->pc_intr_mode) { 1841 case PCIC_INTR_MODE_ISA: 1842 cfg |= PCIC_DEVCTL_INTR_ISA; 1843 break; 1844 } 1845 #ifdef PCIC_DEBUG 1846 if (pcic_debug) { 1847 cmn_err(CE_CONT, "pcic_setup_adapter: " 1848 "write reg 0x%x=%x \n", 1849 PCIC_DEVCTL_REG, cfg); 1850 } 1851 #endif 1852 ddi_put8(pcic->cfg_handle, 1853 pcic->cfgaddr + PCIC_DEVCTL_REG, 1854 cfg); 1855 1856 cfg = ddi_get8(pcic->cfg_handle, 1857 pcic->cfgaddr + PCIC_CRDCTL_REG); 1858 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1859 PCIC_CRDCTL_PCIFUNC); 1860 switch (pcic->pc_intr_mode) { 1861 case PCIC_INTR_MODE_PCI_1: 1862 cfg |= PCIC_CRDCTL_PCIINTR | 1863 PCIC_CRDCTL_PCICSC | 1864 PCIC_CRDCTL_PCIFUNC; 1865 pcic->pc_flags |= PCF_USE_SMI; 1866 break; 1867 } 1868 #ifdef PCIC_DEBUG 1869 if (pcic_debug) { 1870 cmn_err(CE_CONT, "pcic_setup_adapter: " 1871 " write reg 0x%x=%x \n", 1872 PCIC_CRDCTL_REG, cfg); 1873 } 1874 #endif 1875 ddi_put8(pcic->cfg_handle, 1876 pcic->cfgaddr + PCIC_CRDCTL_REG, 1877 cfg); 1878 break; 1879 case PCIC_TI_PCI1221: 1880 case PCIC_TI_PCI1225: 1881 cfg = ddi_get8(pcic->cfg_handle, 1882 pcic->cfgaddr + PCIC_DEVCTL_REG); 1883 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1884 #ifdef PCIC_DEBUG 1885 if (pcic_debug) { 1886 cmn_err(CE_CONT, "pcic_setup_adapter: " 1887 " write reg 0x%x=%x \n", 1888 PCIC_DEVCTL_REG, cfg); 1889 } 1890 #endif 1891 ddi_put8(pcic->cfg_handle, 1892 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1893 1894 cfg = ddi_get8(pcic->cfg_handle, 1895 pcic->cfgaddr + PCIC_DIAG_REG); 1896 if (pcic->pc_type == PCIC_TI_PCI1225) { 1897 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1898 } else { 1899 cfg |= PCIC_DIAG_ASYNC; 1900 } 1901 pcic->pc_flags |= PCF_USE_SMI; 1902 #ifdef PCIC_DEBUG 1903 if (pcic_debug) { 1904 cmn_err(CE_CONT, "pcic_setup_adapter: " 1905 " write reg 0x%x=%x \n", 1906 PCIC_DIAG_REG, cfg); 1907 } 1908 #endif 1909 ddi_put8(pcic->cfg_handle, 1910 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1911 break; 1912 case PCIC_TI_PCI1520: 1913 case PCIC_TI_PCI1510: 1914 case PCIC_TI_VENDOR: 1915 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1916 /* functional intr routed by ExCA register */ 1917 cfg = ddi_get8(pcic->cfg_handle, 1918 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1919 cfg |= PCIC_FUN_INT_MOD_ISA; 1920 ddi_put8(pcic->cfg_handle, 1921 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1922 cfg); 1923 1924 /* IRQ serialized interrupts */ 1925 cfg = ddi_get8(pcic->cfg_handle, 1926 pcic->cfgaddr + PCIC_DEVCTL_REG); 1927 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1928 cfg |= PCIC_DEVCTL_INTR_ISA; 1929 ddi_put8(pcic->cfg_handle, 1930 pcic->cfgaddr + PCIC_DEVCTL_REG, 1931 cfg); 1932 break; 1933 } 1934 1935 /* CSC interrupt routed to PCI */ 1936 cfg = ddi_get8(pcic->cfg_handle, 1937 pcic->cfgaddr + PCIC_DIAG_REG); 1938 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1939 ddi_put8(pcic->cfg_handle, 1940 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1941 1942 #if defined(__i386) || defined(__amd64) 1943 /* 1944 * Some TI chips have 2 cardbus slots(function0 and 1945 * function1), and others may have just 1 cardbus slot. 1946 * The interrupt routing register is shared between the 1947 * 2 functions and can only be accessed through 1948 * function0. Here we check the presence of the second 1949 * cardbus slot and do the right thing. 1950 */ 1951 1952 if (ddi_getlongprop(DDI_DEV_T_ANY, pcic->dip, 1953 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1954 &length) != DDI_PROP_SUCCESS) { 1955 cmn_err(CE_WARN, "pcic_setup_adapter(), failed to" 1956 " read reg property\n"); 1957 break; 1958 } 1959 1960 bus = PCI_REG_BUS_G(reg->pci_phys_hi); 1961 dev = PCI_REG_DEV_G(reg->pci_phys_hi); 1962 func = PCI_REG_FUNC_G(reg->pci_phys_hi); 1963 kmem_free((caddr_t)reg, length); 1964 1965 if (func != 0) { 1966 break; 1967 } 1968 1969 classcode = (*pci_getl_func)(bus, dev, 1, 1970 PCI_CONF_REVID); 1971 classcode >>= 8; 1972 if (classcode != 0x060700 && 1973 classcode != 0x060500) { 1974 break; 1975 } 1976 1977 /* Parallel PCI interrupts only */ 1978 cfg = ddi_get8(pcic->cfg_handle, 1979 pcic->cfgaddr + PCIC_DEVCTL_REG); 1980 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1981 ddi_put8(pcic->cfg_handle, 1982 pcic->cfgaddr + PCIC_DEVCTL_REG, 1983 cfg); 1984 1985 /* tie INTA and INTB together */ 1986 cfg = ddi_get8(pcic->cfg_handle, 1987 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 1988 cfg |= PCIC_SYSCTL_INTRTIE; 1989 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1990 PCIC_SYSCTL_REG + 3), cfg); 1991 #endif 1992 1993 break; 1994 case PCIC_TI_PCI1410: 1995 cfg = ddi_get8(pcic->cfg_handle, 1996 pcic->cfgaddr + PCIC_DIAG_REG); 1997 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1998 ddi_put8(pcic->cfg_handle, 1999 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2000 break; 2001 case PCIC_TOSHIBA_TOPIC100: 2002 case PCIC_TOSHIBA_TOPIC95: 2003 case PCIC_TOSHIBA_VENDOR: 2004 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2005 PCIC_TOSHIBA_SLOT_CTL_REG); 2006 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 2007 PCIC_TOSHIBA_SCR_SLOTEN); 2008 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 2009 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 2010 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 2011 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 2012 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2013 PCIC_TOSHIBA_INTR_CTL_REG); 2014 switch (pcic->pc_intr_mode) { 2015 case PCIC_INTR_MODE_ISA: 2016 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 2017 ddi_put8(pcic->cfg_handle, 2018 pcic->cfgaddr + 2019 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2020 2021 cfg = ddi_get8(pcic->cfg_handle, 2022 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2023 cfg |= PCIC_FUN_INT_MOD_ISA; 2024 ddi_put8(pcic->cfg_handle, 2025 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2026 cfg); 2027 break; 2028 case PCIC_INTR_MODE_PCI_1: 2029 cfg |= PCIC_TOSHIBA_ICR_SRC; 2030 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 2031 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 2032 ddi_put8(pcic->cfg_handle, 2033 pcic->cfgaddr + 2034 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2035 break; 2036 } 2037 break; 2038 case PCIC_O2MICRO_VENDOR: 2039 cfg32 = ddi_get32(pcic->cfg_handle, 2040 (uint32_t *)(pcic->cfgaddr + 2041 PCIC_O2MICRO_MISC_CTL)); 2042 switch (pcic->pc_intr_mode) { 2043 case PCIC_INTR_MODE_ISA: 2044 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 2045 PCIC_O2MICRO_INT_MOD_PCI); 2046 ddi_put32(pcic->cfg_handle, 2047 (uint32_t *)(pcic->cfgaddr + 2048 PCIC_O2MICRO_MISC_CTL), 2049 cfg32); 2050 cfg = ddi_get8(pcic->cfg_handle, 2051 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2052 cfg |= PCIC_FUN_INT_MOD_ISA; 2053 ddi_put8(pcic->cfg_handle, 2054 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2055 cfg); 2056 break; 2057 case PCIC_INTR_MODE_PCI_1: 2058 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2059 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2060 ddi_put32(pcic->cfg_handle, 2061 (uint32_t *)(pcic->cfgaddr + 2062 PCIC_O2MICRO_MISC_CTL), 2063 cfg32); 2064 break; 2065 } 2066 break; 2067 case PCIC_RICOH_VENDOR: 2068 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2069 cfg16 = ddi_get16(pcic->cfg_handle, 2070 (uint16_t *)(pcic->cfgaddr + 2071 PCIC_RICOH_MISC_CTL_2)); 2072 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2073 PCIC_RICOH_FUN_INT_MOD); 2074 ddi_put16(pcic->cfg_handle, 2075 (uint16_t *)(pcic->cfgaddr + 2076 PCIC_RICOH_MISC_CTL_2), 2077 cfg16); 2078 2079 cfg16 = ddi_get16(pcic->cfg_handle, 2080 (uint16_t *)(pcic->cfgaddr + 2081 PCIC_RICOH_MISC_CTL)); 2082 cfg16 |= PCIC_RICOH_SIRQ_EN; 2083 ddi_put16(pcic->cfg_handle, 2084 (uint16_t *)(pcic->cfgaddr + 2085 PCIC_RICOH_MISC_CTL), 2086 cfg16); 2087 2088 cfg = ddi_get8(pcic->cfg_handle, 2089 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2090 cfg |= PCIC_FUN_INT_MOD_ISA; 2091 ddi_put8(pcic->cfg_handle, 2092 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2093 cfg); 2094 } 2095 break; 2096 default: 2097 break; 2098 } /* switch */ 2099 2100 /* 2101 * The default value in the EEPROM (loaded on reset) for 2102 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that 2103 * MFUNC0 is connected to INTA, and MFUNC1 is connected to 2104 * INTB. This applies to all TI CardBus controllers. 2105 */ 2106 if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID && 2107 pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) { 2108 value = ddi_get32(pcic->cfg_handle, 2109 (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG)); 2110 value &= ~0xff; 2111 ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr + 2112 PCIC_MFROUTE_REG), value|PCIC_TI_MFUNC_SEL); 2113 } 2114 2115 /* setup general card status change interrupt */ 2116 switch (pcic->pc_type) { 2117 case PCIC_TI_PCI1225: 2118 case PCIC_TI_PCI1221: 2119 case PCIC_TI_PCI1031: 2120 case PCIC_TI_PCI1520: 2121 case PCIC_TI_PCI1410: 2122 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2123 PCIC_CHANGE_DEFAULT); 2124 break; 2125 default: 2126 if (pcic->pc_intr_mode == 2127 PCIC_INTR_MODE_PCI_1) { 2128 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2129 PCIC_CHANGE_DEFAULT); 2130 break; 2131 } else { 2132 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2133 PCIC_CHANGE_DEFAULT | 2134 (pcic->pc_sockets[i].pcs_smi << 4)); 2135 break; 2136 } 2137 } 2138 2139 pcic->pc_flags |= PCF_INTRENAB; 2140 2141 /* take card out of RESET */ 2142 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2143 /* turn power off and let CS do this */ 2144 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2145 2146 /* final chip specific initialization */ 2147 switch (pcic->pc_type) { 2148 case PCIC_VADEM: 2149 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2150 PCIC_VC_DELAYENABLE); 2151 pcic->pc_flags |= PCF_DEBOUNCE; 2152 /* FALLTHROUGH */ 2153 case PCIC_I82365SL: 2154 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2155 PCIC_GC_CSC_WRITE); 2156 /* clear any pending interrupts */ 2157 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2158 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2159 break; 2160 /* The 82092 uses PCI config space to enable interrupts */ 2161 case PCIC_INTEL_i82092: 2162 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2163 PCIC_82092_INT_ENABLE); 2164 break; 2165 case PCIC_CL_PD6729: 2166 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2167 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2168 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2169 value | PCIC_CL_TIMER_CLK_DIV); 2170 } 2171 break; 2172 } /* switch */ 2173 2174 #if defined(PCIC_DEBUG) 2175 if (pcic_debug) 2176 cmn_err(CE_CONT, 2177 "socket %d value=%x, flags = %x (%s)\n", 2178 i, value, pcic->pc_sockets[i].pcs_flags, 2179 (pcic->pc_sockets[i].pcs_flags & 2180 PCS_CARD_PRESENT) ? 2181 "card present" : "no card"); 2182 #endif 2183 } 2184 } 2185 2186 /* 2187 * pcic_intr(caddr_t, caddr_t) 2188 * interrupt handler for the PCIC style adapter 2189 * handles all basic interrupts and also checks 2190 * for status changes and notifies the nexus if 2191 * necessary 2192 * 2193 * On PCI bus adapters, also handles all card 2194 * IO interrupts. 2195 */ 2196 /*ARGSUSED*/ 2197 uint32_t 2198 pcic_intr(caddr_t arg1, caddr_t arg2) 2199 { 2200 pcicdev_t *pcic = (pcicdev_t *)arg1; 2201 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2202 uint8_t status; 2203 uint_t io_ints; 2204 2205 #if defined(PCIC_DEBUG) 2206 pcic_err(pcic->dip, 0xf, 2207 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2208 " pc_numsockets=%d \n", 2209 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2210 #endif 2211 2212 if (!(pcic->pc_flags & PCF_ATTACHED)) 2213 return (DDI_INTR_UNCLAIMED); 2214 2215 mutex_enter(&pcic->intr_lock); 2216 2217 if (pcic->pc_flags & PCF_SUSPENDED) { 2218 mutex_exit(&pcic->intr_lock); 2219 return (ret); 2220 } 2221 2222 /* 2223 * need to change to only ACK and touch the slot that 2224 * actually caused the interrupt. Currently everything 2225 * is acked 2226 * 2227 * we need to look at all known sockets to determine 2228 * what might have happened, so step through the list 2229 * of them 2230 */ 2231 2232 /* 2233 * Set the bitmask for IO interrupts to initially include all sockets 2234 */ 2235 io_ints = (1 << pcic->pc_numsockets) - 1; 2236 2237 for (i = 0; i < pcic->pc_numsockets; i++) { 2238 int card_type; 2239 pcic_socket_t *sockp; 2240 int value_cb = 0; 2241 2242 sockp = &pcic->pc_sockets[i]; 2243 /* get the socket's I/O addresses */ 2244 2245 if (sockp->pcs_flags & PCS_WAITING) { 2246 io_ints &= ~(1 << i); 2247 continue; 2248 } 2249 2250 if (sockp->pcs_flags & PCS_CARD_IO) 2251 card_type = IF_IO; 2252 else 2253 card_type = IF_MEMORY; 2254 2255 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2256 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2257 2258 value = pcic_change(pcic, i); 2259 2260 if ((value != 0) || (value_cb != 0)) { 2261 int x = pcic->pc_cb_arg; 2262 2263 ret = DDI_INTR_CLAIMED; 2264 2265 #if defined(PCIC_DEBUG) 2266 pcic_err(pcic->dip, 0x9, 2267 "card_type = %d, value_cb = 0x%x\n", 2268 card_type, 2269 value_cb ? value_cb : 2270 pcic_getcb(pcic, CB_STATUS_EVENT)); 2271 if (pcic_debug) 2272 cmn_err(CE_CONT, 2273 "\tchange on socket %d (%x)\n", i, 2274 value); 2275 #endif 2276 /* find out what happened */ 2277 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2278 2279 /* acknowledge the interrupt */ 2280 if (value_cb) 2281 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2282 2283 if (value) 2284 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2285 value); 2286 2287 if (pcic->pc_callback == NULL) { 2288 /* if not callback handler, nothing to do */ 2289 continue; 2290 } 2291 2292 /* Card Detect */ 2293 if (value & PCIC_CD_DETECT || 2294 value_cb & CB_PS_CCDMASK) { 2295 uint8_t irq; 2296 #if defined(PCIC_DEBUG) 2297 if (pcic_debug) 2298 cmn_err(CE_CONT, 2299 "\tcd_detect: status=%x," 2300 " flags=%x\n", 2301 status, sockp->pcs_flags); 2302 #else 2303 #ifdef lint 2304 if (status == 0) 2305 status++; 2306 #endif 2307 #endif 2308 /* 2309 * Turn off all interrupts for this socket here. 2310 */ 2311 irq = pcic_getb(pcic, sockp->pcs_socket, 2312 PCIC_MANAGEMENT_INT); 2313 irq &= ~PCIC_CHANGE_MASK; 2314 pcic_putb(pcic, sockp->pcs_socket, 2315 PCIC_MANAGEMENT_INT, irq); 2316 2317 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2318 2319 /* 2320 * Put the socket in debouncing state so that 2321 * the leaf driver won't receive interrupts. 2322 * Crucial for handling surprise-removal. 2323 */ 2324 sockp->pcs_flags |= PCS_DEBOUNCING; 2325 2326 if (!sockp->pcs_cd_softint_flg) { 2327 sockp->pcs_cd_softint_flg = 1; 2328 (void) ddi_intr_trigger_softint( 2329 sockp->pcs_cd_softint_hdl, NULL); 2330 } 2331 2332 io_ints &= ~(1 << i); 2333 } /* PCIC_CD_DETECT */ 2334 2335 /* Ready/Change Detect */ 2336 sockp->pcs_state ^= SBM_RDYBSY; 2337 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2338 sockp->pcs_flags |= PCS_READY; 2339 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2340 } 2341 2342 /* Battery Warn Detect */ 2343 if (card_type == IF_MEMORY && 2344 value & PCIC_BW_DETECT && 2345 !(sockp->pcs_state & SBM_BVD2)) { 2346 sockp->pcs_state |= SBM_BVD2; 2347 PC_CALLBACK(pcic->dip, x, 2348 PCE_CARD_BATTERY_WARN, i); 2349 } 2350 2351 /* Battery Dead Detect */ 2352 if (value & PCIC_BD_DETECT) { 2353 /* 2354 * need to work out event if RI not enabled 2355 * and card_type == IF_IO 2356 */ 2357 if (card_type == IF_MEMORY && 2358 !(sockp->pcs_state & SBM_BVD1)) { 2359 sockp->pcs_state |= SBM_BVD1; 2360 PC_CALLBACK(pcic->dip, x, 2361 PCE_CARD_BATTERY_DEAD, 2362 i); 2363 } else { 2364 /* 2365 * information in pin replacement 2366 * register if one is available 2367 */ 2368 PC_CALLBACK(pcic->dip, x, 2369 PCE_CARD_STATUS_CHANGE, 2370 i); 2371 } /* IF_MEMORY */ 2372 } /* PCIC_BD_DETECT */ 2373 } /* if pcic_change */ 2374 /* 2375 * for any controllers that we can detect whether a socket 2376 * had an interrupt for the PC Card, we should sort that out 2377 * here. 2378 */ 2379 } /* for pc_numsockets */ 2380 2381 /* 2382 * If we're on a PCI bus, we may need to cycle through each IO 2383 * interrupt handler that is registered since they all 2384 * share the same interrupt line. 2385 */ 2386 2387 2388 #if defined(PCIC_DEBUG) 2389 pcic_err(pcic->dip, 0xf, 2390 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2391 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2392 #endif 2393 2394 if (io_ints) { 2395 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED) 2396 ret = DDI_INTR_CLAIMED; 2397 } 2398 2399 mutex_exit(&pcic->intr_lock); 2400 2401 #if defined(PCIC_DEBUG) 2402 pcic_err(pcic->dip, 0xf, 2403 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2404 ret, value, DDI_INTR_CLAIMED); 2405 #endif 2406 2407 return (ret); 2408 } 2409 2410 /* 2411 * pcic_change() 2412 * check to see if this socket had a change in state 2413 * by checking the status change register 2414 */ 2415 static int 2416 pcic_change(pcicdev_t *pcic, int socket) 2417 { 2418 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2419 } 2420 2421 /* 2422 * pcic_do_io_intr - calls client interrupt handlers 2423 */ 2424 static int 2425 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2426 { 2427 inthandler_t *tmp; 2428 int ret = DDI_INTR_UNCLAIMED; 2429 2430 #if defined(PCIC_DEBUG) 2431 pcic_err(pcic->dip, 0xf, 2432 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2433 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2434 #endif 2435 2436 if (pcic->irq_top != NULL) { 2437 tmp = pcic->irq_current; 2438 2439 do { 2440 int cur = pcic->irq_current->socket; 2441 pcic_socket_t *sockp = 2442 &pcic->pc_sockets[cur]; 2443 2444 #if defined(PCIC_DEBUG) 2445 pcic_err(pcic->dip, 0xf, 2446 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2447 sockp->pcs_flags, PCS_CARD_PRESENT); 2448 pcic_err(pcic->dip, 0xf, 2449 "\t sockets=%d cur=%d intr=%p arg1=%p " 2450 "arg2=%p\n", 2451 sockets, cur, (void *)pcic->irq_current->intr, 2452 pcic->irq_current->arg1, 2453 pcic->irq_current->arg2); 2454 #endif 2455 if ((sockp->pcs_flags & PCS_CARD_PRESENT) && 2456 !(sockp->pcs_flags & PCS_DEBOUNCING) && 2457 (sockets & (1 << cur))) { 2458 2459 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2460 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2461 ret = DDI_INTR_CLAIMED; 2462 2463 #if defined(PCIC_DEBUG) 2464 pcic_err(pcic->dip, 0xf, 2465 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2466 ret, DDI_INTR_CLAIMED); 2467 #endif 2468 } 2469 2470 2471 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2472 pcic->irq_current = pcic->irq_top; 2473 2474 } while (pcic->irq_current != tmp); 2475 2476 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2477 pcic->irq_current = pcic->irq_top; 2478 2479 } else { 2480 ret = DDI_INTR_UNCLAIMED; 2481 } 2482 2483 #if defined(PCIC_DEBUG) 2484 pcic_err(pcic->dip, 0xf, 2485 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2486 ret, DDI_INTR_CLAIMED); 2487 #endif 2488 2489 return (ret); 2490 2491 } 2492 2493 /* 2494 * pcic_inquire_adapter() 2495 * SocketServices InquireAdapter function 2496 * get characteristics of the physical adapter 2497 */ 2498 /*ARGSUSED*/ 2499 static int 2500 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2501 { 2502 anp_t *anp = ddi_get_driver_private(dip); 2503 pcicdev_t *pcic = anp->an_private; 2504 2505 config->NumSockets = pcic->pc_numsockets; 2506 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2507 config->NumEDCs = 0; 2508 config->AdpCaps = 0; 2509 config->ActiveHigh = 0; 2510 config->ActiveLow = PCIC_AVAIL_IRQS; 2511 config->NumPower = pcic->pc_numpower; 2512 config->power_entry = pcic->pc_power; /* until we resolve this */ 2513 #if defined(PCIC_DEBUG) 2514 if (pcic_debug) { 2515 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2516 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2517 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2518 } 2519 #endif 2520 config->ResourceFlags = 0; 2521 switch (pcic->pc_intr_mode) { 2522 case PCIC_INTR_MODE_PCI_1: 2523 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2524 RES_IRQ_SHAREABLE; 2525 break; 2526 } 2527 return (SUCCESS); 2528 } 2529 2530 /* 2531 * pcic_callback() 2532 * The PCMCIA nexus calls us via this function 2533 * in order to set the callback function we are 2534 * to call the nexus with 2535 */ 2536 /*ARGSUSED*/ 2537 static int 2538 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2539 { 2540 anp_t *anp = ddi_get_driver_private(dip); 2541 pcicdev_t *pcic = anp->an_private; 2542 2543 if (handler != NULL) { 2544 pcic->pc_callback = handler; 2545 pcic->pc_cb_arg = arg; 2546 pcic->pc_flags |= PCF_CALLBACK; 2547 } else { 2548 pcic->pc_callback = NULL; 2549 pcic->pc_cb_arg = 0; 2550 pcic->pc_flags &= ~PCF_CALLBACK; 2551 } 2552 /* 2553 * we're now registered with the nexus 2554 * it is acceptable to do callbacks at this point. 2555 * don't call back from here though since it could block 2556 */ 2557 return (PC_SUCCESS); 2558 } 2559 2560 /* 2561 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2562 * calculate the speed bits from the specified memory speed 2563 * there may be more to do here 2564 */ 2565 2566 static int 2567 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2568 { 2569 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2570 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2571 2572 switch (pcic->pc_type) { 2573 case PCIC_I82365SL: 2574 case PCIC_VADEM: 2575 case PCIC_VADEM_VG469: 2576 default: 2577 /* Intel chip wants it in waitstates */ 2578 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2579 if (speed <= wspeed) 2580 wspeed = 0; 2581 else if (speed <= (wspeed += mhztons(bspeed))) 2582 wspeed = 1; 2583 else if (speed <= (wspeed += mhztons(bspeed))) 2584 wspeed = 2; 2585 else 2586 wspeed = 3; 2587 wspeed <<= 6; /* put in right bit positions */ 2588 break; 2589 2590 case PCIC_INTEL_i82092: 2591 wspeed = SYSMEM_82092_80NS; 2592 if (speed > 80) 2593 wspeed = SYSMEM_82092_100NS; 2594 if (speed > 100) 2595 wspeed = SYSMEM_82092_150NS; 2596 if (speed > 150) 2597 wspeed = SYSMEM_82092_200NS; 2598 if (speed > 200) 2599 wspeed = SYSMEM_82092_250NS; 2600 if (speed > 250) 2601 wspeed = SYSMEM_82092_600NS; 2602 wspeed <<= 5; /* put in right bit positions */ 2603 break; 2604 2605 } /* switch */ 2606 2607 return (wspeed); 2608 } 2609 2610 /* 2611 * These values are taken from the PC Card Standard Electrical Specification. 2612 * Generally the larger value is taken if 2 are possible. 2613 */ 2614 static struct pcic_card_times { 2615 uint16_t cycle; /* Speed as found in the atribute space of he card. */ 2616 uint16_t setup; /* Corresponding address setup time. */ 2617 uint16_t width; /* Corresponding width, OE or WE. */ 2618 uint16_t hold; /* Corresponding data or address hold time. */ 2619 } pcic_card_times[] = { 2620 2621 /* 2622 * Note: The rounded up times for 250, 200 & 150 have been increased 2623 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2624 * See BugID 00663. 2625 */ 2626 2627 /* 2628 * Rounded up times Original times from 2629 * that add up to the the PCMCIA Spec. 2630 * cycle time. 2631 */ 2632 {600, 180, 370, 140}, /* 100, 300, 70 */ 2633 {400, 120, 300, 90}, /* Made this one up */ 2634 {250, 100, 190, 70}, /* 30, 150, 30 */ 2635 {200, 80, 170, 70}, /* 20, 120, 30 */ 2636 {150, 50, 110, 40}, /* 20, 80, 20 */ 2637 {100, 40, 80, 40}, /* 10, 60, 15 */ 2638 {0, 10, 60, 15} /* 10, 60, 15 */ 2639 }; 2640 2641 /* 2642 * pcic_set_cdtimers 2643 * This is specific to several Cirrus Logic chips 2644 */ 2645 static void 2646 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2647 { 2648 int cmd, set, rec, offset, clk_pulse; 2649 struct pcic_card_times *ctp; 2650 2651 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2652 offset = 3; 2653 else 2654 offset = 0; 2655 2656 clk_pulse = mhztons(pcic->bus_speed); 2657 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++); 2658 2659 /* 2660 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2661 */ 2662 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2663 if (set < 0) 2664 set = 0; 2665 2666 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2667 if (cmd < 0) 2668 cmd = 0; 2669 2670 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2671 if (rec < 0) 2672 rec = 0; 2673 2674 #if defined(PCIC_DEBUG) 2675 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2676 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2677 (unsigned)speed, offset == 3 ? 1 : 0, 2678 ctp->cycle, clk_pulse, cmd, set, rec); 2679 #endif 2680 2681 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2682 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2683 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2684 } 2685 2686 /* 2687 * pcic_set_window 2688 * essentially the same as the Socket Services specification 2689 * We use socket and not adapter since they are identifiable 2690 * but the rest is the same 2691 * 2692 * dip pcic driver's device information 2693 * window parameters for the request 2694 */ 2695 static int 2696 pcic_set_window(dev_info_t *dip, set_window_t *window) 2697 { 2698 anp_t *anp = ddi_get_driver_private(dip); 2699 pcicdev_t *pcic = anp->an_private; 2700 int select; 2701 int socket, pages, which, ret; 2702 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2703 ra_return_t res; 2704 ndi_ra_request_t req; 2705 uint32_t base = window->base; 2706 2707 #if defined(PCIC_DEBUG) 2708 if (pcic_debug) { 2709 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2710 cmn_err(CE_CONT, 2711 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2712 window->window, window->socket, window->WindowSize, 2713 window->speed); 2714 cmn_err(CE_CONT, 2715 "\tbase=%x, state=%x\n", (unsigned)window->base, 2716 (unsigned)window->state); 2717 } 2718 #endif 2719 2720 /* 2721 * do some basic sanity checking on what we support 2722 * we don't do paged mode 2723 */ 2724 if (window->state & WS_PAGED) { 2725 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2726 return (BAD_ATTRIBUTE); 2727 } 2728 2729 /* 2730 * we don't care about previous mappings. 2731 * Card Services will deal with that so don't 2732 * even check 2733 */ 2734 2735 socket = window->socket; 2736 2737 if (!(window->state & WS_IO)) { 2738 int win, tmp; 2739 pcs_memwin_t *memp; 2740 #if defined(PCIC_DEBUG) 2741 if (pcic_debug) 2742 cmn_err(CE_CONT, "\twindow type is memory\n"); 2743 #endif 2744 /* this is memory window mapping */ 2745 win = window->window % PCIC_NUMWINSOCK; 2746 tmp = window->window / PCIC_NUMWINSOCK; 2747 2748 /* only windows 2-6 can do memory mapping */ 2749 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2750 cmn_err(CE_CONT, 2751 "\tattempt to map to non-mem window\n"); 2752 return (BAD_WINDOW); 2753 } 2754 2755 if (window->WindowSize == 0) 2756 window->WindowSize = MEM_MIN; 2757 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2758 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2759 return (BAD_SIZE); 2760 } 2761 2762 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2763 2764 memp = &sockp->pcs_windows[win].mem; 2765 memp->pcw_speed = window->speed; 2766 2767 win -= PCIC_IOWINDOWS; /* put in right range */ 2768 2769 if (window->WindowSize != memp->pcw_len) 2770 which = memp->pcw_len; 2771 else 2772 which = 0; 2773 2774 if (window->state & WS_ENABLED) { 2775 uint32_t wspeed; 2776 #if defined(PCIC_DEBUG) 2777 if (pcic_debug) { 2778 cmn_err(CE_CONT, 2779 "\tbase=%x, win=%d\n", (unsigned)base, 2780 win); 2781 if (which) 2782 cmn_err(CE_CONT, 2783 "\tneed to remap window\n"); 2784 } 2785 #endif 2786 2787 if (which && (memp->pcw_status & PCW_MAPPED)) { 2788 ddi_regs_map_free(&memp->pcw_handle); 2789 res.ra_addr_lo = memp->pcw_base; 2790 res.ra_len = memp->pcw_len; 2791 (void) pcmcia_free_mem(memp->res_dip, &res); 2792 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2793 memp->pcw_hostmem = NULL; 2794 memp->pcw_base = NULL; 2795 memp->pcw_len = 0; 2796 } 2797 2798 which = window->WindowSize >> PAGE_SHIFT; 2799 2800 if (!(memp->pcw_status & PCW_MAPPED)) { 2801 ret = 0; 2802 2803 memp->pcw_base = base; 2804 bzero(&req, sizeof (req)); 2805 req.ra_len = which << PAGE_SHIFT; 2806 req.ra_addr = (uint64_t)memp->pcw_base; 2807 req.ra_boundbase = pcic->pc_base; 2808 req.ra_boundlen = pcic->pc_bound; 2809 req.ra_flags = (memp->pcw_base ? 2810 NDI_RA_ALLOC_SPECIFIED : 0) | 2811 NDI_RA_ALLOC_BOUNDED; 2812 req.ra_align_mask = 2813 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2814 #if defined(PCIC_DEBUG) 2815 pcic_err(dip, 8, 2816 "\tlen 0x%"PRIx64 2817 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2818 " blen 0x%"PRIx64" flags 0x%x" 2819 " algn 0x%"PRIx64"\n", 2820 req.ra_len, req.ra_addr, 2821 req.ra_boundbase, 2822 req.ra_boundlen, req.ra_flags, 2823 req.ra_align_mask); 2824 #endif 2825 2826 ret = pcmcia_alloc_mem(dip, &req, &res, 2827 &memp->res_dip); 2828 if (ret == DDI_FAILURE) { 2829 mutex_exit(&pcic->pc_lock); 2830 cmn_err(CE_WARN, 2831 "\tpcmcia_alloc_mem() failed\n"); 2832 return (BAD_SIZE); 2833 } 2834 memp->pcw_base = res.ra_addr_lo; 2835 base = memp->pcw_base; 2836 2837 #if defined(PCIC_DEBUG) 2838 if (pcic_debug) 2839 cmn_err(CE_CONT, 2840 "\tsetwindow: new base=%x\n", 2841 (unsigned)memp->pcw_base); 2842 #endif 2843 memp->pcw_len = window->WindowSize; 2844 2845 which = pcmcia_map_reg(pcic->dip, 2846 window->child, 2847 &res, 2848 (uint32_t)(window->state & 2849 0xffff) | 2850 (window->socket << 16), 2851 (caddr_t *)&memp->pcw_hostmem, 2852 &memp->pcw_handle, 2853 &window->attr, NULL); 2854 2855 if (which != DDI_SUCCESS) { 2856 2857 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2858 "failed\n"); 2859 2860 res.ra_addr_lo = memp->pcw_base; 2861 res.ra_len = memp->pcw_len; 2862 (void) pcmcia_free_mem(memp->res_dip, &res); 2863 2864 mutex_exit(&pcic->pc_lock); 2865 2866 return (BAD_WINDOW); 2867 } 2868 memp->pcw_status |= PCW_MAPPED; 2869 #if defined(PCIC_DEBUG) 2870 if (pcic_debug) 2871 cmn_err(CE_CONT, 2872 "\tmap=%x, hostmem=%p\n", 2873 which, 2874 (void *)memp->pcw_hostmem); 2875 #endif 2876 } else { 2877 base = memp->pcw_base; 2878 } 2879 2880 /* report the handle back to caller */ 2881 window->handle = memp->pcw_handle; 2882 2883 #if defined(PCIC_DEBUG) 2884 if (pcic_debug) { 2885 cmn_err(CE_CONT, 2886 "\twindow mapped to %x@%x len=%d\n", 2887 (unsigned)window->base, 2888 (unsigned)memp->pcw_base, 2889 memp->pcw_len); 2890 } 2891 #endif 2892 2893 /* find the register set offset */ 2894 select = win * PCIC_MEM_1_OFFSET; 2895 #if defined(PCIC_DEBUG) 2896 if (pcic_debug) 2897 cmn_err(CE_CONT, "\tselect=%x\n", select); 2898 #endif 2899 2900 /* 2901 * at this point, the register window indicator has 2902 * been converted to be an offset from the first 2903 * set of registers that are used for programming 2904 * the window mapping and the offset used to select 2905 * the correct set of registers to access the 2906 * specified socket. This allows basing everything 2907 * off the _0 window 2908 */ 2909 2910 /* map the physical page base address */ 2911 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2912 which |= (window->speed <= MEM_SPEED_MIN) ? 2913 SYSMEM_ZERO_WAIT : 0; 2914 2915 /* need to select register set */ 2916 select = PCIC_MEM_1_OFFSET * win; 2917 2918 pcic_putb(pcic, socket, 2919 PCIC_SYSMEM_0_STARTLOW + select, 2920 SYSMEM_LOW(base)); 2921 pcic_putb(pcic, socket, 2922 PCIC_SYSMEM_0_STARTHI + select, 2923 SYSMEM_HIGH(base) | which); 2924 2925 /* 2926 * Some adapters can decode window addresses greater 2927 * than 16-bits worth, so handle them here. 2928 */ 2929 switch (pcic->pc_type) { 2930 case PCIC_INTEL_i82092: 2931 pcic_putb(pcic, socket, 2932 PCIC_82092_CPAGE, 2933 SYSMEM_EXT(base)); 2934 break; 2935 case PCIC_CL_PD6729: 2936 case PCIC_CL_PD6730: 2937 clext_reg_write(pcic, socket, 2938 PCIC_CLEXT_MMAP0_UA + win, 2939 SYSMEM_EXT(base)); 2940 break; 2941 case PCIC_TI_PCI1130: 2942 /* 2943 * Note that the TI chip has one upper byte 2944 * per socket so all windows get bound to a 2945 * 16MB segment. This must be detected and 2946 * handled appropriately. We can detect that 2947 * it is done by seeing if the pc_base has 2948 * changed and changing when the register 2949 * is first set. This will force the bounds 2950 * to be correct. 2951 */ 2952 if (pcic->pc_bound == 0xffffffff) { 2953 pcic_putb(pcic, socket, 2954 PCIC_TI_WINDOW_PAGE_PCI, 2955 SYSMEM_EXT(base)); 2956 pcic->pc_base = SYSMEM_EXT(base) << 24; 2957 pcic->pc_bound = 0x1000000; 2958 } 2959 break; 2960 case PCIC_TI_PCI1031: 2961 case PCIC_TI_PCI1131: 2962 case PCIC_TI_PCI1250: 2963 case PCIC_TI_PCI1225: 2964 case PCIC_TI_PCI1221: 2965 case PCIC_SMC_34C90: 2966 case PCIC_CL_PD6832: 2967 case PCIC_RICOH_RL5C466: 2968 case PCIC_TI_PCI1410: 2969 case PCIC_ENE_1410: 2970 case PCIC_TI_PCI1510: 2971 case PCIC_TI_PCI1520: 2972 case PCIC_O2_OZ6912: 2973 case PCIC_TI_PCI1420: 2974 case PCIC_ENE_1420: 2975 case PCIC_TI_VENDOR: 2976 case PCIC_TOSHIBA_TOPIC100: 2977 case PCIC_TOSHIBA_TOPIC95: 2978 case PCIC_TOSHIBA_VENDOR: 2979 case PCIC_RICOH_VENDOR: 2980 case PCIC_O2MICRO_VENDOR: 2981 pcic_putb(pcic, socket, 2982 PCIC_YENTA_MEM_PAGE + win, 2983 SYSMEM_EXT(base)); 2984 break; 2985 default: 2986 cmn_err(CE_NOTE, "pcic_set_window: unknown " 2987 "cardbus vendor:0x%X\n", 2988 pcic->pc_type); 2989 pcic_putb(pcic, socket, 2990 PCIC_YENTA_MEM_PAGE + win, 2991 SYSMEM_EXT(base)); 2992 2993 break; 2994 } /* switch */ 2995 2996 /* 2997 * specify the length of the mapped range 2998 * we convert to pages (rounding up) so that 2999 * the hardware gets the right thing 3000 */ 3001 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 3002 3003 /* 3004 * Setup this window's timing. 3005 */ 3006 switch (pcic->pc_type) { 3007 case PCIC_CL_PD6729: 3008 case PCIC_CL_PD6730: 3009 case PCIC_CL_PD6710: 3010 case PCIC_CL_PD6722: 3011 wspeed = SYSMEM_CLTIMER_SET_0; 3012 pcic_set_cdtimers(pcic, socket, 3013 window->speed, 3014 wspeed); 3015 break; 3016 3017 case PCIC_INTEL_i82092: 3018 default: 3019 wspeed = pcic_calc_speed(pcic, window->speed); 3020 break; 3021 } /* switch */ 3022 3023 #if defined(PCIC_DEBUG) 3024 if (pcic_debug) 3025 cmn_err(CE_CONT, 3026 "\twindow %d speed bits = %x for " 3027 "%dns\n", 3028 win, (unsigned)wspeed, window->speed); 3029 #endif 3030 3031 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 3032 SYSMEM_LOW(base + 3033 (pages * PCIC_PAGE)-1)); 3034 3035 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 3036 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 3037 wspeed); 3038 3039 /* 3040 * now map the card's memory pages - we start with page 3041 * 0 3042 * we also default to AM -- set page might change it 3043 */ 3044 base = memp->pcw_base; 3045 pcic_putb(pcic, socket, 3046 PCIC_CARDMEM_0_LOW + select, 3047 CARDMEM_LOW(0 - (uint32_t)base)); 3048 3049 pcic_putb(pcic, socket, 3050 PCIC_CARDMEM_0_HI + select, 3051 CARDMEM_HIGH(0 - (uint32_t)base) | 3052 CARDMEM_REG_ACTIVE); 3053 3054 /* 3055 * enable the window even though redundant 3056 * and SetPage may do it again. 3057 */ 3058 select = pcic_getb(pcic, socket, 3059 PCIC_MAPPING_ENABLE); 3060 select |= SYSMEM_WINDOW(win); 3061 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3062 memp->pcw_offset = 0; 3063 memp->pcw_status |= PCW_ENABLED; 3064 } else { 3065 /* 3066 * not only do we unmap the memory, the 3067 * window has been turned off. 3068 */ 3069 if (which && memp->pcw_status & PCW_MAPPED) { 3070 ddi_regs_map_free(&memp->pcw_handle); 3071 res.ra_addr_lo = memp->pcw_base; 3072 res.ra_len = memp->pcw_len; 3073 (void) pcmcia_free_mem(memp->res_dip, &res); 3074 memp->pcw_hostmem = NULL; 3075 memp->pcw_status &= ~PCW_MAPPED; 3076 } 3077 3078 /* disable current mapping */ 3079 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3080 select &= ~SYSMEM_WINDOW(win); 3081 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3082 memp->pcw_status &= ~PCW_ENABLED; 3083 } 3084 memp->pcw_len = window->WindowSize; 3085 window->handle = memp->pcw_handle; 3086 #if defined(PCIC_DEBUG) 3087 if (pcic_debug) 3088 xxdmp_all_regs(pcic, window->socket, -1); 3089 #endif 3090 } else { 3091 /* 3092 * This is a request for an IO window 3093 */ 3094 int win, tmp; 3095 pcs_iowin_t *winp; 3096 /* I/O windows */ 3097 #if defined(PCIC_DEBUG) 3098 if (pcic_debug) 3099 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3100 #endif 3101 3102 /* only windows 0 and 1 can do I/O */ 3103 win = window->window % PCIC_NUMWINSOCK; 3104 tmp = window->window / PCIC_NUMWINSOCK; 3105 3106 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3107 cmn_err(CE_WARN, 3108 "\twindow is out of range (%d)\n", 3109 window->window); 3110 return (BAD_WINDOW); 3111 } 3112 3113 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3114 3115 winp = &sockp->pcs_windows[win].io; 3116 winp->pcw_speed = window->speed; 3117 if (window->WindowSize != 1 && window->WindowSize & 1) { 3118 /* we don't want an odd-size window */ 3119 window->WindowSize++; 3120 } 3121 winp->pcw_len = window->WindowSize; 3122 3123 if (window->state & WS_ENABLED) { 3124 if (winp->pcw_status & PCW_MAPPED) { 3125 ddi_regs_map_free(&winp->pcw_handle); 3126 res.ra_addr_lo = winp->pcw_base; 3127 res.ra_len = winp->pcw_len; 3128 (void) pcmcia_free_io(winp->res_dip, &res); 3129 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3130 } 3131 3132 /* 3133 * if the I/O address wasn't allocated, allocate 3134 * it now. If it was allocated, it better 3135 * be free to use. 3136 * The winp->pcw_offset value is set and used 3137 * later on if the particular adapter 3138 * that we're running on has the ability 3139 * to translate IO accesses to the card 3140 * (such as some adapters in the Cirrus 3141 * Logic family). 3142 */ 3143 winp->pcw_offset = 0; 3144 3145 /* 3146 * Setup the request parameters for the 3147 * requested base and length. If 3148 * we're on an adapter that has 3149 * IO window offset registers, then 3150 * we don't need a specific base 3151 * address, just a length, and then 3152 * we'll cause the correct IO address 3153 * to be generated on the socket by 3154 * setting up the IO window offset 3155 * registers. 3156 * For adapters that support this capability, we 3157 * always use the IO window offset registers, 3158 * even if the passed base/length would be in 3159 * range. 3160 */ 3161 base = window->base; 3162 bzero(&req, sizeof (req)); 3163 req.ra_len = window->WindowSize; 3164 3165 req.ra_addr = (uint64_t) 3166 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3167 req.ra_flags = (req.ra_addr) ? 3168 NDI_RA_ALLOC_SPECIFIED : 0; 3169 3170 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3171 /* need to rethink this */ 3172 req.ra_boundbase = pcic->pc_iobase; 3173 req.ra_boundlen = pcic->pc_iobound; 3174 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3175 3176 #if defined(PCIC_DEBUG) 3177 pcic_err(dip, 8, 3178 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3179 "bbase 0x%"PRIx64 3180 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3181 PRIx64"\n", 3182 req.ra_len, (uint64_t)req.ra_addr, 3183 req.ra_boundbase, 3184 req.ra_boundlen, req.ra_flags, 3185 req.ra_align_mask); 3186 #endif 3187 3188 /* 3189 * Try to allocate the space. If we fail this, 3190 * return the appropriate error depending 3191 * on whether the caller specified a 3192 * specific base address or not. 3193 */ 3194 if (pcmcia_alloc_io(dip, &req, &res, 3195 &winp->res_dip) == DDI_FAILURE) { 3196 winp->pcw_status &= ~PCW_ENABLED; 3197 mutex_exit(&pcic->pc_lock); 3198 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3199 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3200 "bbase 0x%" PRIx64 3201 "blen 0x%" PRIx64 "flags 0x%x" 3202 "algn 0x%" PRIx64 "\n", 3203 req.ra_len, req.ra_addr, 3204 req.ra_boundbase, 3205 req.ra_boundlen, req.ra_flags, 3206 req.ra_align_mask); 3207 3208 return (base?BAD_BASE:BAD_SIZE); 3209 } /* pcmcia_alloc_io */ 3210 3211 /* 3212 * Don't change the original base. Either we use 3213 * the offset registers below (PCF_IO_REMAP is set) 3214 * or it was allocated correctly anyway. 3215 */ 3216 winp->pcw_base = res.ra_addr_lo; 3217 3218 #if defined(PCIC_DEBUG) 3219 pcic_err(dip, 8, 3220 "\tsetwindow: new base=%x orig base 0x%x\n", 3221 (unsigned)winp->pcw_base, base); 3222 #endif 3223 3224 if ((which = pcmcia_map_reg(pcic->dip, 3225 window->child, 3226 &res, 3227 (uint32_t)(window->state & 3228 0xffff) | 3229 (window->socket << 16), 3230 (caddr_t *)&winp->pcw_hostmem, 3231 &winp->pcw_handle, 3232 &window->attr, 3233 base)) != DDI_SUCCESS) { 3234 3235 cmn_err(CE_WARN, "pcmcia_map_reg()" 3236 "failed\n"); 3237 3238 res.ra_addr_lo = winp->pcw_base; 3239 res.ra_len = winp->pcw_len; 3240 (void) pcmcia_free_io(winp->res_dip, &res); 3241 3242 mutex_exit(&pcic->pc_lock); 3243 return (BAD_WINDOW); 3244 } 3245 3246 window->handle = winp->pcw_handle; 3247 winp->pcw_status |= PCW_MAPPED; 3248 3249 /* find the register set offset */ 3250 select = win * PCIC_IO_OFFSET; 3251 3252 #if defined(PCIC_DEBUG) 3253 if (pcic_debug) { 3254 cmn_err(CE_CONT, 3255 "\tenable: window=%d, select=%x, " 3256 "base=%x, handle=%p\n", 3257 win, select, 3258 (unsigned)window->base, 3259 (void *)window->handle); 3260 } 3261 #endif 3262 /* 3263 * at this point, the register window indicator has 3264 * been converted to be an offset from the first 3265 * set of registers that are used for programming 3266 * the window mapping and the offset used to select 3267 * the correct set of registers to access the 3268 * specified socket. This allows basing everything 3269 * off the _0 window 3270 */ 3271 3272 /* map the I/O base in */ 3273 pcic_putb(pcic, socket, 3274 PCIC_IO_ADDR_0_STARTLOW + select, 3275 LOW_BYTE((uint32_t)winp->pcw_base)); 3276 pcic_putb(pcic, socket, 3277 PCIC_IO_ADDR_0_STARTHI + select, 3278 HIGH_BYTE((uint32_t)winp->pcw_base)); 3279 3280 pcic_putb(pcic, socket, 3281 PCIC_IO_ADDR_0_STOPLOW + select, 3282 LOW_BYTE((uint32_t)winp->pcw_base + 3283 window->WindowSize - 1)); 3284 pcic_putb(pcic, socket, 3285 PCIC_IO_ADDR_0_STOPHI + select, 3286 HIGH_BYTE((uint32_t)winp->pcw_base + 3287 window->WindowSize - 1)); 3288 3289 /* 3290 * We've got the requested IO space, now see if we 3291 * need to adjust the IO window offset registers 3292 * so that the correct IO address is generated 3293 * at the socket. If this window doesn't have 3294 * this capability, then we're all done setting 3295 * up the IO resources. 3296 */ 3297 if (pcic->pc_flags & PCF_IO_REMAP) { 3298 3299 3300 /* 3301 * Note that only 16 bits are used to program 3302 * the registers but leave 32 bits on pcw_offset 3303 * so that we can generate the original base 3304 * in get_window() 3305 */ 3306 winp->pcw_offset = (base - winp->pcw_base); 3307 3308 pcic_putb(pcic, socket, 3309 PCIC_IO_OFFSET_LOW + 3310 (win * PCIC_IO_OFFSET_OFFSET), 3311 winp->pcw_offset & 0x0ff); 3312 pcic_putb(pcic, socket, 3313 PCIC_IO_OFFSET_HI + 3314 (win * PCIC_IO_OFFSET_OFFSET), 3315 (winp->pcw_offset >> 8) & 0x0ff); 3316 3317 } /* PCF_IO_REMAP */ 3318 3319 /* now get the other details (size, etc) right */ 3320 3321 /* 3322 * Set the data size control bits here. Most of the 3323 * adapters will ignore IOMEM_16BIT when 3324 * IOMEM_IOCS16 is set, except for the Intel 3325 * 82092, which only pays attention to the 3326 * IOMEM_16BIT bit. Sigh... Intel can't even 3327 * make a proper clone of their own chip. 3328 * The 82092 also apparently can't set the timing 3329 * of I/O windows. 3330 */ 3331 which = (window->state & WS_16BIT) ? 3332 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3333 3334 switch (pcic->pc_type) { 3335 case PCIC_CL_PD6729: 3336 case PCIC_CL_PD6730: 3337 case PCIC_CL_PD6710: 3338 case PCIC_CL_PD6722: 3339 case PCIC_CL_PD6832: 3340 /* 3341 * Select Timer Set 1 - this will take 3342 * effect when the PCIC_IO_CONTROL 3343 * register is written to later on; 3344 * the call to pcic_set_cdtimers 3345 * just sets up the timer itself. 3346 */ 3347 which |= IOMEM_CLTIMER_SET_1; 3348 pcic_set_cdtimers(pcic, socket, 3349 window->speed, 3350 IOMEM_CLTIMER_SET_1); 3351 which |= IOMEM_IOCS16; 3352 break; 3353 case PCIC_TI_PCI1031: 3354 3355 if (window->state & WS_16BIT) 3356 which |= IOMEM_WAIT16; 3357 3358 break; 3359 case PCIC_TI_PCI1130: 3360 3361 if (window->state & WS_16BIT) 3362 which |= IOMEM_WAIT16; 3363 3364 break; 3365 case PCIC_INTEL_i82092: 3366 break; 3367 default: 3368 if (window->speed > 3369 mhztons(pcic->bus_speed) * 3) 3370 which |= IOMEM_WAIT16; 3371 #ifdef notdef 3372 if (window->speed < 3373 mhztons(pcic->bus_speed) * 6) 3374 which |= IOMEM_ZERO_WAIT; 3375 #endif 3376 break; 3377 } /* switch (pc_type) */ 3378 3379 /* 3380 * Setup the data width and timing 3381 */ 3382 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3383 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3384 select |= IOMEM_SETWIN(win, which); 3385 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3386 3387 /* 3388 * Enable the IO window 3389 */ 3390 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3391 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3392 select | IOMEM_WINDOW(win)); 3393 3394 winp->pcw_status |= PCW_ENABLED; 3395 3396 #if defined(PCIC_DEBUG) 3397 if (pcic_debug) { 3398 cmn_err(CE_CONT, 3399 "\twhich = %x, select = %x (%x)\n", 3400 which, select, 3401 IOMEM_SETWIN(win, which)); 3402 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3403 } 3404 #endif 3405 } else { 3406 /* 3407 * not only do we unmap the IO space, the 3408 * window has been turned off. 3409 */ 3410 if (winp->pcw_status & PCW_MAPPED) { 3411 ddi_regs_map_free(&winp->pcw_handle); 3412 res.ra_addr_lo = winp->pcw_base; 3413 res.ra_len = winp->pcw_len; 3414 (void) pcmcia_free_io(winp->res_dip, &res); 3415 winp->pcw_status &= ~PCW_MAPPED; 3416 } 3417 3418 /* disable current mapping */ 3419 select = pcic_getb(pcic, socket, 3420 PCIC_MAPPING_ENABLE); 3421 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3422 select &= ~IOMEM_WINDOW(win)); 3423 winp->pcw_status &= ~PCW_ENABLED; 3424 3425 winp->pcw_base = 0; 3426 winp->pcw_len = 0; 3427 winp->pcw_offset = 0; 3428 window->base = 0; 3429 /* now make sure we don't accidentally re-enable */ 3430 /* find the register set offset */ 3431 select = win * PCIC_IO_OFFSET; 3432 pcic_putb(pcic, socket, 3433 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3434 pcic_putb(pcic, socket, 3435 PCIC_IO_ADDR_0_STARTHI + select, 0); 3436 pcic_putb(pcic, socket, 3437 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3438 pcic_putb(pcic, socket, 3439 PCIC_IO_ADDR_0_STOPHI + select, 0); 3440 } 3441 } 3442 mutex_exit(&pcic->pc_lock); 3443 3444 return (SUCCESS); 3445 } 3446 3447 /* 3448 * pcic_card_state() 3449 * compute the instantaneous Card State information 3450 */ 3451 static int 3452 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3453 { 3454 int value, result; 3455 #if defined(PCIC_DEBUG) 3456 int orig_value; 3457 #endif 3458 3459 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3460 3461 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3462 3463 #if defined(PCIC_DEBUG) 3464 orig_value = value; 3465 if (pcic_debug >= 8) 3466 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3467 (void *)sockp, 3468 value, 3469 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3470 sockp->pcs_socket); 3471 #endif 3472 /* 3473 * Lie to socket services if we are not ready. 3474 * This is when we are starting up or during debounce timeouts 3475 * or if the card is a cardbus card. 3476 */ 3477 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3478 !sockp->pcs_debounce_id && 3479 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3480 result = SBM_CD; 3481 3482 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3483 result |= SBM_WP; 3484 if (value & PCIC_POWER_ON) { 3485 if (value & PCIC_READY) 3486 result |= SBM_RDYBSY; 3487 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3488 if (value & PCIC_BVD1) 3489 result |= SBM_BVD1; 3490 if (value & PCIC_BVD2) 3491 result |= SBM_BVD2; 3492 } 3493 } else 3494 result = 0; 3495 3496 mutex_exit(&pcic->pc_lock); 3497 3498 #if defined(PCIC_DEBUG) 3499 pcic_err(pcic->dip, 8, 3500 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3501 (void *) sockp, orig_value, 3502 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3503 sockp->pcs_socket, result); 3504 #endif 3505 3506 return (result); 3507 } 3508 3509 /* 3510 * pcic_set_page() 3511 * SocketServices SetPage function 3512 * set the page of PC Card memory that should be in the mapped 3513 * window 3514 */ 3515 /*ARGSUSED*/ 3516 static int 3517 pcic_set_page(dev_info_t *dip, set_page_t *page) 3518 { 3519 anp_t *anp = ddi_get_driver_private(dip); 3520 pcicdev_t *pcic = anp->an_private; 3521 int select; 3522 int which, socket, window; 3523 uint32_t base; 3524 pcs_memwin_t *memp; 3525 3526 /* get real socket/window numbers */ 3527 window = page->window % PCIC_NUMWINSOCK; 3528 socket = page->window / PCIC_NUMWINSOCK; 3529 3530 #if defined(PCIC_DEBUG) 3531 if (pcic_debug) { 3532 cmn_err(CE_CONT, 3533 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3534 window, socket, page->page); 3535 } 3536 #endif 3537 /* only windows 2-6 work on memory */ 3538 if (window < PCIC_IOWINDOWS) 3539 return (BAD_WINDOW); 3540 3541 /* only one page supported (but any size) */ 3542 if (page->page != 0) 3543 return (BAD_PAGE); 3544 3545 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3546 3547 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3548 window -= PCIC_IOWINDOWS; 3549 3550 #if defined(PCIC_DEBUG) 3551 if (pcic_debug) 3552 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3553 (uint32_t)memp->pcw_base, 3554 (void *)memp->pcw_hostmem, memp->pcw_len); 3555 #endif 3556 3557 /* window must be enabled */ 3558 if (!(memp->pcw_status & PCW_ENABLED)) 3559 return (BAD_ATTRIBUTE); 3560 3561 /* find the register set offset */ 3562 select = window * PCIC_MEM_1_OFFSET; 3563 #if defined(PCIC_DEBUG) 3564 if (pcic_debug) 3565 cmn_err(CE_CONT, "\tselect=%x\n", select); 3566 #endif 3567 3568 /* 3569 * now map the card's memory pages - we start with page 0 3570 */ 3571 3572 which = 0; /* assume simple case */ 3573 if (page->state & PS_ATTRIBUTE) { 3574 which |= CARDMEM_REG_ACTIVE; 3575 memp->pcw_status |= PCW_ATTRIBUTE; 3576 } else { 3577 memp->pcw_status &= ~PCW_ATTRIBUTE; 3578 } 3579 3580 /* 3581 * if caller says Write Protect, enforce it. 3582 */ 3583 if (page->state & PS_WP) { 3584 which |= CARDMEM_WRITE_PROTECT; 3585 memp->pcw_status |= PCW_WP; 3586 } else { 3587 memp->pcw_status &= ~PCW_WP; 3588 } 3589 #if defined(PCIC_DEBUG) 3590 if (pcic_debug) { 3591 cmn_err(CE_CONT, "\tmemory type = %s\n", 3592 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3593 if (which & CARDMEM_WRITE_PROTECT) 3594 cmn_err(CE_CONT, "\twrite protect\n"); 3595 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3596 (unsigned)page->offset, 3597 (unsigned)memp->pcw_base, 3598 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3599 } 3600 #endif 3601 /* address computation based on 64MB range and not larger */ 3602 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3603 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3604 CARDMEM_LOW((int)page->offset - (int)base)); 3605 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3606 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3607 CARDMEM_HIGH((int)page->offset - base) | which); 3608 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3609 3610 /* 3611 * while not really necessary, this just makes sure 3612 * nothing turned the window off behind our backs 3613 */ 3614 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3615 which |= SYSMEM_WINDOW(window); 3616 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3617 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3618 3619 memp->pcw_offset = (off_t)page->offset; 3620 3621 #if defined(PCIC_DEBUG) 3622 if (pcic_debug) { 3623 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3624 (void *)memp->pcw_hostmem, 3625 (uint32_t)*memp->pcw_hostmem); 3626 3627 xxdmp_all_regs(pcic, socket, -1); 3628 3629 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3630 (void *)memp->pcw_hostmem, 3631 (uint32_t)*memp->pcw_hostmem); 3632 } 3633 #endif 3634 3635 if (which & PCW_ATTRIBUTE) 3636 pcic_mswait(pcic, socket, 2); 3637 3638 mutex_exit(&pcic->pc_lock); 3639 3640 return (SUCCESS); 3641 } 3642 3643 /* 3644 * pcic_set_vcc_level() 3645 * 3646 * set voltage based on adapter information 3647 * 3648 * this routine implements a limited solution for support of 3.3v cards. 3649 * the general solution, which would fully support the pcmcia spec 3650 * as far as allowing client drivers to request which voltage levels 3651 * to be set, requires more framework support and driver changes - ess 3652 */ 3653 static int 3654 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3655 { 3656 uint32_t socket_present_state; 3657 3658 #if defined(PCIC_DEBUG) 3659 if (pcic_debug) { 3660 cmn_err(CE_CONT, 3661 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3662 (void *)pcic, socket->VccLevel); 3663 } 3664 #endif 3665 3666 /* 3667 * check VccLevel 3668 * if this is zero, power is being turned off 3669 * if it is non-zero, power is being turned on. 3670 */ 3671 if (socket->VccLevel == 0) { 3672 return (0); 3673 } 3674 3675 /* 3676 * range checking for sanity's sake 3677 */ 3678 if (socket->VccLevel >= pcic->pc_numpower) { 3679 return (BAD_VCC); 3680 } 3681 3682 switch (pcic->pc_io_type) { 3683 /* 3684 * Yenta-compliant adapters have vcc info in the extended registers 3685 * Other adapters can be added as needed, but the 'default' case 3686 * has been left as it was previously so as not to break existing 3687 * adapters. 3688 */ 3689 case PCIC_IO_TYPE_YENTA: 3690 /* 3691 * Here we ignore the VccLevel passed in and read the 3692 * card type from the adapter socket present state register 3693 */ 3694 socket_present_state = 3695 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3696 PCIC_PRESENT_STATE_REG)); 3697 #if defined(PCIC_DEBUG) 3698 if (pcic_debug) { 3699 cmn_err(CE_CONT, 3700 "socket present state = 0x%x\n", 3701 socket_present_state); 3702 } 3703 #endif 3704 switch (socket_present_state & PCIC_VCC_MASK) { 3705 case PCIC_VCC_3VCARD: 3706 /* fall through */ 3707 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3708 socket->VccLevel = PCIC_VCC_3VLEVEL; 3709 return 3710 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3711 case PCIC_VCC_5VCARD: 3712 socket->VccLevel = PCIC_VCC_5VLEVEL; 3713 return 3714 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3715 default: 3716 /* 3717 * if no card is present, this can be the 3718 * case of a client making a SetSocket call 3719 * after card removal. In this case we return 3720 * the current power level 3721 */ 3722 return ((unsigned)ddi_get8(pcic->handle, 3723 pcic->ioaddr + CB_R2_OFFSET + 3724 PCIC_POWER_CONTROL)); 3725 } 3726 3727 default: 3728 3729 switch (socket->VccLevel) { 3730 case PCIC_VCC_3VLEVEL: 3731 return (BAD_VCC); 3732 case PCIC_VCC_5VLEVEL: 3733 /* enable Vcc */ 3734 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3735 default: 3736 return (BAD_VCC); 3737 } 3738 } 3739 } 3740 3741 3742 /* 3743 * pcic_set_socket() 3744 * Socket Services SetSocket call 3745 * sets basic socket configuration 3746 */ 3747 static int 3748 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3749 { 3750 anp_t *anp = ddi_get_driver_private(dip); 3751 pcicdev_t *pcic = anp->an_private; 3752 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3753 int irq, interrupt, mirq; 3754 int powerlevel = 0; 3755 int ind, value, orig_pwrctl; 3756 3757 #if defined(PCIC_DEBUG) 3758 if (pcic_debug) { 3759 cmn_err(CE_CONT, 3760 "pcic_set_socket(dip=%p, socket=%d)" 3761 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3762 socket->socket, socket->VccLevel, socket->Vpp1Level, 3763 socket->Vpp2Level); 3764 } 3765 #endif 3766 /* 3767 * check VccLevel, etc. before setting mutex 3768 * if this is zero, power is being turned off 3769 * if it is non-zero, power is being turned on. 3770 * the default case is to assume Vcc only. 3771 */ 3772 3773 /* this appears to be very implementation specific */ 3774 3775 if (socket->Vpp1Level != socket->Vpp2Level) 3776 return (BAD_VPP); 3777 3778 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3779 powerlevel = 0; 3780 sockp->pcs_vcc = 0; 3781 sockp->pcs_vpp1 = 0; 3782 sockp->pcs_vpp2 = 0; 3783 } else { 3784 #if defined(PCIC_DEBUG) 3785 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3786 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3787 #endif 3788 /* valid Vcc power level? */ 3789 if (socket->VccLevel >= pcic->pc_numpower) 3790 return (BAD_VCC); 3791 3792 switch (pcic_power[socket->VccLevel].PowerLevel) { 3793 case 33: /* 3.3V */ 3794 case 60: /* for bad CIS in Option GPRS card */ 3795 if (!(pcic->pc_flags & PCF_33VCAP)) { 3796 cmn_err(CE_WARN, 3797 "%s%d: Bad Request for 3.3V " 3798 "(Controller incapable)\n", 3799 ddi_get_name(pcic->dip), 3800 ddi_get_instance(pcic->dip)); 3801 return (BAD_VCC); 3802 } 3803 /* FALLTHROUGH */ 3804 case 50: /* 5V */ 3805 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3806 pcic_getcb(pcic, CB_PRESENT_STATE) & 3807 CB_PS_33VCARD) { 3808 /* 3809 * This is actually a 3.3V card. 3810 * Solaris Card Services 3811 * doesn't understand 3.3V 3812 * so we cheat and change 3813 * the setting to the one appropriate to 3.3V. 3814 * Note that this is the entry number 3815 * in the pcic_power[] array. 3816 */ 3817 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3818 } else 3819 sockp->pcs_vcc = socket->VccLevel; 3820 break; 3821 default: 3822 return (BAD_VCC); 3823 } 3824 3825 /* enable Vcc */ 3826 powerlevel = POWER_CARD_ENABLE; 3827 3828 #if defined(PCIC_DEBUG) 3829 if (pcic_debug) { 3830 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3831 socket->VccLevel, powerlevel); 3832 } 3833 #endif 3834 ind = 0; /* default index to 0 power */ 3835 if ((int)socket->Vpp1Level >= 0 && 3836 socket->Vpp1Level < pcic->pc_numpower) { 3837 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3838 & VPP1)) { 3839 return (BAD_VPP); 3840 } 3841 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3842 powerlevel |= pcic_vpp_levels[ind]; 3843 sockp->pcs_vpp1 = socket->Vpp1Level; 3844 } 3845 if ((int)socket->Vpp2Level >= 0 && 3846 socket->Vpp2Level < pcic->pc_numpower) { 3847 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3848 & VPP2)) { 3849 return (BAD_VPP); 3850 } 3851 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3852 powerlevel |= (pcic_vpp_levels[ind] << 2); 3853 sockp->pcs_vpp2 = socket->Vpp2Level; 3854 } 3855 3856 if (pcic->pc_flags & PCF_VPPX) { 3857 /* 3858 * this adapter doesn't allow separate Vpp1/Vpp2 3859 * if one is turned on, both are turned on and only 3860 * the Vpp1 bits should be set 3861 */ 3862 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3863 /* must be the same if one not zero */ 3864 if (sockp->pcs_vpp1 != 0 && 3865 sockp->pcs_vpp2 != 0) { 3866 cmn_err(CE_WARN, 3867 "%s%d: Bad Power Request " 3868 "(Vpp1/2 not the same)\n", 3869 ddi_get_name(pcic->dip), 3870 ddi_get_instance(pcic->dip)); 3871 return (BAD_VPP); 3872 } 3873 } 3874 powerlevel &= ~(3<<2); 3875 } 3876 3877 #if defined(PCIC_DEBUG) 3878 if (pcic_debug) { 3879 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3880 powerlevel, ind); 3881 } 3882 #endif 3883 } 3884 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3885 3886 /* turn socket->IREQRouting off while programming */ 3887 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3888 interrupt &= ~PCIC_INTR_MASK; 3889 if (pcic->pc_flags & PCF_USE_SMI) 3890 interrupt |= PCIC_INTR_ENABLE; 3891 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3892 3893 switch (pcic->pc_type) { 3894 case PCIC_INTEL_i82092: 3895 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3896 PCIC_82092_INT_DISABLE); 3897 break; 3898 default: 3899 break; 3900 } /* switch */ 3901 3902 /* the SCIntMask specifies events to detect */ 3903 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3904 3905 #if defined(PCIC_DEBUG) 3906 if (pcic_debug) 3907 cmn_err(CE_CONT, 3908 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3909 socket->SCIntMask, interrupt, mirq); 3910 #endif 3911 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3912 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3913 mirq & ~PCIC_CHANGE_MASK); 3914 3915 /* save the mask we want to use */ 3916 sockp->pcs_intmask = socket->SCIntMask; 3917 3918 /* 3919 * Until there is a card present it's not worth enabling 3920 * any interrupts except "Card detect". This is done 3921 * elsewhere in the driver so don't change things if 3922 * there is no card! 3923 */ 3924 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3925 3926 /* now update the hardware to reflect events desired */ 3927 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3928 mirq |= PCIC_BD_DETECT; 3929 3930 if (sockp->pcs_intmask & SBM_BVD2) 3931 mirq |= PCIC_BW_DETECT; 3932 3933 if (sockp->pcs_intmask & SBM_RDYBSY) 3934 mirq |= PCIC_RD_DETECT; 3935 3936 if (sockp->pcs_intmask & SBM_CD) 3937 mirq |= PCIC_CD_DETECT; 3938 } 3939 3940 if (sockp->pcs_flags & PCS_READY) { 3941 /* 3942 * card just came ready. 3943 * make sure enough time elapses 3944 * before touching it. 3945 */ 3946 sockp->pcs_flags &= ~PCS_READY; 3947 pcic_mswait(pcic, socket->socket, 10); 3948 } 3949 3950 #if defined(PCIC_DEBUG) 3951 if (pcic_debug) { 3952 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3953 } 3954 #endif 3955 3956 switch (pcic->pc_type) { 3957 case PCIC_I82365SL: 3958 case PCIC_VADEM: 3959 case PCIC_VADEM_VG469: 3960 /* 3961 * The Intel version has different options. This is a 3962 * special case of GPI which might be used for eject 3963 */ 3964 3965 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 3966 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 3967 pcic->pc_flags & PCF_GPI_EJECT) { 3968 irq |= PCIC_GPI_ENABLE; 3969 } else { 3970 irq &= ~PCIC_GPI_ENABLE; 3971 } 3972 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 3973 break; 3974 case PCIC_CL_PD6710: 3975 case PCIC_CL_PD6722: 3976 if (socket->IFType == IF_IO) { 3977 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 3978 value = pcic_getb(pcic, socket->socket, 3979 PCIC_MISC_CTL_1); 3980 if (pcic->pc_flags & PCF_AUDIO) 3981 value |= PCIC_MC_SPEAKER_ENB; 3982 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3983 value); 3984 } else { 3985 value = pcic_getb(pcic, socket->socket, 3986 PCIC_MISC_CTL_1); 3987 value &= ~PCIC_MC_SPEAKER_ENB; 3988 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3989 value); 3990 } 3991 break; 3992 case PCIC_CL_PD6729: 3993 case PCIC_CL_PD6730: 3994 case PCIC_CL_PD6832: 3995 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 3996 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 3997 value |= PCIC_MC_SPEAKER_ENB; 3998 } else { 3999 value &= ~PCIC_MC_SPEAKER_ENB; 4000 } 4001 4002 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4003 value |= PCIC_MC_3VCC; 4004 else 4005 value &= ~PCIC_MC_3VCC; 4006 4007 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 4008 break; 4009 4010 case PCIC_O2_OZ6912: 4011 value = pcic_getcb(pcic, CB_MISCCTRL); 4012 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 4013 value |= (1<<25); 4014 else 4015 value &= ~(1<<25); 4016 pcic_putcb(pcic, CB_MISCCTRL, value); 4017 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4018 powerlevel |= 0x08; 4019 break; 4020 4021 case PCIC_TI_PCI1250: 4022 case PCIC_TI_PCI1221: 4023 case PCIC_TI_PCI1225: 4024 case PCIC_TI_PCI1410: 4025 case PCIC_ENE_1410: 4026 case PCIC_TI_PCI1510: 4027 case PCIC_TI_PCI1520: 4028 case PCIC_TI_PCI1420: 4029 case PCIC_ENE_1420: 4030 value = ddi_get8(pcic->cfg_handle, 4031 pcic->cfgaddr + PCIC_CRDCTL_REG); 4032 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4033 value |= PCIC_CRDCTL_SPKR_ENBL; 4034 } else { 4035 value &= ~PCIC_CRDCTL_SPKR_ENBL; 4036 } 4037 ddi_put8(pcic->cfg_handle, 4038 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 4039 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4040 powerlevel |= 0x08; 4041 break; 4042 } 4043 4044 /* 4045 * ctlind processing -- we can ignore this 4046 * there aren't any outputs on the chip for this and 4047 * the GUI will display what it thinks is correct 4048 */ 4049 4050 /* 4051 * If outputs are enabled and the power is going off 4052 * turn off outputs first. 4053 */ 4054 4055 /* power setup -- if necessary */ 4056 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4057 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 4058 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4059 pcic_putb(pcic, socket->socket, 4060 PCIC_POWER_CONTROL, orig_pwrctl); 4061 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4062 } 4063 4064 if (pcic->pc_flags & PCF_CBPWRCTL) { 4065 value = pcic_cbus_powerctl(pcic, socket->socket); 4066 powerlevel = 0; 4067 } else 4068 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4069 4070 if (value != SUCCESS) { 4071 mutex_exit(&pcic->pc_lock); 4072 return (value); 4073 } 4074 4075 /* 4076 * If outputs were disabled and the power is going on 4077 * turn on outputs afterwards. 4078 */ 4079 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4080 orig_pwrctl = pcic_getb(pcic, socket->socket, 4081 PCIC_POWER_CONTROL); 4082 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4083 pcic_putb(pcic, socket->socket, 4084 PCIC_POWER_CONTROL, orig_pwrctl); 4085 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4086 } 4087 4088 /* 4089 * Once we have done the power stuff can re-enable management 4090 * interrupts. 4091 */ 4092 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4093 4094 #if defined(PCIC_DEBUG) 4095 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4096 "cbctl 0x%x\n", 4097 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4098 pcic_getcb(pcic, CB_CONTROL)); 4099 #endif 4100 4101 /* irq processing */ 4102 if (socket->IFType == IF_IO) { 4103 /* IRQ only for I/O */ 4104 irq = socket->IREQRouting & PCIC_INTR_MASK; 4105 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4106 value &= ~PCIC_INTR_MASK; 4107 4108 /* to enable I/O operation */ 4109 value |= PCIC_IO_CARD | PCIC_RESET; 4110 sockp->pcs_flags |= PCS_CARD_IO; 4111 if (irq != sockp->pcs_irq) { 4112 if (sockp->pcs_irq != 0) 4113 cmn_err(CE_CONT, 4114 "SetSocket: IRQ mismatch %x != %x!\n", 4115 irq, sockp->pcs_irq); 4116 else 4117 sockp->pcs_irq = irq; 4118 } 4119 irq = sockp->pcs_irq; 4120 4121 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4122 if (socket->IREQRouting & IRQ_ENABLE) { 4123 pcic_enable_io_intr(pcic, socket->socket, irq); 4124 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4125 } else { 4126 pcic_disable_io_intr(pcic, socket->socket); 4127 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4128 } 4129 #if defined(PCIC_DEBUG) 4130 if (pcic_debug) { 4131 cmn_err(CE_CONT, 4132 "\tsocket type is I/O and irq %x is %s\n", irq, 4133 (socket->IREQRouting & IRQ_ENABLE) ? 4134 "enabled" : "not enabled"); 4135 xxdmp_all_regs(pcic, socket->socket, 20); 4136 } 4137 #endif 4138 } else { 4139 /* make sure I/O mode is off */ 4140 4141 sockp->pcs_irq = 0; 4142 4143 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4144 value &= ~PCIC_IO_CARD; 4145 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4146 pcic_disable_io_intr(pcic, socket->socket); 4147 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4148 } 4149 4150 sockp->pcs_state &= ~socket->State; 4151 4152 mutex_exit(&pcic->pc_lock); 4153 return (SUCCESS); 4154 } 4155 4156 /* 4157 * pcic_inquire_socket() 4158 * SocketServices InquireSocket function 4159 * returns basic characteristics of the socket 4160 */ 4161 /*ARGSUSED*/ 4162 static int 4163 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4164 { 4165 anp_t *anp = ddi_get_driver_private(dip); 4166 pcicdev_t *pcic = anp->an_private; 4167 int value; 4168 4169 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4170 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4171 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4172 value = pcic->pc_sockets[socket->socket].pcs_flags; 4173 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4174 socket->ActiveHigh = 0; 4175 /* these are the usable IRQs */ 4176 socket->ActiveLow = 0xfff0; 4177 return (SUCCESS); 4178 } 4179 4180 /* 4181 * pcic_inquire_window() 4182 * SocketServices InquireWindow function 4183 * returns detailed characteristics of the window 4184 * this is where windows get tied to sockets 4185 */ 4186 /*ARGSUSED*/ 4187 static int 4188 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4189 { 4190 int type, socket; 4191 4192 type = window->window % PCIC_NUMWINSOCK; 4193 socket = window->window / PCIC_NUMWINSOCK; 4194 4195 #if defined(PCIC_DEBUG) 4196 if (pcic_debug >= 8) 4197 cmn_err(CE_CONT, 4198 "pcic_inquire_window: window = %d/%d socket=%d\n", 4199 window->window, type, socket); 4200 #endif 4201 if (type < PCIC_IOWINDOWS) { 4202 window->WndCaps = WC_IO|WC_WAIT; 4203 type = IF_IO; 4204 } else { 4205 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4206 type = IF_MEMORY; 4207 } 4208 4209 /* initialize the socket map - one socket per window */ 4210 PR_ZERO(window->Sockets); 4211 PR_SET(window->Sockets, socket); 4212 4213 if (type == IF_IO) { 4214 iowin_char_t *io; 4215 io = &window->iowin_char; 4216 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4217 WC_16BIT; 4218 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4219 io->LastByte = (baseaddr_t)IOMEM_LAST; 4220 io->MinSize = IOMEM_MIN; 4221 io->MaxSize = IOMEM_MAX; 4222 io->ReqGran = IOMEM_GRAN; 4223 io->AddrLines = IOMEM_DECODE; 4224 io->EISASlot = 0; 4225 } else { 4226 mem_win_char_t *mem; 4227 mem = &window->mem_win_char; 4228 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4229 WC_16BIT|WC_WP; 4230 4231 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4232 mem->LastByte = (baseaddr_t)MEM_LAST; 4233 4234 mem->MinSize = MEM_MIN; 4235 mem->MaxSize = MEM_MAX; 4236 mem->ReqGran = PCIC_PAGE; 4237 mem->ReqBase = 0; 4238 mem->ReqOffset = PCIC_PAGE; 4239 mem->Slowest = MEM_SPEED_MAX; 4240 mem->Fastest = MEM_SPEED_MIN; 4241 } 4242 return (SUCCESS); 4243 } 4244 4245 /* 4246 * pcic_get_adapter() 4247 * SocketServices GetAdapter function 4248 * this is nearly a no-op. 4249 */ 4250 /*ARGSUSED*/ 4251 static int 4252 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4253 { 4254 anp_t *anp = ddi_get_driver_private(dip); 4255 pcicdev_t *pcic = anp->an_private; 4256 4257 if (pcic->pc_flags & PCF_INTRENAB) 4258 adapt->SCRouting = IRQ_ENABLE; 4259 adapt->state = 0; 4260 return (SUCCESS); 4261 } 4262 4263 /* 4264 * pcic_get_page() 4265 * SocketServices GetPage function 4266 * returns info about the window 4267 */ 4268 /*ARGSUSED*/ 4269 static int 4270 pcic_get_page(dev_info_t *dip, get_page_t *page) 4271 { 4272 anp_t *anp = ddi_get_driver_private(dip); 4273 pcicdev_t *pcic = anp->an_private; 4274 int socket, window; 4275 pcs_memwin_t *winp; 4276 4277 socket = page->window / PCIC_NUMWINSOCK; 4278 window = page->window % PCIC_NUMWINSOCK; 4279 4280 /* I/O windows are the first two */ 4281 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4282 return (BAD_WINDOW); 4283 } 4284 4285 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4286 4287 if (page->page != 0) 4288 return (BAD_PAGE); 4289 4290 page->state = 0; 4291 if (winp->pcw_status & PCW_ENABLED) 4292 page->state |= PS_ENABLED; 4293 if (winp->pcw_status & PCW_ATTRIBUTE) 4294 page->state |= PS_ATTRIBUTE; 4295 if (winp->pcw_status & PCW_WP) 4296 page->state |= PS_WP; 4297 4298 page->offset = (off_t)winp->pcw_offset; 4299 4300 return (SUCCESS); 4301 } 4302 4303 /* 4304 * pcic_get_socket() 4305 * SocketServices GetSocket 4306 * returns information about the current socket setting 4307 */ 4308 /*ARGSUSED*/ 4309 static int 4310 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4311 { 4312 anp_t *anp = ddi_get_driver_private(dip); 4313 pcicdev_t *pcic = anp->an_private; 4314 int socknum, irq_enabled; 4315 pcic_socket_t *sockp; 4316 4317 socknum = socket->socket; 4318 sockp = &pcic->pc_sockets[socknum]; 4319 4320 socket->SCIntMask = sockp->pcs_intmask; 4321 sockp->pcs_state = pcic_card_state(pcic, sockp); 4322 4323 socket->state = sockp->pcs_state; 4324 if (socket->state & SBM_CD) { 4325 socket->VccLevel = sockp->pcs_vcc; 4326 socket->Vpp1Level = sockp->pcs_vpp1; 4327 socket->Vpp2Level = sockp->pcs_vpp2; 4328 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4329 IRQ_ENABLE : 0; 4330 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4331 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4332 IF_IO : IF_MEMORY; 4333 } else { 4334 socket->VccLevel = 0; 4335 socket->Vpp1Level = 0; 4336 socket->Vpp2Level = 0; 4337 socket->IRQRouting = 0; 4338 socket->IFType = IF_MEMORY; 4339 } 4340 socket->CtlInd = 0; /* no indicators */ 4341 4342 return (SUCCESS); 4343 } 4344 4345 /* 4346 * pcic_get_status() 4347 * SocketServices GetStatus 4348 * returns status information about the PC Card in 4349 * the selected socket 4350 */ 4351 /*ARGSUSED*/ 4352 static int 4353 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4354 { 4355 anp_t *anp = ddi_get_driver_private(dip); 4356 pcicdev_t *pcic = anp->an_private; 4357 int socknum, irq_enabled; 4358 pcic_socket_t *sockp; 4359 4360 socknum = status->socket; 4361 sockp = &pcic->pc_sockets[socknum]; 4362 4363 status->CardState = pcic_card_state(pcic, sockp); 4364 status->SocketState = sockp->pcs_state; 4365 status->CtlInd = 0; /* no indicators */ 4366 4367 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4368 status->SocketState |= SBM_CD; 4369 if (status->CardState & SBM_CD) { 4370 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4371 IRQ_ENABLE : 0; 4372 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4373 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4374 IF_IO : IF_MEMORY; 4375 } else { 4376 status->IRQRouting = 0; 4377 status->IFType = IF_MEMORY; 4378 } 4379 4380 #if defined(PCIC_DEBUG) 4381 if (pcic_debug >= 8) 4382 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4383 "SocketState=%x\n", 4384 socknum, status->CardState, status->SocketState); 4385 #endif 4386 switch (pcic->pc_type) { 4387 uint32_t present_state; 4388 case PCIC_TI_PCI1410: 4389 case PCIC_TI_PCI1520: 4390 case PCIC_TI_PCI1420: 4391 case PCIC_ENE_1420: 4392 case PCIC_TOSHIBA_TOPIC100: 4393 case PCIC_TOSHIBA_TOPIC95: 4394 case PCIC_TOSHIBA_VENDOR: 4395 case PCIC_O2MICRO_VENDOR: 4396 case PCIC_TI_VENDOR: 4397 case PCIC_RICOH_VENDOR: 4398 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4399 if (present_state & PCIC_CB_CARD) 4400 status->IFType = IF_CARDBUS; 4401 #if defined(PCIC_DEBUG) 4402 if (pcic_debug >= 8) 4403 cmn_err(CE_CONT, "pcic_get_status: present_state=0x%x\n", 4404 present_state); 4405 #endif 4406 break; 4407 default: 4408 break; 4409 } 4410 4411 return (SUCCESS); 4412 } 4413 4414 /* 4415 * pcic_get_window() 4416 * SocketServices GetWindow function 4417 * returns state information about the specified window 4418 */ 4419 /*ARGSUSED*/ 4420 static int 4421 pcic_get_window(dev_info_t *dip, get_window_t *window) 4422 { 4423 anp_t *anp = ddi_get_driver_private(dip); 4424 pcicdev_t *pcic = anp->an_private; 4425 int socket, win; 4426 pcic_socket_t *sockp; 4427 pcs_memwin_t *winp; 4428 4429 socket = window->window / PCIC_NUMWINSOCK; 4430 win = window->window % PCIC_NUMWINSOCK; 4431 #if defined(PCIC_DEBUG) 4432 if (pcic_debug) { 4433 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4434 socket, win); 4435 } 4436 #endif 4437 4438 if (socket > pcic->pc_numsockets) 4439 return (BAD_WINDOW); 4440 4441 sockp = &pcic->pc_sockets[socket]; 4442 winp = &sockp->pcs_windows[win].mem; 4443 4444 window->socket = socket; 4445 window->size = winp->pcw_len; 4446 window->speed = winp->pcw_speed; 4447 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4448 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4449 4450 if (win >= PCIC_IOWINDOWS) { 4451 window->state = 0; 4452 } else { 4453 window->state = WS_IO; 4454 } 4455 if (winp->pcw_status & PCW_ENABLED) 4456 window->state |= WS_ENABLED; 4457 4458 if (winp->pcw_status & PCS_CARD_16BIT) 4459 window->state |= WS_16BIT; 4460 #if defined(PCIC_DEBUG) 4461 if (pcic_debug) 4462 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4463 window->size, (unsigned)window->speed, 4464 (void *)window->handle, window->state); 4465 #endif 4466 4467 return (SUCCESS); 4468 } 4469 4470 /* 4471 * pcic_ll_reset 4472 * low level reset 4473 * separated out so it can be called when already locked 4474 * 4475 * There are two variables that control the RESET timing: 4476 * pcic_prereset_time - time in mS before asserting RESET 4477 * pcic_reset_time - time in mS to assert RESET 4478 * 4479 */ 4480 int pcic_prereset_time = 1; 4481 int pcic_reset_time = 10; 4482 int pcic_postreset_time = 20; 4483 int pcic_vpp_is_vcc_during_reset = 0; 4484 4485 static int 4486 pcic_ll_reset(pcicdev_t *pcic, int socket) 4487 { 4488 int windowbits, iobits; 4489 uint32_t pwr; 4490 4491 /* save windows that were on */ 4492 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4493 if (pcic_reset_time == 0) 4494 return (windowbits); 4495 /* turn all windows off */ 4496 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4497 4498 #if defined(PCIC_DEBUG) 4499 pcic_err(pcic->dip, 6, 4500 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4501 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4502 pcic_getcb(pcic, CB_CONTROL), 4503 pcic_getcb(pcic, CB_PRESENT_STATE)); 4504 #endif 4505 4506 if (pcic_vpp_is_vcc_during_reset) { 4507 4508 /* 4509 * Set VPP to VCC for the duration of the reset - for aironet 4510 * card. 4511 */ 4512 if (pcic->pc_flags & PCF_CBPWRCTL) { 4513 pwr = pcic_getcb(pcic, CB_CONTROL); 4514 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4515 (void) pcic_getcb(pcic, CB_CONTROL); 4516 } else { 4517 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4518 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4519 pwr | 1); 4520 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4521 } 4522 } 4523 4524 if (pcic_prereset_time > 0) { 4525 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4526 pcic_prereset_time); 4527 pcic_mswait(pcic, socket, pcic_prereset_time); 4528 } 4529 4530 /* turn interrupts off and start a reset */ 4531 pcic_err(pcic->dip, 8, 4532 "pcic_ll_reset turn interrupts off and start a reset\n"); 4533 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4534 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4535 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4536 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4537 4538 switch (pcic->pc_type) { 4539 case PCIC_INTEL_i82092: 4540 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4541 PCIC_82092_INT_DISABLE); 4542 break; 4543 default: 4544 break; 4545 } /* switch */ 4546 4547 pcic->pc_sockets[socket].pcs_state = 0; 4548 4549 if (pcic_reset_time > 0) { 4550 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4551 pcic_reset_time); 4552 pcic_mswait(pcic, socket, pcic_reset_time); 4553 } 4554 4555 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4556 4557 /* take it out of RESET now */ 4558 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4559 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4560 4561 /* 4562 * can't access the card for 20ms, but we really don't 4563 * want to sit around that long. The pcic is still usable. 4564 * memory accesses must wait for RDY to come up. 4565 */ 4566 if (pcic_postreset_time > 0) { 4567 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4568 pcic_postreset_time); 4569 pcic_mswait(pcic, socket, pcic_postreset_time); 4570 } 4571 4572 if (pcic_vpp_is_vcc_during_reset > 1) { 4573 4574 /* 4575 * Return VPP power to whatever it was before. 4576 */ 4577 if (pcic->pc_flags & PCF_CBPWRCTL) { 4578 pcic_putcb(pcic, CB_CONTROL, pwr); 4579 (void) pcic_getcb(pcic, CB_CONTROL); 4580 } else { 4581 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4582 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4583 } 4584 } 4585 4586 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4587 4588 return (windowbits); 4589 } 4590 4591 /* 4592 * pcic_reset_socket() 4593 * SocketServices ResetSocket function 4594 * puts the PC Card in the socket into the RESET state 4595 * and then takes it out after the the cycle time 4596 * The socket is back to initial state when done 4597 */ 4598 static int 4599 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4600 { 4601 anp_t *anp = ddi_get_driver_private(dip); 4602 pcicdev_t *pcic = anp->an_private; 4603 int value; 4604 int i, mint; 4605 pcic_socket_t *sockp; 4606 4607 #if defined(PCIC_DEBUG) 4608 if (pcic_debug >= 8) 4609 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4610 (void *)dip, socket, mode, 4611 mode == RESET_MODE_FULL ? "full" : "partial"); 4612 #endif 4613 4614 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4615 4616 /* Turn off management interupts. */ 4617 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4618 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4619 4620 sockp = &pcic->pc_sockets[socket]; 4621 4622 value = pcic_ll_reset(pcic, socket); 4623 if (mode == RESET_MODE_FULL) { 4624 /* disable and unmap all mapped windows */ 4625 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4626 if (i < PCIC_IOWINDOWS) { 4627 if (sockp->pcs_windows[i].io.pcw_status & 4628 PCW_MAPPED) { 4629 pcs_iowin_t *io; 4630 io = &sockp->pcs_windows[i].io; 4631 io->pcw_status &= ~PCW_ENABLED; 4632 } 4633 } else { 4634 if (sockp->pcs_windows[i].mem.pcw_status & 4635 PCW_MAPPED) { 4636 pcs_memwin_t *mem; 4637 mem = &sockp->pcs_windows[i].mem; 4638 mem->pcw_status &= ~PCW_ENABLED; 4639 } 4640 } 4641 } 4642 } else { 4643 /* turn windows back on */ 4644 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4645 /* wait the rest of the time here */ 4646 pcic_mswait(pcic, socket, 10); 4647 } 4648 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4649 mutex_exit(&pcic->pc_lock); 4650 return (SUCCESS); 4651 } 4652 4653 /* 4654 * pcic_set_interrupt() 4655 * SocketServices SetInterrupt function 4656 */ 4657 static int 4658 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4659 { 4660 anp_t *anp = ddi_get_driver_private(dip); 4661 pcicdev_t *pcic = anp->an_private; 4662 int value = DDI_SUCCESS; 4663 inthandler_t *intr; 4664 4665 #if defined(PCIC_DEBUG) 4666 if (pcic_debug) { 4667 cmn_err(CE_CONT, 4668 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4669 pcic->pc_intr_mode); 4670 cmn_err(CE_CONT, 4671 "\t irq_top=%p handler=%p handler_id=%x\n", 4672 (void *)pcic->irq_top, (void *)handler->handler, 4673 handler->handler_id); 4674 } 4675 #endif 4676 4677 /* 4678 * If we're on a PCI bus, we route all IO IRQs through a single 4679 * PCI interrupt (typically INT A#) so we don't have to do 4680 * much other than add the caller to general interrupt handler 4681 * and set some state. 4682 */ 4683 4684 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4685 if (intr == NULL) 4686 return (NO_RESOURCE); 4687 4688 switch (pcic->pc_intr_mode) { 4689 case PCIC_INTR_MODE_PCI_1: 4690 /* 4691 * We only allow above-lock-level IO IRQ handlers 4692 * in the PCI bus case. 4693 */ 4694 4695 mutex_enter(&pcic->intr_lock); 4696 4697 if (pcic->irq_top == NULL) { 4698 pcic->irq_top = intr; 4699 pcic->irq_current = pcic->irq_top; 4700 } else { 4701 while (pcic->irq_current->next != NULL) 4702 pcic->irq_current = pcic->irq_current->next; 4703 pcic->irq_current->next = intr; 4704 pcic->irq_current = pcic->irq_current->next; 4705 } 4706 4707 pcic->irq_current->intr = 4708 (ddi_intr_handler_t *)handler->handler; 4709 pcic->irq_current->handler_id = handler->handler_id; 4710 pcic->irq_current->arg1 = handler->arg1; 4711 pcic->irq_current->arg2 = handler->arg2; 4712 pcic->irq_current->socket = handler->socket; 4713 4714 mutex_exit(&pcic->intr_lock); 4715 4716 handler->iblk_cookie = &pcic->pc_pri; 4717 handler->idev_cookie = &pcic->pc_dcookie; 4718 break; 4719 4720 default: 4721 intr->intr = (ddi_intr_handler_t *)handler->handler; 4722 intr->handler_id = handler->handler_id; 4723 intr->arg1 = handler->arg1; 4724 intr->arg2 = handler->arg2; 4725 intr->socket = handler->socket; 4726 intr->irq = handler->irq; 4727 4728 /* 4729 * need to revisit this to see if interrupts can be 4730 * shared someday. Note that IRQ is set in the common 4731 * code. 4732 */ 4733 mutex_enter(&pcic->pc_lock); 4734 if (pcic->pc_handlers == NULL) { 4735 pcic->pc_handlers = intr; 4736 intr->next = intr->prev = intr; 4737 } else { 4738 insque(intr, pcic->pc_handlers); 4739 } 4740 mutex_exit(&pcic->pc_lock); 4741 4742 break; 4743 } 4744 4745 /* 4746 * need to fill in cookies in event of multiple high priority 4747 * interrupt handlers on same IRQ 4748 */ 4749 4750 #if defined(PCIC_DEBUG) 4751 if (pcic_debug) { 4752 cmn_err(CE_CONT, 4753 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4754 (void *)pcic->irq_top, value); 4755 } 4756 #endif 4757 4758 if (value == DDI_SUCCESS) { 4759 return (SUCCESS); 4760 } else { 4761 return (BAD_IRQ); 4762 } 4763 } 4764 4765 /* 4766 * pcic_clear_interrupt() 4767 * SocketServices ClearInterrupt function 4768 * 4769 * Interrupts for PCIC are complicated by the fact that we must 4770 * follow several different models for interrupts. 4771 * ISA: there is an interrupt per adapter and per socket and 4772 * they can't be shared. 4773 * PCI: some adapters have one PCI interrupt available while others 4774 * have up to 4. Solaris may or may not allow us to use more 4775 * than 1 so we essentially share them all at this point. 4776 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4777 * This is like ISA but we have to fudge and create an intrspec 4778 * that PCI's parent understands and bypass the PCI nexus. 4779 * multifunction: this requires sharing the interrupts on a per-socket 4780 * basis. 4781 */ 4782 static int 4783 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4784 { 4785 anp_t *anp = ddi_get_driver_private(dip); 4786 pcicdev_t *pcic = anp->an_private; 4787 inthandler_t *intr, *prev, *current; 4788 int i; 4789 4790 /* 4791 * If we're on a PCI bus, we route all IO IRQs through a single 4792 * PCI interrupt (typically INT A#) so we don't have to do 4793 * much other than remove the caller from the general 4794 * interrupt handler callout list. 4795 */ 4796 4797 #if defined(PCIC_DEBUG) 4798 if (pcic_debug) { 4799 cmn_err(CE_CONT, 4800 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4801 pcic->pc_intr_mode); 4802 cmn_err(CE_CONT, 4803 "\t irq_top=%p handler=%p handler_id=%x\n", 4804 (void *)pcic->irq_top, (void *)handler->handler, 4805 handler->handler_id); 4806 } 4807 #endif 4808 4809 switch (pcic->pc_intr_mode) { 4810 case PCIC_INTR_MODE_PCI_1: 4811 4812 mutex_enter(&pcic->intr_lock); 4813 if (pcic->irq_top == NULL) { 4814 mutex_exit(&pcic->intr_lock); 4815 return (BAD_IRQ); 4816 } 4817 4818 intr = NULL; 4819 pcic->irq_current = pcic->irq_top; 4820 4821 while ((pcic->irq_current != NULL) && 4822 (pcic->irq_current->handler_id != 4823 handler->handler_id)) { 4824 intr = pcic->irq_current; 4825 pcic->irq_current = pcic->irq_current->next; 4826 } 4827 4828 if (pcic->irq_current == NULL) { 4829 mutex_exit(&pcic->intr_lock); 4830 return (BAD_IRQ); 4831 } 4832 4833 if (intr != NULL) { 4834 intr->next = pcic->irq_current->next; 4835 } else { 4836 pcic->irq_top = pcic->irq_current->next; 4837 } 4838 4839 current = pcic->irq_current; 4840 pcic->irq_current = pcic->irq_top; 4841 mutex_exit(&pcic->intr_lock); 4842 kmem_free(current, sizeof (inthandler_t)); 4843 4844 break; 4845 4846 default: 4847 4848 mutex_enter(&pcic->pc_lock); 4849 intr = pcic_handlers; 4850 prev = (inthandler_t *)&pcic_handlers; 4851 4852 while (intr != NULL) { 4853 if (intr->handler_id == handler->handler_id) { 4854 i = intr->irq & PCIC_INTR_MASK; 4855 if (--pcic_irq_map[i].count == 0) { 4856 /* multi-handler form */ 4857 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4858 (void) ddi_intr_remove_handler( 4859 pcic->pc_intr_htblp[i]); 4860 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4861 (void) pcmcia_return_intr(pcic->dip, i); 4862 #if defined(PCIC_DEBUG) 4863 if (pcic_debug) { 4864 cmn_err(CE_CONT, 4865 "removing interrupt %d at %s " 4866 "priority\n", i, "high"); 4867 cmn_err(CE_CONT, 4868 "ddi_remove_intr(%p, %x, %p)\n", 4869 (void *)dip, 4870 0, 4871 (void *)intr->iblk_cookie); 4872 } 4873 #endif 4874 } 4875 prev->next = intr->next; 4876 kmem_free(intr, sizeof (inthandler_t)); 4877 intr = prev->next; 4878 } else { 4879 prev = intr; 4880 intr = intr->next; 4881 } /* if (handler_id) */ 4882 } /* while */ 4883 4884 mutex_exit(&pcic->pc_lock); 4885 } 4886 4887 #if defined(PCIC_DEBUG) 4888 if (pcic_debug) { 4889 cmn_err(CE_CONT, 4890 "pcic_clear_interrupt: exit irq_top=%p\n", 4891 (void *)pcic->irq_top); 4892 } 4893 #endif 4894 4895 4896 return (SUCCESS); 4897 } 4898 4899 struct intel_regs { 4900 char *name; 4901 int off; 4902 char *fmt; 4903 } iregs[] = { 4904 {"ident ", 0}, 4905 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4906 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4907 "\7DRD\10OE"}, 4908 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4909 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4910 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4911 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4912 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4913 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4914 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4915 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4916 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4917 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4918 {"io0-slow ", 8}, 4919 {"io0-shi ", 9}, 4920 {"io0-elow ", 0xa}, 4921 {"io0-ehi ", 0xb}, 4922 {"io1-slow ", 0xc}, 4923 {"io1-shi ", 0xd}, 4924 {"io1-elow ", 0xe}, 4925 {"io1-ehi ", 0xf}, 4926 {"mem0-slow ", 0x10}, 4927 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4928 {"mem0-elow ", 0x12}, 4929 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4930 {"card0-low ", 0x14}, 4931 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4932 {"mem1-slow ", 0x18}, 4933 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4934 {"mem1-elow ", 0x1a}, 4935 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4936 {"card1-low ", 0x1c}, 4937 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4938 {"mem2-slow ", 0x20}, 4939 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4940 {"mem2-elow ", 0x22}, 4941 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4942 {"card2-low ", 0x24}, 4943 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4944 {"mem3-slow ", 0x28}, 4945 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4946 {"mem3-elow ", 0x2a}, 4947 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4948 {"card3-low ", 0x2c}, 4949 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4950 4951 {"mem4-slow ", 0x30}, 4952 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4953 {"mem4-elow ", 0x32}, 4954 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4955 {"card4-low ", 0x34}, 4956 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4957 {"mpage0 ", 0x40}, 4958 {"mpage1 ", 0x41}, 4959 {"mpage2 ", 0x42}, 4960 {"mpage3 ", 0x43}, 4961 {"mpage4 ", 0x44}, 4962 {NULL}, 4963 }; 4964 4965 static struct intel_regs cregs[] = { 4966 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 4967 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 4968 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 4969 {"chip-info ", 0x1f, "\20\6DUAL"}, 4970 {"IO-offlow0", 0x36}, 4971 {"IO-offhi0 ", 0x37}, 4972 {"IO-offlow1", 0x38}, 4973 {"IO-offhi1 ", 0x39}, 4974 NULL, 4975 }; 4976 4977 static struct intel_regs cxregs[] = { 4978 {"ext-ctl-1 ", 0x03, 4979 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 4980 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 4981 {"mem0-up ", 0x05}, 4982 {"mem1-up ", 0x06}, 4983 {"mem2-up ", 0x07}, 4984 {"mem3-up ", 0x08}, 4985 {"mem4-up ", 0x09}, 4986 {NULL} 4987 }; 4988 4989 void 4990 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 4991 { 4992 int i, value, j; 4993 char buff[256]; 4994 char *fmt; 4995 4996 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 4997 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 4998 int sval; 4999 if (cregs[i].off == PCIC_MISC_CTL_2) 5000 sval = 0; 5001 else 5002 sval = socket; 5003 value = pcic_getb(pcic, sval, cregs[i].off); 5004 if (i & 1) { 5005 if (cregs[i].fmt) 5006 fmt = "%s\t%s\t%b\n"; 5007 else 5008 fmt = "%s\t%s\t%x\n"; 5009 cmn_err(CE_CONT, fmt, buff, 5010 cregs[i].name, value, cregs[i].fmt); 5011 buff[0] = '\0'; 5012 } else { 5013 if (cregs[i].fmt) 5014 fmt = "\t%s\t%b"; 5015 else 5016 fmt = "\t%s\t%x"; 5017 (void) sprintf(buff, fmt, 5018 cregs[i].name, value, cregs[i].fmt); 5019 for (j = strlen(buff); j < 40; j++) 5020 buff[j] = ' '; 5021 buff[40] = '\0'; 5022 } 5023 } 5024 cmn_err(CE_CONT, "%s\n", buff); 5025 5026 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 5027 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 5028 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 5029 5030 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 5031 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 5032 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 5033 5034 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 5035 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 5036 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 5037 5038 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 5039 5040 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 5041 value = clext_reg_read(pcic, socket, cxregs[i].off); 5042 if (i & 1) { 5043 if (cxregs[i].fmt) 5044 fmt = "%s\t%s\t%b\n"; 5045 else 5046 fmt = "%s\t%s\t%x\n"; 5047 cmn_err(CE_CONT, fmt, buff, 5048 cxregs[i].name, value, cxregs[i].fmt); 5049 buff[0] = '\0'; 5050 } else { 5051 if (cxregs[i].fmt) 5052 fmt = "\t%s\t%b"; 5053 else 5054 fmt = "\t%s\t%x"; 5055 (void) sprintf(buff, fmt, 5056 cxregs[i].name, value, cxregs[i].fmt); 5057 for (j = strlen(buff); j < 40; j++) 5058 buff[j] = ' '; 5059 buff[40] = '\0'; 5060 } 5061 } 5062 } 5063 5064 #if defined(PCIC_DEBUG) 5065 static void 5066 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5067 { 5068 int i, value, j; 5069 char buff[256]; 5070 char *fmt; 5071 5072 #if defined(PCIC_DEBUG) 5073 if (pcic_debug < 2) 5074 return; 5075 #endif 5076 cmn_err(CE_CONT, 5077 "----------- PCIC Registers for socket %d---------\n", 5078 socket); 5079 cmn_err(CE_CONT, 5080 "\tname value name value\n"); 5081 5082 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5083 value = pcic_getb(pcic, socket, iregs[i].off); 5084 if (i & 1) { 5085 if (iregs[i].fmt) 5086 fmt = "%s\t%s\t%b\n"; 5087 else 5088 fmt = "%s\t%s\t%x\n"; 5089 cmn_err(CE_CONT, fmt, buff, 5090 iregs[i].name, value, iregs[i].fmt); 5091 buff[0] = '\0'; 5092 } else { 5093 if (iregs[i].fmt) 5094 fmt = "\t%s\t%b"; 5095 else 5096 fmt = "\t%s\t%x"; 5097 (void) sprintf(buff, fmt, 5098 iregs[i].name, value, iregs[i].fmt); 5099 for (j = strlen(buff); j < 40; j++) 5100 buff[j] = ' '; 5101 buff[40] = '\0'; 5102 } 5103 } 5104 switch (pcic->pc_type) { 5105 case PCIC_CL_PD6710: 5106 case PCIC_CL_PD6722: 5107 case PCIC_CL_PD6729: 5108 case PCIC_CL_PD6832: 5109 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5110 break; 5111 } 5112 cmn_err(CE_CONT, "%s\n", buff); 5113 } 5114 #endif 5115 5116 /* 5117 * pcic_mswait(ms) 5118 * sleep ms milliseconds 5119 * call drv_usecwait once for each ms 5120 */ 5121 static void 5122 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5123 { 5124 if (ms) { 5125 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5126 pcic_mutex_exit(&pcic->pc_lock); 5127 delay(drv_usectohz(ms*1000)); 5128 pcic_mutex_enter(&pcic->pc_lock); 5129 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5130 } 5131 } 5132 5133 /* 5134 * pcic_check_ready(pcic, index, off) 5135 * Wait for card to come ready 5136 * We only wait if the card is NOT in RESET 5137 * and power is on. 5138 */ 5139 static boolean_t 5140 pcic_check_ready(pcicdev_t *pcic, int socket) 5141 { 5142 int ifstate, intstate; 5143 5144 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5145 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5146 5147 if ((intstate & PCIC_RESET) && 5148 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5149 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5150 return (B_TRUE); 5151 5152 #ifdef PCIC_DEBUG 5153 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5154 "ifstate = 0x%x\n", intstate, ifstate); 5155 if (pcic_debug) { 5156 pcic_debug += 4; 5157 xxdmp_all_regs(pcic, socket, -1); 5158 pcic_debug -= 4; 5159 } 5160 #endif 5161 return (B_FALSE); 5162 } 5163 5164 /* 5165 * Cirrus Logic extended register read/write routines 5166 */ 5167 static int 5168 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5169 { 5170 int val; 5171 5172 switch (pcic->pc_io_type) { 5173 case PCIC_IO_TYPE_YENTA: 5174 val = ddi_get8(pcic->handle, 5175 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5176 break; 5177 default: 5178 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5179 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5180 break; 5181 } 5182 5183 return (val); 5184 } 5185 5186 static void 5187 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5188 { 5189 switch (pcic->pc_io_type) { 5190 case PCIC_IO_TYPE_YENTA: 5191 ddi_put8(pcic->handle, 5192 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5193 break; 5194 default: 5195 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5196 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5197 break; 5198 } 5199 } 5200 5201 /* 5202 * Misc PCI functions 5203 */ 5204 static void 5205 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5206 { 5207 unsigned cmd; 5208 5209 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5210 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5211 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5212 (PCI_COMM_IO|PCI_COMM_MAE)) 5213 return; 5214 5215 if (flags & PCIC_ENABLE_IO) 5216 cmd |= PCI_COMM_IO; 5217 5218 if (flags & PCIC_ENABLE_MEM) 5219 cmd |= PCI_COMM_MAE; 5220 5221 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5222 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5223 } 5224 5225 /* 5226 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5227 */ 5228 static int 5229 pcic_find_pci_type(pcicdev_t *pcic) 5230 { 5231 uint32_t vend, device; 5232 5233 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5234 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5235 "vendor-id", -1); 5236 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5237 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5238 "device-id", -1); 5239 5240 device = PCI_ID(vend, device); 5241 pcic->pc_type = device; 5242 pcic->pc_chipname = "PCI:unknown"; 5243 5244 switch (device) { 5245 case PCIC_INTEL_i82092: 5246 pcic->pc_chipname = PCIC_TYPE_i82092; 5247 break; 5248 case PCIC_CL_PD6729: 5249 pcic->pc_chipname = PCIC_TYPE_PD6729; 5250 /* 5251 * Some 6730's incorrectly identify themselves 5252 * as a 6729, so we need to do some more tests 5253 * here to see if the device that's claiming 5254 * to be a 6729 is really a 6730. 5255 */ 5256 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5257 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5258 0) { 5259 pcic->pc_chipname = PCIC_TYPE_PD6730; 5260 pcic->pc_type = PCIC_CL_PD6730; 5261 } 5262 break; 5263 case PCIC_CL_PD6730: 5264 pcic->pc_chipname = PCIC_TYPE_PD6730; 5265 break; 5266 case PCIC_CL_PD6832: 5267 pcic->pc_chipname = PCIC_TYPE_PD6832; 5268 break; 5269 case PCIC_SMC_34C90: 5270 pcic->pc_chipname = PCIC_TYPE_34C90; 5271 break; 5272 case PCIC_TOSHIBA_TOPIC95: 5273 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5274 break; 5275 case PCIC_TOSHIBA_TOPIC100: 5276 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5277 break; 5278 case PCIC_TI_PCI1031: 5279 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5280 break; 5281 case PCIC_TI_PCI1130: 5282 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5283 break; 5284 case PCIC_TI_PCI1131: 5285 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5286 break; 5287 case PCIC_TI_PCI1250: 5288 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5289 break; 5290 case PCIC_TI_PCI1225: 5291 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5292 break; 5293 case PCIC_TI_PCI1410: 5294 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5295 break; 5296 case PCIC_TI_PCI1510: 5297 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5298 break; 5299 case PCIC_TI_PCI1520: 5300 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5301 break; 5302 case PCIC_TI_PCI1221: 5303 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5304 break; 5305 case PCIC_TI_PCI1050: 5306 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5307 break; 5308 case PCIC_ENE_1410: 5309 pcic->pc_chipname = PCIC_TYPE_1410; 5310 break; 5311 case PCIC_O2_OZ6912: 5312 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5313 break; 5314 case PCIC_RICOH_RL5C466: 5315 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5316 break; 5317 case PCIC_TI_PCI1420: 5318 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5319 break; 5320 case PCIC_ENE_1420: 5321 pcic->pc_chipname = PCIC_TYPE_1420; 5322 break; 5323 default: 5324 switch (PCI_ID(vend, (uint32_t)0)) { 5325 case PCIC_TOSHIBA_VENDOR: 5326 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5327 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5328 break; 5329 case PCIC_TI_VENDOR: 5330 pcic->pc_chipname = PCIC_TYPE_TI; 5331 pcic->pc_type = PCIC_TI_VENDOR; 5332 break; 5333 case PCIC_O2MICRO_VENDOR: 5334 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5335 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5336 break; 5337 case PCIC_RICOH_VENDOR: 5338 pcic->pc_chipname = PCIC_TYPE_RICOH; 5339 pcic->pc_type = PCIC_RICOH_VENDOR; 5340 break; 5341 default: 5342 if (!(pcic->pc_flags & PCF_CARDBUS)) 5343 return (DDI_FAILURE); 5344 pcic->pc_chipname = PCIC_TYPE_YENTA; 5345 break; 5346 } 5347 } 5348 return (DDI_SUCCESS); 5349 } 5350 5351 static void 5352 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5353 { 5354 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5355 pcic->cfgaddr + PCIC_82092_PPIRR); 5356 uchar_t val; 5357 5358 if (intr == PCIC_82092_CTL_SMI) { 5359 val = PCIC_82092_SMI_CTL(socket, 5360 PCIC_82092_INT_DISABLE); 5361 ppirr &= ~val; 5362 val = PCIC_82092_SMI_CTL(socket, state); 5363 ppirr |= val; 5364 } else { 5365 val = PCIC_82092_IRQ_CTL(socket, 5366 PCIC_82092_INT_DISABLE); 5367 ppirr &= ~val; 5368 val = PCIC_82092_IRQ_CTL(socket, state); 5369 ppirr |= val; 5370 } 5371 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5372 ppirr); 5373 } 5374 5375 static uint_t 5376 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5377 { 5378 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5379 uint_t rc = DDI_INTR_UNCLAIMED; 5380 5381 _NOTE(ARGUNUSED(arg2)) 5382 5383 mutex_enter(&sockp->pcs_pcic->pc_lock); 5384 if (sockp->pcs_cd_softint_flg) { 5385 uint8_t status; 5386 sockp->pcs_cd_softint_flg = 0; 5387 rc = DDI_INTR_CLAIMED; 5388 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5389 PCIC_INTERFACE_STATUS); 5390 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5391 } 5392 mutex_exit(&sockp->pcs_pcic->pc_lock); 5393 return (rc); 5394 } 5395 5396 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5397 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5398 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5399 5400 #ifdef CARDBUS 5401 static uint32_t pcic_cbps_on = 0; 5402 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5403 CB_PS_XVCARD | CB_PS_YVCARD; 5404 #else 5405 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5406 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5407 CB_PS_CBCARD | 5408 CB_PS_XVCARD | CB_PS_YVCARD; 5409 #endif 5410 static void 5411 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5412 { 5413 boolean_t do_debounce = B_FALSE; 5414 int debounce_time = drv_usectohz(pcic_debounce_time); 5415 uint8_t irq; 5416 timeout_id_t debounce; 5417 5418 /* 5419 * Always reset debounce but may need to check original state later. 5420 */ 5421 debounce = sockp->pcs_debounce_id; 5422 sockp->pcs_debounce_id = 0; 5423 5424 /* 5425 * Check to see whether a card is present or not. There are 5426 * only two states that we are concerned with - the state 5427 * where both CD pins are asserted, which means that the 5428 * card is fully seated, and the state where neither CD 5429 * pin is asserted, which means that the card is not 5430 * present. 5431 * The CD signals are generally very noisy and cause a lot of 5432 * contact bounce as the card is being inserted and 5433 * removed, so we need to do some software debouncing. 5434 */ 5435 5436 #ifdef PCIC_DEBUG 5437 pcic_err(pcic->dip, 6, 5438 "pcic%d handle_cd_change: socket %d card status 0x%x" 5439 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5440 sockp->pcs_socket, status, debounce); 5441 #endif 5442 switch (status & PCIC_ISTAT_CD_MASK) { 5443 case PCIC_CD_PRESENT_OK: 5444 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5445 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5446 uint32_t cbps; 5447 #ifdef PCIC_DEBUG 5448 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5449 #endif 5450 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5451 #ifdef PCIC_DEBUG 5452 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5453 #endif 5454 /* 5455 * Check the CB bits are sane. 5456 */ 5457 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5458 cbps & pcic_cbps_off) { 5459 cmn_err(CE_WARN, 5460 "%s%d: Odd Cardbus Present State 0x%x\n", 5461 ddi_get_name(pcic->dip), 5462 ddi_get_instance(pcic->dip), 5463 cbps); 5464 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5465 debounce = 0; 5466 debounce_time = drv_usectohz(1000000); 5467 } 5468 if (debounce) { 5469 sockp->pcs_flags |= PCS_CARD_PRESENT; 5470 if (pcic_do_insertion) { 5471 5472 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5473 5474 if (cbps & CB_PS_16BITCARD) { 5475 pcic_err(pcic->dip, 8, "16 bit card inserted\n"); 5476 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5477 /* calls pcm_adapter_callback() */ 5478 if (pcic->pc_callback) { 5479 5480 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 5481 pcic->dip, PCM_DEVICETYPE, 5482 "pccard"); 5483 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5484 PCE_CARD_INSERT, 5485 sockp->pcs_socket); 5486 } 5487 } else if (cbps & CB_PS_CBCARD) { 5488 pcic_err(pcic->dip, 8, "32 bit card inserted\n"); 5489 5490 if (pcic->pc_flags & PCF_CARDBUS) { 5491 sockp->pcs_flags |= PCS_CARD_ISCARDBUS; 5492 #ifdef CARDBUS 5493 if (!pcic_load_cardbus(pcic, sockp)) { 5494 pcic_unload_cardbus(pcic, sockp); 5495 } 5496 5497 #else 5498 cmn_err(CE_NOTE, 5499 "32 bit Cardbus not supported in" 5500 " this device driver\n"); 5501 #endif 5502 } else { 5503 /* 5504 * Ignore the card 5505 */ 5506 cmn_err(CE_NOTE, 5507 "32 bit Cardbus not supported on this" 5508 " device\n"); 5509 } 5510 } else { 5511 cmn_err(CE_NOTE, 5512 "Unsupported PCMCIA card inserted\n"); 5513 } 5514 } 5515 } else { 5516 do_debounce = B_TRUE; 5517 } 5518 } else { 5519 /* 5520 * It is possible to come through here if the system 5521 * starts up with cards already inserted. Do nothing 5522 * and don't worry about it. 5523 */ 5524 #ifdef PCIC_DEBUG 5525 pcic_err(pcic->dip, 5, 5526 "pcic%d: Odd card insertion indication on socket %d\n", 5527 ddi_get_instance(pcic->dip), 5528 sockp->pcs_socket); 5529 #endif 5530 } 5531 break; 5532 5533 default: 5534 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5535 /* 5536 * Someone has started to insert a card so delay a while. 5537 */ 5538 do_debounce = B_TRUE; 5539 break; 5540 } 5541 /* 5542 * Otherwise this is basically the same as not present 5543 * so fall through. 5544 */ 5545 5546 /* FALLTHRU */ 5547 case 0: 5548 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5549 if (pcic->pc_flags & PCF_CBPWRCTL) { 5550 pcic_putcb(pcic, CB_CONTROL, 0); 5551 } else { 5552 pcic_putb(pcic, sockp->pcs_socket, PCIC_POWER_CONTROL, 0); 5553 (void) pcic_getb(pcic, sockp->pcs_socket, 5554 PCIC_POWER_CONTROL); 5555 } 5556 #ifdef PCIC_DEBUG 5557 pcic_err(pcic->dip, 8, "Card removed\n"); 5558 #endif 5559 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5560 5561 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5562 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5563 if (pcic_do_removal && pcic->pc_callback) { 5564 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5565 PCE_CARD_REMOVAL, sockp->pcs_socket); 5566 } 5567 } 5568 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5569 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5570 sockp->pcs_flags |= PCS_CARD_CBREM; 5571 } 5572 sockp->pcs_flags |= PCS_CARD_REMOVED; 5573 5574 do_debounce = B_TRUE; 5575 } 5576 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5577 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5578 /* 5579 * Ensure that we do the unloading in the 5580 * debounce handler, that way we're not doing 5581 * nasty things in an interrupt handler. e.g. 5582 * a USB device will wait for data which will 5583 * obviously never come because we've 5584 * unplugged the device, but the wait will 5585 * wait forever because no interrupts can 5586 * come in... 5587 */ 5588 #ifdef CARDBUS 5589 pcic_unload_cardbus(pcic, sockp); 5590 /* pcic_dump_all(pcic); */ 5591 #endif 5592 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5593 } 5594 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5595 } 5596 break; 5597 } /* switch */ 5598 5599 if (do_debounce) { 5600 /* 5601 * Delay doing 5602 * anything for a while so that things can settle 5603 * down a little. Interrupts are already disabled. 5604 * Reset the state and we'll reevaluate the 5605 * whole kit 'n kaboodle when the timeout fires 5606 */ 5607 #ifdef PCIC_DEBUG 5608 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5609 "socket %d.%d\n", 5610 ddi_get_instance(pcic->dip), 5611 sockp->pcs_socket); 5612 #endif 5613 sockp->pcs_debounce_id = pcic_add_debqueue(sockp, debounce_time); 5614 5615 /* 5616 * We bug out here without re-enabling interrupts. They will 5617 * be re-enabled when the debounce timeout swings through 5618 * here. 5619 */ 5620 return; 5621 } 5622 5623 /* 5624 * Turn on Card detect interrupts. Other interrupts will be 5625 * enabled during set_socket calls. 5626 * 5627 * Note that set_socket only changes interrupt settings when there 5628 * is a card present. 5629 */ 5630 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5631 irq |= PCIC_CD_DETECT; 5632 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5633 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK); 5634 5635 /* Out from debouncing state */ 5636 sockp->pcs_flags &= ~PCS_DEBOUNCING; 5637 5638 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5639 } 5640 5641 /* 5642 * pcic_getb() 5643 * get an I/O byte based on the yardware decode method 5644 */ 5645 static uint8_t 5646 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5647 { 5648 int work; 5649 5650 #if defined(PCIC_DEBUG) 5651 if (pcic_debug == 0x7fff) { 5652 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5653 (void *)pcic, socket, reg); 5654 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5655 pcic->pc_io_type, (void *)pcic->handle, 5656 (void *)pcic->ioaddr); 5657 } 5658 #endif 5659 5660 switch (pcic->pc_io_type) { 5661 case PCIC_IO_TYPE_YENTA: 5662 return (ddi_get8(pcic->handle, 5663 pcic->ioaddr + CB_R2_OFFSET + reg)); 5664 default: 5665 work = (socket * PCIC_SOCKET_1) | reg; 5666 ddi_put8(pcic->handle, pcic->ioaddr, work); 5667 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5668 } 5669 } 5670 5671 static void 5672 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5673 { 5674 int work; 5675 5676 #if defined(PCIC_DEBUG) 5677 if (pcic_debug == 0x7fff) { 5678 cmn_err(CE_CONT, 5679 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5680 (void *)pcic, socket, reg, value); 5681 cmn_err(CE_CONT, 5682 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5683 pcic->pc_io_type, (void *)pcic->handle, 5684 (void *)pcic->ioaddr); 5685 } 5686 #endif 5687 5688 5689 switch (pcic->pc_io_type) { 5690 case PCIC_IO_TYPE_YENTA: 5691 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5692 value); 5693 break; 5694 default: 5695 work = (socket * PCIC_SOCKET_1) | reg; 5696 ddi_put8(pcic->handle, pcic->ioaddr, work); 5697 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5698 break; 5699 } 5700 } 5701 5702 /* 5703 * chip identification functions 5704 */ 5705 5706 /* 5707 * chip identification: Cirrus Logic PD6710/6720/6722 5708 */ 5709 static int 5710 pcic_ci_cirrus(pcicdev_t *pcic) 5711 { 5712 int value1, value2; 5713 5714 /* Init the CL id mode */ 5715 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5716 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5717 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5718 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5719 5720 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5721 (value2 & PCIC_CI_ID) == 0) { 5722 /* chip is a Cirrus Logic and not Intel */ 5723 pcic->pc_type = PCIC_CL_PD6710; 5724 if (value1 & PCIC_CI_SLOTS) 5725 pcic->pc_chipname = PCIC_TYPE_PD6720; 5726 else 5727 pcic->pc_chipname = PCIC_TYPE_PD6710; 5728 /* now fine tune things just in case a 6722 */ 5729 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5730 if (value1 == 0) { 5731 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5732 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5733 if (value1 == 0x55) { 5734 pcic->pc_chipname = PCIC_TYPE_PD6722; 5735 pcic->pc_type = PCIC_CL_PD6722; 5736 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5737 } 5738 } 5739 return (1); 5740 } 5741 return (0); 5742 } 5743 5744 /* 5745 * chip identification: Vadem (VG365/465/468/469) 5746 */ 5747 5748 static void 5749 pcic_vadem_enable(pcicdev_t *pcic) 5750 { 5751 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5752 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5753 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5754 } 5755 5756 static int 5757 pcic_ci_vadem(pcicdev_t *pcic) 5758 { 5759 int value; 5760 5761 pcic_vadem_enable(pcic); 5762 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5763 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5764 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5765 (value | PCIC_VADEM_D3) || 5766 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5767 PCIC_VADEM_469) { 5768 int vadem, new; 5769 pcic_vadem_enable(pcic); 5770 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5771 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5772 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5773 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5774 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5775 5776 /* want to lock but leave mouse or other on */ 5777 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5778 switch (value & PCIC_REV_MASK) { 5779 case PCIC_VADEM_365: 5780 pcic->pc_chipname = PCIC_VG_365; 5781 pcic->pc_type = PCIC_VADEM; 5782 break; 5783 case PCIC_VADEM_465: 5784 pcic->pc_chipname = PCIC_VG_465; 5785 pcic->pc_type = PCIC_VADEM; 5786 pcic->pc_flags |= PCF_1SOCKET; 5787 break; 5788 case PCIC_VADEM_468: 5789 pcic->pc_chipname = PCIC_VG_468; 5790 pcic->pc_type = PCIC_VADEM; 5791 break; 5792 case PCIC_VADEM_469: 5793 pcic->pc_chipname = PCIC_VG_469; 5794 pcic->pc_type = PCIC_VADEM_VG469; 5795 break; 5796 } 5797 return (1); 5798 } 5799 return (0); 5800 } 5801 5802 /* 5803 * chip identification: Ricoh 5804 */ 5805 static int 5806 pcic_ci_ricoh(pcicdev_t *pcic) 5807 { 5808 int value; 5809 5810 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5811 switch (value) { 5812 case PCIC_RF_296: 5813 pcic->pc_type = PCIC_RICOH; 5814 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5815 return (1); 5816 case PCIC_RF_396: 5817 pcic->pc_type = PCIC_RICOH; 5818 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5819 return (1); 5820 } 5821 return (0); 5822 } 5823 5824 5825 /* 5826 * set up available address spaces in busra 5827 */ 5828 static void 5829 pcic_init_assigned(dev_info_t *dip) 5830 { 5831 pcm_regs_t *pcic_avail_p; 5832 pci_regspec_t *pci_avail_p, *regs; 5833 int len, entries, rlen; 5834 dev_info_t *pdip; 5835 5836 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5837 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5838 /* 5839 * found "available" property at the cardbus/pcmcia node 5840 * need to translate address space entries from pcmcia 5841 * format to pci format 5842 */ 5843 entries = len / sizeof (pcm_regs_t); 5844 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5845 KM_SLEEP); 5846 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5847 entries) == DDI_SUCCESS) 5848 (void) pci_resource_setup_avail(dip, pci_avail_p, 5849 entries); 5850 kmem_free(pcic_avail_p, len); 5851 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5852 return; 5853 } 5854 5855 /* 5856 * "legacy" platforms will have "available" property in pci node 5857 */ 5858 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5859 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5860 "available", (caddr_t)&pci_avail_p, &len) == 5861 DDI_PROP_SUCCESS) { 5862 /* (void) pci_resource_setup(pdip); */ 5863 kmem_free(pci_avail_p, len); 5864 break; 5865 } 5866 } 5867 5868 if (pdip == NULL) { 5869 int len; 5870 char bus_type[16] = "(unknown)"; 5871 dev_info_t *par; 5872 5873 cmn_err(CE_CONT, 5874 "?pcic_init_assigned: no available property for pcmcia\n"); 5875 5876 /* 5877 * This code is taken from pci_resource_setup() but does 5878 * not attempt to use the "available" property to populate 5879 * the ndi maps that are created. 5880 * The fact that we will actually 5881 * free some resource below (that was allocated by OBP) 5882 * should be enough to be going on with. 5883 */ 5884 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5885 len = sizeof (bus_type); 5886 5887 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5888 PROP_LEN_AND_VAL_BUF, 5889 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5890 "device_type", 5891 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5892 (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 5893 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0)) 5894 break; 5895 } 5896 if (par != NULL && 5897 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5898 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5899 par = NULL; 5900 } else { 5901 #ifdef CARDBUS 5902 cardbus_bus_range_t *bus_range; 5903 int k; 5904 5905 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5906 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5907 if (bus_range->lo != bus_range->hi) 5908 pcic_err(pdip, 9, "allowable bus range is " 5909 "%u->%u\n", bus_range->lo, bus_range->hi); 5910 else { 5911 pcic_err(pdip, 0, 5912 "!No spare PCI bus numbers, range is " 5913 "%u->%u, cardbus isn't usable\n", 5914 bus_range->lo, bus_range->hi); 5915 } 5916 kmem_free(bus_range, k); 5917 } else 5918 pcic_err(pdip, 0, "!No bus-range property seems to " 5919 "have been set up\n"); 5920 #endif 5921 /* 5922 * Have a valid parent with the "available" property 5923 */ 5924 (void) pci_resource_setup(pdip); 5925 } 5926 5927 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5928 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5929 "assigned-addresses", 5930 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5931 ra_return_t ra; 5932 5933 /* 5934 * On the UltraBook IIi the ranges are assigned under 5935 * openboot. If we don't free them here the first I/O 5936 * space that can be used is up above 0x10000 which 5937 * doesn't work for this driver due to restrictions 5938 * on the PCI I/O addresses the controllers can cope with. 5939 * They are never going to be used by anything else 5940 * so free them up to the general pool. AG. 5941 */ 5942 pcic_err(dip, 1, "Free assigned addresses\n"); 5943 5944 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5945 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5946 regs[0].pci_size_low == 0x1000000) { 5947 ra.ra_addr_lo = regs[0].pci_phys_low; 5948 ra.ra_len = regs[0].pci_size_low; 5949 (void) pcmcia_free_mem(dip, &ra); 5950 } 5951 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 5952 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 5953 (regs[1].pci_size_low == 0x8000 || 5954 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 5955 { 5956 ra.ra_addr_lo = regs[1].pci_phys_low; 5957 ra.ra_len = regs[1].pci_size_low; 5958 (void) pcmcia_free_io(dip, &ra); 5959 } 5960 kmem_free((caddr_t)regs, rlen); 5961 } 5962 } 5963 5964 /* 5965 * translate "available" from pcmcia format to pci format 5966 */ 5967 static int 5968 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 5969 pci_regspec_t *pci_p, int entries) 5970 { 5971 int i, range_len, range_entries; 5972 pcic_ranges_t *pcic_range_p; 5973 5974 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 5975 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 5976 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 5977 "no ranges property for pcmcia\n"); 5978 return (DDI_FAILURE); 5979 } 5980 5981 range_entries = range_len / sizeof (pcic_ranges_t); 5982 5983 /* for each "available" entry to be translated */ 5984 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 5985 int j; 5986 pcic_ranges_t *range_p = pcic_range_p; 5987 pci_p->pci_phys_hi = -1u; /* default invalid value */ 5988 5989 /* for each "ranges" entry to be searched */ 5990 for (j = 0; j < range_entries; j++, range_p++) { 5991 uint64_t range_end = range_p->pcic_range_caddrlo + 5992 range_p->pcic_range_size; 5993 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 5994 5995 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 5996 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 5997 (range_end < avail_end)) 5998 continue; 5999 6000 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 6001 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 6002 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 6003 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 6004 pci_p->pci_size_hi = 0; 6005 pci_p->pci_size_low = pcic_p->phys_len; 6006 } 6007 } 6008 kmem_free(pcic_range_p, range_len); 6009 return (DDI_SUCCESS); 6010 } 6011 6012 static int 6013 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 6014 { 6015 #ifdef CARDBUS 6016 if (cardbus_is_cb_minor(*dev)) 6017 return (cardbus_open(dev, flag, otyp, cred)); 6018 #endif 6019 return (EINVAL); 6020 } 6021 6022 static int 6023 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 6024 { 6025 #ifdef CARDBUS 6026 if (cardbus_is_cb_minor(dev)) 6027 return (cardbus_close(dev, flag, otyp, cred)); 6028 #endif 6029 return (EINVAL); 6030 } 6031 6032 static int 6033 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 6034 int *rval) 6035 { 6036 #ifdef CARDBUS 6037 if (cardbus_is_cb_minor(dev)) 6038 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 6039 #endif 6040 return (EINVAL); 6041 } 6042 6043 6044 static boolean_t 6045 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6046 { 6047 uint32_t present_state; 6048 dev_info_t *dip = pcic->dip; 6049 set_socket_t s; 6050 get_socket_t g; 6051 boolean_t retval; 6052 unsigned vccLevel; 6053 6054 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 6055 6056 pcic_mutex_exit(&pcic->pc_lock); 6057 6058 bzero(&s, sizeof (set_socket_t)); 6059 s.socket = sockp->pcs_socket; 6060 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6061 s.IFType = IF_CARDBUS; 6062 s.State = (unsigned)~0; 6063 6064 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6065 if (present_state & PCIC_VCC_3VCARD) 6066 s.VccLevel = PCIC_VCC_3VLEVEL; 6067 else if (present_state & PCIC_VCC_5VCARD) 6068 s.VccLevel = PCIC_VCC_5VLEVEL; 6069 else { 6070 cmn_err(CE_CONT, 6071 "pcic_load_cardbus: unsupported card voltage\n"); 6072 goto failure; 6073 } 6074 vccLevel = s.VccLevel; 6075 s.Vpp1Level = s.Vpp2Level = 0; 6076 6077 if (pcic_set_socket(dip, &s) != SUCCESS) 6078 goto failure; 6079 6080 if (pcic_reset_socket(dip, sockp->pcs_socket, 6081 RESET_MODE_CARD_ONLY) != SUCCESS) 6082 goto failure; 6083 6084 bzero(&g, sizeof (get_socket_t)); 6085 g.socket = sockp->pcs_socket; 6086 if (pcic_get_socket(dip, &g) != SUCCESS) 6087 goto failure; 6088 6089 bzero(&s, sizeof (set_socket_t)); 6090 s.socket = sockp->pcs_socket; 6091 s.SCIntMask = SBM_CD; 6092 s.IREQRouting = g.IRQRouting; 6093 s.IFType = g.IFType; 6094 s.CtlInd = g.CtlInd; 6095 s.State = (unsigned)~0; 6096 s.VccLevel = vccLevel; 6097 s.Vpp1Level = s.Vpp2Level = 0; 6098 6099 retval = pcic_set_socket(dip, &s); 6100 pcmcia_cb_resumed(s.socket); 6101 if (retval != SUCCESS) 6102 goto failure; 6103 6104 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6105 goto exit; 6106 6107 failure: 6108 retval = B_FALSE; 6109 6110 exit: 6111 pcic_mutex_enter(&pcic->pc_lock); 6112 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6113 retval ? "success" : "failure"); 6114 return (retval); 6115 } 6116 6117 static void 6118 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6119 { 6120 dev_info_t *dip = pcic->dip; 6121 set_socket_t s; 6122 6123 pcic_mutex_exit(&pcic->pc_lock); 6124 6125 cardbus_unload_cardbus(dip); 6126 6127 bzero(&s, sizeof (set_socket_t)); 6128 s.socket = sockp->pcs_socket; 6129 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6130 s.IREQRouting = 0; 6131 s.IFType = IF_MEMORY; 6132 s.CtlInd = 0; 6133 s.State = 0; 6134 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6135 6136 (void) pcic_set_socket(dip, &s); 6137 6138 pcic_mutex_enter(&pcic->pc_lock); 6139 } 6140 6141 static uint32_t 6142 pcic_getcb(pcicdev_t *pcic, int reg) 6143 { 6144 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6145 6146 return (ddi_get32(pcic->handle, 6147 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6148 } 6149 6150 static void 6151 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6152 { 6153 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6154 6155 ddi_put32(pcic->handle, 6156 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6157 } 6158 6159 static void 6160 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6161 { 6162 uint8_t value; 6163 uint16_t brdgctl; 6164 6165 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6166 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6167 6168 switch (pcic->pc_type) { 6169 case PCIC_INTEL_i82092: 6170 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6171 PCIC_82092_INT_ENABLE); 6172 break; 6173 case PCIC_O2_OZ6912: 6174 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6175 value |= 0x8; 6176 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6177 break; 6178 case PCIC_CL_PD6832: 6179 case PCIC_TI_PCI1250: 6180 case PCIC_TI_PCI1221: 6181 case PCIC_TI_PCI1225: 6182 case PCIC_TI_PCI1410: 6183 case PCIC_ENE_1410: 6184 case PCIC_TI_PCI1510: 6185 case PCIC_TI_PCI1520: 6186 case PCIC_TI_PCI1420: 6187 case PCIC_ENE_1420: 6188 /* route card functional interrupts to PCI interrupts */ 6189 brdgctl = ddi_get16(pcic->cfg_handle, 6190 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6191 pcic_err(NULL, 1, 6192 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6193 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6194 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6195 ddi_put16(pcic->cfg_handle, 6196 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6197 brdgctl); 6198 /* Flush the write */ 6199 (void) ddi_get16(pcic->cfg_handle, 6200 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6201 break; 6202 default: 6203 break; 6204 } 6205 } 6206 6207 static void 6208 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6209 { 6210 uint8_t value; 6211 uint16_t brdgctl; 6212 6213 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6214 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6215 6216 switch (pcic->pc_type) { 6217 case PCIC_INTEL_i82092: 6218 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6219 PCIC_82092_INT_DISABLE); 6220 break; 6221 case PCIC_O2_OZ6912: 6222 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6223 value &= ~0x8; 6224 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6225 /* Flush the write */ 6226 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6227 break; 6228 case PCIC_CL_PD6832: 6229 case PCIC_TI_PCI1250: 6230 case PCIC_TI_PCI1221: 6231 case PCIC_TI_PCI1225: 6232 case PCIC_TI_PCI1410: 6233 case PCIC_ENE_1410: 6234 case PCIC_TI_PCI1510: 6235 case PCIC_TI_PCI1520: 6236 case PCIC_TI_PCI1420: 6237 case PCIC_ENE_1420: 6238 /* 6239 * This maps I/O interrupts to ExCA which 6240 * have been turned off by the write to 6241 * PCIC_INTERRUPT above. It would appear to 6242 * be the only way to actually turn I/O Ints off 6243 * while retaining CS Ints. 6244 */ 6245 brdgctl = ddi_get16(pcic->cfg_handle, 6246 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6247 pcic_err(NULL, 1, 6248 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6249 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6250 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6251 ddi_put16(pcic->cfg_handle, 6252 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6253 brdgctl); 6254 /* Flush the write */ 6255 (void) ddi_get16(pcic->cfg_handle, 6256 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6257 break; 6258 default: 6259 break; 6260 } 6261 } 6262 6263 static void 6264 pcic_cb_enable_intr(dev_info_t *dip) 6265 { 6266 anp_t *anp = ddi_get_driver_private(dip); 6267 pcicdev_t *pcic = anp->an_private; 6268 6269 mutex_enter(&pcic->pc_lock); 6270 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6271 mutex_exit(&pcic->pc_lock); 6272 } 6273 6274 static void 6275 pcic_cb_disable_intr(dev_info_t *dip) 6276 { 6277 anp_t *anp = ddi_get_driver_private(dip); 6278 pcicdev_t *pcic = anp->an_private; 6279 6280 mutex_enter(&pcic->pc_lock); 6281 pcic_disable_io_intr(pcic, 0); 6282 mutex_exit(&pcic->pc_lock); 6283 } 6284 6285 static int 6286 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6287 { 6288 int nerr = 0; 6289 if (e & PCI_STAT_PERROR) { 6290 nerr++; 6291 cmn_err(CE_CONT, "detected parity error.\n"); 6292 } 6293 if (e & PCI_STAT_S_SYSERR) { 6294 nerr++; 6295 if (bridge_secondary) 6296 cmn_err(CE_CONT, "received system error.\n"); 6297 else 6298 cmn_err(CE_CONT, "signalled system error.\n"); 6299 } 6300 if (e & PCI_STAT_R_MAST_AB) { 6301 nerr++; 6302 cmn_err(CE_CONT, "received master abort.\n"); 6303 } 6304 if (e & PCI_STAT_R_TARG_AB) 6305 cmn_err(CE_CONT, "received target abort.\n"); 6306 if (e & PCI_STAT_S_TARG_AB) 6307 cmn_err(CE_CONT, "signalled target abort\n"); 6308 if (e & PCI_STAT_S_PERROR) { 6309 nerr++; 6310 cmn_err(CE_CONT, "signalled parity error\n"); 6311 } 6312 return (nerr); 6313 } 6314 6315 #if defined(__sparc) 6316 static int 6317 pcic_fault(enum pci_fault_ops op, void *arg) 6318 { 6319 pcicdev_t *pcic = (pcicdev_t *)arg; 6320 ushort_t pci_cfg_stat = 6321 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6322 ushort_t pci_cfg_sec_stat = 6323 pci_config_get16(pcic->cfg_handle, 0x16); 6324 char nm[24]; 6325 int nerr = 0; 6326 6327 cardbus_dump_pci_config(pcic->dip); 6328 6329 switch (op) { 6330 case FAULT_LOG: 6331 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6332 ddi_get_instance(pcic->dip)); 6333 6334 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6335 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6336 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6337 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6338 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6339 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6340 return (nerr); 6341 case FAULT_POKEFINI: 6342 case FAULT_RESET: 6343 pci_config_put16(pcic->cfg_handle, 6344 PCI_CONF_STAT, pci_cfg_stat); 6345 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6346 break; 6347 case FAULT_POKEFLT: 6348 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6349 return (1); 6350 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6351 return (1); 6352 break; 6353 default: 6354 break; 6355 } 6356 return (DDI_SUCCESS); 6357 } 6358 #endif 6359 6360 static void 6361 pcic_do_resume(pcicdev_t *pcic) 6362 { 6363 int i, interrupt; 6364 uint8_t cfg; 6365 6366 6367 #if defined(PCIC_DEBUG) 6368 pcic_err(NULL, 6, "pcic_do_resume(): entered\n"); 6369 #endif 6370 6371 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6372 for (i = 0; i < pcic->pc_numsockets; i++) { 6373 /* Enable interrupts on PCI if needs be */ 6374 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6375 if (pcic->pc_flags & PCF_USE_SMI) 6376 interrupt |= PCIC_INTR_ENABLE; 6377 pcic_putb(pcic, i, PCIC_INTERRUPT, 6378 PCIC_RESET | interrupt); 6379 pcic->pc_sockets[i].pcs_debounce_id = 6380 pcic_add_debqueue(&pcic->pc_sockets[i], 6381 drv_usectohz(pcic_debounce_time)); 6382 } 6383 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6384 if (pcic_do_pcmcia_sr) 6385 (void) pcmcia_wait_insert(pcic->dip); 6386 /* 6387 * The CardBus controller may be in RESET state after the 6388 * system is resumed from sleeping. The RESET bit is in 6389 * the Bridge Control register. This is true for all(TI, 6390 * Toshiba ToPIC95/97, RICOH, and O2Micro) CardBus 6391 * controllers. Need to clear the RESET bit explicitly. 6392 */ 6393 cfg = ddi_get8(pcic->cfg_handle, 6394 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 6395 if (cfg & (1<<6)) { 6396 cfg &= ~(1<<6); 6397 ddi_put8(pcic->cfg_handle, 6398 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 6399 cfg); 6400 cfg = ddi_get8(pcic->cfg_handle, 6401 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 6402 if (cfg & (1<<6)) { 6403 pcic_err(pcic->dip, 1, "Failed to take pcic out of reset"); 6404 } 6405 } 6406 6407 } 6408 6409 static void 6410 pcic_debounce(pcic_socket_t *pcs) 6411 { 6412 uint8_t status, stschng; 6413 6414 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6415 pcs->pcs_flags &= ~PCS_STARTING; 6416 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6417 PCIC_CARD_STATUS_CHANGE); 6418 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6419 PCIC_INTERFACE_STATUS); 6420 #ifdef PCIC_DEBUG 6421 pcic_err(pcs->pcs_pcic->dip, 8, 6422 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6423 "chg 0x%x flg 0x%x\n", 6424 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6425 status, stschng, pcs->pcs_flags); 6426 #endif 6427 6428 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6429 PCIC_CD_DETECT); 6430 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6431 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6432 } 6433 6434 static void 6435 pcic_deb_thread() 6436 { 6437 callb_cpr_t cprinfo; 6438 struct debounce *debp; 6439 clock_t lastt; 6440 6441 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6442 callb_generic_cpr, "pcic debounce thread"); 6443 mutex_enter(&pcic_deb_mtx); 6444 while (pcic_deb_threadid) { 6445 while (pcic_deb_queue) { 6446 #ifdef PCIC_DEBUG 6447 pcic_dump_debqueue("Thread"); 6448 #endif 6449 debp = pcic_deb_queue; 6450 (void) drv_getparm(LBOLT, &lastt); 6451 if (lastt >= debp->expire) { 6452 pcic_deb_queue = debp->next; 6453 mutex_exit(&pcic_deb_mtx); 6454 pcic_debounce(debp->pcs); 6455 mutex_enter(&pcic_deb_mtx); 6456 kmem_free(debp, sizeof (*debp)); 6457 } else { 6458 (void) cv_timedwait(&pcic_deb_cv, 6459 &pcic_deb_mtx, debp->expire); 6460 } 6461 } 6462 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6463 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6464 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6465 } 6466 pcic_deb_threadid = (kthread_t *)1; 6467 cv_signal(&pcic_deb_cv); 6468 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6469 thread_exit(); 6470 } 6471 6472 static void * 6473 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6474 { 6475 clock_t lbolt; 6476 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6477 6478 (void) drv_getparm(LBOLT, &lbolt); 6479 dbp = kmem_alloc(sizeof (struct debounce), KM_SLEEP); 6480 6481 dbp->expire = lbolt + clocks; 6482 dbp->pcs = pcs; 6483 mutex_enter(&pcic_deb_mtx); 6484 while (*dbpp) { 6485 if (dbp->expire > (*dbpp)->expire) 6486 dbpp = &((*dbpp)->next); 6487 else 6488 break; 6489 } 6490 dbp->next = *dbpp; 6491 *dbpp = dbp; 6492 #ifdef PCIC_DEBUG 6493 pcic_dump_debqueue("Add"); 6494 #endif 6495 cv_signal(&pcic_deb_cv); 6496 mutex_exit(&pcic_deb_mtx); 6497 return (dbp); 6498 } 6499 6500 static void 6501 pcic_rm_debqueue(void *id) 6502 { 6503 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6504 6505 dbp = (struct debounce *)id; 6506 mutex_enter(&pcic_deb_mtx); 6507 while (*dbpp) { 6508 if (*dbpp == dbp) { 6509 *dbpp = dbp->next; 6510 kmem_free(dbp, sizeof (*dbp)); 6511 #ifdef PCIC_DEBUG 6512 pcic_dump_debqueue("Remove"); 6513 #endif 6514 cv_signal(&pcic_deb_cv); 6515 mutex_exit(&pcic_deb_mtx); 6516 return; 6517 } 6518 dbpp = &((*dbpp)->next); 6519 } 6520 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6521 mutex_exit(&pcic_deb_mtx); 6522 } 6523 6524 6525 static int pcic_powerdelay = 0; 6526 6527 static int 6528 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6529 { 6530 int ind, value, orig_pwrctl; 6531 6532 /* power setup -- if necessary */ 6533 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6534 6535 #if defined(PCIC_DEBUG) 6536 pcic_err(pcic->dip, 6, 6537 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6538 socket, powerlevel, orig_pwrctl); 6539 #endif 6540 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6541 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6542 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6543 if (powerlevel != orig_pwrctl) { 6544 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6545 int ifs; 6546 /* 6547 * set power to socket 6548 * note that the powerlevel was calculated earlier 6549 */ 6550 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6551 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6552 6553 /* 6554 * this second write to the power control register 6555 * is needed to resolve a problem on 6556 * the IBM ThinkPad 750 6557 * where the first write doesn't latch. 6558 * The second write appears to always work and 6559 * doesn't hurt the operation of other chips 6560 * so we can just use it -- this is good since we can't 6561 * determine what chip the 750 actually uses 6562 * (I suspect an early Ricoh). 6563 */ 6564 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6565 6566 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6567 pcic_mswait(pcic, socket, pcic_powerdelay); 6568 #if defined(PCIC_DEBUG) 6569 pcic_err(pcic->dip, 8, 6570 "\tpowerlevel reg = %x (ifs %x)\n", 6571 value, pcic_getb(pcic, socket, 6572 PCIC_INTERFACE_STATUS)); 6573 pcic_err(pcic->dip, 8, 6574 "CBus regs: PS 0x%x, Control 0x%x\n", 6575 pcic_getcb(pcic, CB_PRESENT_STATE), 6576 pcic_getcb(pcic, CB_CONTROL)); 6577 #endif 6578 /* 6579 * since power was touched, make sure it says it 6580 * is on. This lets it become stable. 6581 */ 6582 for (ind = 0; ind < 20; ind++) { 6583 ifs = pcic_getb(pcic, socket, 6584 PCIC_INTERFACE_STATUS); 6585 if (ifs & PCIC_POWER_ON) 6586 break; 6587 else { 6588 pcic_putb(pcic, socket, 6589 PCIC_POWER_CONTROL, 0); 6590 (void) pcic_getb(pcic, socket, 6591 PCIC_POWER_CONTROL); 6592 pcic_mswait(pcic, socket, 40); 6593 if (ind == 10) { 6594 pcic_putcb(pcic, CB_EVENT_FORCE, 6595 CB_EF_CVTEST); 6596 pcic_mswait(pcic, socket, 100); 6597 } 6598 pcic_putb(pcic, socket, 6599 PCIC_POWER_CONTROL, 6600 powerlevel & ~POWER_OUTPUT_ENABLE); 6601 (void) pcic_getb(pcic, socket, 6602 PCIC_POWER_CONTROL); 6603 pcic_mswait(pcic, socket, 6604 pcic_powerdelay); 6605 pcic_putb(pcic, socket, 6606 PCIC_POWER_CONTROL, powerlevel); 6607 (void) pcic_getb(pcic, socket, 6608 PCIC_POWER_CONTROL); 6609 pcic_mswait(pcic, socket, 6610 pcic_powerdelay); 6611 } 6612 } 6613 6614 if (!(ifs & PCIC_POWER_ON)) { 6615 cmn_err(CE_WARN, 6616 "pcic socket %d: Power didn't get turned" 6617 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6618 "misc1 0x%x igc 0x%x ind %d\n", 6619 socket, ifs, 6620 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6621 orig_pwrctl, 6622 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6623 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6624 ind); 6625 return (BAD_VCC); 6626 } 6627 #if defined(PCIC_DEBUG) 6628 pcic_err(pcic->dip, 8, 6629 "\tind = %d, if status %x pwrc 0x%x " 6630 "misc1 0x%x igc 0x%x\n", 6631 ind, ifs, 6632 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6633 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6634 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6635 #endif 6636 } else { 6637 /* explicitly turned off the power */ 6638 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6639 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6640 } 6641 } 6642 return (SUCCESS); 6643 } 6644 6645 static int pcic_cbdoreset_during_poweron = 1; 6646 static int 6647 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6648 { 6649 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6650 int ind, iobits; 6651 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6652 6653 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6654 6655 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6656 cbctl |= pcic_cbv_levels[ind]; 6657 6658 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6659 cbctl |= (pcic_cbv_levels[ind]<<4); 6660 6661 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6662 6663 #if defined(PCIC_DEBUG) 6664 pcic_err(pcic->dip, 6, 6665 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6666 "cbctl 0x%x->0x%x\n", 6667 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6668 #endif 6669 if (cbctl != orig_cbctl) { 6670 if (pcic_cbdoreset_during_poweron && 6671 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6672 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6673 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits & ~PCIC_RESET); 6674 } 6675 pcic_putcb(pcic, CB_CONTROL, cbctl); 6676 6677 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6678 pcic_mswait(pcic, socket, pcic_powerdelay); 6679 return (SUCCESS); 6680 } 6681 for (ind = 0; ind < 20; ind++) { 6682 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6683 6684 if (cbstev & CB_SE_POWER_CYCLE) { 6685 6686 /* 6687 * delay 400 ms: though the standard defines that the Vcc 6688 * set-up time is 20 ms, some PC-Card bridge requires longer 6689 * duration. 6690 * Note: We should check the status AFTER the delay to give time 6691 * for things to stabilize. 6692 */ 6693 pcic_mswait(pcic, socket, 400); 6694 6695 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6696 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6697 /* break; */ 6698 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6699 } 6700 if (cbctl & CB_PS_BADVCC) { 6701 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6702 break; 6703 } 6704 6705 #if defined(PCIC_DEBUG) 6706 pcic_err(pcic->dip, 8, 6707 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6708 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6709 cbctl, orig_cbctl); 6710 #endif 6711 if (pcic_cbdoreset_during_poweron && 6712 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6713 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6714 } 6715 return (SUCCESS); 6716 } 6717 pcic_mswait(pcic, socket, 40); 6718 } 6719 if (pcic_cbdoreset_during_poweron && 6720 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6721 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6722 } 6723 cmn_err(CE_WARN, 6724 "pcic socket %d: Power didn't get turned on/off!\n" 6725 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6726 "vcc %d vpp1 %d", socket, cbstev, 6727 pcic_getcb(pcic, CB_PRESENT_STATE), 6728 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6729 return (BAD_VCC); 6730 } 6731 return (SUCCESS); 6732 } 6733 6734 static int pcic_do_pprintf = 0; 6735 6736 static void 6737 pcic_dump_debqueue(char *msg) 6738 { 6739 struct debounce *debp = pcic_deb_queue; 6740 clock_t lbolt; 6741 6742 (void) drv_getparm(LBOLT, &lbolt); 6743 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6744 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6745 while (debp) { 6746 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6747 (void *) debp, (int)debp->expire, (void *) debp->next, 6748 debp->pcs->pcs_debounce_id); 6749 debp = debp->next; 6750 } 6751 } 6752 6753 6754 /* PRINTFLIKE3 */ 6755 static void 6756 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6757 { 6758 if (pcic_debug && (level <= pcic_debug)) { 6759 va_list adx; 6760 int instance; 6761 char buf[256]; 6762 const char *name; 6763 #if !defined(PCIC_DEBUG) 6764 int ce; 6765 char qmark = 0; 6766 6767 if (level <= 3) 6768 ce = CE_WARN; 6769 else 6770 ce = CE_CONT; 6771 if (level == 4) 6772 qmark = 1; 6773 #endif 6774 6775 if (dip) { 6776 instance = ddi_get_instance(dip); 6777 /* name = ddi_binding_name(dip); */ 6778 name = ddi_driver_name(dip); 6779 } else { 6780 instance = 0; 6781 name = ""; 6782 } 6783 6784 va_start(adx, fmt); 6785 (void) vsprintf(buf, fmt, adx); 6786 va_end(adx); 6787 6788 #if defined(PCIC_DEBUG) 6789 if (pcic_do_pprintf) { 6790 if (dip) { 6791 if (instance >= 0) 6792 prom_printf("%s(%d),0x%p: %s", name, 6793 instance, (void *)dip, buf); 6794 else 6795 prom_printf("%s,0x%p: %s", 6796 name, (void *)dip, buf); 6797 } else 6798 prom_printf(buf); 6799 } else { 6800 if (dip) { 6801 if (instance >= 0) 6802 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6803 name, instance, (void *) dip, buf); 6804 else 6805 cmn_err(CE_CONT, "%s,0x%p: %s", 6806 name, (void *) dip, buf); 6807 } else 6808 cmn_err(CE_CONT, buf); 6809 } 6810 #else 6811 if (dip) 6812 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6813 instance, buf); 6814 else 6815 cmn_err(ce, qmark ? "?%s" : buf, buf); 6816 #endif 6817 } 6818 } 6819