1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCIC device/interrupt handler 31 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 32 * and Toshiba (and possibly other clones) PCMCIA adapter chip 33 * sets. It implements a subset of Socket Services as defined 34 * in the Solaris PCMCIA design documents 35 */ 36 37 /* 38 * currently defined "properties" 39 * 40 * clock-frequency bus clock frequency 41 * smi system management interrupt override 42 * need-mult-irq need status IRQ for each pair of sockets 43 * disable-audio don't route audio signal to speaker 44 */ 45 46 47 #include <sys/types.h> 48 #include <sys/inttypes.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/user.h> 52 #include <sys/buf.h> 53 #include <sys/file.h> 54 #include <sys/uio.h> 55 #include <sys/conf.h> 56 #include <sys/stat.h> 57 #include <sys/autoconf.h> 58 #include <sys/vtoc.h> 59 #include <sys/dkio.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/sunndi.h> 63 #include <sys/var.h> 64 #include <sys/callb.h> 65 #include <sys/open.h> 66 #include <sys/ddidmareq.h> 67 #include <sys/dma_engine.h> 68 #include <sys/kstat.h> 69 #include <sys/kmem.h> 70 #include <sys/modctl.h> 71 #include <sys/pci.h> 72 #include <sys/pci_impl.h> 73 74 #include <sys/pctypes.h> 75 #include <sys/pcmcia.h> 76 #include <sys/sservice.h> 77 78 #include <sys/note.h> 79 80 #include <sys/pcic_reg.h> 81 #include <sys/pcic_var.h> 82 83 #if defined(__sparc) 84 #include <sys/pci/pci_nexus.h> 85 #endif 86 87 #include <sys/hotplug/hpcsvc.h> 88 #include <sys/syshw.h> 89 #include "cardbus/cardbus.h" 90 91 #define SOFTC_SIZE (sizeof (anp_t)) 92 93 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 94 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 95 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 96 static uint_t pcic_intr(caddr_t, caddr_t); 97 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 98 static int pcic_probe(dev_info_t *); 99 100 static int pcic_open(dev_t *, int, int, cred_t *); 101 static int pcic_close(dev_t, int, int, cred_t *); 102 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 103 104 typedef struct pcm_regs pcm_regs_t; 105 106 static void pcic_init_assigned(dev_info_t *); 107 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 108 pci_regspec_t *, int); 109 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 110 111 /* 112 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 113 * are xlated into DMA ctlops. To make this nexus work on x86, we 114 * need to have the default ddi_dma_mctl ctlops in the bus_ops 115 * structure, just to pass the request to the parent. The correct 116 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 117 */ 118 static 119 struct bus_ops pcmciabus_ops = { 120 BUSO_REV, 121 pcmcia_bus_map, 122 NULL, 123 NULL, 124 NULL, 125 i_ddi_map_fault, 126 ddi_no_dma_map, 127 ddi_no_dma_allochdl, 128 ddi_no_dma_freehdl, 129 ddi_no_dma_bindhdl, 130 ddi_no_dma_unbindhdl, 131 ddi_no_dma_flush, 132 ddi_no_dma_win, 133 ddi_dma_mctl, 134 pcmcia_ctlops, 135 pcmcia_prop_op, 136 NULL, /* (*bus_get_eventcookie)(); */ 137 NULL, /* (*bus_add_eventcall)(); */ 138 NULL, /* (*bus_remove_eventcall)(); */ 139 NULL, /* (*bus_post_event)(); */ 140 NULL, /* (*bus_intr_ctl)(); */ 141 NULL, /* (*bus_config)(); */ 142 NULL, /* (*bus_unconfig)(); */ 143 NULL, /* (*bus_fm_init)(); */ 144 NULL, /* (*bus_fm_fini)(); */ 145 NULL, /* (*bus_enter)() */ 146 NULL, /* (*bus_exit)() */ 147 NULL, /* (*bus_power)() */ 148 pcmcia_intr_ops /* (*bus_intr_op)(); */ 149 }; 150 151 static struct cb_ops pcic_cbops = { 152 pcic_open, 153 pcic_close, 154 nodev, 155 nodev, 156 nodev, 157 nodev, 158 nodev, 159 pcic_ioctl, 160 nodev, 161 nodev, 162 nodev, 163 nochpoll, 164 ddi_prop_op, 165 NULL, 166 #ifdef CARDBUS 167 D_NEW | D_MP | D_HOTPLUG 168 #else 169 D_NEW | D_MP 170 #endif 171 }; 172 173 static struct dev_ops pcic_devops = { 174 DEVO_REV, 175 0, 176 pcic_getinfo, 177 nulldev, 178 pcic_probe, 179 pcic_attach, 180 pcic_detach, 181 nulldev, 182 &pcic_cbops, 183 &pcmciabus_ops, 184 NULL 185 }; 186 187 void *pcic_soft_state_p = NULL; 188 static int pcic_maxinst = -1; 189 static timeout_id_t pcic_delayed_resume_toid; 190 191 int pcic_do_insertion = 1; 192 int pcic_do_removal = 1; 193 194 struct irqmap { 195 int irq; 196 int count; 197 } pcic_irq_map[16]; 198 199 200 int pcic_debug = 0x0; 201 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 202 extern void cardbus_dump_pci_config(dev_info_t *dip); 203 extern void cardbus_dump_socket(dev_info_t *dip); 204 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 205 static void pcic_dump_debqueue(char *msg); 206 207 #if defined(PCIC_DEBUG) 208 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 209 210 #define pcic_mutex_enter(a) \ 211 { \ 212 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 213 mutex_enter(a); \ 214 }; 215 216 #define pcic_mutex_exit(a) \ 217 { \ 218 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 219 mutex_exit(a); \ 220 }; 221 222 #else 223 #define pcic_mutex_enter(a) mutex_enter(a) 224 #define pcic_mutex_exit(a) mutex_exit(a) 225 #endif 226 227 #define PCIC_VCC_3VLEVEL 1 228 #define PCIC_VCC_5VLEVEL 2 229 #define PCIC_VCC_12LEVEL 3 230 231 /* bit patterns to select voltage levels */ 232 int pcic_vpp_levels[13] = { 233 0, 0, 0, 234 1, /* 3.3V */ 235 0, 236 1, /* 5V */ 237 0, 0, 0, 0, 0, 0, 238 2 /* 12V */ 239 }; 240 241 uint8_t pcic_cbv_levels[13] = { 242 0, 0, 0, 243 3, /* 3.3V */ 244 0, 245 2, /* 5V */ 246 0, 0, 0, 0, 0, 0, 247 1 /* 12V */ 248 }; 249 250 struct power_entry pcic_power[4] = { 251 { 252 0, VCC|VPP1|VPP2 253 }, 254 { 255 33, /* 3.3Volt */ 256 VCC|VPP1|VPP2 257 }, 258 { 259 5*10, /* 5Volt */ 260 VCC|VPP1|VPP2 /* currently only know about this */ 261 }, 262 { 263 12*10, /* 12Volt */ 264 VPP1|VPP2 265 } 266 }; 267 268 /* 269 * Base used to allocate ranges of PCI memory on x86 systems 270 * Each instance gets a chunk above the base that is used to map 271 * in the memory and I/O windows for that device. 272 * Pages below the base are also allocated for the EXCA registers, 273 * one per instance. 274 */ 275 #define PCIC_PCI_MEMCHUNK 0x1000000 276 277 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 278 static int pcic_debounce_time = 200000; /* In micro-seconds */ 279 280 struct debounce { 281 pcic_socket_t *pcs; 282 clock_t expire; 283 struct debounce *next; 284 }; 285 286 static syshw_t pcic_syshw = { 287 0, "PC Card Socket 0", SH_CONNECTION, 288 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID|SYSHW_VAL0_VALID, 289 B_FALSE, {2, 0, 0, 0} 290 }; 291 292 static struct debounce *pcic_deb_queue = NULL; 293 static kmutex_t pcic_deb_mtx; 294 static kcondvar_t pcic_deb_cv; 295 static kthread_t *pcic_deb_threadid; 296 297 static inthandler_t *pcic_handlers; 298 299 static void pcic_setup_adapter(pcicdev_t *); 300 static int pcic_change(pcicdev_t *, int); 301 static int pcic_ll_reset(pcicdev_t *, int); 302 static void pcic_mswait(pcicdev_t *, int, int); 303 static boolean_t pcic_check_ready(pcicdev_t *, int); 304 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 305 static void pcic_ready_wait(pcicdev_t *, int); 306 extern int pcmcia_get_intr(dev_info_t *, int); 307 extern int pcmcia_return_intr(dev_info_t *, int); 308 309 static int pcic_callback(dev_info_t *, int (*)(), int); 310 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 311 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 312 static int pcic_get_page(dev_info_t *, get_page_t *); 313 static int pcic_get_socket(dev_info_t *, get_socket_t *); 314 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 315 static int pcic_get_window(dev_info_t *, get_window_t *); 316 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 317 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 318 static int pcic_reset_socket(dev_info_t *, int, int); 319 static int pcic_set_page(dev_info_t *, set_page_t *); 320 static int pcic_set_window(dev_info_t *, set_window_t *); 321 static int pcic_set_socket(dev_info_t *, set_socket_t *); 322 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 323 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 324 static void pcic_pm_detection(void *); 325 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 326 static int clext_reg_read(pcicdev_t *, int, uchar_t); 327 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 328 static int pcic_calc_speed(pcicdev_t *, uint32_t); 329 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 330 static int pcic_find_pci_type(pcicdev_t *); 331 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 332 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 333 static uint_t pcic_cd_softint(caddr_t, caddr_t); 334 static uint8_t pcic_getb(pcicdev_t *, int, int); 335 static void pcic_putb(pcicdev_t *, int, int, int8_t); 336 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 337 static uint_t pcic_softintr(caddr_t, caddr_t); 338 339 static void pcic_debounce(pcic_socket_t *); 340 static void pcic_delayed_resume(void *); 341 static void *pcic_add_debqueue(pcic_socket_t *, int); 342 static void pcic_rm_debqueue(void *); 343 static void pcic_deb_thread(); 344 345 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 346 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 347 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 348 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 349 static void pcic_cb_enable_intr(dev_info_t *); 350 static void pcic_cb_disable_intr(dev_info_t *); 351 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 352 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 353 354 static cb_nexus_cb_t pcic_cbnexus_ops = { 355 pcic_cb_enable_intr, 356 pcic_cb_disable_intr 357 }; 358 359 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 360 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 361 362 static void pcic_syshw_cardstate(syshw_t *, void *); 363 364 #if defined(__sparc) 365 static int pcic_fault(enum pci_fault_ops op, void *arg); 366 #endif 367 368 /* 369 * Default to support for Voyager IIi if sparc is defined. 370 * Appart from the PCI base addresses this only effect the TI1250. 371 */ 372 #if defined(sparc) 373 #define VOYAGER 374 #endif 375 376 377 /* 378 * pcmcia_attach() uses 0 and 128 upwards for the initpcmcia and devctl 379 * interfaces so we use 254. 380 */ 381 #define SYSHW_MINOR 254 382 383 /* 384 * Forward declarations for syshw interface (See end of file). 385 */ 386 static void syshw_attach(pcicdev_t *); 387 static void syshw_detach(pcicdev_t *); 388 static void syshw_resume(pcicdev_t *); 389 390 #ifdef VOYAGER 391 static uint_t syshw_intr(caddr_t); 392 static uint_t syshw_intr_hi(pcicdev_t *); 393 #endif 394 395 static int syshw_open(dev_t *, int, int, cred_t *); 396 static int syshw_close(dev_t, int, int, cred_t *); 397 static int syshw_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 398 static uint32_t syshw_add2map(syshw_t *, void (*)(syshw_t *, void *), void *); 399 static void syshw_send_signal(int); 400 401 /* 402 * pcmcia interface operations structure 403 * this is the private interface that is exported to the nexus 404 */ 405 pcmcia_if_t pcic_if_ops = { 406 PCIF_MAGIC, 407 PCIF_VERSION, 408 pcic_callback, 409 pcic_get_adapter, 410 pcic_get_page, 411 pcic_get_socket, 412 pcic_get_status, 413 pcic_get_window, 414 pcic_inquire_adapter, 415 pcic_inquire_socket, 416 pcic_inquire_window, 417 pcic_reset_socket, 418 pcic_set_page, 419 pcic_set_window, 420 pcic_set_socket, 421 pcic_set_interrupt, 422 pcic_clear_interrupt, 423 NULL, 424 }; 425 426 /* 427 * chip type identification routines 428 * this list of functions is searched until one of them succeeds 429 * or all fail. i82365SL is assumed if failed. 430 */ 431 static int pcic_ci_cirrus(pcicdev_t *); 432 static int pcic_ci_vadem(pcicdev_t *); 433 static int pcic_ci_ricoh(pcicdev_t *); 434 435 int (*pcic_ci_funcs[])(pcicdev_t *) = { 436 pcic_ci_cirrus, 437 pcic_ci_vadem, 438 pcic_ci_ricoh, 439 NULL 440 }; 441 442 static struct modldrv modldrv = { 443 &mod_driverops, /* Type of module. This one is a driver */ 444 "PCIC PCMCIA adapter driver %I%", /* Name of the module. */ 445 &pcic_devops, /* driver ops */ 446 }; 447 448 static struct modlinkage modlinkage = { 449 MODREV_1, (void *)&modldrv, NULL 450 }; 451 452 int 453 _init() 454 { 455 int stat; 456 457 /* Allocate soft state */ 458 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 459 SOFTC_SIZE, 2)) != DDI_SUCCESS) 460 return (stat); 461 462 if ((stat = mod_install(&modlinkage)) != 0) 463 ddi_soft_state_fini(&pcic_soft_state_p); 464 465 return (stat); 466 } 467 468 int 469 _fini() 470 { 471 int stat = 0; 472 473 if ((stat = mod_remove(&modlinkage)) != 0) 474 return (stat); 475 476 if (pcic_deb_threadid) { 477 mutex_enter(&pcic_deb_mtx); 478 pcic_deb_threadid = 0; 479 while (!pcic_deb_threadid) 480 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 481 pcic_deb_threadid = 0; 482 mutex_exit(&pcic_deb_mtx); 483 484 mutex_destroy(&pcic_deb_mtx); 485 cv_destroy(&pcic_deb_cv); 486 } 487 488 ddi_soft_state_fini(&pcic_soft_state_p); 489 490 return (stat); 491 } 492 493 int 494 _info(struct modinfo *modinfop) 495 { 496 return (mod_info(&modlinkage, modinfop)); 497 } 498 499 /* 500 * pcic_getinfo() 501 * provide instance/device information about driver 502 */ 503 /*ARGSUSED*/ 504 static int 505 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 506 { 507 anp_t *anp; 508 int error = DDI_SUCCESS; 509 minor_t minor; 510 511 switch (cmd) { 512 case DDI_INFO_DEVT2DEVINFO: 513 minor = getminor((dev_t)arg); 514 if (minor == SYSHW_MINOR) 515 minor = 0; 516 else 517 minor &= 0x7f; 518 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 519 *result = NULL; 520 else 521 *result = anp->an_dip; 522 break; 523 case DDI_INFO_DEVT2INSTANCE: 524 minor = getminor((dev_t)arg); 525 if (minor == SYSHW_MINOR) 526 minor = 0; 527 else 528 minor &= 0x7f; 529 *result = (void *)((long)minor); 530 break; 531 default: 532 error = DDI_FAILURE; 533 break; 534 } 535 return (error); 536 } 537 538 static int 539 pcic_probe(dev_info_t *dip) 540 { 541 int value; 542 ddi_device_acc_attr_t attr; 543 ddi_acc_handle_t handle; 544 uchar_t *index, *data; 545 546 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 547 return (DDI_PROBE_DONTCARE); 548 549 /* 550 * find a PCIC device (any vendor) 551 * while there can be up to 4 such devices in 552 * a system, we currently only look for 1 553 * per probe. There will be up to 2 chips per 554 * instance since they share I/O space 555 */ 556 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 557 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 558 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 559 560 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 561 (caddr_t *)&index, 562 PCIC_ISA_CONTROL_REG_OFFSET, 563 PCIC_ISA_CONTROL_REG_LENGTH, 564 &attr, &handle) != DDI_SUCCESS) 565 return (DDI_PROBE_FAILURE); 566 567 data = index + 1; 568 569 #if defined(PCIC_DEBUG) 570 if (pcic_debug) 571 cmn_err(CE_CONT, "pcic_probe: entered\n"); 572 if (pcic_debug) 573 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 574 #endif 575 ddi_put8(handle, index, PCIC_CHIP_REVISION); 576 ddi_put8(handle, data, 0); 577 value = ddi_get8(handle, data); 578 #if defined(PCIC_DEBUG) 579 if (pcic_debug) 580 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 581 #endif 582 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 583 (value & 0x30) == 0) { 584 /* 585 * we probably have a PCIC chip in the system 586 * do a little more checking. If we find one, 587 * reset everything in case of softboot 588 */ 589 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 590 ddi_put8(handle, data, 0); 591 value = ddi_get8(handle, data); 592 #if defined(PCIC_DEBUG) 593 if (pcic_debug) 594 cmn_err(CE_CONT, "\tzero test = %x\n", value); 595 #endif 596 /* should read back as zero */ 597 if (value == 0) { 598 /* 599 * we do have one and it is off the bus 600 */ 601 #if defined(PCIC_DEBUG) 602 if (pcic_debug) 603 cmn_err(CE_CONT, "pcic_probe: success\n"); 604 #endif 605 ddi_regs_map_free(&handle); 606 return (DDI_PROBE_SUCCESS); 607 } 608 } 609 #if defined(PCIC_DEBUG) 610 if (pcic_debug) 611 cmn_err(CE_CONT, "pcic_probe: failed\n"); 612 #endif 613 ddi_regs_map_free(&handle); 614 return (DDI_PROBE_FAILURE); 615 } 616 617 /* 618 * These are just defaults they can also be changed via a property in the 619 * conf file. 620 */ 621 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 622 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 623 static int pcic_do_pcmcia_sr = 0; 624 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 625 626 /* 627 * enable insertion/removal interrupt for 32bit cards 628 */ 629 static int 630 cardbus_enable_cd_intr(dev_info_t *dip) 631 { 632 ddi_acc_handle_t iohandle; 633 caddr_t ioaddr; 634 ddi_device_acc_attr_t attr; 635 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 636 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 637 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 638 (void) ddi_regs_map_setup(dip, 1, 639 (caddr_t *)&ioaddr, 640 0, 641 4096, 642 &attr, &iohandle); 643 644 /* CSC Interrupt: Card detect interrupt on */ 645 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 646 ddi_get32(iohandle, 647 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 648 649 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 650 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 651 652 ddi_regs_map_free(&iohandle); 653 return (1); 654 } 655 656 /* 657 * pcic_attach() 658 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 659 * to the system. This is a child of "sysbus" since that is where 660 * the hardware lives, but it provides services to the "pcmcia" 661 * nexus driver. It gives a pointer back via its private data 662 * structure which contains both the dip and socket services entry 663 * points 664 */ 665 static int 666 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 667 { 668 anp_t *pcic_nexus; 669 pcicdev_t *pcic; 670 int irqlevel, value; 671 int pci_cfrn, pci_ctrn; 672 int i, j, smi, actual; 673 char *typename; 674 char bus_type[16] = "(unknown)"; 675 int len = sizeof (bus_type); 676 ddi_device_acc_attr_t attr; 677 anp_t *anp = ddi_get_driver_private(dip); 678 uint_t pri; 679 syshw_t *shwp; 680 681 #if defined(PCIC_DEBUG) 682 if (pcic_debug) { 683 cmn_err(CE_CONT, "pcic_attach: entered\n"); 684 } 685 #endif 686 switch (cmd) { 687 case DDI_ATTACH: 688 break; 689 case DDI_RESUME: 690 pcic = anp->an_private; 691 /* 692 * for now, this is a simulated resume. 693 * a real one may need different things. 694 */ 695 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 696 mutex_enter(&pcic->pc_lock); 697 /* should probe for new sockets showing up */ 698 pcic_setup_adapter(pcic); 699 syshw_resume(pcic); 700 pcic->pc_flags &= ~PCF_SUSPENDED; 701 mutex_exit(&pcic->pc_lock); 702 (void) pcmcia_begin_resume(dip); 703 /* 704 * this will do the CARD_INSERTION 705 * due to needing time for threads to 706 * run, it must be delayed for a short amount 707 * of time. pcmcia_wait_insert checks for all 708 * children to be removed and then triggers insert. 709 */ 710 /* 711 * The reason for having a single timeout here 712 * rather than seperate timeout()s for each instance 713 * is due to the limited number (2) of callout threads 714 * available in Solaris 2.6. A single 1250A ends up 715 * as two instances of the interface with one slot each. 716 * The pcic_delayed_resume() function ends by calling 717 * pcmcia_wait_insert() which at one point does a 718 * delay(). delay() is implemented with a timeout() 719 * call so you end up with both the callout() 720 * threads waiting to be woken up by another callout(). 721 * This situation locks up the machine hence the 722 * convolution here to only use one timeout. 723 */ 724 if (!pcic_delayed_resume_toid) 725 pcic_delayed_resume_toid = 726 timeout(pcic_delayed_resume, (caddr_t)0, 727 drv_usectohz(pcic_wait_insert_time)); 728 729 /* 730 * for complete implementation need END_RESUME (later) 731 */ 732 return (DDI_SUCCESS); 733 734 } 735 return (DDI_SUCCESS); 736 default: 737 return (DDI_FAILURE); 738 } 739 740 /* 741 * Allocate soft state associated with this instance. 742 */ 743 if (ddi_soft_state_zalloc(pcic_soft_state_p, 744 ddi_get_instance(dip)) != DDI_SUCCESS) { 745 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 746 ddi_get_instance(dip)); 747 return (DDI_FAILURE); 748 } 749 750 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 751 ddi_get_instance(dip)); 752 753 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 754 755 pcic->dip = dip; 756 pcic_nexus->an_dip = dip; 757 pcic_nexus->an_if = &pcic_if_ops; 758 pcic_nexus->an_private = pcic; 759 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 760 pcic->pc_power = pcic_power; 761 762 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 763 "pci-control-reg-number", pci_control_reg_num); 764 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 765 "pci-config-reg-number", pci_config_reg_num); 766 767 ddi_set_driver_private(dip, pcic_nexus); 768 769 /* 770 * pcic->pc_irq is really the IPL level we want to run at 771 * set the default values here and override from intr spec 772 */ 773 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 774 "interrupt-priorities", -1); 775 776 if (pcic->pc_irq == -1) { 777 int actual; 778 uint_t pri; 779 ddi_intr_handle_t hdl; 780 781 /* see if intrspec tells us different */ 782 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 783 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 784 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 785 pcic->pc_irq = pri; 786 else 787 pcic->pc_irq = LOCK_LEVEL + 1; 788 (void) ddi_intr_free(hdl); 789 } 790 } 791 pcic_nexus->an_ipl = pcic->pc_irq; 792 793 /* 794 * Check our parent bus type. We do different things based on which 795 * bus we're on. 796 */ 797 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 798 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 799 "device_type", (caddr_t)&bus_type[0], &len) != 800 DDI_PROP_SUCCESS) { 801 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 802 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 803 "bus-type", (caddr_t)&bus_type[0], &len) != 804 DDI_PROP_SUCCESS) { 805 806 cmn_err(CE_CONT, 807 "pcic%d: can't find parent bus type\n", 808 ddi_get_instance(dip)); 809 810 kmem_free(pcic, sizeof (pcicdev_t)); 811 return (DDI_FAILURE); 812 } 813 } /* ddi_prop_op("device_type") */ 814 815 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0) { 816 pcic->pc_flags = PCF_PCIBUS; 817 } else { 818 #if defined(__sparc) 819 cmn_err(CE_CONT, "pcic%d: unsupported parent bus type: [%s]\n", 820 ddi_get_instance(dip), bus_type); 821 822 kmem_free(pcic, sizeof (pcicdev_t)); 823 return (DDI_FAILURE); 824 #else 825 pcic->pc_flags = 0; 826 #endif 827 } 828 829 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 830 DDI_PROP_CANSLEEP, 831 "clock-frequency", 0)) == 0) { 832 if (pcic->pc_flags & PCF_PCIBUS) 833 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 834 else 835 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 836 } else { 837 /* 838 * OBP can declare the speed in Hz... 839 */ 840 if (pcic->bus_speed > 1000000) 841 pcic->bus_speed /= 1000000; 842 } /* ddi_prop_op("clock-frequency") */ 843 844 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 845 846 #ifdef PCIC_DEBUG 847 if (pcic_debug) { 848 cmn_err(CE_CONT, 849 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 850 ddi_get_instance(dip), 851 bus_type, pcic->bus_speed); 852 } 853 #endif 854 855 /* 856 * The reg properties on a PCI node are different than those 857 * on a non-PCI node. Handle that difference here. 858 * If it turns out to be a CardBus chip, we have even more 859 * differences. 860 */ 861 if (pcic->pc_flags & PCF_PCIBUS) { 862 int class_code; 863 #if defined(__i386) || defined(__amd64) 864 pcic->pc_base = 0x1000000; 865 pcic->pc_bound = (uint32_t)~0; 866 pcic->pc_iobase = 0x1000; 867 pcic->pc_iobound = 0xefff; 868 #elif defined(__sparc) 869 pcic->pc_base = 0x0; 870 pcic->pc_bound = (uint32_t)~0; 871 pcic->pc_iobase = 0x00000; 872 pcic->pc_iobound = 0xffff; 873 #endif 874 875 /* usually need to get at config space so map first */ 876 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 877 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 878 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 879 880 if (ddi_regs_map_setup(dip, pci_cfrn, 881 (caddr_t *)&pcic->cfgaddr, 882 PCIC_PCI_CONFIG_REG_OFFSET, 883 PCIC_PCI_CONFIG_REG_LENGTH, 884 &attr, 885 &pcic->cfg_handle) != 886 DDI_SUCCESS) { 887 cmn_err(CE_CONT, 888 "pcic%d: unable to map config space" 889 "regs\n", 890 ddi_get_instance(dip)); 891 892 kmem_free(pcic, sizeof (pcicdev_t)); 893 return (DDI_FAILURE); 894 } /* ddi_regs_map_setup */ 895 896 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 897 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 898 "class-code", -1); 899 #ifdef PCIC_DEBUG 900 if (pcic_debug) { 901 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 902 class_code); 903 } 904 #endif 905 906 switch (class_code) { 907 case PCIC_PCI_CARDBUS: 908 pcic->pc_flags |= PCF_CARDBUS; 909 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 910 /* 911 * Get access to the adapter registers on the 912 * PCI bus. A 4K memory page 913 */ 914 #if defined(PCIC_DEBUG) 915 pcic_err(dip, 8, "Is Cardbus device\n"); 916 if (pcic_debug) { 917 int nr; 918 long rs; 919 (void) ddi_dev_nregs(dip, &nr); 920 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 921 "cfghndl 0x%p nregs %d", 922 (void *)pcic->cfgaddr, 923 (void *)pcic->cfg_handle, nr); 924 925 (void) ddi_dev_regsize(dip, 926 PCIC_PCI_CONTROL_REG_NUM, &rs); 927 928 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 929 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 930 } 931 #endif 932 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 933 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 934 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 935 936 if (ddi_regs_map_setup(dip, pci_ctrn, 937 (caddr_t *)&pcic->ioaddr, 938 PCIC_PCI_CONTROL_REG_OFFSET, 939 PCIC_CB_CONTROL_REG_LENGTH, 940 &attr, &pcic->handle) != 941 DDI_SUCCESS) { 942 cmn_err(CE_CONT, 943 "pcic%d: unable to map PCI regs\n", 944 ddi_get_instance(dip)); 945 ddi_regs_map_free(&pcic->cfg_handle); 946 kmem_free(pcic, sizeof (pcicdev_t)); 947 return (DDI_FAILURE); 948 } /* ddi_regs_map_setup */ 949 950 /* 951 * Find out the chip type - If we're on a PCI bus, 952 * the adapter has that information in the PCI 953 * config space. 954 * Note that we call pcic_find_pci_type here since 955 * it needs a valid mapped pcic->handle to 956 * access some of the adapter registers in 957 * some cases. 958 */ 959 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 960 ddi_regs_map_free(&pcic->handle); 961 ddi_regs_map_free(&pcic->cfg_handle); 962 kmem_free(pcic, sizeof (pcicdev_t)); 963 cmn_err(CE_WARN, "pcic: %s: unsupported " 964 "bridge\n", 965 ddi_get_name_addr(dip)); 966 return (DDI_FAILURE); 967 } 968 break; 969 970 default: 971 case PCIC_PCI_PCMCIA: 972 /* 973 * Get access to the adapter IO registers on the 974 * PCI bus config space. 975 */ 976 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 977 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 978 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 979 980 /* 981 * We need a default mapping to the adapter's IO 982 * control register space. For most adapters 983 * that are of class PCIC_PCI_PCMCIA (or of 984 * a default class) the control registers 985 * will be using the 82365-type control/data 986 * format. 987 */ 988 if (ddi_regs_map_setup(dip, pci_ctrn, 989 (caddr_t *)&pcic->ioaddr, 990 PCIC_PCI_CONTROL_REG_OFFSET, 991 PCIC_PCI_CONTROL_REG_LENGTH, 992 &attr, 993 &pcic->handle) != DDI_SUCCESS) { 994 cmn_err(CE_CONT, 995 "pcic%d: unable to map PCI regs\n", 996 ddi_get_instance(dip)); 997 ddi_regs_map_free(&pcic->cfg_handle); 998 kmem_free(pcic, sizeof (pcicdev_t)); 999 return (DDI_FAILURE); 1000 } /* ddi_regs_map_setup */ 1001 1002 /* 1003 * Find out the chip type - If we're on a PCI bus, 1004 * the adapter has that information in the PCI 1005 * config space. 1006 * Note that we call pcic_find_pci_type here since 1007 * it needs a valid mapped pcic->handle to 1008 * access some of the adapter registers in 1009 * some cases. 1010 */ 1011 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 1012 ddi_regs_map_free(&pcic->handle); 1013 ddi_regs_map_free(&pcic->cfg_handle); 1014 kmem_free(pcic, sizeof (pcicdev_t)); 1015 cmn_err(CE_WARN, "pcic: %s: unsupported " 1016 "bridge\n", 1017 ddi_get_name_addr(dip)); 1018 return (DDI_FAILURE); 1019 } 1020 1021 /* 1022 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 1023 * for extended registers even though they are 1024 * not CardBus adapters. For those adapters, 1025 * re-map pcic->handle to be large enough to 1026 * encompass the Yenta registers. 1027 */ 1028 switch (pcic->pc_type) { 1029 case PCIC_TI_PCI1031: 1030 ddi_regs_map_free(&pcic->handle); 1031 1032 if (ddi_regs_map_setup(dip, 1033 PCIC_PCI_CONTROL_REG_NUM, 1034 (caddr_t *)&pcic->ioaddr, 1035 PCIC_PCI_CONTROL_REG_OFFSET, 1036 PCIC_CB_CONTROL_REG_LENGTH, 1037 &attr, 1038 &pcic->handle) != DDI_SUCCESS) { 1039 cmn_err(CE_CONT, 1040 "pcic%d: unable to map " 1041 "PCI regs\n", 1042 ddi_get_instance(dip)); 1043 ddi_regs_map_free(&pcic->cfg_handle); 1044 kmem_free(pcic, sizeof (pcicdev_t)); 1045 return (DDI_FAILURE); 1046 } /* ddi_regs_map_setup */ 1047 break; 1048 default: 1049 break; 1050 } /* switch (pcic->pc_type) */ 1051 break; 1052 } /* switch (class_code) */ 1053 } else { 1054 /* 1055 * We're not on a PCI bus, so assume an ISA bus type 1056 * register property. Get access to the adapter IO 1057 * registers on a non-PCI bus. 1058 */ 1059 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1060 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 1061 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1062 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 1063 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 1064 1065 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 1066 (caddr_t *)&pcic->ioaddr, 1067 PCIC_ISA_CONTROL_REG_OFFSET, 1068 PCIC_ISA_CONTROL_REG_LENGTH, 1069 &attr, 1070 &pcic->handle) != DDI_SUCCESS) { 1071 cmn_err(CE_CONT, 1072 "pcic%d: unable to map ISA registers\n", 1073 ddi_get_instance(dip)); 1074 1075 kmem_free(pcic, sizeof (pcicdev_t)); 1076 return (DDI_FAILURE); 1077 } /* ddi_regs_map_setup */ 1078 1079 /* ISA bus is limited to 24-bits, but not first 640K */ 1080 pcic->pc_base = 0xd0000; 1081 pcic->pc_bound = (uint32_t)~0; 1082 pcic->pc_iobase = 0x1000; 1083 pcic->pc_iobound = 0xefff; 1084 } /* !PCF_PCIBUS */ 1085 1086 #ifdef PCIC_DEBUG 1087 if (pcic_debug) { 1088 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1089 pcic->pc_flags, pcic->pc_type); 1090 } 1091 #endif 1092 1093 /* 1094 * Setup various adapter registers for the PCI case. For the 1095 * non-PCI case, find out the chip type. 1096 */ 1097 if (pcic->pc_flags & PCF_PCIBUS) { 1098 int iline; 1099 #if defined(__sparc) 1100 iline = 0; 1101 #else 1102 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1103 #endif 1104 1105 /* set flags and socket counts based on chip type */ 1106 switch (pcic->pc_type) { 1107 uint32_t cfg; 1108 case PCIC_INTEL_i82092: 1109 cfg = ddi_get8(pcic->cfg_handle, 1110 pcic->cfgaddr + PCIC_82092_PCICON); 1111 /* we can only support 4 Socket version */ 1112 if (cfg & PCIC_82092_4_SOCKETS) { 1113 pcic->pc_numsockets = 4; 1114 pcic->pc_type = PCIC_INTEL_i82092; 1115 if (iline != 0xFF) 1116 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1117 else 1118 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1119 } else { 1120 cmn_err(CE_CONT, 1121 "pcic%d: Intel 82092 adapter " 1122 "in unsupported configuration: 0x%x", 1123 ddi_get_instance(pcic->dip), cfg); 1124 pcic->pc_numsockets = 0; 1125 } /* PCIC_82092_4_SOCKETS */ 1126 break; 1127 case PCIC_CL_PD6730: 1128 case PCIC_CL_PD6729: 1129 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1130 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1131 DDI_PROP_CANSLEEP, 1132 "interrupts", 0); 1133 /* if not interrupt pin then must use ISA style IRQs */ 1134 if (cfg == 0 || iline == 0xFF) 1135 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1136 else { 1137 /* 1138 * we have the option to use PCI interrupts. 1139 * this might not be optimal but in some cases 1140 * is the only thing possible (sparc case). 1141 * we now deterine what is possible. 1142 */ 1143 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1144 } 1145 pcic->pc_numsockets = 2; 1146 pcic->pc_flags |= PCF_IO_REMAP; 1147 break; 1148 case PCIC_TI_PCI1031: 1149 /* this chip doesn't do CardBus but looks like one */ 1150 pcic->pc_flags &= ~PCF_CARDBUS; 1151 /* FALLTHROUGH */ 1152 default: 1153 pcic->pc_flags |= PCF_IO_REMAP; 1154 /* FALLTHROUGH */ 1155 /* indicate feature even if not supported */ 1156 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1157 /* Not sure if these apply to all these chips */ 1158 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1159 pcic->pc_flags |= pcic_use_cbpwrctl; 1160 1161 pcic->pc_numsockets = 1; /* one per function */ 1162 if (iline != 0xFF) { 1163 uint8_t cfg; 1164 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1165 1166 cfg = ddi_get8(pcic->cfg_handle, 1167 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1168 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1169 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1170 PCIC_BRIDGE_CTL_REG), cfg); 1171 } 1172 else 1173 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1174 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1175 break; 1176 } 1177 } else { 1178 /* 1179 * We're not on a PCI bus so do some more 1180 * checking for adapter type here. 1181 * For the non-PCI bus case: 1182 * It could be any one of a number of different chips 1183 * If we can't determine anything else, it is assumed 1184 * to be an Intel 82365SL. The Cirrus Logic PD6710 1185 * has an extension register that provides unique 1186 * identification. Toshiba chip isn't detailed as yet. 1187 */ 1188 1189 /* Init the CL id mode */ 1190 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1191 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1192 1193 /* default to Intel i82365SL and then refine */ 1194 pcic->pc_type = PCIC_I82365SL; 1195 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1196 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1197 /* go until one succeeds or none left */ 1198 if (pcic_ci_funcs[value](pcic)) 1199 break; 1200 } 1201 1202 /* any chip specific flags get set here */ 1203 switch (pcic->pc_type) { 1204 case PCIC_CL_PD6722: 1205 pcic->pc_flags |= PCF_DMA; 1206 } 1207 1208 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1209 /* 1210 * look for total number of sockets. 1211 * basically check each possible socket for 1212 * presence like in probe 1213 */ 1214 1215 /* turn all windows off */ 1216 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1217 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1218 1219 /* 1220 * if a zero is read back, then this socket 1221 * might be present. It would be except for 1222 * some systems that map the secondary PCIC 1223 * chip space back to the first. 1224 */ 1225 if (value != 0) { 1226 /* definitely not so skip */ 1227 /* note: this is for Compaq support */ 1228 continue; 1229 } 1230 1231 /* further tests */ 1232 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1233 PCIC_REV_MASK; 1234 if (!(value >= PCIC_REV_LEVEL_LOW && 1235 value <= PCIC_REV_LEVEL_HI)) 1236 break; 1237 1238 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1239 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1240 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1241 1242 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1243 if (value != 0xaa || j != 0x55) 1244 break; 1245 1246 /* 1247 * at this point we know if we have hardware 1248 * of some type and not just the bus holding 1249 * a pattern for us. We still have to determine 1250 * the case where more than 2 sockets are 1251 * really the same due to peculiar mappings of 1252 * hardware. 1253 */ 1254 j = pcic->pc_numsockets++; 1255 pcic->pc_sockets[j].pcs_flags = 0; 1256 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1257 pcic->pc_sockets[j].pcs_socket = i; 1258 1259 /* put PC Card into RESET, just in case */ 1260 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1261 pcic_putb(pcic, i, PCIC_INTERRUPT, 1262 value & ~PCIC_RESET); 1263 } 1264 1265 #if defined(PCIC_DEBUG) 1266 if (pcic_debug) 1267 cmn_err(CE_CONT, "num sockets = %d\n", 1268 pcic->pc_numsockets); 1269 #endif 1270 if (pcic->pc_numsockets == 0) { 1271 ddi_regs_map_free(&pcic->handle); 1272 kmem_free(pcic, sizeof (pcicdev_t)); 1273 return (DDI_FAILURE); 1274 } 1275 1276 /* 1277 * need to think this through again in light of 1278 * Compaq not following the model that all the 1279 * chip vendors recommend. IBM 755 seems to be 1280 * afflicted as well. Basically, if the vendor 1281 * wired things wrong, socket 0 responds for socket 2 1282 * accesses, etc. 1283 */ 1284 if (pcic->pc_numsockets > 2) { 1285 int count = pcic->pc_numsockets / 4; 1286 for (i = 0; i < count; i++) { 1287 /* put pattern into socket 0 */ 1288 pcic_putb(pcic, i, 1289 PCIC_SYSMEM_0_STARTLOW, 0x11); 1290 1291 /* put pattern into socket 2 */ 1292 pcic_putb(pcic, i + 2, 1293 PCIC_SYSMEM_0_STARTLOW, 0x33); 1294 1295 /* read back socket 0 */ 1296 value = pcic_getb(pcic, i, 1297 PCIC_SYSMEM_0_STARTLOW); 1298 1299 /* read back chip 1 socket 0 */ 1300 j = pcic_getb(pcic, i + 2, 1301 PCIC_SYSMEM_0_STARTLOW); 1302 if (j == value) { 1303 pcic->pc_numsockets -= 2; 1304 } 1305 } 1306 } 1307 1308 smi = 0xff; /* no more override */ 1309 1310 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1311 DDI_PROP_DONTPASS, "need-mult-irq", 1312 0xffff) != 0xffff) 1313 pcic->pc_flags |= PCF_MULT_IRQ; 1314 1315 } /* !PCF_PCIBUS */ 1316 1317 /* 1318 * some platforms/busses need to have resources setup 1319 * this is temporary until a real resource allocator is 1320 * implemented. 1321 */ 1322 1323 pcic_init_assigned(dip); 1324 1325 typename = pcic->pc_chipname; 1326 1327 #ifdef PCIC_DEBUG 1328 if (pcic_debug) { 1329 int nregs, nintrs; 1330 1331 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1332 nregs = 0; 1333 1334 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1335 nintrs = 0; 1336 1337 cmn_err(CE_CONT, 1338 "pcic%d: %d register sets, %d interrupts\n", 1339 ddi_get_instance(dip), nregs, nintrs); 1340 1341 nintrs = 0; 1342 while (nregs--) { 1343 off_t size; 1344 1345 if (ddi_dev_regsize(dip, nintrs, &size) == 1346 DDI_SUCCESS) { 1347 cmn_err(CE_CONT, 1348 "\tregnum %d size %ld (0x%lx)" 1349 "bytes", 1350 nintrs, size, size); 1351 if (nintrs == 1352 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1353 PCIC_ISA_CONTROL_REG_NUM : 1354 PCIC_PCI_CONTROL_REG_NUM)) 1355 cmn_err(CE_CONT, 1356 " mapped at: 0x%p\n", 1357 (void *)pcic->ioaddr); 1358 else 1359 cmn_err(CE_CONT, "\n"); 1360 } else { 1361 cmn_err(CE_CONT, 1362 "\tddi_dev_regsize(rnumber" 1363 "= %d) returns DDI_FAILURE\n", 1364 nintrs); 1365 } 1366 nintrs++; 1367 } /* while */ 1368 } /* if (pcic_debug) */ 1369 #endif 1370 1371 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1372 1373 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1374 "disable-audio", 0)) 1375 pcic->pc_flags |= PCF_AUDIO; 1376 1377 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1378 "disable-cardbus", 0)) 1379 pcic->pc_flags &= ~PCF_CARDBUS; 1380 1381 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1382 typename); 1383 1384 /* 1385 * Init all socket SMI levels to 0 (no SMI) 1386 */ 1387 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1388 pcic->pc_sockets[i].pcs_smi = 0; 1389 pcic->pc_sockets[i].pcs_debounce_id = 0; 1390 pcic->pc_sockets[i].pcs_pcic = pcic; 1391 } 1392 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1393 1394 /* 1395 * Setup the IRQ handler(s) 1396 */ 1397 switch (pcic->pc_intr_mode) { 1398 int xx; 1399 case PCIC_INTR_MODE_ISA: 1400 /* 1401 * On a non-PCI bus, we just use whatever SMI IRQ level was 1402 * specified above, and the IO IRQ levels are allocated 1403 * dynamically. 1404 */ 1405 for (xx = 15, smi = 0; xx >= 0; xx--) { 1406 if (PCIC_IRQ(xx) & 1407 PCIC_AVAIL_IRQS) { 1408 smi = pcmcia_get_intr(dip, xx); 1409 if (smi >= 0) 1410 break; 1411 } 1412 } 1413 #if defined(PCIC_DEBUG) 1414 if (pcic_debug) 1415 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1416 #endif 1417 /* init to same so share is easy */ 1418 for (i = 0; i < pcic->pc_numsockets; i++) 1419 pcic->pc_sockets[i].pcs_smi = smi; 1420 /* any special handling of IRQ levels */ 1421 if (pcic->pc_flags & PCF_MULT_IRQ) { 1422 for (i = 2; i < pcic->pc_numsockets; i++) { 1423 if ((i & 1) == 0) { 1424 int xx; 1425 for (xx = 15, smi = 0; xx >= 0; xx--) { 1426 if (PCIC_IRQ(xx) & 1427 PCIC_AVAIL_IRQS) { 1428 smi = 1429 pcmcia_get_intr(dip, 1430 xx); 1431 if (smi >= 0) 1432 break; 1433 } 1434 } 1435 } 1436 if (smi >= 0) 1437 pcic->pc_sockets[i].pcs_smi = smi; 1438 } 1439 } 1440 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1441 sizeof (ddi_intr_handle_t), KM_SLEEP); 1442 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1443 struct intrspec *ispecp; 1444 struct ddi_parent_private_data *pdp; 1445 1446 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1447 continue; 1448 else { 1449 irqlevel = pcic->pc_sockets[i].pcs_smi; 1450 } 1451 /* 1452 * now convert the allocated IRQ into an intrspec 1453 * and ask our parent to add it. Don't use 1454 * the ddi_add_intr since we don't have a 1455 * default intrspec in all cases. 1456 * 1457 * note: this sort of violates DDI but we don't 1458 * get hardware intrspecs for many of the devices. 1459 * at the same time, we know how to allocate them 1460 * so we do the right thing. 1461 */ 1462 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1463 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1464 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1465 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1466 ddi_get_name(dip)); 1467 goto isa_exit1; 1468 } 1469 1470 /* 1471 * See earlier note: 1472 * Since some devices don't have 'intrspec' 1473 * we make one up in rootnex. 1474 * 1475 * However, it is not properly initialized as 1476 * the data it needs is present in this driver 1477 * and there is no interface to pass that up. 1478 * Specially 'irqlevel' is very important and 1479 * it is part of pcic struct. 1480 * 1481 * Set 'intrspec' up here; otherwise adding the 1482 * interrupt will fail. 1483 */ 1484 pdp = ddi_get_parent_data(dip); 1485 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1486 ispecp->intrspec_vec = irqlevel; 1487 ispecp->intrspec_pri = pcic->pc_irq; 1488 1489 /* Stay compatible w/ PCMCIA */ 1490 pcic->pc_pri = (ddi_iblock_cookie_t) 1491 (uintptr_t)pcic->pc_irq; 1492 pcic->pc_dcookie.idev_priority = 1493 (uintptr_t)pcic->pc_pri; 1494 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1495 1496 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1497 pcic->pc_irq); 1498 1499 if (i == 0) { 1500 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1501 DDI_INTR_PRI(pcic->pc_irq)); 1502 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1503 NULL); 1504 } 1505 1506 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1507 pcic_intr, (caddr_t)pcic, NULL)) { 1508 cmn_err(CE_WARN, 1509 "%s: ddi_intr_add_handler failed", 1510 ddi_get_name(dip)); 1511 goto isa_exit2; 1512 } 1513 1514 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1515 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1516 ddi_get_name(dip)); 1517 for (j = i; j < 0; j--) 1518 (void) ddi_intr_remove_handler( 1519 pcic->pc_intr_htblp[j]); 1520 goto isa_exit2; 1521 } 1522 } 1523 break; 1524 case PCIC_INTR_MODE_PCI_1: 1525 case PCIC_INTR_MODE_PCI: 1526 /* 1527 * If we're on a PCI bus, we route all interrupts, both SMI 1528 * and IO interrupts, through a single interrupt line. 1529 * Assign the SMI IRQ level to the IO IRQ level here. 1530 */ 1531 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1532 KM_SLEEP); 1533 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1534 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1535 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1536 goto pci_exit1; 1537 1538 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1539 &pri) != DDI_SUCCESS) { 1540 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1541 goto pci_exit1; 1542 } 1543 1544 pcic->pc_pri = (void *)(uintptr_t)pri; 1545 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1546 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1547 1548 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1549 pcic_intr, (caddr_t)pcic, NULL)) 1550 goto pci_exit2; 1551 1552 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1553 (void) ddi_intr_remove_handler( 1554 pcic->pc_pci_intr_hdlp[0]); 1555 goto pci_exit2; 1556 } 1557 1558 /* Stay compatible w/ PCMCIA */ 1559 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1560 1561 /* init to same (PCI) so share is easy */ 1562 for (i = 0; i < pcic->pc_numsockets; i++) 1563 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1564 break; 1565 } 1566 1567 /* 1568 * Setup the adapter hardware to some reasonable defaults. 1569 */ 1570 mutex_enter(&pcic->pc_lock); 1571 /* mark the driver state as attached */ 1572 pcic->pc_flags |= PCF_ATTACHED; 1573 pcic_setup_adapter(pcic); 1574 1575 for (j = 0; j < pcic->pc_numsockets; j++) 1576 if (ddi_intr_add_softint(dip, 1577 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1578 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1579 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1580 goto pci_exit2; 1581 1582 #if defined(PCIC_DEBUG) 1583 if (pcic_debug) 1584 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1585 pcic->pc_numsockets); 1586 #endif 1587 1588 pcic_nexus->an_iblock = &pcic->pc_pri; 1589 pcic_nexus->an_idev = &pcic->pc_dcookie; 1590 1591 mutex_exit(&pcic->pc_lock); 1592 1593 #ifdef CARDBUS 1594 (void) cardbus_enable_cd_intr(dip); 1595 if (pcic_debug) { 1596 1597 cardbus_dump_pci_config(dip); 1598 cardbus_dump_socket(dip); 1599 } 1600 1601 /* 1602 * Give the Cardbus misc module a chance to do it's per-adapter 1603 * instance setup. Note that there is no corresponding detach() 1604 * call. 1605 */ 1606 if (pcic->pc_flags & PCF_CARDBUS) 1607 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1608 cmn_err(CE_CONT, 1609 "pcic_attach: cardbus_attach failed\n"); 1610 goto pci_exit2; 1611 } 1612 #endif 1613 1614 /* 1615 * Give the PCMCIA misc module a chance to do it's per-adapter 1616 * instance setup. 1617 */ 1618 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1619 goto pci_exit2; 1620 1621 syshw_attach(pcic); 1622 if (pcic_maxinst == -1) { 1623 /* This assumes that all instances run at the same IPL. */ 1624 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1625 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1626 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1627 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1628 v.v_maxsyspri - 2); 1629 } 1630 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1631 /* 1632 * Setup a debounce timeout to do an initial card detect 1633 * and enable interrupts. 1634 */ 1635 for (j = 0; j < pcic->pc_numsockets; j++) { 1636 shwp = kmem_alloc(sizeof (syshw_t), KM_SLEEP); 1637 if (shwp) { 1638 bcopy(&pcic_syshw, shwp, sizeof (pcic_syshw)); 1639 pcic_syshw.id_string[15]++; 1640 pcic->pc_sockets[j].pcs_syshwsig = 1641 syshw_add2map(shwp, pcic_syshw_cardstate, 1642 &pcic->pc_sockets[j]); 1643 } 1644 pcic->pc_sockets[j].pcs_debounce_id = 1645 pcic_add_debqueue(&pcic->pc_sockets[j], 1646 drv_usectohz(pcic_debounce_time)); 1647 } 1648 1649 return (i); 1650 1651 isa_exit2: 1652 mutex_destroy(&pcic->intr_lock); 1653 mutex_destroy(&pcic->pc_lock); 1654 for (j = i; j < 0; j--) 1655 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1656 isa_exit1: 1657 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1658 ddi_regs_map_free(&pcic->handle); 1659 if (pcic->pc_flags & PCF_PCIBUS) 1660 ddi_regs_map_free(&pcic->cfg_handle); 1661 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1662 sizeof (ddi_intr_handle_t)); 1663 kmem_free(pcic, sizeof (pcicdev_t)); 1664 return (DDI_FAILURE); 1665 1666 pci_exit2: 1667 mutex_destroy(&pcic->intr_lock); 1668 mutex_destroy(&pcic->pc_lock); 1669 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1670 pci_exit1: 1671 ddi_regs_map_free(&pcic->handle); 1672 if (pcic->pc_flags & PCF_PCIBUS) 1673 ddi_regs_map_free(&pcic->cfg_handle); 1674 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1675 kmem_free(pcic, sizeof (pcicdev_t)); 1676 return (DDI_FAILURE); 1677 } 1678 1679 /* 1680 * pcic_detach() 1681 * request to detach from the system 1682 */ 1683 static int 1684 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1685 { 1686 anp_t *anp = ddi_get_driver_private(dip); 1687 pcicdev_t *pcic = anp->an_private; 1688 int i; 1689 1690 switch (cmd) { 1691 case DDI_DETACH: 1692 /* don't detach if the nexus still talks to us */ 1693 if (pcic->pc_callback != NULL) 1694 return (DDI_FAILURE); 1695 syshw_detach(pcic); 1696 1697 /* kill off the pm simulation */ 1698 if (pcic->pc_pmtimer) 1699 (void) untimeout(pcic->pc_pmtimer); 1700 1701 /* turn everything off for all sockets and chips */ 1702 for (i = 0; i < pcic->pc_numsockets; i++) { 1703 if (pcic->pc_sockets[i].pcs_debounce_id) 1704 pcic_rm_debqueue( 1705 pcic->pc_sockets[i].pcs_debounce_id); 1706 pcic->pc_sockets[i].pcs_debounce_id = 0; 1707 1708 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1709 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1710 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1711 /* disable interrupts and put card into RESET */ 1712 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1713 } 1714 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1715 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1716 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1717 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1718 pcic->pc_flags = 0; 1719 mutex_destroy(&pcic->pc_lock); 1720 mutex_destroy(&pcic->intr_lock); 1721 cv_destroy(&pcic->pm_cv); 1722 if (pcic->pc_flags & PCF_PCIBUS) 1723 ddi_regs_map_free(&pcic->cfg_handle); 1724 if (pcic->handle) 1725 ddi_regs_map_free(&pcic->handle); 1726 kmem_free(pcic, sizeof (pcicdev_t)); 1727 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1728 return (DDI_SUCCESS); 1729 1730 case DDI_SUSPEND: 1731 case DDI_PM_SUSPEND: 1732 /* 1733 * we got a suspend event (either real or imagined) 1734 * so notify the nexus proper that all existing cards 1735 * should go away. 1736 */ 1737 mutex_enter(&pcic->pc_lock); 1738 #ifdef CARDBUS 1739 if (pcic->pc_flags & PCF_CARDBUS) 1740 for (i = 0; i < pcic->pc_numsockets; i++) 1741 if ((pcic->pc_sockets[i].pcs_flags & 1742 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1743 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) 1744 if (!cardbus_can_suspend(dip)) { 1745 mutex_exit(&pcic->pc_lock); 1746 cmn_err(CE_WARN, 1747 "Please unconfigure all " 1748 "CardBus devices before " 1749 "attempting to suspend\n"); 1750 return (DDI_FAILURE); 1751 } 1752 #endif 1753 /* turn everything off for all sockets and chips */ 1754 for (i = 0; i < pcic->pc_numsockets; i++) { 1755 if (pcic->pc_sockets[i].pcs_debounce_id) 1756 pcic_rm_debqueue( 1757 pcic->pc_sockets[i].pcs_debounce_id); 1758 pcic->pc_sockets[i].pcs_debounce_id = 0; 1759 1760 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1761 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1762 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1763 /* disable interrupts and put card into RESET */ 1764 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1765 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1766 if (pcic->pc_flags & PCF_CBPWRCTL) 1767 pcic_putcb(pcic, CB_CONTROL, 0); 1768 1769 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1770 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1771 /* 1772 * Because we are half way through a save 1773 * all this does is schedule a removal event 1774 * to cs for when the system comes back. 1775 * This doesn't actually matter. 1776 */ 1777 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1778 pcic->pc_callback) { 1779 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1780 PCE_CARD_REMOVAL, 1781 pcic->pc_sockets[i].pcs_socket); 1782 } 1783 } 1784 } 1785 1786 pcic->pc_flags |= PCF_SUSPENDED; 1787 mutex_exit(&pcic->pc_lock); 1788 pcic_delayed_resume_toid = 0; 1789 1790 /* 1791 * when true power management exists, save the adapter 1792 * state here to enable a recovery. For the emulation 1793 * condition, the state is gone 1794 */ 1795 return (DDI_SUCCESS); 1796 1797 default: 1798 return (EINVAL); 1799 } 1800 } 1801 1802 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1803 static uint32_t pcic_tisysctl_offbits = 0; 1804 static uint32_t pcic_default_latency = 0x40; 1805 1806 static void 1807 pcic_setup_adapter(pcicdev_t *pcic) 1808 { 1809 int i; 1810 int value, flags; 1811 1812 if (pcic->pc_flags & PCF_PCIBUS) { 1813 /* 1814 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1815 */ 1816 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1817 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1818 } 1819 /* enable each socket */ 1820 for (i = 0; i < pcic->pc_numsockets; i++) { 1821 pcic->pc_sockets[i].pcs_flags = 0; 1822 /* find out the socket capabilities (I/O vs memory) */ 1823 value = pcic_getb(pcic, i, 1824 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1825 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1826 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1827 1828 /* disable all windows just in case */ 1829 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1830 1831 switch (pcic->pc_type) { 1832 uint32_t cfg32; 1833 uint16_t cfg16; 1834 uint8_t cfg; 1835 1836 /* enable extended registers for Vadem */ 1837 case PCIC_VADEM_VG469: 1838 case PCIC_VADEM: 1839 1840 /* enable card status change interrupt for socket */ 1841 break; 1842 1843 case PCIC_I82365SL: 1844 break; 1845 1846 case PCIC_CL_PD6710: 1847 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1848 break; 1849 1850 /* 1851 * On the CL_6730, we need to set up the interrupt 1852 * signalling mode (PCI mode) and set the SMI and 1853 * IRQ interrupt lines to PCI/level-mode. 1854 */ 1855 case PCIC_CL_PD6730: 1856 switch (pcic->pc_intr_mode) { 1857 case PCIC_INTR_MODE_PCI_1: 1858 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1859 ((clext_reg_read(pcic, i, 1860 PCIC_CLEXT_MISC_CTL_3) & 1861 ~PCIC_CLEXT_INT_PCI) | 1862 PCIC_CLEXT_INT_PCI)); 1863 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1864 (PCIC_CLEXT_IRQ_LVL_MODE | 1865 PCIC_CLEXT_SMI_LVL_MODE)); 1866 cfg = PCIC_CL_LP_DYN_MODE; 1867 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1868 break; 1869 case PCIC_INTR_MODE_ISA: 1870 break; 1871 } 1872 break; 1873 /* 1874 * On the CL_6729, we set the SMI and IRQ interrupt 1875 * lines to PCI/level-mode. as well as program the 1876 * correct clock speed divider bit. 1877 */ 1878 case PCIC_CL_PD6729: 1879 switch (pcic->pc_intr_mode) { 1880 case PCIC_INTR_MODE_PCI_1: 1881 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1882 (PCIC_CLEXT_IRQ_LVL_MODE | 1883 PCIC_CLEXT_SMI_LVL_MODE)); 1884 1885 break; 1886 case PCIC_INTR_MODE_ISA: 1887 break; 1888 } 1889 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1890 cfg = 0; 1891 cfg |= PCIC_CL_TIMER_CLK_DIV; 1892 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1893 } 1894 break; 1895 case PCIC_INTEL_i82092: 1896 cfg = PCIC_82092_EN_TIMING; 1897 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1898 cfg |= PCIC_82092_PCICLK_25MHZ; 1899 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1900 PCIC_82092_PCICON, cfg); 1901 break; 1902 case PCIC_TI_PCI1130: 1903 case PCIC_TI_PCI1131: 1904 case PCIC_TI_PCI1250: 1905 case PCIC_TI_PCI1031: 1906 cfg = ddi_get8(pcic->cfg_handle, 1907 pcic->cfgaddr + PCIC_DEVCTL_REG); 1908 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1909 switch (pcic->pc_intr_mode) { 1910 case PCIC_INTR_MODE_ISA: 1911 cfg |= PCIC_DEVCTL_INTR_ISA; 1912 break; 1913 } 1914 #ifdef PCIC_DEBUG 1915 if (pcic_debug) { 1916 cmn_err(CE_CONT, "pcic_setup_adapter: " 1917 "write reg 0x%x=%x \n", 1918 PCIC_DEVCTL_REG, cfg); 1919 } 1920 #endif 1921 ddi_put8(pcic->cfg_handle, 1922 pcic->cfgaddr + PCIC_DEVCTL_REG, 1923 cfg); 1924 1925 cfg = ddi_get8(pcic->cfg_handle, 1926 pcic->cfgaddr + PCIC_CRDCTL_REG); 1927 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1928 PCIC_CRDCTL_PCIFUNC); 1929 switch (pcic->pc_intr_mode) { 1930 case PCIC_INTR_MODE_PCI_1: 1931 cfg |= PCIC_CRDCTL_PCIINTR | 1932 PCIC_CRDCTL_PCICSC | 1933 PCIC_CRDCTL_PCIFUNC; 1934 pcic->pc_flags |= PCF_USE_SMI; 1935 break; 1936 } 1937 #ifdef PCIC_DEBUG 1938 if (pcic_debug) { 1939 cmn_err(CE_CONT, "pcic_setup_adapter: " 1940 " write reg 0x%x=%x \n", 1941 PCIC_CRDCTL_REG, cfg); 1942 } 1943 #endif 1944 ddi_put8(pcic->cfg_handle, 1945 pcic->cfgaddr + PCIC_CRDCTL_REG, 1946 cfg); 1947 break; 1948 case PCIC_TI_PCI1221: 1949 case PCIC_TI_PCI1225: 1950 cfg = ddi_get8(pcic->cfg_handle, 1951 pcic->cfgaddr + PCIC_DEVCTL_REG); 1952 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1953 #ifdef PCIC_DEBUG 1954 if (pcic_debug) { 1955 cmn_err(CE_CONT, "pcic_setup_adapter: " 1956 " write reg 0x%x=%x \n", 1957 PCIC_DEVCTL_REG, cfg); 1958 } 1959 #endif 1960 ddi_put8(pcic->cfg_handle, 1961 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1962 1963 cfg = ddi_get8(pcic->cfg_handle, 1964 pcic->cfgaddr + PCIC_DIAG_REG); 1965 if (pcic->pc_type == PCIC_TI_PCI1225) { 1966 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1967 } else { 1968 cfg |= PCIC_DIAG_ASYNC; 1969 } 1970 pcic->pc_flags |= PCF_USE_SMI; 1971 #ifdef PCIC_DEBUG 1972 if (pcic_debug) { 1973 cmn_err(CE_CONT, "pcic_setup_adapter: " 1974 " write reg 0x%x=%x \n", 1975 PCIC_DIAG_REG, cfg); 1976 } 1977 #endif 1978 ddi_put8(pcic->cfg_handle, 1979 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1980 break; 1981 case PCIC_TI_PCI1520: 1982 case PCIC_TI_PCI1510: 1983 case PCIC_TI_VENDOR: 1984 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1985 cfg = ddi_get8(pcic->cfg_handle, 1986 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1987 cfg |= PCIC_FUN_INT_MOD_ISA; 1988 ddi_put8(pcic->cfg_handle, 1989 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1990 cfg); 1991 } 1992 cfg = ddi_get8(pcic->cfg_handle, 1993 pcic->cfgaddr + PCIC_DEVCTL_REG); 1994 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1995 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) 1996 cfg |= PCIC_DEVCTL_INTR_ISA; 1997 ddi_put8(pcic->cfg_handle, 1998 pcic->cfgaddr + PCIC_DEVCTL_REG, 1999 cfg); 2000 2001 /* tie INTA and INTB together */ 2002 cfg = ddi_get8(pcic->cfg_handle, 2003 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 2004 cfg |= PCIC_SYSCTL_INTRTIE; 2005 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 2006 PCIC_SYSCTL_REG + 3), cfg); 2007 cfg = ddi_get8(pcic->cfg_handle, 2008 pcic->cfgaddr + PCIC_DIAG_REG); 2009 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2010 ddi_put8(pcic->cfg_handle, 2011 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2012 break; 2013 case PCIC_TI_PCI1410: 2014 cfg = ddi_get8(pcic->cfg_handle, 2015 pcic->cfgaddr + PCIC_DIAG_REG); 2016 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2017 ddi_put8(pcic->cfg_handle, 2018 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2019 break; 2020 case PCIC_TOSHIBA_TOPIC100: 2021 case PCIC_TOSHIBA_TOPIC95: 2022 case PCIC_TOSHIBA_VENDOR: 2023 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2024 PCIC_TOSHIBA_SLOT_CTL_REG); 2025 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 2026 PCIC_TOSHIBA_SCR_SLOTEN); 2027 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 2028 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 2029 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 2030 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 2031 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2032 PCIC_TOSHIBA_INTR_CTL_REG); 2033 switch (pcic->pc_intr_mode) { 2034 case PCIC_INTR_MODE_ISA: 2035 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 2036 ddi_put8(pcic->cfg_handle, 2037 pcic->cfgaddr + 2038 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2039 2040 cfg = ddi_get8(pcic->cfg_handle, 2041 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2042 cfg |= PCIC_FUN_INT_MOD_ISA; 2043 ddi_put8(pcic->cfg_handle, 2044 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2045 cfg); 2046 break; 2047 case PCIC_INTR_MODE_PCI_1: 2048 cfg |= PCIC_TOSHIBA_ICR_SRC; 2049 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 2050 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 2051 ddi_put8(pcic->cfg_handle, 2052 pcic->cfgaddr + 2053 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2054 break; 2055 } 2056 break; 2057 case PCIC_O2MICRO_VENDOR: 2058 cfg32 = ddi_get32(pcic->cfg_handle, 2059 (uint32_t *)(pcic->cfgaddr + 2060 PCIC_O2MICRO_MISC_CTL)); 2061 switch (pcic->pc_intr_mode) { 2062 case PCIC_INTR_MODE_ISA: 2063 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 2064 PCIC_O2MICRO_INT_MOD_PCI); 2065 ddi_put32(pcic->cfg_handle, 2066 (uint32_t *)(pcic->cfgaddr + 2067 PCIC_O2MICRO_MISC_CTL), 2068 cfg32); 2069 cfg = ddi_get8(pcic->cfg_handle, 2070 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2071 cfg |= PCIC_FUN_INT_MOD_ISA; 2072 ddi_put8(pcic->cfg_handle, 2073 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2074 cfg); 2075 break; 2076 case PCIC_INTR_MODE_PCI_1: 2077 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2078 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2079 ddi_put32(pcic->cfg_handle, 2080 (uint32_t *)(pcic->cfgaddr + 2081 PCIC_O2MICRO_MISC_CTL), 2082 cfg32); 2083 break; 2084 } 2085 break; 2086 case PCIC_RICOH_VENDOR: 2087 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2088 cfg16 = ddi_get16(pcic->cfg_handle, 2089 (uint16_t *)(pcic->cfgaddr + 2090 PCIC_RICOH_MISC_CTL_2)); 2091 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2092 PCIC_RICOH_FUN_INT_MOD); 2093 ddi_put16(pcic->cfg_handle, 2094 (uint16_t *)(pcic->cfgaddr + 2095 PCIC_RICOH_MISC_CTL_2), 2096 cfg16); 2097 2098 cfg16 = ddi_get16(pcic->cfg_handle, 2099 (uint16_t *)(pcic->cfgaddr + 2100 PCIC_RICOH_MISC_CTL)); 2101 cfg16 |= PCIC_RICOH_SIRQ_EN; 2102 ddi_put16(pcic->cfg_handle, 2103 (uint16_t *)(pcic->cfgaddr + 2104 PCIC_RICOH_MISC_CTL), 2105 cfg16); 2106 2107 cfg = ddi_get8(pcic->cfg_handle, 2108 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2109 cfg |= PCIC_FUN_INT_MOD_ISA; 2110 ddi_put8(pcic->cfg_handle, 2111 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2112 cfg); 2113 } 2114 break; 2115 default: 2116 break; 2117 } /* switch */ 2118 2119 /* setup general card status change interrupt */ 2120 switch (pcic->pc_type) { 2121 case PCIC_TI_PCI1225: 2122 case PCIC_TI_PCI1221: 2123 case PCIC_TI_PCI1031: 2124 case PCIC_TI_PCI1520: 2125 case PCIC_TI_PCI1410: 2126 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2127 PCIC_CHANGE_DEFAULT); 2128 break; 2129 default: 2130 if (pcic->pc_intr_mode == 2131 PCIC_INTR_MODE_PCI_1) { 2132 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2133 PCIC_CHANGE_DEFAULT); 2134 break; 2135 } else { 2136 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2137 PCIC_CHANGE_DEFAULT | 2138 (pcic->pc_sockets[i].pcs_smi << 4)); 2139 break; 2140 } 2141 } 2142 2143 pcic->pc_flags |= PCF_INTRENAB; 2144 2145 /* take card out of RESET */ 2146 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2147 /* turn power off and let CS do this */ 2148 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2149 2150 /* final chip specific initialization */ 2151 switch (pcic->pc_type) { 2152 case PCIC_VADEM: 2153 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2154 PCIC_VC_DELAYENABLE); 2155 pcic->pc_flags |= PCF_DEBOUNCE; 2156 /* FALLTHROUGH */ 2157 case PCIC_I82365SL: 2158 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2159 PCIC_GC_CSC_WRITE); 2160 /* clear any pending interrupts */ 2161 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2162 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2163 break; 2164 /* The 82092 uses PCI config space to enable interrupts */ 2165 case PCIC_INTEL_i82092: 2166 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2167 PCIC_82092_INT_ENABLE); 2168 break; 2169 case PCIC_CL_PD6729: 2170 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2171 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2172 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2173 value | PCIC_CL_TIMER_CLK_DIV); 2174 } 2175 break; 2176 } /* switch */ 2177 2178 #if defined(PCIC_DEBUG) 2179 if (pcic_debug) 2180 cmn_err(CE_CONT, 2181 "socket %d value=%x, flags = %x (%s)\n", 2182 i, value, pcic->pc_sockets[i].pcs_flags, 2183 (pcic->pc_sockets[i].pcs_flags & 2184 PCS_CARD_PRESENT) ? 2185 "card present" : "no card"); 2186 #endif 2187 } 2188 } 2189 2190 /* 2191 * pcic_intr(caddr_t, caddr_t) 2192 * interrupt handler for the PCIC style adapter 2193 * handles all basic interrupts and also checks 2194 * for status changes and notifies the nexus if 2195 * necessary 2196 * 2197 * On PCI bus adapters, also handles all card 2198 * IO interrupts. 2199 */ 2200 /*ARGSUSED*/ 2201 uint32_t 2202 pcic_intr(caddr_t arg1, caddr_t arg2) 2203 { 2204 pcicdev_t *pcic = (pcicdev_t *)arg1; 2205 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2206 uint8_t status; 2207 uint_t io_ints; 2208 2209 #if defined(PCIC_DEBUG) 2210 pcic_err(pcic->dip, 0xf, 2211 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2212 " pc_numsockets=%d \n", 2213 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2214 #endif 2215 2216 if (!(pcic->pc_flags & PCF_ATTACHED)) 2217 return (DDI_INTR_UNCLAIMED); 2218 2219 mutex_enter(&pcic->intr_lock); 2220 2221 if (pcic->pc_flags & PCF_SUSPENDED) { 2222 mutex_exit(&pcic->intr_lock); 2223 return (ret); 2224 } 2225 2226 /* 2227 * need to change to only ACK and touch the slot that 2228 * actually caused the interrupt. Currently everything 2229 * is acked 2230 * 2231 * we need to look at all known sockets to determine 2232 * what might have happened, so step through the list 2233 * of them 2234 */ 2235 #ifdef VOYAGER 2236 ret = syshw_intr_hi(pcic); 2237 #endif 2238 2239 /* 2240 * Set the bitmask for IO interrupts to initially include all sockets 2241 */ 2242 io_ints = (1 << pcic->pc_numsockets) - 1; 2243 2244 for (i = 0; i < pcic->pc_numsockets; i++) { 2245 int card_type; 2246 pcic_socket_t *sockp; 2247 int value_cb = 0; 2248 2249 sockp = &pcic->pc_sockets[i]; 2250 /* get the socket's I/O addresses */ 2251 2252 if (sockp->pcs_flags & PCS_WAITING) { 2253 io_ints &= ~(1 << i); 2254 continue; 2255 } 2256 2257 if (sockp->pcs_flags & PCS_CARD_IO) 2258 card_type = IF_IO; 2259 else 2260 card_type = IF_MEMORY; 2261 2262 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2263 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2264 2265 value = pcic_change(pcic, i); 2266 2267 if ((value != 0) || (value_cb != 0)) { 2268 int x = pcic->pc_cb_arg; 2269 2270 ret = DDI_INTR_CLAIMED; 2271 2272 #if defined(PCIC_DEBUG) 2273 pcic_err(pcic->dip, 0x9, 2274 "card_type = %d, value_cb = 0x%x\n", 2275 card_type, 2276 value_cb ? value_cb : 2277 pcic_getcb(pcic, CB_STATUS_EVENT)); 2278 if (pcic_debug) 2279 cmn_err(CE_CONT, 2280 "\tchange on socket %d (%x)\n", i, 2281 value); 2282 #endif 2283 /* find out what happened */ 2284 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2285 2286 /* acknowledge the interrupt */ 2287 if (value_cb) 2288 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2289 2290 if (value) 2291 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2292 value); 2293 2294 if (pcic->pc_callback == NULL) { 2295 /* if not callback handler, nothing to do */ 2296 continue; 2297 } 2298 2299 /* Card Detect */ 2300 if (value & PCIC_CD_DETECT || 2301 value_cb & CB_PS_CCDMASK) { 2302 uint8_t irq; 2303 #if defined(PCIC_DEBUG) 2304 if (pcic_debug) 2305 cmn_err(CE_CONT, 2306 "\tcd_detect: status=%x," 2307 " flags=%x\n", 2308 status, sockp->pcs_flags); 2309 #else 2310 #ifdef lint 2311 if (status == 0) 2312 status++; 2313 #endif 2314 #endif 2315 /* 2316 * Turn off all interrupts for this socket here. 2317 */ 2318 irq = pcic_getb(pcic, sockp->pcs_socket, 2319 PCIC_MANAGEMENT_INT); 2320 irq &= ~PCIC_CHANGE_MASK; 2321 pcic_putb(pcic, sockp->pcs_socket, 2322 PCIC_MANAGEMENT_INT, irq); 2323 2324 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2325 2326 /* 2327 * Put the socket in debouncing state so that 2328 * the leaf driver won't receive interrupts. 2329 * Crucial for handling surprise-removal. 2330 */ 2331 sockp->pcs_flags |= PCS_DEBOUNCING; 2332 2333 if (!sockp->pcs_cd_softint_flg) { 2334 sockp->pcs_cd_softint_flg = 1; 2335 (void) ddi_intr_trigger_softint( 2336 sockp->pcs_cd_softint_hdl, NULL); 2337 } 2338 2339 io_ints &= ~(1 << i); 2340 } /* PCIC_CD_DETECT */ 2341 2342 /* Ready/Change Detect */ 2343 sockp->pcs_state ^= SBM_RDYBSY; 2344 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2345 sockp->pcs_flags |= PCS_READY; 2346 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2347 } 2348 2349 /* Battery Warn Detect */ 2350 if (card_type == IF_MEMORY && 2351 value & PCIC_BW_DETECT && 2352 !(sockp->pcs_state & SBM_BVD2)) { 2353 sockp->pcs_state |= SBM_BVD2; 2354 PC_CALLBACK(pcic->dip, x, 2355 PCE_CARD_BATTERY_WARN, i); 2356 } 2357 2358 /* Battery Dead Detect */ 2359 if (value & PCIC_BD_DETECT) { 2360 /* 2361 * need to work out event if RI not enabled 2362 * and card_type == IF_IO 2363 */ 2364 if (card_type == IF_MEMORY && 2365 !(sockp->pcs_state & SBM_BVD1)) { 2366 sockp->pcs_state |= SBM_BVD1; 2367 PC_CALLBACK(pcic->dip, x, 2368 PCE_CARD_BATTERY_DEAD, 2369 i); 2370 } else { 2371 /* 2372 * information in pin replacement 2373 * register if one is available 2374 */ 2375 PC_CALLBACK(pcic->dip, x, 2376 PCE_CARD_STATUS_CHANGE, 2377 i); 2378 } /* IF_MEMORY */ 2379 } /* PCIC_BD_DETECT */ 2380 } /* if pcic_change */ 2381 /* 2382 * for any controllers that we can detect whether a socket 2383 * had an interrupt for the PC Card, we should sort that out 2384 * here. 2385 */ 2386 } /* for pc_numsockets */ 2387 2388 /* 2389 * If we're on a PCI bus, we may need to cycle through each IO 2390 * interrupt handler that is registered since they all 2391 * share the same interrupt line. 2392 */ 2393 2394 2395 #if defined(PCIC_DEBUG) 2396 pcic_err(pcic->dip, 0xf, 2397 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2398 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2399 #endif 2400 2401 if (io_ints) { 2402 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED) 2403 ret = DDI_INTR_CLAIMED; 2404 } 2405 2406 mutex_exit(&pcic->intr_lock); 2407 2408 #if defined(PCIC_DEBUG) 2409 pcic_err(pcic->dip, 0xf, 2410 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2411 ret, value, DDI_INTR_CLAIMED); 2412 #endif 2413 2414 return (ret); 2415 } 2416 2417 /* 2418 * pcic_change() 2419 * check to see if this socket had a change in state 2420 * by checking the status change register 2421 */ 2422 static int 2423 pcic_change(pcicdev_t *pcic, int socket) 2424 { 2425 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2426 } 2427 2428 /* 2429 * pcic_do_io_intr - calls client interrupt handlers 2430 */ 2431 static int 2432 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2433 { 2434 inthandler_t *tmp; 2435 int ret = DDI_INTR_UNCLAIMED; 2436 2437 #if defined(PCIC_DEBUG) 2438 pcic_err(pcic->dip, 0xf, 2439 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2440 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2441 #endif 2442 2443 if (pcic->irq_top != NULL) { 2444 tmp = pcic->irq_current; 2445 2446 do { 2447 int cur = pcic->irq_current->socket; 2448 pcic_socket_t *sockp = 2449 &pcic->pc_sockets[cur]; 2450 2451 #if defined(PCIC_DEBUG) 2452 pcic_err(pcic->dip, 0xf, 2453 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2454 sockp->pcs_flags, PCS_CARD_PRESENT); 2455 pcic_err(pcic->dip, 0xf, 2456 "\t sockets=%d cur=%d intr=%p arg1=%p " 2457 "arg2=%p\n", 2458 sockets, cur, (void *)pcic->irq_current->intr, 2459 pcic->irq_current->arg1, 2460 pcic->irq_current->arg2); 2461 #endif 2462 if ((sockp->pcs_flags & PCS_CARD_PRESENT) && 2463 !(sockp->pcs_flags & PCS_DEBOUNCING) && 2464 (sockets & (1 << cur))) { 2465 2466 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2467 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2468 ret = DDI_INTR_CLAIMED; 2469 2470 #if defined(PCIC_DEBUG) 2471 pcic_err(pcic->dip, 0xf, 2472 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2473 ret, DDI_INTR_CLAIMED); 2474 #endif 2475 } 2476 2477 2478 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2479 pcic->irq_current = pcic->irq_top; 2480 2481 } while (pcic->irq_current != tmp); 2482 2483 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2484 pcic->irq_current = pcic->irq_top; 2485 2486 } else { 2487 ret = DDI_INTR_UNCLAIMED; 2488 } 2489 2490 #if defined(PCIC_DEBUG) 2491 pcic_err(pcic->dip, 0xf, 2492 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2493 ret, DDI_INTR_CLAIMED); 2494 #endif 2495 2496 return (ret); 2497 2498 } 2499 2500 /* 2501 * pcic_inquire_adapter() 2502 * SocketServices InquireAdapter function 2503 * get characteristics of the physical adapter 2504 */ 2505 /*ARGSUSED*/ 2506 static int 2507 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2508 { 2509 anp_t *anp = ddi_get_driver_private(dip); 2510 pcicdev_t *pcic = anp->an_private; 2511 2512 config->NumSockets = pcic->pc_numsockets; 2513 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2514 config->NumEDCs = 0; 2515 config->AdpCaps = 0; 2516 config->ActiveHigh = 0; 2517 config->ActiveLow = PCIC_AVAIL_IRQS; 2518 config->NumPower = pcic->pc_numpower; 2519 config->power_entry = pcic->pc_power; /* until we resolve this */ 2520 #if defined(PCIC_DEBUG) 2521 if (pcic_debug) { 2522 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2523 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2524 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2525 } 2526 #endif 2527 config->ResourceFlags = 0; 2528 switch (pcic->pc_intr_mode) { 2529 case PCIC_INTR_MODE_PCI_1: 2530 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2531 RES_IRQ_SHAREABLE; 2532 break; 2533 } 2534 return (SUCCESS); 2535 } 2536 2537 /* 2538 * pcic_callback() 2539 * The PCMCIA nexus calls us via this function 2540 * in order to set the callback function we are 2541 * to call the nexus with 2542 */ 2543 /*ARGSUSED*/ 2544 static int 2545 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2546 { 2547 anp_t *anp = ddi_get_driver_private(dip); 2548 pcicdev_t *pcic = anp->an_private; 2549 2550 if (handler != NULL) { 2551 pcic->pc_callback = handler; 2552 pcic->pc_cb_arg = arg; 2553 pcic->pc_flags |= PCF_CALLBACK; 2554 } else { 2555 pcic->pc_callback = NULL; 2556 pcic->pc_cb_arg = 0; 2557 pcic->pc_flags &= ~PCF_CALLBACK; 2558 } 2559 /* 2560 * we're now registered with the nexus 2561 * it is acceptable to do callbacks at this point. 2562 * don't call back from here though since it could block 2563 */ 2564 return (PC_SUCCESS); 2565 } 2566 2567 /* 2568 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2569 * calculate the speed bits from the specified memory speed 2570 * there may be more to do here 2571 */ 2572 2573 static int 2574 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2575 { 2576 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2577 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2578 2579 switch (pcic->pc_type) { 2580 case PCIC_I82365SL: 2581 case PCIC_VADEM: 2582 case PCIC_VADEM_VG469: 2583 default: 2584 /* Intel chip wants it in waitstates */ 2585 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2586 if (speed <= wspeed) 2587 wspeed = 0; 2588 else if (speed <= (wspeed += mhztons(bspeed))) 2589 wspeed = 1; 2590 else if (speed <= (wspeed += mhztons(bspeed))) 2591 wspeed = 2; 2592 else 2593 wspeed = 3; 2594 wspeed <<= 6; /* put in right bit positions */ 2595 break; 2596 2597 case PCIC_INTEL_i82092: 2598 wspeed = SYSMEM_82092_80NS; 2599 if (speed > 80) 2600 wspeed = SYSMEM_82092_100NS; 2601 if (speed > 100) 2602 wspeed = SYSMEM_82092_150NS; 2603 if (speed > 150) 2604 wspeed = SYSMEM_82092_200NS; 2605 if (speed > 200) 2606 wspeed = SYSMEM_82092_250NS; 2607 if (speed > 250) 2608 wspeed = SYSMEM_82092_600NS; 2609 wspeed <<= 5; /* put in right bit positions */ 2610 break; 2611 2612 } /* switch */ 2613 2614 return (wspeed); 2615 } 2616 2617 /* 2618 * These values are taken from the PC Card Standard Electrical Specification. 2619 * Generally the larger value is taken if 2 are possible. 2620 */ 2621 static struct pcic_card_times { 2622 uint16_t cycle; /* Speed as found in the atribute space of he card. */ 2623 uint16_t setup; /* Corresponding address setup time. */ 2624 uint16_t width; /* Corresponding width, OE or WE. */ 2625 uint16_t hold; /* Corresponding data or address hold time. */ 2626 } pcic_card_times[] = { 2627 2628 /* 2629 * Note: The rounded up times for 250, 200 & 150 have been increased 2630 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2631 * See BugID 00663. 2632 */ 2633 2634 /* 2635 * Rounded up times Original times from 2636 * that add up to the the PCMCIA Spec. 2637 * cycle time. 2638 */ 2639 {600, 180, 370, 140}, /* 100, 300, 70 */ 2640 {400, 120, 300, 90}, /* Made this one up */ 2641 {250, 100, 190, 70}, /* 30, 150, 30 */ 2642 {200, 80, 170, 70}, /* 20, 120, 30 */ 2643 {150, 50, 110, 40}, /* 20, 80, 20 */ 2644 {100, 40, 80, 40}, /* 10, 60, 15 */ 2645 {0, 10, 60, 15} /* 10, 60, 15 */ 2646 }; 2647 2648 /* 2649 * pcic_set_cdtimers 2650 * This is specific to several Cirrus Logic chips 2651 */ 2652 static void 2653 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2654 { 2655 int cmd, set, rec, offset, clk_pulse; 2656 struct pcic_card_times *ctp; 2657 2658 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2659 offset = 3; 2660 else 2661 offset = 0; 2662 2663 clk_pulse = mhztons(pcic->bus_speed); 2664 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++); 2665 2666 /* 2667 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2668 */ 2669 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2670 if (set < 0) 2671 set = 0; 2672 2673 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2674 if (cmd < 0) 2675 cmd = 0; 2676 2677 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2678 if (rec < 0) 2679 rec = 0; 2680 2681 #if defined(PCIC_DEBUG) 2682 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2683 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2684 (unsigned)speed, offset == 3 ? 1 : 0, 2685 ctp->cycle, clk_pulse, cmd, set, rec); 2686 #endif 2687 2688 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2689 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2690 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2691 } 2692 2693 /* 2694 * pcic_set_window 2695 * essentially the same as the Socket Services specification 2696 * We use socket and not adapter since they are identifiable 2697 * but the rest is the same 2698 * 2699 * dip pcic driver's device information 2700 * window parameters for the request 2701 */ 2702 static int 2703 pcic_set_window(dev_info_t *dip, set_window_t *window) 2704 { 2705 anp_t *anp = ddi_get_driver_private(dip); 2706 pcicdev_t *pcic = anp->an_private; 2707 int select; 2708 int socket, pages, which, ret; 2709 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2710 ra_return_t res; 2711 ndi_ra_request_t req; 2712 uint32_t base = window->base; 2713 2714 #if defined(PCIC_DEBUG) 2715 if (pcic_debug) { 2716 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2717 cmn_err(CE_CONT, 2718 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2719 window->window, window->socket, window->WindowSize, 2720 window->speed); 2721 cmn_err(CE_CONT, 2722 "\tbase=%x, state=%x\n", (unsigned)window->base, 2723 (unsigned)window->state); 2724 } 2725 #endif 2726 2727 /* 2728 * do some basic sanity checking on what we support 2729 * we don't do paged mode 2730 */ 2731 if (window->state & WS_PAGED) { 2732 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2733 return (BAD_ATTRIBUTE); 2734 } 2735 2736 /* 2737 * we don't care about previous mappings. 2738 * Card Services will deal with that so don't 2739 * even check 2740 */ 2741 2742 socket = window->socket; 2743 2744 if (!(window->state & WS_IO)) { 2745 int win, tmp; 2746 pcs_memwin_t *memp; 2747 #if defined(PCIC_DEBUG) 2748 if (pcic_debug) 2749 cmn_err(CE_CONT, "\twindow type is memory\n"); 2750 #endif 2751 /* this is memory window mapping */ 2752 win = window->window % PCIC_NUMWINSOCK; 2753 tmp = window->window / PCIC_NUMWINSOCK; 2754 2755 /* only windows 2-6 can do memory mapping */ 2756 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2757 cmn_err(CE_CONT, 2758 "\tattempt to map to non-mem window\n"); 2759 return (BAD_WINDOW); 2760 } 2761 2762 if (window->WindowSize == 0) 2763 window->WindowSize = MEM_MIN; 2764 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2765 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2766 return (BAD_SIZE); 2767 } 2768 2769 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2770 2771 memp = &sockp->pcs_windows[win].mem; 2772 memp->pcw_speed = window->speed; 2773 2774 win -= PCIC_IOWINDOWS; /* put in right range */ 2775 2776 if (window->WindowSize != memp->pcw_len) 2777 which = memp->pcw_len; 2778 else 2779 which = 0; 2780 2781 if (window->state & WS_ENABLED) { 2782 uint32_t wspeed; 2783 #if defined(PCIC_DEBUG) 2784 if (pcic_debug) { 2785 cmn_err(CE_CONT, 2786 "\tbase=%x, win=%d\n", (unsigned)base, 2787 win); 2788 if (which) 2789 cmn_err(CE_CONT, 2790 "\tneed to remap window\n"); 2791 } 2792 #endif 2793 2794 if (which && (memp->pcw_status & PCW_MAPPED)) { 2795 ddi_regs_map_free(&memp->pcw_handle); 2796 res.ra_addr_lo = memp->pcw_base; 2797 res.ra_len = memp->pcw_len; 2798 (void) pcmcia_free_mem(dip, &res); 2799 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2800 memp->pcw_hostmem = NULL; 2801 memp->pcw_base = NULL; 2802 memp->pcw_len = 0; 2803 } 2804 2805 which = window->WindowSize >> PAGE_SHIFT; 2806 2807 if (!(memp->pcw_status & PCW_MAPPED)) { 2808 ret = 0; 2809 2810 memp->pcw_base = base; 2811 bzero(&req, sizeof (req)); 2812 req.ra_len = which << PAGE_SHIFT; 2813 req.ra_addr = (uint64_t)memp->pcw_base; 2814 req.ra_boundbase = pcic->pc_base; 2815 req.ra_boundlen = pcic->pc_bound; 2816 req.ra_flags = (memp->pcw_base ? 2817 NDI_RA_ALLOC_SPECIFIED : 0) | 2818 NDI_RA_ALLOC_BOUNDED; 2819 req.ra_align_mask = 2820 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2821 #if defined(PCIC_DEBUG) 2822 pcic_err(dip, 8, 2823 "\tlen 0x%"PRIx64 2824 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2825 " blen 0x%"PRIx64" flags 0x%x" 2826 " algn 0x%"PRIx64"\n", 2827 req.ra_len, req.ra_addr, 2828 req.ra_boundbase, 2829 req.ra_boundlen, req.ra_flags, 2830 req.ra_align_mask); 2831 #endif 2832 2833 ret = pcmcia_alloc_mem(dip, &req, &res); 2834 if (ret == DDI_FAILURE) { 2835 mutex_exit(&pcic->pc_lock); 2836 cmn_err(CE_WARN, 2837 "\tpcmcia_alloc_mem() failed\n"); 2838 return (BAD_SIZE); 2839 } 2840 memp->pcw_base = res.ra_addr_lo; 2841 base = memp->pcw_base; 2842 2843 #if defined(PCIC_DEBUG) 2844 if (pcic_debug) 2845 cmn_err(CE_CONT, 2846 "\tsetwindow: new base=%x\n", 2847 (unsigned)memp->pcw_base); 2848 #endif 2849 memp->pcw_len = window->WindowSize; 2850 2851 which = pcmcia_map_reg(pcic->dip, 2852 window->child, 2853 &res, 2854 (uint32_t)(window->state & 2855 0xffff) | 2856 (window->socket << 16), 2857 (caddr_t *)&memp->pcw_hostmem, 2858 &memp->pcw_handle, 2859 &window->attr, NULL); 2860 2861 if (which != DDI_SUCCESS) { 2862 2863 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2864 "failed\n"); 2865 2866 res.ra_addr_lo = memp->pcw_base; 2867 res.ra_len = memp->pcw_len; 2868 (void) pcmcia_free_mem(pcic->dip, &res); 2869 2870 mutex_exit(&pcic->pc_lock); 2871 2872 return (BAD_WINDOW); 2873 } 2874 memp->pcw_status |= PCW_MAPPED; 2875 #if defined(PCIC_DEBUG) 2876 if (pcic_debug) 2877 cmn_err(CE_CONT, 2878 "\tmap=%x, hostmem=%p\n", 2879 which, 2880 (void *)memp->pcw_hostmem); 2881 #endif 2882 } else { 2883 base = memp->pcw_base; 2884 } 2885 2886 /* report the handle back to caller */ 2887 window->handle = memp->pcw_handle; 2888 2889 #if defined(PCIC_DEBUG) 2890 if (pcic_debug) { 2891 cmn_err(CE_CONT, 2892 "\twindow mapped to %x@%x len=%d\n", 2893 (unsigned)window->base, 2894 (unsigned)memp->pcw_base, 2895 memp->pcw_len); 2896 } 2897 #endif 2898 2899 /* find the register set offset */ 2900 select = win * PCIC_MEM_1_OFFSET; 2901 #if defined(PCIC_DEBUG) 2902 if (pcic_debug) 2903 cmn_err(CE_CONT, "\tselect=%x\n", select); 2904 #endif 2905 2906 /* 2907 * at this point, the register window indicator has 2908 * been converted to be an offset from the first 2909 * set of registers that are used for programming 2910 * the window mapping and the offset used to select 2911 * the correct set of registers to access the 2912 * specified socket. This allows basing everything 2913 * off the _0 window 2914 */ 2915 2916 /* map the physical page base address */ 2917 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2918 which |= (window->speed <= MEM_SPEED_MIN) ? 2919 SYSMEM_ZERO_WAIT : 0; 2920 2921 /* need to select register set */ 2922 select = PCIC_MEM_1_OFFSET * win; 2923 2924 pcic_putb(pcic, socket, 2925 PCIC_SYSMEM_0_STARTLOW + select, 2926 SYSMEM_LOW(base)); 2927 pcic_putb(pcic, socket, 2928 PCIC_SYSMEM_0_STARTHI + select, 2929 SYSMEM_HIGH(base) | which); 2930 2931 /* 2932 * Some adapters can decode window addresses greater 2933 * than 16-bits worth, so handle them here. 2934 */ 2935 switch (pcic->pc_type) { 2936 case PCIC_INTEL_i82092: 2937 pcic_putb(pcic, socket, 2938 PCIC_82092_CPAGE, 2939 SYSMEM_EXT(base)); 2940 break; 2941 case PCIC_CL_PD6729: 2942 case PCIC_CL_PD6730: 2943 clext_reg_write(pcic, socket, 2944 PCIC_CLEXT_MMAP0_UA + win, 2945 SYSMEM_EXT(base)); 2946 break; 2947 case PCIC_TI_PCI1130: 2948 /* 2949 * Note that the TI chip has one upper byte 2950 * per socket so all windows get bound to a 2951 * 16MB segment. This must be detected and 2952 * handled appropriately. We can detect that 2953 * it is done by seeing if the pc_base has 2954 * changed and changing when the register 2955 * is first set. This will force the bounds 2956 * to be correct. 2957 */ 2958 if (pcic->pc_bound == 0xffffffff) { 2959 pcic_putb(pcic, socket, 2960 PCIC_TI_WINDOW_PAGE_PCI, 2961 SYSMEM_EXT(base)); 2962 pcic->pc_base = SYSMEM_EXT(base) << 24; 2963 pcic->pc_bound = 0x1000000; 2964 } 2965 break; 2966 case PCIC_TI_PCI1031: 2967 case PCIC_TI_PCI1131: 2968 case PCIC_TI_PCI1250: 2969 case PCIC_TI_PCI1225: 2970 case PCIC_TI_PCI1221: 2971 case PCIC_SMC_34C90: 2972 case PCIC_CL_PD6832: 2973 case PCIC_RICOH_RL5C466: 2974 case PCIC_TI_PCI1410: 2975 case PCIC_ENE_1410: 2976 case PCIC_TI_PCI1510: 2977 case PCIC_TI_PCI1520: 2978 case PCIC_O2_OZ6912: 2979 case PCIC_TI_PCI1420: 2980 case PCIC_ENE_1420: 2981 case PCIC_TI_VENDOR: 2982 case PCIC_TOSHIBA_TOPIC100: 2983 case PCIC_TOSHIBA_TOPIC95: 2984 case PCIC_TOSHIBA_VENDOR: 2985 case PCIC_RICOH_VENDOR: 2986 case PCIC_O2MICRO_VENDOR: 2987 pcic_putb(pcic, socket, 2988 PCIC_YENTA_MEM_PAGE + win, 2989 SYSMEM_EXT(base)); 2990 break; 2991 default: 2992 cmn_err(CE_NOTE, "pcic_set_window: unknown " 2993 "cardbus vendor:0x%X\n", 2994 pcic->pc_type); 2995 pcic_putb(pcic, socket, 2996 PCIC_YENTA_MEM_PAGE + win, 2997 SYSMEM_EXT(base)); 2998 2999 break; 3000 } /* switch */ 3001 3002 /* 3003 * specify the length of the mapped range 3004 * we convert to pages (rounding up) so that 3005 * the hardware gets the right thing 3006 */ 3007 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 3008 3009 /* 3010 * Setup this window's timing. 3011 */ 3012 switch (pcic->pc_type) { 3013 case PCIC_CL_PD6729: 3014 case PCIC_CL_PD6730: 3015 case PCIC_CL_PD6710: 3016 case PCIC_CL_PD6722: 3017 wspeed = SYSMEM_CLTIMER_SET_0; 3018 pcic_set_cdtimers(pcic, socket, 3019 window->speed, 3020 wspeed); 3021 break; 3022 3023 case PCIC_INTEL_i82092: 3024 default: 3025 wspeed = pcic_calc_speed(pcic, window->speed); 3026 break; 3027 } /* switch */ 3028 3029 #if defined(PCIC_DEBUG) 3030 if (pcic_debug) 3031 cmn_err(CE_CONT, 3032 "\twindow %d speed bits = %x for " 3033 "%dns\n", 3034 win, (unsigned)wspeed, window->speed); 3035 #endif 3036 3037 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 3038 SYSMEM_LOW(base + 3039 (pages * PCIC_PAGE)-1)); 3040 3041 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 3042 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 3043 wspeed); 3044 3045 /* 3046 * now map the card's memory pages - we start with page 3047 * 0 3048 * we also default to AM -- set page might change it 3049 */ 3050 base = memp->pcw_base; 3051 pcic_putb(pcic, socket, 3052 PCIC_CARDMEM_0_LOW + select, 3053 CARDMEM_LOW(0 - (uint32_t)base)); 3054 3055 pcic_putb(pcic, socket, 3056 PCIC_CARDMEM_0_HI + select, 3057 CARDMEM_HIGH(0 - (uint32_t)base) | 3058 CARDMEM_REG_ACTIVE); 3059 3060 /* 3061 * enable the window even though redundant 3062 * and SetPage may do it again. 3063 */ 3064 select = pcic_getb(pcic, socket, 3065 PCIC_MAPPING_ENABLE); 3066 select |= SYSMEM_WINDOW(win); 3067 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3068 memp->pcw_offset = 0; 3069 memp->pcw_status |= PCW_ENABLED; 3070 } else { 3071 /* 3072 * not only do we unmap the memory, the 3073 * window has been turned off. 3074 */ 3075 if (which && memp->pcw_status & PCW_MAPPED) { 3076 ddi_regs_map_free(&memp->pcw_handle); 3077 res.ra_addr_lo = memp->pcw_base; 3078 res.ra_len = memp->pcw_len; 3079 (void) pcmcia_free_mem(pcic->dip, &res); 3080 memp->pcw_hostmem = NULL; 3081 memp->pcw_status &= ~PCW_MAPPED; 3082 } 3083 3084 /* disable current mapping */ 3085 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3086 select &= ~SYSMEM_WINDOW(win); 3087 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3088 memp->pcw_status &= ~PCW_ENABLED; 3089 } 3090 memp->pcw_len = window->WindowSize; 3091 window->handle = memp->pcw_handle; 3092 #if defined(PCIC_DEBUG) 3093 if (pcic_debug) 3094 xxdmp_all_regs(pcic, window->socket, -1); 3095 #endif 3096 } else { 3097 /* 3098 * This is a request for an IO window 3099 */ 3100 int win, tmp; 3101 pcs_iowin_t *winp; 3102 /* I/O windows */ 3103 #if defined(PCIC_DEBUG) 3104 if (pcic_debug) 3105 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3106 #endif 3107 3108 /* only windows 0 and 1 can do I/O */ 3109 win = window->window % PCIC_NUMWINSOCK; 3110 tmp = window->window / PCIC_NUMWINSOCK; 3111 3112 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3113 cmn_err(CE_WARN, 3114 "\twindow is out of range (%d)\n", 3115 window->window); 3116 return (BAD_WINDOW); 3117 } 3118 3119 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3120 3121 winp = &sockp->pcs_windows[win].io; 3122 winp->pcw_speed = window->speed; 3123 if (window->WindowSize != 1 && window->WindowSize & 1) { 3124 /* we don't want an odd-size window */ 3125 window->WindowSize++; 3126 } 3127 winp->pcw_len = window->WindowSize; 3128 3129 if (window->state & WS_ENABLED) { 3130 if (winp->pcw_status & PCW_MAPPED) { 3131 ddi_regs_map_free(&winp->pcw_handle); 3132 res.ra_addr_lo = winp->pcw_base; 3133 res.ra_len = winp->pcw_len; 3134 (void) pcmcia_free_io(pcic->dip, &res); 3135 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3136 } 3137 3138 /* 3139 * if the I/O address wasn't allocated, allocate 3140 * it now. If it was allocated, it better 3141 * be free to use. 3142 * The winp->pcw_offset value is set and used 3143 * later on if the particular adapter 3144 * that we're running on has the ability 3145 * to translate IO accesses to the card 3146 * (such as some adapters in the Cirrus 3147 * Logic family). 3148 */ 3149 winp->pcw_offset = 0; 3150 3151 /* 3152 * Setup the request parameters for the 3153 * requested base and length. If 3154 * we're on an adapter that has 3155 * IO window offset registers, then 3156 * we don't need a specific base 3157 * address, just a length, and then 3158 * we'll cause the correct IO address 3159 * to be generated on the socket by 3160 * setting up the IO window offset 3161 * registers. 3162 * For adapters that support this capability, we 3163 * always use the IO window offset registers, 3164 * even if the passed base/length would be in 3165 * range. 3166 */ 3167 base = window->base; 3168 bzero(&req, sizeof (req)); 3169 req.ra_len = window->WindowSize; 3170 3171 req.ra_addr = (uint64_t) 3172 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3173 req.ra_flags = (req.ra_addr) ? 3174 NDI_RA_ALLOC_SPECIFIED : 0; 3175 3176 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3177 /* need to rethink this */ 3178 req.ra_boundbase = pcic->pc_iobase; 3179 req.ra_boundlen = pcic->pc_iobound; 3180 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3181 3182 #if defined(PCIC_DEBUG) 3183 pcic_err(dip, 8, 3184 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3185 "bbase 0x%"PRIx64 3186 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3187 PRIx64"\n", 3188 req.ra_len, (uint64_t)req.ra_addr, 3189 req.ra_boundbase, 3190 req.ra_boundlen, req.ra_flags, 3191 req.ra_align_mask); 3192 #endif 3193 3194 /* 3195 * Try to allocate the space. If we fail this, 3196 * return the appropriate error depending 3197 * on whether the caller specified a 3198 * specific base address or not. 3199 */ 3200 if (pcmcia_alloc_io(dip, &req, &res) == DDI_FAILURE) { 3201 winp->pcw_status &= ~PCW_ENABLED; 3202 mutex_exit(&pcic->pc_lock); 3203 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3204 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3205 "bbase 0x%" PRIx64 3206 "blen 0x%" PRIx64 "flags 0x%x" 3207 "algn 0x%" PRIx64 "\n", 3208 req.ra_len, req.ra_addr, 3209 req.ra_boundbase, 3210 req.ra_boundlen, req.ra_flags, 3211 req.ra_align_mask); 3212 3213 return (base?BAD_BASE:BAD_SIZE); 3214 } /* pcmcia_alloc_io */ 3215 3216 /* 3217 * Don't change the original base. Either we use 3218 * the offset registers below (PCF_IO_REMAP is set) 3219 * or it was allocated correctly anyway. 3220 */ 3221 winp->pcw_base = res.ra_addr_lo; 3222 3223 #if defined(PCIC_DEBUG) 3224 pcic_err(dip, 8, 3225 "\tsetwindow: new base=%x orig base 0x%x\n", 3226 (unsigned)winp->pcw_base, base); 3227 #endif 3228 3229 if ((which = pcmcia_map_reg(pcic->dip, 3230 window->child, 3231 &res, 3232 (uint32_t)(window->state & 3233 0xffff) | 3234 (window->socket << 16), 3235 (caddr_t *)&winp->pcw_hostmem, 3236 &winp->pcw_handle, 3237 &window->attr, 3238 base)) != DDI_SUCCESS) { 3239 3240 cmn_err(CE_WARN, "pcmcia_map_reg()" 3241 "failed\n"); 3242 3243 res.ra_addr_lo = winp->pcw_base; 3244 res.ra_len = winp->pcw_len; 3245 (void) pcmcia_free_io(pcic->dip, &res); 3246 3247 mutex_exit(&pcic->pc_lock); 3248 return (BAD_WINDOW); 3249 } 3250 3251 window->handle = winp->pcw_handle; 3252 winp->pcw_status |= PCW_MAPPED; 3253 3254 /* find the register set offset */ 3255 select = win * PCIC_IO_OFFSET; 3256 3257 #if defined(PCIC_DEBUG) 3258 if (pcic_debug) { 3259 cmn_err(CE_CONT, 3260 "\tenable: window=%d, select=%x, " 3261 "base=%x, handle=%p\n", 3262 win, select, 3263 (unsigned)window->base, 3264 (void *)window->handle); 3265 } 3266 #endif 3267 /* 3268 * at this point, the register window indicator has 3269 * been converted to be an offset from the first 3270 * set of registers that are used for programming 3271 * the window mapping and the offset used to select 3272 * the correct set of registers to access the 3273 * specified socket. This allows basing everything 3274 * off the _0 window 3275 */ 3276 3277 /* map the I/O base in */ 3278 pcic_putb(pcic, socket, 3279 PCIC_IO_ADDR_0_STARTLOW + select, 3280 LOW_BYTE((uint32_t)winp->pcw_base)); 3281 pcic_putb(pcic, socket, 3282 PCIC_IO_ADDR_0_STARTHI + select, 3283 HIGH_BYTE((uint32_t)winp->pcw_base)); 3284 3285 pcic_putb(pcic, socket, 3286 PCIC_IO_ADDR_0_STOPLOW + select, 3287 LOW_BYTE((uint32_t)winp->pcw_base + 3288 window->WindowSize - 1)); 3289 pcic_putb(pcic, socket, 3290 PCIC_IO_ADDR_0_STOPHI + select, 3291 HIGH_BYTE((uint32_t)winp->pcw_base + 3292 window->WindowSize - 1)); 3293 3294 /* 3295 * We've got the requested IO space, now see if we 3296 * need to adjust the IO window offset registers 3297 * so that the correct IO address is generated 3298 * at the socket. If this window doesn't have 3299 * this capability, then we're all done setting 3300 * up the IO resources. 3301 */ 3302 if (pcic->pc_flags & PCF_IO_REMAP) { 3303 3304 3305 /* 3306 * Note that only 16 bits are used to program 3307 * the registers but leave 32 bits on pcw_offset 3308 * so that we can generate the original base 3309 * in get_window() 3310 */ 3311 winp->pcw_offset = (base - winp->pcw_base); 3312 3313 pcic_putb(pcic, socket, 3314 PCIC_IO_OFFSET_LOW + 3315 (win * PCIC_IO_OFFSET_OFFSET), 3316 winp->pcw_offset & 0x0ff); 3317 pcic_putb(pcic, socket, 3318 PCIC_IO_OFFSET_HI + 3319 (win * PCIC_IO_OFFSET_OFFSET), 3320 (winp->pcw_offset >> 8) & 0x0ff); 3321 3322 } /* PCF_IO_REMAP */ 3323 3324 /* now get the other details (size, etc) right */ 3325 3326 /* 3327 * Set the data size control bits here. Most of the 3328 * adapters will ignore IOMEM_16BIT when 3329 * IOMEM_IOCS16 is set, except for the Intel 3330 * 82092, which only pays attention to the 3331 * IOMEM_16BIT bit. Sigh... Intel can't even 3332 * make a proper clone of their own chip. 3333 * The 82092 also apparently can't set the timing 3334 * of I/O windows. 3335 */ 3336 which = (window->state & WS_16BIT) ? 3337 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3338 3339 switch (pcic->pc_type) { 3340 case PCIC_CL_PD6729: 3341 case PCIC_CL_PD6730: 3342 case PCIC_CL_PD6710: 3343 case PCIC_CL_PD6722: 3344 case PCIC_CL_PD6832: 3345 /* 3346 * Select Timer Set 1 - this will take 3347 * effect when the PCIC_IO_CONTROL 3348 * register is written to later on; 3349 * the call to pcic_set_cdtimers 3350 * just sets up the timer itself. 3351 */ 3352 which |= IOMEM_CLTIMER_SET_1; 3353 pcic_set_cdtimers(pcic, socket, 3354 window->speed, 3355 IOMEM_CLTIMER_SET_1); 3356 which |= IOMEM_IOCS16; 3357 break; 3358 case PCIC_TI_PCI1031: 3359 3360 if (window->state & WS_16BIT) 3361 which |= IOMEM_WAIT16; 3362 3363 break; 3364 case PCIC_TI_PCI1130: 3365 3366 if (window->state & WS_16BIT) 3367 which |= IOMEM_WAIT16; 3368 3369 break; 3370 case PCIC_INTEL_i82092: 3371 break; 3372 default: 3373 if (window->speed > 3374 mhztons(pcic->bus_speed) * 3) 3375 which |= IOMEM_WAIT16; 3376 #ifdef notdef 3377 if (window->speed < 3378 mhztons(pcic->bus_speed) * 6) 3379 which |= IOMEM_ZERO_WAIT; 3380 #endif 3381 break; 3382 } /* switch (pc_type) */ 3383 3384 /* 3385 * Setup the data width and timing 3386 */ 3387 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3388 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3389 select |= IOMEM_SETWIN(win, which); 3390 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3391 3392 /* 3393 * Enable the IO window 3394 */ 3395 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3396 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3397 select | IOMEM_WINDOW(win)); 3398 3399 winp->pcw_status |= PCW_ENABLED; 3400 3401 #if defined(PCIC_DEBUG) 3402 if (pcic_debug) { 3403 cmn_err(CE_CONT, 3404 "\twhich = %x, select = %x (%x)\n", 3405 which, select, 3406 IOMEM_SETWIN(win, which)); 3407 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3408 } 3409 #endif 3410 } else { 3411 /* 3412 * not only do we unmap the IO space, the 3413 * window has been turned off. 3414 */ 3415 if (winp->pcw_status & PCW_MAPPED) { 3416 ddi_regs_map_free(&winp->pcw_handle); 3417 res.ra_addr_lo = winp->pcw_base; 3418 res.ra_len = winp->pcw_len; 3419 (void) pcmcia_free_io(pcic->dip, &res); 3420 winp->pcw_status &= ~PCW_MAPPED; 3421 } 3422 3423 /* disable current mapping */ 3424 select = pcic_getb(pcic, socket, 3425 PCIC_MAPPING_ENABLE); 3426 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3427 select &= ~IOMEM_WINDOW(win)); 3428 winp->pcw_status &= ~PCW_ENABLED; 3429 3430 winp->pcw_base = 0; 3431 winp->pcw_len = 0; 3432 winp->pcw_offset = 0; 3433 window->base = 0; 3434 /* now make sure we don't accidentally re-enable */ 3435 /* find the register set offset */ 3436 select = win * PCIC_IO_OFFSET; 3437 pcic_putb(pcic, socket, 3438 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3439 pcic_putb(pcic, socket, 3440 PCIC_IO_ADDR_0_STARTHI + select, 0); 3441 pcic_putb(pcic, socket, 3442 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3443 pcic_putb(pcic, socket, 3444 PCIC_IO_ADDR_0_STOPHI + select, 0); 3445 } 3446 } 3447 mutex_exit(&pcic->pc_lock); 3448 3449 return (SUCCESS); 3450 } 3451 3452 /* 3453 * pcic_card_state() 3454 * compute the instantaneous Card State information 3455 */ 3456 static int 3457 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3458 { 3459 int value, result; 3460 #if defined(PCIC_DEBUG) 3461 int orig_value; 3462 #endif 3463 3464 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3465 3466 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3467 3468 #if defined(PCIC_DEBUG) 3469 orig_value = value; 3470 if (pcic_debug >= 8) 3471 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3472 (void *)sockp, 3473 value, 3474 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3475 sockp->pcs_socket); 3476 #endif 3477 /* 3478 * Lie to socket services if we are not ready. 3479 * This is when we are starting up or during debounce timeouts 3480 * or if the card is a cardbus card. 3481 */ 3482 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3483 !sockp->pcs_debounce_id && 3484 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3485 result = SBM_CD; 3486 3487 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3488 result |= SBM_WP; 3489 if (value & PCIC_POWER_ON) { 3490 if (value & PCIC_READY) 3491 result |= SBM_RDYBSY; 3492 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3493 if (value & PCIC_BVD1) 3494 result |= SBM_BVD1; 3495 if (value & PCIC_BVD2) 3496 result |= SBM_BVD2; 3497 } 3498 } else 3499 result = 0; 3500 3501 mutex_exit(&pcic->pc_lock); 3502 3503 #if defined(PCIC_DEBUG) 3504 pcic_err(pcic->dip, 8, 3505 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3506 (void *) sockp, orig_value, 3507 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3508 sockp->pcs_socket, result); 3509 #endif 3510 3511 return (result); 3512 } 3513 3514 /* 3515 * pcic_set_page() 3516 * SocketServices SetPage function 3517 * set the page of PC Card memory that should be in the mapped 3518 * window 3519 */ 3520 /*ARGSUSED*/ 3521 static int 3522 pcic_set_page(dev_info_t *dip, set_page_t *page) 3523 { 3524 anp_t *anp = ddi_get_driver_private(dip); 3525 pcicdev_t *pcic = anp->an_private; 3526 int select; 3527 int which, socket, window; 3528 uint32_t base; 3529 pcs_memwin_t *memp; 3530 3531 /* get real socket/window numbers */ 3532 window = page->window % PCIC_NUMWINSOCK; 3533 socket = page->window / PCIC_NUMWINSOCK; 3534 3535 #if defined(PCIC_DEBUG) 3536 if (pcic_debug) { 3537 cmn_err(CE_CONT, 3538 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3539 window, socket, page->page); 3540 } 3541 #endif 3542 /* only windows 2-6 work on memory */ 3543 if (window < PCIC_IOWINDOWS) 3544 return (BAD_WINDOW); 3545 3546 /* only one page supported (but any size) */ 3547 if (page->page != 0) 3548 return (BAD_PAGE); 3549 3550 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3551 3552 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3553 window -= PCIC_IOWINDOWS; 3554 3555 #if defined(PCIC_DEBUG) 3556 if (pcic_debug) 3557 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3558 (uint32_t)memp->pcw_base, 3559 (void *)memp->pcw_hostmem, memp->pcw_len); 3560 #endif 3561 3562 /* window must be enabled */ 3563 if (!(memp->pcw_status & PCW_ENABLED)) 3564 return (BAD_ATTRIBUTE); 3565 3566 /* find the register set offset */ 3567 select = window * PCIC_MEM_1_OFFSET; 3568 #if defined(PCIC_DEBUG) 3569 if (pcic_debug) 3570 cmn_err(CE_CONT, "\tselect=%x\n", select); 3571 #endif 3572 3573 /* 3574 * now map the card's memory pages - we start with page 0 3575 */ 3576 3577 which = 0; /* assume simple case */ 3578 if (page->state & PS_ATTRIBUTE) { 3579 which |= CARDMEM_REG_ACTIVE; 3580 memp->pcw_status |= PCW_ATTRIBUTE; 3581 } else { 3582 memp->pcw_status &= ~PCW_ATTRIBUTE; 3583 } 3584 3585 /* 3586 * if caller says Write Protect, enforce it. 3587 */ 3588 if (page->state & PS_WP) { 3589 which |= CARDMEM_WRITE_PROTECT; 3590 memp->pcw_status |= PCW_WP; 3591 } else { 3592 memp->pcw_status &= ~PCW_WP; 3593 } 3594 #if defined(PCIC_DEBUG) 3595 if (pcic_debug) { 3596 cmn_err(CE_CONT, "\tmemory type = %s\n", 3597 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3598 if (which & CARDMEM_WRITE_PROTECT) 3599 cmn_err(CE_CONT, "\twrite protect\n"); 3600 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3601 (unsigned)page->offset, 3602 (unsigned)memp->pcw_base, 3603 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3604 } 3605 #endif 3606 /* address computation based on 64MB range and not larger */ 3607 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3608 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3609 CARDMEM_LOW((int)page->offset - (int)base)); 3610 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3611 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3612 CARDMEM_HIGH((int)page->offset - base) | which); 3613 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3614 3615 /* 3616 * while not really necessary, this just makes sure 3617 * nothing turned the window off behind our backs 3618 */ 3619 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3620 which |= SYSMEM_WINDOW(window); 3621 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3622 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3623 3624 memp->pcw_offset = (off_t)page->offset; 3625 3626 #if defined(PCIC_DEBUG) 3627 if (pcic_debug) { 3628 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3629 (void *)memp->pcw_hostmem, 3630 (uint32_t)*memp->pcw_hostmem); 3631 3632 xxdmp_all_regs(pcic, socket, -1); 3633 3634 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3635 (void *)memp->pcw_hostmem, 3636 (uint32_t)*memp->pcw_hostmem); 3637 } 3638 #endif 3639 3640 if (which & PCW_ATTRIBUTE) 3641 pcic_mswait(pcic, socket, 2); 3642 3643 mutex_exit(&pcic->pc_lock); 3644 3645 return (SUCCESS); 3646 } 3647 3648 /* 3649 * pcic_set_vcc_level() 3650 * 3651 * set voltage based on adapter information 3652 * 3653 * this routine implements a limited solution for support of 3.3v cards. 3654 * the general solution, which would fully support the pcmcia spec 3655 * as far as allowing client drivers to request which voltage levels 3656 * to be set, requires more framework support and driver changes - ess 3657 */ 3658 static int 3659 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3660 { 3661 uint32_t socket_present_state; 3662 3663 #if defined(PCIC_DEBUG) 3664 if (pcic_debug) { 3665 cmn_err(CE_CONT, 3666 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3667 (void *)pcic, socket->VccLevel); 3668 } 3669 #endif 3670 3671 /* 3672 * check VccLevel 3673 * if this is zero, power is being turned off 3674 * if it is non-zero, power is being turned on. 3675 */ 3676 if (socket->VccLevel == 0) { 3677 return (0); 3678 } 3679 3680 /* 3681 * range checking for sanity's sake 3682 */ 3683 if (socket->VccLevel >= pcic->pc_numpower) { 3684 return (BAD_VCC); 3685 } 3686 3687 switch (pcic->pc_io_type) { 3688 /* 3689 * Yenta-compliant adapters have vcc info in the extended registers 3690 * Other adapters can be added as needed, but the 'default' case 3691 * has been left as it was previously so as not to break existing 3692 * adapters. 3693 */ 3694 case PCIC_IO_TYPE_YENTA: 3695 /* 3696 * Here we ignore the VccLevel passed in and read the 3697 * card type from the adapter socket present state register 3698 */ 3699 socket_present_state = 3700 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3701 PCIC_PRESENT_STATE_REG)); 3702 #if defined(PCIC_DEBUG) 3703 if (pcic_debug) { 3704 cmn_err(CE_CONT, 3705 "socket present state = 0x%x\n", 3706 socket_present_state); 3707 } 3708 #endif 3709 switch (socket_present_state & PCIC_VCC_MASK) { 3710 case PCIC_VCC_3VCARD: 3711 /* fall through */ 3712 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3713 socket->VccLevel = PCIC_VCC_3VLEVEL; 3714 return 3715 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3716 case PCIC_VCC_5VCARD: 3717 socket->VccLevel = PCIC_VCC_5VLEVEL; 3718 return 3719 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3720 default: 3721 /* 3722 * if no card is present, this can be the 3723 * case of a client making a SetSocket call 3724 * after card removal. In this case we return 3725 * the current power level 3726 */ 3727 return ((unsigned)ddi_get8(pcic->handle, 3728 pcic->ioaddr + CB_R2_OFFSET + 3729 PCIC_POWER_CONTROL)); 3730 } 3731 3732 default: 3733 3734 switch (socket->VccLevel) { 3735 case PCIC_VCC_3VLEVEL: 3736 return (BAD_VCC); 3737 case PCIC_VCC_5VLEVEL: 3738 /* enable Vcc */ 3739 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3740 default: 3741 return (BAD_VCC); 3742 } 3743 } 3744 } 3745 3746 3747 /* 3748 * pcic_set_socket() 3749 * Socket Services SetSocket call 3750 * sets basic socket configuration 3751 */ 3752 static int 3753 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3754 { 3755 anp_t *anp = ddi_get_driver_private(dip); 3756 pcicdev_t *pcic = anp->an_private; 3757 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3758 int irq, interrupt, mirq; 3759 int powerlevel = 0; 3760 int ind, value, orig_pwrctl; 3761 3762 #if defined(PCIC_DEBUG) 3763 if (pcic_debug) { 3764 cmn_err(CE_CONT, 3765 "pcic_set_socket(dip=%p, socket=%d)" 3766 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3767 socket->socket, socket->VccLevel, socket->Vpp1Level, 3768 socket->Vpp2Level); 3769 } 3770 #endif 3771 /* 3772 * check VccLevel, etc. before setting mutex 3773 * if this is zero, power is being turned off 3774 * if it is non-zero, power is being turned on. 3775 * the default case is to assume Vcc only. 3776 */ 3777 3778 /* this appears to be very implementation specific */ 3779 3780 if (socket->Vpp1Level != socket->Vpp2Level) 3781 return (BAD_VPP); 3782 3783 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3784 powerlevel = 0; 3785 sockp->pcs_vcc = 0; 3786 sockp->pcs_vpp1 = 0; 3787 sockp->pcs_vpp2 = 0; 3788 } else { 3789 #if defined(PCIC_DEBUG) 3790 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3791 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3792 #endif 3793 /* valid Vcc power level? */ 3794 if (socket->VccLevel >= pcic->pc_numpower) 3795 return (BAD_VCC); 3796 3797 switch (pcic_power[socket->VccLevel].PowerLevel) { 3798 case 33: /* 3.3V */ 3799 case 60: /* for bad CIS in Option GPRS card */ 3800 if (!(pcic->pc_flags & PCF_33VCAP)) { 3801 cmn_err(CE_WARN, 3802 "%s%d: Bad Request for 3.3V " 3803 "(Controller incapable)\n", 3804 ddi_get_name(pcic->dip), 3805 ddi_get_instance(pcic->dip)); 3806 return (BAD_VCC); 3807 } 3808 /* FALLTHROUGH */ 3809 case 50: /* 5V */ 3810 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3811 pcic_getcb(pcic, CB_PRESENT_STATE) & 3812 CB_PS_33VCARD) { 3813 /* 3814 * This is actually a 3.3V card. 3815 * Solaris Card Services 3816 * doesn't understand 3.3V 3817 * so we cheat and change 3818 * the setting to the one appropriate to 3.3V. 3819 * Note that this is the entry number 3820 * in the pcic_power[] array. 3821 */ 3822 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3823 } else 3824 sockp->pcs_vcc = socket->VccLevel; 3825 break; 3826 default: 3827 return (BAD_VCC); 3828 } 3829 3830 /* enable Vcc */ 3831 powerlevel = POWER_CARD_ENABLE; 3832 3833 #if defined(PCIC_DEBUG) 3834 if (pcic_debug) { 3835 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3836 socket->VccLevel, powerlevel); 3837 } 3838 #endif 3839 ind = 0; /* default index to 0 power */ 3840 if ((int)socket->Vpp1Level >= 0 && 3841 socket->Vpp1Level < pcic->pc_numpower) { 3842 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3843 & VPP1)) { 3844 return (BAD_VPP); 3845 } 3846 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3847 powerlevel |= pcic_vpp_levels[ind]; 3848 sockp->pcs_vpp1 = socket->Vpp1Level; 3849 } 3850 if ((int)socket->Vpp2Level >= 0 && 3851 socket->Vpp2Level < pcic->pc_numpower) { 3852 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3853 & VPP2)) { 3854 return (BAD_VPP); 3855 } 3856 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3857 powerlevel |= (pcic_vpp_levels[ind] << 2); 3858 sockp->pcs_vpp2 = socket->Vpp2Level; 3859 } 3860 3861 if (pcic->pc_flags & PCF_VPPX) { 3862 /* 3863 * this adapter doesn't allow separate Vpp1/Vpp2 3864 * if one is turned on, both are turned on and only 3865 * the Vpp1 bits should be set 3866 */ 3867 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3868 /* must be the same if one not zero */ 3869 if (sockp->pcs_vpp1 != 0 && 3870 sockp->pcs_vpp2 != 0) { 3871 cmn_err(CE_WARN, 3872 "%s%d: Bad Power Request " 3873 "(Vpp1/2 not the same)\n", 3874 ddi_get_name(pcic->dip), 3875 ddi_get_instance(pcic->dip)); 3876 return (BAD_VPP); 3877 } 3878 } 3879 powerlevel &= ~(3<<2); 3880 } 3881 3882 #if defined(PCIC_DEBUG) 3883 if (pcic_debug) { 3884 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3885 powerlevel, ind); 3886 } 3887 #endif 3888 } 3889 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3890 3891 /* turn socket->IREQRouting off while programming */ 3892 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3893 interrupt &= ~PCIC_INTR_MASK; 3894 if (pcic->pc_flags & PCF_USE_SMI) 3895 interrupt |= PCIC_INTR_ENABLE; 3896 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3897 3898 switch (pcic->pc_type) { 3899 case PCIC_INTEL_i82092: 3900 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3901 PCIC_82092_INT_DISABLE); 3902 break; 3903 default: 3904 break; 3905 } /* switch */ 3906 3907 /* the SCIntMask specifies events to detect */ 3908 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3909 3910 #if defined(PCIC_DEBUG) 3911 if (pcic_debug) 3912 cmn_err(CE_CONT, 3913 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3914 socket->SCIntMask, interrupt, mirq); 3915 #endif 3916 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3917 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3918 mirq & ~PCIC_CHANGE_MASK); 3919 3920 /* save the mask we want to use */ 3921 sockp->pcs_intmask = socket->SCIntMask; 3922 3923 /* 3924 * Until there is a card present it's not worth enabling 3925 * any interrupts except "Card detect". This is done 3926 * elsewhere in the driver so don't change things if 3927 * there is no card! 3928 */ 3929 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3930 3931 /* now update the hardware to reflect events desired */ 3932 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3933 mirq |= PCIC_BD_DETECT; 3934 3935 if (sockp->pcs_intmask & SBM_BVD2) 3936 mirq |= PCIC_BW_DETECT; 3937 3938 if (sockp->pcs_intmask & SBM_RDYBSY) 3939 mirq |= PCIC_RD_DETECT; 3940 3941 if (sockp->pcs_intmask & SBM_CD) 3942 mirq |= PCIC_CD_DETECT; 3943 } 3944 3945 if (sockp->pcs_flags & PCS_READY) { 3946 /* 3947 * card just came ready. 3948 * make sure enough time elapses 3949 * before touching it. 3950 */ 3951 sockp->pcs_flags &= ~PCS_READY; 3952 pcic_mswait(pcic, socket->socket, 10); 3953 } 3954 3955 #if defined(PCIC_DEBUG) 3956 if (pcic_debug) { 3957 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3958 } 3959 #endif 3960 3961 switch (pcic->pc_type) { 3962 case PCIC_I82365SL: 3963 case PCIC_VADEM: 3964 case PCIC_VADEM_VG469: 3965 /* 3966 * The Intel version has different options. This is a 3967 * special case of GPI which might be used for eject 3968 */ 3969 3970 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 3971 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 3972 pcic->pc_flags & PCF_GPI_EJECT) { 3973 irq |= PCIC_GPI_ENABLE; 3974 } else { 3975 irq &= ~PCIC_GPI_ENABLE; 3976 } 3977 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 3978 break; 3979 case PCIC_CL_PD6710: 3980 case PCIC_CL_PD6722: 3981 if (socket->IFType == IF_IO) { 3982 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 3983 value = pcic_getb(pcic, socket->socket, 3984 PCIC_MISC_CTL_1); 3985 if (pcic->pc_flags & PCF_AUDIO) 3986 value |= PCIC_MC_SPEAKER_ENB; 3987 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3988 value); 3989 } else { 3990 value = pcic_getb(pcic, socket->socket, 3991 PCIC_MISC_CTL_1); 3992 value &= ~PCIC_MC_SPEAKER_ENB; 3993 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 3994 value); 3995 } 3996 break; 3997 case PCIC_CL_PD6729: 3998 case PCIC_CL_PD6730: 3999 case PCIC_CL_PD6832: 4000 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 4001 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4002 value |= PCIC_MC_SPEAKER_ENB; 4003 } else { 4004 value &= ~PCIC_MC_SPEAKER_ENB; 4005 } 4006 4007 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4008 value |= PCIC_MC_3VCC; 4009 else 4010 value &= ~PCIC_MC_3VCC; 4011 4012 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 4013 break; 4014 4015 case PCIC_O2_OZ6912: 4016 value = pcic_getcb(pcic, CB_MISCCTRL); 4017 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 4018 value |= (1<<25); 4019 else 4020 value &= ~(1<<25); 4021 pcic_putcb(pcic, CB_MISCCTRL, value); 4022 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4023 powerlevel |= 0x08; 4024 break; 4025 4026 case PCIC_TI_PCI1250: 4027 case PCIC_TI_PCI1221: 4028 case PCIC_TI_PCI1225: 4029 case PCIC_TI_PCI1410: 4030 case PCIC_ENE_1410: 4031 case PCIC_TI_PCI1510: 4032 case PCIC_TI_PCI1520: 4033 case PCIC_TI_PCI1420: 4034 case PCIC_ENE_1420: 4035 value = ddi_get8(pcic->cfg_handle, 4036 pcic->cfgaddr + PCIC_CRDCTL_REG); 4037 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4038 value |= PCIC_CRDCTL_SPKR_ENBL; 4039 } else { 4040 value &= ~PCIC_CRDCTL_SPKR_ENBL; 4041 } 4042 ddi_put8(pcic->cfg_handle, 4043 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 4044 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4045 powerlevel |= 0x08; 4046 break; 4047 } 4048 4049 /* 4050 * ctlind processing -- we can ignore this 4051 * there aren't any outputs on the chip for this and 4052 * the GUI will display what it thinks is correct 4053 */ 4054 4055 /* 4056 * If outputs are enabled and the power is going off 4057 * turn off outputs first. 4058 */ 4059 4060 /* power setup -- if necessary */ 4061 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4062 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 4063 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4064 pcic_putb(pcic, socket->socket, 4065 PCIC_POWER_CONTROL, orig_pwrctl); 4066 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4067 } 4068 4069 if (pcic->pc_flags & PCF_CBPWRCTL) { 4070 value = pcic_cbus_powerctl(pcic, socket->socket); 4071 powerlevel = 0; 4072 } else 4073 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4074 4075 if (value != SUCCESS) { 4076 mutex_exit(&pcic->pc_lock); 4077 return (value); 4078 } 4079 4080 /* 4081 * If outputs were disabled and the power is going on 4082 * turn on outputs afterwards. 4083 */ 4084 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4085 orig_pwrctl = pcic_getb(pcic, socket->socket, 4086 PCIC_POWER_CONTROL); 4087 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4088 pcic_putb(pcic, socket->socket, 4089 PCIC_POWER_CONTROL, orig_pwrctl); 4090 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4091 } 4092 4093 /* 4094 * Once we have done the power stuff can re-enable management 4095 * interrupts. 4096 */ 4097 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4098 4099 #if defined(PCIC_DEBUG) 4100 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4101 "cbctl 0x%x\n", 4102 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4103 pcic_getcb(pcic, CB_CONTROL)); 4104 #endif 4105 4106 /* irq processing */ 4107 if (socket->IFType == IF_IO) { 4108 /* IRQ only for I/O */ 4109 irq = socket->IREQRouting & PCIC_INTR_MASK; 4110 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4111 value &= ~PCIC_INTR_MASK; 4112 4113 /* to enable I/O operation */ 4114 value |= PCIC_IO_CARD | PCIC_RESET; 4115 sockp->pcs_flags |= PCS_CARD_IO; 4116 if (irq != sockp->pcs_irq) { 4117 if (sockp->pcs_irq != 0) 4118 cmn_err(CE_CONT, 4119 "SetSocket: IRQ mismatch %x != %x!\n", 4120 irq, sockp->pcs_irq); 4121 else 4122 sockp->pcs_irq = irq; 4123 } 4124 irq = sockp->pcs_irq; 4125 4126 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4127 if (socket->IREQRouting & IRQ_ENABLE) { 4128 pcic_enable_io_intr(pcic, socket->socket, irq); 4129 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4130 } else { 4131 pcic_disable_io_intr(pcic, socket->socket); 4132 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4133 } 4134 #if defined(PCIC_DEBUG) 4135 if (pcic_debug) { 4136 cmn_err(CE_CONT, 4137 "\tsocket type is I/O and irq %x is %s\n", irq, 4138 (socket->IREQRouting & IRQ_ENABLE) ? 4139 "enabled" : "not enabled"); 4140 xxdmp_all_regs(pcic, socket->socket, 20); 4141 } 4142 #endif 4143 } else { 4144 /* make sure I/O mode is off */ 4145 4146 sockp->pcs_irq = 0; 4147 4148 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4149 value &= ~PCIC_IO_CARD; 4150 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4151 pcic_disable_io_intr(pcic, socket->socket); 4152 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4153 } 4154 4155 sockp->pcs_state &= ~socket->State; 4156 4157 mutex_exit(&pcic->pc_lock); 4158 return (SUCCESS); 4159 } 4160 4161 /* 4162 * pcic_inquire_socket() 4163 * SocketServices InquireSocket function 4164 * returns basic characteristics of the socket 4165 */ 4166 /*ARGSUSED*/ 4167 static int 4168 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4169 { 4170 anp_t *anp = ddi_get_driver_private(dip); 4171 pcicdev_t *pcic = anp->an_private; 4172 int value; 4173 4174 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4175 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4176 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4177 value = pcic->pc_sockets[socket->socket].pcs_flags; 4178 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4179 socket->ActiveHigh = 0; 4180 /* these are the usable IRQs */ 4181 socket->ActiveLow = 0xfff0; 4182 return (SUCCESS); 4183 } 4184 4185 /* 4186 * pcic_inquire_window() 4187 * SocketServices InquireWindow function 4188 * returns detailed characteristics of the window 4189 * this is where windows get tied to sockets 4190 */ 4191 /*ARGSUSED*/ 4192 static int 4193 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4194 { 4195 int type, socket; 4196 4197 type = window->window % PCIC_NUMWINSOCK; 4198 socket = window->window / PCIC_NUMWINSOCK; 4199 4200 #if defined(PCIC_DEBUG) 4201 if (pcic_debug >= 8) 4202 cmn_err(CE_CONT, 4203 "pcic_inquire_window: window = %d/%d socket=%d\n", 4204 window->window, type, socket); 4205 #endif 4206 if (type < PCIC_IOWINDOWS) { 4207 window->WndCaps = WC_IO|WC_WAIT; 4208 type = IF_IO; 4209 } else { 4210 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4211 type = IF_MEMORY; 4212 } 4213 4214 /* initialize the socket map - one socket per window */ 4215 PR_ZERO(window->Sockets); 4216 PR_SET(window->Sockets, socket); 4217 4218 if (type == IF_IO) { 4219 iowin_char_t *io; 4220 io = &window->iowin_char; 4221 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4222 WC_16BIT; 4223 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4224 io->LastByte = (baseaddr_t)IOMEM_LAST; 4225 io->MinSize = IOMEM_MIN; 4226 io->MaxSize = IOMEM_MAX; 4227 io->ReqGran = IOMEM_GRAN; 4228 io->AddrLines = IOMEM_DECODE; 4229 io->EISASlot = 0; 4230 } else { 4231 mem_win_char_t *mem; 4232 mem = &window->mem_win_char; 4233 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4234 WC_16BIT|WC_WP; 4235 4236 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4237 mem->LastByte = (baseaddr_t)MEM_LAST; 4238 4239 mem->MinSize = MEM_MIN; 4240 mem->MaxSize = MEM_MAX; 4241 mem->ReqGran = PCIC_PAGE; 4242 mem->ReqBase = 0; 4243 mem->ReqOffset = PCIC_PAGE; 4244 mem->Slowest = MEM_SPEED_MAX; 4245 mem->Fastest = MEM_SPEED_MIN; 4246 } 4247 return (SUCCESS); 4248 } 4249 4250 /* 4251 * pcic_get_adapter() 4252 * SocketServices GetAdapter function 4253 * this is nearly a no-op. 4254 */ 4255 /*ARGSUSED*/ 4256 static int 4257 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4258 { 4259 anp_t *anp = ddi_get_driver_private(dip); 4260 pcicdev_t *pcic = anp->an_private; 4261 4262 if (pcic->pc_flags & PCF_INTRENAB) 4263 adapt->SCRouting = IRQ_ENABLE; 4264 adapt->state = 0; 4265 return (SUCCESS); 4266 } 4267 4268 /* 4269 * pcic_get_page() 4270 * SocketServices GetPage function 4271 * returns info about the window 4272 */ 4273 /*ARGSUSED*/ 4274 static int 4275 pcic_get_page(dev_info_t *dip, get_page_t *page) 4276 { 4277 anp_t *anp = ddi_get_driver_private(dip); 4278 pcicdev_t *pcic = anp->an_private; 4279 int socket, window; 4280 pcs_memwin_t *winp; 4281 4282 socket = page->window / PCIC_NUMWINSOCK; 4283 window = page->window % PCIC_NUMWINSOCK; 4284 4285 /* I/O windows are the first two */ 4286 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4287 return (BAD_WINDOW); 4288 } 4289 4290 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4291 4292 if (page->page != 0) 4293 return (BAD_PAGE); 4294 4295 page->state = 0; 4296 if (winp->pcw_status & PCW_ENABLED) 4297 page->state |= PS_ENABLED; 4298 if (winp->pcw_status & PCW_ATTRIBUTE) 4299 page->state |= PS_ATTRIBUTE; 4300 if (winp->pcw_status & PCW_WP) 4301 page->state |= PS_WP; 4302 4303 page->offset = (off_t)winp->pcw_offset; 4304 4305 return (SUCCESS); 4306 } 4307 4308 /* 4309 * pcic_get_socket() 4310 * SocketServices GetSocket 4311 * returns information about the current socket setting 4312 */ 4313 /*ARGSUSED*/ 4314 static int 4315 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4316 { 4317 anp_t *anp = ddi_get_driver_private(dip); 4318 pcicdev_t *pcic = anp->an_private; 4319 int socknum, irq_enabled; 4320 pcic_socket_t *sockp; 4321 4322 socknum = socket->socket; 4323 sockp = &pcic->pc_sockets[socknum]; 4324 4325 socket->SCIntMask = sockp->pcs_intmask; 4326 sockp->pcs_state = pcic_card_state(pcic, sockp); 4327 4328 socket->state = sockp->pcs_state; 4329 if (socket->state & SBM_CD) { 4330 socket->VccLevel = sockp->pcs_vcc; 4331 socket->Vpp1Level = sockp->pcs_vpp1; 4332 socket->Vpp2Level = sockp->pcs_vpp2; 4333 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4334 IRQ_ENABLE : 0; 4335 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4336 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4337 IF_IO : IF_MEMORY; 4338 } else { 4339 socket->VccLevel = 0; 4340 socket->Vpp1Level = 0; 4341 socket->Vpp2Level = 0; 4342 socket->IRQRouting = 0; 4343 socket->IFType = IF_MEMORY; 4344 } 4345 socket->CtlInd = 0; /* no indicators */ 4346 4347 return (SUCCESS); 4348 } 4349 4350 /* 4351 * pcic_get_status() 4352 * SocketServices GetStatus 4353 * returns status information about the PC Card in 4354 * the selected socket 4355 */ 4356 /*ARGSUSED*/ 4357 static int 4358 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4359 { 4360 anp_t *anp = ddi_get_driver_private(dip); 4361 pcicdev_t *pcic = anp->an_private; 4362 int socknum, irq_enabled; 4363 pcic_socket_t *sockp; 4364 4365 socknum = status->socket; 4366 sockp = &pcic->pc_sockets[socknum]; 4367 4368 status->CardState = pcic_card_state(pcic, sockp); 4369 status->SocketState = sockp->pcs_state; 4370 status->CtlInd = 0; /* no indicators */ 4371 4372 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4373 status->SocketState |= SBM_CD; 4374 if (status->CardState & SBM_CD) { 4375 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4376 IRQ_ENABLE : 0; 4377 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4378 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4379 IF_IO : IF_MEMORY; 4380 } else { 4381 status->IRQRouting = 0; 4382 status->IFType = IF_MEMORY; 4383 } 4384 4385 #if defined(PCIC_DEBUG) 4386 if (pcic_debug >= 8) 4387 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4388 "SocketState=%x\n", 4389 socknum, status->CardState, status->SocketState); 4390 #endif 4391 switch (pcic->pc_type) { 4392 uint32_t present_state; 4393 case PCIC_TI_PCI1410: 4394 case PCIC_TI_PCI1520: 4395 case PCIC_TI_PCI1420: 4396 case PCIC_ENE_1420: 4397 case PCIC_TOSHIBA_TOPIC100: 4398 case PCIC_TOSHIBA_TOPIC95: 4399 case PCIC_TOSHIBA_VENDOR: 4400 case PCIC_O2MICRO_VENDOR: 4401 case PCIC_TI_VENDOR: 4402 case PCIC_RICOH_VENDOR: 4403 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4404 if (present_state & PCIC_CB_CARD) 4405 status->IFType = IF_CARDBUS; 4406 #if defined(PCIC_DEBUG) 4407 if (pcic_debug >= 8) 4408 cmn_err(CE_CONT, "pcic_get_status: present_state=0x%x\n", 4409 present_state); 4410 #endif 4411 break; 4412 default: 4413 break; 4414 } 4415 4416 return (SUCCESS); 4417 } 4418 4419 /* 4420 * pcic_get_window() 4421 * SocketServices GetWindow function 4422 * returns state information about the specified window 4423 */ 4424 /*ARGSUSED*/ 4425 static int 4426 pcic_get_window(dev_info_t *dip, get_window_t *window) 4427 { 4428 anp_t *anp = ddi_get_driver_private(dip); 4429 pcicdev_t *pcic = anp->an_private; 4430 int socket, win; 4431 pcic_socket_t *sockp; 4432 pcs_memwin_t *winp; 4433 4434 socket = window->window / PCIC_NUMWINSOCK; 4435 win = window->window % PCIC_NUMWINSOCK; 4436 #if defined(PCIC_DEBUG) 4437 if (pcic_debug) { 4438 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4439 socket, win); 4440 } 4441 #endif 4442 4443 if (socket > pcic->pc_numsockets) 4444 return (BAD_WINDOW); 4445 4446 sockp = &pcic->pc_sockets[socket]; 4447 winp = &sockp->pcs_windows[win].mem; 4448 4449 window->socket = socket; 4450 window->size = winp->pcw_len; 4451 window->speed = winp->pcw_speed; 4452 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4453 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4454 4455 if (win >= PCIC_IOWINDOWS) { 4456 window->state = 0; 4457 } else { 4458 window->state = WS_IO; 4459 } 4460 if (winp->pcw_status & PCW_ENABLED) 4461 window->state |= WS_ENABLED; 4462 4463 if (winp->pcw_status & PCS_CARD_16BIT) 4464 window->state |= WS_16BIT; 4465 #if defined(PCIC_DEBUG) 4466 if (pcic_debug) 4467 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4468 window->size, (unsigned)window->speed, 4469 (void *)window->handle, window->state); 4470 #endif 4471 4472 return (SUCCESS); 4473 } 4474 4475 /* 4476 * pcic_ll_reset 4477 * low level reset 4478 * separated out so it can be called when already locked 4479 * 4480 * There are two variables that control the RESET timing: 4481 * pcic_prereset_time - time in mS before asserting RESET 4482 * pcic_reset_time - time in mS to assert RESET 4483 * 4484 */ 4485 int pcic_prereset_time = 1; 4486 int pcic_reset_time = 10; 4487 int pcic_postreset_time = 20; 4488 int pcic_vpp_is_vcc_during_reset = 0; 4489 4490 static int 4491 pcic_ll_reset(pcicdev_t *pcic, int socket) 4492 { 4493 int windowbits, iobits; 4494 uint32_t pwr; 4495 4496 /* save windows that were on */ 4497 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4498 if (pcic_reset_time == 0) 4499 return (windowbits); 4500 /* turn all windows off */ 4501 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4502 4503 #if defined(PCIC_DEBUG) 4504 pcic_err(pcic->dip, 6, 4505 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4506 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4507 pcic_getcb(pcic, CB_CONTROL), 4508 pcic_getcb(pcic, CB_PRESENT_STATE)); 4509 #endif 4510 4511 if (pcic_vpp_is_vcc_during_reset) { 4512 4513 /* 4514 * Set VPP to VCC for the duration of the reset - for aironet 4515 * card. 4516 */ 4517 if (pcic->pc_flags & PCF_CBPWRCTL) { 4518 pwr = pcic_getcb(pcic, CB_CONTROL); 4519 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4520 (void) pcic_getcb(pcic, CB_CONTROL); 4521 } else { 4522 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4523 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4524 pwr | 1); 4525 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4526 } 4527 } 4528 4529 if (pcic_prereset_time > 0) { 4530 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4531 pcic_prereset_time); 4532 pcic_mswait(pcic, socket, pcic_prereset_time); 4533 } 4534 4535 /* turn interrupts off and start a reset */ 4536 pcic_err(pcic->dip, 8, 4537 "pcic_ll_reset turn interrupts off and start a reset\n"); 4538 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4539 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4540 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4541 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4542 4543 switch (pcic->pc_type) { 4544 case PCIC_INTEL_i82092: 4545 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4546 PCIC_82092_INT_DISABLE); 4547 break; 4548 default: 4549 break; 4550 } /* switch */ 4551 4552 pcic->pc_sockets[socket].pcs_state = 0; 4553 4554 if (pcic_reset_time > 0) { 4555 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4556 pcic_reset_time); 4557 pcic_mswait(pcic, socket, pcic_reset_time); 4558 } 4559 4560 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4561 4562 /* take it out of RESET now */ 4563 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4564 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4565 4566 /* 4567 * can't access the card for 20ms, but we really don't 4568 * want to sit around that long. The pcic is still usable. 4569 * memory accesses must wait for RDY to come up. 4570 */ 4571 if (pcic_postreset_time > 0) { 4572 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4573 pcic_postreset_time); 4574 pcic_mswait(pcic, socket, pcic_postreset_time); 4575 } 4576 4577 if (pcic_vpp_is_vcc_during_reset > 1) { 4578 4579 /* 4580 * Return VPP power to whatever it was before. 4581 */ 4582 if (pcic->pc_flags & PCF_CBPWRCTL) { 4583 pcic_putcb(pcic, CB_CONTROL, pwr); 4584 (void) pcic_getcb(pcic, CB_CONTROL); 4585 } else { 4586 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4587 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4588 } 4589 } 4590 4591 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4592 4593 return (windowbits); 4594 } 4595 4596 /* 4597 * pcic_reset_socket() 4598 * SocketServices ResetSocket function 4599 * puts the PC Card in the socket into the RESET state 4600 * and then takes it out after the the cycle time 4601 * The socket is back to initial state when done 4602 */ 4603 static int 4604 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4605 { 4606 anp_t *anp = ddi_get_driver_private(dip); 4607 pcicdev_t *pcic = anp->an_private; 4608 int value; 4609 int i, mint; 4610 pcic_socket_t *sockp; 4611 4612 #if defined(PCIC_DEBUG) 4613 if (pcic_debug >= 8) 4614 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4615 (void *)dip, socket, mode, 4616 mode == RESET_MODE_FULL ? "full" : "partial"); 4617 #endif 4618 4619 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4620 4621 /* Turn off management interupts. */ 4622 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4623 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4624 4625 sockp = &pcic->pc_sockets[socket]; 4626 4627 value = pcic_ll_reset(pcic, socket); 4628 if (mode == RESET_MODE_FULL) { 4629 /* disable and unmap all mapped windows */ 4630 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4631 if (i < PCIC_IOWINDOWS) { 4632 if (sockp->pcs_windows[i].io.pcw_status & 4633 PCW_MAPPED) { 4634 pcs_iowin_t *io; 4635 io = &sockp->pcs_windows[i].io; 4636 io->pcw_status &= ~PCW_ENABLED; 4637 } 4638 } else { 4639 if (sockp->pcs_windows[i].mem.pcw_status & 4640 PCW_MAPPED) { 4641 pcs_memwin_t *mem; 4642 mem = &sockp->pcs_windows[i].mem; 4643 mem->pcw_status &= ~PCW_ENABLED; 4644 } 4645 } 4646 } 4647 } else { 4648 /* turn windows back on */ 4649 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4650 /* wait the rest of the time here */ 4651 pcic_mswait(pcic, socket, 10); 4652 } 4653 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4654 mutex_exit(&pcic->pc_lock); 4655 return (SUCCESS); 4656 } 4657 4658 /* 4659 * pcic_set_interrupt() 4660 * SocketServices SetInterrupt function 4661 */ 4662 static int 4663 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4664 { 4665 anp_t *anp = ddi_get_driver_private(dip); 4666 pcicdev_t *pcic = anp->an_private; 4667 int value = DDI_SUCCESS; 4668 inthandler_t *intr; 4669 4670 #if defined(PCIC_DEBUG) 4671 if (pcic_debug) { 4672 cmn_err(CE_CONT, 4673 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4674 pcic->pc_intr_mode); 4675 cmn_err(CE_CONT, 4676 "\t irq_top=%p handler=%p handler_id=%x\n", 4677 (void *)pcic->irq_top, (void *)handler->handler, 4678 handler->handler_id); 4679 } 4680 #endif 4681 4682 /* 4683 * If we're on a PCI bus, we route all IO IRQs through a single 4684 * PCI interrupt (typically INT A#) so we don't have to do 4685 * much other than add the caller to general interrupt handler 4686 * and set some state. 4687 */ 4688 4689 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4690 if (intr == NULL) 4691 return (NO_RESOURCE); 4692 4693 switch (pcic->pc_intr_mode) { 4694 case PCIC_INTR_MODE_PCI_1: 4695 /* 4696 * We only allow above-lock-level IO IRQ handlers 4697 * in the PCI bus case. 4698 */ 4699 4700 mutex_enter(&pcic->intr_lock); 4701 4702 if (pcic->irq_top == NULL) { 4703 pcic->irq_top = intr; 4704 pcic->irq_current = pcic->irq_top; 4705 } else { 4706 while (pcic->irq_current->next != NULL) 4707 pcic->irq_current = pcic->irq_current->next; 4708 pcic->irq_current->next = intr; 4709 pcic->irq_current = pcic->irq_current->next; 4710 } 4711 4712 pcic->irq_current->intr = 4713 (ddi_intr_handler_t *)handler->handler; 4714 pcic->irq_current->handler_id = handler->handler_id; 4715 pcic->irq_current->arg1 = handler->arg1; 4716 pcic->irq_current->arg2 = handler->arg2; 4717 pcic->irq_current->socket = handler->socket; 4718 4719 mutex_exit(&pcic->intr_lock); 4720 4721 handler->iblk_cookie = &pcic->pc_pri; 4722 handler->idev_cookie = &pcic->pc_dcookie; 4723 break; 4724 4725 default: 4726 intr->intr = (ddi_intr_handler_t *)handler->handler; 4727 intr->handler_id = handler->handler_id; 4728 intr->arg1 = handler->arg1; 4729 intr->arg2 = handler->arg2; 4730 intr->socket = handler->socket; 4731 intr->irq = handler->irq; 4732 4733 /* 4734 * need to revisit this to see if interrupts can be 4735 * shared someday. Note that IRQ is set in the common 4736 * code. 4737 */ 4738 mutex_enter(&pcic->pc_lock); 4739 if (pcic->pc_handlers == NULL) { 4740 pcic->pc_handlers = intr; 4741 intr->next = intr->prev = intr; 4742 } else { 4743 insque(intr, pcic->pc_handlers); 4744 } 4745 mutex_exit(&pcic->pc_lock); 4746 4747 break; 4748 } 4749 4750 /* 4751 * need to fill in cookies in event of multiple high priority 4752 * interrupt handlers on same IRQ 4753 */ 4754 4755 #if defined(PCIC_DEBUG) 4756 if (pcic_debug) { 4757 cmn_err(CE_CONT, 4758 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4759 (void *)pcic->irq_top, value); 4760 } 4761 #endif 4762 4763 if (value == DDI_SUCCESS) { 4764 return (SUCCESS); 4765 } else { 4766 return (BAD_IRQ); 4767 } 4768 } 4769 4770 /* 4771 * pcic_clear_interrupt() 4772 * SocketServices ClearInterrupt function 4773 * 4774 * Interrupts for PCIC are complicated by the fact that we must 4775 * follow several different models for interrupts. 4776 * ISA: there is an interrupt per adapter and per socket and 4777 * they can't be shared. 4778 * PCI: some adapters have one PCI interrupt available while others 4779 * have up to 4. Solaris may or may not allow us to use more 4780 * than 1 so we essentially share them all at this point. 4781 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4782 * This is like ISA but we have to fudge and create an intrspec 4783 * that PCI's parent understands and bypass the PCI nexus. 4784 * multifunction: this requires sharing the interrupts on a per-socket 4785 * basis. 4786 */ 4787 static int 4788 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4789 { 4790 anp_t *anp = ddi_get_driver_private(dip); 4791 pcicdev_t *pcic = anp->an_private; 4792 inthandler_t *intr, *prev, *current; 4793 int i; 4794 4795 /* 4796 * If we're on a PCI bus, we route all IO IRQs through a single 4797 * PCI interrupt (typically INT A#) so we don't have to do 4798 * much other than remove the caller from the general 4799 * interrupt handler callout list. 4800 */ 4801 4802 #if defined(PCIC_DEBUG) 4803 if (pcic_debug) { 4804 cmn_err(CE_CONT, 4805 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4806 pcic->pc_intr_mode); 4807 cmn_err(CE_CONT, 4808 "\t irq_top=%p handler=%p handler_id=%x\n", 4809 (void *)pcic->irq_top, (void *)handler->handler, 4810 handler->handler_id); 4811 } 4812 #endif 4813 4814 switch (pcic->pc_intr_mode) { 4815 case PCIC_INTR_MODE_PCI_1: 4816 4817 mutex_enter(&pcic->intr_lock); 4818 if (pcic->irq_top == NULL) { 4819 mutex_exit(&pcic->intr_lock); 4820 return (BAD_IRQ); 4821 } 4822 4823 intr = NULL; 4824 pcic->irq_current = pcic->irq_top; 4825 4826 while ((pcic->irq_current != NULL) && 4827 (pcic->irq_current->handler_id != 4828 handler->handler_id)) { 4829 intr = pcic->irq_current; 4830 pcic->irq_current = pcic->irq_current->next; 4831 } 4832 4833 if (pcic->irq_current == NULL) { 4834 mutex_exit(&pcic->intr_lock); 4835 return (BAD_IRQ); 4836 } 4837 4838 if (intr != NULL) { 4839 intr->next = pcic->irq_current->next; 4840 } else { 4841 pcic->irq_top = pcic->irq_current->next; 4842 } 4843 4844 current = pcic->irq_current; 4845 pcic->irq_current = pcic->irq_top; 4846 mutex_exit(&pcic->intr_lock); 4847 kmem_free(current, sizeof (inthandler_t)); 4848 4849 break; 4850 4851 default: 4852 4853 mutex_enter(&pcic->pc_lock); 4854 intr = pcic_handlers; 4855 prev = (inthandler_t *)&pcic_handlers; 4856 4857 while (intr != NULL) { 4858 if (intr->handler_id == handler->handler_id) { 4859 i = intr->irq & PCIC_INTR_MASK; 4860 if (--pcic_irq_map[i].count == 0) { 4861 /* multi-handler form */ 4862 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4863 (void) ddi_intr_remove_handler( 4864 pcic->pc_intr_htblp[i]); 4865 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4866 (void) pcmcia_return_intr(pcic->dip, i); 4867 #if defined(PCIC_DEBUG) 4868 if (pcic_debug) { 4869 cmn_err(CE_CONT, 4870 "removing interrupt %d at %s " 4871 "priority\n", i, "high"); 4872 cmn_err(CE_CONT, 4873 "ddi_remove_intr(%p, %x, %p)\n", 4874 (void *)dip, 4875 0, 4876 (void *)intr->iblk_cookie); 4877 } 4878 #endif 4879 } 4880 prev->next = intr->next; 4881 kmem_free(intr, sizeof (inthandler_t)); 4882 intr = prev->next; 4883 } else { 4884 prev = intr; 4885 intr = intr->next; 4886 } /* if (handler_id) */ 4887 } /* while */ 4888 4889 mutex_exit(&pcic->pc_lock); 4890 } 4891 4892 #if defined(PCIC_DEBUG) 4893 if (pcic_debug) { 4894 cmn_err(CE_CONT, 4895 "pcic_clear_interrupt: exit irq_top=%p\n", 4896 (void *)pcic->irq_top); 4897 } 4898 #endif 4899 4900 4901 return (SUCCESS); 4902 } 4903 4904 struct intel_regs { 4905 char *name; 4906 int off; 4907 char *fmt; 4908 } iregs[] = { 4909 {"ident ", 0}, 4910 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4911 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4912 "\7DRD\10OE"}, 4913 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4914 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4915 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4916 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4917 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4918 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4919 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4920 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4921 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4922 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4923 {"io0-slow ", 8}, 4924 {"io0-shi ", 9}, 4925 {"io0-elow ", 0xa}, 4926 {"io0-ehi ", 0xb}, 4927 {"io1-slow ", 0xc}, 4928 {"io1-shi ", 0xd}, 4929 {"io1-elow ", 0xe}, 4930 {"io1-ehi ", 0xf}, 4931 {"mem0-slow ", 0x10}, 4932 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4933 {"mem0-elow ", 0x12}, 4934 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4935 {"card0-low ", 0x14}, 4936 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4937 {"mem1-slow ", 0x18}, 4938 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4939 {"mem1-elow ", 0x1a}, 4940 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4941 {"card1-low ", 0x1c}, 4942 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4943 {"mem2-slow ", 0x20}, 4944 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4945 {"mem2-elow ", 0x22}, 4946 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4947 {"card2-low ", 0x24}, 4948 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4949 {"mem3-slow ", 0x28}, 4950 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4951 {"mem3-elow ", 0x2a}, 4952 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4953 {"card3-low ", 0x2c}, 4954 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4955 4956 {"mem4-slow ", 0x30}, 4957 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4958 {"mem4-elow ", 0x32}, 4959 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4960 {"card4-low ", 0x34}, 4961 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4962 {"mpage0 ", 0x40}, 4963 {"mpage1 ", 0x41}, 4964 {"mpage2 ", 0x42}, 4965 {"mpage3 ", 0x43}, 4966 {"mpage4 ", 0x44}, 4967 {NULL}, 4968 }; 4969 4970 static struct intel_regs cregs[] = { 4971 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 4972 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 4973 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 4974 {"chip-info ", 0x1f, "\20\6DUAL"}, 4975 {"IO-offlow0", 0x36}, 4976 {"IO-offhi0 ", 0x37}, 4977 {"IO-offlow1", 0x38}, 4978 {"IO-offhi1 ", 0x39}, 4979 NULL, 4980 }; 4981 4982 static struct intel_regs cxregs[] = { 4983 {"ext-ctl-1 ", 0x03, 4984 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 4985 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 4986 {"mem0-up ", 0x05}, 4987 {"mem1-up ", 0x06}, 4988 {"mem2-up ", 0x07}, 4989 {"mem3-up ", 0x08}, 4990 {"mem4-up ", 0x09}, 4991 {NULL} 4992 }; 4993 4994 void 4995 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 4996 { 4997 int i, value, j; 4998 char buff[256]; 4999 char *fmt; 5000 5001 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 5002 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 5003 int sval; 5004 if (cregs[i].off == PCIC_MISC_CTL_2) 5005 sval = 0; 5006 else 5007 sval = socket; 5008 value = pcic_getb(pcic, sval, cregs[i].off); 5009 if (i & 1) { 5010 if (cregs[i].fmt) 5011 fmt = "%s\t%s\t%b\n"; 5012 else 5013 fmt = "%s\t%s\t%x\n"; 5014 cmn_err(CE_CONT, fmt, buff, 5015 cregs[i].name, value, cregs[i].fmt); 5016 buff[0] = '\0'; 5017 } else { 5018 if (cregs[i].fmt) 5019 fmt = "\t%s\t%b"; 5020 else 5021 fmt = "\t%s\t%x"; 5022 (void) sprintf(buff, fmt, 5023 cregs[i].name, value, cregs[i].fmt); 5024 for (j = strlen(buff); j < 40; j++) 5025 buff[j] = ' '; 5026 buff[40] = '\0'; 5027 } 5028 } 5029 cmn_err(CE_CONT, "%s\n", buff); 5030 5031 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 5032 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 5033 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 5034 5035 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 5036 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 5037 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 5038 5039 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 5040 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 5041 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 5042 5043 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 5044 5045 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 5046 value = clext_reg_read(pcic, socket, cxregs[i].off); 5047 if (i & 1) { 5048 if (cxregs[i].fmt) 5049 fmt = "%s\t%s\t%b\n"; 5050 else 5051 fmt = "%s\t%s\t%x\n"; 5052 cmn_err(CE_CONT, fmt, buff, 5053 cxregs[i].name, value, cxregs[i].fmt); 5054 buff[0] = '\0'; 5055 } else { 5056 if (cxregs[i].fmt) 5057 fmt = "\t%s\t%b"; 5058 else 5059 fmt = "\t%s\t%x"; 5060 (void) sprintf(buff, fmt, 5061 cxregs[i].name, value, cxregs[i].fmt); 5062 for (j = strlen(buff); j < 40; j++) 5063 buff[j] = ' '; 5064 buff[40] = '\0'; 5065 } 5066 } 5067 } 5068 5069 #if defined(PCIC_DEBUG) 5070 static void 5071 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5072 { 5073 int i, value, j; 5074 char buff[256]; 5075 char *fmt; 5076 5077 #if defined(PCIC_DEBUG) 5078 if (pcic_debug < 2) 5079 return; 5080 #endif 5081 cmn_err(CE_CONT, 5082 "----------- PCIC Registers for socket %d---------\n", 5083 socket); 5084 cmn_err(CE_CONT, 5085 "\tname value name value\n"); 5086 5087 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5088 value = pcic_getb(pcic, socket, iregs[i].off); 5089 if (i & 1) { 5090 if (iregs[i].fmt) 5091 fmt = "%s\t%s\t%b\n"; 5092 else 5093 fmt = "%s\t%s\t%x\n"; 5094 cmn_err(CE_CONT, fmt, buff, 5095 iregs[i].name, value, iregs[i].fmt); 5096 buff[0] = '\0'; 5097 } else { 5098 if (iregs[i].fmt) 5099 fmt = "\t%s\t%b"; 5100 else 5101 fmt = "\t%s\t%x"; 5102 (void) sprintf(buff, fmt, 5103 iregs[i].name, value, iregs[i].fmt); 5104 for (j = strlen(buff); j < 40; j++) 5105 buff[j] = ' '; 5106 buff[40] = '\0'; 5107 } 5108 } 5109 switch (pcic->pc_type) { 5110 case PCIC_CL_PD6710: 5111 case PCIC_CL_PD6722: 5112 case PCIC_CL_PD6729: 5113 case PCIC_CL_PD6832: 5114 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5115 break; 5116 } 5117 cmn_err(CE_CONT, "%s\n", buff); 5118 } 5119 #endif 5120 5121 /* 5122 * pcic_mswait(ms) 5123 * sleep ms milliseconds 5124 * call drv_usecwait once for each ms 5125 */ 5126 static void 5127 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5128 { 5129 if (ms) { 5130 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5131 pcic_mutex_exit(&pcic->pc_lock); 5132 delay(drv_usectohz(ms*1000)); 5133 pcic_mutex_enter(&pcic->pc_lock); 5134 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5135 } 5136 } 5137 5138 /* 5139 * pcic_check_ready(pcic, index, off) 5140 * Wait for card to come ready 5141 * We only wait if the card is NOT in RESET 5142 * and power is on. 5143 */ 5144 static boolean_t 5145 pcic_check_ready(pcicdev_t *pcic, int socket) 5146 { 5147 int ifstate, intstate; 5148 5149 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5150 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5151 5152 if ((intstate & PCIC_RESET) && 5153 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5154 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5155 return (B_TRUE); 5156 5157 #ifdef PCIC_DEBUG 5158 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5159 "ifstate = 0x%x\n", intstate, ifstate); 5160 if (pcic_debug) { 5161 pcic_debug += 4; 5162 xxdmp_all_regs(pcic, socket, -1); 5163 pcic_debug -= 4; 5164 } 5165 #endif 5166 return (B_FALSE); 5167 } 5168 5169 /* 5170 * Cirrus Logic extended register read/write routines 5171 */ 5172 static int 5173 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5174 { 5175 int val; 5176 5177 switch (pcic->pc_io_type) { 5178 case PCIC_IO_TYPE_YENTA: 5179 val = ddi_get8(pcic->handle, 5180 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5181 break; 5182 default: 5183 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5184 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5185 break; 5186 } 5187 5188 return (val); 5189 } 5190 5191 static void 5192 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5193 { 5194 switch (pcic->pc_io_type) { 5195 case PCIC_IO_TYPE_YENTA: 5196 ddi_put8(pcic->handle, 5197 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5198 break; 5199 default: 5200 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5201 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5202 break; 5203 } 5204 } 5205 5206 /* 5207 * Misc PCI functions 5208 */ 5209 static void 5210 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5211 { 5212 unsigned cmd; 5213 5214 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5215 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5216 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5217 (PCI_COMM_IO|PCI_COMM_MAE)) 5218 return; 5219 5220 if (flags & PCIC_ENABLE_IO) 5221 cmd |= PCI_COMM_IO; 5222 5223 if (flags & PCIC_ENABLE_MEM) 5224 cmd |= PCI_COMM_MAE; 5225 5226 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5227 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5228 } 5229 5230 /* 5231 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5232 */ 5233 static int 5234 pcic_find_pci_type(pcicdev_t *pcic) 5235 { 5236 uint32_t vend, device; 5237 5238 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5239 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5240 "vendor-id", -1); 5241 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5242 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5243 "device-id", -1); 5244 5245 device = PCI_ID(vend, device); 5246 pcic->pc_type = device; 5247 pcic->pc_chipname = "PCI:unknown"; 5248 5249 switch (device) { 5250 case PCIC_INTEL_i82092: 5251 pcic->pc_chipname = PCIC_TYPE_i82092; 5252 break; 5253 case PCIC_CL_PD6729: 5254 pcic->pc_chipname = PCIC_TYPE_PD6729; 5255 /* 5256 * Some 6730's incorrectly identify themselves 5257 * as a 6729, so we need to do some more tests 5258 * here to see if the device that's claiming 5259 * to be a 6729 is really a 6730. 5260 */ 5261 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5262 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5263 0) { 5264 pcic->pc_chipname = PCIC_TYPE_PD6730; 5265 pcic->pc_type = PCIC_CL_PD6730; 5266 } 5267 break; 5268 case PCIC_CL_PD6730: 5269 pcic->pc_chipname = PCIC_TYPE_PD6730; 5270 break; 5271 case PCIC_CL_PD6832: 5272 pcic->pc_chipname = PCIC_TYPE_PD6832; 5273 break; 5274 case PCIC_SMC_34C90: 5275 pcic->pc_chipname = PCIC_TYPE_34C90; 5276 break; 5277 case PCIC_TOSHIBA_TOPIC95: 5278 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5279 break; 5280 case PCIC_TOSHIBA_TOPIC100: 5281 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5282 break; 5283 case PCIC_TI_PCI1031: 5284 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5285 break; 5286 case PCIC_TI_PCI1130: 5287 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5288 break; 5289 case PCIC_TI_PCI1131: 5290 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5291 break; 5292 case PCIC_TI_PCI1250: 5293 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5294 break; 5295 case PCIC_TI_PCI1225: 5296 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5297 break; 5298 case PCIC_TI_PCI1410: 5299 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5300 break; 5301 case PCIC_TI_PCI1510: 5302 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5303 break; 5304 case PCIC_TI_PCI1520: 5305 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5306 break; 5307 case PCIC_TI_PCI1221: 5308 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5309 break; 5310 case PCIC_TI_PCI1050: 5311 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5312 break; 5313 case PCIC_ENE_1410: 5314 pcic->pc_chipname = PCIC_TYPE_1410; 5315 break; 5316 case PCIC_O2_OZ6912: 5317 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5318 break; 5319 case PCIC_RICOH_RL5C466: 5320 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5321 break; 5322 case PCIC_TI_PCI1420: 5323 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5324 break; 5325 case PCIC_ENE_1420: 5326 pcic->pc_chipname = PCIC_TYPE_1420; 5327 break; 5328 default: 5329 switch (PCI_ID(vend, (uint32_t)0)) { 5330 case PCIC_TOSHIBA_VENDOR: 5331 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5332 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5333 break; 5334 case PCIC_TI_VENDOR: 5335 pcic->pc_chipname = PCIC_TYPE_TI; 5336 pcic->pc_type = PCIC_TI_VENDOR; 5337 break; 5338 case PCIC_O2MICRO_VENDOR: 5339 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5340 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5341 break; 5342 case PCIC_RICOH_VENDOR: 5343 pcic->pc_chipname = PCIC_TYPE_RICOH; 5344 pcic->pc_type = PCIC_RICOH_VENDOR; 5345 break; 5346 default: 5347 if (!(pcic->pc_flags & PCF_CARDBUS)) 5348 return (DDI_FAILURE); 5349 pcic->pc_chipname = PCIC_TYPE_YENTA; 5350 break; 5351 } 5352 } 5353 return (DDI_SUCCESS); 5354 } 5355 5356 static void 5357 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5358 { 5359 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5360 pcic->cfgaddr + PCIC_82092_PPIRR); 5361 uchar_t val; 5362 5363 if (intr == PCIC_82092_CTL_SMI) { 5364 val = PCIC_82092_SMI_CTL(socket, 5365 PCIC_82092_INT_DISABLE); 5366 ppirr &= ~val; 5367 val = PCIC_82092_SMI_CTL(socket, state); 5368 ppirr |= val; 5369 } else { 5370 val = PCIC_82092_IRQ_CTL(socket, 5371 PCIC_82092_INT_DISABLE); 5372 ppirr &= ~val; 5373 val = PCIC_82092_IRQ_CTL(socket, state); 5374 ppirr |= val; 5375 } 5376 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5377 ppirr); 5378 } 5379 5380 static uint_t 5381 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5382 { 5383 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5384 uint_t rc = DDI_INTR_UNCLAIMED; 5385 5386 _NOTE(ARGUNUSED(arg2)) 5387 5388 mutex_enter(&sockp->pcs_pcic->pc_lock); 5389 if (sockp->pcs_cd_softint_flg) { 5390 uint8_t status; 5391 sockp->pcs_cd_softint_flg = 0; 5392 rc = DDI_INTR_CLAIMED; 5393 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5394 PCIC_INTERFACE_STATUS); 5395 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5396 } 5397 mutex_exit(&sockp->pcs_pcic->pc_lock); 5398 return (rc); 5399 } 5400 5401 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5402 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5403 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5404 5405 #ifdef CARDBUS 5406 static uint32_t pcic_cbps_on = 0; 5407 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5408 CB_PS_XVCARD | CB_PS_YVCARD; 5409 #else 5410 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5411 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5412 CB_PS_CBCARD | 5413 CB_PS_XVCARD | CB_PS_YVCARD; 5414 #endif 5415 static void 5416 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5417 { 5418 boolean_t do_debounce = B_FALSE; 5419 int debounce_time = drv_usectohz(pcic_debounce_time); 5420 uint8_t irq; 5421 timeout_id_t debounce; 5422 5423 /* 5424 * Always reset debounce but may need to check original state later. 5425 */ 5426 debounce = sockp->pcs_debounce_id; 5427 sockp->pcs_debounce_id = 0; 5428 5429 /* 5430 * Check to see whether a card is present or not. There are 5431 * only two states that we are concerned with - the state 5432 * where both CD pins are asserted, which means that the 5433 * card is fully seated, and the state where neither CD 5434 * pin is asserted, which means that the card is not 5435 * present. 5436 * The CD signals are generally very noisy and cause a lot of 5437 * contact bounce as the card is being inserted and 5438 * removed, so we need to do some software debouncing. 5439 */ 5440 5441 #ifdef PCIC_DEBUG 5442 pcic_err(pcic->dip, 6, 5443 "pcic%d handle_cd_change: socket %d card status 0x%x" 5444 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5445 sockp->pcs_socket, status, debounce); 5446 #endif 5447 switch (status & PCIC_ISTAT_CD_MASK) { 5448 case PCIC_CD_PRESENT_OK: 5449 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5450 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5451 uint32_t cbps; 5452 #ifdef PCIC_DEBUG 5453 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5454 #endif 5455 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5456 #ifdef PCIC_DEBUG 5457 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5458 #endif 5459 /* 5460 * Check the CB bits are sane. 5461 */ 5462 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5463 cbps & pcic_cbps_off) { 5464 cmn_err(CE_WARN, 5465 "%s%d: Odd Cardbus Present State 0x%x\n", 5466 ddi_get_name(pcic->dip), 5467 ddi_get_instance(pcic->dip), 5468 cbps); 5469 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5470 debounce = 0; 5471 debounce_time = drv_usectohz(1000000); 5472 } 5473 if (debounce) { 5474 sockp->pcs_flags |= PCS_CARD_PRESENT; 5475 if (pcic_do_insertion) { 5476 5477 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5478 5479 if (cbps & CB_PS_16BITCARD) { 5480 pcic_err(pcic->dip, 8, "16 bit card inserted\n"); 5481 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5482 /* calls pcm_adapter_callback() */ 5483 if (pcic->pc_callback) { 5484 5485 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 5486 pcic->dip, PCM_DEVICETYPE, 5487 "pccard"); 5488 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5489 PCE_CARD_INSERT, 5490 sockp->pcs_socket); 5491 } 5492 } else if (cbps & CB_PS_CBCARD) { 5493 pcic_err(pcic->dip, 8, "32 bit card inserted\n"); 5494 5495 if (pcic->pc_flags & PCF_CARDBUS) { 5496 sockp->pcs_flags |= PCS_CARD_ISCARDBUS; 5497 #ifdef CARDBUS 5498 if (!pcic_load_cardbus(pcic, sockp)) { 5499 pcic_unload_cardbus(pcic, sockp); 5500 } 5501 5502 #else 5503 cmn_err(CE_NOTE, 5504 "32 bit Cardbus not supported in" 5505 " this device driver\n"); 5506 #endif 5507 } else { 5508 /* 5509 * Ignore the card 5510 */ 5511 cmn_err(CE_NOTE, 5512 "32 bit Cardbus not supported on this" 5513 " device\n"); 5514 } 5515 } else { 5516 cmn_err(CE_NOTE, 5517 "Unsupported PCMCIA card inserted\n"); 5518 } 5519 } 5520 syshw_send_signal(sockp->pcs_syshwsig); 5521 } else { 5522 do_debounce = B_TRUE; 5523 } 5524 } else { 5525 /* 5526 * It is possible to come through here if the system 5527 * starts up with cards already inserted. Do nothing 5528 * and don't worry about it. 5529 */ 5530 #ifdef PCIC_DEBUG 5531 pcic_err(pcic->dip, 5, 5532 "pcic%d: Odd card insertion indication on socket %d\n", 5533 ddi_get_instance(pcic->dip), 5534 sockp->pcs_socket); 5535 #endif 5536 } 5537 break; 5538 5539 default: 5540 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5541 /* 5542 * Someone has started to insert a card so delay a while. 5543 */ 5544 do_debounce = B_TRUE; 5545 break; 5546 } 5547 /* 5548 * Otherwise this is basically the same as not present 5549 * so fall through. 5550 */ 5551 5552 /* FALLTHRU */ 5553 case 0: 5554 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5555 if (pcic->pc_flags & PCF_CBPWRCTL) { 5556 pcic_putcb(pcic, CB_CONTROL, 0); 5557 } else { 5558 pcic_putb(pcic, sockp->pcs_socket, PCIC_POWER_CONTROL, 0); 5559 (void) pcic_getb(pcic, sockp->pcs_socket, 5560 PCIC_POWER_CONTROL); 5561 } 5562 #ifdef PCIC_DEBUG 5563 pcic_err(pcic->dip, 8, "Card removed\n"); 5564 #endif 5565 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5566 5567 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5568 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5569 if (pcic_do_removal && pcic->pc_callback) { 5570 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5571 PCE_CARD_REMOVAL, sockp->pcs_socket); 5572 } 5573 } 5574 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5575 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5576 sockp->pcs_flags |= PCS_CARD_CBREM; 5577 } 5578 sockp->pcs_flags |= PCS_CARD_REMOVED; 5579 5580 do_debounce = B_TRUE; 5581 } 5582 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5583 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5584 /* 5585 * Ensure that we do the unloading in the 5586 * debounce handler, that way we're not doing 5587 * nasty things in an interrupt handler. e.g. 5588 * a USB device will wait for data which will 5589 * obviously never come because we've 5590 * unplugged the device, but the wait will 5591 * wait forever because no interrupts can 5592 * come in... 5593 */ 5594 #ifdef CARDBUS 5595 pcic_unload_cardbus(pcic, sockp); 5596 /* pcic_dump_all(pcic); */ 5597 #endif 5598 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5599 } 5600 syshw_send_signal(sockp->pcs_syshwsig); 5601 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5602 } 5603 break; 5604 } /* switch */ 5605 5606 if (do_debounce) { 5607 /* 5608 * Delay doing 5609 * anything for a while so that things can settle 5610 * down a little. Interrupts are already disabled. 5611 * Reset the state and we'll reevaluate the 5612 * whole kit 'n kaboodle when the timeout fires 5613 */ 5614 #ifdef PCIC_DEBUG 5615 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5616 "socket %d.%d\n", 5617 ddi_get_instance(pcic->dip), 5618 sockp->pcs_socket); 5619 #endif 5620 sockp->pcs_debounce_id = pcic_add_debqueue(sockp, debounce_time); 5621 5622 /* 5623 * We bug out here without re-enabling interrupts. They will 5624 * be re-enabled when the debounce timeout swings through 5625 * here. 5626 */ 5627 return; 5628 } 5629 5630 /* 5631 * Turn on Card detect interrupts. Other interrupts will be 5632 * enabled during set_socket calls. 5633 * 5634 * Note that set_socket only changes interrupt settings when there 5635 * is a card present. 5636 */ 5637 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5638 irq |= PCIC_CD_DETECT; 5639 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5640 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK); 5641 5642 /* Out from debouncing state */ 5643 sockp->pcs_flags &= ~PCS_DEBOUNCING; 5644 5645 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5646 } 5647 5648 /* 5649 * pcic_getb() 5650 * get an I/O byte based on the yardware decode method 5651 */ 5652 static uint8_t 5653 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5654 { 5655 int work; 5656 5657 #if defined(PCIC_DEBUG) 5658 if (pcic_debug == 0x7fff) { 5659 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5660 (void *)pcic, socket, reg); 5661 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5662 pcic->pc_io_type, (void *)pcic->handle, 5663 (void *)pcic->ioaddr); 5664 } 5665 #endif 5666 5667 switch (pcic->pc_io_type) { 5668 case PCIC_IO_TYPE_YENTA: 5669 return (ddi_get8(pcic->handle, 5670 pcic->ioaddr + CB_R2_OFFSET + reg)); 5671 default: 5672 work = (socket * PCIC_SOCKET_1) | reg; 5673 ddi_put8(pcic->handle, pcic->ioaddr, work); 5674 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5675 } 5676 } 5677 5678 static void 5679 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5680 { 5681 int work; 5682 5683 #if defined(PCIC_DEBUG) 5684 if (pcic_debug == 0x7fff) { 5685 cmn_err(CE_CONT, 5686 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5687 (void *)pcic, socket, reg, value); 5688 cmn_err(CE_CONT, 5689 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5690 pcic->pc_io_type, (void *)pcic->handle, 5691 (void *)pcic->ioaddr); 5692 } 5693 #endif 5694 5695 5696 switch (pcic->pc_io_type) { 5697 case PCIC_IO_TYPE_YENTA: 5698 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5699 value); 5700 break; 5701 default: 5702 work = (socket * PCIC_SOCKET_1) | reg; 5703 ddi_put8(pcic->handle, pcic->ioaddr, work); 5704 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5705 break; 5706 } 5707 } 5708 5709 /* 5710 * chip identification functions 5711 */ 5712 5713 /* 5714 * chip identification: Cirrus Logic PD6710/6720/6722 5715 */ 5716 static int 5717 pcic_ci_cirrus(pcicdev_t *pcic) 5718 { 5719 int value1, value2; 5720 5721 /* Init the CL id mode */ 5722 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5723 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5724 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5725 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5726 5727 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5728 (value2 & PCIC_CI_ID) == 0) { 5729 /* chip is a Cirrus Logic and not Intel */ 5730 pcic->pc_type = PCIC_CL_PD6710; 5731 if (value1 & PCIC_CI_SLOTS) 5732 pcic->pc_chipname = PCIC_TYPE_PD6720; 5733 else 5734 pcic->pc_chipname = PCIC_TYPE_PD6710; 5735 /* now fine tune things just in case a 6722 */ 5736 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5737 if (value1 == 0) { 5738 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5739 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5740 if (value1 == 0x55) { 5741 pcic->pc_chipname = PCIC_TYPE_PD6722; 5742 pcic->pc_type = PCIC_CL_PD6722; 5743 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5744 } 5745 } 5746 return (1); 5747 } 5748 return (0); 5749 } 5750 5751 /* 5752 * chip identification: Vadem (VG365/465/468/469) 5753 */ 5754 5755 static void 5756 pcic_vadem_enable(pcicdev_t *pcic) 5757 { 5758 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5759 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5760 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5761 } 5762 5763 static int 5764 pcic_ci_vadem(pcicdev_t *pcic) 5765 { 5766 int value; 5767 5768 pcic_vadem_enable(pcic); 5769 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5770 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5771 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5772 (value | PCIC_VADEM_D3) || 5773 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5774 PCIC_VADEM_469) { 5775 int vadem, new; 5776 pcic_vadem_enable(pcic); 5777 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5778 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5779 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5780 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5781 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5782 5783 /* want to lock but leave mouse or other on */ 5784 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5785 switch (value & PCIC_REV_MASK) { 5786 case PCIC_VADEM_365: 5787 pcic->pc_chipname = PCIC_VG_365; 5788 pcic->pc_type = PCIC_VADEM; 5789 break; 5790 case PCIC_VADEM_465: 5791 pcic->pc_chipname = PCIC_VG_465; 5792 pcic->pc_type = PCIC_VADEM; 5793 pcic->pc_flags |= PCF_1SOCKET; 5794 break; 5795 case PCIC_VADEM_468: 5796 pcic->pc_chipname = PCIC_VG_468; 5797 pcic->pc_type = PCIC_VADEM; 5798 break; 5799 case PCIC_VADEM_469: 5800 pcic->pc_chipname = PCIC_VG_469; 5801 pcic->pc_type = PCIC_VADEM_VG469; 5802 break; 5803 } 5804 return (1); 5805 } 5806 return (0); 5807 } 5808 5809 /* 5810 * chip identification: Ricoh 5811 */ 5812 static int 5813 pcic_ci_ricoh(pcicdev_t *pcic) 5814 { 5815 int value; 5816 5817 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5818 switch (value) { 5819 case PCIC_RF_296: 5820 pcic->pc_type = PCIC_RICOH; 5821 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5822 return (1); 5823 case PCIC_RF_396: 5824 pcic->pc_type = PCIC_RICOH; 5825 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5826 return (1); 5827 } 5828 return (0); 5829 } 5830 5831 5832 /* 5833 * set up available address spaces in busra 5834 */ 5835 static void 5836 pcic_init_assigned(dev_info_t *dip) 5837 { 5838 pcm_regs_t *pcic_avail_p; 5839 pci_regspec_t *pci_avail_p, *regs; 5840 int len, entries, rlen; 5841 dev_info_t *pdip; 5842 5843 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5844 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5845 /* 5846 * found "available" property at the cardbus/pcmcia node 5847 * need to translate address space entries from pcmcia 5848 * format to pci format 5849 */ 5850 entries = len / sizeof (pcm_regs_t); 5851 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5852 KM_SLEEP); 5853 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5854 entries) == DDI_SUCCESS) 5855 (void) pci_resource_setup_avail(dip, pci_avail_p, 5856 entries); 5857 kmem_free(pcic_avail_p, len); 5858 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5859 return; 5860 } 5861 5862 /* 5863 * "legacy" platforms will have "available" property in pci node 5864 */ 5865 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5866 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5867 "available", (caddr_t)&pci_avail_p, &len) == 5868 DDI_PROP_SUCCESS) { 5869 /* (void) pci_resource_setup(pdip); */ 5870 kmem_free(pci_avail_p, len); 5871 break; 5872 } 5873 } 5874 5875 if (pdip == NULL) { 5876 int len; 5877 char bus_type[16] = "(unknown)"; 5878 dev_info_t *par; 5879 5880 cmn_err(CE_CONT, 5881 "?pcic_init_assigned: no available property for pcmcia\n"); 5882 5883 /* 5884 * This code is taken from pci_resource_setup() but does 5885 * not attempt to use the "available" property to populate 5886 * the ndi maps that are created. 5887 * The fact that we will actually 5888 * free some resource below (that was allocated by OBP) 5889 * should be enough to be going on with. 5890 */ 5891 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5892 len = sizeof (bus_type); 5893 5894 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5895 PROP_LEN_AND_VAL_BUF, 5896 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5897 "device_type", 5898 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5899 (strcmp(bus_type, "pci") == 0)) 5900 break; 5901 } 5902 if (par != NULL && 5903 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5904 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5905 par = NULL; 5906 } else { 5907 #ifdef CARDBUS 5908 cardbus_bus_range_t *bus_range; 5909 int k; 5910 5911 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5912 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5913 if (bus_range->lo != bus_range->hi) 5914 pcic_err(pdip, 9, "allowable bus range is " 5915 "%u->%u\n", bus_range->lo, bus_range->hi); 5916 else { 5917 pcic_err(pdip, 0, 5918 "!No spare PCI bus numbers, range is " 5919 "%u->%u, cardbus isn't usable\n", 5920 bus_range->lo, bus_range->hi); 5921 } 5922 kmem_free(bus_range, k); 5923 } else 5924 pcic_err(pdip, 0, "!No bus-range property seems to " 5925 "have been set up\n"); 5926 #endif 5927 /* 5928 * Have a valid parent with the "available" property 5929 */ 5930 (void) pci_resource_setup(pdip); 5931 } 5932 5933 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5934 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5935 "assigned-addresses", 5936 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5937 ra_return_t ra; 5938 5939 /* 5940 * On the UltraBook IIi the ranges are assigned under 5941 * openboot. If we don't free them here the first I/O 5942 * space that can be used is up above 0x10000 which 5943 * doesn't work for this driver due to restrictions 5944 * on the PCI I/O addresses the controllers can cope with. 5945 * They are never going to be used by anything else 5946 * so free them up to the general pool. AG. 5947 */ 5948 pcic_err(dip, 1, "Free assigned addresses\n"); 5949 5950 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5951 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5952 regs[0].pci_size_low == 0x1000000) { 5953 ra.ra_addr_lo = regs[0].pci_phys_low; 5954 ra.ra_len = regs[0].pci_size_low; 5955 (void) pcmcia_free_mem(dip, &ra); 5956 } 5957 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 5958 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 5959 (regs[1].pci_size_low == 0x8000 || 5960 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 5961 { 5962 ra.ra_addr_lo = regs[1].pci_phys_low; 5963 ra.ra_len = regs[1].pci_size_low; 5964 (void) pcmcia_free_io(dip, &ra); 5965 } 5966 kmem_free((caddr_t)regs, rlen); 5967 } 5968 } 5969 5970 /* 5971 * translate "available" from pcmcia format to pci format 5972 */ 5973 static int 5974 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 5975 pci_regspec_t *pci_p, int entries) 5976 { 5977 int i, range_len, range_entries; 5978 pcic_ranges_t *pcic_range_p; 5979 5980 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 5981 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 5982 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 5983 "no ranges property for pcmcia\n"); 5984 return (DDI_FAILURE); 5985 } 5986 5987 range_entries = range_len / sizeof (pcic_ranges_t); 5988 5989 /* for each "available" entry to be translated */ 5990 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 5991 int j; 5992 pcic_ranges_t *range_p = pcic_range_p; 5993 pci_p->pci_phys_hi = -1u; /* default invalid value */ 5994 5995 /* for each "ranges" entry to be searched */ 5996 for (j = 0; j < range_entries; j++, range_p++) { 5997 uint64_t range_end = range_p->pcic_range_caddrlo + 5998 range_p->pcic_range_size; 5999 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 6000 6001 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 6002 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 6003 (range_end < avail_end)) 6004 continue; 6005 6006 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 6007 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 6008 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 6009 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 6010 pci_p->pci_size_hi = 0; 6011 pci_p->pci_size_low = pcic_p->phys_len; 6012 } 6013 } 6014 kmem_free(pcic_range_p, range_len); 6015 return (DDI_SUCCESS); 6016 } 6017 6018 static int 6019 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 6020 { 6021 if (getminor(*dev) == SYSHW_MINOR) 6022 return (syshw_open(dev, flag, otyp, cred)); 6023 #ifdef CARDBUS 6024 if (cardbus_is_cb_minor(*dev)) 6025 return (cardbus_open(dev, flag, otyp, cred)); 6026 #endif 6027 return (EINVAL); 6028 } 6029 6030 static int 6031 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 6032 { 6033 if (getminor(dev) == SYSHW_MINOR) 6034 return (syshw_close(dev, flag, otyp, cred)); 6035 #ifdef CARDBUS 6036 if (cardbus_is_cb_minor(dev)) 6037 return (cardbus_close(dev, flag, otyp, cred)); 6038 #endif 6039 return (EINVAL); 6040 } 6041 6042 static int 6043 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 6044 int *rval) 6045 { 6046 if (getminor(dev) == SYSHW_MINOR) 6047 return (syshw_ioctl(dev, cmd, arg, mode, cred, rval)); 6048 #ifdef CARDBUS 6049 if (cardbus_is_cb_minor(dev)) 6050 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 6051 #endif 6052 return (EINVAL); 6053 } 6054 6055 6056 static boolean_t 6057 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6058 { 6059 uint32_t present_state; 6060 dev_info_t *dip = pcic->dip; 6061 set_socket_t s; 6062 get_socket_t g; 6063 boolean_t retval; 6064 unsigned vccLevel; 6065 6066 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 6067 6068 pcic_mutex_exit(&pcic->pc_lock); 6069 6070 bzero(&s, sizeof (set_socket_t)); 6071 s.socket = sockp->pcs_socket; 6072 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6073 s.IFType = IF_CARDBUS; 6074 s.State = (unsigned)~0; 6075 6076 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6077 if (present_state & PCIC_VCC_3VCARD) 6078 s.VccLevel = PCIC_VCC_3VLEVEL; 6079 else if (present_state & PCIC_VCC_5VCARD) 6080 s.VccLevel = PCIC_VCC_5VLEVEL; 6081 else { 6082 cmn_err(CE_CONT, 6083 "pcic_load_cardbus: unsupported card voltage\n"); 6084 goto failure; 6085 } 6086 vccLevel = s.VccLevel; 6087 s.Vpp1Level = s.Vpp2Level = 0; 6088 6089 if (pcic_set_socket(dip, &s) != SUCCESS) 6090 goto failure; 6091 6092 if (pcic_reset_socket(dip, sockp->pcs_socket, 6093 RESET_MODE_CARD_ONLY) != SUCCESS) 6094 goto failure; 6095 6096 bzero(&g, sizeof (get_socket_t)); 6097 g.socket = sockp->pcs_socket; 6098 if (pcic_get_socket(dip, &g) != SUCCESS) 6099 goto failure; 6100 6101 bzero(&s, sizeof (set_socket_t)); 6102 s.socket = sockp->pcs_socket; 6103 s.SCIntMask = SBM_CD; 6104 s.IREQRouting = g.IRQRouting; 6105 s.IFType = g.IFType; 6106 s.CtlInd = g.CtlInd; 6107 s.State = (unsigned)~0; 6108 s.VccLevel = vccLevel; 6109 s.Vpp1Level = s.Vpp2Level = 0; 6110 6111 if (pcic_set_socket(dip, &s) != SUCCESS) 6112 goto failure; 6113 6114 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6115 goto exit; 6116 6117 failure: 6118 retval = B_FALSE; 6119 6120 exit: 6121 pcic_mutex_enter(&pcic->pc_lock); 6122 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6123 retval ? "success" : "failure"); 6124 return (retval); 6125 } 6126 6127 static void 6128 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6129 { 6130 dev_info_t *dip = pcic->dip; 6131 set_socket_t s; 6132 6133 pcic_mutex_exit(&pcic->pc_lock); 6134 6135 cardbus_unload_cardbus(dip); 6136 6137 bzero(&s, sizeof (set_socket_t)); 6138 s.socket = sockp->pcs_socket; 6139 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6140 s.IREQRouting = 0; 6141 s.IFType = IF_MEMORY; 6142 s.CtlInd = 0; 6143 s.State = 0; 6144 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6145 6146 (void) pcic_set_socket(dip, &s); 6147 6148 pcic_mutex_enter(&pcic->pc_lock); 6149 } 6150 6151 static uint32_t 6152 pcic_getcb(pcicdev_t *pcic, int reg) 6153 { 6154 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6155 6156 return (ddi_get32(pcic->handle, 6157 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6158 } 6159 6160 static void 6161 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6162 { 6163 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6164 6165 ddi_put32(pcic->handle, 6166 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6167 } 6168 6169 static void 6170 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6171 { 6172 uint8_t value; 6173 uint16_t brdgctl; 6174 6175 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6176 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6177 6178 switch (pcic->pc_type) { 6179 case PCIC_INTEL_i82092: 6180 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6181 PCIC_82092_INT_ENABLE); 6182 break; 6183 case PCIC_O2_OZ6912: 6184 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6185 value |= 0x8; 6186 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6187 break; 6188 case PCIC_CL_PD6832: 6189 case PCIC_TI_PCI1250: 6190 case PCIC_TI_PCI1221: 6191 case PCIC_TI_PCI1225: 6192 case PCIC_TI_PCI1410: 6193 case PCIC_ENE_1410: 6194 case PCIC_TI_PCI1510: 6195 case PCIC_TI_PCI1520: 6196 case PCIC_TI_PCI1420: 6197 case PCIC_ENE_1420: 6198 /* route card functional interrupts to PCI interrupts */ 6199 brdgctl = ddi_get16(pcic->cfg_handle, 6200 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6201 pcic_err(NULL, 1, 6202 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6203 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6204 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6205 ddi_put16(pcic->cfg_handle, 6206 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6207 brdgctl); 6208 /* Flush the write */ 6209 (void) ddi_get16(pcic->cfg_handle, 6210 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6211 break; 6212 default: 6213 break; 6214 } 6215 } 6216 6217 static void 6218 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6219 { 6220 uint8_t value; 6221 uint16_t brdgctl; 6222 6223 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6224 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6225 6226 switch (pcic->pc_type) { 6227 case PCIC_INTEL_i82092: 6228 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6229 PCIC_82092_INT_DISABLE); 6230 break; 6231 case PCIC_O2_OZ6912: 6232 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6233 value &= ~0x8; 6234 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6235 /* Flush the write */ 6236 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6237 break; 6238 case PCIC_CL_PD6832: 6239 case PCIC_TI_PCI1250: 6240 case PCIC_TI_PCI1221: 6241 case PCIC_TI_PCI1225: 6242 case PCIC_TI_PCI1410: 6243 case PCIC_ENE_1410: 6244 case PCIC_TI_PCI1510: 6245 case PCIC_TI_PCI1520: 6246 case PCIC_TI_PCI1420: 6247 case PCIC_ENE_1420: 6248 /* 6249 * This maps I/O interrupts to ExCA which 6250 * have been turned off by the write to 6251 * PCIC_INTERRUPT above. It would appear to 6252 * be the only way to actually turn I/O Ints off 6253 * while retaining CS Ints. 6254 */ 6255 brdgctl = ddi_get16(pcic->cfg_handle, 6256 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6257 pcic_err(NULL, 1, 6258 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6259 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6260 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6261 ddi_put16(pcic->cfg_handle, 6262 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6263 brdgctl); 6264 /* Flush the write */ 6265 (void) ddi_get16(pcic->cfg_handle, 6266 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6267 break; 6268 default: 6269 break; 6270 } 6271 } 6272 6273 static void 6274 pcic_cb_enable_intr(dev_info_t *dip) 6275 { 6276 anp_t *anp = ddi_get_driver_private(dip); 6277 pcicdev_t *pcic = anp->an_private; 6278 6279 mutex_enter(&pcic->pc_lock); 6280 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6281 mutex_exit(&pcic->pc_lock); 6282 } 6283 6284 static void 6285 pcic_cb_disable_intr(dev_info_t *dip) 6286 { 6287 anp_t *anp = ddi_get_driver_private(dip); 6288 pcicdev_t *pcic = anp->an_private; 6289 6290 mutex_enter(&pcic->pc_lock); 6291 pcic_disable_io_intr(pcic, 0); 6292 mutex_exit(&pcic->pc_lock); 6293 } 6294 6295 static int 6296 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6297 { 6298 int nerr = 0; 6299 if (e & PCI_STAT_PERROR) { 6300 nerr++; 6301 cmn_err(CE_CONT, "detected parity error.\n"); 6302 } 6303 if (e & PCI_STAT_S_SYSERR) { 6304 nerr++; 6305 if (bridge_secondary) 6306 cmn_err(CE_CONT, "received system error.\n"); 6307 else 6308 cmn_err(CE_CONT, "signalled system error.\n"); 6309 } 6310 if (e & PCI_STAT_R_MAST_AB) { 6311 nerr++; 6312 cmn_err(CE_CONT, "received master abort.\n"); 6313 } 6314 if (e & PCI_STAT_R_TARG_AB) 6315 cmn_err(CE_CONT, "received target abort.\n"); 6316 if (e & PCI_STAT_S_TARG_AB) 6317 cmn_err(CE_CONT, "signalled target abort\n"); 6318 if (e & PCI_STAT_S_PERROR) { 6319 nerr++; 6320 cmn_err(CE_CONT, "signalled parity error\n"); 6321 } 6322 return (nerr); 6323 } 6324 6325 #if defined(__sparc) 6326 static int 6327 pcic_fault(enum pci_fault_ops op, void *arg) 6328 { 6329 pcicdev_t *pcic = (pcicdev_t *)arg; 6330 ushort_t pci_cfg_stat = 6331 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6332 ushort_t pci_cfg_sec_stat = 6333 pci_config_get16(pcic->cfg_handle, 0x16); 6334 char nm[24]; 6335 int nerr = 0; 6336 6337 cardbus_dump_pci_config(pcic->dip); 6338 6339 switch (op) { 6340 case FAULT_LOG: 6341 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6342 ddi_get_instance(pcic->dip)); 6343 6344 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6345 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6346 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6347 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6348 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6349 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6350 return (nerr); 6351 case FAULT_POKEFINI: 6352 case FAULT_RESET: 6353 pci_config_put16(pcic->cfg_handle, 6354 PCI_CONF_STAT, pci_cfg_stat); 6355 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6356 break; 6357 case FAULT_POKEFLT: 6358 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6359 return (1); 6360 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6361 return (1); 6362 break; 6363 default: 6364 break; 6365 } 6366 return (DDI_SUCCESS); 6367 } 6368 #endif 6369 6370 static void 6371 pcic_delayed_resume(void *arg) 6372 { 6373 int i, j, interrupt; 6374 anp_t *pcic_nexus; 6375 pcicdev_t *pcic; 6376 6377 _NOTE(ARGUNUSED(arg)) 6378 6379 #if defined(PCIC_DEBUG) 6380 pcic_err(NULL, 6, "pcic_delayed_resume(): entered\n"); 6381 #endif 6382 for (j = 0; j <= pcic_maxinst; j++) { 6383 6384 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, j); 6385 if (!pcic_nexus) 6386 continue; 6387 pcic = (pcicdev_t *)pcic_nexus->an_private; 6388 if (!pcic) 6389 continue; 6390 6391 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6392 for (i = 0; i < pcic->pc_numsockets; i++) { 6393 /* Enable interrupts on PCI if needs be */ 6394 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6395 if (pcic->pc_flags & PCF_USE_SMI) 6396 interrupt |= PCIC_INTR_ENABLE; 6397 pcic_putb(pcic, i, PCIC_INTERRUPT, 6398 PCIC_RESET | interrupt); 6399 pcic->pc_sockets[i].pcs_debounce_id = 6400 pcic_add_debqueue(&pcic->pc_sockets[i], 6401 drv_usectohz(pcic_debounce_time)); 6402 } 6403 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6404 if (pcic_do_pcmcia_sr) 6405 (void) pcmcia_wait_insert(pcic->dip); 6406 } 6407 } 6408 6409 static void 6410 pcic_debounce(pcic_socket_t *pcs) 6411 { 6412 uint8_t status, stschng; 6413 6414 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6415 pcs->pcs_flags &= ~PCS_STARTING; 6416 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6417 PCIC_CARD_STATUS_CHANGE); 6418 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6419 PCIC_INTERFACE_STATUS); 6420 #ifdef PCIC_DEBUG 6421 pcic_err(pcs->pcs_pcic->dip, 8, 6422 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6423 "chg 0x%x flg 0x%x\n", 6424 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6425 status, stschng, pcs->pcs_flags); 6426 #endif 6427 6428 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6429 PCIC_CD_DETECT); 6430 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6431 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6432 } 6433 6434 static void 6435 pcic_deb_thread() 6436 { 6437 callb_cpr_t cprinfo; 6438 struct debounce *debp; 6439 clock_t lastt; 6440 6441 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6442 callb_generic_cpr, "pcic debounce thread"); 6443 mutex_enter(&pcic_deb_mtx); 6444 while (pcic_deb_threadid) { 6445 while (pcic_deb_queue) { 6446 #ifdef PCIC_DEBUG 6447 pcic_dump_debqueue("Thread"); 6448 #endif 6449 debp = pcic_deb_queue; 6450 (void) drv_getparm(LBOLT, &lastt); 6451 if (lastt >= debp->expire) { 6452 pcic_deb_queue = debp->next; 6453 mutex_exit(&pcic_deb_mtx); 6454 pcic_debounce(debp->pcs); 6455 mutex_enter(&pcic_deb_mtx); 6456 kmem_free(debp, sizeof (*debp)); 6457 } else { 6458 (void) cv_timedwait(&pcic_deb_cv, 6459 &pcic_deb_mtx, debp->expire); 6460 } 6461 } 6462 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6463 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6464 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6465 } 6466 pcic_deb_threadid = (kthread_t *)1; 6467 cv_signal(&pcic_deb_cv); 6468 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6469 thread_exit(); 6470 } 6471 6472 static void * 6473 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6474 { 6475 clock_t lbolt; 6476 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6477 6478 (void) drv_getparm(LBOLT, &lbolt); 6479 dbp = kmem_alloc(sizeof (struct debounce), KM_NOSLEEP); 6480 6481 dbp->expire = lbolt + clocks; 6482 dbp->pcs = pcs; 6483 mutex_enter(&pcic_deb_mtx); 6484 while (*dbpp) { 6485 if (dbp->expire > (*dbpp)->expire) 6486 dbpp = &((*dbpp)->next); 6487 else 6488 break; 6489 } 6490 dbp->next = *dbpp; 6491 *dbpp = dbp; 6492 #ifdef PCIC_DEBUG 6493 pcic_dump_debqueue("Add"); 6494 #endif 6495 cv_signal(&pcic_deb_cv); 6496 mutex_exit(&pcic_deb_mtx); 6497 return (dbp); 6498 } 6499 6500 static void 6501 pcic_rm_debqueue(void *id) 6502 { 6503 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6504 6505 dbp = (struct debounce *)id; 6506 mutex_enter(&pcic_deb_mtx); 6507 while (*dbpp) { 6508 if (*dbpp == dbp) { 6509 *dbpp = dbp->next; 6510 kmem_free(dbp, sizeof (*dbp)); 6511 #ifdef PCIC_DEBUG 6512 pcic_dump_debqueue("Remove"); 6513 #endif 6514 cv_signal(&pcic_deb_cv); 6515 mutex_exit(&pcic_deb_mtx); 6516 return; 6517 } 6518 dbpp = &((*dbpp)->next); 6519 } 6520 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6521 mutex_exit(&pcic_deb_mtx); 6522 } 6523 6524 6525 static int pcic_powerdelay = 0; 6526 6527 static int 6528 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6529 { 6530 int ind, value, orig_pwrctl; 6531 6532 /* power setup -- if necessary */ 6533 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6534 6535 #if defined(PCIC_DEBUG) 6536 pcic_err(pcic->dip, 6, 6537 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6538 socket, powerlevel, orig_pwrctl); 6539 #endif 6540 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6541 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6542 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6543 if (powerlevel != orig_pwrctl) { 6544 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6545 int ifs; 6546 /* 6547 * set power to socket 6548 * note that the powerlevel was calculated earlier 6549 */ 6550 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6551 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6552 6553 /* 6554 * this second write to the power control register 6555 * is needed to resolve a problem on 6556 * the IBM ThinkPad 750 6557 * where the first write doesn't latch. 6558 * The second write appears to always work and 6559 * doesn't hurt the operation of other chips 6560 * so we can just use it -- this is good since we can't 6561 * determine what chip the 750 actually uses 6562 * (I suspect an early Ricoh). 6563 */ 6564 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6565 6566 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6567 pcic_mswait(pcic, socket, pcic_powerdelay); 6568 #if defined(PCIC_DEBUG) 6569 pcic_err(pcic->dip, 8, 6570 "\tpowerlevel reg = %x (ifs %x)\n", 6571 value, pcic_getb(pcic, socket, 6572 PCIC_INTERFACE_STATUS)); 6573 pcic_err(pcic->dip, 8, 6574 "CBus regs: PS 0x%x, Control 0x%x\n", 6575 pcic_getcb(pcic, CB_PRESENT_STATE), 6576 pcic_getcb(pcic, CB_CONTROL)); 6577 #endif 6578 /* 6579 * since power was touched, make sure it says it 6580 * is on. This lets it become stable. 6581 */ 6582 for (ind = 0; ind < 20; ind++) { 6583 ifs = pcic_getb(pcic, socket, 6584 PCIC_INTERFACE_STATUS); 6585 if (ifs & PCIC_POWER_ON) 6586 break; 6587 else { 6588 pcic_putb(pcic, socket, 6589 PCIC_POWER_CONTROL, 0); 6590 (void) pcic_getb(pcic, socket, 6591 PCIC_POWER_CONTROL); 6592 pcic_mswait(pcic, socket, 40); 6593 if (ind == 10) { 6594 pcic_putcb(pcic, CB_EVENT_FORCE, 6595 CB_EF_CVTEST); 6596 pcic_mswait(pcic, socket, 100); 6597 } 6598 pcic_putb(pcic, socket, 6599 PCIC_POWER_CONTROL, 6600 powerlevel & ~POWER_OUTPUT_ENABLE); 6601 (void) pcic_getb(pcic, socket, 6602 PCIC_POWER_CONTROL); 6603 pcic_mswait(pcic, socket, 6604 pcic_powerdelay); 6605 pcic_putb(pcic, socket, 6606 PCIC_POWER_CONTROL, powerlevel); 6607 (void) pcic_getb(pcic, socket, 6608 PCIC_POWER_CONTROL); 6609 pcic_mswait(pcic, socket, 6610 pcic_powerdelay); 6611 } 6612 } 6613 6614 if (!(ifs & PCIC_POWER_ON)) { 6615 cmn_err(CE_WARN, 6616 "pcic socket %d: Power didn't get turned" 6617 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6618 "misc1 0x%x igc 0x%x ind %d\n", 6619 socket, ifs, 6620 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6621 orig_pwrctl, 6622 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6623 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6624 ind); 6625 return (BAD_VCC); 6626 } 6627 #if defined(PCIC_DEBUG) 6628 pcic_err(pcic->dip, 8, 6629 "\tind = %d, if status %x pwrc 0x%x " 6630 "misc1 0x%x igc 0x%x\n", 6631 ind, ifs, 6632 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6633 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6634 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6635 #endif 6636 } else { 6637 /* explicitly turned off the power */ 6638 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6639 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6640 } 6641 } 6642 return (SUCCESS); 6643 } 6644 6645 static int pcic_cbdoreset_during_poweron = 1; 6646 static int 6647 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6648 { 6649 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6650 int ind, iobits; 6651 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6652 6653 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6654 6655 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6656 cbctl |= pcic_cbv_levels[ind]; 6657 6658 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6659 cbctl |= (pcic_cbv_levels[ind]<<4); 6660 6661 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6662 6663 #if defined(PCIC_DEBUG) 6664 pcic_err(pcic->dip, 6, 6665 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6666 "cbctl 0x%x->0x%x\n", 6667 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6668 #endif 6669 if (cbctl != orig_cbctl) { 6670 if (pcic_cbdoreset_during_poweron && 6671 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6672 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6673 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits & ~PCIC_RESET); 6674 } 6675 pcic_putcb(pcic, CB_CONTROL, cbctl); 6676 6677 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6678 pcic_mswait(pcic, socket, pcic_powerdelay); 6679 return (SUCCESS); 6680 } 6681 for (ind = 0; ind < 20; ind++) { 6682 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6683 6684 if (cbstev & CB_SE_POWER_CYCLE) { 6685 6686 /* 6687 * delay 400 ms: though the standard defines that the Vcc 6688 * set-up time is 20 ms, some PC-Card bridge requires longer 6689 * duration. 6690 * Note: We should check the status AFTER the delay to give time 6691 * for things to stabilize. 6692 */ 6693 pcic_mswait(pcic, socket, 400); 6694 6695 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6696 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6697 /* break; */ 6698 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6699 } 6700 if (cbctl & CB_PS_BADVCC) { 6701 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6702 break; 6703 } 6704 6705 #if defined(PCIC_DEBUG) 6706 pcic_err(pcic->dip, 8, 6707 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6708 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6709 cbctl, orig_cbctl); 6710 #endif 6711 if (pcic_cbdoreset_during_poweron && 6712 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6713 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6714 } 6715 return (SUCCESS); 6716 } 6717 pcic_mswait(pcic, socket, 40); 6718 } 6719 if (pcic_cbdoreset_during_poweron && 6720 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6721 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6722 } 6723 cmn_err(CE_WARN, 6724 "pcic socket %d: Power didn't get turned on/off!\n" 6725 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6726 "vcc %d vpp1 %d", socket, cbstev, 6727 pcic_getcb(pcic, CB_PRESENT_STATE), 6728 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6729 return (BAD_VCC); 6730 } 6731 return (SUCCESS); 6732 } 6733 6734 static int pcic_do_pprintf = 0; 6735 6736 static void 6737 pcic_dump_debqueue(char *msg) 6738 { 6739 struct debounce *debp = pcic_deb_queue; 6740 clock_t lbolt; 6741 6742 (void) drv_getparm(LBOLT, &lbolt); 6743 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6744 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6745 while (debp) { 6746 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6747 (void *) debp, (int)debp->expire, (void *) debp->next, 6748 debp->pcs->pcs_debounce_id); 6749 debp = debp->next; 6750 } 6751 } 6752 6753 6754 /* PRINTFLIKE3 */ 6755 static void 6756 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6757 { 6758 if (pcic_debug && (level <= pcic_debug)) { 6759 va_list adx; 6760 int instance; 6761 char buf[256]; 6762 const char *name; 6763 #if !defined(PCIC_DEBUG) 6764 int ce; 6765 char qmark = 0; 6766 6767 if (level <= 3) 6768 ce = CE_WARN; 6769 else 6770 ce = CE_CONT; 6771 if (level == 4) 6772 qmark = 1; 6773 #endif 6774 6775 if (dip) { 6776 instance = ddi_get_instance(dip); 6777 /* name = ddi_binding_name(dip); */ 6778 name = ddi_driver_name(dip); 6779 } else { 6780 instance = 0; 6781 name = ""; 6782 } 6783 6784 va_start(adx, fmt); 6785 (void) vsprintf(buf, fmt, adx); 6786 va_end(adx); 6787 6788 #if defined(PCIC_DEBUG) 6789 if (pcic_do_pprintf) { 6790 if (dip) { 6791 if (instance >= 0) 6792 prom_printf("%s(%d),0x%p: %s", name, 6793 instance, dip, buf); 6794 else 6795 prom_printf("%s,0x%p: %s", 6796 name, dip, buf); 6797 } else 6798 prom_printf(buf); 6799 } else { 6800 if (dip) { 6801 if (instance >= 0) 6802 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6803 name, instance, (void *) dip, buf); 6804 else 6805 cmn_err(CE_CONT, "%s,0x%p: %s", 6806 name, (void *) dip, buf); 6807 } else 6808 cmn_err(CE_CONT, buf); 6809 } 6810 #else 6811 if (dip) 6812 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6813 instance, buf); 6814 else 6815 cmn_err(ce, qmark ? "?%s" : buf, buf); 6816 #endif 6817 } 6818 } 6819 6820 6821 static void 6822 pcic_syshw_cardstate(syshw_t *item, void *arg) 6823 { 6824 pcic_socket_t *pcs = (pcic_socket_t *)arg; 6825 6826 if (pcs->pcs_flags & PCS_CARD_PRESENT) { 6827 item->state = B_TRUE; 6828 if (pcs->pcs_flags & PCS_CARD_IS16BIT) 6829 item->values[0] = 1; 6830 else if (pcs->pcs_flags & PCS_CARD_ISCARDBUS) 6831 item->values[0] = 2; 6832 else 6833 item->values[0] = 0; 6834 } else { 6835 item->state = B_FALSE; 6836 item->values[0] = 0; 6837 } 6838 } 6839 6840 /* 6841 * Tadpole additional for the syshw interface used to control the 6842 * start/stop switch which is physically linked to the GPIO1 pin 6843 * on the 1250a. 6844 */ 6845 6846 #define CLIENT_CALLED 0x8000000 6847 #define NCE_EVENT_MASK 0xffff 6848 6849 typedef struct _client { 6850 pid_t pid; /* set by kernel */ 6851 int flags; /* NCE_REGISTER... */ 6852 int priority; /* >100 unless root */ 6853 int events; /* pending event flags */ 6854 int event_sig; /* SIG... etc */ 6855 struct _client *next; /* set by kernel */ 6856 struct _client *prev; /* set by kernel */ 6857 } client_data; 6858 6859 static client_data *cl_data; 6860 static int n_clients; 6861 static kmutex_t client_mtx, intr_mtx; 6862 6863 static void delete_client(int); 6864 6865 #ifdef VOYAGER 6866 static uint32_t runstop_sig; 6867 static ddi_softintr_t softint_id; 6868 static uchar_t softint_flag; 6869 static int switch_debounce_time = 100; /* in milliseconds */ 6870 static timeout_id_t switch_to_id; 6871 6872 static syshw_t syshw_run_stop = { 6873 0, "Run/Stop", SH_SWITCH, 6874 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID, 6875 B_FALSE, { 0 } }; 6876 6877 static void 6878 syshw_get_run_stop(syshw_t *item, void *arg) 6879 { 6880 pcicdev_t *pcic = (pcicdev_t *)arg; 6881 6882 if (ddi_get8(pcic->cfg_handle, 6883 pcic->cfgaddr + PCIC_GPIO1_REG) & PCIC_GPIO_DIN) 6884 item->state = B_TRUE; 6885 else 6886 item->state = B_FALSE; 6887 } 6888 6889 6890 #endif 6891 6892 static void 6893 syshw_attach(pcicdev_t *pcic) 6894 { 6895 if (ddi_get_instance(pcic->dip) != 0) 6896 return; 6897 6898 #ifdef VOYAGER 6899 if (pcic->pc_type == PCIC_TI_PCI1250) { 6900 6901 /* 6902 * Only setup run/stop on a Voyager. 6903 * This is currently defined as 6904 * a TI1250 on a SPARC architecture. May have to make this a 6905 * property definition in the future. 6906 */ 6907 if (ddi_add_softintr(pcic->dip, 6908 DDI_SOFTINT_LOW, &softint_id, 6909 NULL, NULL, syshw_intr, 6910 (caddr_t)pcic) == DDI_SUCCESS) { 6911 runstop_sig = syshw_add2map(&syshw_run_stop, 6912 syshw_get_run_stop, pcic); 6913 mutex_init(&intr_mtx, NULL, MUTEX_DRIVER, 6914 pcic->pc_pri); 6915 ddi_put8(pcic->cfg_handle, 6916 pcic->cfgaddr + PCIC_GPIO1_REG, 6917 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | 6918 PCIC_GPIO_DELTA); 6919 } 6920 } 6921 #endif 6922 mutex_init(&client_mtx, "syshw client", MUTEX_DRIVER, NULL); 6923 (void) ddi_create_minor_node(pcic->dip, "syshw", S_IFCHR, 6924 SYSHW_MINOR, NULL, NULL); 6925 } 6926 6927 static void 6928 syshw_detach(pcicdev_t *pcic) 6929 { 6930 #ifdef VOYAGER 6931 if (pcic->pc_type == PCIC_TI_PCI1250) { 6932 pcic_mutex_enter(&intr_mtx); 6933 6934 /* 6935 * Turn off this interrupt. 6936 */ 6937 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6938 PCIC_GPIO_FINPUT); 6939 6940 if (switch_to_id) 6941 (void) untimeout(switch_to_id); 6942 switch_to_id = 0; 6943 softint_flag = 0; 6944 6945 pcic_mutex_exit(&intr_mtx); 6946 ddi_remove_softintr(softint_id); 6947 mutex_destroy(&intr_mtx); 6948 } 6949 #endif 6950 6951 ddi_remove_minor_node(pcic->dip, NULL); 6952 mutex_destroy(&client_mtx); 6953 } 6954 6955 static void 6956 syshw_resume(pcicdev_t *pcic) 6957 { 6958 #ifdef VOYAGER 6959 if (pcic->pc_type == PCIC_TI_PCI1250) { 6960 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6961 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | PCIC_GPIO_DELTA); 6962 } 6963 #else 6964 _NOTE(ARGUNUSED(pcic)) 6965 #endif 6966 } 6967 6968 #ifdef VOYAGER 6969 static uint_t 6970 syshw_intr_hi(pcicdev_t *pcic) 6971 { 6972 uchar_t regval; 6973 6974 if (pcic->pc_type != PCIC_TI_PCI1250) 6975 return (DDI_INTR_UNCLAIMED); 6976 6977 regval = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG); 6978 if (regval & PCIC_GPIO_DELTA) { 6979 pcic_mutex_enter(&intr_mtx); 6980 if (softint_flag == 0 && switch_to_id == 0) { 6981 softint_flag = 1; 6982 ddi_trigger_softintr(softint_id); 6983 } 6984 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6985 regval); 6986 pcic_mutex_exit(&intr_mtx); 6987 return (DDI_INTR_CLAIMED); 6988 } 6989 6990 return (DDI_INTR_UNCLAIMED); 6991 } 6992 6993 /* 6994 * Don't deliver the signal until the debounce period has expired. 6995 * Unfortuately this means it end up as a three tier interrupt just 6996 * to indicate a bit change. 6997 */ 6998 static void 6999 syshw_debounce_to(void *arg) 7000 { 7001 _NOTE(ARGUNUSED(arg)) 7002 7003 if (switch_to_id) { 7004 pcic_mutex_enter(&intr_mtx); 7005 switch_to_id = 0; 7006 pcic_mutex_exit(&intr_mtx); 7007 syshw_send_signal(runstop_sig); 7008 return; 7009 } 7010 } 7011 7012 static uint_t 7013 syshw_intr(caddr_t arg) 7014 { 7015 _NOTE(ARGUNUSED(arg)) 7016 7017 if (softint_flag) { 7018 pcic_mutex_enter(&intr_mtx); 7019 softint_flag = 0; 7020 if (!switch_to_id) 7021 switch_to_id = timeout(syshw_debounce_to, arg, 7022 drv_usectohz(switch_debounce_time * 1000)); 7023 pcic_mutex_exit(&intr_mtx); 7024 return (DDI_INTR_CLAIMED); 7025 } 7026 return (DDI_INTR_UNCLAIMED); 7027 } 7028 #endif 7029 7030 /* 7031 * Send signals to the registered clients 7032 */ 7033 static void 7034 syshw_send_signal(int events) 7035 { 7036 client_data *ptr; 7037 proc_t *pr; 7038 int done_flag; 7039 7040 ptr = cl_data; 7041 while (ptr != NULL) { 7042 done_flag = CLIENT_CALLED; 7043 7044 if ((ptr->flags & events) && 7045 (ptr->event_sig != 0) && 7046 ((ptr->flags & done_flag) == 0)) { 7047 7048 /* 7049 * only call the process if: 7050 * it has not already received the nce signal 7051 * its signal was not zero (just in case) 7052 * and it is registered to receive this signal 7053 */ 7054 pcic_mutex_enter(&pidlock); 7055 pr = prfind(ptr->pid); 7056 pcic_mutex_exit(&pidlock); 7057 if (pr == NULL) { 7058 /* 7059 * This process has died, 7060 * so we free its memory and move on 7061 * start at the begining again: 7062 * a waste of cycles but it makes things easy.. 7063 */ 7064 delete_client(ptr->pid); 7065 ptr = cl_data; 7066 } else { 7067 ptr->events |= (events & ptr->flags & 7068 NCE_EVENT_MASK); 7069 psignal(pr, ptr->event_sig); 7070 ptr->flags |= done_flag; 7071 ptr = ptr->next; 7072 } 7073 } else { 7074 ptr = ptr->next; 7075 } 7076 } 7077 7078 ptr = cl_data; 7079 while (ptr != NULL) { 7080 ptr->flags &= ~done_flag; 7081 ptr = ptr->next; 7082 } 7083 } 7084 7085 static int 7086 syshw_open(dev_t *dev, int flag, int otyp, cred_t *cred) 7087 { 7088 _NOTE(ARGUNUSED(dev, flag, cred)) 7089 7090 if (otyp != OTYP_CHR) 7091 return (EINVAL); 7092 7093 return (0); 7094 } 7095 7096 static int 7097 syshw_close(dev_t dev, int flag, int otyp, cred_t *cred) 7098 { 7099 _NOTE(ARGUNUSED(dev, flag, otyp, cred)) 7100 7101 return (0); 7102 } 7103 7104 /* 7105 * Add a client to the list of interested processes 7106 */ 7107 static void 7108 add_client(client_data *new) 7109 { 7110 client_data * ptr; 7111 7112 n_clients++; 7113 if (cl_data == NULL) { 7114 cl_data = new; 7115 return; 7116 } 7117 7118 ptr = cl_data; 7119 while ((ptr->next != NULL) && (ptr->priority <= new->priority)) 7120 ptr = ptr->next; 7121 7122 if (ptr == cl_data) { 7123 /* at head of the list */ 7124 cl_data = new; 7125 new->next = ptr; 7126 new->prev = NULL; 7127 if (ptr != NULL) 7128 ptr->prev = new; 7129 } else { 7130 /* somewhere else in the list - insert after */ 7131 new->next = ptr->next; 7132 ptr->next = new; 7133 new->prev = ptr; 7134 if (new->next != NULL) 7135 (new->next)->prev = new; 7136 } 7137 } 7138 7139 /* 7140 * Locate a client data structure in the client list by looking for a PID match. 7141 */ 7142 static client_data * 7143 locate_client(pid_t pid) 7144 { 7145 client_data * ptr = cl_data; 7146 7147 while ((ptr != NULL) && (ptr->pid != pid)) 7148 ptr = ptr->next; 7149 7150 return (ptr); 7151 } 7152 7153 /* 7154 * Remove a client record from the client list 7155 */ 7156 static void 7157 delete_client(pid_t pid) 7158 { 7159 client_data * ptr; 7160 7161 ptr = locate_client(pid); 7162 if (ptr == NULL) 7163 return; /* hmmm!! */ 7164 7165 n_clients--; 7166 7167 if (ptr == cl_data) { 7168 /* remove the head of the list */ 7169 cl_data = ptr->next; 7170 } 7171 if (ptr->prev != NULL) 7172 (ptr->prev)->next = ptr->next; 7173 if (ptr->next != NULL) 7174 (ptr->next)->prev = ptr->prev; 7175 7176 kmem_free(ptr, sizeof (client_data)); 7177 } 7178 7179 static void 7180 unregister_event_client() 7181 { 7182 pcic_mutex_enter(&client_mtx); 7183 delete_client(ddi_get_pid()); 7184 pcic_mutex_exit(&client_mtx); 7185 } 7186 7187 static int 7188 register_event_client(client_data *u_client) 7189 { 7190 int error; 7191 client_data * client; 7192 7193 pcic_mutex_enter(&client_mtx); 7194 client = locate_client(ddi_get_pid()); 7195 if (client) { 7196 /* 7197 * we are re-registering ourself 7198 * so we delete the previous entry 7199 */ 7200 delete_client(ddi_get_pid()); 7201 } 7202 7203 client = (client_data *)kmem_alloc(sizeof (client_data), KM_SLEEP); 7204 7205 if (client) { 7206 client->pid = ddi_get_pid(); 7207 client->priority = u_client->priority; 7208 client->flags = u_client->flags & NCE_EVENT_MASK; 7209 client->events = 0; 7210 client->event_sig = u_client->event_sig; 7211 client->next = NULL; 7212 client->prev = NULL; 7213 add_client(client); 7214 error = 0; 7215 } else 7216 error = EIO; 7217 7218 pcic_mutex_exit(&client_mtx); 7219 return (error); 7220 } 7221 7222 /* 7223 * Read the currently pending event flags for the process in question 7224 */ 7225 static int 7226 check_events_pending(caddr_t data) 7227 { 7228 client_data * client; 7229 int error = 0; 7230 7231 pcic_mutex_enter(&client_mtx); 7232 client = locate_client(ddi_get_pid()); 7233 if (client) { 7234 if (copyout((caddr_t)&client->events, data, sizeof (int))) 7235 error = EFAULT; 7236 else 7237 client->events = 0; 7238 } else 7239 error = EINVAL; 7240 7241 pcic_mutex_exit(&client_mtx); 7242 return (error); 7243 } 7244 7245 7246 #define MAXITEMS 8 7247 static syshw_t *syshw_map[MAXITEMS]; 7248 static void (*syshw_getfuncs[MAXITEMS])(syshw_t *, void *); 7249 static void *syshw_getfunc_args[MAXITEMS]; 7250 static int nsyshw_items = 0; 7251 #define NSYSHW_ITEMS nsyshw_items 7252 7253 static uint32_t 7254 syshw_add2map(syshw_t *item, void (*getfunc)(syshw_t *, void *), void *getarg) 7255 { 7256 uint32_t rval = (1 << nsyshw_items); 7257 if (nsyshw_items == MAXITEMS) 7258 return (0); 7259 item->hw_id = nsyshw_items; 7260 syshw_map[nsyshw_items] = item; 7261 syshw_getfuncs[nsyshw_items] = getfunc; 7262 syshw_getfunc_args[nsyshw_items] = getarg; 7263 nsyshw_items++; 7264 return (rval); 7265 } 7266 7267 static int 7268 syshw_ioctl(dev_t dev, int cmd, intptr_t ioctldata, int mode, 7269 cred_t *cred, int *rval) 7270 { 7271 caddr_t data = (caddr_t)ioctldata; 7272 syshw_t sh; 7273 hwev_t hwev; 7274 client_data dummy_client; 7275 int rc = 0, i; 7276 7277 _NOTE(ARGUNUSED(dev, mode, cred, rval)) 7278 7279 switch (cmd) { 7280 default: 7281 rc = EINVAL; 7282 break; 7283 7284 case SYSHW_GET_ITEM: 7285 case SYSHW_GET_ITEM_MAXVALUES: 7286 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7287 rc = EFAULT; 7288 break; 7289 } 7290 7291 if (sh.hw_id >= NSYSHW_ITEMS) { 7292 rc = EINVAL; 7293 break; 7294 } 7295 7296 sh = *syshw_map[sh.hw_id]; 7297 if (!sh.id_string[0]) { 7298 rc = ENOTTY; 7299 break; 7300 } 7301 if (cmd == SYSHW_GET_ITEM) { 7302 if (syshw_getfuncs[sh.hw_id]) 7303 syshw_getfuncs[sh.hw_id](&sh, 7304 syshw_getfunc_args[sh.hw_id]); 7305 else 7306 rc = ENOTTY; 7307 } 7308 7309 if (copyout((caddr_t)&sh, data, sizeof (sh))) { 7310 rc = EFAULT; 7311 break; 7312 } 7313 break; 7314 7315 case SYSHW_SET_ITEM: 7316 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7317 rc = EFAULT; 7318 break; 7319 } 7320 7321 if (sh.hw_id >= NSYSHW_ITEMS || 7322 !syshw_map[sh.hw_id]->id_string[0] || 7323 !(syshw_map[sh.hw_id]->capabilities & 7324 (SYSHW_STATE_MODIFY | SYSHW_VAL0_MODIFY | 7325 SYSHW_VAL1_MODIFY | SYSHW_VAL2_MODIFY | 7326 SYSHW_VAL3_MODIFY))) { 7327 rc = EINVAL; 7328 break; 7329 } 7330 7331 switch (sh.hw_id) { 7332 default: 7333 rc = EINVAL; 7334 break; 7335 } 7336 break; 7337 7338 case SYSHW_EVREG: 7339 if (copyin(data, (caddr_t)&hwev, sizeof (hwev))) { 7340 rc = EFAULT; 7341 break; 7342 } 7343 7344 for (i = 0; i < NSYSHW_ITEMS; i++) { 7345 if (hwev.events & (1 << i) && 7346 !(syshw_map[i]->capabilities & 7347 SYSHW_CAN_SIGNAL_CHANGE)) { 7348 rc = EINVAL; 7349 break; 7350 } 7351 } 7352 if (hwev.event_sig != SIGUSR1 && hwev.event_sig != SIGUSR2) 7353 rc = EINVAL; 7354 7355 if (!rc) { 7356 dummy_client.priority = 100; 7357 dummy_client.flags = hwev.events; 7358 dummy_client.event_sig = hwev.event_sig; 7359 rc = register_event_client(&dummy_client); 7360 } 7361 break; 7362 7363 case SYSHW_EVUNREG: 7364 unregister_event_client(); 7365 break; 7366 7367 case SYSHW_CHKEV: 7368 rc = check_events_pending(data); 7369 break; 7370 } 7371 return (rc); 7372 } 7373