1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 * Copyright (c) 2016 by Delphix. All rights reserved. 26 */ 27 28 /* 29 * PCIC device/interrupt handler 30 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 31 * and Toshiba (and possibly other clones) PCMCIA adapter chip 32 * sets. It implements a subset of Socket Services as defined 33 * in the Solaris PCMCIA design documents 34 */ 35 36 /* 37 * currently defined "properties" 38 * 39 * clock-frequency bus clock frequency 40 * smi system management interrupt override 41 * need-mult-irq need status IRQ for each pair of sockets 42 * disable-audio don't route audio signal to speaker 43 */ 44 45 46 #include <sys/types.h> 47 #include <sys/inttypes.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/user.h> 51 #include <sys/buf.h> 52 #include <sys/file.h> 53 #include <sys/uio.h> 54 #include <sys/conf.h> 55 #include <sys/stat.h> 56 #include <sys/autoconf.h> 57 #include <sys/vtoc.h> 58 #include <sys/dkio.h> 59 #include <sys/ddi.h> 60 #include <sys/sunddi.h> 61 #include <sys/sunndi.h> 62 #include <sys/var.h> 63 #include <sys/callb.h> 64 #include <sys/open.h> 65 #include <sys/ddidmareq.h> 66 #include <sys/dma_engine.h> 67 #include <sys/kstat.h> 68 #include <sys/kmem.h> 69 #include <sys/modctl.h> 70 #include <sys/pci.h> 71 #include <sys/pci_impl.h> 72 73 #include <sys/pctypes.h> 74 #include <sys/pcmcia.h> 75 #include <sys/sservice.h> 76 77 #include <sys/note.h> 78 79 #include <sys/pcic_reg.h> 80 #include <sys/pcic_var.h> 81 82 #if defined(__x86) 83 #include <sys/pci_cfgspace.h> 84 #endif 85 86 #if defined(__sparc) 87 #include <sys/pci/pci_nexus.h> 88 #endif 89 90 #include <sys/hotplug/hpcsvc.h> 91 #include "cardbus/cardbus.h" 92 93 #define SOFTC_SIZE (sizeof (anp_t)) 94 95 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 96 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 97 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 98 static int32_t pcic_quiesce(dev_info_t *); 99 static uint_t pcic_intr(caddr_t, caddr_t); 100 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 101 static int pcic_probe(dev_info_t *); 102 103 static int pcic_open(dev_t *, int, int, cred_t *); 104 static int pcic_close(dev_t, int, int, cred_t *); 105 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 106 107 typedef struct pcm_regs pcm_regs_t; 108 109 static void pcic_init_assigned(dev_info_t *); 110 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 111 pci_regspec_t *, int); 112 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 113 114 /* 115 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 116 * are xlated into DMA ctlops. To make this nexus work on x86, we 117 * need to have the default ddi_dma_mctl ctlops in the bus_ops 118 * structure, just to pass the request to the parent. The correct 119 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 120 */ 121 static 122 struct bus_ops pcmciabus_ops = { 123 BUSO_REV, 124 pcmcia_bus_map, 125 NULL, 126 NULL, 127 NULL, 128 i_ddi_map_fault, 129 ddi_no_dma_map, 130 ddi_no_dma_allochdl, 131 ddi_no_dma_freehdl, 132 ddi_no_dma_bindhdl, 133 ddi_no_dma_unbindhdl, 134 ddi_no_dma_flush, 135 ddi_no_dma_win, 136 ddi_dma_mctl, 137 pcmcia_ctlops, 138 pcmcia_prop_op, 139 NULL, /* (*bus_get_eventcookie)(); */ 140 NULL, /* (*bus_add_eventcall)(); */ 141 NULL, /* (*bus_remove_eventcall)(); */ 142 NULL, /* (*bus_post_event)(); */ 143 NULL, /* (*bus_intr_ctl)(); */ 144 NULL, /* (*bus_config)(); */ 145 NULL, /* (*bus_unconfig)(); */ 146 NULL, /* (*bus_fm_init)(); */ 147 NULL, /* (*bus_fm_fini)(); */ 148 NULL, /* (*bus_enter)() */ 149 NULL, /* (*bus_exit)() */ 150 NULL, /* (*bus_power)() */ 151 pcmcia_intr_ops /* (*bus_intr_op)(); */ 152 }; 153 154 static struct cb_ops pcic_cbops = { 155 pcic_open, 156 pcic_close, 157 nodev, 158 nodev, 159 nodev, 160 nodev, 161 nodev, 162 pcic_ioctl, 163 nodev, 164 nodev, 165 nodev, 166 nochpoll, 167 ddi_prop_op, 168 NULL, 169 #ifdef CARDBUS 170 D_NEW | D_MP | D_HOTPLUG 171 #else 172 D_NEW | D_MP 173 #endif 174 }; 175 176 static struct dev_ops pcic_devops = { 177 DEVO_REV, 178 0, 179 pcic_getinfo, 180 nulldev, 181 pcic_probe, 182 pcic_attach, 183 pcic_detach, 184 nulldev, 185 &pcic_cbops, 186 &pcmciabus_ops, 187 NULL, 188 pcic_quiesce, /* devo_quiesce */ 189 }; 190 191 void *pcic_soft_state_p = NULL; 192 static int pcic_maxinst = -1; 193 194 int pcic_do_insertion = 1; 195 int pcic_do_removal = 1; 196 197 struct irqmap { 198 int irq; 199 int count; 200 } pcic_irq_map[16]; 201 202 203 int pcic_debug = 0x0; 204 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 205 extern void cardbus_dump_pci_config(dev_info_t *dip); 206 extern void cardbus_dump_socket(dev_info_t *dip); 207 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 208 static void pcic_dump_debqueue(char *msg); 209 210 #if defined(PCIC_DEBUG) 211 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 212 213 #define pcic_mutex_enter(a) \ 214 { \ 215 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 216 mutex_enter(a); \ 217 }; 218 219 #define pcic_mutex_exit(a) \ 220 { \ 221 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 222 mutex_exit(a); \ 223 }; 224 225 #else 226 #define pcic_mutex_enter(a) mutex_enter(a) 227 #define pcic_mutex_exit(a) mutex_exit(a) 228 #endif 229 230 #define PCIC_VCC_3VLEVEL 1 231 #define PCIC_VCC_5VLEVEL 2 232 #define PCIC_VCC_12LEVEL 3 233 234 /* bit patterns to select voltage levels */ 235 int pcic_vpp_levels[13] = { 236 0, 0, 0, 237 1, /* 3.3V */ 238 0, 239 1, /* 5V */ 240 0, 0, 0, 0, 0, 0, 241 2 /* 12V */ 242 }; 243 244 uint8_t pcic_cbv_levels[13] = { 245 0, 0, 0, 246 3, /* 3.3V */ 247 0, 248 2, /* 5V */ 249 0, 0, 0, 0, 0, 0, 250 1 /* 12V */ 251 }; 252 253 struct power_entry pcic_power[4] = { 254 { 255 0, VCC|VPP1|VPP2 256 }, 257 { 258 33, /* 3.3Volt */ 259 VCC|VPP1|VPP2 260 }, 261 { 262 5*10, /* 5Volt */ 263 VCC|VPP1|VPP2 /* currently only know about this */ 264 }, 265 { 266 12*10, /* 12Volt */ 267 VPP1|VPP2 268 } 269 }; 270 271 /* 272 * Base used to allocate ranges of PCI memory on x86 systems 273 * Each instance gets a chunk above the base that is used to map 274 * in the memory and I/O windows for that device. 275 * Pages below the base are also allocated for the EXCA registers, 276 * one per instance. 277 */ 278 #define PCIC_PCI_MEMCHUNK 0x1000000 279 280 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 281 static int pcic_debounce_time = 200000; /* In micro-seconds */ 282 283 struct debounce { 284 pcic_socket_t *pcs; 285 clock_t expire; 286 struct debounce *next; 287 }; 288 289 static struct debounce *pcic_deb_queue = NULL; 290 static kmutex_t pcic_deb_mtx; 291 static kcondvar_t pcic_deb_cv; 292 static kthread_t *pcic_deb_threadid; 293 294 static inthandler_t *pcic_handlers; 295 296 static void pcic_setup_adapter(pcicdev_t *); 297 static int pcic_change(pcicdev_t *, int); 298 static int pcic_ll_reset(pcicdev_t *, int); 299 static void pcic_mswait(pcicdev_t *, int, int); 300 static boolean_t pcic_check_ready(pcicdev_t *, int); 301 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 302 static void pcic_ready_wait(pcicdev_t *, int); 303 extern int pcmcia_get_intr(dev_info_t *, int); 304 extern int pcmcia_return_intr(dev_info_t *, int); 305 extern void pcmcia_cb_suspended(int); 306 extern void pcmcia_cb_resumed(int); 307 308 static int pcic_callback(dev_info_t *, int (*)(), int); 309 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 310 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 311 static int pcic_get_page(dev_info_t *, get_page_t *); 312 static int pcic_get_socket(dev_info_t *, get_socket_t *); 313 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 314 static int pcic_get_window(dev_info_t *, get_window_t *); 315 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 316 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 317 static int pcic_reset_socket(dev_info_t *, int, int); 318 static int pcic_set_page(dev_info_t *, set_page_t *); 319 static int pcic_set_window(dev_info_t *, set_window_t *); 320 static int pcic_set_socket(dev_info_t *, set_socket_t *); 321 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 322 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 323 static void pcic_pm_detection(void *); 324 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 325 static int clext_reg_read(pcicdev_t *, int, uchar_t); 326 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 327 static int pcic_calc_speed(pcicdev_t *, uint32_t); 328 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 329 static int pcic_find_pci_type(pcicdev_t *); 330 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 331 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 332 static uint_t pcic_cd_softint(caddr_t, caddr_t); 333 static uint8_t pcic_getb(pcicdev_t *, int, int); 334 static void pcic_putb(pcicdev_t *, int, int, int8_t); 335 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 336 static uint_t pcic_softintr(caddr_t, caddr_t); 337 338 static void pcic_debounce(pcic_socket_t *); 339 static void pcic_do_resume(pcicdev_t *); 340 static void *pcic_add_debqueue(pcic_socket_t *, int); 341 static void pcic_rm_debqueue(void *); 342 static void pcic_deb_thread(); 343 344 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 345 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 346 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 347 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 348 static void pcic_cb_enable_intr(dev_info_t *); 349 static void pcic_cb_disable_intr(dev_info_t *); 350 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 351 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 352 353 static cb_nexus_cb_t pcic_cbnexus_ops = { 354 pcic_cb_enable_intr, 355 pcic_cb_disable_intr 356 }; 357 358 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 359 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 360 361 #if defined(__sparc) 362 static int pcic_fault(enum pci_fault_ops op, void *arg); 363 #endif 364 365 366 /* 367 * pcmcia interface operations structure 368 * this is the private interface that is exported to the nexus 369 */ 370 pcmcia_if_t pcic_if_ops = { 371 PCIF_MAGIC, 372 PCIF_VERSION, 373 pcic_callback, 374 pcic_get_adapter, 375 pcic_get_page, 376 pcic_get_socket, 377 pcic_get_status, 378 pcic_get_window, 379 pcic_inquire_adapter, 380 pcic_inquire_socket, 381 pcic_inquire_window, 382 pcic_reset_socket, 383 pcic_set_page, 384 pcic_set_window, 385 pcic_set_socket, 386 pcic_set_interrupt, 387 pcic_clear_interrupt, 388 NULL, 389 }; 390 391 /* 392 * chip type identification routines 393 * this list of functions is searched until one of them succeeds 394 * or all fail. i82365SL is assumed if failed. 395 */ 396 static int pcic_ci_cirrus(pcicdev_t *); 397 static int pcic_ci_vadem(pcicdev_t *); 398 static int pcic_ci_ricoh(pcicdev_t *); 399 400 int (*pcic_ci_funcs[])(pcicdev_t *) = { 401 pcic_ci_cirrus, 402 pcic_ci_vadem, 403 pcic_ci_ricoh, 404 NULL 405 }; 406 407 static struct modldrv modldrv = { 408 &mod_driverops, /* Type of module. This one is a driver */ 409 "PCIC PCMCIA adapter driver", /* Name of the module. */ 410 &pcic_devops, /* driver ops */ 411 }; 412 413 static struct modlinkage modlinkage = { 414 MODREV_1, (void *)&modldrv, NULL 415 }; 416 417 int 418 _init() 419 { 420 int stat; 421 422 /* Allocate soft state */ 423 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 424 SOFTC_SIZE, 2)) != DDI_SUCCESS) 425 return (stat); 426 427 if ((stat = mod_install(&modlinkage)) != 0) 428 ddi_soft_state_fini(&pcic_soft_state_p); 429 430 return (stat); 431 } 432 433 int 434 _fini() 435 { 436 int stat = 0; 437 438 if ((stat = mod_remove(&modlinkage)) != 0) 439 return (stat); 440 441 if (pcic_deb_threadid) { 442 mutex_enter(&pcic_deb_mtx); 443 pcic_deb_threadid = 0; 444 while (!pcic_deb_threadid) 445 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 446 pcic_deb_threadid = 0; 447 mutex_exit(&pcic_deb_mtx); 448 449 mutex_destroy(&pcic_deb_mtx); 450 cv_destroy(&pcic_deb_cv); 451 } 452 453 ddi_soft_state_fini(&pcic_soft_state_p); 454 455 return (stat); 456 } 457 458 int 459 _info(struct modinfo *modinfop) 460 { 461 return (mod_info(&modlinkage, modinfop)); 462 } 463 464 /* 465 * pcic_getinfo() 466 * provide instance/device information about driver 467 */ 468 /*ARGSUSED*/ 469 static int 470 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 471 { 472 anp_t *anp; 473 int error = DDI_SUCCESS; 474 minor_t minor; 475 476 switch (cmd) { 477 case DDI_INFO_DEVT2DEVINFO: 478 minor = getminor((dev_t)arg); 479 minor &= 0x7f; 480 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 481 *result = NULL; 482 else 483 *result = anp->an_dip; 484 break; 485 case DDI_INFO_DEVT2INSTANCE: 486 minor = getminor((dev_t)arg); 487 minor &= 0x7f; 488 *result = (void *)((long)minor); 489 break; 490 default: 491 error = DDI_FAILURE; 492 break; 493 } 494 return (error); 495 } 496 497 static int 498 pcic_probe(dev_info_t *dip) 499 { 500 int value; 501 ddi_device_acc_attr_t attr; 502 ddi_acc_handle_t handle; 503 uchar_t *index, *data; 504 505 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 506 return (DDI_PROBE_DONTCARE); 507 508 /* 509 * find a PCIC device (any vendor) 510 * while there can be up to 4 such devices in 511 * a system, we currently only look for 1 512 * per probe. There will be up to 2 chips per 513 * instance since they share I/O space 514 */ 515 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 516 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 517 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 518 519 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 520 (caddr_t *)&index, 521 PCIC_ISA_CONTROL_REG_OFFSET, 522 PCIC_ISA_CONTROL_REG_LENGTH, 523 &attr, &handle) != DDI_SUCCESS) 524 return (DDI_PROBE_FAILURE); 525 526 data = index + 1; 527 528 #if defined(PCIC_DEBUG) 529 if (pcic_debug) 530 cmn_err(CE_CONT, "pcic_probe: entered\n"); 531 if (pcic_debug) 532 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 533 #endif 534 ddi_put8(handle, index, PCIC_CHIP_REVISION); 535 ddi_put8(handle, data, 0); 536 value = ddi_get8(handle, data); 537 #if defined(PCIC_DEBUG) 538 if (pcic_debug) 539 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 540 #endif 541 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 542 (value & 0x30) == 0) { 543 /* 544 * we probably have a PCIC chip in the system 545 * do a little more checking. If we find one, 546 * reset everything in case of softboot 547 */ 548 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 549 ddi_put8(handle, data, 0); 550 value = ddi_get8(handle, data); 551 #if defined(PCIC_DEBUG) 552 if (pcic_debug) 553 cmn_err(CE_CONT, "\tzero test = %x\n", value); 554 #endif 555 /* should read back as zero */ 556 if (value == 0) { 557 /* 558 * we do have one and it is off the bus 559 */ 560 #if defined(PCIC_DEBUG) 561 if (pcic_debug) 562 cmn_err(CE_CONT, "pcic_probe: success\n"); 563 #endif 564 ddi_regs_map_free(&handle); 565 return (DDI_PROBE_SUCCESS); 566 } 567 } 568 #if defined(PCIC_DEBUG) 569 if (pcic_debug) 570 cmn_err(CE_CONT, "pcic_probe: failed\n"); 571 #endif 572 ddi_regs_map_free(&handle); 573 return (DDI_PROBE_FAILURE); 574 } 575 576 /* 577 * These are just defaults they can also be changed via a property in the 578 * conf file. 579 */ 580 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 581 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 582 static int pcic_do_pcmcia_sr = 1; 583 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 584 585 /* 586 * enable insertion/removal interrupt for 32bit cards 587 */ 588 static int 589 cardbus_enable_cd_intr(dev_info_t *dip) 590 { 591 ddi_acc_handle_t iohandle; 592 caddr_t ioaddr; 593 ddi_device_acc_attr_t attr; 594 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 595 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 596 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 597 (void) ddi_regs_map_setup(dip, 1, 598 (caddr_t *)&ioaddr, 599 0, 600 4096, 601 &attr, &iohandle); 602 603 /* CSC Interrupt: Card detect interrupt on */ 604 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 605 ddi_get32(iohandle, 606 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 607 608 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 609 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 610 611 ddi_regs_map_free(&iohandle); 612 return (1); 613 } 614 615 /* 616 * quiesce(9E) entry point. 617 * 618 * This function is called when the system is single-threaded at high 619 * PIL with preemption disabled. Therefore, this function must not be 620 * blocked. 621 * 622 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 623 * DDI_FAILURE indicates an error condition and should almost never happen. 624 */ 625 static int32_t 626 pcic_quiesce(dev_info_t *dip) 627 { 628 anp_t *anp = ddi_get_driver_private(dip); 629 pcicdev_t *pcic = anp->an_private; 630 int i; 631 632 for (i = 0; i < pcic->pc_numsockets; i++) { 633 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 634 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 635 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 636 /* disable interrupts and put card into RESET */ 637 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 638 /* poweroff socket */ 639 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 640 pcic_putcb(pcic, CB_CONTROL, 0); 641 } 642 643 return (DDI_SUCCESS); 644 } 645 646 /* 647 * pcic_attach() 648 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 649 * to the system. This is a child of "sysbus" since that is where 650 * the hardware lives, but it provides services to the "pcmcia" 651 * nexus driver. It gives a pointer back via its private data 652 * structure which contains both the dip and socket services entry 653 * points 654 */ 655 static int 656 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 657 { 658 anp_t *pcic_nexus; 659 pcicdev_t *pcic; 660 int irqlevel, value; 661 int pci_cfrn, pci_ctrn; 662 int i, j, smi, actual; 663 char *typename; 664 char bus_type[16] = "(unknown)"; 665 int len = sizeof (bus_type); 666 ddi_device_acc_attr_t attr; 667 anp_t *anp = ddi_get_driver_private(dip); 668 uint_t pri; 669 670 #if defined(PCIC_DEBUG) 671 if (pcic_debug) { 672 cmn_err(CE_CONT, "pcic_attach: entered\n"); 673 } 674 #endif 675 switch (cmd) { 676 case DDI_ATTACH: 677 break; 678 case DDI_RESUME: 679 pcic = anp->an_private; 680 /* 681 * for now, this is a simulated resume. 682 * a real one may need different things. 683 */ 684 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 685 mutex_enter(&pcic->pc_lock); 686 /* should probe for new sockets showing up */ 687 pcic_setup_adapter(pcic); 688 pcic->pc_flags &= ~PCF_SUSPENDED; 689 mutex_exit(&pcic->pc_lock); 690 (void) pcmcia_begin_resume(dip); 691 692 pcic_do_resume(pcic); 693 #ifdef CARDBUS 694 cardbus_restore_children(ddi_get_child(dip)); 695 #endif 696 697 /* 698 * for complete implementation need END_RESUME (later) 699 */ 700 return (DDI_SUCCESS); 701 702 } 703 return (DDI_SUCCESS); 704 default: 705 return (DDI_FAILURE); 706 } 707 708 /* 709 * Allocate soft state associated with this instance. 710 */ 711 if (ddi_soft_state_zalloc(pcic_soft_state_p, 712 ddi_get_instance(dip)) != DDI_SUCCESS) { 713 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 714 ddi_get_instance(dip)); 715 return (DDI_FAILURE); 716 } 717 718 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 719 ddi_get_instance(dip)); 720 721 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 722 723 pcic->dip = dip; 724 pcic_nexus->an_dip = dip; 725 pcic_nexus->an_if = &pcic_if_ops; 726 pcic_nexus->an_private = pcic; 727 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 728 pcic->pc_power = pcic_power; 729 730 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 731 "pci-control-reg-number", pci_control_reg_num); 732 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 733 "pci-config-reg-number", pci_config_reg_num); 734 735 ddi_set_driver_private(dip, pcic_nexus); 736 737 /* 738 * pcic->pc_irq is really the IPL level we want to run at 739 * set the default values here and override from intr spec 740 */ 741 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 742 "interrupt-priorities", -1); 743 744 if (pcic->pc_irq == -1) { 745 int actual; 746 uint_t pri; 747 ddi_intr_handle_t hdl; 748 749 /* see if intrspec tells us different */ 750 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 751 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 752 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 753 pcic->pc_irq = pri; 754 else 755 pcic->pc_irq = LOCK_LEVEL + 1; 756 (void) ddi_intr_free(hdl); 757 } 758 } 759 pcic_nexus->an_ipl = pcic->pc_irq; 760 761 /* 762 * Check our parent bus type. We do different things based on which 763 * bus we're on. 764 */ 765 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 766 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 767 "device_type", (caddr_t)&bus_type[0], &len) != 768 DDI_PROP_SUCCESS) { 769 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 770 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 771 "bus-type", (caddr_t)&bus_type[0], &len) != 772 DDI_PROP_SUCCESS) { 773 774 cmn_err(CE_CONT, 775 "pcic%d: can't find parent bus type\n", 776 ddi_get_instance(dip)); 777 778 kmem_free(pcic, sizeof (pcicdev_t)); 779 ddi_soft_state_free(pcic_soft_state_p, 780 ddi_get_instance(dip)); 781 return (DDI_FAILURE); 782 } 783 } /* ddi_prop_op("device_type") */ 784 785 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 786 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0) { 787 pcic->pc_flags = PCF_PCIBUS; 788 } else { 789 cmn_err(CE_WARN, "!pcic%d: non-pci mode (%s) not supported, " 790 "set BIOS to yenta mode if applicable\n", 791 ddi_get_instance(dip), bus_type); 792 kmem_free(pcic, sizeof (pcicdev_t)); 793 ddi_soft_state_free(pcic_soft_state_p, 794 ddi_get_instance(dip)); 795 return (DDI_FAILURE); 796 } 797 798 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 799 DDI_PROP_CANSLEEP, 800 "clock-frequency", 0)) == 0) { 801 if (pcic->pc_flags & PCF_PCIBUS) 802 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 803 else 804 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 805 } else { 806 /* 807 * OBP can declare the speed in Hz... 808 */ 809 if (pcic->bus_speed > 1000000) 810 pcic->bus_speed /= 1000000; 811 } /* ddi_prop_op("clock-frequency") */ 812 813 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 814 815 #ifdef PCIC_DEBUG 816 if (pcic_debug) { 817 cmn_err(CE_CONT, 818 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 819 ddi_get_instance(dip), 820 bus_type, pcic->bus_speed); 821 } 822 #endif 823 824 /* 825 * The reg properties on a PCI node are different than those 826 * on a non-PCI node. Handle that difference here. 827 * If it turns out to be a CardBus chip, we have even more 828 * differences. 829 */ 830 if (pcic->pc_flags & PCF_PCIBUS) { 831 int class_code; 832 #if defined(__x86) 833 pcic->pc_base = 0x1000000; 834 pcic->pc_bound = (uint32_t)~0; 835 pcic->pc_iobase = 0x1000; 836 pcic->pc_iobound = 0xefff; 837 #elif defined(__sparc) 838 pcic->pc_base = 0x0; 839 pcic->pc_bound = (uint32_t)~0; 840 pcic->pc_iobase = 0x00000; 841 pcic->pc_iobound = 0xffff; 842 #endif 843 844 /* usually need to get at config space so map first */ 845 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 846 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 847 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 848 849 if (ddi_regs_map_setup(dip, pci_cfrn, 850 (caddr_t *)&pcic->cfgaddr, 851 PCIC_PCI_CONFIG_REG_OFFSET, 852 PCIC_PCI_CONFIG_REG_LENGTH, 853 &attr, 854 &pcic->cfg_handle) != 855 DDI_SUCCESS) { 856 cmn_err(CE_CONT, 857 "pcic%d: unable to map config space" 858 "regs\n", 859 ddi_get_instance(dip)); 860 861 kmem_free(pcic, sizeof (pcicdev_t)); 862 return (DDI_FAILURE); 863 } /* ddi_regs_map_setup */ 864 865 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 866 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 867 "class-code", -1); 868 #ifdef PCIC_DEBUG 869 if (pcic_debug) { 870 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 871 class_code); 872 } 873 #endif 874 875 switch (class_code) { 876 case PCIC_PCI_CARDBUS: 877 pcic->pc_flags |= PCF_CARDBUS; 878 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 879 /* 880 * Get access to the adapter registers on the 881 * PCI bus. A 4K memory page 882 */ 883 #if defined(PCIC_DEBUG) 884 pcic_err(dip, 8, "Is Cardbus device\n"); 885 if (pcic_debug) { 886 int nr; 887 long rs; 888 (void) ddi_dev_nregs(dip, &nr); 889 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 890 "cfghndl 0x%p nregs %d", 891 (void *)pcic->cfgaddr, 892 (void *)pcic->cfg_handle, nr); 893 894 (void) ddi_dev_regsize(dip, 895 PCIC_PCI_CONTROL_REG_NUM, &rs); 896 897 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 898 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 899 } 900 #endif 901 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 902 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 903 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 904 905 if (ddi_regs_map_setup(dip, pci_ctrn, 906 (caddr_t *)&pcic->ioaddr, 907 PCIC_PCI_CONTROL_REG_OFFSET, 908 PCIC_CB_CONTROL_REG_LENGTH, 909 &attr, &pcic->handle) != 910 DDI_SUCCESS) { 911 cmn_err(CE_CONT, 912 "pcic%d: unable to map PCI regs\n", 913 ddi_get_instance(dip)); 914 ddi_regs_map_free(&pcic->cfg_handle); 915 kmem_free(pcic, sizeof (pcicdev_t)); 916 return (DDI_FAILURE); 917 } /* ddi_regs_map_setup */ 918 919 /* 920 * Find out the chip type - If we're on a PCI bus, 921 * the adapter has that information in the PCI 922 * config space. 923 * Note that we call pcic_find_pci_type here since 924 * it needs a valid mapped pcic->handle to 925 * access some of the adapter registers in 926 * some cases. 927 */ 928 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 929 ddi_regs_map_free(&pcic->handle); 930 ddi_regs_map_free(&pcic->cfg_handle); 931 kmem_free(pcic, sizeof (pcicdev_t)); 932 cmn_err(CE_WARN, "pcic: %s: unsupported " 933 "bridge\n", ddi_get_name_addr(dip)); 934 return (DDI_FAILURE); 935 } 936 break; 937 938 default: 939 case PCIC_PCI_PCMCIA: 940 /* 941 * Get access to the adapter IO registers on the 942 * PCI bus config space. 943 */ 944 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 945 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 946 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 947 948 /* 949 * We need a default mapping to the adapter's IO 950 * control register space. For most adapters 951 * that are of class PCIC_PCI_PCMCIA (or of 952 * a default class) the control registers 953 * will be using the 82365-type control/data 954 * format. 955 */ 956 if (ddi_regs_map_setup(dip, pci_ctrn, 957 (caddr_t *)&pcic->ioaddr, 958 PCIC_PCI_CONTROL_REG_OFFSET, 959 PCIC_PCI_CONTROL_REG_LENGTH, 960 &attr, 961 &pcic->handle) != DDI_SUCCESS) { 962 cmn_err(CE_CONT, 963 "pcic%d: unable to map PCI regs\n", 964 ddi_get_instance(dip)); 965 ddi_regs_map_free(&pcic->cfg_handle); 966 kmem_free(pcic, sizeof (pcicdev_t)); 967 return (DDI_FAILURE); 968 } /* ddi_regs_map_setup */ 969 970 /* 971 * Find out the chip type - If we're on a PCI bus, 972 * the adapter has that information in the PCI 973 * config space. 974 * Note that we call pcic_find_pci_type here since 975 * it needs a valid mapped pcic->handle to 976 * access some of the adapter registers in 977 * some cases. 978 */ 979 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 980 ddi_regs_map_free(&pcic->handle); 981 ddi_regs_map_free(&pcic->cfg_handle); 982 kmem_free(pcic, sizeof (pcicdev_t)); 983 cmn_err(CE_WARN, "pcic: %s: unsupported " 984 "bridge\n", 985 ddi_get_name_addr(dip)); 986 return (DDI_FAILURE); 987 } 988 989 /* 990 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 991 * for extended registers even though they are 992 * not CardBus adapters. For those adapters, 993 * re-map pcic->handle to be large enough to 994 * encompass the Yenta registers. 995 */ 996 switch (pcic->pc_type) { 997 case PCIC_TI_PCI1031: 998 ddi_regs_map_free(&pcic->handle); 999 1000 if (ddi_regs_map_setup(dip, 1001 PCIC_PCI_CONTROL_REG_NUM, 1002 (caddr_t *)&pcic->ioaddr, 1003 PCIC_PCI_CONTROL_REG_OFFSET, 1004 PCIC_CB_CONTROL_REG_LENGTH, 1005 &attr, 1006 &pcic->handle) != DDI_SUCCESS) { 1007 cmn_err(CE_CONT, 1008 "pcic%d: unable to map " 1009 "PCI regs\n", 1010 ddi_get_instance(dip)); 1011 ddi_regs_map_free(&pcic->cfg_handle); 1012 kmem_free(pcic, sizeof (pcicdev_t)); 1013 return (DDI_FAILURE); 1014 } /* ddi_regs_map_setup */ 1015 break; 1016 default: 1017 break; 1018 } /* switch (pcic->pc_type) */ 1019 break; 1020 } /* switch (class_code) */ 1021 } else { 1022 /* 1023 * We're not on a PCI bus, so assume an ISA bus type 1024 * register property. Get access to the adapter IO 1025 * registers on a non-PCI bus. 1026 */ 1027 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1028 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 1029 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1030 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 1031 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 1032 1033 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 1034 (caddr_t *)&pcic->ioaddr, 1035 PCIC_ISA_CONTROL_REG_OFFSET, 1036 PCIC_ISA_CONTROL_REG_LENGTH, 1037 &attr, 1038 &pcic->handle) != DDI_SUCCESS) { 1039 cmn_err(CE_CONT, 1040 "pcic%d: unable to map ISA registers\n", 1041 ddi_get_instance(dip)); 1042 1043 kmem_free(pcic, sizeof (pcicdev_t)); 1044 return (DDI_FAILURE); 1045 } /* ddi_regs_map_setup */ 1046 1047 /* ISA bus is limited to 24-bits, but not first 640K */ 1048 pcic->pc_base = 0xd0000; 1049 pcic->pc_bound = (uint32_t)~0; 1050 pcic->pc_iobase = 0x1000; 1051 pcic->pc_iobound = 0xefff; 1052 } /* !PCF_PCIBUS */ 1053 1054 #ifdef PCIC_DEBUG 1055 if (pcic_debug) { 1056 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1057 pcic->pc_flags, pcic->pc_type); 1058 } 1059 #endif 1060 1061 /* 1062 * Setup various adapter registers for the PCI case. For the 1063 * non-PCI case, find out the chip type. 1064 */ 1065 if (pcic->pc_flags & PCF_PCIBUS) { 1066 int iline; 1067 #if defined(__sparc) 1068 iline = 0; 1069 #else 1070 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1071 #endif 1072 1073 /* set flags and socket counts based on chip type */ 1074 switch (pcic->pc_type) { 1075 uint32_t cfg; 1076 case PCIC_INTEL_i82092: 1077 cfg = ddi_get8(pcic->cfg_handle, 1078 pcic->cfgaddr + PCIC_82092_PCICON); 1079 /* we can only support 4 Socket version */ 1080 if (cfg & PCIC_82092_4_SOCKETS) { 1081 pcic->pc_numsockets = 4; 1082 pcic->pc_type = PCIC_INTEL_i82092; 1083 if (iline != 0xFF) 1084 pcic->pc_intr_mode = 1085 PCIC_INTR_MODE_PCI_1; 1086 else 1087 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1088 } else { 1089 cmn_err(CE_CONT, 1090 "pcic%d: Intel 82092 adapter " 1091 "in unsupported configuration: 0x%x", 1092 ddi_get_instance(pcic->dip), cfg); 1093 pcic->pc_numsockets = 0; 1094 } /* PCIC_82092_4_SOCKETS */ 1095 break; 1096 case PCIC_CL_PD6730: 1097 case PCIC_CL_PD6729: 1098 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1099 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1100 DDI_PROP_CANSLEEP, 1101 "interrupts", 0); 1102 /* if not interrupt pin then must use ISA style IRQs */ 1103 if (cfg == 0 || iline == 0xFF) 1104 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1105 else { 1106 /* 1107 * we have the option to use PCI interrupts. 1108 * this might not be optimal but in some cases 1109 * is the only thing possible (sparc case). 1110 * we now deterine what is possible. 1111 */ 1112 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1113 } 1114 pcic->pc_numsockets = 2; 1115 pcic->pc_flags |= PCF_IO_REMAP; 1116 break; 1117 case PCIC_TI_PCI1031: 1118 /* this chip doesn't do CardBus but looks like one */ 1119 pcic->pc_flags &= ~PCF_CARDBUS; 1120 /* FALLTHROUGH */ 1121 default: 1122 pcic->pc_flags |= PCF_IO_REMAP; 1123 /* FALLTHROUGH */ 1124 /* indicate feature even if not supported */ 1125 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1126 /* Not sure if these apply to all these chips */ 1127 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1128 pcic->pc_flags |= pcic_use_cbpwrctl; 1129 1130 pcic->pc_numsockets = 1; /* one per function */ 1131 if (iline != 0xFF) { 1132 uint8_t cfg; 1133 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1134 1135 cfg = ddi_get8(pcic->cfg_handle, 1136 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1137 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1138 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1139 PCIC_BRIDGE_CTL_REG), cfg); 1140 } 1141 else 1142 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1143 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1144 break; 1145 } 1146 } else { 1147 /* 1148 * We're not on a PCI bus so do some more 1149 * checking for adapter type here. 1150 * For the non-PCI bus case: 1151 * It could be any one of a number of different chips 1152 * If we can't determine anything else, it is assumed 1153 * to be an Intel 82365SL. The Cirrus Logic PD6710 1154 * has an extension register that provides unique 1155 * identification. Toshiba chip isn't detailed as yet. 1156 */ 1157 1158 /* Init the CL id mode */ 1159 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1160 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1161 1162 /* default to Intel i82365SL and then refine */ 1163 pcic->pc_type = PCIC_I82365SL; 1164 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1165 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1166 /* go until one succeeds or none left */ 1167 if (pcic_ci_funcs[value](pcic)) 1168 break; 1169 } 1170 1171 /* any chip specific flags get set here */ 1172 switch (pcic->pc_type) { 1173 case PCIC_CL_PD6722: 1174 pcic->pc_flags |= PCF_DMA; 1175 } 1176 1177 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1178 /* 1179 * look for total number of sockets. 1180 * basically check each possible socket for 1181 * presence like in probe 1182 */ 1183 1184 /* turn all windows off */ 1185 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1186 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1187 1188 /* 1189 * if a zero is read back, then this socket 1190 * might be present. It would be except for 1191 * some systems that map the secondary PCIC 1192 * chip space back to the first. 1193 */ 1194 if (value != 0) { 1195 /* definitely not so skip */ 1196 /* note: this is for Compaq support */ 1197 continue; 1198 } 1199 1200 /* further tests */ 1201 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1202 PCIC_REV_MASK; 1203 if (!(value >= PCIC_REV_LEVEL_LOW && 1204 value <= PCIC_REV_LEVEL_HI)) 1205 break; 1206 1207 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1208 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1209 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1210 1211 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1212 if (value != 0xaa || j != 0x55) 1213 break; 1214 1215 /* 1216 * at this point we know if we have hardware 1217 * of some type and not just the bus holding 1218 * a pattern for us. We still have to determine 1219 * the case where more than 2 sockets are 1220 * really the same due to peculiar mappings of 1221 * hardware. 1222 */ 1223 j = pcic->pc_numsockets++; 1224 pcic->pc_sockets[j].pcs_flags = 0; 1225 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1226 pcic->pc_sockets[j].pcs_socket = i; 1227 1228 /* put PC Card into RESET, just in case */ 1229 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1230 pcic_putb(pcic, i, PCIC_INTERRUPT, 1231 value & ~PCIC_RESET); 1232 } 1233 1234 #if defined(PCIC_DEBUG) 1235 if (pcic_debug) 1236 cmn_err(CE_CONT, "num sockets = %d\n", 1237 pcic->pc_numsockets); 1238 #endif 1239 if (pcic->pc_numsockets == 0) { 1240 ddi_regs_map_free(&pcic->handle); 1241 kmem_free(pcic, sizeof (pcicdev_t)); 1242 return (DDI_FAILURE); 1243 } 1244 1245 /* 1246 * need to think this through again in light of 1247 * Compaq not following the model that all the 1248 * chip vendors recommend. IBM 755 seems to be 1249 * afflicted as well. Basically, if the vendor 1250 * wired things wrong, socket 0 responds for socket 2 1251 * accesses, etc. 1252 */ 1253 if (pcic->pc_numsockets > 2) { 1254 int count = pcic->pc_numsockets / 4; 1255 for (i = 0; i < count; i++) { 1256 /* put pattern into socket 0 */ 1257 pcic_putb(pcic, i, 1258 PCIC_SYSMEM_0_STARTLOW, 0x11); 1259 1260 /* put pattern into socket 2 */ 1261 pcic_putb(pcic, i + 2, 1262 PCIC_SYSMEM_0_STARTLOW, 0x33); 1263 1264 /* read back socket 0 */ 1265 value = pcic_getb(pcic, i, 1266 PCIC_SYSMEM_0_STARTLOW); 1267 1268 /* read back chip 1 socket 0 */ 1269 j = pcic_getb(pcic, i + 2, 1270 PCIC_SYSMEM_0_STARTLOW); 1271 if (j == value) { 1272 pcic->pc_numsockets -= 2; 1273 } 1274 } 1275 } 1276 1277 smi = 0xff; /* no more override */ 1278 1279 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1280 DDI_PROP_DONTPASS, "need-mult-irq", 1281 0xffff) != 0xffff) 1282 pcic->pc_flags |= PCF_MULT_IRQ; 1283 1284 } /* !PCF_PCIBUS */ 1285 1286 /* 1287 * some platforms/busses need to have resources setup 1288 * this is temporary until a real resource allocator is 1289 * implemented. 1290 */ 1291 1292 pcic_init_assigned(dip); 1293 1294 typename = pcic->pc_chipname; 1295 1296 #ifdef PCIC_DEBUG 1297 if (pcic_debug) { 1298 int nregs, nintrs; 1299 1300 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1301 nregs = 0; 1302 1303 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1304 nintrs = 0; 1305 1306 cmn_err(CE_CONT, 1307 "pcic%d: %d register sets, %d interrupts\n", 1308 ddi_get_instance(dip), nregs, nintrs); 1309 1310 nintrs = 0; 1311 while (nregs--) { 1312 off_t size; 1313 1314 if (ddi_dev_regsize(dip, nintrs, &size) == 1315 DDI_SUCCESS) { 1316 cmn_err(CE_CONT, 1317 "\tregnum %d size %ld (0x%lx)" 1318 "bytes", 1319 nintrs, size, size); 1320 if (nintrs == 1321 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1322 PCIC_ISA_CONTROL_REG_NUM : 1323 PCIC_PCI_CONTROL_REG_NUM)) 1324 cmn_err(CE_CONT, 1325 " mapped at: 0x%p\n", 1326 (void *)pcic->ioaddr); 1327 else 1328 cmn_err(CE_CONT, "\n"); 1329 } else { 1330 cmn_err(CE_CONT, 1331 "\tddi_dev_regsize(rnumber" 1332 "= %d) returns DDI_FAILURE\n", 1333 nintrs); 1334 } 1335 nintrs++; 1336 } /* while */ 1337 } /* if (pcic_debug) */ 1338 #endif 1339 1340 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1341 1342 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1343 "disable-audio", 0)) 1344 pcic->pc_flags |= PCF_AUDIO; 1345 1346 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1347 "disable-cardbus", 0)) 1348 pcic->pc_flags &= ~PCF_CARDBUS; 1349 1350 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1351 typename); 1352 1353 /* 1354 * Init all socket SMI levels to 0 (no SMI) 1355 */ 1356 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1357 pcic->pc_sockets[i].pcs_smi = 0; 1358 pcic->pc_sockets[i].pcs_debounce_id = 0; 1359 pcic->pc_sockets[i].pcs_pcic = pcic; 1360 } 1361 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1362 1363 /* 1364 * Setup the IRQ handler(s) 1365 */ 1366 switch (pcic->pc_intr_mode) { 1367 int xx; 1368 case PCIC_INTR_MODE_ISA: 1369 /* 1370 * On a non-PCI bus, we just use whatever SMI IRQ level was 1371 * specified above, and the IO IRQ levels are allocated 1372 * dynamically. 1373 */ 1374 for (xx = 15, smi = 0; xx >= 0; xx--) { 1375 if (PCIC_IRQ(xx) & 1376 PCIC_AVAIL_IRQS) { 1377 smi = pcmcia_get_intr(dip, xx); 1378 if (smi >= 0) 1379 break; 1380 } 1381 } 1382 #if defined(PCIC_DEBUG) 1383 if (pcic_debug) 1384 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1385 #endif 1386 /* init to same so share is easy */ 1387 for (i = 0; i < pcic->pc_numsockets; i++) 1388 pcic->pc_sockets[i].pcs_smi = smi; 1389 /* any special handling of IRQ levels */ 1390 if (pcic->pc_flags & PCF_MULT_IRQ) { 1391 for (i = 2; i < pcic->pc_numsockets; i++) { 1392 if ((i & 1) == 0) { 1393 int xx; 1394 for (xx = 15, smi = 0; xx >= 0; xx--) { 1395 if (PCIC_IRQ(xx) & 1396 PCIC_AVAIL_IRQS) { 1397 smi = 1398 pcmcia_get_intr(dip, 1399 xx); 1400 if (smi >= 0) 1401 break; 1402 } 1403 } 1404 } 1405 if (smi >= 0) 1406 pcic->pc_sockets[i].pcs_smi = smi; 1407 } 1408 } 1409 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1410 sizeof (ddi_intr_handle_t), KM_SLEEP); 1411 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1412 struct intrspec *ispecp; 1413 struct ddi_parent_private_data *pdp; 1414 1415 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1416 continue; 1417 else { 1418 irqlevel = pcic->pc_sockets[i].pcs_smi; 1419 } 1420 /* 1421 * now convert the allocated IRQ into an intrspec 1422 * and ask our parent to add it. Don't use 1423 * the ddi_add_intr since we don't have a 1424 * default intrspec in all cases. 1425 * 1426 * note: this sort of violates DDI but we don't 1427 * get hardware intrspecs for many of the devices. 1428 * at the same time, we know how to allocate them 1429 * so we do the right thing. 1430 */ 1431 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1432 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1433 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1434 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1435 ddi_get_name(dip)); 1436 goto isa_exit1; 1437 } 1438 1439 /* 1440 * See earlier note: 1441 * Since some devices don't have 'intrspec' 1442 * we make one up in rootnex. 1443 * 1444 * However, it is not properly initialized as 1445 * the data it needs is present in this driver 1446 * and there is no interface to pass that up. 1447 * Specially 'irqlevel' is very important and 1448 * it is part of pcic struct. 1449 * 1450 * Set 'intrspec' up here; otherwise adding the 1451 * interrupt will fail. 1452 */ 1453 pdp = ddi_get_parent_data(dip); 1454 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1455 ispecp->intrspec_vec = irqlevel; 1456 ispecp->intrspec_pri = pcic->pc_irq; 1457 1458 /* Stay compatible w/ PCMCIA */ 1459 pcic->pc_pri = (ddi_iblock_cookie_t) 1460 (uintptr_t)pcic->pc_irq; 1461 pcic->pc_dcookie.idev_priority = 1462 (uintptr_t)pcic->pc_pri; 1463 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1464 1465 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1466 pcic->pc_irq); 1467 1468 if (i == 0) { 1469 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1470 DDI_INTR_PRI(pcic->pc_irq)); 1471 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1472 NULL); 1473 } 1474 1475 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1476 pcic_intr, (caddr_t)pcic, NULL)) { 1477 cmn_err(CE_WARN, 1478 "%s: ddi_intr_add_handler failed", 1479 ddi_get_name(dip)); 1480 goto isa_exit2; 1481 } 1482 1483 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1484 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1485 ddi_get_name(dip)); 1486 for (j = i; j < 0; j--) 1487 (void) ddi_intr_remove_handler( 1488 pcic->pc_intr_htblp[j]); 1489 goto isa_exit2; 1490 } 1491 } 1492 break; 1493 case PCIC_INTR_MODE_PCI_1: 1494 case PCIC_INTR_MODE_PCI: 1495 /* 1496 * If we're on a PCI bus, we route all interrupts, both SMI 1497 * and IO interrupts, through a single interrupt line. 1498 * Assign the SMI IRQ level to the IO IRQ level here. 1499 */ 1500 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1501 KM_SLEEP); 1502 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1503 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1504 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1505 goto pci_exit1; 1506 1507 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1508 &pri) != DDI_SUCCESS) { 1509 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1510 goto pci_exit1; 1511 } 1512 1513 pcic->pc_pri = (void *)(uintptr_t)pri; 1514 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1515 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1516 1517 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1518 pcic_intr, (caddr_t)pcic, NULL)) 1519 goto pci_exit2; 1520 1521 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1522 (void) ddi_intr_remove_handler( 1523 pcic->pc_pci_intr_hdlp[0]); 1524 goto pci_exit2; 1525 } 1526 1527 /* Stay compatible w/ PCMCIA */ 1528 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1529 1530 /* init to same (PCI) so share is easy */ 1531 for (i = 0; i < pcic->pc_numsockets; i++) 1532 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1533 break; 1534 } 1535 1536 /* 1537 * Setup the adapter hardware to some reasonable defaults. 1538 */ 1539 mutex_enter(&pcic->pc_lock); 1540 /* mark the driver state as attached */ 1541 pcic->pc_flags |= PCF_ATTACHED; 1542 pcic_setup_adapter(pcic); 1543 1544 for (j = 0; j < pcic->pc_numsockets; j++) 1545 if (ddi_intr_add_softint(dip, 1546 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1547 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1548 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1549 goto pci_exit2; 1550 1551 #if defined(PCIC_DEBUG) 1552 if (pcic_debug) 1553 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1554 pcic->pc_numsockets); 1555 #endif 1556 1557 pcic_nexus->an_iblock = &pcic->pc_pri; 1558 pcic_nexus->an_idev = &pcic->pc_dcookie; 1559 1560 mutex_exit(&pcic->pc_lock); 1561 1562 #ifdef CARDBUS 1563 (void) cardbus_enable_cd_intr(dip); 1564 if (pcic_debug) { 1565 1566 cardbus_dump_pci_config(dip); 1567 cardbus_dump_socket(dip); 1568 } 1569 1570 /* 1571 * Give the Cardbus misc module a chance to do it's per-adapter 1572 * instance setup. Note that there is no corresponding detach() 1573 * call. 1574 */ 1575 if (pcic->pc_flags & PCF_CARDBUS) 1576 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1577 cmn_err(CE_CONT, 1578 "pcic_attach: cardbus_attach failed\n"); 1579 goto pci_exit2; 1580 } 1581 #endif 1582 1583 /* 1584 * Give the PCMCIA misc module a chance to do it's per-adapter 1585 * instance setup. 1586 */ 1587 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1588 goto pci_exit2; 1589 1590 if (pcic_maxinst == -1) { 1591 /* This assumes that all instances run at the same IPL. */ 1592 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1593 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1594 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1595 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1596 v.v_maxsyspri - 2); 1597 } 1598 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1599 /* 1600 * Setup a debounce timeout to do an initial card detect 1601 * and enable interrupts. 1602 */ 1603 for (j = 0; j < pcic->pc_numsockets; j++) { 1604 pcic->pc_sockets[j].pcs_debounce_id = 1605 pcic_add_debqueue(&pcic->pc_sockets[j], 1606 drv_usectohz(pcic_debounce_time)); 1607 } 1608 1609 return (i); 1610 1611 isa_exit2: 1612 mutex_destroy(&pcic->intr_lock); 1613 mutex_destroy(&pcic->pc_lock); 1614 for (j = i; j < 0; j--) 1615 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1616 isa_exit1: 1617 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1618 ddi_regs_map_free(&pcic->handle); 1619 if (pcic->pc_flags & PCF_PCIBUS) 1620 ddi_regs_map_free(&pcic->cfg_handle); 1621 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1622 sizeof (ddi_intr_handle_t)); 1623 kmem_free(pcic, sizeof (pcicdev_t)); 1624 return (DDI_FAILURE); 1625 1626 pci_exit2: 1627 mutex_destroy(&pcic->intr_lock); 1628 mutex_destroy(&pcic->pc_lock); 1629 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1630 pci_exit1: 1631 ddi_regs_map_free(&pcic->handle); 1632 if (pcic->pc_flags & PCF_PCIBUS) 1633 ddi_regs_map_free(&pcic->cfg_handle); 1634 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1635 kmem_free(pcic, sizeof (pcicdev_t)); 1636 return (DDI_FAILURE); 1637 } 1638 1639 /* 1640 * pcic_detach() 1641 * request to detach from the system 1642 */ 1643 static int 1644 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1645 { 1646 anp_t *anp = ddi_get_driver_private(dip); 1647 pcicdev_t *pcic = anp->an_private; 1648 int i; 1649 1650 switch (cmd) { 1651 case DDI_DETACH: 1652 /* don't detach if the nexus still talks to us */ 1653 if (pcic->pc_callback != NULL) 1654 return (DDI_FAILURE); 1655 1656 /* kill off the pm simulation */ 1657 if (pcic->pc_pmtimer) 1658 (void) untimeout(pcic->pc_pmtimer); 1659 1660 /* turn everything off for all sockets and chips */ 1661 for (i = 0; i < pcic->pc_numsockets; i++) { 1662 if (pcic->pc_sockets[i].pcs_debounce_id) 1663 pcic_rm_debqueue( 1664 pcic->pc_sockets[i].pcs_debounce_id); 1665 pcic->pc_sockets[i].pcs_debounce_id = 0; 1666 1667 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1668 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1669 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1670 /* disable interrupts and put card into RESET */ 1671 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1672 } 1673 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1674 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1675 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1676 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1677 pcic->pc_flags = 0; 1678 mutex_destroy(&pcic->pc_lock); 1679 mutex_destroy(&pcic->intr_lock); 1680 cv_destroy(&pcic->pm_cv); 1681 if (pcic->pc_flags & PCF_PCIBUS) 1682 ddi_regs_map_free(&pcic->cfg_handle); 1683 if (pcic->handle) 1684 ddi_regs_map_free(&pcic->handle); 1685 kmem_free(pcic, sizeof (pcicdev_t)); 1686 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1687 return (DDI_SUCCESS); 1688 1689 case DDI_SUSPEND: 1690 case DDI_PM_SUSPEND: 1691 /* 1692 * we got a suspend event (either real or imagined) 1693 * so notify the nexus proper that all existing cards 1694 * should go away. 1695 */ 1696 mutex_enter(&pcic->pc_lock); 1697 #ifdef CARDBUS 1698 if (pcic->pc_flags & PCF_CARDBUS) { 1699 for (i = 0; i < pcic->pc_numsockets; i++) { 1700 if ((pcic->pc_sockets[i].pcs_flags & 1701 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1702 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) { 1703 1704 pcmcia_cb_suspended( 1705 pcic->pc_sockets[i].pcs_socket); 1706 } 1707 } 1708 1709 cardbus_save_children(ddi_get_child(dip)); 1710 } 1711 #endif 1712 /* turn everything off for all sockets and chips */ 1713 for (i = 0; i < pcic->pc_numsockets; i++) { 1714 if (pcic->pc_sockets[i].pcs_debounce_id) 1715 pcic_rm_debqueue( 1716 pcic->pc_sockets[i].pcs_debounce_id); 1717 pcic->pc_sockets[i].pcs_debounce_id = 0; 1718 1719 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1720 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1721 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1722 /* disable interrupts and put card into RESET */ 1723 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1724 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1725 if (pcic->pc_flags & PCF_CBPWRCTL) 1726 pcic_putcb(pcic, CB_CONTROL, 0); 1727 1728 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1729 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1730 /* 1731 * Because we are half way through a save 1732 * all this does is schedule a removal event 1733 * to cs for when the system comes back. 1734 * This doesn't actually matter. 1735 */ 1736 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1737 pcic->pc_callback) { 1738 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1739 PCE_CARD_REMOVAL, 1740 pcic->pc_sockets[i].pcs_socket); 1741 } 1742 } 1743 } 1744 1745 pcic->pc_flags |= PCF_SUSPENDED; 1746 mutex_exit(&pcic->pc_lock); 1747 1748 /* 1749 * when true power management exists, save the adapter 1750 * state here to enable a recovery. For the emulation 1751 * condition, the state is gone 1752 */ 1753 return (DDI_SUCCESS); 1754 1755 default: 1756 return (EINVAL); 1757 } 1758 } 1759 1760 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1761 static uint32_t pcic_tisysctl_offbits = 0; 1762 static uint32_t pcic_default_latency = 0x40; 1763 1764 static void 1765 pcic_setup_adapter(pcicdev_t *pcic) 1766 { 1767 int i; 1768 int value, flags; 1769 1770 #if defined(__x86) 1771 pci_regspec_t *reg; 1772 uchar_t bus, dev, func; 1773 uint_t classcode; 1774 int length; 1775 #endif 1776 1777 if (pcic->pc_flags & PCF_PCIBUS) { 1778 /* 1779 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1780 */ 1781 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1782 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1783 } 1784 /* enable each socket */ 1785 for (i = 0; i < pcic->pc_numsockets; i++) { 1786 pcic->pc_sockets[i].pcs_flags = 0; 1787 /* find out the socket capabilities (I/O vs memory) */ 1788 value = pcic_getb(pcic, i, 1789 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1790 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1791 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1792 1793 /* disable all windows just in case */ 1794 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1795 1796 switch (pcic->pc_type) { 1797 uint32_t cfg32; 1798 uint16_t cfg16; 1799 uint8_t cfg; 1800 1801 /* enable extended registers for Vadem */ 1802 case PCIC_VADEM_VG469: 1803 case PCIC_VADEM: 1804 1805 /* enable card status change interrupt for socket */ 1806 break; 1807 1808 case PCIC_I82365SL: 1809 break; 1810 1811 case PCIC_CL_PD6710: 1812 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1813 break; 1814 1815 /* 1816 * On the CL_6730, we need to set up the interrupt 1817 * signalling mode (PCI mode) and set the SMI and 1818 * IRQ interrupt lines to PCI/level-mode. 1819 */ 1820 case PCIC_CL_PD6730: 1821 switch (pcic->pc_intr_mode) { 1822 case PCIC_INTR_MODE_PCI_1: 1823 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1824 ((clext_reg_read(pcic, i, 1825 PCIC_CLEXT_MISC_CTL_3) & 1826 ~PCIC_CLEXT_INT_PCI) | 1827 PCIC_CLEXT_INT_PCI)); 1828 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1829 (PCIC_CLEXT_IRQ_LVL_MODE | 1830 PCIC_CLEXT_SMI_LVL_MODE)); 1831 cfg = PCIC_CL_LP_DYN_MODE; 1832 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1833 break; 1834 case PCIC_INTR_MODE_ISA: 1835 break; 1836 } 1837 break; 1838 /* 1839 * On the CL_6729, we set the SMI and IRQ interrupt 1840 * lines to PCI/level-mode. as well as program the 1841 * correct clock speed divider bit. 1842 */ 1843 case PCIC_CL_PD6729: 1844 switch (pcic->pc_intr_mode) { 1845 case PCIC_INTR_MODE_PCI_1: 1846 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1847 (PCIC_CLEXT_IRQ_LVL_MODE | 1848 PCIC_CLEXT_SMI_LVL_MODE)); 1849 1850 break; 1851 case PCIC_INTR_MODE_ISA: 1852 break; 1853 } 1854 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1855 cfg = 0; 1856 cfg |= PCIC_CL_TIMER_CLK_DIV; 1857 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1858 } 1859 break; 1860 case PCIC_INTEL_i82092: 1861 cfg = PCIC_82092_EN_TIMING; 1862 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1863 cfg |= PCIC_82092_PCICLK_25MHZ; 1864 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1865 PCIC_82092_PCICON, cfg); 1866 break; 1867 case PCIC_TI_PCI1130: 1868 case PCIC_TI_PCI1131: 1869 case PCIC_TI_PCI1250: 1870 case PCIC_TI_PCI1031: 1871 cfg = ddi_get8(pcic->cfg_handle, 1872 pcic->cfgaddr + PCIC_DEVCTL_REG); 1873 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1874 switch (pcic->pc_intr_mode) { 1875 case PCIC_INTR_MODE_ISA: 1876 cfg |= PCIC_DEVCTL_INTR_ISA; 1877 break; 1878 } 1879 #ifdef PCIC_DEBUG 1880 if (pcic_debug) { 1881 cmn_err(CE_CONT, "pcic_setup_adapter: " 1882 "write reg 0x%x=%x \n", 1883 PCIC_DEVCTL_REG, cfg); 1884 } 1885 #endif 1886 ddi_put8(pcic->cfg_handle, 1887 pcic->cfgaddr + PCIC_DEVCTL_REG, 1888 cfg); 1889 1890 cfg = ddi_get8(pcic->cfg_handle, 1891 pcic->cfgaddr + PCIC_CRDCTL_REG); 1892 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1893 PCIC_CRDCTL_PCIFUNC); 1894 switch (pcic->pc_intr_mode) { 1895 case PCIC_INTR_MODE_PCI_1: 1896 cfg |= PCIC_CRDCTL_PCIINTR | 1897 PCIC_CRDCTL_PCICSC | 1898 PCIC_CRDCTL_PCIFUNC; 1899 pcic->pc_flags |= PCF_USE_SMI; 1900 break; 1901 } 1902 #ifdef PCIC_DEBUG 1903 if (pcic_debug) { 1904 cmn_err(CE_CONT, "pcic_setup_adapter: " 1905 " write reg 0x%x=%x \n", 1906 PCIC_CRDCTL_REG, cfg); 1907 } 1908 #endif 1909 ddi_put8(pcic->cfg_handle, 1910 pcic->cfgaddr + PCIC_CRDCTL_REG, 1911 cfg); 1912 break; 1913 case PCIC_TI_PCI1221: 1914 case PCIC_TI_PCI1225: 1915 cfg = ddi_get8(pcic->cfg_handle, 1916 pcic->cfgaddr + PCIC_DEVCTL_REG); 1917 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1918 #ifdef PCIC_DEBUG 1919 if (pcic_debug) { 1920 cmn_err(CE_CONT, "pcic_setup_adapter: " 1921 " write reg 0x%x=%x \n", 1922 PCIC_DEVCTL_REG, cfg); 1923 } 1924 #endif 1925 ddi_put8(pcic->cfg_handle, 1926 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1927 1928 cfg = ddi_get8(pcic->cfg_handle, 1929 pcic->cfgaddr + PCIC_DIAG_REG); 1930 if (pcic->pc_type == PCIC_TI_PCI1225) { 1931 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1932 } else { 1933 cfg |= PCIC_DIAG_ASYNC; 1934 } 1935 pcic->pc_flags |= PCF_USE_SMI; 1936 #ifdef PCIC_DEBUG 1937 if (pcic_debug) { 1938 cmn_err(CE_CONT, "pcic_setup_adapter: " 1939 " write reg 0x%x=%x \n", 1940 PCIC_DIAG_REG, cfg); 1941 } 1942 #endif 1943 ddi_put8(pcic->cfg_handle, 1944 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1945 break; 1946 case PCIC_TI_PCI1520: 1947 case PCIC_TI_PCI1510: 1948 case PCIC_TI_VENDOR: 1949 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1950 /* functional intr routed by ExCA register */ 1951 cfg = ddi_get8(pcic->cfg_handle, 1952 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1953 cfg |= PCIC_FUN_INT_MOD_ISA; 1954 ddi_put8(pcic->cfg_handle, 1955 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1956 cfg); 1957 1958 /* IRQ serialized interrupts */ 1959 cfg = ddi_get8(pcic->cfg_handle, 1960 pcic->cfgaddr + PCIC_DEVCTL_REG); 1961 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1962 cfg |= PCIC_DEVCTL_INTR_ISA; 1963 ddi_put8(pcic->cfg_handle, 1964 pcic->cfgaddr + PCIC_DEVCTL_REG, 1965 cfg); 1966 break; 1967 } 1968 1969 /* CSC interrupt routed to PCI */ 1970 cfg = ddi_get8(pcic->cfg_handle, 1971 pcic->cfgaddr + PCIC_DIAG_REG); 1972 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1973 ddi_put8(pcic->cfg_handle, 1974 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1975 1976 #if defined(__x86) 1977 /* 1978 * Some TI chips have 2 cardbus slots(function0 and 1979 * function1), and others may have just 1 cardbus slot. 1980 * The interrupt routing register is shared between the 1981 * 2 functions and can only be accessed through 1982 * function0. Here we check the presence of the second 1983 * cardbus slot and do the right thing. 1984 */ 1985 1986 if (ddi_getlongprop(DDI_DEV_T_ANY, pcic->dip, 1987 DDI_PROP_DONTPASS, "reg", (caddr_t)®, 1988 &length) != DDI_PROP_SUCCESS) { 1989 cmn_err(CE_WARN, 1990 "pcic_setup_adapter(), failed to" 1991 " read reg property\n"); 1992 break; 1993 } 1994 1995 bus = PCI_REG_BUS_G(reg->pci_phys_hi); 1996 dev = PCI_REG_DEV_G(reg->pci_phys_hi); 1997 func = PCI_REG_FUNC_G(reg->pci_phys_hi); 1998 kmem_free((caddr_t)reg, length); 1999 2000 if (func != 0) { 2001 break; 2002 } 2003 2004 classcode = (*pci_getl_func)(bus, dev, 1, 2005 PCI_CONF_REVID); 2006 classcode >>= 8; 2007 if (classcode != 0x060700 && 2008 classcode != 0x060500) { 2009 break; 2010 } 2011 2012 /* Parallel PCI interrupts only */ 2013 cfg = ddi_get8(pcic->cfg_handle, 2014 pcic->cfgaddr + PCIC_DEVCTL_REG); 2015 cfg &= ~PCIC_DEVCTL_INTR_MASK; 2016 ddi_put8(pcic->cfg_handle, 2017 pcic->cfgaddr + PCIC_DEVCTL_REG, 2018 cfg); 2019 2020 /* tie INTA and INTB together */ 2021 cfg = ddi_get8(pcic->cfg_handle, 2022 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 2023 cfg |= PCIC_SYSCTL_INTRTIE; 2024 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 2025 PCIC_SYSCTL_REG + 3), cfg); 2026 #endif 2027 2028 break; 2029 case PCIC_TI_PCI1410: 2030 cfg = ddi_get8(pcic->cfg_handle, 2031 pcic->cfgaddr + PCIC_DIAG_REG); 2032 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2033 ddi_put8(pcic->cfg_handle, 2034 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2035 break; 2036 case PCIC_TOSHIBA_TOPIC100: 2037 case PCIC_TOSHIBA_TOPIC95: 2038 case PCIC_TOSHIBA_VENDOR: 2039 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2040 PCIC_TOSHIBA_SLOT_CTL_REG); 2041 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 2042 PCIC_TOSHIBA_SCR_SLOTEN); 2043 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 2044 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 2045 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 2046 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 2047 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2048 PCIC_TOSHIBA_INTR_CTL_REG); 2049 switch (pcic->pc_intr_mode) { 2050 case PCIC_INTR_MODE_ISA: 2051 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 2052 ddi_put8(pcic->cfg_handle, 2053 pcic->cfgaddr + 2054 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2055 2056 cfg = ddi_get8(pcic->cfg_handle, 2057 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2058 cfg |= PCIC_FUN_INT_MOD_ISA; 2059 ddi_put8(pcic->cfg_handle, 2060 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2061 cfg); 2062 break; 2063 case PCIC_INTR_MODE_PCI_1: 2064 cfg |= PCIC_TOSHIBA_ICR_SRC; 2065 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 2066 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 2067 ddi_put8(pcic->cfg_handle, 2068 pcic->cfgaddr + 2069 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2070 break; 2071 } 2072 break; 2073 case PCIC_O2MICRO_VENDOR: 2074 cfg32 = ddi_get32(pcic->cfg_handle, 2075 (uint32_t *)(pcic->cfgaddr + 2076 PCIC_O2MICRO_MISC_CTL)); 2077 switch (pcic->pc_intr_mode) { 2078 case PCIC_INTR_MODE_ISA: 2079 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 2080 PCIC_O2MICRO_INT_MOD_PCI); 2081 ddi_put32(pcic->cfg_handle, 2082 (uint32_t *)(pcic->cfgaddr + 2083 PCIC_O2MICRO_MISC_CTL), 2084 cfg32); 2085 cfg = ddi_get8(pcic->cfg_handle, 2086 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2087 cfg |= PCIC_FUN_INT_MOD_ISA; 2088 ddi_put8(pcic->cfg_handle, 2089 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2090 cfg); 2091 break; 2092 case PCIC_INTR_MODE_PCI_1: 2093 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2094 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2095 ddi_put32(pcic->cfg_handle, 2096 (uint32_t *)(pcic->cfgaddr + 2097 PCIC_O2MICRO_MISC_CTL), 2098 cfg32); 2099 break; 2100 } 2101 break; 2102 case PCIC_RICOH_VENDOR: 2103 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2104 cfg16 = ddi_get16(pcic->cfg_handle, 2105 (uint16_t *)(pcic->cfgaddr + 2106 PCIC_RICOH_MISC_CTL_2)); 2107 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2108 PCIC_RICOH_FUN_INT_MOD); 2109 ddi_put16(pcic->cfg_handle, 2110 (uint16_t *)(pcic->cfgaddr + 2111 PCIC_RICOH_MISC_CTL_2), 2112 cfg16); 2113 2114 cfg16 = ddi_get16(pcic->cfg_handle, 2115 (uint16_t *)(pcic->cfgaddr + 2116 PCIC_RICOH_MISC_CTL)); 2117 cfg16 |= PCIC_RICOH_SIRQ_EN; 2118 ddi_put16(pcic->cfg_handle, 2119 (uint16_t *)(pcic->cfgaddr + 2120 PCIC_RICOH_MISC_CTL), 2121 cfg16); 2122 2123 cfg = ddi_get8(pcic->cfg_handle, 2124 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2125 cfg |= PCIC_FUN_INT_MOD_ISA; 2126 ddi_put8(pcic->cfg_handle, 2127 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2128 cfg); 2129 } 2130 break; 2131 default: 2132 break; 2133 } /* switch */ 2134 2135 /* 2136 * The default value in the EEPROM (loaded on reset) for 2137 * MFUNC0/MFUNC1 may be incorrect. Here we make sure that 2138 * MFUNC0 is connected to INTA, and MFUNC1 is connected to 2139 * INTB. This applies to all TI CardBus controllers. 2140 */ 2141 if ((pcic->pc_type >> 16) == PCIC_TI_VENDORID && 2142 pcic->pc_intr_mode == PCIC_INTR_MODE_PCI_1) { 2143 value = ddi_get32(pcic->cfg_handle, 2144 (uint32_t *)(pcic->cfgaddr + PCIC_MFROUTE_REG)); 2145 value &= ~0xff; 2146 ddi_put32(pcic->cfg_handle, (uint32_t *)(pcic->cfgaddr + 2147 PCIC_MFROUTE_REG), value|PCIC_TI_MFUNC_SEL); 2148 } 2149 2150 /* setup general card status change interrupt */ 2151 switch (pcic->pc_type) { 2152 case PCIC_TI_PCI1225: 2153 case PCIC_TI_PCI1221: 2154 case PCIC_TI_PCI1031: 2155 case PCIC_TI_PCI1520: 2156 case PCIC_TI_PCI1410: 2157 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2158 PCIC_CHANGE_DEFAULT); 2159 break; 2160 default: 2161 if (pcic->pc_intr_mode == 2162 PCIC_INTR_MODE_PCI_1) { 2163 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2164 PCIC_CHANGE_DEFAULT); 2165 break; 2166 } else { 2167 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2168 PCIC_CHANGE_DEFAULT | 2169 (pcic->pc_sockets[i].pcs_smi << 4)); 2170 break; 2171 } 2172 } 2173 2174 pcic->pc_flags |= PCF_INTRENAB; 2175 2176 /* take card out of RESET */ 2177 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2178 /* turn power off and let CS do this */ 2179 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2180 2181 /* final chip specific initialization */ 2182 switch (pcic->pc_type) { 2183 case PCIC_VADEM: 2184 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2185 PCIC_VC_DELAYENABLE); 2186 pcic->pc_flags |= PCF_DEBOUNCE; 2187 /* FALLTHROUGH */ 2188 case PCIC_I82365SL: 2189 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2190 PCIC_GC_CSC_WRITE); 2191 /* clear any pending interrupts */ 2192 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2193 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2194 break; 2195 /* The 82092 uses PCI config space to enable interrupts */ 2196 case PCIC_INTEL_i82092: 2197 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2198 PCIC_82092_INT_ENABLE); 2199 break; 2200 case PCIC_CL_PD6729: 2201 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2202 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2203 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2204 value | PCIC_CL_TIMER_CLK_DIV); 2205 } 2206 break; 2207 } /* switch */ 2208 2209 #if defined(PCIC_DEBUG) 2210 if (pcic_debug) 2211 cmn_err(CE_CONT, 2212 "socket %d value=%x, flags = %x (%s)\n", 2213 i, value, pcic->pc_sockets[i].pcs_flags, 2214 (pcic->pc_sockets[i].pcs_flags & 2215 PCS_CARD_PRESENT) ? 2216 "card present" : "no card"); 2217 #endif 2218 } 2219 } 2220 2221 /* 2222 * pcic_intr(caddr_t, caddr_t) 2223 * interrupt handler for the PCIC style adapter 2224 * handles all basic interrupts and also checks 2225 * for status changes and notifies the nexus if 2226 * necessary 2227 * 2228 * On PCI bus adapters, also handles all card 2229 * IO interrupts. 2230 */ 2231 /*ARGSUSED*/ 2232 uint32_t 2233 pcic_intr(caddr_t arg1, caddr_t arg2) 2234 { 2235 pcicdev_t *pcic = (pcicdev_t *)arg1; 2236 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2237 uint8_t status; 2238 uint_t io_ints; 2239 2240 #if defined(PCIC_DEBUG) 2241 pcic_err(pcic->dip, 0xf, 2242 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2243 " pc_numsockets=%d \n", 2244 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2245 #endif 2246 2247 if (!(pcic->pc_flags & PCF_ATTACHED)) 2248 return (DDI_INTR_UNCLAIMED); 2249 2250 mutex_enter(&pcic->intr_lock); 2251 2252 if (pcic->pc_flags & PCF_SUSPENDED) { 2253 mutex_exit(&pcic->intr_lock); 2254 return (ret); 2255 } 2256 2257 /* 2258 * need to change to only ACK and touch the slot that 2259 * actually caused the interrupt. Currently everything 2260 * is acked 2261 * 2262 * we need to look at all known sockets to determine 2263 * what might have happened, so step through the list 2264 * of them 2265 */ 2266 2267 /* 2268 * Set the bitmask for IO interrupts to initially include all sockets 2269 */ 2270 io_ints = (1 << pcic->pc_numsockets) - 1; 2271 2272 for (i = 0; i < pcic->pc_numsockets; i++) { 2273 int card_type; 2274 pcic_socket_t *sockp; 2275 int value_cb = 0; 2276 2277 sockp = &pcic->pc_sockets[i]; 2278 /* get the socket's I/O addresses */ 2279 2280 if (sockp->pcs_flags & PCS_WAITING) { 2281 io_ints &= ~(1 << i); 2282 continue; 2283 } 2284 2285 if (sockp->pcs_flags & PCS_CARD_IO) 2286 card_type = IF_IO; 2287 else 2288 card_type = IF_MEMORY; 2289 2290 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2291 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2292 2293 value = pcic_change(pcic, i); 2294 2295 if ((value != 0) || (value_cb != 0)) { 2296 int x = pcic->pc_cb_arg; 2297 2298 ret = DDI_INTR_CLAIMED; 2299 2300 #if defined(PCIC_DEBUG) 2301 pcic_err(pcic->dip, 0x9, 2302 "card_type = %d, value_cb = 0x%x\n", 2303 card_type, 2304 value_cb ? value_cb : 2305 pcic_getcb(pcic, CB_STATUS_EVENT)); 2306 if (pcic_debug) 2307 cmn_err(CE_CONT, 2308 "\tchange on socket %d (%x)\n", i, 2309 value); 2310 #endif 2311 /* find out what happened */ 2312 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2313 2314 /* acknowledge the interrupt */ 2315 if (value_cb) 2316 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2317 2318 if (value) 2319 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2320 value); 2321 2322 if (pcic->pc_callback == NULL) { 2323 /* if not callback handler, nothing to do */ 2324 continue; 2325 } 2326 2327 /* Card Detect */ 2328 if (value & PCIC_CD_DETECT || 2329 value_cb & CB_PS_CCDMASK) { 2330 uint8_t irq; 2331 #if defined(PCIC_DEBUG) 2332 if (pcic_debug) 2333 cmn_err(CE_CONT, 2334 "\tcd_detect: status=%x," 2335 " flags=%x\n", 2336 status, sockp->pcs_flags); 2337 #else 2338 #ifdef lint 2339 if (status == 0) 2340 status++; 2341 #endif 2342 #endif 2343 /* 2344 * Turn off all interrupts for this socket here. 2345 */ 2346 irq = pcic_getb(pcic, sockp->pcs_socket, 2347 PCIC_MANAGEMENT_INT); 2348 irq &= ~PCIC_CHANGE_MASK; 2349 pcic_putb(pcic, sockp->pcs_socket, 2350 PCIC_MANAGEMENT_INT, irq); 2351 2352 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2353 2354 /* 2355 * Put the socket in debouncing state so that 2356 * the leaf driver won't receive interrupts. 2357 * Crucial for handling surprise-removal. 2358 */ 2359 sockp->pcs_flags |= PCS_DEBOUNCING; 2360 2361 if (!sockp->pcs_cd_softint_flg) { 2362 sockp->pcs_cd_softint_flg = 1; 2363 (void) ddi_intr_trigger_softint( 2364 sockp->pcs_cd_softint_hdl, NULL); 2365 } 2366 2367 io_ints &= ~(1 << i); 2368 } /* PCIC_CD_DETECT */ 2369 2370 /* Ready/Change Detect */ 2371 sockp->pcs_state ^= SBM_RDYBSY; 2372 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2373 sockp->pcs_flags |= PCS_READY; 2374 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2375 } 2376 2377 /* Battery Warn Detect */ 2378 if (card_type == IF_MEMORY && 2379 value & PCIC_BW_DETECT && 2380 !(sockp->pcs_state & SBM_BVD2)) { 2381 sockp->pcs_state |= SBM_BVD2; 2382 PC_CALLBACK(pcic->dip, x, 2383 PCE_CARD_BATTERY_WARN, i); 2384 } 2385 2386 /* Battery Dead Detect */ 2387 if (value & PCIC_BD_DETECT) { 2388 /* 2389 * need to work out event if RI not enabled 2390 * and card_type == IF_IO 2391 */ 2392 if (card_type == IF_MEMORY && 2393 !(sockp->pcs_state & SBM_BVD1)) { 2394 sockp->pcs_state |= SBM_BVD1; 2395 PC_CALLBACK(pcic->dip, x, 2396 PCE_CARD_BATTERY_DEAD, 2397 i); 2398 } else { 2399 /* 2400 * information in pin replacement 2401 * register if one is available 2402 */ 2403 PC_CALLBACK(pcic->dip, x, 2404 PCE_CARD_STATUS_CHANGE, 2405 i); 2406 } /* IF_MEMORY */ 2407 } /* PCIC_BD_DETECT */ 2408 } /* if pcic_change */ 2409 /* 2410 * for any controllers that we can detect whether a socket 2411 * had an interrupt for the PC Card, we should sort that out 2412 * here. 2413 */ 2414 } /* for pc_numsockets */ 2415 2416 /* 2417 * If we're on a PCI bus, we may need to cycle through each IO 2418 * interrupt handler that is registered since they all 2419 * share the same interrupt line. 2420 */ 2421 2422 2423 #if defined(PCIC_DEBUG) 2424 pcic_err(pcic->dip, 0xf, 2425 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2426 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2427 #endif 2428 2429 if (io_ints) { 2430 if (pcic_do_io_intr(pcic, io_ints) == DDI_INTR_CLAIMED) 2431 ret = DDI_INTR_CLAIMED; 2432 } 2433 2434 mutex_exit(&pcic->intr_lock); 2435 2436 #if defined(PCIC_DEBUG) 2437 pcic_err(pcic->dip, 0xf, 2438 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2439 ret, value, DDI_INTR_CLAIMED); 2440 #endif 2441 2442 return (ret); 2443 } 2444 2445 /* 2446 * pcic_change() 2447 * check to see if this socket had a change in state 2448 * by checking the status change register 2449 */ 2450 static int 2451 pcic_change(pcicdev_t *pcic, int socket) 2452 { 2453 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2454 } 2455 2456 /* 2457 * pcic_do_io_intr - calls client interrupt handlers 2458 */ 2459 static int 2460 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2461 { 2462 inthandler_t *tmp; 2463 int ret = DDI_INTR_UNCLAIMED; 2464 2465 #if defined(PCIC_DEBUG) 2466 pcic_err(pcic->dip, 0xf, 2467 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2468 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2469 #endif 2470 2471 if (pcic->irq_top != NULL) { 2472 tmp = pcic->irq_current; 2473 2474 do { 2475 int cur = pcic->irq_current->socket; 2476 pcic_socket_t *sockp = 2477 &pcic->pc_sockets[cur]; 2478 2479 #if defined(PCIC_DEBUG) 2480 pcic_err(pcic->dip, 0xf, 2481 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2482 sockp->pcs_flags, PCS_CARD_PRESENT); 2483 pcic_err(pcic->dip, 0xf, 2484 "\t sockets=%d cur=%d intr=%p arg1=%p " 2485 "arg2=%p\n", 2486 sockets, cur, (void *)pcic->irq_current->intr, 2487 pcic->irq_current->arg1, 2488 pcic->irq_current->arg2); 2489 #endif 2490 if ((sockp->pcs_flags & PCS_CARD_PRESENT) && 2491 !(sockp->pcs_flags & PCS_DEBOUNCING) && 2492 (sockets & (1 << cur))) { 2493 2494 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2495 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2496 ret = DDI_INTR_CLAIMED; 2497 2498 #if defined(PCIC_DEBUG) 2499 pcic_err(pcic->dip, 0xf, 2500 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2501 ret, DDI_INTR_CLAIMED); 2502 #endif 2503 } 2504 2505 2506 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2507 pcic->irq_current = pcic->irq_top; 2508 2509 } while (pcic->irq_current != tmp); 2510 2511 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2512 pcic->irq_current = pcic->irq_top; 2513 2514 } else { 2515 ret = DDI_INTR_UNCLAIMED; 2516 } 2517 2518 #if defined(PCIC_DEBUG) 2519 pcic_err(pcic->dip, 0xf, 2520 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2521 ret, DDI_INTR_CLAIMED); 2522 #endif 2523 2524 return (ret); 2525 2526 } 2527 2528 /* 2529 * pcic_inquire_adapter() 2530 * SocketServices InquireAdapter function 2531 * get characteristics of the physical adapter 2532 */ 2533 /*ARGSUSED*/ 2534 static int 2535 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2536 { 2537 anp_t *anp = ddi_get_driver_private(dip); 2538 pcicdev_t *pcic = anp->an_private; 2539 2540 config->NumSockets = pcic->pc_numsockets; 2541 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2542 config->NumEDCs = 0; 2543 config->AdpCaps = 0; 2544 config->ActiveHigh = 0; 2545 config->ActiveLow = PCIC_AVAIL_IRQS; 2546 config->NumPower = pcic->pc_numpower; 2547 config->power_entry = pcic->pc_power; /* until we resolve this */ 2548 #if defined(PCIC_DEBUG) 2549 if (pcic_debug) { 2550 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2551 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2552 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2553 } 2554 #endif 2555 config->ResourceFlags = 0; 2556 switch (pcic->pc_intr_mode) { 2557 case PCIC_INTR_MODE_PCI_1: 2558 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2559 RES_IRQ_SHAREABLE; 2560 break; 2561 } 2562 return (SUCCESS); 2563 } 2564 2565 /* 2566 * pcic_callback() 2567 * The PCMCIA nexus calls us via this function 2568 * in order to set the callback function we are 2569 * to call the nexus with 2570 */ 2571 /*ARGSUSED*/ 2572 static int 2573 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2574 { 2575 anp_t *anp = ddi_get_driver_private(dip); 2576 pcicdev_t *pcic = anp->an_private; 2577 2578 if (handler != NULL) { 2579 pcic->pc_callback = handler; 2580 pcic->pc_cb_arg = arg; 2581 pcic->pc_flags |= PCF_CALLBACK; 2582 } else { 2583 pcic->pc_callback = NULL; 2584 pcic->pc_cb_arg = 0; 2585 pcic->pc_flags &= ~PCF_CALLBACK; 2586 } 2587 /* 2588 * we're now registered with the nexus 2589 * it is acceptable to do callbacks at this point. 2590 * don't call back from here though since it could block 2591 */ 2592 return (PC_SUCCESS); 2593 } 2594 2595 /* 2596 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2597 * calculate the speed bits from the specified memory speed 2598 * there may be more to do here 2599 */ 2600 2601 static int 2602 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2603 { 2604 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2605 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2606 2607 switch (pcic->pc_type) { 2608 case PCIC_I82365SL: 2609 case PCIC_VADEM: 2610 case PCIC_VADEM_VG469: 2611 default: 2612 /* Intel chip wants it in waitstates */ 2613 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2614 if (speed <= wspeed) 2615 wspeed = 0; 2616 else if (speed <= (wspeed += mhztons(bspeed))) 2617 wspeed = 1; 2618 else if (speed <= (wspeed += mhztons(bspeed))) 2619 wspeed = 2; 2620 else 2621 wspeed = 3; 2622 wspeed <<= 6; /* put in right bit positions */ 2623 break; 2624 2625 case PCIC_INTEL_i82092: 2626 wspeed = SYSMEM_82092_80NS; 2627 if (speed > 80) 2628 wspeed = SYSMEM_82092_100NS; 2629 if (speed > 100) 2630 wspeed = SYSMEM_82092_150NS; 2631 if (speed > 150) 2632 wspeed = SYSMEM_82092_200NS; 2633 if (speed > 200) 2634 wspeed = SYSMEM_82092_250NS; 2635 if (speed > 250) 2636 wspeed = SYSMEM_82092_600NS; 2637 wspeed <<= 5; /* put in right bit positions */ 2638 break; 2639 2640 } /* switch */ 2641 2642 return (wspeed); 2643 } 2644 2645 /* 2646 * These values are taken from the PC Card Standard Electrical Specification. 2647 * Generally the larger value is taken if 2 are possible. 2648 */ 2649 static struct pcic_card_times { 2650 uint16_t cycle; /* Speed as found in the atribute space of the card. */ 2651 uint16_t setup; /* Corresponding address setup time. */ 2652 uint16_t width; /* Corresponding width, OE or WE. */ 2653 uint16_t hold; /* Corresponding data or address hold time. */ 2654 } pcic_card_times[] = { 2655 2656 /* 2657 * Note: The rounded up times for 250, 200 & 150 have been increased 2658 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2659 * See BugID 00663. 2660 */ 2661 2662 /* 2663 * Rounded up times Original times from 2664 * that add up to the the PCMCIA Spec. 2665 * cycle time. 2666 */ 2667 {600, 180, 370, 140}, /* 100, 300, 70 */ 2668 {400, 120, 300, 90}, /* Made this one up */ 2669 {250, 100, 190, 70}, /* 30, 150, 30 */ 2670 {200, 80, 170, 70}, /* 20, 120, 30 */ 2671 {150, 50, 110, 40}, /* 20, 80, 20 */ 2672 {100, 40, 80, 40}, /* 10, 60, 15 */ 2673 {0, 10, 60, 15} /* 10, 60, 15 */ 2674 }; 2675 2676 /* 2677 * pcic_set_cdtimers 2678 * This is specific to several Cirrus Logic chips 2679 */ 2680 static void 2681 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2682 { 2683 int cmd, set, rec, offset, clk_pulse; 2684 struct pcic_card_times *ctp; 2685 2686 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2687 offset = 3; 2688 else 2689 offset = 0; 2690 2691 clk_pulse = mhztons(pcic->bus_speed); 2692 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++) 2693 ; 2694 2695 /* 2696 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2697 */ 2698 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2699 if (set < 0) 2700 set = 0; 2701 2702 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2703 if (cmd < 0) 2704 cmd = 0; 2705 2706 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2707 if (rec < 0) 2708 rec = 0; 2709 2710 #if defined(PCIC_DEBUG) 2711 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2712 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2713 (unsigned)speed, offset == 3 ? 1 : 0, 2714 ctp->cycle, clk_pulse, cmd, set, rec); 2715 #endif 2716 2717 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2718 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2719 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2720 } 2721 2722 /* 2723 * pcic_set_window 2724 * essentially the same as the Socket Services specification 2725 * We use socket and not adapter since they are identifiable 2726 * but the rest is the same 2727 * 2728 * dip pcic driver's device information 2729 * window parameters for the request 2730 */ 2731 static int 2732 pcic_set_window(dev_info_t *dip, set_window_t *window) 2733 { 2734 anp_t *anp = ddi_get_driver_private(dip); 2735 pcicdev_t *pcic = anp->an_private; 2736 int select; 2737 int socket, pages, which, ret; 2738 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2739 ra_return_t res; 2740 ndi_ra_request_t req; 2741 uint32_t base = window->base; 2742 2743 #if defined(PCIC_DEBUG) 2744 if (pcic_debug) { 2745 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2746 cmn_err(CE_CONT, 2747 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2748 window->window, window->socket, window->WindowSize, 2749 window->speed); 2750 cmn_err(CE_CONT, 2751 "\tbase=%x, state=%x\n", (unsigned)window->base, 2752 (unsigned)window->state); 2753 } 2754 #endif 2755 2756 /* 2757 * do some basic sanity checking on what we support 2758 * we don't do paged mode 2759 */ 2760 if (window->state & WS_PAGED) { 2761 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2762 return (BAD_ATTRIBUTE); 2763 } 2764 2765 /* 2766 * we don't care about previous mappings. 2767 * Card Services will deal with that so don't 2768 * even check 2769 */ 2770 2771 socket = window->socket; 2772 2773 if (!(window->state & WS_IO)) { 2774 int win, tmp; 2775 pcs_memwin_t *memp; 2776 #if defined(PCIC_DEBUG) 2777 if (pcic_debug) 2778 cmn_err(CE_CONT, "\twindow type is memory\n"); 2779 #endif 2780 /* this is memory window mapping */ 2781 win = window->window % PCIC_NUMWINSOCK; 2782 tmp = window->window / PCIC_NUMWINSOCK; 2783 2784 /* only windows 2-6 can do memory mapping */ 2785 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2786 cmn_err(CE_CONT, 2787 "\tattempt to map to non-mem window\n"); 2788 return (BAD_WINDOW); 2789 } 2790 2791 if (window->WindowSize == 0) 2792 window->WindowSize = MEM_MIN; 2793 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2794 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2795 return (BAD_SIZE); 2796 } 2797 2798 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2799 2800 memp = &sockp->pcs_windows[win].mem; 2801 memp->pcw_speed = window->speed; 2802 2803 win -= PCIC_IOWINDOWS; /* put in right range */ 2804 2805 if (window->WindowSize != memp->pcw_len) 2806 which = memp->pcw_len; 2807 else 2808 which = 0; 2809 2810 if (window->state & WS_ENABLED) { 2811 uint32_t wspeed; 2812 #if defined(PCIC_DEBUG) 2813 if (pcic_debug) { 2814 cmn_err(CE_CONT, 2815 "\tbase=%x, win=%d\n", (unsigned)base, 2816 win); 2817 if (which) 2818 cmn_err(CE_CONT, 2819 "\tneed to remap window\n"); 2820 } 2821 #endif 2822 2823 if (which && (memp->pcw_status & PCW_MAPPED)) { 2824 ddi_regs_map_free(&memp->pcw_handle); 2825 res.ra_addr_lo = memp->pcw_base; 2826 res.ra_len = memp->pcw_len; 2827 (void) pcmcia_free_mem(memp->res_dip, &res); 2828 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2829 memp->pcw_hostmem = NULL; 2830 memp->pcw_base = 0; 2831 memp->pcw_len = 0; 2832 } 2833 2834 which = window->WindowSize >> PAGE_SHIFT; 2835 2836 if (!(memp->pcw_status & PCW_MAPPED)) { 2837 ret = 0; 2838 2839 memp->pcw_base = base; 2840 bzero(&req, sizeof (req)); 2841 req.ra_len = which << PAGE_SHIFT; 2842 req.ra_addr = (uint64_t)memp->pcw_base; 2843 req.ra_boundbase = pcic->pc_base; 2844 req.ra_boundlen = pcic->pc_bound; 2845 req.ra_flags = (memp->pcw_base ? 2846 NDI_RA_ALLOC_SPECIFIED : 0) | 2847 NDI_RA_ALLOC_BOUNDED; 2848 req.ra_align_mask = 2849 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2850 #if defined(PCIC_DEBUG) 2851 pcic_err(dip, 8, 2852 "\tlen 0x%"PRIx64 2853 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2854 " blen 0x%"PRIx64" flags 0x%x" 2855 " algn 0x%"PRIx64"\n", 2856 req.ra_len, req.ra_addr, 2857 req.ra_boundbase, 2858 req.ra_boundlen, req.ra_flags, 2859 req.ra_align_mask); 2860 #endif 2861 2862 ret = pcmcia_alloc_mem(dip, &req, &res, 2863 &memp->res_dip); 2864 if (ret == DDI_FAILURE) { 2865 mutex_exit(&pcic->pc_lock); 2866 cmn_err(CE_WARN, 2867 "\tpcmcia_alloc_mem() failed\n"); 2868 return (BAD_SIZE); 2869 } 2870 memp->pcw_base = res.ra_addr_lo; 2871 base = memp->pcw_base; 2872 2873 #if defined(PCIC_DEBUG) 2874 if (pcic_debug) 2875 cmn_err(CE_CONT, 2876 "\tsetwindow: new base=%x\n", 2877 (unsigned)memp->pcw_base); 2878 #endif 2879 memp->pcw_len = window->WindowSize; 2880 2881 which = pcmcia_map_reg(pcic->dip, 2882 window->child, 2883 &res, 2884 (uint32_t)(window->state & 2885 0xffff) | 2886 (window->socket << 16), 2887 (caddr_t *)&memp->pcw_hostmem, 2888 &memp->pcw_handle, 2889 &window->attr, 0); 2890 2891 if (which != DDI_SUCCESS) { 2892 2893 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2894 "failed\n"); 2895 2896 res.ra_addr_lo = memp->pcw_base; 2897 res.ra_len = memp->pcw_len; 2898 (void) pcmcia_free_mem(memp->res_dip, 2899 &res); 2900 2901 mutex_exit(&pcic->pc_lock); 2902 2903 return (BAD_WINDOW); 2904 } 2905 memp->pcw_status |= PCW_MAPPED; 2906 #if defined(PCIC_DEBUG) 2907 if (pcic_debug) 2908 cmn_err(CE_CONT, 2909 "\tmap=%x, hostmem=%p\n", 2910 which, 2911 (void *)memp->pcw_hostmem); 2912 #endif 2913 } else { 2914 base = memp->pcw_base; 2915 } 2916 2917 /* report the handle back to caller */ 2918 window->handle = memp->pcw_handle; 2919 2920 #if defined(PCIC_DEBUG) 2921 if (pcic_debug) { 2922 cmn_err(CE_CONT, 2923 "\twindow mapped to %x@%x len=%d\n", 2924 (unsigned)window->base, 2925 (unsigned)memp->pcw_base, 2926 memp->pcw_len); 2927 } 2928 #endif 2929 2930 /* find the register set offset */ 2931 select = win * PCIC_MEM_1_OFFSET; 2932 #if defined(PCIC_DEBUG) 2933 if (pcic_debug) 2934 cmn_err(CE_CONT, "\tselect=%x\n", select); 2935 #endif 2936 2937 /* 2938 * at this point, the register window indicator has 2939 * been converted to be an offset from the first 2940 * set of registers that are used for programming 2941 * the window mapping and the offset used to select 2942 * the correct set of registers to access the 2943 * specified socket. This allows basing everything 2944 * off the _0 window 2945 */ 2946 2947 /* map the physical page base address */ 2948 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2949 which |= (window->speed <= MEM_SPEED_MIN) ? 2950 SYSMEM_ZERO_WAIT : 0; 2951 2952 /* need to select register set */ 2953 select = PCIC_MEM_1_OFFSET * win; 2954 2955 pcic_putb(pcic, socket, 2956 PCIC_SYSMEM_0_STARTLOW + select, 2957 SYSMEM_LOW(base)); 2958 pcic_putb(pcic, socket, 2959 PCIC_SYSMEM_0_STARTHI + select, 2960 SYSMEM_HIGH(base) | which); 2961 2962 /* 2963 * Some adapters can decode window addresses greater 2964 * than 16-bits worth, so handle them here. 2965 */ 2966 switch (pcic->pc_type) { 2967 case PCIC_INTEL_i82092: 2968 pcic_putb(pcic, socket, 2969 PCIC_82092_CPAGE, 2970 SYSMEM_EXT(base)); 2971 break; 2972 case PCIC_CL_PD6729: 2973 case PCIC_CL_PD6730: 2974 clext_reg_write(pcic, socket, 2975 PCIC_CLEXT_MMAP0_UA + win, 2976 SYSMEM_EXT(base)); 2977 break; 2978 case PCIC_TI_PCI1130: 2979 /* 2980 * Note that the TI chip has one upper byte 2981 * per socket so all windows get bound to a 2982 * 16MB segment. This must be detected and 2983 * handled appropriately. We can detect that 2984 * it is done by seeing if the pc_base has 2985 * changed and changing when the register 2986 * is first set. This will force the bounds 2987 * to be correct. 2988 */ 2989 if (pcic->pc_bound == 0xffffffff) { 2990 pcic_putb(pcic, socket, 2991 PCIC_TI_WINDOW_PAGE_PCI, 2992 SYSMEM_EXT(base)); 2993 pcic->pc_base = SYSMEM_EXT(base) << 24; 2994 pcic->pc_bound = 0x1000000; 2995 } 2996 break; 2997 case PCIC_TI_PCI1031: 2998 case PCIC_TI_PCI1131: 2999 case PCIC_TI_PCI1250: 3000 case PCIC_TI_PCI1225: 3001 case PCIC_TI_PCI1221: 3002 case PCIC_SMC_34C90: 3003 case PCIC_CL_PD6832: 3004 case PCIC_RICOH_RL5C466: 3005 case PCIC_TI_PCI1410: 3006 case PCIC_ENE_1410: 3007 case PCIC_TI_PCI1510: 3008 case PCIC_TI_PCI1520: 3009 case PCIC_O2_OZ6912: 3010 case PCIC_TI_PCI1420: 3011 case PCIC_ENE_1420: 3012 case PCIC_TI_VENDOR: 3013 case PCIC_TOSHIBA_TOPIC100: 3014 case PCIC_TOSHIBA_TOPIC95: 3015 case PCIC_TOSHIBA_VENDOR: 3016 case PCIC_RICOH_VENDOR: 3017 case PCIC_O2MICRO_VENDOR: 3018 pcic_putb(pcic, socket, 3019 PCIC_YENTA_MEM_PAGE + win, 3020 SYSMEM_EXT(base)); 3021 break; 3022 default: 3023 cmn_err(CE_NOTE, "pcic_set_window: unknown " 3024 "cardbus vendor:0x%X\n", 3025 pcic->pc_type); 3026 pcic_putb(pcic, socket, 3027 PCIC_YENTA_MEM_PAGE + win, 3028 SYSMEM_EXT(base)); 3029 3030 break; 3031 } /* switch */ 3032 3033 /* 3034 * specify the length of the mapped range 3035 * we convert to pages (rounding up) so that 3036 * the hardware gets the right thing 3037 */ 3038 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 3039 3040 /* 3041 * Setup this window's timing. 3042 */ 3043 switch (pcic->pc_type) { 3044 case PCIC_CL_PD6729: 3045 case PCIC_CL_PD6730: 3046 case PCIC_CL_PD6710: 3047 case PCIC_CL_PD6722: 3048 wspeed = SYSMEM_CLTIMER_SET_0; 3049 pcic_set_cdtimers(pcic, socket, 3050 window->speed, 3051 wspeed); 3052 break; 3053 3054 case PCIC_INTEL_i82092: 3055 default: 3056 wspeed = pcic_calc_speed(pcic, window->speed); 3057 break; 3058 } /* switch */ 3059 3060 #if defined(PCIC_DEBUG) 3061 if (pcic_debug) 3062 cmn_err(CE_CONT, 3063 "\twindow %d speed bits = %x for " 3064 "%dns\n", 3065 win, (unsigned)wspeed, window->speed); 3066 #endif 3067 3068 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 3069 SYSMEM_LOW(base + 3070 (pages * PCIC_PAGE)-1)); 3071 3072 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 3073 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 3074 wspeed); 3075 3076 /* 3077 * now map the card's memory pages - we start with page 3078 * 0 3079 * we also default to AM -- set page might change it 3080 */ 3081 base = memp->pcw_base; 3082 pcic_putb(pcic, socket, 3083 PCIC_CARDMEM_0_LOW + select, 3084 CARDMEM_LOW(0 - (uint32_t)base)); 3085 3086 pcic_putb(pcic, socket, 3087 PCIC_CARDMEM_0_HI + select, 3088 CARDMEM_HIGH(0 - (uint32_t)base) | 3089 CARDMEM_REG_ACTIVE); 3090 3091 /* 3092 * enable the window even though redundant 3093 * and SetPage may do it again. 3094 */ 3095 select = pcic_getb(pcic, socket, 3096 PCIC_MAPPING_ENABLE); 3097 select |= SYSMEM_WINDOW(win); 3098 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3099 memp->pcw_offset = 0; 3100 memp->pcw_status |= PCW_ENABLED; 3101 } else { 3102 /* 3103 * not only do we unmap the memory, the 3104 * window has been turned off. 3105 */ 3106 if (which && memp->pcw_status & PCW_MAPPED) { 3107 ddi_regs_map_free(&memp->pcw_handle); 3108 res.ra_addr_lo = memp->pcw_base; 3109 res.ra_len = memp->pcw_len; 3110 (void) pcmcia_free_mem(memp->res_dip, &res); 3111 memp->pcw_hostmem = NULL; 3112 memp->pcw_status &= ~PCW_MAPPED; 3113 } 3114 3115 /* disable current mapping */ 3116 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3117 select &= ~SYSMEM_WINDOW(win); 3118 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3119 memp->pcw_status &= ~PCW_ENABLED; 3120 } 3121 memp->pcw_len = window->WindowSize; 3122 window->handle = memp->pcw_handle; 3123 #if defined(PCIC_DEBUG) 3124 if (pcic_debug) 3125 xxdmp_all_regs(pcic, window->socket, -1); 3126 #endif 3127 } else { 3128 /* 3129 * This is a request for an IO window 3130 */ 3131 int win, tmp; 3132 pcs_iowin_t *winp; 3133 /* I/O windows */ 3134 #if defined(PCIC_DEBUG) 3135 if (pcic_debug) 3136 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3137 #endif 3138 3139 /* only windows 0 and 1 can do I/O */ 3140 win = window->window % PCIC_NUMWINSOCK; 3141 tmp = window->window / PCIC_NUMWINSOCK; 3142 3143 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3144 cmn_err(CE_WARN, 3145 "\twindow is out of range (%d)\n", 3146 window->window); 3147 return (BAD_WINDOW); 3148 } 3149 3150 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3151 3152 winp = &sockp->pcs_windows[win].io; 3153 winp->pcw_speed = window->speed; 3154 if (window->WindowSize != 1 && window->WindowSize & 1) { 3155 /* we don't want an odd-size window */ 3156 window->WindowSize++; 3157 } 3158 winp->pcw_len = window->WindowSize; 3159 3160 if (window->state & WS_ENABLED) { 3161 if (winp->pcw_status & PCW_MAPPED) { 3162 ddi_regs_map_free(&winp->pcw_handle); 3163 res.ra_addr_lo = winp->pcw_base; 3164 res.ra_len = winp->pcw_len; 3165 (void) pcmcia_free_io(winp->res_dip, &res); 3166 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3167 } 3168 3169 /* 3170 * if the I/O address wasn't allocated, allocate 3171 * it now. If it was allocated, it better 3172 * be free to use. 3173 * The winp->pcw_offset value is set and used 3174 * later on if the particular adapter 3175 * that we're running on has the ability 3176 * to translate IO accesses to the card 3177 * (such as some adapters in the Cirrus 3178 * Logic family). 3179 */ 3180 winp->pcw_offset = 0; 3181 3182 /* 3183 * Setup the request parameters for the 3184 * requested base and length. If 3185 * we're on an adapter that has 3186 * IO window offset registers, then 3187 * we don't need a specific base 3188 * address, just a length, and then 3189 * we'll cause the correct IO address 3190 * to be generated on the socket by 3191 * setting up the IO window offset 3192 * registers. 3193 * For adapters that support this capability, we 3194 * always use the IO window offset registers, 3195 * even if the passed base/length would be in 3196 * range. 3197 */ 3198 base = window->base; 3199 bzero(&req, sizeof (req)); 3200 req.ra_len = window->WindowSize; 3201 3202 req.ra_addr = (uint64_t) 3203 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3204 req.ra_flags = (req.ra_addr) ? 3205 NDI_RA_ALLOC_SPECIFIED : 0; 3206 3207 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3208 /* need to rethink this */ 3209 req.ra_boundbase = pcic->pc_iobase; 3210 req.ra_boundlen = pcic->pc_iobound; 3211 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3212 3213 #if defined(PCIC_DEBUG) 3214 pcic_err(dip, 8, 3215 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3216 "bbase 0x%"PRIx64 3217 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3218 PRIx64"\n", 3219 req.ra_len, (uint64_t)req.ra_addr, 3220 req.ra_boundbase, 3221 req.ra_boundlen, req.ra_flags, 3222 req.ra_align_mask); 3223 #endif 3224 3225 /* 3226 * Try to allocate the space. If we fail this, 3227 * return the appropriate error depending 3228 * on whether the caller specified a 3229 * specific base address or not. 3230 */ 3231 if (pcmcia_alloc_io(dip, &req, &res, 3232 &winp->res_dip) == DDI_FAILURE) { 3233 winp->pcw_status &= ~PCW_ENABLED; 3234 mutex_exit(&pcic->pc_lock); 3235 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3236 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3237 "bbase 0x%" PRIx64 3238 "blen 0x%" PRIx64 "flags 0x%x" 3239 "algn 0x%" PRIx64 "\n", 3240 req.ra_len, req.ra_addr, 3241 req.ra_boundbase, 3242 req.ra_boundlen, req.ra_flags, 3243 req.ra_align_mask); 3244 3245 return (base?BAD_BASE:BAD_SIZE); 3246 } /* pcmcia_alloc_io */ 3247 3248 /* 3249 * Don't change the original base. Either we use 3250 * the offset registers below (PCF_IO_REMAP is set) 3251 * or it was allocated correctly anyway. 3252 */ 3253 winp->pcw_base = res.ra_addr_lo; 3254 3255 #if defined(PCIC_DEBUG) 3256 pcic_err(dip, 8, 3257 "\tsetwindow: new base=%x orig base 0x%x\n", 3258 (unsigned)winp->pcw_base, base); 3259 #endif 3260 3261 if ((which = pcmcia_map_reg(pcic->dip, 3262 window->child, 3263 &res, 3264 (uint32_t)(window->state & 3265 0xffff) | 3266 (window->socket << 16), 3267 (caddr_t *)&winp->pcw_hostmem, 3268 &winp->pcw_handle, 3269 &window->attr, 3270 base)) != DDI_SUCCESS) { 3271 3272 cmn_err(CE_WARN, "pcmcia_map_reg()" 3273 "failed\n"); 3274 3275 res.ra_addr_lo = winp->pcw_base; 3276 res.ra_len = winp->pcw_len; 3277 (void) pcmcia_free_io(winp->res_dip, 3278 &res); 3279 3280 mutex_exit(&pcic->pc_lock); 3281 return (BAD_WINDOW); 3282 } 3283 3284 window->handle = winp->pcw_handle; 3285 winp->pcw_status |= PCW_MAPPED; 3286 3287 /* find the register set offset */ 3288 select = win * PCIC_IO_OFFSET; 3289 3290 #if defined(PCIC_DEBUG) 3291 if (pcic_debug) { 3292 cmn_err(CE_CONT, 3293 "\tenable: window=%d, select=%x, " 3294 "base=%x, handle=%p\n", 3295 win, select, 3296 (unsigned)window->base, 3297 (void *)window->handle); 3298 } 3299 #endif 3300 /* 3301 * at this point, the register window indicator has 3302 * been converted to be an offset from the first 3303 * set of registers that are used for programming 3304 * the window mapping and the offset used to select 3305 * the correct set of registers to access the 3306 * specified socket. This allows basing everything 3307 * off the _0 window 3308 */ 3309 3310 /* map the I/O base in */ 3311 pcic_putb(pcic, socket, 3312 PCIC_IO_ADDR_0_STARTLOW + select, 3313 LOW_BYTE((uint32_t)winp->pcw_base)); 3314 pcic_putb(pcic, socket, 3315 PCIC_IO_ADDR_0_STARTHI + select, 3316 HIGH_BYTE((uint32_t)winp->pcw_base)); 3317 3318 pcic_putb(pcic, socket, 3319 PCIC_IO_ADDR_0_STOPLOW + select, 3320 LOW_BYTE((uint32_t)winp->pcw_base + 3321 window->WindowSize - 1)); 3322 pcic_putb(pcic, socket, 3323 PCIC_IO_ADDR_0_STOPHI + select, 3324 HIGH_BYTE((uint32_t)winp->pcw_base + 3325 window->WindowSize - 1)); 3326 3327 /* 3328 * We've got the requested IO space, now see if we 3329 * need to adjust the IO window offset registers 3330 * so that the correct IO address is generated 3331 * at the socket. If this window doesn't have 3332 * this capability, then we're all done setting 3333 * up the IO resources. 3334 */ 3335 if (pcic->pc_flags & PCF_IO_REMAP) { 3336 3337 3338 /* 3339 * Note that only 16 bits are used to program 3340 * the registers but leave 32 bits on pcw_offset 3341 * so that we can generate the original base 3342 * in get_window() 3343 */ 3344 winp->pcw_offset = (base - winp->pcw_base); 3345 3346 pcic_putb(pcic, socket, 3347 PCIC_IO_OFFSET_LOW + 3348 (win * PCIC_IO_OFFSET_OFFSET), 3349 winp->pcw_offset & 0x0ff); 3350 pcic_putb(pcic, socket, 3351 PCIC_IO_OFFSET_HI + 3352 (win * PCIC_IO_OFFSET_OFFSET), 3353 (winp->pcw_offset >> 8) & 0x0ff); 3354 3355 } /* PCF_IO_REMAP */ 3356 3357 /* now get the other details (size, etc) right */ 3358 3359 /* 3360 * Set the data size control bits here. Most of the 3361 * adapters will ignore IOMEM_16BIT when 3362 * IOMEM_IOCS16 is set, except for the Intel 3363 * 82092, which only pays attention to the 3364 * IOMEM_16BIT bit. Sigh... Intel can't even 3365 * make a proper clone of their own chip. 3366 * The 82092 also apparently can't set the timing 3367 * of I/O windows. 3368 */ 3369 which = (window->state & WS_16BIT) ? 3370 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3371 3372 switch (pcic->pc_type) { 3373 case PCIC_CL_PD6729: 3374 case PCIC_CL_PD6730: 3375 case PCIC_CL_PD6710: 3376 case PCIC_CL_PD6722: 3377 case PCIC_CL_PD6832: 3378 /* 3379 * Select Timer Set 1 - this will take 3380 * effect when the PCIC_IO_CONTROL 3381 * register is written to later on; 3382 * the call to pcic_set_cdtimers 3383 * just sets up the timer itself. 3384 */ 3385 which |= IOMEM_CLTIMER_SET_1; 3386 pcic_set_cdtimers(pcic, socket, 3387 window->speed, 3388 IOMEM_CLTIMER_SET_1); 3389 which |= IOMEM_IOCS16; 3390 break; 3391 case PCIC_TI_PCI1031: 3392 3393 if (window->state & WS_16BIT) 3394 which |= IOMEM_WAIT16; 3395 3396 break; 3397 case PCIC_TI_PCI1130: 3398 3399 if (window->state & WS_16BIT) 3400 which |= IOMEM_WAIT16; 3401 3402 break; 3403 case PCIC_INTEL_i82092: 3404 break; 3405 default: 3406 if (window->speed > 3407 mhztons(pcic->bus_speed) * 3) 3408 which |= IOMEM_WAIT16; 3409 #ifdef notdef 3410 if (window->speed < 3411 mhztons(pcic->bus_speed) * 6) 3412 which |= IOMEM_ZERO_WAIT; 3413 #endif 3414 break; 3415 } /* switch (pc_type) */ 3416 3417 /* 3418 * Setup the data width and timing 3419 */ 3420 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3421 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3422 select |= IOMEM_SETWIN(win, which); 3423 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3424 3425 /* 3426 * Enable the IO window 3427 */ 3428 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3429 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3430 select | IOMEM_WINDOW(win)); 3431 3432 winp->pcw_status |= PCW_ENABLED; 3433 3434 #if defined(PCIC_DEBUG) 3435 if (pcic_debug) { 3436 cmn_err(CE_CONT, 3437 "\twhich = %x, select = %x (%x)\n", 3438 which, select, 3439 IOMEM_SETWIN(win, which)); 3440 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3441 } 3442 #endif 3443 } else { 3444 /* 3445 * not only do we unmap the IO space, the 3446 * window has been turned off. 3447 */ 3448 if (winp->pcw_status & PCW_MAPPED) { 3449 ddi_regs_map_free(&winp->pcw_handle); 3450 res.ra_addr_lo = winp->pcw_base; 3451 res.ra_len = winp->pcw_len; 3452 (void) pcmcia_free_io(winp->res_dip, &res); 3453 winp->pcw_status &= ~PCW_MAPPED; 3454 } 3455 3456 /* disable current mapping */ 3457 select = pcic_getb(pcic, socket, 3458 PCIC_MAPPING_ENABLE); 3459 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3460 select &= ~IOMEM_WINDOW(win)); 3461 winp->pcw_status &= ~PCW_ENABLED; 3462 3463 winp->pcw_base = 0; 3464 winp->pcw_len = 0; 3465 winp->pcw_offset = 0; 3466 window->base = 0; 3467 /* now make sure we don't accidentally re-enable */ 3468 /* find the register set offset */ 3469 select = win * PCIC_IO_OFFSET; 3470 pcic_putb(pcic, socket, 3471 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3472 pcic_putb(pcic, socket, 3473 PCIC_IO_ADDR_0_STARTHI + select, 0); 3474 pcic_putb(pcic, socket, 3475 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3476 pcic_putb(pcic, socket, 3477 PCIC_IO_ADDR_0_STOPHI + select, 0); 3478 } 3479 } 3480 mutex_exit(&pcic->pc_lock); 3481 3482 return (SUCCESS); 3483 } 3484 3485 /* 3486 * pcic_card_state() 3487 * compute the instantaneous Card State information 3488 */ 3489 static int 3490 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3491 { 3492 int value, result; 3493 #if defined(PCIC_DEBUG) 3494 int orig_value; 3495 #endif 3496 3497 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3498 3499 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3500 3501 #if defined(PCIC_DEBUG) 3502 orig_value = value; 3503 if (pcic_debug >= 8) 3504 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3505 (void *)sockp, 3506 value, 3507 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3508 sockp->pcs_socket); 3509 #endif 3510 /* 3511 * Lie to socket services if we are not ready. 3512 * This is when we are starting up or during debounce timeouts 3513 * or if the card is a cardbus card. 3514 */ 3515 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3516 !sockp->pcs_debounce_id && 3517 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3518 result = SBM_CD; 3519 3520 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3521 result |= SBM_WP; 3522 if (value & PCIC_POWER_ON) { 3523 if (value & PCIC_READY) 3524 result |= SBM_RDYBSY; 3525 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3526 if (value & PCIC_BVD1) 3527 result |= SBM_BVD1; 3528 if (value & PCIC_BVD2) 3529 result |= SBM_BVD2; 3530 } 3531 } else 3532 result = 0; 3533 3534 mutex_exit(&pcic->pc_lock); 3535 3536 #if defined(PCIC_DEBUG) 3537 pcic_err(pcic->dip, 8, 3538 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3539 (void *) sockp, orig_value, 3540 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3541 sockp->pcs_socket, result); 3542 #endif 3543 3544 return (result); 3545 } 3546 3547 /* 3548 * pcic_set_page() 3549 * SocketServices SetPage function 3550 * set the page of PC Card memory that should be in the mapped 3551 * window 3552 */ 3553 /*ARGSUSED*/ 3554 static int 3555 pcic_set_page(dev_info_t *dip, set_page_t *page) 3556 { 3557 anp_t *anp = ddi_get_driver_private(dip); 3558 pcicdev_t *pcic = anp->an_private; 3559 int select; 3560 int which, socket, window; 3561 uint32_t base; 3562 pcs_memwin_t *memp; 3563 3564 /* get real socket/window numbers */ 3565 window = page->window % PCIC_NUMWINSOCK; 3566 socket = page->window / PCIC_NUMWINSOCK; 3567 3568 #if defined(PCIC_DEBUG) 3569 if (pcic_debug) { 3570 cmn_err(CE_CONT, 3571 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3572 window, socket, page->page); 3573 } 3574 #endif 3575 /* only windows 2-6 work on memory */ 3576 if (window < PCIC_IOWINDOWS) 3577 return (BAD_WINDOW); 3578 3579 /* only one page supported (but any size) */ 3580 if (page->page != 0) 3581 return (BAD_PAGE); 3582 3583 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3584 3585 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3586 window -= PCIC_IOWINDOWS; 3587 3588 #if defined(PCIC_DEBUG) 3589 if (pcic_debug) 3590 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3591 (uint32_t)memp->pcw_base, 3592 (void *)memp->pcw_hostmem, memp->pcw_len); 3593 #endif 3594 3595 /* window must be enabled */ 3596 if (!(memp->pcw_status & PCW_ENABLED)) 3597 return (BAD_ATTRIBUTE); 3598 3599 /* find the register set offset */ 3600 select = window * PCIC_MEM_1_OFFSET; 3601 #if defined(PCIC_DEBUG) 3602 if (pcic_debug) 3603 cmn_err(CE_CONT, "\tselect=%x\n", select); 3604 #endif 3605 3606 /* 3607 * now map the card's memory pages - we start with page 0 3608 */ 3609 3610 which = 0; /* assume simple case */ 3611 if (page->state & PS_ATTRIBUTE) { 3612 which |= CARDMEM_REG_ACTIVE; 3613 memp->pcw_status |= PCW_ATTRIBUTE; 3614 } else { 3615 memp->pcw_status &= ~PCW_ATTRIBUTE; 3616 } 3617 3618 /* 3619 * if caller says Write Protect, enforce it. 3620 */ 3621 if (page->state & PS_WP) { 3622 which |= CARDMEM_WRITE_PROTECT; 3623 memp->pcw_status |= PCW_WP; 3624 } else { 3625 memp->pcw_status &= ~PCW_WP; 3626 } 3627 #if defined(PCIC_DEBUG) 3628 if (pcic_debug) { 3629 cmn_err(CE_CONT, "\tmemory type = %s\n", 3630 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3631 if (which & CARDMEM_WRITE_PROTECT) 3632 cmn_err(CE_CONT, "\twrite protect\n"); 3633 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3634 (unsigned)page->offset, 3635 (unsigned)memp->pcw_base, 3636 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3637 } 3638 #endif 3639 /* address computation based on 64MB range and not larger */ 3640 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3641 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3642 CARDMEM_LOW((int)page->offset - (int)base)); 3643 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3644 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3645 CARDMEM_HIGH((int)page->offset - base) | which); 3646 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3647 3648 /* 3649 * while not really necessary, this just makes sure 3650 * nothing turned the window off behind our backs 3651 */ 3652 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3653 which |= SYSMEM_WINDOW(window); 3654 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3655 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3656 3657 memp->pcw_offset = (off_t)page->offset; 3658 3659 #if defined(PCIC_DEBUG) 3660 if (pcic_debug) { 3661 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3662 (void *)memp->pcw_hostmem, 3663 (uint32_t)*memp->pcw_hostmem); 3664 3665 xxdmp_all_regs(pcic, socket, -1); 3666 3667 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3668 (void *)memp->pcw_hostmem, 3669 (uint32_t)*memp->pcw_hostmem); 3670 } 3671 #endif 3672 3673 if (which & PCW_ATTRIBUTE) 3674 pcic_mswait(pcic, socket, 2); 3675 3676 mutex_exit(&pcic->pc_lock); 3677 3678 return (SUCCESS); 3679 } 3680 3681 /* 3682 * pcic_set_vcc_level() 3683 * 3684 * set voltage based on adapter information 3685 * 3686 * this routine implements a limited solution for support of 3.3v cards. 3687 * the general solution, which would fully support the pcmcia spec 3688 * as far as allowing client drivers to request which voltage levels 3689 * to be set, requires more framework support and driver changes - ess 3690 */ 3691 static int 3692 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3693 { 3694 uint32_t socket_present_state; 3695 3696 #if defined(PCIC_DEBUG) 3697 if (pcic_debug) { 3698 cmn_err(CE_CONT, 3699 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3700 (void *)pcic, socket->VccLevel); 3701 } 3702 #endif 3703 3704 /* 3705 * check VccLevel 3706 * if this is zero, power is being turned off 3707 * if it is non-zero, power is being turned on. 3708 */ 3709 if (socket->VccLevel == 0) { 3710 return (0); 3711 } 3712 3713 /* 3714 * range checking for sanity's sake 3715 */ 3716 if (socket->VccLevel >= pcic->pc_numpower) { 3717 return (BAD_VCC); 3718 } 3719 3720 switch (pcic->pc_io_type) { 3721 /* 3722 * Yenta-compliant adapters have vcc info in the extended registers 3723 * Other adapters can be added as needed, but the 'default' case 3724 * has been left as it was previously so as not to break existing 3725 * adapters. 3726 */ 3727 case PCIC_IO_TYPE_YENTA: 3728 /* 3729 * Here we ignore the VccLevel passed in and read the 3730 * card type from the adapter socket present state register 3731 */ 3732 socket_present_state = 3733 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3734 PCIC_PRESENT_STATE_REG)); 3735 #if defined(PCIC_DEBUG) 3736 if (pcic_debug) { 3737 cmn_err(CE_CONT, 3738 "socket present state = 0x%x\n", 3739 socket_present_state); 3740 } 3741 #endif 3742 switch (socket_present_state & PCIC_VCC_MASK) { 3743 case PCIC_VCC_3VCARD: 3744 /* fall through */ 3745 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3746 socket->VccLevel = PCIC_VCC_3VLEVEL; 3747 return 3748 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3749 case PCIC_VCC_5VCARD: 3750 socket->VccLevel = PCIC_VCC_5VLEVEL; 3751 return 3752 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3753 default: 3754 /* 3755 * if no card is present, this can be the 3756 * case of a client making a SetSocket call 3757 * after card removal. In this case we return 3758 * the current power level 3759 */ 3760 return ((unsigned)ddi_get8(pcic->handle, 3761 pcic->ioaddr + CB_R2_OFFSET + 3762 PCIC_POWER_CONTROL)); 3763 } 3764 3765 default: 3766 3767 switch (socket->VccLevel) { 3768 case PCIC_VCC_3VLEVEL: 3769 return (BAD_VCC); 3770 case PCIC_VCC_5VLEVEL: 3771 /* enable Vcc */ 3772 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3773 default: 3774 return (BAD_VCC); 3775 } 3776 } 3777 } 3778 3779 3780 /* 3781 * pcic_set_socket() 3782 * Socket Services SetSocket call 3783 * sets basic socket configuration 3784 */ 3785 static int 3786 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3787 { 3788 anp_t *anp = ddi_get_driver_private(dip); 3789 pcicdev_t *pcic = anp->an_private; 3790 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3791 int irq, interrupt, mirq; 3792 int powerlevel = 0; 3793 int ind, value, orig_pwrctl; 3794 3795 #if defined(PCIC_DEBUG) 3796 if (pcic_debug) { 3797 cmn_err(CE_CONT, 3798 "pcic_set_socket(dip=%p, socket=%d)" 3799 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3800 socket->socket, socket->VccLevel, socket->Vpp1Level, 3801 socket->Vpp2Level); 3802 } 3803 #endif 3804 /* 3805 * check VccLevel, etc. before setting mutex 3806 * if this is zero, power is being turned off 3807 * if it is non-zero, power is being turned on. 3808 * the default case is to assume Vcc only. 3809 */ 3810 3811 /* this appears to be very implementation specific */ 3812 3813 if (socket->Vpp1Level != socket->Vpp2Level) 3814 return (BAD_VPP); 3815 3816 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3817 powerlevel = 0; 3818 sockp->pcs_vcc = 0; 3819 sockp->pcs_vpp1 = 0; 3820 sockp->pcs_vpp2 = 0; 3821 } else { 3822 #if defined(PCIC_DEBUG) 3823 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3824 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3825 #endif 3826 /* valid Vcc power level? */ 3827 if (socket->VccLevel >= pcic->pc_numpower) 3828 return (BAD_VCC); 3829 3830 switch (pcic_power[socket->VccLevel].PowerLevel) { 3831 case 33: /* 3.3V */ 3832 case 60: /* for bad CIS in Option GPRS card */ 3833 if (!(pcic->pc_flags & PCF_33VCAP)) { 3834 cmn_err(CE_WARN, 3835 "%s%d: Bad Request for 3.3V " 3836 "(Controller incapable)\n", 3837 ddi_get_name(pcic->dip), 3838 ddi_get_instance(pcic->dip)); 3839 return (BAD_VCC); 3840 } 3841 /* FALLTHROUGH */ 3842 case 50: /* 5V */ 3843 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3844 pcic_getcb(pcic, CB_PRESENT_STATE) & 3845 CB_PS_33VCARD) { 3846 /* 3847 * This is actually a 3.3V card. 3848 * Solaris Card Services 3849 * doesn't understand 3.3V 3850 * so we cheat and change 3851 * the setting to the one appropriate to 3.3V. 3852 * Note that this is the entry number 3853 * in the pcic_power[] array. 3854 */ 3855 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3856 } else 3857 sockp->pcs_vcc = socket->VccLevel; 3858 break; 3859 default: 3860 return (BAD_VCC); 3861 } 3862 3863 /* enable Vcc */ 3864 powerlevel = POWER_CARD_ENABLE; 3865 3866 #if defined(PCIC_DEBUG) 3867 if (pcic_debug) { 3868 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3869 socket->VccLevel, powerlevel); 3870 } 3871 #endif 3872 ind = 0; /* default index to 0 power */ 3873 if ((int)socket->Vpp1Level >= 0 && 3874 socket->Vpp1Level < pcic->pc_numpower) { 3875 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3876 & VPP1)) { 3877 return (BAD_VPP); 3878 } 3879 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3880 powerlevel |= pcic_vpp_levels[ind]; 3881 sockp->pcs_vpp1 = socket->Vpp1Level; 3882 } 3883 if ((int)socket->Vpp2Level >= 0 && 3884 socket->Vpp2Level < pcic->pc_numpower) { 3885 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3886 & VPP2)) { 3887 return (BAD_VPP); 3888 } 3889 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3890 powerlevel |= (pcic_vpp_levels[ind] << 2); 3891 sockp->pcs_vpp2 = socket->Vpp2Level; 3892 } 3893 3894 if (pcic->pc_flags & PCF_VPPX) { 3895 /* 3896 * this adapter doesn't allow separate Vpp1/Vpp2 3897 * if one is turned on, both are turned on and only 3898 * the Vpp1 bits should be set 3899 */ 3900 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3901 /* must be the same if one not zero */ 3902 if (sockp->pcs_vpp1 != 0 && 3903 sockp->pcs_vpp2 != 0) { 3904 cmn_err(CE_WARN, 3905 "%s%d: Bad Power Request " 3906 "(Vpp1/2 not the same)\n", 3907 ddi_get_name(pcic->dip), 3908 ddi_get_instance(pcic->dip)); 3909 return (BAD_VPP); 3910 } 3911 } 3912 powerlevel &= ~(3<<2); 3913 } 3914 3915 #if defined(PCIC_DEBUG) 3916 if (pcic_debug) { 3917 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3918 powerlevel, ind); 3919 } 3920 #endif 3921 } 3922 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3923 3924 /* turn socket->IREQRouting off while programming */ 3925 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3926 interrupt &= ~PCIC_INTR_MASK; 3927 if (pcic->pc_flags & PCF_USE_SMI) 3928 interrupt |= PCIC_INTR_ENABLE; 3929 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3930 3931 switch (pcic->pc_type) { 3932 case PCIC_INTEL_i82092: 3933 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3934 PCIC_82092_INT_DISABLE); 3935 break; 3936 default: 3937 break; 3938 } /* switch */ 3939 3940 /* the SCIntMask specifies events to detect */ 3941 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3942 3943 #if defined(PCIC_DEBUG) 3944 if (pcic_debug) 3945 cmn_err(CE_CONT, 3946 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3947 socket->SCIntMask, interrupt, mirq); 3948 #endif 3949 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3950 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3951 mirq & ~PCIC_CHANGE_MASK); 3952 3953 /* save the mask we want to use */ 3954 sockp->pcs_intmask = socket->SCIntMask; 3955 3956 /* 3957 * Until there is a card present it's not worth enabling 3958 * any interrupts except "Card detect". This is done 3959 * elsewhere in the driver so don't change things if 3960 * there is no card! 3961 */ 3962 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3963 3964 /* now update the hardware to reflect events desired */ 3965 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3966 mirq |= PCIC_BD_DETECT; 3967 3968 if (sockp->pcs_intmask & SBM_BVD2) 3969 mirq |= PCIC_BW_DETECT; 3970 3971 if (sockp->pcs_intmask & SBM_RDYBSY) 3972 mirq |= PCIC_RD_DETECT; 3973 3974 if (sockp->pcs_intmask & SBM_CD) 3975 mirq |= PCIC_CD_DETECT; 3976 } 3977 3978 if (sockp->pcs_flags & PCS_READY) { 3979 /* 3980 * card just came ready. 3981 * make sure enough time elapses 3982 * before touching it. 3983 */ 3984 sockp->pcs_flags &= ~PCS_READY; 3985 pcic_mswait(pcic, socket->socket, 10); 3986 } 3987 3988 #if defined(PCIC_DEBUG) 3989 if (pcic_debug) { 3990 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3991 } 3992 #endif 3993 3994 switch (pcic->pc_type) { 3995 case PCIC_I82365SL: 3996 case PCIC_VADEM: 3997 case PCIC_VADEM_VG469: 3998 /* 3999 * The Intel version has different options. This is a 4000 * special case of GPI which might be used for eject 4001 */ 4002 4003 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 4004 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 4005 pcic->pc_flags & PCF_GPI_EJECT) { 4006 irq |= PCIC_GPI_ENABLE; 4007 } else { 4008 irq &= ~PCIC_GPI_ENABLE; 4009 } 4010 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 4011 break; 4012 case PCIC_CL_PD6710: 4013 case PCIC_CL_PD6722: 4014 if (socket->IFType == IF_IO) { 4015 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 4016 value = pcic_getb(pcic, socket->socket, 4017 PCIC_MISC_CTL_1); 4018 if (pcic->pc_flags & PCF_AUDIO) 4019 value |= PCIC_MC_SPEAKER_ENB; 4020 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4021 value); 4022 } else { 4023 value = pcic_getb(pcic, socket->socket, 4024 PCIC_MISC_CTL_1); 4025 value &= ~PCIC_MC_SPEAKER_ENB; 4026 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4027 value); 4028 } 4029 break; 4030 case PCIC_CL_PD6729: 4031 case PCIC_CL_PD6730: 4032 case PCIC_CL_PD6832: 4033 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 4034 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4035 value |= PCIC_MC_SPEAKER_ENB; 4036 } else { 4037 value &= ~PCIC_MC_SPEAKER_ENB; 4038 } 4039 4040 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4041 value |= PCIC_MC_3VCC; 4042 else 4043 value &= ~PCIC_MC_3VCC; 4044 4045 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 4046 break; 4047 4048 case PCIC_O2_OZ6912: 4049 value = pcic_getcb(pcic, CB_MISCCTRL); 4050 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 4051 value |= (1<<25); 4052 else 4053 value &= ~(1<<25); 4054 pcic_putcb(pcic, CB_MISCCTRL, value); 4055 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4056 powerlevel |= 0x08; 4057 break; 4058 4059 case PCIC_TI_PCI1250: 4060 case PCIC_TI_PCI1221: 4061 case PCIC_TI_PCI1225: 4062 case PCIC_TI_PCI1410: 4063 case PCIC_ENE_1410: 4064 case PCIC_TI_PCI1510: 4065 case PCIC_TI_PCI1520: 4066 case PCIC_TI_PCI1420: 4067 case PCIC_ENE_1420: 4068 value = ddi_get8(pcic->cfg_handle, 4069 pcic->cfgaddr + PCIC_CRDCTL_REG); 4070 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4071 value |= PCIC_CRDCTL_SPKR_ENBL; 4072 } else { 4073 value &= ~PCIC_CRDCTL_SPKR_ENBL; 4074 } 4075 ddi_put8(pcic->cfg_handle, 4076 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 4077 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4078 powerlevel |= 0x08; 4079 break; 4080 } 4081 4082 /* 4083 * ctlind processing -- we can ignore this 4084 * there aren't any outputs on the chip for this and 4085 * the GUI will display what it thinks is correct 4086 */ 4087 4088 /* 4089 * If outputs are enabled and the power is going off 4090 * turn off outputs first. 4091 */ 4092 4093 /* power setup -- if necessary */ 4094 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4095 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 4096 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4097 pcic_putb(pcic, socket->socket, 4098 PCIC_POWER_CONTROL, orig_pwrctl); 4099 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4100 } 4101 4102 if (pcic->pc_flags & PCF_CBPWRCTL) { 4103 value = pcic_cbus_powerctl(pcic, socket->socket); 4104 powerlevel = 0; 4105 } else 4106 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4107 4108 if (value != SUCCESS) { 4109 mutex_exit(&pcic->pc_lock); 4110 return (value); 4111 } 4112 4113 /* 4114 * If outputs were disabled and the power is going on 4115 * turn on outputs afterwards. 4116 */ 4117 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4118 orig_pwrctl = pcic_getb(pcic, socket->socket, 4119 PCIC_POWER_CONTROL); 4120 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4121 pcic_putb(pcic, socket->socket, 4122 PCIC_POWER_CONTROL, orig_pwrctl); 4123 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4124 } 4125 4126 /* 4127 * Once we have done the power stuff can re-enable management 4128 * interrupts. 4129 */ 4130 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4131 4132 #if defined(PCIC_DEBUG) 4133 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4134 "cbctl 0x%x\n", 4135 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4136 pcic_getcb(pcic, CB_CONTROL)); 4137 #endif 4138 4139 /* irq processing */ 4140 if (socket->IFType == IF_IO) { 4141 /* IRQ only for I/O */ 4142 irq = socket->IREQRouting & PCIC_INTR_MASK; 4143 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4144 value &= ~PCIC_INTR_MASK; 4145 4146 /* to enable I/O operation */ 4147 value |= PCIC_IO_CARD | PCIC_RESET; 4148 sockp->pcs_flags |= PCS_CARD_IO; 4149 if (irq != sockp->pcs_irq) { 4150 if (sockp->pcs_irq != 0) 4151 cmn_err(CE_CONT, 4152 "SetSocket: IRQ mismatch %x != %x!\n", 4153 irq, sockp->pcs_irq); 4154 else 4155 sockp->pcs_irq = irq; 4156 } 4157 irq = sockp->pcs_irq; 4158 4159 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4160 if (socket->IREQRouting & IRQ_ENABLE) { 4161 pcic_enable_io_intr(pcic, socket->socket, irq); 4162 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4163 } else { 4164 pcic_disable_io_intr(pcic, socket->socket); 4165 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4166 } 4167 #if defined(PCIC_DEBUG) 4168 if (pcic_debug) { 4169 cmn_err(CE_CONT, 4170 "\tsocket type is I/O and irq %x is %s\n", irq, 4171 (socket->IREQRouting & IRQ_ENABLE) ? 4172 "enabled" : "not enabled"); 4173 xxdmp_all_regs(pcic, socket->socket, 20); 4174 } 4175 #endif 4176 } else { 4177 /* make sure I/O mode is off */ 4178 4179 sockp->pcs_irq = 0; 4180 4181 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4182 value &= ~PCIC_IO_CARD; 4183 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4184 pcic_disable_io_intr(pcic, socket->socket); 4185 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4186 } 4187 4188 sockp->pcs_state &= ~socket->State; 4189 4190 mutex_exit(&pcic->pc_lock); 4191 return (SUCCESS); 4192 } 4193 4194 /* 4195 * pcic_inquire_socket() 4196 * SocketServices InquireSocket function 4197 * returns basic characteristics of the socket 4198 */ 4199 /*ARGSUSED*/ 4200 static int 4201 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4202 { 4203 anp_t *anp = ddi_get_driver_private(dip); 4204 pcicdev_t *pcic = anp->an_private; 4205 int value; 4206 4207 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4208 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4209 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4210 value = pcic->pc_sockets[socket->socket].pcs_flags; 4211 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4212 socket->ActiveHigh = 0; 4213 /* these are the usable IRQs */ 4214 socket->ActiveLow = 0xfff0; 4215 return (SUCCESS); 4216 } 4217 4218 /* 4219 * pcic_inquire_window() 4220 * SocketServices InquireWindow function 4221 * returns detailed characteristics of the window 4222 * this is where windows get tied to sockets 4223 */ 4224 /*ARGSUSED*/ 4225 static int 4226 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4227 { 4228 int type, socket; 4229 4230 type = window->window % PCIC_NUMWINSOCK; 4231 socket = window->window / PCIC_NUMWINSOCK; 4232 4233 #if defined(PCIC_DEBUG) 4234 if (pcic_debug >= 8) 4235 cmn_err(CE_CONT, 4236 "pcic_inquire_window: window = %d/%d socket=%d\n", 4237 window->window, type, socket); 4238 #endif 4239 if (type < PCIC_IOWINDOWS) { 4240 window->WndCaps = WC_IO|WC_WAIT; 4241 type = IF_IO; 4242 } else { 4243 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4244 type = IF_MEMORY; 4245 } 4246 4247 /* initialize the socket map - one socket per window */ 4248 PR_ZERO(window->Sockets); 4249 PR_SET(window->Sockets, socket); 4250 4251 if (type == IF_IO) { 4252 iowin_char_t *io; 4253 io = &window->iowin_char; 4254 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4255 WC_16BIT; 4256 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4257 io->LastByte = (baseaddr_t)IOMEM_LAST; 4258 io->MinSize = IOMEM_MIN; 4259 io->MaxSize = IOMEM_MAX; 4260 io->ReqGran = IOMEM_GRAN; 4261 io->AddrLines = IOMEM_DECODE; 4262 io->EISASlot = 0; 4263 } else { 4264 mem_win_char_t *mem; 4265 mem = &window->mem_win_char; 4266 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4267 WC_16BIT|WC_WP; 4268 4269 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4270 mem->LastByte = (baseaddr_t)MEM_LAST; 4271 4272 mem->MinSize = MEM_MIN; 4273 mem->MaxSize = MEM_MAX; 4274 mem->ReqGran = PCIC_PAGE; 4275 mem->ReqBase = 0; 4276 mem->ReqOffset = PCIC_PAGE; 4277 mem->Slowest = MEM_SPEED_MAX; 4278 mem->Fastest = MEM_SPEED_MIN; 4279 } 4280 return (SUCCESS); 4281 } 4282 4283 /* 4284 * pcic_get_adapter() 4285 * SocketServices GetAdapter function 4286 * this is nearly a no-op. 4287 */ 4288 /*ARGSUSED*/ 4289 static int 4290 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4291 { 4292 anp_t *anp = ddi_get_driver_private(dip); 4293 pcicdev_t *pcic = anp->an_private; 4294 4295 if (pcic->pc_flags & PCF_INTRENAB) 4296 adapt->SCRouting = IRQ_ENABLE; 4297 adapt->state = 0; 4298 return (SUCCESS); 4299 } 4300 4301 /* 4302 * pcic_get_page() 4303 * SocketServices GetPage function 4304 * returns info about the window 4305 */ 4306 /*ARGSUSED*/ 4307 static int 4308 pcic_get_page(dev_info_t *dip, get_page_t *page) 4309 { 4310 anp_t *anp = ddi_get_driver_private(dip); 4311 pcicdev_t *pcic = anp->an_private; 4312 int socket, window; 4313 pcs_memwin_t *winp; 4314 4315 socket = page->window / PCIC_NUMWINSOCK; 4316 window = page->window % PCIC_NUMWINSOCK; 4317 4318 /* I/O windows are the first two */ 4319 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4320 return (BAD_WINDOW); 4321 } 4322 4323 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4324 4325 if (page->page != 0) 4326 return (BAD_PAGE); 4327 4328 page->state = 0; 4329 if (winp->pcw_status & PCW_ENABLED) 4330 page->state |= PS_ENABLED; 4331 if (winp->pcw_status & PCW_ATTRIBUTE) 4332 page->state |= PS_ATTRIBUTE; 4333 if (winp->pcw_status & PCW_WP) 4334 page->state |= PS_WP; 4335 4336 page->offset = (off_t)winp->pcw_offset; 4337 4338 return (SUCCESS); 4339 } 4340 4341 /* 4342 * pcic_get_socket() 4343 * SocketServices GetSocket 4344 * returns information about the current socket setting 4345 */ 4346 /*ARGSUSED*/ 4347 static int 4348 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4349 { 4350 anp_t *anp = ddi_get_driver_private(dip); 4351 pcicdev_t *pcic = anp->an_private; 4352 int socknum, irq_enabled; 4353 pcic_socket_t *sockp; 4354 4355 socknum = socket->socket; 4356 sockp = &pcic->pc_sockets[socknum]; 4357 4358 socket->SCIntMask = sockp->pcs_intmask; 4359 sockp->pcs_state = pcic_card_state(pcic, sockp); 4360 4361 socket->state = sockp->pcs_state; 4362 if (socket->state & SBM_CD) { 4363 socket->VccLevel = sockp->pcs_vcc; 4364 socket->Vpp1Level = sockp->pcs_vpp1; 4365 socket->Vpp2Level = sockp->pcs_vpp2; 4366 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4367 IRQ_ENABLE : 0; 4368 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4369 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4370 IF_IO : IF_MEMORY; 4371 } else { 4372 socket->VccLevel = 0; 4373 socket->Vpp1Level = 0; 4374 socket->Vpp2Level = 0; 4375 socket->IRQRouting = 0; 4376 socket->IFType = IF_MEMORY; 4377 } 4378 socket->CtlInd = 0; /* no indicators */ 4379 4380 return (SUCCESS); 4381 } 4382 4383 /* 4384 * pcic_get_status() 4385 * SocketServices GetStatus 4386 * returns status information about the PC Card in 4387 * the selected socket 4388 */ 4389 /*ARGSUSED*/ 4390 static int 4391 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4392 { 4393 anp_t *anp = ddi_get_driver_private(dip); 4394 pcicdev_t *pcic = anp->an_private; 4395 int socknum, irq_enabled; 4396 pcic_socket_t *sockp; 4397 4398 socknum = status->socket; 4399 sockp = &pcic->pc_sockets[socknum]; 4400 4401 status->CardState = pcic_card_state(pcic, sockp); 4402 status->SocketState = sockp->pcs_state; 4403 status->CtlInd = 0; /* no indicators */ 4404 4405 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4406 status->SocketState |= SBM_CD; 4407 if (status->CardState & SBM_CD) { 4408 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4409 IRQ_ENABLE : 0; 4410 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4411 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4412 IF_IO : IF_MEMORY; 4413 } else { 4414 status->IRQRouting = 0; 4415 status->IFType = IF_MEMORY; 4416 } 4417 4418 #if defined(PCIC_DEBUG) 4419 if (pcic_debug >= 8) 4420 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4421 "SocketState=%x\n", 4422 socknum, status->CardState, status->SocketState); 4423 #endif 4424 switch (pcic->pc_type) { 4425 uint32_t present_state; 4426 case PCIC_TI_PCI1410: 4427 case PCIC_TI_PCI1520: 4428 case PCIC_TI_PCI1420: 4429 case PCIC_ENE_1420: 4430 case PCIC_TOSHIBA_TOPIC100: 4431 case PCIC_TOSHIBA_TOPIC95: 4432 case PCIC_TOSHIBA_VENDOR: 4433 case PCIC_O2MICRO_VENDOR: 4434 case PCIC_TI_VENDOR: 4435 case PCIC_RICOH_VENDOR: 4436 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4437 if (present_state & PCIC_CB_CARD) 4438 status->IFType = IF_CARDBUS; 4439 #if defined(PCIC_DEBUG) 4440 if (pcic_debug >= 8) 4441 cmn_err(CE_CONT, 4442 "pcic_get_status: present_state=0x%x\n", 4443 present_state); 4444 #endif 4445 break; 4446 default: 4447 break; 4448 } 4449 4450 return (SUCCESS); 4451 } 4452 4453 /* 4454 * pcic_get_window() 4455 * SocketServices GetWindow function 4456 * returns state information about the specified window 4457 */ 4458 /*ARGSUSED*/ 4459 static int 4460 pcic_get_window(dev_info_t *dip, get_window_t *window) 4461 { 4462 anp_t *anp = ddi_get_driver_private(dip); 4463 pcicdev_t *pcic = anp->an_private; 4464 int socket, win; 4465 pcic_socket_t *sockp; 4466 pcs_memwin_t *winp; 4467 4468 socket = window->window / PCIC_NUMWINSOCK; 4469 win = window->window % PCIC_NUMWINSOCK; 4470 #if defined(PCIC_DEBUG) 4471 if (pcic_debug) { 4472 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4473 socket, win); 4474 } 4475 #endif 4476 4477 if (socket > pcic->pc_numsockets) 4478 return (BAD_WINDOW); 4479 4480 sockp = &pcic->pc_sockets[socket]; 4481 winp = &sockp->pcs_windows[win].mem; 4482 4483 window->socket = socket; 4484 window->size = winp->pcw_len; 4485 window->speed = winp->pcw_speed; 4486 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4487 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4488 4489 if (win >= PCIC_IOWINDOWS) { 4490 window->state = 0; 4491 } else { 4492 window->state = WS_IO; 4493 } 4494 if (winp->pcw_status & PCW_ENABLED) 4495 window->state |= WS_ENABLED; 4496 4497 if (winp->pcw_status & PCS_CARD_16BIT) 4498 window->state |= WS_16BIT; 4499 #if defined(PCIC_DEBUG) 4500 if (pcic_debug) 4501 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4502 window->size, (unsigned)window->speed, 4503 (void *)window->handle, window->state); 4504 #endif 4505 4506 return (SUCCESS); 4507 } 4508 4509 /* 4510 * pcic_ll_reset 4511 * low level reset 4512 * separated out so it can be called when already locked 4513 * 4514 * There are two variables that control the RESET timing: 4515 * pcic_prereset_time - time in mS before asserting RESET 4516 * pcic_reset_time - time in mS to assert RESET 4517 * 4518 */ 4519 int pcic_prereset_time = 1; 4520 int pcic_reset_time = 10; 4521 int pcic_postreset_time = 20; 4522 int pcic_vpp_is_vcc_during_reset = 0; 4523 4524 static int 4525 pcic_ll_reset(pcicdev_t *pcic, int socket) 4526 { 4527 int windowbits, iobits; 4528 uint32_t pwr; 4529 4530 /* save windows that were on */ 4531 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4532 if (pcic_reset_time == 0) 4533 return (windowbits); 4534 /* turn all windows off */ 4535 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4536 4537 #if defined(PCIC_DEBUG) 4538 pcic_err(pcic->dip, 6, 4539 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4540 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4541 pcic_getcb(pcic, CB_CONTROL), 4542 pcic_getcb(pcic, CB_PRESENT_STATE)); 4543 #endif 4544 4545 if (pcic_vpp_is_vcc_during_reset) { 4546 4547 /* 4548 * Set VPP to VCC for the duration of the reset - for aironet 4549 * card. 4550 */ 4551 if (pcic->pc_flags & PCF_CBPWRCTL) { 4552 pwr = pcic_getcb(pcic, CB_CONTROL); 4553 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4554 (void) pcic_getcb(pcic, CB_CONTROL); 4555 } else { 4556 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4557 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4558 pwr | 1); 4559 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4560 } 4561 } 4562 4563 if (pcic_prereset_time > 0) { 4564 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4565 pcic_prereset_time); 4566 pcic_mswait(pcic, socket, pcic_prereset_time); 4567 } 4568 4569 /* turn interrupts off and start a reset */ 4570 pcic_err(pcic->dip, 8, 4571 "pcic_ll_reset turn interrupts off and start a reset\n"); 4572 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4573 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4574 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4575 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4576 4577 switch (pcic->pc_type) { 4578 case PCIC_INTEL_i82092: 4579 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4580 PCIC_82092_INT_DISABLE); 4581 break; 4582 default: 4583 break; 4584 } /* switch */ 4585 4586 pcic->pc_sockets[socket].pcs_state = 0; 4587 4588 if (pcic_reset_time > 0) { 4589 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4590 pcic_reset_time); 4591 pcic_mswait(pcic, socket, pcic_reset_time); 4592 } 4593 4594 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4595 4596 /* take it out of RESET now */ 4597 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4598 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4599 4600 /* 4601 * can't access the card for 20ms, but we really don't 4602 * want to sit around that long. The pcic is still usable. 4603 * memory accesses must wait for RDY to come up. 4604 */ 4605 if (pcic_postreset_time > 0) { 4606 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4607 pcic_postreset_time); 4608 pcic_mswait(pcic, socket, pcic_postreset_time); 4609 } 4610 4611 if (pcic_vpp_is_vcc_during_reset > 1) { 4612 4613 /* 4614 * Return VPP power to whatever it was before. 4615 */ 4616 if (pcic->pc_flags & PCF_CBPWRCTL) { 4617 pcic_putcb(pcic, CB_CONTROL, pwr); 4618 (void) pcic_getcb(pcic, CB_CONTROL); 4619 } else { 4620 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4621 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4622 } 4623 } 4624 4625 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4626 4627 return (windowbits); 4628 } 4629 4630 /* 4631 * pcic_reset_socket() 4632 * SocketServices ResetSocket function 4633 * puts the PC Card in the socket into the RESET state 4634 * and then takes it out after the the cycle time 4635 * The socket is back to initial state when done 4636 */ 4637 static int 4638 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4639 { 4640 anp_t *anp = ddi_get_driver_private(dip); 4641 pcicdev_t *pcic = anp->an_private; 4642 int value; 4643 int i, mint; 4644 pcic_socket_t *sockp; 4645 4646 #if defined(PCIC_DEBUG) 4647 if (pcic_debug >= 8) 4648 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4649 (void *)dip, socket, mode, 4650 mode == RESET_MODE_FULL ? "full" : "partial"); 4651 #endif 4652 4653 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4654 4655 /* Turn off management interupts. */ 4656 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4657 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4658 4659 sockp = &pcic->pc_sockets[socket]; 4660 4661 value = pcic_ll_reset(pcic, socket); 4662 if (mode == RESET_MODE_FULL) { 4663 /* disable and unmap all mapped windows */ 4664 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4665 if (i < PCIC_IOWINDOWS) { 4666 if (sockp->pcs_windows[i].io.pcw_status & 4667 PCW_MAPPED) { 4668 pcs_iowin_t *io; 4669 io = &sockp->pcs_windows[i].io; 4670 io->pcw_status &= ~PCW_ENABLED; 4671 } 4672 } else { 4673 if (sockp->pcs_windows[i].mem.pcw_status & 4674 PCW_MAPPED) { 4675 pcs_memwin_t *mem; 4676 mem = &sockp->pcs_windows[i].mem; 4677 mem->pcw_status &= ~PCW_ENABLED; 4678 } 4679 } 4680 } 4681 } else { 4682 /* turn windows back on */ 4683 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4684 /* wait the rest of the time here */ 4685 pcic_mswait(pcic, socket, 10); 4686 } 4687 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4688 mutex_exit(&pcic->pc_lock); 4689 return (SUCCESS); 4690 } 4691 4692 /* 4693 * pcic_set_interrupt() 4694 * SocketServices SetInterrupt function 4695 */ 4696 static int 4697 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4698 { 4699 anp_t *anp = ddi_get_driver_private(dip); 4700 pcicdev_t *pcic = anp->an_private; 4701 int value = DDI_SUCCESS; 4702 inthandler_t *intr; 4703 4704 #if defined(PCIC_DEBUG) 4705 if (pcic_debug) { 4706 cmn_err(CE_CONT, 4707 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4708 pcic->pc_intr_mode); 4709 cmn_err(CE_CONT, 4710 "\t irq_top=%p handler=%p handler_id=%x\n", 4711 (void *)pcic->irq_top, (void *)handler->handler, 4712 handler->handler_id); 4713 } 4714 #endif 4715 4716 /* 4717 * If we're on a PCI bus, we route all IO IRQs through a single 4718 * PCI interrupt (typically INT A#) so we don't have to do 4719 * much other than add the caller to general interrupt handler 4720 * and set some state. 4721 */ 4722 4723 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4724 if (intr == NULL) 4725 return (NO_RESOURCE); 4726 4727 switch (pcic->pc_intr_mode) { 4728 case PCIC_INTR_MODE_PCI_1: 4729 /* 4730 * We only allow above-lock-level IO IRQ handlers 4731 * in the PCI bus case. 4732 */ 4733 4734 mutex_enter(&pcic->intr_lock); 4735 4736 if (pcic->irq_top == NULL) { 4737 pcic->irq_top = intr; 4738 pcic->irq_current = pcic->irq_top; 4739 } else { 4740 while (pcic->irq_current->next != NULL) 4741 pcic->irq_current = pcic->irq_current->next; 4742 pcic->irq_current->next = intr; 4743 pcic->irq_current = pcic->irq_current->next; 4744 } 4745 4746 pcic->irq_current->intr = 4747 (ddi_intr_handler_t *)(uintptr_t)handler->handler; 4748 pcic->irq_current->handler_id = handler->handler_id; 4749 pcic->irq_current->arg1 = handler->arg1; 4750 pcic->irq_current->arg2 = handler->arg2; 4751 pcic->irq_current->socket = handler->socket; 4752 4753 mutex_exit(&pcic->intr_lock); 4754 4755 handler->iblk_cookie = &pcic->pc_pri; 4756 handler->idev_cookie = &pcic->pc_dcookie; 4757 break; 4758 4759 default: 4760 intr->intr = (ddi_intr_handler_t *)(uintptr_t)handler->handler; 4761 intr->handler_id = handler->handler_id; 4762 intr->arg1 = handler->arg1; 4763 intr->arg2 = handler->arg2; 4764 intr->socket = handler->socket; 4765 intr->irq = handler->irq; 4766 4767 /* 4768 * need to revisit this to see if interrupts can be 4769 * shared someday. Note that IRQ is set in the common 4770 * code. 4771 */ 4772 mutex_enter(&pcic->pc_lock); 4773 if (pcic->pc_handlers == NULL) { 4774 pcic->pc_handlers = intr; 4775 intr->next = intr->prev = intr; 4776 } else { 4777 insque(intr, pcic->pc_handlers); 4778 } 4779 mutex_exit(&pcic->pc_lock); 4780 4781 break; 4782 } 4783 4784 /* 4785 * need to fill in cookies in event of multiple high priority 4786 * interrupt handlers on same IRQ 4787 */ 4788 4789 #if defined(PCIC_DEBUG) 4790 if (pcic_debug) { 4791 cmn_err(CE_CONT, 4792 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4793 (void *)pcic->irq_top, value); 4794 } 4795 #endif 4796 4797 if (value == DDI_SUCCESS) { 4798 return (SUCCESS); 4799 } else { 4800 return (BAD_IRQ); 4801 } 4802 } 4803 4804 /* 4805 * pcic_clear_interrupt() 4806 * SocketServices ClearInterrupt function 4807 * 4808 * Interrupts for PCIC are complicated by the fact that we must 4809 * follow several different models for interrupts. 4810 * ISA: there is an interrupt per adapter and per socket and 4811 * they can't be shared. 4812 * PCI: some adapters have one PCI interrupt available while others 4813 * have up to 4. Solaris may or may not allow us to use more 4814 * than 1 so we essentially share them all at this point. 4815 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4816 * This is like ISA but we have to fudge and create an intrspec 4817 * that PCI's parent understands and bypass the PCI nexus. 4818 * multifunction: this requires sharing the interrupts on a per-socket 4819 * basis. 4820 */ 4821 static int 4822 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4823 { 4824 anp_t *anp = ddi_get_driver_private(dip); 4825 pcicdev_t *pcic = anp->an_private; 4826 inthandler_t *intr, *prev, *current; 4827 int i; 4828 4829 /* 4830 * If we're on a PCI bus, we route all IO IRQs through a single 4831 * PCI interrupt (typically INT A#) so we don't have to do 4832 * much other than remove the caller from the general 4833 * interrupt handler callout list. 4834 */ 4835 4836 #if defined(PCIC_DEBUG) 4837 if (pcic_debug) { 4838 cmn_err(CE_CONT, 4839 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4840 pcic->pc_intr_mode); 4841 cmn_err(CE_CONT, 4842 "\t irq_top=%p handler=%p handler_id=%x\n", 4843 (void *)pcic->irq_top, (void *)handler->handler, 4844 handler->handler_id); 4845 } 4846 #endif 4847 4848 switch (pcic->pc_intr_mode) { 4849 case PCIC_INTR_MODE_PCI_1: 4850 4851 mutex_enter(&pcic->intr_lock); 4852 if (pcic->irq_top == NULL) { 4853 mutex_exit(&pcic->intr_lock); 4854 return (BAD_IRQ); 4855 } 4856 4857 intr = NULL; 4858 pcic->irq_current = pcic->irq_top; 4859 4860 while ((pcic->irq_current != NULL) && 4861 (pcic->irq_current->handler_id != 4862 handler->handler_id)) { 4863 intr = pcic->irq_current; 4864 pcic->irq_current = pcic->irq_current->next; 4865 } 4866 4867 if (pcic->irq_current == NULL) { 4868 mutex_exit(&pcic->intr_lock); 4869 return (BAD_IRQ); 4870 } 4871 4872 if (intr != NULL) { 4873 intr->next = pcic->irq_current->next; 4874 } else { 4875 pcic->irq_top = pcic->irq_current->next; 4876 } 4877 4878 current = pcic->irq_current; 4879 pcic->irq_current = pcic->irq_top; 4880 mutex_exit(&pcic->intr_lock); 4881 kmem_free(current, sizeof (inthandler_t)); 4882 4883 break; 4884 4885 default: 4886 4887 mutex_enter(&pcic->pc_lock); 4888 intr = pcic_handlers; 4889 prev = (inthandler_t *)&pcic_handlers; 4890 4891 while (intr != NULL) { 4892 if (intr->handler_id == handler->handler_id) { 4893 i = intr->irq & PCIC_INTR_MASK; 4894 if (--pcic_irq_map[i].count == 0) { 4895 /* multi-handler form */ 4896 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4897 (void) ddi_intr_remove_handler( 4898 pcic->pc_intr_htblp[i]); 4899 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4900 (void) pcmcia_return_intr(pcic->dip, i); 4901 #if defined(PCIC_DEBUG) 4902 if (pcic_debug) { 4903 cmn_err(CE_CONT, 4904 "removing interrupt %d at %s " 4905 "priority\n", i, "high"); 4906 cmn_err(CE_CONT, 4907 "ddi_remove_intr(%p, %x, %p)\n", 4908 (void *)dip, 4909 0, 4910 (void *)intr->iblk_cookie); 4911 } 4912 #endif 4913 } 4914 prev->next = intr->next; 4915 kmem_free(intr, sizeof (inthandler_t)); 4916 intr = prev->next; 4917 } else { 4918 prev = intr; 4919 intr = intr->next; 4920 } /* if (handler_id) */ 4921 } /* while */ 4922 4923 mutex_exit(&pcic->pc_lock); 4924 } 4925 4926 #if defined(PCIC_DEBUG) 4927 if (pcic_debug) { 4928 cmn_err(CE_CONT, 4929 "pcic_clear_interrupt: exit irq_top=%p\n", 4930 (void *)pcic->irq_top); 4931 } 4932 #endif 4933 4934 4935 return (SUCCESS); 4936 } 4937 4938 struct intel_regs { 4939 char *name; 4940 int off; 4941 char *fmt; 4942 } iregs[] = { 4943 {"ident ", 0}, 4944 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4945 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4946 "\7DRD\10OE"}, 4947 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4948 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4949 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4950 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4951 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4952 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4953 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4954 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4955 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4956 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4957 {"io0-slow ", 8}, 4958 {"io0-shi ", 9}, 4959 {"io0-elow ", 0xa}, 4960 {"io0-ehi ", 0xb}, 4961 {"io1-slow ", 0xc}, 4962 {"io1-shi ", 0xd}, 4963 {"io1-elow ", 0xe}, 4964 {"io1-ehi ", 0xf}, 4965 {"mem0-slow ", 0x10}, 4966 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4967 {"mem0-elow ", 0x12}, 4968 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4969 {"card0-low ", 0x14}, 4970 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4971 {"mem1-slow ", 0x18}, 4972 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4973 {"mem1-elow ", 0x1a}, 4974 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4975 {"card1-low ", 0x1c}, 4976 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4977 {"mem2-slow ", 0x20}, 4978 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4979 {"mem2-elow ", 0x22}, 4980 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4981 {"card2-low ", 0x24}, 4982 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4983 {"mem3-slow ", 0x28}, 4984 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4985 {"mem3-elow ", 0x2a}, 4986 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4987 {"card3-low ", 0x2c}, 4988 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4989 4990 {"mem4-slow ", 0x30}, 4991 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4992 {"mem4-elow ", 0x32}, 4993 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4994 {"card4-low ", 0x34}, 4995 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4996 {"mpage0 ", 0x40}, 4997 {"mpage1 ", 0x41}, 4998 {"mpage2 ", 0x42}, 4999 {"mpage3 ", 0x43}, 5000 {"mpage4 ", 0x44}, 5001 {NULL}, 5002 }; 5003 5004 static struct intel_regs cregs[] = { 5005 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 5006 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 5007 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 5008 {"chip-info ", 0x1f, "\20\6DUAL"}, 5009 {"IO-offlow0", 0x36}, 5010 {"IO-offhi0 ", 0x37}, 5011 {"IO-offlow1", 0x38}, 5012 {"IO-offhi1 ", 0x39}, 5013 NULL, 5014 }; 5015 5016 static struct intel_regs cxregs[] = { 5017 {"ext-ctl-1 ", 0x03, 5018 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 5019 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 5020 {"mem0-up ", 0x05}, 5021 {"mem1-up ", 0x06}, 5022 {"mem2-up ", 0x07}, 5023 {"mem3-up ", 0x08}, 5024 {"mem4-up ", 0x09}, 5025 {NULL} 5026 }; 5027 5028 void 5029 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 5030 { 5031 int i, value, j; 5032 char buff[256]; 5033 char *fmt; 5034 5035 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 5036 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 5037 int sval; 5038 if (cregs[i].off == PCIC_MISC_CTL_2) 5039 sval = 0; 5040 else 5041 sval = socket; 5042 value = pcic_getb(pcic, sval, cregs[i].off); 5043 if (i & 1) { 5044 if (cregs[i].fmt) 5045 fmt = "%s\t%s\t%b\n"; 5046 else 5047 fmt = "%s\t%s\t%x\n"; 5048 cmn_err(CE_CONT, fmt, buff, 5049 cregs[i].name, value, cregs[i].fmt); 5050 buff[0] = '\0'; 5051 } else { 5052 if (cregs[i].fmt) 5053 fmt = "\t%s\t%b"; 5054 else 5055 fmt = "\t%s\t%x"; 5056 (void) sprintf(buff, fmt, 5057 cregs[i].name, value, cregs[i].fmt); 5058 for (j = strlen(buff); j < 40; j++) 5059 buff[j] = ' '; 5060 buff[40] = '\0'; 5061 } 5062 } 5063 cmn_err(CE_CONT, "%s\n", buff); 5064 5065 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 5066 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 5067 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 5068 5069 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 5070 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 5071 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 5072 5073 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 5074 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 5075 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 5076 5077 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 5078 5079 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 5080 value = clext_reg_read(pcic, socket, cxregs[i].off); 5081 if (i & 1) { 5082 if (cxregs[i].fmt) 5083 fmt = "%s\t%s\t%b\n"; 5084 else 5085 fmt = "%s\t%s\t%x\n"; 5086 cmn_err(CE_CONT, fmt, buff, 5087 cxregs[i].name, value, cxregs[i].fmt); 5088 buff[0] = '\0'; 5089 } else { 5090 if (cxregs[i].fmt) 5091 fmt = "\t%s\t%b"; 5092 else 5093 fmt = "\t%s\t%x"; 5094 (void) sprintf(buff, fmt, 5095 cxregs[i].name, value, cxregs[i].fmt); 5096 for (j = strlen(buff); j < 40; j++) 5097 buff[j] = ' '; 5098 buff[40] = '\0'; 5099 } 5100 } 5101 } 5102 5103 #if defined(PCIC_DEBUG) 5104 static void 5105 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5106 { 5107 int i, value, j; 5108 char buff[256]; 5109 char *fmt; 5110 5111 #if defined(PCIC_DEBUG) 5112 if (pcic_debug < 2) 5113 return; 5114 #endif 5115 cmn_err(CE_CONT, 5116 "----------- PCIC Registers for socket %d---------\n", 5117 socket); 5118 cmn_err(CE_CONT, 5119 "\tname value name value\n"); 5120 5121 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5122 value = pcic_getb(pcic, socket, iregs[i].off); 5123 if (i & 1) { 5124 if (iregs[i].fmt) 5125 fmt = "%s\t%s\t%b\n"; 5126 else 5127 fmt = "%s\t%s\t%x\n"; 5128 cmn_err(CE_CONT, fmt, buff, 5129 iregs[i].name, value, iregs[i].fmt); 5130 buff[0] = '\0'; 5131 } else { 5132 if (iregs[i].fmt) 5133 fmt = "\t%s\t%b"; 5134 else 5135 fmt = "\t%s\t%x"; 5136 (void) sprintf(buff, fmt, 5137 iregs[i].name, value, iregs[i].fmt); 5138 for (j = strlen(buff); j < 40; j++) 5139 buff[j] = ' '; 5140 buff[40] = '\0'; 5141 } 5142 } 5143 switch (pcic->pc_type) { 5144 case PCIC_CL_PD6710: 5145 case PCIC_CL_PD6722: 5146 case PCIC_CL_PD6729: 5147 case PCIC_CL_PD6832: 5148 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5149 break; 5150 } 5151 cmn_err(CE_CONT, "%s\n", buff); 5152 } 5153 #endif 5154 5155 /* 5156 * pcic_mswait(ms) 5157 * sleep ms milliseconds 5158 * call drv_usecwait once for each ms 5159 */ 5160 static void 5161 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5162 { 5163 if (ms) { 5164 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5165 pcic_mutex_exit(&pcic->pc_lock); 5166 delay(drv_usectohz(ms*1000)); 5167 pcic_mutex_enter(&pcic->pc_lock); 5168 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5169 } 5170 } 5171 5172 /* 5173 * pcic_check_ready(pcic, index, off) 5174 * Wait for card to come ready 5175 * We only wait if the card is NOT in RESET 5176 * and power is on. 5177 */ 5178 static boolean_t 5179 pcic_check_ready(pcicdev_t *pcic, int socket) 5180 { 5181 int ifstate, intstate; 5182 5183 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5184 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5185 5186 if ((intstate & PCIC_RESET) && 5187 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5188 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5189 return (B_TRUE); 5190 5191 #ifdef PCIC_DEBUG 5192 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5193 "ifstate = 0x%x\n", intstate, ifstate); 5194 if (pcic_debug) { 5195 pcic_debug += 4; 5196 xxdmp_all_regs(pcic, socket, -1); 5197 pcic_debug -= 4; 5198 } 5199 #endif 5200 return (B_FALSE); 5201 } 5202 5203 /* 5204 * Cirrus Logic extended register read/write routines 5205 */ 5206 static int 5207 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5208 { 5209 int val; 5210 5211 switch (pcic->pc_io_type) { 5212 case PCIC_IO_TYPE_YENTA: 5213 val = ddi_get8(pcic->handle, 5214 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5215 break; 5216 default: 5217 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5218 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5219 break; 5220 } 5221 5222 return (val); 5223 } 5224 5225 static void 5226 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5227 { 5228 switch (pcic->pc_io_type) { 5229 case PCIC_IO_TYPE_YENTA: 5230 ddi_put8(pcic->handle, 5231 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5232 break; 5233 default: 5234 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5235 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5236 break; 5237 } 5238 } 5239 5240 /* 5241 * Misc PCI functions 5242 */ 5243 static void 5244 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5245 { 5246 unsigned cmd; 5247 5248 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5249 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5250 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5251 (PCI_COMM_IO|PCI_COMM_MAE)) 5252 return; 5253 5254 if (flags & PCIC_ENABLE_IO) 5255 cmd |= PCI_COMM_IO; 5256 5257 if (flags & PCIC_ENABLE_MEM) 5258 cmd |= PCI_COMM_MAE; 5259 5260 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5261 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5262 } 5263 5264 /* 5265 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5266 */ 5267 static int 5268 pcic_find_pci_type(pcicdev_t *pcic) 5269 { 5270 uint32_t vend, device; 5271 5272 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5273 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5274 "vendor-id", -1); 5275 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5276 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5277 "device-id", -1); 5278 5279 device = PCI_ID(vend, device); 5280 pcic->pc_type = device; 5281 pcic->pc_chipname = "PCI:unknown"; 5282 5283 switch (device) { 5284 case PCIC_INTEL_i82092: 5285 pcic->pc_chipname = PCIC_TYPE_i82092; 5286 break; 5287 case PCIC_CL_PD6729: 5288 pcic->pc_chipname = PCIC_TYPE_PD6729; 5289 /* 5290 * Some 6730's incorrectly identify themselves 5291 * as a 6729, so we need to do some more tests 5292 * here to see if the device that's claiming 5293 * to be a 6729 is really a 6730. 5294 */ 5295 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5296 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5297 0) { 5298 pcic->pc_chipname = PCIC_TYPE_PD6730; 5299 pcic->pc_type = PCIC_CL_PD6730; 5300 } 5301 break; 5302 case PCIC_CL_PD6730: 5303 pcic->pc_chipname = PCIC_TYPE_PD6730; 5304 break; 5305 case PCIC_CL_PD6832: 5306 pcic->pc_chipname = PCIC_TYPE_PD6832; 5307 break; 5308 case PCIC_SMC_34C90: 5309 pcic->pc_chipname = PCIC_TYPE_34C90; 5310 break; 5311 case PCIC_TOSHIBA_TOPIC95: 5312 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5313 break; 5314 case PCIC_TOSHIBA_TOPIC100: 5315 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5316 break; 5317 case PCIC_TI_PCI1031: 5318 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5319 break; 5320 case PCIC_TI_PCI1130: 5321 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5322 break; 5323 case PCIC_TI_PCI1131: 5324 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5325 break; 5326 case PCIC_TI_PCI1250: 5327 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5328 break; 5329 case PCIC_TI_PCI1225: 5330 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5331 break; 5332 case PCIC_TI_PCI1410: 5333 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5334 break; 5335 case PCIC_TI_PCI1510: 5336 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5337 break; 5338 case PCIC_TI_PCI1520: 5339 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5340 break; 5341 case PCIC_TI_PCI1221: 5342 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5343 break; 5344 case PCIC_TI_PCI1050: 5345 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5346 break; 5347 case PCIC_ENE_1410: 5348 pcic->pc_chipname = PCIC_TYPE_1410; 5349 break; 5350 case PCIC_O2_OZ6912: 5351 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5352 break; 5353 case PCIC_RICOH_RL5C466: 5354 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5355 break; 5356 case PCIC_TI_PCI1420: 5357 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5358 break; 5359 case PCIC_ENE_1420: 5360 pcic->pc_chipname = PCIC_TYPE_1420; 5361 break; 5362 default: 5363 switch (PCI_ID(vend, (uint32_t)0)) { 5364 case PCIC_TOSHIBA_VENDOR: 5365 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5366 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5367 break; 5368 case PCIC_TI_VENDOR: 5369 pcic->pc_chipname = PCIC_TYPE_TI; 5370 pcic->pc_type = PCIC_TI_VENDOR; 5371 break; 5372 case PCIC_O2MICRO_VENDOR: 5373 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5374 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5375 break; 5376 case PCIC_RICOH_VENDOR: 5377 pcic->pc_chipname = PCIC_TYPE_RICOH; 5378 pcic->pc_type = PCIC_RICOH_VENDOR; 5379 break; 5380 default: 5381 if (!(pcic->pc_flags & PCF_CARDBUS)) 5382 return (DDI_FAILURE); 5383 pcic->pc_chipname = PCIC_TYPE_YENTA; 5384 break; 5385 } 5386 } 5387 return (DDI_SUCCESS); 5388 } 5389 5390 static void 5391 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5392 { 5393 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5394 pcic->cfgaddr + PCIC_82092_PPIRR); 5395 uchar_t val; 5396 5397 if (intr == PCIC_82092_CTL_SMI) { 5398 val = PCIC_82092_SMI_CTL(socket, 5399 PCIC_82092_INT_DISABLE); 5400 ppirr &= ~val; 5401 val = PCIC_82092_SMI_CTL(socket, state); 5402 ppirr |= val; 5403 } else { 5404 val = PCIC_82092_IRQ_CTL(socket, 5405 PCIC_82092_INT_DISABLE); 5406 ppirr &= ~val; 5407 val = PCIC_82092_IRQ_CTL(socket, state); 5408 ppirr |= val; 5409 } 5410 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5411 ppirr); 5412 } 5413 5414 static uint_t 5415 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5416 { 5417 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5418 uint_t rc = DDI_INTR_UNCLAIMED; 5419 5420 _NOTE(ARGUNUSED(arg2)) 5421 5422 mutex_enter(&sockp->pcs_pcic->pc_lock); 5423 if (sockp->pcs_cd_softint_flg) { 5424 uint8_t status; 5425 sockp->pcs_cd_softint_flg = 0; 5426 rc = DDI_INTR_CLAIMED; 5427 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5428 PCIC_INTERFACE_STATUS); 5429 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5430 } 5431 mutex_exit(&sockp->pcs_pcic->pc_lock); 5432 return (rc); 5433 } 5434 5435 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5436 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5437 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5438 5439 #ifdef CARDBUS 5440 static uint32_t pcic_cbps_on = 0; 5441 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5442 CB_PS_XVCARD | CB_PS_YVCARD; 5443 #else 5444 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5445 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5446 CB_PS_CBCARD | 5447 CB_PS_XVCARD | CB_PS_YVCARD; 5448 #endif 5449 static void 5450 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5451 { 5452 boolean_t do_debounce = B_FALSE; 5453 int debounce_time = drv_usectohz(pcic_debounce_time); 5454 uint8_t irq; 5455 timeout_id_t debounce; 5456 5457 /* 5458 * Always reset debounce but may need to check original state later. 5459 */ 5460 debounce = sockp->pcs_debounce_id; 5461 sockp->pcs_debounce_id = 0; 5462 5463 /* 5464 * Check to see whether a card is present or not. There are 5465 * only two states that we are concerned with - the state 5466 * where both CD pins are asserted, which means that the 5467 * card is fully seated, and the state where neither CD 5468 * pin is asserted, which means that the card is not 5469 * present. 5470 * The CD signals are generally very noisy and cause a lot of 5471 * contact bounce as the card is being inserted and 5472 * removed, so we need to do some software debouncing. 5473 */ 5474 5475 #ifdef PCIC_DEBUG 5476 pcic_err(pcic->dip, 6, 5477 "pcic%d handle_cd_change: socket %d card status 0x%x" 5478 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5479 sockp->pcs_socket, status, debounce); 5480 #endif 5481 switch (status & PCIC_ISTAT_CD_MASK) { 5482 case PCIC_CD_PRESENT_OK: 5483 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5484 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5485 uint32_t cbps; 5486 #ifdef PCIC_DEBUG 5487 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5488 #endif 5489 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5490 #ifdef PCIC_DEBUG 5491 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5492 #endif 5493 /* 5494 * Check the CB bits are sane. 5495 */ 5496 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5497 cbps & pcic_cbps_off) { 5498 cmn_err(CE_WARN, 5499 "%s%d: Odd Cardbus Present State 0x%x\n", 5500 ddi_get_name(pcic->dip), 5501 ddi_get_instance(pcic->dip), 5502 cbps); 5503 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5504 debounce = 0; 5505 debounce_time = drv_usectohz(1000000); 5506 } 5507 if (debounce) { 5508 sockp->pcs_flags |= PCS_CARD_PRESENT; 5509 if (pcic_do_insertion) { 5510 5511 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5512 5513 if (cbps & CB_PS_16BITCARD) { 5514 pcic_err(pcic->dip, 5515 8, "16 bit card inserted\n"); 5516 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5517 /* calls pcm_adapter_callback() */ 5518 if (pcic->pc_callback) { 5519 5520 (void) ddi_prop_update_string( 5521 DDI_DEV_T_NONE, 5522 pcic->dip, PCM_DEVICETYPE, 5523 "pccard"); 5524 PC_CALLBACK(pcic->dip, 5525 pcic->pc_cb_arg, 5526 PCE_CARD_INSERT, 5527 sockp->pcs_socket); 5528 } 5529 } else if (cbps & CB_PS_CBCARD) { 5530 pcic_err(pcic->dip, 5531 8, "32 bit card inserted\n"); 5532 5533 if (pcic->pc_flags & PCF_CARDBUS) { 5534 sockp->pcs_flags |= 5535 PCS_CARD_ISCARDBUS; 5536 #ifdef CARDBUS 5537 if (!pcic_load_cardbus(pcic, 5538 sockp)) { 5539 pcic_unload_cardbus( 5540 pcic, sockp); 5541 } 5542 5543 #else 5544 cmn_err(CE_NOTE, 5545 "32 bit Cardbus not" 5546 " supported in" 5547 " this device driver\n"); 5548 #endif 5549 } else { 5550 /* 5551 * Ignore the card 5552 */ 5553 cmn_err(CE_NOTE, 5554 "32 bit Cardbus not" 5555 " supported on this" 5556 " device\n"); 5557 } 5558 } else { 5559 cmn_err(CE_NOTE, 5560 "Unsupported PCMCIA card" 5561 " inserted\n"); 5562 } 5563 } 5564 } else { 5565 do_debounce = B_TRUE; 5566 } 5567 } else { 5568 /* 5569 * It is possible to come through here if the system 5570 * starts up with cards already inserted. Do nothing 5571 * and don't worry about it. 5572 */ 5573 #ifdef PCIC_DEBUG 5574 pcic_err(pcic->dip, 5, 5575 "pcic%d: Odd card insertion indication on socket %d\n", 5576 ddi_get_instance(pcic->dip), 5577 sockp->pcs_socket); 5578 #endif 5579 } 5580 break; 5581 5582 default: 5583 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5584 /* 5585 * Someone has started to insert a card so delay a while. 5586 */ 5587 do_debounce = B_TRUE; 5588 break; 5589 } 5590 /* 5591 * Otherwise this is basically the same as not present 5592 * so fall through. 5593 */ 5594 5595 /* FALLTHRU */ 5596 case 0: 5597 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5598 if (pcic->pc_flags & PCF_CBPWRCTL) { 5599 pcic_putcb(pcic, CB_CONTROL, 0); 5600 } else { 5601 pcic_putb(pcic, sockp->pcs_socket, 5602 PCIC_POWER_CONTROL, 0); 5603 (void) pcic_getb(pcic, sockp->pcs_socket, 5604 PCIC_POWER_CONTROL); 5605 } 5606 #ifdef PCIC_DEBUG 5607 pcic_err(pcic->dip, 8, "Card removed\n"); 5608 #endif 5609 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5610 5611 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5612 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5613 if (pcic_do_removal && pcic->pc_callback) { 5614 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5615 PCE_CARD_REMOVAL, sockp->pcs_socket); 5616 } 5617 } 5618 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5619 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5620 sockp->pcs_flags |= PCS_CARD_CBREM; 5621 } 5622 sockp->pcs_flags |= PCS_CARD_REMOVED; 5623 5624 do_debounce = B_TRUE; 5625 } 5626 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5627 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5628 /* 5629 * Ensure that we do the unloading in the 5630 * debounce handler, that way we're not doing 5631 * nasty things in an interrupt handler. e.g. 5632 * a USB device will wait for data which will 5633 * obviously never come because we've 5634 * unplugged the device, but the wait will 5635 * wait forever because no interrupts can 5636 * come in... 5637 */ 5638 #ifdef CARDBUS 5639 pcic_unload_cardbus(pcic, sockp); 5640 /* pcic_dump_all(pcic); */ 5641 #endif 5642 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5643 } 5644 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5645 } 5646 break; 5647 } /* switch */ 5648 5649 if (do_debounce) { 5650 /* 5651 * Delay doing 5652 * anything for a while so that things can settle 5653 * down a little. Interrupts are already disabled. 5654 * Reset the state and we'll reevaluate the 5655 * whole kit 'n kaboodle when the timeout fires 5656 */ 5657 #ifdef PCIC_DEBUG 5658 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5659 "socket %d.%d\n", 5660 ddi_get_instance(pcic->dip), 5661 sockp->pcs_socket); 5662 #endif 5663 sockp->pcs_debounce_id = 5664 pcic_add_debqueue(sockp, debounce_time); 5665 5666 /* 5667 * We bug out here without re-enabling interrupts. They will 5668 * be re-enabled when the debounce timeout swings through 5669 * here. 5670 */ 5671 return; 5672 } 5673 5674 /* 5675 * Turn on Card detect interrupts. Other interrupts will be 5676 * enabled during set_socket calls. 5677 * 5678 * Note that set_socket only changes interrupt settings when there 5679 * is a card present. 5680 */ 5681 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5682 irq |= PCIC_CD_DETECT; 5683 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5684 pcic_putcb(pcic, CB_STATUS_MASK, CB_SE_CCDMASK); 5685 5686 /* Out from debouncing state */ 5687 sockp->pcs_flags &= ~PCS_DEBOUNCING; 5688 5689 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5690 } 5691 5692 /* 5693 * pcic_getb() 5694 * get an I/O byte based on the yardware decode method 5695 */ 5696 static uint8_t 5697 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5698 { 5699 int work; 5700 5701 #if defined(PCIC_DEBUG) 5702 if (pcic_debug == 0x7fff) { 5703 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5704 (void *)pcic, socket, reg); 5705 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5706 pcic->pc_io_type, (void *)pcic->handle, 5707 (void *)pcic->ioaddr); 5708 } 5709 #endif 5710 5711 switch (pcic->pc_io_type) { 5712 case PCIC_IO_TYPE_YENTA: 5713 return (ddi_get8(pcic->handle, 5714 pcic->ioaddr + CB_R2_OFFSET + reg)); 5715 default: 5716 work = (socket * PCIC_SOCKET_1) | reg; 5717 ddi_put8(pcic->handle, pcic->ioaddr, work); 5718 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5719 } 5720 } 5721 5722 static void 5723 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5724 { 5725 int work; 5726 5727 #if defined(PCIC_DEBUG) 5728 if (pcic_debug == 0x7fff) { 5729 cmn_err(CE_CONT, 5730 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5731 (void *)pcic, socket, reg, value); 5732 cmn_err(CE_CONT, 5733 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5734 pcic->pc_io_type, (void *)pcic->handle, 5735 (void *)pcic->ioaddr); 5736 } 5737 #endif 5738 5739 5740 switch (pcic->pc_io_type) { 5741 case PCIC_IO_TYPE_YENTA: 5742 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5743 value); 5744 break; 5745 default: 5746 work = (socket * PCIC_SOCKET_1) | reg; 5747 ddi_put8(pcic->handle, pcic->ioaddr, work); 5748 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5749 break; 5750 } 5751 } 5752 5753 /* 5754 * chip identification functions 5755 */ 5756 5757 /* 5758 * chip identification: Cirrus Logic PD6710/6720/6722 5759 */ 5760 static int 5761 pcic_ci_cirrus(pcicdev_t *pcic) 5762 { 5763 int value1, value2; 5764 5765 /* Init the CL id mode */ 5766 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5767 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5768 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5769 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5770 5771 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5772 (value2 & PCIC_CI_ID) == 0) { 5773 /* chip is a Cirrus Logic and not Intel */ 5774 pcic->pc_type = PCIC_CL_PD6710; 5775 if (value1 & PCIC_CI_SLOTS) 5776 pcic->pc_chipname = PCIC_TYPE_PD6720; 5777 else 5778 pcic->pc_chipname = PCIC_TYPE_PD6710; 5779 /* now fine tune things just in case a 6722 */ 5780 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5781 if (value1 == 0) { 5782 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5783 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5784 if (value1 == 0x55) { 5785 pcic->pc_chipname = PCIC_TYPE_PD6722; 5786 pcic->pc_type = PCIC_CL_PD6722; 5787 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5788 } 5789 } 5790 return (1); 5791 } 5792 return (0); 5793 } 5794 5795 /* 5796 * chip identification: Vadem (VG365/465/468/469) 5797 */ 5798 5799 static void 5800 pcic_vadem_enable(pcicdev_t *pcic) 5801 { 5802 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5803 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5804 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5805 } 5806 5807 static int 5808 pcic_ci_vadem(pcicdev_t *pcic) 5809 { 5810 int value; 5811 5812 pcic_vadem_enable(pcic); 5813 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5814 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5815 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5816 (value | PCIC_VADEM_D3) || 5817 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5818 PCIC_VADEM_469) { 5819 int vadem, new; 5820 pcic_vadem_enable(pcic); 5821 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5822 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5823 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5824 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5825 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5826 5827 /* want to lock but leave mouse or other on */ 5828 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5829 switch (value & PCIC_REV_MASK) { 5830 case PCIC_VADEM_365: 5831 pcic->pc_chipname = PCIC_VG_365; 5832 pcic->pc_type = PCIC_VADEM; 5833 break; 5834 case PCIC_VADEM_465: 5835 pcic->pc_chipname = PCIC_VG_465; 5836 pcic->pc_type = PCIC_VADEM; 5837 pcic->pc_flags |= PCF_1SOCKET; 5838 break; 5839 case PCIC_VADEM_468: 5840 pcic->pc_chipname = PCIC_VG_468; 5841 pcic->pc_type = PCIC_VADEM; 5842 break; 5843 case PCIC_VADEM_469: 5844 pcic->pc_chipname = PCIC_VG_469; 5845 pcic->pc_type = PCIC_VADEM_VG469; 5846 break; 5847 } 5848 return (1); 5849 } 5850 return (0); 5851 } 5852 5853 /* 5854 * chip identification: Ricoh 5855 */ 5856 static int 5857 pcic_ci_ricoh(pcicdev_t *pcic) 5858 { 5859 int value; 5860 5861 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5862 switch (value) { 5863 case PCIC_RF_296: 5864 pcic->pc_type = PCIC_RICOH; 5865 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5866 return (1); 5867 case PCIC_RF_396: 5868 pcic->pc_type = PCIC_RICOH; 5869 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5870 return (1); 5871 } 5872 return (0); 5873 } 5874 5875 5876 /* 5877 * set up available address spaces in busra 5878 */ 5879 static void 5880 pcic_init_assigned(dev_info_t *dip) 5881 { 5882 pcm_regs_t *pcic_avail_p; 5883 pci_regspec_t *pci_avail_p, *regs; 5884 int len, entries, rlen; 5885 dev_info_t *pdip; 5886 5887 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5888 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5889 /* 5890 * found "available" property at the cardbus/pcmcia node 5891 * need to translate address space entries from pcmcia 5892 * format to pci format 5893 */ 5894 entries = len / sizeof (pcm_regs_t); 5895 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5896 KM_SLEEP); 5897 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5898 entries) == DDI_SUCCESS) 5899 (void) pci_resource_setup_avail(dip, pci_avail_p, 5900 entries); 5901 kmem_free(pcic_avail_p, len); 5902 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5903 return; 5904 } 5905 5906 /* 5907 * "legacy" platforms will have "available" property in pci node 5908 */ 5909 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5910 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5911 "available", (caddr_t)&pci_avail_p, &len) == 5912 DDI_PROP_SUCCESS) { 5913 /* (void) pci_resource_setup(pdip); */ 5914 kmem_free(pci_avail_p, len); 5915 break; 5916 } 5917 } 5918 5919 if (pdip == NULL) { 5920 int len; 5921 char bus_type[16] = "(unknown)"; 5922 dev_info_t *par; 5923 5924 cmn_err(CE_CONT, 5925 "?pcic_init_assigned: no available property for pcmcia\n"); 5926 5927 /* 5928 * This code is taken from pci_resource_setup() but does 5929 * not attempt to use the "available" property to populate 5930 * the ndi maps that are created. 5931 * The fact that we will actually 5932 * free some resource below (that was allocated by OBP) 5933 * should be enough to be going on with. 5934 */ 5935 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5936 len = sizeof (bus_type); 5937 5938 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5939 PROP_LEN_AND_VAL_BUF, 5940 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5941 "device_type", 5942 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5943 (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0 || 5944 strcmp(bus_type, DEVI_PCIEX_NEXNAME) == 0)) 5945 break; 5946 } 5947 if (par != NULL && 5948 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5949 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5950 par = NULL; 5951 } else { 5952 #ifdef CARDBUS 5953 cardbus_bus_range_t *bus_range; 5954 int k; 5955 5956 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5957 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5958 if (bus_range->lo != bus_range->hi) 5959 pcic_err(pdip, 9, "allowable bus range is " 5960 "%u->%u\n", bus_range->lo, bus_range->hi); 5961 else { 5962 pcic_err(pdip, 0, 5963 "!No spare PCI bus numbers, range is " 5964 "%u->%u, cardbus isn't usable\n", 5965 bus_range->lo, bus_range->hi); 5966 } 5967 kmem_free(bus_range, k); 5968 } else 5969 pcic_err(pdip, 0, "!No bus-range property seems to " 5970 "have been set up\n"); 5971 #endif 5972 /* 5973 * Have a valid parent with the "available" property 5974 */ 5975 (void) pci_resource_setup(pdip); 5976 } 5977 5978 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5979 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5980 "assigned-addresses", 5981 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5982 ra_return_t ra; 5983 5984 /* 5985 * On the UltraBook IIi the ranges are assigned under 5986 * openboot. If we don't free them here the first I/O 5987 * space that can be used is up above 0x10000 which 5988 * doesn't work for this driver due to restrictions 5989 * on the PCI I/O addresses the controllers can cope with. 5990 * They are never going to be used by anything else 5991 * so free them up to the general pool. AG. 5992 */ 5993 pcic_err(dip, 1, "Free assigned addresses\n"); 5994 5995 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5996 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5997 regs[0].pci_size_low == 0x1000000) { 5998 ra.ra_addr_lo = regs[0].pci_phys_low; 5999 ra.ra_len = regs[0].pci_size_low; 6000 (void) pcmcia_free_mem(dip, &ra); 6001 } 6002 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 6003 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 6004 (regs[1].pci_size_low == 0x8000 || 6005 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 6006 { 6007 ra.ra_addr_lo = regs[1].pci_phys_low; 6008 ra.ra_len = regs[1].pci_size_low; 6009 (void) pcmcia_free_io(dip, &ra); 6010 } 6011 kmem_free((caddr_t)regs, rlen); 6012 } 6013 } 6014 6015 /* 6016 * translate "available" from pcmcia format to pci format 6017 */ 6018 static int 6019 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 6020 pci_regspec_t *pci_p, int entries) 6021 { 6022 int i, range_len, range_entries; 6023 pcic_ranges_t *pcic_range_p; 6024 6025 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 6026 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 6027 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 6028 "no ranges property for pcmcia\n"); 6029 return (DDI_FAILURE); 6030 } 6031 6032 range_entries = range_len / sizeof (pcic_ranges_t); 6033 6034 /* for each "available" entry to be translated */ 6035 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 6036 int j; 6037 pcic_ranges_t *range_p = pcic_range_p; 6038 pci_p->pci_phys_hi = -1u; /* default invalid value */ 6039 6040 /* for each "ranges" entry to be searched */ 6041 for (j = 0; j < range_entries; j++, range_p++) { 6042 uint64_t range_end = range_p->pcic_range_caddrlo + 6043 range_p->pcic_range_size; 6044 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 6045 6046 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 6047 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 6048 (range_end < avail_end)) 6049 continue; 6050 6051 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 6052 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 6053 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 6054 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 6055 pci_p->pci_size_hi = 0; 6056 pci_p->pci_size_low = pcic_p->phys_len; 6057 } 6058 } 6059 kmem_free(pcic_range_p, range_len); 6060 return (DDI_SUCCESS); 6061 } 6062 6063 static int 6064 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 6065 { 6066 #ifdef CARDBUS 6067 if (cardbus_is_cb_minor(*dev)) 6068 return (cardbus_open(dev, flag, otyp, cred)); 6069 #endif 6070 return (EINVAL); 6071 } 6072 6073 static int 6074 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 6075 { 6076 #ifdef CARDBUS 6077 if (cardbus_is_cb_minor(dev)) 6078 return (cardbus_close(dev, flag, otyp, cred)); 6079 #endif 6080 return (EINVAL); 6081 } 6082 6083 static int 6084 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 6085 int *rval) 6086 { 6087 #ifdef CARDBUS 6088 if (cardbus_is_cb_minor(dev)) 6089 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 6090 #endif 6091 return (EINVAL); 6092 } 6093 6094 6095 static boolean_t 6096 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6097 { 6098 uint32_t present_state; 6099 dev_info_t *dip = pcic->dip; 6100 set_socket_t s; 6101 get_socket_t g; 6102 boolean_t retval; 6103 unsigned vccLevel; 6104 6105 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 6106 6107 pcic_mutex_exit(&pcic->pc_lock); 6108 6109 bzero(&s, sizeof (set_socket_t)); 6110 s.socket = sockp->pcs_socket; 6111 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6112 s.IFType = IF_CARDBUS; 6113 s.State = (unsigned)~0; 6114 6115 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6116 if (present_state & PCIC_VCC_3VCARD) 6117 s.VccLevel = PCIC_VCC_3VLEVEL; 6118 else if (present_state & PCIC_VCC_5VCARD) 6119 s.VccLevel = PCIC_VCC_5VLEVEL; 6120 else { 6121 cmn_err(CE_CONT, 6122 "pcic_load_cardbus: unsupported card voltage\n"); 6123 goto failure; 6124 } 6125 vccLevel = s.VccLevel; 6126 s.Vpp1Level = s.Vpp2Level = 0; 6127 6128 if (pcic_set_socket(dip, &s) != SUCCESS) 6129 goto failure; 6130 6131 if (pcic_reset_socket(dip, sockp->pcs_socket, 6132 RESET_MODE_CARD_ONLY) != SUCCESS) 6133 goto failure; 6134 6135 bzero(&g, sizeof (get_socket_t)); 6136 g.socket = sockp->pcs_socket; 6137 if (pcic_get_socket(dip, &g) != SUCCESS) 6138 goto failure; 6139 6140 bzero(&s, sizeof (set_socket_t)); 6141 s.socket = sockp->pcs_socket; 6142 s.SCIntMask = SBM_CD; 6143 s.IREQRouting = g.IRQRouting; 6144 s.IFType = g.IFType; 6145 s.CtlInd = g.CtlInd; 6146 s.State = (unsigned)~0; 6147 s.VccLevel = vccLevel; 6148 s.Vpp1Level = s.Vpp2Level = 0; 6149 6150 retval = pcic_set_socket(dip, &s); 6151 pcmcia_cb_resumed(s.socket); 6152 if (retval != SUCCESS) 6153 goto failure; 6154 6155 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6156 goto exit; 6157 6158 failure: 6159 retval = B_FALSE; 6160 6161 exit: 6162 pcic_mutex_enter(&pcic->pc_lock); 6163 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6164 retval ? "success" : "failure"); 6165 return (retval); 6166 } 6167 6168 static void 6169 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6170 { 6171 dev_info_t *dip = pcic->dip; 6172 set_socket_t s; 6173 6174 pcic_mutex_exit(&pcic->pc_lock); 6175 6176 cardbus_unload_cardbus(dip); 6177 6178 bzero(&s, sizeof (set_socket_t)); 6179 s.socket = sockp->pcs_socket; 6180 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6181 s.IREQRouting = 0; 6182 s.IFType = IF_MEMORY; 6183 s.CtlInd = 0; 6184 s.State = 0; 6185 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6186 6187 (void) pcic_set_socket(dip, &s); 6188 6189 pcic_mutex_enter(&pcic->pc_lock); 6190 } 6191 6192 static uint32_t 6193 pcic_getcb(pcicdev_t *pcic, int reg) 6194 { 6195 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6196 6197 return (ddi_get32(pcic->handle, 6198 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6199 } 6200 6201 static void 6202 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6203 { 6204 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6205 6206 ddi_put32(pcic->handle, 6207 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6208 } 6209 6210 static void 6211 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6212 { 6213 uint8_t value; 6214 uint16_t brdgctl; 6215 6216 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6217 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6218 6219 switch (pcic->pc_type) { 6220 case PCIC_INTEL_i82092: 6221 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6222 PCIC_82092_INT_ENABLE); 6223 break; 6224 case PCIC_O2_OZ6912: 6225 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6226 value |= 0x8; 6227 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6228 break; 6229 case PCIC_CL_PD6832: 6230 case PCIC_TI_PCI1250: 6231 case PCIC_TI_PCI1221: 6232 case PCIC_TI_PCI1225: 6233 case PCIC_TI_PCI1410: 6234 case PCIC_ENE_1410: 6235 case PCIC_TI_PCI1510: 6236 case PCIC_TI_PCI1520: 6237 case PCIC_TI_PCI1420: 6238 case PCIC_ENE_1420: 6239 /* route card functional interrupts to PCI interrupts */ 6240 brdgctl = ddi_get16(pcic->cfg_handle, 6241 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6242 pcic_err(NULL, 1, 6243 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6244 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6245 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6246 ddi_put16(pcic->cfg_handle, 6247 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6248 brdgctl); 6249 /* Flush the write */ 6250 (void) ddi_get16(pcic->cfg_handle, 6251 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6252 break; 6253 default: 6254 break; 6255 } 6256 } 6257 6258 static void 6259 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6260 { 6261 uint8_t value; 6262 uint16_t brdgctl; 6263 6264 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6265 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6266 6267 switch (pcic->pc_type) { 6268 case PCIC_INTEL_i82092: 6269 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6270 PCIC_82092_INT_DISABLE); 6271 break; 6272 case PCIC_O2_OZ6912: 6273 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6274 value &= ~0x8; 6275 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6276 /* Flush the write */ 6277 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6278 break; 6279 case PCIC_CL_PD6832: 6280 case PCIC_TI_PCI1250: 6281 case PCIC_TI_PCI1221: 6282 case PCIC_TI_PCI1225: 6283 case PCIC_TI_PCI1410: 6284 case PCIC_ENE_1410: 6285 case PCIC_TI_PCI1510: 6286 case PCIC_TI_PCI1520: 6287 case PCIC_TI_PCI1420: 6288 case PCIC_ENE_1420: 6289 /* 6290 * This maps I/O interrupts to ExCA which 6291 * have been turned off by the write to 6292 * PCIC_INTERRUPT above. It would appear to 6293 * be the only way to actually turn I/O Ints off 6294 * while retaining CS Ints. 6295 */ 6296 brdgctl = ddi_get16(pcic->cfg_handle, 6297 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6298 pcic_err(NULL, 1, 6299 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6300 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6301 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6302 ddi_put16(pcic->cfg_handle, 6303 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6304 brdgctl); 6305 /* Flush the write */ 6306 (void) ddi_get16(pcic->cfg_handle, 6307 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6308 break; 6309 default: 6310 break; 6311 } 6312 } 6313 6314 static void 6315 pcic_cb_enable_intr(dev_info_t *dip) 6316 { 6317 anp_t *anp = ddi_get_driver_private(dip); 6318 pcicdev_t *pcic = anp->an_private; 6319 6320 mutex_enter(&pcic->pc_lock); 6321 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6322 mutex_exit(&pcic->pc_lock); 6323 } 6324 6325 static void 6326 pcic_cb_disable_intr(dev_info_t *dip) 6327 { 6328 anp_t *anp = ddi_get_driver_private(dip); 6329 pcicdev_t *pcic = anp->an_private; 6330 6331 mutex_enter(&pcic->pc_lock); 6332 pcic_disable_io_intr(pcic, 0); 6333 mutex_exit(&pcic->pc_lock); 6334 } 6335 6336 #if defined(__sparc) 6337 static int 6338 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6339 { 6340 int nerr = 0; 6341 if (e & PCI_STAT_PERROR) { 6342 nerr++; 6343 cmn_err(CE_CONT, "detected parity error.\n"); 6344 } 6345 if (e & PCI_STAT_S_SYSERR) { 6346 nerr++; 6347 if (bridge_secondary) 6348 cmn_err(CE_CONT, "received system error.\n"); 6349 else 6350 cmn_err(CE_CONT, "signalled system error.\n"); 6351 } 6352 if (e & PCI_STAT_R_MAST_AB) { 6353 nerr++; 6354 cmn_err(CE_CONT, "received master abort.\n"); 6355 } 6356 if (e & PCI_STAT_R_TARG_AB) 6357 cmn_err(CE_CONT, "received target abort.\n"); 6358 if (e & PCI_STAT_S_TARG_AB) 6359 cmn_err(CE_CONT, "signalled target abort\n"); 6360 if (e & PCI_STAT_S_PERROR) { 6361 nerr++; 6362 cmn_err(CE_CONT, "signalled parity error\n"); 6363 } 6364 return (nerr); 6365 } 6366 6367 static int 6368 pcic_fault(enum pci_fault_ops op, void *arg) 6369 { 6370 pcicdev_t *pcic = (pcicdev_t *)arg; 6371 ushort_t pci_cfg_stat = 6372 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6373 ushort_t pci_cfg_sec_stat = 6374 pci_config_get16(pcic->cfg_handle, 0x16); 6375 char nm[24]; 6376 int nerr = 0; 6377 6378 cardbus_dump_pci_config(pcic->dip); 6379 6380 switch (op) { 6381 case FAULT_LOG: 6382 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6383 ddi_get_instance(pcic->dip)); 6384 6385 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6386 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6387 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6388 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6389 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6390 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6391 return (nerr); 6392 case FAULT_POKEFINI: 6393 case FAULT_RESET: 6394 pci_config_put16(pcic->cfg_handle, 6395 PCI_CONF_STAT, pci_cfg_stat); 6396 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6397 break; 6398 case FAULT_POKEFLT: 6399 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6400 return (1); 6401 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6402 return (1); 6403 break; 6404 default: 6405 break; 6406 } 6407 return (DDI_SUCCESS); 6408 } 6409 #endif 6410 6411 static void 6412 pcic_do_resume(pcicdev_t *pcic) 6413 { 6414 int i, interrupt; 6415 uint8_t cfg; 6416 6417 6418 #if defined(PCIC_DEBUG) 6419 pcic_err(NULL, 6, "pcic_do_resume(): entered\n"); 6420 #endif 6421 6422 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6423 for (i = 0; i < pcic->pc_numsockets; i++) { 6424 /* Enable interrupts on PCI if needs be */ 6425 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6426 if (pcic->pc_flags & PCF_USE_SMI) 6427 interrupt |= PCIC_INTR_ENABLE; 6428 pcic_putb(pcic, i, PCIC_INTERRUPT, 6429 PCIC_RESET | interrupt); 6430 pcic->pc_sockets[i].pcs_debounce_id = 6431 pcic_add_debqueue(&pcic->pc_sockets[i], 6432 drv_usectohz(pcic_debounce_time)); 6433 } 6434 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6435 if (pcic_do_pcmcia_sr) 6436 (void) pcmcia_wait_insert(pcic->dip); 6437 /* 6438 * The CardBus controller may be in RESET state after the 6439 * system is resumed from sleeping. The RESET bit is in 6440 * the Bridge Control register. This is true for all(TI, 6441 * Toshiba ToPIC95/97, RICOH, and O2Micro) CardBus 6442 * controllers. Need to clear the RESET bit explicitly. 6443 */ 6444 cfg = ddi_get8(pcic->cfg_handle, 6445 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 6446 if (cfg & (1<<6)) { 6447 cfg &= ~(1<<6); 6448 ddi_put8(pcic->cfg_handle, 6449 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 6450 cfg); 6451 cfg = ddi_get8(pcic->cfg_handle, 6452 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 6453 if (cfg & (1<<6)) { 6454 pcic_err(pcic->dip, 1, 6455 "Failed to take pcic out of reset"); 6456 } 6457 } 6458 6459 } 6460 6461 static void 6462 pcic_debounce(pcic_socket_t *pcs) 6463 { 6464 uint8_t status, stschng; 6465 6466 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6467 pcs->pcs_flags &= ~PCS_STARTING; 6468 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6469 PCIC_CARD_STATUS_CHANGE); 6470 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6471 PCIC_INTERFACE_STATUS); 6472 #ifdef PCIC_DEBUG 6473 pcic_err(pcs->pcs_pcic->dip, 8, 6474 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6475 "chg 0x%x flg 0x%x\n", 6476 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6477 status, stschng, pcs->pcs_flags); 6478 #endif 6479 6480 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6481 PCIC_CD_DETECT); 6482 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6483 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6484 } 6485 6486 static void 6487 pcic_deb_thread() 6488 { 6489 callb_cpr_t cprinfo; 6490 struct debounce *debp; 6491 clock_t lastt; 6492 6493 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6494 callb_generic_cpr, "pcic debounce thread"); 6495 mutex_enter(&pcic_deb_mtx); 6496 while (pcic_deb_threadid) { 6497 while (pcic_deb_queue) { 6498 #ifdef PCIC_DEBUG 6499 pcic_dump_debqueue("Thread"); 6500 #endif 6501 debp = pcic_deb_queue; 6502 (void) drv_getparm(LBOLT, &lastt); 6503 if (lastt >= debp->expire) { 6504 pcic_deb_queue = debp->next; 6505 mutex_exit(&pcic_deb_mtx); 6506 pcic_debounce(debp->pcs); 6507 mutex_enter(&pcic_deb_mtx); 6508 kmem_free(debp, sizeof (*debp)); 6509 } else { 6510 (void) cv_timedwait(&pcic_deb_cv, 6511 &pcic_deb_mtx, debp->expire); 6512 } 6513 } 6514 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6515 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6516 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6517 } 6518 pcic_deb_threadid = (kthread_t *)1; 6519 cv_signal(&pcic_deb_cv); 6520 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6521 thread_exit(); 6522 } 6523 6524 static void * 6525 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6526 { 6527 clock_t lbolt; 6528 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6529 6530 (void) drv_getparm(LBOLT, &lbolt); 6531 dbp = kmem_alloc(sizeof (struct debounce), KM_SLEEP); 6532 6533 dbp->expire = lbolt + clocks; 6534 dbp->pcs = pcs; 6535 mutex_enter(&pcic_deb_mtx); 6536 while (*dbpp) { 6537 if (dbp->expire > (*dbpp)->expire) 6538 dbpp = &((*dbpp)->next); 6539 else 6540 break; 6541 } 6542 dbp->next = *dbpp; 6543 *dbpp = dbp; 6544 #ifdef PCIC_DEBUG 6545 pcic_dump_debqueue("Add"); 6546 #endif 6547 cv_signal(&pcic_deb_cv); 6548 mutex_exit(&pcic_deb_mtx); 6549 return (dbp); 6550 } 6551 6552 static void 6553 pcic_rm_debqueue(void *id) 6554 { 6555 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6556 6557 dbp = (struct debounce *)id; 6558 mutex_enter(&pcic_deb_mtx); 6559 while (*dbpp) { 6560 if (*dbpp == dbp) { 6561 *dbpp = dbp->next; 6562 kmem_free(dbp, sizeof (*dbp)); 6563 #ifdef PCIC_DEBUG 6564 pcic_dump_debqueue("Remove"); 6565 #endif 6566 cv_signal(&pcic_deb_cv); 6567 mutex_exit(&pcic_deb_mtx); 6568 return; 6569 } 6570 dbpp = &((*dbpp)->next); 6571 } 6572 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6573 mutex_exit(&pcic_deb_mtx); 6574 } 6575 6576 6577 static int pcic_powerdelay = 0; 6578 6579 static int 6580 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6581 { 6582 int ind, value, orig_pwrctl; 6583 6584 /* power setup -- if necessary */ 6585 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6586 6587 #if defined(PCIC_DEBUG) 6588 pcic_err(pcic->dip, 6, 6589 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6590 socket, powerlevel, orig_pwrctl); 6591 #endif 6592 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6593 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6594 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6595 if (powerlevel != orig_pwrctl) { 6596 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6597 int ifs; 6598 /* 6599 * set power to socket 6600 * note that the powerlevel was calculated earlier 6601 */ 6602 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6603 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6604 6605 /* 6606 * this second write to the power control register 6607 * is needed to resolve a problem on 6608 * the IBM ThinkPad 750 6609 * where the first write doesn't latch. 6610 * The second write appears to always work and 6611 * doesn't hurt the operation of other chips 6612 * so we can just use it -- this is good since we can't 6613 * determine what chip the 750 actually uses 6614 * (I suspect an early Ricoh). 6615 */ 6616 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6617 6618 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6619 pcic_mswait(pcic, socket, pcic_powerdelay); 6620 #if defined(PCIC_DEBUG) 6621 pcic_err(pcic->dip, 8, 6622 "\tpowerlevel reg = %x (ifs %x)\n", 6623 value, pcic_getb(pcic, socket, 6624 PCIC_INTERFACE_STATUS)); 6625 pcic_err(pcic->dip, 8, 6626 "CBus regs: PS 0x%x, Control 0x%x\n", 6627 pcic_getcb(pcic, CB_PRESENT_STATE), 6628 pcic_getcb(pcic, CB_CONTROL)); 6629 #endif 6630 /* 6631 * since power was touched, make sure it says it 6632 * is on. This lets it become stable. 6633 */ 6634 for (ind = 0; ind < 20; ind++) { 6635 ifs = pcic_getb(pcic, socket, 6636 PCIC_INTERFACE_STATUS); 6637 if (ifs & PCIC_POWER_ON) 6638 break; 6639 else { 6640 pcic_putb(pcic, socket, 6641 PCIC_POWER_CONTROL, 0); 6642 (void) pcic_getb(pcic, socket, 6643 PCIC_POWER_CONTROL); 6644 pcic_mswait(pcic, socket, 40); 6645 if (ind == 10) { 6646 pcic_putcb(pcic, CB_EVENT_FORCE, 6647 CB_EF_CVTEST); 6648 pcic_mswait(pcic, socket, 100); 6649 } 6650 pcic_putb(pcic, socket, 6651 PCIC_POWER_CONTROL, 6652 powerlevel & ~POWER_OUTPUT_ENABLE); 6653 (void) pcic_getb(pcic, socket, 6654 PCIC_POWER_CONTROL); 6655 pcic_mswait(pcic, socket, 6656 pcic_powerdelay); 6657 pcic_putb(pcic, socket, 6658 PCIC_POWER_CONTROL, powerlevel); 6659 (void) pcic_getb(pcic, socket, 6660 PCIC_POWER_CONTROL); 6661 pcic_mswait(pcic, socket, 6662 pcic_powerdelay); 6663 } 6664 } 6665 6666 if (!(ifs & PCIC_POWER_ON)) { 6667 cmn_err(CE_WARN, 6668 "pcic socket %d: Power didn't get turned" 6669 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6670 "misc1 0x%x igc 0x%x ind %d\n", 6671 socket, ifs, 6672 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6673 orig_pwrctl, 6674 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6675 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6676 ind); 6677 return (BAD_VCC); 6678 } 6679 #if defined(PCIC_DEBUG) 6680 pcic_err(pcic->dip, 8, 6681 "\tind = %d, if status %x pwrc 0x%x " 6682 "misc1 0x%x igc 0x%x\n", 6683 ind, ifs, 6684 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6685 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6686 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6687 #endif 6688 } else { 6689 /* explicitly turned off the power */ 6690 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6691 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6692 } 6693 } 6694 return (SUCCESS); 6695 } 6696 6697 static int pcic_cbdoreset_during_poweron = 1; 6698 static int 6699 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6700 { 6701 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6702 int ind, iobits; 6703 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6704 6705 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6706 6707 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6708 cbctl |= pcic_cbv_levels[ind]; 6709 6710 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6711 cbctl |= (pcic_cbv_levels[ind]<<4); 6712 6713 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6714 6715 #if defined(PCIC_DEBUG) 6716 pcic_err(pcic->dip, 6, 6717 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6718 "cbctl 0x%x->0x%x\n", 6719 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6720 #endif 6721 if (cbctl != orig_cbctl) { 6722 if (pcic_cbdoreset_during_poweron && 6723 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6724 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6725 pcic_putb(pcic, socket, PCIC_INTERRUPT, 6726 iobits & ~PCIC_RESET); 6727 } 6728 pcic_putcb(pcic, CB_CONTROL, cbctl); 6729 6730 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6731 pcic_mswait(pcic, socket, pcic_powerdelay); 6732 return (SUCCESS); 6733 } 6734 for (ind = 0; ind < 20; ind++) { 6735 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6736 6737 if (cbstev & CB_SE_POWER_CYCLE) { 6738 6739 /* 6740 * delay 400 ms: though the standard defines that the Vcc 6741 * set-up time is 20 ms, some PC-Card bridge requires longer 6742 * duration. 6743 * Note: We should check the status AFTER the delay to give time 6744 * for things to stabilize. 6745 */ 6746 pcic_mswait(pcic, socket, 400); 6747 6748 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6749 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6750 /* break; */ 6751 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6752 } 6753 if (cbctl & CB_PS_BADVCC) { 6754 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6755 break; 6756 } 6757 6758 #if defined(PCIC_DEBUG) 6759 pcic_err(pcic->dip, 8, 6760 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6761 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6762 cbctl, orig_cbctl); 6763 #endif 6764 if (pcic_cbdoreset_during_poweron && 6765 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6766 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6767 } 6768 return (SUCCESS); 6769 } 6770 pcic_mswait(pcic, socket, 40); 6771 } 6772 if (pcic_cbdoreset_during_poweron && 6773 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6774 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6775 } 6776 cmn_err(CE_WARN, 6777 "pcic socket %d: Power didn't get turned on/off!\n" 6778 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6779 "vcc %d vpp1 %d", socket, cbstev, 6780 pcic_getcb(pcic, CB_PRESENT_STATE), 6781 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6782 return (BAD_VCC); 6783 } 6784 return (SUCCESS); 6785 } 6786 6787 static int pcic_do_pprintf = 0; 6788 6789 #ifdef PCIC_DEBUG 6790 static void 6791 pcic_dump_debqueue(char *msg) 6792 { 6793 struct debounce *debp = pcic_deb_queue; 6794 clock_t lbolt; 6795 6796 (void) drv_getparm(LBOLT, &lbolt); 6797 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6798 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6799 while (debp) { 6800 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6801 (void *) debp, (int)debp->expire, (void *) debp->next, 6802 debp->pcs->pcs_debounce_id); 6803 debp = debp->next; 6804 } 6805 } 6806 #endif /* PCIC_DEBUG */ 6807 6808 6809 /* PRINTFLIKE3 */ 6810 static void 6811 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6812 { 6813 if (pcic_debug && (level <= pcic_debug)) { 6814 va_list adx; 6815 int instance; 6816 char buf[256]; 6817 const char *name; 6818 #if !defined(PCIC_DEBUG) 6819 int ce; 6820 char qmark = 0; 6821 6822 if (level <= 3) 6823 ce = CE_WARN; 6824 else 6825 ce = CE_CONT; 6826 if (level == 4) 6827 qmark = 1; 6828 #endif 6829 6830 if (dip) { 6831 instance = ddi_get_instance(dip); 6832 /* name = ddi_binding_name(dip); */ 6833 name = ddi_driver_name(dip); 6834 } else { 6835 instance = 0; 6836 name = ""; 6837 } 6838 6839 va_start(adx, fmt); 6840 (void) vsprintf(buf, fmt, adx); 6841 va_end(adx); 6842 6843 #if defined(PCIC_DEBUG) 6844 if (pcic_do_pprintf) { 6845 if (dip) { 6846 if (instance >= 0) 6847 prom_printf("%s(%d),0x%p: %s", name, 6848 instance, (void *)dip, buf); 6849 else 6850 prom_printf("%s,0x%p: %s", 6851 name, (void *)dip, buf); 6852 } else 6853 prom_printf(buf); 6854 } else { 6855 if (dip) { 6856 if (instance >= 0) 6857 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6858 name, instance, (void *) dip, buf); 6859 else 6860 cmn_err(CE_CONT, "%s,0x%p: %s", 6861 name, (void *) dip, buf); 6862 } else 6863 cmn_err(CE_CONT, buf); 6864 } 6865 #else 6866 if (dip) 6867 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6868 instance, buf); 6869 else 6870 cmn_err(ce, qmark ? "?%s" : buf, buf); 6871 #endif 6872 } 6873 } 6874