1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_mac.h> 30 31 static void nxge_get_niu_property(dev_info_t *, niu_type_t *); 32 static nxge_status_t nxge_get_mac_addr_properties(p_nxge_t); 33 static nxge_status_t nxge_use_cfg_n2niu_properties(p_nxge_t); 34 static void nxge_use_cfg_neptune_properties(p_nxge_t); 35 static void nxge_use_cfg_dma_config(p_nxge_t); 36 static void nxge_use_cfg_vlan_class_config(p_nxge_t); 37 static void nxge_use_cfg_mac_class_config(p_nxge_t); 38 static void nxge_use_cfg_class_config(p_nxge_t); 39 static void nxge_use_cfg_link_cfg(p_nxge_t); 40 static void nxge_set_hw_dma_config(p_nxge_t); 41 static void nxge_set_hw_vlan_class_config(p_nxge_t); 42 static void nxge_set_hw_mac_class_config(p_nxge_t); 43 static void nxge_set_hw_class_config(p_nxge_t); 44 static nxge_status_t nxge_use_default_dma_config_n2(p_nxge_t); 45 static void nxge_ldgv_setup(p_nxge_ldg_t *, p_nxge_ldv_t *, uint8_t, 46 uint8_t, int *); 47 static void nxge_init_mmac(p_nxge_t, boolean_t); 48 49 uint32_t nxge_use_hw_property = 1; 50 uint32_t nxge_groups_per_port = 2; 51 52 extern uint32_t nxge_use_partition; 53 extern uint32_t nxge_dma_obp_props_only; 54 55 extern uint16_t nxge_rcr_timeout; 56 extern uint16_t nxge_rcr_threshold; 57 58 extern uint_t nxge_rx_intr(void *, void *); 59 extern uint_t nxge_tx_intr(void *, void *); 60 extern uint_t nxge_mif_intr(void *, void *); 61 extern uint_t nxge_mac_intr(void *, void *); 62 extern uint_t nxge_syserr_intr(void *, void *); 63 extern void *nxge_list; 64 65 #define NXGE_SHARED_REG_SW_SIM 66 67 #ifdef NXGE_SHARED_REG_SW_SIM 68 uint64_t global_dev_ctrl = 0; 69 #endif 70 71 #define MAX_SIBLINGS NXGE_MAX_PORTS 72 73 extern uint32_t nxge_rbr_size; 74 extern uint32_t nxge_rcr_size; 75 extern uint32_t nxge_tx_ring_size; 76 extern uint32_t nxge_rbr_spare_size; 77 78 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 79 80 static uint8_t p2_tx_fair[2] = {12, 12}; 81 static uint8_t p2_tx_equal[2] = {12, 12}; 82 static uint8_t p4_tx_fair[4] = {6, 6, 6, 6}; 83 static uint8_t p4_tx_equal[4] = {6, 6, 6, 6}; 84 static uint8_t p2_rx_fair[2] = {8, 8}; 85 static uint8_t p2_rx_equal[2] = {8, 8}; 86 static uint8_t p4_rx_fair[4] = {4, 4, 4, 4}; 87 static uint8_t p4_rx_equal[4] = {4, 4, 4, 4}; 88 89 static uint8_t p2_rdcgrp_fair[2] = {4, 4}; 90 static uint8_t p2_rdcgrp_equal[2] = {4, 4}; 91 static uint8_t p4_rdcgrp_fair[4] = {2, 2, 1, 1}; 92 static uint8_t p4_rdcgrp_equal[4] = {2, 2, 2, 2}; 93 static uint8_t p2_rdcgrp_cls[2] = {1, 1}; 94 static uint8_t p4_rdcgrp_cls[4] = {1, 1, 1, 1}; 95 96 static uint8_t rx_4_1G[4] = {4, 4, 4, 4}; 97 static uint8_t rx_2_10G[2] = {8, 8}; 98 static uint8_t rx_2_10G_2_1G[4] = {6, 6, 2, 2}; 99 static uint8_t rx_1_10G_3_1G[4] = {10, 2, 2, 2}; 100 static uint8_t rx_1_1G_1_10G_2_1G[4] = {2, 10, 2, 2}; 101 102 static uint8_t tx_4_1G[4] = {6, 6, 6, 6}; 103 static uint8_t tx_2_10G[2] = {12, 12}; 104 static uint8_t tx_2_10G_2_1G[4] = {10, 10, 2, 2}; 105 static uint8_t tx_1_10G_3_1G[4] = {12, 4, 4, 4}; 106 static uint8_t tx_1_1G_1_10G_2_1G[4] = {4, 12, 4, 4}; 107 108 typedef enum { 109 DEFAULT = 0, 110 EQUAL, 111 FAIR, 112 CUSTOM, 113 CLASSIFY, 114 L2_CLASSIFY, 115 L3_DISTRIBUTE, 116 L3_CLASSIFY, 117 L3_TCAM, 118 CONFIG_TOKEN_NONE 119 } config_token_t; 120 121 static char *token_names[] = { 122 "default", 123 "equal", 124 "fair", 125 "custom", 126 "classify", 127 "l2_classify", 128 "l3_distribute", 129 "l3_classify", 130 "l3_tcam", 131 "none", 132 }; 133 134 void nxge_virint_regs_dump(p_nxge_t nxgep); 135 136 void 137 nxge_virint_regs_dump(p_nxge_t nxgep) 138 { 139 npi_handle_t handle; 140 141 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_virint_regs_dump")); 142 handle = NXGE_DEV_NPI_HANDLE(nxgep); 143 (void) npi_vir_dump_pio_fzc_regs_one(handle); 144 (void) npi_vir_dump_ldgnum(handle); 145 (void) npi_vir_dump_ldsv(handle); 146 (void) npi_vir_dump_imask0(handle); 147 (void) npi_vir_dump_sid(handle); 148 (void) npi_mac_dump_regs(handle, nxgep->function_num); 149 (void) npi_ipp_dump_regs(handle, nxgep->function_num); 150 (void) npi_fflp_dump_regs(handle); 151 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_virint_regs_dump")); 152 } 153 154 /* 155 * For now: we hard coded the DMA configurations. 156 * and assume for one partition only. 157 * 158 * OBP. Then OBP will pass this partition's 159 * Neptune configurations to fcode to create 160 * properties for them. 161 * 162 * Since Neptune(PCI-E) and NIU (Niagara-2) has 163 * different bus interfaces, the driver needs 164 * to know which bus it is connected to. 165 * Ravinder suggested: create a device property. 166 * In partitioning environment, we cannot 167 * use .conf file (need to check). If conf changes, 168 * need to reboot the system. 169 * The following function assumes that we will 170 * retrieve its properties from a virtualized nexus driver. 171 */ 172 173 nxge_status_t 174 nxge_cntlops(dev_info_t *dip, nxge_ctl_enum_t ctlop, void *arg, void *result) 175 { 176 nxge_status_t status = NXGE_OK; 177 int instance; 178 p_nxge_t nxgep; 179 180 #ifndef NXGE_SHARED_REG_SW_SIM 181 npi_handle_t handle; 182 uint16_t sr16, cr16; 183 #endif 184 instance = ddi_get_instance(dip); 185 NXGE_DEBUG_MSG((NULL, VIR_CTL, "Instance %d ", instance)); 186 187 if (nxge_list == NULL) { 188 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 189 "nxge_cntlops: nxge_list null")); 190 return (NXGE_ERROR); 191 } 192 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 193 if (nxgep == NULL) { 194 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 195 "nxge_cntlops: nxgep null")); 196 return (NXGE_ERROR); 197 } 198 #ifndef NXGE_SHARED_REG_SW_SIM 199 handle = nxgep->npi_reg_handle; 200 #endif 201 switch (ctlop) { 202 case NXGE_CTLOPS_NIUTYPE: 203 nxge_get_niu_property(dip, (niu_type_t *)result); 204 return (status); 205 206 case NXGE_CTLOPS_GET_SHARED_REG: 207 #ifdef NXGE_SHARED_REG_SW_SIM 208 *(uint64_t *)result = global_dev_ctrl; 209 return (0); 210 #else 211 status = npi_dev_func_sr_sr_get(handle, &sr16); 212 *(uint16_t *)result = sr16; 213 NXGE_DEBUG_MSG((NULL, VIR_CTL, 214 "nxge_cntlops: NXGE_CTLOPS_GET_SHARED_REG")); 215 return (0); 216 #endif 217 218 case NXGE_CTLOPS_SET_SHARED_REG_LOCK: 219 #ifdef NXGE_SHARED_REG_SW_SIM 220 global_dev_ctrl = *(uint64_t *)arg; 221 return (0); 222 #else 223 status = NPI_FAILURE; 224 while (status != NPI_SUCCESS) 225 status = npi_dev_func_sr_lock_enter(handle); 226 227 sr16 = *(uint16_t *)arg; 228 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 229 status = npi_dev_func_sr_lock_free(handle); 230 NXGE_DEBUG_MSG((NULL, VIR_CTL, 231 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 232 return (0); 233 #endif 234 235 case NXGE_CTLOPS_UPDATE_SHARED_REG: 236 #ifdef NXGE_SHARED_REG_SW_SIM 237 global_dev_ctrl |= *(uint64_t *)arg; 238 return (0); 239 #else 240 status = NPI_FAILURE; 241 while (status != NPI_SUCCESS) 242 status = npi_dev_func_sr_lock_enter(handle); 243 status = npi_dev_func_sr_sr_get(handle, &sr16); 244 sr16 |= *(uint16_t *)arg; 245 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 246 status = npi_dev_func_sr_lock_free(handle); 247 NXGE_DEBUG_MSG((NULL, VIR_CTL, 248 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 249 return (0); 250 #endif 251 252 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG_UL: 253 #ifdef NXGE_SHARED_REG_SW_SIM 254 global_dev_ctrl |= *(uint64_t *)arg; 255 return (0); 256 #else 257 status = npi_dev_func_sr_sr_get(handle, &sr16); 258 cr16 = *(uint16_t *)arg; 259 sr16 &= ~cr16; 260 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 261 NXGE_DEBUG_MSG((NULL, VIR_CTL, 262 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 263 return (0); 264 #endif 265 266 case NXGE_CTLOPS_CLEAR_BIT_SHARED_REG: 267 #ifdef NXGE_SHARED_REG_SW_SIM 268 global_dev_ctrl |= *(uint64_t *)arg; 269 return (0); 270 #else 271 status = NPI_FAILURE; 272 while (status != NPI_SUCCESS) 273 status = npi_dev_func_sr_lock_enter(handle); 274 status = npi_dev_func_sr_sr_get(handle, &sr16); 275 cr16 = *(uint16_t *)arg; 276 sr16 &= ~cr16; 277 status = npi_dev_func_sr_sr_set_only(handle, &sr16); 278 status = npi_dev_func_sr_lock_free(handle); 279 NXGE_DEBUG_MSG((NULL, VIR_CTL, 280 "nxge_cntlops: NXGE_CTLOPS_SET_SHARED_REG")); 281 return (0); 282 #endif 283 284 case NXGE_CTLOPS_GET_LOCK_BLOCK: 285 #ifdef NXGE_SHARED_REG_SW_SIM 286 global_dev_ctrl |= *(uint64_t *)arg; 287 return (0); 288 #else 289 status = NPI_FAILURE; 290 while (status != NPI_SUCCESS) 291 status = npi_dev_func_sr_lock_enter(handle); 292 NXGE_DEBUG_MSG((NULL, VIR_CTL, 293 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_BLOCK")); 294 return (0); 295 #endif 296 case NXGE_CTLOPS_GET_LOCK_TRY: 297 #ifdef NXGE_SHARED_REG_SW_SIM 298 global_dev_ctrl |= *(uint64_t *)arg; 299 return (0); 300 #else 301 status = npi_dev_func_sr_lock_enter(handle); 302 NXGE_DEBUG_MSG((NULL, VIR_CTL, 303 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_TRY")); 304 if (status == NPI_SUCCESS) 305 return (NXGE_OK); 306 else 307 return (NXGE_ERROR); 308 #endif 309 case NXGE_CTLOPS_FREE_LOCK: 310 #ifdef NXGE_SHARED_REG_SW_SIM 311 global_dev_ctrl |= *(uint64_t *)arg; 312 return (0); 313 #else 314 status = npi_dev_func_sr_lock_free(handle); 315 NXGE_DEBUG_MSG((NULL, VIR_CTL, 316 "nxge_cntlops: NXGE_CTLOPS_GET_LOCK_FREE")); 317 if (status == NPI_SUCCESS) 318 return (NXGE_OK); 319 else 320 return (NXGE_ERROR); 321 #endif 322 323 default: 324 status = NXGE_ERROR; 325 } 326 327 return (status); 328 } 329 330 void 331 nxge_common_lock_get(p_nxge_t nxgep) 332 { 333 uint32_t status = NPI_FAILURE; 334 npi_handle_t handle; 335 336 #if defined(NXGE_SHARE_REG_SW_SIM) 337 return; 338 #endif 339 handle = nxgep->npi_reg_handle; 340 while (status != NPI_SUCCESS) 341 status = npi_dev_func_sr_lock_enter(handle); 342 } 343 344 void 345 nxge_common_lock_free(p_nxge_t nxgep) 346 { 347 npi_handle_t handle; 348 349 #if defined(NXGE_SHARE_REG_SW_SIM) 350 return; 351 #endif 352 handle = nxgep->npi_reg_handle; 353 (void) npi_dev_func_sr_lock_free(handle); 354 } 355 356 357 static void 358 nxge_get_niu_property(dev_info_t *dip, niu_type_t *niu_type) 359 { 360 uchar_t *prop_val; 361 uint_t prop_len; 362 363 *niu_type = NIU_TYPE_NONE; 364 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, 365 "niu-type", (uchar_t **)&prop_val, 366 &prop_len) == DDI_PROP_SUCCESS) { 367 if (strncmp("niu", (caddr_t)prop_val, (size_t)prop_len) == 0) { 368 *niu_type = N2_NIU; 369 } 370 ddi_prop_free(prop_val); 371 } 372 } 373 374 static config_token_t 375 nxge_get_config_token(char *prop) 376 { 377 config_token_t token = DEFAULT; 378 379 while (token < CONFIG_TOKEN_NONE) { 380 if (strncmp(prop, token_names[token], 4) == 0) 381 break; 382 token++; 383 } 384 return (token); 385 } 386 387 /* per port */ 388 389 static nxge_status_t 390 nxge_update_rxdma_grp_properties(p_nxge_t nxgep, config_token_t token, 391 dev_info_t *s_dip[]) 392 { 393 nxge_status_t status = NXGE_OK; 394 int ddi_status; 395 int num_ports = nxgep->nports; 396 int port, bits, j; 397 uint8_t start_grp = 0, num_grps = 0; 398 p_nxge_param_t param_arr; 399 uint32_t grp_bitmap[MAX_SIBLINGS]; 400 int custom_start_grp[MAX_SIBLINGS]; 401 int custom_num_grp[MAX_SIBLINGS]; 402 uint8_t bad_config = B_FALSE; 403 char *start_prop, *num_prop, *cfg_prop; 404 405 start_grp = 0; 406 param_arr = nxgep->param_arr; 407 start_prop = param_arr[param_rdc_grps_start].fcode_name; 408 num_prop = param_arr[param_rx_rdc_grps].fcode_name; 409 410 switch (token) { 411 case FAIR: 412 cfg_prop = "fair"; 413 for (port = 0; port < num_ports; port++) { 414 custom_num_grp[port] = 415 (num_ports == 4) ? 416 p4_rdcgrp_fair[port] : 417 p2_rdcgrp_fair[port]; 418 custom_start_grp[port] = start_grp; 419 start_grp += custom_num_grp[port]; 420 } 421 break; 422 423 case EQUAL: 424 cfg_prop = "equal"; 425 for (port = 0; port < num_ports; port++) { 426 custom_num_grp[port] = 427 (num_ports == 4) ? 428 p4_rdcgrp_equal[port] : 429 p2_rdcgrp_equal[port]; 430 custom_start_grp[port] = start_grp; 431 start_grp += custom_num_grp[port]; 432 } 433 break; 434 435 436 case CLASSIFY: 437 cfg_prop = "classify"; 438 for (port = 0; port < num_ports; port++) { 439 custom_num_grp[port] = (num_ports == 4) ? 440 p4_rdcgrp_cls[port] : p2_rdcgrp_cls[port]; 441 custom_start_grp[port] = start_grp; 442 start_grp += custom_num_grp[port]; 443 } 444 break; 445 446 case CUSTOM: 447 cfg_prop = "custom"; 448 /* See if it is good config */ 449 num_grps = 0; 450 for (port = 0; port < num_ports; port++) { 451 custom_start_grp[port] = 452 ddi_prop_get_int(DDI_DEV_T_NONE, s_dip[port], 453 DDI_PROP_DONTPASS, start_prop, -1); 454 if ((custom_start_grp[port] == -1) || 455 (custom_start_grp[port] >= 456 NXGE_MAX_RDC_GRPS)) { 457 bad_config = B_TRUE; 458 break; 459 } 460 custom_num_grp[port] = ddi_prop_get_int( 461 DDI_DEV_T_NONE, 462 s_dip[port], 463 DDI_PROP_DONTPASS, 464 num_prop, -1); 465 466 if ((custom_num_grp[port] == -1) || 467 (custom_num_grp[port] > 468 NXGE_MAX_RDC_GRPS) || 469 ((custom_num_grp[port] + 470 custom_start_grp[port]) >= 471 NXGE_MAX_RDC_GRPS)) { 472 bad_config = B_TRUE; 473 break; 474 } 475 num_grps += custom_num_grp[port]; 476 if (num_grps > NXGE_MAX_RDC_GRPS) { 477 bad_config = B_TRUE; 478 break; 479 } 480 grp_bitmap[port] = 0; 481 for (bits = 0; 482 bits < custom_num_grp[port]; 483 bits++) { 484 grp_bitmap[port] |= 485 (1 << (bits + custom_start_grp[port])); 486 } 487 488 } 489 490 if (bad_config == B_FALSE) { 491 /* check for overlap */ 492 for (port = 0; port < num_ports - 1; port++) { 493 for (j = port + 1; j < num_ports; j++) { 494 if (grp_bitmap[port] & 495 grp_bitmap[j]) { 496 bad_config = B_TRUE; 497 break; 498 } 499 } 500 if (bad_config == B_TRUE) 501 break; 502 } 503 } 504 if (bad_config == B_TRUE) { 505 /* use default config */ 506 for (port = 0; port < num_ports; port++) { 507 custom_num_grp[port] = 508 (num_ports == 4) ? 509 p4_rx_fair[port] : p2_rx_fair[port]; 510 custom_start_grp[port] = start_grp; 511 start_grp += custom_num_grp[port]; 512 } 513 } 514 break; 515 516 default: 517 /* use default config */ 518 cfg_prop = "fair"; 519 for (port = 0; port < num_ports; port++) { 520 custom_num_grp[port] = (num_ports == 4) ? 521 p4_rx_fair[port] : p2_rx_fair[port]; 522 custom_start_grp[port] = start_grp; 523 start_grp += custom_num_grp[port]; 524 } 525 break; 526 } 527 528 /* Now Update the rx properties */ 529 for (port = 0; port < num_ports; port++) { 530 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 531 "rxdma-grp-cfg", cfg_prop); 532 if (ddi_status != DDI_PROP_SUCCESS) { 533 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 534 " property %s not updating", 535 cfg_prop)); 536 status |= NXGE_DDI_FAILED; 537 } 538 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 539 num_prop, custom_num_grp[port]); 540 541 if (ddi_status != DDI_PROP_SUCCESS) { 542 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 543 " property %s not updating", 544 num_prop)); 545 status |= NXGE_DDI_FAILED; 546 } 547 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 548 start_prop, custom_start_grp[port]); 549 550 if (ddi_status != DDI_PROP_SUCCESS) { 551 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 552 " property %s not updating", 553 start_prop)); 554 status |= NXGE_DDI_FAILED; 555 } 556 } 557 if (status & NXGE_DDI_FAILED) 558 status |= NXGE_ERROR; 559 560 return (status); 561 } 562 563 static nxge_status_t 564 nxge_update_rxdma_properties(p_nxge_t nxgep, config_token_t token, 565 dev_info_t *s_dip[]) 566 { 567 nxge_status_t status = NXGE_OK; 568 int ddi_status; 569 int num_ports = nxgep->nports; 570 int port, bits, j; 571 uint8_t start_rdc = 0, num_rdc = 0; 572 p_nxge_param_t param_arr; 573 uint32_t rdc_bitmap[MAX_SIBLINGS]; 574 int custom_start_rdc[MAX_SIBLINGS]; 575 int custom_num_rdc[MAX_SIBLINGS]; 576 uint8_t bad_config = B_FALSE; 577 int *prop_val; 578 uint_t prop_len; 579 char *start_rdc_prop, *num_rdc_prop, *cfg_prop; 580 581 start_rdc = 0; 582 param_arr = nxgep->param_arr; 583 start_rdc_prop = param_arr[param_rxdma_channels_begin].fcode_name; 584 num_rdc_prop = param_arr[param_rxdma_channels].fcode_name; 585 586 switch (token) { 587 case FAIR: 588 cfg_prop = "fair"; 589 for (port = 0; port < num_ports; port++) { 590 custom_num_rdc[port] = (num_ports == 4) ? 591 p4_rx_fair[port] : p2_rx_fair[port]; 592 custom_start_rdc[port] = start_rdc; 593 start_rdc += custom_num_rdc[port]; 594 } 595 break; 596 597 case EQUAL: 598 cfg_prop = "equal"; 599 for (port = 0; port < num_ports; port++) { 600 custom_num_rdc[port] = (num_ports == 4) ? 601 p4_rx_equal[port] : 602 p2_rx_equal[port]; 603 custom_start_rdc[port] = start_rdc; 604 start_rdc += custom_num_rdc[port]; 605 } 606 break; 607 608 case CUSTOM: 609 cfg_prop = "custom"; 610 /* See if it is good config */ 611 num_rdc = 0; 612 for (port = 0; port < num_ports; port++) { 613 ddi_status = ddi_prop_lookup_int_array( 614 DDI_DEV_T_ANY, 615 s_dip[port], 0, 616 start_rdc_prop, 617 &prop_val, 618 &prop_len); 619 if (ddi_status == DDI_SUCCESS) 620 custom_start_rdc[port] = *prop_val; 621 else { 622 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 623 " %s custom start port %d" 624 " read failed ", 625 " rxdma-cfg", port)); 626 bad_config = B_TRUE; 627 status |= NXGE_DDI_FAILED; 628 } 629 if ((custom_start_rdc[port] == -1) || 630 (custom_start_rdc[port] >= 631 NXGE_MAX_RDCS)) { 632 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 633 " %s custom start %d" 634 " out of range %x ", 635 " rxdma-cfg", 636 port, 637 custom_start_rdc[port])); 638 bad_config = B_TRUE; 639 break; 640 } 641 ddi_status = ddi_prop_lookup_int_array( 642 DDI_DEV_T_ANY, 643 s_dip[port], 644 0, 645 num_rdc_prop, 646 &prop_val, 647 &prop_len); 648 649 if (ddi_status == DDI_SUCCESS) 650 custom_num_rdc[port] = *prop_val; 651 else { 652 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 653 " %s custom num port %d" 654 " read failed ", 655 "rxdma-cfg", port)); 656 bad_config = B_TRUE; 657 status |= NXGE_DDI_FAILED; 658 } 659 660 if ((custom_num_rdc[port] == -1) || 661 (custom_num_rdc[port] > 662 NXGE_MAX_RDCS) || 663 ((custom_num_rdc[port] + 664 custom_start_rdc[port]) > 665 NXGE_MAX_RDCS)) { 666 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 667 " %s custom num %d" 668 " out of range %x ", 669 " rxdma-cfg", 670 port, custom_num_rdc[port])); 671 bad_config = B_TRUE; 672 break; 673 } 674 num_rdc += custom_num_rdc[port]; 675 if (num_rdc > NXGE_MAX_RDCS) { 676 bad_config = B_TRUE; 677 break; 678 } 679 rdc_bitmap[port] = 0; 680 for (bits = 0; 681 bits < custom_num_rdc[port]; bits++) { 682 rdc_bitmap[port] |= 683 (1 << (bits + custom_start_rdc[port])); 684 } 685 } 686 687 if (bad_config == B_FALSE) { 688 /* check for overlap */ 689 for (port = 0; port < num_ports - 1; port++) { 690 for (j = port + 1; j < num_ports; j++) { 691 if (rdc_bitmap[port] & 692 rdc_bitmap[j]) { 693 NXGE_DEBUG_MSG((nxgep, 694 CFG_CTL, 695 " rxdma-cfg" 696 " property custom" 697 " bit overlap" 698 " %d %d ", 699 port, j)); 700 bad_config = B_TRUE; 701 break; 702 } 703 } 704 if (bad_config == B_TRUE) 705 break; 706 } 707 } 708 if (bad_config == B_TRUE) { 709 /* use default config */ 710 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 711 " rxdma-cfg property:" 712 " bad custom config:" 713 " use default")); 714 for (port = 0; port < num_ports; port++) { 715 custom_num_rdc[port] = 716 (num_ports == 4) ? 717 p4_rx_fair[port] : 718 p2_rx_fair[port]; 719 custom_start_rdc[port] = start_rdc; 720 start_rdc += custom_num_rdc[port]; 721 } 722 } 723 break; 724 725 default: 726 /* use default config */ 727 cfg_prop = "fair"; 728 for (port = 0; port < num_ports; port++) { 729 custom_num_rdc[port] = (num_ports == 4) ? 730 p4_rx_fair[port] : p2_rx_fair[port]; 731 custom_start_rdc[port] = start_rdc; 732 start_rdc += custom_num_rdc[port]; 733 } 734 break; 735 } 736 737 /* Now Update the rx properties */ 738 for (port = 0; port < num_ports; port++) { 739 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 740 " update property rxdma-cfg with %s ", cfg_prop)); 741 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 742 "rxdma-cfg", cfg_prop); 743 if (ddi_status != DDI_PROP_SUCCESS) { 744 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 745 " property rxdma-cfg is not updating to %s", 746 cfg_prop)); 747 status |= NXGE_DDI_FAILED; 748 } 749 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 750 num_rdc_prop, custom_num_rdc[port])); 751 752 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 753 num_rdc_prop, custom_num_rdc[port]); 754 755 if (ddi_status != DDI_PROP_SUCCESS) { 756 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 757 " property %s not updating with %d", 758 num_rdc_prop, custom_num_rdc[port])); 759 status |= NXGE_DDI_FAILED; 760 } 761 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 762 start_rdc_prop, custom_start_rdc[port])); 763 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 764 start_rdc_prop, custom_start_rdc[port]); 765 766 if (ddi_status != DDI_PROP_SUCCESS) { 767 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 768 " property %s not updating with %d ", 769 start_rdc_prop, custom_start_rdc[port])); 770 status |= NXGE_DDI_FAILED; 771 } 772 } 773 if (status & NXGE_DDI_FAILED) 774 status |= NXGE_ERROR; 775 return (status); 776 } 777 778 static nxge_status_t 779 nxge_update_txdma_properties(p_nxge_t nxgep, config_token_t token, 780 dev_info_t *s_dip[]) 781 { 782 nxge_status_t status = NXGE_OK; 783 int ddi_status = DDI_SUCCESS; 784 int num_ports = nxgep->nports; 785 int port, bits, j; 786 uint8_t start_tdc = 0, num_tdc = 0; 787 p_nxge_param_t param_arr; 788 uint32_t tdc_bitmap[MAX_SIBLINGS]; 789 int custom_start_tdc[MAX_SIBLINGS]; 790 int custom_num_tdc[MAX_SIBLINGS]; 791 uint8_t bad_config = B_FALSE; 792 int *prop_val; 793 uint_t prop_len; 794 char *start_tdc_prop, *num_tdc_prop, *cfg_prop; 795 796 start_tdc = 0; 797 param_arr = nxgep->param_arr; 798 start_tdc_prop = param_arr[param_txdma_channels_begin].fcode_name; 799 num_tdc_prop = param_arr[param_txdma_channels].fcode_name; 800 801 switch (token) { 802 case FAIR: 803 cfg_prop = "fair"; 804 for (port = 0; port < num_ports; port++) { 805 custom_num_tdc[port] = (num_ports == 4) ? 806 p4_tx_fair[port] : p2_tx_fair[port]; 807 custom_start_tdc[port] = start_tdc; 808 start_tdc += custom_num_tdc[port]; 809 } 810 break; 811 812 case EQUAL: 813 cfg_prop = "equal"; 814 for (port = 0; port < num_ports; port++) { 815 custom_num_tdc[port] = (num_ports == 4) ? 816 p4_tx_equal[port] : p2_tx_equal[port]; 817 custom_start_tdc[port] = start_tdc; 818 start_tdc += custom_num_tdc[port]; 819 } 820 break; 821 822 case CUSTOM: 823 cfg_prop = "custom"; 824 /* See if it is good config */ 825 num_tdc = 0; 826 for (port = 0; port < num_ports; port++) { 827 ddi_status = ddi_prop_lookup_int_array( 828 DDI_DEV_T_ANY, s_dip[port], 0, start_tdc_prop, 829 &prop_val, &prop_len); 830 if (ddi_status == DDI_SUCCESS) 831 custom_start_tdc[port] = *prop_val; 832 else { 833 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 834 " %s custom start port %d" 835 " read failed ", " txdma-cfg", port)); 836 bad_config = B_TRUE; 837 status |= NXGE_DDI_FAILED; 838 } 839 840 if ((custom_start_tdc[port] == -1) || 841 (custom_start_tdc[port] >= 842 NXGE_MAX_RDCS)) { 843 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 844 " %s custom start %d" 845 " out of range %x ", " txdma-cfg", 846 port, custom_start_tdc[port])); 847 bad_config = B_TRUE; 848 break; 849 } 850 851 ddi_status = ddi_prop_lookup_int_array( 852 DDI_DEV_T_ANY, s_dip[port], 0, num_tdc_prop, 853 &prop_val, &prop_len); 854 if (ddi_status == DDI_SUCCESS) 855 custom_num_tdc[port] = *prop_val; 856 else { 857 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 858 " %s custom num port %d" 859 " read failed ", " txdma-cfg", port)); 860 bad_config = B_TRUE; 861 status |= NXGE_DDI_FAILED; 862 } 863 864 if ((custom_num_tdc[port] == -1) || 865 (custom_num_tdc[port] > 866 NXGE_MAX_TDCS) || 867 ((custom_num_tdc[port] + 868 custom_start_tdc[port]) > 869 NXGE_MAX_TDCS)) { 870 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 871 " %s custom num %d" 872 " out of range %x ", " rxdma-cfg", 873 port, custom_num_tdc[port])); 874 bad_config = B_TRUE; 875 break; 876 } 877 num_tdc += custom_num_tdc[port]; 878 if (num_tdc > NXGE_MAX_TDCS) { 879 bad_config = B_TRUE; 880 break; 881 } 882 tdc_bitmap[port] = 0; 883 for (bits = 0; 884 bits < custom_num_tdc[port]; bits++) { 885 tdc_bitmap[port] |= 886 (1 << 887 (bits + custom_start_tdc[port])); 888 } 889 890 } 891 892 if (bad_config == B_FALSE) { 893 /* check for overlap */ 894 for (port = 0; port < num_ports - 1; port++) { 895 for (j = port + 1; j < num_ports; j++) { 896 if (tdc_bitmap[port] & 897 tdc_bitmap[j]) { 898 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 899 " rxdma-cfg" 900 " property custom" 901 " bit overlap" 902 " %d %d ", 903 port, j)); 904 bad_config = B_TRUE; 905 break; 906 } 907 } 908 if (bad_config == B_TRUE) 909 break; 910 } 911 } 912 if (bad_config == B_TRUE) { 913 /* use default config */ 914 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 915 " txdma-cfg property:" 916 " bad custom config:" " use default")); 917 918 for (port = 0; port < num_ports; port++) { 919 custom_num_tdc[port] = (num_ports == 4) ? 920 p4_tx_fair[port] : p2_tx_fair[port]; 921 custom_start_tdc[port] = start_tdc; 922 start_tdc += custom_num_tdc[port]; 923 } 924 } 925 break; 926 927 default: 928 /* use default config */ 929 cfg_prop = "fair"; 930 for (port = 0; port < num_ports; port++) { 931 custom_num_tdc[port] = (num_ports == 4) ? 932 p4_tx_fair[port] : p2_tx_fair[port]; 933 custom_start_tdc[port] = start_tdc; 934 start_tdc += custom_num_tdc[port]; 935 } 936 break; 937 } 938 939 /* Now Update the tx properties */ 940 for (port = 0; port < num_ports; port++) { 941 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 942 " update property txdma-cfg with %s ", cfg_prop)); 943 ddi_status = ddi_prop_update_string(DDI_DEV_T_NONE, s_dip[port], 944 "txdma-cfg", cfg_prop); 945 if (ddi_status != DDI_PROP_SUCCESS) { 946 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 947 " property txdma-cfg is not updating to %s", 948 cfg_prop)); 949 status |= NXGE_DDI_FAILED; 950 } 951 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 952 num_tdc_prop, custom_num_tdc[port])); 953 954 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 955 num_tdc_prop, custom_num_tdc[port]); 956 957 if (ddi_status != DDI_PROP_SUCCESS) { 958 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 959 " property %s not updating with %d", 960 num_tdc_prop, 961 custom_num_tdc[port])); 962 status |= NXGE_DDI_FAILED; 963 } 964 965 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " update property %s with %d ", 966 start_tdc_prop, custom_start_tdc[port])); 967 968 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, s_dip[port], 969 start_tdc_prop, custom_start_tdc[port]); 970 if (ddi_status != DDI_PROP_SUCCESS) { 971 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 972 " property %s not updating with %d ", 973 start_tdc_prop, custom_start_tdc[port])); 974 status |= NXGE_DDI_FAILED; 975 } 976 } 977 if (status & NXGE_DDI_FAILED) 978 status |= NXGE_ERROR; 979 return (status); 980 } 981 982 static nxge_status_t 983 nxge_update_cfg_properties(p_nxge_t nxgep, uint32_t flags, 984 config_token_t token, dev_info_t *s_dip[]) 985 { 986 nxge_status_t status = NXGE_OK; 987 988 switch (flags) { 989 case COMMON_TXDMA_CFG: 990 if (nxge_dma_obp_props_only == 0) 991 status = nxge_update_txdma_properties(nxgep, 992 token, s_dip); 993 break; 994 case COMMON_RXDMA_CFG: 995 if (nxge_dma_obp_props_only == 0) 996 status = nxge_update_rxdma_properties(nxgep, 997 token, s_dip); 998 999 break; 1000 case COMMON_RXDMA_GRP_CFG: 1001 status = nxge_update_rxdma_grp_properties(nxgep, 1002 token, s_dip); 1003 break; 1004 default: 1005 return (NXGE_ERROR); 1006 } 1007 return (status); 1008 } 1009 1010 /* 1011 * verify consistence. 1012 * (May require publishing the properties on all the ports. 1013 * 1014 * What if properties are published on function 0 device only? 1015 * 1016 * 1017 * rxdma-cfg, txdma-cfg, rxdma-grp-cfg (required ) 1018 * What about class configs? 1019 * 1020 * If consistent, update the property on all the siblings. 1021 * set a flag on hardware shared register 1022 * The rest of the siblings will check the flag 1023 * if the flag is set, they will use the updated property 1024 * without doing any validation. 1025 */ 1026 1027 nxge_status_t 1028 nxge_cfg_verify_set_classify_prop(p_nxge_t nxgep, char *prop, 1029 uint64_t known_cfg, uint32_t override, dev_info_t *c_dip[]) 1030 { 1031 nxge_status_t status = NXGE_OK; 1032 int ddi_status = DDI_SUCCESS; 1033 int i = 0, found = 0, update_prop = B_TRUE; 1034 int *cfg_val; 1035 uint_t new_value, cfg_value[MAX_SIBLINGS]; 1036 uint_t prop_len; 1037 uint_t known_cfg_value; 1038 1039 known_cfg_value = (uint_t)known_cfg; 1040 1041 if (override == B_TRUE) { 1042 new_value = known_cfg_value; 1043 for (i = 0; i < nxgep->nports; i++) { 1044 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1045 c_dip[i], prop, new_value); 1046 #ifdef NXGE_DEBUG_ERROR 1047 if (ddi_status != DDI_PROP_SUCCESS) 1048 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1049 " property %s failed update ", prop)); 1050 #endif 1051 } 1052 if (ddi_status != DDI_PROP_SUCCESS) 1053 return (NXGE_ERROR | NXGE_DDI_FAILED); 1054 } 1055 for (i = 0; i < nxgep->nports; i++) { 1056 cfg_value[i] = known_cfg_value; 1057 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, c_dip[i], 0, 1058 prop, &cfg_val, 1059 &prop_len) == DDI_PROP_SUCCESS) { 1060 cfg_value[i] = *cfg_val; 1061 ddi_prop_free(cfg_val); 1062 found++; 1063 } 1064 } 1065 1066 if (found != i) { 1067 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1068 " property %s not specified on all ports", prop)); 1069 if (found == 0) { 1070 /* not specified: Use default */ 1071 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1072 " property %s not specified on any port:" 1073 " Using default", prop)); 1074 new_value = known_cfg_value; 1075 } else { 1076 /* specified on some */ 1077 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1078 " property %s not specified" 1079 " on some ports: Using default", prop)); 1080 /* ? use p0 value instead ? */ 1081 new_value = known_cfg_value; 1082 } 1083 } else { 1084 /* check type and consistence */ 1085 /* found on all devices */ 1086 for (i = 1; i < found; i++) { 1087 if (cfg_value[i] != cfg_value[i - 1]) { 1088 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1089 " property %s inconsistent:" 1090 " Using default", prop)); 1091 new_value = known_cfg_value; 1092 break; 1093 } 1094 /* 1095 * Found on all the ports and consistent. Nothing to 1096 * do. 1097 */ 1098 update_prop = B_FALSE; 1099 } 1100 } 1101 1102 if (update_prop == B_TRUE) { 1103 for (i = 0; i < nxgep->nports; i++) { 1104 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, 1105 c_dip[i], prop, new_value); 1106 #ifdef NXGE_DEBUG_ERROR 1107 if (ddi_status != DDI_SUCCESS) 1108 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1109 " property %s not updating with %d" 1110 " Using default", 1111 prop, new_value)); 1112 #endif 1113 if (ddi_status != DDI_PROP_SUCCESS) 1114 status |= NXGE_DDI_FAILED; 1115 } 1116 } 1117 if (status & NXGE_DDI_FAILED) 1118 status |= NXGE_ERROR; 1119 1120 return (status); 1121 } 1122 1123 static uint64_t 1124 nxge_class_get_known_cfg(p_nxge_t nxgep, int class_prop, int rx_quick_cfg) 1125 { 1126 int start_prop; 1127 uint64_t cfg_value; 1128 p_nxge_param_t param_arr; 1129 1130 param_arr = nxgep->param_arr; 1131 cfg_value = param_arr[class_prop].value; 1132 start_prop = param_h1_init_value; 1133 1134 /* update the properties per quick config */ 1135 switch (rx_quick_cfg) { 1136 case CFG_L3_WEB: 1137 case CFG_L3_DISTRIBUTE: 1138 cfg_value = nxge_classify_get_cfg_value(nxgep, 1139 rx_quick_cfg, class_prop - start_prop); 1140 break; 1141 default: 1142 cfg_value = param_arr[class_prop].value; 1143 break; 1144 } 1145 return (cfg_value); 1146 } 1147 1148 static nxge_status_t 1149 nxge_cfg_verify_set_classify(p_nxge_t nxgep, dev_info_t *c_dip[]) 1150 { 1151 nxge_status_t status = NXGE_OK; 1152 int rx_quick_cfg, class_prop, start_prop, end_prop; 1153 char *prop_name; 1154 int override = B_TRUE; 1155 uint64_t cfg_value; 1156 p_nxge_param_t param_arr; 1157 1158 param_arr = nxgep->param_arr; 1159 rx_quick_cfg = param_arr[param_rx_quick_cfg].value; 1160 start_prop = param_h1_init_value; 1161 end_prop = param_class_opt_ipv6_sctp; 1162 1163 /* update the properties per quick config */ 1164 if (rx_quick_cfg == CFG_NOT_SPECIFIED) 1165 override = B_FALSE; 1166 1167 /* 1168 * these parameter affect the classification outcome. 1169 * these parameters are used to configure the Flow key and 1170 * the TCAM key for each of the IP classes. 1171 * Included here are also the H1 and H2 initial values 1172 * which affect the distribution as well as final hash value 1173 * (hence the offset into RDC table and FCRAM bucket location) 1174 * 1175 */ 1176 for (class_prop = start_prop; class_prop <= end_prop; class_prop++) { 1177 prop_name = param_arr[class_prop].fcode_name; 1178 cfg_value = nxge_class_get_known_cfg(nxgep, 1179 class_prop, rx_quick_cfg); 1180 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name, 1181 cfg_value, override, c_dip); 1182 } 1183 1184 /* 1185 * these properties do not affect the actual classification outcome. 1186 * used to enable/disable or tune the fflp hardware 1187 * 1188 * fcram_access_ratio, tcam_access_ratio, tcam_enable, llc_snap_enable 1189 * 1190 */ 1191 override = B_FALSE; 1192 for (class_prop = param_fcram_access_ratio; 1193 class_prop <= param_llc_snap_enable; class_prop++) { 1194 prop_name = param_arr[class_prop].fcode_name; 1195 cfg_value = param_arr[class_prop].value; 1196 status = nxge_cfg_verify_set_classify_prop(nxgep, prop_name, 1197 cfg_value, override, c_dip); 1198 } 1199 1200 return (status); 1201 } 1202 1203 nxge_status_t 1204 nxge_cfg_verify_set(p_nxge_t nxgep, uint32_t flag) 1205 { 1206 nxge_status_t status = NXGE_OK; 1207 int i = 0, found = 0; 1208 int num_siblings; 1209 dev_info_t *c_dip[MAX_SIBLINGS + 1]; 1210 char *prop_val[MAX_SIBLINGS]; 1211 config_token_t c_token[MAX_SIBLINGS]; 1212 char *prop; 1213 1214 if (nxge_dma_obp_props_only) 1215 return (NXGE_OK); 1216 1217 num_siblings = 0; 1218 c_dip[num_siblings] = ddi_get_child(nxgep->p_dip); 1219 while (c_dip[num_siblings]) { 1220 c_dip[num_siblings + 1] = 1221 ddi_get_next_sibling(c_dip[num_siblings]); 1222 num_siblings++; 1223 } 1224 1225 switch (flag) { 1226 case COMMON_TXDMA_CFG: 1227 prop = "txdma-cfg"; 1228 break; 1229 case COMMON_RXDMA_CFG: 1230 prop = "rxdma-cfg"; 1231 break; 1232 case COMMON_RXDMA_GRP_CFG: 1233 prop = "rxdma-grp-cfg"; 1234 break; 1235 case COMMON_CLASS_CFG: 1236 status = nxge_cfg_verify_set_classify(nxgep, c_dip); 1237 return (status); 1238 default: 1239 return (NXGE_ERROR); 1240 } 1241 1242 i = 0; 1243 while (i < num_siblings) { 1244 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, c_dip[i], 0, prop, 1245 (char **)&prop_val[i]) == DDI_PROP_SUCCESS) { 1246 c_token[i] = nxge_get_config_token(prop_val[i]); 1247 ddi_prop_free(prop_val[i]); 1248 found++; 1249 } else 1250 c_token[i] = CONFIG_TOKEN_NONE; 1251 i++; 1252 } 1253 1254 if (found != i) { 1255 if (found == 0) { 1256 /* not specified: Use default */ 1257 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1258 " property %s not specified on any port:" 1259 " Using default", prop)); 1260 1261 status = nxge_update_cfg_properties(nxgep, 1262 flag, FAIR, c_dip); 1263 return (status); 1264 } else { 1265 /* 1266 * if the convention is to use function 0 device then 1267 * populate the other devices with this configuration. 1268 * 1269 * The other alternative is to use the default config. 1270 */ 1271 /* not specified: Use default */ 1272 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1273 " property %s not specified on some ports:" 1274 " Using default", prop)); 1275 status = nxge_update_cfg_properties(nxgep, 1276 flag, FAIR, c_dip); 1277 return (status); 1278 } 1279 } 1280 1281 /* check type and consistence */ 1282 /* found on all devices */ 1283 for (i = 1; i < found; i++) { 1284 if (c_token[i] != c_token[i - 1]) { 1285 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1286 " property %s inconsistent:" 1287 " Using default", prop)); 1288 status = nxge_update_cfg_properties(nxgep, 1289 flag, FAIR, c_dip); 1290 return (status); 1291 } 1292 } 1293 1294 /* 1295 * Found on all the ports check if it is custom configuration. if 1296 * custom, then verify consistence 1297 * 1298 * finally create soft properties 1299 */ 1300 status = nxge_update_cfg_properties(nxgep, flag, c_token[0], c_dip); 1301 return (status); 1302 } 1303 1304 nxge_status_t 1305 nxge_cfg_verify_set_quick_config(p_nxge_t nxgep) 1306 { 1307 nxge_status_t status = NXGE_OK; 1308 int ddi_status = DDI_SUCCESS; 1309 char *prop_val; 1310 char *rx_prop; 1311 char *prop; 1312 uint32_t cfg_value = CFG_NOT_SPECIFIED; 1313 p_nxge_param_t param_arr; 1314 1315 param_arr = nxgep->param_arr; 1316 rx_prop = param_arr[param_rx_quick_cfg].fcode_name; 1317 1318 prop = "rx-quick-cfg"; 1319 1320 /* 1321 * good value are 1322 * 1323 * "web-server" "generic-server" "l3-classify" "flow-classify" 1324 */ 1325 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, nxgep->dip, 0, 1326 prop, (char **)&prop_val) != DDI_PROP_SUCCESS) { 1327 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1328 " property %s not specified: using default ", prop)); 1329 cfg_value = CFG_NOT_SPECIFIED; 1330 } else { 1331 cfg_value = CFG_L3_DISTRIBUTE; 1332 if (strncmp("web-server", (caddr_t)prop_val, 8) == 0) { 1333 cfg_value = CFG_L3_WEB; 1334 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1335 " %s: web server ", prop)); 1336 } 1337 if (strncmp("generic-server", (caddr_t)prop_val, 8) == 0) { 1338 cfg_value = CFG_L3_DISTRIBUTE; 1339 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 1340 " %s: distribute ", prop)); 1341 } 1342 /* more */ 1343 ddi_prop_free(prop_val); 1344 } 1345 1346 ddi_status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1347 rx_prop, cfg_value); 1348 if (ddi_status != DDI_PROP_SUCCESS) 1349 status |= NXGE_DDI_FAILED; 1350 1351 /* now handle specified cases: */ 1352 if (status & NXGE_DDI_FAILED) 1353 status |= NXGE_ERROR; 1354 return (status); 1355 } 1356 1357 static void 1358 nxge_use_cfg_link_cfg(p_nxge_t nxgep) 1359 { 1360 int *prop_val; 1361 uint_t prop_len; 1362 dev_info_t *dip; 1363 int speed; 1364 int duplex; 1365 int adv_autoneg_cap; 1366 int adv_10gfdx_cap; 1367 int adv_10ghdx_cap; 1368 int adv_1000fdx_cap; 1369 int adv_1000hdx_cap; 1370 int adv_100fdx_cap; 1371 int adv_100hdx_cap; 1372 int adv_10fdx_cap; 1373 int adv_10hdx_cap; 1374 int status = DDI_SUCCESS; 1375 1376 dip = nxgep->dip; 1377 1378 /* 1379 * first find out the card type and the supported link speeds and 1380 * features 1381 */ 1382 /* add code for card type */ 1383 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-autoneg-cap", 1384 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1385 ddi_prop_free(prop_val); 1386 return; 1387 } 1388 1389 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10gfdx-cap", 1390 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1391 ddi_prop_free(prop_val); 1392 return; 1393 } 1394 1395 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000hdx-cap", 1396 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1397 ddi_prop_free(prop_val); 1398 return; 1399 } 1400 1401 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-1000fdx-cap", 1402 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1403 ddi_prop_free(prop_val); 1404 return; 1405 } 1406 1407 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100fdx-cap", 1408 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1409 ddi_prop_free(prop_val); 1410 return; 1411 } 1412 1413 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-100hdx-cap", 1414 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1415 ddi_prop_free(prop_val); 1416 return; 1417 } 1418 1419 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10fdx-cap", 1420 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1421 ddi_prop_free(prop_val); 1422 return; 1423 } 1424 1425 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, "adv-10hdx-cap", 1426 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1427 ddi_prop_free(prop_val); 1428 return; 1429 } 1430 1431 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "speed", 1432 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1433 if (strncmp("10000", (caddr_t)prop_val, 1434 (size_t)prop_len) == 0) { 1435 speed = 10000; 1436 } else if (strncmp("1000", (caddr_t)prop_val, 1437 (size_t)prop_len) == 0) { 1438 speed = 1000; 1439 } else if (strncmp("100", (caddr_t)prop_val, 1440 (size_t)prop_len) == 0) { 1441 speed = 100; 1442 } else if (strncmp("10", (caddr_t)prop_val, 1443 (size_t)prop_len) == 0) { 1444 speed = 10; 1445 } else if (strncmp("auto", (caddr_t)prop_val, 1446 (size_t)prop_len) == 0) { 1447 speed = 0; 1448 } else { 1449 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1450 "speed property is invalid reverting to auto")); 1451 speed = 0; 1452 } 1453 ddi_prop_free(prop_val); 1454 } else 1455 speed = 0; 1456 1457 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, dip, 0, "duplex", 1458 (uchar_t **)&prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1459 if (strncmp("full", (caddr_t)prop_val, 1460 (size_t)prop_len) == 0) { 1461 duplex = 2; 1462 } else if (strncmp("half", (caddr_t)prop_val, 1463 (size_t)prop_len) == 0) { 1464 duplex = 1; 1465 } else if (strncmp("auto", (caddr_t)prop_val, 1466 (size_t)prop_len) == 0) { 1467 duplex = 0; 1468 } else { 1469 NXGE_ERROR_MSG((nxgep, NXGE_NOTE, 1470 "duplex property is invalid" 1471 " reverting to auto")); 1472 duplex = 0; 1473 } 1474 ddi_prop_free(prop_val); 1475 } else 1476 duplex = 0; 1477 1478 adv_autoneg_cap = (speed == 0) || (duplex == 0); 1479 if (adv_autoneg_cap == 0) { 1480 adv_10gfdx_cap = ((speed == 10000) && (duplex == 2)); 1481 adv_10ghdx_cap = adv_10gfdx_cap; 1482 adv_10ghdx_cap |= ((speed == 10000) && (duplex == 1)); 1483 adv_1000fdx_cap = adv_10ghdx_cap; 1484 adv_1000fdx_cap |= ((speed == 1000) && (duplex == 2)); 1485 adv_1000hdx_cap = adv_1000fdx_cap; 1486 adv_1000hdx_cap |= ((speed == 1000) && (duplex == 1)); 1487 adv_100fdx_cap = adv_1000hdx_cap; 1488 adv_100fdx_cap |= ((speed == 100) && (duplex == 2)); 1489 adv_100hdx_cap = adv_100fdx_cap; 1490 adv_100hdx_cap |= ((speed == 100) && (duplex == 1)); 1491 adv_10fdx_cap = adv_100hdx_cap; 1492 adv_10fdx_cap |= ((speed == 10) && (duplex == 2)); 1493 adv_10hdx_cap = adv_10fdx_cap; 1494 adv_10hdx_cap |= ((speed == 10) && (duplex == 1)); 1495 } else if (speed == 0) { 1496 adv_10gfdx_cap = (duplex == 2); 1497 adv_10ghdx_cap = (duplex == 1); 1498 adv_1000fdx_cap = (duplex == 2); 1499 adv_1000hdx_cap = (duplex == 1); 1500 adv_100fdx_cap = (duplex == 2); 1501 adv_100hdx_cap = (duplex == 1); 1502 adv_10fdx_cap = (duplex == 2); 1503 adv_10hdx_cap = (duplex == 1); 1504 } 1505 if (duplex == 0) { 1506 adv_10gfdx_cap = (speed == 0); 1507 adv_10gfdx_cap |= (speed == 10000); 1508 adv_10ghdx_cap = adv_10gfdx_cap; 1509 adv_10ghdx_cap |= (speed == 10000); 1510 adv_1000fdx_cap = adv_10ghdx_cap; 1511 adv_1000fdx_cap |= (speed == 1000); 1512 adv_1000hdx_cap = adv_1000fdx_cap; 1513 adv_1000hdx_cap |= (speed == 1000); 1514 adv_100fdx_cap = adv_1000hdx_cap; 1515 adv_100fdx_cap |= (speed == 100); 1516 adv_100hdx_cap = adv_100fdx_cap; 1517 adv_100hdx_cap |= (speed == 100); 1518 adv_10fdx_cap = adv_100hdx_cap; 1519 adv_10fdx_cap |= (speed == 10); 1520 adv_10hdx_cap = adv_10fdx_cap; 1521 adv_10hdx_cap |= (speed == 10); 1522 } 1523 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1524 "adv-autoneg-cap", &adv_autoneg_cap, 1); 1525 if (status) 1526 return; 1527 1528 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1529 "adv-10gfdx-cap", &adv_10gfdx_cap, 1); 1530 if (status) 1531 goto nxge_map_myargs_to_gmii_fail1; 1532 1533 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1534 "adv-10ghdx-cap", &adv_10ghdx_cap, 1); 1535 if (status) 1536 goto nxge_map_myargs_to_gmii_fail2; 1537 1538 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1539 "adv-1000fdx-cap", &adv_1000fdx_cap, 1); 1540 if (status) 1541 goto nxge_map_myargs_to_gmii_fail3; 1542 1543 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1544 "adv-1000hdx-cap", &adv_1000hdx_cap, 1); 1545 if (status) 1546 goto nxge_map_myargs_to_gmii_fail4; 1547 1548 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1549 "adv-100fdx-cap", &adv_100fdx_cap, 1); 1550 if (status) 1551 goto nxge_map_myargs_to_gmii_fail5; 1552 1553 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1554 "adv-100hdx-cap", &adv_100hdx_cap, 1); 1555 if (status) 1556 goto nxge_map_myargs_to_gmii_fail6; 1557 1558 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1559 "adv-10fdx-cap", &adv_10fdx_cap, 1); 1560 if (status) 1561 goto nxge_map_myargs_to_gmii_fail7; 1562 1563 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1564 "adv-10hdx-cap", &adv_10hdx_cap, 1); 1565 if (status) 1566 goto nxge_map_myargs_to_gmii_fail8; 1567 1568 return; 1569 1570 nxge_map_myargs_to_gmii_fail9: 1571 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10hdx-cap"); 1572 1573 nxge_map_myargs_to_gmii_fail8: 1574 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10fdx-cap"); 1575 1576 nxge_map_myargs_to_gmii_fail7: 1577 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100hdx-cap"); 1578 1579 nxge_map_myargs_to_gmii_fail6: 1580 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-100fdx-cap"); 1581 1582 nxge_map_myargs_to_gmii_fail5: 1583 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000hdx-cap"); 1584 1585 nxge_map_myargs_to_gmii_fail4: 1586 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-1000fdx-cap"); 1587 1588 nxge_map_myargs_to_gmii_fail3: 1589 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10ghdx-cap"); 1590 1591 nxge_map_myargs_to_gmii_fail2: 1592 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-10gfdx-cap"); 1593 1594 nxge_map_myargs_to_gmii_fail1: 1595 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "adv-autoneg-cap"); 1596 } 1597 1598 nxge_status_t 1599 nxge_get_config_properties(p_nxge_t nxgep) 1600 { 1601 nxge_status_t status = NXGE_OK; 1602 p_nxge_hw_list_t hw_p; 1603 1604 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " ==> nxge_get_config_properties")); 1605 1606 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 1607 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1608 " nxge_get_config_properties:" 1609 " common hardware not set", nxgep->niu_type)); 1610 return (NXGE_ERROR); 1611 } 1612 1613 /* 1614 * Get info on how many ports Neptune card has. 1615 */ 1616 nxgep->nports = nxge_nports_from_niu_type(nxgep->niu_type); 1617 if (nxgep->nports <= 0) { 1618 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1619 "<==nxge_get_config_properties: Invalid Neptune type 0x%x", 1620 nxgep->niu_type)); 1621 return (NXGE_ERROR); 1622 } 1623 nxgep->classifier.tcam_size = TCAM_NIU_TCAM_MAX_ENTRY; 1624 if (nxgep->function_num >= nxgep->nports) { 1625 return (NXGE_ERROR); 1626 } 1627 1628 status = nxge_get_mac_addr_properties(nxgep); 1629 if (status != NXGE_OK) 1630 return (NXGE_ERROR); 1631 1632 /* 1633 * read the configuration type. If none is specified, used default. 1634 * Config types: equal: (default) DMA channels, RDC groups, TCAM, FCRAM 1635 * are shared equally across all the ports. 1636 * 1637 * Fair: DMA channels, RDC groups, TCAM, FCRAM are shared proportional 1638 * to the port speed. 1639 * 1640 * 1641 * custom: DMA channels, RDC groups, TCAM, FCRAM partition is 1642 * specified in nxge.conf. Need to read each parameter and set 1643 * up the parameters in nxge structures. 1644 * 1645 */ 1646 switch (nxgep->niu_type) { 1647 case N2_NIU: 1648 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1649 " ==> nxge_get_config_properties: N2")); 1650 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1651 if ((hw_p->flags & COMMON_CFG_VALID) != 1652 COMMON_CFG_VALID) { 1653 status = nxge_cfg_verify_set(nxgep, 1654 COMMON_RXDMA_GRP_CFG); 1655 status = nxge_cfg_verify_set(nxgep, 1656 COMMON_CLASS_CFG); 1657 hw_p->flags |= COMMON_CFG_VALID; 1658 } 1659 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1660 status = nxge_use_cfg_n2niu_properties(nxgep); 1661 break; 1662 default: 1663 if (!NXGE_IS_VALID_NEPTUNE_TYPE(nxgep->niu_type)) { 1664 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1665 " nxge_get_config_properties:" 1666 " unknown NIU type 0x%x", nxgep->niu_type)); 1667 return (NXGE_ERROR); 1668 } 1669 1670 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1671 " ==> nxge_get_config_properties: Neptune")); 1672 status = nxge_cfg_verify_set_quick_config(nxgep); 1673 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 1674 if ((hw_p->flags & COMMON_CFG_VALID) != 1675 COMMON_CFG_VALID) { 1676 status = nxge_cfg_verify_set(nxgep, 1677 COMMON_TXDMA_CFG); 1678 status = nxge_cfg_verify_set(nxgep, 1679 COMMON_RXDMA_CFG); 1680 status = nxge_cfg_verify_set(nxgep, 1681 COMMON_RXDMA_GRP_CFG); 1682 status = nxge_cfg_verify_set(nxgep, 1683 COMMON_CLASS_CFG); 1684 hw_p->flags |= COMMON_CFG_VALID; 1685 } 1686 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 1687 nxge_use_cfg_neptune_properties(nxgep); 1688 status = NXGE_OK; 1689 break; 1690 } 1691 1692 NXGE_DEBUG_MSG((nxgep, VPD_CTL, " <== nxge_get_config_properties")); 1693 return (status); 1694 } 1695 1696 static nxge_status_t 1697 nxge_use_cfg_n2niu_properties(p_nxge_t nxgep) 1698 { 1699 nxge_status_t status = NXGE_OK; 1700 1701 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_n2niu_properties")); 1702 1703 status = nxge_use_default_dma_config_n2(nxgep); 1704 if (status != NXGE_OK) { 1705 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1706 " ==> nxge_use_cfg_n2niu_properties (err 0x%x)", 1707 status)); 1708 return (status | NXGE_ERROR); 1709 } 1710 1711 (void) nxge_use_cfg_vlan_class_config(nxgep); 1712 (void) nxge_use_cfg_mac_class_config(nxgep); 1713 (void) nxge_use_cfg_class_config(nxgep); 1714 (void) nxge_use_cfg_link_cfg(nxgep); 1715 1716 /* 1717 * Read in the hardware (fcode) properties. Use the ndd array to read 1718 * each property. 1719 */ 1720 (void) nxge_get_param_soft_properties(nxgep); 1721 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_n2niu_properties")); 1722 1723 return (status); 1724 } 1725 1726 static void 1727 nxge_use_cfg_neptune_properties(p_nxge_t nxgep) 1728 { 1729 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_neptune_properties")); 1730 1731 (void) nxge_use_cfg_dma_config(nxgep); 1732 (void) nxge_use_cfg_vlan_class_config(nxgep); 1733 (void) nxge_use_cfg_mac_class_config(nxgep); 1734 (void) nxge_use_cfg_class_config(nxgep); 1735 (void) nxge_use_cfg_link_cfg(nxgep); 1736 1737 /* 1738 * Read in the hardware (fcode) properties. Use the ndd array to read 1739 * each property. 1740 */ 1741 (void) nxge_get_param_soft_properties(nxgep); 1742 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_neptune_properties")); 1743 } 1744 1745 /* 1746 * FWARC 2006/556 1747 */ 1748 1749 static nxge_status_t 1750 nxge_use_default_dma_config_n2(p_nxge_t nxgep) 1751 { 1752 int ndmas; 1753 int nrxgp; 1754 uint8_t func; 1755 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1756 p_nxge_hw_pt_cfg_t p_cfgp; 1757 int *prop_val; 1758 uint_t prop_len; 1759 int i; 1760 nxge_status_t status = NXGE_OK; 1761 1762 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2")); 1763 1764 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1765 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1766 1767 func = nxgep->function_num; 1768 p_cfgp->function_number = func; 1769 ndmas = NXGE_TDMA_PER_NIU_PORT; 1770 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1771 "tx-dma-channels", (int **)&prop_val, 1772 &prop_len) == DDI_PROP_SUCCESS) { 1773 p_cfgp->start_tdc = prop_val[0]; 1774 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1775 "==> nxge_use_default_dma_config_n2: tdc starts %d " 1776 "(#%d)", p_cfgp->start_tdc, prop_len)); 1777 1778 ndmas = prop_val[1]; 1779 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1780 "==> nxge_use_default_dma_config_n2: #tdc %d (#%d)", 1781 ndmas, prop_len)); 1782 ddi_prop_free(prop_val); 1783 } else { 1784 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1785 "==> nxge_use_default_dma_config_n2: " 1786 "get tx-dma-channels failed")); 1787 return (NXGE_DDI_FAILED); 1788 } 1789 1790 p_cfgp->max_tdcs = nxgep->max_tdcs = ndmas; 1791 nxgep->tdc_mask = (ndmas - 1); 1792 1793 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1794 "p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d start %d", 1795 p_cfgp, p_cfgp->max_tdcs, nxgep->max_tdcs, p_cfgp->start_tdc)); 1796 1797 /* Receive DMA */ 1798 ndmas = NXGE_RDMA_PER_NIU_PORT; 1799 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1800 "rx-dma-channels", (int **)&prop_val, 1801 &prop_len) == DDI_PROP_SUCCESS) { 1802 p_cfgp->start_rdc = prop_val[0]; 1803 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1804 "==> nxge_use_default_dma_config_n2(obp): rdc start %d" 1805 " (#%d)", p_cfgp->start_rdc, prop_len)); 1806 ndmas = prop_val[1]; 1807 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1808 "==> nxge_use_default_dma_config_n2(obp):#rdc %d (#%d)", 1809 ndmas, prop_len)); 1810 ddi_prop_free(prop_val); 1811 } else { 1812 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1813 "==> nxge_use_default_dma_config_n2: " 1814 "get rx-dma-channel failed")); 1815 return (NXGE_DDI_FAILED); 1816 } 1817 1818 p_cfgp->max_rdcs = nxgep->max_rdcs = ndmas; 1819 nxgep->rdc_mask = (ndmas - 1); 1820 1821 /* Hypervisor: rdc # and group # use the same # !! */ 1822 p_cfgp->max_grpids = p_cfgp->max_rdcs + p_cfgp->max_tdcs; 1823 p_cfgp->start_grpid = 0; 1824 p_cfgp->mif_ldvid = p_cfgp->mac_ldvid = p_cfgp->ser_ldvid = 0; 1825 1826 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 1827 "interrupts", (int **)&prop_val, 1828 &prop_len) == DDI_PROP_SUCCESS) { 1829 /* 1830 * For each device assigned, the content of each interrupts 1831 * property is its logical device group. 1832 * 1833 * Assignment of interrupts property is in the the following 1834 * order: 1835 * 1836 * MAC MIF (if configured) SYSTEM ERROR (if configured) first 1837 * receive channel next channel...... last receive channel 1838 * first transmit channel next channel...... last transmit 1839 * channel 1840 * 1841 * prop_len should be at least for one mac and total # of rx and 1842 * tx channels. Function 0 owns MIF and ERROR 1843 */ 1844 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1845 "==> nxge_use_default_dma_config_n2(obp): " 1846 "# interrupts %d", prop_len)); 1847 1848 switch (func) { 1849 case 0: 1850 p_cfgp->ldg_chn_start = 3; 1851 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT0; 1852 p_cfgp->mif_ldvid = NXGE_MIF_LD; 1853 p_cfgp->ser_ldvid = NXGE_SYS_ERROR_LD; 1854 1855 break; 1856 case 1: 1857 p_cfgp->ldg_chn_start = 1; 1858 p_cfgp->mac_ldvid = NXGE_MAC_LD_PORT1; 1859 1860 break; 1861 default: 1862 status = NXGE_DDI_FAILED; 1863 break; 1864 } 1865 1866 if (status != NXGE_OK) 1867 return (status); 1868 1869 for (i = 0; i < prop_len; i++) { 1870 p_cfgp->ldg[i] = prop_val[i]; 1871 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1872 "==> nxge_use_default_dma_config_n2(obp): " 1873 "interrupt #%d, ldg %d", 1874 i, p_cfgp->ldg[i])); 1875 } 1876 1877 p_cfgp->max_grpids = prop_len; 1878 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1879 "==> nxge_use_default_dma_config_n2(obp): %d " 1880 "(#%d) maxgrpids %d channel starts %d", 1881 p_cfgp->mac_ldvid, i, p_cfgp->max_grpids, 1882 p_cfgp->ldg_chn_start)); 1883 ddi_prop_free(prop_val); 1884 } else { 1885 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1886 "==> nxge_use_default_dma_config_n2: " 1887 "get interrupts failed")); 1888 return (NXGE_DDI_FAILED); 1889 } 1890 1891 p_cfgp->max_ldgs = p_cfgp->max_grpids; 1892 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1893 "==> nxge_use_default_dma_config_n2: " 1894 "p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d" 1895 "start_grpid %d macid %d mifid %d serrid %d", 1896 p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids, 1897 p_cfgp->start_grpid, 1898 p_cfgp->mac_ldvid, p_cfgp->mif_ldvid, p_cfgp->ser_ldvid)); 1899 1900 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1901 "p_cfgp p%p start_ldg %d nxgep->max_ldgs %d", 1902 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs)); 1903 1904 /* 1905 * RDC groups and the beginning RDC group assigned to this function. 1906 */ 1907 nrxgp = 2; 1908 p_cfgp->max_rdc_grpids = nrxgp; 1909 p_cfgp->start_rdc_grpid = (nxgep->function_num * nrxgp); 1910 1911 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1912 "rx-rdc-grps", nrxgp); 1913 if (status) { 1914 return (NXGE_DDI_FAILED); 1915 } 1916 status = ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1917 "rx-rdc-grps-begin", p_cfgp->start_rdc_grpid); 1918 if (status) { 1919 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 1920 "rx-rdc-grps"); 1921 return (NXGE_DDI_FAILED); 1922 } 1923 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "==> nxge_use_default_dma_config_n2: " 1924 "p_cfgp $%p # rdc groups %d start rdc group id %d", 1925 p_cfgp, p_cfgp->max_rdc_grpids, 1926 p_cfgp->start_rdc_grpid)); 1927 1928 nxge_set_hw_dma_config(nxgep); 1929 NXGE_DEBUG_MSG((nxgep, OBP_CTL, "<== nxge_use_default_dma_config_n2")); 1930 return (status); 1931 } 1932 1933 static void 1934 nxge_use_cfg_dma_config(p_nxge_t nxgep) 1935 { 1936 int tx_ndmas, rx_ndmas, nrxgp, st_txdma, st_rxdma; 1937 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1938 p_nxge_hw_pt_cfg_t p_cfgp; 1939 dev_info_t *dip; 1940 p_nxge_param_t param_arr; 1941 char *prop; 1942 int *prop_val; 1943 uint_t prop_len; 1944 int i; 1945 uint8_t *ch_arr_p; 1946 1947 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_dma_config")); 1948 param_arr = nxgep->param_arr; 1949 1950 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1951 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1952 dip = nxgep->dip; 1953 p_cfgp->function_number = nxgep->function_num; 1954 prop = param_arr[param_txdma_channels_begin].fcode_name; 1955 1956 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 1957 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1958 p_cfgp->start_tdc = *prop_val; 1959 ddi_prop_free(prop_val); 1960 } else { 1961 switch (nxgep->niu_type) { 1962 case NEPTUNE_4_1GC: 1963 ch_arr_p = &tx_4_1G[0]; 1964 break; 1965 case NEPTUNE_2_10GF: 1966 ch_arr_p = &tx_2_10G[0]; 1967 break; 1968 case NEPTUNE_2_10GF_2_1GC: 1969 ch_arr_p = &tx_2_10G_2_1G[0]; 1970 break; 1971 case NEPTUNE_1_10GF_3_1GC: 1972 ch_arr_p = &tx_1_10G_3_1G[0]; 1973 break; 1974 case NEPTUNE_1_1GC_1_10GF_2_1GC: 1975 ch_arr_p = &tx_1_1G_1_10G_2_1G[0]; 1976 break; 1977 default: 1978 ch_arr_p = &p4_tx_equal[0]; 1979 break; 1980 } 1981 st_txdma = 0; 1982 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++) 1983 st_txdma += *ch_arr_p; 1984 1985 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 1986 prop, st_txdma); 1987 p_cfgp->start_tdc = st_txdma; 1988 } 1989 1990 prop = param_arr[param_txdma_channels].fcode_name; 1991 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 1992 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 1993 tx_ndmas = *prop_val; 1994 ddi_prop_free(prop_val); 1995 } else { 1996 switch (nxgep->niu_type) { 1997 case NEPTUNE_4_1GC: 1998 tx_ndmas = tx_4_1G[nxgep->function_num]; 1999 break; 2000 case NEPTUNE_2_10GF: 2001 tx_ndmas = tx_2_10G[nxgep->function_num]; 2002 break; 2003 case NEPTUNE_2_10GF_2_1GC: 2004 tx_ndmas = tx_2_10G_2_1G[nxgep->function_num]; 2005 break; 2006 case NEPTUNE_1_10GF_3_1GC: 2007 tx_ndmas = tx_1_10G_3_1G[nxgep->function_num]; 2008 break; 2009 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2010 tx_ndmas = tx_1_1G_1_10G_2_1G[nxgep->function_num]; 2011 break; 2012 default: 2013 tx_ndmas = p4_tx_equal[nxgep->function_num]; 2014 break; 2015 } 2016 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2017 prop, tx_ndmas); 2018 } 2019 2020 p_cfgp->max_tdcs = nxgep->max_tdcs = tx_ndmas; 2021 nxgep->tdc_mask = (tx_ndmas - 1); 2022 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2023 "p_cfgp 0x%llx max_tdcs %d nxgep->max_tdcs %d", 2024 p_cfgp, p_cfgp->max_tdcs, nxgep->max_tdcs)); 2025 2026 prop = param_arr[param_rxdma_channels_begin].fcode_name; 2027 2028 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2029 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2030 p_cfgp->start_rdc = *prop_val; 2031 ddi_prop_free(prop_val); 2032 } else { 2033 switch (nxgep->niu_type) { 2034 case NEPTUNE_4_1GC: 2035 ch_arr_p = &rx_4_1G[0]; 2036 break; 2037 case NEPTUNE_2_10GF: 2038 ch_arr_p = &rx_2_10G[0]; 2039 break; 2040 case NEPTUNE_2_10GF_2_1GC: 2041 ch_arr_p = &rx_2_10G_2_1G[0]; 2042 break; 2043 case NEPTUNE_1_10GF_3_1GC: 2044 ch_arr_p = &rx_1_10G_3_1G[0]; 2045 break; 2046 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2047 ch_arr_p = &rx_1_1G_1_10G_2_1G[0]; 2048 break; 2049 default: 2050 ch_arr_p = &p4_rx_equal[0]; 2051 break; 2052 } 2053 st_rxdma = 0; 2054 for (i = 0; i < nxgep->function_num; i++, ch_arr_p++) 2055 st_rxdma += *ch_arr_p; 2056 2057 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2058 prop, st_rxdma); 2059 p_cfgp->start_rdc = st_rxdma; 2060 } 2061 2062 prop = param_arr[param_rxdma_channels].fcode_name; 2063 2064 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2065 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2066 rx_ndmas = *prop_val; 2067 ddi_prop_free(prop_val); 2068 } else { 2069 switch (nxgep->niu_type) { 2070 case NEPTUNE_4_1GC: 2071 rx_ndmas = rx_4_1G[nxgep->function_num]; 2072 break; 2073 case NEPTUNE_2_10GF: 2074 rx_ndmas = rx_2_10G[nxgep->function_num]; 2075 break; 2076 case NEPTUNE_2_10GF_2_1GC: 2077 rx_ndmas = rx_2_10G_2_1G[nxgep->function_num]; 2078 break; 2079 case NEPTUNE_1_10GF_3_1GC: 2080 rx_ndmas = rx_1_10G_3_1G[nxgep->function_num]; 2081 break; 2082 case NEPTUNE_1_1GC_1_10GF_2_1GC: 2083 rx_ndmas = rx_1_1G_1_10G_2_1G[nxgep->function_num]; 2084 break; 2085 default: 2086 rx_ndmas = p4_rx_equal[nxgep->function_num]; 2087 break; 2088 } 2089 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2090 prop, rx_ndmas); 2091 } 2092 2093 p_cfgp->max_rdcs = nxgep->max_rdcs = rx_ndmas; 2094 2095 prop = param_arr[param_rdc_grps_start].fcode_name; 2096 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2097 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2098 p_cfgp->start_rdc_grpid = *prop_val; 2099 ddi_prop_free(prop_val); 2100 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2101 "==> nxge_use_default_dma_config: " 2102 "use property " "start_grpid %d ", 2103 p_cfgp->start_grpid)); 2104 } else { 2105 p_cfgp->start_rdc_grpid = nxgep->function_num; 2106 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2107 prop, p_cfgp->start_rdc_grpid); 2108 2109 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2110 "==> nxge_use_default_dma_config: " 2111 "use default " 2112 "start_grpid %d (same as function #)", 2113 p_cfgp->start_grpid)); 2114 } 2115 2116 prop = param_arr[param_rx_rdc_grps].fcode_name; 2117 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2118 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2119 nrxgp = *prop_val; 2120 ddi_prop_free(prop_val); 2121 } else { 2122 nrxgp = 1; 2123 (void) ddi_prop_update_int(DDI_DEV_T_NONE, nxgep->dip, 2124 prop, nrxgp); 2125 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2126 "==> nxge_use_default_dma_config: " 2127 "num_rdc_grpid not found: use def:# of " 2128 "rdc groups %d\n", nrxgp)); 2129 } 2130 2131 p_cfgp->max_rdc_grpids = nrxgp; 2132 2133 /* 2134 * 2/4 ports have the same hard-wired logical groups assigned. 2135 */ 2136 p_cfgp->start_ldg = nxgep->function_num * NXGE_LDGRP_PER_4PORTS; 2137 p_cfgp->max_ldgs = NXGE_LDGRP_PER_4PORTS; 2138 2139 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_default_dma_config: " 2140 "p_cfgp 0x%llx max_rdcs %d nxgep->max_rdcs %d max_grpids %d" 2141 "start_grpid %d", 2142 p_cfgp, p_cfgp->max_rdcs, nxgep->max_rdcs, p_cfgp->max_grpids, 2143 p_cfgp->start_grpid)); 2144 2145 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_dma_config: " 2146 "p_cfgp 0x%016llx start_ldg %d nxgep->max_ldgs %d " 2147 "start_rdc_grpid %d", 2148 p_cfgp, p_cfgp->start_ldg, p_cfgp->max_ldgs, 2149 p_cfgp->start_rdc_grpid)); 2150 2151 prop = param_arr[param_rxdma_intr_time].fcode_name; 2152 2153 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2154 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2155 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2156 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2157 nxgep->dip, prop, prop_val, prop_len); 2158 } 2159 ddi_prop_free(prop_val); 2160 } 2161 prop = param_arr[param_rxdma_intr_pkts].fcode_name; 2162 2163 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, prop, 2164 &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 2165 if ((prop_len > 0) && (prop_len <= p_cfgp->max_rdcs)) { 2166 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2167 nxgep->dip, prop, prop_val, prop_len); 2168 } 2169 ddi_prop_free(prop_val); 2170 } 2171 nxge_set_hw_dma_config(nxgep); 2172 2173 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config: " 2174 "sTDC[%d] nTDC[%d] sRDC[%d] nRDC[%d]", 2175 p_cfgp->start_tdc, p_cfgp->max_tdcs, 2176 p_cfgp->start_rdc, p_cfgp->max_rdcs)); 2177 2178 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_use_cfg_dma_config")); 2179 } 2180 2181 static void 2182 nxge_use_cfg_vlan_class_config(p_nxge_t nxgep) 2183 { 2184 uint_t vlan_cnt; 2185 int *vlan_cfg_val; 2186 int status; 2187 p_nxge_param_t param_arr; 2188 char *prop; 2189 2190 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_use_cfg_vlan_config")); 2191 param_arr = nxgep->param_arr; 2192 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2193 2194 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2195 &vlan_cfg_val, &vlan_cnt); 2196 if (status == DDI_PROP_SUCCESS) { 2197 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2198 nxgep->dip, prop, vlan_cfg_val, vlan_cnt); 2199 ddi_prop_free(vlan_cfg_val); 2200 } 2201 nxge_set_hw_vlan_class_config(nxgep); 2202 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_vlan_config")); 2203 } 2204 2205 static void 2206 nxge_use_cfg_mac_class_config(p_nxge_t nxgep) 2207 { 2208 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2209 p_nxge_hw_pt_cfg_t p_cfgp; 2210 uint_t mac_cnt; 2211 int *mac_cfg_val; 2212 int status; 2213 p_nxge_param_t param_arr; 2214 char *prop; 2215 2216 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_use_cfg_mac_class_config")); 2217 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2218 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2219 p_cfgp->start_mac_entry = 0; 2220 param_arr = nxgep->param_arr; 2221 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2222 2223 switch (nxgep->function_num) { 2224 case 0: 2225 case 1: 2226 /* 10G ports */ 2227 p_cfgp->max_macs = NXGE_MAX_MACS_XMACS; 2228 break; 2229 case 2: 2230 case 3: 2231 /* 1G ports */ 2232 default: 2233 p_cfgp->max_macs = NXGE_MAX_MACS_BMACS; 2234 break; 2235 } 2236 2237 p_cfgp->mac_pref = 1; 2238 p_cfgp->def_mac_rxdma_grpid = p_cfgp->start_rdc_grpid; 2239 2240 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 2241 "== nxge_use_cfg_mac_class_config: " 2242 " mac_pref bit set def_mac_rxdma_grpid %d", 2243 p_cfgp->def_mac_rxdma_grpid)); 2244 2245 status = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2246 &mac_cfg_val, &mac_cnt); 2247 if (status == DDI_PROP_SUCCESS) { 2248 if (mac_cnt <= p_cfgp->max_macs) 2249 status = ddi_prop_update_int_array(DDI_DEV_T_NONE, 2250 nxgep->dip, prop, mac_cfg_val, mac_cnt); 2251 ddi_prop_free(mac_cfg_val); 2252 } 2253 nxge_set_hw_mac_class_config(nxgep); 2254 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_use_cfg_mac_class_config")); 2255 } 2256 2257 static void 2258 nxge_use_cfg_class_config(p_nxge_t nxgep) 2259 { 2260 nxge_set_hw_class_config(nxgep); 2261 } 2262 2263 static void 2264 nxge_set_rdc_intr_property(p_nxge_t nxgep) 2265 { 2266 int i; 2267 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2268 2269 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_rdc_intr_property")); 2270 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2271 2272 for (i = 0; i < NXGE_MAX_RDCS; i++) { 2273 p_dma_cfgp->rcr_timeout[i] = nxge_rcr_timeout; 2274 p_dma_cfgp->rcr_threshold[i] = nxge_rcr_threshold; 2275 } 2276 2277 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_rdc_intr_property")); 2278 } 2279 2280 static void 2281 nxge_set_hw_dma_config(p_nxge_t nxgep) 2282 { 2283 int i, j, rdc, ndmas, ngrps, bitmap, end, st_rdc; 2284 int32_t status; 2285 uint8_t rdcs_per_grp; 2286 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2287 p_nxge_hw_pt_cfg_t p_cfgp; 2288 p_nxge_rdc_grp_t rdc_grp_p; 2289 int rdcgrp_cfg = CFG_NOT_SPECIFIED, rx_quick_cfg; 2290 char *prop, *prop_val; 2291 p_nxge_param_t param_arr; 2292 config_token_t token; 2293 2294 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_dma_config")); 2295 2296 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2297 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2298 rdc_grp_p = p_dma_cfgp->rdc_grps; 2299 2300 /* Transmit DMA Channels */ 2301 bitmap = 0; 2302 end = p_cfgp->start_tdc + p_cfgp->max_tdcs; 2303 nxgep->ntdc = p_cfgp->max_tdcs; 2304 p_dma_cfgp->tx_dma_map = 0; 2305 for (i = p_cfgp->start_tdc; i < end; i++) { 2306 bitmap |= (1 << i); 2307 nxgep->tdc[i - p_cfgp->start_tdc] = (uint8_t)i; 2308 } 2309 2310 p_dma_cfgp->tx_dma_map = bitmap; 2311 param_arr = nxgep->param_arr; 2312 2313 /* Assume RDCs are evenly distributed */ 2314 rx_quick_cfg = param_arr[param_rx_quick_cfg].value; 2315 switch (rx_quick_cfg) { 2316 case CFG_NOT_SPECIFIED: 2317 prop = "rxdma-grp-cfg"; 2318 status = ddi_prop_lookup_string(DDI_DEV_T_NONE, 2319 nxgep->dip, 0, prop, (char **)&prop_val); 2320 if (status != DDI_PROP_SUCCESS) { 2321 NXGE_DEBUG_MSG((nxgep, CFG_CTL, 2322 " property %s not found", prop)); 2323 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2324 } else { 2325 token = nxge_get_config_token(prop_val); 2326 switch (token) { 2327 case L2_CLASSIFY: 2328 break; 2329 case CLASSIFY: 2330 case L3_CLASSIFY: 2331 case L3_DISTRIBUTE: 2332 case L3_TCAM: 2333 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2334 break; 2335 default: 2336 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2337 break; 2338 } 2339 ddi_prop_free(prop_val); 2340 } 2341 break; 2342 case CFG_L3_WEB: 2343 case CFG_L3_DISTRIBUTE: 2344 case CFG_L2_CLASSIFY: 2345 case CFG_L3_TCAM: 2346 rdcgrp_cfg = rx_quick_cfg; 2347 break; 2348 default: 2349 rdcgrp_cfg = CFG_L3_DISTRIBUTE; 2350 break; 2351 } 2352 2353 /* Receive DMA Channels */ 2354 st_rdc = p_cfgp->start_rdc; 2355 nxgep->nrdc = p_cfgp->max_rdcs; 2356 2357 for (i = 0; i < p_cfgp->max_rdcs; i++) { 2358 nxgep->rdc[i] = i + p_cfgp->start_rdc; 2359 } 2360 2361 switch (rdcgrp_cfg) { 2362 case CFG_L3_DISTRIBUTE: 2363 case CFG_L3_WEB: 2364 case CFG_L3_TCAM: 2365 ndmas = p_cfgp->max_rdcs; 2366 ngrps = 1; 2367 rdcs_per_grp = ndmas / ngrps; 2368 break; 2369 case CFG_L2_CLASSIFY: 2370 ndmas = p_cfgp->max_rdcs / 2; 2371 if (p_cfgp->max_rdcs < 2) 2372 ndmas = 1; 2373 ngrps = 1; 2374 rdcs_per_grp = ndmas / ngrps; 2375 break; 2376 default: 2377 ngrps = p_cfgp->max_rdc_grpids; 2378 ndmas = p_cfgp->max_rdcs; 2379 rdcs_per_grp = ndmas / ngrps; 2380 break; 2381 } 2382 2383 for (i = 0; i < ngrps; i++) { 2384 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 2385 rdc_grp_p->start_rdc = st_rdc + i * rdcs_per_grp; 2386 rdc_grp_p->max_rdcs = rdcs_per_grp; 2387 2388 /* default to: 0, 1, 2, 3, ...., 0, 1, 2, 3.... */ 2389 rdc_grp_p->config_method = RDC_TABLE_ENTRY_METHOD_SEQ; 2390 rdc = rdc_grp_p->start_rdc; 2391 for (j = 0; j < NXGE_MAX_RDCS; j++) { 2392 rdc_grp_p->rdc[j] = rdc++; 2393 if (rdc == (rdc_grp_p->start_rdc + rdcs_per_grp)) { 2394 rdc = rdc_grp_p->start_rdc; 2395 } 2396 } 2397 rdc_grp_p->def_rdc = rdc_grp_p->rdc[0]; 2398 rdc_grp_p->flag = 1; /* configured */ 2399 } 2400 2401 /* default RDC */ 2402 p_cfgp->def_rdc = p_cfgp->start_rdc; 2403 nxgep->def_rdc = p_cfgp->start_rdc; 2404 2405 /* full 18 byte header ? */ 2406 p_dma_cfgp->rcr_full_header = NXGE_RCR_FULL_HEADER; 2407 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_10G; 2408 if (nxgep->function_num > 1) 2409 p_dma_cfgp->rx_drr_weight = PT_DRR_WT_DEFAULT_1G; 2410 p_dma_cfgp->rbr_size = nxge_rbr_size; 2411 p_dma_cfgp->rcr_size = nxge_rcr_size; 2412 2413 nxge_set_rdc_intr_property(nxgep); 2414 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_dma_config")); 2415 } 2416 2417 boolean_t 2418 nxge_check_rxdma_port_member(p_nxge_t nxgep, uint8_t rdc) 2419 { 2420 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2421 p_nxge_hw_pt_cfg_t p_cfgp; 2422 int status = B_TRUE; 2423 2424 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member")); 2425 2426 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2427 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2428 2429 /* Receive DMA Channels */ 2430 if (rdc < p_cfgp->max_rdcs) 2431 status = B_TRUE; 2432 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member")); 2433 return (status); 2434 } 2435 2436 boolean_t 2437 nxge_check_txdma_port_member(p_nxge_t nxgep, uint8_t tdc) 2438 { 2439 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2440 p_nxge_hw_pt_cfg_t p_cfgp; 2441 int status = B_FALSE; 2442 2443 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rxdma_port_member")); 2444 2445 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2446 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2447 2448 /* Receive DMA Channels */ 2449 if (tdc < p_cfgp->max_tdcs) 2450 status = B_TRUE; 2451 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rxdma_port_member")); 2452 return (status); 2453 } 2454 2455 boolean_t 2456 nxge_check_rxdma_rdcgrp_member(p_nxge_t nxgep, uint8_t rdc_grp, uint8_t rdc) 2457 { 2458 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2459 int status = B_TRUE; 2460 p_nxge_rdc_grp_t rdc_grp_p; 2461 2462 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2463 " ==> nxge_check_rxdma_rdcgrp_member")); 2464 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " nxge_check_rxdma_rdcgrp_member" 2465 " rdc %d group %d", rdc, rdc_grp)); 2466 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2467 2468 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 2469 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " max %d ", rdc_grp_p->max_rdcs)); 2470 if (rdc >= rdc_grp_p->max_rdcs) { 2471 status = B_FALSE; 2472 } 2473 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2474 " <== nxge_check_rxdma_rdcgrp_member")); 2475 return (status); 2476 } 2477 2478 boolean_t 2479 nxge_check_rdcgrp_port_member(p_nxge_t nxgep, uint8_t rdc_grp) 2480 { 2481 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2482 p_nxge_hw_pt_cfg_t p_cfgp; 2483 int status = B_TRUE; 2484 2485 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, "==> nxge_check_rdcgrp_port_member")); 2486 2487 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2488 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2489 2490 if (rdc_grp >= p_cfgp->max_rdc_grpids) 2491 status = B_FALSE; 2492 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, " <== nxge_check_rdcgrp_port_member")); 2493 return (status); 2494 } 2495 2496 static void 2497 nxge_set_hw_vlan_class_config(p_nxge_t nxgep) 2498 { 2499 int i; 2500 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2501 p_nxge_hw_pt_cfg_t p_cfgp; 2502 p_nxge_param_t param_arr; 2503 uint_t vlan_cnt; 2504 int *vlan_cfg_val; 2505 nxge_param_map_t *vmap; 2506 char *prop; 2507 p_nxge_class_pt_cfg_t p_class_cfgp; 2508 uint32_t good_cfg[32]; 2509 int good_count = 0; 2510 nxge_mv_cfg_t *vlan_tbl; 2511 2512 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_vlan_config")); 2513 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2514 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2515 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2516 2517 param_arr = nxgep->param_arr; 2518 prop = param_arr[param_vlan_2rdc_grp].fcode_name; 2519 2520 /* 2521 * By default, VLAN to RDC group mapping is disabled Need to read HW or 2522 * .conf properties to find out if mapping is required 2523 * 2524 * Format 2525 * 2526 * uint32_t array, each array entry specifying the VLAN id and the 2527 * mapping 2528 * 2529 * bit[30] = add bit[29] = remove bit[28] = preference bits[23-16] = 2530 * rdcgrp bits[15-0] = VLAN ID ( ) 2531 */ 2532 2533 for (i = 0; i < NXGE_MAX_VLANS; i++) { 2534 p_class_cfgp->vlan_tbl[i].flag = 0; 2535 } 2536 2537 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 2538 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2539 &vlan_cfg_val, &vlan_cnt) == DDI_PROP_SUCCESS) { 2540 for (i = 0; i < vlan_cnt; i++) { 2541 vmap = (nxge_param_map_t *)&vlan_cfg_val[i]; 2542 if ((vmap->param_id) && 2543 (vmap->param_id < NXGE_MAX_VLANS) && 2544 (vmap->map_to < 2545 p_cfgp->max_rdc_grpids) && 2546 (vmap->map_to >= (uint8_t)0)) { 2547 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2548 " nxge_vlan_config mapping" 2549 " id %d grp %d", 2550 vmap->param_id, vmap->map_to)); 2551 good_cfg[good_count] = vlan_cfg_val[i]; 2552 if (vlan_tbl[vmap->param_id].flag == 0) 2553 good_count++; 2554 vlan_tbl[vmap->param_id].flag = 1; 2555 vlan_tbl[vmap->param_id].rdctbl = 2556 vmap->map_to + p_cfgp->start_rdc_grpid; 2557 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 2558 } 2559 } 2560 ddi_prop_free(vlan_cfg_val); 2561 if (good_count != vlan_cnt) { 2562 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2563 nxgep->dip, prop, (int *)good_cfg, good_count); 2564 } 2565 } 2566 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_vlan_config")); 2567 } 2568 2569 static void 2570 nxge_set_hw_mac_class_config(p_nxge_t nxgep) 2571 { 2572 int i; 2573 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2574 p_nxge_hw_pt_cfg_t p_cfgp; 2575 p_nxge_param_t param_arr; 2576 uint_t mac_cnt; 2577 int *mac_cfg_val; 2578 nxge_param_map_t *mac_map; 2579 char *prop; 2580 p_nxge_class_pt_cfg_t p_class_cfgp; 2581 int good_count = 0; 2582 int good_cfg[NXGE_MAX_MACS]; 2583 nxge_mv_cfg_t *mac_host_info; 2584 2585 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "==> nxge_set_hw_mac_config")); 2586 2587 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2588 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2589 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2590 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 2591 2592 param_arr = nxgep->param_arr; 2593 prop = param_arr[param_mac_2rdc_grp].fcode_name; 2594 2595 for (i = 0; i < NXGE_MAX_MACS; i++) { 2596 p_class_cfgp->mac_host_info[i].flag = 0; 2597 p_class_cfgp->mac_host_info[i].rdctbl = 2598 p_cfgp->def_mac_rxdma_grpid; 2599 } 2600 2601 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2602 &mac_cfg_val, &mac_cnt) == DDI_PROP_SUCCESS) { 2603 for (i = 0; i < mac_cnt; i++) { 2604 mac_map = (nxge_param_map_t *)&mac_cfg_val[i]; 2605 if ((mac_map->param_id < p_cfgp->max_macs) && 2606 (mac_map->map_to < 2607 p_cfgp->max_rdc_grpids) && 2608 (mac_map->map_to >= (uint8_t)0)) { 2609 NXGE_DEBUG_MSG((nxgep, CFG2_CTL, 2610 " nxge_mac_config mapping" 2611 " id %d grp %d", 2612 mac_map->param_id, mac_map->map_to)); 2613 mac_host_info[mac_map->param_id].mpr_npr = 2614 mac_map->pref; 2615 mac_host_info[mac_map->param_id].rdctbl = 2616 mac_map->map_to + 2617 p_cfgp->start_rdc_grpid; 2618 good_cfg[good_count] = mac_cfg_val[i]; 2619 if (mac_host_info[mac_map->param_id].flag == 0) 2620 good_count++; 2621 mac_host_info[mac_map->param_id].flag = 1; 2622 } 2623 } 2624 ddi_prop_free(mac_cfg_val); 2625 if (good_count != mac_cnt) { 2626 (void) ddi_prop_update_int_array(DDI_DEV_T_NONE, 2627 nxgep->dip, prop, good_cfg, good_count); 2628 } 2629 } 2630 NXGE_DEBUG_MSG((nxgep, CFG_CTL, "<== nxge_set_hw_mac_config")); 2631 } 2632 2633 static void 2634 nxge_set_hw_class_config(p_nxge_t nxgep) 2635 { 2636 int i; 2637 p_nxge_param_t param_arr; 2638 int *int_prop_val; 2639 uint32_t cfg_value; 2640 char *prop; 2641 p_nxge_class_pt_cfg_t p_class_cfgp; 2642 int start_prop, end_prop; 2643 uint_t prop_cnt; 2644 2645 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " ==> nxge_set_hw_class_config")); 2646 2647 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 2648 param_arr = nxgep->param_arr; 2649 start_prop = param_class_opt_ip_usr4; 2650 end_prop = param_class_opt_ipv6_sctp; 2651 2652 for (i = start_prop; i <= end_prop; i++) { 2653 prop = param_arr[i].fcode_name; 2654 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 2655 0, prop, &int_prop_val, 2656 &prop_cnt) == DDI_PROP_SUCCESS) { 2657 cfg_value = (uint32_t)*int_prop_val; 2658 ddi_prop_free(int_prop_val); 2659 } else { 2660 cfg_value = (uint32_t)param_arr[i].value; 2661 } 2662 p_class_cfgp->class_cfg[i - start_prop] = cfg_value; 2663 } 2664 2665 prop = param_arr[param_h1_init_value].fcode_name; 2666 2667 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2668 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) { 2669 cfg_value = (uint32_t)*int_prop_val; 2670 ddi_prop_free(int_prop_val); 2671 } else { 2672 cfg_value = (uint32_t)param_arr[param_h1_init_value].value; 2673 } 2674 2675 p_class_cfgp->init_h1 = (uint32_t)cfg_value; 2676 prop = param_arr[param_h2_init_value].fcode_name; 2677 2678 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, prop, 2679 &int_prop_val, &prop_cnt) == DDI_PROP_SUCCESS) { 2680 cfg_value = (uint32_t)*int_prop_val; 2681 ddi_prop_free(int_prop_val); 2682 } else { 2683 cfg_value = (uint32_t)param_arr[param_h2_init_value].value; 2684 } 2685 2686 p_class_cfgp->init_h2 = (uint16_t)cfg_value; 2687 NXGE_DEBUG_MSG((nxgep, CFG_CTL, " <== nxge_set_hw_class_config")); 2688 } 2689 2690 nxge_status_t 2691 nxge_ldgv_init_n2(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 2692 { 2693 int i, maxldvs, maxldgs, start, end, nldvs; 2694 int ldv, endldg; 2695 uint8_t func; 2696 uint8_t channel; 2697 uint8_t chn_start; 2698 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 2699 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2700 p_nxge_hw_pt_cfg_t p_cfgp; 2701 p_nxge_ldgv_t ldgvp; 2702 p_nxge_ldg_t ldgp, ptr; 2703 p_nxge_ldv_t ldvp; 2704 nxge_status_t status = NXGE_OK; 2705 2706 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2")); 2707 if (!*navail_p) { 2708 *nrequired_p = 0; 2709 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2710 "<== nxge_ldgv_init:no avail")); 2711 return (NXGE_ERROR); 2712 } 2713 /* 2714 * N2/NIU: one logical device owns one logical group. and each 2715 * device/group will be assigned one vector by Hypervisor. 2716 */ 2717 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2718 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2719 maxldgs = p_cfgp->max_ldgs; 2720 if (!maxldgs) { 2721 /* No devices configured. */ 2722 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init_n2: " 2723 "no logical groups configured.")); 2724 return (NXGE_ERROR); 2725 } else { 2726 maxldvs = maxldgs + 1; 2727 } 2728 2729 /* 2730 * If function zero instance, it needs to handle the system and MIF 2731 * error interrupts. MIF interrupt may not be needed for N2/NIU. 2732 */ 2733 func = nxgep->function_num; 2734 if (func == 0) { 2735 own_sys_err = B_TRUE; 2736 if (!p_cfgp->ser_ldvid) { 2737 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2738 "nxge_ldgv_init_n2: func 0, ERR ID not set!")); 2739 } 2740 /* MIF interrupt */ 2741 if (!p_cfgp->mif_ldvid) { 2742 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2743 "nxge_ldgv_init_n2: func 0, MIF ID not set!")); 2744 } 2745 } 2746 2747 /* 2748 * Assume single partition, each function owns mac. 2749 */ 2750 if (!nxge_use_partition) 2751 own_fzc = B_TRUE; 2752 2753 ldgvp = nxgep->ldgvp; 2754 if (ldgvp == NULL) { 2755 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 2756 nxgep->ldgvp = ldgvp; 2757 ldgvp->maxldgs = (uint8_t)maxldgs; 2758 ldgvp->maxldvs = (uint8_t)maxldvs; 2759 ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs, 2760 KM_SLEEP); 2761 ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs, 2762 KM_SLEEP); 2763 } else { 2764 ldgp = ldgvp->ldgp; 2765 ldvp = ldgvp->ldvp; 2766 } 2767 2768 ldgvp->ndma_ldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs; 2769 ldgvp->tmres = NXGE_TIMER_RESO; 2770 2771 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2772 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d", 2773 maxldvs, maxldgs)); 2774 2775 /* logical start_ldg is ldv */ 2776 ptr = ldgp; 2777 for (i = 0; i < maxldgs; i++) { 2778 ptr->func = func; 2779 ptr->arm = B_TRUE; 2780 ptr->vldg_index = (uint8_t)i; 2781 ptr->ldg_timer = NXGE_TIMER_LDG; 2782 ptr->ldg = p_cfgp->ldg[i]; 2783 ptr->sys_intr_handler = nxge_intr; 2784 ptr->nldvs = 0; 2785 ptr->ldvp = NULL; 2786 ptr->nxgep = nxgep; 2787 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2788 "==> nxge_ldgv_init_n2: maxldvs %d maxldgs %d " 2789 "ldg %d ldgptr $%p", 2790 maxldvs, maxldgs, ptr->ldg, ptr)); 2791 ptr++; 2792 } 2793 2794 endldg = NXGE_INT_MAX_LDG; 2795 nldvs = 0; 2796 ldgvp->nldvs = 0; 2797 ldgp->ldvp = NULL; 2798 *nrequired_p = 0; 2799 2800 /* 2801 * logical device group table is organized in the following order (same 2802 * as what interrupt property has). function 0: owns MAC, MIF, error, 2803 * rx, tx. function 1: owns MAC, rx, tx. 2804 */ 2805 2806 if (own_fzc && p_cfgp->mac_ldvid) { 2807 /* Each function should own MAC interrupt */ 2808 ldv = p_cfgp->mac_ldvid; 2809 ldvp->ldv = (uint8_t)ldv; 2810 ldvp->is_mac = B_TRUE; 2811 ldvp->ldv_intr_handler = nxge_mac_intr; 2812 ldvp->ldv_ldf_masks = 0; 2813 ldvp->nxgep = nxgep; 2814 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2815 "==> nxge_ldgv_init_n2(mac): maxldvs %d ldv %d " 2816 "ldg %d ldgptr $%p ldvptr $%p", 2817 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2818 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2819 nldvs++; 2820 } 2821 2822 if (own_fzc && p_cfgp->mif_ldvid) { 2823 ldv = p_cfgp->mif_ldvid; 2824 ldvp->ldv = (uint8_t)ldv; 2825 ldvp->is_mif = B_TRUE; 2826 ldvp->ldv_intr_handler = nxge_mif_intr; 2827 ldvp->ldv_ldf_masks = 0; 2828 ldvp->nxgep = nxgep; 2829 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2830 "==> nxge_ldgv_init_n2(mif): maxldvs %d ldv %d " 2831 "ldg %d ldgptr $%p ldvptr $%p", 2832 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2833 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2834 nldvs++; 2835 } 2836 2837 ldv = NXGE_SYS_ERROR_LD; 2838 ldvp->use_timer = B_TRUE; 2839 if (own_sys_err && p_cfgp->ser_ldvid) { 2840 ldv = p_cfgp->ser_ldvid; 2841 /* 2842 * Unmask the system interrupt states. 2843 */ 2844 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 2845 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 2846 SYS_ERR_ZCP_MASK); 2847 } 2848 ldvp->ldv = (uint8_t)ldv; 2849 ldvp->is_syserr = B_TRUE; 2850 ldvp->ldv_intr_handler = nxge_syserr_intr; 2851 ldvp->ldv_ldf_masks = 0; 2852 ldvp->nxgep = nxgep; 2853 ldgvp->ldvp_syserr = ldvp; 2854 2855 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2856 "==> nxge_ldgv_init_n2(syserr): maxldvs %d ldv %d " 2857 "ldg %d ldgptr $%p ldvptr p%p", 2858 maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2859 2860 if (own_sys_err && p_cfgp->ser_ldvid) { 2861 (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2862 } else { 2863 ldvp++; 2864 } 2865 2866 nldvs++; 2867 2868 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 2869 "(before rx) func %d nldvs %d navail %d nrequired %d", 2870 func, nldvs, *navail_p, *nrequired_p)); 2871 2872 /* 2873 * Receive DMA channels. 2874 */ 2875 channel = p_cfgp->start_rdc; 2876 start = p_cfgp->start_rdc + NXGE_RDMA_LD_START; 2877 end = start + p_cfgp->max_rdcs; 2878 chn_start = p_cfgp->ldg_chn_start; 2879 /* 2880 * Start with RDC to configure logical devices for each group. 2881 */ 2882 for (i = 0, ldv = start; ldv < end; i++, ldv++, chn_start++) { 2883 ldvp->is_rxdma = B_TRUE; 2884 ldvp->ldv = (uint8_t)ldv; 2885 ldvp->channel = channel++; 2886 ldvp->vdma_index = (uint8_t)i; 2887 ldvp->ldv_intr_handler = nxge_rx_intr; 2888 ldvp->ldv_ldf_masks = 0; 2889 ldvp->nxgep = nxgep; 2890 ldgp->ldg = p_cfgp->ldg[chn_start]; 2891 2892 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2893 "==> nxge_ldgv_init_n2(rx%d): maxldvs %d ldv %d " 2894 "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx", 2895 i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2896 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2897 nldvs++; 2898 } 2899 2900 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 2901 "func %d nldvs %d navail %d nrequired %d", 2902 func, nldvs, *navail_p, *nrequired_p)); 2903 2904 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 2905 "func %d nldvs %d navail %d nrequired %d ldgp 0x%llx " 2906 "ldvp 0x%llx", 2907 func, nldvs, *navail_p, *nrequired_p, ldgp, ldvp)); 2908 /* 2909 * Transmit DMA channels. 2910 */ 2911 channel = p_cfgp->start_tdc; 2912 start = p_cfgp->start_tdc + NXGE_TDMA_LD_START; 2913 end = start + p_cfgp->max_tdcs; 2914 for (i = 0, ldv = start; ldv < end; i++, ldv++, chn_start++) { 2915 ldvp->is_txdma = B_TRUE; 2916 ldvp->ldv = (uint8_t)ldv; 2917 ldvp->channel = channel++; 2918 ldvp->vdma_index = (uint8_t)i; 2919 ldvp->ldv_intr_handler = nxge_tx_intr; 2920 ldvp->ldv_ldf_masks = 0; 2921 ldgp->ldg = p_cfgp->ldg[chn_start]; 2922 ldvp->nxgep = nxgep; 2923 NXGE_DEBUG_MSG((nxgep, INT_CTL, 2924 "==> nxge_ldgv_init_n2(tx%d): maxldvs %d ldv %d " 2925 "ldg %d ldgptr 0x%016llx ldvptr 0x%016llx", 2926 i, maxldvs, ldv, ldgp->ldg, ldgp, ldvp)); 2927 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 2928 nldvs++; 2929 } 2930 2931 ldgvp->ldg_intrs = *nrequired_p; 2932 ldgvp->nldvs = (uint8_t)nldvs; 2933 2934 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init_n2: " 2935 "func %d nldvs %d maxgrps %d navail %d nrequired %d", 2936 func, nldvs, maxldgs, *navail_p, *nrequired_p)); 2937 2938 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init_n2")); 2939 return (status); 2940 } 2941 2942 /* 2943 * Interrupts related interface functions. 2944 */ 2945 2946 nxge_status_t 2947 nxge_ldgv_init(p_nxge_t nxgep, int *navail_p, int *nrequired_p) 2948 { 2949 int i, maxldvs, maxldgs, start, end, nldvs; 2950 int ldv, ldg, endldg, ngrps; 2951 uint8_t func; 2952 uint8_t channel; 2953 boolean_t own_sys_err = B_FALSE, own_fzc = B_FALSE; 2954 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2955 p_nxge_hw_pt_cfg_t p_cfgp; 2956 p_nxge_ldgv_t ldgvp; 2957 p_nxge_ldg_t ldgp, ptr; 2958 p_nxge_ldv_t ldvp; 2959 nxge_status_t status = NXGE_OK; 2960 2961 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init")); 2962 if (!*navail_p) { 2963 *nrequired_p = 0; 2964 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2965 "<== nxge_ldgv_init:no avail")); 2966 return (NXGE_ERROR); 2967 } 2968 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2969 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2970 2971 nldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs; 2972 2973 /* 2974 * If function zero instance, it needs to handle the system error 2975 * interrupts. 2976 */ 2977 func = nxgep->function_num; 2978 if (func == 0) { 2979 nldvs++; 2980 own_sys_err = B_TRUE; 2981 } else { 2982 /* use timer */ 2983 nldvs++; 2984 } 2985 2986 /* 2987 * Assume single partition, each function owns mac. 2988 */ 2989 if (!nxge_use_partition) { 2990 /* mac */ 2991 nldvs++; 2992 /* MIF */ 2993 nldvs++; 2994 own_fzc = B_TRUE; 2995 } 2996 maxldvs = nldvs; 2997 maxldgs = p_cfgp->max_ldgs; 2998 if (!maxldvs || !maxldgs) { 2999 /* No devices configured. */ 3000 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_init: " 3001 "no logical devices or groups configured.")); 3002 return (NXGE_ERROR); 3003 } 3004 ldgvp = nxgep->ldgvp; 3005 if (ldgvp == NULL) { 3006 ldgvp = KMEM_ZALLOC(sizeof (nxge_ldgv_t), KM_SLEEP); 3007 nxgep->ldgvp = ldgvp; 3008 ldgvp->maxldgs = (uint8_t)maxldgs; 3009 ldgvp->maxldvs = (uint8_t)maxldvs; 3010 ldgp = ldgvp->ldgp = KMEM_ZALLOC(sizeof (nxge_ldg_t) * maxldgs, 3011 KM_SLEEP); 3012 ldvp = ldgvp->ldvp = KMEM_ZALLOC(sizeof (nxge_ldv_t) * maxldvs, 3013 KM_SLEEP); 3014 } 3015 ldgvp->ndma_ldvs = p_cfgp->max_tdcs + p_cfgp->max_rdcs; 3016 ldgvp->tmres = NXGE_TIMER_RESO; 3017 3018 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3019 "==> nxge_ldgv_init: maxldvs %d maxldgs %d nldvs %d", 3020 maxldvs, maxldgs, nldvs)); 3021 ldg = p_cfgp->start_ldg; 3022 ptr = ldgp; 3023 for (i = 0; i < maxldgs; i++) { 3024 ptr->func = func; 3025 ptr->arm = B_TRUE; 3026 ptr->vldg_index = (uint8_t)i; 3027 ptr->ldg_timer = NXGE_TIMER_LDG; 3028 ptr->ldg = ldg++; 3029 ptr->sys_intr_handler = nxge_intr; 3030 ptr->nldvs = 0; 3031 ptr->nxgep = nxgep; 3032 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3033 "==> nxge_ldgv_init: maxldvs %d maxldgs %d ldg %d", 3034 maxldvs, maxldgs, ptr->ldg)); 3035 ptr++; 3036 } 3037 3038 ldg = p_cfgp->start_ldg; 3039 if (maxldgs > *navail_p) { 3040 ngrps = *navail_p; 3041 } else { 3042 ngrps = maxldgs; 3043 } 3044 endldg = ldg + ngrps; 3045 3046 /* 3047 * Receive DMA channels. 3048 */ 3049 channel = p_cfgp->start_rdc; 3050 start = p_cfgp->start_rdc + NXGE_RDMA_LD_START; 3051 end = start + p_cfgp->max_rdcs; 3052 nldvs = 0; 3053 ldgvp->nldvs = 0; 3054 ldgp->ldvp = NULL; 3055 *nrequired_p = 0; 3056 3057 /* 3058 * Start with RDC to configure logical devices for each group. 3059 */ 3060 for (i = 0, ldv = start; ldv < end; i++, ldv++) { 3061 ldvp->is_rxdma = B_TRUE; 3062 ldvp->ldv = (uint8_t)ldv; 3063 /* If non-seq needs to change the following code */ 3064 ldvp->channel = channel++; 3065 ldvp->vdma_index = (uint8_t)i; 3066 ldvp->ldv_intr_handler = nxge_rx_intr; 3067 ldvp->ldv_ldf_masks = 0; 3068 ldvp->use_timer = B_FALSE; 3069 ldvp->nxgep = nxgep; 3070 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3071 nldvs++; 3072 } 3073 3074 /* 3075 * Transmit DMA channels. 3076 */ 3077 channel = p_cfgp->start_tdc; 3078 start = p_cfgp->start_tdc + NXGE_TDMA_LD_START; 3079 end = start + p_cfgp->max_tdcs; 3080 for (i = 0, ldv = start; ldv < end; i++, ldv++) { 3081 ldvp->is_txdma = B_TRUE; 3082 ldvp->ldv = (uint8_t)ldv; 3083 ldvp->channel = channel++; 3084 ldvp->vdma_index = (uint8_t)i; 3085 ldvp->ldv_intr_handler = nxge_tx_intr; 3086 ldvp->ldv_ldf_masks = 0; 3087 ldvp->use_timer = B_FALSE; 3088 ldvp->nxgep = nxgep; 3089 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3090 nldvs++; 3091 } 3092 3093 if (own_fzc) { 3094 ldv = NXGE_MIF_LD; 3095 ldvp->ldv = (uint8_t)ldv; 3096 ldvp->is_mif = B_TRUE; 3097 ldvp->ldv_intr_handler = nxge_mif_intr; 3098 ldvp->ldv_ldf_masks = 0; 3099 ldvp->use_timer = B_FALSE; 3100 ldvp->nxgep = nxgep; 3101 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3102 nldvs++; 3103 } 3104 /* 3105 * MAC port (function zero control) 3106 */ 3107 if (own_fzc) { 3108 ldvp->is_mac = B_TRUE; 3109 ldvp->ldv_intr_handler = nxge_mac_intr; 3110 ldvp->ldv_ldf_masks = 0; 3111 ldv = func + NXGE_MAC_LD_START; 3112 ldvp->ldv = (uint8_t)ldv; 3113 ldvp->use_timer = B_FALSE; 3114 ldvp->nxgep = nxgep; 3115 nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3116 nldvs++; 3117 } 3118 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3119 "func %d nldvs %d navail %d nrequired %d", 3120 func, nldvs, *navail_p, *nrequired_p)); 3121 /* 3122 * Function 0 owns system error interrupts. 3123 */ 3124 ldvp->use_timer = B_TRUE; 3125 if (own_sys_err) { 3126 ldv = NXGE_SYS_ERROR_LD; 3127 ldvp->ldv = (uint8_t)ldv; 3128 ldvp->is_syserr = B_TRUE; 3129 ldvp->ldv_intr_handler = nxge_syserr_intr; 3130 ldvp->ldv_ldf_masks = 0; 3131 ldvp->nxgep = nxgep; 3132 ldgvp->ldvp_syserr = ldvp; 3133 /* 3134 * Unmask the system interrupt states. 3135 */ 3136 (void) nxge_fzc_sys_err_mask_set(nxgep, SYS_ERR_SMX_MASK | 3137 SYS_ERR_IPP_MASK | SYS_ERR_TXC_MASK | 3138 SYS_ERR_ZCP_MASK); 3139 3140 (void) nxge_ldgv_setup(&ldgp, &ldvp, ldv, endldg, nrequired_p); 3141 nldvs++; 3142 } else { 3143 ldv = NXGE_SYS_ERROR_LD; 3144 ldvp->ldv = (uint8_t)ldv; 3145 ldvp->is_syserr = B_TRUE; 3146 ldvp->ldv_intr_handler = nxge_syserr_intr; 3147 ldvp->nxgep = nxgep; 3148 ldvp->ldv_ldf_masks = 0; 3149 ldgvp->ldvp_syserr = ldvp; 3150 } 3151 3152 ldgvp->ldg_intrs = *nrequired_p; 3153 3154 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_init: " 3155 "func %d nldvs %d navail %d nrequired %d", 3156 func, nldvs, *navail_p, *nrequired_p)); 3157 3158 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_init")); 3159 return (status); 3160 } 3161 3162 nxge_status_t 3163 nxge_ldgv_uninit(p_nxge_t nxgep) 3164 { 3165 p_nxge_ldgv_t ldgvp; 3166 3167 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_ldgv_uninit")); 3168 ldgvp = nxgep->ldgvp; 3169 if (ldgvp == NULL) { 3170 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_ldgv_uninit: " 3171 "no logical group configured.")); 3172 return (NXGE_OK); 3173 } 3174 if (ldgvp->ldgp) { 3175 KMEM_FREE(ldgvp->ldgp, sizeof (nxge_ldg_t) * ldgvp->maxldgs); 3176 } 3177 if (ldgvp->ldvp) { 3178 KMEM_FREE(ldgvp->ldvp, sizeof (nxge_ldv_t) * ldgvp->maxldvs); 3179 } 3180 KMEM_FREE(ldgvp, sizeof (nxge_ldgv_t)); 3181 nxgep->ldgvp = NULL; 3182 3183 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_ldgv_uninit")); 3184 return (NXGE_OK); 3185 } 3186 3187 nxge_status_t 3188 nxge_intr_ldgv_init(p_nxge_t nxgep) 3189 { 3190 nxge_status_t status = NXGE_OK; 3191 3192 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_ldgv_init")); 3193 /* 3194 * Configure the logical device group numbers, state vectors and 3195 * interrupt masks for each logical device. 3196 */ 3197 status = nxge_fzc_intr_init(nxgep); 3198 3199 /* 3200 * Configure logical device masks and timers. 3201 */ 3202 status = nxge_intr_mask_mgmt(nxgep); 3203 3204 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_ldgv_init")); 3205 return (status); 3206 } 3207 3208 nxge_status_t 3209 nxge_intr_mask_mgmt(p_nxge_t nxgep) 3210 { 3211 p_nxge_ldgv_t ldgvp; 3212 p_nxge_ldg_t ldgp; 3213 p_nxge_ldv_t ldvp; 3214 npi_handle_t handle; 3215 int i, j; 3216 npi_status_t rs = NPI_SUCCESS; 3217 3218 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_mask_mgmt")); 3219 3220 if ((ldgvp = nxgep->ldgvp) == NULL) { 3221 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3222 "<== nxge_intr_mask_mgmt: Null ldgvp")); 3223 return (NXGE_ERROR); 3224 } 3225 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3226 ldgp = ldgvp->ldgp; 3227 ldvp = ldgvp->ldvp; 3228 if (ldgp == NULL || ldvp == NULL) { 3229 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3230 "<== nxge_intr_mask_mgmt: Null ldgp or ldvp")); 3231 return (NXGE_ERROR); 3232 } 3233 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3234 "==> nxge_intr_mask_mgmt: # of intrs %d ", ldgvp->ldg_intrs)); 3235 /* Initialize masks. */ 3236 if (nxgep->niu_type != N2_NIU) { 3237 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3238 "==> nxge_intr_mask_mgmt(Neptune): # intrs %d ", 3239 ldgvp->ldg_intrs)); 3240 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3241 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3242 "==> nxge_intr_mask_mgmt(Neptune): # ldv %d " 3243 "in group %d", ldgp->nldvs, ldgp->ldg)); 3244 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3245 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3246 "==> nxge_intr_mask_mgmt: set ldv # %d " 3247 "for ldg %d", ldvp->ldv, ldgp->ldg)); 3248 rs = npi_intr_mask_set(handle, ldvp->ldv, 3249 ldvp->ldv_ldf_masks); 3250 if (rs != NPI_SUCCESS) { 3251 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3252 "<== nxge_intr_mask_mgmt: " 3253 "set mask failed " 3254 " rs 0x%x ldv %d mask 0x%x", 3255 rs, ldvp->ldv, 3256 ldvp->ldv_ldf_masks)); 3257 return (NXGE_ERROR | rs); 3258 } 3259 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3260 "==> nxge_intr_mask_mgmt: " 3261 "set mask OK " 3262 " rs 0x%x ldv %d mask 0x%x", 3263 rs, ldvp->ldv, 3264 ldvp->ldv_ldf_masks)); 3265 } 3266 } 3267 } 3268 ldgp = ldgvp->ldgp; 3269 /* Configure timer and arm bit */ 3270 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3271 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3272 ldgp->arm, ldgp->ldg_timer); 3273 if (rs != NPI_SUCCESS) { 3274 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3275 "<== nxge_intr_mask_mgmt: " 3276 "set timer failed " 3277 " rs 0x%x dg %d timer 0x%x", 3278 rs, ldgp->ldg, ldgp->ldg_timer)); 3279 return (NXGE_ERROR | rs); 3280 } 3281 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3282 "==> nxge_intr_mask_mgmt: " 3283 "set timer OK " 3284 " rs 0x%x ldg %d timer 0x%x", 3285 rs, ldgp->ldg, ldgp->ldg_timer)); 3286 } 3287 3288 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_fzc_intr_mask_mgmt")); 3289 return (NXGE_OK); 3290 } 3291 3292 nxge_status_t 3293 nxge_intr_mask_mgmt_set(p_nxge_t nxgep, boolean_t on) 3294 { 3295 p_nxge_ldgv_t ldgvp; 3296 p_nxge_ldg_t ldgp; 3297 p_nxge_ldv_t ldvp; 3298 npi_handle_t handle; 3299 int i, j; 3300 npi_status_t rs = NPI_SUCCESS; 3301 3302 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3303 "==> nxge_intr_mask_mgmt_set (%d)", on)); 3304 3305 if (nxgep->niu_type == N2_NIU) { 3306 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3307 "<== nxge_intr_mask_mgmt_set (%d) not set (N2/NIU)", 3308 on)); 3309 return (NXGE_ERROR); 3310 } 3311 3312 if ((ldgvp = nxgep->ldgvp) == NULL) { 3313 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3314 "==> nxge_intr_mask_mgmt_set: Null ldgvp")); 3315 return (NXGE_ERROR); 3316 } 3317 3318 handle = NXGE_DEV_NPI_HANDLE(nxgep); 3319 ldgp = ldgvp->ldgp; 3320 ldvp = ldgvp->ldvp; 3321 if (ldgp == NULL || ldvp == NULL) { 3322 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3323 "<== nxge_intr_mask_mgmt_set: Null ldgp or ldvp")); 3324 return (NXGE_ERROR); 3325 } 3326 /* set masks. */ 3327 for (i = 0; i < ldgvp->ldg_intrs; i++, ldgp++) { 3328 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3329 "==> nxge_intr_mask_mgmt_set: flag %d ldg %d" 3330 "set mask nldvs %d", on, ldgp->ldg, ldgp->nldvs)); 3331 for (j = 0; j < ldgp->nldvs; j++, ldvp++) { 3332 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3333 "==> nxge_intr_mask_mgmt_set: " 3334 "for %d %d flag %d", i, j, on)); 3335 if (on) { 3336 ldvp->ldv_ldf_masks = 0; 3337 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3338 "==> nxge_intr_mask_mgmt_set: " 3339 "ON mask off")); 3340 } else if (!on) { 3341 ldvp->ldv_ldf_masks = (uint8_t)LD_IM1_MASK; 3342 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3343 "==> nxge_intr_mask_mgmt_set:mask on")); 3344 } 3345 rs = npi_intr_mask_set(handle, ldvp->ldv, 3346 ldvp->ldv_ldf_masks); 3347 if (rs != NPI_SUCCESS) { 3348 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3349 "==> nxge_intr_mask_mgmt_set: " 3350 "set mask failed " 3351 " rs 0x%x ldv %d mask 0x%x", 3352 rs, ldvp->ldv, ldvp->ldv_ldf_masks)); 3353 return (NXGE_ERROR | rs); 3354 } 3355 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3356 "==> nxge_intr_mask_mgmt_set: flag %d" 3357 "set mask OK " 3358 " ldv %d mask 0x%x", 3359 on, ldvp->ldv, ldvp->ldv_ldf_masks)); 3360 } 3361 } 3362 3363 ldgp = ldgvp->ldgp; 3364 /* set the arm bit */ 3365 for (i = 0; i < nxgep->ldgvp->ldg_intrs; i++, ldgp++) { 3366 if (on && !ldgp->arm) { 3367 ldgp->arm = B_TRUE; 3368 } else if (!on && ldgp->arm) { 3369 ldgp->arm = B_FALSE; 3370 } 3371 rs = npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 3372 ldgp->arm, ldgp->ldg_timer); 3373 if (rs != NPI_SUCCESS) { 3374 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3375 "<== nxge_intr_mask_mgmt_set: " 3376 "set timer failed " 3377 " rs 0x%x ldg %d timer 0x%x", 3378 rs, ldgp->ldg, ldgp->ldg_timer)); 3379 return (NXGE_ERROR | rs); 3380 } 3381 NXGE_DEBUG_MSG((nxgep, INT_CTL, 3382 "==> nxge_intr_mask_mgmt_set: OK (flag %d) " 3383 "set timer " 3384 " ldg %d timer 0x%x", 3385 on, ldgp->ldg, ldgp->ldg_timer)); 3386 } 3387 3388 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_mask_mgmt_set")); 3389 return (NXGE_OK); 3390 } 3391 3392 static nxge_status_t 3393 nxge_get_mac_addr_properties(p_nxge_t nxgep) 3394 { 3395 #if defined(_BIG_ENDIAN) 3396 uchar_t *prop_val; 3397 uint_t prop_len; 3398 uint_t j; 3399 #endif 3400 uint_t i; 3401 uint8_t func_num; 3402 boolean_t compute_macs = B_TRUE; 3403 3404 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_mac_addr_properties ")); 3405 3406 #if defined(_BIG_ENDIAN) 3407 /* 3408 * Get the ethernet address. 3409 */ 3410 (void) localetheraddr((struct ether_addr *)NULL, &nxgep->ouraddr); 3411 3412 /* 3413 * Check if it is an adapter with its own local mac address If it is 3414 * present, override the system mac address. 3415 */ 3416 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3417 "local-mac-address", &prop_val, 3418 &prop_len) == DDI_PROP_SUCCESS) { 3419 if (prop_len == ETHERADDRL) { 3420 nxgep->factaddr = *(p_ether_addr_t)prop_val; 3421 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Local mac address = " 3422 "%02x:%02x:%02x:%02x:%02x:%02x", 3423 prop_val[0], prop_val[1], prop_val[2], 3424 prop_val[3], prop_val[4], prop_val[5])); 3425 } 3426 ddi_prop_free(prop_val); 3427 } 3428 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3429 "local-mac-address?", &prop_val, 3430 &prop_len) == DDI_PROP_SUCCESS) { 3431 if (strncmp("true", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3432 nxgep->ouraddr = nxgep->factaddr; 3433 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3434 "Using local MAC address")); 3435 } 3436 ddi_prop_free(prop_val); 3437 } else { 3438 nxgep->ouraddr = nxgep->factaddr; 3439 } 3440 3441 if ((nxgep->nxge_hw_p->platform_type != P_NEPTUNE_ATLAS) || 3442 (nxge_is_valid_local_mac(nxgep->factaddr))) 3443 goto got_mac_addr; 3444 3445 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_get_mac_addr_properties: " 3446 "MAC address from properties is not valid...reading from PROM")); 3447 3448 #endif 3449 if (!nxgep->vpd_info.ver_valid) { 3450 (void) nxge_espc_mac_addrs_get(nxgep); 3451 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3452 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 3453 "[%s] invalid...please update", 3454 nxgep->vpd_info.ver)); 3455 return (NXGE_ERROR); 3456 } 3457 nxgep->ouraddr = nxgep->factaddr; 3458 goto got_mac_addr; 3459 } 3460 /* 3461 * First get the MAC address from the info in the VPD data read 3462 * from the EEPROM. 3463 */ 3464 nxge_espc_get_next_mac_addr(nxgep->vpd_info.mac_addr, 3465 nxgep->function_num, &nxgep->factaddr); 3466 3467 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3468 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3469 "nxge_get_mac_addr_properties: " 3470 "MAC address in EEPROM VPD data not valid" 3471 "...reading from NCR registers")); 3472 (void) nxge_espc_mac_addrs_get(nxgep); 3473 if (!nxge_is_valid_local_mac(nxgep->factaddr)) { 3474 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "EEPROM version " 3475 "[%s] invalid...please update", 3476 nxgep->vpd_info.ver)); 3477 return (NXGE_ERROR); 3478 } 3479 } 3480 3481 nxgep->ouraddr = nxgep->factaddr; 3482 3483 got_mac_addr: 3484 func_num = nxgep->function_num; 3485 3486 /* 3487 * Note: mac-addresses property is the list of mac addresses for a 3488 * port. NXGE_MAX_MMAC_ADDRS is the total number of MAC addresses 3489 * allocated for a board. 3490 */ 3491 nxgep->nxge_mmac_info.total_factory_macs = NXGE_MAX_MMAC_ADDRS; 3492 3493 #if defined(_BIG_ENDIAN) 3494 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3495 "mac-addresses", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3496 /* 3497 * XAUI may have up to 18 MACs, more than the XMAC can 3498 * use (1 unique MAC plus 16 alternate MACs) 3499 */ 3500 nxgep->nxge_mmac_info.num_factory_mmac = 3501 prop_len / ETHERADDRL - 1; 3502 if (nxgep->nxge_mmac_info.num_factory_mmac > 3503 XMAC_MAX_ALT_ADDR_ENTRY) { 3504 nxgep->nxge_mmac_info.num_factory_mmac = 3505 XMAC_MAX_ALT_ADDR_ENTRY; 3506 } 3507 3508 for (i = 1; i <= nxgep->nxge_mmac_info.num_factory_mmac; i++) { 3509 for (j = 0; j < ETHERADDRL; j++) { 3510 nxgep->nxge_mmac_info.factory_mac_pool[i][j] = 3511 *(prop_val + (i * ETHERADDRL) + j); 3512 } 3513 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3514 "nxge_get_mac_addr_properties: Alt mac[%d] from " 3515 "mac-addresses property[%2x:%2x:%2x:%2x:%2x:%2x]", 3516 i, nxgep->nxge_mmac_info.factory_mac_pool[i][0], 3517 nxgep->nxge_mmac_info.factory_mac_pool[i][1], 3518 nxgep->nxge_mmac_info.factory_mac_pool[i][2], 3519 nxgep->nxge_mmac_info.factory_mac_pool[i][3], 3520 nxgep->nxge_mmac_info.factory_mac_pool[i][4], 3521 nxgep->nxge_mmac_info.factory_mac_pool[i][5])); 3522 } 3523 3524 compute_macs = B_FALSE; 3525 ddi_prop_free(prop_val); 3526 goto got_mmac_info; 3527 } 3528 #endif 3529 /* 3530 * total_factory_macs = 32 3531 * num_factory_mmac = (32 >> (nports/2)) - 1 3532 * So if nports = 4, then num_factory_mmac = 7 3533 * if nports = 2, then num_factory_mmac = 15 3534 */ 3535 nxgep->nxge_mmac_info.num_factory_mmac = 3536 ((nxgep->nxge_mmac_info.total_factory_macs >> 3537 (nxgep->nports >> 1))) - 1; 3538 3539 got_mmac_info: 3540 3541 if ((nxgep->function_num < 2) && 3542 (nxgep->nxge_mmac_info.num_factory_mmac > 3543 XMAC_MAX_ALT_ADDR_ENTRY)) { 3544 nxgep->nxge_mmac_info.num_factory_mmac = 3545 XMAC_MAX_ALT_ADDR_ENTRY; 3546 } else if ((nxgep->function_num > 1) && 3547 (nxgep->nxge_mmac_info.num_factory_mmac > 3548 BMAC_MAX_ALT_ADDR_ENTRY)) { 3549 nxgep->nxge_mmac_info.num_factory_mmac = 3550 BMAC_MAX_ALT_ADDR_ENTRY; 3551 } 3552 3553 for (i = 0; i <= nxgep->nxge_mmac_info.num_mmac; i++) { 3554 (void) npi_mac_altaddr_disable(nxgep->npi_handle, 3555 NXGE_GET_PORT_NUM(func_num), i); 3556 } 3557 3558 (void) nxge_init_mmac(nxgep, compute_macs); 3559 return (NXGE_OK); 3560 } 3561 3562 void 3563 nxge_get_xcvr_properties(p_nxge_t nxgep) 3564 { 3565 uchar_t *prop_val; 3566 uint_t prop_len; 3567 3568 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_get_xcvr_properties")); 3569 3570 /* 3571 * Read the type of physical layer interface being used. 3572 */ 3573 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3574 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3575 "phy-type", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 3576 if (strncmp("pcs", (caddr_t)prop_val, 3577 (size_t)prop_len) == 0) { 3578 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3579 } else { 3580 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3581 } 3582 ddi_prop_free(prop_val); 3583 } else if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 3584 "phy-interface", &prop_val, 3585 &prop_len) == DDI_PROP_SUCCESS) { 3586 if (strncmp("pcs", (caddr_t)prop_val, (size_t)prop_len) == 0) { 3587 nxgep->statsp->mac_stats.xcvr_inuse = PCS_XCVR; 3588 } else { 3589 nxgep->statsp->mac_stats.xcvr_inuse = INT_MII_XCVR; 3590 } 3591 ddi_prop_free(prop_val); 3592 } 3593 } 3594 3595 /* 3596 * Static functions start here. 3597 */ 3598 3599 static void 3600 nxge_ldgv_setup(p_nxge_ldg_t *ldgp, p_nxge_ldv_t *ldvp, uint8_t ldv, 3601 uint8_t endldg, int *ngrps) 3602 { 3603 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup")); 3604 /* Assign the group number for each device. */ 3605 (*ldvp)->ldg_assigned = (*ldgp)->ldg; 3606 (*ldvp)->ldgp = *ldgp; 3607 (*ldvp)->ldv = ldv; 3608 3609 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 3610 "ldv %d endldg %d ldg %d, ldvp $%p", 3611 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 3612 3613 (*ldgp)->nldvs++; 3614 if ((*ldgp)->ldg == (endldg - 1)) { 3615 if ((*ldgp)->ldvp == NULL) { 3616 (*ldgp)->ldvp = *ldvp; 3617 *ngrps += 1; 3618 NXGE_DEBUG_MSG((NULL, INT_CTL, 3619 "==> nxge_ldgv_setup: ngrps %d", *ngrps)); 3620 } 3621 NXGE_DEBUG_MSG((NULL, INT_CTL, 3622 "==> nxge_ldgv_setup: ldvp $%p ngrps %d", 3623 *ldvp, *ngrps)); 3624 ++*ldvp; 3625 } else { 3626 (*ldgp)->ldvp = *ldvp; 3627 *ngrps += 1; 3628 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup(done): " 3629 "ldv %d endldg %d ldg %d, ldvp $%p", 3630 ldv, endldg, (*ldgp)->ldg, (*ldgp)->ldvp)); 3631 (*ldvp) = ++*ldvp; 3632 (*ldgp) = ++*ldgp; 3633 NXGE_DEBUG_MSG((NULL, INT_CTL, 3634 "==> nxge_ldgv_setup: new ngrps %d", *ngrps)); 3635 } 3636 3637 NXGE_DEBUG_MSG((NULL, INT_CTL, "==> nxge_ldgv_setup: " 3638 "ldv %d ldvp $%p endldg %d ngrps %d", 3639 ldv, ldvp, endldg, *ngrps)); 3640 3641 NXGE_DEBUG_MSG((NULL, INT_CTL, "<== nxge_ldgv_setup")); 3642 } 3643 3644 /* 3645 * Note: This function assumes the following distribution of mac 3646 * addresses among 4 ports in neptune: 3647 * 3648 * ------------- 3649 * 0| |0 - local-mac-address for fn 0 3650 * ------------- 3651 * 1| |1 - local-mac-address for fn 1 3652 * ------------- 3653 * 2| |2 - local-mac-address for fn 2 3654 * ------------- 3655 * 3| |3 - local-mac-address for fn 3 3656 * ------------- 3657 * | |4 - Start of alt. mac addr. for fn 0 3658 * | | 3659 * | | 3660 * | |10 3661 * -------------- 3662 * | |11 - Start of alt. mac addr. for fn 1 3663 * | | 3664 * | | 3665 * | |17 3666 * -------------- 3667 * | |18 - Start of alt. mac addr. for fn 2 3668 * | | 3669 * | | 3670 * | |24 3671 * -------------- 3672 * | |25 - Start of alt. mac addr. for fn 3 3673 * | | 3674 * | | 3675 * | |31 3676 * -------------- 3677 * 3678 * For N2/NIU the mac addresses is from XAUI card. 3679 * 3680 * When 'compute_addrs' is true, the alternate mac addresses are computed 3681 * using the unique mac address as base. Otherwise the alternate addresses 3682 * are assigned from the list read off the 'mac-addresses' property. 3683 */ 3684 3685 static void 3686 nxge_init_mmac(p_nxge_t nxgep, boolean_t compute_addrs) 3687 { 3688 int slot; 3689 uint8_t func_num; 3690 uint16_t *base_mmac_addr; 3691 uint32_t alt_mac_ls4b; 3692 uint16_t *mmac_addr; 3693 uint32_t base_mac_ls4b; /* least significant 4 bytes */ 3694 nxge_mmac_t *mmac_info; 3695 npi_mac_addr_t mac_addr; 3696 3697 func_num = nxgep->function_num; 3698 base_mmac_addr = (uint16_t *)&nxgep->factaddr; 3699 mmac_info = (nxge_mmac_t *)&nxgep->nxge_mmac_info; 3700 3701 if (compute_addrs) { 3702 base_mac_ls4b = ((uint32_t)base_mmac_addr[1]) << 16 | 3703 base_mmac_addr[2]; 3704 3705 if (nxgep->niu_type == N2_NIU) { 3706 /* ls4b of 1st altmac */ 3707 alt_mac_ls4b = base_mac_ls4b + 1; 3708 } else { /* Neptune */ 3709 alt_mac_ls4b = base_mac_ls4b + 3710 (nxgep->nports - func_num) + 3711 (func_num * (mmac_info->num_factory_mmac)); 3712 } 3713 } 3714 3715 /* Set flags for unique MAC */ 3716 mmac_info->mac_pool[0].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 3717 3718 /* Clear flags of all alternate MAC slots */ 3719 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 3720 if (slot <= mmac_info->num_factory_mmac) 3721 mmac_info->mac_pool[slot].flags = MMAC_VENDOR_ADDR; 3722 else 3723 mmac_info->mac_pool[slot].flags = 0; 3724 } 3725 3726 /* Generate and store factory alternate MACs */ 3727 for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 3728 mmac_addr = (uint16_t *)&mmac_info->factory_mac_pool[slot]; 3729 if (compute_addrs) { 3730 mmac_addr[0] = base_mmac_addr[0]; 3731 mac_addr.w2 = mmac_addr[0]; 3732 3733 mmac_addr[1] = (alt_mac_ls4b >> 16) & 0x0FFFF; 3734 mac_addr.w1 = mmac_addr[1]; 3735 3736 mmac_addr[2] = alt_mac_ls4b & 0x0FFFF; 3737 mac_addr.w0 = mmac_addr[2]; 3738 3739 alt_mac_ls4b++; 3740 } else { 3741 mac_addr.w2 = mmac_addr[0]; 3742 mac_addr.w1 = mmac_addr[1]; 3743 mac_addr.w0 = mmac_addr[2]; 3744 } 3745 3746 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 3747 "mac_pool_addr[%2x:%2x:%2x:%2x:%2x:%2x] npi_addr[%x%x%x]", 3748 mmac_info->factory_mac_pool[slot][0], 3749 mmac_info->factory_mac_pool[slot][1], 3750 mmac_info->factory_mac_pool[slot][2], 3751 mmac_info->factory_mac_pool[slot][3], 3752 mmac_info->factory_mac_pool[slot][4], 3753 mmac_info->factory_mac_pool[slot][5], 3754 mac_addr.w0, mac_addr.w1, mac_addr.w2)); 3755 /* 3756 * slot minus 1 because npi_mac_altaddr_entry expects 0 3757 * for the first alternate mac address. 3758 */ 3759 (void) npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, 3760 NXGE_GET_PORT_NUM(func_num), slot - 1, &mac_addr); 3761 } 3762 /* Initialize the first two parameters for mmac kstat */ 3763 nxgep->statsp->mmac_stats.mmac_max_cnt = mmac_info->num_mmac; 3764 nxgep->statsp->mmac_stats.mmac_avail_cnt = mmac_info->num_mmac; 3765 } 3766