1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <inet/common.h> 30 #include <inet/mi.h> 31 #include <inet/nd.h> 32 33 extern uint64_t npi_debug_level; 34 35 #define NXGE_PARAM_MAC_RW \ 36 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 37 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 38 39 #define NXGE_PARAM_MAC_DONT_SHOW \ 40 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 41 42 #define NXGE_PARAM_RXDMA_RW \ 43 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 44 NXGE_PARAM_READ_PROP 45 46 #define NXGE_PARAM_RXDMA_RWC \ 47 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 48 NXGE_PARAM_READ_PROP 49 50 #define NXGE_PARAM_L2CLASS_CFG \ 51 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 52 NXGE_PARAM_NDD_WR_OK 53 54 #define NXGE_PARAM_CLASS_RWS \ 55 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 56 57 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 58 59 #define SET_RX_INTR_TIME_DISABLE 0 60 #define SET_RX_INTR_TIME_ENABLE 1 61 #define SET_RX_INTR_PKTS 2 62 63 #define BASE_ANY 0 64 #define BASE_BINARY 2 65 #define BASE_HEX 16 66 #define BASE_DECIMAL 10 67 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 68 #define ALL_FF_32 0xFFFFFFFFUL 69 70 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 71 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 72 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 73 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 74 75 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 76 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 77 78 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 79 ((mblk_t *)pmp)->b_wptr += plen; \ 80 rlen -= plen; \ 81 } 82 83 static int nxge_param_rx_intr_pkts(p_nxge_t, queue_t *, 84 mblk_t *, char *, caddr_t); 85 static int nxge_param_rx_intr_time(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_mac(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 90 mblk_t *, char *, caddr_t); 91 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 92 mblk_t *, char *, caddr_t); 93 static int nxge_param_set_ether_usr(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_ip_usr(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_set_ip_opt(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 100 queue_t *, mblk_t *, char *, caddr_t); 101 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 102 queue_t *, mblk_t *, char *, caddr_t); 103 static int nxge_param_fflp_hash_init(p_nxge_t, 104 queue_t *, mblk_t *, char *, caddr_t); 105 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 106 mblk_t *, char *, caddr_t); 107 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 108 mblk_t *, char *, caddr_t); 109 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 110 mblk_t *, char *, caddr_t); 111 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 112 p_mblk_t, caddr_t); 113 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 114 p_mblk_t, caddr_t); 115 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 116 p_mblk_t, caddr_t); 117 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 118 p_mblk_t, caddr_t); 119 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 120 p_mblk_t, caddr_t); 121 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 122 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 123 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 124 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 125 char *, caddr_t); 126 static int nxge_param_set_npi_debug_flag(p_nxge_t, 127 queue_t *, mblk_t *, char *, caddr_t); 128 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 129 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 130 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 131 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 135 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 136 static boolean_t nxge_param_link_update(p_nxge_t); 137 138 /* 139 * Global array of Neptune changable parameters. 140 * This array is initialized to correspond to the default 141 * Neptune 4 port configuration. This array would be copied 142 * into each port's parameter structure and modifed per 143 * fcode and nxge.conf configuration. Later, the parameters are 144 * exported to ndd to display and run-time configuration (at least 145 * some of them). 146 * 147 */ 148 149 static nxge_param_t nxge_param_arr[] = { 150 /* 151 * min max value old hw-name conf-name 152 */ 153 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 154 0, 999, 1000, 0, "instance", "instance"}, 155 156 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 157 0, 999, 1000, 0, "main-instance", "main_instance"}, 158 159 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 160 0, 3, 0, 0, "function-number", "function_number"}, 161 162 /* Partition Id */ 163 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 164 0, 8, 0, 0, "partition-id", "partition_id"}, 165 166 /* Read Write Permission Mode */ 167 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 168 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 169 170 /* hw cfg types */ 171 /* control the DMA config of Neptune/NIU */ 172 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 173 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 174 "niu-cfg-type", "niu_cfg_type"}, 175 176 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 177 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 178 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 179 "tx-qcfg-type", "tx_qcfg_type"}, 180 181 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 182 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 183 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 184 "rx-qcfg-type", "rx_qcfg_type"}, 185 186 { nxge_param_get_mac, nxge_param_set_mac, 187 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 188 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 189 190 { nxge_param_get_mac, nxge_param_set_mac, 191 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 195 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 196 197 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 198 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 199 200 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 201 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 202 203 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 204 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 205 206 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 207 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 208 209 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 210 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 211 212 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 213 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 214 215 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 216 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 217 218 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 219 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 220 221 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 222 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 223 224 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 225 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 226 227 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 228 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 229 230 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 231 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 232 233 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 234 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 235 236 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 237 0, 255, 8, 8, "ipg0", "ipg0"}, 238 239 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 240 0, 255, 8, 8, "ipg1", "ipg1"}, 241 242 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 243 0, 255, 4, 4, "ipg2", "ipg2"}, 244 245 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 246 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 247 248 /* Transmit DMA channels */ 249 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 250 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 251 252 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 253 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 254 255 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 256 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 257 { nxge_param_get_txdma_info, NULL, 258 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 259 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 260 261 /* Receive DMA channels */ 262 { nxge_param_get_generic, NULL, 263 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 264 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 265 266 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 267 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 268 269 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 270 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 271 "rx-drr-weight", "rx_drr_weight"}, 272 273 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_READ_PROP, 274 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 275 276 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ, 277 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 278 279 { nxge_param_get_rxdma_info, NULL, 280 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 281 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 282 "rx-rbr-size", "rx_rbr_size"}, 283 284 { nxge_param_get_rxdma_info, NULL, 285 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 286 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 287 "rx-rcr-size", "rx_rcr_size"}, 288 289 { nxge_param_get_generic, nxge_param_set_port_rdc, NXGE_PARAM_RXDMA_RW, 290 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 291 292 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 293 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 294 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 295 296 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 297 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 298 RXDMA_RCR_PTHRES_DEFAULT, 0, 299 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 300 301 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP, 302 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 303 304 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP, 305 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 306 307 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 308 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 309 310 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 311 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 312 313 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 314 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 315 316 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 317 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 318 319 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 320 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 321 322 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 323 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 326 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 327 328 { nxge_param_get_generic, nxge_param_set_grp_rdc, NXGE_PARAM_RXDMA_RW, 329 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 330 331 { nxge_param_get_rxdma_rdcgrp_info, NULL, 332 NXGE_PARAM_READ | NXGE_PARAM_CMPLX, 333 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 334 335 /* Logical device groups */ 336 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 337 0, 63, 0, 0, "start-ldg", "start_ldg"}, 338 339 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 340 0, 64, 0, 0, "max-ldg", "max_ldg" }, 341 342 /* MAC table information */ 343 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 344 NXGE_PARAM_L2CLASS_CFG, 345 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 346 347 /* VLAN table information */ 348 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 349 NXGE_PARAM_L2CLASS_CFG, 350 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 351 352 { nxge_param_get_generic, NULL, 353 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | NXGE_PARAM_PROP_ARR32, 354 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 355 356 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS, 357 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 358 359 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS, 360 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 361 362 { nxge_param_get_generic, nxge_param_tcam_enable, 363 NXGE_PARAM_CLASS_RWS, 364 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 365 366 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 367 NXGE_PARAM_CLASS_RWS, 368 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 369 370 { nxge_param_get_generic, nxge_param_llc_snap_enable, 371 NXGE_PARAM_CLASS_RWS, 372 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 373 374 { nxge_param_get_generic, nxge_param_fflp_hash_init, 375 NXGE_PARAM_CLASS_RWS, 376 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 377 378 { nxge_param_get_generic, nxge_param_fflp_hash_init, 379 NXGE_PARAM_CLASS_RWS, 380 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 381 382 { nxge_param_get_generic, nxge_param_set_ether_usr, 383 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 384 0, ALL_FF_32, 0x0, 0, 385 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 386 387 { nxge_param_get_generic, nxge_param_set_ether_usr, 388 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389 0, ALL_FF_32, 0x0, 0, 390 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 391 392 { nxge_param_get_generic, nxge_param_set_ip_usr, 393 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 394 0, ALL_FF_32, 0x0, 0, 395 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 396 397 { nxge_param_get_generic, nxge_param_set_ip_usr, 398 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 399 0, ALL_FF_32, 0x0, 0, 400 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 401 402 { nxge_param_get_generic, nxge_param_set_ip_usr, 403 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 404 0, ALL_FF_32, 0x0, 0, 405 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 406 407 { nxge_param_get_generic, nxge_param_set_ip_usr, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, ALL_FF_32, 0x0, 0, 410 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 411 412 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 413 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414 0, ALL_FF_32, 0x0, 0, 415 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 416 417 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 418 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419 0, ALL_FF_32, 0x0, 0, 420 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 421 422 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 423 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424 0, ALL_FF_32, 0x0, 0, 425 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 426 427 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 428 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429 0, ALL_FF_32, 0x0, 0, 430 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 431 432 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 433 NXGE_PARAM_CLASS_RWS, 434 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 435 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 436 437 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438 NXGE_PARAM_CLASS_RWS, 439 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 440 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 441 442 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443 NXGE_PARAM_CLASS_RWS, 444 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 445 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 446 447 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448 NXGE_PARAM_CLASS_RWS, 449 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 450 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 451 452 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 453 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 454 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 455 456 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 457 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 458 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 459 460 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 461 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 462 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 463 464 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 465 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 466 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 467 468 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 469 NXGE_PARAM_RW, 470 0ULL, ALL_FF_64, 0ULL, 0ULL, 471 "nxge-debug-flag", "nxge_debug_flag"}, 472 473 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 474 NXGE_PARAM_RW, 475 0ULL, ALL_FF_64, 0ULL, 0ULL, 476 "npi-debug-flag", "npi_debug_flag"}, 477 478 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ, 479 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 480 481 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ, 482 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 483 484 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ, 485 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 486 487 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ, 488 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 489 490 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ, 491 0, 0x0fffffff, 0x0fffffff, 0, 492 "dump-fflp-regs", "dump_fflp_regs"}, 493 494 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ, 495 0, 0x0fffffff, 0x0fffffff, 0, 496 "dump-vlan-table", "dump_vlan_table"}, 497 498 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ, 499 0, 0x0fffffff, 0x0fffffff, 0, 500 "dump-rdc-table", "dump_rdc_table"}, 501 502 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ, 503 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 504 505 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 506 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 507 }; 508 509 extern void *nxge_list; 510 511 void 512 nxge_get_param_soft_properties(p_nxge_t nxgep) 513 { 514 515 p_nxge_param_t param_arr; 516 uint_t prop_len; 517 int i, j; 518 uint32_t param_count; 519 uint32_t *int_prop_val; 520 521 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 522 523 param_arr = nxgep->param_arr; 524 param_count = nxgep->param_count; 525 for (i = 0; i < param_count; i++) { 526 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 527 continue; 528 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 529 continue; 530 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 531 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 532 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 533 nxgep->dip, 0, param_arr[i].fcode_name, 534 (int **)&int_prop_val, 535 (uint_t *)&prop_len) 536 == DDI_PROP_SUCCESS) { 537 uint32_t *cfg_value; 538 uint64_t prop_count; 539 540 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 541 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 542 cfg_value = (uint32_t *)param_arr[i].value; 543 for (j = 0; j < prop_len; j++) { 544 cfg_value[j] = int_prop_val[j]; 545 } 546 prop_count = prop_len; 547 param_arr[i].type |= 548 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 549 ddi_prop_free(int_prop_val); 550 } 551 continue; 552 } 553 554 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 555 param_arr[i].fcode_name, 556 (int **)&int_prop_val, 557 &prop_len) == DDI_PROP_SUCCESS) { 558 if ((*int_prop_val >= param_arr[i].minimum) && 559 (*int_prop_val <= param_arr[i].maximum)) 560 param_arr[i].value = *int_prop_val; 561 #ifdef NXGE_DEBUG_ERROR 562 else { 563 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 564 "nxge%d: 'prom' file parameter error\n", 565 nxgep->instance)); 566 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 567 "Parameter keyword '%s'" 568 " is outside valid range\n", 569 param_arr[i].name)); 570 } 571 #endif 572 ddi_prop_free(int_prop_val); 573 } 574 575 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 576 param_arr[i].name, 577 (int **)&int_prop_val, 578 &prop_len) == DDI_PROP_SUCCESS) { 579 if ((*int_prop_val >= param_arr[i].minimum) && 580 (*int_prop_val <= param_arr[i].maximum)) 581 param_arr[i].value = *int_prop_val; 582 #ifdef NXGE_DEBUG_ERROR 583 else { 584 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 585 "nxge%d: 'conf' file parameter error\n", 586 nxgep->instance)); 587 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 588 "Parameter keyword '%s'" 589 "is outside valid range\n", 590 param_arr[i].name)); 591 } 592 #endif 593 ddi_prop_free(int_prop_val); 594 } 595 } 596 } 597 598 static int 599 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 600 { 601 int status = B_TRUE; 602 int channel; 603 uint8_t grp; 604 char *prop_name; 605 char *end; 606 uint32_t name_chars; 607 608 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 609 "nxge_private_param_register %s", param_arr->name)); 610 611 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 612 return (B_TRUE); 613 614 prop_name = param_arr->name; 615 if (param_arr->type & NXGE_PARAM_RXDMA) { 616 if (strncmp("rxdma_intr", prop_name, 10) == 0) 617 return (B_TRUE); 618 name_chars = strlen("default_grp"); 619 if (strncmp("default_grp", prop_name, name_chars) == 0) { 620 prop_name += name_chars; 621 grp = mi_strtol(prop_name, &end, 10); 622 /* now check if this rdcgrp is in config */ 623 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 624 } 625 name_chars = strlen(prop_name); 626 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 627 return (B_TRUE); 628 } 629 return (B_FALSE); 630 } 631 632 if (param_arr->type & NXGE_PARAM_TXDMA) { 633 name_chars = strlen("txdma"); 634 if (strncmp("txdma", prop_name, name_chars) == 0) { 635 prop_name += name_chars; 636 channel = mi_strtol(prop_name, &end, 10); 637 /* now check if this rdc is in config */ 638 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 639 " nxge_private_param_register: %d", 640 channel)); 641 return (nxge_check_txdma_port_member(nxgep, channel)); 642 } 643 return (B_FALSE); 644 } 645 646 status = B_FALSE; 647 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 648 649 return (status); 650 } 651 652 void 653 nxge_setup_param(p_nxge_t nxgep) 654 { 655 p_nxge_param_t param_arr; 656 int i; 657 pfi_t set_pfi; 658 659 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 660 661 /* 662 * Make sure the param_instance is set to a valid device instance. 663 */ 664 if (nxge_param_arr[param_instance].value == 1000) 665 nxge_param_arr[param_instance].value = nxgep->instance; 666 667 param_arr = nxgep->param_arr; 668 param_arr[param_instance].value = nxgep->instance; 669 param_arr[param_function_number].value = nxgep->function_num; 670 671 for (i = 0; i < nxgep->param_count; i++) { 672 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 673 (nxge_private_param_register(nxgep, 674 ¶m_arr[i]) == B_FALSE)) { 675 param_arr[i].setf = NULL; 676 param_arr[i].getf = NULL; 677 } 678 679 if (param_arr[i].type & NXGE_PARAM_CMPLX) 680 param_arr[i].setf = NULL; 681 682 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 683 param_arr[i].setf = NULL; 684 param_arr[i].getf = NULL; 685 } 686 687 set_pfi = (pfi_t)param_arr[i].setf; 688 689 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 690 set_pfi = NULL; 691 } 692 693 if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 694 (pfi_t)param_arr[i].getf, set_pfi, 695 (caddr_t)¶m_arr[i])) { 696 (void) nxge_nd_free(&nxgep->param_list); 697 break; 698 } 699 } 700 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 701 } 702 703 void 704 nxge_init_param(p_nxge_t nxgep) 705 { 706 p_nxge_param_t param_arr; 707 int i, alloc_size; 708 uint64_t alloc_count; 709 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 710 /* 711 * Make sure the param_instance is set to a valid device instance. 712 */ 713 if (nxge_param_arr[param_instance].value == 1000) 714 nxge_param_arr[param_instance].value = nxgep->instance; 715 716 param_arr = nxgep->param_arr; 717 if (param_arr == NULL) { 718 param_arr = (p_nxge_param_t) 719 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 720 } 721 722 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 723 param_arr[i] = nxge_param_arr[i]; 724 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 725 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 726 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 727 alloc_size = alloc_count * sizeof (uint64_t); 728 param_arr[i].value = 729 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 730 param_arr[i].old_value = 731 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 732 param_arr[i].type |= 733 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 734 } 735 } 736 737 nxgep->param_arr = param_arr; 738 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 739 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 740 nxgep->param_count)); 741 } 742 743 void 744 nxge_destroy_param(p_nxge_t nxgep) 745 { 746 int i; 747 uint64_t free_size, free_count; 748 749 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 750 751 /* 752 * Make sure the param_instance is set to a valid device instance. 753 */ 754 if (nxge_param_arr[param_instance].value == nxgep->instance) { 755 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 756 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 757 (i != nxgep->instance)) 758 break; 759 } 760 nxge_param_arr[param_instance].value = i; 761 } 762 763 if (nxgep->param_list) 764 nxge_nd_free(&nxgep->param_list); 765 for (i = 0; i < nxgep->param_count; i++) 766 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 767 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 768 free_count = ((nxgep->param_arr[i].type & 769 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 770 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 771 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 772 free_size = sizeof (uint64_t) * free_count; 773 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 774 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 775 free_size); 776 } 777 778 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 779 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 780 } 781 782 /* 783 * Extracts the value from the 'nxge' parameter array and prints the 784 * parameter value. cp points to the required parameter. 785 */ 786 787 /* ARGSUSED */ 788 int 789 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 790 { 791 p_nxge_param_t pa = (p_nxge_param_t)cp; 792 793 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 794 "==> nxge_param_get_generic name %s ", pa->name)); 795 796 if (pa->value > 0xffffffff) 797 (void) mi_mpprintf(mp, "%x%x", 798 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 799 else 800 (void) mi_mpprintf(mp, "%x", (int)pa->value); 801 802 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 803 return (0); 804 } 805 806 /* ARGSUSED */ 807 static int 808 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 809 { 810 p_nxge_param_t pa = (p_nxge_param_t)cp; 811 812 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 813 814 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 815 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 816 return (0); 817 } 818 819 /* ARGSUSED */ 820 int 821 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 822 { 823 824 uint_t print_len, buf_len; 825 p_mblk_t np; 826 int tdc; 827 828 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 829 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 830 831 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 832 nxgep->function_num); 833 834 835 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 836 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 837 return (0); 838 } 839 840 buf_len = buff_alloc_size; 841 mp->b_cont = np; 842 843 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 844 "Total TDCs\t %d\n", nxgep->ntdc); 845 846 ((mblk_t *)np)->b_wptr += print_len; 847 buf_len -= print_len; 848 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 849 "TDC\t HW TDC\t\n"); 850 ((mblk_t *)np)->b_wptr += print_len; 851 852 buf_len -= print_len; 853 for (tdc = 0; tdc < nxgep->ntdc; tdc++) { 854 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 855 buf_len, "%d\t %d\n", 856 tdc, nxgep->tdc[tdc]); 857 ((mblk_t *)np)->b_wptr += print_len; 858 buf_len -= print_len; 859 } 860 861 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 862 return (0); 863 } 864 865 /* ARGSUSED */ 866 int 867 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 868 { 869 uint_t print_len, buf_len; 870 p_mblk_t np; 871 int rdc; 872 p_nxge_dma_pt_cfg_t p_dma_cfgp; 873 p_nxge_hw_pt_cfg_t p_cfgp; 874 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 875 p_rx_rcr_rings_t rx_rcr_rings; 876 p_rx_rcr_ring_t *rcr_rings; 877 p_rx_rbr_rings_t rx_rbr_rings; 878 p_rx_rbr_ring_t *rbr_rings; 879 880 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 881 882 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 883 nxgep->function_num); 884 885 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 886 /* The following may work even if we cannot get a large buf. */ 887 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 888 return (0); 889 } 890 891 buf_len = buff_alloc_size; 892 mp->b_cont = np; 893 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 894 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 895 896 rx_rcr_rings = nxgep->rx_rcr_rings; 897 rcr_rings = rx_rcr_rings->rcr_rings; 898 rx_rbr_rings = nxgep->rx_rbr_rings; 899 rbr_rings = rx_rbr_rings->rbr_rings; 900 901 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 902 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 903 904 ((mblk_t *)np)->b_wptr += print_len; 905 buf_len -= print_len; 906 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 907 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 908 "chunks\t RCR ptr\n"); 909 910 ((mblk_t *)np)->b_wptr += print_len; 911 buf_len -= print_len; 912 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 913 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 914 " %d\t %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 915 rdc, nxgep->rdc[rdc], 916 p_dma_cfgp->rcr_timeout[rdc], 917 p_dma_cfgp->rcr_threshold[rdc], 918 rbr_rings[rdc], 919 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 920 ((mblk_t *)np)->b_wptr += print_len; 921 buf_len -= print_len; 922 } 923 924 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 925 return (0); 926 } 927 928 /* ARGSUSED */ 929 int 930 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 931 p_mblk_t mp, caddr_t cp) 932 { 933 uint_t print_len, buf_len; 934 p_mblk_t np; 935 int offset, rdc, i, rdc_grp; 936 p_nxge_rdc_grp_t rdc_grp_p; 937 p_nxge_dma_pt_cfg_t p_dma_cfgp; 938 p_nxge_hw_pt_cfg_t p_cfgp; 939 940 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 941 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 942 "==> nxge_param_get_rxdma_rdcgrp_info")); 943 944 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 945 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 946 947 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 948 nxgep->function_num); 949 950 rdc_grp = p_cfgp->start_rdc_grpid; 951 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 952 /* The following may work even if we cannot get a large buf. */ 953 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 954 return (0); 955 } 956 957 buf_len = buff_alloc_size; 958 mp->b_cont = np; 959 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 960 "Total RDC Groups\t %d \n" 961 "start RDC group\t %d\n", 962 p_cfgp->max_rdc_grpids, 963 p_cfgp->start_rdc_grpid); 964 965 ((mblk_t *)np)->b_wptr += print_len; 966 buf_len -= print_len; 967 968 for (i = 0, rdc_grp = p_cfgp->start_rdc_grpid; 969 rdc_grp < (p_cfgp->max_rdc_grpids + p_cfgp->start_rdc_grpid); 970 rdc_grp++, i++) { 971 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 972 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 973 "\nRDC Group Info for Group [%d] %d\n" 974 "RDC Count %d\tstart RDC %d\n" 975 "RDC Group Population Information" 976 " (offsets 0 - 15)\n", 977 i, rdc_grp, rdc_grp_p->max_rdcs, 978 rdc_grp_p->start_rdc); 979 980 ((mblk_t *)np)->b_wptr += print_len; 981 buf_len -= print_len; 982 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 983 buf_len, "\n"); 984 ((mblk_t *)np)->b_wptr += print_len; 985 buf_len -= print_len; 986 987 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 988 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 989 buf_len, "[%d]=%d ", rdc, 990 rdc_grp_p->start_rdc + rdc); 991 ((mblk_t *)np)->b_wptr += print_len; 992 buf_len -= print_len; 993 } 994 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 995 buf_len, "\n"); 996 ((mblk_t *)np)->b_wptr += print_len; 997 buf_len -= print_len; 998 999 for (offset = 0; offset < 16; offset++) { 1000 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1001 buf_len, " %2d ", 1002 rdc_grp_p->rdc[offset]); 1003 ((mblk_t *)np)->b_wptr += print_len; 1004 buf_len -= print_len; 1005 } 1006 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1007 buf_len, "\n"); 1008 ((mblk_t *)np)->b_wptr += print_len; 1009 buf_len -= print_len; 1010 } 1011 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1012 "<== nxge_param_get_rxdma_rdcgrp_info")); 1013 return (0); 1014 } 1015 1016 int 1017 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1018 { 1019 p_mblk_t tmp; 1020 1021 tmp = mp; 1022 while (tmp->b_cont) 1023 tmp = tmp->b_cont; 1024 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1025 tmp->b_cont = allocb(1024, BPRI_HI); 1026 tmp = tmp->b_cont; 1027 if (!tmp) 1028 return (ENOMEM); 1029 } 1030 1031 *nmp = tmp; 1032 return (0); 1033 } 1034 1035 /* 1036 * Sets the ge parameter to the value in the nxge_param_register using 1037 * nxge_nd_load(). 1038 */ 1039 1040 /* ARGSUSED */ 1041 int 1042 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1043 char *value, caddr_t cp) 1044 { 1045 char *end; 1046 uint32_t new_value; 1047 p_nxge_param_t pa = (p_nxge_param_t)cp; 1048 1049 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1050 new_value = (uint32_t)mi_strtol(value, &end, 10); 1051 if (end == value || new_value < pa->minimum || 1052 new_value > pa->maximum) { 1053 return (EINVAL); 1054 } 1055 pa->value = new_value; 1056 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1057 return (0); 1058 } 1059 1060 /* 1061 * Sets the ge parameter to the value in the nxge_param_register using 1062 * nxge_nd_load(). 1063 */ 1064 1065 /* ARGSUSED */ 1066 int 1067 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1068 char *value, caddr_t cp) 1069 { 1070 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1071 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1072 return (0); 1073 } 1074 1075 /* 1076 * Sets the ge parameter to the value in the nxge_param_register using 1077 * nxge_nd_load(). 1078 */ 1079 1080 /* ARGSUSED */ 1081 int 1082 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1083 char *value, caddr_t cp) 1084 { 1085 char *end; 1086 uint32_t new_value; 1087 int status = 0; 1088 p_nxge_param_t pa = (p_nxge_param_t)cp; 1089 1090 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1091 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1092 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1093 return (EINVAL); 1094 } 1095 1096 if (pa->value != new_value) { 1097 pa->old_value = pa->value; 1098 pa->value = new_value; 1099 } 1100 1101 if (!nxge_param_link_update(nxgep)) { 1102 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1103 " false ret from nxge_param_link_update")); 1104 status = EINVAL; 1105 } 1106 1107 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1108 return (status); 1109 } 1110 1111 /* ARGSUSED */ 1112 static int 1113 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1114 char *value, caddr_t cp) 1115 { 1116 char *end; 1117 uint32_t cfg_value; 1118 p_nxge_param_t pa = (p_nxge_param_t)cp; 1119 1120 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1121 1122 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1123 1124 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1125 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1126 return (EINVAL); 1127 } 1128 1129 if ((pa->value != cfg_value)) { 1130 pa->old_value = pa->value; 1131 pa->value = cfg_value; 1132 nxgep->intr_threshold = pa->value; 1133 } 1134 1135 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1136 return (0); 1137 } 1138 1139 /* ARGSUSED */ 1140 static int 1141 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1142 char *value, caddr_t cp) 1143 { 1144 char *end; 1145 uint32_t cfg_value; 1146 p_nxge_param_t pa = (p_nxge_param_t)cp; 1147 1148 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1149 1150 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1151 1152 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1153 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1154 return (EINVAL); 1155 } 1156 1157 if ((pa->value != cfg_value)) { 1158 pa->old_value = pa->value; 1159 pa->value = cfg_value; 1160 nxgep->intr_timeout = pa->value; 1161 } 1162 1163 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1164 return (0); 1165 } 1166 1167 /* ARGSUSED */ 1168 static int 1169 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1170 mblk_t *mp, char *value, caddr_t cp) 1171 { 1172 char *end; 1173 uint32_t status = 0, cfg_value; 1174 p_nxge_param_t pa = (p_nxge_param_t)cp; 1175 uint32_t cfg_it = B_FALSE; 1176 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1177 p_nxge_hw_pt_cfg_t p_cfgp; 1178 uint32_t *val_ptr, *old_val_ptr; 1179 nxge_param_map_t *mac_map; 1180 p_nxge_class_pt_cfg_t p_class_cfgp; 1181 nxge_mv_cfg_t *mac_host_info; 1182 1183 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1184 1185 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1186 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1187 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1188 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1189 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1190 1191 /* 1192 * now do decoding 1193 */ 1194 mac_map = (nxge_param_map_t *)&cfg_value; 1195 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1196 cfg_value, mac_map->param_id, mac_map->map_to)); 1197 1198 if ((mac_map->param_id < p_cfgp->max_macs) && 1199 (mac_map->map_to < (p_cfgp->max_rdc_grpids + 1200 p_cfgp->start_rdc_grpid)) && (mac_map->map_to >= 1201 p_cfgp->start_rdc_grpid)) { 1202 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1203 " nxge_param_set_mac_rdcgrp mapping" 1204 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1205 val_ptr = (uint32_t *)pa->value; 1206 old_val_ptr = (uint32_t *)pa->old_value; 1207 if (val_ptr[mac_map->param_id] != cfg_value) { 1208 old_val_ptr[mac_map->param_id] = 1209 val_ptr[mac_map->param_id]; 1210 val_ptr[mac_map->param_id] = cfg_value; 1211 mac_host_info[mac_map->param_id].mpr_npr = 1212 mac_map->pref; 1213 mac_host_info[mac_map->param_id].flag = 1; 1214 mac_host_info[mac_map->param_id].rdctbl = 1215 mac_map->map_to; 1216 cfg_it = B_TRUE; 1217 } 1218 } else { 1219 return (EINVAL); 1220 } 1221 1222 if (cfg_it == B_TRUE) { 1223 status = nxge_logical_mac_assign_rdc_table(nxgep, 1224 (uint8_t)mac_map->param_id); 1225 if (status != NXGE_OK) 1226 return (EINVAL); 1227 } 1228 1229 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1230 return (0); 1231 } 1232 1233 /* ARGSUSED */ 1234 static int 1235 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1236 mblk_t *mp, char *value, caddr_t cp) 1237 { 1238 char *end; 1239 uint32_t status = 0, cfg_value; 1240 p_nxge_param_t pa = (p_nxge_param_t)cp; 1241 uint32_t cfg_it = B_FALSE; 1242 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1243 p_nxge_hw_pt_cfg_t p_cfgp; 1244 uint32_t *val_ptr, *old_val_ptr; 1245 nxge_param_map_t *vmap, *old_map; 1246 p_nxge_class_pt_cfg_t p_class_cfgp; 1247 uint64_t cfgd_vlans; 1248 int i, inc = 0, cfg_position; 1249 nxge_mv_cfg_t *vlan_tbl; 1250 1251 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1252 1253 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1254 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1255 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1256 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1257 1258 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1259 1260 /* now do decoding */ 1261 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1262 NXGE_PARAM_ARRAY_CNT_SHIFT); 1263 1264 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1265 /* 1266 * for now, we process only upto max 1267 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1268 * In the future, we may want to expand 1269 * the storage array and continue 1270 */ 1271 return (EINVAL); 1272 } 1273 1274 vmap = (nxge_param_map_t *)&cfg_value; 1275 if ((vmap->param_id) && 1276 (vmap->param_id < NXGE_MAX_VLANS) && 1277 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1278 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1279 "nxge_param_set_vlan_rdcgrp mapping" 1280 " id %d grp %d", 1281 vmap->param_id, vmap->map_to)); 1282 val_ptr = (uint32_t *)pa->value; 1283 old_val_ptr = (uint32_t *)pa->old_value; 1284 1285 /* search to see if this vlan id is already configured */ 1286 for (i = 0; i < cfgd_vlans; i++) { 1287 old_map = (nxge_param_map_t *)&val_ptr[i]; 1288 if ((old_map->param_id == 0) || 1289 (vmap->param_id == old_map->param_id) || 1290 (vlan_tbl[vmap->param_id].flag)) { 1291 cfg_position = i; 1292 break; 1293 } 1294 } 1295 1296 if (cfgd_vlans == 0) { 1297 cfg_position = 0; 1298 inc++; 1299 } 1300 1301 if (i == cfgd_vlans) { 1302 cfg_position = i; 1303 inc++; 1304 } 1305 1306 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1307 "set_vlan_rdcgrp mapping" 1308 " i %d cfgd_vlans %llx position %d ", 1309 i, cfgd_vlans, cfg_position)); 1310 if (val_ptr[cfg_position] != cfg_value) { 1311 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1312 val_ptr[cfg_position] = cfg_value; 1313 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1314 vlan_tbl[vmap->param_id].flag = 1; 1315 vlan_tbl[vmap->param_id].rdctbl = 1316 vmap->map_to + p_cfgp->start_rdc_grpid; 1317 cfg_it = B_TRUE; 1318 if (inc) { 1319 cfgd_vlans++; 1320 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1321 pa->type |= (cfgd_vlans << 1322 NXGE_PARAM_ARRAY_CNT_SHIFT); 1323 1324 } 1325 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1326 "after: param_set_vlan_rdcgrp " 1327 " cfg_vlans %llx position %d \n", 1328 cfgd_vlans, cfg_position)); 1329 } 1330 } else { 1331 return (EINVAL); 1332 } 1333 1334 if (cfg_it == B_TRUE) { 1335 status = nxge_fflp_config_vlan_table(nxgep, 1336 (uint16_t)vmap->param_id); 1337 if (status != NXGE_OK) 1338 return (EINVAL); 1339 } 1340 1341 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1342 return (0); 1343 } 1344 1345 /* ARGSUSED */ 1346 static int 1347 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1348 mblk_t *mp, caddr_t cp) 1349 { 1350 1351 uint_t print_len, buf_len; 1352 p_mblk_t np; 1353 int i; 1354 uint32_t *val_ptr; 1355 nxge_param_map_t *vmap; 1356 p_nxge_param_t pa = (p_nxge_param_t)cp; 1357 p_nxge_class_pt_cfg_t p_class_cfgp; 1358 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1359 p_nxge_hw_pt_cfg_t p_cfgp; 1360 uint64_t cfgd_vlans = 0; 1361 nxge_mv_cfg_t *vlan_tbl; 1362 int buff_alloc_size = 1363 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1364 1365 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1366 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1367 nxgep->function_num); 1368 1369 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1370 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1371 return (0); 1372 } 1373 1374 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1375 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1376 1377 buf_len = buff_alloc_size; 1378 mp->b_cont = np; 1379 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1380 NXGE_PARAM_ARRAY_CNT_SHIFT; 1381 1382 i = (int)cfgd_vlans; 1383 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1384 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1385 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1386 "Configured VLANs %d\n" 1387 "VLAN ID\t RDC GRP (Actual/Port)\t" 1388 " Prefernce\n", i); 1389 ((mblk_t *)np)->b_wptr += print_len; 1390 buf_len -= print_len; 1391 1392 val_ptr = (uint32_t *)pa->value; 1393 1394 for (i = 0; i < cfgd_vlans; i++) { 1395 vmap = (nxge_param_map_t *)&val_ptr[i]; 1396 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1397 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1398 buf_len, 1399 " %d\t\t %d/%d\t\t %d\n", 1400 vmap->param_id, 1401 vlan_tbl[vmap->param_id].rdctbl, 1402 vlan_tbl[vmap->param_id].rdctbl - 1403 p_cfgp->start_rdc_grpid, 1404 vlan_tbl[vmap->param_id].mpr_npr); 1405 ((mblk_t *)np)->b_wptr += print_len; 1406 buf_len -= print_len; 1407 } 1408 } 1409 1410 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1411 return (0); 1412 } 1413 1414 /* ARGSUSED */ 1415 static int 1416 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1417 mblk_t *mp, caddr_t cp) 1418 { 1419 uint_t print_len, buf_len; 1420 p_mblk_t np; 1421 int i; 1422 p_nxge_class_pt_cfg_t p_class_cfgp; 1423 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1424 p_nxge_hw_pt_cfg_t p_cfgp; 1425 nxge_mv_cfg_t *mac_host_info; 1426 1427 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1428 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1429 (void) mi_mpprintf(mp, 1430 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1431 nxgep->function_num); 1432 1433 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1434 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1435 return (0); 1436 } 1437 1438 buf_len = buff_alloc_size; 1439 mp->b_cont = np; 1440 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1441 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1442 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1443 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1444 print_len = snprintf((char *)np->b_wptr, buf_len, 1445 "MAC ID\t RDC GRP (Actual/Port)\t" 1446 " Prefernce\n"); 1447 ((mblk_t *)np)->b_wptr += print_len; 1448 buf_len -= print_len; 1449 for (i = 0; i < p_cfgp->max_macs; i++) { 1450 if (mac_host_info[i].flag) { 1451 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1452 buf_len, 1453 " %d\t %d/%d\t\t %d\n", 1454 i, mac_host_info[i].rdctbl, 1455 mac_host_info[i].rdctbl - 1456 p_cfgp->start_rdc_grpid, 1457 mac_host_info[i].mpr_npr); 1458 ((mblk_t *)np)->b_wptr += print_len; 1459 buf_len -= print_len; 1460 } 1461 } 1462 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1463 "Done Info Dumping \n"); 1464 ((mblk_t *)np)->b_wptr += print_len; 1465 buf_len -= print_len; 1466 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1467 return (0); 1468 } 1469 1470 /* ARGSUSED */ 1471 static int 1472 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1473 mblk_t *mp, char *value, caddr_t cp) 1474 { 1475 uint32_t status = 0, cfg_value; 1476 p_nxge_param_t pa = (p_nxge_param_t)cp; 1477 uint32_t cfg_it = B_FALSE; 1478 char *end; 1479 1480 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1481 1482 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1483 if (pa->value != cfg_value) { 1484 pa->old_value = pa->value; 1485 pa->value = cfg_value; 1486 cfg_it = B_TRUE; 1487 } 1488 1489 if (cfg_it == B_TRUE) { 1490 if (pa->value) 1491 status = nxge_fflp_config_tcam_enable(nxgep); 1492 else 1493 status = nxge_fflp_config_tcam_disable(nxgep); 1494 if (status != NXGE_OK) 1495 return (EINVAL); 1496 } 1497 1498 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1499 return (0); 1500 } 1501 1502 /* ARGSUSED */ 1503 static int 1504 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1505 mblk_t *mp, char *value, caddr_t cp) 1506 { 1507 uint32_t status = 0, cfg_value; 1508 p_nxge_param_t pa = (p_nxge_param_t)cp; 1509 uint32_t cfg_it = B_FALSE; 1510 char *end; 1511 1512 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1513 1514 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1515 if (pa->value != cfg_value) { 1516 pa->old_value = pa->value; 1517 pa->value = cfg_value; 1518 cfg_it = B_TRUE; 1519 } 1520 1521 if (cfg_it == B_TRUE) { 1522 if (pa->value) 1523 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1524 else 1525 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1526 if (status != NXGE_OK) 1527 return (EINVAL); 1528 } 1529 1530 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1531 return (0); 1532 } 1533 1534 /* ARGSUSED */ 1535 static int 1536 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1537 mblk_t *mp, char *value, caddr_t cp) 1538 { 1539 char *end; 1540 uint32_t status = 0, cfg_value; 1541 p_nxge_param_t pa = (p_nxge_param_t)cp; 1542 uint32_t cfg_it = B_FALSE; 1543 1544 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1545 1546 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1547 if (pa->value != cfg_value) { 1548 pa->old_value = pa->value; 1549 pa->value = cfg_value; 1550 cfg_it = B_TRUE; 1551 } 1552 1553 if (cfg_it == B_TRUE) { 1554 if (pa->value) 1555 status = nxge_fflp_config_tcam_enable(nxgep); 1556 else 1557 status = nxge_fflp_config_tcam_disable(nxgep); 1558 if (status != NXGE_OK) 1559 return (EINVAL); 1560 } 1561 1562 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1563 return (0); 1564 } 1565 1566 /* ARGSUSED */ 1567 static int 1568 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1569 mblk_t *mp, char *value, caddr_t cp) 1570 { 1571 char *end; 1572 uint8_t ether_class; 1573 uint32_t status = 0, cfg_value; 1574 p_nxge_param_t pa = (p_nxge_param_t)cp; 1575 uint8_t cfg_it = B_FALSE; 1576 1577 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1578 1579 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1580 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1581 return (EINVAL); 1582 } 1583 1584 if (pa->value != cfg_value) { 1585 pa->old_value = pa->value; 1586 pa->value = cfg_value; 1587 cfg_it = B_TRUE; 1588 } 1589 1590 /* do the actual hw setup */ 1591 if (cfg_it == B_TRUE) { 1592 ether_class = mi_strtol(pa->name, &end, 10); 1593 #ifdef lint 1594 ether_class = ether_class; 1595 #endif 1596 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1597 } 1598 1599 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1600 return (status); 1601 } 1602 1603 /* ARGSUSED */ 1604 static int 1605 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1606 mblk_t *mp, char *value, caddr_t cp) 1607 { 1608 char *end; 1609 tcam_class_t class; 1610 uint32_t status, cfg_value; 1611 p_nxge_param_t pa = (p_nxge_param_t)cp; 1612 uint32_t cfg_it = B_FALSE; 1613 1614 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1615 1616 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1617 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1618 return (EINVAL); 1619 } 1620 1621 if (pa->value != cfg_value) { 1622 pa->old_value = pa->value; 1623 pa->value = cfg_value; 1624 cfg_it = B_TRUE; 1625 } 1626 1627 /* do the actual hw setup with cfg_value. */ 1628 if (cfg_it == B_TRUE) { 1629 class = mi_strtol(pa->name, &end, 10); 1630 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1631 } 1632 1633 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1634 return (status); 1635 } 1636 1637 /* ARGSUSED */ 1638 static int 1639 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1640 { 1641 int i; 1642 int class_instance = param_class_opt_ip_usr4; 1643 p_nxge_param_t param_arr; 1644 1645 param_arr = nxgep->param_arr; 1646 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1647 if (strcmp(param_arr[class_instance].name, name) == 0) 1648 return (i); 1649 class_instance++; 1650 } 1651 return (-1); 1652 } 1653 1654 /* ARGSUSED */ 1655 static int 1656 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1657 mblk_t *mp, char *value, caddr_t cp) 1658 { 1659 char *end; 1660 uint32_t status, cfg_value; 1661 p_nxge_param_t pa = (p_nxge_param_t)cp; 1662 tcam_class_t class; 1663 uint32_t cfg_it = B_FALSE; 1664 1665 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1666 1667 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1668 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1669 return (EINVAL); 1670 } 1671 1672 if (pa->value != cfg_value) { 1673 pa->old_value = pa->value; 1674 pa->value = cfg_value; 1675 cfg_it = B_TRUE; 1676 } 1677 1678 if (cfg_it == B_TRUE) { 1679 /* do the actual hw setup */ 1680 class = nxge_class_name_2value(nxgep, pa->name); 1681 if (class == -1) 1682 return (EINVAL); 1683 1684 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1685 if (status != NXGE_OK) 1686 return (EINVAL); 1687 } 1688 1689 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1690 return (0); 1691 } 1692 1693 /* ARGSUSED */ 1694 static int 1695 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1696 mblk_t *mp, caddr_t cp) 1697 { 1698 uint32_t status, cfg_value; 1699 p_nxge_param_t pa = (p_nxge_param_t)cp; 1700 tcam_class_t class; 1701 1702 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1703 1704 /* do the actual hw setup */ 1705 class = nxge_class_name_2value(nxgep, pa->name); 1706 if (class == -1) 1707 return (EINVAL); 1708 1709 cfg_value = 0; 1710 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1711 if (status != NXGE_OK) 1712 return (EINVAL); 1713 1714 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1715 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1716 1717 pa->value = cfg_value; 1718 (void) mi_mpprintf(mp, "%x", cfg_value); 1719 1720 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1721 return (0); 1722 } 1723 1724 /* ARGSUSED */ 1725 static int 1726 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1727 mblk_t *mp, char *value, caddr_t cp) 1728 { 1729 char *end; 1730 uint32_t status, cfg_value; 1731 p_nxge_param_t pa = (p_nxge_param_t)cp; 1732 tcam_class_t class; 1733 uint32_t cfg_it = B_FALSE; 1734 1735 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1736 1737 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1738 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1739 return (EINVAL); 1740 } 1741 1742 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1743 "nxge_param_fflp_hash_init value %x", cfg_value)); 1744 1745 if (pa->value != cfg_value) { 1746 pa->old_value = pa->value; 1747 pa->value = cfg_value; 1748 cfg_it = B_TRUE; 1749 } 1750 1751 if (cfg_it == B_TRUE) { 1752 char *h_name; 1753 1754 /* do the actual hw setup */ 1755 h_name = pa->name; 1756 h_name++; 1757 class = mi_strtol(h_name, &end, 10); 1758 switch (class) { 1759 case 1: 1760 status = nxge_fflp_set_hash1(nxgep, 1761 (uint32_t)pa->value); 1762 break; 1763 case 2: 1764 status = nxge_fflp_set_hash2(nxgep, 1765 (uint16_t)pa->value); 1766 break; 1767 1768 default: 1769 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1770 " nxge_param_fflp_hash_init" 1771 " %s Wrong hash var %d", 1772 pa->name, class)); 1773 return (EINVAL); 1774 } 1775 if (status != NXGE_OK) 1776 return (EINVAL); 1777 } 1778 1779 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1780 return (0); 1781 } 1782 1783 /* ARGSUSED */ 1784 static int 1785 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1786 mblk_t *mp, char *value, caddr_t cp) 1787 { 1788 char *end; 1789 uint32_t status = 0, cfg_value; 1790 p_nxge_param_t pa = (p_nxge_param_t)cp; 1791 uint32_t cfg_it = B_FALSE; 1792 int rdc_grp; 1793 uint8_t real_rdc; 1794 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1795 p_nxge_hw_pt_cfg_t p_cfgp; 1796 p_nxge_rdc_grp_t rdc_grp_p; 1797 1798 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1799 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1800 1801 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1802 1803 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1804 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1805 return (EINVAL); 1806 } 1807 1808 if (cfg_value >= p_cfgp->max_rdcs) { 1809 return (EINVAL); 1810 } 1811 1812 if (pa->value != cfg_value) { 1813 pa->old_value = pa->value; 1814 pa->value = cfg_value; 1815 cfg_it = B_TRUE; 1816 } 1817 1818 if (cfg_it == B_TRUE) { 1819 char *grp_name; 1820 grp_name = pa->name; 1821 grp_name += strlen("default-grp"); 1822 rdc_grp = mi_strtol(grp_name, &end, 10); 1823 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1824 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1825 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1826 cfg_value) == B_FALSE) { 1827 pa->value = pa->old_value; 1828 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1829 " nxge_param_set_grp_rdc" 1830 " %d read %d actual %d outof range", 1831 rdc_grp, cfg_value, real_rdc)); 1832 return (EINVAL); 1833 } 1834 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1835 real_rdc); 1836 if (status != NXGE_OK) 1837 return (EINVAL); 1838 } 1839 1840 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1841 return (0); 1842 } 1843 1844 /* ARGSUSED */ 1845 static int 1846 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1847 mblk_t *mp, char *value, caddr_t cp) 1848 { 1849 char *end; 1850 uint32_t status = B_TRUE, cfg_value; 1851 p_nxge_param_t pa = (p_nxge_param_t)cp; 1852 uint32_t cfg_it = B_FALSE; 1853 1854 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1855 p_nxge_hw_pt_cfg_t p_cfgp; 1856 1857 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 1858 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1859 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1860 1861 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1862 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1863 return (EINVAL); 1864 } 1865 1866 if (pa->value != cfg_value) { 1867 if (cfg_value >= p_cfgp->max_rdcs) 1868 return (EINVAL); 1869 pa->old_value = pa->value; 1870 pa->value = cfg_value; 1871 cfg_it = B_TRUE; 1872 } 1873 1874 if (cfg_it == B_TRUE) { 1875 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 1876 nxgep->function_num, 1877 nxgep->rdc[cfg_value]); 1878 if (status != NXGE_OK) 1879 return (EINVAL); 1880 } 1881 1882 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 1883 return (0); 1884 } 1885 1886 /* ARGSUSED */ 1887 static int 1888 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 1889 mblk_t *mp, char *value, caddr_t cp) 1890 { 1891 char *end; 1892 uint32_t status = 0; 1893 uint64_t cfg_value = 0; 1894 p_nxge_param_t pa = (p_nxge_param_t)cp; 1895 uint32_t cfg_it = B_FALSE; 1896 1897 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 1898 cfg_value = mi_strtol(value, &end, BASE_HEX); 1899 1900 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1901 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1902 " nxge_param_set_nxge_debug_flag" 1903 " outof range %llx", cfg_value)); 1904 return (EINVAL); 1905 } 1906 if (pa->value != cfg_value) { 1907 pa->old_value = pa->value; 1908 pa->value = cfg_value; 1909 cfg_it = B_TRUE; 1910 } 1911 1912 if (cfg_it == B_TRUE) { 1913 nxgep->nxge_debug_level = pa->value; 1914 } 1915 1916 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 1917 return (status); 1918 } 1919 1920 /* ARGSUSED */ 1921 static int 1922 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1923 { 1924 int status = 0; 1925 p_nxge_param_t pa = (p_nxge_param_t)cp; 1926 1927 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 1928 1929 if (pa->value > 0xffffffff) 1930 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 1931 (int)(pa->value & 0xffffffff)); 1932 else 1933 (void) mi_mpprintf(mp, "%x", (int)pa->value); 1934 1935 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 1936 return (status); 1937 } 1938 1939 /* ARGSUSED */ 1940 static int 1941 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 1942 mblk_t *mp, char *value, caddr_t cp) 1943 { 1944 char *end; 1945 uint32_t status = 0; 1946 uint64_t cfg_value = 0; 1947 p_nxge_param_t pa; 1948 uint32_t cfg_it = B_FALSE; 1949 1950 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 1951 cfg_value = mi_strtol(value, &end, BASE_HEX); 1952 pa = (p_nxge_param_t)cp; 1953 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1954 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 1955 " outof range %llx", cfg_value)); 1956 return (EINVAL); 1957 } 1958 if (pa->value != cfg_value) { 1959 pa->old_value = pa->value; 1960 pa->value = cfg_value; 1961 cfg_it = B_TRUE; 1962 } 1963 1964 if (cfg_it == B_TRUE) { 1965 npi_debug_level = pa->value; 1966 } 1967 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 1968 return (status); 1969 } 1970 1971 /* ARGSUSED */ 1972 static int 1973 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1974 { 1975 uint_t rdc; 1976 1977 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 1978 1979 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 1980 for (rdc = 0; rdc < nxgep->nrdc; rdc++) 1981 (void) nxge_dump_rxdma_channel(nxgep, nxgep->rdc[rdc]); 1982 1983 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 1984 return (0); 1985 } 1986 1987 /* ARGSUSED */ 1988 static int 1989 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1990 { 1991 uint_t tdc; 1992 1993 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 1994 1995 for (tdc = 0; tdc < nxgep->ntdc; tdc++) 1996 (void) nxge_txdma_regs_dump(nxgep, nxgep->tdc[tdc]); 1997 1998 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 1999 return (0); 2000 } 2001 2002 /* ARGSUSED */ 2003 static int 2004 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2005 { 2006 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2007 2008 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2009 2010 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2011 return (0); 2012 } 2013 2014 /* ARGSUSED */ 2015 static int 2016 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2017 { 2018 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2019 2020 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2021 nxgep->function_num); 2022 2023 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2024 return (0); 2025 } 2026 2027 /* ARGSUSED */ 2028 static int 2029 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2030 { 2031 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2032 2033 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2034 nxgep->function_num); 2035 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2036 return (0); 2037 } 2038 2039 /* ARGSUSED */ 2040 static int 2041 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2042 { 2043 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2044 2045 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2046 2047 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2048 return (0); 2049 } 2050 2051 /* ARGSUSED */ 2052 static int 2053 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2054 { 2055 uint8_t table; 2056 2057 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2058 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2059 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2060 table); 2061 } 2062 2063 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2064 return (0); 2065 } 2066 2067 typedef struct block_info { 2068 char *name; 2069 uint32_t offset; 2070 } block_info_t; 2071 2072 block_info_t reg_block[] = { 2073 {"PIO", PIO}, 2074 {"FZC_PIO", FZC_PIO}, 2075 {"FZC_XMAC", FZC_MAC}, 2076 {"FZC_IPP", FZC_IPP}, 2077 {"FFLP", FFLP}, 2078 {"FZC_FFLP", FZC_FFLP}, 2079 {"PIO_VADDR", PIO_VADDR}, 2080 {"ZCP", ZCP}, 2081 {"FZC_ZCP", FZC_ZCP}, 2082 {"DMC", DMC}, 2083 {"FZC_DMC", FZC_DMC}, 2084 {"TXC", TXC}, 2085 {"FZC_TXC", FZC_TXC}, 2086 {"PIO_LDSV", PIO_LDSV}, 2087 {"PIO_LDGIM", PIO_LDGIM}, 2088 {"PIO_IMASK0", PIO_IMASK0}, 2089 {"PIO_IMASK1", PIO_IMASK1}, 2090 {"FZC_PROM", FZC_PROM}, 2091 {"END", ALL_FF_32}, 2092 }; 2093 2094 /* ARGSUSED */ 2095 static int 2096 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2097 { 2098 uint_t print_len, buf_len; 2099 p_mblk_t np; 2100 int rdc, tdc, block; 2101 uint64_t base; 2102 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2103 p_nxge_hw_pt_cfg_t p_cfgp; 2104 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2105 p_tx_ring_t *tx_rings; 2106 p_rx_rcr_rings_t rx_rcr_rings; 2107 p_rx_rcr_ring_t *rcr_rings; 2108 p_rx_rbr_rings_t rx_rbr_rings; 2109 p_rx_rbr_ring_t *rbr_rings; 2110 2111 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2112 "==> nxge_param_dump_ptrs")); 2113 2114 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2115 nxgep->function_num); 2116 2117 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2118 /* The following may work even if we cannot get a large buf. */ 2119 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2120 return (0); 2121 } 2122 2123 buf_len = buff_alloc_size; 2124 mp->b_cont = np; 2125 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2126 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2127 2128 rx_rcr_rings = nxgep->rx_rcr_rings; 2129 rcr_rings = rx_rcr_rings->rcr_rings; 2130 rx_rbr_rings = nxgep->rx_rbr_rings; 2131 rbr_rings = rx_rbr_rings->rbr_rings; 2132 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2133 "nxgep (nxge_t) $%p\n" 2134 "dev_regs (dev_regs_t) $%p\n", 2135 nxgep, nxgep->dev_regs); 2136 2137 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2138 2139 /* do register pointers */ 2140 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2141 "reg base (npi_reg_ptr_t) $%p\t " 2142 "pci reg (npi_reg_ptr_t) $%p\n", 2143 nxgep->dev_regs->nxge_regp, 2144 nxgep->dev_regs->nxge_pciregp); 2145 2146 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2147 2148 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2149 "\nBlock \t Offset \n"); 2150 2151 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2152 block = 0; 2153 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2154 while (reg_block[block].offset != ALL_FF_32) { 2155 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2156 "%9s\t 0x%llx\n", 2157 reg_block[block].name, 2158 (unsigned long long)(reg_block[block].offset + base)); 2159 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2160 block++; 2161 } 2162 2163 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2164 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2165 "rbrp (rx_rbr_ring_t)\n"); 2166 2167 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2168 2169 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2170 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2171 " %d\t $%p\t\t $%p\n", 2172 rdc, rcr_rings[rdc], 2173 rbr_rings[rdc]); 2174 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2175 } 2176 2177 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2178 "\nTDC\t tdcp (tx_ring_t)\n"); 2179 2180 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2181 tx_rings = nxgep->tx_rings->rings; 2182 for (tdc = 0; tdc < p_cfgp->max_tdcs; tdc++) { 2183 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2184 " %d\t $%p\n", tdc, tx_rings[tdc]); 2185 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2186 } 2187 2188 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2189 2190 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2191 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2192 return (0); 2193 } 2194 2195 /* 2196 * Load 'name' into the named dispatch table pointed to by 'ndp'. 2197 * 'ndp' should be the address of a char pointer cell. If the table 2198 * does not exist (*ndp == 0), a new table is allocated and 'ndp' 2199 * is stuffed. If there is not enough space in the table for a new 2200 * entry, more space is allocated. 2201 */ 2202 /* ARGSUSED */ 2203 boolean_t 2204 nxge_nd_load(caddr_t *pparam, char *name, 2205 pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 2206 { 2207 ND *nd; 2208 NDE *nde; 2209 2210 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 2211 if (!pparam) 2212 return (B_FALSE); 2213 2214 if ((nd = (ND *)*pparam) == NULL) { 2215 if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 2216 return (B_FALSE); 2217 *pparam = (caddr_t)nd; 2218 } 2219 2220 if (nd->nd_tbl) { 2221 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2222 if (strcmp(name, nde->nde_name) == 0) 2223 goto fill_it; 2224 } 2225 } 2226 2227 if (nd->nd_free_count <= 1) { 2228 if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 2229 NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 2230 return (B_FALSE); 2231 nd->nd_free_count += NDE_ALLOC_COUNT; 2232 if (nd->nd_tbl) { 2233 bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 2234 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2235 } else { 2236 nd->nd_free_count--; 2237 nde->nde_name = "?"; 2238 nde->nde_get_pfi = nxge_nd_get_names; 2239 nde->nde_set_pfi = nxge_set_default; 2240 } 2241 nde->nde_data = (caddr_t)nd; 2242 nd->nd_tbl = nde; 2243 nd->nd_size += NDE_ALLOC_SIZE; 2244 } 2245 for (nde = nd->nd_tbl; nde->nde_name; nde++) 2246 noop; 2247 nd->nd_free_count--; 2248 fill_it: 2249 nde->nde_name = name; 2250 nde->nde_get_pfi = get_pfi; 2251 nde->nde_set_pfi = set_pfi; 2252 nde->nde_data = data; 2253 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 2254 2255 return (B_TRUE); 2256 } 2257 2258 /* 2259 * Free the table pointed to by 'pparam' 2260 */ 2261 void 2262 nxge_nd_free(caddr_t *pparam) 2263 { 2264 ND *nd; 2265 2266 if ((nd = (ND *)*pparam) != NULL) { 2267 if (nd->nd_tbl) 2268 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2269 KMEM_FREE((char *)nd, sizeof (ND)); 2270 *pparam = nil(caddr_t); 2271 } 2272 } 2273 2274 int 2275 nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 2276 { 2277 int err; 2278 IOCP iocp; 2279 p_mblk_t mp1, mp2; 2280 ND *nd; 2281 NDE *nde; 2282 char *valp; 2283 size_t avail; 2284 2285 if (!param) { 2286 return (B_FALSE); 2287 } 2288 2289 nd = (ND *)param; 2290 iocp = (IOCP)mp->b_rptr; 2291 if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 2292 mp->b_datap->db_type = M_IOCACK; 2293 iocp->ioc_count = 0; 2294 iocp->ioc_error = EINVAL; 2295 return (B_FALSE); 2296 } 2297 2298 /* 2299 * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 2300 * However, existing code sends in some big buffers. 2301 */ 2302 avail = iocp->ioc_count; 2303 if (mp1->b_cont) { 2304 freemsg(mp1->b_cont); 2305 mp1->b_cont = NULL; 2306 } 2307 2308 mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 2309 for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 2310 if (*valp == '-') 2311 *valp = '_'; 2312 } 2313 2314 valp = (char *)mp1->b_rptr; 2315 2316 for (nde = nd->nd_tbl; /* */; nde++) { 2317 if (!nde->nde_name) 2318 return (B_FALSE); 2319 if (strcmp(nde->nde_name, valp) == 0) 2320 break; 2321 } 2322 err = EINVAL; 2323 while (*valp++) 2324 noop; 2325 if (!*valp || valp >= (char *)mp1->b_wptr) 2326 valp = nilp(char); 2327 switch (iocp->ioc_cmd) { 2328 case ND_GET: 2329 /* 2330 * (temporary) hack: "*valp" is size of user buffer for 2331 * copyout. If result of action routine is too big, free 2332 * excess and return ioc_rval as buffer size needed. 2333 * Return as many mblocks as will fit, free the rest. For 2334 * backward compatibility, assume size of original ioctl 2335 * buffer if "*valp" bad or not given. 2336 */ 2337 if (valp) 2338 avail = mi_strtol(valp, (char **)0, 10); 2339 /* 2340 * We overwrite the name/value with the reply data 2341 */ 2342 mp2 = mp1; 2343 while (mp2) { 2344 mp2->b_wptr = mp2->b_rptr; 2345 mp2 = mp2->b_cont; 2346 } 2347 2348 err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2349 2350 if (!err) { 2351 size_t size_out = 0; 2352 size_t excess; 2353 2354 iocp->ioc_rval = 0; 2355 2356 /* Tack on the null */ 2357 err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 2358 if (!err) { 2359 *mp2->b_wptr++ = '\0'; 2360 size_out = msgdsize(mp1); 2361 excess = size_out - avail; 2362 if (excess > 0) { 2363 iocp->ioc_rval = (int)size_out; 2364 size_out -= excess; 2365 (void) adjmsg(mp1, -(excess + 1)); 2366 err = nxge_mk_mblk_tail_space( 2367 mp1, &mp2, 1); 2368 if (!err) 2369 *mp2->b_wptr++ = '\0'; 2370 else 2371 size_out = 0; 2372 } 2373 } else 2374 size_out = 0; 2375 iocp->ioc_count = size_out; 2376 } 2377 break; 2378 2379 case ND_SET: 2380 if (valp) { 2381 if (nde->nde_set_pfi) { 2382 err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 2383 nde->nde_data); 2384 iocp->ioc_count = 0; 2385 freemsg(mp1); 2386 mp->b_cont = NULL; 2387 } 2388 } 2389 break; 2390 2391 default: 2392 break; 2393 } 2394 iocp->ioc_error = err; 2395 mp->b_datap->db_type = M_IOCACK; 2396 return (B_TRUE); 2397 } 2398 2399 /* ARGSUSED */ 2400 int 2401 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2402 { 2403 ND *nd; 2404 NDE *nde; 2405 char *rwtag; 2406 boolean_t get_ok, set_ok; 2407 size_t param_len; 2408 int status = 0; 2409 2410 nd = (ND *)param; 2411 if (!nd) 2412 return (ENOENT); 2413 2414 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2415 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2416 (nde->nde_get_pfi != NULL); 2417 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2418 (nde->nde_set_pfi != NULL); 2419 if (get_ok) { 2420 if (set_ok) 2421 rwtag = "read and write"; 2422 else 2423 rwtag = "read only"; 2424 } else if (set_ok) 2425 rwtag = "write only"; 2426 else { 2427 continue; 2428 } 2429 param_len = strlen(rwtag); 2430 param_len += strlen(nde->nde_name); 2431 param_len += 4; 2432 2433 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2434 } 2435 return (status); 2436 } 2437 2438 /* ARGSUSED */ 2439 int 2440 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2441 { 2442 return (EACCES); 2443 } 2444 2445 /* ARGSUSED */ 2446 int 2447 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2448 caddr_t data) 2449 { 2450 return (EACCES); 2451 } 2452 2453 void 2454 nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2455 { 2456 int cmd; 2457 int status = B_FALSE; 2458 2459 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 2460 cmd = iocp->ioc_cmd; 2461 2462 switch (cmd) { 2463 default: 2464 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2465 "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 2466 break; 2467 2468 case ND_GET: 2469 case ND_SET: 2470 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2471 "nxge_param_ioctl: cmd 0x%0x", cmd)); 2472 if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 2473 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2474 "false ret from nxge_nd_getset")); 2475 break; 2476 } 2477 status = B_TRUE; 2478 break; 2479 } 2480 2481 if (status) { 2482 qreply(wq, mp); 2483 } else { 2484 miocnak(wq, mp, 0, EINVAL); 2485 } 2486 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 2487 } 2488 2489 /* ARGSUSED */ 2490 static boolean_t 2491 nxge_param_link_update(p_nxge_t nxgep) 2492 { 2493 p_nxge_param_t param_arr; 2494 nxge_param_index_t i; 2495 boolean_t update_xcvr; 2496 boolean_t update_dev; 2497 int instance; 2498 boolean_t status = B_TRUE; 2499 2500 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_link_update")); 2501 2502 param_arr = nxgep->param_arr; 2503 instance = nxgep->instance; 2504 update_xcvr = B_FALSE; 2505 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2506 update_xcvr |= param_arr[i].value; 2507 } 2508 2509 if (update_xcvr) { 2510 update_xcvr = B_FALSE; 2511 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2512 update_xcvr |= 2513 (param_arr[i].value != param_arr[i].old_value); 2514 param_arr[i].old_value = param_arr[i].value; 2515 } 2516 if (update_xcvr) { 2517 RW_ENTER_WRITER(&nxgep->filter_lock); 2518 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2519 (void) nxge_link_init(nxgep); 2520 (void) nxge_mac_init(nxgep); 2521 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2522 RW_EXIT(&nxgep->filter_lock); 2523 } 2524 } else { 2525 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2526 " no link capabilities.", instance); 2527 cmn_err(CE_WARN, " Restoring previous setting."); 2528 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2529 param_arr[i].value = param_arr[i].old_value; 2530 } 2531 2532 update_dev = B_FALSE; 2533 2534 if (update_dev) { 2535 RW_ENTER_WRITER(&nxgep->filter_lock); 2536 (void) nxge_rx_mac_disable(nxgep); 2537 (void) nxge_tx_mac_disable(nxgep); 2538 (void) nxge_tx_mac_enable(nxgep); 2539 (void) nxge_rx_mac_enable(nxgep); 2540 RW_EXIT(&nxgep->filter_lock); 2541 } 2542 2543 nxge_param_hw_update_exit: 2544 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2545 "<== nxge_param_link_update status = 0x%08x", status)); 2546 return (status); 2547 } 2548