1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_hio.h> 30 31 #include <inet/common.h> 32 #include <inet/mi.h> 33 #include <inet/nd.h> 34 35 extern uint64_t npi_debug_level; 36 37 #define NXGE_PARAM_MAC_RW \ 38 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 39 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 40 41 #define NXGE_PARAM_MAC_DONT_SHOW \ 42 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 43 44 #define NXGE_PARAM_RXDMA_RW \ 45 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 46 NXGE_PARAM_READ_PROP 47 48 #define NXGE_PARAM_RXDMA_RWC \ 49 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 50 NXGE_PARAM_READ_PROP 51 52 #define NXGE_PARAM_L2CLASS_CFG \ 53 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 54 NXGE_PARAM_NDD_WR_OK 55 56 #define NXGE_PARAM_CLASS_RWS \ 57 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 58 59 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 60 61 #define SET_RX_INTR_TIME_DISABLE 0 62 #define SET_RX_INTR_TIME_ENABLE 1 63 #define SET_RX_INTR_PKTS 2 64 65 #define BASE_ANY 0 66 #define BASE_BINARY 2 67 #define BASE_HEX 16 68 #define BASE_DECIMAL 10 69 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 70 #define ALL_FF_32 0xFFFFFFFFUL 71 72 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 73 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 74 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 75 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 76 77 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 78 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 79 80 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 81 ((mblk_t *)pmp)->b_wptr += plen; \ 82 rlen -= plen; \ 83 } 84 85 static int nxge_param_set_mac(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 90 mblk_t *, char *, caddr_t); 91 static int nxge_param_set_ether_usr(p_nxge_t, 92 queue_t *, mblk_t *, char *, caddr_t); 93 static int nxge_param_set_ip_usr(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_fflp_hash_init(p_nxge_t, 100 queue_t *, mblk_t *, char *, caddr_t); 101 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 102 mblk_t *, char *, caddr_t); 103 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 104 mblk_t *, char *, caddr_t); 105 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 106 mblk_t *, char *, caddr_t); 107 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 108 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 109 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 110 p_mblk_t, caddr_t); 111 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 112 p_mblk_t, caddr_t); 113 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 114 p_mblk_t, caddr_t); 115 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 116 p_mblk_t, caddr_t); 117 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 118 p_mblk_t, caddr_t); 119 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 120 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 121 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 122 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 123 char *, caddr_t); 124 static int nxge_param_set_npi_debug_flag(p_nxge_t, 125 queue_t *, mblk_t *, char *, caddr_t); 126 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 127 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 128 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 129 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 130 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 131 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static void nxge_param_sync(p_nxge_t); 135 136 /* 137 * Global array of Neptune changable parameters. 138 * This array is initialized to correspond to the default 139 * Neptune 4 port configuration. This array would be copied 140 * into each port's parameter structure and modifed per 141 * fcode and nxge.conf configuration. Later, the parameters are 142 * exported to ndd to display and run-time configuration (at least 143 * some of them). 144 * 145 */ 146 147 static nxge_param_t nxge_param_arr[] = { 148 /* 149 * min max value old hw-name conf-name 150 */ 151 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 152 0, 999, 1000, 0, "instance", "instance"}, 153 154 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 155 0, 999, 1000, 0, "main-instance", "main_instance"}, 156 157 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 158 0, 3, 0, 0, "function-number", "function_number"}, 159 160 /* Partition Id */ 161 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 162 0, 8, 0, 0, "partition-id", "partition_id"}, 163 164 /* Read Write Permission Mode */ 165 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 166 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 167 168 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 169 0, 32, 0, 0, "version", "fw_version"}, 170 171 { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 172 0, 32, 0, 0, "port-mode", "port_mode"}, 173 174 /* hw cfg types */ 175 /* control the DMA config of Neptune/NIU */ 176 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 177 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178 "niu-cfg-type", "niu_cfg_type"}, 179 180 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 182 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183 "tx-qcfg-type", "tx_qcfg_type"}, 184 185 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 187 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188 "rx-qcfg-type", "rx_qcfg_type"}, 189 190 { nxge_param_get_mac, nxge_param_set_mac, 191 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, 195 NXGE_PARAM_DONT_SHOW, 196 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197 198 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200 201 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203 204 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206 207 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209 210 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212 213 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215 216 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218 219 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221 222 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224 225 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227 228 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 229 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230 231 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233 234 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 235 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236 237 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 238 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239 240 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 241 0, 255, 8, 8, "ipg0", "ipg0"}, 242 243 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 244 0, 255, 8, 8, "ipg1", "ipg1"}, 245 246 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 247 0, 255, 4, 4, "ipg2", "ipg2"}, 248 249 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251 252 /* Transmit DMA channels */ 253 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 254 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 255 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 256 257 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 260 261 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 264 { nxge_param_get_txdma_info, NULL, 265 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 266 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 267 268 /* Receive DMA channels */ 269 { nxge_param_get_generic, NULL, 270 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 271 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 272 273 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 274 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 276 277 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 280 "rx-drr-weight", "rx_drr_weight"}, 281 282 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 283 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 284 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 285 286 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 287 NXGE_PARAM_DONT_SHOW, 288 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 289 290 { nxge_param_get_rxdma_info, NULL, 291 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 292 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 293 "rx-rbr-size", "rx_rbr_size"}, 294 295 { nxge_param_get_rxdma_info, NULL, 296 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 297 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 298 "rx-rcr-size", "rx_rcr_size"}, 299 300 { nxge_param_get_generic, nxge_param_set_port_rdc, 301 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 302 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 303 304 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 305 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 306 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307 308 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 309 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 310 RXDMA_RCR_PTHRES_DEFAULT, 0, 311 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 312 313 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 314 NXGE_PARAM_DONT_SHOW, 315 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 316 317 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318 NXGE_PARAM_DONT_SHOW, 319 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 320 321 { nxge_param_get_generic, nxge_param_set_grp_rdc, 322 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 323 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, 326 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, 330 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 332 333 { nxge_param_get_generic, nxge_param_set_grp_rdc, 334 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 336 337 { nxge_param_get_generic, nxge_param_set_grp_rdc, 338 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 340 341 { nxge_param_get_generic, nxge_param_set_grp_rdc, 342 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 344 345 { nxge_param_get_generic, nxge_param_set_grp_rdc, 346 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 348 349 { nxge_param_get_generic, nxge_param_set_grp_rdc, 350 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 352 353 { nxge_param_get_rxdma_rdcgrp_info, NULL, 354 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 355 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 356 357 /* Logical device groups */ 358 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 359 0, 63, 0, 0, "start-ldg", "start_ldg"}, 360 361 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 362 0, 64, 0, 0, "max-ldg", "max_ldg" }, 363 364 /* MAC table information */ 365 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 366 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 367 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 368 369 /* VLAN table information */ 370 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 371 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 372 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 373 374 { nxge_param_get_generic, NULL, 375 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 376 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 377 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 378 379 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 380 NXGE_PARAM_DONT_SHOW, 381 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 382 383 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384 NXGE_PARAM_DONT_SHOW, 385 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 386 387 { nxge_param_get_generic, nxge_param_tcam_enable, 388 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 390 391 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 394 395 { nxge_param_get_generic, nxge_param_llc_snap_enable, 396 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 398 399 { nxge_param_get_generic, nxge_param_fflp_hash_init, 400 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 402 403 { nxge_param_get_generic, nxge_param_fflp_hash_init, 404 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 406 407 { nxge_param_get_generic, nxge_param_set_ether_usr, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, ALL_FF_32, 0x0, 0, 410 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 411 412 { nxge_param_get_generic, nxge_param_set_ether_usr, 413 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414 0, ALL_FF_32, 0x0, 0, 415 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 416 417 { nxge_param_get_generic, nxge_param_set_ip_usr, 418 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419 0, ALL_FF_32, 0x0, 0, 420 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 421 422 { nxge_param_get_generic, nxge_param_set_ip_usr, 423 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424 0, ALL_FF_32, 0x0, 0, 425 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 426 427 { nxge_param_get_generic, nxge_param_set_ip_usr, 428 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429 0, ALL_FF_32, 0x0, 0, 430 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 431 432 { nxge_param_get_generic, nxge_param_set_ip_usr, 433 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 434 0, ALL_FF_32, 0x0, 0, 435 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 436 437 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 439 0, ALL_FF_32, 0x0, 0, 440 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 441 442 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 444 0, ALL_FF_32, 0x0, 0, 445 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 446 447 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 449 0, ALL_FF_32, 0x0, 0, 450 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 451 452 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 453 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 454 0, ALL_FF_32, 0x0, 0, 455 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 456 457 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 458 NXGE_PARAM_CLASS_RWS, 459 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 460 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 461 462 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 463 NXGE_PARAM_CLASS_RWS, 464 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 465 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 466 467 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 468 NXGE_PARAM_CLASS_RWS, 469 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 471 472 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 473 NXGE_PARAM_CLASS_RWS, 474 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 475 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 476 477 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 478 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 480 481 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 484 485 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 488 489 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 492 493 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 494 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 495 0ULL, ALL_FF_64, 0ULL, 0ULL, 496 "nxge-debug-flag", "nxge_debug_flag"}, 497 498 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 499 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 500 0ULL, ALL_FF_64, 0ULL, 0ULL, 501 "npi-debug-flag", "npi_debug_flag"}, 502 503 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 504 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 505 506 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 507 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 508 509 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 510 NXGE_PARAM_DONT_SHOW, 511 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 512 513 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 514 NXGE_PARAM_DONT_SHOW, 515 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 516 517 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 518 NXGE_PARAM_DONT_SHOW, 519 0, 0x0fffffff, 0x0fffffff, 0, 520 "dump-fflp-regs", "dump_fflp_regs"}, 521 522 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 523 NXGE_PARAM_DONT_SHOW, 524 0, 0x0fffffff, 0x0fffffff, 0, 525 "dump-vlan-table", "dump_vlan_table"}, 526 527 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 528 NXGE_PARAM_DONT_SHOW, 529 0, 0x0fffffff, 0x0fffffff, 0, 530 "dump-rdc-table", "dump_rdc_table"}, 531 532 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 533 NXGE_PARAM_DONT_SHOW, 534 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 535 536 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 537 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 538 }; 539 540 extern void *nxge_list; 541 542 void 543 nxge_get_param_soft_properties(p_nxge_t nxgep) 544 { 545 546 p_nxge_param_t param_arr; 547 uint_t prop_len; 548 int i, j; 549 uint32_t param_count; 550 uint32_t *int_prop_val; 551 552 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 553 554 param_arr = nxgep->param_arr; 555 param_count = nxgep->param_count; 556 for (i = 0; i < param_count; i++) { 557 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 558 continue; 559 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 560 continue; 561 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 562 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 563 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 564 nxgep->dip, 0, param_arr[i].fcode_name, 565 (int **)&int_prop_val, 566 (uint_t *)&prop_len) 567 == DDI_PROP_SUCCESS) { 568 uint32_t *cfg_value; 569 uint64_t prop_count; 570 571 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 572 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 573 #if defined(__i386) 574 cfg_value = 575 (uint32_t *)(int32_t)param_arr[i].value; 576 #else 577 cfg_value = (uint32_t *)param_arr[i].value; 578 #endif 579 for (j = 0; j < prop_len; j++) { 580 cfg_value[j] = int_prop_val[j]; 581 } 582 prop_count = prop_len; 583 param_arr[i].type |= 584 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 585 ddi_prop_free(int_prop_val); 586 } 587 continue; 588 } 589 590 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 591 param_arr[i].fcode_name, 592 (int **)&int_prop_val, 593 &prop_len) == DDI_PROP_SUCCESS) { 594 if ((*int_prop_val >= param_arr[i].minimum) && 595 (*int_prop_val <= param_arr[i].maximum)) 596 param_arr[i].value = *int_prop_val; 597 #ifdef NXGE_DEBUG_ERROR 598 else { 599 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 600 "nxge%d: 'prom' file parameter error\n", 601 nxgep->instance)); 602 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 603 "Parameter keyword '%s'" 604 " is outside valid range\n", 605 param_arr[i].name)); 606 } 607 #endif 608 ddi_prop_free(int_prop_val); 609 } 610 611 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 612 param_arr[i].name, 613 (int **)&int_prop_val, 614 &prop_len) == DDI_PROP_SUCCESS) { 615 if ((*int_prop_val >= param_arr[i].minimum) && 616 (*int_prop_val <= param_arr[i].maximum)) 617 param_arr[i].value = *int_prop_val; 618 #ifdef NXGE_DEBUG_ERROR 619 else { 620 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 621 "nxge%d: 'conf' file parameter error\n", 622 nxgep->instance)); 623 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 624 "Parameter keyword '%s'" 625 "is outside valid range\n", 626 param_arr[i].name)); 627 } 628 #endif 629 ddi_prop_free(int_prop_val); 630 } 631 } 632 } 633 634 static int 635 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 636 { 637 int status = B_TRUE; 638 int channel; 639 uint8_t grp; 640 char *prop_name; 641 char *end; 642 uint32_t name_chars; 643 644 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 645 "nxge_private_param_register %s", param_arr->name)); 646 647 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 648 return (B_TRUE); 649 650 prop_name = param_arr->name; 651 if (param_arr->type & NXGE_PARAM_RXDMA) { 652 if (strncmp("rxdma_intr", prop_name, 10) == 0) 653 return (B_TRUE); 654 name_chars = strlen("default_grp"); 655 if (strncmp("default_grp", prop_name, name_chars) == 0) { 656 prop_name += name_chars; 657 grp = mi_strtol(prop_name, &end, 10); 658 /* now check if this rdcgrp is in config */ 659 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 660 } 661 name_chars = strlen(prop_name); 662 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 663 return (B_TRUE); 664 } 665 return (B_FALSE); 666 } 667 668 if (param_arr->type & NXGE_PARAM_TXDMA) { 669 name_chars = strlen("txdma"); 670 if (strncmp("txdma", prop_name, name_chars) == 0) { 671 prop_name += name_chars; 672 channel = mi_strtol(prop_name, &end, 10); 673 /* now check if this rdc is in config */ 674 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 675 " nxge_private_param_register: %d", 676 channel)); 677 return (nxge_check_txdma_port_member(nxgep, channel)); 678 } 679 return (B_FALSE); 680 } 681 682 status = B_FALSE; 683 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 684 685 return (status); 686 } 687 688 void 689 nxge_setup_param(p_nxge_t nxgep) 690 { 691 p_nxge_param_t param_arr; 692 int i; 693 pfi_t set_pfi; 694 695 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 696 697 /* 698 * Make sure the param_instance is set to a valid device instance. 699 */ 700 if (nxge_param_arr[param_instance].value == 1000) 701 nxge_param_arr[param_instance].value = nxgep->instance; 702 703 param_arr = nxgep->param_arr; 704 param_arr[param_instance].value = nxgep->instance; 705 param_arr[param_function_number].value = nxgep->function_num; 706 707 for (i = 0; i < nxgep->param_count; i++) { 708 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 709 (nxge_private_param_register(nxgep, 710 ¶m_arr[i]) == B_FALSE)) { 711 param_arr[i].setf = NULL; 712 param_arr[i].getf = NULL; 713 } 714 715 if (param_arr[i].type & NXGE_PARAM_CMPLX) 716 param_arr[i].setf = NULL; 717 718 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 719 param_arr[i].setf = NULL; 720 param_arr[i].getf = NULL; 721 } 722 723 set_pfi = (pfi_t)param_arr[i].setf; 724 725 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 726 set_pfi = NULL; 727 } 728 729 if (!nxge_nd_load(&nxgep->param_list, param_arr[i].name, 730 (pfi_t)param_arr[i].getf, set_pfi, 731 (caddr_t)¶m_arr[i])) { 732 (void) nxge_nd_free(&nxgep->param_list); 733 break; 734 } 735 } 736 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 737 } 738 739 void 740 nxge_init_param(p_nxge_t nxgep) 741 { 742 p_nxge_param_t param_arr; 743 int i, alloc_size; 744 uint64_t alloc_count; 745 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 746 /* 747 * Make sure the param_instance is set to a valid device instance. 748 */ 749 if (nxge_param_arr[param_instance].value == 1000) 750 nxge_param_arr[param_instance].value = nxgep->instance; 751 752 param_arr = nxgep->param_arr; 753 if (param_arr == NULL) { 754 param_arr = (p_nxge_param_t) 755 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 756 } 757 758 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 759 param_arr[i] = nxge_param_arr[i]; 760 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 761 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 762 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 763 alloc_size = alloc_count * sizeof (uint64_t); 764 param_arr[i].value = 765 #if defined(__i386) 766 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 767 #else 768 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 769 #endif 770 param_arr[i].old_value = 771 #if defined(__i386) 772 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 773 KM_SLEEP); 774 #else 775 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 776 #endif 777 param_arr[i].type |= 778 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 779 } 780 } 781 782 nxgep->param_arr = param_arr; 783 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 784 785 nxge_param_sync(nxgep); 786 787 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 788 nxgep->param_count)); 789 } 790 791 void 792 nxge_destroy_param(p_nxge_t nxgep) 793 { 794 int i; 795 uint64_t free_size, free_count; 796 797 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 798 799 if (nxgep->param_arr == NULL) 800 return; 801 /* 802 * Make sure the param_instance is set to a valid device instance. 803 */ 804 if (nxge_param_arr[param_instance].value == nxgep->instance) { 805 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 806 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 807 (i != nxgep->instance)) 808 break; 809 } 810 nxge_param_arr[param_instance].value = i; 811 } 812 813 if (nxgep->param_list) 814 nxge_nd_free(&nxgep->param_list); 815 for (i = 0; i < nxgep->param_count; i++) 816 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 817 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 818 free_count = ((nxgep->param_arr[i].type & 819 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 820 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 821 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 822 free_size = sizeof (uint64_t) * free_count; 823 #if defined(__i386) 824 KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 825 free_size); 826 #else 827 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 828 #endif 829 #if defined(__i386) 830 KMEM_FREE((void *)(uint32_t) 831 nxgep->param_arr[i].old_value, free_size); 832 #else 833 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 834 free_size); 835 #endif 836 } 837 838 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 839 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 840 } 841 842 /* 843 * Extracts the value from the 'nxge' parameter array and prints the 844 * parameter value. cp points to the required parameter. 845 */ 846 847 /* ARGSUSED */ 848 int 849 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 850 { 851 p_nxge_param_t pa = (p_nxge_param_t)cp; 852 853 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 854 "==> nxge_param_get_generic name %s ", pa->name)); 855 856 if (pa->value > 0xffffffff) 857 (void) mi_mpprintf(mp, "%x%x", 858 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 859 else 860 (void) mi_mpprintf(mp, "%x", (int)pa->value); 861 862 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 863 return (0); 864 } 865 866 /* ARGSUSED */ 867 static int 868 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 869 { 870 p_nxge_param_t pa = (p_nxge_param_t)cp; 871 872 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 873 874 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 875 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 876 return (0); 877 } 878 879 /* ARGSUSED */ 880 static int 881 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 882 { 883 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 884 885 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 886 nxgep->instance, nxgep->vpd_info.ver); 887 888 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 889 return (0); 890 } 891 892 /* ARGSUSED */ 893 static int 894 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 895 { 896 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 897 898 switch (nxgep->mac.portmode) { 899 case PORT_1G_COPPER: 900 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 901 nxgep->instance, 902 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 903 break; 904 case PORT_1G_FIBER: 905 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 906 nxgep->instance, 907 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 908 break; 909 case PORT_10G_COPPER: 910 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 911 "%s\n", nxgep->instance, 912 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 913 break; 914 case PORT_10G_FIBER: 915 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 916 nxgep->instance, 917 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 918 break; 919 case PORT_10G_SERDES: 920 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 921 "%s\n", nxgep->instance, 922 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 923 break; 924 case PORT_1G_SERDES: 925 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 926 nxgep->instance, 927 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 928 break; 929 case PORT_1G_RGMII_FIBER: 930 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 931 "Fiber %s\n", nxgep->instance, 932 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 933 break; 934 case PORT_HSP_MODE: 935 (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 936 "PHY, Currently NOT present\n", nxgep->instance); 937 break; 938 default: 939 (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 940 nxgep->instance, 941 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 942 break; 943 } 944 945 (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 946 nxgep->instance, 947 nxgep->soft_lso_enable ? "enable" : "disable"); 948 949 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 950 return (0); 951 } 952 953 /* ARGSUSED */ 954 int 955 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 956 { 957 958 uint_t print_len, buf_len; 959 p_mblk_t np; 960 961 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 962 int tdc; 963 964 nxge_grp_set_t *set; 965 966 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 967 968 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 969 nxgep->function_num); 970 971 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 972 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 973 return (0); 974 } 975 976 buf_len = buff_alloc_size; 977 mp->b_cont = np; 978 print_len = 0; 979 980 ((mblk_t *)np)->b_wptr += print_len; 981 buf_len -= print_len; 982 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 983 "TDC\t HW TDC\t\n"); 984 ((mblk_t *)np)->b_wptr += print_len; 985 buf_len -= print_len; 986 987 set = &nxgep->tx_set; 988 for (tdc = 0; tdc < NXGE_MAX_RDCS; tdc++) { 989 if ((1 << tdc) & set->owned.map) { 990 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 991 buf_len, "%d\n", tdc); 992 ((mblk_t *)np)->b_wptr += print_len; 993 buf_len -= print_len; 994 } 995 } 996 997 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 998 return (0); 999 } 1000 1001 /* ARGSUSED */ 1002 int 1003 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 1004 { 1005 uint_t print_len, buf_len; 1006 p_mblk_t np; 1007 int rdc; 1008 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1009 p_nxge_hw_pt_cfg_t p_cfgp; 1010 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1011 p_rx_rcr_rings_t rx_rcr_rings; 1012 p_rx_rcr_ring_t *rcr_rings; 1013 p_rx_rbr_rings_t rx_rbr_rings; 1014 p_rx_rbr_ring_t *rbr_rings; 1015 nxge_grp_set_t *set; 1016 1017 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 1018 1019 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1020 nxgep->function_num); 1021 1022 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1023 /* The following may work even if we cannot get a large buf. */ 1024 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1025 return (0); 1026 } 1027 1028 buf_len = buff_alloc_size; 1029 mp->b_cont = np; 1030 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1031 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1032 1033 rx_rcr_rings = nxgep->rx_rcr_rings; 1034 rcr_rings = rx_rcr_rings->rcr_rings; 1035 rx_rbr_rings = nxgep->rx_rbr_rings; 1036 rbr_rings = rx_rbr_rings->rbr_rings; 1037 1038 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1039 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 1040 1041 ((mblk_t *)np)->b_wptr += print_len; 1042 buf_len -= print_len; 1043 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1044 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1045 "chunks\t RCR ptr\n"); 1046 1047 ((mblk_t *)np)->b_wptr += print_len; 1048 buf_len -= print_len; 1049 1050 set = &nxgep->rx_set; 1051 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1052 if ((1 << rdc) & set->owned.map) { 1053 print_len = snprintf((char *) 1054 ((mblk_t *)np)->b_wptr, buf_len, 1055 " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1056 rdc, 1057 p_dma_cfgp->rcr_timeout[rdc], 1058 p_dma_cfgp->rcr_threshold[rdc], 1059 rbr_rings[rdc], 1060 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 1061 ((mblk_t *)np)->b_wptr += print_len; 1062 buf_len -= print_len; 1063 } 1064 } 1065 1066 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 1067 return (0); 1068 } 1069 1070 /* ARGSUSED */ 1071 int 1072 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1073 p_mblk_t mp, caddr_t cp) 1074 { 1075 uint_t print_len, buf_len; 1076 p_mblk_t np; 1077 int offset, rdc, i, rdc_grp; 1078 p_nxge_rdc_grp_t rdc_grp_p; 1079 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1080 p_nxge_hw_pt_cfg_t p_cfgp; 1081 1082 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1083 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1084 "==> nxge_param_get_rxdma_rdcgrp_info")); 1085 1086 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1087 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1088 1089 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1090 nxgep->function_num); 1091 1092 rdc_grp = p_cfgp->def_mac_rxdma_grpid; 1093 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1094 /* The following may work even if we cannot get a large buf. */ 1095 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1096 return (0); 1097 } 1098 1099 buf_len = buff_alloc_size; 1100 mp->b_cont = np; 1101 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1102 "Total RDC Groups\t %d \n" 1103 "default RDC group\t %d\n", 1104 p_cfgp->max_rdc_grpids, 1105 p_cfgp->def_mac_rxdma_grpid); 1106 1107 ((mblk_t *)np)->b_wptr += print_len; 1108 buf_len -= print_len; 1109 1110 for (i = 0; i < NXGE_MAX_RDCS; i++) { 1111 if (p_cfgp->grpids[i]) { 1112 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1113 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1114 buf_len, 1115 "\nRDC Group Info for Group [%d] %d\n" 1116 "RDC Count %d\tstart RDC %d\n" 1117 "RDC Group Population Information" 1118 " (offsets 0 - 15)\n", 1119 i, rdc_grp, rdc_grp_p->max_rdcs, 1120 rdc_grp_p->start_rdc); 1121 1122 ((mblk_t *)np)->b_wptr += print_len; 1123 buf_len -= print_len; 1124 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1125 buf_len, "\n"); 1126 ((mblk_t *)np)->b_wptr += print_len; 1127 buf_len -= print_len; 1128 1129 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1130 print_len = snprintf( 1131 (char *)((mblk_t *)np)->b_wptr, 1132 buf_len, "[%d]=%d ", rdc, 1133 rdc_grp_p->start_rdc + rdc); 1134 ((mblk_t *)np)->b_wptr += print_len; 1135 buf_len -= print_len; 1136 } 1137 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1138 buf_len, "\n"); 1139 ((mblk_t *)np)->b_wptr += print_len; 1140 buf_len -= print_len; 1141 1142 for (offset = 0; offset < 16; offset++) { 1143 print_len = snprintf( 1144 (char *)((mblk_t *)np)->b_wptr, 1145 buf_len, " %c", 1146 rdc_grp_p->map & (1 << offset) ? 1147 '1' : '0'); 1148 ((mblk_t *)np)->b_wptr += print_len; 1149 buf_len -= print_len; 1150 } 1151 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1152 buf_len, "\n"); 1153 ((mblk_t *)np)->b_wptr += print_len; 1154 buf_len -= print_len; 1155 } 1156 } 1157 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1158 "<== nxge_param_get_rxdma_rdcgrp_info")); 1159 return (0); 1160 } 1161 1162 int 1163 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1164 { 1165 p_mblk_t tmp; 1166 1167 tmp = mp; 1168 while (tmp->b_cont) 1169 tmp = tmp->b_cont; 1170 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1171 tmp->b_cont = allocb(1024, BPRI_HI); 1172 tmp = tmp->b_cont; 1173 if (!tmp) 1174 return (ENOMEM); 1175 } 1176 1177 *nmp = tmp; 1178 return (0); 1179 } 1180 1181 /* 1182 * Sets the ge parameter to the value in the nxge_param_register using 1183 * nxge_nd_load(). 1184 */ 1185 1186 /* ARGSUSED */ 1187 int 1188 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1189 char *value, caddr_t cp) 1190 { 1191 char *end; 1192 uint32_t new_value; 1193 p_nxge_param_t pa = (p_nxge_param_t)cp; 1194 1195 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1196 new_value = (uint32_t)mi_strtol(value, &end, 10); 1197 if (end == value || new_value < pa->minimum || 1198 new_value > pa->maximum) { 1199 return (EINVAL); 1200 } 1201 pa->value = new_value; 1202 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1203 return (0); 1204 } 1205 1206 /* 1207 * Sets the ge parameter to the value in the nxge_param_register using 1208 * nxge_nd_load(). 1209 */ 1210 1211 /* ARGSUSED */ 1212 int 1213 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1214 char *value, caddr_t cp) 1215 { 1216 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1217 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1218 return (0); 1219 } 1220 1221 /* 1222 * Sets the ge parameter to the value in the nxge_param_register using 1223 * nxge_nd_load(). 1224 */ 1225 1226 /* ARGSUSED */ 1227 int 1228 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1229 char *value, caddr_t cp) 1230 { 1231 char *end; 1232 uint32_t new_value; 1233 int status = 0; 1234 p_nxge_param_t pa = (p_nxge_param_t)cp; 1235 1236 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1237 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1238 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1239 return (EINVAL); 1240 } 1241 1242 if (pa->value != new_value) { 1243 pa->old_value = pa->value; 1244 pa->value = new_value; 1245 } 1246 1247 if (!nxge_param_link_update(nxgep)) { 1248 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1249 " false ret from nxge_param_link_update")); 1250 status = EINVAL; 1251 } 1252 1253 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1254 return (status); 1255 } 1256 1257 /* ARGSUSED */ 1258 int 1259 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1260 char *value, caddr_t cp) 1261 { 1262 char *end; 1263 uint32_t cfg_value; 1264 p_nxge_param_t pa = (p_nxge_param_t)cp; 1265 1266 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1267 1268 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1269 1270 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1271 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1272 return (EINVAL); 1273 } 1274 1275 if ((pa->value != cfg_value)) { 1276 pa->old_value = pa->value; 1277 pa->value = cfg_value; 1278 nxgep->intr_threshold = pa->value; 1279 } 1280 1281 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1282 return (0); 1283 } 1284 1285 /* ARGSUSED */ 1286 int 1287 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1288 char *value, caddr_t cp) 1289 { 1290 char *end; 1291 uint32_t cfg_value; 1292 p_nxge_param_t pa = (p_nxge_param_t)cp; 1293 1294 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1295 1296 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1297 1298 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1299 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1300 return (EINVAL); 1301 } 1302 1303 if ((pa->value != cfg_value)) { 1304 pa->old_value = pa->value; 1305 pa->value = cfg_value; 1306 nxgep->intr_timeout = pa->value; 1307 } 1308 1309 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1310 return (0); 1311 } 1312 1313 /* ARGSUSED */ 1314 static int 1315 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1316 mblk_t *mp, char *value, caddr_t cp) 1317 { 1318 char *end; 1319 uint32_t status = 0, cfg_value; 1320 p_nxge_param_t pa = (p_nxge_param_t)cp; 1321 uint32_t cfg_it = B_FALSE; 1322 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1323 p_nxge_hw_pt_cfg_t p_cfgp; 1324 uint32_t *val_ptr, *old_val_ptr; 1325 nxge_param_map_t *mac_map; 1326 p_nxge_class_pt_cfg_t p_class_cfgp; 1327 nxge_mv_cfg_t *mac_host_info; 1328 1329 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1330 1331 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1332 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1333 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1334 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1335 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1336 1337 /* 1338 * now do decoding 1339 */ 1340 mac_map = (nxge_param_map_t *)&cfg_value; 1341 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1342 cfg_value, mac_map->param_id, mac_map->map_to)); 1343 1344 if ((mac_map->param_id < p_cfgp->max_macs) && 1345 p_cfgp->grpids[mac_map->map_to]) { 1346 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1347 " nxge_param_set_mac_rdcgrp mapping" 1348 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1349 #if defined(__i386) 1350 val_ptr = (uint32_t *)(uint32_t)pa->value; 1351 #else 1352 val_ptr = (uint32_t *)pa->value; 1353 #endif 1354 #if defined(__i386) 1355 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1356 #else 1357 old_val_ptr = (uint32_t *)pa->old_value; 1358 #endif 1359 if (val_ptr[mac_map->param_id] != cfg_value) { 1360 old_val_ptr[mac_map->param_id] = 1361 val_ptr[mac_map->param_id]; 1362 val_ptr[mac_map->param_id] = cfg_value; 1363 mac_host_info[mac_map->param_id].mpr_npr = 1364 mac_map->pref; 1365 mac_host_info[mac_map->param_id].flag = 1; 1366 mac_host_info[mac_map->param_id].rdctbl = 1367 mac_map->map_to; 1368 cfg_it = B_TRUE; 1369 } 1370 } else { 1371 return (EINVAL); 1372 } 1373 1374 if (cfg_it == B_TRUE) { 1375 status = nxge_logical_mac_assign_rdc_table(nxgep, 1376 (uint8_t)mac_map->param_id); 1377 if (status != NXGE_OK) 1378 return (EINVAL); 1379 } 1380 1381 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1382 return (0); 1383 } 1384 1385 /* ARGSUSED */ 1386 static int 1387 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1388 mblk_t *mp, char *value, caddr_t cp) 1389 { 1390 char *end; 1391 uint32_t status = 0, cfg_value; 1392 p_nxge_param_t pa = (p_nxge_param_t)cp; 1393 uint32_t cfg_it = B_FALSE; 1394 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1395 p_nxge_hw_pt_cfg_t p_cfgp; 1396 uint32_t *val_ptr, *old_val_ptr; 1397 nxge_param_map_t *vmap, *old_map; 1398 p_nxge_class_pt_cfg_t p_class_cfgp; 1399 uint64_t cfgd_vlans; 1400 int i, inc = 0, cfg_position; 1401 nxge_mv_cfg_t *vlan_tbl; 1402 1403 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1404 1405 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1406 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1407 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1408 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1409 1410 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1411 1412 /* now do decoding */ 1413 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1414 NXGE_PARAM_ARRAY_CNT_SHIFT); 1415 1416 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1417 /* 1418 * for now, we process only upto max 1419 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1420 * In the future, we may want to expand 1421 * the storage array and continue 1422 */ 1423 return (EINVAL); 1424 } 1425 1426 vmap = (nxge_param_map_t *)&cfg_value; 1427 if ((vmap->param_id) && 1428 (vmap->param_id < NXGE_MAX_VLANS) && 1429 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1430 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1431 "nxge_param_set_vlan_rdcgrp mapping" 1432 " id %d grp %d", 1433 vmap->param_id, vmap->map_to)); 1434 #if defined(__i386) 1435 val_ptr = (uint32_t *)(uint32_t)pa->value; 1436 #else 1437 val_ptr = (uint32_t *)pa->value; 1438 #endif 1439 #if defined(__i386) 1440 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1441 #else 1442 old_val_ptr = (uint32_t *)pa->old_value; 1443 #endif 1444 1445 /* search to see if this vlan id is already configured */ 1446 for (i = 0; i < cfgd_vlans; i++) { 1447 old_map = (nxge_param_map_t *)&val_ptr[i]; 1448 if ((old_map->param_id == 0) || 1449 (vmap->param_id == old_map->param_id) || 1450 (vlan_tbl[vmap->param_id].flag)) { 1451 cfg_position = i; 1452 break; 1453 } 1454 } 1455 1456 if (cfgd_vlans == 0) { 1457 cfg_position = 0; 1458 inc++; 1459 } 1460 1461 if (i == cfgd_vlans) { 1462 cfg_position = i; 1463 inc++; 1464 } 1465 1466 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1467 "set_vlan_rdcgrp mapping" 1468 " i %d cfgd_vlans %llx position %d ", 1469 i, cfgd_vlans, cfg_position)); 1470 if (val_ptr[cfg_position] != cfg_value) { 1471 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1472 val_ptr[cfg_position] = cfg_value; 1473 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1474 vlan_tbl[vmap->param_id].flag = 1; 1475 vlan_tbl[vmap->param_id].rdctbl = 1476 vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 1477 cfg_it = B_TRUE; 1478 if (inc) { 1479 cfgd_vlans++; 1480 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1481 pa->type |= (cfgd_vlans << 1482 NXGE_PARAM_ARRAY_CNT_SHIFT); 1483 1484 } 1485 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1486 "after: param_set_vlan_rdcgrp " 1487 " cfg_vlans %llx position %d \n", 1488 cfgd_vlans, cfg_position)); 1489 } 1490 } else { 1491 return (EINVAL); 1492 } 1493 1494 if (cfg_it == B_TRUE) { 1495 status = nxge_fflp_config_vlan_table(nxgep, 1496 (uint16_t)vmap->param_id); 1497 if (status != NXGE_OK) 1498 return (EINVAL); 1499 } 1500 1501 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1502 return (0); 1503 } 1504 1505 /* ARGSUSED */ 1506 static int 1507 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1508 mblk_t *mp, caddr_t cp) 1509 { 1510 1511 uint_t print_len, buf_len; 1512 p_mblk_t np; 1513 int i; 1514 uint32_t *val_ptr; 1515 nxge_param_map_t *vmap; 1516 p_nxge_param_t pa = (p_nxge_param_t)cp; 1517 p_nxge_class_pt_cfg_t p_class_cfgp; 1518 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1519 p_nxge_hw_pt_cfg_t p_cfgp; 1520 uint64_t cfgd_vlans = 0; 1521 nxge_mv_cfg_t *vlan_tbl; 1522 int buff_alloc_size = 1523 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1524 1525 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1526 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1527 nxgep->function_num); 1528 1529 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1530 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1531 return (0); 1532 } 1533 1534 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1535 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1536 1537 buf_len = buff_alloc_size; 1538 mp->b_cont = np; 1539 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1540 NXGE_PARAM_ARRAY_CNT_SHIFT; 1541 1542 i = (int)cfgd_vlans; 1543 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1544 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1545 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1546 "Configured VLANs %d\n" 1547 "VLAN ID\t RDC GRP (Actual/Port)\t" 1548 " Prefernce\n", i); 1549 ((mblk_t *)np)->b_wptr += print_len; 1550 buf_len -= print_len; 1551 #if defined(__i386) 1552 val_ptr = (uint32_t *)(uint32_t)pa->value; 1553 #else 1554 val_ptr = (uint32_t *)pa->value; 1555 #endif 1556 1557 for (i = 0; i < cfgd_vlans; i++) { 1558 vmap = (nxge_param_map_t *)&val_ptr[i]; 1559 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1560 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1561 buf_len, 1562 " %d\t\t %d/%d\t\t %d\n", 1563 vmap->param_id, 1564 vlan_tbl[vmap->param_id].rdctbl, 1565 vlan_tbl[vmap->param_id].rdctbl - 1566 p_cfgp->def_mac_rxdma_grpid, 1567 vlan_tbl[vmap->param_id].mpr_npr); 1568 ((mblk_t *)np)->b_wptr += print_len; 1569 buf_len -= print_len; 1570 } 1571 } 1572 1573 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1574 return (0); 1575 } 1576 1577 /* ARGSUSED */ 1578 static int 1579 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1580 mblk_t *mp, caddr_t cp) 1581 { 1582 uint_t print_len, buf_len; 1583 p_mblk_t np; 1584 int i; 1585 p_nxge_class_pt_cfg_t p_class_cfgp; 1586 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1587 p_nxge_hw_pt_cfg_t p_cfgp; 1588 nxge_mv_cfg_t *mac_host_info; 1589 1590 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1591 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1592 (void) mi_mpprintf(mp, 1593 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1594 nxgep->function_num); 1595 1596 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1597 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1598 return (0); 1599 } 1600 1601 buf_len = buff_alloc_size; 1602 mp->b_cont = np; 1603 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1604 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1605 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1606 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1607 print_len = snprintf((char *)np->b_wptr, buf_len, 1608 "MAC ID\t RDC GRP (Actual/Port)\t" 1609 " Prefernce\n"); 1610 ((mblk_t *)np)->b_wptr += print_len; 1611 buf_len -= print_len; 1612 for (i = 0; i < p_cfgp->max_macs; i++) { 1613 if (mac_host_info[i].flag) { 1614 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1615 buf_len, 1616 " %d\t %d/%d\t\t %d\n", 1617 i, mac_host_info[i].rdctbl, 1618 mac_host_info[i].rdctbl - 1619 p_cfgp->def_mac_rxdma_grpid, 1620 mac_host_info[i].mpr_npr); 1621 ((mblk_t *)np)->b_wptr += print_len; 1622 buf_len -= print_len; 1623 } 1624 } 1625 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1626 "Done Info Dumping \n"); 1627 ((mblk_t *)np)->b_wptr += print_len; 1628 buf_len -= print_len; 1629 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1630 return (0); 1631 } 1632 1633 /* ARGSUSED */ 1634 static int 1635 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1636 mblk_t *mp, char *value, caddr_t cp) 1637 { 1638 uint32_t status = 0, cfg_value; 1639 p_nxge_param_t pa = (p_nxge_param_t)cp; 1640 uint32_t cfg_it = B_FALSE; 1641 char *end; 1642 1643 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1644 1645 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1646 if (pa->value != cfg_value) { 1647 pa->old_value = pa->value; 1648 pa->value = cfg_value; 1649 cfg_it = B_TRUE; 1650 } 1651 1652 if (cfg_it == B_TRUE) { 1653 if (pa->value) 1654 status = nxge_fflp_config_tcam_enable(nxgep); 1655 else 1656 status = nxge_fflp_config_tcam_disable(nxgep); 1657 if (status != NXGE_OK) 1658 return (EINVAL); 1659 } 1660 1661 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1662 return (0); 1663 } 1664 1665 /* ARGSUSED */ 1666 static int 1667 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1668 mblk_t *mp, char *value, caddr_t cp) 1669 { 1670 uint32_t status = 0, cfg_value; 1671 p_nxge_param_t pa = (p_nxge_param_t)cp; 1672 uint32_t cfg_it = B_FALSE; 1673 char *end; 1674 1675 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1676 1677 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1678 if (pa->value != cfg_value) { 1679 pa->old_value = pa->value; 1680 pa->value = cfg_value; 1681 cfg_it = B_TRUE; 1682 } 1683 1684 if (cfg_it == B_TRUE) { 1685 if (pa->value) 1686 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1687 else 1688 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1689 if (status != NXGE_OK) 1690 return (EINVAL); 1691 } 1692 1693 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1694 return (0); 1695 } 1696 1697 /* ARGSUSED */ 1698 static int 1699 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1700 mblk_t *mp, char *value, caddr_t cp) 1701 { 1702 char *end; 1703 uint32_t status = 0, cfg_value; 1704 p_nxge_param_t pa = (p_nxge_param_t)cp; 1705 uint32_t cfg_it = B_FALSE; 1706 1707 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1708 1709 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1710 if (pa->value != cfg_value) { 1711 pa->old_value = pa->value; 1712 pa->value = cfg_value; 1713 cfg_it = B_TRUE; 1714 } 1715 1716 if (cfg_it == B_TRUE) { 1717 if (pa->value) 1718 status = nxge_fflp_config_tcam_enable(nxgep); 1719 else 1720 status = nxge_fflp_config_tcam_disable(nxgep); 1721 if (status != NXGE_OK) 1722 return (EINVAL); 1723 } 1724 1725 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1726 return (0); 1727 } 1728 1729 /* ARGSUSED */ 1730 static int 1731 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1732 mblk_t *mp, char *value, caddr_t cp) 1733 { 1734 char *end; 1735 uint8_t ether_class; 1736 uint32_t status = 0, cfg_value; 1737 p_nxge_param_t pa = (p_nxge_param_t)cp; 1738 uint8_t cfg_it = B_FALSE; 1739 1740 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1741 1742 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1743 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1744 return (EINVAL); 1745 } 1746 1747 if (pa->value != cfg_value) { 1748 pa->old_value = pa->value; 1749 pa->value = cfg_value; 1750 cfg_it = B_TRUE; 1751 } 1752 1753 /* do the actual hw setup */ 1754 if (cfg_it == B_TRUE) { 1755 ether_class = mi_strtol(pa->name, &end, 10); 1756 #ifdef lint 1757 ether_class = ether_class; 1758 #endif 1759 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1760 } 1761 1762 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1763 return (status); 1764 } 1765 1766 /* ARGSUSED */ 1767 static int 1768 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1769 mblk_t *mp, char *value, caddr_t cp) 1770 { 1771 char *end; 1772 tcam_class_t class; 1773 uint32_t status, cfg_value; 1774 p_nxge_param_t pa = (p_nxge_param_t)cp; 1775 uint32_t cfg_it = B_FALSE; 1776 1777 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1778 1779 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1780 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1781 return (EINVAL); 1782 } 1783 1784 if (pa->value != cfg_value) { 1785 pa->old_value = pa->value; 1786 pa->value = cfg_value; 1787 cfg_it = B_TRUE; 1788 } 1789 1790 /* do the actual hw setup with cfg_value. */ 1791 if (cfg_it == B_TRUE) { 1792 class = mi_strtol(pa->name, &end, 10); 1793 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1794 } 1795 1796 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1797 return (status); 1798 } 1799 1800 /* ARGSUSED */ 1801 static int 1802 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1803 { 1804 int i; 1805 int class_instance = param_class_opt_ip_usr4; 1806 p_nxge_param_t param_arr; 1807 1808 param_arr = nxgep->param_arr; 1809 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1810 if (strcmp(param_arr[class_instance].name, name) == 0) 1811 return (i); 1812 class_instance++; 1813 } 1814 return (-1); 1815 } 1816 1817 /* ARGSUSED */ 1818 int 1819 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1820 mblk_t *mp, char *value, caddr_t cp) 1821 { 1822 char *end; 1823 uint32_t status, cfg_value; 1824 p_nxge_param_t pa = (p_nxge_param_t)cp; 1825 tcam_class_t class; 1826 uint32_t cfg_it = B_FALSE; 1827 1828 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1829 1830 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1831 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1832 return (EINVAL); 1833 } 1834 1835 if (pa->value != cfg_value) { 1836 pa->old_value = pa->value; 1837 pa->value = cfg_value; 1838 cfg_it = B_TRUE; 1839 } 1840 1841 if (cfg_it == B_TRUE) { 1842 /* do the actual hw setup */ 1843 class = nxge_class_name_2value(nxgep, pa->name); 1844 if (class == -1) 1845 return (EINVAL); 1846 1847 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1848 if (status != NXGE_OK) 1849 return (EINVAL); 1850 } 1851 1852 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1853 return (0); 1854 } 1855 1856 /* ARGSUSED */ 1857 static int 1858 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1859 mblk_t *mp, caddr_t cp) 1860 { 1861 uint32_t status, cfg_value; 1862 p_nxge_param_t pa = (p_nxge_param_t)cp; 1863 tcam_class_t class; 1864 1865 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1866 1867 /* do the actual hw setup */ 1868 class = nxge_class_name_2value(nxgep, pa->name); 1869 if (class == -1) 1870 return (EINVAL); 1871 1872 cfg_value = 0; 1873 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1874 if (status != NXGE_OK) 1875 return (EINVAL); 1876 1877 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1878 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1879 1880 pa->value = cfg_value; 1881 (void) mi_mpprintf(mp, "%x", cfg_value); 1882 1883 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1884 return (0); 1885 } 1886 1887 /* ARGSUSED */ 1888 static int 1889 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1890 mblk_t *mp, char *value, caddr_t cp) 1891 { 1892 char *end; 1893 uint32_t status, cfg_value; 1894 p_nxge_param_t pa = (p_nxge_param_t)cp; 1895 tcam_class_t class; 1896 uint32_t cfg_it = B_FALSE; 1897 1898 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1899 1900 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1901 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1902 return (EINVAL); 1903 } 1904 1905 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1906 "nxge_param_fflp_hash_init value %x", cfg_value)); 1907 1908 if (pa->value != cfg_value) { 1909 pa->old_value = pa->value; 1910 pa->value = cfg_value; 1911 cfg_it = B_TRUE; 1912 } 1913 1914 if (cfg_it == B_TRUE) { 1915 char *h_name; 1916 1917 /* do the actual hw setup */ 1918 h_name = pa->name; 1919 h_name++; 1920 class = mi_strtol(h_name, &end, 10); 1921 switch (class) { 1922 case 1: 1923 status = nxge_fflp_set_hash1(nxgep, 1924 (uint32_t)pa->value); 1925 break; 1926 case 2: 1927 status = nxge_fflp_set_hash2(nxgep, 1928 (uint16_t)pa->value); 1929 break; 1930 1931 default: 1932 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1933 " nxge_param_fflp_hash_init" 1934 " %s Wrong hash var %d", 1935 pa->name, class)); 1936 return (EINVAL); 1937 } 1938 if (status != NXGE_OK) 1939 return (EINVAL); 1940 } 1941 1942 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1943 return (0); 1944 } 1945 1946 /* ARGSUSED */ 1947 static int 1948 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1949 mblk_t *mp, char *value, caddr_t cp) 1950 { 1951 char *end; 1952 uint32_t status = 0, cfg_value; 1953 p_nxge_param_t pa = (p_nxge_param_t)cp; 1954 uint32_t cfg_it = B_FALSE; 1955 int rdc_grp; 1956 uint8_t real_rdc; 1957 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1958 p_nxge_hw_pt_cfg_t p_cfgp; 1959 p_nxge_rdc_grp_t rdc_grp_p; 1960 1961 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1962 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1963 1964 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1965 1966 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1967 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1968 return (EINVAL); 1969 } 1970 1971 if (cfg_value >= p_cfgp->max_rdcs) { 1972 return (EINVAL); 1973 } 1974 1975 if (pa->value != cfg_value) { 1976 pa->old_value = pa->value; 1977 pa->value = cfg_value; 1978 cfg_it = B_TRUE; 1979 } 1980 1981 if (cfg_it == B_TRUE) { 1982 char *grp_name; 1983 grp_name = pa->name; 1984 grp_name += strlen("default-grp"); 1985 rdc_grp = mi_strtol(grp_name, &end, 10); 1986 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1987 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1988 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1989 cfg_value) == B_FALSE) { 1990 pa->value = pa->old_value; 1991 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1992 " nxge_param_set_grp_rdc" 1993 " %d read %d actual %d outof range", 1994 rdc_grp, cfg_value, real_rdc)); 1995 return (EINVAL); 1996 } 1997 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1998 real_rdc); 1999 if (status != NXGE_OK) 2000 return (EINVAL); 2001 } 2002 2003 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 2004 return (0); 2005 } 2006 2007 /* ARGSUSED */ 2008 static int 2009 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 2010 mblk_t *mp, char *value, caddr_t cp) 2011 { 2012 char *end; 2013 uint32_t status = B_TRUE, cfg_value; 2014 p_nxge_param_t pa = (p_nxge_param_t)cp; 2015 uint32_t cfg_it = B_FALSE; 2016 2017 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2018 p_nxge_hw_pt_cfg_t p_cfgp; 2019 2020 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 2021 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2022 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2023 2024 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2025 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2026 return (EINVAL); 2027 } 2028 2029 if (pa->value != cfg_value) { 2030 if (cfg_value >= p_cfgp->max_rdcs) 2031 return (EINVAL); 2032 pa->old_value = pa->value; 2033 pa->value = cfg_value; 2034 cfg_it = B_TRUE; 2035 } 2036 2037 if (cfg_it == B_TRUE) { 2038 int rdc; 2039 if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2040 return (EINVAL); 2041 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2042 nxgep->function_num, rdc); 2043 if (status != NXGE_OK) 2044 return (EINVAL); 2045 } 2046 2047 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 2048 return (0); 2049 } 2050 2051 /* ARGSUSED */ 2052 static int 2053 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2054 mblk_t *mp, char *value, caddr_t cp) 2055 { 2056 char *end; 2057 uint32_t status = 0; 2058 uint64_t cfg_value = 0; 2059 p_nxge_param_t pa = (p_nxge_param_t)cp; 2060 uint32_t cfg_it = B_FALSE; 2061 2062 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 2063 cfg_value = mi_strtol(value, &end, BASE_HEX); 2064 2065 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2066 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2067 " nxge_param_set_nxge_debug_flag" 2068 " outof range %llx", cfg_value)); 2069 return (EINVAL); 2070 } 2071 if (pa->value != cfg_value) { 2072 pa->old_value = pa->value; 2073 pa->value = cfg_value; 2074 cfg_it = B_TRUE; 2075 } 2076 2077 if (cfg_it == B_TRUE) { 2078 nxgep->nxge_debug_level = pa->value; 2079 } 2080 2081 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 2082 return (status); 2083 } 2084 2085 /* ARGSUSED */ 2086 static int 2087 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2088 { 2089 int status = 0; 2090 p_nxge_param_t pa = (p_nxge_param_t)cp; 2091 2092 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 2093 2094 if (pa->value > 0xffffffff) 2095 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2096 (int)(pa->value & 0xffffffff)); 2097 else 2098 (void) mi_mpprintf(mp, "%x", (int)pa->value); 2099 2100 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 2101 return (status); 2102 } 2103 2104 /* ARGSUSED */ 2105 static int 2106 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2107 mblk_t *mp, char *value, caddr_t cp) 2108 { 2109 char *end; 2110 uint32_t status = 0; 2111 uint64_t cfg_value = 0; 2112 p_nxge_param_t pa; 2113 uint32_t cfg_it = B_FALSE; 2114 2115 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 2116 cfg_value = mi_strtol(value, &end, BASE_HEX); 2117 pa = (p_nxge_param_t)cp; 2118 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2119 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2120 " outof range %llx", cfg_value)); 2121 return (EINVAL); 2122 } 2123 if (pa->value != cfg_value) { 2124 pa->old_value = pa->value; 2125 pa->value = cfg_value; 2126 cfg_it = B_TRUE; 2127 } 2128 2129 if (cfg_it == B_TRUE) { 2130 npi_debug_level = pa->value; 2131 } 2132 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2133 return (status); 2134 } 2135 2136 /* ARGSUSED */ 2137 static int 2138 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2139 { 2140 nxge_grp_set_t *set = &nxgep->rx_set; 2141 int rdc; 2142 2143 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2144 2145 if (!isLDOMguest(nxgep)) 2146 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2147 2148 for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2149 if ((1 << rdc) & set->owned.map) { 2150 (void) nxge_dump_rxdma_channel(nxgep, rdc); 2151 } 2152 } 2153 2154 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2155 return (0); 2156 } 2157 2158 /* ARGSUSED */ 2159 static int 2160 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2161 { 2162 nxge_grp_set_t *set = &nxgep->tx_set; 2163 int tdc; 2164 2165 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2166 2167 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2168 if ((1 << tdc) & set->owned.map) { 2169 (void) nxge_txdma_regs_dump(nxgep, tdc); 2170 } 2171 } 2172 2173 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2174 return (0); 2175 } 2176 2177 /* ARGSUSED */ 2178 static int 2179 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2180 { 2181 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2182 2183 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2184 2185 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2186 return (0); 2187 } 2188 2189 /* ARGSUSED */ 2190 static int 2191 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2192 { 2193 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2194 2195 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2196 nxgep->function_num); 2197 2198 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2199 return (0); 2200 } 2201 2202 /* ARGSUSED */ 2203 static int 2204 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2205 { 2206 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2207 2208 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2209 nxgep->function_num); 2210 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2211 return (0); 2212 } 2213 2214 /* ARGSUSED */ 2215 static int 2216 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2217 { 2218 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2219 2220 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2221 2222 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2223 return (0); 2224 } 2225 2226 /* ARGSUSED */ 2227 static int 2228 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2229 { 2230 uint8_t table; 2231 2232 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2233 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2234 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2235 table); 2236 } 2237 2238 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2239 return (0); 2240 } 2241 2242 typedef struct block_info { 2243 char *name; 2244 uint32_t offset; 2245 } block_info_t; 2246 2247 block_info_t reg_block[] = { 2248 {"PIO", PIO}, 2249 {"FZC_PIO", FZC_PIO}, 2250 {"FZC_XMAC", FZC_MAC}, 2251 {"FZC_IPP", FZC_IPP}, 2252 {"FFLP", FFLP}, 2253 {"FZC_FFLP", FZC_FFLP}, 2254 {"PIO_VADDR", PIO_VADDR}, 2255 {"ZCP", ZCP}, 2256 {"FZC_ZCP", FZC_ZCP}, 2257 {"DMC", DMC}, 2258 {"FZC_DMC", FZC_DMC}, 2259 {"TXC", TXC}, 2260 {"FZC_TXC", FZC_TXC}, 2261 {"PIO_LDSV", PIO_LDSV}, 2262 {"PIO_LDGIM", PIO_LDGIM}, 2263 {"PIO_IMASK0", PIO_IMASK0}, 2264 {"PIO_IMASK1", PIO_IMASK1}, 2265 {"FZC_PROM", FZC_PROM}, 2266 {"END", ALL_FF_32}, 2267 }; 2268 2269 /* ARGSUSED */ 2270 static int 2271 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2272 { 2273 uint_t print_len, buf_len; 2274 p_mblk_t np; 2275 int rdc, tdc, block; 2276 uint64_t base; 2277 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2278 p_nxge_hw_pt_cfg_t p_cfgp; 2279 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2280 p_tx_ring_t *tx_rings; 2281 p_rx_rcr_rings_t rx_rcr_rings; 2282 p_rx_rcr_ring_t *rcr_rings; 2283 p_rx_rbr_rings_t rx_rbr_rings; 2284 p_rx_rbr_ring_t *rbr_rings; 2285 2286 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2287 "==> nxge_param_dump_ptrs")); 2288 2289 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2290 nxgep->function_num); 2291 2292 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2293 /* The following may work even if we cannot get a large buf. */ 2294 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2295 return (0); 2296 } 2297 2298 buf_len = buff_alloc_size; 2299 mp->b_cont = np; 2300 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2301 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2302 2303 rx_rcr_rings = nxgep->rx_rcr_rings; 2304 rcr_rings = rx_rcr_rings->rcr_rings; 2305 rx_rbr_rings = nxgep->rx_rbr_rings; 2306 rbr_rings = rx_rbr_rings->rbr_rings; 2307 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2308 "nxgep (nxge_t) $%p\n" 2309 "dev_regs (dev_regs_t) $%p\n", 2310 nxgep, nxgep->dev_regs); 2311 2312 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2313 2314 /* do register pointers */ 2315 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2316 "reg base (npi_reg_ptr_t) $%p\t " 2317 "pci reg (npi_reg_ptr_t) $%p\n", 2318 nxgep->dev_regs->nxge_regp, 2319 nxgep->dev_regs->nxge_pciregp); 2320 2321 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2322 2323 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2324 "\nBlock \t Offset \n"); 2325 2326 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2327 block = 0; 2328 #if defined(__i386) 2329 base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2330 #else 2331 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2332 #endif 2333 while (reg_block[block].offset != ALL_FF_32) { 2334 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2335 "%9s\t 0x%llx\n", 2336 reg_block[block].name, 2337 (unsigned long long)(reg_block[block].offset + base)); 2338 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2339 block++; 2340 } 2341 2342 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2343 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2344 "rbrp (rx_rbr_ring_t)\n"); 2345 2346 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2347 2348 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2349 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2350 " %d\t $%p\t\t $%p\n", 2351 rdc, rcr_rings[rdc], 2352 rbr_rings[rdc]); 2353 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2354 } 2355 2356 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2357 "\nTDC\t tdcp (tx_ring_t)\n"); 2358 2359 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2360 tx_rings = nxgep->tx_rings->rings; 2361 for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 2362 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2363 " %d\t $%p\n", tdc, tx_rings[tdc]); 2364 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2365 } 2366 2367 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2368 2369 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2370 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2371 return (0); 2372 } 2373 2374 /* 2375 * Load 'name' into the named dispatch table pointed to by 'ndp'. 2376 * 'ndp' should be the address of a char pointer cell. If the table 2377 * does not exist (*ndp == 0), a new table is allocated and 'ndp' 2378 * is stuffed. If there is not enough space in the table for a new 2379 * entry, more space is allocated. 2380 */ 2381 /* ARGSUSED */ 2382 boolean_t 2383 nxge_nd_load(caddr_t *pparam, char *name, 2384 pfi_t get_pfi, pfi_t set_pfi, caddr_t data) 2385 { 2386 ND *nd; 2387 NDE *nde; 2388 2389 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " ==> nxge_nd_load")); 2390 if (!pparam) 2391 return (B_FALSE); 2392 2393 if ((nd = (ND *)*pparam) == NULL) { 2394 if ((nd = (ND *)KMEM_ZALLOC(sizeof (ND), KM_NOSLEEP)) == NULL) 2395 return (B_FALSE); 2396 *pparam = (caddr_t)nd; 2397 } 2398 2399 if (nd->nd_tbl) { 2400 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2401 if (strcmp(name, nde->nde_name) == 0) 2402 goto fill_it; 2403 } 2404 } 2405 2406 if (nd->nd_free_count <= 1) { 2407 if ((nde = (NDE *)KMEM_ZALLOC(nd->nd_size + 2408 NDE_ALLOC_SIZE, KM_NOSLEEP)) == NULL) 2409 return (B_FALSE); 2410 nd->nd_free_count += NDE_ALLOC_COUNT; 2411 if (nd->nd_tbl) { 2412 bcopy((char *)nd->nd_tbl, (char *)nde, nd->nd_size); 2413 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2414 } else { 2415 nd->nd_free_count--; 2416 nde->nde_name = "?"; 2417 nde->nde_get_pfi = nxge_nd_get_names; 2418 nde->nde_set_pfi = nxge_set_default; 2419 } 2420 nde->nde_data = (caddr_t)nd; 2421 nd->nd_tbl = nde; 2422 nd->nd_size += NDE_ALLOC_SIZE; 2423 } 2424 for (nde = nd->nd_tbl; nde->nde_name; nde++) 2425 noop; 2426 nd->nd_free_count--; 2427 fill_it: 2428 nde->nde_name = name; 2429 nde->nde_get_pfi = get_pfi; 2430 nde->nde_set_pfi = set_pfi; 2431 nde->nde_data = data; 2432 NXGE_DEBUG_MSG((NULL, NDD2_CTL, " <== nxge_nd_load")); 2433 2434 return (B_TRUE); 2435 } 2436 2437 /* 2438 * Free the table pointed to by 'pparam' 2439 */ 2440 void 2441 nxge_nd_free(caddr_t *pparam) 2442 { 2443 ND *nd; 2444 2445 if ((nd = (ND *)*pparam) != NULL) { 2446 if (nd->nd_tbl) 2447 KMEM_FREE((char *)nd->nd_tbl, nd->nd_size); 2448 KMEM_FREE((char *)nd, sizeof (ND)); 2449 *pparam = nil(caddr_t); 2450 } 2451 } 2452 2453 int 2454 nxge_nd_getset(p_nxge_t nxgep, queue_t *q, caddr_t param, p_mblk_t mp) 2455 { 2456 int err; 2457 IOCP iocp; 2458 p_mblk_t mp1, mp2; 2459 ND *nd; 2460 NDE *nde; 2461 char *valp; 2462 size_t avail; 2463 2464 if (!param) { 2465 return (B_FALSE); 2466 } 2467 2468 nd = (ND *)param; 2469 iocp = (IOCP)mp->b_rptr; 2470 if ((iocp->ioc_count == 0) || !(mp1 = mp->b_cont)) { 2471 mp->b_datap->db_type = M_IOCACK; 2472 iocp->ioc_count = 0; 2473 iocp->ioc_error = EINVAL; 2474 return (B_FALSE); 2475 } 2476 2477 /* 2478 * NOTE - logic throughout nd_xxx assumes single data block for ioctl. 2479 * However, existing code sends in some big buffers. 2480 */ 2481 avail = iocp->ioc_count; 2482 if (mp1->b_cont) { 2483 freemsg(mp1->b_cont); 2484 mp1->b_cont = NULL; 2485 } 2486 2487 mp1->b_datap->db_lim[-1] = '\0'; /* Force null termination */ 2488 for (valp = (char *)mp1->b_rptr; *valp != '\0'; valp++) { 2489 if (*valp == '-') 2490 *valp = '_'; 2491 } 2492 2493 valp = (char *)mp1->b_rptr; 2494 2495 for (nde = nd->nd_tbl; /* */; nde++) { 2496 if (!nde->nde_name) 2497 return (B_FALSE); 2498 if (strcmp(nde->nde_name, valp) == 0) 2499 break; 2500 } 2501 err = EINVAL; 2502 while (*valp++) 2503 noop; 2504 if (!*valp || valp >= (char *)mp1->b_wptr) 2505 valp = nilp(char); 2506 switch (iocp->ioc_cmd) { 2507 case ND_GET: 2508 /* 2509 * (temporary) hack: "*valp" is size of user buffer for 2510 * copyout. If result of action routine is too big, free 2511 * excess and return ioc_rval as buffer size needed. 2512 * Return as many mblocks as will fit, free the rest. For 2513 * backward compatibility, assume size of original ioctl 2514 * buffer if "*valp" bad or not given. 2515 */ 2516 if (valp) 2517 avail = mi_strtol(valp, (char **)0, 10); 2518 /* 2519 * We overwrite the name/value with the reply data 2520 */ 2521 mp2 = mp1; 2522 while (mp2) { 2523 mp2->b_wptr = mp2->b_rptr; 2524 mp2 = mp2->b_cont; 2525 } 2526 2527 if (nde->nde_get_pfi) { 2528 err = (*nde->nde_get_pfi)(nxgep, q, mp1, nde->nde_data); 2529 } 2530 2531 if (!err) { 2532 size_t size_out = 0; 2533 ssize_t excess; 2534 2535 iocp->ioc_rval = 0; 2536 2537 /* Tack on the null */ 2538 err = nxge_mk_mblk_tail_space(mp1, &mp2, 1); 2539 if (!err) { 2540 *mp2->b_wptr++ = '\0'; 2541 size_out = msgdsize(mp1); 2542 excess = size_out - avail; 2543 if (excess > 0) { 2544 iocp->ioc_rval = (int)size_out; 2545 size_out -= excess; 2546 (void) adjmsg(mp1, -(excess + 1)); 2547 err = nxge_mk_mblk_tail_space( 2548 mp1, &mp2, 1); 2549 if (!err) 2550 *mp2->b_wptr++ = '\0'; 2551 else 2552 size_out = 0; 2553 } 2554 } else 2555 size_out = 0; 2556 iocp->ioc_count = size_out; 2557 } 2558 break; 2559 2560 case ND_SET: 2561 if (valp) { 2562 if (nde->nde_set_pfi) { 2563 err = (*nde->nde_set_pfi)(nxgep, q, mp1, valp, 2564 nde->nde_data); 2565 iocp->ioc_count = 0; 2566 freemsg(mp1); 2567 mp->b_cont = NULL; 2568 } 2569 } 2570 2571 nxge_param_sync(nxgep); 2572 2573 break; 2574 2575 default: 2576 break; 2577 } 2578 iocp->ioc_error = err; 2579 mp->b_datap->db_type = M_IOCACK; 2580 return (B_TRUE); 2581 } 2582 2583 /* ARGSUSED */ 2584 int 2585 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2586 { 2587 ND *nd; 2588 NDE *nde; 2589 char *rwtag; 2590 boolean_t get_ok, set_ok; 2591 size_t param_len; 2592 int status = 0; 2593 2594 nd = (ND *)param; 2595 if (!nd) 2596 return (ENOENT); 2597 2598 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2599 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2600 (nde->nde_get_pfi != NULL); 2601 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2602 (nde->nde_set_pfi != NULL); 2603 if (get_ok) { 2604 if (set_ok) 2605 rwtag = "read and write"; 2606 else 2607 rwtag = "read only"; 2608 } else if (set_ok) 2609 rwtag = "write only"; 2610 else { 2611 continue; 2612 } 2613 param_len = strlen(rwtag); 2614 param_len += strlen(nde->nde_name); 2615 param_len += 4; 2616 2617 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2618 } 2619 return (status); 2620 } 2621 2622 /* ARGSUSED */ 2623 int 2624 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2625 { 2626 return (EACCES); 2627 } 2628 2629 /* ARGSUSED */ 2630 int 2631 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2632 caddr_t data) 2633 { 2634 return (EACCES); 2635 } 2636 2637 void 2638 nxge_param_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2639 { 2640 int cmd; 2641 int status = B_FALSE; 2642 2643 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_ioctl")); 2644 cmd = iocp->ioc_cmd; 2645 2646 switch (cmd) { 2647 default: 2648 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2649 "nxge_param_ioctl: bad cmd 0x%0x", cmd)); 2650 break; 2651 2652 case ND_GET: 2653 case ND_SET: 2654 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2655 "nxge_param_ioctl: cmd 0x%0x", cmd)); 2656 if (!nxge_nd_getset(nxgep, wq, nxgep->param_list, mp)) { 2657 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2658 "false ret from nxge_nd_getset")); 2659 break; 2660 } 2661 status = B_TRUE; 2662 break; 2663 } 2664 2665 if (status) { 2666 qreply(wq, mp); 2667 } else { 2668 miocnak(wq, mp, 0, EINVAL); 2669 } 2670 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_ioctl")); 2671 } 2672 2673 boolean_t 2674 nxge_param_link_update(p_nxge_t nxgep) 2675 { 2676 p_nxge_param_t param_arr; 2677 nxge_param_index_t i; 2678 boolean_t update_xcvr; 2679 boolean_t update_dev; 2680 int instance; 2681 boolean_t status = B_TRUE; 2682 2683 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 2684 2685 param_arr = nxgep->param_arr; 2686 instance = nxgep->instance; 2687 update_xcvr = B_FALSE; 2688 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2689 update_xcvr |= param_arr[i].value; 2690 } 2691 2692 if (update_xcvr) { 2693 update_xcvr = B_FALSE; 2694 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2695 update_xcvr |= 2696 (param_arr[i].value != param_arr[i].old_value); 2697 param_arr[i].old_value = param_arr[i].value; 2698 } 2699 if (update_xcvr) { 2700 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2701 "==> nxge_param_link_update: update xcvr")); 2702 RW_ENTER_WRITER(&nxgep->filter_lock); 2703 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2704 (void) nxge_link_init(nxgep); 2705 (void) nxge_mac_init(nxgep); 2706 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2707 RW_EXIT(&nxgep->filter_lock); 2708 } 2709 } else { 2710 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2711 " no link capabilities.", instance); 2712 cmn_err(CE_WARN, " Restoring previous setting."); 2713 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2714 param_arr[i].value = param_arr[i].old_value; 2715 } 2716 2717 update_dev = B_FALSE; 2718 2719 if (update_dev) { 2720 RW_ENTER_WRITER(&nxgep->filter_lock); 2721 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2722 "==> nxge_param_link_update: update dev")); 2723 (void) nxge_rx_mac_disable(nxgep); 2724 (void) nxge_tx_mac_disable(nxgep); 2725 (void) nxge_tx_mac_enable(nxgep); 2726 (void) nxge_rx_mac_enable(nxgep); 2727 RW_EXIT(&nxgep->filter_lock); 2728 } 2729 2730 nxge_param_hw_update_exit: 2731 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2732 "<== nxge_param_link_update status = 0x%08x", status)); 2733 return (status); 2734 } 2735 2736 /* 2737 * synchronize the adv* and en* parameters. 2738 * 2739 * See comments in <sys/dld.h> for details of the *_en_* 2740 * parameters. The usage of ndd for setting adv parameters will 2741 * synchronize all the en parameters with the nxge parameters, 2742 * implicitly disabling any settings made via dladm. 2743 */ 2744 static void 2745 nxge_param_sync(p_nxge_t nxgep) 2746 { 2747 p_nxge_param_t param_arr; 2748 param_arr = nxgep->param_arr; 2749 2750 nxgep->param_en_pause = param_arr[param_anar_pause].value; 2751 nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 2752 nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 2753 nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 2754 } 2755 2756 /* ARGSUSED */ 2757 int 2758 nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 2759 { 2760 uint32_t status, cfg_value; 2761 p_nxge_param_t pa = (p_nxge_param_t)cp; 2762 tcam_class_t class; 2763 2764 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 2765 2766 /* do the actual hw setup */ 2767 class = nxge_class_name_2value(nxgep, pa->name); 2768 if (class == -1) 2769 return (EINVAL); 2770 2771 cfg_value = 0; 2772 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 2773 if (status != NXGE_OK) 2774 return (EINVAL); 2775 2776 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2777 "nxge_param_get_ip_opt_get %x ", cfg_value)); 2778 2779 pa->value = cfg_value; 2780 2781 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 2782 return (0); 2783 } 2784