1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 #include <sys/nxge/nxge_hio.h> 30 31 #include <inet/common.h> 32 #include <inet/mi.h> 33 #include <inet/nd.h> 34 35 extern uint64_t npi_debug_level; 36 37 #define NXGE_PARAM_MAC_RW \ 38 NXGE_PARAM_RW | NXGE_PARAM_MAC | \ 39 NXGE_PARAM_NDD_WR_OK | NXGE_PARAM_READ_PROP 40 41 #define NXGE_PARAM_MAC_DONT_SHOW \ 42 NXGE_PARAM_RW | NXGE_PARAM_MAC | NXGE_PARAM_DONT_SHOW 43 44 #define NXGE_PARAM_RXDMA_RW \ 45 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_NDD_WR_OK | \ 46 NXGE_PARAM_READ_PROP 47 48 #define NXGE_PARAM_RXDMA_RWC \ 49 NXGE_PARAM_RWP | NXGE_PARAM_RXDMA | NXGE_PARAM_INIT_ONLY | \ 50 NXGE_PARAM_READ_PROP 51 52 #define NXGE_PARAM_L2CLASS_CFG \ 53 NXGE_PARAM_RW | NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_READ_PROP | \ 54 NXGE_PARAM_NDD_WR_OK 55 56 #define NXGE_PARAM_CLASS_RWS \ 57 NXGE_PARAM_RWS | NXGE_PARAM_READ_PROP 58 59 #define NXGE_PARAM_ARRAY_INIT_SIZE 0x20ULL 60 61 #define SET_RX_INTR_TIME_DISABLE 0 62 #define SET_RX_INTR_TIME_ENABLE 1 63 #define SET_RX_INTR_PKTS 2 64 65 #define BASE_ANY 0 66 #define BASE_BINARY 2 67 #define BASE_HEX 16 68 #define BASE_DECIMAL 10 69 #define ALL_FF_64 0xFFFFFFFFFFFFFFFFULL 70 #define ALL_FF_32 0xFFFFFFFFUL 71 72 #define NXGE_NDD_INFODUMP_BUFF_SIZE 2048 /* is 2k enough? */ 73 #define NXGE_NDD_INFODUMP_BUFF_8K 8192 74 #define NXGE_NDD_INFODUMP_BUFF_16K 0x2000 75 #define NXGE_NDD_INFODUMP_BUFF_64K 0x8000 76 77 #define PARAM_OUTOF_RANGE(vptr, eptr, rval, pa) \ 78 ((vptr == eptr) || (rval < pa->minimum) || (rval > pa->maximum)) 79 80 #define ADVANCE_PRINT_BUFFER(pmp, plen, rlen) { \ 81 ((mblk_t *)pmp)->b_wptr += plen; \ 82 rlen -= plen; \ 83 } 84 85 int nxge_param_set_mac(p_nxge_t, queue_t *, 86 mblk_t *, char *, caddr_t); 87 static int nxge_param_set_port_rdc(p_nxge_t, queue_t *, 88 mblk_t *, char *, caddr_t); 89 static int nxge_param_set_grp_rdc(p_nxge_t, queue_t *, 90 mblk_t *, char *, caddr_t); 91 static int nxge_param_set_ether_usr(p_nxge_t, 92 queue_t *, mblk_t *, char *, caddr_t); 93 static int nxge_param_set_ip_usr(p_nxge_t, 94 queue_t *, mblk_t *, char *, caddr_t); 95 static int nxge_param_set_vlan_rdcgrp(p_nxge_t, 96 queue_t *, mblk_t *, char *, caddr_t); 97 static int nxge_param_set_mac_rdcgrp(p_nxge_t, 98 queue_t *, mblk_t *, char *, caddr_t); 99 static int nxge_param_fflp_hash_init(p_nxge_t, 100 queue_t *, mblk_t *, char *, caddr_t); 101 static int nxge_param_llc_snap_enable(p_nxge_t, queue_t *, 102 mblk_t *, char *, caddr_t); 103 static int nxge_param_hash_lookup_enable(p_nxge_t, queue_t *, 104 mblk_t *, char *, caddr_t); 105 static int nxge_param_tcam_enable(p_nxge_t, queue_t *, 106 mblk_t *, char *, caddr_t); 107 static int nxge_param_get_fw_ver(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 108 static int nxge_param_get_port_mode(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 109 static int nxge_param_get_rxdma_info(p_nxge_t, queue_t *q, 110 p_mblk_t, caddr_t); 111 static int nxge_param_get_txdma_info(p_nxge_t, queue_t *q, 112 p_mblk_t, caddr_t); 113 static int nxge_param_get_vlan_rdcgrp(p_nxge_t, queue_t *, 114 p_mblk_t, caddr_t); 115 static int nxge_param_get_mac_rdcgrp(p_nxge_t, queue_t *, 116 p_mblk_t, caddr_t); 117 static int nxge_param_get_rxdma_rdcgrp_info(p_nxge_t, queue_t *, 118 p_mblk_t, caddr_t); 119 static int nxge_param_get_ip_opt(p_nxge_t, queue_t *, mblk_t *, caddr_t); 120 static int nxge_param_get_mac(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 121 static int nxge_param_get_debug_flag(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 122 static int nxge_param_set_nxge_debug_flag(p_nxge_t, queue_t *, mblk_t *, 123 char *, caddr_t); 124 static int nxge_param_set_npi_debug_flag(p_nxge_t, 125 queue_t *, mblk_t *, char *, caddr_t); 126 static int nxge_param_dump_rdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 127 static int nxge_param_dump_tdc(p_nxge_t, queue_t *q, p_mblk_t, caddr_t); 128 static int nxge_param_dump_mac_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 129 static int nxge_param_dump_ipp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 130 static int nxge_param_dump_fflp_regs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 131 static int nxge_param_dump_vlan_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 132 static int nxge_param_dump_rdc_table(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 133 static int nxge_param_dump_ptrs(p_nxge_t, queue_t *, p_mblk_t, caddr_t); 134 static void nxge_param_sync(p_nxge_t); 135 136 /* 137 * Global array of Neptune changable parameters. 138 * This array is initialized to correspond to the default 139 * Neptune 4 port configuration. This array would be copied 140 * into each port's parameter structure and modifed per 141 * fcode and nxge.conf configuration. Later, the parameters are 142 * exported to ndd to display and run-time configuration (at least 143 * some of them). 144 * 145 */ 146 147 static nxge_param_t nxge_param_arr[] = { 148 /* 149 * min max value old hw-name conf-name 150 */ 151 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 152 0, 999, 1000, 0, "instance", "instance"}, 153 154 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 155 0, 999, 1000, 0, "main-instance", "main_instance"}, 156 157 { nxge_param_get_generic, NULL, NXGE_PARAM_READ, 158 0, 3, 0, 0, "function-number", "function_number"}, 159 160 /* Partition Id */ 161 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 162 0, 8, 0, 0, "partition-id", "partition_id"}, 163 164 /* Read Write Permission Mode */ 165 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 166 0, 2, 0, 0, "read-write-mode", "read_write_mode"}, 167 168 { nxge_param_get_fw_ver, NULL, NXGE_PARAM_READ, 169 0, 32, 0, 0, "version", "fw_version"}, 170 171 { nxge_param_get_port_mode, NULL, NXGE_PARAM_READ, 172 0, 32, 0, 0, "port-mode", "port_mode"}, 173 174 /* hw cfg types */ 175 /* control the DMA config of Neptune/NIU */ 176 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 177 CFG_DEFAULT, CFG_CUSTOM, CFG_DEFAULT, CFG_DEFAULT, 178 "niu-cfg-type", "niu_cfg_type"}, 179 180 /* control the TXDMA config of the Port controlled by tx-quick-cfg */ 181 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 182 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 183 "tx-qcfg-type", "tx_qcfg_type"}, 184 185 /* control the RXDMA config of the Port controlled by rx-quick-cfg */ 186 { nxge_param_get_generic, NULL, NXGE_PARAM_DONT_SHOW, 187 CFG_DEFAULT, CFG_CUSTOM, CFG_NOT_SPECIFIED, CFG_DEFAULT, 188 "rx-qcfg-type", "rx_qcfg_type"}, 189 190 { nxge_param_get_mac, nxge_param_set_mac, 191 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 192 0, 1, 0, 0, "master-cfg-enable", "master_cfg_enable"}, 193 194 { nxge_param_get_mac, nxge_param_set_mac, 195 NXGE_PARAM_DONT_SHOW, 196 0, 1, 0, 0, "master-cfg-value", "master_cfg_value"}, 197 198 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 199 0, 1, 1, 1, "adv-autoneg-cap", "adv_autoneg_cap"}, 200 201 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 202 0, 1, 1, 1, "adv-10gfdx-cap", "adv_10gfdx_cap"}, 203 204 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 205 0, 1, 0, 0, "adv-10ghdx-cap", "adv_10ghdx_cap"}, 206 207 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 208 0, 1, 1, 1, "adv-1000fdx-cap", "adv_1000fdx_cap"}, 209 210 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 211 0, 1, 0, 0, "adv-1000hdx-cap", "adv_1000hdx_cap"}, 212 213 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 214 0, 1, 0, 0, "adv-100T4-cap", "adv_100T4_cap"}, 215 216 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 217 0, 1, 1, 1, "adv-100fdx-cap", "adv_100fdx_cap"}, 218 219 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 220 0, 1, 0, 0, "adv-100hdx-cap", "adv_100hdx_cap"}, 221 222 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 223 0, 1, 1, 1, "adv-10fdx-cap", "adv_10fdx_cap"}, 224 225 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_DONT_SHOW, 226 0, 1, 0, 0, "adv-10hdx-cap", "adv_10hdx_cap"}, 227 228 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 229 0, 1, 0, 0, "adv-asmpause-cap", "adv_asmpause_cap"}, 230 231 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 232 0, 1, 0, 0, "adv-pause-cap", "adv_pause_cap"}, 233 234 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 235 0, 1, 0, 0, "use-int-xcvr", "use_int_xcvr"}, 236 237 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 238 0, 1, 1, 1, "enable-ipg0", "enable_ipg0"}, 239 240 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 241 0, 255, 8, 8, "ipg0", "ipg0"}, 242 243 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 244 0, 255, 8, 8, "ipg1", "ipg1"}, 245 246 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_DONT_SHOW, 247 0, 255, 4, 4, "ipg2", "ipg2"}, 248 249 { nxge_param_get_mac, nxge_param_set_mac, NXGE_PARAM_MAC_RW, 250 0, 1, 0, 0, "accept-jumbo", "accept_jumbo"}, 251 252 /* Transmit DMA channels */ 253 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 254 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 255 0, 3, 0, 0, "tx-dma-weight", "tx_dma_weight"}, 256 257 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 258 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 259 0, 31, 0, 0, "tx-dma-channels-begin", "tx_dma_channels_begin"}, 260 261 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 262 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 263 0, 32, 0, 0, "tx-dma-channels", "tx_dma_channels"}, 264 { nxge_param_get_txdma_info, NULL, 265 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 266 0, 32, 0, 0, "tx-dma-info", "tx_dma_info"}, 267 268 /* Receive DMA channels */ 269 { nxge_param_get_generic, NULL, 270 NXGE_PARAM_READ | NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 271 0, 31, 0, 0, "rx-dma-channels-begin", "rx_dma_channels_begin"}, 272 273 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 274 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 275 0, 32, 0, 0, "rx-dma-channels", "rx_dma_channels"}, 276 277 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 278 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 279 0, 65535, PT_DRR_WT_DEFAULT_10G, 0, 280 "rx-drr-weight", "rx_drr_weight"}, 281 282 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | 283 NXGE_PARAM_READ_PROP | NXGE_PARAM_DONT_SHOW, 284 0, 1, 1, 0, "rx-full-header", "rx_full_header"}, 285 286 { nxge_param_get_rxdma_info, NULL, NXGE_PARAM_READ | 287 NXGE_PARAM_DONT_SHOW, 288 0, 32, 0, 0, "rx-dma-info", "rx_dma_info"}, 289 290 { nxge_param_get_rxdma_info, NULL, 291 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 292 NXGE_RBR_RBB_MIN, NXGE_RBR_RBB_MAX, NXGE_RBR_RBB_DEFAULT, 0, 293 "rx-rbr-size", "rx_rbr_size"}, 294 295 { nxge_param_get_rxdma_info, NULL, 296 NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 297 NXGE_RCR_MIN, NXGE_RCR_MAX, NXGE_RCR_DEFAULT, 0, 298 "rx-rcr-size", "rx_rcr_size"}, 299 300 { nxge_param_get_generic, nxge_param_set_port_rdc, 301 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 302 0, 15, 0, 0, "default-port-rdc", "default_port_rdc"}, 303 304 { nxge_param_get_generic, nxge_param_rx_intr_time, NXGE_PARAM_RXDMA_RW, 305 NXGE_RDC_RCR_TIMEOUT_MIN, NXGE_RDC_RCR_TIMEOUT_MAX, 306 RXDMA_RCR_TO_DEFAULT, 0, "rxdma-intr-time", "rxdma_intr_time"}, 307 308 { nxge_param_get_generic, nxge_param_rx_intr_pkts, NXGE_PARAM_RXDMA_RW, 309 NXGE_RDC_RCR_THRESHOLD_MIN, NXGE_RDC_RCR_THRESHOLD_MAX, 310 RXDMA_RCR_PTHRES_DEFAULT, 0, 311 "rxdma-intr-pkts", "rxdma_intr_pkts"}, 312 313 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 314 NXGE_PARAM_DONT_SHOW, 315 0, 8, 0, 0, "rx-rdc-grps-begin", "rx_rdc_grps_begin"}, 316 317 { nxge_param_get_generic, NULL, NXGE_PARAM_READ_PROP | 318 NXGE_PARAM_DONT_SHOW, 319 0, 8, 0, 0, "rx-rdc-grps", "rx_rdc_grps"}, 320 321 { nxge_param_get_generic, nxge_param_set_grp_rdc, 322 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 323 0, 15, 0, 0, "default-grp0-rdc", "default_grp0_rdc"}, 324 325 { nxge_param_get_generic, nxge_param_set_grp_rdc, 326 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 327 0, 15, 2, 0, "default-grp1-rdc", "default_grp1_rdc"}, 328 329 { nxge_param_get_generic, nxge_param_set_grp_rdc, 330 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 331 0, 15, 4, 0, "default-grp2-rdc", "default_grp2_rdc"}, 332 333 { nxge_param_get_generic, nxge_param_set_grp_rdc, 334 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 335 0, 15, 6, 0, "default-grp3-rdc", "default_grp3_rdc"}, 336 337 { nxge_param_get_generic, nxge_param_set_grp_rdc, 338 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 339 0, 15, 8, 0, "default-grp4-rdc", "default_grp4_rdc"}, 340 341 { nxge_param_get_generic, nxge_param_set_grp_rdc, 342 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 343 0, 15, 10, 0, "default-grp5-rdc", "default_grp5_rdc"}, 344 345 { nxge_param_get_generic, nxge_param_set_grp_rdc, 346 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 347 0, 15, 12, 0, "default-grp6-rdc", "default_grp6_rdc"}, 348 349 { nxge_param_get_generic, nxge_param_set_grp_rdc, 350 NXGE_PARAM_RXDMA_RW | NXGE_PARAM_DONT_SHOW, 351 0, 15, 14, 0, "default-grp7-rdc", "default_grp7_rdc"}, 352 353 { nxge_param_get_rxdma_rdcgrp_info, NULL, 354 NXGE_PARAM_READ | NXGE_PARAM_CMPLX | NXGE_PARAM_DONT_SHOW, 355 0, 8, 0, 0, "rdc-groups-info", "rdc_groups_info"}, 356 357 /* Logical device groups */ 358 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 359 0, 63, 0, 0, "start-ldg", "start_ldg"}, 360 361 { nxge_param_get_generic, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 362 0, 64, 0, 0, "max-ldg", "max_ldg" }, 363 364 /* MAC table information */ 365 { nxge_param_get_mac_rdcgrp, nxge_param_set_mac_rdcgrp, 366 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 367 0, 31, 0, 0, "mac-2rdc-grp", "mac_2rdc_grp"}, 368 369 /* VLAN table information */ 370 { nxge_param_get_vlan_rdcgrp, nxge_param_set_vlan_rdcgrp, 371 NXGE_PARAM_L2CLASS_CFG | NXGE_PARAM_DONT_SHOW, 372 0, 31, 0, 0, "vlan-2rdc-grp", "vlan_2rdc_grp"}, 373 374 { nxge_param_get_generic, NULL, 375 NXGE_PARAM_READ_PROP | NXGE_PARAM_READ | 376 NXGE_PARAM_PROP_ARR32 | NXGE_PARAM_DONT_SHOW, 377 0, 0x0ffff, 0x0ffff, 0, "fcram-part-cfg", "fcram_part_cfg"}, 378 379 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 380 NXGE_PARAM_DONT_SHOW, 381 0, 0x10, 0xa, 0, "fcram-access-ratio", "fcram_access_ratio"}, 382 383 { nxge_param_get_generic, NULL, NXGE_PARAM_CLASS_RWS | 384 NXGE_PARAM_DONT_SHOW, 385 0, 0x10, 0xa, 0, "tcam-access-ratio", "tcam_access_ratio"}, 386 387 { nxge_param_get_generic, nxge_param_tcam_enable, 388 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 389 0, 0x1, 0x0, 0, "tcam-enable", "tcam_enable"}, 390 391 { nxge_param_get_generic, nxge_param_hash_lookup_enable, 392 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 393 0, 0x01, 0x0, 0, "hash-lookup-enable", "hash_lookup_enable"}, 394 395 { nxge_param_get_generic, nxge_param_llc_snap_enable, 396 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 397 0, 0x01, 0x01, 0, "llc-snap-enable", "llc_snap_enable"}, 398 399 { nxge_param_get_generic, nxge_param_fflp_hash_init, 400 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 401 0, ALL_FF_32, ALL_FF_32, 0, "h1-init-value", "h1_init_value"}, 402 403 { nxge_param_get_generic, nxge_param_fflp_hash_init, 404 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 405 0, 0x0ffff, 0x0ffff, 0, "h2-init-value", "h2_init_value"}, 406 407 { nxge_param_get_generic, nxge_param_set_ether_usr, 408 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 409 0, ALL_FF_32, 0x0, 0, 410 "class-cfg-ether-usr1", "class_cfg_ether_usr1"}, 411 412 { nxge_param_get_generic, nxge_param_set_ether_usr, 413 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 414 0, ALL_FF_32, 0x0, 0, 415 "class-cfg-ether-usr2", "class_cfg_ether_usr2"}, 416 417 { nxge_param_get_generic, nxge_param_set_ip_usr, 418 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 419 0, ALL_FF_32, 0x0, 0, 420 "class-cfg-ip-usr4", "class_cfg_ip_usr4"}, 421 422 { nxge_param_get_generic, nxge_param_set_ip_usr, 423 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 424 0, ALL_FF_32, 0x0, 0, 425 "class-cfg-ip-usr5", "class_cfg_ip_usr5"}, 426 427 { nxge_param_get_generic, nxge_param_set_ip_usr, 428 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 429 0, ALL_FF_32, 0x0, 0, 430 "class-cfg-ip-usr6", "class_cfg_ip_usr6"}, 431 432 { nxge_param_get_generic, nxge_param_set_ip_usr, 433 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 434 0, ALL_FF_32, 0x0, 0, 435 "class-cfg-ip-usr7", "class_cfg_ip_usr7"}, 436 437 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 438 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 439 0, ALL_FF_32, 0x0, 0, 440 "class-opt-ip-usr4", "class_opt_ip_usr4"}, 441 442 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 443 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 444 0, ALL_FF_32, 0x0, 0, 445 "class-opt-ip-usr5", "class_opt_ip_usr5"}, 446 447 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 448 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 449 0, ALL_FF_32, 0x0, 0, 450 "class-opt-ip-usr6", "class_opt_ip_usr6"}, 451 452 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 453 NXGE_PARAM_CLASS_RWS | NXGE_PARAM_DONT_SHOW, 454 0, ALL_FF_32, 0x0, 0, 455 "class-opt-ip-usr7", "class_opt_ip_usr7"}, 456 457 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 458 NXGE_PARAM_CLASS_RWS, 459 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 460 "class-opt-ipv4-tcp", "class_opt_ipv4_tcp"}, 461 462 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 463 NXGE_PARAM_CLASS_RWS, 464 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 465 "class-opt-ipv4-udp", "class_opt_ipv4_udp"}, 466 467 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 468 NXGE_PARAM_CLASS_RWS, 469 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 470 "class-opt-ipv4-ah", "class_opt_ipv4_ah"}, 471 472 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, 473 NXGE_PARAM_CLASS_RWS, 474 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 475 "class-opt-ipv4-sctp", "class_opt_ipv4_sctp"}, 476 477 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 478 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 479 "class-opt-ipv6-tcp", "class_opt_ipv6_tcp"}, 480 481 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 482 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 483 "class-opt-ipv6-udp", "class_opt_ipv6_udp"}, 484 485 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 486 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 487 "class-opt-ipv6-ah", "class_opt_ipv6_ah"}, 488 489 { nxge_param_get_ip_opt, nxge_param_set_ip_opt, NXGE_PARAM_CLASS_RWS, 490 0, ALL_FF_32, NXGE_CLASS_FLOW_GEN_SERVER, 0, 491 "class-opt-ipv6-sctp", "class_opt_ipv6_sctp"}, 492 493 { nxge_param_get_debug_flag, nxge_param_set_nxge_debug_flag, 494 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 495 0ULL, ALL_FF_64, 0ULL, 0ULL, 496 "nxge-debug-flag", "nxge_debug_flag"}, 497 498 { nxge_param_get_debug_flag, nxge_param_set_npi_debug_flag, 499 NXGE_PARAM_RW | NXGE_PARAM_DONT_SHOW, 500 0ULL, ALL_FF_64, 0ULL, 0ULL, 501 "npi-debug-flag", "npi_debug_flag"}, 502 503 { nxge_param_dump_tdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 504 0, 0x0fffffff, 0x0fffffff, 0, "dump-tdc", "dump_tdc"}, 505 506 { nxge_param_dump_rdc, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 507 0, 0x0fffffff, 0x0fffffff, 0, "dump-rdc", "dump_rdc"}, 508 509 { nxge_param_dump_mac_regs, NULL, NXGE_PARAM_READ | 510 NXGE_PARAM_DONT_SHOW, 511 0, 0x0fffffff, 0x0fffffff, 0, "dump-mac-regs", "dump_mac_regs"}, 512 513 { nxge_param_dump_ipp_regs, NULL, NXGE_PARAM_READ | 514 NXGE_PARAM_DONT_SHOW, 515 0, 0x0fffffff, 0x0fffffff, 0, "dump-ipp-regs", "dump_ipp_regs"}, 516 517 { nxge_param_dump_fflp_regs, NULL, NXGE_PARAM_READ | 518 NXGE_PARAM_DONT_SHOW, 519 0, 0x0fffffff, 0x0fffffff, 0, 520 "dump-fflp-regs", "dump_fflp_regs"}, 521 522 { nxge_param_dump_vlan_table, NULL, NXGE_PARAM_READ | 523 NXGE_PARAM_DONT_SHOW, 524 0, 0x0fffffff, 0x0fffffff, 0, 525 "dump-vlan-table", "dump_vlan_table"}, 526 527 { nxge_param_dump_rdc_table, NULL, NXGE_PARAM_READ | 528 NXGE_PARAM_DONT_SHOW, 529 0, 0x0fffffff, 0x0fffffff, 0, 530 "dump-rdc-table", "dump_rdc_table"}, 531 532 { nxge_param_dump_ptrs, NULL, NXGE_PARAM_READ | 533 NXGE_PARAM_DONT_SHOW, 534 0, 0x0fffffff, 0x0fffffff, 0, "dump-ptrs", "dump_ptrs"}, 535 536 { NULL, NULL, NXGE_PARAM_READ | NXGE_PARAM_DONT_SHOW, 537 0, 0x0fffffff, 0x0fffffff, 0, "end", "end"}, 538 }; 539 540 extern void *nxge_list; 541 542 void 543 nxge_get_param_soft_properties(p_nxge_t nxgep) 544 { 545 546 p_nxge_param_t param_arr; 547 uint_t prop_len; 548 int i, j; 549 uint32_t param_count; 550 uint32_t *int_prop_val; 551 552 NXGE_DEBUG_MSG((nxgep, DDI_CTL, " ==> nxge_get_param_soft_properties")); 553 554 param_arr = nxgep->param_arr; 555 param_count = nxgep->param_count; 556 for (i = 0; i < param_count; i++) { 557 if ((param_arr[i].type & NXGE_PARAM_READ_PROP) == 0) 558 continue; 559 if ((param_arr[i].type & NXGE_PARAM_PROP_STR)) 560 continue; 561 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 562 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 563 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 564 nxgep->dip, 0, param_arr[i].fcode_name, 565 (int **)&int_prop_val, 566 (uint_t *)&prop_len) 567 == DDI_PROP_SUCCESS) { 568 uint32_t *cfg_value; 569 uint64_t prop_count; 570 571 if (prop_len > NXGE_PARAM_ARRAY_INIT_SIZE) 572 prop_len = NXGE_PARAM_ARRAY_INIT_SIZE; 573 #if defined(__i386) 574 cfg_value = 575 (uint32_t *)(int32_t)param_arr[i].value; 576 #else 577 cfg_value = (uint32_t *)param_arr[i].value; 578 #endif 579 for (j = 0; j < prop_len; j++) { 580 cfg_value[j] = int_prop_val[j]; 581 } 582 prop_count = prop_len; 583 param_arr[i].type |= 584 (prop_count << NXGE_PARAM_ARRAY_CNT_SHIFT); 585 ddi_prop_free(int_prop_val); 586 } 587 continue; 588 } 589 590 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 591 param_arr[i].fcode_name, 592 (int **)&int_prop_val, 593 &prop_len) == DDI_PROP_SUCCESS) { 594 if ((*int_prop_val >= param_arr[i].minimum) && 595 (*int_prop_val <= param_arr[i].maximum)) 596 param_arr[i].value = *int_prop_val; 597 #ifdef NXGE_DEBUG_ERROR 598 else { 599 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 600 "nxge%d: 'prom' file parameter error\n", 601 nxgep->instance)); 602 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 603 "Parameter keyword '%s'" 604 " is outside valid range\n", 605 param_arr[i].name)); 606 } 607 #endif 608 ddi_prop_free(int_prop_val); 609 } 610 611 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 0, 612 param_arr[i].name, 613 (int **)&int_prop_val, 614 &prop_len) == DDI_PROP_SUCCESS) { 615 if ((*int_prop_val >= param_arr[i].minimum) && 616 (*int_prop_val <= param_arr[i].maximum)) 617 param_arr[i].value = *int_prop_val; 618 #ifdef NXGE_DEBUG_ERROR 619 else { 620 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 621 "nxge%d: 'conf' file parameter error\n", 622 nxgep->instance)); 623 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 624 "Parameter keyword '%s'" 625 "is outside valid range\n", 626 param_arr[i].name)); 627 } 628 #endif 629 ddi_prop_free(int_prop_val); 630 } 631 } 632 } 633 634 static int 635 nxge_private_param_register(p_nxge_t nxgep, p_nxge_param_t param_arr) 636 { 637 int status = B_TRUE; 638 int channel; 639 uint8_t grp; 640 char *prop_name; 641 char *end; 642 uint32_t name_chars; 643 644 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 645 "nxge_private_param_register %s", param_arr->name)); 646 647 if ((param_arr->type & NXGE_PARAM_PRIV) != NXGE_PARAM_PRIV) 648 return (B_TRUE); 649 650 prop_name = param_arr->name; 651 if (param_arr->type & NXGE_PARAM_RXDMA) { 652 if (strncmp("rxdma_intr", prop_name, 10) == 0) 653 return (B_TRUE); 654 name_chars = strlen("default_grp"); 655 if (strncmp("default_grp", prop_name, name_chars) == 0) { 656 prop_name += name_chars; 657 grp = mi_strtol(prop_name, &end, 10); 658 /* now check if this rdcgrp is in config */ 659 return (nxge_check_rdcgrp_port_member(nxgep, grp)); 660 } 661 name_chars = strlen(prop_name); 662 if (strncmp("default_port_rdc", prop_name, name_chars) == 0) { 663 return (B_TRUE); 664 } 665 return (B_FALSE); 666 } 667 668 if (param_arr->type & NXGE_PARAM_TXDMA) { 669 name_chars = strlen("txdma"); 670 if (strncmp("txdma", prop_name, name_chars) == 0) { 671 prop_name += name_chars; 672 channel = mi_strtol(prop_name, &end, 10); 673 /* now check if this rdc is in config */ 674 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 675 " nxge_private_param_register: %d", 676 channel)); 677 return (nxge_check_txdma_port_member(nxgep, channel)); 678 } 679 return (B_FALSE); 680 } 681 682 status = B_FALSE; 683 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, "<== nxge_private_param_register")); 684 685 return (status); 686 } 687 688 void 689 nxge_setup_param(p_nxge_t nxgep) 690 { 691 p_nxge_param_t param_arr; 692 int i; 693 pfi_t set_pfi; 694 695 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_setup_param")); 696 697 /* 698 * Make sure the param_instance is set to a valid device instance. 699 */ 700 if (nxge_param_arr[param_instance].value == 1000) 701 nxge_param_arr[param_instance].value = nxgep->instance; 702 703 param_arr = nxgep->param_arr; 704 param_arr[param_instance].value = nxgep->instance; 705 param_arr[param_function_number].value = nxgep->function_num; 706 707 for (i = 0; i < nxgep->param_count; i++) { 708 if ((param_arr[i].type & NXGE_PARAM_PRIV) && 709 (nxge_private_param_register(nxgep, 710 ¶m_arr[i]) == B_FALSE)) { 711 param_arr[i].setf = NULL; 712 param_arr[i].getf = NULL; 713 } 714 715 if (param_arr[i].type & NXGE_PARAM_CMPLX) 716 param_arr[i].setf = NULL; 717 718 if (param_arr[i].type & NXGE_PARAM_DONT_SHOW) { 719 param_arr[i].setf = NULL; 720 param_arr[i].getf = NULL; 721 } 722 723 set_pfi = (pfi_t)param_arr[i].setf; 724 725 if ((set_pfi) && (param_arr[i].type & NXGE_PARAM_INIT_ONLY)) { 726 set_pfi = NULL; 727 } 728 729 } 730 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_setup_param")); 731 } 732 733 void 734 nxge_init_param(p_nxge_t nxgep) 735 { 736 p_nxge_param_t param_arr; 737 int i, alloc_size; 738 uint64_t alloc_count; 739 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_init_param")); 740 /* 741 * Make sure the param_instance is set to a valid device instance. 742 */ 743 if (nxge_param_arr[param_instance].value == 1000) 744 nxge_param_arr[param_instance].value = nxgep->instance; 745 746 param_arr = nxgep->param_arr; 747 if (param_arr == NULL) { 748 param_arr = (p_nxge_param_t) 749 KMEM_ZALLOC(sizeof (nxge_param_arr), KM_SLEEP); 750 } 751 752 for (i = 0; i < sizeof (nxge_param_arr)/sizeof (nxge_param_t); i++) { 753 param_arr[i] = nxge_param_arr[i]; 754 if ((param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 755 (param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 756 alloc_count = NXGE_PARAM_ARRAY_INIT_SIZE; 757 alloc_size = alloc_count * sizeof (uint64_t); 758 param_arr[i].value = 759 #if defined(__i386) 760 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 761 KM_SLEEP); 762 #else 763 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 764 #endif 765 param_arr[i].old_value = 766 #if defined(__i386) 767 (uint64_t)(uint32_t)KMEM_ZALLOC(alloc_size, 768 KM_SLEEP); 769 #else 770 (uint64_t)KMEM_ZALLOC(alloc_size, KM_SLEEP); 771 #endif 772 param_arr[i].type |= 773 (alloc_count << NXGE_PARAM_ARRAY_ALLOC_SHIFT); 774 } 775 } 776 777 nxgep->param_arr = param_arr; 778 nxgep->param_count = sizeof (nxge_param_arr)/sizeof (nxge_param_t); 779 780 nxge_param_sync(nxgep); 781 782 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init_param: count %d", 783 nxgep->param_count)); 784 } 785 786 void 787 nxge_destroy_param(p_nxge_t nxgep) 788 { 789 int i; 790 uint64_t free_size, free_count; 791 792 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_param")); 793 794 if (nxgep->param_arr == NULL) 795 return; 796 /* 797 * Make sure the param_instance is set to a valid device instance. 798 */ 799 if (nxge_param_arr[param_instance].value == nxgep->instance) { 800 for (i = 0; i <= nxge_param_arr[param_instance].maximum; i++) { 801 if ((ddi_get_soft_state(nxge_list, i) != NULL) && 802 (i != nxgep->instance)) 803 break; 804 } 805 nxge_param_arr[param_instance].value = i; 806 } 807 808 for (i = 0; i < nxgep->param_count; i++) 809 if ((nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR32) || 810 (nxgep->param_arr[i].type & NXGE_PARAM_PROP_ARR64)) { 811 free_count = ((nxgep->param_arr[i].type & 812 NXGE_PARAM_ARRAY_ALLOC_MASK) >> 813 NXGE_PARAM_ARRAY_ALLOC_SHIFT); 814 free_count = NXGE_PARAM_ARRAY_INIT_SIZE; 815 free_size = sizeof (uint64_t) * free_count; 816 #if defined(__i386) 817 KMEM_FREE((void *)(uint32_t)nxgep->param_arr[i].value, 818 free_size); 819 #else 820 KMEM_FREE((void *)nxgep->param_arr[i].value, free_size); 821 #endif 822 #if defined(__i386) 823 KMEM_FREE((void *)(uint32_t) 824 nxgep->param_arr[i].old_value, free_size); 825 #else 826 KMEM_FREE((void *)nxgep->param_arr[i].old_value, 827 free_size); 828 #endif 829 } 830 831 KMEM_FREE(nxgep->param_arr, sizeof (nxge_param_arr)); 832 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_param")); 833 } 834 835 /* 836 * Extracts the value from the 'nxge' parameter array and prints the 837 * parameter value. cp points to the required parameter. 838 */ 839 840 /* ARGSUSED */ 841 int 842 nxge_param_get_generic(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 843 { 844 p_nxge_param_t pa = (p_nxge_param_t)cp; 845 846 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 847 "==> nxge_param_get_generic name %s ", pa->name)); 848 849 if (pa->value > 0xffffffff) 850 (void) mi_mpprintf(mp, "%x%x", 851 (int)(pa->value >> 32), (int)(pa->value & 0xffffffff)); 852 else 853 (void) mi_mpprintf(mp, "%x", (int)pa->value); 854 855 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_generic")); 856 return (0); 857 } 858 859 /* ARGSUSED */ 860 static int 861 nxge_param_get_mac(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 862 { 863 p_nxge_param_t pa = (p_nxge_param_t)cp; 864 865 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac")); 866 867 (void) mi_mpprintf(mp, "%d", (uint32_t)pa->value); 868 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_mac")); 869 return (0); 870 } 871 872 /* ARGSUSED */ 873 static int 874 nxge_param_get_fw_ver(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 875 { 876 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_fw_ver")); 877 878 (void) mi_mpprintf(mp, "Firmware version for nxge%d: %s\n", 879 nxgep->instance, nxgep->vpd_info.ver); 880 881 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_fw_ver")); 882 return (0); 883 } 884 885 /* ARGSUSED */ 886 static int 887 nxge_param_get_port_mode(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 888 { 889 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_port_mode")); 890 891 switch (nxgep->mac.portmode) { 892 case PORT_1G_COPPER: 893 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Copper %s\n", 894 nxgep->instance, 895 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 896 break; 897 case PORT_1G_FIBER: 898 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Fiber %s\n", 899 nxgep->instance, 900 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 901 break; 902 case PORT_10G_COPPER: 903 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Copper " 904 "%s\n", nxgep->instance, 905 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 906 break; 907 case PORT_10G_FIBER: 908 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Fiber %s\n", 909 nxgep->instance, 910 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 911 break; 912 case PORT_10G_SERDES: 913 (void) mi_mpprintf(mp, "Port mode for nxge%d: 10G Serdes " 914 "%s\n", nxgep->instance, 915 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 916 break; 917 case PORT_1G_SERDES: 918 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G Serdes %s\n", 919 nxgep->instance, 920 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 921 break; 922 case PORT_1G_RGMII_FIBER: 923 (void) mi_mpprintf(mp, "Port mode for nxge%d: 1G RGMII " 924 "Fiber %s\n", nxgep->instance, 925 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 926 break; 927 case PORT_HSP_MODE: 928 (void) mi_mpprintf(mp, "Port mode for nxge%d: Hot Swappable " 929 "PHY, Currently NOT present\n", nxgep->instance); 930 break; 931 default: 932 (void) mi_mpprintf(mp, "Port mode for nxge%d: Unknown %s\n", 933 nxgep->instance, 934 nxgep->hot_swappable_phy ? "[Hot Swappable]" : ""); 935 break; 936 } 937 938 (void) mi_mpprintf(mp, "Software LSO for nxge%d: %s\n", 939 nxgep->instance, 940 nxgep->soft_lso_enable ? "enable" : "disable"); 941 942 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_port_mode")); 943 return (0); 944 } 945 946 /* ARGSUSED */ 947 int 948 nxge_param_get_txdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 949 { 950 951 uint_t print_len, buf_len; 952 p_mblk_t np; 953 954 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 955 int tdc; 956 957 nxge_grp_set_t *set; 958 959 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_txdma_info")); 960 961 (void) mi_mpprintf(mp, "TXDMA Information for Port\t %d \n", 962 nxgep->function_num); 963 964 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 965 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 966 return (0); 967 } 968 969 buf_len = buff_alloc_size; 970 mp->b_cont = np; 971 print_len = 0; 972 973 ((mblk_t *)np)->b_wptr += print_len; 974 buf_len -= print_len; 975 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 976 "TDC\t HW TDC\t\n"); 977 ((mblk_t *)np)->b_wptr += print_len; 978 buf_len -= print_len; 979 980 set = &nxgep->tx_set; 981 for (tdc = 0; tdc < NXGE_MAX_RDCS; tdc++) { 982 if ((1 << tdc) & set->owned.map) { 983 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 984 buf_len, "%d\n", tdc); 985 ((mblk_t *)np)->b_wptr += print_len; 986 buf_len -= print_len; 987 } 988 } 989 990 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_txdma_info")); 991 return (0); 992 } 993 994 /* ARGSUSED */ 995 int 996 nxge_param_get_rxdma_info(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 997 { 998 uint_t print_len, buf_len; 999 p_mblk_t np; 1000 int rdc; 1001 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1002 p_nxge_hw_pt_cfg_t p_cfgp; 1003 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1004 p_rx_rcr_rings_t rx_rcr_rings; 1005 p_rx_rcr_ring_t *rcr_rings; 1006 p_rx_rbr_rings_t rx_rbr_rings; 1007 p_rx_rbr_ring_t *rbr_rings; 1008 nxge_grp_set_t *set; 1009 1010 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_rxdma_info")); 1011 1012 (void) mi_mpprintf(mp, "RXDMA Information for Port\t %d \n", 1013 nxgep->function_num); 1014 1015 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1016 /* The following may work even if we cannot get a large buf. */ 1017 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1018 return (0); 1019 } 1020 1021 buf_len = buff_alloc_size; 1022 mp->b_cont = np; 1023 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1024 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1025 1026 rx_rcr_rings = nxgep->rx_rcr_rings; 1027 rcr_rings = rx_rcr_rings->rcr_rings; 1028 rx_rbr_rings = nxgep->rx_rbr_rings; 1029 rbr_rings = rx_rbr_rings->rbr_rings; 1030 1031 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1032 "Total RDCs\t %d\n", p_cfgp->max_rdcs); 1033 1034 ((mblk_t *)np)->b_wptr += print_len; 1035 buf_len -= print_len; 1036 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1037 "RDC\t HW RDC\t Timeout\t Packets RBR ptr \t" 1038 "chunks\t RCR ptr\n"); 1039 1040 ((mblk_t *)np)->b_wptr += print_len; 1041 buf_len -= print_len; 1042 1043 set = &nxgep->rx_set; 1044 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 1045 if ((1 << rdc) & set->owned.map) { 1046 print_len = snprintf((char *) 1047 ((mblk_t *)np)->b_wptr, buf_len, 1048 " %d\t %x\t\t %x\t $%p\t 0x%x\t $%p\n", 1049 rdc, 1050 p_dma_cfgp->rcr_timeout[rdc], 1051 p_dma_cfgp->rcr_threshold[rdc], 1052 rbr_rings[rdc], 1053 rbr_rings[rdc]->num_blocks, rcr_rings[rdc]); 1054 ((mblk_t *)np)->b_wptr += print_len; 1055 buf_len -= print_len; 1056 } 1057 } 1058 1059 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_rxdma_info")); 1060 return (0); 1061 } 1062 1063 /* ARGSUSED */ 1064 int 1065 nxge_param_get_rxdma_rdcgrp_info(p_nxge_t nxgep, queue_t *q, 1066 p_mblk_t mp, caddr_t cp) 1067 { 1068 uint_t print_len, buf_len; 1069 p_mblk_t np; 1070 int offset, rdc, i, rdc_grp; 1071 p_nxge_rdc_grp_t rdc_grp_p; 1072 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1073 p_nxge_hw_pt_cfg_t p_cfgp; 1074 1075 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE; 1076 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1077 "==> nxge_param_get_rxdma_rdcgrp_info")); 1078 1079 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1080 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1081 1082 (void) mi_mpprintf(mp, "RXDMA RDC Group Information for Port\t %d \n", 1083 nxgep->function_num); 1084 1085 rdc_grp = p_cfgp->def_mac_rxdma_grpid; 1086 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1087 /* The following may work even if we cannot get a large buf. */ 1088 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1089 return (0); 1090 } 1091 1092 buf_len = buff_alloc_size; 1093 mp->b_cont = np; 1094 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1095 "Total RDC Groups\t %d \n" 1096 "default RDC group\t %d\n", 1097 p_cfgp->max_rdc_grpids, 1098 p_cfgp->def_mac_rxdma_grpid); 1099 1100 ((mblk_t *)np)->b_wptr += print_len; 1101 buf_len -= print_len; 1102 1103 for (i = 0; i < NXGE_MAX_RDCS; i++) { 1104 if (p_cfgp->grpids[i]) { 1105 rdc_grp_p = &p_dma_cfgp->rdc_grps[i]; 1106 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1107 buf_len, 1108 "\nRDC Group Info for Group [%d] %d\n" 1109 "RDC Count %d\tstart RDC %d\n" 1110 "RDC Group Population Information" 1111 " (offsets 0 - 15)\n", 1112 i, rdc_grp, rdc_grp_p->max_rdcs, 1113 rdc_grp_p->start_rdc); 1114 1115 ((mblk_t *)np)->b_wptr += print_len; 1116 buf_len -= print_len; 1117 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1118 buf_len, "\n"); 1119 ((mblk_t *)np)->b_wptr += print_len; 1120 buf_len -= print_len; 1121 1122 for (rdc = 0; rdc < rdc_grp_p->max_rdcs; rdc++) { 1123 print_len = snprintf( 1124 (char *)((mblk_t *)np)->b_wptr, 1125 buf_len, "[%d]=%d ", rdc, 1126 rdc_grp_p->start_rdc + rdc); 1127 ((mblk_t *)np)->b_wptr += print_len; 1128 buf_len -= print_len; 1129 } 1130 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1131 buf_len, "\n"); 1132 ((mblk_t *)np)->b_wptr += print_len; 1133 buf_len -= print_len; 1134 1135 for (offset = 0; offset < 16; offset++) { 1136 print_len = snprintf( 1137 (char *)((mblk_t *)np)->b_wptr, 1138 buf_len, " %c", 1139 rdc_grp_p->map & (1 << offset) ? 1140 '1' : '0'); 1141 ((mblk_t *)np)->b_wptr += print_len; 1142 buf_len -= print_len; 1143 } 1144 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1145 buf_len, "\n"); 1146 ((mblk_t *)np)->b_wptr += print_len; 1147 buf_len -= print_len; 1148 } 1149 } 1150 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1151 "<== nxge_param_get_rxdma_rdcgrp_info")); 1152 return (0); 1153 } 1154 1155 int 1156 nxge_mk_mblk_tail_space(p_mblk_t mp, p_mblk_t *nmp, size_t size) 1157 { 1158 p_mblk_t tmp; 1159 1160 tmp = mp; 1161 while (tmp->b_cont) 1162 tmp = tmp->b_cont; 1163 if ((tmp->b_wptr + size) >= tmp->b_datap->db_lim) { 1164 tmp->b_cont = allocb(1024, BPRI_HI); 1165 tmp = tmp->b_cont; 1166 if (!tmp) 1167 return (ENOMEM); 1168 } 1169 1170 *nmp = tmp; 1171 return (0); 1172 } 1173 1174 1175 /* ARGSUSED */ 1176 int 1177 nxge_param_set_generic(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1178 char *value, caddr_t cp) 1179 { 1180 char *end; 1181 uint32_t new_value; 1182 p_nxge_param_t pa = (p_nxge_param_t)cp; 1183 1184 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " ==> nxge_param_set_generic")); 1185 new_value = (uint32_t)mi_strtol(value, &end, 10); 1186 if (end == value || new_value < pa->minimum || 1187 new_value > pa->maximum) { 1188 return (EINVAL); 1189 } 1190 pa->value = new_value; 1191 NXGE_DEBUG_MSG((nxgep, IOC_CTL, " <== nxge_param_set_generic")); 1192 return (0); 1193 } 1194 1195 1196 /* ARGSUSED */ 1197 int 1198 nxge_param_set_instance(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1199 char *value, caddr_t cp) 1200 { 1201 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " ==> nxge_param_set_instance")); 1202 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_set_instance")); 1203 return (0); 1204 } 1205 1206 1207 /* ARGSUSED */ 1208 int 1209 nxge_param_set_mac(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1210 char *value, caddr_t cp) 1211 { 1212 char *end; 1213 uint32_t new_value; 1214 int status = 0; 1215 p_nxge_param_t pa = (p_nxge_param_t)cp; 1216 1217 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac")); 1218 new_value = (uint32_t)mi_strtol(value, &end, BASE_DECIMAL); 1219 if (PARAM_OUTOF_RANGE(value, end, new_value, pa)) { 1220 return (EINVAL); 1221 } 1222 1223 if (pa->value != new_value) { 1224 pa->old_value = pa->value; 1225 pa->value = new_value; 1226 } 1227 1228 if (!nxge_param_link_update(nxgep)) { 1229 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1230 " false ret from nxge_param_link_update")); 1231 status = EINVAL; 1232 } 1233 1234 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac")); 1235 return (status); 1236 } 1237 1238 /* ARGSUSED */ 1239 int 1240 nxge_param_rx_intr_pkts(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1241 char *value, caddr_t cp) 1242 { 1243 char *end; 1244 uint32_t cfg_value; 1245 p_nxge_param_t pa = (p_nxge_param_t)cp; 1246 1247 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_pkts")); 1248 1249 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1250 1251 if ((cfg_value > NXGE_RDC_RCR_THRESHOLD_MAX) || 1252 (cfg_value < NXGE_RDC_RCR_THRESHOLD_MIN)) { 1253 return (EINVAL); 1254 } 1255 1256 if ((pa->value != cfg_value)) { 1257 pa->old_value = pa->value; 1258 pa->value = cfg_value; 1259 nxgep->intr_threshold = pa->value; 1260 } 1261 1262 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_pkts")); 1263 return (0); 1264 } 1265 1266 /* ARGSUSED */ 1267 int 1268 nxge_param_rx_intr_time(p_nxge_t nxgep, queue_t *q, mblk_t *mp, 1269 char *value, caddr_t cp) 1270 { 1271 char *end; 1272 uint32_t cfg_value; 1273 p_nxge_param_t pa = (p_nxge_param_t)cp; 1274 1275 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_rx_intr_time")); 1276 1277 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1278 1279 if ((cfg_value > NXGE_RDC_RCR_TIMEOUT_MAX) || 1280 (cfg_value < NXGE_RDC_RCR_TIMEOUT_MIN)) { 1281 return (EINVAL); 1282 } 1283 1284 if ((pa->value != cfg_value)) { 1285 pa->old_value = pa->value; 1286 pa->value = cfg_value; 1287 nxgep->intr_timeout = pa->value; 1288 } 1289 1290 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_rx_intr_time")); 1291 return (0); 1292 } 1293 1294 /* ARGSUSED */ 1295 static int 1296 nxge_param_set_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1297 mblk_t *mp, char *value, caddr_t cp) 1298 { 1299 char *end; 1300 uint32_t status = 0, cfg_value; 1301 p_nxge_param_t pa = (p_nxge_param_t)cp; 1302 uint32_t cfg_it = B_FALSE; 1303 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1304 p_nxge_hw_pt_cfg_t p_cfgp; 1305 uint32_t *val_ptr, *old_val_ptr; 1306 nxge_param_map_t *mac_map; 1307 p_nxge_class_pt_cfg_t p_class_cfgp; 1308 nxge_mv_cfg_t *mac_host_info; 1309 1310 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_mac_rdcgrp ")); 1311 1312 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1313 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1314 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1315 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1316 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1317 1318 /* 1319 * now do decoding 1320 */ 1321 mac_map = (nxge_param_map_t *)&cfg_value; 1322 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " cfg_value %x id %x map_to %x", 1323 cfg_value, mac_map->param_id, mac_map->map_to)); 1324 1325 if ((mac_map->param_id < p_cfgp->max_macs) && 1326 p_cfgp->grpids[mac_map->map_to]) { 1327 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1328 " nxge_param_set_mac_rdcgrp mapping" 1329 " id %d grp %d", mac_map->param_id, mac_map->map_to)); 1330 #if defined(__i386) 1331 val_ptr = (uint32_t *)(uint32_t)pa->value; 1332 #else 1333 val_ptr = (uint32_t *)pa->value; 1334 #endif 1335 #if defined(__i386) 1336 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1337 #else 1338 old_val_ptr = (uint32_t *)pa->old_value; 1339 #endif 1340 if (val_ptr[mac_map->param_id] != cfg_value) { 1341 old_val_ptr[mac_map->param_id] = 1342 val_ptr[mac_map->param_id]; 1343 val_ptr[mac_map->param_id] = cfg_value; 1344 mac_host_info[mac_map->param_id].mpr_npr = 1345 mac_map->pref; 1346 mac_host_info[mac_map->param_id].flag = 1; 1347 mac_host_info[mac_map->param_id].rdctbl = 1348 mac_map->map_to; 1349 cfg_it = B_TRUE; 1350 } 1351 } else { 1352 return (EINVAL); 1353 } 1354 1355 if (cfg_it == B_TRUE) { 1356 status = nxge_logical_mac_assign_rdc_table(nxgep, 1357 (uint8_t)mac_map->param_id); 1358 if (status != NXGE_OK) 1359 return (EINVAL); 1360 } 1361 1362 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_mac_rdcgrp")); 1363 return (0); 1364 } 1365 1366 /* ARGSUSED */ 1367 static int 1368 nxge_param_set_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1369 mblk_t *mp, char *value, caddr_t cp) 1370 { 1371 char *end; 1372 uint32_t status = 0, cfg_value; 1373 p_nxge_param_t pa = (p_nxge_param_t)cp; 1374 uint32_t cfg_it = B_FALSE; 1375 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1376 p_nxge_hw_pt_cfg_t p_cfgp; 1377 uint32_t *val_ptr, *old_val_ptr; 1378 nxge_param_map_t *vmap, *old_map; 1379 p_nxge_class_pt_cfg_t p_class_cfgp; 1380 uint64_t cfgd_vlans; 1381 int i, inc = 0, cfg_position; 1382 nxge_mv_cfg_t *vlan_tbl; 1383 1384 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1385 1386 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1387 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1388 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1389 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1390 1391 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1392 1393 /* now do decoding */ 1394 cfgd_vlans = ((pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1395 NXGE_PARAM_ARRAY_CNT_SHIFT); 1396 1397 if (cfgd_vlans == NXGE_PARAM_ARRAY_INIT_SIZE) { 1398 /* 1399 * for now, we process only upto max 1400 * NXGE_PARAM_ARRAY_INIT_SIZE parameters 1401 * In the future, we may want to expand 1402 * the storage array and continue 1403 */ 1404 return (EINVAL); 1405 } 1406 1407 vmap = (nxge_param_map_t *)&cfg_value; 1408 if ((vmap->param_id) && 1409 (vmap->param_id < NXGE_MAX_VLANS) && 1410 (vmap->map_to < p_cfgp->max_rdc_grpids)) { 1411 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1412 "nxge_param_set_vlan_rdcgrp mapping" 1413 " id %d grp %d", 1414 vmap->param_id, vmap->map_to)); 1415 #if defined(__i386) 1416 val_ptr = (uint32_t *)(uint32_t)pa->value; 1417 #else 1418 val_ptr = (uint32_t *)pa->value; 1419 #endif 1420 #if defined(__i386) 1421 old_val_ptr = (uint32_t *)(uint32_t)pa->old_value; 1422 #else 1423 old_val_ptr = (uint32_t *)pa->old_value; 1424 #endif 1425 1426 /* search to see if this vlan id is already configured */ 1427 for (i = 0; i < cfgd_vlans; i++) { 1428 old_map = (nxge_param_map_t *)&val_ptr[i]; 1429 if ((old_map->param_id == 0) || 1430 (vmap->param_id == old_map->param_id) || 1431 (vlan_tbl[vmap->param_id].flag)) { 1432 cfg_position = i; 1433 break; 1434 } 1435 } 1436 1437 if (cfgd_vlans == 0) { 1438 cfg_position = 0; 1439 inc++; 1440 } 1441 1442 if (i == cfgd_vlans) { 1443 cfg_position = i; 1444 inc++; 1445 } 1446 1447 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1448 "set_vlan_rdcgrp mapping" 1449 " i %d cfgd_vlans %llx position %d ", 1450 i, cfgd_vlans, cfg_position)); 1451 if (val_ptr[cfg_position] != cfg_value) { 1452 old_val_ptr[cfg_position] = val_ptr[cfg_position]; 1453 val_ptr[cfg_position] = cfg_value; 1454 vlan_tbl[vmap->param_id].mpr_npr = vmap->pref; 1455 vlan_tbl[vmap->param_id].flag = 1; 1456 vlan_tbl[vmap->param_id].rdctbl = 1457 vmap->map_to + p_cfgp->def_mac_rxdma_grpid; 1458 cfg_it = B_TRUE; 1459 if (inc) { 1460 cfgd_vlans++; 1461 pa->type &= ~NXGE_PARAM_ARRAY_CNT_MASK; 1462 pa->type |= (cfgd_vlans << 1463 NXGE_PARAM_ARRAY_CNT_SHIFT); 1464 1465 } 1466 NXGE_DEBUG_MSG((nxgep, NDD2_CTL, 1467 "after: param_set_vlan_rdcgrp " 1468 " cfg_vlans %llx position %d \n", 1469 cfgd_vlans, cfg_position)); 1470 } 1471 } else { 1472 return (EINVAL); 1473 } 1474 1475 if (cfg_it == B_TRUE) { 1476 status = nxge_fflp_config_vlan_table(nxgep, 1477 (uint16_t)vmap->param_id); 1478 if (status != NXGE_OK) 1479 return (EINVAL); 1480 } 1481 1482 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_vlan_rdcgrp")); 1483 return (0); 1484 } 1485 1486 /* ARGSUSED */ 1487 static int 1488 nxge_param_get_vlan_rdcgrp(p_nxge_t nxgep, queue_t *q, 1489 mblk_t *mp, caddr_t cp) 1490 { 1491 1492 uint_t print_len, buf_len; 1493 p_mblk_t np; 1494 int i; 1495 uint32_t *val_ptr; 1496 nxge_param_map_t *vmap; 1497 p_nxge_param_t pa = (p_nxge_param_t)cp; 1498 p_nxge_class_pt_cfg_t p_class_cfgp; 1499 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1500 p_nxge_hw_pt_cfg_t p_cfgp; 1501 uint64_t cfgd_vlans = 0; 1502 nxge_mv_cfg_t *vlan_tbl; 1503 int buff_alloc_size = 1504 NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1505 1506 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_vlan_rdcgrp ")); 1507 (void) mi_mpprintf(mp, "VLAN RDC Mapping Information for Port\t %d \n", 1508 nxgep->function_num); 1509 1510 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1511 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1512 return (0); 1513 } 1514 1515 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1516 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1517 1518 buf_len = buff_alloc_size; 1519 mp->b_cont = np; 1520 cfgd_vlans = (pa->type & NXGE_PARAM_ARRAY_CNT_MASK) >> 1521 NXGE_PARAM_ARRAY_CNT_SHIFT; 1522 1523 i = (int)cfgd_vlans; 1524 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1525 vlan_tbl = (nxge_mv_cfg_t *)&p_class_cfgp->vlan_tbl[0]; 1526 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1527 "Configured VLANs %d\n" 1528 "VLAN ID\t RDC GRP (Actual/Port)\t" 1529 " Prefernce\n", i); 1530 ((mblk_t *)np)->b_wptr += print_len; 1531 buf_len -= print_len; 1532 #if defined(__i386) 1533 val_ptr = (uint32_t *)(uint32_t)pa->value; 1534 #else 1535 val_ptr = (uint32_t *)pa->value; 1536 #endif 1537 1538 for (i = 0; i < cfgd_vlans; i++) { 1539 vmap = (nxge_param_map_t *)&val_ptr[i]; 1540 if (p_class_cfgp->vlan_tbl[vmap->param_id].flag) { 1541 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1542 buf_len, 1543 " %d\t\t %d/%d\t\t %d\n", 1544 vmap->param_id, 1545 vlan_tbl[vmap->param_id].rdctbl, 1546 vlan_tbl[vmap->param_id].rdctbl - 1547 p_cfgp->def_mac_rxdma_grpid, 1548 vlan_tbl[vmap->param_id].mpr_npr); 1549 ((mblk_t *)np)->b_wptr += print_len; 1550 buf_len -= print_len; 1551 } 1552 } 1553 1554 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_vlan_rdcgrp")); 1555 return (0); 1556 } 1557 1558 /* ARGSUSED */ 1559 static int 1560 nxge_param_get_mac_rdcgrp(p_nxge_t nxgep, queue_t *q, 1561 mblk_t *mp, caddr_t cp) 1562 { 1563 uint_t print_len, buf_len; 1564 p_mblk_t np; 1565 int i; 1566 p_nxge_class_pt_cfg_t p_class_cfgp; 1567 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1568 p_nxge_hw_pt_cfg_t p_cfgp; 1569 nxge_mv_cfg_t *mac_host_info; 1570 1571 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_SIZE * 32; 1572 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_mac_rdcgrp ")); 1573 (void) mi_mpprintf(mp, 1574 "MAC ADDR RDC Mapping Information for Port\t %d\n", 1575 nxgep->function_num); 1576 1577 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 1578 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 1579 return (0); 1580 } 1581 1582 buf_len = buff_alloc_size; 1583 mp->b_cont = np; 1584 p_class_cfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 1585 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1586 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1587 mac_host_info = (nxge_mv_cfg_t *)&p_class_cfgp->mac_host_info[0]; 1588 print_len = snprintf((char *)np->b_wptr, buf_len, 1589 "MAC ID\t RDC GRP (Actual/Port)\t" 1590 " Prefernce\n"); 1591 ((mblk_t *)np)->b_wptr += print_len; 1592 buf_len -= print_len; 1593 for (i = 0; i < p_cfgp->max_macs; i++) { 1594 if (mac_host_info[i].flag) { 1595 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, 1596 buf_len, 1597 " %d\t %d/%d\t\t %d\n", 1598 i, mac_host_info[i].rdctbl, 1599 mac_host_info[i].rdctbl - 1600 p_cfgp->def_mac_rxdma_grpid, 1601 mac_host_info[i].mpr_npr); 1602 ((mblk_t *)np)->b_wptr += print_len; 1603 buf_len -= print_len; 1604 } 1605 } 1606 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 1607 "Done Info Dumping \n"); 1608 ((mblk_t *)np)->b_wptr += print_len; 1609 buf_len -= print_len; 1610 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_macrdcgrp")); 1611 return (0); 1612 } 1613 1614 /* ARGSUSED */ 1615 static int 1616 nxge_param_tcam_enable(p_nxge_t nxgep, queue_t *q, 1617 mblk_t *mp, char *value, caddr_t cp) 1618 { 1619 uint32_t status = 0, cfg_value; 1620 p_nxge_param_t pa = (p_nxge_param_t)cp; 1621 uint32_t cfg_it = B_FALSE; 1622 char *end; 1623 1624 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_tcam_enable")); 1625 1626 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1627 if (pa->value != cfg_value) { 1628 pa->old_value = pa->value; 1629 pa->value = cfg_value; 1630 cfg_it = B_TRUE; 1631 } 1632 1633 if (cfg_it == B_TRUE) { 1634 if (pa->value) 1635 status = nxge_fflp_config_tcam_enable(nxgep); 1636 else 1637 status = nxge_fflp_config_tcam_disable(nxgep); 1638 if (status != NXGE_OK) 1639 return (EINVAL); 1640 } 1641 1642 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_tcam_enable")); 1643 return (0); 1644 } 1645 1646 /* ARGSUSED */ 1647 static int 1648 nxge_param_hash_lookup_enable(p_nxge_t nxgep, queue_t *q, 1649 mblk_t *mp, char *value, caddr_t cp) 1650 { 1651 uint32_t status = 0, cfg_value; 1652 p_nxge_param_t pa = (p_nxge_param_t)cp; 1653 uint32_t cfg_it = B_FALSE; 1654 char *end; 1655 1656 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_hash_lookup_enable")); 1657 1658 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1659 if (pa->value != cfg_value) { 1660 pa->old_value = pa->value; 1661 pa->value = cfg_value; 1662 cfg_it = B_TRUE; 1663 } 1664 1665 if (cfg_it == B_TRUE) { 1666 if (pa->value) 1667 status = nxge_fflp_config_hash_lookup_enable(nxgep); 1668 else 1669 status = nxge_fflp_config_hash_lookup_disable(nxgep); 1670 if (status != NXGE_OK) 1671 return (EINVAL); 1672 } 1673 1674 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_hash_lookup_enable")); 1675 return (0); 1676 } 1677 1678 /* ARGSUSED */ 1679 static int 1680 nxge_param_llc_snap_enable(p_nxge_t nxgep, queue_t *q, 1681 mblk_t *mp, char *value, caddr_t cp) 1682 { 1683 char *end; 1684 uint32_t status = 0, cfg_value; 1685 p_nxge_param_t pa = (p_nxge_param_t)cp; 1686 uint32_t cfg_it = B_FALSE; 1687 1688 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_llc_snap_enable")); 1689 1690 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_BINARY); 1691 if (pa->value != cfg_value) { 1692 pa->old_value = pa->value; 1693 pa->value = cfg_value; 1694 cfg_it = B_TRUE; 1695 } 1696 1697 if (cfg_it == B_TRUE) { 1698 if (pa->value) 1699 status = nxge_fflp_config_tcam_enable(nxgep); 1700 else 1701 status = nxge_fflp_config_tcam_disable(nxgep); 1702 if (status != NXGE_OK) 1703 return (EINVAL); 1704 } 1705 1706 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_llc_snap_enable")); 1707 return (0); 1708 } 1709 1710 /* ARGSUSED */ 1711 static int 1712 nxge_param_set_ether_usr(p_nxge_t nxgep, queue_t *q, 1713 mblk_t *mp, char *value, caddr_t cp) 1714 { 1715 char *end; 1716 uint8_t ether_class; 1717 uint32_t status = 0, cfg_value; 1718 p_nxge_param_t pa = (p_nxge_param_t)cp; 1719 uint8_t cfg_it = B_FALSE; 1720 1721 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ether_usr")); 1722 1723 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1724 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1725 return (EINVAL); 1726 } 1727 1728 if (pa->value != cfg_value) { 1729 pa->old_value = pa->value; 1730 pa->value = cfg_value; 1731 cfg_it = B_TRUE; 1732 } 1733 1734 /* do the actual hw setup */ 1735 if (cfg_it == B_TRUE) { 1736 ether_class = mi_strtol(pa->name, &end, 10); 1737 #ifdef lint 1738 ether_class = ether_class; 1739 #endif 1740 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_ether_usr")); 1741 } 1742 1743 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ether_usr")); 1744 return (status); 1745 } 1746 1747 /* ARGSUSED */ 1748 static int 1749 nxge_param_set_ip_usr(p_nxge_t nxgep, queue_t *q, 1750 mblk_t *mp, char *value, caddr_t cp) 1751 { 1752 char *end; 1753 tcam_class_t class; 1754 uint32_t status, cfg_value; 1755 p_nxge_param_t pa = (p_nxge_param_t)cp; 1756 uint32_t cfg_it = B_FALSE; 1757 1758 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_usr")); 1759 1760 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1761 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1762 return (EINVAL); 1763 } 1764 1765 if (pa->value != cfg_value) { 1766 pa->old_value = pa->value; 1767 pa->value = cfg_value; 1768 cfg_it = B_TRUE; 1769 } 1770 1771 /* do the actual hw setup with cfg_value. */ 1772 if (cfg_it == B_TRUE) { 1773 class = mi_strtol(pa->name, &end, 10); 1774 status = nxge_fflp_ip_usr_class_config(nxgep, class, pa->value); 1775 } 1776 1777 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_usr")); 1778 return (status); 1779 } 1780 1781 /* ARGSUSED */ 1782 static int 1783 nxge_class_name_2value(p_nxge_t nxgep, char *name) 1784 { 1785 int i; 1786 int class_instance = param_class_opt_ip_usr4; 1787 p_nxge_param_t param_arr; 1788 1789 param_arr = nxgep->param_arr; 1790 for (i = TCAM_CLASS_IP_USER_4; i <= TCAM_CLASS_SCTP_IPV6; i++) { 1791 if (strcmp(param_arr[class_instance].name, name) == 0) 1792 return (i); 1793 class_instance++; 1794 } 1795 return (-1); 1796 } 1797 1798 /* ARGSUSED */ 1799 int 1800 nxge_param_set_ip_opt(p_nxge_t nxgep, queue_t *q, 1801 mblk_t *mp, char *value, caddr_t cp) 1802 { 1803 char *end; 1804 uint32_t status, cfg_value; 1805 p_nxge_param_t pa = (p_nxge_param_t)cp; 1806 tcam_class_t class; 1807 uint32_t cfg_it = B_FALSE; 1808 1809 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_ip_opt")); 1810 1811 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1812 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1813 return (EINVAL); 1814 } 1815 1816 if (pa->value != cfg_value) { 1817 pa->old_value = pa->value; 1818 pa->value = cfg_value; 1819 cfg_it = B_TRUE; 1820 } 1821 1822 if (cfg_it == B_TRUE) { 1823 /* do the actual hw setup */ 1824 class = nxge_class_name_2value(nxgep, pa->name); 1825 if (class == -1) 1826 return (EINVAL); 1827 1828 status = nxge_fflp_ip_class_config(nxgep, class, pa->value); 1829 if (status != NXGE_OK) 1830 return (EINVAL); 1831 } 1832 1833 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_ip_opt")); 1834 return (0); 1835 } 1836 1837 /* ARGSUSED */ 1838 static int 1839 nxge_param_get_ip_opt(p_nxge_t nxgep, queue_t *q, 1840 mblk_t *mp, caddr_t cp) 1841 { 1842 uint32_t status, cfg_value; 1843 p_nxge_param_t pa = (p_nxge_param_t)cp; 1844 tcam_class_t class; 1845 1846 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_ip_opt")); 1847 1848 /* do the actual hw setup */ 1849 class = nxge_class_name_2value(nxgep, pa->name); 1850 if (class == -1) 1851 return (EINVAL); 1852 1853 cfg_value = 0; 1854 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 1855 if (status != NXGE_OK) 1856 return (EINVAL); 1857 1858 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1859 "nxge_param_get_ip_opt_get %x ", cfg_value)); 1860 1861 pa->value = cfg_value; 1862 (void) mi_mpprintf(mp, "%x", cfg_value); 1863 1864 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 1865 return (0); 1866 } 1867 1868 /* ARGSUSED */ 1869 static int 1870 nxge_param_fflp_hash_init(p_nxge_t nxgep, queue_t *q, 1871 mblk_t *mp, char *value, caddr_t cp) 1872 { 1873 char *end; 1874 uint32_t status, cfg_value; 1875 p_nxge_param_t pa = (p_nxge_param_t)cp; 1876 tcam_class_t class; 1877 uint32_t cfg_it = B_FALSE; 1878 1879 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_fflp_hash_init")); 1880 1881 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_HEX); 1882 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1883 return (EINVAL); 1884 } 1885 1886 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1887 "nxge_param_fflp_hash_init value %x", cfg_value)); 1888 1889 if (pa->value != cfg_value) { 1890 pa->old_value = pa->value; 1891 pa->value = cfg_value; 1892 cfg_it = B_TRUE; 1893 } 1894 1895 if (cfg_it == B_TRUE) { 1896 char *h_name; 1897 1898 /* do the actual hw setup */ 1899 h_name = pa->name; 1900 h_name++; 1901 class = mi_strtol(h_name, &end, 10); 1902 switch (class) { 1903 case 1: 1904 status = nxge_fflp_set_hash1(nxgep, 1905 (uint32_t)pa->value); 1906 break; 1907 case 2: 1908 status = nxge_fflp_set_hash2(nxgep, 1909 (uint16_t)pa->value); 1910 break; 1911 1912 default: 1913 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1914 " nxge_param_fflp_hash_init" 1915 " %s Wrong hash var %d", 1916 pa->name, class)); 1917 return (EINVAL); 1918 } 1919 if (status != NXGE_OK) 1920 return (EINVAL); 1921 } 1922 1923 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " <== nxge_param_fflp_hash_init")); 1924 return (0); 1925 } 1926 1927 /* ARGSUSED */ 1928 static int 1929 nxge_param_set_grp_rdc(p_nxge_t nxgep, queue_t *q, 1930 mblk_t *mp, char *value, caddr_t cp) 1931 { 1932 char *end; 1933 uint32_t status = 0, cfg_value; 1934 p_nxge_param_t pa = (p_nxge_param_t)cp; 1935 uint32_t cfg_it = B_FALSE; 1936 int rdc_grp; 1937 uint8_t real_rdc; 1938 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1939 p_nxge_hw_pt_cfg_t p_cfgp; 1940 p_nxge_rdc_grp_t rdc_grp_p; 1941 1942 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 1943 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 1944 1945 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_grp_rdc")); 1946 1947 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 1948 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 1949 return (EINVAL); 1950 } 1951 1952 if (cfg_value >= p_cfgp->max_rdcs) { 1953 return (EINVAL); 1954 } 1955 1956 if (pa->value != cfg_value) { 1957 pa->old_value = pa->value; 1958 pa->value = cfg_value; 1959 cfg_it = B_TRUE; 1960 } 1961 1962 if (cfg_it == B_TRUE) { 1963 char *grp_name; 1964 grp_name = pa->name; 1965 grp_name += strlen("default-grp"); 1966 rdc_grp = mi_strtol(grp_name, &end, 10); 1967 rdc_grp_p = &p_dma_cfgp->rdc_grps[rdc_grp]; 1968 real_rdc = rdc_grp_p->start_rdc + cfg_value; 1969 if (nxge_check_rxdma_rdcgrp_member(nxgep, rdc_grp, 1970 cfg_value) == B_FALSE) { 1971 pa->value = pa->old_value; 1972 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 1973 " nxge_param_set_grp_rdc" 1974 " %d read %d actual %d outof range", 1975 rdc_grp, cfg_value, real_rdc)); 1976 return (EINVAL); 1977 } 1978 status = nxge_rxdma_cfg_rdcgrp_default_rdc(nxgep, rdc_grp, 1979 real_rdc); 1980 if (status != NXGE_OK) 1981 return (EINVAL); 1982 } 1983 1984 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_grp_rdc")); 1985 return (0); 1986 } 1987 1988 /* ARGSUSED */ 1989 static int 1990 nxge_param_set_port_rdc(p_nxge_t nxgep, queue_t *q, 1991 mblk_t *mp, char *value, caddr_t cp) 1992 { 1993 char *end; 1994 uint32_t status = B_TRUE, cfg_value; 1995 p_nxge_param_t pa = (p_nxge_param_t)cp; 1996 uint32_t cfg_it = B_FALSE; 1997 1998 p_nxge_dma_pt_cfg_t p_dma_cfgp; 1999 p_nxge_hw_pt_cfg_t p_cfgp; 2000 2001 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_port_rdc")); 2002 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2003 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2004 2005 cfg_value = (uint32_t)mi_strtol(value, &end, BASE_ANY); 2006 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2007 return (EINVAL); 2008 } 2009 2010 if (pa->value != cfg_value) { 2011 if (cfg_value >= p_cfgp->max_rdcs) 2012 return (EINVAL); 2013 pa->old_value = pa->value; 2014 pa->value = cfg_value; 2015 cfg_it = B_TRUE; 2016 } 2017 2018 if (cfg_it == B_TRUE) { 2019 int rdc; 2020 if ((rdc = nxge_dci_map(nxgep, VP_BOUND_RX, cfg_value)) < 0) 2021 return (EINVAL); 2022 status = nxge_rxdma_cfg_port_default_rdc(nxgep, 2023 nxgep->function_num, rdc); 2024 if (status != NXGE_OK) 2025 return (EINVAL); 2026 } 2027 2028 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_port_rdc")); 2029 return (0); 2030 } 2031 2032 /* ARGSUSED */ 2033 static int 2034 nxge_param_set_nxge_debug_flag(p_nxge_t nxgep, queue_t *q, 2035 mblk_t *mp, char *value, caddr_t cp) 2036 { 2037 char *end; 2038 uint32_t status = 0; 2039 uint64_t cfg_value = 0; 2040 p_nxge_param_t pa = (p_nxge_param_t)cp; 2041 uint32_t cfg_it = B_FALSE; 2042 2043 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_nxge_debug_flag")); 2044 cfg_value = mi_strtol(value, &end, BASE_HEX); 2045 2046 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2047 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2048 " nxge_param_set_nxge_debug_flag" 2049 " outof range %llx", cfg_value)); 2050 return (EINVAL); 2051 } 2052 if (pa->value != cfg_value) { 2053 pa->old_value = pa->value; 2054 pa->value = cfg_value; 2055 cfg_it = B_TRUE; 2056 } 2057 2058 if (cfg_it == B_TRUE) { 2059 nxgep->nxge_debug_level = pa->value; 2060 } 2061 2062 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_nxge_debug_flag")); 2063 return (status); 2064 } 2065 2066 /* ARGSUSED */ 2067 static int 2068 nxge_param_get_debug_flag(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2069 { 2070 int status = 0; 2071 p_nxge_param_t pa = (p_nxge_param_t)cp; 2072 2073 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_get_debug_flag")); 2074 2075 if (pa->value > 0xffffffff) 2076 (void) mi_mpprintf(mp, "%x%x", (int)(pa->value >> 32), 2077 (int)(pa->value & 0xffffffff)); 2078 else 2079 (void) mi_mpprintf(mp, "%x", (int)pa->value); 2080 2081 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_debug_flag")); 2082 return (status); 2083 } 2084 2085 /* ARGSUSED */ 2086 static int 2087 nxge_param_set_npi_debug_flag(p_nxge_t nxgep, queue_t *q, 2088 mblk_t *mp, char *value, caddr_t cp) 2089 { 2090 char *end; 2091 uint32_t status = 0; 2092 uint64_t cfg_value = 0; 2093 p_nxge_param_t pa; 2094 uint32_t cfg_it = B_FALSE; 2095 2096 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_set_npi_debug_flag")); 2097 cfg_value = mi_strtol(value, &end, BASE_HEX); 2098 pa = (p_nxge_param_t)cp; 2099 if (PARAM_OUTOF_RANGE(value, end, cfg_value, pa)) { 2100 NXGE_DEBUG_MSG((nxgep, NDD_CTL, " nxge_param_set_npi_debug_flag" 2101 " outof range %llx", cfg_value)); 2102 return (EINVAL); 2103 } 2104 if (pa->value != cfg_value) { 2105 pa->old_value = pa->value; 2106 pa->value = cfg_value; 2107 cfg_it = B_TRUE; 2108 } 2109 2110 if (cfg_it == B_TRUE) { 2111 npi_debug_level = pa->value; 2112 } 2113 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_set_debug_flag")); 2114 return (status); 2115 } 2116 2117 /* ARGSUSED */ 2118 static int 2119 nxge_param_dump_rdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2120 { 2121 nxge_grp_set_t *set = &nxgep->rx_set; 2122 int rdc; 2123 2124 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_rdc")); 2125 2126 if (!isLDOMguest(nxgep)) 2127 (void) npi_rxdma_dump_fzc_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2128 2129 for (rdc = 0; rdc < NXGE_MAX_TDCS; rdc++) { 2130 if ((1 << rdc) & set->owned.map) { 2131 (void) nxge_dump_rxdma_channel(nxgep, rdc); 2132 } 2133 } 2134 2135 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_rdc")); 2136 return (0); 2137 } 2138 2139 /* ARGSUSED */ 2140 static int 2141 nxge_param_dump_tdc(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2142 { 2143 nxge_grp_set_t *set = &nxgep->tx_set; 2144 int tdc; 2145 2146 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_tdc")); 2147 2148 for (tdc = 0; tdc < NXGE_MAX_TDCS; tdc++) { 2149 if ((1 << tdc) & set->owned.map) { 2150 (void) nxge_txdma_regs_dump(nxgep, tdc); 2151 } 2152 } 2153 2154 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_tdc")); 2155 return (0); 2156 } 2157 2158 /* ARGSUSED */ 2159 static int 2160 nxge_param_dump_fflp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2161 { 2162 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_fflp_regs")); 2163 2164 (void) npi_fflp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep)); 2165 2166 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_fflp_regs")); 2167 return (0); 2168 } 2169 2170 /* ARGSUSED */ 2171 static int 2172 nxge_param_dump_mac_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2173 { 2174 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_mac_regs")); 2175 2176 (void) npi_mac_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2177 nxgep->function_num); 2178 2179 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_mac_regs")); 2180 return (0); 2181 } 2182 2183 /* ARGSUSED */ 2184 static int 2185 nxge_param_dump_ipp_regs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2186 { 2187 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_param_dump_ipp_regs")); 2188 2189 (void) npi_ipp_dump_regs(NXGE_DEV_NPI_HANDLE(nxgep), 2190 nxgep->function_num); 2191 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ipp_regs")); 2192 return (0); 2193 } 2194 2195 /* ARGSUSED */ 2196 static int 2197 nxge_param_dump_vlan_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2198 { 2199 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_vlan_table")); 2200 2201 (void) npi_fflp_vlan_tbl_dump(NXGE_DEV_NPI_HANDLE(nxgep)); 2202 2203 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_vlan_table")); 2204 return (0); 2205 } 2206 2207 /* ARGSUSED */ 2208 static int 2209 nxge_param_dump_rdc_table(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2210 { 2211 uint8_t table; 2212 2213 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_dump_rdc_table")); 2214 for (table = 0; table < NXGE_MAX_RDC_GROUPS; table++) { 2215 (void) npi_rxdma_dump_rdc_table(NXGE_DEV_NPI_HANDLE(nxgep), 2216 table); 2217 } 2218 2219 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_dump_rdc_table")); 2220 return (0); 2221 } 2222 2223 typedef struct block_info { 2224 char *name; 2225 uint32_t offset; 2226 } block_info_t; 2227 2228 block_info_t reg_block[] = { 2229 {"PIO", PIO}, 2230 {"FZC_PIO", FZC_PIO}, 2231 {"FZC_XMAC", FZC_MAC}, 2232 {"FZC_IPP", FZC_IPP}, 2233 {"FFLP", FFLP}, 2234 {"FZC_FFLP", FZC_FFLP}, 2235 {"PIO_VADDR", PIO_VADDR}, 2236 {"ZCP", ZCP}, 2237 {"FZC_ZCP", FZC_ZCP}, 2238 {"DMC", DMC}, 2239 {"FZC_DMC", FZC_DMC}, 2240 {"TXC", TXC}, 2241 {"FZC_TXC", FZC_TXC}, 2242 {"PIO_LDSV", PIO_LDSV}, 2243 {"PIO_LDGIM", PIO_LDGIM}, 2244 {"PIO_IMASK0", PIO_IMASK0}, 2245 {"PIO_IMASK1", PIO_IMASK1}, 2246 {"FZC_PROM", FZC_PROM}, 2247 {"END", ALL_FF_32}, 2248 }; 2249 2250 /* ARGSUSED */ 2251 static int 2252 nxge_param_dump_ptrs(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t cp) 2253 { 2254 uint_t print_len, buf_len; 2255 p_mblk_t np; 2256 int rdc, tdc, block; 2257 uint64_t base; 2258 p_nxge_dma_pt_cfg_t p_dma_cfgp; 2259 p_nxge_hw_pt_cfg_t p_cfgp; 2260 int buff_alloc_size = NXGE_NDD_INFODUMP_BUFF_8K; 2261 p_tx_ring_t *tx_rings; 2262 p_rx_rcr_rings_t rx_rcr_rings; 2263 p_rx_rcr_ring_t *rcr_rings; 2264 p_rx_rbr_rings_t rx_rbr_rings; 2265 p_rx_rbr_ring_t *rbr_rings; 2266 2267 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 2268 "==> nxge_param_dump_ptrs")); 2269 2270 (void) mi_mpprintf(mp, "ptr information for Port\t %d \n", 2271 nxgep->function_num); 2272 2273 if ((np = allocb(buff_alloc_size, BPRI_HI)) == NULL) { 2274 /* The following may work even if we cannot get a large buf. */ 2275 (void) mi_mpprintf(mp, "%s\n", "out of buffer"); 2276 return (0); 2277 } 2278 2279 buf_len = buff_alloc_size; 2280 mp->b_cont = np; 2281 p_dma_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2282 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 2283 2284 rx_rcr_rings = nxgep->rx_rcr_rings; 2285 rcr_rings = rx_rcr_rings->rcr_rings; 2286 rx_rbr_rings = nxgep->rx_rbr_rings; 2287 rbr_rings = rx_rbr_rings->rbr_rings; 2288 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2289 "nxgep (nxge_t) $%p\n" 2290 "dev_regs (dev_regs_t) $%p\n", 2291 nxgep, nxgep->dev_regs); 2292 2293 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2294 2295 /* do register pointers */ 2296 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2297 "reg base (npi_reg_ptr_t) $%p\t " 2298 "pci reg (npi_reg_ptr_t) $%p\n", 2299 nxgep->dev_regs->nxge_regp, 2300 nxgep->dev_regs->nxge_pciregp); 2301 2302 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2303 2304 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2305 "\nBlock \t Offset \n"); 2306 2307 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2308 block = 0; 2309 #if defined(__i386) 2310 base = (uint64_t)(uint32_t)nxgep->dev_regs->nxge_regp; 2311 #else 2312 base = (uint64_t)nxgep->dev_regs->nxge_regp; 2313 #endif 2314 while (reg_block[block].offset != ALL_FF_32) { 2315 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2316 "%9s\t 0x%llx\n", 2317 reg_block[block].name, 2318 (unsigned long long)(reg_block[block].offset + base)); 2319 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2320 block++; 2321 } 2322 2323 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2324 "\nRDC\t rcrp (rx_rcr_ring_t)\t " 2325 "rbrp (rx_rbr_ring_t)\n"); 2326 2327 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2328 2329 for (rdc = 0; rdc < p_cfgp->max_rdcs; rdc++) { 2330 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2331 " %d\t $%p\t\t $%p\n", 2332 rdc, rcr_rings[rdc], 2333 rbr_rings[rdc]); 2334 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2335 } 2336 2337 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2338 "\nTDC\t tdcp (tx_ring_t)\n"); 2339 2340 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2341 tx_rings = nxgep->tx_rings->rings; 2342 for (tdc = 0; tdc < p_cfgp->tdc.count; tdc++) { 2343 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, 2344 " %d\t $%p\n", tdc, tx_rings[tdc]); 2345 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2346 } 2347 2348 print_len = snprintf((char *)((mblk_t *)np)->b_wptr, buf_len, "\n\n"); 2349 2350 ADVANCE_PRINT_BUFFER(np, print_len, buf_len); 2351 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_param_dump_ptrs")); 2352 return (0); 2353 } 2354 2355 2356 /* ARGSUSED */ 2357 int 2358 nxge_nd_get_names(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t param) 2359 { 2360 ND *nd; 2361 NDE *nde; 2362 char *rwtag; 2363 boolean_t get_ok, set_ok; 2364 size_t param_len; 2365 int status = 0; 2366 2367 nd = (ND *)param; 2368 if (!nd) 2369 return (ENOENT); 2370 2371 for (nde = nd->nd_tbl; nde->nde_name; nde++) { 2372 get_ok = (nde->nde_get_pfi != nxge_get_default) && 2373 (nde->nde_get_pfi != NULL); 2374 set_ok = (nde->nde_set_pfi != nxge_set_default) && 2375 (nde->nde_set_pfi != NULL); 2376 if (get_ok) { 2377 if (set_ok) 2378 rwtag = "read and write"; 2379 else 2380 rwtag = "read only"; 2381 } else if (set_ok) 2382 rwtag = "write only"; 2383 else { 2384 continue; 2385 } 2386 param_len = strlen(rwtag); 2387 param_len += strlen(nde->nde_name); 2388 param_len += 4; 2389 2390 (void) mi_mpprintf(mp, "%s (%s)", nde->nde_name, rwtag); 2391 } 2392 return (status); 2393 } 2394 2395 /* ARGSUSED */ 2396 int 2397 nxge_get_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, caddr_t data) 2398 { 2399 return (EACCES); 2400 } 2401 2402 /* ARGSUSED */ 2403 int 2404 nxge_set_default(p_nxge_t nxgep, queue_t *q, p_mblk_t mp, char *value, 2405 caddr_t data) 2406 { 2407 return (EACCES); 2408 } 2409 2410 boolean_t 2411 nxge_param_link_update(p_nxge_t nxgep) 2412 { 2413 p_nxge_param_t param_arr; 2414 nxge_param_index_t i; 2415 boolean_t update_xcvr; 2416 boolean_t update_dev; 2417 int instance; 2418 boolean_t status = B_TRUE; 2419 2420 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_param_link_update")); 2421 2422 param_arr = nxgep->param_arr; 2423 instance = nxgep->instance; 2424 update_xcvr = B_FALSE; 2425 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) { 2426 update_xcvr |= param_arr[i].value; 2427 } 2428 2429 if (update_xcvr) { 2430 update_xcvr = B_FALSE; 2431 for (i = param_autoneg; i < param_enable_ipg0; i++) { 2432 update_xcvr |= 2433 (param_arr[i].value != param_arr[i].old_value); 2434 param_arr[i].old_value = param_arr[i].value; 2435 } 2436 if (update_xcvr) { 2437 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2438 "==> nxge_param_link_update: update xcvr")); 2439 RW_ENTER_WRITER(&nxgep->filter_lock); 2440 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2441 (void) nxge_link_init(nxgep); 2442 (void) nxge_mac_init(nxgep); 2443 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 2444 RW_EXIT(&nxgep->filter_lock); 2445 } 2446 } else { 2447 cmn_err(CE_WARN, " Last setting will leave nxge%d with " 2448 " no link capabilities.", instance); 2449 cmn_err(CE_WARN, " Restoring previous setting."); 2450 for (i = param_anar_1000fdx; i < param_anar_asmpause; i++) 2451 param_arr[i].value = param_arr[i].old_value; 2452 } 2453 2454 update_dev = B_FALSE; 2455 2456 if (update_dev) { 2457 RW_ENTER_WRITER(&nxgep->filter_lock); 2458 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2459 "==> nxge_param_link_update: update dev")); 2460 (void) nxge_rx_mac_disable(nxgep); 2461 (void) nxge_tx_mac_disable(nxgep); 2462 (void) nxge_tx_mac_enable(nxgep); 2463 (void) nxge_rx_mac_enable(nxgep); 2464 RW_EXIT(&nxgep->filter_lock); 2465 } 2466 2467 nxge_param_hw_update_exit: 2468 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2469 "<== nxge_param_link_update status = 0x%08x", status)); 2470 return (status); 2471 } 2472 2473 /* 2474 * synchronize the adv* and en* parameters. 2475 * 2476 * See comments in <sys/dld.h> for details of the *_en_* 2477 * parameters. The usage of ndd for setting adv parameters will 2478 * synchronize all the en parameters with the nxge parameters, 2479 * implicitly disabling any settings made via dladm. 2480 */ 2481 static void 2482 nxge_param_sync(p_nxge_t nxgep) 2483 { 2484 p_nxge_param_t param_arr; 2485 param_arr = nxgep->param_arr; 2486 2487 nxgep->param_en_pause = param_arr[param_anar_pause].value; 2488 nxgep->param_en_1000fdx = param_arr[param_anar_1000fdx].value; 2489 nxgep->param_en_100fdx = param_arr[param_anar_100fdx].value; 2490 nxgep->param_en_10fdx = param_arr[param_anar_10fdx].value; 2491 } 2492 2493 /* ARGSUSED */ 2494 int 2495 nxge_dld_get_ip_opt(p_nxge_t nxgep, caddr_t cp) 2496 { 2497 uint32_t status, cfg_value; 2498 p_nxge_param_t pa = (p_nxge_param_t)cp; 2499 tcam_class_t class; 2500 2501 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "==> nxge_dld_get_ip_opt")); 2502 2503 /* do the actual hw setup */ 2504 class = nxge_class_name_2value(nxgep, pa->name); 2505 if (class == -1) 2506 return (EINVAL); 2507 2508 cfg_value = 0; 2509 status = nxge_fflp_ip_class_config_get(nxgep, class, &cfg_value); 2510 if (status != NXGE_OK) 2511 return (EINVAL); 2512 2513 NXGE_DEBUG_MSG((nxgep, NDD_CTL, 2514 "nxge_param_get_ip_opt_get %x ", cfg_value)); 2515 2516 pa->value = cfg_value; 2517 2518 NXGE_DEBUG_MSG((nxgep, NDD_CTL, "<== nxge_param_get_ip_opt status ")); 2519 return (0); 2520 } 2521