1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * SunOs MT STREAMS NIU/Neptune 10Gb Ethernet Device Driver. 28 */ 29 #include <sys/nxge/nxge_impl.h> 30 #include <sys/nxge/nxge_hio.h> 31 #include <sys/nxge/nxge_rxdma.h> 32 #include <sys/pcie.h> 33 34 uint32_t nxge_use_partition = 0; /* debug partition flag */ 35 uint32_t nxge_dma_obp_props_only = 1; /* use obp published props */ 36 uint32_t nxge_use_rdc_intr = 1; /* debug to assign rdc intr */ 37 /* 38 * PSARC/2007/453 MSI-X interrupt limit override 39 * (This PSARC case is limited to MSI-X vectors 40 * and SPARC platforms only). 41 */ 42 #if defined(_BIG_ENDIAN) 43 uint32_t nxge_msi_enable = 2; 44 #else 45 uint32_t nxge_msi_enable = 1; 46 #endif 47 48 /* 49 * Software workaround for a Neptune (PCI-E) 50 * hardware interrupt bug which the hardware 51 * may generate spurious interrupts after the 52 * device interrupt handler was removed. If this flag 53 * is enabled, the driver will reset the 54 * hardware when devices are being detached. 55 */ 56 uint32_t nxge_peu_reset_enable = 0; 57 58 /* 59 * Software workaround for the hardware 60 * checksum bugs that affect packet transmission 61 * and receive: 62 * 63 * Usage of nxge_cksum_offload: 64 * 65 * (1) nxge_cksum_offload = 0 (default): 66 * - transmits packets: 67 * TCP: uses the hardware checksum feature. 68 * UDP: driver will compute the software checksum 69 * based on the partial checksum computed 70 * by the IP layer. 71 * - receives packets 72 * TCP: marks packets checksum flags based on hardware result. 73 * UDP: will not mark checksum flags. 74 * 75 * (2) nxge_cksum_offload = 1: 76 * - transmit packets: 77 * TCP/UDP: uses the hardware checksum feature. 78 * - receives packets 79 * TCP/UDP: marks packet checksum flags based on hardware result. 80 * 81 * (3) nxge_cksum_offload = 2: 82 * - The driver will not register its checksum capability. 83 * Checksum for both TCP and UDP will be computed 84 * by the stack. 85 * - The software LSO is not allowed in this case. 86 * 87 * (4) nxge_cksum_offload > 2: 88 * - Will be treated as it is set to 2 89 * (stack will compute the checksum). 90 * 91 * (5) If the hardware bug is fixed, this workaround 92 * needs to be updated accordingly to reflect 93 * the new hardware revision. 94 */ 95 uint32_t nxge_cksum_offload = 0; 96 97 /* 98 * Globals: tunable parameters (/etc/system or adb) 99 * 100 */ 101 uint32_t nxge_rbr_size = NXGE_RBR_RBB_DEFAULT; 102 uint32_t nxge_rbr_spare_size = 0; 103 uint32_t nxge_rcr_size = NXGE_RCR_DEFAULT; 104 uint32_t nxge_tx_ring_size = NXGE_TX_RING_DEFAULT; 105 boolean_t nxge_no_msg = B_TRUE; /* control message display */ 106 uint32_t nxge_no_link_notify = 0; /* control DL_NOTIFY */ 107 uint32_t nxge_bcopy_thresh = TX_BCOPY_MAX; 108 uint32_t nxge_dvma_thresh = TX_FASTDVMA_MIN; 109 uint32_t nxge_dma_stream_thresh = TX_STREAM_MIN; 110 uint32_t nxge_jumbo_mtu = TX_JUMBO_MTU; 111 boolean_t nxge_jumbo_enable = B_FALSE; 112 uint16_t nxge_rcr_timeout = NXGE_RDC_RCR_TIMEOUT; 113 uint16_t nxge_rcr_threshold = NXGE_RDC_RCR_THRESHOLD; 114 nxge_tx_mode_t nxge_tx_scheme = NXGE_USE_SERIAL; 115 116 /* MAX LSO size */ 117 #define NXGE_LSO_MAXLEN 65535 118 uint32_t nxge_lso_max = NXGE_LSO_MAXLEN; 119 120 /* 121 * Debugging flags: 122 * nxge_no_tx_lb : transmit load balancing 123 * nxge_tx_lb_policy: 0 - TCP port (default) 124 * 3 - DEST MAC 125 */ 126 uint32_t nxge_no_tx_lb = 0; 127 uint32_t nxge_tx_lb_policy = NXGE_TX_LB_TCPUDP; 128 129 /* 130 * Add tunable to reduce the amount of time spent in the 131 * ISR doing Rx Processing. 132 */ 133 uint32_t nxge_max_rx_pkts = 1024; 134 135 /* 136 * Tunables to manage the receive buffer blocks. 137 * 138 * nxge_rx_threshold_hi: copy all buffers. 139 * nxge_rx_bcopy_size_type: receive buffer block size type. 140 * nxge_rx_threshold_lo: copy only up to tunable block size type. 141 */ 142 nxge_rxbuf_threshold_t nxge_rx_threshold_hi = NXGE_RX_COPY_6; 143 nxge_rxbuf_type_t nxge_rx_buf_size_type = RCR_PKTBUFSZ_0; 144 nxge_rxbuf_threshold_t nxge_rx_threshold_lo = NXGE_RX_COPY_3; 145 146 /* Use kmem_alloc() to allocate data buffers. */ 147 #if defined(_BIG_ENDIAN) 148 uint32_t nxge_use_kmem_alloc = 1; 149 #else 150 uint32_t nxge_use_kmem_alloc = 0; 151 #endif 152 153 rtrace_t npi_rtracebuf; 154 155 /* 156 * The hardware sometimes fails to allow enough time for the link partner 157 * to send an acknowledgement for packets that the hardware sent to it. The 158 * hardware resends the packets earlier than it should be in those instances. 159 * This behavior caused some switches to acknowledge the wrong packets 160 * and it triggered the fatal error. 161 * This software workaround is to set the replay timer to a value 162 * suggested by the hardware team. 163 * 164 * PCI config space replay timer register: 165 * The following replay timeout value is 0xc 166 * for bit 14:18. 167 */ 168 #define PCI_REPLAY_TIMEOUT_CFG_OFFSET 0xb8 169 #define PCI_REPLAY_TIMEOUT_SHIFT 14 170 171 uint32_t nxge_set_replay_timer = 1; 172 uint32_t nxge_replay_timeout = 0xc; 173 174 /* 175 * The transmit serialization sometimes causes 176 * longer sleep before calling the driver transmit 177 * function as it sleeps longer than it should. 178 * The performace group suggests that a time wait tunable 179 * can be used to set the maximum wait time when needed 180 * and the default is set to 1 tick. 181 */ 182 uint32_t nxge_tx_serial_maxsleep = 1; 183 184 #if defined(sun4v) 185 /* 186 * Hypervisor N2/NIU services information. 187 */ 188 static hsvc_info_t niu_hsvc = { 189 HSVC_REV_1, NULL, HSVC_GROUP_NIU, NIU_MAJOR_VER, 190 NIU_MINOR_VER, "nxge" 191 }; 192 193 static int nxge_hsvc_register(p_nxge_t); 194 #endif 195 196 /* 197 * Function Prototypes 198 */ 199 static int nxge_attach(dev_info_t *, ddi_attach_cmd_t); 200 static int nxge_detach(dev_info_t *, ddi_detach_cmd_t); 201 static void nxge_unattach(p_nxge_t); 202 static int nxge_quiesce(dev_info_t *); 203 204 #if NXGE_PROPERTY 205 static void nxge_remove_hard_properties(p_nxge_t); 206 #endif 207 208 /* 209 * These two functions are required by nxge_hio.c 210 */ 211 extern int nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr); 212 extern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot); 213 extern void nxge_grp_cleanup(p_nxge_t nxge); 214 215 static nxge_status_t nxge_setup_system_dma_pages(p_nxge_t); 216 217 static nxge_status_t nxge_setup_mutexes(p_nxge_t); 218 static void nxge_destroy_mutexes(p_nxge_t); 219 220 static nxge_status_t nxge_map_regs(p_nxge_t nxgep); 221 static void nxge_unmap_regs(p_nxge_t nxgep); 222 #ifdef NXGE_DEBUG 223 static void nxge_test_map_regs(p_nxge_t nxgep); 224 #endif 225 226 static nxge_status_t nxge_add_intrs(p_nxge_t nxgep); 227 static nxge_status_t nxge_add_soft_intrs(p_nxge_t nxgep); 228 static void nxge_remove_intrs(p_nxge_t nxgep); 229 static void nxge_remove_soft_intrs(p_nxge_t nxgep); 230 231 static nxge_status_t nxge_add_intrs_adv(p_nxge_t nxgep); 232 static nxge_status_t nxge_add_intrs_adv_type(p_nxge_t, uint32_t); 233 static nxge_status_t nxge_add_intrs_adv_type_fix(p_nxge_t, uint32_t); 234 static void nxge_intrs_enable(p_nxge_t nxgep); 235 static void nxge_intrs_disable(p_nxge_t nxgep); 236 237 static void nxge_suspend(p_nxge_t); 238 static nxge_status_t nxge_resume(p_nxge_t); 239 240 static nxge_status_t nxge_setup_dev(p_nxge_t); 241 static void nxge_destroy_dev(p_nxge_t); 242 243 static nxge_status_t nxge_alloc_mem_pool(p_nxge_t); 244 static void nxge_free_mem_pool(p_nxge_t); 245 246 nxge_status_t nxge_alloc_rx_mem_pool(p_nxge_t); 247 static void nxge_free_rx_mem_pool(p_nxge_t); 248 249 nxge_status_t nxge_alloc_tx_mem_pool(p_nxge_t); 250 static void nxge_free_tx_mem_pool(p_nxge_t); 251 252 static nxge_status_t nxge_dma_mem_alloc(p_nxge_t, dma_method_t, 253 struct ddi_dma_attr *, 254 size_t, ddi_device_acc_attr_t *, uint_t, 255 p_nxge_dma_common_t); 256 257 static void nxge_dma_mem_free(p_nxge_dma_common_t); 258 static void nxge_dma_free_rx_data_buf(p_nxge_dma_common_t); 259 260 static nxge_status_t nxge_alloc_rx_buf_dma(p_nxge_t, uint16_t, 261 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 262 static void nxge_free_rx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 263 264 static nxge_status_t nxge_alloc_rx_cntl_dma(p_nxge_t, uint16_t, 265 p_nxge_dma_common_t *, size_t); 266 static void nxge_free_rx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 267 268 extern nxge_status_t nxge_alloc_tx_buf_dma(p_nxge_t, uint16_t, 269 p_nxge_dma_common_t *, size_t, size_t, uint32_t *); 270 static void nxge_free_tx_buf_dma(p_nxge_t, p_nxge_dma_common_t, uint32_t); 271 272 extern nxge_status_t nxge_alloc_tx_cntl_dma(p_nxge_t, uint16_t, 273 p_nxge_dma_common_t *, 274 size_t); 275 static void nxge_free_tx_cntl_dma(p_nxge_t, p_nxge_dma_common_t); 276 277 static int nxge_init_common_dev(p_nxge_t); 278 static void nxge_uninit_common_dev(p_nxge_t); 279 extern int nxge_param_set_mac(p_nxge_t, queue_t *, mblk_t *, 280 char *, caddr_t); 281 282 /* 283 * The next declarations are for the GLDv3 interface. 284 */ 285 static int nxge_m_start(void *); 286 static void nxge_m_stop(void *); 287 static int nxge_m_unicst(void *, const uint8_t *); 288 static int nxge_m_multicst(void *, boolean_t, const uint8_t *); 289 static int nxge_m_promisc(void *, boolean_t); 290 static void nxge_m_ioctl(void *, queue_t *, mblk_t *); 291 static void nxge_m_resources(void *); 292 mblk_t *nxge_m_tx(void *arg, mblk_t *); 293 static nxge_status_t nxge_mac_register(p_nxge_t); 294 int nxge_altmac_set(p_nxge_t nxgep, uint8_t *mac_addr, 295 mac_addr_slot_t slot, uint8_t rdctbl); 296 void nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, 297 boolean_t factory); 298 static int nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr); 299 static int nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr); 300 static int nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr); 301 static boolean_t nxge_m_getcapab(void *, mac_capab_t, void *); 302 static int nxge_m_setprop(void *, const char *, mac_prop_id_t, 303 uint_t, const void *); 304 static int nxge_m_getprop(void *, const char *, mac_prop_id_t, 305 uint_t, uint_t, void *); 306 static int nxge_set_priv_prop(nxge_t *, const char *, uint_t, 307 const void *); 308 static int nxge_get_priv_prop(nxge_t *, const char *, uint_t, uint_t, 309 void *); 310 static int nxge_get_def_val(nxge_t *, mac_prop_id_t, uint_t, void *); 311 312 static void nxge_niu_peu_reset(p_nxge_t nxgep); 313 static void nxge_set_pci_replay_timeout(nxge_t *); 314 315 mac_priv_prop_t nxge_priv_props[] = { 316 {"_adv_10gfdx_cap", MAC_PROP_PERM_RW}, 317 {"_adv_pause_cap", MAC_PROP_PERM_RW}, 318 {"_function_number", MAC_PROP_PERM_READ}, 319 {"_fw_version", MAC_PROP_PERM_READ}, 320 {"_port_mode", MAC_PROP_PERM_READ}, 321 {"_hot_swap_phy", MAC_PROP_PERM_READ}, 322 {"_accept_jumbo", MAC_PROP_PERM_RW}, 323 {"_rxdma_intr_time", MAC_PROP_PERM_RW}, 324 {"_rxdma_intr_pkts", MAC_PROP_PERM_RW}, 325 {"_class_opt_ipv4_tcp", MAC_PROP_PERM_RW}, 326 {"_class_opt_ipv4_udp", MAC_PROP_PERM_RW}, 327 {"_class_opt_ipv4_ah", MAC_PROP_PERM_RW}, 328 {"_class_opt_ipv4_sctp", MAC_PROP_PERM_RW}, 329 {"_class_opt_ipv6_tcp", MAC_PROP_PERM_RW}, 330 {"_class_opt_ipv6_udp", MAC_PROP_PERM_RW}, 331 {"_class_opt_ipv6_ah", MAC_PROP_PERM_RW}, 332 {"_class_opt_ipv6_sctp", MAC_PROP_PERM_RW}, 333 {"_soft_lso_enable", MAC_PROP_PERM_RW} 334 }; 335 336 #define NXGE_MAX_PRIV_PROPS \ 337 (sizeof (nxge_priv_props)/sizeof (mac_priv_prop_t)) 338 339 #define NXGE_M_CALLBACK_FLAGS\ 340 (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 341 342 343 #define NXGE_NEPTUNE_MAGIC 0x4E584745UL 344 #define MAX_DUMP_SZ 256 345 346 #define NXGE_M_CALLBACK_FLAGS \ 347 (MC_RESOURCES | MC_IOCTL | MC_GETCAPAB | MC_SETPROP | MC_GETPROP) 348 349 mac_callbacks_t nxge_m_callbacks = { 350 NXGE_M_CALLBACK_FLAGS, 351 nxge_m_stat, 352 nxge_m_start, 353 nxge_m_stop, 354 nxge_m_promisc, 355 nxge_m_multicst, 356 nxge_m_unicst, 357 nxge_m_tx, 358 nxge_m_resources, 359 nxge_m_ioctl, 360 nxge_m_getcapab, 361 NULL, 362 NULL, 363 nxge_m_setprop, 364 nxge_m_getprop 365 }; 366 367 void 368 nxge_err_inject(p_nxge_t, queue_t *, mblk_t *); 369 370 /* PSARC/2007/453 MSI-X interrupt limit override. */ 371 #define NXGE_MSIX_REQUEST_10G 8 372 #define NXGE_MSIX_REQUEST_1G 2 373 static int nxge_create_msi_property(p_nxge_t); 374 375 /* 376 * These global variables control the message 377 * output. 378 */ 379 out_dbgmsg_t nxge_dbgmsg_out = DBG_CONSOLE | STR_LOG; 380 uint64_t nxge_debug_level; 381 382 /* 383 * This list contains the instance structures for the Neptune 384 * devices present in the system. The lock exists to guarantee 385 * mutually exclusive access to the list. 386 */ 387 void *nxge_list = NULL; 388 389 void *nxge_hw_list = NULL; 390 nxge_os_mutex_t nxge_common_lock; 391 392 extern uint64_t npi_debug_level; 393 394 extern nxge_status_t nxge_ldgv_init(p_nxge_t, int *, int *); 395 extern nxge_status_t nxge_ldgv_init_n2(p_nxge_t, int *, int *); 396 extern nxge_status_t nxge_ldgv_uninit(p_nxge_t); 397 extern nxge_status_t nxge_intr_ldgv_init(p_nxge_t); 398 extern void nxge_fm_init(p_nxge_t, 399 ddi_device_acc_attr_t *, 400 ddi_device_acc_attr_t *, 401 ddi_dma_attr_t *); 402 extern void nxge_fm_fini(p_nxge_t); 403 extern npi_status_t npi_mac_altaddr_disable(npi_handle_t, uint8_t, uint8_t); 404 405 /* 406 * Count used to maintain the number of buffers being used 407 * by Neptune instances and loaned up to the upper layers. 408 */ 409 uint32_t nxge_mblks_pending = 0; 410 411 /* 412 * Device register access attributes for PIO. 413 */ 414 static ddi_device_acc_attr_t nxge_dev_reg_acc_attr = { 415 DDI_DEVICE_ATTR_V0, 416 DDI_STRUCTURE_LE_ACC, 417 DDI_STRICTORDER_ACC, 418 }; 419 420 /* 421 * Device descriptor access attributes for DMA. 422 */ 423 static ddi_device_acc_attr_t nxge_dev_desc_dma_acc_attr = { 424 DDI_DEVICE_ATTR_V0, 425 DDI_STRUCTURE_LE_ACC, 426 DDI_STRICTORDER_ACC 427 }; 428 429 /* 430 * Device buffer access attributes for DMA. 431 */ 432 static ddi_device_acc_attr_t nxge_dev_buf_dma_acc_attr = { 433 DDI_DEVICE_ATTR_V0, 434 DDI_STRUCTURE_BE_ACC, 435 DDI_STRICTORDER_ACC 436 }; 437 438 ddi_dma_attr_t nxge_desc_dma_attr = { 439 DMA_ATTR_V0, /* version number. */ 440 0, /* low address */ 441 0xffffffffffffffff, /* high address */ 442 0xffffffffffffffff, /* address counter max */ 443 #ifndef NIU_PA_WORKAROUND 444 0x100000, /* alignment */ 445 #else 446 0x2000, 447 #endif 448 0xfc00fc, /* dlim_burstsizes */ 449 0x1, /* minimum transfer size */ 450 0xffffffffffffffff, /* maximum transfer size */ 451 0xffffffffffffffff, /* maximum segment size */ 452 1, /* scatter/gather list length */ 453 (unsigned int) 1, /* granularity */ 454 0 /* attribute flags */ 455 }; 456 457 ddi_dma_attr_t nxge_tx_dma_attr = { 458 DMA_ATTR_V0, /* version number. */ 459 0, /* low address */ 460 0xffffffffffffffff, /* high address */ 461 0xffffffffffffffff, /* address counter max */ 462 #if defined(_BIG_ENDIAN) 463 0x2000, /* alignment */ 464 #else 465 0x1000, /* alignment */ 466 #endif 467 0xfc00fc, /* dlim_burstsizes */ 468 0x1, /* minimum transfer size */ 469 0xffffffffffffffff, /* maximum transfer size */ 470 0xffffffffffffffff, /* maximum segment size */ 471 5, /* scatter/gather list length */ 472 (unsigned int) 1, /* granularity */ 473 0 /* attribute flags */ 474 }; 475 476 ddi_dma_attr_t nxge_rx_dma_attr = { 477 DMA_ATTR_V0, /* version number. */ 478 0, /* low address */ 479 0xffffffffffffffff, /* high address */ 480 0xffffffffffffffff, /* address counter max */ 481 0x2000, /* alignment */ 482 0xfc00fc, /* dlim_burstsizes */ 483 0x1, /* minimum transfer size */ 484 0xffffffffffffffff, /* maximum transfer size */ 485 0xffffffffffffffff, /* maximum segment size */ 486 1, /* scatter/gather list length */ 487 (unsigned int) 1, /* granularity */ 488 DDI_DMA_RELAXED_ORDERING /* attribute flags */ 489 }; 490 491 ddi_dma_lim_t nxge_dma_limits = { 492 (uint_t)0, /* dlim_addr_lo */ 493 (uint_t)0xffffffff, /* dlim_addr_hi */ 494 (uint_t)0xffffffff, /* dlim_cntr_max */ 495 (uint_t)0xfc00fc, /* dlim_burstsizes for 32 and 64 bit xfers */ 496 0x1, /* dlim_minxfer */ 497 1024 /* dlim_speed */ 498 }; 499 500 dma_method_t nxge_force_dma = DVMA; 501 502 /* 503 * dma chunk sizes. 504 * 505 * Try to allocate the largest possible size 506 * so that fewer number of dma chunks would be managed 507 */ 508 #ifdef NIU_PA_WORKAROUND 509 size_t alloc_sizes [] = {0x2000}; 510 #else 511 size_t alloc_sizes [] = {0x1000, 0x2000, 0x4000, 0x8000, 512 0x10000, 0x20000, 0x40000, 0x80000, 513 0x100000, 0x200000, 0x400000, 0x800000, 514 0x1000000, 0x2000000, 0x4000000}; 515 #endif 516 517 /* 518 * Translate "dev_t" to a pointer to the associated "dev_info_t". 519 */ 520 521 extern void nxge_get_environs(nxge_t *); 522 523 static int 524 nxge_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 525 { 526 p_nxge_t nxgep = NULL; 527 int instance; 528 int status = DDI_SUCCESS; 529 uint8_t portn; 530 nxge_mmac_t *mmac_info; 531 p_nxge_param_t param_arr; 532 533 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_attach")); 534 535 /* 536 * Get the device instance since we'll need to setup 537 * or retrieve a soft state for this instance. 538 */ 539 instance = ddi_get_instance(dip); 540 541 switch (cmd) { 542 case DDI_ATTACH: 543 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_ATTACH")); 544 break; 545 546 case DDI_RESUME: 547 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_RESUME")); 548 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 549 if (nxgep == NULL) { 550 status = DDI_FAILURE; 551 break; 552 } 553 if (nxgep->dip != dip) { 554 status = DDI_FAILURE; 555 break; 556 } 557 if (nxgep->suspended == DDI_PM_SUSPEND) { 558 status = ddi_dev_is_needed(nxgep->dip, 0, 1); 559 } else { 560 status = nxge_resume(nxgep); 561 } 562 goto nxge_attach_exit; 563 564 case DDI_PM_RESUME: 565 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_RESUME")); 566 nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 567 if (nxgep == NULL) { 568 status = DDI_FAILURE; 569 break; 570 } 571 if (nxgep->dip != dip) { 572 status = DDI_FAILURE; 573 break; 574 } 575 status = nxge_resume(nxgep); 576 goto nxge_attach_exit; 577 578 default: 579 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing unknown")); 580 status = DDI_FAILURE; 581 goto nxge_attach_exit; 582 } 583 584 585 if (ddi_soft_state_zalloc(nxge_list, instance) == DDI_FAILURE) { 586 status = DDI_FAILURE; 587 goto nxge_attach_exit; 588 } 589 590 nxgep = ddi_get_soft_state(nxge_list, instance); 591 if (nxgep == NULL) { 592 status = NXGE_ERROR; 593 goto nxge_attach_fail2; 594 } 595 596 nxgep->nxge_magic = NXGE_MAGIC; 597 598 nxgep->drv_state = 0; 599 nxgep->dip = dip; 600 nxgep->instance = instance; 601 nxgep->p_dip = ddi_get_parent(dip); 602 nxgep->nxge_debug_level = nxge_debug_level; 603 npi_debug_level = nxge_debug_level; 604 605 /* Are we a guest running in a Hybrid I/O environment? */ 606 nxge_get_environs(nxgep); 607 608 status = nxge_map_regs(nxgep); 609 610 if (status != NXGE_OK) { 611 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_map_regs failed")); 612 goto nxge_attach_fail3; 613 } 614 615 nxge_fm_init(nxgep, &nxge_dev_reg_acc_attr, 616 &nxge_dev_desc_dma_acc_attr, 617 &nxge_rx_dma_attr); 618 619 /* Create & initialize the per-Neptune data structure */ 620 /* (even if we're a guest). */ 621 status = nxge_init_common_dev(nxgep); 622 if (status != NXGE_OK) { 623 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 624 "nxge_init_common_dev failed")); 625 goto nxge_attach_fail4; 626 } 627 628 /* 629 * Software workaround: set the replay timer. 630 */ 631 if (nxgep->niu_type != N2_NIU) { 632 nxge_set_pci_replay_timeout(nxgep); 633 } 634 635 #if defined(sun4v) 636 /* This is required by nxge_hio_init(), which follows. */ 637 if ((status = nxge_hsvc_register(nxgep)) != DDI_SUCCESS) 638 goto nxge_attach_fail4; 639 #endif 640 641 if ((status = nxge_hio_init(nxgep)) != NXGE_OK) { 642 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 643 "nxge_hio_init failed")); 644 goto nxge_attach_fail4; 645 } 646 647 if (nxgep->niu_type == NEPTUNE_2_10GF) { 648 if (nxgep->function_num > 1) { 649 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Unsupported" 650 " function %d. Only functions 0 and 1 are " 651 "supported for this card.", nxgep->function_num)); 652 status = NXGE_ERROR; 653 goto nxge_attach_fail4; 654 } 655 } 656 657 if (isLDOMguest(nxgep)) { 658 /* 659 * Use the function number here. 660 */ 661 nxgep->mac.portnum = nxgep->function_num; 662 nxgep->mac.porttype = PORT_TYPE_LOGICAL; 663 664 /* XXX We'll set the MAC address counts to 1 for now. */ 665 mmac_info = &nxgep->nxge_mmac_info; 666 mmac_info->num_mmac = 1; 667 mmac_info->naddrfree = 1; 668 } else { 669 portn = NXGE_GET_PORT_NUM(nxgep->function_num); 670 nxgep->mac.portnum = portn; 671 if ((portn == 0) || (portn == 1)) 672 nxgep->mac.porttype = PORT_TYPE_XMAC; 673 else 674 nxgep->mac.porttype = PORT_TYPE_BMAC; 675 /* 676 * Neptune has 4 ports, the first 2 ports use XMAC (10G MAC) 677 * internally, the rest 2 ports use BMAC (1G "Big" MAC). 678 * The two types of MACs have different characterizations. 679 */ 680 mmac_info = &nxgep->nxge_mmac_info; 681 if (nxgep->function_num < 2) { 682 mmac_info->num_mmac = XMAC_MAX_ALT_ADDR_ENTRY; 683 mmac_info->naddrfree = XMAC_MAX_ALT_ADDR_ENTRY; 684 } else { 685 mmac_info->num_mmac = BMAC_MAX_ALT_ADDR_ENTRY; 686 mmac_info->naddrfree = BMAC_MAX_ALT_ADDR_ENTRY; 687 } 688 } 689 /* 690 * Setup the Ndd parameters for the this instance. 691 */ 692 nxge_init_param(nxgep); 693 694 /* 695 * Setup Register Tracing Buffer. 696 */ 697 npi_rtrace_buf_init((rtrace_t *)&npi_rtracebuf); 698 699 /* init stats ptr */ 700 nxge_init_statsp(nxgep); 701 702 /* 703 * Copy the vpd info from eeprom to a local data 704 * structure, and then check its validity. 705 */ 706 if (!isLDOMguest(nxgep)) { 707 int *regp; 708 uint_t reglen; 709 int rv; 710 711 nxge_vpd_info_get(nxgep); 712 713 /* Find the NIU config handle. */ 714 rv = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 715 ddi_get_parent(nxgep->dip), DDI_PROP_DONTPASS, 716 "reg", ®p, ®len); 717 718 if (rv != DDI_PROP_SUCCESS) { 719 goto nxge_attach_fail5; 720 } 721 /* 722 * The address_hi, that is the first int, in the reg 723 * property consists of config handle, but need to remove 724 * the bits 28-31 which are OBP specific info. 725 */ 726 nxgep->niu_cfg_hdl = (*regp) & 0xFFFFFFF; 727 ddi_prop_free(regp); 728 } 729 730 if (isLDOMguest(nxgep)) { 731 uchar_t *prop_val; 732 uint_t prop_len; 733 uint32_t max_frame_size; 734 735 extern void nxge_get_logical_props(p_nxge_t); 736 737 nxgep->statsp->mac_stats.xcvr_inuse = LOGICAL_XCVR; 738 nxgep->mac.portmode = PORT_LOGICAL; 739 (void) ddi_prop_update_string(DDI_DEV_T_NONE, nxgep->dip, 740 "phy-type", "virtual transceiver"); 741 742 nxgep->nports = 1; 743 nxgep->board_ver = 0; /* XXX What? */ 744 745 /* 746 * local-mac-address property gives us info on which 747 * specific MAC address the Hybrid resource is associated 748 * with. 749 */ 750 if (ddi_prop_lookup_byte_array(DDI_DEV_T_ANY, nxgep->dip, 0, 751 "local-mac-address", &prop_val, 752 &prop_len) != DDI_PROP_SUCCESS) { 753 goto nxge_attach_fail5; 754 } 755 if (prop_len != ETHERADDRL) { 756 ddi_prop_free(prop_val); 757 goto nxge_attach_fail5; 758 } 759 ether_copy(prop_val, nxgep->hio_mac_addr); 760 ddi_prop_free(prop_val); 761 nxge_get_logical_props(nxgep); 762 763 /* 764 * Enable Jumbo property based on the "max-frame-size" 765 * property value. 766 */ 767 max_frame_size = ddi_prop_get_int(DDI_DEV_T_ANY, 768 nxgep->dip, DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 769 "max-frame-size", NXGE_MTU_DEFAULT_MAX); 770 if ((max_frame_size > NXGE_MTU_DEFAULT_MAX) && 771 (max_frame_size <= TX_JUMBO_MTU)) { 772 param_arr = nxgep->param_arr; 773 774 param_arr[param_accept_jumbo].value = 1; 775 nxgep->mac.is_jumbo = B_TRUE; 776 nxgep->mac.maxframesize = (uint16_t)max_frame_size; 777 nxgep->mac.default_mtu = nxgep->mac.maxframesize - 778 NXGE_EHEADER_VLAN_CRC; 779 } 780 } else { 781 status = nxge_xcvr_find(nxgep); 782 783 if (status != NXGE_OK) { 784 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "nxge_attach: " 785 " Couldn't determine card type" 786 " .... exit ")); 787 goto nxge_attach_fail5; 788 } 789 790 status = nxge_get_config_properties(nxgep); 791 792 if (status != NXGE_OK) { 793 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 794 "get_hw create failed")); 795 goto nxge_attach_fail; 796 } 797 } 798 799 /* 800 * Setup the Kstats for the driver. 801 */ 802 nxge_setup_kstats(nxgep); 803 804 if (!isLDOMguest(nxgep)) 805 nxge_setup_param(nxgep); 806 807 status = nxge_setup_system_dma_pages(nxgep); 808 if (status != NXGE_OK) { 809 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "set dma page failed")); 810 goto nxge_attach_fail; 811 } 812 813 nxge_hw_id_init(nxgep); 814 815 if (!isLDOMguest(nxgep)) 816 nxge_hw_init_niu_common(nxgep); 817 818 status = nxge_setup_mutexes(nxgep); 819 if (status != NXGE_OK) { 820 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set mutex failed")); 821 goto nxge_attach_fail; 822 } 823 824 #if defined(sun4v) 825 if (isLDOMguest(nxgep)) { 826 /* Find our VR & channel sets. */ 827 status = nxge_hio_vr_add(nxgep); 828 if (status != NXGE_OK) { 829 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 830 "nxge_hio_vr_add failed")); 831 (void) hsvc_unregister(&nxgep->niu_hsvc); 832 nxgep->niu_hsvc_available = B_FALSE; 833 } 834 goto nxge_attach_exit; 835 } 836 #endif 837 838 status = nxge_setup_dev(nxgep); 839 if (status != DDI_SUCCESS) { 840 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "set dev failed")); 841 goto nxge_attach_fail; 842 } 843 844 status = nxge_add_intrs(nxgep); 845 if (status != DDI_SUCCESS) { 846 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "add_intr failed")); 847 goto nxge_attach_fail; 848 } 849 850 status = nxge_add_soft_intrs(nxgep); 851 if (status != DDI_SUCCESS) { 852 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 853 "add_soft_intr failed")); 854 goto nxge_attach_fail; 855 } 856 857 /* If a guest, register with vio_net instead. */ 858 if ((status = nxge_mac_register(nxgep)) != NXGE_OK) { 859 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 860 "unable to register to mac layer (%d)", status)); 861 goto nxge_attach_fail; 862 } 863 864 mac_link_update(nxgep->mach, LINK_STATE_UNKNOWN); 865 866 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 867 "registered to mac (instance %d)", instance)); 868 869 /* nxge_link_monitor calls xcvr.check_link recursively */ 870 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 871 872 goto nxge_attach_exit; 873 874 nxge_attach_fail: 875 nxge_unattach(nxgep); 876 goto nxge_attach_fail1; 877 878 nxge_attach_fail5: 879 /* 880 * Tear down the ndd parameters setup. 881 */ 882 nxge_destroy_param(nxgep); 883 884 /* 885 * Tear down the kstat setup. 886 */ 887 nxge_destroy_kstats(nxgep); 888 889 nxge_attach_fail4: 890 if (nxgep->nxge_hw_p) { 891 nxge_uninit_common_dev(nxgep); 892 nxgep->nxge_hw_p = NULL; 893 } 894 895 nxge_attach_fail3: 896 /* 897 * Unmap the register setup. 898 */ 899 nxge_unmap_regs(nxgep); 900 901 nxge_fm_fini(nxgep); 902 903 nxge_attach_fail2: 904 ddi_soft_state_free(nxge_list, nxgep->instance); 905 906 nxge_attach_fail1: 907 if (status != NXGE_OK) 908 status = (NXGE_ERROR | NXGE_DDI_FAILED); 909 nxgep = NULL; 910 911 nxge_attach_exit: 912 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_attach status = 0x%08x", 913 status)); 914 915 return (status); 916 } 917 918 static int 919 nxge_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 920 { 921 int status = DDI_SUCCESS; 922 int instance; 923 p_nxge_t nxgep = NULL; 924 925 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_detach")); 926 instance = ddi_get_instance(dip); 927 nxgep = ddi_get_soft_state(nxge_list, instance); 928 if (nxgep == NULL) { 929 status = DDI_FAILURE; 930 goto nxge_detach_exit; 931 } 932 933 switch (cmd) { 934 case DDI_DETACH: 935 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_DETACH")); 936 break; 937 938 case DDI_PM_SUSPEND: 939 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_PM_SUSPEND")); 940 nxgep->suspended = DDI_PM_SUSPEND; 941 nxge_suspend(nxgep); 942 break; 943 944 case DDI_SUSPEND: 945 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "doing DDI_SUSPEND")); 946 if (nxgep->suspended != DDI_PM_SUSPEND) { 947 nxgep->suspended = DDI_SUSPEND; 948 nxge_suspend(nxgep); 949 } 950 break; 951 952 default: 953 status = DDI_FAILURE; 954 } 955 956 if (cmd != DDI_DETACH) 957 goto nxge_detach_exit; 958 959 /* 960 * Stop the xcvr polling. 961 */ 962 nxgep->suspended = cmd; 963 964 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 965 966 if (isLDOMguest(nxgep)) { 967 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 968 nxge_m_stop((void *)nxgep); 969 nxge_hio_unregister(nxgep); 970 } else if (nxgep->mach && (status = mac_unregister(nxgep->mach)) != 0) { 971 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 972 "<== nxge_detach status = 0x%08X", status)); 973 return (DDI_FAILURE); 974 } 975 976 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 977 "<== nxge_detach (mac_unregister) status = 0x%08X", status)); 978 979 nxge_unattach(nxgep); 980 nxgep = NULL; 981 982 nxge_detach_exit: 983 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_detach status = 0x%08X", 984 status)); 985 986 return (status); 987 } 988 989 static void 990 nxge_unattach(p_nxge_t nxgep) 991 { 992 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unattach")); 993 994 if (nxgep == NULL || nxgep->dev_regs == NULL) { 995 return; 996 } 997 998 nxgep->nxge_magic = 0; 999 1000 if (nxgep->nxge_timerid) { 1001 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 1002 nxgep->nxge_timerid = 0; 1003 } 1004 1005 /* 1006 * If this flag is set, it will affect the Neptune 1007 * only. 1008 */ 1009 if ((nxgep->niu_type != N2_NIU) && nxge_peu_reset_enable) { 1010 nxge_niu_peu_reset(nxgep); 1011 } 1012 1013 #if defined(sun4v) 1014 if (isLDOMguest(nxgep)) { 1015 (void) nxge_hio_vr_release(nxgep); 1016 } 1017 #endif 1018 1019 if (nxgep->nxge_hw_p) { 1020 nxge_uninit_common_dev(nxgep); 1021 nxgep->nxge_hw_p = NULL; 1022 } 1023 1024 #if defined(sun4v) 1025 if (nxgep->niu_type == N2_NIU && nxgep->niu_hsvc_available == B_TRUE) { 1026 (void) hsvc_unregister(&nxgep->niu_hsvc); 1027 nxgep->niu_hsvc_available = B_FALSE; 1028 } 1029 #endif 1030 /* 1031 * Stop any further interrupts. 1032 */ 1033 nxge_remove_intrs(nxgep); 1034 1035 /* remove soft interrups */ 1036 nxge_remove_soft_intrs(nxgep); 1037 1038 /* 1039 * Stop the device and free resources. 1040 */ 1041 if (!isLDOMguest(nxgep)) { 1042 nxge_destroy_dev(nxgep); 1043 } 1044 1045 /* 1046 * Tear down the ndd parameters setup. 1047 */ 1048 nxge_destroy_param(nxgep); 1049 1050 /* 1051 * Tear down the kstat setup. 1052 */ 1053 nxge_destroy_kstats(nxgep); 1054 1055 /* 1056 * Destroy all mutexes. 1057 */ 1058 nxge_destroy_mutexes(nxgep); 1059 1060 /* 1061 * Remove the list of ndd parameters which 1062 * were setup during attach. 1063 */ 1064 if (nxgep->dip) { 1065 NXGE_DEBUG_MSG((nxgep, OBP_CTL, 1066 " nxge_unattach: remove all properties")); 1067 1068 (void) ddi_prop_remove_all(nxgep->dip); 1069 } 1070 1071 #if NXGE_PROPERTY 1072 nxge_remove_hard_properties(nxgep); 1073 #endif 1074 1075 /* 1076 * Unmap the register setup. 1077 */ 1078 nxge_unmap_regs(nxgep); 1079 1080 nxge_fm_fini(nxgep); 1081 1082 ddi_soft_state_free(nxge_list, nxgep->instance); 1083 1084 NXGE_DEBUG_MSG((NULL, DDI_CTL, "<== nxge_unattach")); 1085 } 1086 1087 #if defined(sun4v) 1088 int 1089 nxge_hsvc_register(nxge_t *nxgep) 1090 { 1091 nxge_status_t status; 1092 1093 if (nxgep->niu_type == N2_NIU) { 1094 nxgep->niu_hsvc_available = B_FALSE; 1095 bcopy(&niu_hsvc, &nxgep->niu_hsvc, sizeof (hsvc_info_t)); 1096 if ((status = hsvc_register(&nxgep->niu_hsvc, 1097 &nxgep->niu_min_ver)) != 0) { 1098 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1099 "nxge_attach: %s: cannot negotiate " 1100 "hypervisor services revision %d group: 0x%lx " 1101 "major: 0x%lx minor: 0x%lx errno: %d", 1102 niu_hsvc.hsvc_modname, niu_hsvc.hsvc_rev, 1103 niu_hsvc.hsvc_group, niu_hsvc.hsvc_major, 1104 niu_hsvc.hsvc_minor, status)); 1105 return (DDI_FAILURE); 1106 } 1107 nxgep->niu_hsvc_available = B_TRUE; 1108 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1109 "NIU Hypervisor service enabled")); 1110 } 1111 1112 return (DDI_SUCCESS); 1113 } 1114 #endif 1115 1116 static char n2_siu_name[] = "niu"; 1117 1118 static nxge_status_t 1119 nxge_map_regs(p_nxge_t nxgep) 1120 { 1121 int ddi_status = DDI_SUCCESS; 1122 p_dev_regs_t dev_regs; 1123 char buf[MAXPATHLEN + 1]; 1124 char *devname; 1125 #ifdef NXGE_DEBUG 1126 char *sysname; 1127 #endif 1128 off_t regsize; 1129 nxge_status_t status = NXGE_OK; 1130 #if !defined(_BIG_ENDIAN) 1131 off_t pci_offset; 1132 uint16_t pcie_devctl; 1133 #endif 1134 1135 if (isLDOMguest(nxgep)) { 1136 return (nxge_guest_regs_map(nxgep)); 1137 } 1138 1139 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_map_regs")); 1140 nxgep->dev_regs = NULL; 1141 dev_regs = KMEM_ZALLOC(sizeof (dev_regs_t), KM_SLEEP); 1142 dev_regs->nxge_regh = NULL; 1143 dev_regs->nxge_pciregh = NULL; 1144 dev_regs->nxge_msix_regh = NULL; 1145 dev_regs->nxge_vir_regh = NULL; 1146 dev_regs->nxge_vir2_regh = NULL; 1147 nxgep->niu_type = NIU_TYPE_NONE; 1148 1149 devname = ddi_pathname(nxgep->dip, buf); 1150 ASSERT(strlen(devname) > 0); 1151 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1152 "nxge_map_regs: pathname devname %s", devname)); 1153 1154 /* 1155 * The driver is running on a N2-NIU system if devname is something 1156 * like "/niu@80/network@0" 1157 */ 1158 if (strstr(devname, n2_siu_name)) { 1159 /* N2/NIU */ 1160 nxgep->niu_type = N2_NIU; 1161 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1162 "nxge_map_regs: N2/NIU devname %s", devname)); 1163 /* get function number */ 1164 nxgep->function_num = 1165 (devname[strlen(devname) -1] == '1' ? 1 : 0); 1166 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1167 "nxge_map_regs: N2/NIU function number %d", 1168 nxgep->function_num)); 1169 } else { 1170 int *prop_val; 1171 uint_t prop_len; 1172 uint8_t func_num; 1173 1174 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, nxgep->dip, 1175 0, "reg", 1176 &prop_val, &prop_len) != DDI_PROP_SUCCESS) { 1177 NXGE_DEBUG_MSG((nxgep, VPD_CTL, 1178 "Reg property not found")); 1179 ddi_status = DDI_FAILURE; 1180 goto nxge_map_regs_fail0; 1181 1182 } else { 1183 func_num = (prop_val[0] >> 8) & 0x7; 1184 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1185 "Reg property found: fun # %d", 1186 func_num)); 1187 nxgep->function_num = func_num; 1188 if (isLDOMguest(nxgep)) { 1189 nxgep->function_num /= 2; 1190 return (NXGE_OK); 1191 } 1192 ddi_prop_free(prop_val); 1193 } 1194 } 1195 1196 switch (nxgep->niu_type) { 1197 default: 1198 (void) ddi_dev_regsize(nxgep->dip, 0, ®size); 1199 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1200 "nxge_map_regs: pci config size 0x%x", regsize)); 1201 1202 ddi_status = ddi_regs_map_setup(nxgep->dip, 0, 1203 (caddr_t *)&(dev_regs->nxge_pciregp), 0, 0, 1204 &nxge_dev_reg_acc_attr, &dev_regs->nxge_pciregh); 1205 if (ddi_status != DDI_SUCCESS) { 1206 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1207 "ddi_map_regs, nxge bus config regs failed")); 1208 goto nxge_map_regs_fail0; 1209 } 1210 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1211 "nxge_map_reg: PCI config addr 0x%0llx " 1212 " handle 0x%0llx", dev_regs->nxge_pciregp, 1213 dev_regs->nxge_pciregh)); 1214 /* 1215 * IMP IMP 1216 * workaround for bit swapping bug in HW 1217 * which ends up in no-snoop = yes 1218 * resulting, in DMA not synched properly 1219 */ 1220 #if !defined(_BIG_ENDIAN) 1221 /* workarounds for x86 systems */ 1222 pci_offset = 0x80 + PCIE_DEVCTL; 1223 pcie_devctl = 0x0; 1224 pcie_devctl &= PCIE_DEVCTL_ENABLE_NO_SNOOP; 1225 pcie_devctl |= PCIE_DEVCTL_RO_EN; 1226 pci_config_put16(dev_regs->nxge_pciregh, pci_offset, 1227 pcie_devctl); 1228 #endif 1229 1230 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1231 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1232 "nxge_map_regs: pio size 0x%x", regsize)); 1233 /* set up the device mapped register */ 1234 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1235 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1236 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1237 if (ddi_status != DDI_SUCCESS) { 1238 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1239 "ddi_map_regs for Neptune global reg failed")); 1240 goto nxge_map_regs_fail1; 1241 } 1242 1243 /* set up the msi/msi-x mapped register */ 1244 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1245 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1246 "nxge_map_regs: msix size 0x%x", regsize)); 1247 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1248 (caddr_t *)&(dev_regs->nxge_msix_regp), 0, 0, 1249 &nxge_dev_reg_acc_attr, &dev_regs->nxge_msix_regh); 1250 if (ddi_status != DDI_SUCCESS) { 1251 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1252 "ddi_map_regs for msi reg failed")); 1253 goto nxge_map_regs_fail2; 1254 } 1255 1256 /* set up the vio region mapped register */ 1257 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1258 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1259 "nxge_map_regs: vio size 0x%x", regsize)); 1260 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1261 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1262 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1263 1264 if (ddi_status != DDI_SUCCESS) { 1265 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1266 "ddi_map_regs for nxge vio reg failed")); 1267 goto nxge_map_regs_fail3; 1268 } 1269 nxgep->dev_regs = dev_regs; 1270 1271 NPI_PCI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_pciregh); 1272 NPI_PCI_ADD_HANDLE_SET(nxgep, 1273 (npi_reg_ptr_t)dev_regs->nxge_pciregp); 1274 NPI_MSI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_msix_regh); 1275 NPI_MSI_ADD_HANDLE_SET(nxgep, 1276 (npi_reg_ptr_t)dev_regs->nxge_msix_regp); 1277 1278 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1279 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1280 1281 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1282 NPI_REG_ADD_HANDLE_SET(nxgep, 1283 (npi_reg_ptr_t)dev_regs->nxge_regp); 1284 1285 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1286 NPI_VREG_ADD_HANDLE_SET(nxgep, 1287 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1288 1289 break; 1290 1291 case N2_NIU: 1292 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "ddi_map_regs, NIU")); 1293 /* 1294 * Set up the device mapped register (FWARC 2006/556) 1295 * (changed back to 1: reg starts at 1!) 1296 */ 1297 (void) ddi_dev_regsize(nxgep->dip, 1, ®size); 1298 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1299 "nxge_map_regs: dev size 0x%x", regsize)); 1300 ddi_status = ddi_regs_map_setup(nxgep->dip, 1, 1301 (caddr_t *)&(dev_regs->nxge_regp), 0, 0, 1302 &nxge_dev_reg_acc_attr, &dev_regs->nxge_regh); 1303 1304 if (ddi_status != DDI_SUCCESS) { 1305 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1306 "ddi_map_regs for N2/NIU, global reg failed ")); 1307 goto nxge_map_regs_fail1; 1308 } 1309 1310 /* set up the first vio region mapped register */ 1311 (void) ddi_dev_regsize(nxgep->dip, 2, ®size); 1312 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1313 "nxge_map_regs: vio (1) size 0x%x", regsize)); 1314 ddi_status = ddi_regs_map_setup(nxgep->dip, 2, 1315 (caddr_t *)&(dev_regs->nxge_vir_regp), 0, 0, 1316 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir_regh); 1317 1318 if (ddi_status != DDI_SUCCESS) { 1319 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1320 "ddi_map_regs for nxge vio reg failed")); 1321 goto nxge_map_regs_fail2; 1322 } 1323 /* set up the second vio region mapped register */ 1324 (void) ddi_dev_regsize(nxgep->dip, 3, ®size); 1325 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1326 "nxge_map_regs: vio (3) size 0x%x", regsize)); 1327 ddi_status = ddi_regs_map_setup(nxgep->dip, 3, 1328 (caddr_t *)&(dev_regs->nxge_vir2_regp), 0, 0, 1329 &nxge_dev_reg_acc_attr, &dev_regs->nxge_vir2_regh); 1330 1331 if (ddi_status != DDI_SUCCESS) { 1332 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1333 "ddi_map_regs for nxge vio2 reg failed")); 1334 goto nxge_map_regs_fail3; 1335 } 1336 nxgep->dev_regs = dev_regs; 1337 1338 NPI_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1339 NPI_ADD_HANDLE_SET(nxgep, (npi_reg_ptr_t)dev_regs->nxge_regp); 1340 1341 NPI_REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_regh); 1342 NPI_REG_ADD_HANDLE_SET(nxgep, 1343 (npi_reg_ptr_t)dev_regs->nxge_regp); 1344 1345 NPI_VREG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir_regh); 1346 NPI_VREG_ADD_HANDLE_SET(nxgep, 1347 (npi_reg_ptr_t)dev_regs->nxge_vir_regp); 1348 1349 NPI_V2REG_ACC_HANDLE_SET(nxgep, dev_regs->nxge_vir2_regh); 1350 NPI_V2REG_ADD_HANDLE_SET(nxgep, 1351 (npi_reg_ptr_t)dev_regs->nxge_vir2_regp); 1352 1353 break; 1354 } 1355 1356 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "nxge_map_reg: hardware addr 0x%0llx " 1357 " handle 0x%0llx", dev_regs->nxge_regp, dev_regs->nxge_regh)); 1358 1359 goto nxge_map_regs_exit; 1360 nxge_map_regs_fail3: 1361 if (dev_regs->nxge_msix_regh) { 1362 ddi_regs_map_free(&dev_regs->nxge_msix_regh); 1363 } 1364 if (dev_regs->nxge_vir_regh) { 1365 ddi_regs_map_free(&dev_regs->nxge_regh); 1366 } 1367 nxge_map_regs_fail2: 1368 if (dev_regs->nxge_regh) { 1369 ddi_regs_map_free(&dev_regs->nxge_regh); 1370 } 1371 nxge_map_regs_fail1: 1372 if (dev_regs->nxge_pciregh) { 1373 ddi_regs_map_free(&dev_regs->nxge_pciregh); 1374 } 1375 nxge_map_regs_fail0: 1376 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "Freeing register set memory")); 1377 kmem_free(dev_regs, sizeof (dev_regs_t)); 1378 1379 nxge_map_regs_exit: 1380 if (ddi_status != DDI_SUCCESS) 1381 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1382 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_map_regs")); 1383 return (status); 1384 } 1385 1386 static void 1387 nxge_unmap_regs(p_nxge_t nxgep) 1388 { 1389 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_unmap_regs")); 1390 1391 if (isLDOMguest(nxgep)) { 1392 nxge_guest_regs_map_free(nxgep); 1393 return; 1394 } 1395 1396 if (nxgep->dev_regs) { 1397 if (nxgep->dev_regs->nxge_pciregh) { 1398 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1399 "==> nxge_unmap_regs: bus")); 1400 ddi_regs_map_free(&nxgep->dev_regs->nxge_pciregh); 1401 nxgep->dev_regs->nxge_pciregh = NULL; 1402 } 1403 if (nxgep->dev_regs->nxge_regh) { 1404 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1405 "==> nxge_unmap_regs: device registers")); 1406 ddi_regs_map_free(&nxgep->dev_regs->nxge_regh); 1407 nxgep->dev_regs->nxge_regh = NULL; 1408 } 1409 if (nxgep->dev_regs->nxge_msix_regh) { 1410 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1411 "==> nxge_unmap_regs: device interrupts")); 1412 ddi_regs_map_free(&nxgep->dev_regs->nxge_msix_regh); 1413 nxgep->dev_regs->nxge_msix_regh = NULL; 1414 } 1415 if (nxgep->dev_regs->nxge_vir_regh) { 1416 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1417 "==> nxge_unmap_regs: vio region")); 1418 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir_regh); 1419 nxgep->dev_regs->nxge_vir_regh = NULL; 1420 } 1421 if (nxgep->dev_regs->nxge_vir2_regh) { 1422 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1423 "==> nxge_unmap_regs: vio2 region")); 1424 ddi_regs_map_free(&nxgep->dev_regs->nxge_vir2_regh); 1425 nxgep->dev_regs->nxge_vir2_regh = NULL; 1426 } 1427 1428 kmem_free(nxgep->dev_regs, sizeof (dev_regs_t)); 1429 nxgep->dev_regs = NULL; 1430 } 1431 1432 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_unmap_regs")); 1433 } 1434 1435 static nxge_status_t 1436 nxge_setup_mutexes(p_nxge_t nxgep) 1437 { 1438 int ddi_status = DDI_SUCCESS; 1439 nxge_status_t status = NXGE_OK; 1440 nxge_classify_t *classify_ptr; 1441 int partition; 1442 1443 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_mutexes")); 1444 1445 /* 1446 * Get the interrupt cookie so the mutexes can be 1447 * Initialized. 1448 */ 1449 if (isLDOMguest(nxgep)) { 1450 nxgep->interrupt_cookie = 0; 1451 } else { 1452 ddi_status = ddi_get_iblock_cookie(nxgep->dip, 0, 1453 &nxgep->interrupt_cookie); 1454 1455 if (ddi_status != DDI_SUCCESS) { 1456 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1457 "<== nxge_setup_mutexes: failed 0x%x", 1458 ddi_status)); 1459 goto nxge_setup_mutexes_exit; 1460 } 1461 } 1462 1463 cv_init(&nxgep->poll_cv, NULL, CV_DRIVER, NULL); 1464 MUTEX_INIT(&nxgep->poll_lock, NULL, 1465 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1466 1467 /* 1468 * Initialize mutexes for this device. 1469 */ 1470 MUTEX_INIT(nxgep->genlock, NULL, 1471 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1472 MUTEX_INIT(&nxgep->ouraddr_lock, NULL, 1473 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1474 MUTEX_INIT(&nxgep->mif_lock, NULL, 1475 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1476 MUTEX_INIT(&nxgep->group_lock, NULL, 1477 MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1478 RW_INIT(&nxgep->filter_lock, NULL, 1479 RW_DRIVER, (void *)nxgep->interrupt_cookie); 1480 1481 classify_ptr = &nxgep->classifier; 1482 /* 1483 * FFLP Mutexes are never used in interrupt context 1484 * as fflp operation can take very long time to 1485 * complete and hence not suitable to invoke from interrupt 1486 * handlers. 1487 */ 1488 MUTEX_INIT(&classify_ptr->tcam_lock, NULL, 1489 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1490 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1491 MUTEX_INIT(&classify_ptr->fcram_lock, NULL, 1492 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1493 for (partition = 0; partition < MAX_PARTITION; partition++) { 1494 MUTEX_INIT(&classify_ptr->hash_lock[partition], NULL, 1495 NXGE_MUTEX_DRIVER, (void *)nxgep->interrupt_cookie); 1496 } 1497 } 1498 1499 nxge_setup_mutexes_exit: 1500 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1501 "<== nxge_setup_mutexes status = %x", status)); 1502 1503 if (ddi_status != DDI_SUCCESS) 1504 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 1505 1506 return (status); 1507 } 1508 1509 static void 1510 nxge_destroy_mutexes(p_nxge_t nxgep) 1511 { 1512 int partition; 1513 nxge_classify_t *classify_ptr; 1514 1515 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_mutexes")); 1516 RW_DESTROY(&nxgep->filter_lock); 1517 MUTEX_DESTROY(&nxgep->group_lock); 1518 MUTEX_DESTROY(&nxgep->mif_lock); 1519 MUTEX_DESTROY(&nxgep->ouraddr_lock); 1520 MUTEX_DESTROY(nxgep->genlock); 1521 1522 classify_ptr = &nxgep->classifier; 1523 MUTEX_DESTROY(&classify_ptr->tcam_lock); 1524 1525 /* Destroy all polling resources. */ 1526 MUTEX_DESTROY(&nxgep->poll_lock); 1527 cv_destroy(&nxgep->poll_cv); 1528 1529 /* free data structures, based on HW type */ 1530 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1531 MUTEX_DESTROY(&classify_ptr->fcram_lock); 1532 for (partition = 0; partition < MAX_PARTITION; partition++) { 1533 MUTEX_DESTROY(&classify_ptr->hash_lock[partition]); 1534 } 1535 } 1536 1537 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_mutexes")); 1538 } 1539 1540 nxge_status_t 1541 nxge_init(p_nxge_t nxgep) 1542 { 1543 nxge_status_t status = NXGE_OK; 1544 1545 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_init")); 1546 1547 if (nxgep->drv_state & STATE_HW_INITIALIZED) { 1548 return (status); 1549 } 1550 1551 /* 1552 * Allocate system memory for the receive/transmit buffer blocks 1553 * and receive/transmit descriptor rings. 1554 */ 1555 status = nxge_alloc_mem_pool(nxgep); 1556 if (status != NXGE_OK) { 1557 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "alloc mem failed\n")); 1558 goto nxge_init_fail1; 1559 } 1560 1561 if (!isLDOMguest(nxgep)) { 1562 /* 1563 * Initialize and enable the TXC registers. 1564 * (Globally enable the Tx controller, 1565 * enable the port, configure the dma channel bitmap, 1566 * configure the max burst size). 1567 */ 1568 status = nxge_txc_init(nxgep); 1569 if (status != NXGE_OK) { 1570 NXGE_ERROR_MSG((nxgep, 1571 NXGE_ERR_CTL, "init txc failed\n")); 1572 goto nxge_init_fail2; 1573 } 1574 } 1575 1576 /* 1577 * Initialize and enable TXDMA channels. 1578 */ 1579 status = nxge_init_txdma_channels(nxgep); 1580 if (status != NXGE_OK) { 1581 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init txdma failed\n")); 1582 goto nxge_init_fail3; 1583 } 1584 1585 /* 1586 * Initialize and enable RXDMA channels. 1587 */ 1588 status = nxge_init_rxdma_channels(nxgep); 1589 if (status != NXGE_OK) { 1590 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init rxdma failed\n")); 1591 goto nxge_init_fail4; 1592 } 1593 1594 /* 1595 * The guest domain is now done. 1596 */ 1597 if (isLDOMguest(nxgep)) { 1598 nxgep->drv_state |= STATE_HW_INITIALIZED; 1599 goto nxge_init_exit; 1600 } 1601 1602 /* 1603 * Initialize TCAM and FCRAM (Neptune). 1604 */ 1605 status = nxge_classify_init(nxgep); 1606 if (status != NXGE_OK) { 1607 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init classify failed\n")); 1608 goto nxge_init_fail5; 1609 } 1610 1611 /* 1612 * Initialize ZCP 1613 */ 1614 status = nxge_zcp_init(nxgep); 1615 if (status != NXGE_OK) { 1616 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init ZCP failed\n")); 1617 goto nxge_init_fail5; 1618 } 1619 1620 /* 1621 * Initialize IPP. 1622 */ 1623 status = nxge_ipp_init(nxgep); 1624 if (status != NXGE_OK) { 1625 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init IPP failed\n")); 1626 goto nxge_init_fail5; 1627 } 1628 1629 /* 1630 * Initialize the MAC block. 1631 */ 1632 status = nxge_mac_init(nxgep); 1633 if (status != NXGE_OK) { 1634 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "init MAC failed\n")); 1635 goto nxge_init_fail5; 1636 } 1637 1638 nxge_intrs_enable(nxgep); /* XXX What changes do I need to make here? */ 1639 1640 /* 1641 * Enable hardware interrupts. 1642 */ 1643 nxge_intr_hw_enable(nxgep); 1644 nxgep->drv_state |= STATE_HW_INITIALIZED; 1645 1646 goto nxge_init_exit; 1647 1648 nxge_init_fail5: 1649 nxge_uninit_rxdma_channels(nxgep); 1650 nxge_init_fail4: 1651 nxge_uninit_txdma_channels(nxgep); 1652 nxge_init_fail3: 1653 if (!isLDOMguest(nxgep)) { 1654 (void) nxge_txc_uninit(nxgep); 1655 } 1656 nxge_init_fail2: 1657 nxge_free_mem_pool(nxgep); 1658 nxge_init_fail1: 1659 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1660 "<== nxge_init status (failed) = 0x%08x", status)); 1661 return (status); 1662 1663 nxge_init_exit: 1664 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_init status = 0x%08x", 1665 status)); 1666 return (status); 1667 } 1668 1669 1670 timeout_id_t 1671 nxge_start_timer(p_nxge_t nxgep, fptrv_t func, int msec) 1672 { 1673 if ((nxgep->suspended == 0) || (nxgep->suspended == DDI_RESUME)) { 1674 return (timeout(func, (caddr_t)nxgep, 1675 drv_usectohz(1000 * msec))); 1676 } 1677 return (NULL); 1678 } 1679 1680 /*ARGSUSED*/ 1681 void 1682 nxge_stop_timer(p_nxge_t nxgep, timeout_id_t timerid) 1683 { 1684 if (timerid) { 1685 (void) untimeout(timerid); 1686 } 1687 } 1688 1689 void 1690 nxge_uninit(p_nxge_t nxgep) 1691 { 1692 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_uninit")); 1693 1694 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1695 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1696 "==> nxge_uninit: not initialized")); 1697 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1698 "<== nxge_uninit")); 1699 return; 1700 } 1701 1702 /* stop timer */ 1703 if (nxgep->nxge_timerid) { 1704 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 1705 nxgep->nxge_timerid = 0; 1706 } 1707 1708 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 1709 (void) nxge_intr_hw_disable(nxgep); 1710 1711 /* 1712 * Reset the receive MAC side. 1713 */ 1714 (void) nxge_rx_mac_disable(nxgep); 1715 1716 /* Disable and soft reset the IPP */ 1717 if (!isLDOMguest(nxgep)) 1718 (void) nxge_ipp_disable(nxgep); 1719 1720 /* Free classification resources */ 1721 (void) nxge_classify_uninit(nxgep); 1722 1723 /* 1724 * Reset the transmit/receive DMA side. 1725 */ 1726 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 1727 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 1728 1729 nxge_uninit_txdma_channels(nxgep); 1730 nxge_uninit_rxdma_channels(nxgep); 1731 1732 /* 1733 * Reset the transmit MAC side. 1734 */ 1735 (void) nxge_tx_mac_disable(nxgep); 1736 1737 nxge_free_mem_pool(nxgep); 1738 1739 /* 1740 * Start the timer if the reset flag is not set. 1741 * If this reset flag is set, the link monitor 1742 * will not be started in order to stop furthur bus 1743 * activities coming from this interface. 1744 * The driver will start the monitor function 1745 * if the interface was initialized again later. 1746 */ 1747 if (!nxge_peu_reset_enable) { 1748 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1749 } 1750 1751 nxgep->drv_state &= ~STATE_HW_INITIALIZED; 1752 1753 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_uninit: " 1754 "nxge_mblks_pending %d", nxge_mblks_pending)); 1755 } 1756 1757 void 1758 nxge_get64(p_nxge_t nxgep, p_mblk_t mp) 1759 { 1760 #if defined(__i386) 1761 size_t reg; 1762 #else 1763 uint64_t reg; 1764 #endif 1765 uint64_t regdata; 1766 int i, retry; 1767 1768 bcopy((char *)mp->b_rptr, (char *)®, sizeof (uint64_t)); 1769 regdata = 0; 1770 retry = 1; 1771 1772 for (i = 0; i < retry; i++) { 1773 NXGE_REG_RD64(nxgep->npi_handle, reg, ®data); 1774 } 1775 bcopy((char *)®data, (char *)mp->b_rptr, sizeof (uint64_t)); 1776 } 1777 1778 void 1779 nxge_put64(p_nxge_t nxgep, p_mblk_t mp) 1780 { 1781 #if defined(__i386) 1782 size_t reg; 1783 #else 1784 uint64_t reg; 1785 #endif 1786 uint64_t buf[2]; 1787 1788 bcopy((char *)mp->b_rptr, (char *)&buf[0], 2 * sizeof (uint64_t)); 1789 #if defined(__i386) 1790 reg = (size_t)buf[0]; 1791 #else 1792 reg = buf[0]; 1793 #endif 1794 1795 NXGE_NPI_PIO_WRITE64(nxgep->npi_handle, reg, buf[1]); 1796 } 1797 1798 1799 nxge_os_mutex_t nxgedebuglock; 1800 int nxge_debug_init = 0; 1801 1802 /*ARGSUSED*/ 1803 /*VARARGS*/ 1804 void 1805 nxge_debug_msg(p_nxge_t nxgep, uint64_t level, char *fmt, ...) 1806 { 1807 char msg_buffer[1048]; 1808 char prefix_buffer[32]; 1809 int instance; 1810 uint64_t debug_level; 1811 int cmn_level = CE_CONT; 1812 va_list ap; 1813 1814 if (nxgep && nxgep->nxge_debug_level != nxge_debug_level) { 1815 /* In case a developer has changed nxge_debug_level. */ 1816 if (nxgep->nxge_debug_level != nxge_debug_level) 1817 nxgep->nxge_debug_level = nxge_debug_level; 1818 } 1819 1820 debug_level = (nxgep == NULL) ? nxge_debug_level : 1821 nxgep->nxge_debug_level; 1822 1823 if ((level & debug_level) || 1824 (level == NXGE_NOTE) || 1825 (level == NXGE_ERR_CTL)) { 1826 /* do the msg processing */ 1827 if (nxge_debug_init == 0) { 1828 MUTEX_INIT(&nxgedebuglock, NULL, MUTEX_DRIVER, NULL); 1829 nxge_debug_init = 1; 1830 } 1831 1832 MUTEX_ENTER(&nxgedebuglock); 1833 1834 if ((level & NXGE_NOTE)) { 1835 cmn_level = CE_NOTE; 1836 } 1837 1838 if (level & NXGE_ERR_CTL) { 1839 cmn_level = CE_WARN; 1840 } 1841 1842 va_start(ap, fmt); 1843 (void) vsprintf(msg_buffer, fmt, ap); 1844 va_end(ap); 1845 if (nxgep == NULL) { 1846 instance = -1; 1847 (void) sprintf(prefix_buffer, "%s :", "nxge"); 1848 } else { 1849 instance = nxgep->instance; 1850 (void) sprintf(prefix_buffer, 1851 "%s%d :", "nxge", instance); 1852 } 1853 1854 MUTEX_EXIT(&nxgedebuglock); 1855 cmn_err(cmn_level, "!%s %s\n", 1856 prefix_buffer, msg_buffer); 1857 1858 } 1859 } 1860 1861 char * 1862 nxge_dump_packet(char *addr, int size) 1863 { 1864 uchar_t *ap = (uchar_t *)addr; 1865 int i; 1866 static char etherbuf[1024]; 1867 char *cp = etherbuf; 1868 char digits[] = "0123456789abcdef"; 1869 1870 if (!size) 1871 size = 60; 1872 1873 if (size > MAX_DUMP_SZ) { 1874 /* Dump the leading bytes */ 1875 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1876 if (*ap > 0x0f) 1877 *cp++ = digits[*ap >> 4]; 1878 *cp++ = digits[*ap++ & 0xf]; 1879 *cp++ = ':'; 1880 } 1881 for (i = 0; i < 20; i++) 1882 *cp++ = '.'; 1883 /* Dump the last MAX_DUMP_SZ/2 bytes */ 1884 ap = (uchar_t *)(addr + (size - MAX_DUMP_SZ/2)); 1885 for (i = 0; i < MAX_DUMP_SZ/2; i++) { 1886 if (*ap > 0x0f) 1887 *cp++ = digits[*ap >> 4]; 1888 *cp++ = digits[*ap++ & 0xf]; 1889 *cp++ = ':'; 1890 } 1891 } else { 1892 for (i = 0; i < size; i++) { 1893 if (*ap > 0x0f) 1894 *cp++ = digits[*ap >> 4]; 1895 *cp++ = digits[*ap++ & 0xf]; 1896 *cp++ = ':'; 1897 } 1898 } 1899 *--cp = 0; 1900 return (etherbuf); 1901 } 1902 1903 #ifdef NXGE_DEBUG 1904 static void 1905 nxge_test_map_regs(p_nxge_t nxgep) 1906 { 1907 ddi_acc_handle_t cfg_handle; 1908 p_pci_cfg_t cfg_ptr; 1909 ddi_acc_handle_t dev_handle; 1910 char *dev_ptr; 1911 ddi_acc_handle_t pci_config_handle; 1912 uint32_t regval; 1913 int i; 1914 1915 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_test_map_regs")); 1916 1917 dev_handle = nxgep->dev_regs->nxge_regh; 1918 dev_ptr = (char *)nxgep->dev_regs->nxge_regp; 1919 1920 if (NXGE_IS_VALID_NEPTUNE_TYPE(nxgep)) { 1921 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1922 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1923 1924 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1925 "Neptune PCI regp cfg_ptr 0x%llx", (char *)cfg_ptr)); 1926 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1927 "Neptune PCI cfg_ptr vendor id ptr 0x%llx", 1928 &cfg_ptr->vendorid)); 1929 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1930 "\tvendorid 0x%x devid 0x%x", 1931 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->vendorid, 0), 1932 NXGE_PIO_READ16(cfg_handle, &cfg_ptr->devid, 0))); 1933 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1934 "PCI BAR: base 0x%x base14 0x%x base 18 0x%x " 1935 "bar1c 0x%x", 1936 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base, 0), 1937 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base14, 0), 1938 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base18, 0), 1939 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base1c, 0))); 1940 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1941 "\nNeptune PCI BAR: base20 0x%x base24 0x%x " 1942 "base 28 0x%x bar2c 0x%x\n", 1943 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base20, 0), 1944 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base24, 0), 1945 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base28, 0), 1946 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base2c, 0))); 1947 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1948 "\nNeptune PCI BAR: base30 0x%x\n", 1949 NXGE_PIO_READ32(cfg_handle, &cfg_ptr->base30, 0))); 1950 1951 cfg_handle = nxgep->dev_regs->nxge_pciregh; 1952 cfg_ptr = (void *)nxgep->dev_regs->nxge_pciregp; 1953 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1954 "first 0x%llx second 0x%llx third 0x%llx " 1955 "last 0x%llx ", 1956 NXGE_PIO_READ64(dev_handle, 1957 (uint64_t *)(dev_ptr + 0), 0), 1958 NXGE_PIO_READ64(dev_handle, 1959 (uint64_t *)(dev_ptr + 8), 0), 1960 NXGE_PIO_READ64(dev_handle, 1961 (uint64_t *)(dev_ptr + 16), 0), 1962 NXGE_PIO_READ64(cfg_handle, 1963 (uint64_t *)(dev_ptr + 24), 0))); 1964 } 1965 } 1966 1967 #endif 1968 1969 static void 1970 nxge_suspend(p_nxge_t nxgep) 1971 { 1972 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_suspend")); 1973 1974 nxge_intrs_disable(nxgep); 1975 nxge_destroy_dev(nxgep); 1976 1977 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_suspend")); 1978 } 1979 1980 static nxge_status_t 1981 nxge_resume(p_nxge_t nxgep) 1982 { 1983 nxge_status_t status = NXGE_OK; 1984 1985 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_resume")); 1986 1987 nxgep->suspended = DDI_RESUME; 1988 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 1989 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_START); 1990 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_START); 1991 (void) nxge_rx_mac_enable(nxgep); 1992 (void) nxge_tx_mac_enable(nxgep); 1993 nxge_intrs_enable(nxgep); 1994 nxgep->suspended = 0; 1995 1996 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1997 "<== nxge_resume status = 0x%x", status)); 1998 return (status); 1999 } 2000 2001 static nxge_status_t 2002 nxge_setup_dev(p_nxge_t nxgep) 2003 { 2004 nxge_status_t status = NXGE_OK; 2005 2006 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_setup_dev port %d", 2007 nxgep->mac.portnum)); 2008 2009 status = nxge_link_init(nxgep); 2010 2011 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 2012 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2013 "port%d Bad register acc handle", nxgep->mac.portnum)); 2014 status = NXGE_ERROR; 2015 } 2016 2017 if (status != NXGE_OK) { 2018 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2019 " nxge_setup_dev status " 2020 "(xcvr init 0x%08x)", status)); 2021 goto nxge_setup_dev_exit; 2022 } 2023 2024 nxge_setup_dev_exit: 2025 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2026 "<== nxge_setup_dev port %d status = 0x%08x", 2027 nxgep->mac.portnum, status)); 2028 2029 return (status); 2030 } 2031 2032 static void 2033 nxge_destroy_dev(p_nxge_t nxgep) 2034 { 2035 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_destroy_dev")); 2036 2037 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 2038 2039 (void) nxge_hw_stop(nxgep); 2040 2041 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_destroy_dev")); 2042 } 2043 2044 static nxge_status_t 2045 nxge_setup_system_dma_pages(p_nxge_t nxgep) 2046 { 2047 int ddi_status = DDI_SUCCESS; 2048 uint_t count; 2049 ddi_dma_cookie_t cookie; 2050 uint_t iommu_pagesize; 2051 nxge_status_t status = NXGE_OK; 2052 2053 NXGE_ERROR_MSG((nxgep, DDI_CTL, "==> nxge_setup_system_dma_pages")); 2054 nxgep->sys_page_sz = ddi_ptob(nxgep->dip, (ulong_t)1); 2055 if (nxgep->niu_type != N2_NIU) { 2056 iommu_pagesize = dvma_pagesize(nxgep->dip); 2057 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2058 " nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2059 " default_block_size %d iommu_pagesize %d", 2060 nxgep->sys_page_sz, 2061 ddi_ptob(nxgep->dip, (ulong_t)1), 2062 nxgep->rx_default_block_size, 2063 iommu_pagesize)); 2064 2065 if (iommu_pagesize != 0) { 2066 if (nxgep->sys_page_sz == iommu_pagesize) { 2067 if (iommu_pagesize > 0x4000) 2068 nxgep->sys_page_sz = 0x4000; 2069 } else { 2070 if (nxgep->sys_page_sz > iommu_pagesize) 2071 nxgep->sys_page_sz = iommu_pagesize; 2072 } 2073 } 2074 } 2075 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2076 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2077 "==> nxge_setup_system_dma_pages: page %d (ddi_ptob %d) " 2078 "default_block_size %d page mask %d", 2079 nxgep->sys_page_sz, 2080 ddi_ptob(nxgep->dip, (ulong_t)1), 2081 nxgep->rx_default_block_size, 2082 nxgep->sys_page_mask)); 2083 2084 2085 switch (nxgep->sys_page_sz) { 2086 default: 2087 nxgep->sys_page_sz = 0x1000; 2088 nxgep->sys_page_mask = ~(nxgep->sys_page_sz - 1); 2089 nxgep->rx_default_block_size = 0x1000; 2090 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2091 break; 2092 case 0x1000: 2093 nxgep->rx_default_block_size = 0x1000; 2094 nxgep->rx_bksize_code = RBR_BKSIZE_4K; 2095 break; 2096 case 0x2000: 2097 nxgep->rx_default_block_size = 0x2000; 2098 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2099 break; 2100 case 0x4000: 2101 nxgep->rx_default_block_size = 0x4000; 2102 nxgep->rx_bksize_code = RBR_BKSIZE_16K; 2103 break; 2104 case 0x8000: 2105 nxgep->rx_default_block_size = 0x8000; 2106 nxgep->rx_bksize_code = RBR_BKSIZE_32K; 2107 break; 2108 } 2109 2110 #ifndef USE_RX_BIG_BUF 2111 nxge_rx_dma_attr.dma_attr_align = nxgep->sys_page_sz; 2112 #else 2113 nxgep->rx_default_block_size = 0x2000; 2114 nxgep->rx_bksize_code = RBR_BKSIZE_8K; 2115 #endif 2116 /* 2117 * Get the system DMA burst size. 2118 */ 2119 ddi_status = ddi_dma_alloc_handle(nxgep->dip, &nxge_tx_dma_attr, 2120 DDI_DMA_DONTWAIT, 0, 2121 &nxgep->dmasparehandle); 2122 if (ddi_status != DDI_SUCCESS) { 2123 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2124 "ddi_dma_alloc_handle: failed " 2125 " status 0x%x", ddi_status)); 2126 goto nxge_get_soft_properties_exit; 2127 } 2128 2129 ddi_status = ddi_dma_addr_bind_handle(nxgep->dmasparehandle, NULL, 2130 (caddr_t)nxgep->dmasparehandle, 2131 sizeof (nxgep->dmasparehandle), 2132 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2133 DDI_DMA_DONTWAIT, 0, 2134 &cookie, &count); 2135 if (ddi_status != DDI_DMA_MAPPED) { 2136 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2137 "Binding spare handle to find system" 2138 " burstsize failed.")); 2139 ddi_status = DDI_FAILURE; 2140 goto nxge_get_soft_properties_fail1; 2141 } 2142 2143 nxgep->sys_burst_sz = ddi_dma_burstsizes(nxgep->dmasparehandle); 2144 (void) ddi_dma_unbind_handle(nxgep->dmasparehandle); 2145 2146 nxge_get_soft_properties_fail1: 2147 ddi_dma_free_handle(&nxgep->dmasparehandle); 2148 2149 nxge_get_soft_properties_exit: 2150 2151 if (ddi_status != DDI_SUCCESS) 2152 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2153 2154 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 2155 "<== nxge_setup_system_dma_pages status = 0x%08x", status)); 2156 return (status); 2157 } 2158 2159 static nxge_status_t 2160 nxge_alloc_mem_pool(p_nxge_t nxgep) 2161 { 2162 nxge_status_t status = NXGE_OK; 2163 2164 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_alloc_mem_pool")); 2165 2166 status = nxge_alloc_rx_mem_pool(nxgep); 2167 if (status != NXGE_OK) { 2168 return (NXGE_ERROR); 2169 } 2170 2171 status = nxge_alloc_tx_mem_pool(nxgep); 2172 if (status != NXGE_OK) { 2173 nxge_free_rx_mem_pool(nxgep); 2174 return (NXGE_ERROR); 2175 } 2176 2177 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_alloc_mem_pool")); 2178 return (NXGE_OK); 2179 } 2180 2181 static void 2182 nxge_free_mem_pool(p_nxge_t nxgep) 2183 { 2184 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_mem_pool")); 2185 2186 nxge_free_rx_mem_pool(nxgep); 2187 nxge_free_tx_mem_pool(nxgep); 2188 2189 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_mem_pool")); 2190 } 2191 2192 nxge_status_t 2193 nxge_alloc_rx_mem_pool(p_nxge_t nxgep) 2194 { 2195 uint32_t rdc_max; 2196 p_nxge_dma_pt_cfg_t p_all_cfgp; 2197 p_nxge_hw_pt_cfg_t p_cfgp; 2198 p_nxge_dma_pool_t dma_poolp; 2199 p_nxge_dma_common_t *dma_buf_p; 2200 p_nxge_dma_pool_t dma_cntl_poolp; 2201 p_nxge_dma_common_t *dma_cntl_p; 2202 uint32_t *num_chunks; /* per dma */ 2203 nxge_status_t status = NXGE_OK; 2204 2205 uint32_t nxge_port_rbr_size; 2206 uint32_t nxge_port_rbr_spare_size; 2207 uint32_t nxge_port_rcr_size; 2208 uint32_t rx_cntl_alloc_size; 2209 2210 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_mem_pool")); 2211 2212 p_all_cfgp = (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 2213 p_cfgp = (p_nxge_hw_pt_cfg_t)&p_all_cfgp->hw_config; 2214 rdc_max = NXGE_MAX_RDCS; 2215 2216 /* 2217 * Allocate memory for the common DMA data structures. 2218 */ 2219 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2220 KM_SLEEP); 2221 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2222 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2223 2224 dma_cntl_poolp = (p_nxge_dma_pool_t) 2225 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2226 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2227 sizeof (p_nxge_dma_common_t) * rdc_max, KM_SLEEP); 2228 2229 num_chunks = (uint32_t *)KMEM_ZALLOC( 2230 sizeof (uint32_t) * rdc_max, KM_SLEEP); 2231 2232 /* 2233 * Assume that each DMA channel will be configured with 2234 * the default block size. 2235 * rbr block counts are modulo the batch count (16). 2236 */ 2237 nxge_port_rbr_size = p_all_cfgp->rbr_size; 2238 nxge_port_rcr_size = p_all_cfgp->rcr_size; 2239 2240 if (!nxge_port_rbr_size) { 2241 nxge_port_rbr_size = NXGE_RBR_RBB_DEFAULT; 2242 } 2243 if (nxge_port_rbr_size % NXGE_RXDMA_POST_BATCH) { 2244 nxge_port_rbr_size = (NXGE_RXDMA_POST_BATCH * 2245 (nxge_port_rbr_size / NXGE_RXDMA_POST_BATCH + 1)); 2246 } 2247 2248 p_all_cfgp->rbr_size = nxge_port_rbr_size; 2249 nxge_port_rbr_spare_size = nxge_rbr_spare_size; 2250 2251 if (nxge_port_rbr_spare_size % NXGE_RXDMA_POST_BATCH) { 2252 nxge_port_rbr_spare_size = (NXGE_RXDMA_POST_BATCH * 2253 (nxge_port_rbr_spare_size / NXGE_RXDMA_POST_BATCH + 1)); 2254 } 2255 if (nxge_port_rbr_size > RBR_DEFAULT_MAX_BLKS) { 2256 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2257 "nxge_alloc_rx_mem_pool: RBR size too high %d, " 2258 "set to default %d", 2259 nxge_port_rbr_size, RBR_DEFAULT_MAX_BLKS)); 2260 nxge_port_rbr_size = RBR_DEFAULT_MAX_BLKS; 2261 } 2262 if (nxge_port_rcr_size > RCR_DEFAULT_MAX) { 2263 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2264 "nxge_alloc_rx_mem_pool: RCR too high %d, " 2265 "set to default %d", 2266 nxge_port_rcr_size, RCR_DEFAULT_MAX)); 2267 nxge_port_rcr_size = RCR_DEFAULT_MAX; 2268 } 2269 2270 /* 2271 * N2/NIU has limitation on the descriptor sizes (contiguous 2272 * memory allocation on data buffers to 4M (contig_mem_alloc) 2273 * and little endian for control buffers (must use the ddi/dki mem alloc 2274 * function). 2275 */ 2276 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2277 if (nxgep->niu_type == N2_NIU) { 2278 nxge_port_rbr_spare_size = 0; 2279 if ((nxge_port_rbr_size > NXGE_NIU_CONTIG_RBR_MAX) || 2280 (!ISP2(nxge_port_rbr_size))) { 2281 nxge_port_rbr_size = NXGE_NIU_CONTIG_RBR_MAX; 2282 } 2283 if ((nxge_port_rcr_size > NXGE_NIU_CONTIG_RCR_MAX) || 2284 (!ISP2(nxge_port_rcr_size))) { 2285 nxge_port_rcr_size = NXGE_NIU_CONTIG_RCR_MAX; 2286 } 2287 } 2288 #endif 2289 2290 /* 2291 * Addresses of receive block ring, receive completion ring and the 2292 * mailbox must be all cache-aligned (64 bytes). 2293 */ 2294 rx_cntl_alloc_size = nxge_port_rbr_size + nxge_port_rbr_spare_size; 2295 rx_cntl_alloc_size *= (sizeof (rx_desc_t)); 2296 rx_cntl_alloc_size += (sizeof (rcr_entry_t) * nxge_port_rcr_size); 2297 rx_cntl_alloc_size += sizeof (rxdma_mailbox_t); 2298 2299 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_alloc_rx_mem_pool: " 2300 "nxge_port_rbr_size = %d nxge_port_rbr_spare_size = %d " 2301 "nxge_port_rcr_size = %d " 2302 "rx_cntl_alloc_size = %d", 2303 nxge_port_rbr_size, nxge_port_rbr_spare_size, 2304 nxge_port_rcr_size, 2305 rx_cntl_alloc_size)); 2306 2307 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2308 if (nxgep->niu_type == N2_NIU) { 2309 uint32_t rx_buf_alloc_size = (nxgep->rx_default_block_size * 2310 (nxge_port_rbr_size + nxge_port_rbr_spare_size)); 2311 2312 if (!ISP2(rx_buf_alloc_size)) { 2313 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2314 "==> nxge_alloc_rx_mem_pool: " 2315 " must be power of 2")); 2316 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2317 goto nxge_alloc_rx_mem_pool_exit; 2318 } 2319 2320 if (rx_buf_alloc_size > (1 << 22)) { 2321 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2322 "==> nxge_alloc_rx_mem_pool: " 2323 " limit size to 4M")); 2324 status |= (NXGE_ERROR | NXGE_DDI_FAILED); 2325 goto nxge_alloc_rx_mem_pool_exit; 2326 } 2327 2328 if (rx_cntl_alloc_size < 0x2000) { 2329 rx_cntl_alloc_size = 0x2000; 2330 } 2331 } 2332 #endif 2333 nxgep->nxge_port_rbr_size = nxge_port_rbr_size; 2334 nxgep->nxge_port_rcr_size = nxge_port_rcr_size; 2335 nxgep->nxge_port_rbr_spare_size = nxge_port_rbr_spare_size; 2336 nxgep->nxge_port_rx_cntl_alloc_size = rx_cntl_alloc_size; 2337 2338 dma_poolp->ndmas = p_cfgp->max_rdcs; 2339 dma_poolp->num_chunks = num_chunks; 2340 dma_poolp->buf_allocated = B_TRUE; 2341 nxgep->rx_buf_pool_p = dma_poolp; 2342 dma_poolp->dma_buf_pool_p = dma_buf_p; 2343 2344 dma_cntl_poolp->ndmas = p_cfgp->max_rdcs; 2345 dma_cntl_poolp->buf_allocated = B_TRUE; 2346 nxgep->rx_cntl_pool_p = dma_cntl_poolp; 2347 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 2348 2349 /* Allocate the receive rings, too. */ 2350 nxgep->rx_rbr_rings = 2351 KMEM_ZALLOC(sizeof (rx_rbr_rings_t), KM_SLEEP); 2352 nxgep->rx_rbr_rings->rbr_rings = 2353 KMEM_ZALLOC(sizeof (p_rx_rbr_ring_t) * rdc_max, KM_SLEEP); 2354 nxgep->rx_rcr_rings = 2355 KMEM_ZALLOC(sizeof (rx_rcr_rings_t), KM_SLEEP); 2356 nxgep->rx_rcr_rings->rcr_rings = 2357 KMEM_ZALLOC(sizeof (p_rx_rcr_ring_t) * rdc_max, KM_SLEEP); 2358 nxgep->rx_mbox_areas_p = 2359 KMEM_ZALLOC(sizeof (rx_mbox_areas_t), KM_SLEEP); 2360 nxgep->rx_mbox_areas_p->rxmbox_areas = 2361 KMEM_ZALLOC(sizeof (p_rx_mbox_t) * rdc_max, KM_SLEEP); 2362 2363 nxgep->rx_rbr_rings->ndmas = nxgep->rx_rcr_rings->ndmas = 2364 p_cfgp->max_rdcs; 2365 2366 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2367 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2368 2369 nxge_alloc_rx_mem_pool_exit: 2370 return (status); 2371 } 2372 2373 /* 2374 * nxge_alloc_rxb 2375 * 2376 * Allocate buffers for an RDC. 2377 * 2378 * Arguments: 2379 * nxgep 2380 * channel The channel to map into our kernel space. 2381 * 2382 * Notes: 2383 * 2384 * NPI function calls: 2385 * 2386 * NXGE function calls: 2387 * 2388 * Registers accessed: 2389 * 2390 * Context: 2391 * 2392 * Taking apart: 2393 * 2394 * Open questions: 2395 * 2396 */ 2397 nxge_status_t 2398 nxge_alloc_rxb( 2399 p_nxge_t nxgep, 2400 int channel) 2401 { 2402 size_t rx_buf_alloc_size; 2403 nxge_status_t status = NXGE_OK; 2404 2405 nxge_dma_common_t **data; 2406 nxge_dma_common_t **control; 2407 uint32_t *num_chunks; 2408 2409 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2410 2411 /* 2412 * Allocate memory for the receive buffers and descriptor rings. 2413 * Replace these allocation functions with the interface functions 2414 * provided by the partition manager if/when they are available. 2415 */ 2416 2417 /* 2418 * Allocate memory for the receive buffer blocks. 2419 */ 2420 rx_buf_alloc_size = (nxgep->rx_default_block_size * 2421 (nxgep->nxge_port_rbr_size + nxgep->nxge_port_rbr_spare_size)); 2422 2423 data = &nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2424 num_chunks = &nxgep->rx_buf_pool_p->num_chunks[channel]; 2425 2426 if ((status = nxge_alloc_rx_buf_dma( 2427 nxgep, channel, data, rx_buf_alloc_size, 2428 nxgep->rx_default_block_size, num_chunks)) != NXGE_OK) { 2429 return (status); 2430 } 2431 2432 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_alloc_rxb(): " 2433 "dma %d dma_buf_p %llx &dma_buf_p %llx", channel, *data, data)); 2434 2435 /* 2436 * Allocate memory for descriptor rings and mailbox. 2437 */ 2438 control = &nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2439 2440 if ((status = nxge_alloc_rx_cntl_dma( 2441 nxgep, channel, control, nxgep->nxge_port_rx_cntl_alloc_size)) 2442 != NXGE_OK) { 2443 nxge_free_rx_cntl_dma(nxgep, *control); 2444 (*data)->buf_alloc_state |= BUF_ALLOCATED_WAIT_FREE; 2445 nxge_free_rx_buf_dma(nxgep, *data, *num_chunks); 2446 return (status); 2447 } 2448 2449 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2450 "<== nxge_alloc_rx_mem_pool:status 0x%08x", status)); 2451 2452 return (status); 2453 } 2454 2455 void 2456 nxge_free_rxb( 2457 p_nxge_t nxgep, 2458 int channel) 2459 { 2460 nxge_dma_common_t *data; 2461 nxge_dma_common_t *control; 2462 uint32_t num_chunks; 2463 2464 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rbb")); 2465 2466 data = nxgep->rx_buf_pool_p->dma_buf_pool_p[channel]; 2467 num_chunks = nxgep->rx_buf_pool_p->num_chunks[channel]; 2468 nxge_free_rx_buf_dma(nxgep, data, num_chunks); 2469 2470 nxgep->rx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2471 nxgep->rx_buf_pool_p->num_chunks[channel] = 0; 2472 2473 control = nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel]; 2474 nxge_free_rx_cntl_dma(nxgep, control); 2475 2476 nxgep->rx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2477 2478 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2479 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2480 2481 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_alloc_rbb")); 2482 } 2483 2484 static void 2485 nxge_free_rx_mem_pool(p_nxge_t nxgep) 2486 { 2487 int rdc_max = NXGE_MAX_RDCS; 2488 2489 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_mem_pool")); 2490 2491 if (!nxgep->rx_buf_pool_p || !nxgep->rx_buf_pool_p->buf_allocated) { 2492 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2493 "<== nxge_free_rx_mem_pool " 2494 "(null rx buf pool or buf not allocated")); 2495 return; 2496 } 2497 if (!nxgep->rx_cntl_pool_p || !nxgep->rx_cntl_pool_p->buf_allocated) { 2498 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2499 "<== nxge_free_rx_mem_pool " 2500 "(null rx cntl buf pool or cntl buf not allocated")); 2501 return; 2502 } 2503 2504 KMEM_FREE(nxgep->rx_cntl_pool_p->dma_buf_pool_p, 2505 sizeof (p_nxge_dma_common_t) * rdc_max); 2506 KMEM_FREE(nxgep->rx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 2507 2508 KMEM_FREE(nxgep->rx_buf_pool_p->num_chunks, 2509 sizeof (uint32_t) * rdc_max); 2510 KMEM_FREE(nxgep->rx_buf_pool_p->dma_buf_pool_p, 2511 sizeof (p_nxge_dma_common_t) * rdc_max); 2512 KMEM_FREE(nxgep->rx_buf_pool_p, sizeof (nxge_dma_pool_t)); 2513 2514 nxgep->rx_buf_pool_p = 0; 2515 nxgep->rx_cntl_pool_p = 0; 2516 2517 KMEM_FREE(nxgep->rx_rbr_rings->rbr_rings, 2518 sizeof (p_rx_rbr_ring_t) * rdc_max); 2519 KMEM_FREE(nxgep->rx_rbr_rings, sizeof (rx_rbr_rings_t)); 2520 KMEM_FREE(nxgep->rx_rcr_rings->rcr_rings, 2521 sizeof (p_rx_rcr_ring_t) * rdc_max); 2522 KMEM_FREE(nxgep->rx_rcr_rings, sizeof (rx_rcr_rings_t)); 2523 KMEM_FREE(nxgep->rx_mbox_areas_p->rxmbox_areas, 2524 sizeof (p_rx_mbox_t) * rdc_max); 2525 KMEM_FREE(nxgep->rx_mbox_areas_p, sizeof (rx_mbox_areas_t)); 2526 2527 nxgep->rx_rbr_rings = 0; 2528 nxgep->rx_rcr_rings = 0; 2529 nxgep->rx_mbox_areas_p = 0; 2530 2531 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_rx_mem_pool")); 2532 } 2533 2534 2535 static nxge_status_t 2536 nxge_alloc_rx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 2537 p_nxge_dma_common_t *dmap, 2538 size_t alloc_size, size_t block_size, uint32_t *num_chunks) 2539 { 2540 p_nxge_dma_common_t rx_dmap; 2541 nxge_status_t status = NXGE_OK; 2542 size_t total_alloc_size; 2543 size_t allocated = 0; 2544 int i, size_index, array_size; 2545 boolean_t use_kmem_alloc = B_FALSE; 2546 2547 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_buf_dma")); 2548 2549 rx_dmap = (p_nxge_dma_common_t) 2550 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 2551 KM_SLEEP); 2552 2553 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2554 " alloc_rx_buf_dma rdc %d asize %x bsize %x bbuf %llx ", 2555 dma_channel, alloc_size, block_size, dmap)); 2556 2557 total_alloc_size = alloc_size; 2558 2559 #if defined(RX_USE_RECLAIM_POST) 2560 total_alloc_size = alloc_size + alloc_size/4; 2561 #endif 2562 2563 i = 0; 2564 size_index = 0; 2565 array_size = sizeof (alloc_sizes)/sizeof (size_t); 2566 while ((alloc_sizes[size_index] < alloc_size) && 2567 (size_index < array_size)) 2568 size_index++; 2569 if (size_index >= array_size) { 2570 size_index = array_size - 1; 2571 } 2572 2573 /* For Neptune, use kmem_alloc if the kmem flag is set. */ 2574 if (nxgep->niu_type != N2_NIU && nxge_use_kmem_alloc) { 2575 use_kmem_alloc = B_TRUE; 2576 #if defined(__i386) || defined(__amd64) 2577 size_index = 0; 2578 #endif 2579 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2580 "==> nxge_alloc_rx_buf_dma: " 2581 "Neptune use kmem_alloc() - size_index %d", 2582 size_index)); 2583 } 2584 2585 while ((allocated < total_alloc_size) && 2586 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 2587 rx_dmap[i].dma_chunk_index = i; 2588 rx_dmap[i].block_size = block_size; 2589 rx_dmap[i].alength = alloc_sizes[size_index]; 2590 rx_dmap[i].orig_alength = rx_dmap[i].alength; 2591 rx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 2592 rx_dmap[i].dma_channel = dma_channel; 2593 rx_dmap[i].contig_alloc_type = B_FALSE; 2594 rx_dmap[i].kmem_alloc_type = B_FALSE; 2595 rx_dmap[i].buf_alloc_type = DDI_MEM_ALLOC; 2596 2597 /* 2598 * N2/NIU: data buffers must be contiguous as the driver 2599 * needs to call Hypervisor api to set up 2600 * logical pages. 2601 */ 2602 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 2603 rx_dmap[i].contig_alloc_type = B_TRUE; 2604 rx_dmap[i].buf_alloc_type = CONTIG_MEM_ALLOC; 2605 } else if (use_kmem_alloc) { 2606 /* For Neptune, use kmem_alloc */ 2607 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2608 "==> nxge_alloc_rx_buf_dma: " 2609 "Neptune use kmem_alloc()")); 2610 rx_dmap[i].kmem_alloc_type = B_TRUE; 2611 rx_dmap[i].buf_alloc_type = KMEM_ALLOC; 2612 } 2613 2614 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2615 "alloc_rx_buf_dma rdc %d chunk %d bufp %llx size %x " 2616 "i %d nblocks %d alength %d", 2617 dma_channel, i, &rx_dmap[i], block_size, 2618 i, rx_dmap[i].nblocks, 2619 rx_dmap[i].alength)); 2620 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2621 &nxge_rx_dma_attr, 2622 rx_dmap[i].alength, 2623 &nxge_dev_buf_dma_acc_attr, 2624 DDI_DMA_READ | DDI_DMA_STREAMING, 2625 (p_nxge_dma_common_t)(&rx_dmap[i])); 2626 if (status != NXGE_OK) { 2627 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2628 "nxge_alloc_rx_buf_dma: Alloc Failed: " 2629 "dma %d size_index %d size requested %d", 2630 dma_channel, 2631 size_index, 2632 rx_dmap[i].alength)); 2633 size_index--; 2634 } else { 2635 rx_dmap[i].buf_alloc_state = BUF_ALLOCATED; 2636 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2637 " nxge_alloc_rx_buf_dma DONE alloc mem: " 2638 "dma %d dma_buf_p $%p kaddrp $%p alength %d " 2639 "buf_alloc_state %d alloc_type %d", 2640 dma_channel, 2641 &rx_dmap[i], 2642 rx_dmap[i].kaddrp, 2643 rx_dmap[i].alength, 2644 rx_dmap[i].buf_alloc_state, 2645 rx_dmap[i].buf_alloc_type)); 2646 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2647 " alloc_rx_buf_dma allocated rdc %d " 2648 "chunk %d size %x dvma %x bufp %llx kaddrp $%p", 2649 dma_channel, i, rx_dmap[i].alength, 2650 rx_dmap[i].ioaddr_pp, &rx_dmap[i], 2651 rx_dmap[i].kaddrp)); 2652 i++; 2653 allocated += alloc_sizes[size_index]; 2654 } 2655 } 2656 2657 if (allocated < total_alloc_size) { 2658 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2659 "==> nxge_alloc_rx_buf_dma: not enough for channel %d " 2660 "allocated 0x%x requested 0x%x", 2661 dma_channel, 2662 allocated, total_alloc_size)); 2663 status = NXGE_ERROR; 2664 goto nxge_alloc_rx_mem_fail1; 2665 } 2666 2667 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2668 "==> nxge_alloc_rx_buf_dma: Allocated for channel %d " 2669 "allocated 0x%x requested 0x%x", 2670 dma_channel, 2671 allocated, total_alloc_size)); 2672 2673 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2674 " alloc_rx_buf_dma rdc %d allocated %d chunks", 2675 dma_channel, i)); 2676 *num_chunks = i; 2677 *dmap = rx_dmap; 2678 2679 goto nxge_alloc_rx_mem_exit; 2680 2681 nxge_alloc_rx_mem_fail1: 2682 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2683 2684 nxge_alloc_rx_mem_exit: 2685 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2686 "<== nxge_alloc_rx_buf_dma status 0x%08x", status)); 2687 2688 return (status); 2689 } 2690 2691 /*ARGSUSED*/ 2692 static void 2693 nxge_free_rx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 2694 uint32_t num_chunks) 2695 { 2696 int i; 2697 2698 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2699 "==> nxge_free_rx_buf_dma: # of chunks %d", num_chunks)); 2700 2701 if (dmap == 0) 2702 return; 2703 2704 for (i = 0; i < num_chunks; i++) { 2705 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 2706 "==> nxge_free_rx_buf_dma: chunk %d dmap 0x%llx", 2707 i, dmap)); 2708 nxge_dma_free_rx_data_buf(dmap++); 2709 } 2710 2711 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_rx_buf_dma")); 2712 } 2713 2714 /*ARGSUSED*/ 2715 static nxge_status_t 2716 nxge_alloc_rx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 2717 p_nxge_dma_common_t *dmap, size_t size) 2718 { 2719 p_nxge_dma_common_t rx_dmap; 2720 nxge_status_t status = NXGE_OK; 2721 2722 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_rx_cntl_dma")); 2723 2724 rx_dmap = (p_nxge_dma_common_t) 2725 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 2726 2727 rx_dmap->contig_alloc_type = B_FALSE; 2728 rx_dmap->kmem_alloc_type = B_FALSE; 2729 2730 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 2731 &nxge_desc_dma_attr, 2732 size, 2733 &nxge_dev_desc_dma_acc_attr, 2734 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2735 rx_dmap); 2736 if (status != NXGE_OK) { 2737 goto nxge_alloc_rx_cntl_dma_fail1; 2738 } 2739 2740 *dmap = rx_dmap; 2741 goto nxge_alloc_rx_cntl_dma_exit; 2742 2743 nxge_alloc_rx_cntl_dma_fail1: 2744 KMEM_FREE(rx_dmap, sizeof (nxge_dma_common_t)); 2745 2746 nxge_alloc_rx_cntl_dma_exit: 2747 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2748 "<== nxge_alloc_rx_cntl_dma status 0x%08x", status)); 2749 2750 return (status); 2751 } 2752 2753 /*ARGSUSED*/ 2754 static void 2755 nxge_free_rx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 2756 { 2757 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_rx_cntl_dma")); 2758 2759 if (dmap == 0) 2760 return; 2761 2762 nxge_dma_mem_free(dmap); 2763 2764 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_rx_cntl_dma")); 2765 } 2766 2767 typedef struct { 2768 size_t tx_size; 2769 size_t cr_size; 2770 size_t threshhold; 2771 } nxge_tdc_sizes_t; 2772 2773 static 2774 nxge_status_t 2775 nxge_tdc_sizes( 2776 nxge_t *nxgep, 2777 nxge_tdc_sizes_t *sizes) 2778 { 2779 uint32_t threshhold; /* The bcopy() threshhold */ 2780 size_t tx_size; /* Transmit buffer size */ 2781 size_t cr_size; /* Completion ring size */ 2782 2783 /* 2784 * Assume that each DMA channel will be configured with the 2785 * default transmit buffer size for copying transmit data. 2786 * (If a packet is bigger than this, it will not be copied.) 2787 */ 2788 if (nxgep->niu_type == N2_NIU) { 2789 threshhold = TX_BCOPY_SIZE; 2790 } else { 2791 threshhold = nxge_bcopy_thresh; 2792 } 2793 tx_size = nxge_tx_ring_size * threshhold; 2794 2795 cr_size = nxge_tx_ring_size * sizeof (tx_desc_t); 2796 cr_size += sizeof (txdma_mailbox_t); 2797 2798 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2799 if (nxgep->niu_type == N2_NIU) { 2800 if (!ISP2(tx_size)) { 2801 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2802 "==> nxge_tdc_sizes: Tx size" 2803 " must be power of 2")); 2804 return (NXGE_ERROR); 2805 } 2806 2807 if (tx_size > (1 << 22)) { 2808 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 2809 "==> nxge_tdc_sizes: Tx size" 2810 " limited to 4M")); 2811 return (NXGE_ERROR); 2812 } 2813 2814 if (cr_size < 0x2000) 2815 cr_size = 0x2000; 2816 } 2817 #endif 2818 2819 sizes->threshhold = threshhold; 2820 sizes->tx_size = tx_size; 2821 sizes->cr_size = cr_size; 2822 2823 return (NXGE_OK); 2824 } 2825 /* 2826 * nxge_alloc_txb 2827 * 2828 * Allocate buffers for an TDC. 2829 * 2830 * Arguments: 2831 * nxgep 2832 * channel The channel to map into our kernel space. 2833 * 2834 * Notes: 2835 * 2836 * NPI function calls: 2837 * 2838 * NXGE function calls: 2839 * 2840 * Registers accessed: 2841 * 2842 * Context: 2843 * 2844 * Taking apart: 2845 * 2846 * Open questions: 2847 * 2848 */ 2849 nxge_status_t 2850 nxge_alloc_txb( 2851 p_nxge_t nxgep, 2852 int channel) 2853 { 2854 nxge_dma_common_t **dma_buf_p; 2855 nxge_dma_common_t **dma_cntl_p; 2856 uint32_t *num_chunks; 2857 nxge_status_t status = NXGE_OK; 2858 2859 nxge_tdc_sizes_t sizes; 2860 2861 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tbb")); 2862 2863 if (nxge_tdc_sizes(nxgep, &sizes) != NXGE_OK) 2864 return (NXGE_ERROR); 2865 2866 /* 2867 * Allocate memory for transmit buffers and descriptor rings. 2868 * Replace these allocation functions with the interface functions 2869 * provided by the partition manager Real Soon Now. 2870 */ 2871 dma_buf_p = &nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2872 num_chunks = &nxgep->tx_buf_pool_p->num_chunks[channel]; 2873 2874 dma_cntl_p = &nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2875 2876 /* 2877 * Allocate memory for transmit buffers and descriptor rings. 2878 * Replace allocation functions with interface functions provided 2879 * by the partition manager when it is available. 2880 * 2881 * Allocate memory for the transmit buffer pool. 2882 */ 2883 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 2884 "sizes: tx: %ld, cr:%ld, th:%ld", 2885 sizes.tx_size, sizes.cr_size, sizes.threshhold)); 2886 2887 *num_chunks = 0; 2888 status = nxge_alloc_tx_buf_dma(nxgep, channel, dma_buf_p, 2889 sizes.tx_size, sizes.threshhold, num_chunks); 2890 if (status != NXGE_OK) { 2891 cmn_err(CE_NOTE, "nxge_alloc_tx_buf_dma failed!"); 2892 return (status); 2893 } 2894 2895 /* 2896 * Allocate memory for descriptor rings and mailbox. 2897 */ 2898 status = nxge_alloc_tx_cntl_dma(nxgep, channel, dma_cntl_p, 2899 sizes.cr_size); 2900 if (status != NXGE_OK) { 2901 nxge_free_tx_buf_dma(nxgep, *dma_buf_p, *num_chunks); 2902 cmn_err(CE_NOTE, "nxge_alloc_tx_cntl_dma failed!"); 2903 return (status); 2904 } 2905 2906 return (NXGE_OK); 2907 } 2908 2909 void 2910 nxge_free_txb( 2911 p_nxge_t nxgep, 2912 int channel) 2913 { 2914 nxge_dma_common_t *data; 2915 nxge_dma_common_t *control; 2916 uint32_t num_chunks; 2917 2918 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_txb")); 2919 2920 data = nxgep->tx_buf_pool_p->dma_buf_pool_p[channel]; 2921 num_chunks = nxgep->tx_buf_pool_p->num_chunks[channel]; 2922 nxge_free_tx_buf_dma(nxgep, data, num_chunks); 2923 2924 nxgep->tx_buf_pool_p->dma_buf_pool_p[channel] = 0; 2925 nxgep->tx_buf_pool_p->num_chunks[channel] = 0; 2926 2927 control = nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel]; 2928 nxge_free_tx_cntl_dma(nxgep, control); 2929 2930 nxgep->tx_cntl_pool_p->dma_buf_pool_p[channel] = 0; 2931 2932 KMEM_FREE(data, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 2933 KMEM_FREE(control, sizeof (nxge_dma_common_t)); 2934 2935 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_txb")); 2936 } 2937 2938 /* 2939 * nxge_alloc_tx_mem_pool 2940 * 2941 * This function allocates all of the per-port TDC control data structures. 2942 * The per-channel (TDC) data structures are allocated when needed. 2943 * 2944 * Arguments: 2945 * nxgep 2946 * 2947 * Notes: 2948 * 2949 * Context: 2950 * Any domain 2951 */ 2952 nxge_status_t 2953 nxge_alloc_tx_mem_pool(p_nxge_t nxgep) 2954 { 2955 nxge_hw_pt_cfg_t *p_cfgp; 2956 nxge_dma_pool_t *dma_poolp; 2957 nxge_dma_common_t **dma_buf_p; 2958 nxge_dma_pool_t *dma_cntl_poolp; 2959 nxge_dma_common_t **dma_cntl_p; 2960 uint32_t *num_chunks; /* per dma */ 2961 int tdc_max; 2962 2963 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_alloc_tx_mem_pool")); 2964 2965 p_cfgp = &nxgep->pt_config.hw_config; 2966 tdc_max = NXGE_MAX_TDCS; 2967 2968 /* 2969 * Allocate memory for each transmit DMA channel. 2970 */ 2971 dma_poolp = (p_nxge_dma_pool_t)KMEM_ZALLOC(sizeof (nxge_dma_pool_t), 2972 KM_SLEEP); 2973 dma_buf_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2974 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2975 2976 dma_cntl_poolp = (p_nxge_dma_pool_t) 2977 KMEM_ZALLOC(sizeof (nxge_dma_pool_t), KM_SLEEP); 2978 dma_cntl_p = (p_nxge_dma_common_t *)KMEM_ZALLOC( 2979 sizeof (p_nxge_dma_common_t) * tdc_max, KM_SLEEP); 2980 2981 if (nxge_tx_ring_size > TDC_DEFAULT_MAX) { 2982 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 2983 "nxge_alloc_tx_mem_pool: TDC too high %d, " 2984 "set to default %d", 2985 nxge_tx_ring_size, TDC_DEFAULT_MAX)); 2986 nxge_tx_ring_size = TDC_DEFAULT_MAX; 2987 } 2988 2989 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 2990 /* 2991 * N2/NIU has limitation on the descriptor sizes (contiguous 2992 * memory allocation on data buffers to 4M (contig_mem_alloc) 2993 * and little endian for control buffers (must use the ddi/dki mem alloc 2994 * function). The transmit ring is limited to 8K (includes the 2995 * mailbox). 2996 */ 2997 if (nxgep->niu_type == N2_NIU) { 2998 if ((nxge_tx_ring_size > NXGE_NIU_CONTIG_TX_MAX) || 2999 (!ISP2(nxge_tx_ring_size))) { 3000 nxge_tx_ring_size = NXGE_NIU_CONTIG_TX_MAX; 3001 } 3002 } 3003 #endif 3004 3005 nxgep->nxge_port_tx_ring_size = nxge_tx_ring_size; 3006 3007 num_chunks = (uint32_t *)KMEM_ZALLOC( 3008 sizeof (uint32_t) * tdc_max, KM_SLEEP); 3009 3010 dma_poolp->ndmas = p_cfgp->tdc.owned; 3011 dma_poolp->num_chunks = num_chunks; 3012 dma_poolp->dma_buf_pool_p = dma_buf_p; 3013 nxgep->tx_buf_pool_p = dma_poolp; 3014 3015 dma_poolp->buf_allocated = B_TRUE; 3016 3017 dma_cntl_poolp->ndmas = p_cfgp->tdc.owned; 3018 dma_cntl_poolp->dma_buf_pool_p = dma_cntl_p; 3019 nxgep->tx_cntl_pool_p = dma_cntl_poolp; 3020 3021 dma_cntl_poolp->buf_allocated = B_TRUE; 3022 3023 nxgep->tx_rings = 3024 KMEM_ZALLOC(sizeof (tx_rings_t), KM_SLEEP); 3025 nxgep->tx_rings->rings = 3026 KMEM_ZALLOC(sizeof (p_tx_ring_t) * tdc_max, KM_SLEEP); 3027 nxgep->tx_mbox_areas_p = 3028 KMEM_ZALLOC(sizeof (tx_mbox_areas_t), KM_SLEEP); 3029 nxgep->tx_mbox_areas_p->txmbox_areas_p = 3030 KMEM_ZALLOC(sizeof (p_tx_mbox_t) * tdc_max, KM_SLEEP); 3031 3032 nxgep->tx_rings->ndmas = p_cfgp->tdc.owned; 3033 3034 NXGE_DEBUG_MSG((nxgep, MEM_CTL, 3035 "==> nxge_alloc_tx_mem_pool: ndmas %d poolp->ndmas %d", 3036 tdc_max, dma_poolp->ndmas)); 3037 3038 return (NXGE_OK); 3039 } 3040 3041 nxge_status_t 3042 nxge_alloc_tx_buf_dma(p_nxge_t nxgep, uint16_t dma_channel, 3043 p_nxge_dma_common_t *dmap, size_t alloc_size, 3044 size_t block_size, uint32_t *num_chunks) 3045 { 3046 p_nxge_dma_common_t tx_dmap; 3047 nxge_status_t status = NXGE_OK; 3048 size_t total_alloc_size; 3049 size_t allocated = 0; 3050 int i, size_index, array_size; 3051 3052 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_buf_dma")); 3053 3054 tx_dmap = (p_nxge_dma_common_t) 3055 KMEM_ZALLOC(sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK, 3056 KM_SLEEP); 3057 3058 total_alloc_size = alloc_size; 3059 i = 0; 3060 size_index = 0; 3061 array_size = sizeof (alloc_sizes) / sizeof (size_t); 3062 while ((alloc_sizes[size_index] < alloc_size) && 3063 (size_index < array_size)) 3064 size_index++; 3065 if (size_index >= array_size) { 3066 size_index = array_size - 1; 3067 } 3068 3069 while ((allocated < total_alloc_size) && 3070 (size_index >= 0) && (i < NXGE_DMA_BLOCK)) { 3071 3072 tx_dmap[i].dma_chunk_index = i; 3073 tx_dmap[i].block_size = block_size; 3074 tx_dmap[i].alength = alloc_sizes[size_index]; 3075 tx_dmap[i].orig_alength = tx_dmap[i].alength; 3076 tx_dmap[i].nblocks = alloc_sizes[size_index] / block_size; 3077 tx_dmap[i].dma_channel = dma_channel; 3078 tx_dmap[i].contig_alloc_type = B_FALSE; 3079 tx_dmap[i].kmem_alloc_type = B_FALSE; 3080 3081 /* 3082 * N2/NIU: data buffers must be contiguous as the driver 3083 * needs to call Hypervisor api to set up 3084 * logical pages. 3085 */ 3086 if ((nxgep->niu_type == N2_NIU) && (NXGE_DMA_BLOCK == 1)) { 3087 tx_dmap[i].contig_alloc_type = B_TRUE; 3088 } 3089 3090 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3091 &nxge_tx_dma_attr, 3092 tx_dmap[i].alength, 3093 &nxge_dev_buf_dma_acc_attr, 3094 DDI_DMA_WRITE | DDI_DMA_STREAMING, 3095 (p_nxge_dma_common_t)(&tx_dmap[i])); 3096 if (status != NXGE_OK) { 3097 size_index--; 3098 } else { 3099 i++; 3100 allocated += alloc_sizes[size_index]; 3101 } 3102 } 3103 3104 if (allocated < total_alloc_size) { 3105 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3106 "==> nxge_alloc_tx_buf_dma: not enough channel %d: " 3107 "allocated 0x%x requested 0x%x", 3108 dma_channel, 3109 allocated, total_alloc_size)); 3110 status = NXGE_ERROR; 3111 goto nxge_alloc_tx_mem_fail1; 3112 } 3113 3114 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3115 "==> nxge_alloc_tx_buf_dma: Allocated for channel %d: " 3116 "allocated 0x%x requested 0x%x", 3117 dma_channel, 3118 allocated, total_alloc_size)); 3119 3120 *num_chunks = i; 3121 *dmap = tx_dmap; 3122 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3123 "==> nxge_alloc_tx_buf_dma dmap 0x%016llx num chunks %d", 3124 *dmap, i)); 3125 goto nxge_alloc_tx_mem_exit; 3126 3127 nxge_alloc_tx_mem_fail1: 3128 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t) * NXGE_DMA_BLOCK); 3129 3130 nxge_alloc_tx_mem_exit: 3131 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3132 "<== nxge_alloc_tx_buf_dma status 0x%08x", status)); 3133 3134 return (status); 3135 } 3136 3137 /*ARGSUSED*/ 3138 static void 3139 nxge_free_tx_buf_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap, 3140 uint32_t num_chunks) 3141 { 3142 int i; 3143 3144 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "==> nxge_free_tx_buf_dma")); 3145 3146 if (dmap == 0) 3147 return; 3148 3149 for (i = 0; i < num_chunks; i++) { 3150 nxge_dma_mem_free(dmap++); 3151 } 3152 3153 NXGE_DEBUG_MSG((nxgep, MEM_CTL, "<== nxge_free_tx_buf_dma")); 3154 } 3155 3156 /*ARGSUSED*/ 3157 nxge_status_t 3158 nxge_alloc_tx_cntl_dma(p_nxge_t nxgep, uint16_t dma_channel, 3159 p_nxge_dma_common_t *dmap, size_t size) 3160 { 3161 p_nxge_dma_common_t tx_dmap; 3162 nxge_status_t status = NXGE_OK; 3163 3164 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_alloc_tx_cntl_dma")); 3165 tx_dmap = (p_nxge_dma_common_t) 3166 KMEM_ZALLOC(sizeof (nxge_dma_common_t), KM_SLEEP); 3167 3168 tx_dmap->contig_alloc_type = B_FALSE; 3169 tx_dmap->kmem_alloc_type = B_FALSE; 3170 3171 status = nxge_dma_mem_alloc(nxgep, nxge_force_dma, 3172 &nxge_desc_dma_attr, 3173 size, 3174 &nxge_dev_desc_dma_acc_attr, 3175 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3176 tx_dmap); 3177 if (status != NXGE_OK) { 3178 goto nxge_alloc_tx_cntl_dma_fail1; 3179 } 3180 3181 *dmap = tx_dmap; 3182 goto nxge_alloc_tx_cntl_dma_exit; 3183 3184 nxge_alloc_tx_cntl_dma_fail1: 3185 KMEM_FREE(tx_dmap, sizeof (nxge_dma_common_t)); 3186 3187 nxge_alloc_tx_cntl_dma_exit: 3188 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3189 "<== nxge_alloc_tx_cntl_dma status 0x%08x", status)); 3190 3191 return (status); 3192 } 3193 3194 /*ARGSUSED*/ 3195 static void 3196 nxge_free_tx_cntl_dma(p_nxge_t nxgep, p_nxge_dma_common_t dmap) 3197 { 3198 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "==> nxge_free_tx_cntl_dma")); 3199 3200 if (dmap == 0) 3201 return; 3202 3203 nxge_dma_mem_free(dmap); 3204 3205 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_free_tx_cntl_dma")); 3206 } 3207 3208 /* 3209 * nxge_free_tx_mem_pool 3210 * 3211 * This function frees all of the per-port TDC control data structures. 3212 * The per-channel (TDC) data structures are freed when the channel 3213 * is stopped. 3214 * 3215 * Arguments: 3216 * nxgep 3217 * 3218 * Notes: 3219 * 3220 * Context: 3221 * Any domain 3222 */ 3223 static void 3224 nxge_free_tx_mem_pool(p_nxge_t nxgep) 3225 { 3226 int tdc_max = NXGE_MAX_TDCS; 3227 3228 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "==> nxge_free_tx_mem_pool")); 3229 3230 if (!nxgep->tx_buf_pool_p || !nxgep->tx_buf_pool_p->buf_allocated) { 3231 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3232 "<== nxge_free_tx_mem_pool " 3233 "(null tx buf pool or buf not allocated")); 3234 return; 3235 } 3236 if (!nxgep->tx_cntl_pool_p || !nxgep->tx_cntl_pool_p->buf_allocated) { 3237 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, 3238 "<== nxge_free_tx_mem_pool " 3239 "(null tx cntl buf pool or cntl buf not allocated")); 3240 return; 3241 } 3242 3243 /* 1. Free the mailboxes. */ 3244 KMEM_FREE(nxgep->tx_mbox_areas_p->txmbox_areas_p, 3245 sizeof (p_tx_mbox_t) * tdc_max); 3246 KMEM_FREE(nxgep->tx_mbox_areas_p, sizeof (tx_mbox_areas_t)); 3247 3248 nxgep->tx_mbox_areas_p = 0; 3249 3250 /* 2. Free the transmit ring arrays. */ 3251 KMEM_FREE(nxgep->tx_rings->rings, 3252 sizeof (p_tx_ring_t) * tdc_max); 3253 KMEM_FREE(nxgep->tx_rings, sizeof (tx_rings_t)); 3254 3255 nxgep->tx_rings = 0; 3256 3257 /* 3. Free the completion ring data structures. */ 3258 KMEM_FREE(nxgep->tx_cntl_pool_p->dma_buf_pool_p, 3259 sizeof (p_nxge_dma_common_t) * tdc_max); 3260 KMEM_FREE(nxgep->tx_cntl_pool_p, sizeof (nxge_dma_pool_t)); 3261 3262 nxgep->tx_cntl_pool_p = 0; 3263 3264 /* 4. Free the data ring data structures. */ 3265 KMEM_FREE(nxgep->tx_buf_pool_p->num_chunks, 3266 sizeof (uint32_t) * tdc_max); 3267 KMEM_FREE(nxgep->tx_buf_pool_p->dma_buf_pool_p, 3268 sizeof (p_nxge_dma_common_t) * tdc_max); 3269 KMEM_FREE(nxgep->tx_buf_pool_p, sizeof (nxge_dma_pool_t)); 3270 3271 nxgep->tx_buf_pool_p = 0; 3272 3273 NXGE_DEBUG_MSG((nxgep, MEM2_CTL, "<== nxge_free_tx_mem_pool")); 3274 } 3275 3276 /*ARGSUSED*/ 3277 static nxge_status_t 3278 nxge_dma_mem_alloc(p_nxge_t nxgep, dma_method_t method, 3279 struct ddi_dma_attr *dma_attrp, 3280 size_t length, ddi_device_acc_attr_t *acc_attr_p, uint_t xfer_flags, 3281 p_nxge_dma_common_t dma_p) 3282 { 3283 caddr_t kaddrp; 3284 int ddi_status = DDI_SUCCESS; 3285 boolean_t contig_alloc_type; 3286 boolean_t kmem_alloc_type; 3287 3288 contig_alloc_type = dma_p->contig_alloc_type; 3289 3290 if (contig_alloc_type && (nxgep->niu_type != N2_NIU)) { 3291 /* 3292 * contig_alloc_type for contiguous memory only allowed 3293 * for N2/NIU. 3294 */ 3295 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3296 "nxge_dma_mem_alloc: alloc type not allowed (%d)", 3297 dma_p->contig_alloc_type)); 3298 return (NXGE_ERROR | NXGE_DDI_FAILED); 3299 } 3300 3301 dma_p->dma_handle = NULL; 3302 dma_p->acc_handle = NULL; 3303 dma_p->kaddrp = dma_p->last_kaddrp = NULL; 3304 dma_p->first_ioaddr_pp = dma_p->last_ioaddr_pp = NULL; 3305 ddi_status = ddi_dma_alloc_handle(nxgep->dip, dma_attrp, 3306 DDI_DMA_DONTWAIT, NULL, &dma_p->dma_handle); 3307 if (ddi_status != DDI_SUCCESS) { 3308 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3309 "nxge_dma_mem_alloc:ddi_dma_alloc_handle failed.")); 3310 return (NXGE_ERROR | NXGE_DDI_FAILED); 3311 } 3312 3313 kmem_alloc_type = dma_p->kmem_alloc_type; 3314 3315 switch (contig_alloc_type) { 3316 case B_FALSE: 3317 switch (kmem_alloc_type) { 3318 case B_FALSE: 3319 ddi_status = ddi_dma_mem_alloc(dma_p->dma_handle, 3320 length, 3321 acc_attr_p, 3322 xfer_flags, 3323 DDI_DMA_DONTWAIT, 0, &kaddrp, &dma_p->alength, 3324 &dma_p->acc_handle); 3325 if (ddi_status != DDI_SUCCESS) { 3326 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3327 "nxge_dma_mem_alloc: " 3328 "ddi_dma_mem_alloc failed")); 3329 ddi_dma_free_handle(&dma_p->dma_handle); 3330 dma_p->dma_handle = NULL; 3331 return (NXGE_ERROR | NXGE_DDI_FAILED); 3332 } 3333 if (dma_p->alength < length) { 3334 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3335 "nxge_dma_mem_alloc:di_dma_mem_alloc " 3336 "< length.")); 3337 ddi_dma_mem_free(&dma_p->acc_handle); 3338 ddi_dma_free_handle(&dma_p->dma_handle); 3339 dma_p->acc_handle = NULL; 3340 dma_p->dma_handle = NULL; 3341 return (NXGE_ERROR); 3342 } 3343 3344 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3345 NULL, 3346 kaddrp, dma_p->alength, xfer_flags, 3347 DDI_DMA_DONTWAIT, 3348 0, &dma_p->dma_cookie, &dma_p->ncookies); 3349 if (ddi_status != DDI_DMA_MAPPED) { 3350 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3351 "nxge_dma_mem_alloc: ddi_dma_addr_bind " 3352 "failed " 3353 "(staus 0x%x ncookies %d.)", ddi_status, 3354 dma_p->ncookies)); 3355 if (dma_p->acc_handle) { 3356 ddi_dma_mem_free(&dma_p->acc_handle); 3357 dma_p->acc_handle = NULL; 3358 } 3359 ddi_dma_free_handle(&dma_p->dma_handle); 3360 dma_p->dma_handle = NULL; 3361 return (NXGE_ERROR | NXGE_DDI_FAILED); 3362 } 3363 3364 if (dma_p->ncookies != 1) { 3365 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3366 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3367 "> 1 cookie" 3368 "(staus 0x%x ncookies %d.)", ddi_status, 3369 dma_p->ncookies)); 3370 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3371 if (dma_p->acc_handle) { 3372 ddi_dma_mem_free(&dma_p->acc_handle); 3373 dma_p->acc_handle = NULL; 3374 } 3375 ddi_dma_free_handle(&dma_p->dma_handle); 3376 dma_p->dma_handle = NULL; 3377 dma_p->acc_handle = NULL; 3378 return (NXGE_ERROR); 3379 } 3380 break; 3381 3382 case B_TRUE: 3383 kaddrp = KMEM_ALLOC(length, KM_NOSLEEP); 3384 if (kaddrp == NULL) { 3385 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3386 "nxge_dma_mem_alloc:ddi_dma_mem_alloc " 3387 "kmem alloc failed")); 3388 return (NXGE_ERROR); 3389 } 3390 3391 dma_p->alength = length; 3392 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, 3393 NULL, kaddrp, dma_p->alength, xfer_flags, 3394 DDI_DMA_DONTWAIT, 0, 3395 &dma_p->dma_cookie, &dma_p->ncookies); 3396 if (ddi_status != DDI_DMA_MAPPED) { 3397 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3398 "nxge_dma_mem_alloc:ddi_dma_addr_bind: " 3399 "(kmem_alloc) failed kaddrp $%p length %d " 3400 "(staus 0x%x (%d) ncookies %d.)", 3401 kaddrp, length, 3402 ddi_status, ddi_status, dma_p->ncookies)); 3403 KMEM_FREE(kaddrp, length); 3404 dma_p->acc_handle = NULL; 3405 ddi_dma_free_handle(&dma_p->dma_handle); 3406 dma_p->dma_handle = NULL; 3407 dma_p->kaddrp = NULL; 3408 return (NXGE_ERROR | NXGE_DDI_FAILED); 3409 } 3410 3411 if (dma_p->ncookies != 1) { 3412 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3413 "nxge_dma_mem_alloc:ddi_dma_addr_bind " 3414 "(kmem_alloc) > 1 cookie" 3415 "(staus 0x%x ncookies %d.)", ddi_status, 3416 dma_p->ncookies)); 3417 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3418 KMEM_FREE(kaddrp, length); 3419 ddi_dma_free_handle(&dma_p->dma_handle); 3420 dma_p->dma_handle = NULL; 3421 dma_p->acc_handle = NULL; 3422 dma_p->kaddrp = NULL; 3423 return (NXGE_ERROR); 3424 } 3425 3426 dma_p->kaddrp = kaddrp; 3427 3428 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 3429 "nxge_dma_mem_alloc: kmem_alloc dmap $%p " 3430 "kaddr $%p alength %d", 3431 dma_p, 3432 kaddrp, 3433 dma_p->alength)); 3434 break; 3435 } 3436 break; 3437 3438 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3439 case B_TRUE: 3440 kaddrp = (caddr_t)contig_mem_alloc(length); 3441 if (kaddrp == NULL) { 3442 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3443 "nxge_dma_mem_alloc:contig_mem_alloc failed.")); 3444 ddi_dma_free_handle(&dma_p->dma_handle); 3445 return (NXGE_ERROR | NXGE_DDI_FAILED); 3446 } 3447 3448 dma_p->alength = length; 3449 ddi_status = ddi_dma_addr_bind_handle(dma_p->dma_handle, NULL, 3450 kaddrp, dma_p->alength, xfer_flags, DDI_DMA_DONTWAIT, 0, 3451 &dma_p->dma_cookie, &dma_p->ncookies); 3452 if (ddi_status != DDI_DMA_MAPPED) { 3453 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3454 "nxge_dma_mem_alloc:di_dma_addr_bind failed " 3455 "(status 0x%x ncookies %d.)", ddi_status, 3456 dma_p->ncookies)); 3457 3458 NXGE_DEBUG_MSG((nxgep, DMA_CTL, 3459 "==> nxge_dma_mem_alloc: (not mapped)" 3460 "length %lu (0x%x) " 3461 "free contig kaddrp $%p " 3462 "va_to_pa $%p", 3463 length, length, 3464 kaddrp, 3465 va_to_pa(kaddrp))); 3466 3467 3468 contig_mem_free((void *)kaddrp, length); 3469 ddi_dma_free_handle(&dma_p->dma_handle); 3470 3471 dma_p->dma_handle = NULL; 3472 dma_p->acc_handle = NULL; 3473 dma_p->alength = NULL; 3474 dma_p->kaddrp = NULL; 3475 3476 return (NXGE_ERROR | NXGE_DDI_FAILED); 3477 } 3478 3479 if (dma_p->ncookies != 1 || 3480 (dma_p->dma_cookie.dmac_laddress == NULL)) { 3481 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3482 "nxge_dma_mem_alloc:di_dma_addr_bind > 1 " 3483 "cookie or " 3484 "dmac_laddress is NULL $%p size %d " 3485 " (status 0x%x ncookies %d.)", 3486 ddi_status, 3487 dma_p->dma_cookie.dmac_laddress, 3488 dma_p->dma_cookie.dmac_size, 3489 dma_p->ncookies)); 3490 3491 contig_mem_free((void *)kaddrp, length); 3492 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3493 ddi_dma_free_handle(&dma_p->dma_handle); 3494 3495 dma_p->alength = 0; 3496 dma_p->dma_handle = NULL; 3497 dma_p->acc_handle = NULL; 3498 dma_p->kaddrp = NULL; 3499 3500 return (NXGE_ERROR | NXGE_DDI_FAILED); 3501 } 3502 break; 3503 3504 #else 3505 case B_TRUE: 3506 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3507 "nxge_dma_mem_alloc: invalid alloc type for !sun4v")); 3508 return (NXGE_ERROR | NXGE_DDI_FAILED); 3509 #endif 3510 } 3511 3512 dma_p->kaddrp = kaddrp; 3513 dma_p->last_kaddrp = (unsigned char *)kaddrp + 3514 dma_p->alength - RXBUF_64B_ALIGNED; 3515 #if defined(__i386) 3516 dma_p->ioaddr_pp = 3517 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress; 3518 #else 3519 dma_p->ioaddr_pp = (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3520 #endif 3521 dma_p->last_ioaddr_pp = 3522 #if defined(__i386) 3523 (unsigned char *)(uint32_t)dma_p->dma_cookie.dmac_laddress + 3524 #else 3525 (unsigned char *)dma_p->dma_cookie.dmac_laddress + 3526 #endif 3527 dma_p->alength - RXBUF_64B_ALIGNED; 3528 3529 NPI_DMA_ACC_HANDLE_SET(dma_p, dma_p->acc_handle); 3530 3531 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3532 dma_p->orig_ioaddr_pp = 3533 (unsigned char *)dma_p->dma_cookie.dmac_laddress; 3534 dma_p->orig_alength = length; 3535 dma_p->orig_kaddrp = kaddrp; 3536 dma_p->orig_vatopa = (uint64_t)va_to_pa(kaddrp); 3537 #endif 3538 3539 NXGE_DEBUG_MSG((nxgep, DMA_CTL, "<== nxge_dma_mem_alloc: " 3540 "dma buffer allocated: dma_p $%p " 3541 "return dmac_ladress from cookie $%p cookie dmac_size %d " 3542 "dma_p->ioaddr_p $%p " 3543 "dma_p->orig_ioaddr_p $%p " 3544 "orig_vatopa $%p " 3545 "alength %d (0x%x) " 3546 "kaddrp $%p " 3547 "length %d (0x%x)", 3548 dma_p, 3549 dma_p->dma_cookie.dmac_laddress, dma_p->dma_cookie.dmac_size, 3550 dma_p->ioaddr_pp, 3551 dma_p->orig_ioaddr_pp, 3552 dma_p->orig_vatopa, 3553 dma_p->alength, dma_p->alength, 3554 kaddrp, 3555 length, length)); 3556 3557 return (NXGE_OK); 3558 } 3559 3560 static void 3561 nxge_dma_mem_free(p_nxge_dma_common_t dma_p) 3562 { 3563 if (dma_p->dma_handle != NULL) { 3564 if (dma_p->ncookies) { 3565 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3566 dma_p->ncookies = 0; 3567 } 3568 ddi_dma_free_handle(&dma_p->dma_handle); 3569 dma_p->dma_handle = NULL; 3570 } 3571 3572 if (dma_p->acc_handle != NULL) { 3573 ddi_dma_mem_free(&dma_p->acc_handle); 3574 dma_p->acc_handle = NULL; 3575 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3576 } 3577 3578 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3579 if (dma_p->contig_alloc_type && 3580 dma_p->orig_kaddrp && dma_p->orig_alength) { 3581 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_mem_free: " 3582 "kaddrp $%p (orig_kaddrp $%p)" 3583 "mem type %d ", 3584 "orig_alength %d " 3585 "alength 0x%x (%d)", 3586 dma_p->kaddrp, 3587 dma_p->orig_kaddrp, 3588 dma_p->contig_alloc_type, 3589 dma_p->orig_alength, 3590 dma_p->alength, dma_p->alength)); 3591 3592 contig_mem_free(dma_p->orig_kaddrp, dma_p->orig_alength); 3593 dma_p->orig_alength = NULL; 3594 dma_p->orig_kaddrp = NULL; 3595 dma_p->contig_alloc_type = B_FALSE; 3596 } 3597 #endif 3598 dma_p->kaddrp = NULL; 3599 dma_p->alength = NULL; 3600 } 3601 3602 static void 3603 nxge_dma_free_rx_data_buf(p_nxge_dma_common_t dma_p) 3604 { 3605 uint64_t kaddr; 3606 uint32_t buf_size; 3607 3608 NXGE_DEBUG_MSG((NULL, DMA_CTL, "==> nxge_dma_free_rx_data_buf")); 3609 3610 if (dma_p->dma_handle != NULL) { 3611 if (dma_p->ncookies) { 3612 (void) ddi_dma_unbind_handle(dma_p->dma_handle); 3613 dma_p->ncookies = 0; 3614 } 3615 ddi_dma_free_handle(&dma_p->dma_handle); 3616 dma_p->dma_handle = NULL; 3617 } 3618 3619 if (dma_p->acc_handle != NULL) { 3620 ddi_dma_mem_free(&dma_p->acc_handle); 3621 dma_p->acc_handle = NULL; 3622 NPI_DMA_ACC_HANDLE_SET(dma_p, NULL); 3623 } 3624 3625 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3626 "==> nxge_dma_free_rx_data_buf: dmap $%p buf_alloc_state %d", 3627 dma_p, 3628 dma_p->buf_alloc_state)); 3629 3630 if (!(dma_p->buf_alloc_state & BUF_ALLOCATED_WAIT_FREE)) { 3631 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3632 "<== nxge_dma_free_rx_data_buf: " 3633 "outstanding data buffers")); 3634 return; 3635 } 3636 3637 #if defined(sun4v) && defined(NIU_LP_WORKAROUND) 3638 if (dma_p->contig_alloc_type && 3639 dma_p->orig_kaddrp && dma_p->orig_alength) { 3640 NXGE_DEBUG_MSG((NULL, DMA_CTL, "nxge_dma_free_rx_data_buf: " 3641 "kaddrp $%p (orig_kaddrp $%p)" 3642 "mem type %d ", 3643 "orig_alength %d " 3644 "alength 0x%x (%d)", 3645 dma_p->kaddrp, 3646 dma_p->orig_kaddrp, 3647 dma_p->contig_alloc_type, 3648 dma_p->orig_alength, 3649 dma_p->alength, dma_p->alength)); 3650 3651 kaddr = (uint64_t)dma_p->orig_kaddrp; 3652 buf_size = dma_p->orig_alength; 3653 nxge_free_buf(CONTIG_MEM_ALLOC, kaddr, buf_size); 3654 dma_p->orig_alength = NULL; 3655 dma_p->orig_kaddrp = NULL; 3656 dma_p->contig_alloc_type = B_FALSE; 3657 dma_p->kaddrp = NULL; 3658 dma_p->alength = NULL; 3659 return; 3660 } 3661 #endif 3662 3663 if (dma_p->kmem_alloc_type) { 3664 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3665 "nxge_dma_free_rx_data_buf: free kmem " 3666 "kaddrp $%p (orig_kaddrp $%p)" 3667 "alloc type %d " 3668 "orig_alength %d " 3669 "alength 0x%x (%d)", 3670 dma_p->kaddrp, 3671 dma_p->orig_kaddrp, 3672 dma_p->kmem_alloc_type, 3673 dma_p->orig_alength, 3674 dma_p->alength, dma_p->alength)); 3675 #if defined(__i386) 3676 kaddr = (uint64_t)(uint32_t)dma_p->kaddrp; 3677 #else 3678 kaddr = (uint64_t)dma_p->kaddrp; 3679 #endif 3680 buf_size = dma_p->orig_alength; 3681 NXGE_DEBUG_MSG((NULL, DMA_CTL, 3682 "nxge_dma_free_rx_data_buf: free dmap $%p " 3683 "kaddr $%p buf_size %d", 3684 dma_p, 3685 kaddr, buf_size)); 3686 nxge_free_buf(KMEM_ALLOC, kaddr, buf_size); 3687 dma_p->alength = 0; 3688 dma_p->orig_alength = 0; 3689 dma_p->kaddrp = NULL; 3690 dma_p->kmem_alloc_type = B_FALSE; 3691 } 3692 3693 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_dma_free_rx_data_buf")); 3694 } 3695 3696 /* 3697 * nxge_m_start() -- start transmitting and receiving. 3698 * 3699 * This function is called by the MAC layer when the first 3700 * stream is open to prepare the hardware ready for sending 3701 * and transmitting packets. 3702 */ 3703 static int 3704 nxge_m_start(void *arg) 3705 { 3706 p_nxge_t nxgep = (p_nxge_t)arg; 3707 3708 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_start")); 3709 3710 if (nxge_peu_reset_enable && !nxgep->nxge_link_poll_timerid) { 3711 (void) nxge_link_monitor(nxgep, LINK_MONITOR_START); 3712 } 3713 3714 MUTEX_ENTER(nxgep->genlock); 3715 if (nxge_init(nxgep) != NXGE_OK) { 3716 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3717 "<== nxge_m_start: initialization failed")); 3718 MUTEX_EXIT(nxgep->genlock); 3719 return (EIO); 3720 } 3721 3722 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) 3723 goto nxge_m_start_exit; 3724 /* 3725 * Start timer to check the system error and tx hangs 3726 */ 3727 if (!isLDOMguest(nxgep)) 3728 nxgep->nxge_timerid = nxge_start_timer(nxgep, 3729 nxge_check_hw_state, NXGE_CHECK_TIMER); 3730 #if defined(sun4v) 3731 else 3732 nxge_hio_start_timer(nxgep); 3733 #endif 3734 3735 nxgep->link_notify = B_TRUE; 3736 3737 nxgep->nxge_mac_state = NXGE_MAC_STARTED; 3738 3739 nxge_m_start_exit: 3740 MUTEX_EXIT(nxgep->genlock); 3741 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_start")); 3742 return (0); 3743 } 3744 3745 /* 3746 * nxge_m_stop(): stop transmitting and receiving. 3747 */ 3748 static void 3749 nxge_m_stop(void *arg) 3750 { 3751 p_nxge_t nxgep = (p_nxge_t)arg; 3752 3753 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_stop")); 3754 3755 MUTEX_ENTER(nxgep->genlock); 3756 nxgep->nxge_mac_state = NXGE_MAC_STOPPING; 3757 3758 if (nxgep->nxge_timerid) { 3759 nxge_stop_timer(nxgep, nxgep->nxge_timerid); 3760 nxgep->nxge_timerid = 0; 3761 } 3762 3763 nxge_uninit(nxgep); 3764 3765 nxgep->nxge_mac_state = NXGE_MAC_STOPPED; 3766 3767 MUTEX_EXIT(nxgep->genlock); 3768 3769 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_stop")); 3770 } 3771 3772 static int 3773 nxge_m_unicst(void *arg, const uint8_t *macaddr) 3774 { 3775 p_nxge_t nxgep = (p_nxge_t)arg; 3776 struct ether_addr addrp; 3777 3778 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "==> nxge_m_unicst")); 3779 3780 bcopy(macaddr, (uint8_t *)&addrp, ETHERADDRL); 3781 if (nxge_set_mac_addr(nxgep, &addrp)) { 3782 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3783 "<== nxge_m_unicst: set unitcast failed")); 3784 return (EINVAL); 3785 } 3786 3787 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_unicst")); 3788 3789 return (0); 3790 } 3791 3792 static int 3793 nxge_m_multicst(void *arg, boolean_t add, const uint8_t *mca) 3794 { 3795 p_nxge_t nxgep = (p_nxge_t)arg; 3796 struct ether_addr addrp; 3797 3798 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3799 "==> nxge_m_multicst: add %d", add)); 3800 3801 bcopy(mca, (uint8_t *)&addrp, ETHERADDRL); 3802 if (add) { 3803 if (nxge_add_mcast_addr(nxgep, &addrp)) { 3804 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3805 "<== nxge_m_multicst: add multicast failed")); 3806 return (EINVAL); 3807 } 3808 } else { 3809 if (nxge_del_mcast_addr(nxgep, &addrp)) { 3810 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3811 "<== nxge_m_multicst: del multicast failed")); 3812 return (EINVAL); 3813 } 3814 } 3815 3816 NXGE_DEBUG_MSG((nxgep, MAC_CTL, "<== nxge_m_multicst")); 3817 3818 return (0); 3819 } 3820 3821 static int 3822 nxge_m_promisc(void *arg, boolean_t on) 3823 { 3824 p_nxge_t nxgep = (p_nxge_t)arg; 3825 3826 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3827 "==> nxge_m_promisc: on %d", on)); 3828 3829 if (nxge_set_promisc(nxgep, on)) { 3830 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3831 "<== nxge_m_promisc: set promisc failed")); 3832 return (EINVAL); 3833 } 3834 3835 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 3836 "<== nxge_m_promisc: on %d", on)); 3837 3838 return (0); 3839 } 3840 3841 static void 3842 nxge_m_ioctl(void *arg, queue_t *wq, mblk_t *mp) 3843 { 3844 p_nxge_t nxgep = (p_nxge_t)arg; 3845 struct iocblk *iocp; 3846 boolean_t need_privilege; 3847 int err; 3848 int cmd; 3849 3850 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl")); 3851 3852 iocp = (struct iocblk *)mp->b_rptr; 3853 iocp->ioc_error = 0; 3854 need_privilege = B_TRUE; 3855 cmd = iocp->ioc_cmd; 3856 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_ioctl: cmd 0x%08x", cmd)); 3857 switch (cmd) { 3858 default: 3859 miocnak(wq, mp, 0, EINVAL); 3860 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl: invalid")); 3861 return; 3862 3863 case LB_GET_INFO_SIZE: 3864 case LB_GET_INFO: 3865 case LB_GET_MODE: 3866 need_privilege = B_FALSE; 3867 break; 3868 case LB_SET_MODE: 3869 break; 3870 3871 3872 case NXGE_GET_MII: 3873 case NXGE_PUT_MII: 3874 case NXGE_GET64: 3875 case NXGE_PUT64: 3876 case NXGE_GET_TX_RING_SZ: 3877 case NXGE_GET_TX_DESC: 3878 case NXGE_TX_SIDE_RESET: 3879 case NXGE_RX_SIDE_RESET: 3880 case NXGE_GLOBAL_RESET: 3881 case NXGE_RESET_MAC: 3882 case NXGE_TX_REGS_DUMP: 3883 case NXGE_RX_REGS_DUMP: 3884 case NXGE_INT_REGS_DUMP: 3885 case NXGE_VIR_INT_REGS_DUMP: 3886 case NXGE_PUT_TCAM: 3887 case NXGE_GET_TCAM: 3888 case NXGE_RTRACE: 3889 case NXGE_RDUMP: 3890 3891 need_privilege = B_FALSE; 3892 break; 3893 case NXGE_INJECT_ERR: 3894 cmn_err(CE_NOTE, "!nxge_m_ioctl: Inject error\n"); 3895 nxge_err_inject(nxgep, wq, mp); 3896 break; 3897 } 3898 3899 if (need_privilege) { 3900 err = secpolicy_net_config(iocp->ioc_cr, B_FALSE); 3901 if (err != 0) { 3902 miocnak(wq, mp, 0, err); 3903 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 3904 "<== nxge_m_ioctl: no priv")); 3905 return; 3906 } 3907 } 3908 3909 switch (cmd) { 3910 3911 case LB_GET_MODE: 3912 case LB_SET_MODE: 3913 case LB_GET_INFO_SIZE: 3914 case LB_GET_INFO: 3915 nxge_loopback_ioctl(nxgep, wq, mp, iocp); 3916 break; 3917 3918 case NXGE_GET_MII: 3919 case NXGE_PUT_MII: 3920 case NXGE_PUT_TCAM: 3921 case NXGE_GET_TCAM: 3922 case NXGE_GET64: 3923 case NXGE_PUT64: 3924 case NXGE_GET_TX_RING_SZ: 3925 case NXGE_GET_TX_DESC: 3926 case NXGE_TX_SIDE_RESET: 3927 case NXGE_RX_SIDE_RESET: 3928 case NXGE_GLOBAL_RESET: 3929 case NXGE_RESET_MAC: 3930 case NXGE_TX_REGS_DUMP: 3931 case NXGE_RX_REGS_DUMP: 3932 case NXGE_INT_REGS_DUMP: 3933 case NXGE_VIR_INT_REGS_DUMP: 3934 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 3935 "==> nxge_m_ioctl: cmd 0x%x", cmd)); 3936 nxge_hw_ioctl(nxgep, wq, mp, iocp); 3937 break; 3938 } 3939 3940 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_ioctl")); 3941 } 3942 3943 extern void nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count); 3944 3945 static void 3946 nxge_m_resources(void *arg) 3947 { 3948 p_nxge_t nxgep = arg; 3949 mac_rx_fifo_t mrf; 3950 3951 nxge_grp_set_t *set = &nxgep->rx_set; 3952 uint8_t rdc; 3953 3954 rx_rcr_ring_t *ring; 3955 3956 NXGE_DEBUG_MSG((nxgep, RX_CTL, "==> nxge_m_resources")); 3957 3958 MUTEX_ENTER(nxgep->genlock); 3959 3960 if (set->owned.map == 0) { 3961 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 3962 "nxge_m_resources: no receive resources")); 3963 goto nxge_m_resources_exit; 3964 } 3965 3966 /* 3967 * CR 6492541 Check to see if the drv_state has been initialized, 3968 * if not * call nxge_init(). 3969 */ 3970 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 3971 if (nxge_init(nxgep) != NXGE_OK) 3972 goto nxge_m_resources_exit; 3973 } 3974 3975 mrf.mrf_type = MAC_RX_FIFO; 3976 mrf.mrf_blank = nxge_rx_hw_blank; 3977 mrf.mrf_arg = (void *)nxgep; 3978 3979 mrf.mrf_normal_blank_time = 128; 3980 mrf.mrf_normal_pkt_count = 8; 3981 3982 /* 3983 * Export our receive resources to the MAC layer. 3984 */ 3985 for (rdc = 0; rdc < NXGE_MAX_RDCS; rdc++) { 3986 if ((1 << rdc) & set->owned.map) { 3987 ring = nxgep->rx_rcr_rings->rcr_rings[rdc]; 3988 if (ring == 0) { 3989 /* 3990 * This is a big deal only if we are 3991 * *not* in an LDOMs environment. 3992 */ 3993 if (nxgep->environs == SOLARIS_DOMAIN) { 3994 cmn_err(CE_NOTE, 3995 "==> nxge_m_resources: " 3996 "ring %d == 0", rdc); 3997 } 3998 continue; 3999 } 4000 ring->rcr_mac_handle = mac_resource_add 4001 (nxgep->mach, (mac_resource_t *)&mrf); 4002 4003 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4004 "==> nxge_m_resources: RDC %d RCR %p MAC handle %p", 4005 rdc, ring, ring->rcr_mac_handle)); 4006 } 4007 } 4008 4009 nxge_m_resources_exit: 4010 MUTEX_EXIT(nxgep->genlock); 4011 NXGE_DEBUG_MSG((nxgep, RX_CTL, "<== nxge_m_resources")); 4012 } 4013 4014 void 4015 nxge_mmac_kstat_update(p_nxge_t nxgep, mac_addr_slot_t slot, boolean_t factory) 4016 { 4017 p_nxge_mmac_stats_t mmac_stats; 4018 int i; 4019 nxge_mmac_t *mmac_info; 4020 4021 mmac_info = &nxgep->nxge_mmac_info; 4022 4023 mmac_stats = &nxgep->statsp->mmac_stats; 4024 mmac_stats->mmac_max_cnt = mmac_info->num_mmac; 4025 mmac_stats->mmac_avail_cnt = mmac_info->naddrfree; 4026 4027 for (i = 0; i < ETHERADDRL; i++) { 4028 if (factory) { 4029 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4030 = mmac_info->factory_mac_pool[slot][ 4031 (ETHERADDRL-1) - i]; 4032 } else { 4033 mmac_stats->mmac_avail_pool[slot-1].ether_addr_octet[i] 4034 = mmac_info->mac_pool[slot].addr[ 4035 (ETHERADDRL - 1) - i]; 4036 } 4037 } 4038 } 4039 4040 /* 4041 * nxge_altmac_set() -- Set an alternate MAC address 4042 */ 4043 int 4044 nxge_altmac_set(p_nxge_t nxgep, uint8_t *maddr, mac_addr_slot_t slot, 4045 uint8_t rdctbl) 4046 { 4047 uint8_t addrn; 4048 uint8_t portn; 4049 npi_mac_addr_t altmac; 4050 hostinfo_t mac_rdc; 4051 p_nxge_class_pt_cfg_t clscfgp; 4052 4053 altmac.w2 = ((uint16_t)maddr[0] << 8) | ((uint16_t)maddr[1] & 0x0ff); 4054 altmac.w1 = ((uint16_t)maddr[2] << 8) | ((uint16_t)maddr[3] & 0x0ff); 4055 altmac.w0 = ((uint16_t)maddr[4] << 8) | ((uint16_t)maddr[5] & 0x0ff); 4056 4057 portn = nxgep->mac.portnum; 4058 addrn = (uint8_t)slot - 1; 4059 4060 if (npi_mac_altaddr_entry(nxgep->npi_handle, OP_SET, portn, 4061 addrn, &altmac) != NPI_SUCCESS) 4062 return (EIO); 4063 4064 /* 4065 * Set the rdc table number for the host info entry 4066 * for this mac address slot. 4067 */ 4068 clscfgp = (p_nxge_class_pt_cfg_t)&nxgep->class_config; 4069 mac_rdc.value = 0; 4070 clscfgp->mac_host_info[addrn].rdctbl = rdctbl; 4071 mac_rdc.bits.w0.rdc_tbl_num = rdctbl; 4072 mac_rdc.bits.w0.mac_pref = clscfgp->mac_host_info[addrn].mpr_npr; 4073 4074 if (npi_mac_hostinfo_entry(nxgep->npi_handle, OP_SET, 4075 nxgep->function_num, addrn, &mac_rdc) != NPI_SUCCESS) { 4076 return (EIO); 4077 } 4078 4079 /* 4080 * Enable comparison with the alternate MAC address. 4081 * While the first alternate addr is enabled by bit 1 of register 4082 * BMAC_ALTAD_CMPEN, it is enabled by bit 0 of register 4083 * XMAC_ADDR_CMPEN, so slot needs to be converted to addrn 4084 * accordingly before calling npi_mac_altaddr_entry. 4085 */ 4086 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4087 addrn = (uint8_t)slot - 1; 4088 else 4089 addrn = (uint8_t)slot; 4090 4091 if (npi_mac_altaddr_enable(nxgep->npi_handle, portn, addrn) 4092 != NPI_SUCCESS) 4093 return (EIO); 4094 return (0); 4095 } 4096 4097 /* 4098 * nxeg_m_mmac_add() - find an unused address slot, set the address 4099 * value to the one specified, enable the port to start filtering on 4100 * the new MAC address. Returns 0 on success. 4101 */ 4102 int 4103 nxge_m_mmac_add(void *arg, mac_multi_addr_t *maddr) 4104 { 4105 p_nxge_t nxgep = arg; 4106 mac_addr_slot_t slot; 4107 nxge_mmac_t *mmac_info; 4108 int err; 4109 nxge_status_t status; 4110 4111 mutex_enter(nxgep->genlock); 4112 4113 /* 4114 * Make sure that nxge is initialized, if _start() has 4115 * not been called. 4116 */ 4117 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4118 status = nxge_init(nxgep); 4119 if (status != NXGE_OK) { 4120 mutex_exit(nxgep->genlock); 4121 return (ENXIO); 4122 } 4123 } 4124 4125 mmac_info = &nxgep->nxge_mmac_info; 4126 if (mmac_info->naddrfree == 0) { 4127 mutex_exit(nxgep->genlock); 4128 return (ENOSPC); 4129 } 4130 if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 4131 maddr->mma_addrlen)) { 4132 mutex_exit(nxgep->genlock); 4133 return (EINVAL); 4134 } 4135 /* 4136 * Search for the first available slot. Because naddrfree 4137 * is not zero, we are guaranteed to find one. 4138 * Slot 0 is for unique (primary) MAC. The first alternate 4139 * MAC slot is slot 1. 4140 * Each of the first two ports of Neptune has 16 alternate 4141 * MAC slots but only the first 7 (of 15) slots have assigned factory 4142 * MAC addresses. We first search among the slots without bundled 4143 * factory MACs. If we fail to find one in that range, then we 4144 * search the slots with bundled factory MACs. A factory MAC 4145 * will be wasted while the slot is used with a user MAC address. 4146 * But the slot could be used by factory MAC again after calling 4147 * nxge_m_mmac_remove and nxge_m_mmac_reserve. 4148 */ 4149 if (mmac_info->num_factory_mmac < mmac_info->num_mmac) { 4150 for (slot = mmac_info->num_factory_mmac + 1; 4151 slot <= mmac_info->num_mmac; slot++) { 4152 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4153 break; 4154 } 4155 if (slot > mmac_info->num_mmac) { 4156 for (slot = 1; slot <= mmac_info->num_factory_mmac; 4157 slot++) { 4158 if (!(mmac_info->mac_pool[slot].flags 4159 & MMAC_SLOT_USED)) 4160 break; 4161 } 4162 } 4163 } else { 4164 for (slot = 1; slot <= mmac_info->num_mmac; slot++) { 4165 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4166 break; 4167 } 4168 } 4169 ASSERT(slot <= mmac_info->num_mmac); 4170 4171 /* 4172 * def_mac_rxdma_grpid is the default rdc table for the port. 4173 */ 4174 if ((err = nxge_altmac_set(nxgep, maddr->mma_addr, slot, 4175 nxgep->pt_config.hw_config.def_mac_rxdma_grpid)) != 0) { 4176 mutex_exit(nxgep->genlock); 4177 return (err); 4178 } 4179 4180 bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, ETHERADDRL); 4181 mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED; 4182 mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 4183 mmac_info->naddrfree--; 4184 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4185 4186 maddr->mma_slot = slot; 4187 4188 mutex_exit(nxgep->genlock); 4189 return (0); 4190 } 4191 4192 /* 4193 * This function reserves an unused slot and programs the slot and the HW 4194 * with a factory mac address. 4195 */ 4196 static int 4197 nxge_m_mmac_reserve(void *arg, mac_multi_addr_t *maddr) 4198 { 4199 p_nxge_t nxgep = arg; 4200 mac_addr_slot_t slot; 4201 nxge_mmac_t *mmac_info; 4202 int err; 4203 nxge_status_t status; 4204 4205 mutex_enter(nxgep->genlock); 4206 4207 /* 4208 * Make sure that nxge is initialized, if _start() has 4209 * not been called. 4210 */ 4211 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4212 status = nxge_init(nxgep); 4213 if (status != NXGE_OK) { 4214 mutex_exit(nxgep->genlock); 4215 return (ENXIO); 4216 } 4217 } 4218 4219 mmac_info = &nxgep->nxge_mmac_info; 4220 if (mmac_info->naddrfree == 0) { 4221 mutex_exit(nxgep->genlock); 4222 return (ENOSPC); 4223 } 4224 4225 slot = maddr->mma_slot; 4226 if (slot == -1) { /* -1: Take the first available slot */ 4227 for (slot = 1; slot <= mmac_info->num_factory_mmac; slot++) { 4228 if (!(mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED)) 4229 break; 4230 } 4231 if (slot > mmac_info->num_factory_mmac) { 4232 mutex_exit(nxgep->genlock); 4233 return (ENOSPC); 4234 } 4235 } 4236 if (slot < 1 || slot > mmac_info->num_factory_mmac) { 4237 /* 4238 * Do not support factory MAC at a slot greater than 4239 * num_factory_mmac even when there are available factory 4240 * MAC addresses because the alternate MACs are bundled with 4241 * slot[1] through slot[num_factory_mmac] 4242 */ 4243 mutex_exit(nxgep->genlock); 4244 return (EINVAL); 4245 } 4246 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4247 mutex_exit(nxgep->genlock); 4248 return (EBUSY); 4249 } 4250 /* Verify the address to be reserved */ 4251 if (!mac_unicst_verify(nxgep->mach, 4252 mmac_info->factory_mac_pool[slot], ETHERADDRL)) { 4253 mutex_exit(nxgep->genlock); 4254 return (EINVAL); 4255 } 4256 if (err = nxge_altmac_set(nxgep, 4257 mmac_info->factory_mac_pool[slot], slot, 4258 nxgep->pt_config.hw_config.def_mac_rxdma_grpid)) { 4259 mutex_exit(nxgep->genlock); 4260 return (err); 4261 } 4262 bcopy(mmac_info->factory_mac_pool[slot], maddr->mma_addr, ETHERADDRL); 4263 mmac_info->mac_pool[slot].flags |= MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 4264 mmac_info->naddrfree--; 4265 4266 nxge_mmac_kstat_update(nxgep, slot, B_TRUE); 4267 mutex_exit(nxgep->genlock); 4268 4269 /* Pass info back to the caller */ 4270 maddr->mma_slot = slot; 4271 maddr->mma_addrlen = ETHERADDRL; 4272 maddr->mma_flags = MMAC_SLOT_USED | MMAC_VENDOR_ADDR; 4273 4274 return (0); 4275 } 4276 4277 /* 4278 * Remove the specified mac address and update the HW not to filter 4279 * the mac address anymore. 4280 */ 4281 int 4282 nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot) 4283 { 4284 p_nxge_t nxgep = arg; 4285 nxge_mmac_t *mmac_info; 4286 uint8_t addrn; 4287 uint8_t portn; 4288 int err = 0; 4289 nxge_status_t status; 4290 4291 mutex_enter(nxgep->genlock); 4292 4293 /* 4294 * Make sure that nxge is initialized, if _start() has 4295 * not been called. 4296 */ 4297 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4298 status = nxge_init(nxgep); 4299 if (status != NXGE_OK) { 4300 mutex_exit(nxgep->genlock); 4301 return (ENXIO); 4302 } 4303 } 4304 4305 mmac_info = &nxgep->nxge_mmac_info; 4306 if (slot < 1 || slot > mmac_info->num_mmac) { 4307 mutex_exit(nxgep->genlock); 4308 return (EINVAL); 4309 } 4310 4311 portn = nxgep->mac.portnum; 4312 if (portn == XMAC_PORT_0 || portn == XMAC_PORT_1) 4313 addrn = (uint8_t)slot - 1; 4314 else 4315 addrn = (uint8_t)slot; 4316 4317 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4318 if (npi_mac_altaddr_disable(nxgep->npi_handle, portn, addrn) 4319 == NPI_SUCCESS) { 4320 mmac_info->naddrfree++; 4321 mmac_info->mac_pool[slot].flags &= ~MMAC_SLOT_USED; 4322 /* 4323 * Regardless if the MAC we just stopped filtering 4324 * is a user addr or a facory addr, we must set 4325 * the MMAC_VENDOR_ADDR flag if this slot has an 4326 * associated factory MAC to indicate that a factory 4327 * MAC is available. 4328 */ 4329 if (slot <= mmac_info->num_factory_mmac) { 4330 mmac_info->mac_pool[slot].flags 4331 |= MMAC_VENDOR_ADDR; 4332 } 4333 /* 4334 * Clear mac_pool[slot].addr so that kstat shows 0 4335 * alternate MAC address if the slot is not used. 4336 * (But nxge_m_mmac_get returns the factory MAC even 4337 * when the slot is not used!) 4338 */ 4339 bzero(mmac_info->mac_pool[slot].addr, ETHERADDRL); 4340 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4341 } else { 4342 err = EIO; 4343 } 4344 } else { 4345 err = EINVAL; 4346 } 4347 4348 mutex_exit(nxgep->genlock); 4349 return (err); 4350 } 4351 4352 /* 4353 * Modify a mac address added by nxge_m_mmac_add or nxge_m_mmac_reserve(). 4354 */ 4355 static int 4356 nxge_m_mmac_modify(void *arg, mac_multi_addr_t *maddr) 4357 { 4358 p_nxge_t nxgep = arg; 4359 mac_addr_slot_t slot; 4360 nxge_mmac_t *mmac_info; 4361 int err = 0; 4362 nxge_status_t status; 4363 4364 if (!mac_unicst_verify(nxgep->mach, maddr->mma_addr, 4365 maddr->mma_addrlen)) 4366 return (EINVAL); 4367 4368 slot = maddr->mma_slot; 4369 4370 mutex_enter(nxgep->genlock); 4371 4372 /* 4373 * Make sure that nxge is initialized, if _start() has 4374 * not been called. 4375 */ 4376 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4377 status = nxge_init(nxgep); 4378 if (status != NXGE_OK) { 4379 mutex_exit(nxgep->genlock); 4380 return (ENXIO); 4381 } 4382 } 4383 4384 mmac_info = &nxgep->nxge_mmac_info; 4385 if (slot < 1 || slot > mmac_info->num_mmac) { 4386 mutex_exit(nxgep->genlock); 4387 return (EINVAL); 4388 } 4389 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) { 4390 if ((err = nxge_altmac_set(nxgep, 4391 maddr->mma_addr, slot, 4392 nxgep->pt_config.hw_config.def_mac_rxdma_grpid)) != 0) { 4393 bcopy(maddr->mma_addr, mmac_info->mac_pool[slot].addr, 4394 ETHERADDRL); 4395 /* 4396 * Assume that the MAC passed down from the caller 4397 * is not a factory MAC address (The user should 4398 * call mmac_remove followed by mmac_reserve if 4399 * he wants to use the factory MAC for this slot). 4400 */ 4401 mmac_info->mac_pool[slot].flags &= ~MMAC_VENDOR_ADDR; 4402 nxge_mmac_kstat_update(nxgep, slot, B_FALSE); 4403 } 4404 } else { 4405 err = EINVAL; 4406 } 4407 mutex_exit(nxgep->genlock); 4408 return (err); 4409 } 4410 4411 /* 4412 * nxge_m_mmac_get() - Get the MAC address and other information 4413 * related to the slot. mma_flags should be set to 0 in the call. 4414 * Note: although kstat shows MAC address as zero when a slot is 4415 * not used, Crossbow expects nxge_m_mmac_get to copy factory MAC 4416 * to the caller as long as the slot is not using a user MAC address. 4417 * The following table shows the rules, 4418 * 4419 * USED VENDOR mma_addr 4420 * ------------------------------------------------------------ 4421 * (1) Slot uses a user MAC: yes no user MAC 4422 * (2) Slot uses a factory MAC: yes yes factory MAC 4423 * (3) Slot is not used but is 4424 * factory MAC capable: no yes factory MAC 4425 * (4) Slot is not used and is 4426 * not factory MAC capable: no no 0 4427 * ------------------------------------------------------------ 4428 */ 4429 static int 4430 nxge_m_mmac_get(void *arg, mac_multi_addr_t *maddr) 4431 { 4432 nxge_t *nxgep = arg; 4433 mac_addr_slot_t slot; 4434 nxge_mmac_t *mmac_info; 4435 nxge_status_t status; 4436 4437 slot = maddr->mma_slot; 4438 4439 mutex_enter(nxgep->genlock); 4440 4441 /* 4442 * Make sure that nxge is initialized, if _start() has 4443 * not been called. 4444 */ 4445 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 4446 status = nxge_init(nxgep); 4447 if (status != NXGE_OK) { 4448 mutex_exit(nxgep->genlock); 4449 return (ENXIO); 4450 } 4451 } 4452 4453 mmac_info = &nxgep->nxge_mmac_info; 4454 4455 if (slot < 1 || slot > mmac_info->num_mmac) { 4456 mutex_exit(nxgep->genlock); 4457 return (EINVAL); 4458 } 4459 maddr->mma_flags = 0; 4460 if (mmac_info->mac_pool[slot].flags & MMAC_SLOT_USED) 4461 maddr->mma_flags |= MMAC_SLOT_USED; 4462 4463 if (mmac_info->mac_pool[slot].flags & MMAC_VENDOR_ADDR) { 4464 maddr->mma_flags |= MMAC_VENDOR_ADDR; 4465 bcopy(mmac_info->factory_mac_pool[slot], 4466 maddr->mma_addr, ETHERADDRL); 4467 maddr->mma_addrlen = ETHERADDRL; 4468 } else { 4469 if (maddr->mma_flags & MMAC_SLOT_USED) { 4470 bcopy(mmac_info->mac_pool[slot].addr, 4471 maddr->mma_addr, ETHERADDRL); 4472 maddr->mma_addrlen = ETHERADDRL; 4473 } else { 4474 bzero(maddr->mma_addr, ETHERADDRL); 4475 maddr->mma_addrlen = 0; 4476 } 4477 } 4478 mutex_exit(nxgep->genlock); 4479 return (0); 4480 } 4481 4482 static boolean_t 4483 nxge_m_getcapab(void *arg, mac_capab_t cap, void *cap_data) 4484 { 4485 nxge_t *nxgep = arg; 4486 uint32_t *txflags = cap_data; 4487 multiaddress_capab_t *mmacp = cap_data; 4488 4489 switch (cap) { 4490 case MAC_CAPAB_HCKSUM: 4491 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4492 "==> nxge_m_getcapab: checksum %d", nxge_cksum_offload)); 4493 if (nxge_cksum_offload <= 1) { 4494 *txflags = HCKSUM_INET_PARTIAL; 4495 } 4496 break; 4497 4498 case MAC_CAPAB_POLL: 4499 /* 4500 * There's nothing for us to fill in, simply returning 4501 * B_TRUE stating that we support polling is sufficient. 4502 */ 4503 break; 4504 4505 case MAC_CAPAB_MULTIADDRESS: 4506 mmacp = (multiaddress_capab_t *)cap_data; 4507 mutex_enter(nxgep->genlock); 4508 4509 mmacp->maddr_naddr = nxgep->nxge_mmac_info.num_mmac; 4510 mmacp->maddr_naddrfree = nxgep->nxge_mmac_info.naddrfree; 4511 mmacp->maddr_flag = 0; /* 0 is required by PSARC2006/265 */ 4512 /* 4513 * maddr_handle is driver's private data, passed back to 4514 * entry point functions as arg. 4515 */ 4516 mmacp->maddr_handle = nxgep; 4517 mmacp->maddr_add = nxge_m_mmac_add; 4518 mmacp->maddr_remove = nxge_m_mmac_remove; 4519 mmacp->maddr_modify = nxge_m_mmac_modify; 4520 mmacp->maddr_get = nxge_m_mmac_get; 4521 mmacp->maddr_reserve = nxge_m_mmac_reserve; 4522 4523 mutex_exit(nxgep->genlock); 4524 break; 4525 4526 case MAC_CAPAB_LSO: { 4527 mac_capab_lso_t *cap_lso = cap_data; 4528 4529 if (nxgep->soft_lso_enable) { 4530 if (nxge_cksum_offload <= 1) { 4531 cap_lso->lso_flags = LSO_TX_BASIC_TCP_IPV4; 4532 if (nxge_lso_max > NXGE_LSO_MAXLEN) { 4533 nxge_lso_max = NXGE_LSO_MAXLEN; 4534 } 4535 cap_lso->lso_basic_tcp_ipv4.lso_max = 4536 nxge_lso_max; 4537 } 4538 break; 4539 } else { 4540 return (B_FALSE); 4541 } 4542 } 4543 4544 #if defined(sun4v) 4545 case MAC_CAPAB_RINGS: { 4546 mac_capab_rings_t *mrings = (mac_capab_rings_t *)cap_data; 4547 4548 /* 4549 * Only the service domain driver responds to 4550 * this capability request. 4551 */ 4552 if (isLDOMservice(nxgep)) { 4553 mrings->mr_handle = (void *)nxgep; 4554 4555 /* 4556 * No dynamic allocation of groups and 4557 * rings at this time. Shares dictate the 4558 * configuration. 4559 */ 4560 mrings->mr_gadd_ring = NULL; 4561 mrings->mr_grem_ring = NULL; 4562 mrings->mr_rget = NULL; 4563 mrings->mr_gget = nxge_hio_group_get; 4564 4565 if (mrings->mr_type == MAC_RING_TYPE_RX) { 4566 mrings->mr_rnum = 8; /* XXX */ 4567 mrings->mr_gnum = 6; /* XXX */ 4568 } else { 4569 mrings->mr_rnum = 8; /* XXX */ 4570 mrings->mr_gnum = 0; /* XXX */ 4571 } 4572 } else 4573 return (B_FALSE); 4574 break; 4575 } 4576 4577 case MAC_CAPAB_SHARES: { 4578 mac_capab_share_t *mshares = (mac_capab_share_t *)cap_data; 4579 4580 /* 4581 * Only the service domain driver responds to 4582 * this capability request. 4583 */ 4584 if (isLDOMservice(nxgep)) { 4585 mshares->ms_snum = 3; 4586 mshares->ms_handle = (void *)nxgep; 4587 mshares->ms_salloc = nxge_hio_share_alloc; 4588 mshares->ms_sfree = nxge_hio_share_free; 4589 mshares->ms_sadd = NULL; 4590 mshares->ms_sremove = NULL; 4591 mshares->ms_squery = nxge_hio_share_query; 4592 } else 4593 return (B_FALSE); 4594 break; 4595 } 4596 #endif 4597 default: 4598 return (B_FALSE); 4599 } 4600 return (B_TRUE); 4601 } 4602 4603 static boolean_t 4604 nxge_param_locked(mac_prop_id_t pr_num) 4605 { 4606 /* 4607 * All adv_* parameters are locked (read-only) while 4608 * the device is in any sort of loopback mode ... 4609 */ 4610 switch (pr_num) { 4611 case MAC_PROP_ADV_1000FDX_CAP: 4612 case MAC_PROP_EN_1000FDX_CAP: 4613 case MAC_PROP_ADV_1000HDX_CAP: 4614 case MAC_PROP_EN_1000HDX_CAP: 4615 case MAC_PROP_ADV_100FDX_CAP: 4616 case MAC_PROP_EN_100FDX_CAP: 4617 case MAC_PROP_ADV_100HDX_CAP: 4618 case MAC_PROP_EN_100HDX_CAP: 4619 case MAC_PROP_ADV_10FDX_CAP: 4620 case MAC_PROP_EN_10FDX_CAP: 4621 case MAC_PROP_ADV_10HDX_CAP: 4622 case MAC_PROP_EN_10HDX_CAP: 4623 case MAC_PROP_AUTONEG: 4624 case MAC_PROP_FLOWCTRL: 4625 return (B_TRUE); 4626 } 4627 return (B_FALSE); 4628 } 4629 4630 /* 4631 * callback functions for set/get of properties 4632 */ 4633 static int 4634 nxge_m_setprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4635 uint_t pr_valsize, const void *pr_val) 4636 { 4637 nxge_t *nxgep = barg; 4638 p_nxge_param_t param_arr; 4639 p_nxge_stats_t statsp; 4640 int err = 0; 4641 uint8_t val; 4642 uint32_t cur_mtu, new_mtu, old_framesize; 4643 link_flowctrl_t fl; 4644 4645 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "==> nxge_m_setprop")); 4646 param_arr = nxgep->param_arr; 4647 statsp = nxgep->statsp; 4648 mutex_enter(nxgep->genlock); 4649 if (statsp->port_stats.lb_mode != nxge_lb_normal && 4650 nxge_param_locked(pr_num)) { 4651 /* 4652 * All adv_* parameters are locked (read-only) 4653 * while the device is in any sort of loopback mode. 4654 */ 4655 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4656 "==> nxge_m_setprop: loopback mode: read only")); 4657 mutex_exit(nxgep->genlock); 4658 return (EBUSY); 4659 } 4660 4661 val = *(uint8_t *)pr_val; 4662 switch (pr_num) { 4663 case MAC_PROP_EN_1000FDX_CAP: 4664 nxgep->param_en_1000fdx = val; 4665 param_arr[param_anar_1000fdx].value = val; 4666 4667 goto reprogram; 4668 4669 case MAC_PROP_EN_100FDX_CAP: 4670 nxgep->param_en_100fdx = val; 4671 param_arr[param_anar_100fdx].value = val; 4672 4673 goto reprogram; 4674 4675 case MAC_PROP_EN_10FDX_CAP: 4676 nxgep->param_en_10fdx = val; 4677 param_arr[param_anar_10fdx].value = val; 4678 4679 goto reprogram; 4680 4681 case MAC_PROP_EN_1000HDX_CAP: 4682 case MAC_PROP_EN_100HDX_CAP: 4683 case MAC_PROP_EN_10HDX_CAP: 4684 case MAC_PROP_ADV_1000FDX_CAP: 4685 case MAC_PROP_ADV_1000HDX_CAP: 4686 case MAC_PROP_ADV_100FDX_CAP: 4687 case MAC_PROP_ADV_100HDX_CAP: 4688 case MAC_PROP_ADV_10FDX_CAP: 4689 case MAC_PROP_ADV_10HDX_CAP: 4690 case MAC_PROP_STATUS: 4691 case MAC_PROP_SPEED: 4692 case MAC_PROP_DUPLEX: 4693 err = EINVAL; /* cannot set read-only properties */ 4694 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4695 "==> nxge_m_setprop: read only property %d", 4696 pr_num)); 4697 break; 4698 4699 case MAC_PROP_AUTONEG: 4700 param_arr[param_autoneg].value = val; 4701 4702 goto reprogram; 4703 4704 case MAC_PROP_MTU: 4705 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 4706 err = EBUSY; 4707 break; 4708 } 4709 4710 cur_mtu = nxgep->mac.default_mtu; 4711 bcopy(pr_val, &new_mtu, sizeof (new_mtu)); 4712 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4713 "==> nxge_m_setprop: set MTU: %d is_jumbo %d", 4714 new_mtu, nxgep->mac.is_jumbo)); 4715 4716 if (new_mtu == cur_mtu) { 4717 err = 0; 4718 break; 4719 } 4720 if (new_mtu < NXGE_DEFAULT_MTU || 4721 new_mtu > NXGE_MAXIMUM_MTU) { 4722 err = EINVAL; 4723 break; 4724 } 4725 4726 if ((new_mtu > NXGE_DEFAULT_MTU) && 4727 !nxgep->mac.is_jumbo) { 4728 err = EINVAL; 4729 break; 4730 } 4731 4732 old_framesize = (uint32_t)nxgep->mac.maxframesize; 4733 nxgep->mac.maxframesize = (uint16_t) 4734 (new_mtu + NXGE_EHEADER_VLAN_CRC); 4735 if (nxge_mac_set_framesize(nxgep)) { 4736 nxgep->mac.maxframesize = 4737 (uint16_t)old_framesize; 4738 err = EINVAL; 4739 break; 4740 } 4741 4742 err = mac_maxsdu_update(nxgep->mach, new_mtu); 4743 if (err) { 4744 nxgep->mac.maxframesize = 4745 (uint16_t)old_framesize; 4746 err = EINVAL; 4747 break; 4748 } 4749 4750 nxgep->mac.default_mtu = new_mtu; 4751 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4752 "==> nxge_m_setprop: set MTU: %d maxframe %d", 4753 new_mtu, nxgep->mac.maxframesize)); 4754 break; 4755 4756 case MAC_PROP_FLOWCTRL: 4757 bcopy(pr_val, &fl, sizeof (fl)); 4758 switch (fl) { 4759 default: 4760 err = EINVAL; 4761 break; 4762 4763 case LINK_FLOWCTRL_NONE: 4764 param_arr[param_anar_pause].value = 0; 4765 break; 4766 4767 case LINK_FLOWCTRL_RX: 4768 param_arr[param_anar_pause].value = 1; 4769 break; 4770 4771 case LINK_FLOWCTRL_TX: 4772 case LINK_FLOWCTRL_BI: 4773 err = EINVAL; 4774 break; 4775 } 4776 4777 reprogram: 4778 if (err == 0) { 4779 if (!nxge_param_link_update(nxgep)) { 4780 err = EINVAL; 4781 } 4782 } 4783 break; 4784 case MAC_PROP_PRIVATE: 4785 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4786 "==> nxge_m_setprop: private property")); 4787 err = nxge_set_priv_prop(nxgep, pr_name, pr_valsize, 4788 pr_val); 4789 break; 4790 4791 default: 4792 err = ENOTSUP; 4793 break; 4794 } 4795 4796 mutex_exit(nxgep->genlock); 4797 4798 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4799 "<== nxge_m_setprop (return %d)", err)); 4800 return (err); 4801 } 4802 4803 static int 4804 nxge_m_getprop(void *barg, const char *pr_name, mac_prop_id_t pr_num, 4805 uint_t pr_flags, uint_t pr_valsize, void *pr_val) 4806 { 4807 nxge_t *nxgep = barg; 4808 p_nxge_param_t param_arr = nxgep->param_arr; 4809 p_nxge_stats_t statsp = nxgep->statsp; 4810 int err = 0; 4811 link_flowctrl_t fl; 4812 uint64_t tmp = 0; 4813 link_state_t ls; 4814 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 4815 4816 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4817 "==> nxge_m_getprop: pr_num %d", pr_num)); 4818 4819 if (pr_valsize == 0) 4820 return (EINVAL); 4821 4822 if ((is_default) && (pr_num != MAC_PROP_PRIVATE)) { 4823 err = nxge_get_def_val(nxgep, pr_num, pr_valsize, pr_val); 4824 return (err); 4825 } 4826 4827 bzero(pr_val, pr_valsize); 4828 switch (pr_num) { 4829 case MAC_PROP_DUPLEX: 4830 *(uint8_t *)pr_val = statsp->mac_stats.link_duplex; 4831 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4832 "==> nxge_m_getprop: duplex mode %d", 4833 *(uint8_t *)pr_val)); 4834 break; 4835 4836 case MAC_PROP_SPEED: 4837 if (pr_valsize < sizeof (uint64_t)) 4838 return (EINVAL); 4839 tmp = statsp->mac_stats.link_speed * 1000000ull; 4840 bcopy(&tmp, pr_val, sizeof (tmp)); 4841 break; 4842 4843 case MAC_PROP_STATUS: 4844 if (pr_valsize < sizeof (link_state_t)) 4845 return (EINVAL); 4846 if (!statsp->mac_stats.link_up) 4847 ls = LINK_STATE_DOWN; 4848 else 4849 ls = LINK_STATE_UP; 4850 bcopy(&ls, pr_val, sizeof (ls)); 4851 break; 4852 4853 case MAC_PROP_AUTONEG: 4854 *(uint8_t *)pr_val = 4855 param_arr[param_autoneg].value; 4856 break; 4857 4858 case MAC_PROP_FLOWCTRL: 4859 if (pr_valsize < sizeof (link_flowctrl_t)) 4860 return (EINVAL); 4861 4862 fl = LINK_FLOWCTRL_NONE; 4863 if (param_arr[param_anar_pause].value) { 4864 fl = LINK_FLOWCTRL_RX; 4865 } 4866 bcopy(&fl, pr_val, sizeof (fl)); 4867 break; 4868 4869 case MAC_PROP_ADV_1000FDX_CAP: 4870 *(uint8_t *)pr_val = 4871 param_arr[param_anar_1000fdx].value; 4872 break; 4873 4874 case MAC_PROP_EN_1000FDX_CAP: 4875 *(uint8_t *)pr_val = nxgep->param_en_1000fdx; 4876 break; 4877 4878 case MAC_PROP_ADV_100FDX_CAP: 4879 *(uint8_t *)pr_val = 4880 param_arr[param_anar_100fdx].value; 4881 break; 4882 4883 case MAC_PROP_EN_100FDX_CAP: 4884 *(uint8_t *)pr_val = nxgep->param_en_100fdx; 4885 break; 4886 4887 case MAC_PROP_ADV_10FDX_CAP: 4888 *(uint8_t *)pr_val = 4889 param_arr[param_anar_10fdx].value; 4890 break; 4891 4892 case MAC_PROP_EN_10FDX_CAP: 4893 *(uint8_t *)pr_val = nxgep->param_en_10fdx; 4894 break; 4895 4896 case MAC_PROP_EN_1000HDX_CAP: 4897 case MAC_PROP_EN_100HDX_CAP: 4898 case MAC_PROP_EN_10HDX_CAP: 4899 case MAC_PROP_ADV_1000HDX_CAP: 4900 case MAC_PROP_ADV_100HDX_CAP: 4901 case MAC_PROP_ADV_10HDX_CAP: 4902 err = ENOTSUP; 4903 break; 4904 4905 case MAC_PROP_PRIVATE: 4906 err = nxge_get_priv_prop(nxgep, pr_name, pr_flags, 4907 pr_valsize, pr_val); 4908 break; 4909 default: 4910 err = EINVAL; 4911 break; 4912 } 4913 4914 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, "<== nxge_m_getprop")); 4915 4916 return (err); 4917 } 4918 4919 /* ARGSUSED */ 4920 static int 4921 nxge_set_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_valsize, 4922 const void *pr_val) 4923 { 4924 p_nxge_param_t param_arr = nxgep->param_arr; 4925 int err = 0; 4926 long result; 4927 4928 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4929 "==> nxge_set_priv_prop: name %s", pr_name)); 4930 4931 if (strcmp(pr_name, "_accept_jumbo") == 0) { 4932 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 4933 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4934 "<== nxge_set_priv_prop: name %s " 4935 "pr_val %s result %d " 4936 "param %d is_jumbo %d", 4937 pr_name, pr_val, result, 4938 param_arr[param_accept_jumbo].value, 4939 nxgep->mac.is_jumbo)); 4940 4941 if (result > 1 || result < 0) { 4942 err = EINVAL; 4943 } else { 4944 if (nxgep->mac.is_jumbo == 4945 (uint32_t)result) { 4946 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4947 "no change (%d %d)", 4948 nxgep->mac.is_jumbo, 4949 result)); 4950 return (0); 4951 } 4952 } 4953 4954 param_arr[param_accept_jumbo].value = result; 4955 nxgep->mac.is_jumbo = B_FALSE; 4956 if (result) { 4957 nxgep->mac.is_jumbo = B_TRUE; 4958 } 4959 4960 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4961 "<== nxge_set_priv_prop: name %s (value %d) is_jumbo %d", 4962 pr_name, result, nxgep->mac.is_jumbo)); 4963 4964 return (err); 4965 } 4966 4967 /* Blanking */ 4968 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 4969 err = nxge_param_rx_intr_time(nxgep, NULL, NULL, 4970 (char *)pr_val, 4971 (caddr_t)¶m_arr[param_rxdma_intr_time]); 4972 if (err) { 4973 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4974 "<== nxge_set_priv_prop: " 4975 "unable to set (%s)", pr_name)); 4976 err = EINVAL; 4977 } else { 4978 err = 0; 4979 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4980 "<== nxge_set_priv_prop: " 4981 "set (%s)", pr_name)); 4982 } 4983 4984 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4985 "<== nxge_set_priv_prop: name %s (value %d)", 4986 pr_name, result)); 4987 4988 return (err); 4989 } 4990 4991 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 4992 err = nxge_param_rx_intr_pkts(nxgep, NULL, NULL, 4993 (char *)pr_val, 4994 (caddr_t)¶m_arr[param_rxdma_intr_pkts]); 4995 if (err) { 4996 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 4997 "<== nxge_set_priv_prop: " 4998 "unable to set (%s)", pr_name)); 4999 err = EINVAL; 5000 } else { 5001 err = 0; 5002 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5003 "<== nxge_set_priv_prop: " 5004 "set (%s)", pr_name)); 5005 } 5006 5007 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5008 "<== nxge_set_priv_prop: name %s (value %d)", 5009 pr_name, result)); 5010 5011 return (err); 5012 } 5013 5014 /* Classification */ 5015 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 5016 if (pr_val == NULL) { 5017 err = EINVAL; 5018 return (err); 5019 } 5020 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5021 5022 err = nxge_param_set_ip_opt(nxgep, NULL, 5023 NULL, (char *)pr_val, 5024 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 5025 5026 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5027 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5028 pr_name, result)); 5029 5030 return (err); 5031 } 5032 5033 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 5034 if (pr_val == NULL) { 5035 err = EINVAL; 5036 return (err); 5037 } 5038 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5039 5040 err = nxge_param_set_ip_opt(nxgep, NULL, 5041 NULL, (char *)pr_val, 5042 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 5043 5044 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5045 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5046 pr_name, result)); 5047 5048 return (err); 5049 } 5050 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 5051 if (pr_val == NULL) { 5052 err = EINVAL; 5053 return (err); 5054 } 5055 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5056 5057 err = nxge_param_set_ip_opt(nxgep, NULL, 5058 NULL, (char *)pr_val, 5059 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 5060 5061 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5062 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5063 pr_name, result)); 5064 5065 return (err); 5066 } 5067 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 5068 if (pr_val == NULL) { 5069 err = EINVAL; 5070 return (err); 5071 } 5072 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5073 5074 err = nxge_param_set_ip_opt(nxgep, NULL, 5075 NULL, (char *)pr_val, 5076 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 5077 5078 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5079 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5080 pr_name, result)); 5081 5082 return (err); 5083 } 5084 5085 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 5086 if (pr_val == NULL) { 5087 err = EINVAL; 5088 return (err); 5089 } 5090 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5091 5092 err = nxge_param_set_ip_opt(nxgep, NULL, 5093 NULL, (char *)pr_val, 5094 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 5095 5096 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5097 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5098 pr_name, result)); 5099 5100 return (err); 5101 } 5102 5103 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 5104 if (pr_val == NULL) { 5105 err = EINVAL; 5106 return (err); 5107 } 5108 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5109 5110 err = nxge_param_set_ip_opt(nxgep, NULL, 5111 NULL, (char *)pr_val, 5112 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 5113 5114 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5115 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5116 pr_name, result)); 5117 5118 return (err); 5119 } 5120 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 5121 if (pr_val == NULL) { 5122 err = EINVAL; 5123 return (err); 5124 } 5125 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5126 5127 err = nxge_param_set_ip_opt(nxgep, NULL, 5128 NULL, (char *)pr_val, 5129 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 5130 5131 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5132 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5133 pr_name, result)); 5134 5135 return (err); 5136 } 5137 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 5138 if (pr_val == NULL) { 5139 err = EINVAL; 5140 return (err); 5141 } 5142 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5143 5144 err = nxge_param_set_ip_opt(nxgep, NULL, 5145 NULL, (char *)pr_val, 5146 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 5147 5148 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5149 "<== nxge_set_priv_prop: name %s (value 0x%x)", 5150 pr_name, result)); 5151 5152 return (err); 5153 } 5154 5155 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 5156 if (nxgep->nxge_mac_state == NXGE_MAC_STARTED) { 5157 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5158 "==> nxge_set_priv_prop: name %s (busy)", pr_name)); 5159 err = EBUSY; 5160 return (err); 5161 } 5162 if (pr_val == NULL) { 5163 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5164 "==> nxge_set_priv_prop: name %s (null)", pr_name)); 5165 err = EINVAL; 5166 return (err); 5167 } 5168 5169 (void) ddi_strtol(pr_val, (char **)NULL, 0, &result); 5170 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5171 "<== nxge_set_priv_prop: name %s " 5172 "(lso %d pr_val %s value %d)", 5173 pr_name, nxgep->soft_lso_enable, pr_val, result)); 5174 5175 if (result > 1 || result < 0) { 5176 err = EINVAL; 5177 } else { 5178 if (nxgep->soft_lso_enable == (uint32_t)result) { 5179 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5180 "no change (%d %d)", 5181 nxgep->soft_lso_enable, result)); 5182 return (0); 5183 } 5184 } 5185 5186 nxgep->soft_lso_enable = (int)result; 5187 5188 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5189 "<== nxge_set_priv_prop: name %s (value %d)", 5190 pr_name, result)); 5191 5192 return (err); 5193 } 5194 /* 5195 * Commands like "ndd -set /dev/nxge0 adv_10gfdx_cap 1" cause the 5196 * following code to be executed. 5197 */ 5198 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 5199 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 5200 (caddr_t)¶m_arr[param_anar_10gfdx]); 5201 return (err); 5202 } 5203 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 5204 err = nxge_param_set_mac(nxgep, NULL, NULL, (char *)pr_val, 5205 (caddr_t)¶m_arr[param_anar_pause]); 5206 return (err); 5207 } 5208 5209 return (EINVAL); 5210 } 5211 5212 static int 5213 nxge_get_priv_prop(p_nxge_t nxgep, const char *pr_name, uint_t pr_flags, 5214 uint_t pr_valsize, void *pr_val) 5215 { 5216 p_nxge_param_t param_arr = nxgep->param_arr; 5217 char valstr[MAXNAMELEN]; 5218 int err = EINVAL; 5219 uint_t strsize; 5220 boolean_t is_default = (pr_flags & MAC_PROP_DEFAULT); 5221 5222 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5223 "==> nxge_get_priv_prop: property %s", pr_name)); 5224 5225 /* function number */ 5226 if (strcmp(pr_name, "_function_number") == 0) { 5227 if (is_default) 5228 return (ENOTSUP); 5229 (void) snprintf(valstr, sizeof (valstr), "%d", 5230 nxgep->function_num); 5231 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5232 "==> nxge_get_priv_prop: name %s " 5233 "(value %d valstr %s)", 5234 pr_name, nxgep->function_num, valstr)); 5235 5236 err = 0; 5237 goto done; 5238 } 5239 5240 /* Neptune firmware version */ 5241 if (strcmp(pr_name, "_fw_version") == 0) { 5242 if (is_default) 5243 return (ENOTSUP); 5244 (void) snprintf(valstr, sizeof (valstr), "%s", 5245 nxgep->vpd_info.ver); 5246 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5247 "==> nxge_get_priv_prop: name %s " 5248 "(value %d valstr %s)", 5249 pr_name, nxgep->vpd_info.ver, valstr)); 5250 5251 err = 0; 5252 goto done; 5253 } 5254 5255 /* port PHY mode */ 5256 if (strcmp(pr_name, "_port_mode") == 0) { 5257 if (is_default) 5258 return (ENOTSUP); 5259 switch (nxgep->mac.portmode) { 5260 case PORT_1G_COPPER: 5261 (void) snprintf(valstr, sizeof (valstr), "1G copper %s", 5262 nxgep->hot_swappable_phy ? 5263 "[Hot Swappable]" : ""); 5264 break; 5265 case PORT_1G_FIBER: 5266 (void) snprintf(valstr, sizeof (valstr), "1G fiber %s", 5267 nxgep->hot_swappable_phy ? 5268 "[hot swappable]" : ""); 5269 break; 5270 case PORT_10G_COPPER: 5271 (void) snprintf(valstr, sizeof (valstr), 5272 "10G copper %s", 5273 nxgep->hot_swappable_phy ? 5274 "[hot swappable]" : ""); 5275 break; 5276 case PORT_10G_FIBER: 5277 (void) snprintf(valstr, sizeof (valstr), "10G fiber %s", 5278 nxgep->hot_swappable_phy ? 5279 "[hot swappable]" : ""); 5280 break; 5281 case PORT_10G_SERDES: 5282 (void) snprintf(valstr, sizeof (valstr), 5283 "10G serdes %s", nxgep->hot_swappable_phy ? 5284 "[hot swappable]" : ""); 5285 break; 5286 case PORT_1G_SERDES: 5287 (void) snprintf(valstr, sizeof (valstr), "1G serdes %s", 5288 nxgep->hot_swappable_phy ? 5289 "[hot swappable]" : ""); 5290 break; 5291 case PORT_1G_TN1010: 5292 (void) snprintf(valstr, sizeof (valstr), 5293 "1G TN1010 copper %s", nxgep->hot_swappable_phy ? 5294 "[hot swappable]" : ""); 5295 break; 5296 case PORT_10G_TN1010: 5297 (void) snprintf(valstr, sizeof (valstr), 5298 "10G TN1010 copper %s", nxgep->hot_swappable_phy ? 5299 "[hot swappable]" : ""); 5300 break; 5301 case PORT_1G_RGMII_FIBER: 5302 (void) snprintf(valstr, sizeof (valstr), 5303 "1G rgmii fiber %s", nxgep->hot_swappable_phy ? 5304 "[hot swappable]" : ""); 5305 break; 5306 case PORT_HSP_MODE: 5307 (void) snprintf(valstr, sizeof (valstr), 5308 "phy not present[hot swappable]"); 5309 break; 5310 default: 5311 (void) snprintf(valstr, sizeof (valstr), "unknown %s", 5312 nxgep->hot_swappable_phy ? 5313 "[hot swappable]" : ""); 5314 break; 5315 } 5316 5317 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5318 "==> nxge_get_priv_prop: name %s (value %s)", 5319 pr_name, valstr)); 5320 5321 err = 0; 5322 goto done; 5323 } 5324 5325 /* Hot swappable PHY */ 5326 if (strcmp(pr_name, "_hot_swap_phy") == 0) { 5327 if (is_default) 5328 return (ENOTSUP); 5329 (void) snprintf(valstr, sizeof (valstr), "%s", 5330 nxgep->hot_swappable_phy ? 5331 "yes" : "no"); 5332 5333 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5334 "==> nxge_get_priv_prop: name %s " 5335 "(value %d valstr %s)", 5336 pr_name, nxgep->hot_swappable_phy, valstr)); 5337 5338 err = 0; 5339 goto done; 5340 } 5341 5342 5343 /* accept jumbo */ 5344 if (strcmp(pr_name, "_accept_jumbo") == 0) { 5345 if (is_default) 5346 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5347 else 5348 (void) snprintf(valstr, sizeof (valstr), 5349 "%d", nxgep->mac.is_jumbo); 5350 err = 0; 5351 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5352 "==> nxge_get_priv_prop: name %s (value %d (%d, %d))", 5353 pr_name, 5354 (uint32_t)param_arr[param_accept_jumbo].value, 5355 nxgep->mac.is_jumbo, 5356 nxge_jumbo_enable)); 5357 5358 goto done; 5359 } 5360 5361 /* Receive Interrupt Blanking Parameters */ 5362 if (strcmp(pr_name, "_rxdma_intr_time") == 0) { 5363 err = 0; 5364 if (is_default) { 5365 (void) snprintf(valstr, sizeof (valstr), 5366 "%d", RXDMA_RCR_TO_DEFAULT); 5367 goto done; 5368 } 5369 5370 (void) snprintf(valstr, sizeof (valstr), "%d", 5371 nxgep->intr_timeout); 5372 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5373 "==> nxge_get_priv_prop: name %s (value %d)", 5374 pr_name, 5375 (uint32_t)nxgep->intr_timeout)); 5376 goto done; 5377 } 5378 5379 if (strcmp(pr_name, "_rxdma_intr_pkts") == 0) { 5380 err = 0; 5381 if (is_default) { 5382 (void) snprintf(valstr, sizeof (valstr), 5383 "%d", RXDMA_RCR_PTHRES_DEFAULT); 5384 goto done; 5385 } 5386 (void) snprintf(valstr, sizeof (valstr), "%d", 5387 nxgep->intr_threshold); 5388 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5389 "==> nxge_get_priv_prop: name %s (value %d)", 5390 pr_name, (uint32_t)nxgep->intr_threshold)); 5391 5392 goto done; 5393 } 5394 5395 /* Classification and Load Distribution Configuration */ 5396 if (strcmp(pr_name, "_class_opt_ipv4_tcp") == 0) { 5397 if (is_default) { 5398 (void) snprintf(valstr, sizeof (valstr), "%x", 5399 NXGE_CLASS_FLOW_GEN_SERVER); 5400 err = 0; 5401 goto done; 5402 } 5403 err = nxge_dld_get_ip_opt(nxgep, 5404 (caddr_t)¶m_arr[param_class_opt_ipv4_tcp]); 5405 5406 (void) snprintf(valstr, sizeof (valstr), "%x", 5407 (int)param_arr[param_class_opt_ipv4_tcp].value); 5408 5409 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5410 "==> nxge_get_priv_prop: %s", valstr)); 5411 goto done; 5412 } 5413 5414 if (strcmp(pr_name, "_class_opt_ipv4_udp") == 0) { 5415 if (is_default) { 5416 (void) snprintf(valstr, sizeof (valstr), "%x", 5417 NXGE_CLASS_FLOW_GEN_SERVER); 5418 err = 0; 5419 goto done; 5420 } 5421 err = nxge_dld_get_ip_opt(nxgep, 5422 (caddr_t)¶m_arr[param_class_opt_ipv4_udp]); 5423 5424 (void) snprintf(valstr, sizeof (valstr), "%x", 5425 (int)param_arr[param_class_opt_ipv4_udp].value); 5426 5427 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5428 "==> nxge_get_priv_prop: %s", valstr)); 5429 goto done; 5430 } 5431 if (strcmp(pr_name, "_class_opt_ipv4_ah") == 0) { 5432 if (is_default) { 5433 (void) snprintf(valstr, sizeof (valstr), "%x", 5434 NXGE_CLASS_FLOW_GEN_SERVER); 5435 err = 0; 5436 goto done; 5437 } 5438 err = nxge_dld_get_ip_opt(nxgep, 5439 (caddr_t)¶m_arr[param_class_opt_ipv4_ah]); 5440 5441 (void) snprintf(valstr, sizeof (valstr), "%x", 5442 (int)param_arr[param_class_opt_ipv4_ah].value); 5443 5444 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5445 "==> nxge_get_priv_prop: %s", valstr)); 5446 goto done; 5447 } 5448 5449 if (strcmp(pr_name, "_class_opt_ipv4_sctp") == 0) { 5450 if (is_default) { 5451 (void) snprintf(valstr, sizeof (valstr), "%x", 5452 NXGE_CLASS_FLOW_GEN_SERVER); 5453 err = 0; 5454 goto done; 5455 } 5456 err = nxge_dld_get_ip_opt(nxgep, 5457 (caddr_t)¶m_arr[param_class_opt_ipv4_sctp]); 5458 5459 (void) snprintf(valstr, sizeof (valstr), "%x", 5460 (int)param_arr[param_class_opt_ipv4_sctp].value); 5461 5462 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5463 "==> nxge_get_priv_prop: %s", valstr)); 5464 goto done; 5465 } 5466 5467 if (strcmp(pr_name, "_class_opt_ipv6_tcp") == 0) { 5468 if (is_default) { 5469 (void) snprintf(valstr, sizeof (valstr), "%x", 5470 NXGE_CLASS_FLOW_GEN_SERVER); 5471 err = 0; 5472 goto done; 5473 } 5474 err = nxge_dld_get_ip_opt(nxgep, 5475 (caddr_t)¶m_arr[param_class_opt_ipv6_tcp]); 5476 5477 (void) snprintf(valstr, sizeof (valstr), "%x", 5478 (int)param_arr[param_class_opt_ipv6_tcp].value); 5479 5480 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5481 "==> nxge_get_priv_prop: %s", valstr)); 5482 goto done; 5483 } 5484 5485 if (strcmp(pr_name, "_class_opt_ipv6_udp") == 0) { 5486 if (is_default) { 5487 (void) snprintf(valstr, sizeof (valstr), "%x", 5488 NXGE_CLASS_FLOW_GEN_SERVER); 5489 err = 0; 5490 goto done; 5491 } 5492 err = nxge_dld_get_ip_opt(nxgep, 5493 (caddr_t)¶m_arr[param_class_opt_ipv6_udp]); 5494 5495 (void) snprintf(valstr, sizeof (valstr), "%x", 5496 (int)param_arr[param_class_opt_ipv6_udp].value); 5497 5498 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5499 "==> nxge_get_priv_prop: %s", valstr)); 5500 goto done; 5501 } 5502 5503 if (strcmp(pr_name, "_class_opt_ipv6_ah") == 0) { 5504 if (is_default) { 5505 (void) snprintf(valstr, sizeof (valstr), "%x", 5506 NXGE_CLASS_FLOW_GEN_SERVER); 5507 err = 0; 5508 goto done; 5509 } 5510 err = nxge_dld_get_ip_opt(nxgep, 5511 (caddr_t)¶m_arr[param_class_opt_ipv6_ah]); 5512 5513 (void) snprintf(valstr, sizeof (valstr), "%x", 5514 (int)param_arr[param_class_opt_ipv6_ah].value); 5515 5516 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5517 "==> nxge_get_priv_prop: %s", valstr)); 5518 goto done; 5519 } 5520 5521 if (strcmp(pr_name, "_class_opt_ipv6_sctp") == 0) { 5522 if (is_default) { 5523 (void) snprintf(valstr, sizeof (valstr), "%x", 5524 NXGE_CLASS_FLOW_GEN_SERVER); 5525 err = 0; 5526 goto done; 5527 } 5528 err = nxge_dld_get_ip_opt(nxgep, 5529 (caddr_t)¶m_arr[param_class_opt_ipv6_sctp]); 5530 5531 (void) snprintf(valstr, sizeof (valstr), "%x", 5532 (int)param_arr[param_class_opt_ipv6_sctp].value); 5533 5534 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5535 "==> nxge_get_priv_prop: %s", valstr)); 5536 goto done; 5537 } 5538 5539 /* Software LSO */ 5540 if (strcmp(pr_name, "_soft_lso_enable") == 0) { 5541 if (is_default) { 5542 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5543 err = 0; 5544 goto done; 5545 } 5546 (void) snprintf(valstr, sizeof (valstr), 5547 "%d", nxgep->soft_lso_enable); 5548 err = 0; 5549 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5550 "==> nxge_get_priv_prop: name %s (value %d)", 5551 pr_name, nxgep->soft_lso_enable)); 5552 5553 goto done; 5554 } 5555 if (strcmp(pr_name, "_adv_10gfdx_cap") == 0) { 5556 err = 0; 5557 if (is_default || 5558 nxgep->param_arr[param_anar_10gfdx].value != 0) { 5559 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5560 goto done; 5561 } else { 5562 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5563 goto done; 5564 } 5565 } 5566 if (strcmp(pr_name, "_adv_pause_cap") == 0) { 5567 err = 0; 5568 if (is_default || 5569 nxgep->param_arr[param_anar_pause].value != 0) { 5570 (void) snprintf(valstr, sizeof (valstr), "%d", 1); 5571 goto done; 5572 } else { 5573 (void) snprintf(valstr, sizeof (valstr), "%d", 0); 5574 goto done; 5575 } 5576 } 5577 5578 done: 5579 if (err == 0) { 5580 strsize = (uint_t)strlen(valstr); 5581 if (pr_valsize < strsize) { 5582 err = ENOBUFS; 5583 } else { 5584 (void) strlcpy(pr_val, valstr, pr_valsize); 5585 } 5586 } 5587 5588 NXGE_DEBUG_MSG((nxgep, NXGE_CTL, 5589 "<== nxge_get_priv_prop: return %d", err)); 5590 return (err); 5591 } 5592 5593 /* 5594 * Module loading and removing entry points. 5595 */ 5596 5597 DDI_DEFINE_STREAM_OPS(nxge_dev_ops, nulldev, nulldev, nxge_attach, nxge_detach, 5598 nodev, NULL, D_MP, NULL, nxge_quiesce); 5599 5600 #define NXGE_DESC_VER "Sun NIU 10Gb Ethernet" 5601 5602 /* 5603 * Module linkage information for the kernel. 5604 */ 5605 static struct modldrv nxge_modldrv = { 5606 &mod_driverops, 5607 NXGE_DESC_VER, 5608 &nxge_dev_ops 5609 }; 5610 5611 static struct modlinkage modlinkage = { 5612 MODREV_1, (void *) &nxge_modldrv, NULL 5613 }; 5614 5615 int 5616 _init(void) 5617 { 5618 int status; 5619 5620 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _init")); 5621 mac_init_ops(&nxge_dev_ops, "nxge"); 5622 status = ddi_soft_state_init(&nxge_list, sizeof (nxge_t), 0); 5623 if (status != 0) { 5624 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, 5625 "failed to init device soft state")); 5626 goto _init_exit; 5627 } 5628 status = mod_install(&modlinkage); 5629 if (status != 0) { 5630 ddi_soft_state_fini(&nxge_list); 5631 NXGE_ERROR_MSG((NULL, NXGE_ERR_CTL, "Mod install failed")); 5632 goto _init_exit; 5633 } 5634 5635 MUTEX_INIT(&nxge_common_lock, NULL, MUTEX_DRIVER, NULL); 5636 5637 _init_exit: 5638 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_init status = 0x%X", status)); 5639 5640 return (status); 5641 } 5642 5643 int 5644 _fini(void) 5645 { 5646 int status; 5647 5648 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini")); 5649 5650 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _fini: mod_remove")); 5651 5652 if (nxge_mblks_pending) 5653 return (EBUSY); 5654 5655 status = mod_remove(&modlinkage); 5656 if (status != DDI_SUCCESS) { 5657 NXGE_DEBUG_MSG((NULL, MOD_CTL, 5658 "Module removal failed 0x%08x", 5659 status)); 5660 goto _fini_exit; 5661 } 5662 5663 mac_fini_ops(&nxge_dev_ops); 5664 5665 ddi_soft_state_fini(&nxge_list); 5666 5667 MUTEX_DESTROY(&nxge_common_lock); 5668 _fini_exit: 5669 NXGE_DEBUG_MSG((NULL, MOD_CTL, "_fini status = 0x%08x", status)); 5670 5671 return (status); 5672 } 5673 5674 int 5675 _info(struct modinfo *modinfop) 5676 { 5677 int status; 5678 5679 NXGE_DEBUG_MSG((NULL, MOD_CTL, "==> _info")); 5680 status = mod_info(&modlinkage, modinfop); 5681 NXGE_DEBUG_MSG((NULL, MOD_CTL, " _info status = 0x%X", status)); 5682 5683 return (status); 5684 } 5685 5686 /*ARGSUSED*/ 5687 static nxge_status_t 5688 nxge_add_intrs(p_nxge_t nxgep) 5689 { 5690 5691 int intr_types; 5692 int type = 0; 5693 int ddi_status = DDI_SUCCESS; 5694 nxge_status_t status = NXGE_OK; 5695 5696 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs")); 5697 5698 nxgep->nxge_intr_type.intr_registered = B_FALSE; 5699 nxgep->nxge_intr_type.intr_enabled = B_FALSE; 5700 nxgep->nxge_intr_type.msi_intx_cnt = 0; 5701 nxgep->nxge_intr_type.intr_added = 0; 5702 nxgep->nxge_intr_type.niu_msi_enable = B_FALSE; 5703 nxgep->nxge_intr_type.intr_type = 0; 5704 5705 if (nxgep->niu_type == N2_NIU) { 5706 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5707 } else if (nxge_msi_enable) { 5708 nxgep->nxge_intr_type.niu_msi_enable = B_TRUE; 5709 } 5710 5711 /* Get the supported interrupt types */ 5712 if ((ddi_status = ddi_intr_get_supported_types(nxgep->dip, &intr_types)) 5713 != DDI_SUCCESS) { 5714 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_intrs: " 5715 "ddi_intr_get_supported_types failed: status 0x%08x", 5716 ddi_status)); 5717 return (NXGE_ERROR | NXGE_DDI_FAILED); 5718 } 5719 nxgep->nxge_intr_type.intr_types = intr_types; 5720 5721 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5722 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5723 5724 /* 5725 * Solaris MSIX is not supported yet. use MSI for now. 5726 * nxge_msi_enable (1): 5727 * 1 - MSI 2 - MSI-X others - FIXED 5728 */ 5729 switch (nxge_msi_enable) { 5730 default: 5731 type = DDI_INTR_TYPE_FIXED; 5732 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5733 "use fixed (intx emulation) type %08x", 5734 type)); 5735 break; 5736 5737 case 2: 5738 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5739 "ddi_intr_get_supported_types: 0x%08x", intr_types)); 5740 if (intr_types & DDI_INTR_TYPE_MSIX) { 5741 type = DDI_INTR_TYPE_MSIX; 5742 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5743 "ddi_intr_get_supported_types: MSIX 0x%08x", 5744 type)); 5745 } else if (intr_types & DDI_INTR_TYPE_MSI) { 5746 type = DDI_INTR_TYPE_MSI; 5747 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5748 "ddi_intr_get_supported_types: MSI 0x%08x", 5749 type)); 5750 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5751 type = DDI_INTR_TYPE_FIXED; 5752 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5753 "ddi_intr_get_supported_types: MSXED0x%08x", 5754 type)); 5755 } 5756 break; 5757 5758 case 1: 5759 if (intr_types & DDI_INTR_TYPE_MSI) { 5760 type = DDI_INTR_TYPE_MSI; 5761 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs: " 5762 "ddi_intr_get_supported_types: MSI 0x%08x", 5763 type)); 5764 } else if (intr_types & DDI_INTR_TYPE_MSIX) { 5765 type = DDI_INTR_TYPE_MSIX; 5766 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5767 "ddi_intr_get_supported_types: MSIX 0x%08x", 5768 type)); 5769 } else if (intr_types & DDI_INTR_TYPE_FIXED) { 5770 type = DDI_INTR_TYPE_FIXED; 5771 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5772 "ddi_intr_get_supported_types: MSXED0x%08x", 5773 type)); 5774 } 5775 } 5776 5777 nxgep->nxge_intr_type.intr_type = type; 5778 if ((type == DDI_INTR_TYPE_MSIX || type == DDI_INTR_TYPE_MSI || 5779 type == DDI_INTR_TYPE_FIXED) && 5780 nxgep->nxge_intr_type.niu_msi_enable) { 5781 if ((status = nxge_add_intrs_adv(nxgep)) != DDI_SUCCESS) { 5782 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5783 " nxge_add_intrs: " 5784 " nxge_add_intrs_adv failed: status 0x%08x", 5785 status)); 5786 return (status); 5787 } else { 5788 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs: " 5789 "interrupts registered : type %d", type)); 5790 nxgep->nxge_intr_type.intr_registered = B_TRUE; 5791 5792 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 5793 "\nAdded advanced nxge add_intr_adv " 5794 "intr type 0x%x\n", type)); 5795 5796 return (status); 5797 } 5798 } 5799 5800 if (!nxgep->nxge_intr_type.intr_registered) { 5801 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_add_intrs: " 5802 "failed to register interrupts")); 5803 return (NXGE_ERROR | NXGE_DDI_FAILED); 5804 } 5805 5806 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_add_intrs")); 5807 return (status); 5808 } 5809 5810 /*ARGSUSED*/ 5811 static nxge_status_t 5812 nxge_add_soft_intrs(p_nxge_t nxgep) 5813 { 5814 5815 int ddi_status = DDI_SUCCESS; 5816 nxge_status_t status = NXGE_OK; 5817 5818 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_soft_intrs")); 5819 5820 nxgep->resched_id = NULL; 5821 nxgep->resched_running = B_FALSE; 5822 ddi_status = ddi_add_softintr(nxgep->dip, DDI_SOFTINT_LOW, 5823 &nxgep->resched_id, 5824 NULL, NULL, nxge_reschedule, (caddr_t)nxgep); 5825 if (ddi_status != DDI_SUCCESS) { 5826 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_add_soft_intrs: " 5827 "ddi_add_softintrs failed: status 0x%08x", 5828 ddi_status)); 5829 return (NXGE_ERROR | NXGE_DDI_FAILED); 5830 } 5831 5832 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_ddi_add_soft_intrs")); 5833 5834 return (status); 5835 } 5836 5837 static nxge_status_t 5838 nxge_add_intrs_adv(p_nxge_t nxgep) 5839 { 5840 int intr_type; 5841 p_nxge_intr_t intrp; 5842 5843 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv")); 5844 5845 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5846 intr_type = intrp->intr_type; 5847 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_add_intrs_adv: type 0x%x", 5848 intr_type)); 5849 5850 switch (intr_type) { 5851 case DDI_INTR_TYPE_MSI: /* 0x2 */ 5852 case DDI_INTR_TYPE_MSIX: /* 0x4 */ 5853 return (nxge_add_intrs_adv_type(nxgep, intr_type)); 5854 5855 case DDI_INTR_TYPE_FIXED: /* 0x1 */ 5856 return (nxge_add_intrs_adv_type_fix(nxgep, intr_type)); 5857 5858 default: 5859 return (NXGE_ERROR); 5860 } 5861 } 5862 5863 5864 /*ARGSUSED*/ 5865 static nxge_status_t 5866 nxge_add_intrs_adv_type(p_nxge_t nxgep, uint32_t int_type) 5867 { 5868 dev_info_t *dip = nxgep->dip; 5869 p_nxge_ldg_t ldgp; 5870 p_nxge_intr_t intrp; 5871 uint_t *inthandler; 5872 void *arg1, *arg2; 5873 int behavior; 5874 int nintrs, navail, nrequest; 5875 int nactual, nrequired; 5876 int inum = 0; 5877 int x, y; 5878 int ddi_status = DDI_SUCCESS; 5879 nxge_status_t status = NXGE_OK; 5880 5881 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type")); 5882 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 5883 intrp->start_inum = 0; 5884 5885 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 5886 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 5887 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5888 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 5889 "nintrs: %d", ddi_status, nintrs)); 5890 return (NXGE_ERROR | NXGE_DDI_FAILED); 5891 } 5892 5893 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 5894 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 5895 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5896 "ddi_intr_get_navail() failed, status: 0x%x%, " 5897 "nintrs: %d", ddi_status, navail)); 5898 return (NXGE_ERROR | NXGE_DDI_FAILED); 5899 } 5900 5901 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5902 "ddi_intr_get_navail() returned: nintrs %d, navail %d", 5903 nintrs, navail)); 5904 5905 /* PSARC/2007/453 MSI-X interrupt limit override */ 5906 if (int_type == DDI_INTR_TYPE_MSIX) { 5907 nrequest = nxge_create_msi_property(nxgep); 5908 if (nrequest < navail) { 5909 navail = nrequest; 5910 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5911 "nxge_add_intrs_adv_type: nintrs %d " 5912 "navail %d (nrequest %d)", 5913 nintrs, navail, nrequest)); 5914 } 5915 } 5916 5917 if (int_type == DDI_INTR_TYPE_MSI && !ISP2(navail)) { 5918 /* MSI must be power of 2 */ 5919 if ((navail & 16) == 16) { 5920 navail = 16; 5921 } else if ((navail & 8) == 8) { 5922 navail = 8; 5923 } else if ((navail & 4) == 4) { 5924 navail = 4; 5925 } else if ((navail & 2) == 2) { 5926 navail = 2; 5927 } else { 5928 navail = 1; 5929 } 5930 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5931 "ddi_intr_get_navail(): (msi power of 2) nintrs %d, " 5932 "navail %d", nintrs, navail)); 5933 } 5934 5935 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 5936 DDI_INTR_ALLOC_NORMAL); 5937 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 5938 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 5939 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 5940 navail, &nactual, behavior); 5941 if (ddi_status != DDI_SUCCESS || nactual == 0) { 5942 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5943 " ddi_intr_alloc() failed: %d", 5944 ddi_status)); 5945 kmem_free(intrp->htable, intrp->intr_size); 5946 return (NXGE_ERROR | NXGE_DDI_FAILED); 5947 } 5948 5949 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 5950 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 5951 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5952 " ddi_intr_get_pri() failed: %d", 5953 ddi_status)); 5954 /* Free already allocated interrupts */ 5955 for (y = 0; y < nactual; y++) { 5956 (void) ddi_intr_free(intrp->htable[y]); 5957 } 5958 5959 kmem_free(intrp->htable, intrp->intr_size); 5960 return (NXGE_ERROR | NXGE_DDI_FAILED); 5961 } 5962 5963 nrequired = 0; 5964 switch (nxgep->niu_type) { 5965 default: 5966 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 5967 break; 5968 5969 case N2_NIU: 5970 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 5971 break; 5972 } 5973 5974 if (status != NXGE_OK) { 5975 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 5976 "nxge_add_intrs_adv_typ:nxge_ldgv_init " 5977 "failed: 0x%x", status)); 5978 /* Free already allocated interrupts */ 5979 for (y = 0; y < nactual; y++) { 5980 (void) ddi_intr_free(intrp->htable[y]); 5981 } 5982 5983 kmem_free(intrp->htable, intrp->intr_size); 5984 return (status); 5985 } 5986 5987 ldgp = nxgep->ldgvp->ldgp; 5988 for (x = 0; x < nrequired; x++, ldgp++) { 5989 ldgp->vector = (uint8_t)x; 5990 ldgp->intdata = SID_DATA(ldgp->func, x); 5991 arg1 = ldgp->ldvp; 5992 arg2 = nxgep; 5993 if (ldgp->nldvs == 1) { 5994 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 5995 NXGE_DEBUG_MSG((nxgep, INT_CTL, 5996 "nxge_add_intrs_adv_type: " 5997 "arg1 0x%x arg2 0x%x: " 5998 "1-1 int handler (entry %d intdata 0x%x)\n", 5999 arg1, arg2, 6000 x, ldgp->intdata)); 6001 } else if (ldgp->nldvs > 1) { 6002 inthandler = (uint_t *)ldgp->sys_intr_handler; 6003 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6004 "nxge_add_intrs_adv_type: " 6005 "arg1 0x%x arg2 0x%x: " 6006 "nldevs %d int handler " 6007 "(entry %d intdata 0x%x)\n", 6008 arg1, arg2, 6009 ldgp->nldvs, x, ldgp->intdata)); 6010 } 6011 6012 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6013 "==> nxge_add_intrs_adv_type: ddi_add_intr(inum) #%d " 6014 "htable 0x%llx", x, intrp->htable[x])); 6015 6016 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6017 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 6018 != DDI_SUCCESS) { 6019 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6020 "==> nxge_add_intrs_adv_type: failed #%d " 6021 "status 0x%x", x, ddi_status)); 6022 for (y = 0; y < intrp->intr_added; y++) { 6023 (void) ddi_intr_remove_handler( 6024 intrp->htable[y]); 6025 } 6026 /* Free already allocated intr */ 6027 for (y = 0; y < nactual; y++) { 6028 (void) ddi_intr_free(intrp->htable[y]); 6029 } 6030 kmem_free(intrp->htable, intrp->intr_size); 6031 6032 (void) nxge_ldgv_uninit(nxgep); 6033 6034 return (NXGE_ERROR | NXGE_DDI_FAILED); 6035 } 6036 intrp->intr_added++; 6037 } 6038 6039 intrp->msi_intx_cnt = nactual; 6040 6041 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6042 "Requested: %d, Allowed: %d msi_intx_cnt %d intr_added %d", 6043 navail, nactual, 6044 intrp->msi_intx_cnt, 6045 intrp->intr_added)); 6046 6047 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6048 6049 (void) nxge_intr_ldgv_init(nxgep); 6050 6051 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type")); 6052 6053 return (status); 6054 } 6055 6056 /*ARGSUSED*/ 6057 static nxge_status_t 6058 nxge_add_intrs_adv_type_fix(p_nxge_t nxgep, uint32_t int_type) 6059 { 6060 dev_info_t *dip = nxgep->dip; 6061 p_nxge_ldg_t ldgp; 6062 p_nxge_intr_t intrp; 6063 uint_t *inthandler; 6064 void *arg1, *arg2; 6065 int behavior; 6066 int nintrs, navail; 6067 int nactual, nrequired; 6068 int inum = 0; 6069 int x, y; 6070 int ddi_status = DDI_SUCCESS; 6071 nxge_status_t status = NXGE_OK; 6072 6073 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_add_intrs_adv_type_fix")); 6074 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6075 intrp->start_inum = 0; 6076 6077 ddi_status = ddi_intr_get_nintrs(dip, int_type, &nintrs); 6078 if ((ddi_status != DDI_SUCCESS) || (nintrs == 0)) { 6079 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6080 "ddi_intr_get_nintrs() failed, status: 0x%x%, " 6081 "nintrs: %d", status, nintrs)); 6082 return (NXGE_ERROR | NXGE_DDI_FAILED); 6083 } 6084 6085 ddi_status = ddi_intr_get_navail(dip, int_type, &navail); 6086 if ((ddi_status != DDI_SUCCESS) || (navail == 0)) { 6087 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6088 "ddi_intr_get_navail() failed, status: 0x%x%, " 6089 "nintrs: %d", ddi_status, navail)); 6090 return (NXGE_ERROR | NXGE_DDI_FAILED); 6091 } 6092 6093 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6094 "ddi_intr_get_navail() returned: nintrs %d, naavail %d", 6095 nintrs, navail)); 6096 6097 behavior = ((int_type == DDI_INTR_TYPE_FIXED) ? DDI_INTR_ALLOC_STRICT : 6098 DDI_INTR_ALLOC_NORMAL); 6099 intrp->intr_size = navail * sizeof (ddi_intr_handle_t); 6100 intrp->htable = kmem_alloc(intrp->intr_size, KM_SLEEP); 6101 ddi_status = ddi_intr_alloc(dip, intrp->htable, int_type, inum, 6102 navail, &nactual, behavior); 6103 if (ddi_status != DDI_SUCCESS || nactual == 0) { 6104 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6105 " ddi_intr_alloc() failed: %d", 6106 ddi_status)); 6107 kmem_free(intrp->htable, intrp->intr_size); 6108 return (NXGE_ERROR | NXGE_DDI_FAILED); 6109 } 6110 6111 if ((ddi_status = ddi_intr_get_pri(intrp->htable[0], 6112 (uint_t *)&intrp->pri)) != DDI_SUCCESS) { 6113 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6114 " ddi_intr_get_pri() failed: %d", 6115 ddi_status)); 6116 /* Free already allocated interrupts */ 6117 for (y = 0; y < nactual; y++) { 6118 (void) ddi_intr_free(intrp->htable[y]); 6119 } 6120 6121 kmem_free(intrp->htable, intrp->intr_size); 6122 return (NXGE_ERROR | NXGE_DDI_FAILED); 6123 } 6124 6125 nrequired = 0; 6126 switch (nxgep->niu_type) { 6127 default: 6128 status = nxge_ldgv_init(nxgep, &nactual, &nrequired); 6129 break; 6130 6131 case N2_NIU: 6132 status = nxge_ldgv_init_n2(nxgep, &nactual, &nrequired); 6133 break; 6134 } 6135 6136 if (status != NXGE_OK) { 6137 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6138 "nxge_add_intrs_adv_type_fix:nxge_ldgv_init " 6139 "failed: 0x%x", status)); 6140 /* Free already allocated interrupts */ 6141 for (y = 0; y < nactual; y++) { 6142 (void) ddi_intr_free(intrp->htable[y]); 6143 } 6144 6145 kmem_free(intrp->htable, intrp->intr_size); 6146 return (status); 6147 } 6148 6149 ldgp = nxgep->ldgvp->ldgp; 6150 for (x = 0; x < nrequired; x++, ldgp++) { 6151 ldgp->vector = (uint8_t)x; 6152 if (nxgep->niu_type != N2_NIU) { 6153 ldgp->intdata = SID_DATA(ldgp->func, x); 6154 } 6155 6156 arg1 = ldgp->ldvp; 6157 arg2 = nxgep; 6158 if (ldgp->nldvs == 1) { 6159 inthandler = (uint_t *)ldgp->ldvp->ldv_intr_handler; 6160 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6161 "nxge_add_intrs_adv_type_fix: " 6162 "1-1 int handler(%d) ldg %d ldv %d " 6163 "arg1 $%p arg2 $%p\n", 6164 x, ldgp->ldg, ldgp->ldvp->ldv, 6165 arg1, arg2)); 6166 } else if (ldgp->nldvs > 1) { 6167 inthandler = (uint_t *)ldgp->sys_intr_handler; 6168 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6169 "nxge_add_intrs_adv_type_fix: " 6170 "shared ldv %d int handler(%d) ldv %d ldg %d" 6171 "arg1 0x%016llx arg2 0x%016llx\n", 6172 x, ldgp->nldvs, ldgp->ldg, ldgp->ldvp->ldv, 6173 arg1, arg2)); 6174 } 6175 6176 if ((ddi_status = ddi_intr_add_handler(intrp->htable[x], 6177 (ddi_intr_handler_t *)inthandler, arg1, arg2)) 6178 != DDI_SUCCESS) { 6179 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6180 "==> nxge_add_intrs_adv_type_fix: failed #%d " 6181 "status 0x%x", x, ddi_status)); 6182 for (y = 0; y < intrp->intr_added; y++) { 6183 (void) ddi_intr_remove_handler( 6184 intrp->htable[y]); 6185 } 6186 for (y = 0; y < nactual; y++) { 6187 (void) ddi_intr_free(intrp->htable[y]); 6188 } 6189 /* Free already allocated intr */ 6190 kmem_free(intrp->htable, intrp->intr_size); 6191 6192 (void) nxge_ldgv_uninit(nxgep); 6193 6194 return (NXGE_ERROR | NXGE_DDI_FAILED); 6195 } 6196 intrp->intr_added++; 6197 } 6198 6199 intrp->msi_intx_cnt = nactual; 6200 6201 (void) ddi_intr_get_cap(intrp->htable[0], &intrp->intr_cap); 6202 6203 status = nxge_intr_ldgv_init(nxgep); 6204 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_add_intrs_adv_type_fix")); 6205 6206 return (status); 6207 } 6208 6209 static void 6210 nxge_remove_intrs(p_nxge_t nxgep) 6211 { 6212 int i, inum; 6213 p_nxge_intr_t intrp; 6214 6215 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs")); 6216 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6217 if (!intrp->intr_registered) { 6218 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6219 "<== nxge_remove_intrs: interrupts not registered")); 6220 return; 6221 } 6222 6223 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_intrs:advanced")); 6224 6225 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6226 (void) ddi_intr_block_disable(intrp->htable, 6227 intrp->intr_added); 6228 } else { 6229 for (i = 0; i < intrp->intr_added; i++) { 6230 (void) ddi_intr_disable(intrp->htable[i]); 6231 } 6232 } 6233 6234 for (inum = 0; inum < intrp->intr_added; inum++) { 6235 if (intrp->htable[inum]) { 6236 (void) ddi_intr_remove_handler(intrp->htable[inum]); 6237 } 6238 } 6239 6240 for (inum = 0; inum < intrp->msi_intx_cnt; inum++) { 6241 if (intrp->htable[inum]) { 6242 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6243 "nxge_remove_intrs: ddi_intr_free inum %d " 6244 "msi_intx_cnt %d intr_added %d", 6245 inum, 6246 intrp->msi_intx_cnt, 6247 intrp->intr_added)); 6248 6249 (void) ddi_intr_free(intrp->htable[inum]); 6250 } 6251 } 6252 6253 kmem_free(intrp->htable, intrp->intr_size); 6254 intrp->intr_registered = B_FALSE; 6255 intrp->intr_enabled = B_FALSE; 6256 intrp->msi_intx_cnt = 0; 6257 intrp->intr_added = 0; 6258 6259 (void) nxge_ldgv_uninit(nxgep); 6260 6261 (void) ddi_prop_remove(DDI_DEV_T_NONE, nxgep->dip, 6262 "#msix-request"); 6263 6264 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_intrs")); 6265 } 6266 6267 /*ARGSUSED*/ 6268 static void 6269 nxge_remove_soft_intrs(p_nxge_t nxgep) 6270 { 6271 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_remove_soft_intrs")); 6272 if (nxgep->resched_id) { 6273 ddi_remove_softintr(nxgep->resched_id); 6274 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6275 "==> nxge_remove_soft_intrs: removed")); 6276 nxgep->resched_id = NULL; 6277 } 6278 6279 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_remove_soft_intrs")); 6280 } 6281 6282 /*ARGSUSED*/ 6283 static void 6284 nxge_intrs_enable(p_nxge_t nxgep) 6285 { 6286 p_nxge_intr_t intrp; 6287 int i; 6288 int status; 6289 6290 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable")); 6291 6292 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6293 6294 if (!intrp->intr_registered) { 6295 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_intrs_enable: " 6296 "interrupts are not registered")); 6297 return; 6298 } 6299 6300 if (intrp->intr_enabled) { 6301 NXGE_DEBUG_MSG((nxgep, INT_CTL, 6302 "<== nxge_intrs_enable: already enabled")); 6303 return; 6304 } 6305 6306 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6307 status = ddi_intr_block_enable(intrp->htable, 6308 intrp->intr_added); 6309 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6310 "block enable - status 0x%x total inums #%d\n", 6311 status, intrp->intr_added)); 6312 } else { 6313 for (i = 0; i < intrp->intr_added; i++) { 6314 status = ddi_intr_enable(intrp->htable[i]); 6315 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_enable " 6316 "ddi_intr_enable:enable - status 0x%x " 6317 "total inums %d enable inum #%d\n", 6318 status, intrp->intr_added, i)); 6319 if (status == DDI_SUCCESS) { 6320 intrp->intr_enabled = B_TRUE; 6321 } 6322 } 6323 } 6324 6325 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_enable")); 6326 } 6327 6328 /*ARGSUSED*/ 6329 static void 6330 nxge_intrs_disable(p_nxge_t nxgep) 6331 { 6332 p_nxge_intr_t intrp; 6333 int i; 6334 6335 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intrs_disable")); 6336 6337 intrp = (p_nxge_intr_t)&nxgep->nxge_intr_type; 6338 6339 if (!intrp->intr_registered) { 6340 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable: " 6341 "interrupts are not registered")); 6342 return; 6343 } 6344 6345 if (intrp->intr_cap & DDI_INTR_FLAG_BLOCK) { 6346 (void) ddi_intr_block_disable(intrp->htable, 6347 intrp->intr_added); 6348 } else { 6349 for (i = 0; i < intrp->intr_added; i++) { 6350 (void) ddi_intr_disable(intrp->htable[i]); 6351 } 6352 } 6353 6354 intrp->intr_enabled = B_FALSE; 6355 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intrs_disable")); 6356 } 6357 6358 static nxge_status_t 6359 nxge_mac_register(p_nxge_t nxgep) 6360 { 6361 mac_register_t *macp; 6362 int status; 6363 6364 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_mac_register")); 6365 6366 if ((macp = mac_alloc(MAC_VERSION)) == NULL) 6367 return (NXGE_ERROR); 6368 6369 macp->m_type_ident = MAC_PLUGIN_IDENT_ETHER; 6370 macp->m_driver = nxgep; 6371 macp->m_dip = nxgep->dip; 6372 macp->m_src_addr = nxgep->ouraddr.ether_addr_octet; 6373 macp->m_callbacks = &nxge_m_callbacks; 6374 macp->m_min_sdu = 0; 6375 nxgep->mac.default_mtu = nxgep->mac.maxframesize - 6376 NXGE_EHEADER_VLAN_CRC; 6377 macp->m_max_sdu = nxgep->mac.default_mtu; 6378 macp->m_margin = VLAN_TAGSZ; 6379 macp->m_priv_props = nxge_priv_props; 6380 macp->m_priv_prop_count = NXGE_MAX_PRIV_PROPS; 6381 6382 NXGE_DEBUG_MSG((nxgep, MAC_CTL, 6383 "==> nxge_mac_register: instance %d " 6384 "max_sdu %d margin %d maxframe %d (header %d)", 6385 nxgep->instance, 6386 macp->m_max_sdu, macp->m_margin, 6387 nxgep->mac.maxframesize, 6388 NXGE_EHEADER_VLAN_CRC)); 6389 6390 status = mac_register(macp, &nxgep->mach); 6391 mac_free(macp); 6392 6393 if (status != 0) { 6394 cmn_err(CE_WARN, 6395 "!nxge_mac_register failed (status %d instance %d)", 6396 status, nxgep->instance); 6397 return (NXGE_ERROR); 6398 } 6399 6400 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_mac_register success " 6401 "(instance %d)", nxgep->instance)); 6402 6403 return (NXGE_OK); 6404 } 6405 6406 void 6407 nxge_err_inject(p_nxge_t nxgep, queue_t *wq, mblk_t *mp) 6408 { 6409 ssize_t size; 6410 mblk_t *nmp; 6411 uint8_t blk_id; 6412 uint8_t chan; 6413 uint32_t err_id; 6414 err_inject_t *eip; 6415 6416 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_err_inject")); 6417 6418 size = 1024; 6419 nmp = mp->b_cont; 6420 eip = (err_inject_t *)nmp->b_rptr; 6421 blk_id = eip->blk_id; 6422 err_id = eip->err_id; 6423 chan = eip->chan; 6424 cmn_err(CE_NOTE, "!blk_id = 0x%x\n", blk_id); 6425 cmn_err(CE_NOTE, "!err_id = 0x%x\n", err_id); 6426 cmn_err(CE_NOTE, "!chan = 0x%x\n", chan); 6427 switch (blk_id) { 6428 case MAC_BLK_ID: 6429 break; 6430 case TXMAC_BLK_ID: 6431 break; 6432 case RXMAC_BLK_ID: 6433 break; 6434 case MIF_BLK_ID: 6435 break; 6436 case IPP_BLK_ID: 6437 nxge_ipp_inject_err(nxgep, err_id); 6438 break; 6439 case TXC_BLK_ID: 6440 nxge_txc_inject_err(nxgep, err_id); 6441 break; 6442 case TXDMA_BLK_ID: 6443 nxge_txdma_inject_err(nxgep, err_id, chan); 6444 break; 6445 case RXDMA_BLK_ID: 6446 nxge_rxdma_inject_err(nxgep, err_id, chan); 6447 break; 6448 case ZCP_BLK_ID: 6449 nxge_zcp_inject_err(nxgep, err_id); 6450 break; 6451 case ESPC_BLK_ID: 6452 break; 6453 case FFLP_BLK_ID: 6454 break; 6455 case PHY_BLK_ID: 6456 break; 6457 case ETHER_SERDES_BLK_ID: 6458 break; 6459 case PCIE_SERDES_BLK_ID: 6460 break; 6461 case VIR_BLK_ID: 6462 break; 6463 } 6464 6465 nmp->b_wptr = nmp->b_rptr + size; 6466 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_err_inject")); 6467 6468 miocack(wq, mp, (int)size, 0); 6469 } 6470 6471 static int 6472 nxge_init_common_dev(p_nxge_t nxgep) 6473 { 6474 p_nxge_hw_list_t hw_p; 6475 dev_info_t *p_dip; 6476 6477 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_init_common_device")); 6478 6479 p_dip = nxgep->p_dip; 6480 MUTEX_ENTER(&nxge_common_lock); 6481 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6482 "==> nxge_init_common_dev:func # %d", 6483 nxgep->function_num)); 6484 /* 6485 * Loop through existing per neptune hardware list. 6486 */ 6487 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6488 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6489 "==> nxge_init_common_device:func # %d " 6490 "hw_p $%p parent dip $%p", 6491 nxgep->function_num, 6492 hw_p, 6493 p_dip)); 6494 if (hw_p->parent_devp == p_dip) { 6495 nxgep->nxge_hw_p = hw_p; 6496 hw_p->ndevs++; 6497 hw_p->nxge_p[nxgep->function_num] = nxgep; 6498 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6499 "==> nxge_init_common_device:func # %d " 6500 "hw_p $%p parent dip $%p " 6501 "ndevs %d (found)", 6502 nxgep->function_num, 6503 hw_p, 6504 p_dip, 6505 hw_p->ndevs)); 6506 break; 6507 } 6508 } 6509 6510 if (hw_p == NULL) { 6511 6512 char **prop_val; 6513 uint_t prop_len; 6514 int i; 6515 6516 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6517 "==> nxge_init_common_device:func # %d " 6518 "parent dip $%p (new)", 6519 nxgep->function_num, 6520 p_dip)); 6521 hw_p = kmem_zalloc(sizeof (nxge_hw_list_t), KM_SLEEP); 6522 hw_p->parent_devp = p_dip; 6523 hw_p->magic = NXGE_NEPTUNE_MAGIC; 6524 nxgep->nxge_hw_p = hw_p; 6525 hw_p->ndevs++; 6526 hw_p->nxge_p[nxgep->function_num] = nxgep; 6527 hw_p->next = nxge_hw_list; 6528 if (nxgep->niu_type == N2_NIU) { 6529 hw_p->niu_type = N2_NIU; 6530 hw_p->platform_type = P_NEPTUNE_NIU; 6531 } else { 6532 hw_p->niu_type = NIU_TYPE_NONE; 6533 hw_p->platform_type = P_NEPTUNE_NONE; 6534 } 6535 6536 MUTEX_INIT(&hw_p->nxge_cfg_lock, NULL, MUTEX_DRIVER, NULL); 6537 MUTEX_INIT(&hw_p->nxge_tcam_lock, NULL, MUTEX_DRIVER, NULL); 6538 MUTEX_INIT(&hw_p->nxge_vlan_lock, NULL, MUTEX_DRIVER, NULL); 6539 MUTEX_INIT(&hw_p->nxge_mdio_lock, NULL, MUTEX_DRIVER, NULL); 6540 6541 nxge_hw_list = hw_p; 6542 6543 if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, nxgep->dip, 0, 6544 "compatible", &prop_val, &prop_len) == DDI_PROP_SUCCESS) { 6545 for (i = 0; i < prop_len; i++) { 6546 if ((strcmp((caddr_t)prop_val[i], 6547 NXGE_ROCK_COMPATIBLE) == 0)) { 6548 hw_p->platform_type = P_NEPTUNE_ROCK; 6549 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6550 "ROCK hw_p->platform_type %d", 6551 hw_p->platform_type)); 6552 break; 6553 } 6554 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6555 "nxge_init_common_dev: read compatible" 6556 " property[%d] val[%s]", 6557 i, (caddr_t)prop_val[i])); 6558 } 6559 } 6560 6561 ddi_prop_free(prop_val); 6562 6563 (void) nxge_scan_ports_phy(nxgep, nxge_hw_list); 6564 } 6565 6566 MUTEX_EXIT(&nxge_common_lock); 6567 6568 nxgep->platform_type = hw_p->platform_type; 6569 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxgep->platform_type %d", 6570 nxgep->platform_type)); 6571 if (nxgep->niu_type != N2_NIU) { 6572 nxgep->niu_type = hw_p->niu_type; 6573 } 6574 6575 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6576 "==> nxge_init_common_device (nxge_hw_list) $%p", 6577 nxge_hw_list)); 6578 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<== nxge_init_common_device")); 6579 6580 return (NXGE_OK); 6581 } 6582 6583 static void 6584 nxge_uninit_common_dev(p_nxge_t nxgep) 6585 { 6586 p_nxge_hw_list_t hw_p, h_hw_p; 6587 p_nxge_dma_pt_cfg_t p_dma_cfgp; 6588 p_nxge_hw_pt_cfg_t p_cfgp; 6589 dev_info_t *p_dip; 6590 6591 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==> nxge_uninit_common_device")); 6592 if (nxgep->nxge_hw_p == NULL) { 6593 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6594 "<== nxge_uninit_common_device (no common)")); 6595 return; 6596 } 6597 6598 MUTEX_ENTER(&nxge_common_lock); 6599 h_hw_p = nxge_hw_list; 6600 for (hw_p = nxge_hw_list; hw_p; hw_p = hw_p->next) { 6601 p_dip = hw_p->parent_devp; 6602 if (nxgep->nxge_hw_p == hw_p && 6603 p_dip == nxgep->p_dip && 6604 nxgep->nxge_hw_p->magic == NXGE_NEPTUNE_MAGIC && 6605 hw_p->magic == NXGE_NEPTUNE_MAGIC) { 6606 6607 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6608 "==> nxge_uninit_common_device:func # %d " 6609 "hw_p $%p parent dip $%p " 6610 "ndevs %d (found)", 6611 nxgep->function_num, 6612 hw_p, 6613 p_dip, 6614 hw_p->ndevs)); 6615 6616 /* 6617 * Release the RDC table, a shared resoruce 6618 * of the nxge hardware. The RDC table was 6619 * assigned to this instance of nxge in 6620 * nxge_use_cfg_dma_config(). 6621 */ 6622 if (!isLDOMguest(nxgep)) { 6623 p_dma_cfgp = 6624 (p_nxge_dma_pt_cfg_t)&nxgep->pt_config; 6625 p_cfgp = 6626 (p_nxge_hw_pt_cfg_t)&p_dma_cfgp->hw_config; 6627 (void) nxge_fzc_rdc_tbl_unbind(nxgep, 6628 p_cfgp->def_mac_rxdma_grpid); 6629 6630 /* Cleanup any outstanding groups. */ 6631 nxge_grp_cleanup(nxgep); 6632 } 6633 6634 if (hw_p->ndevs) { 6635 hw_p->ndevs--; 6636 } 6637 hw_p->nxge_p[nxgep->function_num] = NULL; 6638 if (!hw_p->ndevs) { 6639 MUTEX_DESTROY(&hw_p->nxge_vlan_lock); 6640 MUTEX_DESTROY(&hw_p->nxge_tcam_lock); 6641 MUTEX_DESTROY(&hw_p->nxge_cfg_lock); 6642 MUTEX_DESTROY(&hw_p->nxge_mdio_lock); 6643 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6644 "==> nxge_uninit_common_device: " 6645 "func # %d " 6646 "hw_p $%p parent dip $%p " 6647 "ndevs %d (last)", 6648 nxgep->function_num, 6649 hw_p, 6650 p_dip, 6651 hw_p->ndevs)); 6652 6653 nxge_hio_uninit(nxgep); 6654 6655 if (hw_p == nxge_hw_list) { 6656 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6657 "==> nxge_uninit_common_device:" 6658 "remove head func # %d " 6659 "hw_p $%p parent dip $%p " 6660 "ndevs %d (head)", 6661 nxgep->function_num, 6662 hw_p, 6663 p_dip, 6664 hw_p->ndevs)); 6665 nxge_hw_list = hw_p->next; 6666 } else { 6667 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6668 "==> nxge_uninit_common_device:" 6669 "remove middle func # %d " 6670 "hw_p $%p parent dip $%p " 6671 "ndevs %d (middle)", 6672 nxgep->function_num, 6673 hw_p, 6674 p_dip, 6675 hw_p->ndevs)); 6676 h_hw_p->next = hw_p->next; 6677 } 6678 6679 nxgep->nxge_hw_p = NULL; 6680 KMEM_FREE(hw_p, sizeof (nxge_hw_list_t)); 6681 } 6682 break; 6683 } else { 6684 h_hw_p = hw_p; 6685 } 6686 } 6687 6688 MUTEX_EXIT(&nxge_common_lock); 6689 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6690 "==> nxge_uninit_common_device (nxge_hw_list) $%p", 6691 nxge_hw_list)); 6692 6693 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<= nxge_uninit_common_device")); 6694 } 6695 6696 /* 6697 * Determines the number of ports from the niu_type or the platform type. 6698 * Returns the number of ports, or returns zero on failure. 6699 */ 6700 6701 int 6702 nxge_get_nports(p_nxge_t nxgep) 6703 { 6704 int nports = 0; 6705 6706 switch (nxgep->niu_type) { 6707 case N2_NIU: 6708 case NEPTUNE_2_10GF: 6709 nports = 2; 6710 break; 6711 case NEPTUNE_4_1GC: 6712 case NEPTUNE_2_10GF_2_1GC: 6713 case NEPTUNE_1_10GF_3_1GC: 6714 case NEPTUNE_1_1GC_1_10GF_2_1GC: 6715 case NEPTUNE_2_10GF_2_1GRF: 6716 nports = 4; 6717 break; 6718 default: 6719 switch (nxgep->platform_type) { 6720 case P_NEPTUNE_NIU: 6721 case P_NEPTUNE_ATLAS_2PORT: 6722 nports = 2; 6723 break; 6724 case P_NEPTUNE_ATLAS_4PORT: 6725 case P_NEPTUNE_MARAMBA_P0: 6726 case P_NEPTUNE_MARAMBA_P1: 6727 case P_NEPTUNE_ROCK: 6728 case P_NEPTUNE_ALONSO: 6729 nports = 4; 6730 break; 6731 default: 6732 break; 6733 } 6734 break; 6735 } 6736 6737 return (nports); 6738 } 6739 6740 /* 6741 * The following two functions are to support 6742 * PSARC/2007/453 MSI-X interrupt limit override. 6743 */ 6744 static int 6745 nxge_create_msi_property(p_nxge_t nxgep) 6746 { 6747 int nmsi; 6748 extern int ncpus; 6749 6750 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "==>nxge_create_msi_property")); 6751 6752 switch (nxgep->mac.portmode) { 6753 case PORT_10G_COPPER: 6754 case PORT_10G_FIBER: 6755 case PORT_10G_TN1010: 6756 (void) ddi_prop_create(DDI_DEV_T_NONE, nxgep->dip, 6757 DDI_PROP_CANSLEEP, "#msix-request", NULL, 0); 6758 /* 6759 * The maximum MSI-X requested will be 8. 6760 * If the # of CPUs is less than 8, we will reqeust 6761 * # MSI-X based on the # of CPUs. 6762 */ 6763 if (ncpus >= NXGE_MSIX_REQUEST_10G) { 6764 nmsi = NXGE_MSIX_REQUEST_10G; 6765 } else { 6766 nmsi = ncpus; 6767 } 6768 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6769 "==>nxge_create_msi_property(10G): exists 0x%x (nmsi %d)", 6770 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6771 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6772 break; 6773 6774 default: 6775 nmsi = NXGE_MSIX_REQUEST_1G; 6776 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 6777 "==>nxge_create_msi_property(1G): exists 0x%x (nmsi %d)", 6778 ddi_prop_exists(DDI_DEV_T_NONE, nxgep->dip, 6779 DDI_PROP_CANSLEEP, "#msix-request"), nmsi)); 6780 break; 6781 } 6782 6783 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "<==nxge_create_msi_property")); 6784 return (nmsi); 6785 } 6786 6787 /* ARGSUSED */ 6788 static int 6789 nxge_get_def_val(nxge_t *nxgep, mac_prop_id_t pr_num, uint_t pr_valsize, 6790 void *pr_val) 6791 { 6792 int err = 0; 6793 link_flowctrl_t fl; 6794 6795 switch (pr_num) { 6796 case MAC_PROP_AUTONEG: 6797 *(uint8_t *)pr_val = 1; 6798 break; 6799 case MAC_PROP_FLOWCTRL: 6800 if (pr_valsize < sizeof (link_flowctrl_t)) 6801 return (EINVAL); 6802 fl = LINK_FLOWCTRL_RX; 6803 bcopy(&fl, pr_val, sizeof (fl)); 6804 break; 6805 case MAC_PROP_ADV_1000FDX_CAP: 6806 case MAC_PROP_EN_1000FDX_CAP: 6807 *(uint8_t *)pr_val = 1; 6808 break; 6809 case MAC_PROP_ADV_100FDX_CAP: 6810 case MAC_PROP_EN_100FDX_CAP: 6811 *(uint8_t *)pr_val = 1; 6812 break; 6813 default: 6814 err = ENOTSUP; 6815 break; 6816 } 6817 return (err); 6818 } 6819 6820 6821 /* 6822 * The following is a software around for the Neptune hardware's 6823 * interrupt bugs; The Neptune hardware may generate spurious interrupts when 6824 * an interrupr handler is removed. 6825 */ 6826 #define NXGE_PCI_PORT_LOGIC_OFFSET 0x98 6827 #define NXGE_PIM_RESET (1ULL << 29) 6828 #define NXGE_GLU_RESET (1ULL << 30) 6829 #define NXGE_NIU_RESET (1ULL << 31) 6830 #define NXGE_PCI_RESET_ALL (NXGE_PIM_RESET | \ 6831 NXGE_GLU_RESET | \ 6832 NXGE_NIU_RESET) 6833 6834 #define NXGE_WAIT_QUITE_TIME 200000 6835 #define NXGE_WAIT_QUITE_RETRY 40 6836 #define NXGE_PCI_RESET_WAIT 1000000 /* one second */ 6837 6838 static void 6839 nxge_niu_peu_reset(p_nxge_t nxgep) 6840 { 6841 uint32_t rvalue; 6842 p_nxge_hw_list_t hw_p; 6843 p_nxge_t fnxgep; 6844 int i, j; 6845 6846 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "==> nxge_niu_peu_reset")); 6847 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 6848 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6849 "==> nxge_niu_peu_reset: NULL hardware pointer")); 6850 return; 6851 } 6852 6853 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6854 "==> nxge_niu_peu_reset: flags 0x%x link timer id %d timer id %d", 6855 hw_p->flags, nxgep->nxge_link_poll_timerid, 6856 nxgep->nxge_timerid)); 6857 6858 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 6859 /* 6860 * Make sure other instances from the same hardware 6861 * stop sending PIO and in quiescent state. 6862 */ 6863 for (i = 0; i < NXGE_MAX_PORTS; i++) { 6864 fnxgep = hw_p->nxge_p[i]; 6865 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6866 "==> nxge_niu_peu_reset: checking entry %d " 6867 "nxgep $%p", i, fnxgep)); 6868 #ifdef NXGE_DEBUG 6869 if (fnxgep) { 6870 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6871 "==> nxge_niu_peu_reset: entry %d (function %d) " 6872 "link timer id %d hw timer id %d", 6873 i, fnxgep->function_num, 6874 fnxgep->nxge_link_poll_timerid, 6875 fnxgep->nxge_timerid)); 6876 } 6877 #endif 6878 if (fnxgep && fnxgep != nxgep && 6879 (fnxgep->nxge_timerid || fnxgep->nxge_link_poll_timerid)) { 6880 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6881 "==> nxge_niu_peu_reset: checking $%p " 6882 "(function %d) timer ids", 6883 fnxgep, fnxgep->function_num)); 6884 for (j = 0; j < NXGE_WAIT_QUITE_RETRY; j++) { 6885 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6886 "==> nxge_niu_peu_reset: waiting")); 6887 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6888 if (!fnxgep->nxge_timerid && 6889 !fnxgep->nxge_link_poll_timerid) { 6890 break; 6891 } 6892 } 6893 NXGE_DELAY(NXGE_WAIT_QUITE_TIME); 6894 if (fnxgep->nxge_timerid || 6895 fnxgep->nxge_link_poll_timerid) { 6896 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6897 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 6898 "<== nxge_niu_peu_reset: cannot reset " 6899 "hardware (devices are still in use)")); 6900 return; 6901 } 6902 } 6903 } 6904 6905 if ((hw_p->flags & COMMON_RESET_NIU_PCI) != COMMON_RESET_NIU_PCI) { 6906 hw_p->flags |= COMMON_RESET_NIU_PCI; 6907 rvalue = pci_config_get32(nxgep->dev_regs->nxge_pciregh, 6908 NXGE_PCI_PORT_LOGIC_OFFSET); 6909 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6910 "nxge_niu_peu_reset: read offset 0x%x (%d) " 6911 "(data 0x%x)", 6912 NXGE_PCI_PORT_LOGIC_OFFSET, 6913 NXGE_PCI_PORT_LOGIC_OFFSET, 6914 rvalue)); 6915 6916 rvalue |= NXGE_PCI_RESET_ALL; 6917 pci_config_put32(nxgep->dev_regs->nxge_pciregh, 6918 NXGE_PCI_PORT_LOGIC_OFFSET, rvalue); 6919 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 6920 "nxge_niu_peu_reset: RESETTING NIU: write NIU reset 0x%x", 6921 rvalue)); 6922 6923 NXGE_DELAY(NXGE_PCI_RESET_WAIT); 6924 } 6925 6926 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 6927 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, "<== nxge_niu_peu_reset")); 6928 } 6929 6930 static void 6931 nxge_set_pci_replay_timeout(p_nxge_t nxgep) 6932 { 6933 p_dev_regs_t dev_regs; 6934 uint32_t value; 6935 6936 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_pci_replay_timeout")); 6937 6938 if (!nxge_set_replay_timer) { 6939 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6940 "==> nxge_set_pci_replay_timeout: will not change " 6941 "the timeout")); 6942 return; 6943 } 6944 6945 dev_regs = nxgep->dev_regs; 6946 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6947 "==> nxge_set_pci_replay_timeout: dev_regs 0x%p pcireg 0x%p", 6948 dev_regs, dev_regs->nxge_pciregh)); 6949 6950 if (dev_regs == NULL || (dev_regs->nxge_pciregh == NULL)) { 6951 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6952 "==> nxge_set_pci_replay_timeout: NULL dev_regs $%p or " 6953 "no PCI handle", 6954 dev_regs)); 6955 return; 6956 } 6957 value = (pci_config_get32(dev_regs->nxge_pciregh, 6958 PCI_REPLAY_TIMEOUT_CFG_OFFSET) | 6959 (nxge_replay_timeout << PCI_REPLAY_TIMEOUT_SHIFT)); 6960 6961 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6962 "nxge_set_pci_replay_timeout: replay timeout value before set 0x%x " 6963 "(timeout value to set 0x%x at offset 0x%x) value 0x%x", 6964 pci_config_get32(dev_regs->nxge_pciregh, 6965 PCI_REPLAY_TIMEOUT_CFG_OFFSET), nxge_replay_timeout, 6966 PCI_REPLAY_TIMEOUT_CFG_OFFSET, value)); 6967 6968 pci_config_put32(dev_regs->nxge_pciregh, PCI_REPLAY_TIMEOUT_CFG_OFFSET, 6969 value); 6970 6971 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 6972 "nxge_set_pci_replay_timeout: replay timeout value after set 0x%x", 6973 pci_config_get32(dev_regs->nxge_pciregh, 6974 PCI_REPLAY_TIMEOUT_CFG_OFFSET))); 6975 6976 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_pci_replay_timeout")); 6977 } 6978 6979 /* 6980 * quiesce(9E) entry point. 6981 * 6982 * This function is called when the system is single-threaded at high 6983 * PIL with preemption disabled. Therefore, this function must not be 6984 * blocked. 6985 * 6986 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 6987 * DDI_FAILURE indicates an error condition and should almost never happen. 6988 */ 6989 static int 6990 nxge_quiesce(dev_info_t *dip) 6991 { 6992 int instance = ddi_get_instance(dip); 6993 p_nxge_t nxgep = (p_nxge_t)ddi_get_soft_state(nxge_list, instance); 6994 6995 if (nxgep == NULL) 6996 return (DDI_FAILURE); 6997 6998 /* Turn off debugging */ 6999 nxge_debug_level = NO_DEBUG; 7000 nxgep->nxge_debug_level = NO_DEBUG; 7001 npi_debug_level = NO_DEBUG; 7002 7003 /* 7004 * Stop link monitor only when linkchkmod is interrupt based 7005 */ 7006 if (nxgep->mac.linkchkmode == LINKCHK_INTR) { 7007 (void) nxge_link_monitor(nxgep, LINK_MONITOR_STOP); 7008 } 7009 7010 (void) nxge_intr_hw_disable(nxgep); 7011 7012 /* 7013 * Reset the receive MAC side. 7014 */ 7015 (void) nxge_rx_mac_disable(nxgep); 7016 7017 /* Disable and soft reset the IPP */ 7018 if (!isLDOMguest(nxgep)) 7019 (void) nxge_ipp_disable(nxgep); 7020 7021 /* 7022 * Reset the transmit/receive DMA side. 7023 */ 7024 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 7025 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 7026 7027 /* 7028 * Reset the transmit MAC side. 7029 */ 7030 (void) nxge_tx_mac_disable(nxgep); 7031 7032 return (DDI_SUCCESS); 7033 } 7034