1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/nxge/nxge_impl.h> 29 30 /* 31 * Tunable Receive Completion Ring Configuration B parameters. 32 */ 33 uint16_t nxge_rx_pkt_thres; /* 16 bits */ 34 uint8_t nxge_rx_pkt_timeout; /* 6 bits based on DMA clock divider */ 35 36 lb_property_t lb_normal = {normal, "normal", nxge_lb_normal}; 37 lb_property_t lb_external10g = {external, "external10g", nxge_lb_ext10g}; 38 lb_property_t lb_external1000 = {external, "external1000", nxge_lb_ext1000}; 39 lb_property_t lb_external100 = {external, "external100", nxge_lb_ext100}; 40 lb_property_t lb_external10 = {external, "external10", nxge_lb_ext10}; 41 lb_property_t lb_phy10g = {internal, "phy10g", nxge_lb_phy10g}; 42 lb_property_t lb_phy1000 = {internal, "phy1000", nxge_lb_phy1000}; 43 lb_property_t lb_phy = {internal, "phy", nxge_lb_phy}; 44 lb_property_t lb_serdes10g = {internal, "serdes10g", nxge_lb_serdes10g}; 45 lb_property_t lb_serdes1000 = {internal, "serdes", nxge_lb_serdes1000}; 46 lb_property_t lb_mac10g = {internal, "mac10g", nxge_lb_mac10g}; 47 lb_property_t lb_mac1000 = {internal, "mac1000", nxge_lb_mac1000}; 48 lb_property_t lb_mac = {internal, "mac10/100", nxge_lb_mac}; 49 50 uint32_t nxge_lb_dbg = 1; 51 void nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp); 52 void nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp); 53 static nxge_status_t nxge_check_xaui_xfp(p_nxge_t nxgep); 54 55 extern uint32_t nxge_rx_mode; 56 extern uint32_t nxge_jumbo_mtu; 57 extern boolean_t nxge_jumbo_enable; 58 59 static void 60 nxge_rtrace_ioctl(p_nxge_t, queue_t *, mblk_t *, struct iocblk *); 61 62 /* ARGSUSED */ 63 nxge_status_t 64 nxge_global_reset(p_nxge_t nxgep) 65 { 66 nxge_status_t status = NXGE_OK; 67 68 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_global_reset")); 69 70 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 71 return (status); 72 (void) nxge_intr_hw_disable(nxgep); 73 74 if ((nxgep->suspended) || 75 ((nxgep->statsp->port_stats.lb_mode == 76 nxge_lb_phy1000) || 77 (nxgep->statsp->port_stats.lb_mode == 78 nxge_lb_phy10g) || 79 (nxgep->statsp->port_stats.lb_mode == 80 nxge_lb_serdes1000) || 81 (nxgep->statsp->port_stats.lb_mode == 82 nxge_lb_serdes10g))) { 83 if ((status = nxge_link_init(nxgep)) != NXGE_OK) 84 return (status); 85 } 86 87 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_START)) != NXGE_OK) 88 return (status); 89 if ((status = nxge_mac_init(nxgep)) != NXGE_OK) 90 return (status); 91 (void) nxge_intr_hw_enable(nxgep); 92 93 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_global_reset")); 94 return (status); 95 } 96 97 /* ARGSUSED */ 98 void 99 nxge_hw_id_init(p_nxge_t nxgep) 100 { 101 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_id_init")); 102 /* 103 * Set up initial hardware parameters required such as mac mtu size. 104 */ 105 nxgep->mac.is_jumbo = B_FALSE; 106 /* 107 * Set the maxframe size to 1522 (1518 + 4) to account for 108 * VLAN tagged packets. 109 */ 110 nxgep->mac.minframesize = NXGE_MIN_MAC_FRAMESIZE; /* 64 */ 111 nxgep->mac.maxframesize = NXGE_MAX_MAC_FRAMESIZE; /* 1522 */ 112 if (nxgep->param_arr[param_accept_jumbo].value || nxge_jumbo_enable) { 113 nxgep->mac.maxframesize = (uint16_t)nxge_jumbo_mtu; 114 nxgep->mac.is_jumbo = B_TRUE; 115 } 116 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 117 "==> nxge_hw_id_init: maxframesize %d", 118 nxgep->mac.maxframesize)); 119 120 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_id_init")); 121 } 122 123 /* ARGSUSED */ 124 void 125 nxge_hw_init_niu_common(p_nxge_t nxgep) 126 { 127 p_nxge_hw_list_t hw_p; 128 129 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_init_niu_common")); 130 131 if ((hw_p = nxgep->nxge_hw_p) == NULL) { 132 return; 133 } 134 MUTEX_ENTER(&hw_p->nxge_cfg_lock); 135 if (hw_p->flags & COMMON_INIT_DONE) { 136 NXGE_DEBUG_MSG((nxgep, MOD_CTL, 137 "nxge_hw_init_niu_common" 138 " already done for dip $%p function %d exiting", 139 hw_p->parent_devp, nxgep->function_num)); 140 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 141 return; 142 } 143 144 hw_p->flags = COMMON_INIT_START; 145 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 146 " Started for device id %x with function %d", 147 hw_p->parent_devp, nxgep->function_num)); 148 149 /* per neptune common block init */ 150 (void) nxge_fflp_hw_reset(nxgep); 151 152 hw_p->flags = COMMON_INIT_DONE; 153 MUTEX_EXIT(&hw_p->nxge_cfg_lock); 154 155 NXGE_DEBUG_MSG((nxgep, MOD_CTL, "nxge_hw_init_niu_common" 156 " Done for device id %x with function %d", 157 hw_p->parent_devp, nxgep->function_num)); 158 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_init_niu_common")); 159 } 160 161 /* ARGSUSED */ 162 uint_t 163 nxge_intr(void *arg1, void *arg2) 164 { 165 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 166 p_nxge_t nxgep = (p_nxge_t)arg2; 167 uint_t serviced = DDI_INTR_UNCLAIMED; 168 uint8_t ldv; 169 npi_handle_t handle; 170 p_nxge_ldgv_t ldgvp; 171 p_nxge_ldg_t ldgp, t_ldgp; 172 p_nxge_ldv_t t_ldvp; 173 uint64_t vector0 = 0, vector1 = 0, vector2 = 0; 174 int i, j, nldvs, nintrs = 1; 175 npi_status_t rs = NPI_SUCCESS; 176 177 /* DDI interface returns second arg as NULL (n2 niumx driver) !!! */ 178 if (arg2 == NULL || (void *) ldvp->nxgep != arg2) { 179 nxgep = ldvp->nxgep; 180 } 181 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr")); 182 183 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 184 NXGE_ERROR_MSG((nxgep, INT_CTL, 185 "<== nxge_intr: not initialized 0x%x", serviced)); 186 return (serviced); 187 } 188 189 ldgvp = nxgep->ldgvp; 190 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: ldgvp $%p", ldgvp)); 191 if (ldvp == NULL && ldgvp) { 192 t_ldvp = ldvp = ldgvp->ldvp; 193 } 194 if (ldvp) { 195 ldgp = t_ldgp = ldvp->ldgp; 196 } 197 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 198 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 199 if (ldgvp == NULL || ldvp == NULL || ldgp == NULL) { 200 NXGE_ERROR_MSG((nxgep, INT_CTL, "==> nxge_intr: " 201 "ldgvp $%p ldvp $%p ldgp $%p", ldgvp, ldvp, ldgp)); 202 NXGE_ERROR_MSG((nxgep, INT_CTL, "<== nxge_intr: not ready")); 203 return (DDI_INTR_UNCLAIMED); 204 } 205 /* 206 * This interrupt handler will have to go through all the logical 207 * devices to find out which logical device interrupts us and then call 208 * its handler to process the events. 209 */ 210 handle = NXGE_DEV_NPI_HANDLE(nxgep); 211 t_ldgp = ldgp; 212 t_ldvp = ldgp->ldvp; 213 214 nldvs = ldgp->nldvs; 215 216 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: #ldvs %d #intrs %d", 217 nldvs, ldgvp->ldg_intrs)); 218 219 serviced = DDI_INTR_CLAIMED; 220 for (i = 0; i < nintrs; i++, t_ldgp++) { 221 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr(%d): #ldvs %d " 222 " #intrs %d", i, nldvs, nintrs)); 223 /* Get this group's flag bits. */ 224 t_ldgp->interrupted = B_FALSE; 225 rs = npi_ldsv_ldfs_get(handle, t_ldgp->ldg, 226 &vector0, &vector1, &vector2); 227 if (rs) { 228 continue; 229 } 230 if (!vector0 && !vector1 && !vector2) { 231 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 232 "no interrupts on group %d", t_ldgp->ldg)); 233 continue; 234 } 235 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: " 236 "vector0 0x%llx vector1 0x%llx vector2 0x%llx", 237 vector0, vector1, vector2)); 238 t_ldgp->interrupted = B_TRUE; 239 nldvs = t_ldgp->nldvs; 240 for (j = 0; j < nldvs; j++, t_ldvp++) { 241 /* 242 * Call device's handler if flag bits are on. 243 */ 244 ldv = t_ldvp->ldv; 245 if (((ldv < NXGE_MAC_LD_START) && 246 (LDV_ON(ldv, vector0) | 247 (LDV_ON(ldv, vector1)))) || 248 (ldv >= NXGE_MAC_LD_START && 249 ((LDV2_ON_1(ldv, vector2)) || 250 (LDV2_ON_2(ldv, vector2))))) { 251 (void) (t_ldvp->ldv_intr_handler)( 252 (caddr_t)t_ldvp, arg2); 253 NXGE_DEBUG_MSG((nxgep, INT_CTL, 254 "==> nxge_intr: " 255 "calling device %d #ldvs %d #intrs %d", 256 j, nldvs, nintrs)); 257 } 258 } 259 } 260 261 t_ldgp = ldgp; 262 for (i = 0; i < nintrs; i++, t_ldgp++) { 263 /* rearm group interrupts */ 264 if (t_ldgp->interrupted) { 265 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr: arm " 266 "group %d", t_ldgp->ldg)); 267 (void) npi_intr_ldg_mgmt_set(handle, t_ldgp->ldg, 268 t_ldgp->arm, t_ldgp->ldg_timer); 269 } 270 } 271 272 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr: serviced 0x%x", 273 serviced)); 274 return (serviced); 275 } 276 277 278 /* 279 * XFP Related Status Register Values Under 3 Different Conditions 280 * 281 * -------------+-------------------------+------------------------- 282 * | Intel XFP and Avago | Sun XFP 283 * -------------+---------+---------------+---------+--------------- 284 * | STATUS0 | TX_ALARM_STAT | STATUS0 | TX_ALARM_STAT 285 * -------------+---------+---------------+---------+--------------- 286 * No XFP | 0x639C | 0x40 | 0x639C | 0x40 287 * -------------+---------+---------------+---------+--------------- 288 * XFP,linkdown | 0x43BC | 0x40 | 0x639C | 0x40 289 * -------------+---------+---------------+---------+--------------- 290 * XFP,linkup | 0x03FC | 0x0 | 0x03FC | 0x0 291 * -------------+---------+---------------+---------+--------------- 292 * Note: 293 * STATUS0 = BCM8704_USER_ANALOG_STATUS0_REG 294 * TX_ALARM_STAT = BCM8704_USER_TX_ALARM_STATUS_REG 295 */ 296 /* ARGSUSED */ 297 static nxge_status_t 298 nxge_check_xaui_xfp(p_nxge_t nxgep) 299 { 300 nxge_status_t status = NXGE_OK; 301 uint8_t phy_port_addr; 302 uint16_t val; 303 uint16_t val1; 304 uint8_t portn; 305 306 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_check_xaui_xfp")); 307 308 portn = nxgep->mac.portnum; 309 phy_port_addr = nxgep->statsp->mac_stats.xcvr_portn; 310 311 /* 312 * Keep the val1 code even though it is not used. Could be 313 * used to differenciate the "No XFP" case and "XFP,linkdown" 314 * case when a Intel XFP is used. 315 */ 316 if ((status = nxge_mdio_read(nxgep, phy_port_addr, 317 BCM8704_USER_DEV3_ADDR, 318 BCM8704_USER_ANALOG_STATUS0_REG, &val)) == NXGE_OK) { 319 status = nxge_mdio_read(nxgep, phy_port_addr, 320 BCM8704_USER_DEV3_ADDR, 321 BCM8704_USER_TX_ALARM_STATUS_REG, &val1); 322 } 323 324 if (status != NXGE_OK) { 325 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 326 NXGE_FM_EREPORT_XAUI_ERR); 327 if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 328 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 329 "XAUI is bad or absent on port<%d>\n", portn)); 330 } 331 } else if (nxgep->mac.portmode == PORT_10G_FIBER) { 332 /* 333 * 0x03FC = 0000 0011 1111 1100 (XFP is normal) 334 * 0x639C = 0110 0011 1001 1100 (XFP has problem) 335 * bit14 = 1: PDM loss-of-light indicator 336 * bit13 = 1: PDM Rx loss-of-signal 337 * bit6 = 0: Light is NOT ok 338 * bit5 = 0: PMD Rx signal is NOT ok 339 */ 340 if (val == 0x639C) { 341 NXGE_FM_REPORT_ERROR(nxgep, portn, NULL, 342 NXGE_FM_EREPORT_XFP_ERR); 343 if (DDI_FM_EREPORT_CAP(nxgep->fm_capabilities)) { 344 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 345 "XFP is bad or absent on port<%d>\n", 346 portn)); 347 } 348 status = NXGE_ERROR; 349 } 350 } 351 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_check_xaui_xfp")); 352 return (status); 353 } 354 355 356 /* ARGSUSED */ 357 uint_t 358 nxge_syserr_intr(void *arg1, void *arg2) 359 { 360 p_nxge_ldv_t ldvp = (p_nxge_ldv_t)arg1; 361 p_nxge_t nxgep = (p_nxge_t)arg2; 362 p_nxge_ldg_t ldgp = NULL; 363 npi_handle_t handle; 364 sys_err_stat_t estat; 365 uint_t serviced = DDI_INTR_UNCLAIMED; 366 367 if (arg1 == NULL && arg2 == NULL) { 368 return (serviced); 369 } 370 if (arg2 == NULL || ((ldvp != NULL && (void *) ldvp->nxgep != arg2))) { 371 if (ldvp != NULL) { 372 nxgep = ldvp->nxgep; 373 } 374 } 375 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 376 "==> nxge_syserr_intr: arg2 $%p arg1 $%p", nxgep, ldvp)); 377 if (ldvp != NULL && ldvp->use_timer == B_FALSE) { 378 ldgp = ldvp->ldgp; 379 if (ldgp == NULL) { 380 NXGE_ERROR_MSG((nxgep, SYSERR_CTL, 381 "<== nxge_syserrintr(no logical group): " 382 "arg2 $%p arg1 $%p", nxgep, ldvp)); 383 return (DDI_INTR_UNCLAIMED); 384 } 385 /* 386 * Get the logical device state if the function uses interrupt. 387 */ 388 } 389 390 /* This interrupt handler is for system error interrupts. */ 391 handle = NXGE_DEV_NPI_HANDLE(nxgep); 392 estat.value = 0; 393 (void) npi_fzc_sys_err_stat_get(handle, &estat); 394 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, 395 "==> nxge_syserr_intr: device error 0x%016llx", estat.value)); 396 397 if (estat.bits.ldw.smx) { 398 /* SMX */ 399 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 400 "==> nxge_syserr_intr: device error - SMX")); 401 } else if (estat.bits.ldw.mac) { 402 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 403 "==> nxge_syserr_intr: device error - MAC")); 404 /* 405 * There is nothing to be done here. All MAC errors go to per 406 * MAC port interrupt. MIF interrupt is the only MAC sub-block 407 * that can generate status here. MIF status reported will be 408 * ignored here. It is checked by per port timer instead. 409 */ 410 } else if (estat.bits.ldw.ipp) { 411 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 412 "==> nxge_syserr_intr: device error - IPP")); 413 (void) nxge_ipp_handle_sys_errors(nxgep); 414 } else if (estat.bits.ldw.zcp) { 415 /* ZCP */ 416 NXGE_DEBUG_MSG((nxgep, NXGE_ERR_CTL, 417 "==> nxge_syserr_intr: device error - ZCP")); 418 (void) nxge_zcp_handle_sys_errors(nxgep); 419 } else if (estat.bits.ldw.tdmc) { 420 /* TDMC */ 421 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 422 "==> nxge_syserr_intr: device error - TDMC")); 423 /* 424 * There is no TDMC system errors defined in the PRM. All TDMC 425 * channel specific errors are reported on a per channel basis. 426 */ 427 } else if (estat.bits.ldw.rdmc) { 428 /* RDMC */ 429 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 430 "==> nxge_syserr_intr: device error - RDMC")); 431 (void) nxge_rxdma_handle_sys_errors(nxgep); 432 } else if (estat.bits.ldw.txc) { 433 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 434 "==> nxge_syserr_intr: device error - TXC")); 435 (void) nxge_txc_handle_sys_errors(nxgep); 436 } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { 437 /* PCI-E */ 438 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 439 "==> nxge_syserr_intr: device error - PCI-E")); 440 } else if (estat.bits.ldw.meta1) { 441 /* META1 */ 442 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 443 "==> nxge_syserr_intr: device error - META1")); 444 } else if (estat.bits.ldw.meta2) { 445 /* META2 */ 446 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 447 "==> nxge_syserr_intr: device error - META2")); 448 } else if (estat.bits.ldw.fflp) { 449 /* FFLP */ 450 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 451 "==> nxge_syserr_intr: device error - FFLP")); 452 (void) nxge_fflp_handle_sys_errors(nxgep); 453 } 454 455 /* 456 * nxge_check_xaui_xfg checks XAUI for all of the following 457 * portmodes, but checks XFP only if portmode == PORT_10G_FIBER. 458 */ 459 if (nxgep->mac.portmode == PORT_10G_FIBER || 460 nxgep->mac.portmode == PORT_10G_COPPER || 461 nxgep->mac.portmode == PORT_10G_TN1010 || 462 nxgep->mac.portmode == PORT_1G_TN1010) { 463 if (nxge_check_xaui_xfp(nxgep) != NXGE_OK) { 464 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 465 "==> nxge_syserr_intr: device error - XAUI")); 466 } 467 } 468 469 serviced = DDI_INTR_CLAIMED; 470 471 if (ldgp != NULL && ldvp != NULL && ldgp->nldvs == 1 && 472 !ldvp->use_timer) { 473 (void) npi_intr_ldg_mgmt_set(handle, ldgp->ldg, 474 B_TRUE, ldgp->ldg_timer); 475 } 476 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_syserr_intr")); 477 return (serviced); 478 } 479 480 /* ARGSUSED */ 481 void 482 nxge_intr_hw_enable(p_nxge_t nxgep) 483 { 484 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_enable")); 485 (void) nxge_intr_mask_mgmt_set(nxgep, B_TRUE); 486 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_enable")); 487 } 488 489 /* ARGSUSED */ 490 void 491 nxge_intr_hw_disable(p_nxge_t nxgep) 492 { 493 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_intr_hw_disable")); 494 (void) nxge_intr_mask_mgmt_set(nxgep, B_FALSE); 495 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_intr_hw_disable")); 496 } 497 498 /* ARGSUSED */ 499 void 500 nxge_rx_hw_blank(void *arg, time_t ticks, uint_t count) 501 { 502 p_nxge_t nxgep = (p_nxge_t)arg; 503 uint8_t channel; 504 npi_handle_t handle; 505 p_nxge_ldgv_t ldgvp; 506 p_nxge_ldv_t ldvp; 507 int i; 508 509 NXGE_DEBUG_MSG((nxgep, INT_CTL, "==> nxge_rx_hw_blank")); 510 handle = NXGE_DEV_NPI_HANDLE(nxgep); 511 512 if ((ldgvp = nxgep->ldgvp) == NULL) { 513 NXGE_ERROR_MSG((nxgep, INT_CTL, 514 "<== nxge_rx_hw_blank (not enabled)")); 515 return; 516 } 517 ldvp = nxgep->ldgvp->ldvp; 518 if (ldvp == NULL) { 519 return; 520 } 521 for (i = 0; i < ldgvp->nldvs; i++, ldvp++) { 522 if (ldvp->is_rxdma) { 523 channel = ldvp->channel; 524 (void) npi_rxdma_cfg_rdc_rcr_threshold(handle, 525 channel, count); 526 (void) npi_rxdma_cfg_rdc_rcr_timeout(handle, 527 channel, ticks); 528 } 529 } 530 531 NXGE_DEBUG_MSG((nxgep, INT_CTL, "<== nxge_rx_hw_blank")); 532 } 533 534 /* ARGSUSED */ 535 void 536 nxge_hw_stop(p_nxge_t nxgep) 537 { 538 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_hw_stop")); 539 540 (void) nxge_tx_mac_disable(nxgep); 541 (void) nxge_rx_mac_disable(nxgep); 542 (void) nxge_txdma_hw_mode(nxgep, NXGE_DMA_STOP); 543 (void) nxge_rxdma_hw_mode(nxgep, NXGE_DMA_STOP); 544 545 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_hw_stop")); 546 } 547 548 /* ARGSUSED */ 549 void 550 nxge_hw_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 551 { 552 int cmd; 553 554 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_hw_ioctl")); 555 556 if (nxgep == NULL) { 557 miocnak(wq, mp, 0, EINVAL); 558 return; 559 } 560 iocp->ioc_error = 0; 561 cmd = iocp->ioc_cmd; 562 563 switch (cmd) { 564 default: 565 miocnak(wq, mp, 0, EINVAL); 566 return; 567 568 case NXGE_GET_MII: 569 nxge_get_mii(nxgep, mp->b_cont); 570 miocack(wq, mp, sizeof (uint16_t), 0); 571 break; 572 573 case NXGE_PUT_MII: 574 nxge_put_mii(nxgep, mp->b_cont); 575 miocack(wq, mp, 0, 0); 576 break; 577 578 case NXGE_GET64: 579 nxge_get64(nxgep, mp->b_cont); 580 miocack(wq, mp, sizeof (uint32_t), 0); 581 break; 582 583 case NXGE_PUT64: 584 nxge_put64(nxgep, mp->b_cont); 585 miocack(wq, mp, 0, 0); 586 break; 587 588 case NXGE_PUT_TCAM: 589 nxge_put_tcam(nxgep, mp->b_cont); 590 miocack(wq, mp, 0, 0); 591 break; 592 593 case NXGE_GET_TCAM: 594 nxge_get_tcam(nxgep, mp->b_cont); 595 miocack(wq, mp, 0, 0); 596 break; 597 598 case NXGE_TX_REGS_DUMP: 599 nxge_txdma_regs_dump_channels(nxgep); 600 miocack(wq, mp, 0, 0); 601 break; 602 case NXGE_RX_REGS_DUMP: 603 nxge_rxdma_regs_dump_channels(nxgep); 604 miocack(wq, mp, 0, 0); 605 break; 606 case NXGE_VIR_INT_REGS_DUMP: 607 case NXGE_INT_REGS_DUMP: 608 nxge_virint_regs_dump(nxgep); 609 miocack(wq, mp, 0, 0); 610 break; 611 case NXGE_RTRACE: 612 nxge_rtrace_ioctl(nxgep, wq, mp, iocp); 613 break; 614 } 615 } 616 617 /* ARGSUSED */ 618 void 619 nxge_loopback_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 620 struct iocblk *iocp) 621 { 622 p_lb_property_t lb_props; 623 624 size_t size; 625 int i; 626 627 if (mp->b_cont == NULL) { 628 miocnak(wq, mp, 0, EINVAL); 629 } 630 switch (iocp->ioc_cmd) { 631 case LB_GET_MODE: 632 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_MODE command")); 633 if (nxgep != NULL) { 634 *(lb_info_sz_t *)mp->b_cont->b_rptr = 635 nxgep->statsp->port_stats.lb_mode; 636 miocack(wq, mp, sizeof (nxge_lb_t), 0); 637 } else { 638 miocnak(wq, mp, 0, EINVAL); 639 } 640 break; 641 case LB_SET_MODE: 642 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_SET_LB_MODE command")); 643 if (iocp->ioc_count != sizeof (uint32_t)) { 644 miocack(wq, mp, 0, 0); 645 break; 646 } 647 if ((nxgep != NULL) && nxge_set_lb(nxgep, wq, mp->b_cont)) { 648 miocack(wq, mp, 0, 0); 649 } else { 650 miocnak(wq, mp, 0, EPROTO); 651 } 652 break; 653 case LB_GET_INFO_SIZE: 654 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "LB_GET_INFO_SIZE command")); 655 if (nxgep != NULL) { 656 size = sizeof (lb_normal); 657 if (nxgep->statsp->mac_stats.cap_10gfdx) { 658 /* TN1010 does not support external loopback */ 659 if (nxgep->mac.portmode != PORT_1G_TN1010 && 660 nxgep->mac.portmode != PORT_10G_TN1010) { 661 size += sizeof (lb_external10g); 662 } 663 size += sizeof (lb_mac10g); 664 /* Publish PHY loopback if PHY is present */ 665 if (nxgep->mac.portmode == PORT_10G_COPPER || 666 nxgep->mac.portmode == PORT_10G_TN1010 || 667 nxgep->mac.portmode == PORT_10G_FIBER) 668 size += sizeof (lb_phy10g); 669 } 670 671 /* 672 * Even if cap_10gfdx is false, we still do 10G 673 * serdes loopback as a part of SunVTS xnetlbtest 674 * internal loopback test. 675 */ 676 if (nxgep->mac.portmode == PORT_10G_FIBER || 677 nxgep->mac.portmode == PORT_10G_TN1010 || 678 nxgep->mac.portmode == PORT_10G_SERDES) 679 size += sizeof (lb_serdes10g); 680 681 if (nxgep->statsp->mac_stats.cap_1000fdx) { 682 /* TN1010 does not support external loopback */ 683 if (nxgep->mac.portmode != PORT_1G_TN1010 && 684 nxgep->mac.portmode != PORT_10G_TN1010) { 685 size += sizeof (lb_external1000); 686 } 687 size += sizeof (lb_mac1000); 688 if ((nxgep->mac.portmode == PORT_1G_COPPER) || 689 nxgep->mac.portmode == PORT_1G_TN1010 || 690 (nxgep->mac.portmode == 691 PORT_1G_RGMII_FIBER)) 692 size += sizeof (lb_phy1000); 693 } 694 if (nxgep->statsp->mac_stats.cap_100fdx) 695 size += sizeof (lb_external100); 696 if (nxgep->statsp->mac_stats.cap_10fdx) 697 size += sizeof (lb_external10); 698 if (nxgep->mac.portmode == PORT_1G_FIBER || 699 nxgep->mac.portmode == PORT_1G_TN1010 || 700 nxgep->mac.portmode == PORT_1G_SERDES) 701 size += sizeof (lb_serdes1000); 702 703 *(lb_info_sz_t *)mp->b_cont->b_rptr = size; 704 705 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 706 "NXGE_GET_LB_INFO command: size %d", size)); 707 miocack(wq, mp, sizeof (lb_info_sz_t), 0); 708 } else 709 miocnak(wq, mp, 0, EINVAL); 710 break; 711 712 case LB_GET_INFO: 713 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "NXGE_GET_LB_INFO command")); 714 if (nxgep != NULL) { 715 size = sizeof (lb_normal); 716 if (nxgep->statsp->mac_stats.cap_10gfdx) { 717 /* TN1010 does not support external loopback */ 718 if (nxgep->mac.portmode != PORT_1G_TN1010 && 719 nxgep->mac.portmode != PORT_10G_TN1010) { 720 size += sizeof (lb_external10g); 721 } 722 size += sizeof (lb_mac10g); 723 /* Publish PHY loopback if PHY is present */ 724 if (nxgep->mac.portmode == PORT_10G_COPPER || 725 nxgep->mac.portmode == PORT_10G_TN1010 || 726 nxgep->mac.portmode == PORT_10G_FIBER) 727 size += sizeof (lb_phy10g); 728 } 729 if (nxgep->mac.portmode == PORT_10G_FIBER || 730 nxgep->mac.portmode == PORT_10G_TN1010 || 731 nxgep->mac.portmode == PORT_10G_SERDES) 732 size += sizeof (lb_serdes10g); 733 734 if (nxgep->statsp->mac_stats.cap_1000fdx) { 735 /* TN1010 does not support external loopback */ 736 if (nxgep->mac.portmode != PORT_1G_TN1010 && 737 nxgep->mac.portmode != PORT_10G_TN1010) { 738 size += sizeof (lb_external1000); 739 } 740 size += sizeof (lb_mac1000); 741 if ((nxgep->mac.portmode == PORT_1G_COPPER) || 742 nxgep->mac.portmode == PORT_1G_TN1010 || 743 (nxgep->mac.portmode == 744 PORT_1G_RGMII_FIBER)) 745 size += sizeof (lb_phy1000); 746 } 747 if (nxgep->statsp->mac_stats.cap_100fdx) 748 size += sizeof (lb_external100); 749 750 if (nxgep->statsp->mac_stats.cap_10fdx) 751 size += sizeof (lb_external10); 752 753 if (nxgep->mac.portmode == PORT_1G_FIBER || 754 nxgep->mac.portmode == PORT_1G_TN1010 || 755 nxgep->mac.portmode == PORT_1G_SERDES) 756 size += sizeof (lb_serdes1000); 757 758 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 759 "NXGE_GET_LB_INFO command: size %d", size)); 760 if (size == iocp->ioc_count) { 761 i = 0; 762 lb_props = (p_lb_property_t)mp->b_cont->b_rptr; 763 lb_props[i++] = lb_normal; 764 765 if (nxgep->statsp->mac_stats.cap_10gfdx) { 766 lb_props[i++] = lb_mac10g; 767 if (nxgep->mac.portmode == 768 PORT_10G_COPPER || 769 nxgep->mac.portmode == 770 PORT_10G_TN1010 || 771 nxgep->mac.portmode == 772 PORT_10G_FIBER) { 773 lb_props[i++] = lb_phy10g; 774 } 775 /* TN1010 does not support ext lb */ 776 if (nxgep->mac.portmode != 777 PORT_10G_TN1010 && 778 nxgep->mac.portmode != 779 PORT_1G_TN1010) { 780 lb_props[i++] = lb_external10g; 781 } 782 lb_props[i++] = lb_external10g; 783 } 784 785 if (nxgep->mac.portmode == PORT_10G_FIBER || 786 nxgep->mac.portmode == PORT_10G_TN1010 || 787 nxgep->mac.portmode == PORT_10G_SERDES) 788 lb_props[i++] = lb_serdes10g; 789 790 if (nxgep->statsp->mac_stats.cap_1000fdx) { 791 /* TN1010 does not support ext lb */ 792 if (nxgep->mac.portmode != 793 PORT_10G_TN1010 && 794 nxgep->mac.portmode != 795 PORT_1G_TN1010) { 796 lb_props[i++] = lb_external1000; 797 } 798 } 799 800 if (nxgep->statsp->mac_stats.cap_100fdx) 801 lb_props[i++] = lb_external100; 802 803 if (nxgep->statsp->mac_stats.cap_10fdx) 804 lb_props[i++] = lb_external10; 805 806 if (nxgep->statsp->mac_stats.cap_1000fdx) 807 lb_props[i++] = lb_mac1000; 808 809 if ((nxgep->mac.portmode == PORT_1G_COPPER) || 810 nxgep->mac.portmode == PORT_1G_TN1010 || 811 (nxgep->mac.portmode == 812 PORT_1G_RGMII_FIBER)) { 813 if (nxgep->statsp->mac_stats. 814 cap_1000fdx) 815 lb_props[i++] = lb_phy1000; 816 } else if ((nxgep->mac.portmode == 817 PORT_1G_FIBER) || 818 (nxgep->mac.portmode == PORT_1G_TN1010) || 819 (nxgep->mac.portmode == PORT_1G_SERDES)) { 820 lb_props[i++] = lb_serdes1000; 821 } 822 miocack(wq, mp, size, 0); 823 } else 824 miocnak(wq, mp, 0, EINVAL); 825 } else { 826 miocnak(wq, mp, 0, EINVAL); 827 cmn_err(CE_NOTE, "!nxge_hw_ioctl: invalid command 0x%x", 828 iocp->ioc_cmd); 829 } 830 break; 831 } 832 } 833 834 /* 835 * DMA channel interfaces to access various channel specific 836 * hardware functions. 837 */ 838 /* ARGSUSED */ 839 void 840 nxge_rxdma_channel_put64(nxge_os_acc_handle_t handle, void *reg_addrp, 841 uint32_t reg_base, uint16_t channel, uint64_t reg_data) 842 { 843 uint64_t reg_offset; 844 845 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 846 847 /* 848 * Channel is assumed to be from 0 to the maximum DMA channel #. If we 849 * use the virtual DMA CSR address space from the config space (in PCI 850 * case), then the following code need to be use different offset 851 * computation macro. 852 */ 853 reg_offset = reg_base + DMC_OFFSET(channel); 854 NXGE_PIO_WRITE64(handle, reg_addrp, reg_offset, reg_data); 855 856 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_put64")); 857 } 858 859 /* ARGSUSED */ 860 uint64_t 861 nxge_rxdma_channel_get64(nxge_os_acc_handle_t handle, void *reg_addrp, 862 uint32_t reg_base, uint16_t channel) 863 { 864 uint64_t reg_offset; 865 866 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 867 868 /* 869 * Channel is assumed to be from 0 to the maximum DMA channel #. If we 870 * use the virtual DMA CSR address space from the config space (in PCI 871 * case), then the following code need to be use different offset 872 * computation macro. 873 */ 874 reg_offset = reg_base + DMC_OFFSET(channel); 875 876 NXGE_DEBUG_MSG((NULL, DMA_CTL, "<== nxge_rxdma_channel_get64")); 877 878 return (NXGE_PIO_READ64(handle, reg_addrp, reg_offset)); 879 } 880 881 /* ARGSUSED */ 882 void 883 nxge_get32(p_nxge_t nxgep, p_mblk_t mp) 884 { 885 nxge_os_acc_handle_t nxge_regh; 886 887 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 888 nxge_regh = nxgep->dev_regs->nxge_regh; 889 890 *(uint32_t *)mp->b_rptr = NXGE_PIO_READ32(nxge_regh, 891 nxgep->dev_regs->nxge_regp, *(uint32_t *)mp->b_rptr); 892 893 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "value = 0x%08X", 894 *(uint32_t *)mp->b_rptr)); 895 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_get32")); 896 } 897 898 /* ARGSUSED */ 899 void 900 nxge_put32(p_nxge_t nxgep, p_mblk_t mp) 901 { 902 nxge_os_acc_handle_t nxge_regh; 903 uint32_t *buf; 904 uint8_t *reg; 905 906 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 907 nxge_regh = nxgep->dev_regs->nxge_regh; 908 909 buf = (uint32_t *)mp->b_rptr; 910 reg = (uint8_t *)(nxgep->dev_regs->nxge_regp) + buf[0]; 911 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 912 "reg = 0x%016llX index = 0x%08X value = 0x%08X", 913 reg, buf[0], buf[1])); 914 NXGE_PIO_WRITE32(nxge_regh, (uint32_t *)reg, 0, buf[1]); 915 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "nxge_put32")); 916 } 917 918 /*ARGSUSED*/ 919 boolean_t 920 nxge_set_lb(p_nxge_t nxgep, queue_t *wq, p_mblk_t mp) 921 { 922 boolean_t status = B_TRUE; 923 uint32_t lb_mode; 924 lb_property_t *lb_info; 925 926 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_set_lb")); 927 lb_mode = nxgep->statsp->port_stats.lb_mode; 928 if (lb_mode == *(uint32_t *)mp->b_rptr) { 929 cmn_err(CE_NOTE, 930 "!nxge%d: Loopback mode already set (lb_mode %d).\n", 931 nxgep->instance, lb_mode); 932 status = B_FALSE; 933 goto nxge_set_lb_exit; 934 } 935 lb_mode = *(uint32_t *)mp->b_rptr; 936 lb_info = NULL; 937 if (lb_mode == lb_normal.value) 938 lb_info = &lb_normal; 939 else if ((lb_mode == lb_external10g.value) && 940 (nxgep->statsp->mac_stats.cap_10gfdx)) 941 lb_info = &lb_external10g; 942 else if ((lb_mode == lb_external1000.value) && 943 (nxgep->statsp->mac_stats.cap_1000fdx)) 944 lb_info = &lb_external1000; 945 else if ((lb_mode == lb_external100.value) && 946 (nxgep->statsp->mac_stats.cap_100fdx)) 947 lb_info = &lb_external100; 948 else if ((lb_mode == lb_external10.value) && 949 (nxgep->statsp->mac_stats.cap_10fdx)) 950 lb_info = &lb_external10; 951 else if ((lb_mode == lb_phy10g.value) && 952 ((nxgep->mac.portmode == PORT_10G_COPPER) || 953 (nxgep->mac.portmode == PORT_10G_TN1010) || 954 (nxgep->mac.portmode == PORT_10G_FIBER))) 955 lb_info = &lb_phy10g; 956 else if ((lb_mode == lb_phy1000.value) && 957 ((nxgep->mac.portmode == PORT_1G_COPPER) || 958 (nxgep->mac.portmode == PORT_1G_TN1010) || 959 (nxgep->mac.portmode == PORT_1G_RGMII_FIBER))) 960 lb_info = &lb_phy1000; 961 else if ((lb_mode == lb_phy.value) && 962 (nxgep->mac.portmode == PORT_1G_COPPER)) 963 lb_info = &lb_phy; 964 else if ((lb_mode == lb_serdes10g.value) && 965 ((nxgep->mac.portmode == PORT_10G_FIBER) || 966 (nxgep->mac.portmode == PORT_10G_COPPER) || 967 (nxgep->mac.portmode == PORT_10G_TN1010) || 968 (nxgep->mac.portmode == PORT_10G_SERDES))) 969 lb_info = &lb_serdes10g; 970 else if ((lb_mode == lb_serdes1000.value) && 971 (nxgep->mac.portmode == PORT_1G_FIBER) || 972 (nxgep->mac.portmode == PORT_1G_TN1010) || 973 (nxgep->mac.portmode == PORT_1G_SERDES)) 974 lb_info = &lb_serdes1000; 975 else if (lb_mode == lb_mac10g.value) 976 lb_info = &lb_mac10g; 977 else if (lb_mode == lb_mac1000.value) 978 lb_info = &lb_mac1000; 979 else if (lb_mode == lb_mac.value) 980 lb_info = &lb_mac; 981 else { 982 cmn_err(CE_NOTE, 983 "!nxge%d: Loopback mode not supported(mode %d).\n", 984 nxgep->instance, lb_mode); 985 status = B_FALSE; 986 goto nxge_set_lb_exit; 987 } 988 989 if (lb_mode == nxge_lb_normal) { 990 if (nxge_lb_dbg) { 991 cmn_err(CE_NOTE, 992 "!nxge%d: Returning to normal operation", 993 nxgep->instance); 994 } 995 if (nxge_set_lb_normal(nxgep) != NXGE_OK) { 996 status = B_FALSE; 997 cmn_err(CE_NOTE, 998 "!nxge%d: Failed to return to normal operation", 999 nxgep->instance); 1000 } 1001 goto nxge_set_lb_exit; 1002 } 1003 nxgep->statsp->port_stats.lb_mode = lb_mode; 1004 1005 if (nxge_lb_dbg) 1006 cmn_err(CE_NOTE, 1007 "!nxge%d: Adapter now in %s loopback mode", 1008 nxgep->instance, lb_info->key); 1009 nxgep->param_arr[param_autoneg].value = 0; 1010 nxgep->param_arr[param_anar_10gfdx].value = 1011 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 1012 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1013 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 1014 (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes10g); 1015 nxgep->param_arr[param_anar_10ghdx].value = 0; 1016 nxgep->param_arr[param_anar_1000fdx].value = 1017 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 1018 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac1000) || 1019 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 1020 (nxgep->statsp->port_stats.lb_mode == nxge_lb_serdes1000); 1021 nxgep->param_arr[param_anar_1000hdx].value = 0; 1022 nxgep->param_arr[param_anar_100fdx].value = 1023 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy) || 1024 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 1025 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100); 1026 nxgep->param_arr[param_anar_100hdx].value = 0; 1027 nxgep->param_arr[param_anar_10fdx].value = 1028 (nxgep->statsp->port_stats.lb_mode == nxge_lb_mac) || 1029 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10); 1030 if (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) { 1031 nxgep->param_arr[param_master_cfg_enable].value = 1; 1032 nxgep->param_arr[param_master_cfg_value].value = 1; 1033 } 1034 if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10g) || 1035 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext1000) || 1036 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext100) || 1037 (nxgep->statsp->port_stats.lb_mode == nxge_lb_ext10) || 1038 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy10g) || 1039 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy1000) || 1040 (nxgep->statsp->port_stats.lb_mode == nxge_lb_phy)) { 1041 1042 if (nxge_link_monitor(nxgep, LINK_MONITOR_STOP) != NXGE_OK) 1043 goto nxge_set_lb_err; 1044 if (nxge_xcvr_find(nxgep) != NXGE_OK) 1045 goto nxge_set_lb_err; 1046 if (nxge_link_init(nxgep) != NXGE_OK) 1047 goto nxge_set_lb_err; 1048 if (nxge_link_monitor(nxgep, LINK_MONITOR_START) != NXGE_OK) 1049 goto nxge_set_lb_err; 1050 } 1051 if (lb_info->lb_type == internal) { 1052 if ((nxgep->statsp->port_stats.lb_mode == nxge_lb_mac10g) || 1053 (nxgep->statsp->port_stats.lb_mode == 1054 nxge_lb_phy10g) || 1055 (nxgep->statsp->port_stats.lb_mode == 1056 nxge_lb_serdes10g)) { 1057 nxgep->statsp->mac_stats.link_speed = 10000; 1058 } else if ((nxgep->statsp->port_stats.lb_mode 1059 == nxge_lb_mac1000) || 1060 (nxgep->statsp->port_stats.lb_mode == 1061 nxge_lb_phy1000) || 1062 (nxgep->statsp->port_stats.lb_mode == 1063 nxge_lb_serdes1000)) { 1064 nxgep->statsp->mac_stats.link_speed = 1000; 1065 } else { 1066 nxgep->statsp->mac_stats.link_speed = 100; 1067 } 1068 nxgep->statsp->mac_stats.link_duplex = 2; 1069 nxgep->statsp->mac_stats.link_up = 1; 1070 } 1071 if (nxge_global_reset(nxgep) != NXGE_OK) 1072 goto nxge_set_lb_err; 1073 1074 nxge_set_lb_exit: 1075 NXGE_DEBUG_MSG((nxgep, DDI_CTL, 1076 "<== nxge_set_lb status = 0x%08x", status)); 1077 return (status); 1078 nxge_set_lb_err: 1079 status = B_FALSE; 1080 cmn_err(CE_NOTE, 1081 "!nxge%d: Failed to put adapter in %s loopback mode", 1082 nxgep->instance, lb_info->key); 1083 return (status); 1084 } 1085 1086 /* Return to normal (no loopback) mode */ 1087 /* ARGSUSED */ 1088 nxge_status_t 1089 nxge_set_lb_normal(p_nxge_t nxgep) 1090 { 1091 nxge_status_t status = NXGE_OK; 1092 1093 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "==> nxge_set_lb_normal")); 1094 1095 nxgep->statsp->port_stats.lb_mode = nxge_lb_normal; 1096 nxgep->param_arr[param_autoneg].value = 1097 nxgep->param_arr[param_autoneg].old_value; 1098 nxgep->param_arr[param_anar_1000fdx].value = 1099 nxgep->param_arr[param_anar_1000fdx].old_value; 1100 nxgep->param_arr[param_anar_1000hdx].value = 1101 nxgep->param_arr[param_anar_1000hdx].old_value; 1102 nxgep->param_arr[param_anar_100fdx].value = 1103 nxgep->param_arr[param_anar_100fdx].old_value; 1104 nxgep->param_arr[param_anar_100hdx].value = 1105 nxgep->param_arr[param_anar_100hdx].old_value; 1106 nxgep->param_arr[param_anar_10fdx].value = 1107 nxgep->param_arr[param_anar_10fdx].old_value; 1108 nxgep->param_arr[param_master_cfg_enable].value = 1109 nxgep->param_arr[param_master_cfg_enable].old_value; 1110 nxgep->param_arr[param_master_cfg_value].value = 1111 nxgep->param_arr[param_master_cfg_value].old_value; 1112 1113 if ((status = nxge_global_reset(nxgep)) != NXGE_OK) 1114 return (status); 1115 1116 if ((status = nxge_link_monitor(nxgep, LINK_MONITOR_STOP)) != NXGE_OK) 1117 return (status); 1118 if ((status = nxge_xcvr_find(nxgep)) != NXGE_OK) 1119 return (status); 1120 if ((status = nxge_link_init(nxgep)) != NXGE_OK) 1121 return (status); 1122 status = nxge_link_monitor(nxgep, LINK_MONITOR_START); 1123 1124 NXGE_DEBUG_MSG((nxgep, DDI_CTL, "<== nxge_set_lb_normal")); 1125 1126 return (status); 1127 } 1128 1129 /* ARGSUSED */ 1130 void 1131 nxge_get_mii(p_nxge_t nxgep, p_mblk_t mp) 1132 { 1133 uint16_t reg; 1134 1135 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_get_mii")); 1136 1137 reg = *(uint16_t *)mp->b_rptr; 1138 (void) nxge_mii_read(nxgep, nxgep->statsp->mac_stats.xcvr_portn, reg, 1139 (uint16_t *)mp->b_rptr); 1140 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "reg = 0x%08X value = 0x%04X", 1141 reg, *(uint16_t *)mp->b_rptr)); 1142 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_get_mii")); 1143 } 1144 1145 /* ARGSUSED */ 1146 void 1147 nxge_put_mii(p_nxge_t nxgep, p_mblk_t mp) 1148 { 1149 uint16_t *buf; 1150 uint8_t reg; 1151 1152 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "==> nxge_put_mii")); 1153 buf = (uint16_t *)mp->b_rptr; 1154 reg = (uint8_t)buf[0]; 1155 NXGE_DEBUG_MSG((nxgep, IOC_CTL, 1156 "reg = 0x%08X index = 0x%08X value = 0x%08X", 1157 reg, buf[0], buf[1])); 1158 (void) nxge_mii_write(nxgep, nxgep->statsp->mac_stats.xcvr_portn, 1159 reg, buf[1]); 1160 NXGE_DEBUG_MSG((nxgep, IOC_CTL, "<== nxge_put_mii")); 1161 } 1162 1163 /* ARGSUSED */ 1164 void 1165 nxge_check_hw_state(p_nxge_t nxgep) 1166 { 1167 p_nxge_ldgv_t ldgvp; 1168 p_nxge_ldv_t t_ldvp; 1169 1170 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "==> nxge_check_hw_state")); 1171 1172 MUTEX_ENTER(nxgep->genlock); 1173 nxgep->nxge_timerid = 0; 1174 if (!(nxgep->drv_state & STATE_HW_INITIALIZED)) { 1175 goto nxge_check_hw_state_exit; 1176 } 1177 nxge_check_tx_hang(nxgep); 1178 1179 ldgvp = nxgep->ldgvp; 1180 if (ldgvp == NULL || (ldgvp->ldvp_syserr == NULL)) { 1181 NXGE_ERROR_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1182 "NULL ldgvp (interrupt not ready).")); 1183 goto nxge_check_hw_state_exit; 1184 } 1185 t_ldvp = ldgvp->ldvp_syserr; 1186 if (!t_ldvp->use_timer) { 1187 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state: " 1188 "ldgvp $%p t_ldvp $%p use_timer flag %d", 1189 ldgvp, t_ldvp, t_ldvp->use_timer)); 1190 goto nxge_check_hw_state_exit; 1191 } 1192 if (fm_check_acc_handle(nxgep->dev_regs->nxge_regh) != DDI_FM_OK) { 1193 NXGE_ERROR_MSG((nxgep, NXGE_ERR_CTL, 1194 "port%d Bad register acc handle", nxgep->mac.portnum)); 1195 } 1196 (void) nxge_syserr_intr((void *) t_ldvp, (void *) nxgep); 1197 1198 nxgep->nxge_timerid = nxge_start_timer(nxgep, nxge_check_hw_state, 1199 NXGE_CHECK_TIMER); 1200 1201 nxge_check_hw_state_exit: 1202 MUTEX_EXIT(nxgep->genlock); 1203 NXGE_DEBUG_MSG((nxgep, SYSERR_CTL, "<== nxge_check_hw_state")); 1204 } 1205 1206 /*ARGSUSED*/ 1207 static void 1208 nxge_rtrace_ioctl(p_nxge_t nxgep, queue_t *wq, mblk_t *mp, 1209 struct iocblk *iocp) 1210 { 1211 ssize_t size; 1212 rtrace_t *rtp; 1213 mblk_t *nmp; 1214 uint32_t i, j; 1215 uint32_t start_blk; 1216 uint32_t base_entry; 1217 uint32_t num_entries; 1218 1219 NXGE_DEBUG_MSG((nxgep, STR_CTL, "==> nxge_rtrace_ioctl")); 1220 1221 size = 1024; 1222 if (mp->b_cont == NULL || MBLKL(mp->b_cont) < size) { 1223 NXGE_DEBUG_MSG((nxgep, STR_CTL, 1224 "malformed M_IOCTL MBLKL = %d size = %d", 1225 MBLKL(mp->b_cont), size)); 1226 miocnak(wq, mp, 0, EINVAL); 1227 return; 1228 } 1229 nmp = mp->b_cont; 1230 rtp = (rtrace_t *)nmp->b_rptr; 1231 start_blk = rtp->next_idx; 1232 num_entries = rtp->last_idx; 1233 base_entry = start_blk * MAX_RTRACE_IOC_ENTRIES; 1234 1235 NXGE_DEBUG_MSG((nxgep, STR_CTL, "start_blk = %d\n", start_blk)); 1236 NXGE_DEBUG_MSG((nxgep, STR_CTL, "num_entries = %d\n", num_entries)); 1237 NXGE_DEBUG_MSG((nxgep, STR_CTL, "base_entry = %d\n", base_entry)); 1238 1239 rtp->next_idx = npi_rtracebuf.next_idx; 1240 rtp->last_idx = npi_rtracebuf.last_idx; 1241 rtp->wrapped = npi_rtracebuf.wrapped; 1242 for (i = 0, j = base_entry; i < num_entries; i++, j++) { 1243 rtp->buf[i].ctl_addr = npi_rtracebuf.buf[j].ctl_addr; 1244 rtp->buf[i].val_l32 = npi_rtracebuf.buf[j].val_l32; 1245 rtp->buf[i].val_h32 = npi_rtracebuf.buf[j].val_h32; 1246 } 1247 1248 nmp->b_wptr = nmp->b_rptr + size; 1249 NXGE_DEBUG_MSG((nxgep, STR_CTL, "<== nxge_rtrace_ioctl")); 1250 miocack(wq, mp, (int)size, 0); 1251 } 1252