1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * nxge_hio.c 29 * 30 * This file manages the virtualization resources for Neptune 31 * devices. That is, it implements a hybrid I/O (HIO) approach in the 32 * Solaris kernel, whereby a guest domain on an LDOMs server may 33 * request & use hardware resources from the service domain. 34 * 35 */ 36 37 #include <sys/nxge/nxge_impl.h> 38 #include <sys/nxge/nxge_fzc.h> 39 #include <sys/nxge/nxge_rxdma.h> 40 #include <sys/nxge/nxge_txdma.h> 41 #include <sys/nxge/nxge_hio.h> 42 43 #define NXGE_HIO_SHARE_MIN_CHANNELS 2 44 #define NXGE_HIO_SHARE_MAX_CHANNELS 2 45 46 /* 47 * External prototypes 48 */ 49 extern npi_status_t npi_rxdma_dump_rdc_table(npi_handle_t, uint8_t); 50 51 /* The following function may be found in nxge_main.c */ 52 extern int nxge_m_mmac_remove(void *arg, mac_addr_slot_t slot); 53 54 /* The following function may be found in nxge_[t|r]xdma.c */ 55 extern npi_status_t nxge_txdma_channel_disable(nxge_t *, int); 56 extern nxge_status_t nxge_disable_rxdma_channel(nxge_t *, uint16_t); 57 58 /* 59 * Local prototypes 60 */ 61 static void nxge_grp_dc_append(nxge_t *, nxge_grp_t *, nxge_hio_dc_t *); 62 static nxge_hio_dc_t *nxge_grp_dc_unlink(nxge_t *, nxge_grp_t *, int); 63 static void nxge_grp_dc_map(nxge_grp_t *group); 64 65 /* 66 * These functions are used by both service & guest domains to 67 * decide whether they're running in an LDOMs/XEN environment 68 * or not. If so, then the Hybrid I/O (HIO) module is initialized. 69 */ 70 71 /* 72 * nxge_get_environs 73 * 74 * Figure out if we are in a guest domain or not. 75 * 76 * Arguments: 77 * nxge 78 * 79 * Notes: 80 * 81 * Context: 82 * Any domain 83 */ 84 void 85 nxge_get_environs( 86 nxge_t *nxge) 87 { 88 char *string; 89 90 /* 91 * In the beginning, assume that we are running sans LDOMs/XEN. 92 */ 93 nxge->environs = SOLARIS_DOMAIN; 94 95 /* 96 * Are we a hybrid I/O (HIO) guest domain driver? 97 */ 98 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, nxge->dip, 99 DDI_PROP_DONTPASS | DDI_PROP_NOTPROM, 100 "niutype", &string)) == DDI_PROP_SUCCESS) { 101 if (strcmp(string, "n2niu") == 0) { 102 nxge->environs = SOLARIS_GUEST_DOMAIN; 103 /* So we can allocate properly-aligned memory. */ 104 nxge->niu_type = N2_NIU; 105 NXGE_DEBUG_MSG((nxge, HIO_CTL, 106 "Hybrid IO-capable guest domain")); 107 } 108 ddi_prop_free(string); 109 } 110 } 111 112 #if !defined(sun4v) 113 114 /* 115 * nxge_hio_init 116 * 117 * Initialize the HIO module of the NXGE driver. 118 * 119 * Arguments: 120 * nxge 121 * 122 * Notes: 123 * This is the non-hybrid I/O version of this function. 124 * 125 * Context: 126 * Any domain 127 */ 128 int 129 nxge_hio_init(nxge_t *nxge) 130 { 131 nxge_hio_data_t *nhd; 132 133 nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 134 if (nhd == 0) { 135 nhd = KMEM_ZALLOC(sizeof (*nhd), KM_SLEEP); 136 MUTEX_INIT(&nhd->lock, NULL, MUTEX_DRIVER, NULL); 137 nxge->nxge_hw_p->hio = (uintptr_t)nhd; 138 } 139 140 nhd->hio.ldoms = B_FALSE; 141 142 return (NXGE_OK); 143 } 144 145 #endif 146 147 void 148 nxge_hio_uninit(nxge_t *nxge) 149 { 150 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 151 152 ASSERT(nxge->nxge_hw_p->ndevs == 0); 153 154 if (nhd != NULL) { 155 MUTEX_DESTROY(&nhd->lock); 156 KMEM_FREE(nhd, sizeof (*nhd)); 157 nxge->nxge_hw_p->hio = 0; 158 } 159 } 160 161 /* 162 * nxge_dci_map 163 * 164 * Map a DMA channel index to a channel number. 165 * 166 * Arguments: 167 * instance The instance number of the driver. 168 * type The type of channel this is: Tx or Rx. 169 * index The index to convert to a channel number 170 * 171 * Notes: 172 * This function is called by nxge_ndd.c:nxge_param_set_port_rdc() 173 * 174 * Context: 175 * Any domain 176 */ 177 int 178 nxge_dci_map( 179 nxge_t *nxge, 180 vpc_type_t type, 181 int index) 182 { 183 nxge_grp_set_t *set; 184 int dc; 185 186 switch (type) { 187 case VP_BOUND_TX: 188 set = &nxge->tx_set; 189 break; 190 case VP_BOUND_RX: 191 set = &nxge->rx_set; 192 break; 193 } 194 195 for (dc = 0; dc < NXGE_MAX_TDCS; dc++) { 196 if ((1 << dc) & set->owned.map) { 197 if (index == 0) 198 return (dc); 199 else 200 index--; 201 } 202 } 203 204 return (-1); 205 } 206 207 /* 208 * --------------------------------------------------------------------- 209 * These are the general-purpose DMA channel group functions. That is, 210 * these functions are used to manage groups of TDCs or RDCs in an HIO 211 * environment. 212 * 213 * But is also expected that in the future they will be able to manage 214 * Crossbow groups. 215 * --------------------------------------------------------------------- 216 */ 217 218 /* 219 * nxge_grp_cleanup(p_nxge_t nxge) 220 * 221 * Remove all outstanding groups. 222 * 223 * Arguments: 224 * nxge 225 */ 226 void 227 nxge_grp_cleanup(p_nxge_t nxge) 228 { 229 nxge_grp_set_t *set; 230 int i; 231 232 MUTEX_ENTER(&nxge->group_lock); 233 234 /* 235 * Find RX groups that need to be cleaned up. 236 */ 237 set = &nxge->rx_set; 238 for (i = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 239 if (set->group[i] != NULL) { 240 KMEM_FREE(set->group[i], sizeof (nxge_grp_t)); 241 set->group[i] = NULL; 242 } 243 } 244 245 /* 246 * Find TX groups that need to be cleaned up. 247 */ 248 set = &nxge->tx_set; 249 for (i = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 250 if (set->group[i] != NULL) { 251 KMEM_FREE(set->group[i], sizeof (nxge_grp_t)); 252 set->group[i] = NULL; 253 } 254 } 255 MUTEX_EXIT(&nxge->group_lock); 256 } 257 258 259 /* 260 * nxge_grp_add 261 * 262 * Add a group to an instance of NXGE. 263 * 264 * Arguments: 265 * nxge 266 * type Tx or Rx 267 * 268 * Notes: 269 * 270 * Context: 271 * Any domain 272 */ 273 nxge_grp_t * 274 nxge_grp_add( 275 nxge_t *nxge, 276 nxge_grp_type_t type) 277 { 278 nxge_grp_set_t *set; 279 nxge_grp_t *group; 280 int i; 281 282 group = KMEM_ZALLOC(sizeof (*group), KM_SLEEP); 283 group->nxge = nxge; 284 285 MUTEX_ENTER(&nxge->group_lock); 286 switch (type) { 287 case NXGE_TRANSMIT_GROUP: 288 case EXT_TRANSMIT_GROUP: 289 set = &nxge->tx_set; 290 break; 291 default: 292 set = &nxge->rx_set; 293 break; 294 } 295 296 group->type = type; 297 group->active = B_TRUE; 298 group->sequence = set->sequence++; 299 300 /* Find an empty slot for this logical group. */ 301 for (i = 0; i < NXGE_LOGICAL_GROUP_MAX; i++) { 302 if (set->group[i] == 0) { 303 group->index = i; 304 set->group[i] = group; 305 NXGE_DC_SET(set->lg.map, i); 306 set->lg.count++; 307 break; 308 } 309 } 310 MUTEX_EXIT(&nxge->group_lock); 311 312 NXGE_DEBUG_MSG((nxge, HIO_CTL, 313 "nxge_grp_add: %cgroup = %d.%d", 314 type == NXGE_TRANSMIT_GROUP ? 't' : 'r', 315 nxge->mac.portnum, group->sequence)); 316 317 return (group); 318 } 319 320 void 321 nxge_grp_remove( 322 nxge_t *nxge, 323 nxge_grp_t *group) /* The group to remove. */ 324 { 325 nxge_grp_set_t *set; 326 vpc_type_t type; 327 328 MUTEX_ENTER(&nxge->group_lock); 329 switch (group->type) { 330 case NXGE_TRANSMIT_GROUP: 331 case EXT_TRANSMIT_GROUP: 332 set = &nxge->tx_set; 333 break; 334 default: 335 set = &nxge->rx_set; 336 break; 337 } 338 339 if (set->group[group->index] != group) { 340 MUTEX_EXIT(&nxge->group_lock); 341 return; 342 } 343 344 set->group[group->index] = 0; 345 NXGE_DC_RESET(set->lg.map, group->index); 346 set->lg.count--; 347 348 /* While inside the mutex, deactivate <group>. */ 349 group->active = B_FALSE; 350 351 MUTEX_EXIT(&nxge->group_lock); 352 353 NXGE_DEBUG_MSG((nxge, HIO_CTL, 354 "nxge_grp_remove(%c.%d.%d) called", 355 group->type == NXGE_TRANSMIT_GROUP ? 't' : 'r', 356 nxge->mac.portnum, group->sequence)); 357 358 /* Now, remove any DCs which are still active. */ 359 switch (group->type) { 360 default: 361 type = VP_BOUND_TX; 362 break; 363 case NXGE_RECEIVE_GROUP: 364 case EXT_RECEIVE_GROUP: 365 type = VP_BOUND_RX; 366 } 367 368 while (group->dc) { 369 nxge_grp_dc_remove(nxge, type, group->dc->channel); 370 } 371 372 KMEM_FREE(group, sizeof (*group)); 373 } 374 375 /* 376 * nxge_grp_dc_add 377 * 378 * Add a DMA channel to a VR/Group. 379 * 380 * Arguments: 381 * nxge 382 * channel The channel to add. 383 * Notes: 384 * 385 * Context: 386 * Any domain 387 */ 388 /* ARGSUSED */ 389 int 390 nxge_grp_dc_add( 391 nxge_t *nxge, 392 nxge_grp_t *group, /* The group to add <channel> to. */ 393 vpc_type_t type, /* Rx or Tx */ 394 int channel) /* A physical/logical channel number */ 395 { 396 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 397 nxge_hio_dc_t *dc; 398 nxge_grp_set_t *set; 399 nxge_status_t status = NXGE_OK; 400 401 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_grp_dc_add")); 402 403 if (group == NULL) 404 return (0); 405 406 switch (type) { 407 case VP_BOUND_TX: 408 set = &nxge->tx_set; 409 if (channel > NXGE_MAX_TDCS) { 410 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 411 "nxge_grp_dc_add: TDC = %d", channel)); 412 return (NXGE_ERROR); 413 } 414 break; 415 case VP_BOUND_RX: 416 set = &nxge->rx_set; 417 if (channel > NXGE_MAX_RDCS) { 418 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 419 "nxge_grp_dc_add: RDC = %d", channel)); 420 return (NXGE_ERROR); 421 } 422 break; 423 424 default: 425 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 426 "nxge_grp_dc_add: unknown type channel(%d)", channel)); 427 return (NXGE_ERROR); 428 } 429 430 NXGE_DEBUG_MSG((nxge, HIO_CTL, 431 "nxge_grp_dc_add: %cgroup = %d.%d.%d, channel = %d", 432 type == VP_BOUND_TX ? 't' : 'r', 433 nxge->mac.portnum, group->sequence, group->count, channel)); 434 435 MUTEX_ENTER(&nxge->group_lock); 436 if (group->active != B_TRUE) { 437 /* We may be in the process of removing this group. */ 438 MUTEX_EXIT(&nxge->group_lock); 439 return (NXGE_ERROR); 440 } 441 MUTEX_EXIT(&nxge->group_lock); 442 443 if (!(dc = nxge_grp_dc_find(nxge, type, channel))) { 444 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 445 "nxge_grp_dc_add(%d): DC FIND failed", channel)); 446 return (NXGE_ERROR); 447 } 448 449 MUTEX_ENTER(&nhd->lock); 450 451 if (dc->group) { 452 MUTEX_EXIT(&nhd->lock); 453 /* This channel is already in use! */ 454 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 455 "nxge_grp_dc_add(%d): channel already in group", channel)); 456 return (NXGE_ERROR); 457 } 458 459 dc->next = 0; 460 dc->page = channel; 461 dc->channel = (nxge_channel_t)channel; 462 463 dc->type = type; 464 if (type == VP_BOUND_RX) { 465 dc->init = nxge_init_rxdma_channel; 466 dc->uninit = nxge_uninit_rxdma_channel; 467 } else { 468 dc->init = nxge_init_txdma_channel; 469 dc->uninit = nxge_uninit_txdma_channel; 470 } 471 472 dc->group = group; 473 474 if (isLDOMguest(nxge)) 475 (void) nxge_hio_ldsv_add(nxge, dc); 476 477 NXGE_DC_SET(set->owned.map, channel); 478 set->owned.count++; 479 480 MUTEX_EXIT(&nhd->lock); 481 482 if ((status = (*dc->init)(nxge, channel)) != NXGE_OK) { 483 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 484 "nxge_grp_dc_add(%d): channel init failed", channel)); 485 MUTEX_ENTER(&nhd->lock); 486 (void) memset(dc, 0, sizeof (*dc)); 487 NXGE_DC_RESET(set->owned.map, channel); 488 set->owned.count--; 489 MUTEX_EXIT(&nhd->lock); 490 return (NXGE_ERROR); 491 } 492 493 nxge_grp_dc_append(nxge, group, dc); 494 495 if (type == VP_BOUND_TX) { 496 MUTEX_ENTER(&nhd->lock); 497 nxge->tdc_is_shared[channel] = B_FALSE; 498 MUTEX_EXIT(&nhd->lock); 499 } 500 501 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_grp_dc_add")); 502 503 return ((int)status); 504 } 505 506 void 507 nxge_grp_dc_remove( 508 nxge_t *nxge, 509 vpc_type_t type, 510 int channel) 511 { 512 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 513 nxge_hio_dc_t *dc; 514 nxge_grp_set_t *set; 515 nxge_grp_t *group; 516 517 dc_uninit_t uninit; 518 519 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_grp_dc_remove")); 520 521 if ((dc = nxge_grp_dc_find(nxge, type, channel)) == 0) 522 goto nxge_grp_dc_remove_exit; 523 524 if ((dc->group == NULL) && (dc->next == 0) && 525 (dc->channel == 0) && (dc->page == 0) && (dc->type == 0)) { 526 goto nxge_grp_dc_remove_exit; 527 } 528 529 group = (nxge_grp_t *)dc->group; 530 531 if (isLDOMguest(nxge)) { 532 (void) nxge_hio_intr_remove(nxge, type, channel); 533 } 534 535 NXGE_DEBUG_MSG((nxge, HIO_CTL, 536 "DC remove: group = %d.%d.%d, %cdc %d", 537 nxge->mac.portnum, group->sequence, group->count, 538 type == VP_BOUND_TX ? 't' : 'r', dc->channel)); 539 540 MUTEX_ENTER(&nhd->lock); 541 542 set = dc->type == VP_BOUND_TX ? &nxge->tx_set : &nxge->rx_set; 543 if (isLDOMs(nxge) && ((1 << channel) && set->shared.map)) { 544 NXGE_DC_RESET(group->map, channel); 545 } 546 547 /* Remove the DC from its group. */ 548 if (nxge_grp_dc_unlink(nxge, group, channel) != dc) { 549 MUTEX_EXIT(&nhd->lock); 550 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 551 "nxge_grp_dc_remove(%d) failed", channel)); 552 goto nxge_grp_dc_remove_exit; 553 } 554 555 uninit = dc->uninit; 556 channel = dc->channel; 557 558 NXGE_DC_RESET(set->owned.map, channel); 559 set->owned.count--; 560 561 (void) memset(dc, 0, sizeof (*dc)); 562 563 MUTEX_EXIT(&nhd->lock); 564 565 (*uninit)(nxge, channel); 566 567 nxge_grp_dc_remove_exit: 568 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_grp_dc_remove")); 569 } 570 571 nxge_hio_dc_t * 572 nxge_grp_dc_find( 573 nxge_t *nxge, 574 vpc_type_t type, /* Rx or Tx */ 575 int channel) 576 { 577 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 578 nxge_hio_dc_t *current; 579 580 current = (type == VP_BOUND_TX) ? &nhd->tdc[0] : &nhd->rdc[0]; 581 582 if (!isLDOMguest(nxge)) { 583 return (¤t[channel]); 584 } else { 585 /* We're in a guest domain. */ 586 int i, limit = (type == VP_BOUND_TX) ? 587 NXGE_MAX_TDCS : NXGE_MAX_RDCS; 588 589 MUTEX_ENTER(&nhd->lock); 590 for (i = 0; i < limit; i++, current++) { 591 if (current->channel == channel) { 592 if (current->vr && current->vr->nxge == 593 (uintptr_t)nxge) { 594 MUTEX_EXIT(&nhd->lock); 595 return (current); 596 } 597 } 598 } 599 MUTEX_EXIT(&nhd->lock); 600 } 601 602 return (0); 603 } 604 605 /* 606 * nxge_grp_dc_append 607 * 608 * Append a DMA channel to a group. 609 * 610 * Arguments: 611 * nxge 612 * group The group to append to 613 * dc The DMA channel to append 614 * 615 * Notes: 616 * 617 * Context: 618 * Any domain 619 */ 620 static 621 void 622 nxge_grp_dc_append( 623 nxge_t *nxge, 624 nxge_grp_t *group, 625 nxge_hio_dc_t *dc) 626 { 627 MUTEX_ENTER(&nxge->group_lock); 628 629 if (group->dc == 0) { 630 group->dc = dc; 631 } else { 632 nxge_hio_dc_t *current = group->dc; 633 do { 634 if (current->next == 0) { 635 current->next = dc; 636 break; 637 } 638 current = current->next; 639 } while (current); 640 } 641 642 NXGE_DC_SET(group->map, dc->channel); 643 644 nxge_grp_dc_map(group); 645 group->count++; 646 647 MUTEX_EXIT(&nxge->group_lock); 648 } 649 650 /* 651 * nxge_grp_dc_unlink 652 * 653 * Unlink a DMA channel fromits linked list (group). 654 * 655 * Arguments: 656 * nxge 657 * group The group (linked list) to unlink from 658 * dc The DMA channel to append 659 * 660 * Notes: 661 * 662 * Context: 663 * Any domain 664 */ 665 nxge_hio_dc_t * 666 nxge_grp_dc_unlink(nxge_t *nxge, nxge_grp_t *group, int channel) 667 { 668 nxge_hio_dc_t *current, *previous; 669 670 MUTEX_ENTER(&nxge->group_lock); 671 672 if (group == NULL) { 673 MUTEX_EXIT(&nxge->group_lock); 674 return (0); 675 } 676 677 if ((current = group->dc) == 0) { 678 MUTEX_EXIT(&nxge->group_lock); 679 return (0); 680 } 681 682 previous = 0; 683 do { 684 if (current->channel == channel) { 685 if (previous) 686 previous->next = current->next; 687 else 688 group->dc = current->next; 689 break; 690 } 691 previous = current; 692 current = current->next; 693 } while (current); 694 695 if (current == 0) { 696 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 697 "DC unlink: DC %d not found", channel)); 698 } else { 699 current->next = 0; 700 current->group = 0; 701 702 group->count--; 703 } 704 705 nxge_grp_dc_map(group); 706 707 MUTEX_EXIT(&nxge->group_lock); 708 709 return (current); 710 } 711 712 /* 713 * nxge_grp_dc_map 714 * 715 * Map a linked list to an array of channel numbers. 716 * 717 * Arguments: 718 * nxge 719 * group The group to remap. 720 * 721 * Notes: 722 * It is expected that the caller will hold the correct mutex. 723 * 724 * Context: 725 * Service domain 726 */ 727 void 728 nxge_grp_dc_map( 729 nxge_grp_t *group) 730 { 731 nxge_channel_t *legend; 732 nxge_hio_dc_t *dc; 733 734 (void) memset(group->legend, 0, sizeof (group->legend)); 735 736 legend = group->legend; 737 dc = group->dc; 738 while (dc) { 739 *legend = dc->channel; 740 legend++; 741 dc = dc->next; 742 } 743 } 744 745 /* 746 * --------------------------------------------------------------------- 747 * These are HIO debugging functions. 748 * --------------------------------------------------------------------- 749 */ 750 751 /* 752 * nxge_delay 753 * 754 * Delay <seconds> number of seconds. 755 * 756 * Arguments: 757 * nxge 758 * group The group to append to 759 * dc The DMA channel to append 760 * 761 * Notes: 762 * This is a developer-only function. 763 * 764 * Context: 765 * Any domain 766 */ 767 void 768 nxge_delay( 769 int seconds) 770 { 771 delay(drv_usectohz(seconds * 1000000)); 772 } 773 774 static dmc_reg_name_t rx_names[] = { 775 { "RXDMA_CFIG1", 0 }, 776 { "RXDMA_CFIG2", 8 }, 777 { "RBR_CFIG_A", 0x10 }, 778 { "RBR_CFIG_B", 0x18 }, 779 { "RBR_KICK", 0x20 }, 780 { "RBR_STAT", 0x28 }, 781 { "RBR_HDH", 0x30 }, 782 { "RBR_HDL", 0x38 }, 783 { "RCRCFIG_A", 0x40 }, 784 { "RCRCFIG_B", 0x48 }, 785 { "RCRSTAT_A", 0x50 }, 786 { "RCRSTAT_B", 0x58 }, 787 { "RCRSTAT_C", 0x60 }, 788 { "RX_DMA_ENT_MSK", 0x68 }, 789 { "RX_DMA_CTL_STAT", 0x70 }, 790 { "RCR_FLSH", 0x78 }, 791 { "RXMISC", 0x90 }, 792 { "RX_DMA_CTL_STAT_DBG", 0x98 }, 793 { 0, -1 } 794 }; 795 796 static dmc_reg_name_t tx_names[] = { 797 { "Tx_RNG_CFIG", 0 }, 798 { "Tx_RNG_HDL", 0x10 }, 799 { "Tx_RNG_KICK", 0x18 }, 800 { "Tx_ENT_MASK", 0x20 }, 801 { "Tx_CS", 0x28 }, 802 { "TxDMA_MBH", 0x30 }, 803 { "TxDMA_MBL", 0x38 }, 804 { "TxDMA_PRE_ST", 0x40 }, 805 { "Tx_RNG_ERR_LOGH", 0x48 }, 806 { "Tx_RNG_ERR_LOGL", 0x50 }, 807 { "TDMC_INTR_DBG", 0x60 }, 808 { "Tx_CS_DBG", 0x68 }, 809 { 0, -1 } 810 }; 811 812 /* 813 * nxge_xx2str 814 * 815 * Translate a register address into a string. 816 * 817 * Arguments: 818 * offset The address of the register to translate. 819 * 820 * Notes: 821 * These are developer-only function. 822 * 823 * Context: 824 * Any domain 825 */ 826 const char * 827 nxge_rx2str( 828 int offset) 829 { 830 dmc_reg_name_t *reg = &rx_names[0]; 831 832 offset &= DMA_CSR_MASK; 833 834 while (reg->name) { 835 if (offset == reg->offset) 836 return (reg->name); 837 reg++; 838 } 839 840 return (0); 841 } 842 843 const char * 844 nxge_tx2str( 845 int offset) 846 { 847 dmc_reg_name_t *reg = &tx_names[0]; 848 849 offset &= DMA_CSR_MASK; 850 851 while (reg->name) { 852 if (offset == reg->offset) 853 return (reg->name); 854 reg++; 855 } 856 857 return (0); 858 } 859 860 /* 861 * nxge_ddi_perror 862 * 863 * Map a DDI error number to a string. 864 * 865 * Arguments: 866 * ddi_error The DDI error number to map. 867 * 868 * Notes: 869 * 870 * Context: 871 * Any domain 872 */ 873 const char * 874 nxge_ddi_perror( 875 int ddi_error) 876 { 877 switch (ddi_error) { 878 case DDI_SUCCESS: 879 return ("DDI_SUCCESS"); 880 case DDI_FAILURE: 881 return ("DDI_FAILURE"); 882 case DDI_NOT_WELL_FORMED: 883 return ("DDI_NOT_WELL_FORMED"); 884 case DDI_EAGAIN: 885 return ("DDI_EAGAIN"); 886 case DDI_EINVAL: 887 return ("DDI_EINVAL"); 888 case DDI_ENOTSUP: 889 return ("DDI_ENOTSUP"); 890 case DDI_EPENDING: 891 return ("DDI_EPENDING"); 892 case DDI_ENOMEM: 893 return ("DDI_ENOMEM"); 894 case DDI_EBUSY: 895 return ("DDI_EBUSY"); 896 case DDI_ETRANSPORT: 897 return ("DDI_ETRANSPORT"); 898 case DDI_ECONTEXT: 899 return ("DDI_ECONTEXT"); 900 default: 901 return ("Unknown error"); 902 } 903 } 904 905 /* 906 * --------------------------------------------------------------------- 907 * These are Sun4v HIO function definitions 908 * --------------------------------------------------------------------- 909 */ 910 911 #if defined(sun4v) 912 913 /* 914 * Local prototypes 915 */ 916 static nxge_hio_vr_t *nxge_hio_vr_share(nxge_t *); 917 918 static int nxge_hio_dc_share(nxge_t *, nxge_hio_vr_t *, mac_ring_type_t); 919 static void nxge_hio_unshare(nxge_hio_vr_t *); 920 921 static int nxge_hio_addres(nxge_hio_vr_t *, mac_ring_type_t, int); 922 static void nxge_hio_remres(nxge_hio_vr_t *, mac_ring_type_t, res_map_t); 923 924 static void nxge_hio_tdc_unshare(nxge_t *nxge, int channel); 925 static void nxge_hio_rdc_unshare(nxge_t *nxge, int channel); 926 static void nxge_hio_dc_unshare(nxge_t *, nxge_hio_vr_t *, 927 mac_ring_type_t, int); 928 929 /* 930 * nxge_hio_init 931 * 932 * Initialize the HIO module of the NXGE driver. 933 * 934 * Arguments: 935 * nxge 936 * 937 * Notes: 938 * 939 * Context: 940 * Any domain 941 */ 942 int 943 nxge_hio_init( 944 nxge_t *nxge) 945 { 946 nxge_hio_data_t *nhd; 947 int i, region; 948 949 nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 950 if (nhd == 0) { 951 nhd = KMEM_ZALLOC(sizeof (*nhd), KM_SLEEP); 952 MUTEX_INIT(&nhd->lock, NULL, MUTEX_DRIVER, NULL); 953 nxge->nxge_hw_p->hio = (uintptr_t)nhd; 954 } 955 956 if ((nxge->environs == SOLARIS_DOMAIN) && 957 (nxge->niu_type == N2_NIU)) { 958 if (nxge->niu_hsvc_available == B_TRUE) { 959 hsvc_info_t *niu_hsvc = &nxge->niu_hsvc; 960 if (niu_hsvc->hsvc_major == 1 && 961 niu_hsvc->hsvc_minor == 1) 962 nxge->environs = SOLARIS_SERVICE_DOMAIN; 963 NXGE_DEBUG_MSG((nxge, HIO_CTL, 964 "nxge_hio_init: hypervisor services " 965 "version %d.%d", 966 niu_hsvc->hsvc_major, niu_hsvc->hsvc_minor)); 967 } 968 } 969 970 if (!isLDOMs(nxge)) { 971 nhd->hio.ldoms = B_FALSE; 972 return (NXGE_OK); 973 } 974 975 nhd->hio.ldoms = B_TRUE; 976 977 /* 978 * Fill in what we can. 979 */ 980 for (region = 0; region < NXGE_VR_SR_MAX; region++) { 981 nhd->vr[region].region = region; 982 } 983 nhd->vrs = NXGE_VR_SR_MAX - 2; 984 985 /* 986 * Initialize tdc share state, shares and ring group structures. 987 */ 988 for (i = 0; i < NXGE_MAX_TDCS; i++) 989 nxge->tdc_is_shared[i] = B_FALSE; 990 991 for (i = 0; i < NXGE_MAX_RDC_GROUPS; i++) { 992 nxge->rx_hio_groups[i].ghandle = NULL; 993 nxge->rx_hio_groups[i].nxgep = nxge; 994 nxge->rx_hio_groups[i].gindex = 0; 995 nxge->rx_hio_groups[i].sindex = 0; 996 } 997 998 for (i = 0; i < NXGE_VR_SR_MAX; i++) { 999 nxge->shares[i].nxgep = nxge; 1000 nxge->shares[i].index = 0; 1001 nxge->shares[i].vrp = (void *)NULL; 1002 nxge->shares[i].tmap = 0; 1003 nxge->shares[i].rmap = 0; 1004 nxge->shares[i].rxgroup = 0; 1005 nxge->shares[i].active = B_FALSE; 1006 } 1007 1008 /* Fill in the HV HIO function pointers. */ 1009 nxge_hio_hv_init(nxge); 1010 1011 if (isLDOMservice(nxge)) { 1012 NXGE_DEBUG_MSG((nxge, HIO_CTL, 1013 "Hybrid IO-capable service domain")); 1014 return (NXGE_OK); 1015 } else { 1016 /* 1017 * isLDOMguest(nxge) == B_TRUE 1018 */ 1019 nx_vio_fp_t *vio; 1020 nhd->type = NXGE_HIO_TYPE_GUEST; 1021 1022 vio = &nhd->hio.vio; 1023 vio->__register = (vio_net_resource_reg_t) 1024 modgetsymvalue("vio_net_resource_reg", 0); 1025 vio->unregister = (vio_net_resource_unreg_t) 1026 modgetsymvalue("vio_net_resource_unreg", 0); 1027 1028 if (vio->__register == 0 || vio->unregister == 0) { 1029 NXGE_ERROR_MSG((nxge, VIR_CTL, "vio_net is absent!")); 1030 return (NXGE_ERROR); 1031 } 1032 } 1033 1034 return (0); 1035 } 1036 1037 static int 1038 nxge_hio_add_mac(void *arg, const uint8_t *mac_addr) 1039 { 1040 nxge_rx_ring_group_t *rxgroup = (nxge_rx_ring_group_t *)arg; 1041 p_nxge_t nxge = rxgroup->nxgep; 1042 int group = rxgroup->gindex; 1043 int rv, sindex; 1044 nxge_hio_vr_t *vr; /* The Virtualization Region */ 1045 1046 sindex = nxge->rx_hio_groups[group].sindex; 1047 vr = (nxge_hio_vr_t *)nxge->shares[sindex].vrp; 1048 1049 /* 1050 * Program the mac address for the group/share. 1051 */ 1052 if ((rv = nxge_hio_hostinfo_init(nxge, vr, 1053 (ether_addr_t *)mac_addr)) != 0) { 1054 return (rv); 1055 } 1056 1057 return (0); 1058 } 1059 1060 /* ARGSUSED */ 1061 static int 1062 nxge_hio_rem_mac(void *arg, const uint8_t *mac_addr) 1063 { 1064 nxge_rx_ring_group_t *rxgroup = (nxge_rx_ring_group_t *)arg; 1065 p_nxge_t nxge = rxgroup->nxgep; 1066 int group = rxgroup->gindex; 1067 int sindex; 1068 nxge_hio_vr_t *vr; /* The Virtualization Region */ 1069 1070 sindex = nxge->rx_hio_groups[group].sindex; 1071 vr = (nxge_hio_vr_t *)nxge->shares[sindex].vrp; 1072 1073 /* 1074 * Remove the mac address for the group/share. 1075 */ 1076 nxge_hio_hostinfo_uninit(nxge, vr); 1077 1078 return (0); 1079 } 1080 1081 /* ARGSUSED */ 1082 void 1083 nxge_hio_group_get(void *arg, mac_ring_type_t type, int group, 1084 mac_group_info_t *infop, mac_group_handle_t ghdl) 1085 { 1086 p_nxge_t nxgep = (p_nxge_t)arg; 1087 nxge_rx_ring_group_t *rxgroup; 1088 1089 switch (type) { 1090 case MAC_RING_TYPE_RX: 1091 rxgroup = &nxgep->rx_hio_groups[group]; 1092 rxgroup->gindex = group; 1093 1094 infop->mrg_driver = (mac_group_driver_t)rxgroup; 1095 infop->mrg_start = NULL; 1096 infop->mrg_stop = NULL; 1097 infop->mrg_addmac = nxge_hio_add_mac; 1098 infop->mrg_remmac = nxge_hio_rem_mac; 1099 infop->mrg_count = NXGE_HIO_SHARE_MAX_CHANNELS; 1100 break; 1101 1102 case MAC_RING_TYPE_TX: 1103 break; 1104 } 1105 } 1106 1107 int 1108 nxge_hio_share_assign( 1109 nxge_t *nxge, 1110 uint64_t cookie, 1111 res_map_t *tmap, 1112 res_map_t *rmap, 1113 nxge_hio_vr_t *vr) 1114 { 1115 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 1116 uint64_t slot, hv_rv; 1117 nxge_hio_dc_t *dc; 1118 nxhv_vr_fp_t *fp; 1119 int i; 1120 1121 /* 1122 * Ask the Hypervisor to set up the VR for us 1123 */ 1124 fp = &nhd->hio.vr; 1125 if ((hv_rv = (*fp->assign)(vr->region, cookie, &vr->cookie))) { 1126 NXGE_ERROR_MSG((nxge, HIO_CTL, 1127 "nxge_hio_share_assign: " 1128 "vr->assign() returned %d", hv_rv)); 1129 nxge_hio_unshare(vr); 1130 return (-EIO); 1131 } 1132 1133 /* 1134 * For each shared TDC, ask the HV to find us an empty slot. 1135 * ----------------------------------------------------- 1136 */ 1137 dc = vr->tx_group.dc; 1138 for (i = 0; i < NXGE_MAX_TDCS; i++) { 1139 nxhv_dc_fp_t *tx = &nhd->hio.tx; 1140 while (dc) { 1141 hv_rv = (*tx->assign) 1142 (vr->cookie, dc->channel, &slot); 1143 if (hv_rv != 0) { 1144 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1145 "nxge_hio_share_assign: " 1146 "tx->assign(%x, %d) failed: %ld", 1147 vr->cookie, dc->channel, hv_rv)); 1148 return (-EIO); 1149 } 1150 1151 dc->cookie = vr->cookie; 1152 dc->page = (vp_channel_t)slot; 1153 1154 /* Inform the caller about the slot chosen. */ 1155 (*tmap) |= 1 << slot; 1156 1157 dc = dc->next; 1158 } 1159 } 1160 1161 /* 1162 * For each shared RDC, ask the HV to find us an empty slot. 1163 * ----------------------------------------------------- 1164 */ 1165 dc = vr->rx_group.dc; 1166 for (i = 0; i < NXGE_MAX_RDCS; i++) { 1167 nxhv_dc_fp_t *rx = &nhd->hio.rx; 1168 while (dc) { 1169 hv_rv = (*rx->assign) 1170 (vr->cookie, dc->channel, &slot); 1171 if (hv_rv != 0) { 1172 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1173 "nxge_hio_share_assign: " 1174 "rx->assign(%x, %d) failed: %ld", 1175 vr->cookie, dc->channel, hv_rv)); 1176 return (-EIO); 1177 } 1178 1179 dc->cookie = vr->cookie; 1180 dc->page = (vp_channel_t)slot; 1181 1182 /* Inform the caller about the slot chosen. */ 1183 (*rmap) |= 1 << slot; 1184 1185 dc = dc->next; 1186 } 1187 } 1188 1189 return (0); 1190 } 1191 1192 int 1193 nxge_hio_share_unassign( 1194 nxge_hio_vr_t *vr) 1195 { 1196 nxge_t *nxge = (nxge_t *)vr->nxge; 1197 nxge_hio_data_t *nhd; 1198 nxge_hio_dc_t *dc; 1199 nxhv_vr_fp_t *fp; 1200 uint64_t hv_rv; 1201 1202 nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 1203 1204 dc = vr->tx_group.dc; 1205 while (dc) { 1206 nxhv_dc_fp_t *tx = &nhd->hio.tx; 1207 hv_rv = (*tx->unassign)(vr->cookie, dc->page); 1208 if (hv_rv != 0) { 1209 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1210 "nxge_hio_share_unassign: " 1211 "tx->unassign(%x, %d) failed: %ld", 1212 vr->cookie, dc->page, hv_rv)); 1213 } 1214 dc = dc->next; 1215 } 1216 1217 dc = vr->rx_group.dc; 1218 while (dc) { 1219 nxhv_dc_fp_t *rx = &nhd->hio.rx; 1220 hv_rv = (*rx->unassign)(vr->cookie, dc->page); 1221 if (hv_rv != 0) { 1222 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1223 "nxge_hio_share_unassign: " 1224 "rx->unassign(%x, %d) failed: %ld", 1225 vr->cookie, dc->page, hv_rv)); 1226 } 1227 dc = dc->next; 1228 } 1229 1230 fp = &nhd->hio.vr; 1231 if (fp->unassign) { 1232 hv_rv = (*fp->unassign)(vr->cookie); 1233 if (hv_rv != 0) { 1234 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1235 "nxge_hio_share_unassign: " 1236 "vr->assign(%x) failed: %ld", 1237 vr->cookie, hv_rv)); 1238 } 1239 } 1240 1241 return (0); 1242 } 1243 1244 int 1245 nxge_hio_share_alloc(void *arg, uint64_t cookie, uint64_t *rcookie, 1246 mac_share_handle_t *shandle) 1247 { 1248 p_nxge_t nxge = (p_nxge_t)arg; 1249 nxge_rx_ring_group_t *rxgroup; 1250 nxge_share_handle_t *shp; 1251 1252 nxge_hio_vr_t *vr; /* The Virtualization Region */ 1253 uint64_t rmap, tmap; 1254 int rv; 1255 1256 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 1257 1258 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_share")); 1259 1260 if (nhd->hio.vr.assign == 0 || nhd->hio.tx.assign == 0 || 1261 nhd->hio.rx.assign == 0) { 1262 NXGE_ERROR_MSG((nxge, HIO_CTL, "HV assign function(s) NULL")); 1263 return (EIO); 1264 } 1265 1266 /* 1267 * Get a VR. 1268 */ 1269 if ((vr = nxge_hio_vr_share(nxge)) == 0) 1270 return (EAGAIN); 1271 1272 /* 1273 * Get an RDC group for us to use. 1274 */ 1275 if ((vr->rdc_tbl = nxge_hio_hostinfo_get_rdc_table(nxge)) < 0) { 1276 nxge_hio_unshare(vr); 1277 return (EBUSY); 1278 } 1279 1280 /* 1281 * Add resources to the share. 1282 */ 1283 tmap = 0; 1284 rv = nxge_hio_addres(vr, MAC_RING_TYPE_TX, 1285 NXGE_HIO_SHARE_MAX_CHANNELS); 1286 if (rv != 0) { 1287 nxge_hio_unshare(vr); 1288 return (rv); 1289 } 1290 1291 rmap = 0; 1292 rv = nxge_hio_addres(vr, MAC_RING_TYPE_RX, 1293 NXGE_HIO_SHARE_MAX_CHANNELS); 1294 if (rv != 0) { 1295 nxge_hio_remres(vr, MAC_RING_TYPE_TX, tmap); 1296 nxge_hio_unshare(vr); 1297 return (rv); 1298 } 1299 1300 if ((rv = nxge_hio_share_assign(nxge, cookie, &tmap, &rmap, vr))) { 1301 nxge_hio_remres(vr, MAC_RING_TYPE_RX, tmap); 1302 nxge_hio_remres(vr, MAC_RING_TYPE_TX, tmap); 1303 nxge_hio_unshare(vr); 1304 return (rv); 1305 } 1306 1307 rxgroup = &nxge->rx_hio_groups[vr->rdc_tbl]; 1308 rxgroup->gindex = vr->rdc_tbl; 1309 rxgroup->sindex = vr->region; 1310 1311 shp = &nxge->shares[vr->region]; 1312 shp->index = vr->region; 1313 shp->vrp = (void *)vr; 1314 shp->tmap = tmap; 1315 shp->rmap = rmap; 1316 shp->rxgroup = vr->rdc_tbl; 1317 shp->active = B_TRUE; 1318 1319 /* high 32 bits are cfg_hdl and low 32 bits are HV cookie */ 1320 *rcookie = (((uint64_t)nxge->niu_cfg_hdl) << 32) | vr->cookie; 1321 1322 *shandle = (mac_share_handle_t)shp; 1323 1324 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_share")); 1325 return (0); 1326 } 1327 1328 void 1329 nxge_hio_share_free(mac_share_handle_t shandle) 1330 { 1331 nxge_share_handle_t *shp = (nxge_share_handle_t *)shandle; 1332 1333 /* 1334 * First, unassign the VR (take it back), 1335 * so we can enable interrupts again. 1336 */ 1337 (void) nxge_hio_share_unassign(shp->vrp); 1338 1339 /* 1340 * Free Ring Resources for TX and RX 1341 */ 1342 nxge_hio_remres(shp->vrp, MAC_RING_TYPE_TX, shp->tmap); 1343 nxge_hio_remres(shp->vrp, MAC_RING_TYPE_RX, shp->rmap); 1344 1345 /* 1346 * Free VR resource. 1347 */ 1348 nxge_hio_unshare(shp->vrp); 1349 1350 /* 1351 * Clear internal handle state. 1352 */ 1353 shp->index = 0; 1354 shp->vrp = (void *)NULL; 1355 shp->tmap = 0; 1356 shp->rmap = 0; 1357 shp->rxgroup = 0; 1358 shp->active = B_FALSE; 1359 } 1360 1361 void 1362 nxge_hio_share_query(mac_share_handle_t shandle, mac_ring_type_t type, 1363 uint32_t *rmin, uint32_t *rmax, uint64_t *rmap, uint64_t *gnum) 1364 { 1365 nxge_share_handle_t *shp = (nxge_share_handle_t *)shandle; 1366 1367 switch (type) { 1368 case MAC_RING_TYPE_RX: 1369 *rmin = NXGE_HIO_SHARE_MIN_CHANNELS; 1370 *rmax = NXGE_HIO_SHARE_MAX_CHANNELS; 1371 *rmap = shp->rmap; 1372 *gnum = shp->rxgroup; 1373 break; 1374 1375 case MAC_RING_TYPE_TX: 1376 *rmin = NXGE_HIO_SHARE_MIN_CHANNELS; 1377 *rmax = NXGE_HIO_SHARE_MAX_CHANNELS; 1378 *rmap = shp->tmap; 1379 *gnum = 0; 1380 break; 1381 } 1382 } 1383 1384 /* 1385 * nxge_hio_vr_share 1386 * 1387 * Find an unused Virtualization Region (VR). 1388 * 1389 * Arguments: 1390 * nxge 1391 * 1392 * Notes: 1393 * 1394 * Context: 1395 * Service domain 1396 */ 1397 nxge_hio_vr_t * 1398 nxge_hio_vr_share( 1399 nxge_t *nxge) 1400 { 1401 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 1402 nxge_hio_vr_t *vr; 1403 1404 int first, limit, region; 1405 1406 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_vr_share")); 1407 1408 MUTEX_ENTER(&nhd->lock); 1409 1410 if (nhd->vrs == 0) { 1411 MUTEX_EXIT(&nhd->lock); 1412 return (0); 1413 } 1414 1415 /* Find an empty virtual region (VR). */ 1416 if (nxge->function_num == 0) { 1417 // FUNC0_VIR0 'belongs' to NIU port 0. 1418 first = FUNC0_VIR1; 1419 limit = FUNC2_VIR0; 1420 } else if (nxge->function_num == 1) { 1421 // FUNC2_VIR0 'belongs' to NIU port 1. 1422 first = FUNC2_VIR1; 1423 limit = FUNC_VIR_MAX; 1424 } else { 1425 cmn_err(CE_WARN, 1426 "Shares not supported on function(%d) at this time.\n", 1427 nxge->function_num); 1428 } 1429 1430 for (region = first; region < limit; region++) { 1431 if (nhd->vr[region].nxge == 0) 1432 break; 1433 } 1434 1435 if (region == limit) { 1436 MUTEX_EXIT(&nhd->lock); 1437 return (0); 1438 } 1439 1440 vr = &nhd->vr[region]; 1441 vr->nxge = (uintptr_t)nxge; 1442 vr->region = (uintptr_t)region; 1443 1444 nhd->vrs--; 1445 1446 MUTEX_EXIT(&nhd->lock); 1447 1448 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_vr_share")); 1449 1450 return (vr); 1451 } 1452 1453 void 1454 nxge_hio_unshare( 1455 nxge_hio_vr_t *vr) 1456 { 1457 nxge_t *nxge = (nxge_t *)vr->nxge; 1458 nxge_hio_data_t *nhd; 1459 1460 vr_region_t region; 1461 1462 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_unshare")); 1463 1464 if (!nxge) { 1465 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_unshare: " 1466 "vr->nxge is NULL")); 1467 return; 1468 } 1469 1470 /* 1471 * This function is no longer called, but I will keep it 1472 * here in case we want to revisit this topic in the future. 1473 * 1474 * nxge_hio_hostinfo_uninit(nxge, vr); 1475 */ 1476 (void) nxge_fzc_rdc_tbl_unbind(nxge, vr->rdc_tbl); 1477 1478 nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 1479 1480 MUTEX_ENTER(&nhd->lock); 1481 1482 region = vr->region; 1483 (void) memset(vr, 0, sizeof (*vr)); 1484 vr->region = region; 1485 1486 nhd->vrs++; 1487 1488 MUTEX_EXIT(&nhd->lock); 1489 1490 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_unshare")); 1491 } 1492 1493 int 1494 nxge_hio_addres( 1495 nxge_hio_vr_t *vr, 1496 mac_ring_type_t type, 1497 int count) 1498 { 1499 nxge_t *nxge = (nxge_t *)vr->nxge; 1500 int i; 1501 1502 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_addres")); 1503 1504 if (!nxge) 1505 return (EINVAL); 1506 1507 for (i = 0; i < count; i++) { 1508 int rv; 1509 if ((rv = nxge_hio_dc_share(nxge, vr, type)) < 0) { 1510 if (i == 0) /* Couldn't get even one DC. */ 1511 return (-rv); 1512 else 1513 break; 1514 } 1515 } 1516 1517 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_addres")); 1518 1519 return (0); 1520 } 1521 1522 /* ARGSUSED */ 1523 void 1524 nxge_hio_remres( 1525 nxge_hio_vr_t *vr, 1526 mac_ring_type_t type, 1527 res_map_t res_map) 1528 { 1529 nxge_t *nxge = (nxge_t *)vr->nxge; 1530 nxge_grp_t *group; 1531 1532 if (!nxge) { 1533 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_remres: " 1534 "vr->nxge is NULL")); 1535 return; 1536 } 1537 1538 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_remres(%lx)", res_map)); 1539 1540 group = (type == MAC_RING_TYPE_TX ? &vr->tx_group : &vr->rx_group); 1541 while (group->dc) { 1542 nxge_hio_dc_t *dc = group->dc; 1543 NXGE_DC_RESET(res_map, dc->page); 1544 nxge_hio_dc_unshare(nxge, vr, type, dc->channel); 1545 } 1546 1547 if (res_map) { 1548 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_remres: " 1549 "res_map %lx", res_map)); 1550 } 1551 1552 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_remres")); 1553 } 1554 1555 /* 1556 * nxge_hio_tdc_share 1557 * 1558 * Share an unused TDC channel. 1559 * 1560 * Arguments: 1561 * nxge 1562 * 1563 * Notes: 1564 * 1565 * A.7.3 Reconfigure Tx DMA channel 1566 * Disable TxDMA A.9.6.10 1567 * [Rebind TxDMA channel to Port A.9.6.7] 1568 * 1569 * We don't have to Rebind the TDC to the port - it always already bound. 1570 * 1571 * Soft Reset TxDMA A.9.6.2 1572 * 1573 * This procedure will be executed by nxge_init_txdma_channel() in the 1574 * guest domain: 1575 * 1576 * Re-initialize TxDMA A.9.6.8 1577 * Reconfigure TxDMA 1578 * Enable TxDMA A.9.6.9 1579 * 1580 * Context: 1581 * Service domain 1582 */ 1583 int 1584 nxge_hio_tdc_share( 1585 nxge_t *nxge, 1586 int channel) 1587 { 1588 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 1589 nxge_grp_set_t *set = &nxge->tx_set; 1590 tx_ring_t *ring; 1591 int count; 1592 1593 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_tdc_share")); 1594 1595 /* 1596 * Wait until this channel is idle. 1597 */ 1598 ring = nxge->tx_rings->rings[channel]; 1599 1600 (void) atomic_swap_32(&ring->tx_ring_offline, NXGE_TX_RING_OFFLINING); 1601 if (ring->tx_ring_busy) { 1602 /* 1603 * Wait for 30 seconds. 1604 */ 1605 for (count = 30 * 1000; count; count--) { 1606 if (ring->tx_ring_offline & NXGE_TX_RING_OFFLINED) { 1607 break; 1608 } 1609 1610 drv_usecwait(1000); 1611 } 1612 1613 if (count == 0) { 1614 (void) atomic_swap_32(&ring->tx_ring_offline, 1615 NXGE_TX_RING_ONLINE); 1616 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1617 "nxge_hio_tdc_share: " 1618 "Tx ring %d was always BUSY", channel)); 1619 return (-EIO); 1620 } 1621 } else { 1622 (void) atomic_swap_32(&ring->tx_ring_offline, 1623 NXGE_TX_RING_OFFLINED); 1624 } 1625 1626 MUTEX_ENTER(&nhd->lock); 1627 nxge->tdc_is_shared[channel] = B_TRUE; 1628 MUTEX_EXIT(&nhd->lock); 1629 1630 1631 if (nxge_intr_remove(nxge, VP_BOUND_TX, channel) != NXGE_OK) { 1632 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_tdc_share: " 1633 "Failed to remove interrupt for TxDMA channel %d", 1634 channel)); 1635 return (NXGE_ERROR); 1636 } 1637 1638 /* Disable TxDMA A.9.6.10 */ 1639 (void) nxge_txdma_channel_disable(nxge, channel); 1640 1641 /* The SD is sharing this channel. */ 1642 NXGE_DC_SET(set->shared.map, channel); 1643 set->shared.count++; 1644 1645 /* Soft Reset TxDMA A.9.6.2 */ 1646 nxge_grp_dc_remove(nxge, VP_BOUND_TX, channel); 1647 1648 /* 1649 * Initialize the DC-specific FZC control registers. 1650 * ----------------------------------------------------- 1651 */ 1652 if (nxge_init_fzc_tdc(nxge, channel) != NXGE_OK) { 1653 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1654 "nxge_hio_tdc_share: FZC TDC failed: %d", channel)); 1655 return (-EIO); 1656 } 1657 1658 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_tdc_share")); 1659 1660 return (0); 1661 } 1662 1663 /* 1664 * nxge_hio_rdc_share 1665 * 1666 * Share an unused RDC channel. 1667 * 1668 * Arguments: 1669 * nxge 1670 * 1671 * Notes: 1672 * 1673 * This is the latest version of the procedure to 1674 * Reconfigure an Rx DMA channel: 1675 * 1676 * A.6.3 Reconfigure Rx DMA channel 1677 * Stop RxMAC A.9.2.6 1678 * Drain IPP Port A.9.3.6 1679 * Stop and reset RxDMA A.9.5.3 1680 * 1681 * This procedure will be executed by nxge_init_rxdma_channel() in the 1682 * guest domain: 1683 * 1684 * Initialize RxDMA A.9.5.4 1685 * Reconfigure RxDMA 1686 * Enable RxDMA A.9.5.5 1687 * 1688 * We will do this here, since the RDC is a canalis non grata: 1689 * Enable RxMAC A.9.2.10 1690 * 1691 * Context: 1692 * Service domain 1693 */ 1694 int 1695 nxge_hio_rdc_share( 1696 nxge_t *nxge, 1697 nxge_hio_vr_t *vr, 1698 int channel) 1699 { 1700 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 1701 nxge_hw_pt_cfg_t *hardware = &nxge->pt_config.hw_config; 1702 nxge_grp_set_t *set = &nxge->rx_set; 1703 nxge_rdc_grp_t *rdc_grp; 1704 1705 int current, last; 1706 1707 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_rdc_share")); 1708 1709 /* Disable interrupts. */ 1710 if (nxge_intr_remove(nxge, VP_BOUND_RX, channel) != NXGE_OK) { 1711 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_rdc_share: " 1712 "Failed to remove interrupt for RxDMA channel %d", 1713 channel)); 1714 return (NXGE_ERROR); 1715 } 1716 1717 /* Stop RxMAC = A.9.2.6 */ 1718 if (nxge_rx_mac_disable(nxge) != NXGE_OK) { 1719 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_rdc_share: " 1720 "Failed to disable RxMAC")); 1721 } 1722 1723 /* Drain IPP Port = A.9.3.6 */ 1724 (void) nxge_ipp_drain(nxge); 1725 1726 /* Stop and reset RxDMA = A.9.5.3 */ 1727 // De-assert EN: RXDMA_CFIG1[31] = 0 (DMC+00000 ) 1728 if (nxge_disable_rxdma_channel(nxge, channel) != NXGE_OK) { 1729 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_rdc_share: " 1730 "Failed to disable RxDMA channel %d", channel)); 1731 } 1732 1733 /* The SD is sharing this channel. */ 1734 NXGE_DC_SET(set->shared.map, channel); 1735 set->shared.count++; 1736 1737 // Assert RST: RXDMA_CFIG1[30] = 1 1738 nxge_grp_dc_remove(nxge, VP_BOUND_RX, channel); 1739 1740 /* 1741 * We have to reconfigure the RDC table(s) 1742 * to which this channel belongs. 1743 */ 1744 current = hardware->def_mac_rxdma_grpid; 1745 last = current + hardware->max_rdc_grpids; 1746 for (; current < last; current++) { 1747 if (nhd->rdc_tbl[current].nxge == (uintptr_t)nxge) { 1748 rdc_grp = &nxge->pt_config.rdc_grps[current]; 1749 rdc_grp->map = set->owned.map; 1750 rdc_grp->max_rdcs--; 1751 (void) nxge_init_fzc_rdc_tbl(nxge, current); 1752 } 1753 } 1754 1755 /* 1756 * The guest domain will reconfigure the RDC later. 1757 * 1758 * But in the meantime, we must re-enable the Rx MAC so 1759 * that we can start receiving packets again on the 1760 * remaining RDCs: 1761 * 1762 * Enable RxMAC = A.9.2.10 1763 */ 1764 if (nxge_rx_mac_enable(nxge) != NXGE_OK) { 1765 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1766 "nxge_hio_rdc_share: Rx MAC still disabled")); 1767 } 1768 1769 /* 1770 * Initialize the DC-specific FZC control registers. 1771 * ----------------------------------------------------- 1772 */ 1773 if (nxge_init_fzc_rdc(nxge, channel) != NXGE_OK) { 1774 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1775 "nxge_hio_rdc_share: RZC RDC failed: %ld", channel)); 1776 return (-EIO); 1777 } 1778 1779 /* 1780 * We have to initialize the guest's RDC table, too. 1781 * ----------------------------------------------------- 1782 */ 1783 rdc_grp = &nxge->pt_config.rdc_grps[vr->rdc_tbl]; 1784 if (rdc_grp->max_rdcs == 0) { 1785 rdc_grp->start_rdc = (uint8_t)channel; 1786 rdc_grp->def_rdc = (uint8_t)channel; 1787 rdc_grp->max_rdcs = 1; 1788 } else { 1789 rdc_grp->max_rdcs++; 1790 } 1791 NXGE_DC_SET(rdc_grp->map, channel); 1792 1793 if (nxge_init_fzc_rdc_tbl(nxge, vr->rdc_tbl) != NXGE_OK) { 1794 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1795 "nxge_hio_rdc_share: nxge_init_fzc_rdc_tbl failed")); 1796 return (-EIO); 1797 } 1798 1799 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_rdc_share")); 1800 1801 return (0); 1802 } 1803 1804 /* 1805 * nxge_hio_dc_share 1806 * 1807 * Share a DMA channel with a guest domain. 1808 * 1809 * Arguments: 1810 * nxge 1811 * vr The VR that <channel> will belong to. 1812 * type Tx or Rx. 1813 * res_map The resource map used by the caller, which we will 1814 * update if successful. 1815 * 1816 * Notes: 1817 * 1818 * Context: 1819 * Service domain 1820 */ 1821 int 1822 nxge_hio_dc_share( 1823 nxge_t *nxge, 1824 nxge_hio_vr_t *vr, 1825 mac_ring_type_t type) 1826 { 1827 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 1828 nxge_hw_pt_cfg_t *hardware; 1829 nxge_hio_dc_t *dc; 1830 int channel, limit; 1831 1832 nxge_grp_set_t *set; 1833 nxge_grp_t *group; 1834 1835 int slot; 1836 1837 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_dc_share(%cdc %d", 1838 type == MAC_RING_TYPE_TX ? 't' : 'r', channel)); 1839 1840 /* 1841 * In version 1.0, we may only give a VR 2 RDCs or TDCs. 1842 * Not only that, but the HV has statically assigned the 1843 * channels like so: 1844 * VR0: RDC0 & RDC1 1845 * VR1: RDC2 & RDC3, etc. 1846 * The TDCs are assigned in exactly the same way. 1847 * 1848 * So, for example 1849 * hardware->start_rdc + vr->region * 2; 1850 * VR1: hardware->start_rdc + 1 * 2; 1851 * VR3: hardware->start_rdc + 3 * 2; 1852 * If start_rdc is 0, we end up with 2 or 6. 1853 * If start_rdc is 8, we end up with 10 or 14. 1854 */ 1855 1856 set = (type == MAC_RING_TYPE_TX ? &nxge->tx_set : &nxge->rx_set); 1857 hardware = &nxge->pt_config.hw_config; 1858 1859 // This code is still NIU-specific (assuming only 2 ports) 1860 channel = hardware->start_rdc + (vr->region % 4) * 2; 1861 limit = channel + 2; 1862 1863 MUTEX_ENTER(&nhd->lock); 1864 for (; channel < limit; channel++) { 1865 if ((1 << channel) & set->owned.map) { 1866 break; 1867 } 1868 } 1869 1870 if (channel == limit) { 1871 MUTEX_EXIT(&nhd->lock); 1872 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 1873 "nxge_hio_dc_share: there are no channels to share")); 1874 return (-EIO); 1875 } 1876 1877 MUTEX_EXIT(&nhd->lock); 1878 1879 /* -------------------------------------------------- */ 1880 slot = (type == MAC_RING_TYPE_TX) ? 1881 nxge_hio_tdc_share(nxge, channel) : 1882 nxge_hio_rdc_share(nxge, vr, channel); 1883 1884 if (slot < 0) { 1885 if (type == MAC_RING_TYPE_RX) { 1886 nxge_hio_rdc_unshare(nxge, channel); 1887 } else { 1888 nxge_hio_tdc_unshare(nxge, channel); 1889 } 1890 return (slot); 1891 } 1892 1893 MUTEX_ENTER(&nhd->lock); 1894 1895 /* 1896 * Tag this channel. 1897 * -------------------------------------------------- 1898 */ 1899 dc = type == MAC_RING_TYPE_TX ? &nhd->tdc[channel] : &nhd->rdc[channel]; 1900 1901 dc->vr = vr; 1902 dc->channel = (nxge_channel_t)channel; 1903 1904 MUTEX_EXIT(&nhd->lock); 1905 1906 /* 1907 * vr->[t|r]x_group is used by the service domain to 1908 * keep track of its shared DMA channels. 1909 */ 1910 MUTEX_ENTER(&nxge->group_lock); 1911 group = (type == MAC_RING_TYPE_TX ? &vr->tx_group : &vr->rx_group); 1912 1913 dc->group = group; 1914 1915 /* Initialize <group>, if necessary */ 1916 if (group->count == 0) { 1917 group->nxge = nxge; 1918 group->type = (type == MAC_RING_TYPE_TX) ? 1919 VP_BOUND_TX : VP_BOUND_RX; 1920 group->sequence = nhd->sequence++; 1921 group->active = B_TRUE; 1922 } 1923 1924 MUTEX_EXIT(&nxge->group_lock); 1925 1926 NXGE_ERROR_MSG((nxge, HIO_CTL, 1927 "DC share: %cDC %d was assigned to slot %d", 1928 type == MAC_RING_TYPE_TX ? 'T' : 'R', channel, slot)); 1929 1930 nxge_grp_dc_append(nxge, group, dc); 1931 1932 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_dc_share")); 1933 1934 return (0); 1935 } 1936 1937 /* 1938 * nxge_hio_tdc_unshare 1939 * 1940 * Unshare a TDC. 1941 * 1942 * Arguments: 1943 * nxge 1944 * channel The channel to unshare (add again). 1945 * 1946 * Notes: 1947 * 1948 * Context: 1949 * Service domain 1950 */ 1951 void 1952 nxge_hio_tdc_unshare( 1953 nxge_t *nxge, 1954 int channel) 1955 { 1956 nxge_grp_set_t *set = &nxge->tx_set; 1957 nxge_grp_t *group = set->group[0]; 1958 1959 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_tdc_unshare")); 1960 1961 NXGE_DC_RESET(set->shared.map, channel); 1962 set->shared.count--; 1963 1964 if ((nxge_grp_dc_add(nxge, group, VP_BOUND_TX, channel))) { 1965 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_tdc_unshare: " 1966 "Failed to initialize TxDMA channel %d", channel)); 1967 return; 1968 } 1969 1970 /* Re-add this interrupt. */ 1971 if (nxge_intr_add(nxge, VP_BOUND_TX, channel) != NXGE_OK) { 1972 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_tdc_unshare: " 1973 "Failed to add interrupt for TxDMA channel %d", channel)); 1974 } 1975 1976 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_tdc_unshare")); 1977 } 1978 1979 /* 1980 * nxge_hio_rdc_unshare 1981 * 1982 * Unshare an RDC: add it to the SD's RDC groups (tables). 1983 * 1984 * Arguments: 1985 * nxge 1986 * channel The channel to unshare (add again). 1987 * 1988 * Notes: 1989 * 1990 * Context: 1991 * Service domain 1992 */ 1993 void 1994 nxge_hio_rdc_unshare( 1995 nxge_t *nxge, 1996 int channel) 1997 { 1998 nxge_hio_data_t *nhd = (nxge_hio_data_t *)nxge->nxge_hw_p->hio; 1999 nxge_hw_pt_cfg_t *hardware = &nxge->pt_config.hw_config; 2000 2001 nxge_grp_set_t *set = &nxge->rx_set; 2002 nxge_grp_t *group = set->group[0]; 2003 int current, last; 2004 2005 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_rdc_unshare")); 2006 2007 /* Stop RxMAC = A.9.2.6 */ 2008 if (nxge_rx_mac_disable(nxge) != NXGE_OK) { 2009 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_rdc_unshare: " 2010 "Failed to disable RxMAC")); 2011 } 2012 2013 /* Drain IPP Port = A.9.3.6 */ 2014 (void) nxge_ipp_drain(nxge); 2015 2016 /* Stop and reset RxDMA = A.9.5.3 */ 2017 // De-assert EN: RXDMA_CFIG1[31] = 0 (DMC+00000 ) 2018 if (nxge_disable_rxdma_channel(nxge, channel) != NXGE_OK) { 2019 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_rdc_unshare: " 2020 "Failed to disable RxDMA channel %d", channel)); 2021 } 2022 2023 NXGE_DC_RESET(set->shared.map, channel); 2024 set->shared.count--; 2025 2026 /* 2027 * Assert RST: RXDMA_CFIG1[30] = 1 2028 * 2029 * Initialize RxDMA A.9.5.4 2030 * Reconfigure RxDMA 2031 * Enable RxDMA A.9.5.5 2032 */ 2033 if ((nxge_grp_dc_add(nxge, group, VP_BOUND_RX, channel))) { 2034 /* Be sure to re-enable the RX MAC. */ 2035 if (nxge_rx_mac_enable(nxge) != NXGE_OK) { 2036 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 2037 "nxge_hio_rdc_unshare: Rx MAC still disabled")); 2038 } 2039 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, "nxge_hio_rdc_unshare: " 2040 "Failed to initialize RxDMA channel %d", channel)); 2041 return; 2042 } 2043 2044 /* 2045 * We have to reconfigure the RDC table(s) 2046 * to which this channel once again belongs. 2047 */ 2048 current = hardware->def_mac_rxdma_grpid; 2049 last = current + hardware->max_rdc_grpids; 2050 for (; current < last; current++) { 2051 if (nhd->rdc_tbl[current].nxge == (uintptr_t)nxge) { 2052 nxge_rdc_grp_t *group; 2053 group = &nxge->pt_config.rdc_grps[current]; 2054 group->map = set->owned.map; 2055 group->max_rdcs++; 2056 (void) nxge_init_fzc_rdc_tbl(nxge, current); 2057 } 2058 } 2059 2060 /* 2061 * Enable RxMAC = A.9.2.10 2062 */ 2063 if (nxge_rx_mac_enable(nxge) != NXGE_OK) { 2064 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 2065 "nxge_hio_rdc_unshare: Rx MAC still disabled")); 2066 return; 2067 } 2068 2069 /* Re-add this interrupt. */ 2070 if (nxge_intr_add(nxge, VP_BOUND_RX, channel) != NXGE_OK) { 2071 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 2072 "nxge_hio_rdc_unshare: Failed to add interrupt for " 2073 "RxDMA CHANNEL %d", channel)); 2074 } 2075 2076 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_rdc_unshare")); 2077 } 2078 2079 /* 2080 * nxge_hio_dc_unshare 2081 * 2082 * Unshare (reuse) a DMA channel. 2083 * 2084 * Arguments: 2085 * nxge 2086 * vr The VR that <channel> belongs to. 2087 * type Tx or Rx. 2088 * channel The DMA channel to reuse. 2089 * 2090 * Notes: 2091 * 2092 * Context: 2093 * Service domain 2094 */ 2095 void 2096 nxge_hio_dc_unshare( 2097 nxge_t *nxge, 2098 nxge_hio_vr_t *vr, 2099 mac_ring_type_t type, 2100 int channel) 2101 { 2102 nxge_grp_t *group; 2103 nxge_hio_dc_t *dc; 2104 2105 NXGE_DEBUG_MSG((nxge, HIO_CTL, "==> nxge_hio_dc_unshare(%cdc %d)", 2106 type == MAC_RING_TYPE_TX ? 't' : 'r', channel)); 2107 2108 /* Unlink the channel from its group. */ 2109 /* -------------------------------------------------- */ 2110 group = (type == MAC_RING_TYPE_TX) ? &vr->tx_group : &vr->rx_group; 2111 NXGE_DC_RESET(group->map, channel); 2112 if ((dc = nxge_grp_dc_unlink(nxge, group, channel)) == 0) { 2113 NXGE_ERROR_MSG((nxge, NXGE_ERR_CTL, 2114 "nxge_hio_dc_unshare(%d) failed", channel)); 2115 return; 2116 } 2117 2118 dc->vr = 0; 2119 dc->cookie = 0; 2120 2121 if (type == MAC_RING_TYPE_RX) { 2122 nxge_hio_rdc_unshare(nxge, channel); 2123 } else { 2124 nxge_hio_tdc_unshare(nxge, channel); 2125 } 2126 2127 NXGE_DEBUG_MSG((nxge, HIO_CTL, "<== nxge_hio_dc_unshare")); 2128 } 2129 2130 #endif /* if defined(sun4v) */ 2131