1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _NPI_VIR_H 27 #define _NPI_VIR_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <npi.h> 34 #include <nxge_hw.h> 35 36 /* 37 * Virtualization and Logical devices NPI error codes 38 */ 39 #define FUNCID_INVALID PORT_INVALID 40 #define VIR_ERR_ST (VIR_BLK_ID << NPI_BLOCK_ID_SHIFT) 41 #define VIR_ID_SHIFT(n) (n << NPI_PORT_CHAN_SHIFT) 42 43 #define VIR_HW_BUSY (NPI_BK_HW_ERROR_START | 0x1) 44 45 #define VIR_TAS_BUSY (NPI_BK_ERROR_START | 0x1) 46 #define VIR_TAS_NOTREAD (NPI_BK_ERROR_START | 0x2) 47 48 #define VIR_SR_RESET (NPI_BK_ERROR_START | 0x3) 49 #define VIR_SR_FREE (NPI_BK_ERROR_START | 0x4) 50 #define VIR_SR_BUSY (NPI_BK_ERROR_START | 0x5) 51 #define VIR_SR_INVALID (NPI_BK_ERROR_START | 0x6) 52 #define VIR_SR_NOTOWNER (NPI_BK_ERROR_START | 0x7) 53 #define VIR_SR_INITIALIZED (NPI_BK_ERROR_START | 0x8) 54 55 #define VIR_MPC_DENY (NPI_BK_ERROR_START | 0x10) 56 57 #define VIR_BD_FUNC_INVALID (NPI_BK_ERROR_START | 0x20) 58 #define VIR_BD_REG_INVALID (NPI_BK_ERROR_START | 0x21) 59 #define VIR_BD_ID_INVALID (NPI_BK_ERROR_START | 0x22) 60 #define VIR_BD_TXDMA_INVALID (NPI_BK_ERROR_START | 0x23) 61 #define VIR_BD_RXDMA_INVALID (NPI_BK_ERROR_START | 0x24) 62 63 #define VIR_LD_INVALID (NPI_BK_ERROR_START | 0x30) 64 #define VIR_LDG_INVALID (NPI_BK_ERROR_START | 0x31) 65 #define VIR_LDSV_INVALID (NPI_BK_ERROR_START | 0x32) 66 67 #define VIR_INTM_TM_INVALID (NPI_BK_ERROR_START | 0x33) 68 #define VIR_TM_RES_INVALID (NPI_BK_ERROR_START | 0x34) 69 #define VIR_SID_VEC_INVALID (NPI_BK_ERROR_START | 0x35) 70 71 #define NPI_VIR_OCODE_INVALID(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | OPCODE_INVALID) 72 #define NPI_VIR_FUNC_INVALID(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | FUNCID_INVALID) 73 #define NPI_VIR_CN_INVALID(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | CHANNEL_INVALID) 74 75 /* 76 * Errors codes of shared register functions. 77 */ 78 #define NPI_VIR_TAS_BUSY(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_TAS_BUSY) 79 #define NPI_VIR_TAS_NOTREAD(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_TAS_NOTREAD) 80 #define NPI_VIR_SR_RESET(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_RESET) 81 #define NPI_VIR_SR_FREE(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_FREE) 82 #define NPI_VIR_SR_BUSY(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_BUSY) 83 #define NPI_VIR_SR_INVALID(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_INVALID) 84 #define NPI_VIR_SR_NOTOWNER(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_SR_NOTOWNER) 85 #define NPI_VIR_SR_INITIALIZED(n) (VIR_ID_SHIFT(n) | \ 86 VIR_ERR_ST | VIR_SR_INITIALIZED) 87 88 /* 89 * Error codes of muti-partition control register functions. 90 */ 91 #define NPI_VIR_MPC_DENY (VIR_ERR_ST | VIR_MPU_DENY) 92 93 /* 94 * Error codes of DMA binding functions. 95 */ 96 #define NPI_VIR_BD_FUNC_INVALID(n) (VIR_ID_SHIFT(n) | \ 97 VIR_ERR_ST | VIR_BD_FUNC_INVALID) 98 #define NPI_VIR_BD_REG_INVALID(n) (VIR_ID_SHIFT(n) | \ 99 VIR_ERR_ST | VIR_BD_REG_INVALID) 100 #define NPI_VIR_BD_ID_INVALID(n) (VIR_ID_SHIFT(n) | \ 101 VIR_ERR_ST | VIR_BD_ID_INVALID) 102 #define NPI_VIR_BD_TXDMA_INVALID(n) (VIR_ID_SHIFT(n) | \ 103 VIR_ERR_ST | VIR_BD_TXDMA_INVALID) 104 #define NPI_VIR_BD_RXDMA_INVALID(n) (VIR_ID_SHIFT(n) | \ 105 VIR_ERR_ST | VIR_BD_RXDMA_INVALID) 106 107 /* 108 * Error codes of logical devices and groups functions. 109 */ 110 #define NPI_VIR_LD_INVALID(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_LD_INVALID) 111 #define NPI_VIR_LDG_INVALID(n) (VIR_ID_SHIFT(n) | VIR_ERR_ST | VIR_LDG_INVALID) 112 #define NPI_VIR_LDSV_INVALID(n) (VIR_ID_SHIFT(n) | \ 113 VIR_ERR_ST | VIR_LDSV_INVALID) 114 #define NPI_VIR_INTM_TM_INVALID(n) (VIR_ID_SHIFT(n) | \ 115 VIR_ERR_ST | VIR_INTM_TM_INVALID) 116 #define NPI_VIR_TM_RES_INVALID (VIR_ERR_ST | VIR_TM_RES_INVALID) 117 #define NPI_VIR_SID_VEC_INVALID(n) (VIR_ID_SHIFT(n) | \ 118 VIR_ERR_ST | VIR_TM_RES_INVALID) 119 120 /* 121 * Bit definition ([15:0] of the shared register 122 * used by the driver as locking mechanism. 123 * [1:0] lock state (RESET, FREE, BUSY) 124 * [3:2] function ID (owner) 125 * [11:4] Implementation specific states 126 * [15:12] Individual function state 127 */ 128 #define NPI_DEV_SR_LOCK_ST_RESET 0 129 #define NPI_DEV_SR_LOCK_ST_FREE 1 130 #define NPI_DEV_SR_LOCK_ST_BUSY 2 131 132 #define NPI_DEV_SR_LOCK_ST_SHIFT 0 133 #define NPI_DEV_SR_LOCK_ST_MASK 0x03 134 #define NPI_DEV_SR_LOCK_FID_SHIFT 2 135 #define NPI_DEV_SR_LOCK_FID_MASK 0x0C 136 137 #define NPI_DEV_SR_IMPL_ST_SHIFT 4 138 #define NPI_DEV_SR_IMPL_ST_MASK 0xfff0 139 140 #define NPI_GET_LOCK_OWNER(sr) ((sr & NPI_DEV_SR_LOCK_FID_MASK) \ 141 >> NPI_DEV_SR_LOCK_FID_SHIFT) 142 #define NPI_GET_LOCK_ST(sr) (sr & NPI_DEV_SR_LOCK_ST_MASK) 143 #define NPI_GET_LOCK_IMPL_ST(sr) ((sr & NPI_DEV_SR_IMPL_ST_MASK) \ 144 >> NPI_DEV_SR_IMPL_ST_SHIFT) 145 146 /* 147 * DMA channel binding definitions. 148 */ 149 #define DMA_BIND_VADDR_VALIDATE(fn, rn, id, status) \ 150 { \ 151 status = NPI_SUCCESS; \ 152 if (!TXDMA_FUNC_VALID(fn)) { \ 153 status = (NPI_FAILURE | NPI_VIR_BD_FUNC_INVALID(fn)); \ 154 } else if (!SUBREGION_VALID(rn)) { \ 155 status = (NPI_FAILURE | NPI_VIR_BD_REG_INVALID(rn)); \ 156 } else if (!VIR_PAGE_INDEX_VALID(id)) { \ 157 status = (NPI_FAILURE | NPI_VIR_BD_ID_INVALID(id)); \ 158 } \ 159 } 160 161 #define DMA_BIND_TX_VALIDATE(n, status) \ 162 { \ 163 status = NPI_SUCCESS; \ 164 if (!TXDMA_CHANNEL_VALID(n)) { \ 165 status = (NPI_FAILURE | NPI_VIR_BD_TXDMA_INVALID(n)); \ 166 } \ 167 } 168 169 #define DMA_BIND_RX_VALIDATE(n, status) \ 170 { \ 171 status = NPI_SUCCESS; \ 172 if (!VRXDMA_CHANNEL_VALID(n)) { \ 173 status = (NPI_FAILURE | NPI_VIR_BD_RXDMA_INVALID(n)); \ 174 } \ 175 } 176 177 #define DMA_BIND_STEP 8 178 #define DMA_BIND_REG_OFFSET(fn, rn, id) (DMA_BIND_STEP * \ 179 (fn * 2 * VIR_PAGE_INDEX_MAX + \ 180 rn * VIR_PAGE_INDEX_MAX) + id) 181 182 /* 183 * NPI defined data structure to program the DMA binding register. 184 */ 185 typedef struct _fzc_dma_bind { 186 uint8_t function_id; /* 0 to 3 */ 187 uint8_t sub_vir_region; /* 0 or 1 */ 188 uint8_t vir_index; /* 0 to 7 */ 189 boolean_t tx_bind; /* set 1 to bind */ 190 uint8_t tx_channel; /* hardware channel number (0 - 23) */ 191 boolean_t rx_bind; /* set 1 to bind */ 192 uint8_t rx_channel; /* hardware channel number (0 - 15) */ 193 } fzc_dma_bind_t, *p_fzc_dma_bind; 194 195 /* 196 * Logical device definitions. 197 */ 198 #define LD_NUM_STEP 8 199 #define LD_NUM_OFFSET(ld) (ld * LDG_NUM_STEP) 200 #define LDG_NUM_STEP 8 201 #define LDG_NUM_OFFSET(ldg) (ldg * LDG_NUM_STEP) 202 #define LDGNUM_OFFSET(ldg) (ldg * LDG_NUM_STEP) 203 #define LDSV_STEP 8192 204 #define LDSVG_OFFSET(ldg) (ldg * LDSV_STEP) 205 #define LDSV_OFFSET(ldv) (ldv * LDSV_STEP) 206 207 #define LDSV_OFFSET_MASK(ld) \ 208 (((ld < NXGE_MAC_LD_START) ? \ 209 (LD_IM0_REG + LDSV_OFFSET(ld)) : \ 210 (LD_IM1_REG + LDSV_OFFSET((ld - NXGE_MAC_LD_START))))); \ 211 212 #define LDG_SID_STEP 8 213 #define LDG_SID_OFFSET(ldg) (ldg * LDG_SID_STEP) 214 215 typedef enum { 216 LDF0, 217 LDF1 218 } ldf_type_t; 219 220 typedef enum { 221 VECTOR0, 222 VECTOR1, 223 VECTOR2 224 } ldsv_type_t; 225 226 /* 227 * Definitions for the system interrupt data. 228 */ 229 typedef struct _fzc_sid { 230 boolean_t niu; 231 uint8_t ldg; 232 uint8_t func; 233 uint8_t vector; 234 } fzc_sid_t, *p_fzc_sid_t; 235 236 /* 237 * Virtualization and Interrupt Prototypes. 238 */ 239 /* 240 * npi_dev_func_sr_init(): 241 * This function is called to initialize the device function 242 * shared register (set the software implementation lock 243 * state to FREE). 244 * Parameters: 245 * handle - NPI handle 246 * Return: 247 * NPI_SUCCESS - If initialization is complete successfully. 248 * (set sr bits to free). 249 * Error: 250 * NPI_FAILURE 251 * VIR_TAS_BUSY 252 */ 253 npi_status_t npi_dev_func_sr_init(npi_handle_t); 254 255 /* 256 * npi_dev_func_sr_lock_enter(): 257 * This function is called to lock the function shared register 258 * by setting the lock state to busy. 259 * Parameters: 260 * handle - NPI handle 261 * Return: 262 * NPI_SUCCESS - If the function id can own the lock. 263 * 264 * Error: 265 * NPI_FAILURE 266 * VIR_SR_RESET 267 * VIR_SR_BUSY 268 * VIR_SR_INVALID 269 * VIR_TAS_BUSY 270 */ 271 npi_status_t npi_dev_func_sr_lock_enter(npi_handle_t); 272 273 /* 274 * npi_dev_func_sr_lock_free(): 275 * This function is called to free the function shared register 276 * by setting the lock state to free. 277 * Parameters: 278 * handle - NPI handle 279 * Return: 280 * NPI_SUCCESS - If the function id can free the lock. 281 * 282 * Error: 283 * NPI_FAILURE 284 * VIR_SR_NOTOWNER 285 * VIR_TAS_NOTREAD 286 */ 287 npi_status_t npi_dev_func_sr_lock_free(npi_handle_t); 288 289 /* 290 * npi_dev_func_sr_funcid_get(): 291 * This function is called to get the caller's function ID. 292 * (based on address bits [25:26] on read access. 293 * (After read, the TAS bit is always set to 1. Software needs 294 * to write 0 to clear.) This function will write 0 to clear 295 * the TAS bit if we own it. 296 * Parameters: 297 * handle - NPI handle 298 * funcid_p - pointer to store the function id. 299 * Return: 300 * NPI_SUCCESS - If get function id is complete successfully. 301 * 302 * Error: 303 */ 304 npi_status_t npi_dev_func_sr_funcid_get(npi_handle_t, uint8_t *); 305 306 /* 307 * npi_dev_func_sr_sr_raw_get(): 308 * This function is called to get the shared register value. 309 * (After read, the TAS bit is always set to 1. Software needs 310 * to write 0 to clear if we own it.) 311 * 312 * Parameters: 313 * handle - NPI handle 314 * sr_p - pointer to store the shared value of this register. 315 * 316 * Return: 317 * NPI_SUCCESS - If shared value get is complete successfully. 318 * 319 * Error: 320 */ 321 npi_status_t npi_dev_func_sr_sr_raw_get(npi_handle_t, uint16_t *); 322 323 /* 324 * npi_dev_func_sr_sr_get(): 325 * This function is called to get the shared register value. 326 * (After read, the TAS bit is always set to 1. Software needs 327 * to write 0 to clear if we own it.) 328 * 329 * Parameters: 330 * handle - NPI handle 331 * sr_p - pointer to store the shared value of this register. 332 * . this will get only non-lock, non-function id portion 333 * . of the register 334 * 335 * 336 * Return: 337 * NPI_SUCCESS - If shared value get is complete successfully. 338 * 339 * Error: 340 */ 341 342 npi_status_t npi_dev_func_sr_sr_get(npi_handle_t, uint16_t *); 343 344 /* 345 * npi_dev_func_sr_sr_get_set_clear(): 346 * This function is called to set the shared register value. 347 * (Shared register must be read first. If tas bit is 0, then 348 * it implies that the software can proceed to set). After 349 * setting, tas bit will be cleared. 350 * Parameters: 351 * handle - NPI handle 352 * impl_sr - shared value to set (only the 8 bit 353 * implementation specific state info). 354 * 355 * Return: 356 * NPI_SUCCESS - If shared value is set successfully. 357 * 358 * Error: 359 * NPI_FAILURE 360 * VIR_TAS_BUSY 361 */ 362 npi_status_t npi_dev_func_sr_sr_get_set_clear(npi_handle_t, 363 uint16_t); 364 365 /* 366 * npi_dev_func_sr_sr_set_only(): 367 * This function is called to only set the shared register value. 368 * Parameters: 369 * handle - NPI handle 370 * impl_sr - shared value to set. 371 * 372 * Return: 373 * NPI_SUCCESS - If shared value is set successfully. 374 * 375 * Error: 376 * NPI_FAILURE 377 * VIR_TAS_BUSY 378 */ 379 npi_status_t npi_dev_func_sr_sr_set_only(npi_handle_t, uint16_t); 380 381 /* 382 * npi_dev_func_sr_busy(): 383 * This function is called to see if we can own the device. 384 * It will not reset the tas bit. 385 * Parameters: 386 * handle - NPI handle 387 * busy_p - pointer to store busy flag. 388 * (B_TRUE: device is in use, B_FALSE: free). 389 * Return: 390 * NPI_SUCCESS - If tas bit is read successfully. 391 * Error: 392 */ 393 npi_status_t npi_dev_func_sr_busy(npi_handle_t, boolean_t *); 394 395 /* 396 * npi_dev_func_sr_tas_get(): 397 * This function is called to get the tas bit 398 * (after read, this bit is always set to 1, software write 0 399 * to clear it). 400 * 401 * Parameters: 402 * handle - NPI handle 403 * tas_p - pointer to store the tas value 404 * 405 * Return: 406 * NPI_SUCCESS - If tas value get is complete successfully. 407 * Error: 408 */ 409 npi_status_t npi_dev_func_sr_tas_get(npi_handle_t, uint8_t *); 410 411 /* 412 * npi_fzc_mpc_set(): 413 * This function is called to enable the write access 414 * to FZC region to function zero. 415 * Parameters: 416 * handle - NPI handle 417 * Return: 418 * NPI_SUCCESS - 419 * Error: 420 */ 421 npi_status_t npi_fzc_mpc_set(npi_handle_t, boolean_t); 422 423 /* 424 * npi_fzc_mpc_get(): 425 * This function is called to get the access mode. 426 * Parameters: 427 * handle - NPI handle 428 * Return: 429 * NPI_SUCCESS - 430 * 431 */ 432 npi_status_t npi_fzc_mpc_get(npi_handle_t, boolean_t *); 433 434 /* 435 * npi_fzc_dma_bind_set(): 436 * This function is called to set DMA binding register. 437 * Parameters: 438 * handle - NPI handle 439 * dma_bind - NPI defined data structure that 440 * contains the tx/rx channel binding info. 441 * to set. 442 * Return: 443 * NPI_SUCCESS - 444 * Error: 445 * NPI_FAILURE 446 * 447 */ 448 npi_status_t npi_fzc_dma_bind_set(npi_handle_t, fzc_dma_bind_t); 449 450 /* 451 * npi_fzc_dma_bind_get(): 452 * This function is called to get a DMA binding register. 453 * Parameters: 454 * handle - NPI handle 455 * dma_bind - NPI defined data structure that 456 * contains the tx/rx channel binding info. 457 * value - Where to put the register value. 458 * Return: 459 * NPI_SUCCESS - 460 * Error: 461 * NPI_FAILURE 462 * 463 */ 464 npi_status_t npi_fzc_dma_bind_get(npi_handle_t, fzc_dma_bind_t, uint64_t *); 465 466 /* 467 * npi_fzc_ldg_num_set(): 468 * This function is called to set up a logical group number that 469 * a logical device belongs to. 470 * Parameters: 471 * handle - NPI handle 472 * ld - logical device number (0 - 68) 473 * ldg - logical device group number (0 - 63) 474 * Return: 475 * NPI_SUCCESS - 476 * Error: 477 * NPI_FAILURE 478 * 479 */ 480 npi_status_t npi_fzc_ldg_num_set(npi_handle_t, uint8_t, uint8_t); 481 482 /* 483 * npi_fzc_ldg_num_get(): 484 * This function is called to get the logical device group that 485 * a logical device belongs to. 486 * Parameters: 487 * handle - NPI handle 488 * ld - logical device number (0 - 68) 489 * *ldg_p - pointer to store its group number. 490 * Return: 491 * NPI_SUCCESS - 492 * Error: 493 * NPI_FAILURE 494 */ 495 npi_status_t npi_fzc_ldg_num_get(npi_handle_t, uint8_t, 496 uint8_t *); 497 498 npi_status_t npi_ldsv_ldfs_get(npi_handle_t, uint8_t, 499 uint64_t *, uint64_t *, uint64_t *); 500 /* 501 * npi_ldsv_get(): 502 * This function is called to get device state vectors. 503 * Parameters: 504 * handle - NPI handle 505 * ldg - logical device group (0 - 63) 506 * ldf_type - either LDF0 (0) or LDF1 (1) 507 * vector - vector type (0, 1 or 2) 508 * *ldf_p - pointer to store its flag bits. 509 * Return: 510 * NPI_SUCCESS - 511 * Error: 512 * NPI_FAILURE 513 */ 514 npi_status_t npi_ldsv_get(npi_handle_t, uint8_t, ldsv_type_t, 515 uint64_t *); 516 517 /* 518 * npi_ldsv_ld_get(): 519 * This function is called to get the flag bit value of a device. 520 * Parameters: 521 * handle - NPI handle 522 * ldg - logical device group (0 - 63) 523 * ld - logical device (0 - 68) 524 * ldf_type - either LDF0 (0) or LDF1 (1) 525 * vector - vector type (0, 1 or 2) 526 * *ldf_p - pointer to store its flag bits. 527 * Return: 528 * NPI_SUCCESS - 529 * Error: 530 * NPI_FAILURE 531 */ 532 npi_status_t npi_ldsv_ld_get(npi_handle_t, uint8_t, uint8_t, 533 ldsv_type_t, ldf_type_t, boolean_t *); 534 /* 535 * npi_ldsv_ld_ldf0_get(): 536 * This function is called to get the ldf0 bit value of a device. 537 * Parameters: 538 * handle - NPI handle 539 * ldg - logical device group (0 - 63) 540 * ld - logical device (0 - 68) 541 * *ldf_p - pointer to store its flag bits. 542 * Return: 543 * NPI_SUCCESS - 544 * Error: 545 * NPI_FAILURE 546 */ 547 npi_status_t npi_ldsv_ld_ldf0_get(npi_handle_t, uint8_t, uint8_t, 548 boolean_t *); 549 550 /* 551 * npi_ldsv_ld_ldf1_get(): 552 * This function is called to get the ldf1 bit value of a device. 553 * Parameters: 554 * handle - NPI handle 555 * ldg - logical device group (0 - 63) 556 * ld - logical device (0 - 68) 557 * *ldf_p - pointer to store its flag bits. 558 * Return: 559 * NPI_SUCCESS - 560 * Error: 561 * NPI_FAILURE 562 */ 563 npi_status_t npi_ldsv_ld_ldf1_get(npi_handle_t, uint8_t, uint8_t, 564 boolean_t *); 565 /* 566 * npi_intr_mask_set(): 567 * This function is called to select the mask bits for both ldf0 and ldf1. 568 * Parameters: 569 * handle - NPI handle 570 * ld - logical device (0 - 68) 571 * ldf_mask - mask value to set (both ldf0 and ldf1). 572 * Return: 573 * NPI_SUCCESS - 574 * Error: 575 * NPI_FAILURE 576 */ 577 npi_status_t npi_intr_mask_set(npi_handle_t, uint8_t, 578 uint8_t); 579 580 /* 581 * npi_intr_mask_get(): 582 * This function is called to get the mask bits. 583 * Parameters: 584 * handle - NPI handle 585 * ld - logical device (0 - 68) 586 * ldf_mask - pointer to store mask bits info. 587 * Return: 588 * NPI_SUCCESS - 589 * Error: 590 * NPI_FAILURE 591 */ 592 npi_status_t npi_intr_mask_get(npi_handle_t, uint8_t, 593 uint8_t *); 594 595 /* 596 * npi_intr_ldg_mgmt_set(): 597 * This function is called to set interrupt timer and arm bit. 598 * Parameters: 599 * handle - NPI handle 600 * ldg - logical device group (0 - 63) 601 * arm - B_TRUE (arm) B_FALSE (disable) 602 * Return: 603 * NPI_SUCCESS - 604 * Error: 605 * NPI_FAILURE 606 */ 607 npi_status_t npi_intr_ldg_mgmt_set(npi_handle_t, uint8_t, 608 boolean_t, uint8_t); 609 610 611 /* 612 * npi_intr_ldg_mgmt_timer_get(): 613 * This function is called to get the timer counter 614 * Parameters: 615 * handle - NPI handle 616 * ldg - logical device group (0 - 63) 617 * timer_p - pointer to store the timer counter. 618 * Return: 619 * NPI_SUCCESS - 620 * Error: 621 * NPI_FAILURE 622 */ 623 npi_status_t npi_intr_ldg_mgmt_timer_get(npi_handle_t, uint8_t, 624 uint8_t *); 625 626 /* 627 * npi_intr_ldg_mgmt_arm(): 628 * This function is called to arm the group. 629 * Parameters: 630 * handle - NPI handle 631 * ldg - logical device group (0 - 63) 632 * Return: 633 * NPI_SUCCESS - 634 * Error: 635 * NPI_FAILURE 636 */ 637 npi_status_t npi_intr_ldg_mgmt_arm(npi_handle_t, uint8_t); 638 639 /* 640 * npi_fzc_ldg_timer_res_set(): 641 * This function is called to set the timer resolution. 642 * Parameters: 643 * handle - NPI handle 644 * res - timer resolution (# of system clocks) 645 * Return: 646 * NPI_SUCCESS - 647 * Error: 648 * NPI_FAILURE 649 */ 650 npi_status_t npi_fzc_ldg_timer_res_set(npi_handle_t, uint32_t); 651 652 /* 653 * npi_fzc_ldg_timer_res_get(): 654 * This function is called to get the timer resolution. 655 * Parameters: 656 * handle - NPI handle 657 * res_p - pointer to store the timer resolution. 658 * Return: 659 * NPI_SUCCESS - 660 * Error: 661 * NPI_FAILURE 662 */ 663 npi_status_t npi_fzc_ldg_timer_res_get(npi_handle_t, uint8_t *); 664 665 /* 666 * npi_fzc_sid_set(): 667 * This function is called to set the system interrupt data. 668 * Parameters: 669 * handle - NPI handle 670 * ldg - logical group (0 - 63) 671 * sid - NPI defined data to set 672 * Return: 673 * NPI_SUCCESS - 674 * Error: 675 * NPI_FAILURE 676 */ 677 npi_status_t npi_fzc_sid_set(npi_handle_t, fzc_sid_t); 678 679 /* 680 * npi_fzc_sid_get(): 681 * This function is called to get the system interrupt data. 682 * Parameters: 683 * handle - NPI handle 684 * ldg - logical group (0 - 63) 685 * sid_p - NPI defined data to get 686 * Return: 687 * NPI_SUCCESS - 688 * Error: 689 * NPI_FAILURE 690 */ 691 npi_status_t npi_fzc_sid_get(npi_handle_t, p_fzc_sid_t); 692 npi_status_t npi_fzc_sys_err_mask_set(npi_handle_t, uint64_t); 693 npi_status_t npi_fzc_sys_err_stat_get(npi_handle_t, 694 p_sys_err_stat_t); 695 npi_status_t npi_vir_dump_pio_fzc_regs_one(npi_handle_t); 696 npi_status_t npi_vir_dump_ldgnum(npi_handle_t); 697 npi_status_t npi_vir_dump_ldsv(npi_handle_t); 698 npi_status_t npi_vir_dump_imask0(npi_handle_t); 699 npi_status_t npi_vir_dump_sid(npi_handle_t); 700 #ifdef __cplusplus 701 } 702 #endif 703 704 #endif /* _NPI_VIR_H */ 705