1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _NPI_TXDMA_H 27 #define _NPI_TXDMA_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <npi.h> 34 #include <nxge_txdma_hw.h> 35 36 #define DMA_LOG_PAGE_FN_VALIDATE(cn, pn, fn, status) \ 37 { \ 38 status = NPI_SUCCESS; \ 39 if (!TXDMA_CHANNEL_VALID(channel)) { \ 40 status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn)); \ 41 } else if (!TXDMA_PAGE_VALID(pn)) { \ 42 status = (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn)); \ 43 } else if (!TXDMA_FUNC_VALID(fn)) { \ 44 status = (NPI_FAILURE | NPI_TXDMA_FUNC_INVALID(fn)); \ 45 } \ 46 } 47 48 #define DMA_LOG_PAGE_VALIDATE(cn, pn, status) \ 49 { \ 50 status = NPI_SUCCESS; \ 51 if (!TXDMA_CHANNEL_VALID(channel)) { \ 52 status = (NPI_FAILURE | NPI_TXDMA_CHANNEL_INVALID(cn)); \ 53 } else if (!TXDMA_PAGE_VALID(pn)) { \ 54 status = (NPI_FAILURE | NPI_TXDMA_PAGE_INVALID(pn)); \ 55 } \ 56 } 57 58 typedef enum _txdma_cs_cntl_e { 59 TXDMA_INIT_RESET = 0x1, 60 TXDMA_INIT_START = 0x2, 61 TXDMA_START = 0x3, 62 TXDMA_RESET = 0x4, 63 TXDMA_STOP = 0x5, 64 TXDMA_RESUME = 0x6, 65 TXDMA_CLEAR_MMK = 0x7, 66 TXDMA_MBOX_ENABLE = 0x8 67 } txdma_cs_cntl_t; 68 69 typedef enum _txdma_log_cfg_e { 70 TXDMA_LOG_PAGE_MASK = 0x01, 71 TXDMA_LOG_PAGE_VALUE = 0x02, 72 TXDMA_LOG_PAGE_RELOC = 0x04, 73 TXDMA_LOG_PAGE_VALID = 0x08, 74 TXDMA_LOG_PAGE_ALL = (TXDMA_LOG_PAGE_MASK | TXDMA_LOG_PAGE_VALUE | 75 TXDMA_LOG_PAGE_RELOC | TXDMA_LOG_PAGE_VALID) 76 } txdma_log_cfg_t; 77 78 typedef enum _txdma_ent_msk_cfg_e { 79 CFG_TXDMA_PKT_PRT_MASK = TX_ENT_MSK_PKT_PRT_ERR_MASK, 80 CFG_TXDMA_CONF_PART_MASK = TX_ENT_MSK_CONF_PART_ERR_MASK, 81 CFG_TXDMA_NACK_PKT_RD_MASK = TX_ENT_MSK_NACK_PKT_RD_MASK, 82 CFG_TXDMA_NACK_PREF_MASK = TX_ENT_MSK_NACK_PREF_MASK, 83 CFG_TXDMA_PREF_BUF_ECC_ERR_MASK = TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK, 84 CFG_TXDMA_TX_RING_OFLOW_MASK = TX_ENT_MSK_TX_RING_OFLOW_MASK, 85 CFG_TXDMA_PKT_SIZE_ERR_MASK = TX_ENT_MSK_PKT_SIZE_ERR_MASK, 86 CFG_TXDMA_MBOX_ERR_MASK = TX_ENT_MSK_MBOX_ERR_MASK, 87 CFG_TXDMA_MK_MASK = TX_ENT_MSK_MK_MASK, 88 CFG_TXDMA_MASK_ALL = (TX_ENT_MSK_PKT_PRT_ERR_MASK | 89 TX_ENT_MSK_CONF_PART_ERR_MASK | 90 TX_ENT_MSK_NACK_PKT_RD_MASK | 91 TX_ENT_MSK_NACK_PREF_MASK | 92 TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK | 93 TX_ENT_MSK_TX_RING_OFLOW_MASK | 94 TX_ENT_MSK_PKT_SIZE_ERR_MASK | 95 TX_ENT_MSK_MBOX_ERR_MASK | 96 TX_ENT_MSK_MK_MASK) 97 } txdma_ent_msk_cfg_t; 98 99 100 typedef struct _txdma_ring_errlog { 101 tx_rng_err_logl_t logl; 102 tx_rng_err_logh_t logh; 103 } txdma_ring_errlog_t, *p_txdma_ring_errlog_t; 104 105 /* 106 * Register offset (0x200 bytes for each channel) for logical pages registers. 107 */ 108 #define NXGE_TXLOG_OFFSET(x, channel) (x + TX_LOG_DMA_OFFSET(channel)) 109 110 /* 111 * Register offset (0x200 bytes for each channel) for transmit ring registers. 112 * (Ring configuration, kick register, event mask, control and status, 113 * mailbox, prefetch, ring errors). 114 */ 115 #define NXGE_TXDMA_OFFSET(x, v, channel) (x + \ 116 (!v ? DMC_OFFSET(channel) : TDMC_PIOVADDR_OFFSET(channel))) 117 /* 118 * Register offset (0x8 bytes for each port) for transmit mapping registers. 119 */ 120 #define NXGE_TXDMA_MAP_OFFSET(x, port) (x + TX_DMA_MAP_PORT_OFFSET(port)) 121 122 /* 123 * Register offset (0x10 bytes for each channel) for transmit DRR and ring 124 * usage registers. 125 */ 126 #define NXGE_TXDMA_DRR_OFFSET(x, channel) (x + \ 127 TXDMA_DRR_RNG_USE_OFFSET(channel)) 128 129 /* 130 * PIO macros to read and write the transmit registers. 131 */ 132 #define TX_LOG_REG_READ64(handle, reg, channel, val_p) \ 133 NXGE_REG_RD64(handle, NXGE_TXLOG_OFFSET(reg, channel), val_p) 134 135 #define TX_LOG_REG_WRITE64(handle, reg, channel, data) \ 136 NXGE_REG_WR64(handle, NXGE_TXLOG_OFFSET(reg, channel), data) 137 138 /* 139 * Transmit Descriptor Definitions. 140 */ 141 #define TXDMA_DESC_SIZE (sizeof (tx_desc_t)) 142 143 #define NPI_TXDMA_GATHER_INDEX(index) \ 144 ((index <= TX_MAX_GATHER_POINTERS)) ? NPI_SUCCESS : \ 145 (NPI_TXDMA_GATHER_INVALID) 146 147 /* 148 * Transmit NPI error codes 149 */ 150 #define TXDMA_ER_ST (TXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT) 151 #define TXDMA_ID_SHIFT(n) (n << NPI_PORT_CHAN_SHIFT) 152 153 #define TXDMA_HW_STOP_FAILED (NPI_BK_HW_ER_START | 0x1) 154 #define TXDMA_HW_RESUME_FAILED (NPI_BK_HW_ER_START | 0x2) 155 156 #define TXDMA_GATHER_INVALID (NPI_BK_ERROR_START | 0x1) 157 #define TXDMA_XFER_LEN_INVALID (NPI_BK_ERROR_START | 0x2) 158 159 #define NPI_TXDMA_OPCODE_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 160 TXDMA_ER_ST | OPCODE_INVALID) 161 162 #define NPI_TXDMA_FUNC_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 163 TXDMA_ER_ST | PORT_INVALID) 164 #define NPI_TXDMA_CHANNEL_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 165 TXDMA_ER_ST | CHANNEL_INVALID) 166 167 #define NPI_TXDMA_PAGE_INVALID(n) (TXDMA_ID_SHIFT(n) | \ 168 TXDMA_ER_ST | LOGICAL_PAGE_INVALID) 169 170 #define NPI_TXDMA_REGISTER_INVALID (TXDMA_ER_ST | REGISTER_INVALID) 171 #define NPI_TXDMA_COUNTER_INVALID (TXDMA_ER_ST | COUNTER_INVALID) 172 #define NPI_TXDMA_CONFIG_INVALID (TXDMA_ER_ST | CONFIG_INVALID) 173 174 175 #define NPI_TXDMA_GATHER_INVALID (TXDMA_ER_ST | TXDMA_GATHER_INVALID) 176 #define NPI_TXDMA_XFER_LEN_INVALID (TXDMA_ER_ST | TXDMA_XFER_LEN_INVALID) 177 178 #define NPI_TXDMA_RESET_FAILED (TXDMA_ER_ST | RESET_FAILED) 179 #define NPI_TXDMA_STOP_FAILED (TXDMA_ER_ST | TXDMA_HW_STOP_FAILED) 180 #define NPI_TXDMA_RESUME_FAILED (TXDMA_ER_ST | TXDMA_HW_RESUME_FAILED) 181 182 /* 183 * Transmit DMA Channel NPI Prototypes. 184 */ 185 npi_status_t npi_txdma_mode32_set(npi_handle_t, boolean_t); 186 npi_status_t npi_txdma_log_page_set(npi_handle_t, uint8_t, 187 p_dma_log_page_t); 188 npi_status_t npi_txdma_log_page_get(npi_handle_t, uint8_t, 189 p_dma_log_page_t); 190 npi_status_t npi_txdma_log_page_handle_set(npi_handle_t, uint8_t, 191 p_log_page_hdl_t); 192 npi_status_t npi_txdma_log_page_config(npi_handle_t, io_op_t, 193 txdma_log_cfg_t, uint8_t, p_dma_log_page_t); 194 npi_status_t npi_txdma_log_page_vld_config(npi_handle_t, io_op_t, 195 uint8_t, p_log_page_vld_t); 196 npi_status_t npi_txdma_drr_weight_set(npi_handle_t, uint8_t, 197 uint32_t); 198 npi_status_t npi_txdma_channel_reset(npi_handle_t, uint8_t); 199 npi_status_t npi_txdma_channel_init_enable(npi_handle_t, 200 uint8_t); 201 npi_status_t npi_txdma_channel_enable(npi_handle_t, uint8_t); 202 npi_status_t npi_txdma_channel_disable(npi_handle_t, uint8_t); 203 npi_status_t npi_txdma_channel_resume(npi_handle_t, uint8_t); 204 npi_status_t npi_txdma_channel_mmk_clear(npi_handle_t, uint8_t); 205 npi_status_t npi_txdma_channel_mbox_enable(npi_handle_t, uint8_t); 206 npi_status_t npi_txdma_channel_control(npi_handle_t, 207 txdma_cs_cntl_t, uint8_t); 208 npi_status_t npi_txdma_control_status(npi_handle_t, io_op_t, 209 uint8_t, p_tx_cs_t); 210 211 npi_status_t npi_txdma_event_mask(npi_handle_t, io_op_t, 212 uint8_t, p_tx_dma_ent_msk_t); 213 npi_status_t npi_txdma_event_mask_config(npi_handle_t, io_op_t, 214 uint8_t, txdma_ent_msk_cfg_t *); 215 npi_status_t npi_txdma_event_mask_mk_out(npi_handle_t, uint8_t); 216 npi_status_t npi_txdma_event_mask_mk_in(npi_handle_t, uint8_t); 217 218 npi_status_t npi_txdma_ring_addr_set(npi_handle_t, uint8_t, 219 uint64_t, uint32_t); 220 npi_status_t npi_txdma_ring_config(npi_handle_t, io_op_t, 221 uint8_t, uint64_t *); 222 npi_status_t npi_txdma_mbox_config(npi_handle_t, io_op_t, 223 uint8_t, uint64_t *); 224 npi_status_t npi_txdma_desc_gather_set(npi_handle_t, 225 p_tx_desc_t, uint8_t, 226 boolean_t, uint8_t, 227 uint64_t, uint32_t); 228 229 npi_status_t npi_txdma_desc_gather_sop_set(npi_handle_t, 230 p_tx_desc_t, boolean_t, uint8_t); 231 232 npi_status_t npi_txdma_desc_gather_sop_set_1(npi_handle_t, 233 p_tx_desc_t, boolean_t, uint8_t, 234 uint32_t); 235 236 npi_status_t npi_txdma_desc_set_xfer_len(npi_handle_t, 237 p_tx_desc_t, uint32_t); 238 239 npi_status_t npi_txdma_desc_set_zero(npi_handle_t, uint16_t); 240 npi_status_t npi_txdma_desc_mem_get(npi_handle_t, uint16_t, 241 p_tx_desc_t); 242 npi_status_t npi_txdma_desc_kick_reg_set(npi_handle_t, uint8_t, 243 uint16_t, boolean_t); 244 npi_status_t npi_txdma_desc_kick_reg_get(npi_handle_t, uint8_t, 245 p_tx_ring_kick_t); 246 npi_status_t npi_txdma_ring_head_get(npi_handle_t, uint8_t, 247 p_tx_ring_hdl_t); 248 npi_status_t npi_txdma_channel_mbox_get(npi_handle_t, uint8_t, 249 p_txdma_mailbox_t); 250 npi_status_t npi_txdma_channel_pre_state_get(npi_handle_t, 251 uint8_t, p_tx_dma_pre_st_t); 252 npi_status_t npi_txdma_ring_error_get(npi_handle_t, 253 uint8_t, p_txdma_ring_errlog_t); 254 npi_status_t npi_txdma_inj_par_error_clear(npi_handle_t); 255 npi_status_t npi_txdma_inj_par_error_set(npi_handle_t, 256 uint32_t); 257 npi_status_t npi_txdma_inj_par_error_update(npi_handle_t, 258 uint32_t); 259 npi_status_t npi_txdma_inj_par_error_get(npi_handle_t, 260 uint32_t *); 261 npi_status_t npi_txdma_dbg_sel_set(npi_handle_t, uint8_t); 262 npi_status_t npi_txdma_training_vector_set(npi_handle_t, 263 uint32_t); 264 void npi_txdma_dump_desc_one(npi_handle_t, p_tx_desc_t, 265 int); 266 npi_status_t npi_txdma_dump_tdc_regs(npi_handle_t, uint8_t); 267 npi_status_t npi_txdma_dump_fzc_regs(npi_handle_t); 268 npi_status_t npi_txdma_inj_int_error_set(npi_handle_t, uint8_t, 269 p_tdmc_intr_dbg_t); 270 #ifdef __cplusplus 271 } 272 #endif 273 274 #endif /* _NPI_TXDMA_H */ 275