1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _NPI_TXC_H 27 #define _NPI_TXC_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <npi.h> 36 #include <nxge_txc_hw.h> 37 38 /* 39 * Transmit Controller (TXC) NPI error codes 40 */ 41 #define TXC_ER_ST (TXC_BLK_ID << NPI_BLOCK_ID_SHIFT) 42 #define TXC_ID_SHIFT(n) (n << NPI_PORT_CHAN_SHIFT) 43 44 #define NPI_TXC_PORT_INVALID(n) (TXC_ID_SHIFT(n) | IS_PORT |\ 45 TXC_ER_ST | PORT_INVALID) 46 47 #define NPI_TXC_CHANNEL_INVALID(n) (TXC_ID_SHIFT(n) | IS_PORT |\ 48 TXC_ER_ST | CHANNEL_INVALID) 49 50 #define NPI_TXC_OPCODE_INVALID(n) (TXC_ID_SHIFT(n) | IS_PORT |\ 51 TXC_ER_ST | OPCODE_INVALID) 52 53 /* 54 * Register offset (0x1000 bytes for each channel) for TXC registers. 55 */ 56 #define NXGE_TXC_FZC_OFFSET(x, cn) (x + TXC_FZC_CHANNEL_OFFSET(cn)) 57 58 /* 59 * Register offset (0x100 bytes for each port) for TXC Function zero 60 * control registers. 61 */ 62 #define NXGE_TXC_FZC_CNTL_OFFSET(x, port) (x + \ 63 TXC_FZC_CNTL_PORT_OFFSET(port)) 64 /* 65 * PIO macros to read and write the transmit control registers. 66 */ 67 #define TXC_FZC_REG_READ64(handle, reg, cn, val_p) \ 68 NXGE_REG_RD64(handle, \ 69 (NXGE_TXC_FZC_OFFSET(reg, cn)), val_p) 70 71 #define TXC_FZC_REG_WRITE64(handle, reg, cn, data) \ 72 NXGE_REG_WR64(handle, \ 73 (NXGE_TXC_FZC_OFFSET(reg, cn)), data) 74 75 #define TXC_FZC_CNTL_REG_READ64(handle, reg, port, val_p) \ 76 NXGE_REG_RD64(handle, \ 77 (NXGE_TXC_FZC_CNTL_OFFSET(reg, port)), val_p) 78 79 #define TXC_FZC_CNTL_REG_WRITE64(handle, reg, port, data) \ 80 NXGE_REG_WR64(handle, \ 81 (NXGE_TXC_FZC_CNTL_OFFSET(reg, port)), data) 82 83 /* 84 * TXC (Transmit Controller) prototypes. 85 */ 86 npi_status_t npi_txc_dma_max_burst(npi_handle_t, io_op_t, 87 uint8_t, uint32_t *); 88 npi_status_t npi_txc_dma_max_burst_set(npi_handle_t, uint8_t, 89 uint32_t); 90 npi_status_t npi_txc_dma_bytes_transmitted(npi_handle_t, 91 uint8_t, uint32_t *); 92 npi_status_t npi_txc_control(npi_handle_t, io_op_t, 93 p_txc_control_t); 94 npi_status_t npi_txc_global_enable(npi_handle_t); 95 npi_status_t npi_txc_global_disable(npi_handle_t); 96 npi_status_t npi_txc_control_clear(npi_handle_t, uint8_t); 97 npi_status_t npi_txc_training_set(npi_handle_t, uint32_t); 98 npi_status_t npi_txc_training_get(npi_handle_t, uint32_t *); 99 npi_status_t npi_txc_port_control_get(npi_handle_t, uint8_t, 100 uint32_t *); 101 npi_status_t npi_txc_port_enable(npi_handle_t, uint8_t); 102 npi_status_t npi_txc_port_disable(npi_handle_t, uint8_t); 103 npi_status_t npi_txc_dma_max_burst(npi_handle_t, io_op_t, 104 uint8_t, uint32_t *); 105 npi_status_t npi_txc_port_dma_enable(npi_handle_t, uint8_t, 106 uint32_t); 107 npi_status_t npi_txc_port_dma_list_get(npi_handle_t, uint8_t, 108 uint32_t *); 109 npi_status_t npi_txc_port_dma_channel_enable(npi_handle_t, uint8_t, 110 uint8_t); 111 npi_status_t npi_txc_port_dma_channel_disable(npi_handle_t, uint8_t, 112 uint8_t); 113 114 npi_status_t npi_txc_pkt_stuffed_get(npi_handle_t, uint8_t, 115 uint32_t *, uint32_t *); 116 npi_status_t npi_txc_pkt_xmt_to_mac_get(npi_handle_t, uint8_t, 117 uint32_t *, uint32_t *); 118 npi_status_t npi_txc_reorder_get(npi_handle_t, uint8_t, 119 uint32_t *); 120 npi_status_t npi_txc_dump_tdc_fzc_regs(npi_handle_t, uint8_t); 121 npi_status_t npi_txc_dump_fzc_regs(npi_handle_t); 122 npi_status_t npi_txc_dump_port_fzc_regs(npi_handle_t, uint8_t); 123 npi_status_t npi_txc_ro_states_get(npi_handle_t, uint8_t, 124 txc_ro_states_t *); 125 npi_status_t npi_txc_ro_ecc_state_clr(npi_handle_t, uint8_t); 126 npi_status_t npi_txc_sf_states_get(npi_handle_t, uint8_t, 127 txc_sf_states_t *); 128 npi_status_t npi_txc_sf_ecc_state_clr(npi_handle_t, uint8_t); 129 void npi_txc_global_istatus_get(npi_handle_t, txc_int_stat_t *); 130 void npi_txc_global_istatus_clear(npi_handle_t, uint64_t); 131 void npi_txc_global_imask_set(npi_handle_t, uint8_t, 132 uint8_t); 133 134 #ifdef __cplusplus 135 } 136 #endif 137 138 #endif /* _NPI_TXC_H */ 139