1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _NPI_RXDMA_H 27 #define _NPI_RXDMA_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <npi.h> 36 37 #include "nxge_defs.h" 38 #include "nxge_hw.h" 39 #include <nxge_rxdma_hw.h> 40 41 /* 42 * Register offset (0x200 bytes for each channel) for receive ring registers. 43 */ 44 #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \ 45 (!v ? DMC_OFFSET(channel) : \ 46 RDMC_PIOVADDR_OFFSET(channel))) 47 48 49 #define REG_FZC_RDC_OFFSET(reg, rdc) (reg + RX_LOG_DMA_OFFSET(rdc)) 50 51 #define REG_RDC_TABLE_OFFSET(table) \ 52 (RDC_TBL_REG + table * (NXGE_MAX_RDCS * 8)) 53 54 #define RXDMA_REG_READ64(handle, reg, channel, data_p) {\ 55 NXGE_REG_RD64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ 56 channel)), (data_p))\ 57 } 58 59 #define RXDMA_REG_READ32(handle, reg, channel) \ 60 NXGE_NPI_PIO_READ32(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ 61 channel))) 62 63 64 #define RXDMA_REG_WRITE64(handle, reg, channel, data) {\ 65 NXGE_REG_WR64(handle, (NXGE_RXDMA_OFFSET(reg, handle.is_vraddr,\ 66 channel)), (data))\ 67 } 68 69 /* 70 * RX NPI error codes 71 */ 72 #define RXDMA_ER_ST (RXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT) 73 #define RXDMA_ID_SHIFT(n) (n << NPI_PORT_CHAN_SHIFT) 74 75 76 #define NPI_RXDMA_ERROR RXDMA_ER_ST 77 78 #define NPI_RXDMA_SW_PARAM_ERROR (NPI_RXDMA_ERROR | 0x40) 79 #define NPI_RXDMA_HW_ERROR (NPI_RXDMA_ERROR | 0x80) 80 81 #define NPI_RXDMA_RDC_INVALID (NPI_RXDMA_ERROR | CHANNEL_INVALID) 82 #define NPI_RXDMA_PAGE_INVALID (NPI_RXDMA_ERROR | LOGICAL_PAGE_INVALID) 83 #define NPI_RXDMA_RESET_ERR (NPI_RXDMA_HW_ERROR | RESET_FAILED) 84 #define NPI_RXDMA_DISABLE_ERR (NPI_RXDMA_HW_ERROR | 0x0000a) 85 #define NPI_RXDMA_ENABLE_ERR (NPI_RXDMA_HW_ERROR | 0x0000b) 86 #define NPI_RXDMA_FUNC_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000a) 87 #define NPI_RXDMA_BUFSZIE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000b) 88 #define NPI_RXDMA_RBRSZIE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000c) 89 #define NPI_RXDMA_RCRSZIE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000d) 90 #define NPI_RXDMA_PORT_INVALID (NPI_RXDMA_ERROR | PORT_INVALID) 91 #define NPI_RXDMA_TABLE_INVALID (NPI_RXDMA_ERROR | RDC_TAB_INVALID) 92 93 #define NPI_RXDMA_CHANNEL_INVALID(n) (RXDMA_ID_SHIFT(n) | \ 94 NPI_RXDMA_ERROR | CHANNEL_INVALID) 95 #define NPI_RXDMA_OPCODE_INVALID(n) (RXDMA_ID_SHIFT(n) | \ 96 NPI_RXDMA_ERROR | OPCODE_INVALID) 97 98 99 #define NPI_RXDMA_ERROR_ENCODE(err, rdc) \ 100 (RXDMA_ID_SHIFT(rdc) | RXDMA_ER_ST | err) 101 102 103 #define RXDMA_CHANNEL_VALID(rdc) \ 104 ((rdc < NXGE_MAX_RDCS)) 105 106 #define RXDMA_PORT_VALID(port) \ 107 ((port < MAX_PORTS_PER_NXGE)) 108 109 #define RXDMA_TABLE_VALID(table) \ 110 ((table < NXGE_MAX_RDC_GROUPS)) 111 112 113 #define RXDMA_PAGE_VALID(page) \ 114 ((page == 0) || (page == 1)) 115 116 #define RXDMA_BUFF_OFFSET_VALID(offset) \ 117 ((offset == SW_OFFSET_NO_OFFSET) || \ 118 (offset == SW_OFFSET_64) || \ 119 (offset == SW_OFFSET_128)) 120 121 122 #define RXDMA_RCR_TO_VALID(tov) ((tov) && (tov < 64)) 123 #define RXDMA_RCR_THRESH_VALID(thresh) ((thresh) && (thresh < 512)) 124 125 126 /* 127 * RXDMA NPI defined control types. 128 */ 129 typedef enum _rxdma_cs_cntl_e { 130 RXDMA_CS_CLEAR_ALL = 0x1, 131 RXDMA_MEX_SET = 0x2, 132 RXDMA_RCRTO_CLEAR = 0x8, 133 RXDMA_PT_DROP_PKT_CLEAR = 0x10, 134 RXDMA_WRED_DROP_CLEAR = 0x20, 135 RXDMA_RCR_SFULL_CLEAR = 0x40, 136 RXDMA_RCR_FULL_CLEAR = 0x80, 137 RXDMA_RBR_PRE_EMPTY_CLEAR = 0x100, 138 RXDMA_RBR_EMPTY_CLEAR = 0x200 139 } rxdma_cs_cntl_t; 140 141 /* 142 * RXDMA NPI defined event masks (mapped to the hardware defined masks). 143 */ 144 typedef enum _rxdma_ent_msk_cfg_e { 145 CFG_RXDMA_ENT_MSK_CFIGLOGPGE_MASK = RX_DMA_ENT_MSK_CFIGLOGPGE_MASK, 146 CFG_RXDMA_ENT_MSK_RBRLOGPGE_MASK = RX_DMA_ENT_MSK_RBRLOGPGE_MASK, 147 CFG_RXDMA_ENT_MSK_RBRFULL_MASK = RX_DMA_ENT_MSK_RBRFULL_MASK, 148 CFG_RXDMA_ENT_MSK_RBREMPTY_MASK = RX_DMA_ENT_MSK_RBREMPTY_MASK, 149 CFG_RXDMA_ENT_MSK_RCRFULL_MASK = RX_DMA_ENT_MSK_RCRFULL_MASK, 150 CFG_RXDMA_ENT_MSK_RCRINCON_MASK = RX_DMA_ENT_MSK_RCRINCON_MASK, 151 CFG_RXDMA_ENT_MSK_CONFIG_ERR = RX_DMA_ENT_MSK_CONFIG_ERR_MASK, 152 CFG_RXDMA_ENT_MSK_RCR_SH_FULL_MASK = RX_DMA_ENT_MSK_RCRSH_FULL_MASK, 153 CFG_RXDMA_ENT_MSK_RBR_PRE_EMTY_MASK = RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK, 154 CFG_RXDMA_ENT_MSK_WRED_DROP_MASK = RX_DMA_ENT_MSK_WRED_DROP_MASK, 155 CFG_RXDMA_ENT_MSK_PT_DROP_PKT_MASK = RX_DMA_ENT_MSK_PTDROP_PKT_MASK, 156 CFG_RXDMA_ENT_MSK_RBR_PRE_PAR_MASK = RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK, 157 CFG_RXDMA_ENT_MSK_RCR_SHA_PAR_MASK = RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK, 158 CFG_RXDMA_ENT_MSK_RCRTO_MASK = RX_DMA_ENT_MSK_RCRTO_MASK, 159 CFG_RXDMA_ENT_MSK_THRES_MASK = RX_DMA_ENT_MSK_THRES_MASK, 160 CFG_RXDMA_ENT_MSK_DC_FIFO_ERR_MASK = RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK, 161 CFG_RXDMA_ENT_MSK_RCR_ACK_ERR_MASK = RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK, 162 CFG_RXDMA_ENT_MSK_RSP_DAT_ERR_MASK = RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK, 163 CFG_RXDMA_ENT_MSK_BYTE_EN_BUS_MASK = RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK, 164 CFG_RXDMA_ENT_MSK_RSP_CNT_ERR_MASK = RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK, 165 CFG_RXDMA_ENT_MSK_RBR_TMOUT_MASK = RX_DMA_ENT_MSK_RBR_TMOUT_MASK, 166 167 CFG_RXDMA_MASK_ALL = (RX_DMA_ENT_MSK_CFIGLOGPGE_MASK | 168 RX_DMA_ENT_MSK_RBRLOGPGE_MASK | 169 RX_DMA_ENT_MSK_RBRFULL_MASK | 170 RX_DMA_ENT_MSK_RBREMPTY_MASK | 171 RX_DMA_ENT_MSK_RCRFULL_MASK | 172 RX_DMA_ENT_MSK_RCRINCON_MASK | 173 RX_DMA_ENT_MSK_CONFIG_ERR_MASK | 174 RX_DMA_ENT_MSK_RCRSH_FULL_MASK | 175 RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK | 176 RX_DMA_ENT_MSK_WRED_DROP_MASK | 177 RX_DMA_ENT_MSK_PTDROP_PKT_MASK | 178 RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK | 179 RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK | 180 RX_DMA_ENT_MSK_RCRTO_MASK | 181 RX_DMA_ENT_MSK_THRES_MASK | 182 RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK | 183 RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK | 184 RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK | 185 RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK | 186 RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK | 187 RX_DMA_ENT_MSK_RBR_TMOUT_MASK) 188 } rxdma_ent_msk_cfg_t; 189 190 191 192 typedef union _addr44 { 193 uint64_t addr; 194 struct { 195 #if defined(_BIG_ENDIAN) 196 uint32_t rsrvd:20; 197 uint32_t hdw:12; 198 uint32_t ldw; 199 #else 200 uint32_t ldw; 201 uint32_t hdw:12; 202 uint32_t rsrvd:20; 203 #endif 204 } bits; 205 } addr44_t; 206 207 208 /* 209 * npi_rxdma_cfg_default_port_rdc() 210 * Set the default rdc for the port 211 * 212 * Inputs: 213 * handle: register handle interpreted by the underlying OS 214 * portnm: Physical Port Number 215 * rdc: RX DMA Channel number 216 * 217 * Return: 218 * NPI_SUCCESS 219 * NPI_RXDMA_RDC_INVALID 220 * NPI_RXDMA_PORT_INVALID 221 * 222 */ 223 224 npi_status_t npi_rxdma_cfg_default_port_rdc(npi_handle_t, 225 uint8_t, uint8_t); 226 227 /* 228 * npi_rxdma_cfg_rdc_table() 229 * Configure/populate the RDC table 230 * 231 * Inputs: 232 * handle: register handle interpreted by the underlying OS 233 * table: RDC Group Number 234 * rdc[]: Array of RX DMA Channels 235 * 236 * Return: 237 * NPI_SUCCESS 238 * NPI_RXDMA_TABLE_INVALID 239 * 240 */ 241 242 npi_status_t npi_rxdma_cfg_rdc_table(npi_handle_t, 243 uint8_t, uint8_t []); 244 245 npi_status_t npi_rxdma_cfg_rdc_table_default_rdc(npi_handle_t, 246 uint8_t, uint8_t); 247 npi_status_t npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t, 248 uint8_t); 249 250 251 /* 252 * npi_rxdma_32bitmode_enable() 253 * Enable 32 bit mode 254 * 255 * Inputs: 256 * handle: register handle interpreted by the underlying OS 257 * 258 * Return: 259 * NPI_SUCCESS 260 * NPI_FAILURE 261 * NPI_HW_ERR 262 * 263 */ 264 265 npi_status_t npi_rxdma_cfg_32bitmode_enable(npi_handle_t); 266 267 268 /* 269 * npi_rxdma_32bitmode_disable() 270 * disable 32 bit mode 271 * 272 * Inputs: 273 * handle: register handle interpreted by the underlying OS 274 * 275 * Return: 276 * NPI_SUCCESS 277 * NPI_FAILURE 278 * NPI_HW_ERR 279 * 280 */ 281 282 283 npi_status_t npi_rxdma_cfg_32bitmode_disable(npi_handle_t); 284 285 /* 286 * npi_rxdma_cfg_ram_access_enable() 287 * Enable PIO access to shadow and prefetch memory. 288 * In the case of DMA errors, software may need to 289 * initialize the shadow and prefetch memories to 290 * sane value (may be clear it) before re-enabling 291 * the DMA channel. 292 * 293 * Inputs: 294 * handle: register handle interpreted by the underlying OS 295 * 296 * Return: 297 * NPI_SUCCESS 298 * NPI_FAILURE 299 * NPI_HW_ERR 300 * 301 */ 302 303 npi_status_t npi_rxdma_cfg_ram_access_enable(npi_handle_t); 304 305 306 /* 307 * npi_rxdma_cfg_ram_access_disable() 308 * Disable PIO access to shadow and prefetch memory. 309 * This is the normal operation mode. 310 * 311 * Inputs: 312 * handle: register handle interpreted by the underlying OS 313 * 314 * Return: 315 * NPI_SUCCESS 316 * NPI_FAILURE 317 * NPI_HW_ERR 318 * 319 */ 320 321 npi_status_t npi_rxdma_cfg_ram_access_disable(npi_handle_t); 322 323 324 /* 325 * npi_rxdma_cfg_clock_div_set() 326 * init the clock division, used for RX timers 327 * This determines the granularity of RX DMA countdown timers 328 * It depends on the system clock. For example if the system 329 * clock is 300 MHz, a value of 30000 will yield a granularity 330 * of 100usec. 331 * 332 * Inputs: 333 * handle: register handle interpreted by the underlying OS 334 * count: System clock divider 335 * 336 * Return: 337 * NPI_SUCCESS 338 * NPI_FAILURE 339 * NPI_SW_ERR 340 * NPI_HW_ERR 341 * 342 */ 343 344 npi_status_t npi_rxdma_cfg_clock_div_set(npi_handle_t, uint16_t); 345 346 /* 347 * npi_rxdma_cfg_red_rand_init() 348 * init the WRED Discard 349 * By default, it is enabled 350 * 351 * Inputs: 352 * handle: register handle interpreted by the underlying OS 353 * init_value: WRED init value 354 * 355 * Return: 356 * NPI_SUCCESS 357 * NPI_FAILURE 358 * NPI_SW_ERR 359 * NPI_HW_ERR 360 * 361 */ 362 363 npi_status_t npi_rxdma_cfg_red_rand_init(npi_handle_t, uint16_t); 364 365 /* 366 * npi_rxdma_cfg_wred_disable() 367 * init the WRED Discard 368 * By default, it is enabled 369 * 370 * Inputs: 371 * handle: register handle interpreted by the underlying OS 372 * 373 * Return: 374 * NPI_SUCCESS 375 * NPI_FAILURE 376 * NPI_SW_ERR 377 * NPI_HW_ERR 378 * 379 */ 380 381 382 npi_status_t npi_rxdma_cfg_wred_disable(npi_handle_t); 383 384 /* 385 * npi_rxdma_cfg_wred_param() 386 * COnfigure per rxdma channel WRED parameters 387 * By default, it is enabled 388 * 389 * Inputs: 390 * handle: register handle interpreted by the underlying OS 391 * rdc: RX DMA Channel number 392 * wred_params: WRED configuration parameters 393 * 394 * Return: 395 * NPI_SUCCESS 396 * NPI_FAILURE 397 * NPI_SW_ERR 398 * NPI_HW_ERR 399 * 400 */ 401 402 403 404 npi_status_t npi_rxdma_cfg_wred_param(npi_handle_t, uint8_t, 405 rdc_red_para_t *); 406 407 408 /* 409 * npi_rxdma_port_ddr_weight 410 * Set the DDR weight for a port. 411 * 412 * Inputs: 413 * handle: register handle interpreted by the underlying OS 414 * portnm: Physical Port Number 415 * weight: Port relative weight (in approx. bytes) 416 * Default values are: 417 * 0x400 (port 0 and 1) corresponding to 10 standard 418 * size (1500 bytes) Frames 419 * 0x66 (port 2 and 3) corresponding to 10% 10Gig ports 420 * 421 * Return: 422 * NPI_SUCCESS 423 * NPI_FAILURE 424 * NPI_HW_ERR 425 * NPI_SW_ERR 426 * 427 */ 428 429 npi_status_t npi_rxdma_cfg_port_ddr_weight(npi_handle_t, 430 uint8_t, uint32_t); 431 432 433 /* 434 * npi_rxdma_port_usage_get() 435 * Gets the port usage, in terms of 16 byte blocks 436 * 437 * NOTE: The register count is cleared upon reading. 438 * 439 * Inputs: 440 * handle: register handle interpreted by the underlying OS 441 * portnm: Physical Port Number 442 * blocks: ptr to save current count. 443 * 444 * Return: 445 * NPI_SUCCESS 446 * NPI_FAILURE 447 * NPI_HW_ERR 448 * NPI_SW_ERR 449 * 450 */ 451 452 npi_status_t npi_rxdma_port_usage_get(npi_handle_t, 453 uint8_t, uint32_t *); 454 455 456 /* 457 * npi_rxdma_cfg_logical_page() 458 * Configure per rxdma channel Logical page 459 * 460 * To disable the logical page, set valid = 0; 461 * 462 * Inputs: 463 * handle: register handle interpreted by the underlying OS 464 * rdc: RX DMA Channel number 465 * page_params: Logical Page configuration parameters 466 * 467 * Return: 468 * NPI_SUCCESS 469 * NPI_FAILURE 470 * NPI_SW_ERR 471 * NPI_HW_ERR 472 * 473 */ 474 475 476 477 npi_status_t npi_rxdma_cfg_logical_page(npi_handle_t, uint8_t, 478 dma_log_page_t *); 479 480 481 /* 482 * npi_rxdma_cfg_logical_page_handle() 483 * Configure per rxdma channel Logical page handle 484 * 485 * 486 * Inputs: 487 * handle: register handle interpreted by the underlying OS 488 * rdc: RX DMA Channel number 489 * pg_handle: Logical Page handle 490 * 491 * Return: 492 * NPI_SUCCESS 493 * NPI_FAILURE 494 * NPI_SW_ERR 495 * NPI_HW_ERR 496 * 497 */ 498 499 500 npi_status_t npi_rxdma_cfg_logical_page_handle(npi_handle_t, uint8_t, 501 uint64_t); 502 503 504 505 506 npi_status_t npi_rxdma_cfg_logical_page_disable(npi_handle_t, 507 uint8_t, uint8_t); 508 509 typedef enum _bsize { 510 SIZE_0B = 0x0, 511 SIZE_64B, 512 SIZE_128B, 513 SIZE_192B, 514 SIZE_256B, 515 SIZE_512B, 516 SIZE_1KB, 517 SIZE_2KB, 518 SIZE_4KB, 519 SIZE_8KB, 520 SIZE_16KB, 521 SIZE_32KB 522 } bsize_t; 523 524 525 526 /* 527 * npi_rxdma_cfg_rdc_ring() 528 * Configure The RDC channel Rcv Buffer Ring 529 * 530 * Inputs: 531 * rdc: RX DMA Channel number 532 * rdc_params: RDC configuration parameters 533 * 534 * Return: 535 * NPI_SUCCESS 536 * NPI_FAILURE 537 * NPI_SW_ERR 538 * NPI_HW_ERR 539 * 540 */ 541 542 typedef struct _rdc_desc_cfg_t { 543 uint8_t mbox_enable; /* Enable full (18b) header */ 544 uint8_t full_hdr; /* Enable full (18b) header */ 545 uint8_t offset; /* 64 byte offsets */ 546 uint8_t valid2; /* size 2 is valid */ 547 bsize_t size2; /* Size 2 length */ 548 uint8_t valid1; /* size 1 is valid */ 549 bsize_t size1; /* Size 1 length */ 550 uint8_t valid0; /* size 0 is valid */ 551 bsize_t size0; /* Size 1 length */ 552 bsize_t page_size; /* Page or buffer Size */ 553 uint8_t rcr_timeout_enable; 554 uint8_t rcr_timeout; 555 uint16_t rcr_threshold; 556 uint16_t rcr_len; /* RBR Descriptor size (entries) */ 557 uint16_t rbr_len; /* RBR Descriptor size (entries) */ 558 uint64_t mbox_addr; /* Mailbox Address */ 559 uint64_t rcr_addr; /* RCR Address */ 560 uint64_t rbr_addr; /* RBB Address */ 561 } rdc_desc_cfg_t; 562 563 564 565 npi_status_t npi_rxdma_cfg_rdc_ring(npi_handle_t, uint8_t, 566 rdc_desc_cfg_t *); 567 568 569 570 571 /* 572 * npi_rxdma_rdc_rcr_flush 573 * Forces RX completion ring update 574 * 575 * Inputs: 576 * rdc: RX DMA Channel number 577 * 578 * Return: 579 * 580 */ 581 582 #define npi_rxdma_rdc_rcr_flush(handle, rdc) \ 583 RXDMA_REG_WRITE64(handle, RCR_FLSH_REG, rdc, \ 584 (RCR_FLSH_SET << RCR_FLSH_SHIFT)) 585 586 587 588 /* 589 * npi_rxdma_rdc_rcr_read_update 590 * Update the number of rcr packets and buffers processed 591 * 592 * Inputs: 593 * channel: RX DMA Channel number 594 * num_pkts: Number of pkts processed by SW. 595 * A packet could constitute multiple 596 * buffers, in case jumbo packets. 597 * num_bufs: Number of buffer processed by SW. 598 * 599 * Return: 600 * NPI_FAILURE - 601 * NPI_RXDMA_OPCODE_INVALID - 602 * NPI_RXDMA_CHANNEL_INVALID - 603 * 604 */ 605 606 npi_status_t npi_rxdma_rdc_rcr_read_update(npi_handle_t, uint8_t, 607 uint16_t, uint16_t); 608 /* 609 * npi_rxdma_rdc_rcr_pktread_update 610 * Update the number of packets processed 611 * 612 * Inputs: 613 * channel: RX DMA Channel number 614 * num_pkts: Number ofpkts processed by SW. 615 * A packet could constitute multiple 616 * buffers, in case jumbo packets. 617 * 618 * Return: 619 * NPI_FAILURE - 620 * NPI_RXDMA_OPCODE_INVALID - 621 * NPI_RXDMA_CHANNEL_INVALID - 622 * 623 */ 624 625 npi_status_t npi_rxdma_rdc_rcr_pktread_update(npi_handle_t, 626 uint8_t, uint16_t); 627 628 629 630 /* 631 * npi_rxdma_rdc_rcr_bufread_update 632 * Update the number of buffers processed 633 * 634 * Inputs: 635 * channel: RX DMA Channel number 636 * num_bufs: Number of buffer processed by SW. Multiple buffers 637 * could be part of a single packet. 638 * 639 * Return: 640 * NPI_FAILURE - 641 * NPI_RXDMA_OPCODE_INVALID - 642 * NPI_RXDMA_CHANNEL_INVALID - 643 * 644 */ 645 646 npi_status_t npi_rxdma_rdc_rcr_bufread_update(npi_handle_t, 647 uint8_t, uint16_t); 648 649 650 651 /* 652 * npi_rxdma_rdc_rbr_kick 653 * Kick RDC RBR 654 * 655 * Inputs: 656 * rdc: RX DMA Channel number 657 * num_buffers: Number of Buffers posted to the RBR 658 * 659 * Return: 660 * 661 */ 662 663 #define npi_rxdma_rdc_rbr_kick(handle, rdc, num_buffers) \ 664 RXDMA_REG_WRITE64(handle, RBR_KICK_REG, rdc, num_buffers) 665 666 667 /* 668 * npi_rxdma_rdc_rbr_head_get 669 * Gets the current rbr head pointer. 670 * 671 * Inputs: 672 * rdc: RX DMA Channel number 673 * hdptr ptr to write the rbr head value 674 * 675 * Return: 676 * 677 */ 678 679 npi_status_t npi_rxdma_rdc_rbr_head_get(npi_handle_t, 680 uint8_t, addr44_t *); 681 682 683 684 /* 685 * npi_rxdma_rdc_rbr_stat_get 686 * Returns the RBR stat. The stat consists of the 687 * RX buffers in the ring. It also indicates if there 688 * has been an overflow. 689 * 690 * Inputs: 691 * rdc: RX DMA Channel number 692 * rbr_stat_t: Structure to update stat 693 * 694 * Return: 695 * 696 */ 697 698 npi_status_t npi_rxdma_rdc_rbr_stat_get(npi_handle_t, uint8_t, 699 rbr_stat_t *); 700 701 702 703 /* 704 * npi_rxdma_cfg_rdc_reset 705 * Resets the RDC channel 706 * 707 * Inputs: 708 * rdc: RX DMA Channel number 709 * 710 * Return: 711 * 712 */ 713 714 npi_status_t npi_rxdma_cfg_rdc_reset(npi_handle_t, uint8_t); 715 716 717 /* 718 * npi_rxdma_rdc_enable 719 * Enables the RDC channel 720 * 721 * Inputs: 722 * rdc: RX DMA Channel number 723 * 724 * Return: 725 * 726 */ 727 728 npi_status_t npi_rxdma_cfg_rdc_enable(npi_handle_t, uint8_t); 729 730 /* 731 * npi_rxdma_rdc_disable 732 * Disables the RDC channel 733 * 734 * Inputs: 735 * rdc: RX DMA Channel number 736 * 737 * Return: 738 * 739 */ 740 741 npi_status_t npi_rxdma_cfg_rdc_disable(npi_handle_t, uint8_t); 742 743 744 /* 745 * npi_rxdma_cfg_rdc_rcr_timeout() 746 * Configure The RDC channel completion ring timeout. 747 * If a frame has been received, an event would be 748 * generated atleast at the expiration of the timeout. 749 * 750 * Enables timeout by default. 751 * 752 * Inputs: 753 * rdc: RX DMA Channel number 754 * rcr_timeout: Completion Ring timeout value 755 * 756 * Return: 757 * NPI_SUCCESS 758 * NPI_FAILURE 759 * NPI_SW_ERR 760 * NPI_HW_ERR 761 * 762 */ 763 764 npi_status_t npi_rxdma_cfg_rdc_rcr_timeout(npi_handle_t, uint8_t, 765 uint8_t); 766 767 768 /* 769 * npi_rxdma_cfg_rdc_rcr_threshold() 770 * Configure The RDC channel completion ring threshold. 771 * An event would be If the number of frame received, 772 * surpasses the threshold value 773 * 774 * Inputs: 775 * rdc: RX DMA Channel number 776 * rcr_threshold: Completion Ring Threshold count 777 * 778 * Return: 779 * NPI_SUCCESS 780 * NPI_FAILURE 781 * NPI_SW_ERR 782 * NPI_HW_ERR 783 * 784 */ 785 786 npi_status_t npi_rxdma_cfg_rdc_rcr_threshold(npi_handle_t, uint8_t, 787 uint16_t); 788 789 790 npi_status_t npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t, uint8_t); 791 792 typedef struct _rdc_error_stat_t { 793 uint8_t fault:1; 794 uint8_t multi_fault:1; 795 uint8_t rbr_fault:1; 796 uint8_t buff_fault:1; 797 uint8_t rcr_fault:1; 798 addr44_t fault_addr; 799 } rdc_error_stat_t; 800 801 #if OLD 802 /* 803 * npi_rxdma_rdc_error_stat_get 804 * Gets the current Error stat for the RDC. 805 * 806 * Inputs: 807 * rdc: RX DMA Channel number 808 * error_stat Structure to write current RDC Error stat 809 * 810 * Return: 811 * 812 */ 813 814 npi_status_t npi_rxdma_rdc_error_stat_get(npi_handle_t, 815 uint8_t, rdc_error_stat_t *); 816 817 #endif 818 819 /* 820 * npi_rxdma_rdc_rcr_tail_get 821 * Gets the current RCR tail address for the RDC. 822 * 823 * Inputs: 824 * rdc: RX DMA Channel number 825 * tail_addr Structure to write current RDC RCR tail address 826 * 827 * Return: 828 * 829 */ 830 831 npi_status_t npi_rxdma_rdc_rcr_tail_get(npi_handle_t, 832 uint8_t, addr44_t *); 833 834 835 npi_status_t npi_rxdma_rdc_rcr_qlen_get(npi_handle_t, 836 uint8_t, uint16_t *); 837 838 839 840 typedef struct _rdc_discard_stat_t { 841 uint8_t nobuf_ovflow; 842 uint8_t red_ovflow; 843 uint32_t nobuf_discard; 844 uint32_t red_discard; 845 } rdc_discard_stat_t; 846 847 848 /* 849 * npi_rxdma_rdc_discard_stat_get 850 * Gets the current discrad stats for the RDC. 851 * 852 * Inputs: 853 * rdc: RX DMA Channel number 854 * rcr_stat Structure to write current RDC discard stat 855 * 856 * Return: 857 * 858 */ 859 860 npi_status_t npi_rxdma_rdc_discard_stat_get(npi_handle_t, 861 uint8_t, rdc_discard_stat_t); 862 863 864 /* 865 * npi_rx_port_discard_stat_get 866 * Gets the current input (IPP) discrad stats for the rx port. 867 * 868 * Inputs: 869 * rdc: RX DMA Channel number 870 * rx_disc_cnt_t Structure to write current RDC discard stat 871 * 872 * Return: 873 * 874 */ 875 876 npi_status_t npi_rx_port_discard_stat_get(npi_handle_t, 877 uint8_t, 878 rx_disc_cnt_t *); 879 880 881 /* 882 * npi_rxdma_red_discard_stat_get 883 * Gets the current discrad count due RED 884 * The counter overflow bit is cleared, if it has been set. 885 * 886 * Inputs: 887 * rdc: RX DMA Channel number 888 * rx_disc_cnt_t Structure to write current RDC discard stat 889 * 890 * Return: 891 * NPI_SUCCESS 892 * NPI_RXDMA_RDC_INVALID 893 * 894 */ 895 896 npi_status_t npi_rxdma_red_discard_stat_get(npi_handle_t, uint8_t, 897 rx_disc_cnt_t *); 898 899 900 901 /* 902 * npi_rxdma_red_discard_oflow_clear 903 * Clear RED discard counter overflow bit 904 * 905 * Inputs: 906 * rdc: RX DMA Channel number 907 * 908 * Return: 909 * NPI_SUCCESS 910 * NPI_RXDMA_RDC_INVALID 911 * 912 */ 913 914 npi_status_t npi_rxdma_red_discard_oflow_clear(npi_handle_t, 915 uint8_t); 916 917 918 919 920 /* 921 * npi_rxdma_misc_discard_stat_get 922 * Gets the current discrad count for the rdc due to 923 * buffer pool empty 924 * The counter overflow bit is cleared, if it has been set. 925 * 926 * Inputs: 927 * rdc: RX DMA Channel number 928 * rx_disc_cnt_t Structure to write current RDC discard stat 929 * 930 * Return: 931 * NPI_SUCCESS 932 * NPI_RXDMA_RDC_INVALID 933 * 934 */ 935 936 npi_status_t npi_rxdma_misc_discard_stat_get(npi_handle_t, uint8_t, 937 rx_disc_cnt_t *); 938 939 940 941 /* 942 * npi_rxdma_red_discard_oflow_clear 943 * Clear RED discard counter overflow bit 944 * clear the overflow bit for buffer pool empty discrad counter 945 * for the rdc 946 * 947 * 948 * Inputs: 949 * rdc: RX DMA Channel number 950 * 951 * Return: 952 * NPI_SUCCESS 953 * NPI_RXDMA_RDC_INVALID 954 * 955 */ 956 957 npi_status_t npi_rxdma_misc_discard_oflow_clear(npi_handle_t, 958 uint8_t); 959 960 961 962 /* 963 * npi_rxdma_ring_perr_stat_get 964 * Gets the current RDC Memory parity error 965 * The counter overflow bit is cleared, if it has been set. 966 * 967 * Inputs: 968 * pre_cnt: Structure to write current RDC Prefetch memory 969 * Parity Error stat 970 * sha_cnt: Structure to write current RDC Shadow memory 971 * Parity Error stat 972 * 973 * Return: 974 * NPI_SUCCESS 975 * NPI_RXDMA_RDC_INVALID 976 * 977 */ 978 979 npi_status_t npi_rxdma_ring_perr_stat_get(npi_handle_t, 980 rdmc_par_err_log_t *, 981 rdmc_par_err_log_t *); 982 983 984 /* 985 * npi_rxdma_ring_perr_stat_get 986 * Clear RDC Memory Parity Error counter overflow bits 987 * 988 * Inputs: 989 * Return: 990 * NPI_SUCCESS 991 * 992 */ 993 994 npi_status_t npi_rxdma_ring_perr_stat_clear(npi_handle_t); 995 996 997 /* Access the RDMC Memory: used for debugging */ 998 999 npi_status_t npi_rxdma_rdmc_memory_io(npi_handle_t, 1000 rdmc_mem_access_t *, uint8_t); 1001 1002 1003 1004 /* 1005 * npi_rxdma_rxctl_fifo_error_intr_set 1006 * Configure The RX ctrl fifo error interrupt generation 1007 * 1008 * Inputs: 1009 * mask: rx_ctl_dat_fifo_mask_t specifying the errors 1010 * 1011 * Return: 1012 * NPI_SUCCESS 1013 * NPI_FAILURE 1014 * 1015 */ 1016 1017 npi_status_t npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t, 1018 rx_ctl_dat_fifo_mask_t *); 1019 1020 /* 1021 * npi_rxdma_rxctl_fifo_error_status_get 1022 * Read The RX ctrl fifo error Status 1023 * 1024 * Inputs: 1025 * stat: rx_ctl_dat_fifo_stat_t to read the errors to 1026 * valid fields in rx_ctl_dat_fifo_stat_t structure are: 1027 * zcp_eop_err, ipp_eop_err, id_mismatch. 1028 * Return: 1029 * NPI_SUCCESS 1030 * NPI_FAILURE 1031 * 1032 */ 1033 1034 npi_status_t npi_rxdma_rxctl_fifo_error_status_get(npi_handle_t, 1035 rx_ctl_dat_fifo_stat_t *); 1036 1037 1038 /* 1039 * npi_rxdma_channel_mex_set(): 1040 * This function is called to arm the DMA channel with 1041 * mailbox updating capability. Software needs to rearm 1042 * for each update by writing to the control and status register. 1043 * 1044 * Parameters: 1045 * handle - NPI handle (virtualization flag must be defined). 1046 * channel - logical RXDMA channel from 0 to 23. 1047 * (If virtualization flag is not set, then 1048 * logical channel is the same as the hardware 1049 * channel number). 1050 * 1051 * Return: 1052 * NPI_SUCCESS - If enable channel with mailbox update 1053 * is complete successfully. 1054 * 1055 * Error: 1056 * NPI_FAILURE - 1057 * NPI_RXDMA_CHANNEL_INVALID - 1058 */ 1059 npi_status_t npi_rxdma_channel_mex_set(npi_handle_t, uint8_t); 1060 1061 /* 1062 * npi_rxdma_channel_rcrto_clear(): 1063 * This function is called to reset RCRTO bit to 0. 1064 * 1065 * Parameters: 1066 * handle - NPI handle (virtualization flag must be defined). 1067 * channel - logical RXDMA channel from 0 to 23. 1068 * (If virtualization flag is not set, then 1069 * logical channel is the same as the hardware 1070 * channel number). 1071 * Return: 1072 * NPI_SUCCESS 1073 * 1074 * Error: 1075 * NPI_FAILURE - 1076 * NPI_RXDMA_CHANNEL_INVALID - 1077 */ 1078 npi_status_t npi_rxdma_channel_rcrto_clear(npi_handle_t, uint8_t); 1079 1080 /* 1081 * npi_rxdma_channel_pt_drop_pkt_clear(): 1082 * This function is called to clear the port drop packet bit (debug). 1083 * 1084 * Parameters: 1085 * handle - NPI handle (virtualization flag must be defined). 1086 * channel - logical RXDMA channel from 0 to 23. 1087 * (If virtualization flag is not set, then 1088 * logical channel is the same as the hardware 1089 * channel number). 1090 * Return: 1091 * NPI_SUCCESS 1092 * 1093 * Error: 1094 * NPI_FAILURE - 1095 * NPI_RXDMA_CHANNEL_INVALID - 1096 */ 1097 npi_status_t npi_rxdma_channel_pt_drop_pkt_clear(npi_handle_t, uint8_t); 1098 1099 /* 1100 * npi_rxdma_channel_wred_drop_clear(): 1101 * This function is called to wred drop bit (debug only). 1102 * 1103 * Parameters: 1104 * handle - NPI handle (virtualization flag must be defined). 1105 * channel - logical RXDMA channel from 0 to 23. 1106 * (If virtualization flag is not set, then 1107 * logical channel is the same as the hardware 1108 * channel number). 1109 * Return: 1110 * NPI_SUCCESS 1111 * 1112 * Error: 1113 * NPI_FAILURE - 1114 * NPI_RXDMA_CHANNEL_INVALID - 1115 */ 1116 npi_status_t npi_rxdma_channel_wred_drop_clear(npi_handle_t, uint8_t); 1117 1118 /* 1119 * npi_rxdma_channel_rcr_shfull_clear(): 1120 * This function is called to clear RCR shadow full bit. 1121 * 1122 * Parameters: 1123 * handle - NPI handle (virtualization flag must be defined). 1124 * channel - logical RXDMA channel from 0 to 23. 1125 * (If virtualization flag is not set, then 1126 * logical channel is the same as the hardware 1127 * channel number). 1128 * Return: 1129 * NPI_SUCCESS 1130 * 1131 * Error: 1132 * NPI_FAILURE - 1133 * NPI_RXDMA_CHANNEL_INVALID - 1134 */ 1135 npi_status_t npi_rxdma_channel_rcr_shfull_clear(npi_handle_t, uint8_t); 1136 1137 /* 1138 * npi_rxdma_channel_rcrfull_clear(): 1139 * This function is called to clear RCR full bit. 1140 * 1141 * Parameters: 1142 * handle - NPI handle (virtualization flag must be defined). 1143 * channel - logical RXDMA channel from 0 to 23. 1144 * (If virtualization flag is not set, then 1145 * logical channel is the same as the hardware 1146 * channel number). 1147 * Return: 1148 * NPI_SUCCESS 1149 * 1150 * Error: 1151 * NPI_FAILURE - 1152 * NPI_RXDMA_CHANNEL_INVALID - 1153 */ 1154 npi_status_t npi_rxdma_channel_rcrfull_clear(npi_handle_t, uint8_t); 1155 1156 /* 1157 * npi_rxdma_rbr_pre_empty_clear(): 1158 * This function is called to control a receive DMA channel 1159 * for arming the channel with mailbox updates, resetting 1160 * various event status bits (control and status register). 1161 * 1162 * Parameters: 1163 * handle - NPI handle (virtualization flag must be defined). 1164 * control - NPI defined control type supported: 1165 * - RXDMA_MEX_SET 1166 * - RXDMA_RCRTO_CLEAR 1167 * - RXDMA_PT_DROP_PKT_CLEAR 1168 * - RXDMA_WRED_DROP_CLEAR 1169 * - RXDMA_RCR_SFULL_CLEAR 1170 * - RXDMA_RCR_FULL_CLEAR 1171 * - RXDMA_RBR_PRE_EMPTY_CLEAR 1172 * channel - logical RXDMA channel from 0 to 23. 1173 * (If virtualization flag is not set, then 1174 * logical channel is the same as the hardware. 1175 * Return: 1176 * NPI_SUCCESS 1177 * 1178 * Error: 1179 * NPI_FAILURE - 1180 * NPI_RXDMA_CHANNEL_INVALID - 1181 */ 1182 npi_status_t npi_rxdma_channel_rbr_pre_empty_clear(npi_handle_t, uint8_t); 1183 1184 /* 1185 * npi_rxdma_channel_control(): 1186 * This function is called to control a receive DMA channel 1187 * for arming the channel with mailbox updates, resetting 1188 * various event status bits (control and status register). 1189 * 1190 * Parameters: 1191 * handle - NPI handle (virtualization flag must be defined). 1192 * control - NPI defined control type supported: 1193 * - RXDMA_MEX_SET 1194 * - RXDMA_RCRTO_CLEAR 1195 * - RXDMA_PT_DROP_PKT_CLEAR 1196 * - RXDMA_WRED_DROP_CLEAR 1197 * - RXDMA_RCR_SFULL_CLEAR 1198 * - RXDMA_RCR_FULL_CLEAR 1199 * - RXDMA_RBR_PRE_EMPTY_CLEAR 1200 * channel - logical RXDMA channel from 0 to 23. 1201 * (If virtualization flag is not set, then 1202 * logical channel is the same as the hardware. 1203 * Return: 1204 * NPI_SUCCESS 1205 * 1206 * Error: 1207 * NPI_FAILURE - 1208 * NPI_TXDMA_OPCODE_INVALID - 1209 * NPI_TXDMA_CHANNEL_INVALID - 1210 */ 1211 npi_status_t npi_rxdma_channel_control(npi_handle_t, 1212 rxdma_cs_cntl_t, uint8_t); 1213 1214 /* 1215 * npi_rxdma_control_status(): 1216 * This function is called to operate on the control 1217 * and status register. 1218 * 1219 * Parameters: 1220 * handle - NPI handle 1221 * op_mode - OP_GET: get hardware control and status 1222 * OP_SET: set hardware control and status 1223 * OP_UPDATE: update hardware control and status. 1224 * OP_CLEAR: clear control and status register to 0s. 1225 * channel - hardware RXDMA channel from 0 to 23. 1226 * cs_p - pointer to hardware defined control and status 1227 * structure. 1228 * Return: 1229 * NPI_SUCCESS 1230 * 1231 * Error: 1232 * NPI_FAILURE - 1233 * NPI_RXDMA_OPCODE_INVALID - 1234 * NPI_RXDMA_CHANNEL_INVALID - 1235 */ 1236 npi_status_t npi_rxdma_control_status(npi_handle_t, io_op_t, 1237 uint8_t, p_rx_dma_ctl_stat_t); 1238 1239 /* 1240 * npi_rxdma_event_mask(): 1241 * This function is called to operate on the event mask 1242 * register which is used for generating interrupts. 1243 * 1244 * Parameters: 1245 * handle - NPI handle 1246 * op_mode - OP_GET: get hardware event mask 1247 * OP_SET: set hardware interrupt event masks 1248 * OP_CLEAR: clear control and status register to 0s. 1249 * channel - hardware RXDMA channel from 0 to 23. 1250 * mask_p - pointer to hardware defined event mask 1251 * structure. 1252 * Return: 1253 * NPI_SUCCESS - If set is complete successfully. 1254 * 1255 * Error: 1256 * NPI_FAILURE - 1257 * NPI_RXDMA_OPCODE_INVALID - 1258 * NPI_RXDMA_CHANNEL_INVALID - 1259 */ 1260 npi_status_t npi_rxdma_event_mask(npi_handle_t, io_op_t, 1261 uint8_t, p_rx_dma_ent_msk_t); 1262 1263 /* 1264 * npi_rxdma_event_mask_config(): 1265 * This function is called to operate on the event mask 1266 * register which is used for generating interrupts 1267 * and status register. 1268 * 1269 * Parameters: 1270 * handle - NPI handle 1271 * op_mode - OP_GET: get hardware event mask 1272 * OP_SET: set hardware interrupt event masks 1273 * OP_CLEAR: clear control and status register to 0s. 1274 * channel - hardware RXDMA channel from 0 to 23. 1275 * cfgp - pointer to NPI defined event mask 1276 * enum data type. 1277 * Return: 1278 * NPI_SUCCESS - If set is complete successfully. 1279 * 1280 * Error: 1281 * NPI_FAILURE - 1282 * NPI_RXDMA_OPCODE_INVALID - 1283 * NPI_RXDMA_CHANNEL_INVALID - 1284 */ 1285 npi_status_t npi_rxdma_event_mask_config(npi_handle_t, io_op_t, 1286 uint8_t, rxdma_ent_msk_cfg_t *); 1287 1288 1289 /* 1290 * npi_rxdma_dump_rdc_regs 1291 * Dumps the contents of rdc csrs and fzc registers 1292 * 1293 * Input: 1294 * rdc: RX DMA number 1295 * 1296 * return: 1297 * NPI_SUCCESS 1298 * NPI_FAILURE 1299 * NPI_RXDMA_RDC_INVALID 1300 * 1301 */ 1302 1303 npi_status_t npi_rxdma_dump_rdc_regs(npi_handle_t, uint8_t); 1304 1305 1306 /* 1307 * npi_rxdma_dump_fzc_regs 1308 * Dumps the contents of rdc csrs and fzc registers 1309 * 1310 * Input: 1311 * rdc: RX DMA number 1312 * 1313 * return: 1314 * NPI_SUCCESS 1315 * NPI_FAILURE 1316 * NPI_RXDMA_RDC_INVALID 1317 * 1318 */ 1319 1320 npi_status_t npi_rxdma_dump_fzc_regs(npi_handle_t); 1321 1322 npi_status_t npi_rxdma_channel_rbr_empty_clear(npi_handle_t, 1323 uint8_t); 1324 npi_status_t npi_rxdma_rxctl_fifo_error_intr_get(npi_handle_t, 1325 rx_ctl_dat_fifo_stat_t *); 1326 1327 npi_status_t npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t, 1328 rx_ctl_dat_fifo_mask_t *); 1329 1330 npi_status_t npi_rxdma_dump_rdc_table(npi_handle_t, uint8_t); 1331 #ifdef __cplusplus 1332 } 1333 #endif 1334 1335 #endif /* _NPI_RXDMA_H */ 1336