1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _NPI_RXDMA_H 27 #define _NPI_RXDMA_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #include <npi.h> 36 37 #include "nxge_defs.h" 38 #include "nxge_hw.h" 39 #include <nxge_rxdma_hw.h> 40 41 /* 42 * Register offset (0x200 bytes for each channel) for receive ring registers. 43 */ 44 #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \ 45 (!v ? DMC_OFFSET(channel) : \ 46 RDMC_PIOVADDR_OFFSET(channel))) 47 48 49 #define REG_FZC_RDC_OFFSET(reg, rdc) (reg + RX_LOG_DMA_OFFSET(rdc)) 50 51 #define REG_RDC_TABLE_OFFSET(table) \ 52 (RDC_TBL_REG + table * (NXGE_MAX_RDCS * 8)) 53 54 /* 55 * RX NPI error codes 56 */ 57 #define RXDMA_ER_ST (RXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT) 58 #define RXDMA_ID_SHIFT(n) (n << NPI_PORT_CHAN_SHIFT) 59 60 61 #define NPI_RXDMA_ERROR RXDMA_ER_ST 62 63 #define NPI_RXDMA_SW_PARAM_ERROR (NPI_RXDMA_ERROR | 0x40) 64 #define NPI_RXDMA_HW_ERROR (NPI_RXDMA_ERROR | 0x80) 65 66 #define NPI_RXDMA_RDC_INVALID (NPI_RXDMA_ERROR | CHANNEL_INVALID) 67 #define NPI_RXDMA_PAGE_INVALID (NPI_RXDMA_ERROR | LOGICAL_PAGE_INVALID) 68 #define NPI_RXDMA_RESET_ERR (NPI_RXDMA_HW_ERROR | RESET_FAILED) 69 #define NPI_RXDMA_DISABLE_ERR (NPI_RXDMA_HW_ERROR | 0x0000a) 70 #define NPI_RXDMA_ENABLE_ERR (NPI_RXDMA_HW_ERROR | 0x0000b) 71 #define NPI_RXDMA_FUNC_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000a) 72 #define NPI_RXDMA_BUFSIZE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000b) 73 #define NPI_RXDMA_RBRSIZE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000c) 74 #define NPI_RXDMA_RCRSIZE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000d) 75 #define NPI_RXDMA_PORT_INVALID (NPI_RXDMA_ERROR | PORT_INVALID) 76 #define NPI_RXDMA_TABLE_INVALID (NPI_RXDMA_ERROR | RDC_TAB_INVALID) 77 78 #define NPI_RXDMA_CHANNEL_INVALID(n) (RXDMA_ID_SHIFT(n) | \ 79 NPI_RXDMA_ERROR | CHANNEL_INVALID) 80 #define NPI_RXDMA_OPCODE_INVALID(n) (RXDMA_ID_SHIFT(n) | \ 81 NPI_RXDMA_ERROR | OPCODE_INVALID) 82 83 84 #define NPI_RXDMA_ERROR_ENCODE(err, rdc) \ 85 (RXDMA_ID_SHIFT(rdc) | RXDMA_ER_ST | err) 86 87 88 #define RXDMA_CHANNEL_VALID(rdc) \ 89 ((rdc < NXGE_MAX_RDCS)) 90 91 #define RXDMA_PORT_VALID(port) \ 92 ((port < MAX_PORTS_PER_NXGE)) 93 94 #define RXDMA_TABLE_VALID(table) \ 95 ((table < NXGE_MAX_RDC_GROUPS)) 96 97 98 #define RXDMA_PAGE_VALID(page) \ 99 ((page == 0) || (page == 1)) 100 101 #define RXDMA_BUFF_OFFSET_VALID(offset) \ 102 ((offset == SW_OFFSET_NO_OFFSET) || \ 103 (offset == SW_OFFSET_64) || \ 104 (offset == SW_OFFSET_128)) 105 106 107 #define RXDMA_RCR_TO_VALID(tov) ((tov) && (tov < 64)) 108 #define RXDMA_RCR_THRESH_VALID(thresh) ((thresh) && (thresh < 512)) 109 110 /* 111 * RXDMA NPI defined control types. 112 */ 113 typedef enum _rxdma_cs_cntl_e { 114 RXDMA_CS_CLEAR_ALL = 0x1, 115 RXDMA_MEX_SET = 0x2, 116 RXDMA_RCRTO_CLEAR = 0x8, 117 RXDMA_PT_DROP_PKT_CLEAR = 0x10, 118 RXDMA_WRED_DROP_CLEAR = 0x20, 119 RXDMA_RCR_SFULL_CLEAR = 0x40, 120 RXDMA_RCR_FULL_CLEAR = 0x80, 121 RXDMA_RBR_PRE_EMPTY_CLEAR = 0x100, 122 RXDMA_RBR_EMPTY_CLEAR = 0x200 123 } rxdma_cs_cntl_t; 124 125 /* 126 * RXDMA NPI defined event masks (mapped to the hardware defined masks). 127 */ 128 typedef enum _rxdma_ent_msk_cfg_e { 129 CFG_RXDMA_ENT_MSK_CFIGLOGPGE_MASK = RX_DMA_ENT_MSK_CFIGLOGPGE_MASK, 130 CFG_RXDMA_ENT_MSK_RBRLOGPGE_MASK = RX_DMA_ENT_MSK_RBRLOGPGE_MASK, 131 CFG_RXDMA_ENT_MSK_RBRFULL_MASK = RX_DMA_ENT_MSK_RBRFULL_MASK, 132 CFG_RXDMA_ENT_MSK_RBREMPTY_MASK = RX_DMA_ENT_MSK_RBREMPTY_MASK, 133 CFG_RXDMA_ENT_MSK_RCRFULL_MASK = RX_DMA_ENT_MSK_RCRFULL_MASK, 134 CFG_RXDMA_ENT_MSK_RCRINCON_MASK = RX_DMA_ENT_MSK_RCRINCON_MASK, 135 CFG_RXDMA_ENT_MSK_CONFIG_ERR = RX_DMA_ENT_MSK_CONFIG_ERR_MASK, 136 CFG_RXDMA_ENT_MSK_RCR_SH_FULL_MASK = RX_DMA_ENT_MSK_RCRSH_FULL_MASK, 137 CFG_RXDMA_ENT_MSK_RBR_PRE_EMTY_MASK = RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK, 138 CFG_RXDMA_ENT_MSK_WRED_DROP_MASK = RX_DMA_ENT_MSK_WRED_DROP_MASK, 139 CFG_RXDMA_ENT_MSK_PT_DROP_PKT_MASK = RX_DMA_ENT_MSK_PTDROP_PKT_MASK, 140 CFG_RXDMA_ENT_MSK_RBR_PRE_PAR_MASK = RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK, 141 CFG_RXDMA_ENT_MSK_RCR_SHA_PAR_MASK = RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK, 142 CFG_RXDMA_ENT_MSK_RCRTO_MASK = RX_DMA_ENT_MSK_RCRTO_MASK, 143 CFG_RXDMA_ENT_MSK_THRES_MASK = RX_DMA_ENT_MSK_THRES_MASK, 144 CFG_RXDMA_ENT_MSK_DC_FIFO_ERR_MASK = RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK, 145 CFG_RXDMA_ENT_MSK_RCR_ACK_ERR_MASK = RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK, 146 CFG_RXDMA_ENT_MSK_RSP_DAT_ERR_MASK = RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK, 147 CFG_RXDMA_ENT_MSK_BYTE_EN_BUS_MASK = RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK, 148 CFG_RXDMA_ENT_MSK_RSP_CNT_ERR_MASK = RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK, 149 CFG_RXDMA_ENT_MSK_RBR_TMOUT_MASK = RX_DMA_ENT_MSK_RBR_TMOUT_MASK, 150 151 CFG_RXDMA_MASK_ALL = (RX_DMA_ENT_MSK_CFIGLOGPGE_MASK | 152 RX_DMA_ENT_MSK_RBRLOGPGE_MASK | 153 RX_DMA_ENT_MSK_RBRFULL_MASK | 154 RX_DMA_ENT_MSK_RBREMPTY_MASK | 155 RX_DMA_ENT_MSK_RCRFULL_MASK | 156 RX_DMA_ENT_MSK_RCRINCON_MASK | 157 RX_DMA_ENT_MSK_CONFIG_ERR_MASK | 158 RX_DMA_ENT_MSK_RCRSH_FULL_MASK | 159 RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK | 160 RX_DMA_ENT_MSK_WRED_DROP_MASK | 161 RX_DMA_ENT_MSK_PTDROP_PKT_MASK | 162 RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK | 163 RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK | 164 RX_DMA_ENT_MSK_RCRTO_MASK | 165 RX_DMA_ENT_MSK_THRES_MASK | 166 RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK | 167 RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK | 168 RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK | 169 RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK | 170 RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK | 171 RX_DMA_ENT_MSK_RBR_TMOUT_MASK) 172 } rxdma_ent_msk_cfg_t; 173 174 175 176 typedef union _addr44 { 177 uint64_t addr; 178 struct { 179 #if defined(_BIG_ENDIAN) 180 uint32_t rsrvd:20; 181 uint32_t hdw:12; 182 uint32_t ldw; 183 #else 184 uint32_t ldw; 185 uint32_t hdw:12; 186 uint32_t rsrvd:20; 187 #endif 188 } bits; 189 } addr44_t; 190 191 192 /* 193 * npi_rxdma_cfg_default_port_rdc() 194 * Set the default rdc for the port 195 * 196 * Inputs: 197 * handle: register handle interpreted by the underlying OS 198 * portnm: Physical Port Number 199 * rdc: RX DMA Channel number 200 * 201 * Return: 202 * NPI_SUCCESS 203 * NPI_RXDMA_RDC_INVALID 204 * NPI_RXDMA_PORT_INVALID 205 * 206 */ 207 208 npi_status_t npi_rxdma_cfg_default_port_rdc(npi_handle_t, 209 uint8_t, uint8_t); 210 211 /* 212 * npi_rxdma_rdc_table_config 213 * Configure/populate the RDC table 214 * 215 * Inputs: 216 * handle: register handle interpreted by the underlying OS 217 * table: RDC Group Number 218 * map: Bitmap of RDCs to be written to <table>. 219 * count: A count of the number of bits in <map>. 220 * 221 * Return: 222 * NPI_SUCCESS 223 * NPI_RXDMA_TABLE_INVALID 224 * 225 */ 226 227 npi_status_t npi_rxdma_rdc_table_config(npi_handle_t, uint8_t, dc_map_t, 228 int); 229 230 npi_status_t npi_rxdma_cfg_rdc_table_default_rdc(npi_handle_t, 231 uint8_t, uint8_t); 232 npi_status_t npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t, 233 uint8_t); 234 235 236 /* 237 * npi_rxdma_32bitmode_enable() 238 * Enable 32 bit mode 239 * 240 * Inputs: 241 * handle: register handle interpreted by the underlying OS 242 * 243 * Return: 244 * NPI_SUCCESS 245 * NPI_FAILURE 246 * NPI_HW_ERR 247 * 248 */ 249 250 npi_status_t npi_rxdma_cfg_32bitmode_enable(npi_handle_t); 251 252 253 /* 254 * npi_rxdma_32bitmode_disable() 255 * disable 32 bit mode 256 * 257 * Inputs: 258 * handle: register handle interpreted by the underlying OS 259 * 260 * Return: 261 * NPI_SUCCESS 262 * NPI_FAILURE 263 * NPI_HW_ERR 264 * 265 */ 266 267 268 npi_status_t npi_rxdma_cfg_32bitmode_disable(npi_handle_t); 269 270 /* 271 * npi_rxdma_cfg_ram_access_enable() 272 * Enable PIO access to shadow and prefetch memory. 273 * In the case of DMA errors, software may need to 274 * initialize the shadow and prefetch memories to 275 * sane value (may be clear it) before re-enabling 276 * the DMA channel. 277 * 278 * Inputs: 279 * handle: register handle interpreted by the underlying OS 280 * 281 * Return: 282 * NPI_SUCCESS 283 * NPI_FAILURE 284 * NPI_HW_ERR 285 * 286 */ 287 288 npi_status_t npi_rxdma_cfg_ram_access_enable(npi_handle_t); 289 290 291 /* 292 * npi_rxdma_cfg_ram_access_disable() 293 * Disable PIO access to shadow and prefetch memory. 294 * This is the normal operation mode. 295 * 296 * Inputs: 297 * handle: register handle interpreted by the underlying OS 298 * 299 * Return: 300 * NPI_SUCCESS 301 * NPI_FAILURE 302 * NPI_HW_ERR 303 * 304 */ 305 306 npi_status_t npi_rxdma_cfg_ram_access_disable(npi_handle_t); 307 308 309 /* 310 * npi_rxdma_cfg_clock_div_set() 311 * init the clock division, used for RX timers 312 * This determines the granularity of RX DMA countdown timers 313 * It depends on the system clock. For example if the system 314 * clock is 300 MHz, a value of 30000 will yield a granularity 315 * of 100usec. 316 * 317 * Inputs: 318 * handle: register handle interpreted by the underlying OS 319 * count: System clock divider 320 * 321 * Return: 322 * NPI_SUCCESS 323 * NPI_FAILURE 324 * NPI_SW_ERR 325 * NPI_HW_ERR 326 * 327 */ 328 329 npi_status_t npi_rxdma_cfg_clock_div_set(npi_handle_t, uint16_t); 330 331 /* 332 * npi_rxdma_cfg_red_rand_init() 333 * init the WRED Discard 334 * By default, it is enabled 335 * 336 * Inputs: 337 * handle: register handle interpreted by the underlying OS 338 * init_value: WRED init value 339 * 340 * Return: 341 * NPI_SUCCESS 342 * NPI_FAILURE 343 * NPI_SW_ERR 344 * NPI_HW_ERR 345 * 346 */ 347 348 npi_status_t npi_rxdma_cfg_red_rand_init(npi_handle_t, uint16_t); 349 350 /* 351 * npi_rxdma_cfg_wred_disable() 352 * init the WRED Discard 353 * By default, it is enabled 354 * 355 * Inputs: 356 * handle: register handle interpreted by the underlying OS 357 * 358 * Return: 359 * NPI_SUCCESS 360 * NPI_FAILURE 361 * NPI_SW_ERR 362 * NPI_HW_ERR 363 * 364 */ 365 366 367 npi_status_t npi_rxdma_cfg_wred_disable(npi_handle_t); 368 369 /* 370 * npi_rxdma_cfg_wred_param() 371 * COnfigure per rxdma channel WRED parameters 372 * By default, it is enabled 373 * 374 * Inputs: 375 * handle: register handle interpreted by the underlying OS 376 * rdc: RX DMA Channel number 377 * wred_params: WRED configuration parameters 378 * 379 * Return: 380 * NPI_SUCCESS 381 * NPI_FAILURE 382 * NPI_SW_ERR 383 * NPI_HW_ERR 384 * 385 */ 386 387 388 389 npi_status_t npi_rxdma_cfg_wred_param(npi_handle_t, uint8_t, 390 rdc_red_para_t *); 391 392 393 /* 394 * npi_rxdma_port_ddr_weight 395 * Set the DDR weight for a port. 396 * 397 * Inputs: 398 * handle: register handle interpreted by the underlying OS 399 * portnm: Physical Port Number 400 * weight: Port relative weight (in approx. bytes) 401 * Default values are: 402 * 0x400 (port 0 and 1) corresponding to 10 standard 403 * size (1500 bytes) Frames 404 * 0x66 (port 2 and 3) corresponding to 10% 10Gig ports 405 * 406 * Return: 407 * NPI_SUCCESS 408 * NPI_FAILURE 409 * NPI_HW_ERR 410 * NPI_SW_ERR 411 * 412 */ 413 414 npi_status_t npi_rxdma_cfg_port_ddr_weight(npi_handle_t, 415 uint8_t, uint32_t); 416 417 418 /* 419 * npi_rxdma_port_usage_get() 420 * Gets the port usage, in terms of 16 byte blocks 421 * 422 * NOTE: The register count is cleared upon reading. 423 * 424 * Inputs: 425 * handle: register handle interpreted by the underlying OS 426 * portnm: Physical Port Number 427 * blocks: ptr to save current count. 428 * 429 * Return: 430 * NPI_SUCCESS 431 * NPI_FAILURE 432 * NPI_HW_ERR 433 * NPI_SW_ERR 434 * 435 */ 436 437 npi_status_t npi_rxdma_port_usage_get(npi_handle_t, 438 uint8_t, uint32_t *); 439 440 441 /* 442 * npi_rxdma_cfg_logical_page() 443 * Configure per rxdma channel Logical page 444 * 445 * To disable the logical page, set valid = 0; 446 * 447 * Inputs: 448 * handle: register handle interpreted by the underlying OS 449 * rdc: RX DMA Channel number 450 * page_params: Logical Page configuration parameters 451 * 452 * Return: 453 * NPI_SUCCESS 454 * NPI_FAILURE 455 * NPI_SW_ERR 456 * NPI_HW_ERR 457 * 458 */ 459 460 461 462 npi_status_t npi_rxdma_cfg_logical_page(npi_handle_t, uint8_t, 463 dma_log_page_t *); 464 465 466 /* 467 * npi_rxdma_cfg_logical_page_handle() 468 * Configure per rxdma channel Logical page handle 469 * 470 * 471 * Inputs: 472 * handle: register handle interpreted by the underlying OS 473 * rdc: RX DMA Channel number 474 * pg_handle: Logical Page handle 475 * 476 * Return: 477 * NPI_SUCCESS 478 * NPI_FAILURE 479 * NPI_SW_ERR 480 * NPI_HW_ERR 481 * 482 */ 483 484 485 npi_status_t npi_rxdma_cfg_logical_page_handle(npi_handle_t, uint8_t, 486 uint64_t); 487 488 489 490 491 npi_status_t npi_rxdma_cfg_logical_page_disable(npi_handle_t, 492 uint8_t, uint8_t); 493 494 typedef enum _bsize { 495 SIZE_0B = 0x0, 496 SIZE_64B, 497 SIZE_128B, 498 SIZE_192B, 499 SIZE_256B, 500 SIZE_512B, 501 SIZE_1KB, 502 SIZE_2KB, 503 SIZE_4KB, 504 SIZE_8KB, 505 SIZE_16KB, 506 SIZE_32KB 507 } bsize_t; 508 509 510 511 /* 512 * npi_rxdma_cfg_rdc_ring() 513 * Configure The RDC channel Rcv Buffer Ring 514 * 515 * Inputs: 516 * rdc: RX DMA Channel number 517 * rdc_params: RDC configuration parameters 518 * 519 * Return: 520 * NPI_SUCCESS 521 * NPI_FAILURE 522 * NPI_SW_ERR 523 * NPI_HW_ERR 524 * 525 */ 526 527 typedef struct _rdc_desc_cfg_t { 528 uint8_t mbox_enable; /* Enable full (18b) header */ 529 uint8_t full_hdr; /* Enable full (18b) header */ 530 uint8_t offset; /* 64 byte offsets */ 531 uint8_t valid2; /* size 2 is valid */ 532 bsize_t size2; /* Size 2 length */ 533 uint8_t valid1; /* size 1 is valid */ 534 bsize_t size1; /* Size 1 length */ 535 uint8_t valid0; /* size 0 is valid */ 536 bsize_t size0; /* Size 1 length */ 537 bsize_t page_size; /* Page or buffer Size */ 538 uint8_t rcr_timeout_enable; 539 uint8_t rcr_timeout; 540 uint16_t rcr_threshold; 541 uint16_t rcr_len; /* RBR Descriptor size (entries) */ 542 uint16_t rbr_len; /* RBR Descriptor size (entries) */ 543 uint64_t mbox_addr; /* Mailbox Address */ 544 uint64_t rcr_addr; /* RCR Address */ 545 uint64_t rbr_addr; /* RBB Address */ 546 } rdc_desc_cfg_t; 547 548 549 550 npi_status_t npi_rxdma_cfg_rdc_ring(npi_handle_t, uint8_t, 551 rdc_desc_cfg_t *); 552 553 554 555 556 /* 557 * npi_rxdma_rdc_rcr_flush 558 * Forces RX completion ring update 559 * 560 * Inputs: 561 * rdc: RX DMA Channel number 562 * 563 * Return: 564 * 565 */ 566 567 #define npi_rxdma_rdc_rcr_flush(handle, rdc) \ 568 RXDMA_REG_WRITE64(handle, RCR_FLSH_REG, rdc, \ 569 (RCR_FLSH_SET << RCR_FLSH_SHIFT)) 570 571 572 573 /* 574 * npi_rxdma_rdc_rcr_read_update 575 * Update the number of rcr packets and buffers processed 576 * 577 * Inputs: 578 * channel: RX DMA Channel number 579 * num_pkts: Number of pkts processed by SW. 580 * A packet could constitute multiple 581 * buffers, in case jumbo packets. 582 * num_bufs: Number of buffer processed by SW. 583 * 584 * Return: 585 * NPI_FAILURE - 586 * NPI_RXDMA_OPCODE_INVALID - 587 * NPI_RXDMA_CHANNEL_INVALID - 588 * 589 */ 590 591 npi_status_t npi_rxdma_rdc_rcr_read_update(npi_handle_t, uint8_t, 592 uint16_t, uint16_t); 593 /* 594 * npi_rxdma_rdc_rcr_pktread_update 595 * Update the number of packets processed 596 * 597 * Inputs: 598 * channel: RX DMA Channel number 599 * num_pkts: Number ofpkts processed by SW. 600 * A packet could constitute multiple 601 * buffers, in case jumbo packets. 602 * 603 * Return: 604 * NPI_FAILURE - 605 * NPI_RXDMA_OPCODE_INVALID - 606 * NPI_RXDMA_CHANNEL_INVALID - 607 * 608 */ 609 610 npi_status_t npi_rxdma_rdc_rcr_pktread_update(npi_handle_t, 611 uint8_t, uint16_t); 612 613 614 615 /* 616 * npi_rxdma_rdc_rcr_bufread_update 617 * Update the number of buffers processed 618 * 619 * Inputs: 620 * channel: RX DMA Channel number 621 * num_bufs: Number of buffer processed by SW. Multiple buffers 622 * could be part of a single packet. 623 * 624 * Return: 625 * NPI_FAILURE - 626 * NPI_RXDMA_OPCODE_INVALID - 627 * NPI_RXDMA_CHANNEL_INVALID - 628 * 629 */ 630 631 npi_status_t npi_rxdma_rdc_rcr_bufread_update(npi_handle_t, 632 uint8_t, uint16_t); 633 634 635 636 /* 637 * npi_rxdma_rdc_rbr_kick 638 * Kick RDC RBR 639 * 640 * Inputs: 641 * rdc: RX DMA Channel number 642 * num_buffers: Number of Buffers posted to the RBR 643 * 644 * Return: 645 * 646 */ 647 648 #define npi_rxdma_rdc_rbr_kick(handle, rdc, num_buffers) \ 649 RXDMA_REG_WRITE64(handle, RBR_KICK_REG, rdc, num_buffers) 650 651 652 /* 653 * npi_rxdma_rdc_rbr_head_get 654 * Gets the current rbr head pointer. 655 * 656 * Inputs: 657 * rdc: RX DMA Channel number 658 * hdptr ptr to write the rbr head value 659 * 660 * Return: 661 * 662 */ 663 664 npi_status_t npi_rxdma_rdc_rbr_head_get(npi_handle_t, 665 uint8_t, addr44_t *); 666 667 668 669 /* 670 * npi_rxdma_rdc_rbr_stat_get 671 * Returns the RBR stat. The stat consists of the 672 * RX buffers in the ring. It also indicates if there 673 * has been an overflow. 674 * 675 * Inputs: 676 * rdc: RX DMA Channel number 677 * rbr_stat_t: Structure to update stat 678 * 679 * Return: 680 * 681 */ 682 683 npi_status_t npi_rxdma_rdc_rbr_stat_get(npi_handle_t, uint8_t, 684 rbr_stat_t *); 685 686 687 688 /* 689 * npi_rxdma_cfg_rdc_reset 690 * Resets the RDC channel 691 * 692 * Inputs: 693 * rdc: RX DMA Channel number 694 * 695 * Return: 696 * 697 */ 698 699 npi_status_t npi_rxdma_cfg_rdc_reset(npi_handle_t, uint8_t); 700 701 702 /* 703 * npi_rxdma_rdc_enable 704 * Enables the RDC channel 705 * 706 * Inputs: 707 * rdc: RX DMA Channel number 708 * 709 * Return: 710 * 711 */ 712 713 npi_status_t npi_rxdma_cfg_rdc_enable(npi_handle_t, uint8_t); 714 715 /* 716 * npi_rxdma_rdc_disable 717 * Disables the RDC channel 718 * 719 * Inputs: 720 * rdc: RX DMA Channel number 721 * 722 * Return: 723 * 724 */ 725 726 npi_status_t npi_rxdma_cfg_rdc_disable(npi_handle_t, uint8_t); 727 728 729 /* 730 * npi_rxdma_cfg_rdc_rcr_timeout() 731 * Configure The RDC channel completion ring timeout. 732 * If a frame has been received, an event would be 733 * generated atleast at the expiration of the timeout. 734 * 735 * Enables timeout by default. 736 * 737 * Inputs: 738 * rdc: RX DMA Channel number 739 * rcr_timeout: Completion Ring timeout value 740 * 741 * Return: 742 * NPI_SUCCESS 743 * NPI_FAILURE 744 * NPI_SW_ERR 745 * NPI_HW_ERR 746 * 747 */ 748 749 npi_status_t npi_rxdma_cfg_rdc_rcr_timeout(npi_handle_t, uint8_t, 750 uint8_t); 751 752 753 /* 754 * npi_rxdma_cfg_rdc_rcr_threshold() 755 * Configure The RDC channel completion ring threshold. 756 * An event would be If the number of frame received, 757 * surpasses the threshold value 758 * 759 * Inputs: 760 * rdc: RX DMA Channel number 761 * rcr_threshold: Completion Ring Threshold count 762 * 763 * Return: 764 * NPI_SUCCESS 765 * NPI_FAILURE 766 * NPI_SW_ERR 767 * NPI_HW_ERR 768 * 769 */ 770 771 npi_status_t npi_rxdma_cfg_rdc_rcr_threshold(npi_handle_t, uint8_t, 772 uint16_t); 773 774 775 npi_status_t npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t, uint8_t); 776 777 typedef struct _rdc_error_stat_t { 778 uint8_t fault:1; 779 uint8_t multi_fault:1; 780 uint8_t rbr_fault:1; 781 uint8_t buff_fault:1; 782 uint8_t rcr_fault:1; 783 addr44_t fault_addr; 784 } rdc_error_stat_t; 785 786 #if OLD 787 /* 788 * npi_rxdma_rdc_error_stat_get 789 * Gets the current Error stat for the RDC. 790 * 791 * Inputs: 792 * rdc: RX DMA Channel number 793 * error_stat Structure to write current RDC Error stat 794 * 795 * Return: 796 * 797 */ 798 799 npi_status_t npi_rxdma_rdc_error_stat_get(npi_handle_t, 800 uint8_t, rdc_error_stat_t *); 801 802 #endif 803 804 /* 805 * npi_rxdma_rdc_rcr_tail_get 806 * Gets the current RCR tail address for the RDC. 807 * 808 * Inputs: 809 * rdc: RX DMA Channel number 810 * tail_addr Structure to write current RDC RCR tail address 811 * 812 * Return: 813 * 814 */ 815 816 npi_status_t npi_rxdma_rdc_rcr_tail_get(npi_handle_t, 817 uint8_t, addr44_t *); 818 819 820 npi_status_t npi_rxdma_rdc_rcr_qlen_get(npi_handle_t, 821 uint8_t, uint16_t *); 822 823 824 825 typedef struct _rdc_discard_stat_t { 826 uint8_t nobuf_ovflow; 827 uint8_t red_ovflow; 828 uint32_t nobuf_discard; 829 uint32_t red_discard; 830 } rdc_discard_stat_t; 831 832 833 /* 834 * npi_rxdma_rdc_discard_stat_get 835 * Gets the current discrad stats for the RDC. 836 * 837 * Inputs: 838 * rdc: RX DMA Channel number 839 * rcr_stat Structure to write current RDC discard stat 840 * 841 * Return: 842 * 843 */ 844 845 npi_status_t npi_rxdma_rdc_discard_stat_get(npi_handle_t, 846 uint8_t, rdc_discard_stat_t); 847 848 849 /* 850 * npi_rx_port_discard_stat_get 851 * Gets the current input (IPP) discrad stats for the rx port. 852 * 853 * Inputs: 854 * rdc: RX DMA Channel number 855 * rx_disc_cnt_t Structure to write current RDC discard stat 856 * 857 * Return: 858 * 859 */ 860 861 npi_status_t npi_rx_port_discard_stat_get(npi_handle_t, 862 uint8_t, 863 rx_disc_cnt_t *); 864 865 866 /* 867 * npi_rxdma_red_discard_stat_get 868 * Gets the current discrad count due RED 869 * The counter overflow bit is cleared, if it has been set. 870 * 871 * Inputs: 872 * rdc: RX DMA Channel number 873 * rx_disc_cnt_t Structure to write current RDC discard stat 874 * 875 * Return: 876 * NPI_SUCCESS 877 * NPI_RXDMA_RDC_INVALID 878 * 879 */ 880 881 npi_status_t npi_rxdma_red_discard_stat_get(npi_handle_t, uint8_t, 882 rx_disc_cnt_t *); 883 884 885 886 /* 887 * npi_rxdma_red_discard_oflow_clear 888 * Clear RED discard counter overflow bit 889 * 890 * Inputs: 891 * rdc: RX DMA Channel number 892 * 893 * Return: 894 * NPI_SUCCESS 895 * NPI_RXDMA_RDC_INVALID 896 * 897 */ 898 899 npi_status_t npi_rxdma_red_discard_oflow_clear(npi_handle_t, 900 uint8_t); 901 902 903 904 905 /* 906 * npi_rxdma_misc_discard_stat_get 907 * Gets the current discrad count for the rdc due to 908 * buffer pool empty 909 * The counter overflow bit is cleared, if it has been set. 910 * 911 * Inputs: 912 * rdc: RX DMA Channel number 913 * rx_disc_cnt_t Structure to write current RDC discard stat 914 * 915 * Return: 916 * NPI_SUCCESS 917 * NPI_RXDMA_RDC_INVALID 918 * 919 */ 920 921 npi_status_t npi_rxdma_misc_discard_stat_get(npi_handle_t, uint8_t, 922 rx_disc_cnt_t *); 923 924 925 926 /* 927 * npi_rxdma_red_discard_oflow_clear 928 * Clear RED discard counter overflow bit 929 * clear the overflow bit for buffer pool empty discrad counter 930 * for the rdc 931 * 932 * 933 * Inputs: 934 * rdc: RX DMA Channel number 935 * 936 * Return: 937 * NPI_SUCCESS 938 * NPI_RXDMA_RDC_INVALID 939 * 940 */ 941 942 npi_status_t npi_rxdma_misc_discard_oflow_clear(npi_handle_t, 943 uint8_t); 944 945 946 947 /* 948 * npi_rxdma_ring_perr_stat_get 949 * Gets the current RDC Memory parity error 950 * The counter overflow bit is cleared, if it has been set. 951 * 952 * Inputs: 953 * pre_cnt: Structure to write current RDC Prefetch memory 954 * Parity Error stat 955 * sha_cnt: Structure to write current RDC Shadow memory 956 * Parity Error stat 957 * 958 * Return: 959 * NPI_SUCCESS 960 * NPI_RXDMA_RDC_INVALID 961 * 962 */ 963 964 npi_status_t npi_rxdma_ring_perr_stat_get(npi_handle_t, 965 rdmc_par_err_log_t *, 966 rdmc_par_err_log_t *); 967 968 969 /* 970 * npi_rxdma_ring_perr_stat_get 971 * Clear RDC Memory Parity Error counter overflow bits 972 * 973 * Inputs: 974 * Return: 975 * NPI_SUCCESS 976 * 977 */ 978 979 npi_status_t npi_rxdma_ring_perr_stat_clear(npi_handle_t); 980 981 982 /* Access the RDMC Memory: used for debugging */ 983 984 npi_status_t npi_rxdma_rdmc_memory_io(npi_handle_t, 985 rdmc_mem_access_t *, uint8_t); 986 987 988 989 /* 990 * npi_rxdma_rxctl_fifo_error_intr_set 991 * Configure The RX ctrl fifo error interrupt generation 992 * 993 * Inputs: 994 * mask: rx_ctl_dat_fifo_mask_t specifying the errors 995 * 996 * Return: 997 * NPI_SUCCESS 998 * NPI_FAILURE 999 * 1000 */ 1001 1002 npi_status_t npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t, 1003 rx_ctl_dat_fifo_mask_t *); 1004 1005 /* 1006 * npi_rxdma_rxctl_fifo_error_status_get 1007 * Read The RX ctrl fifo error Status 1008 * 1009 * Inputs: 1010 * stat: rx_ctl_dat_fifo_stat_t to read the errors to 1011 * valid fields in rx_ctl_dat_fifo_stat_t structure are: 1012 * zcp_eop_err, ipp_eop_err, id_mismatch. 1013 * Return: 1014 * NPI_SUCCESS 1015 * NPI_FAILURE 1016 * 1017 */ 1018 1019 npi_status_t npi_rxdma_rxctl_fifo_error_status_get(npi_handle_t, 1020 rx_ctl_dat_fifo_stat_t *); 1021 1022 1023 /* 1024 * npi_rxdma_channel_mex_set(): 1025 * This function is called to arm the DMA channel with 1026 * mailbox updating capability. Software needs to rearm 1027 * for each update by writing to the control and status register. 1028 * 1029 * Parameters: 1030 * handle - NPI handle (virtualization flag must be defined). 1031 * channel - logical RXDMA channel from 0 to 23. 1032 * (If virtualization flag is not set, then 1033 * logical channel is the same as the hardware 1034 * channel number). 1035 * 1036 * Return: 1037 * NPI_SUCCESS - If enable channel with mailbox update 1038 * is complete successfully. 1039 * 1040 * Error: 1041 * NPI_FAILURE - 1042 * NPI_RXDMA_CHANNEL_INVALID - 1043 */ 1044 npi_status_t npi_rxdma_channel_mex_set(npi_handle_t, uint8_t); 1045 1046 /* 1047 * npi_rxdma_channel_rcrto_clear(): 1048 * This function is called to reset RCRTO bit to 0. 1049 * 1050 * Parameters: 1051 * handle - NPI handle (virtualization flag must be defined). 1052 * channel - logical RXDMA channel from 0 to 23. 1053 * (If virtualization flag is not set, then 1054 * logical channel is the same as the hardware 1055 * channel number). 1056 * Return: 1057 * NPI_SUCCESS 1058 * 1059 * Error: 1060 * NPI_FAILURE - 1061 * NPI_RXDMA_CHANNEL_INVALID - 1062 */ 1063 npi_status_t npi_rxdma_channel_rcrto_clear(npi_handle_t, uint8_t); 1064 1065 /* 1066 * npi_rxdma_channel_pt_drop_pkt_clear(): 1067 * This function is called to clear the port drop packet bit (debug). 1068 * 1069 * Parameters: 1070 * handle - NPI handle (virtualization flag must be defined). 1071 * channel - logical RXDMA channel from 0 to 23. 1072 * (If virtualization flag is not set, then 1073 * logical channel is the same as the hardware 1074 * channel number). 1075 * Return: 1076 * NPI_SUCCESS 1077 * 1078 * Error: 1079 * NPI_FAILURE - 1080 * NPI_RXDMA_CHANNEL_INVALID - 1081 */ 1082 npi_status_t npi_rxdma_channel_pt_drop_pkt_clear(npi_handle_t, uint8_t); 1083 1084 /* 1085 * npi_rxdma_channel_wred_drop_clear(): 1086 * This function is called to wred drop bit (debug only). 1087 * 1088 * Parameters: 1089 * handle - NPI handle (virtualization flag must be defined). 1090 * channel - logical RXDMA channel from 0 to 23. 1091 * (If virtualization flag is not set, then 1092 * logical channel is the same as the hardware 1093 * channel number). 1094 * Return: 1095 * NPI_SUCCESS 1096 * 1097 * Error: 1098 * NPI_FAILURE - 1099 * NPI_RXDMA_CHANNEL_INVALID - 1100 */ 1101 npi_status_t npi_rxdma_channel_wred_drop_clear(npi_handle_t, uint8_t); 1102 1103 /* 1104 * npi_rxdma_channel_rcr_shfull_clear(): 1105 * This function is called to clear RCR shadow full bit. 1106 * 1107 * Parameters: 1108 * handle - NPI handle (virtualization flag must be defined). 1109 * channel - logical RXDMA channel from 0 to 23. 1110 * (If virtualization flag is not set, then 1111 * logical channel is the same as the hardware 1112 * channel number). 1113 * Return: 1114 * NPI_SUCCESS 1115 * 1116 * Error: 1117 * NPI_FAILURE - 1118 * NPI_RXDMA_CHANNEL_INVALID - 1119 */ 1120 npi_status_t npi_rxdma_channel_rcr_shfull_clear(npi_handle_t, uint8_t); 1121 1122 /* 1123 * npi_rxdma_channel_rcrfull_clear(): 1124 * This function is called to clear RCR full bit. 1125 * 1126 * Parameters: 1127 * handle - NPI handle (virtualization flag must be defined). 1128 * channel - logical RXDMA channel from 0 to 23. 1129 * (If virtualization flag is not set, then 1130 * logical channel is the same as the hardware 1131 * channel number). 1132 * Return: 1133 * NPI_SUCCESS 1134 * 1135 * Error: 1136 * NPI_FAILURE - 1137 * NPI_RXDMA_CHANNEL_INVALID - 1138 */ 1139 npi_status_t npi_rxdma_channel_rcrfull_clear(npi_handle_t, uint8_t); 1140 1141 /* 1142 * npi_rxdma_rbr_pre_empty_clear(): 1143 * This function is called to control a receive DMA channel 1144 * for arming the channel with mailbox updates, resetting 1145 * various event status bits (control and status register). 1146 * 1147 * Parameters: 1148 * handle - NPI handle (virtualization flag must be defined). 1149 * control - NPI defined control type supported: 1150 * - RXDMA_MEX_SET 1151 * - RXDMA_RCRTO_CLEAR 1152 * - RXDMA_PT_DROP_PKT_CLEAR 1153 * - RXDMA_WRED_DROP_CLEAR 1154 * - RXDMA_RCR_SFULL_CLEAR 1155 * - RXDMA_RCR_FULL_CLEAR 1156 * - RXDMA_RBR_PRE_EMPTY_CLEAR 1157 * channel - logical RXDMA channel from 0 to 23. 1158 * (If virtualization flag is not set, then 1159 * logical channel is the same as the hardware. 1160 * Return: 1161 * NPI_SUCCESS 1162 * 1163 * Error: 1164 * NPI_FAILURE - 1165 * NPI_RXDMA_CHANNEL_INVALID - 1166 */ 1167 npi_status_t npi_rxdma_channel_rbr_pre_empty_clear(npi_handle_t, uint8_t); 1168 1169 /* 1170 * npi_rxdma_channel_control(): 1171 * This function is called to control a receive DMA channel 1172 * for arming the channel with mailbox updates, resetting 1173 * various event status bits (control and status register). 1174 * 1175 * Parameters: 1176 * handle - NPI handle (virtualization flag must be defined). 1177 * control - NPI defined control type supported: 1178 * - RXDMA_MEX_SET 1179 * - RXDMA_RCRTO_CLEAR 1180 * - RXDMA_PT_DROP_PKT_CLEAR 1181 * - RXDMA_WRED_DROP_CLEAR 1182 * - RXDMA_RCR_SFULL_CLEAR 1183 * - RXDMA_RCR_FULL_CLEAR 1184 * - RXDMA_RBR_PRE_EMPTY_CLEAR 1185 * channel - logical RXDMA channel from 0 to 23. 1186 * (If virtualization flag is not set, then 1187 * logical channel is the same as the hardware. 1188 * Return: 1189 * NPI_SUCCESS 1190 * 1191 * Error: 1192 * NPI_FAILURE - 1193 * NPI_TXDMA_OPCODE_INVALID - 1194 * NPI_TXDMA_CHANNEL_INVALID - 1195 */ 1196 npi_status_t npi_rxdma_channel_control(npi_handle_t, 1197 rxdma_cs_cntl_t, uint8_t); 1198 1199 /* 1200 * npi_rxdma_control_status(): 1201 * This function is called to operate on the control 1202 * and status register. 1203 * 1204 * Parameters: 1205 * handle - NPI handle 1206 * op_mode - OP_GET: get hardware control and status 1207 * OP_SET: set hardware control and status 1208 * OP_UPDATE: update hardware control and status. 1209 * OP_CLEAR: clear control and status register to 0s. 1210 * channel - hardware RXDMA channel from 0 to 23. 1211 * cs_p - pointer to hardware defined control and status 1212 * structure. 1213 * Return: 1214 * NPI_SUCCESS 1215 * 1216 * Error: 1217 * NPI_FAILURE - 1218 * NPI_RXDMA_OPCODE_INVALID - 1219 * NPI_RXDMA_CHANNEL_INVALID - 1220 */ 1221 npi_status_t npi_rxdma_control_status(npi_handle_t, io_op_t, 1222 uint8_t, p_rx_dma_ctl_stat_t); 1223 1224 /* 1225 * npi_rxdma_event_mask(): 1226 * This function is called to operate on the event mask 1227 * register which is used for generating interrupts. 1228 * 1229 * Parameters: 1230 * handle - NPI handle 1231 * op_mode - OP_GET: get hardware event mask 1232 * OP_SET: set hardware interrupt event masks 1233 * OP_CLEAR: clear control and status register to 0s. 1234 * channel - hardware RXDMA channel from 0 to 23. 1235 * mask_p - pointer to hardware defined event mask 1236 * structure. 1237 * Return: 1238 * NPI_SUCCESS - If set is complete successfully. 1239 * 1240 * Error: 1241 * NPI_FAILURE - 1242 * NPI_RXDMA_OPCODE_INVALID - 1243 * NPI_RXDMA_CHANNEL_INVALID - 1244 */ 1245 npi_status_t npi_rxdma_event_mask(npi_handle_t, io_op_t, 1246 uint8_t, p_rx_dma_ent_msk_t); 1247 1248 /* 1249 * npi_rxdma_event_mask_config(): 1250 * This function is called to operate on the event mask 1251 * register which is used for generating interrupts 1252 * and status register. 1253 * 1254 * Parameters: 1255 * handle - NPI handle 1256 * op_mode - OP_GET: get hardware event mask 1257 * OP_SET: set hardware interrupt event masks 1258 * OP_CLEAR: clear control and status register to 0s. 1259 * channel - hardware RXDMA channel from 0 to 23. 1260 * cfgp - pointer to NPI defined event mask 1261 * enum data type. 1262 * Return: 1263 * NPI_SUCCESS - If set is complete successfully. 1264 * 1265 * Error: 1266 * NPI_FAILURE - 1267 * NPI_RXDMA_OPCODE_INVALID - 1268 * NPI_RXDMA_CHANNEL_INVALID - 1269 */ 1270 npi_status_t npi_rxdma_event_mask_config(npi_handle_t, io_op_t, 1271 uint8_t, rxdma_ent_msk_cfg_t *); 1272 1273 1274 /* 1275 * npi_rxdma_dump_rdc_regs 1276 * Dumps the contents of rdc csrs and fzc registers 1277 * 1278 * Input: 1279 * rdc: RX DMA number 1280 * 1281 * return: 1282 * NPI_SUCCESS 1283 * NPI_FAILURE 1284 * NPI_RXDMA_RDC_INVALID 1285 * 1286 */ 1287 1288 npi_status_t npi_rxdma_dump_rdc_regs(npi_handle_t, uint8_t); 1289 1290 1291 /* 1292 * npi_rxdma_dump_fzc_regs 1293 * Dumps the contents of rdc csrs and fzc registers 1294 * 1295 * Input: 1296 * rdc: RX DMA number 1297 * 1298 * return: 1299 * NPI_SUCCESS 1300 * NPI_FAILURE 1301 * NPI_RXDMA_RDC_INVALID 1302 * 1303 */ 1304 1305 npi_status_t npi_rxdma_dump_fzc_regs(npi_handle_t); 1306 1307 npi_status_t npi_rxdma_channel_rbr_empty_clear(npi_handle_t, 1308 uint8_t); 1309 npi_status_t npi_rxdma_rxctl_fifo_error_intr_get(npi_handle_t, 1310 rx_ctl_dat_fifo_stat_t *); 1311 1312 npi_status_t npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t, 1313 rx_ctl_dat_fifo_mask_t *); 1314 1315 npi_status_t npi_rxdma_dump_rdc_table(npi_handle_t, uint8_t); 1316 #ifdef __cplusplus 1317 } 1318 #endif 1319 1320 #endif /* _NPI_RXDMA_H */ 1321