1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _NPI_RXDMA_H 27 #define _NPI_RXDMA_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #include <npi.h> 34 35 #include "nxge_defs.h" 36 #include "nxge_hw.h" 37 #include <nxge_rxdma_hw.h> 38 39 /* 40 * Register offset (0x200 bytes for each channel) for receive ring registers. 41 */ 42 #define NXGE_RXDMA_OFFSET(x, v, channel) (x + \ 43 (!v ? DMC_OFFSET(channel) : \ 44 RDMC_PIOVADDR_OFFSET(channel))) 45 46 47 #define REG_FZC_RDC_OFFSET(reg, rdc) (reg + RX_LOG_DMA_OFFSET(rdc)) 48 49 #define REG_RDC_TABLE_OFFSET(table) \ 50 (RDC_TBL_REG + table * (NXGE_MAX_RDCS * 8)) 51 52 /* 53 * RX NPI error codes 54 */ 55 #define RXDMA_ER_ST (RXDMA_BLK_ID << NPI_BLOCK_ID_SHIFT) 56 #define RXDMA_ID_SHIFT(n) (n << NPI_PORT_CHAN_SHIFT) 57 58 59 #define NPI_RXDMA_ERROR RXDMA_ER_ST 60 61 #define NPI_RXDMA_SW_PARAM_ERROR (NPI_RXDMA_ERROR | 0x40) 62 #define NPI_RXDMA_HW_ERROR (NPI_RXDMA_ERROR | 0x80) 63 64 #define NPI_RXDMA_RDC_INVALID (NPI_RXDMA_ERROR | CHANNEL_INVALID) 65 #define NPI_RXDMA_PAGE_INVALID (NPI_RXDMA_ERROR | LOGICAL_PAGE_INVALID) 66 #define NPI_RXDMA_RESET_ERR (NPI_RXDMA_HW_ERROR | RESET_FAILED) 67 #define NPI_RXDMA_DISABLE_ERR (NPI_RXDMA_HW_ERROR | 0x0000a) 68 #define NPI_RXDMA_ENABLE_ERR (NPI_RXDMA_HW_ERROR | 0x0000b) 69 #define NPI_RXDMA_FUNC_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000a) 70 #define NPI_RXDMA_BUFSIZE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000b) 71 #define NPI_RXDMA_RBRSIZE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000c) 72 #define NPI_RXDMA_RCRSIZE_INVALID (NPI_RXDMA_SW_PARAM_ERROR | 0x0000d) 73 #define NPI_RXDMA_PORT_INVALID (NPI_RXDMA_ERROR | PORT_INVALID) 74 #define NPI_RXDMA_TABLE_INVALID (NPI_RXDMA_ERROR | RDC_TAB_INVALID) 75 76 #define NPI_RXDMA_CHANNEL_INVALID(n) (RXDMA_ID_SHIFT(n) | \ 77 NPI_RXDMA_ERROR | CHANNEL_INVALID) 78 #define NPI_RXDMA_OPCODE_INVALID(n) (RXDMA_ID_SHIFT(n) | \ 79 NPI_RXDMA_ERROR | OPCODE_INVALID) 80 81 82 #define NPI_RXDMA_ERROR_ENCODE(err, rdc) \ 83 (RXDMA_ID_SHIFT(rdc) | RXDMA_ER_ST | err) 84 85 86 #define RXDMA_CHANNEL_VALID(rdc) \ 87 ((rdc < NXGE_MAX_RDCS)) 88 89 #define RXDMA_PORT_VALID(port) \ 90 ((port < MAX_PORTS_PER_NXGE)) 91 92 #define RXDMA_TABLE_VALID(table) \ 93 ((table < NXGE_MAX_RDC_GROUPS)) 94 95 96 #define RXDMA_PAGE_VALID(page) \ 97 ((page == 0) || (page == 1)) 98 99 #define RXDMA_BUFF_OFFSET_VALID(offset) \ 100 ((offset == SW_OFFSET_NO_OFFSET) || \ 101 (offset == SW_OFFSET_64) || \ 102 (offset == SW_OFFSET_128)) 103 104 #define RXDMA_RF_BUFF_OFFSET_VALID(offset) \ 105 ((offset == SW_OFFSET_NO_OFFSET) || \ 106 (offset == SW_OFFSET_64) || \ 107 (offset == SW_OFFSET_128) || \ 108 (offset == SW_OFFSET_192) || \ 109 (offset == SW_OFFSET_256) || \ 110 (offset == SW_OFFSET_320) || \ 111 (offset == SW_OFFSET_384) || \ 112 (offset == SW_OFFSET_448)) 113 114 115 #define RXDMA_RCR_TO_VALID(tov) ((tov) && (tov < 64)) 116 #define RXDMA_RCR_THRESH_VALID(thresh) ((thresh) && (thresh < 512)) 117 118 /* 119 * RXDMA NPI defined control types. 120 */ 121 typedef enum _rxdma_cs_cntl_e { 122 RXDMA_CS_CLEAR_ALL = 0x1, 123 RXDMA_MEX_SET = 0x2, 124 RXDMA_RCRTO_CLEAR = 0x8, 125 RXDMA_PT_DROP_PKT_CLEAR = 0x10, 126 RXDMA_WRED_DROP_CLEAR = 0x20, 127 RXDMA_RCR_SFULL_CLEAR = 0x40, 128 RXDMA_RCR_FULL_CLEAR = 0x80, 129 RXDMA_RBR_PRE_EMPTY_CLEAR = 0x100, 130 RXDMA_RBR_EMPTY_CLEAR = 0x200 131 } rxdma_cs_cntl_t; 132 133 /* 134 * RXDMA NPI defined event masks (mapped to the hardware defined masks). 135 */ 136 typedef enum _rxdma_ent_msk_cfg_e { 137 CFG_RXDMA_ENT_MSK_CFIGLOGPGE_MASK = RX_DMA_ENT_MSK_CFIGLOGPGE_MASK, 138 CFG_RXDMA_ENT_MSK_RBRLOGPGE_MASK = RX_DMA_ENT_MSK_RBRLOGPGE_MASK, 139 CFG_RXDMA_ENT_MSK_RBRFULL_MASK = RX_DMA_ENT_MSK_RBRFULL_MASK, 140 CFG_RXDMA_ENT_MSK_RBREMPTY_MASK = RX_DMA_ENT_MSK_RBREMPTY_MASK, 141 CFG_RXDMA_ENT_MSK_RCRFULL_MASK = RX_DMA_ENT_MSK_RCRFULL_MASK, 142 CFG_RXDMA_ENT_MSK_RCRINCON_MASK = RX_DMA_ENT_MSK_RCRINCON_MASK, 143 CFG_RXDMA_ENT_MSK_CONFIG_ERR = RX_DMA_ENT_MSK_CONFIG_ERR_MASK, 144 CFG_RXDMA_ENT_MSK_RCR_SH_FULL_MASK = RX_DMA_ENT_MSK_RCRSH_FULL_MASK, 145 CFG_RXDMA_ENT_MSK_RBR_PRE_EMTY_MASK = RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK, 146 CFG_RXDMA_ENT_MSK_WRED_DROP_MASK = RX_DMA_ENT_MSK_WRED_DROP_MASK, 147 CFG_RXDMA_ENT_MSK_PT_DROP_PKT_MASK = RX_DMA_ENT_MSK_PTDROP_PKT_MASK, 148 CFG_RXDMA_ENT_MSK_RBR_PRE_PAR_MASK = RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK, 149 CFG_RXDMA_ENT_MSK_RCR_SHA_PAR_MASK = RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK, 150 CFG_RXDMA_ENT_MSK_RCRTO_MASK = RX_DMA_ENT_MSK_RCRTO_MASK, 151 CFG_RXDMA_ENT_MSK_THRES_MASK = RX_DMA_ENT_MSK_THRES_MASK, 152 CFG_RXDMA_ENT_MSK_DC_FIFO_ERR_MASK = RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK, 153 CFG_RXDMA_ENT_MSK_RCR_ACK_ERR_MASK = RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK, 154 CFG_RXDMA_ENT_MSK_RSP_DAT_ERR_MASK = RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK, 155 CFG_RXDMA_ENT_MSK_BYTE_EN_BUS_MASK = RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK, 156 CFG_RXDMA_ENT_MSK_RSP_CNT_ERR_MASK = RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK, 157 CFG_RXDMA_ENT_MSK_RBR_TMOUT_MASK = RX_DMA_ENT_MSK_RBR_TMOUT_MASK, 158 159 CFG_RXDMA_MASK_ALL = (RX_DMA_ENT_MSK_CFIGLOGPGE_MASK | 160 RX_DMA_ENT_MSK_RBRLOGPGE_MASK | 161 RX_DMA_ENT_MSK_RBRFULL_MASK | 162 RX_DMA_ENT_MSK_RBREMPTY_MASK | 163 RX_DMA_ENT_MSK_RCRFULL_MASK | 164 RX_DMA_ENT_MSK_RCRINCON_MASK | 165 RX_DMA_ENT_MSK_CONFIG_ERR_MASK | 166 RX_DMA_ENT_MSK_RCRSH_FULL_MASK | 167 RX_DMA_ENT_MSK_RBR_PRE_EMPTY_MASK | 168 RX_DMA_ENT_MSK_WRED_DROP_MASK | 169 RX_DMA_ENT_MSK_PTDROP_PKT_MASK | 170 RX_DMA_ENT_MSK_RBR_PRE_PAR_MASK | 171 RX_DMA_ENT_MSK_RCR_SHA_PAR_MASK | 172 RX_DMA_ENT_MSK_RCRTO_MASK | 173 RX_DMA_ENT_MSK_THRES_MASK | 174 RX_DMA_ENT_MSK_DC_FIFO_ERR_MASK | 175 RX_DMA_ENT_MSK_RCR_ACK_ERR_MASK | 176 RX_DMA_ENT_MSK_RSP_DAT_ERR_MASK | 177 RX_DMA_ENT_MSK_BYTE_EN_BUS_MASK | 178 RX_DMA_ENT_MSK_RSP_CNT_ERR_MASK | 179 RX_DMA_ENT_MSK_RBR_TMOUT_MASK) 180 } rxdma_ent_msk_cfg_t; 181 182 183 184 typedef union _addr44 { 185 uint64_t addr; 186 struct { 187 #if defined(_BIG_ENDIAN) 188 uint32_t rsrvd:20; 189 uint32_t hdw:12; 190 uint32_t ldw; 191 #else 192 uint32_t ldw; 193 uint32_t hdw:12; 194 uint32_t rsrvd:20; 195 #endif 196 } bits; 197 } addr44_t; 198 199 200 /* 201 * npi_rxdma_cfg_default_port_rdc() 202 * Set the default rdc for the port 203 * 204 * Inputs: 205 * handle: register handle interpreted by the underlying OS 206 * portnm: Physical Port Number 207 * rdc: RX DMA Channel number 208 * 209 * Return: 210 * NPI_SUCCESS 211 * NPI_RXDMA_RDC_INVALID 212 * NPI_RXDMA_PORT_INVALID 213 * 214 */ 215 216 npi_status_t npi_rxdma_cfg_default_port_rdc(npi_handle_t, 217 uint8_t, uint8_t); 218 219 /* 220 * npi_rxdma_rdc_table_config 221 * Configure/populate the RDC table 222 * 223 * Inputs: 224 * handle: register handle interpreted by the underlying OS 225 * table: RDC Group Number 226 * map: Bitmap of RDCs to be written to <table>. 227 * count: A count of the number of bits in <map>. 228 * 229 * Return: 230 * NPI_SUCCESS 231 * NPI_RXDMA_TABLE_INVALID 232 * 233 */ 234 235 npi_status_t npi_rxdma_rdc_table_config(npi_handle_t, uint8_t, dc_map_t, 236 int); 237 238 npi_status_t npi_rxdma_cfg_rdc_table_default_rdc(npi_handle_t, 239 uint8_t, uint8_t); 240 npi_status_t npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t, 241 uint8_t); 242 243 244 /* 245 * npi_rxdma_32bitmode_enable() 246 * Enable 32 bit mode 247 * 248 * Inputs: 249 * handle: register handle interpreted by the underlying OS 250 * 251 * Return: 252 * NPI_SUCCESS 253 * NPI_FAILURE 254 * NPI_HW_ERR 255 * 256 */ 257 258 npi_status_t npi_rxdma_cfg_32bitmode_enable(npi_handle_t); 259 260 261 /* 262 * npi_rxdma_32bitmode_disable() 263 * disable 32 bit mode 264 * 265 * Inputs: 266 * handle: register handle interpreted by the underlying OS 267 * 268 * Return: 269 * NPI_SUCCESS 270 * NPI_FAILURE 271 * NPI_HW_ERR 272 * 273 */ 274 275 276 npi_status_t npi_rxdma_cfg_32bitmode_disable(npi_handle_t); 277 278 /* 279 * npi_rxdma_cfg_ram_access_enable() 280 * Enable PIO access to shadow and prefetch memory. 281 * In the case of DMA errors, software may need to 282 * initialize the shadow and prefetch memories to 283 * sane value (may be clear it) before re-enabling 284 * the DMA channel. 285 * 286 * Inputs: 287 * handle: register handle interpreted by the underlying OS 288 * 289 * Return: 290 * NPI_SUCCESS 291 * NPI_FAILURE 292 * NPI_HW_ERR 293 * 294 */ 295 296 npi_status_t npi_rxdma_cfg_ram_access_enable(npi_handle_t); 297 298 299 /* 300 * npi_rxdma_cfg_ram_access_disable() 301 * Disable PIO access to shadow and prefetch memory. 302 * This is the normal operation mode. 303 * 304 * Inputs: 305 * handle: register handle interpreted by the underlying OS 306 * 307 * Return: 308 * NPI_SUCCESS 309 * NPI_FAILURE 310 * NPI_HW_ERR 311 * 312 */ 313 314 npi_status_t npi_rxdma_cfg_ram_access_disable(npi_handle_t); 315 316 317 /* 318 * npi_rxdma_cfg_clock_div_set() 319 * init the clock division, used for RX timers 320 * This determines the granularity of RX DMA countdown timers 321 * It depends on the system clock. For example if the system 322 * clock is 300 MHz, a value of 30000 will yield a granularity 323 * of 100usec. 324 * 325 * Inputs: 326 * handle: register handle interpreted by the underlying OS 327 * count: System clock divider 328 * 329 * Return: 330 * NPI_SUCCESS 331 * NPI_FAILURE 332 * NPI_SW_ERR 333 * NPI_HW_ERR 334 * 335 */ 336 337 npi_status_t npi_rxdma_cfg_clock_div_set(npi_handle_t, uint16_t); 338 339 /* 340 * npi_rxdma_cfg_red_rand_init() 341 * init the WRED Discard 342 * By default, it is enabled 343 * 344 * Inputs: 345 * handle: register handle interpreted by the underlying OS 346 * init_value: WRED init value 347 * 348 * Return: 349 * NPI_SUCCESS 350 * NPI_FAILURE 351 * NPI_SW_ERR 352 * NPI_HW_ERR 353 * 354 */ 355 356 npi_status_t npi_rxdma_cfg_red_rand_init(npi_handle_t, uint16_t); 357 358 /* 359 * npi_rxdma_cfg_wred_disable() 360 * init the WRED Discard 361 * By default, it is enabled 362 * 363 * Inputs: 364 * handle: register handle interpreted by the underlying OS 365 * 366 * Return: 367 * NPI_SUCCESS 368 * NPI_FAILURE 369 * NPI_SW_ERR 370 * NPI_HW_ERR 371 * 372 */ 373 374 375 npi_status_t npi_rxdma_cfg_wred_disable(npi_handle_t); 376 377 /* 378 * npi_rxdma_cfg_wred_param() 379 * COnfigure per rxdma channel WRED parameters 380 * By default, it is enabled 381 * 382 * Inputs: 383 * handle: register handle interpreted by the underlying OS 384 * rdc: RX DMA Channel number 385 * wred_params: WRED configuration parameters 386 * 387 * Return: 388 * NPI_SUCCESS 389 * NPI_FAILURE 390 * NPI_SW_ERR 391 * NPI_HW_ERR 392 * 393 */ 394 395 396 397 npi_status_t npi_rxdma_cfg_wred_param(npi_handle_t, uint8_t, 398 rdc_red_para_t *); 399 400 401 /* 402 * npi_rxdma_port_ddr_weight 403 * Set the DDR weight for a port. 404 * 405 * Inputs: 406 * handle: register handle interpreted by the underlying OS 407 * portnm: Physical Port Number 408 * weight: Port relative weight (in approx. bytes) 409 * Default values are: 410 * 0x400 (port 0 and 1) corresponding to 10 standard 411 * size (1500 bytes) Frames 412 * 0x66 (port 2 and 3) corresponding to 10% 10Gig ports 413 * 414 * Return: 415 * NPI_SUCCESS 416 * NPI_FAILURE 417 * NPI_HW_ERR 418 * NPI_SW_ERR 419 * 420 */ 421 422 npi_status_t npi_rxdma_cfg_port_ddr_weight(npi_handle_t, 423 uint8_t, uint32_t); 424 425 426 /* 427 * npi_rxdma_port_usage_get() 428 * Gets the port usage, in terms of 16 byte blocks 429 * 430 * NOTE: The register count is cleared upon reading. 431 * 432 * Inputs: 433 * handle: register handle interpreted by the underlying OS 434 * portnm: Physical Port Number 435 * blocks: ptr to save current count. 436 * 437 * Return: 438 * NPI_SUCCESS 439 * NPI_FAILURE 440 * NPI_HW_ERR 441 * NPI_SW_ERR 442 * 443 */ 444 445 npi_status_t npi_rxdma_port_usage_get(npi_handle_t, 446 uint8_t, uint32_t *); 447 448 449 /* 450 * npi_rxdma_cfg_logical_page() 451 * Configure per rxdma channel Logical page 452 * 453 * To disable the logical page, set valid = 0; 454 * 455 * Inputs: 456 * handle: register handle interpreted by the underlying OS 457 * rdc: RX DMA Channel number 458 * page_params: Logical Page configuration parameters 459 * 460 * Return: 461 * NPI_SUCCESS 462 * NPI_FAILURE 463 * NPI_SW_ERR 464 * NPI_HW_ERR 465 * 466 */ 467 468 469 470 npi_status_t npi_rxdma_cfg_logical_page(npi_handle_t, uint8_t, 471 dma_log_page_t *); 472 473 474 /* 475 * npi_rxdma_cfg_logical_page_handle() 476 * Configure per rxdma channel Logical page handle 477 * 478 * 479 * Inputs: 480 * handle: register handle interpreted by the underlying OS 481 * rdc: RX DMA Channel number 482 * pg_handle: Logical Page handle 483 * 484 * Return: 485 * NPI_SUCCESS 486 * NPI_FAILURE 487 * NPI_SW_ERR 488 * NPI_HW_ERR 489 * 490 */ 491 492 493 npi_status_t npi_rxdma_cfg_logical_page_handle(npi_handle_t, uint8_t, 494 uint64_t); 495 496 497 498 499 npi_status_t npi_rxdma_cfg_logical_page_disable(npi_handle_t, 500 uint8_t, uint8_t); 501 502 typedef enum _bsize { 503 SIZE_0B = 0x0, 504 SIZE_64B, 505 SIZE_128B, 506 SIZE_192B, 507 SIZE_256B, 508 SIZE_512B, 509 SIZE_1KB, 510 SIZE_2KB, 511 SIZE_4KB, 512 SIZE_8KB, 513 SIZE_16KB, 514 SIZE_32KB 515 } bsize_t; 516 517 518 519 /* 520 * npi_rxdma_cfg_rdc_ring() 521 * Configure The RDC channel Rcv Buffer Ring 522 * 523 * Inputs: 524 * rdc: RX DMA Channel number 525 * rdc_params: RDC configuration parameters 526 * 527 * Return: 528 * NPI_SUCCESS 529 * NPI_FAILURE 530 * NPI_SW_ERR 531 * NPI_HW_ERR 532 * 533 */ 534 535 typedef struct _rdc_desc_cfg_t { 536 uint8_t mbox_enable; /* Enable full (18b) header */ 537 uint8_t full_hdr; /* Enable full (18b) header */ 538 uint8_t offset; /* 64 byte offsets */ 539 uint8_t valid2; /* size 2 is valid */ 540 bsize_t size2; /* Size 2 length */ 541 uint8_t valid1; /* size 1 is valid */ 542 bsize_t size1; /* Size 1 length */ 543 uint8_t valid0; /* size 0 is valid */ 544 bsize_t size0; /* Size 1 length */ 545 bsize_t page_size; /* Page or buffer Size */ 546 uint8_t rcr_timeout_enable; 547 uint8_t rcr_timeout; 548 uint16_t rcr_threshold; 549 uint16_t rcr_len; /* RBR Descriptor size (entries) */ 550 uint16_t rbr_len; /* RBR Descriptor size (entries) */ 551 uint64_t mbox_addr; /* Mailbox Address */ 552 uint64_t rcr_addr; /* RCR Address */ 553 uint64_t rbr_addr; /* RBB Address */ 554 } rdc_desc_cfg_t; 555 556 557 558 npi_status_t npi_rxdma_cfg_rdc_ring(npi_handle_t, uint8_t, 559 rdc_desc_cfg_t *, boolean_t); 560 561 562 563 564 /* 565 * npi_rxdma_rdc_rcr_flush 566 * Forces RX completion ring update 567 * 568 * Inputs: 569 * rdc: RX DMA Channel number 570 * 571 * Return: 572 * 573 */ 574 575 #define npi_rxdma_rdc_rcr_flush(handle, rdc) \ 576 RXDMA_REG_WRITE64(handle, RCR_FLSH_REG, rdc, \ 577 (RCR_FLSH_SET << RCR_FLSH_SHIFT)) 578 579 580 581 /* 582 * npi_rxdma_rdc_rcr_read_update 583 * Update the number of rcr packets and buffers processed 584 * 585 * Inputs: 586 * channel: RX DMA Channel number 587 * num_pkts: Number of pkts processed by SW. 588 * A packet could constitute multiple 589 * buffers, in case jumbo packets. 590 * num_bufs: Number of buffer processed by SW. 591 * 592 * Return: 593 * NPI_FAILURE - 594 * NPI_RXDMA_OPCODE_INVALID - 595 * NPI_RXDMA_CHANNEL_INVALID - 596 * 597 */ 598 599 npi_status_t npi_rxdma_rdc_rcr_read_update(npi_handle_t, uint8_t, 600 uint16_t, uint16_t); 601 /* 602 * npi_rxdma_rdc_rcr_pktread_update 603 * Update the number of packets processed 604 * 605 * Inputs: 606 * channel: RX DMA Channel number 607 * num_pkts: Number ofpkts processed by SW. 608 * A packet could constitute multiple 609 * buffers, in case jumbo packets. 610 * 611 * Return: 612 * NPI_FAILURE - 613 * NPI_RXDMA_OPCODE_INVALID - 614 * NPI_RXDMA_CHANNEL_INVALID - 615 * 616 */ 617 618 npi_status_t npi_rxdma_rdc_rcr_pktread_update(npi_handle_t, 619 uint8_t, uint16_t); 620 621 622 623 /* 624 * npi_rxdma_rdc_rcr_bufread_update 625 * Update the number of buffers processed 626 * 627 * Inputs: 628 * channel: RX DMA Channel number 629 * num_bufs: Number of buffer processed by SW. Multiple buffers 630 * could be part of a single packet. 631 * 632 * Return: 633 * NPI_FAILURE - 634 * NPI_RXDMA_OPCODE_INVALID - 635 * NPI_RXDMA_CHANNEL_INVALID - 636 * 637 */ 638 639 npi_status_t npi_rxdma_rdc_rcr_bufread_update(npi_handle_t, 640 uint8_t, uint16_t); 641 642 643 644 /* 645 * npi_rxdma_rdc_rbr_kick 646 * Kick RDC RBR 647 * 648 * Inputs: 649 * rdc: RX DMA Channel number 650 * num_buffers: Number of Buffers posted to the RBR 651 * 652 * Return: 653 * 654 */ 655 656 #define npi_rxdma_rdc_rbr_kick(handle, rdc, num_buffers) \ 657 RXDMA_REG_WRITE64(handle, RBR_KICK_REG, rdc, num_buffers) 658 659 660 /* 661 * npi_rxdma_rdc_rbr_head_get 662 * Gets the current rbr head pointer. 663 * 664 * Inputs: 665 * rdc: RX DMA Channel number 666 * hdptr ptr to write the rbr head value 667 * 668 * Return: 669 * 670 */ 671 672 npi_status_t npi_rxdma_rdc_rbr_head_get(npi_handle_t, 673 uint8_t, addr44_t *); 674 675 676 677 /* 678 * npi_rxdma_rdc_rbr_stat_get 679 * Returns the RBR stat. The stat consists of the 680 * RX buffers in the ring. It also indicates if there 681 * has been an overflow. 682 * 683 * Inputs: 684 * rdc: RX DMA Channel number 685 * rbr_stat_t: Structure to update stat 686 * 687 * Return: 688 * 689 */ 690 691 npi_status_t npi_rxdma_rdc_rbr_stat_get(npi_handle_t, uint8_t, 692 rbr_stat_t *); 693 694 695 696 /* 697 * npi_rxdma_cfg_rdc_reset 698 * Resets the RDC channel 699 * 700 * Inputs: 701 * rdc: RX DMA Channel number 702 * 703 * Return: 704 * 705 */ 706 707 npi_status_t npi_rxdma_cfg_rdc_reset(npi_handle_t, uint8_t); 708 709 710 /* 711 * npi_rxdma_rdc_enable 712 * Enables the RDC channel 713 * 714 * Inputs: 715 * rdc: RX DMA Channel number 716 * 717 * Return: 718 * 719 */ 720 721 npi_status_t npi_rxdma_cfg_rdc_enable(npi_handle_t, uint8_t); 722 723 /* 724 * npi_rxdma_rdc_disable 725 * Disables the RDC channel 726 * 727 * Inputs: 728 * rdc: RX DMA Channel number 729 * 730 * Return: 731 * 732 */ 733 734 npi_status_t npi_rxdma_cfg_rdc_disable(npi_handle_t, uint8_t); 735 736 737 /* 738 * npi_rxdma_cfg_rdc_rcr_timeout() 739 * Configure The RDC channel completion ring timeout. 740 * If a frame has been received, an event would be 741 * generated atleast at the expiration of the timeout. 742 * 743 * Enables timeout by default. 744 * 745 * Inputs: 746 * rdc: RX DMA Channel number 747 * rcr_timeout: Completion Ring timeout value 748 * 749 * Return: 750 * NPI_SUCCESS 751 * NPI_FAILURE 752 * NPI_SW_ERR 753 * NPI_HW_ERR 754 * 755 */ 756 757 npi_status_t npi_rxdma_cfg_rdc_rcr_timeout(npi_handle_t, uint8_t, 758 uint8_t); 759 760 761 /* 762 * npi_rxdma_cfg_rdc_rcr_threshold() 763 * Configure The RDC channel completion ring threshold. 764 * An event would be If the number of frame received, 765 * surpasses the threshold value 766 * 767 * Inputs: 768 * rdc: RX DMA Channel number 769 * rcr_threshold: Completion Ring Threshold count 770 * 771 * Return: 772 * NPI_SUCCESS 773 * NPI_FAILURE 774 * NPI_SW_ERR 775 * NPI_HW_ERR 776 * 777 */ 778 779 npi_status_t npi_rxdma_cfg_rdc_rcr_threshold(npi_handle_t, uint8_t, 780 uint16_t); 781 782 783 npi_status_t npi_rxdma_cfg_rdc_rcr_timeout_disable(npi_handle_t, uint8_t); 784 785 typedef struct _rdc_error_stat_t { 786 uint8_t fault:1; 787 uint8_t multi_fault:1; 788 uint8_t rbr_fault:1; 789 uint8_t buff_fault:1; 790 uint8_t rcr_fault:1; 791 addr44_t fault_addr; 792 } rdc_error_stat_t; 793 794 #if OLD 795 /* 796 * npi_rxdma_rdc_error_stat_get 797 * Gets the current Error stat for the RDC. 798 * 799 * Inputs: 800 * rdc: RX DMA Channel number 801 * error_stat Structure to write current RDC Error stat 802 * 803 * Return: 804 * 805 */ 806 807 npi_status_t npi_rxdma_rdc_error_stat_get(npi_handle_t, 808 uint8_t, rdc_error_stat_t *); 809 810 #endif 811 812 /* 813 * npi_rxdma_rdc_rcr_tail_get 814 * Gets the current RCR tail address for the RDC. 815 * 816 * Inputs: 817 * rdc: RX DMA Channel number 818 * tail_addr Structure to write current RDC RCR tail address 819 * 820 * Return: 821 * 822 */ 823 824 npi_status_t npi_rxdma_rdc_rcr_tail_get(npi_handle_t, 825 uint8_t, addr44_t *); 826 827 828 npi_status_t npi_rxdma_rdc_rcr_qlen_get(npi_handle_t, 829 uint8_t, uint16_t *); 830 831 832 833 typedef struct _rdc_discard_stat_t { 834 uint8_t nobuf_ovflow; 835 uint8_t red_ovflow; 836 uint32_t nobuf_discard; 837 uint32_t red_discard; 838 } rdc_discard_stat_t; 839 840 841 /* 842 * npi_rxdma_rdc_discard_stat_get 843 * Gets the current discrad stats for the RDC. 844 * 845 * Inputs: 846 * rdc: RX DMA Channel number 847 * rcr_stat Structure to write current RDC discard stat 848 * 849 * Return: 850 * 851 */ 852 853 npi_status_t npi_rxdma_rdc_discard_stat_get(npi_handle_t, 854 uint8_t, rdc_discard_stat_t); 855 856 857 /* 858 * npi_rx_port_discard_stat_get 859 * Gets the current input (IPP) discrad stats for the rx port. 860 * 861 * Inputs: 862 * rdc: RX DMA Channel number 863 * rx_disc_cnt_t Structure to write current RDC discard stat 864 * 865 * Return: 866 * 867 */ 868 869 npi_status_t npi_rx_port_discard_stat_get(npi_handle_t, 870 uint8_t, 871 rx_disc_cnt_t *); 872 873 874 /* 875 * npi_rxdma_red_discard_stat_get 876 * Gets the current discrad count due RED 877 * The counter overflow bit is cleared, if it has been set. 878 * 879 * Inputs: 880 * rdc: RX DMA Channel number 881 * rx_disc_cnt_t Structure to write current RDC discard stat 882 * 883 * Return: 884 * NPI_SUCCESS 885 * NPI_RXDMA_RDC_INVALID 886 * 887 */ 888 889 npi_status_t npi_rxdma_red_discard_stat_get(npi_handle_t, uint8_t, 890 rx_disc_cnt_t *); 891 892 893 894 /* 895 * npi_rxdma_red_discard_oflow_clear 896 * Clear RED discard counter overflow bit 897 * 898 * Inputs: 899 * rdc: RX DMA Channel number 900 * 901 * Return: 902 * NPI_SUCCESS 903 * NPI_RXDMA_RDC_INVALID 904 * 905 */ 906 907 npi_status_t npi_rxdma_red_discard_oflow_clear(npi_handle_t, 908 uint8_t); 909 910 911 912 913 /* 914 * npi_rxdma_misc_discard_stat_get 915 * Gets the current discrad count for the rdc due to 916 * buffer pool empty 917 * The counter overflow bit is cleared, if it has been set. 918 * 919 * Inputs: 920 * rdc: RX DMA Channel number 921 * rx_disc_cnt_t Structure to write current RDC discard stat 922 * 923 * Return: 924 * NPI_SUCCESS 925 * NPI_RXDMA_RDC_INVALID 926 * 927 */ 928 929 npi_status_t npi_rxdma_misc_discard_stat_get(npi_handle_t, uint8_t, 930 rx_disc_cnt_t *); 931 932 933 934 /* 935 * npi_rxdma_red_discard_oflow_clear 936 * Clear RED discard counter overflow bit 937 * clear the overflow bit for buffer pool empty discrad counter 938 * for the rdc 939 * 940 * 941 * Inputs: 942 * rdc: RX DMA Channel number 943 * 944 * Return: 945 * NPI_SUCCESS 946 * NPI_RXDMA_RDC_INVALID 947 * 948 */ 949 950 npi_status_t npi_rxdma_misc_discard_oflow_clear(npi_handle_t, 951 uint8_t); 952 953 954 955 /* 956 * npi_rxdma_ring_perr_stat_get 957 * Gets the current RDC Memory parity error 958 * The counter overflow bit is cleared, if it has been set. 959 * 960 * Inputs: 961 * pre_cnt: Structure to write current RDC Prefetch memory 962 * Parity Error stat 963 * sha_cnt: Structure to write current RDC Shadow memory 964 * Parity Error stat 965 * 966 * Return: 967 * NPI_SUCCESS 968 * NPI_RXDMA_RDC_INVALID 969 * 970 */ 971 972 npi_status_t npi_rxdma_ring_perr_stat_get(npi_handle_t, 973 rdmc_par_err_log_t *, 974 rdmc_par_err_log_t *); 975 976 977 /* 978 * npi_rxdma_ring_perr_stat_get 979 * Clear RDC Memory Parity Error counter overflow bits 980 * 981 * Inputs: 982 * Return: 983 * NPI_SUCCESS 984 * 985 */ 986 987 npi_status_t npi_rxdma_ring_perr_stat_clear(npi_handle_t); 988 989 990 /* Access the RDMC Memory: used for debugging */ 991 992 npi_status_t npi_rxdma_rdmc_memory_io(npi_handle_t, 993 rdmc_mem_access_t *, uint8_t); 994 995 996 997 /* 998 * npi_rxdma_rxctl_fifo_error_intr_set 999 * Configure The RX ctrl fifo error interrupt generation 1000 * 1001 * Inputs: 1002 * mask: rx_ctl_dat_fifo_mask_t specifying the errors 1003 * 1004 * Return: 1005 * NPI_SUCCESS 1006 * NPI_FAILURE 1007 * 1008 */ 1009 1010 npi_status_t npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t, 1011 rx_ctl_dat_fifo_mask_t *); 1012 1013 /* 1014 * npi_rxdma_rxctl_fifo_error_status_get 1015 * Read The RX ctrl fifo error Status 1016 * 1017 * Inputs: 1018 * stat: rx_ctl_dat_fifo_stat_t to read the errors to 1019 * valid fields in rx_ctl_dat_fifo_stat_t structure are: 1020 * zcp_eop_err, ipp_eop_err, id_mismatch. 1021 * Return: 1022 * NPI_SUCCESS 1023 * NPI_FAILURE 1024 * 1025 */ 1026 1027 npi_status_t npi_rxdma_rxctl_fifo_error_status_get(npi_handle_t, 1028 rx_ctl_dat_fifo_stat_t *); 1029 1030 1031 /* 1032 * npi_rxdma_channel_mex_set(): 1033 * This function is called to arm the DMA channel with 1034 * mailbox updating capability. Software needs to rearm 1035 * for each update by writing to the control and status register. 1036 * 1037 * Parameters: 1038 * handle - NPI handle (virtualization flag must be defined). 1039 * channel - logical RXDMA channel from 0 to 23. 1040 * (If virtualization flag is not set, then 1041 * logical channel is the same as the hardware 1042 * channel number). 1043 * 1044 * Return: 1045 * NPI_SUCCESS - If enable channel with mailbox update 1046 * is complete successfully. 1047 * 1048 * Error: 1049 * NPI_FAILURE - 1050 * NPI_RXDMA_CHANNEL_INVALID - 1051 */ 1052 npi_status_t npi_rxdma_channel_mex_set(npi_handle_t, uint8_t); 1053 1054 /* 1055 * npi_rxdma_channel_rcrto_clear(): 1056 * This function is called to reset RCRTO bit to 0. 1057 * 1058 * Parameters: 1059 * handle - NPI handle (virtualization flag must be defined). 1060 * channel - logical RXDMA channel from 0 to 23. 1061 * (If virtualization flag is not set, then 1062 * logical channel is the same as the hardware 1063 * channel number). 1064 * Return: 1065 * NPI_SUCCESS 1066 * 1067 * Error: 1068 * NPI_FAILURE - 1069 * NPI_RXDMA_CHANNEL_INVALID - 1070 */ 1071 npi_status_t npi_rxdma_channel_rcrto_clear(npi_handle_t, uint8_t); 1072 1073 /* 1074 * npi_rxdma_channel_pt_drop_pkt_clear(): 1075 * This function is called to clear the port drop packet bit (debug). 1076 * 1077 * Parameters: 1078 * handle - NPI handle (virtualization flag must be defined). 1079 * channel - logical RXDMA channel from 0 to 23. 1080 * (If virtualization flag is not set, then 1081 * logical channel is the same as the hardware 1082 * channel number). 1083 * Return: 1084 * NPI_SUCCESS 1085 * 1086 * Error: 1087 * NPI_FAILURE - 1088 * NPI_RXDMA_CHANNEL_INVALID - 1089 */ 1090 npi_status_t npi_rxdma_channel_pt_drop_pkt_clear(npi_handle_t, uint8_t); 1091 1092 /* 1093 * npi_rxdma_channel_wred_drop_clear(): 1094 * This function is called to wred drop bit (debug only). 1095 * 1096 * Parameters: 1097 * handle - NPI handle (virtualization flag must be defined). 1098 * channel - logical RXDMA channel from 0 to 23. 1099 * (If virtualization flag is not set, then 1100 * logical channel is the same as the hardware 1101 * channel number). 1102 * Return: 1103 * NPI_SUCCESS 1104 * 1105 * Error: 1106 * NPI_FAILURE - 1107 * NPI_RXDMA_CHANNEL_INVALID - 1108 */ 1109 npi_status_t npi_rxdma_channel_wred_drop_clear(npi_handle_t, uint8_t); 1110 1111 /* 1112 * npi_rxdma_channel_rcr_shfull_clear(): 1113 * This function is called to clear RCR shadow full bit. 1114 * 1115 * Parameters: 1116 * handle - NPI handle (virtualization flag must be defined). 1117 * channel - logical RXDMA channel from 0 to 23. 1118 * (If virtualization flag is not set, then 1119 * logical channel is the same as the hardware 1120 * channel number). 1121 * Return: 1122 * NPI_SUCCESS 1123 * 1124 * Error: 1125 * NPI_FAILURE - 1126 * NPI_RXDMA_CHANNEL_INVALID - 1127 */ 1128 npi_status_t npi_rxdma_channel_rcr_shfull_clear(npi_handle_t, uint8_t); 1129 1130 /* 1131 * npi_rxdma_channel_rcrfull_clear(): 1132 * This function is called to clear RCR full bit. 1133 * 1134 * Parameters: 1135 * handle - NPI handle (virtualization flag must be defined). 1136 * channel - logical RXDMA channel from 0 to 23. 1137 * (If virtualization flag is not set, then 1138 * logical channel is the same as the hardware 1139 * channel number). 1140 * Return: 1141 * NPI_SUCCESS 1142 * 1143 * Error: 1144 * NPI_FAILURE - 1145 * NPI_RXDMA_CHANNEL_INVALID - 1146 */ 1147 npi_status_t npi_rxdma_channel_rcrfull_clear(npi_handle_t, uint8_t); 1148 1149 /* 1150 * npi_rxdma_rbr_pre_empty_clear(): 1151 * This function is called to control a receive DMA channel 1152 * for arming the channel with mailbox updates, resetting 1153 * various event status bits (control and status register). 1154 * 1155 * Parameters: 1156 * handle - NPI handle (virtualization flag must be defined). 1157 * control - NPI defined control type supported: 1158 * - RXDMA_MEX_SET 1159 * - RXDMA_RCRTO_CLEAR 1160 * - RXDMA_PT_DROP_PKT_CLEAR 1161 * - RXDMA_WRED_DROP_CLEAR 1162 * - RXDMA_RCR_SFULL_CLEAR 1163 * - RXDMA_RCR_FULL_CLEAR 1164 * - RXDMA_RBR_PRE_EMPTY_CLEAR 1165 * channel - logical RXDMA channel from 0 to 23. 1166 * (If virtualization flag is not set, then 1167 * logical channel is the same as the hardware. 1168 * Return: 1169 * NPI_SUCCESS 1170 * 1171 * Error: 1172 * NPI_FAILURE - 1173 * NPI_RXDMA_CHANNEL_INVALID - 1174 */ 1175 npi_status_t npi_rxdma_channel_rbr_pre_empty_clear(npi_handle_t, uint8_t); 1176 1177 /* 1178 * npi_rxdma_channel_control(): 1179 * This function is called to control a receive DMA channel 1180 * for arming the channel with mailbox updates, resetting 1181 * various event status bits (control and status register). 1182 * 1183 * Parameters: 1184 * handle - NPI handle (virtualization flag must be defined). 1185 * control - NPI defined control type supported: 1186 * - RXDMA_MEX_SET 1187 * - RXDMA_RCRTO_CLEAR 1188 * - RXDMA_PT_DROP_PKT_CLEAR 1189 * - RXDMA_WRED_DROP_CLEAR 1190 * - RXDMA_RCR_SFULL_CLEAR 1191 * - RXDMA_RCR_FULL_CLEAR 1192 * - RXDMA_RBR_PRE_EMPTY_CLEAR 1193 * channel - logical RXDMA channel from 0 to 23. 1194 * (If virtualization flag is not set, then 1195 * logical channel is the same as the hardware. 1196 * Return: 1197 * NPI_SUCCESS 1198 * 1199 * Error: 1200 * NPI_FAILURE - 1201 * NPI_TXDMA_OPCODE_INVALID - 1202 * NPI_TXDMA_CHANNEL_INVALID - 1203 */ 1204 npi_status_t npi_rxdma_channel_control(npi_handle_t, 1205 rxdma_cs_cntl_t, uint8_t); 1206 1207 /* 1208 * npi_rxdma_control_status(): 1209 * This function is called to operate on the control 1210 * and status register. 1211 * 1212 * Parameters: 1213 * handle - NPI handle 1214 * op_mode - OP_GET: get hardware control and status 1215 * OP_SET: set hardware control and status 1216 * OP_UPDATE: update hardware control and status. 1217 * OP_CLEAR: clear control and status register to 0s. 1218 * channel - hardware RXDMA channel from 0 to 23. 1219 * cs_p - pointer to hardware defined control and status 1220 * structure. 1221 * Return: 1222 * NPI_SUCCESS 1223 * 1224 * Error: 1225 * NPI_FAILURE - 1226 * NPI_RXDMA_OPCODE_INVALID - 1227 * NPI_RXDMA_CHANNEL_INVALID - 1228 */ 1229 npi_status_t npi_rxdma_control_status(npi_handle_t, io_op_t, 1230 uint8_t, p_rx_dma_ctl_stat_t); 1231 1232 /* 1233 * npi_rxdma_event_mask(): 1234 * This function is called to operate on the event mask 1235 * register which is used for generating interrupts. 1236 * 1237 * Parameters: 1238 * handle - NPI handle 1239 * op_mode - OP_GET: get hardware event mask 1240 * OP_SET: set hardware interrupt event masks 1241 * OP_CLEAR: clear control and status register to 0s. 1242 * channel - hardware RXDMA channel from 0 to 23. 1243 * mask_p - pointer to hardware defined event mask 1244 * structure. 1245 * Return: 1246 * NPI_SUCCESS - If set is complete successfully. 1247 * 1248 * Error: 1249 * NPI_FAILURE - 1250 * NPI_RXDMA_OPCODE_INVALID - 1251 * NPI_RXDMA_CHANNEL_INVALID - 1252 */ 1253 npi_status_t npi_rxdma_event_mask(npi_handle_t, io_op_t, 1254 uint8_t, p_rx_dma_ent_msk_t); 1255 1256 /* 1257 * npi_rxdma_event_mask_config(): 1258 * This function is called to operate on the event mask 1259 * register which is used for generating interrupts 1260 * and status register. 1261 * 1262 * Parameters: 1263 * handle - NPI handle 1264 * op_mode - OP_GET: get hardware event mask 1265 * OP_SET: set hardware interrupt event masks 1266 * OP_CLEAR: clear control and status register to 0s. 1267 * channel - hardware RXDMA channel from 0 to 23. 1268 * cfgp - pointer to NPI defined event mask 1269 * enum data type. 1270 * Return: 1271 * NPI_SUCCESS - If set is complete successfully. 1272 * 1273 * Error: 1274 * NPI_FAILURE - 1275 * NPI_RXDMA_OPCODE_INVALID - 1276 * NPI_RXDMA_CHANNEL_INVALID - 1277 */ 1278 npi_status_t npi_rxdma_event_mask_config(npi_handle_t, io_op_t, 1279 uint8_t, rxdma_ent_msk_cfg_t *); 1280 1281 1282 /* 1283 * npi_rxdma_dump_rdc_regs 1284 * Dumps the contents of rdc csrs and fzc registers 1285 * 1286 * Input: 1287 * rdc: RX DMA number 1288 * 1289 * return: 1290 * NPI_SUCCESS 1291 * NPI_FAILURE 1292 * NPI_RXDMA_RDC_INVALID 1293 * 1294 */ 1295 1296 npi_status_t npi_rxdma_dump_rdc_regs(npi_handle_t, uint8_t); 1297 1298 1299 /* 1300 * npi_rxdma_dump_fzc_regs 1301 * Dumps the contents of rdc csrs and fzc registers 1302 * 1303 * Input: 1304 * rdc: RX DMA number 1305 * 1306 * return: 1307 * NPI_SUCCESS 1308 * NPI_FAILURE 1309 * NPI_RXDMA_RDC_INVALID 1310 * 1311 */ 1312 1313 npi_status_t npi_rxdma_dump_fzc_regs(npi_handle_t); 1314 1315 npi_status_t npi_rxdma_channel_rbr_empty_clear(npi_handle_t, 1316 uint8_t); 1317 npi_status_t npi_rxdma_rxctl_fifo_error_intr_get(npi_handle_t, 1318 rx_ctl_dat_fifo_stat_t *); 1319 1320 npi_status_t npi_rxdma_rxctl_fifo_error_intr_set(npi_handle_t, 1321 rx_ctl_dat_fifo_mask_t *); 1322 1323 npi_status_t npi_rxdma_dump_rdc_table(npi_handle_t, uint8_t); 1324 #ifdef __cplusplus 1325 } 1326 #endif 1327 1328 #endif /* _NPI_RXDMA_H */ 1329