1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <npi_mac.h> 27 28 #define MIF_DELAY 500 29 30 #define MAX_FRAME_SZ1 0x5EE 31 #define MAX_FRAME_SZ2 0x5F6 32 #define MAX_FRAME_SZ3 0x7D6 33 #define MAX_FRAME_SZ4 0x232E 34 #define MAX_FRAME_SZ5 0x2406 35 36 #define XMAC_WAIT_REG(handle, portn, reg, val) {\ 37 uint32_t cnt = MAX_PIO_RETRIES;\ 38 do {\ 39 NXGE_DELAY(MAC_RESET_WAIT);\ 40 XMAC_REG_RD(handle, portn, reg, &val);\ 41 cnt--;\ 42 } while (((val & 0x3) != 0) && (cnt > 0));\ 43 } 44 45 #define BMAC_WAIT_REG(handle, portn, reg, val) {\ 46 uint32_t cnt = MAX_PIO_RETRIES;\ 47 do {\ 48 NXGE_DELAY(MAC_RESET_WAIT);\ 49 BMAC_REG_RD(handle, portn, reg, &val);\ 50 cnt--;\ 51 } while (((val & 0x3) != 0) && (cnt > 0));\ 52 } 53 54 #define MIF_WAIT_REG(handle, m_frame, t_delay, interval, max_delay) { \ 55 do { \ 56 NXGE_DELAY(interval); \ 57 MIF_REG_RD(handle, MIF_OUTPUT_FRAME_REG, &m_frame.value); \ 58 t_delay++; \ 59 } while ((m_frame.bits.w0.ta_lsb == 0) && t_delay < max_delay); \ 60 } 61 62 uint64_t xmac_offset[] = { 63 XTXMAC_SW_RST_REG, 64 XRXMAC_SW_RST_REG, 65 XTXMAC_STATUS_REG, 66 XRXMAC_STATUS_REG, 67 XMAC_CTRL_STAT_REG, 68 XTXMAC_STAT_MSK_REG, 69 XRXMAC_STAT_MSK_REG, 70 XMAC_C_S_MSK_REG, 71 XMAC_CONFIG_REG, 72 XMAC_IPG_REG, 73 XMAC_MIN_REG, 74 XMAC_MAX_REG, 75 XMAC_ADDR0_REG, 76 XMAC_ADDR1_REG, 77 XMAC_ADDR2_REG, 78 XRXMAC_BT_CNT_REG, 79 XRXMAC_BC_FRM_CNT_REG, 80 XRXMAC_MC_FRM_CNT_REG, 81 XRXMAC_FRAG_CNT_REG, 82 XRXMAC_HIST_CNT1_REG, 83 XRXMAC_HIST_CNT2_REG, 84 XRXMAC_HIST_CNT3_REG, 85 XRXMAC_HIST_CNT4_REG, 86 XRXMAC_HIST_CNT5_REG, 87 XRXMAC_HIST_CNT6_REG, 88 XRXMAC_MPSZER_CNT_REG, 89 XRXMAC_CRC_ER_CNT_REG, 90 XRXMAC_CD_VIO_CNT_REG, 91 XRXMAC_AL_ER_CNT_REG, 92 XTXMAC_FRM_CNT_REG, 93 XTXMAC_BYTE_CNT_REG, 94 XMAC_LINK_FLT_CNT_REG, 95 XRXMAC_HIST_CNT7_REG, 96 XMAC_SM_REG, 97 XMAC_INTERN1_REG, 98 XMAC_INTERN2_REG, 99 XMAC_ADDR_CMPEN_REG, 100 XMAC_ADDR3_REG, 101 XMAC_ADDR4_REG, 102 XMAC_ADDR5_REG, 103 XMAC_ADDR6_REG, 104 XMAC_ADDR7_REG, 105 XMAC_ADDR8_REG, 106 XMAC_ADDR9_REG, 107 XMAC_ADDR10_REG, 108 XMAC_ADDR11_REG, 109 XMAC_ADDR12_REG, 110 XMAC_ADDR13_REG, 111 XMAC_ADDR14_REG, 112 XMAC_ADDR15_REG, 113 XMAC_ADDR16_REG, 114 XMAC_ADDR17_REG, 115 XMAC_ADDR18_REG, 116 XMAC_ADDR19_REG, 117 XMAC_ADDR20_REG, 118 XMAC_ADDR21_REG, 119 XMAC_ADDR22_REG, 120 XMAC_ADDR23_REG, 121 XMAC_ADDR24_REG, 122 XMAC_ADDR25_REG, 123 XMAC_ADDR26_REG, 124 XMAC_ADDR27_REG, 125 XMAC_ADDR28_REG, 126 XMAC_ADDR29_REG, 127 XMAC_ADDR30_REG, 128 XMAC_ADDR31_REG, 129 XMAC_ADDR32_REG, 130 XMAC_ADDR33_REG, 131 XMAC_ADDR34_REG, 132 XMAC_ADDR35_REG, 133 XMAC_ADDR36_REG, 134 XMAC_ADDR37_REG, 135 XMAC_ADDR38_REG, 136 XMAC_ADDR39_REG, 137 XMAC_ADDR40_REG, 138 XMAC_ADDR41_REG, 139 XMAC_ADDR42_REG, 140 XMAC_ADDR43_REG, 141 XMAC_ADDR44_REG, 142 XMAC_ADDR45_REG, 143 XMAC_ADDR46_REG, 144 XMAC_ADDR47_REG, 145 XMAC_ADDR48_REG, 146 XMAC_ADDR49_REG, 147 XMAC_ADDR50_REG, 148 XMAC_ADDR_FILT0_REG, 149 XMAC_ADDR_FILT1_REG, 150 XMAC_ADDR_FILT2_REG, 151 XMAC_ADDR_FILT12_MASK_REG, 152 XMAC_ADDR_FILT0_MASK_REG, 153 XMAC_HASH_TBL0_REG, 154 XMAC_HASH_TBL1_REG, 155 XMAC_HASH_TBL2_REG, 156 XMAC_HASH_TBL3_REG, 157 XMAC_HASH_TBL4_REG, 158 XMAC_HASH_TBL5_REG, 159 XMAC_HASH_TBL6_REG, 160 XMAC_HASH_TBL7_REG, 161 XMAC_HASH_TBL8_REG, 162 XMAC_HASH_TBL9_REG, 163 XMAC_HASH_TBL10_REG, 164 XMAC_HASH_TBL11_REG, 165 XMAC_HASH_TBL12_REG, 166 XMAC_HASH_TBL13_REG, 167 XMAC_HASH_TBL14_REG, 168 XMAC_HASH_TBL15_REG, 169 XMAC_HOST_INF0_REG, 170 XMAC_HOST_INF1_REG, 171 XMAC_HOST_INF2_REG, 172 XMAC_HOST_INF3_REG, 173 XMAC_HOST_INF4_REG, 174 XMAC_HOST_INF5_REG, 175 XMAC_HOST_INF6_REG, 176 XMAC_HOST_INF7_REG, 177 XMAC_HOST_INF8_REG, 178 XMAC_HOST_INF9_REG, 179 XMAC_HOST_INF10_REG, 180 XMAC_HOST_INF11_REG, 181 XMAC_HOST_INF12_REG, 182 XMAC_HOST_INF13_REG, 183 XMAC_HOST_INF14_REG, 184 XMAC_HOST_INF15_REG, 185 XMAC_HOST_INF16_REG, 186 XMAC_HOST_INF17_REG, 187 XMAC_HOST_INF18_REG, 188 XMAC_HOST_INF19_REG, 189 XMAC_PA_DATA0_REG, 190 XMAC_PA_DATA1_REG, 191 XMAC_DEBUG_SEL_REG, 192 XMAC_TRAINING_VECT_REG, 193 }; 194 195 const char *xmac_name[] = { 196 "XTXMAC_SW_RST_REG", 197 "XRXMAC_SW_RST_REG", 198 "XTXMAC_STATUS_REG", 199 "XRXMAC_STATUS_REG", 200 "XMAC_CTRL_STAT_REG", 201 "XTXMAC_STAT_MSK_REG", 202 "XRXMAC_STAT_MSK_REG", 203 "XMAC_C_S_MSK_REG", 204 "XMAC_CONFIG_REG", 205 "XMAC_IPG_REG", 206 "XMAC_MIN_REG", 207 "XMAC_MAX_REG", 208 "XMAC_ADDR0_REG", 209 "XMAC_ADDR1_REG", 210 "XMAC_ADDR2_REG", 211 "XRXMAC_BT_CNT_REG", 212 "XRXMAC_BC_FRM_CNT_REG", 213 "XRXMAC_MC_FRM_CNT_REG", 214 "XRXMAC_FRAG_CNT_REG", 215 "XRXMAC_HIST_CNT1_REG", 216 "XRXMAC_HIST_CNT2_REG", 217 "XRXMAC_HIST_CNT3_REG", 218 "XRXMAC_HIST_CNT4_REG", 219 "XRXMAC_HIST_CNT5_REG", 220 "XRXMAC_HIST_CNT6_REG", 221 "XRXMAC_MPSZER_CNT_REG", 222 "XRXMAC_CRC_ER_CNT_REG", 223 "XRXMAC_CD_VIO_CNT_REG", 224 "XRXMAC_AL_ER_CNT_REG", 225 "XTXMAC_FRM_CNT_REG", 226 "XTXMAC_BYTE_CNT_REG", 227 "XMAC_LINK_FLT_CNT_REG", 228 "XRXMAC_HIST_CNT7_REG", 229 "XMAC_SM_REG", 230 "XMAC_INTERN1_REG", 231 "XMAC_INTERN2_REG", 232 "XMAC_ADDR_CMPEN_REG", 233 "XMAC_ADDR3_REG", 234 "XMAC_ADDR4_REG", 235 "XMAC_ADDR5_REG", 236 "XMAC_ADDR6_REG", 237 "XMAC_ADDR7_REG", 238 "XMAC_ADDR8_REG", 239 "XMAC_ADDR9_REG", 240 "XMAC_ADDR10_REG", 241 "XMAC_ADDR11_REG", 242 "XMAC_ADDR12_REG", 243 "XMAC_ADDR13_REG", 244 "XMAC_ADDR14_REG", 245 "XMAC_ADDR15_REG", 246 "XMAC_ADDR16_REG", 247 "XMAC_ADDR17_REG", 248 "XMAC_ADDR18_REG", 249 "XMAC_ADDR19_REG", 250 "XMAC_ADDR20_REG", 251 "XMAC_ADDR21_REG", 252 "XMAC_ADDR22_REG", 253 "XMAC_ADDR23_REG", 254 "XMAC_ADDR24_REG", 255 "XMAC_ADDR25_REG", 256 "XMAC_ADDR26_REG", 257 "XMAC_ADDR27_REG", 258 "XMAC_ADDR28_REG", 259 "XMAC_ADDR29_REG", 260 "XMAC_ADDR30_REG", 261 "XMAC_ADDR31_REG", 262 "XMAC_ADDR32_REG", 263 "XMAC_ADDR33_REG", 264 "XMAC_ADDR34_REG", 265 "XMAC_ADDR35_REG", 266 "XMAC_ADDR36_REG", 267 "XMAC_ADDR37_REG", 268 "XMAC_ADDR38_REG", 269 "XMAC_ADDR39_REG", 270 "XMAC_ADDR40_REG", 271 "XMAC_ADDR41_REG", 272 "XMAC_ADDR42_REG", 273 "XMAC_ADDR43_REG", 274 "XMAC_ADDR44_REG", 275 "XMAC_ADDR45_REG", 276 "XMAC_ADDR46_REG", 277 "XMAC_ADDR47_REG", 278 "XMAC_ADDR48_REG", 279 "XMAC_ADDR49_REG", 280 "XMAC_ADDR50_RE", 281 "XMAC_ADDR_FILT0_REG", 282 "XMAC_ADDR_FILT1_REG", 283 "XMAC_ADDR_FILT2_REG", 284 "XMAC_ADDR_FILT12_MASK_REG", 285 "XMAC_ADDR_FILT0_MASK_REG", 286 "XMAC_HASH_TBL0_REG", 287 "XMAC_HASH_TBL1_REG", 288 "XMAC_HASH_TBL2_REG", 289 "XMAC_HASH_TBL3_REG", 290 "XMAC_HASH_TBL4_REG", 291 "XMAC_HASH_TBL5_REG", 292 "XMAC_HASH_TBL6_REG", 293 "XMAC_HASH_TBL7_REG", 294 "XMAC_HASH_TBL8_REG", 295 "XMAC_HASH_TBL9_REG", 296 "XMAC_HASH_TBL10_REG", 297 "XMAC_HASH_TBL11_REG", 298 "XMAC_HASH_TBL12_REG", 299 "XMAC_HASH_TBL13_REG", 300 "XMAC_HASH_TBL14_REG", 301 "XMAC_HASH_TBL15_REG", 302 "XMAC_HOST_INF0_REG", 303 "XMAC_HOST_INF1_REG", 304 "XMAC_HOST_INF2_REG", 305 "XMAC_HOST_INF3_REG", 306 "XMAC_HOST_INF4_REG", 307 "XMAC_HOST_INF5_REG", 308 "XMAC_HOST_INF6_REG", 309 "XMAC_HOST_INF7_REG", 310 "XMAC_HOST_INF8_REG", 311 "XMAC_HOST_INF9_REG", 312 "XMAC_HOST_INF10_REG", 313 "XMAC_HOST_INF11_REG", 314 "XMAC_HOST_INF12_REG", 315 "XMAC_HOST_INF13_REG", 316 "XMAC_HOST_INF14_REG", 317 "XMAC_HOST_INF15_REG", 318 "XMAC_HOST_INF16_REG", 319 "XMAC_HOST_INF17_REG", 320 "XMAC_HOST_INF18_REG", 321 "XMAC_HOST_INF19_REG", 322 "XMAC_PA_DATA0_REG", 323 "XMAC_PA_DATA1_REG", 324 "XMAC_DEBUG_SEL_REG", 325 "XMAC_TRAINING_VECT_REG", 326 }; 327 328 uint64_t bmac_offset[] = { 329 BTXMAC_SW_RST_REG, 330 BRXMAC_SW_RST_REG, 331 MAC_SEND_PAUSE_REG, 332 BTXMAC_STATUS_REG, 333 BRXMAC_STATUS_REG, 334 BMAC_CTRL_STAT_REG, 335 BTXMAC_STAT_MSK_REG, 336 BRXMAC_STAT_MSK_REG, 337 BMAC_C_S_MSK_REG, 338 TXMAC_CONFIG_REG, 339 RXMAC_CONFIG_REG, 340 MAC_CTRL_CONFIG_REG, 341 MAC_XIF_CONFIG_REG, 342 BMAC_MIN_REG, 343 BMAC_MAX_REG, 344 MAC_PA_SIZE_REG, 345 MAC_CTRL_TYPE_REG, 346 BMAC_ADDR0_REG, 347 BMAC_ADDR1_REG, 348 BMAC_ADDR2_REG, 349 BMAC_ADDR3_REG, 350 BMAC_ADDR4_REG, 351 BMAC_ADDR5_REG, 352 BMAC_ADDR6_REG, 353 BMAC_ADDR7_REG, 354 BMAC_ADDR8_REG, 355 BMAC_ADDR9_REG, 356 BMAC_ADDR10_REG, 357 BMAC_ADDR11_REG, 358 BMAC_ADDR12_REG, 359 BMAC_ADDR13_REG, 360 BMAC_ADDR14_REG, 361 BMAC_ADDR15_REG, 362 BMAC_ADDR16_REG, 363 BMAC_ADDR17_REG, 364 BMAC_ADDR18_REG, 365 BMAC_ADDR19_REG, 366 BMAC_ADDR20_REG, 367 BMAC_ADDR21_REG, 368 BMAC_ADDR22_REG, 369 BMAC_ADDR23_REG, 370 MAC_FC_ADDR0_REG, 371 MAC_FC_ADDR1_REG, 372 MAC_FC_ADDR2_REG, 373 MAC_ADDR_FILT0_REG, 374 MAC_ADDR_FILT1_REG, 375 MAC_ADDR_FILT2_REG, 376 MAC_ADDR_FILT12_MASK_REG, 377 MAC_ADDR_FILT00_MASK_REG, 378 MAC_HASH_TBL0_REG, 379 MAC_HASH_TBL1_REG, 380 MAC_HASH_TBL2_REG, 381 MAC_HASH_TBL3_REG, 382 MAC_HASH_TBL4_REG, 383 MAC_HASH_TBL5_REG, 384 MAC_HASH_TBL6_REG, 385 MAC_HASH_TBL7_REG, 386 MAC_HASH_TBL8_REG, 387 MAC_HASH_TBL9_REG, 388 MAC_HASH_TBL10_REG, 389 MAC_HASH_TBL11_REG, 390 MAC_HASH_TBL12_REG, 391 MAC_HASH_TBL13_REG, 392 MAC_HASH_TBL14_REG, 393 MAC_HASH_TBL15_REG, 394 RXMAC_FRM_CNT_REG, 395 MAC_LEN_ER_CNT_REG, 396 BMAC_AL_ER_CNT_REG, 397 BMAC_CRC_ER_CNT_REG, 398 BMAC_CD_VIO_CNT_REG, 399 BMAC_SM_REG, 400 BMAC_ALTAD_CMPEN_REG, 401 BMAC_HOST_INF0_REG, 402 BMAC_HOST_INF1_REG, 403 BMAC_HOST_INF2_REG, 404 BMAC_HOST_INF3_REG, 405 BMAC_HOST_INF4_REG, 406 BMAC_HOST_INF5_REG, 407 BMAC_HOST_INF6_REG, 408 BMAC_HOST_INF7_REG, 409 BMAC_HOST_INF8_REG, 410 BTXMAC_BYTE_CNT_REG, 411 BTXMAC_FRM_CNT_REG, 412 BRXMAC_BYTE_CNT_REG, 413 }; 414 415 const char *bmac_name[] = { 416 "BTXMAC_SW_RST_REG", 417 "BRXMAC_SW_RST_REG", 418 "MAC_SEND_PAUSE_REG", 419 "BTXMAC_STATUS_REG", 420 "BRXMAC_STATUS_REG", 421 "BMAC_CTRL_STAT_REG", 422 "BTXMAC_STAT_MSK_REG", 423 "BRXMAC_STAT_MSK_REG", 424 "BMAC_C_S_MSK_REG", 425 "TXMAC_CONFIG_REG", 426 "RXMAC_CONFIG_REG", 427 "MAC_CTRL_CONFIG_REG", 428 "MAC_XIF_CONFIG_REG", 429 "BMAC_MIN_REG", 430 "BMAC_MAX_REG", 431 "MAC_PA_SIZE_REG", 432 "MAC_CTRL_TYPE_REG", 433 "BMAC_ADDR0_REG", 434 "BMAC_ADDR1_REG", 435 "BMAC_ADDR2_REG", 436 "BMAC_ADDR3_REG", 437 "BMAC_ADDR4_REG", 438 "BMAC_ADDR5_REG", 439 "BMAC_ADDR6_REG", 440 "BMAC_ADDR7_REG", 441 "BMAC_ADDR8_REG", 442 "BMAC_ADDR9_REG", 443 "BMAC_ADDR10_REG", 444 "BMAC_ADDR11_REG", 445 "BMAC_ADDR12_REG", 446 "BMAC_ADDR13_REG", 447 "BMAC_ADDR14_REG", 448 "BMAC_ADDR15_REG", 449 "BMAC_ADDR16_REG", 450 "BMAC_ADDR17_REG", 451 "BMAC_ADDR18_REG", 452 "BMAC_ADDR19_REG", 453 "BMAC_ADDR20_REG", 454 "BMAC_ADDR21_REG", 455 "BMAC_ADDR22_REG", 456 "BMAC_ADDR23_REG", 457 "MAC_FC_ADDR0_REG", 458 "MAC_FC_ADDR1_REG", 459 "MAC_FC_ADDR2_REG", 460 "MAC_ADDR_FILT0_REG", 461 "MAC_ADDR_FILT1_REG", 462 "MAC_ADDR_FILT2_REG", 463 "MAC_ADDR_FILT12_MASK_REG", 464 "MAC_ADDR_FILT00_MASK_REG", 465 "MAC_HASH_TBL0_REG", 466 "MAC_HASH_TBL1_REG", 467 "MAC_HASH_TBL2_REG", 468 "MAC_HASH_TBL3_REG", 469 "MAC_HASH_TBL4_REG", 470 "MAC_HASH_TBL5_REG", 471 "MAC_HASH_TBL6_REG", 472 "MAC_HASH_TBL7_REG", 473 "MAC_HASH_TBL8_REG", 474 "MAC_HASH_TBL9_REG", 475 "MAC_HASH_TBL10_REG", 476 "MAC_HASH_TBL11_REG", 477 "MAC_HASH_TBL12_REG", 478 "MAC_HASH_TBL13_REG", 479 "MAC_HASH_TBL14_REG", 480 "MAC_HASH_TBL15_REG", 481 "RXMAC_FRM_CNT_REG", 482 "MAC_LEN_ER_CNT_REG", 483 "BMAC_AL_ER_CNT_REG", 484 "BMAC_CRC_ER_CNT_REG", 485 "BMAC_CD_VIO_CNT_REG", 486 "BMAC_SM_REG", 487 "BMAC_ALTAD_CMPEN_REG", 488 "BMAC_HOST_INF0_REG", 489 "BMAC_HOST_INF1_REG", 490 "BMAC_HOST_INF2_REG", 491 "BMAC_HOST_INF3_REG", 492 "BMAC_HOST_INF4_REG", 493 "BMAC_HOST_INF5_REG", 494 "BMAC_HOST_INF6_REG", 495 "BMAC_HOST_INF7_REG", 496 "BMAC_HOST_INF8_REG", 497 "BTXMAC_BYTE_CNT_REG", 498 "BTXMAC_FRM_CNT_REG", 499 "BRXMAC_BYTE_CNT_REG", 500 }; 501 502 npi_status_t 503 npi_mac_dump_regs(npi_handle_t handle, uint8_t port) 504 { 505 506 uint64_t value; 507 int num_regs, i; 508 509 ASSERT(IS_PORT_NUM_VALID(port)); 510 511 switch (port) { 512 case 0: 513 case 1: 514 num_regs = sizeof (xmac_offset) / sizeof (uint64_t); 515 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 516 "\nXMAC Register Dump for port %d\n", 517 port)); 518 for (i = 0; i < num_regs; i++) { 519 XMAC_REG_RD(handle, port, xmac_offset[i], &value); 520 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 521 "%08llx %s\t %08llx \n", 522 (XMAC_REG_ADDR((port), (xmac_offset[i]))), 523 xmac_name[i], value)); 524 } 525 526 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 527 "\n XMAC Register Dump for port %d done\n", 528 port)); 529 break; 530 531 case 2: 532 case 3: 533 num_regs = sizeof (bmac_offset) / sizeof (uint64_t); 534 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 535 "\nBMAC Register Dump for port %d\n", 536 port)); 537 for (i = 0; i < num_regs; i++) { 538 BMAC_REG_RD(handle, port, bmac_offset[i], &value); 539 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 540 "%08llx %s\t %08llx \n", 541 (BMAC_REG_ADDR((port), (bmac_offset[i]))), 542 bmac_name[i], value)); 543 } 544 545 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 546 "\n BMAC Register Dump for port %d done\n", 547 port)); 548 break; 549 } 550 551 return (NPI_SUCCESS); 552 } 553 554 npi_status_t 555 npi_mac_pcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 556 { 557 pcs_cfg_t pcs_cfg; 558 559 ASSERT(IS_PORT_NUM_VALID(portn)); 560 561 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.value); 562 pcs_cfg.bits.w0.mask = 0; 563 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.value); 564 565 return (NPI_SUCCESS); 566 } 567 568 npi_status_t 569 npi_mac_pcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 570 { 571 pcs_cfg_t pcs_cfg; 572 573 ASSERT(IS_PORT_NUM_VALID(portn)); 574 575 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.val.lsw); 576 pcs_cfg.bits.w0.mask = 1; 577 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.val.lsw); 578 579 return (NPI_SUCCESS); 580 } 581 582 npi_status_t 583 npi_xmac_xpcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 584 { 585 xpcs_stat1_t xpcs_mask1; 586 587 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 588 589 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 590 xpcs_mask1.bits.w0.csr_rx_link_stat = 1; 591 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 592 593 return (NPI_SUCCESS); 594 } 595 596 npi_status_t 597 npi_xmac_xpcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 598 { 599 xpcs_stat1_t xpcs_mask1; 600 601 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 602 603 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 604 xpcs_mask1.bits.w0.csr_rx_link_stat = 0; 605 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 606 607 return (NPI_SUCCESS); 608 } 609 610 npi_status_t 611 npi_mac_mif_link_intr_disable(npi_handle_t handle, uint8_t portn) 612 { 613 mif_cfg_t mif_cfg; 614 615 ASSERT(IS_PORT_NUM_VALID(portn)); 616 617 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.val.lsw); 618 619 mif_cfg.bits.w0.phy_addr = portn; 620 mif_cfg.bits.w0.poll_en = 0; 621 622 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.val.lsw); 623 624 NXGE_DELAY(20); 625 626 return (NPI_SUCCESS); 627 } 628 629 npi_status_t 630 npi_mac_hashtab_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 631 uint8_t entryn, uint16_t *data) 632 { 633 uint64_t val; 634 635 ASSERT((op == OP_GET) || (op == OP_SET)); 636 ASSERT(IS_PORT_NUM_VALID(portn)); 637 638 ASSERT(entryn < MAC_MAX_HASH_ENTRY); 639 if (entryn >= MAC_MAX_HASH_ENTRY) { 640 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 641 " npi_mac_hashtab_entry" 642 " Invalid Input: entryn <0x%x>", 643 entryn)); 644 return (NPI_FAILURE | NPI_MAC_HASHTAB_ENTRY_INVALID(portn)); 645 } 646 647 if (op == OP_SET) { 648 val = *data; 649 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 650 XMAC_REG_WR(handle, portn, 651 XMAC_HASH_TBLN_REG_ADDR(entryn), val); 652 } else { 653 BMAC_REG_WR(handle, portn, 654 BMAC_HASH_TBLN_REG_ADDR(entryn), val); 655 } 656 } else { 657 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 658 XMAC_REG_RD(handle, portn, 659 XMAC_HASH_TBLN_REG_ADDR(entryn), &val); 660 } else { 661 BMAC_REG_RD(handle, portn, 662 BMAC_HASH_TBLN_REG_ADDR(entryn), &val); 663 } 664 *data = val & 0xFFFF; 665 } 666 667 return (NPI_SUCCESS); 668 } 669 670 npi_status_t 671 npi_mac_hostinfo_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 672 uint8_t entryn, hostinfo_t *hostinfo) 673 { 674 ASSERT((op == OP_GET) || (op == OP_SET)); 675 ASSERT(IS_PORT_NUM_VALID(portn)); 676 677 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 678 ASSERT(entryn < XMAC_MAX_HOST_INFO_ENTRY); 679 if (entryn >= XMAC_MAX_HOST_INFO_ENTRY) { 680 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 681 " npi_mac_hostinfo_entry" 682 " Invalid Input: entryn <0x%x>", 683 entryn)); 684 return (NPI_FAILURE | 685 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 686 } 687 } else { 688 ASSERT(entryn < BMAC_MAX_HOST_INFO_ENTRY); 689 if (entryn >= BMAC_MAX_HOST_INFO_ENTRY) { 690 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 691 " npi_mac_hostinfo_entry" 692 " Invalid Input: entryn <0x%x>", 693 entryn)); 694 return (NPI_FAILURE | 695 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 696 } 697 } 698 699 if (op == OP_SET) { 700 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 701 XMAC_REG_WR(handle, portn, 702 XMAC_HOST_INFN_REG_ADDR(entryn), 703 hostinfo->value); 704 } else { 705 BMAC_REG_WR(handle, portn, 706 BMAC_HOST_INFN_REG_ADDR(entryn), 707 hostinfo->value); 708 } 709 } else { 710 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 711 XMAC_REG_RD(handle, portn, 712 XMAC_HOST_INFN_REG_ADDR(entryn), 713 &hostinfo->value); 714 } else { 715 BMAC_REG_RD(handle, portn, 716 BMAC_HOST_INFN_REG_ADDR(entryn), 717 &hostinfo->value); 718 } 719 } 720 721 return (NPI_SUCCESS); 722 } 723 724 npi_status_t 725 npi_mac_altaddr_enable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 726 { 727 uint64_t val; 728 729 ASSERT(IS_PORT_NUM_VALID(portn)); 730 731 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 732 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 733 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 734 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 735 " npi_mac_altaddr_enable" 736 " Invalid Input: addrn <0x%x>", 737 addrn)); 738 return (NPI_FAILURE | 739 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 740 } 741 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 742 val |= (1 << addrn); 743 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 744 } else { 745 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 746 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 747 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 748 " npi_mac_altaddr_enable" 749 " Invalid Input: addrn <0x%x>", 750 addrn)); 751 return (NPI_FAILURE | 752 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 753 } 754 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 755 val |= (1 << addrn); 756 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 757 } 758 759 return (NPI_SUCCESS); 760 } 761 762 /* 763 * While all bits of XMAC_ADDR_CMPEN_REG are for alternate MAC addresses, 764 * bit0 of BMAC_ALTAD_CMPEN_REG is for unique MAC address. 765 */ 766 npi_status_t 767 npi_mac_altaddr_disable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 768 { 769 uint64_t val; 770 771 ASSERT(IS_PORT_NUM_VALID(portn)); 772 773 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 774 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 775 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 776 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 777 " npi_mac_altaddr_disable" 778 " Invalid Input: addrn <0x%x>", 779 addrn)); 780 return (NPI_FAILURE | 781 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 782 } 783 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 784 val &= ~(1 << addrn); 785 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 786 } else { 787 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 788 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 789 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 790 " npi_mac_altaddr_disable" 791 " Invalid Input: addrn <0x%x>", 792 addrn)); 793 return (NPI_FAILURE | 794 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 795 } 796 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 797 val &= ~(1 << addrn); 798 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 799 } 800 801 return (NPI_SUCCESS); 802 } 803 804 npi_status_t 805 npi_mac_altaddr_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 806 uint8_t entryn, npi_mac_addr_t *data) 807 { 808 uint64_t val0, val1, val2; 809 810 ASSERT(IS_PORT_NUM_VALID(portn)); 811 ASSERT((op == OP_GET) || (op == OP_SET)); 812 813 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 814 ASSERT(entryn <= XMAC_MAX_ALT_ADDR_ENTRY); 815 if (entryn > XMAC_MAX_ALT_ADDR_ENTRY) { 816 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 817 " npi_mac_altaddr_entry" 818 " Invalid Input: entryn <0x%x>", 819 entryn)); 820 return (NPI_FAILURE | 821 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 822 } 823 if (op == OP_SET) { 824 val0 = data->w0; 825 val1 = data->w1; 826 val2 = data->w2; 827 XMAC_REG_WR(handle, portn, 828 XMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 829 XMAC_REG_WR(handle, portn, 830 XMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 831 XMAC_REG_WR(handle, portn, 832 XMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 833 } else { 834 XMAC_REG_RD(handle, portn, 835 XMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 836 XMAC_REG_RD(handle, portn, 837 XMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 838 XMAC_REG_RD(handle, portn, 839 XMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 840 data->w0 = val0 & 0xFFFF; 841 data->w1 = val1 & 0xFFFF; 842 data->w2 = val2 & 0xFFFF; 843 } 844 } else { 845 ASSERT(entryn <= BMAC_MAX_ALT_ADDR_ENTRY); 846 if (entryn > BMAC_MAX_ALT_ADDR_ENTRY) { 847 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 848 " npi_mac_altaddr_entry" 849 " Invalid Input: entryn <0x%x>", 850 entryn)); 851 return (NPI_FAILURE | 852 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 853 } 854 if (op == OP_SET) { 855 val0 = data->w0; 856 val1 = data->w1; 857 val2 = data->w2; 858 BMAC_REG_WR(handle, portn, 859 BMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 860 BMAC_REG_WR(handle, portn, 861 BMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 862 BMAC_REG_WR(handle, portn, 863 BMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 864 } else { 865 BMAC_REG_RD(handle, portn, 866 BMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 867 BMAC_REG_RD(handle, portn, 868 BMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 869 BMAC_REG_RD(handle, portn, 870 BMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 871 data->w0 = val0 & 0xFFFF; 872 data->w1 = val1 & 0xFFFF; 873 data->w2 = val2 & 0xFFFF; 874 } 875 } 876 877 return (NPI_SUCCESS); 878 } 879 880 npi_status_t 881 npi_mac_port_attr(npi_handle_t handle, io_op_t op, uint8_t portn, 882 npi_attr_t *attrp) 883 { 884 uint64_t val = 0; 885 uint32_t attr; 886 887 ASSERT(IS_PORT_NUM_VALID(portn)); 888 ASSERT((op == OP_GET) || (op == OP_SET)); 889 890 switch (attrp->type) { 891 case MAC_PORT_MODE: 892 switch (portn) { 893 case XMAC_PORT_0: 894 case XMAC_PORT_1: 895 if (op == OP_SET) { 896 attr = attrp->idata[0]; 897 ASSERT((attr == MAC_MII_MODE) || \ 898 (attr == MAC_GMII_MODE) || \ 899 (attr == MAC_XGMII_MODE)); 900 if ((attr != MAC_MII_MODE) && 901 (attr != MAC_GMII_MODE) && 902 (attr != MAC_XGMII_MODE)) { 903 NPI_ERROR_MSG((handle.function, 904 NPI_ERR_CTL, 905 " npi_mac_port_attr" 906 " Invalid Input:" 907 " MAC_PORT_MODE <0x%x>", 908 attr)); 909 return (NPI_FAILURE | 910 NPI_MAC_PORT_ATTR_INVALID(portn)); 911 } 912 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 913 &val); 914 val &= ~XMAC_XIF_MII_MODE_MASK; 915 switch (attr) { 916 case MAC_MII_MODE: 917 val |= (XMAC_XIF_MII_MODE << 918 XMAC_XIF_MII_MODE_SHIFT); 919 break; 920 case MAC_GMII_MODE: 921 val |= (XMAC_XIF_GMII_MODE << 922 XMAC_XIF_MII_MODE_SHIFT); 923 break; 924 case MAC_XGMII_MODE: 925 val |= (XMAC_XIF_XGMII_MODE << 926 XMAC_XIF_MII_MODE_SHIFT); 927 break; 928 default: 929 return (NPI_FAILURE | 930 NPI_MAC_PORT_ATTR_INVALID(portn)); 931 } 932 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, 933 val); 934 } else { 935 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 936 &val); 937 val &= XMAC_XIF_MII_MODE_MASK; 938 attr = val >> XMAC_XIF_MII_MODE_SHIFT; 939 attrp->odata[0] = attr; 940 } 941 break; 942 case BMAC_PORT_0: 943 case BMAC_PORT_1: 944 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 945 " npi_mac_port_attr" 946 " Invalid Input:" 947 " MAC_PORT_MODE <0x%x>", 948 attrp->type)); 949 return (NPI_FAILURE | 950 NPI_MAC_PORT_ATTR_INVALID(portn)); 951 default: 952 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 953 } 954 break; 955 956 case MAC_PORT_FRAME_SIZE: { 957 uint32_t min_fsize; 958 uint32_t max_fsize; 959 960 switch (portn) { 961 case XMAC_PORT_0: 962 case XMAC_PORT_1: 963 if (op == OP_SET) { 964 min_fsize = attrp->idata[0]; 965 max_fsize = attrp->idata[1]; 966 ASSERT((min_fsize & \ 967 ~XMAC_MIN_TX_FRM_SZ_MASK) == 0); 968 if ((min_fsize & ~XMAC_MIN_TX_FRM_SZ_MASK) 969 != 0) { 970 NPI_ERROR_MSG((handle.function, 971 NPI_ERR_CTL, 972 " npi_mac_port_attr" 973 " MAC_PORT_FRAME_SIZE:" 974 " Invalid Input:" 975 " xmac_min_fsize <0x%x>", 976 min_fsize)); 977 return (NPI_FAILURE | 978 NPI_MAC_PORT_ATTR_INVALID(portn)); 979 } 980 ASSERT((max_fsize & \ 981 ~XMAC_MAX_FRM_SZ_MASK) == 0); 982 if ((max_fsize & ~XMAC_MAX_FRM_SZ_MASK) 983 != 0) { 984 NPI_ERROR_MSG((handle.function, 985 NPI_ERR_CTL, 986 " npi_mac_port_attr" 987 " MAC_PORT_FRAME_SIZE:" 988 " Invalid Input:" 989 " xmac_max_fsize <0x%x>", 990 max_fsize)); 991 return (NPI_FAILURE | 992 NPI_MAC_PORT_ATTR_INVALID(portn)); 993 } 994 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 995 val &= ~(XMAC_MIN_TX_FRM_SZ_MASK | 996 XMAC_MIN_RX_FRM_SZ_MASK); 997 val |= (min_fsize << XMAC_MIN_TX_FRM_SZ_SHIFT); 998 val |= (min_fsize << XMAC_MIN_RX_FRM_SZ_SHIFT); 999 XMAC_REG_WR(handle, portn, XMAC_MIN_REG, val); 1000 XMAC_REG_WR(handle, portn, XMAC_MAX_REG, 1001 max_fsize); 1002 } else { 1003 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1004 min_fsize = (val & XMAC_MIN_TX_FRM_SZ_MASK) 1005 >> XMAC_MIN_TX_FRM_SZ_SHIFT; 1006 XMAC_REG_RD(handle, portn, XMAC_MAX_REG, &val); 1007 max_fsize = val & XMAC_MAX_FRM_SZ_MASK; 1008 attrp->odata[0] = min_fsize; 1009 attrp->odata[1] = max_fsize; 1010 } 1011 break; 1012 case BMAC_PORT_0: 1013 case BMAC_PORT_1: 1014 if (op == OP_SET) { 1015 min_fsize = attrp->idata[0]; 1016 max_fsize = attrp->idata[1]; 1017 ASSERT((min_fsize & ~BMAC_MIN_FRAME_MASK) == 0); 1018 if ((min_fsize & ~BMAC_MIN_FRAME_MASK) 1019 != 0) { 1020 NPI_ERROR_MSG((handle.function, 1021 NPI_ERR_CTL, 1022 " npi_mac_port_attr" 1023 " MAC_FRAME_SIZE:" 1024 " Invalid Input:" 1025 " bmac_min_fsize <0x%x>", 1026 min_fsize)); 1027 return (NPI_FAILURE | 1028 NPI_MAC_PORT_ATTR_INVALID(portn)); 1029 } 1030 ASSERT((max_fsize & ~BMAC_MAX_FRAME_MASK) == 0); 1031 if ((max_fsize & ~BMAC_MAX_FRAME_MASK) 1032 != 0) { 1033 NPI_ERROR_MSG((handle.function, 1034 NPI_ERR_CTL, 1035 " npi_mac_port_attr" 1036 " MAC_FRAME_SIZE:" 1037 " Invalid Input:" 1038 " bmac_max_fsize <0x%x>", 1039 max_fsize)); 1040 return (NPI_FAILURE | 1041 NPI_MAC_PORT_ATTR_INVALID(portn)); 1042 } 1043 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1044 val &= ~BMAC_MAX_FRAME_MASK; 1045 if (max_fsize <= MAX_FRAME_SZ1) 1046 val |= MAX_FRAME_SZ1; 1047 else if ((max_fsize > MAX_FRAME_SZ1) && 1048 (max_fsize <= MAX_FRAME_SZ2)) 1049 val |= MAX_FRAME_SZ2; 1050 else if ((max_fsize > MAX_FRAME_SZ2) && 1051 (max_fsize <= MAX_FRAME_SZ3)) 1052 val |= MAX_FRAME_SZ3; 1053 else if ((max_fsize > MAX_FRAME_SZ3) && 1054 (max_fsize <= MAX_FRAME_SZ4)) 1055 val |= MAX_FRAME_SZ4; 1056 else if ((max_fsize > MAX_FRAME_SZ4) && 1057 (max_fsize <= MAX_FRAME_SZ5)) 1058 val |= MAX_FRAME_SZ5; 1059 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1060 BMAC_REG_WR(handle, portn, BMAC_MIN_REG, 1061 min_fsize); 1062 } else { 1063 BMAC_REG_RD(handle, portn, BMAC_MIN_REG, &val); 1064 min_fsize = val & BMAC_MIN_FRAME_MASK; 1065 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1066 max_fsize = val & BMAC_MAX_FRAME_MASK; 1067 attrp->odata[0] = min_fsize; 1068 attrp->odata[1] = max_fsize; 1069 } 1070 break; 1071 default: 1072 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1073 } 1074 break; 1075 } 1076 1077 case BMAC_PORT_MAX_BURST_SIZE: { 1078 uint32_t burst_size; 1079 switch (portn) { 1080 case XMAC_PORT_0: 1081 case XMAC_PORT_1: 1082 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1083 " npi_mac_port_attr" 1084 " BMAC_PORT_MAX_BURST_SIZE:" 1085 " Invalid Input: portn <%d>", 1086 portn)); 1087 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1088 case BMAC_PORT_0: 1089 case BMAC_PORT_1: 1090 /* NOTE: Not used in Full duplex mode */ 1091 if (op == OP_SET) { 1092 burst_size = attrp->idata[0]; 1093 ASSERT((burst_size & ~0x7FFF) == 0); 1094 if ((burst_size & ~0x7FFF) != 0) { 1095 NPI_ERROR_MSG((handle.function, 1096 NPI_ERR_CTL, 1097 " npi_mac_port_attr" 1098 " BMAC_MAX_BURST_SIZE:" 1099 " Invalid Input:" 1100 " burst_size <0x%x>", 1101 burst_size)); 1102 return (NPI_FAILURE | 1103 NPI_MAC_PORT_ATTR_INVALID(portn)); 1104 } 1105 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1106 val &= ~BMAC_MAX_BURST_MASK; 1107 val |= (burst_size << BMAC_MAX_BURST_SHIFT); 1108 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1109 } else { 1110 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1111 burst_size = (val & BMAC_MAX_BURST_MASK) 1112 >> BMAC_MAX_BURST_SHIFT; 1113 attrp->odata[0] = burst_size; 1114 } 1115 break; 1116 default: 1117 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1118 } 1119 break; 1120 } 1121 1122 case BMAC_PORT_PA_SIZE: { 1123 uint32_t pa_size; 1124 switch (portn) { 1125 case XMAC_PORT_0: 1126 case XMAC_PORT_1: 1127 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1128 " npi_mac_port_attr" 1129 " BMAC_PORT_PA_SIZE:" 1130 " Invalid Input: portn <%d>", 1131 portn)); 1132 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1133 case BMAC_PORT_0: 1134 case BMAC_PORT_1: 1135 if (op == OP_SET) { 1136 pa_size = attrp->idata[0]; 1137 ASSERT((pa_size & ~0x3FF) == 0); 1138 if ((pa_size & ~0x3FF) != 0) { 1139 NPI_ERROR_MSG((handle.function, 1140 NPI_ERR_CTL, 1141 " npi_mac_port_attr" 1142 " BMAC_PORT_PA_SIZE:" 1143 " Invalid Input: pa_size <0x%x>", 1144 pa_size)); 1145 1146 return (NPI_FAILURE | 1147 NPI_MAC_PORT_ATTR_INVALID(portn)); 1148 } 1149 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1150 &val); 1151 val &= ~BMAC_PA_SIZE_MASK; 1152 val |= (pa_size << 0); 1153 BMAC_REG_WR(handle, portn, MAC_PA_SIZE_REG, 1154 val); 1155 } else { 1156 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1157 &val); 1158 pa_size = (val & BMAC_PA_SIZE_MASK) >> 0; 1159 attrp->odata[0] = pa_size; 1160 } 1161 break; 1162 default: 1163 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1164 } 1165 break; 1166 } 1167 1168 case BMAC_PORT_CTRL_TYPE: { 1169 uint32_t ctrl_type; 1170 switch (portn) { 1171 case XMAC_PORT_0: 1172 case XMAC_PORT_1: 1173 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1174 " npi_mac_port_attr" 1175 " BMAC_PORT_CTRL_TYPE:" 1176 " Invalid Input: portn <%d>", 1177 portn)); 1178 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1179 case BMAC_PORT_0: 1180 case BMAC_PORT_1: 1181 if (op == OP_SET) { 1182 ctrl_type = attrp->idata[0]; 1183 ASSERT((ctrl_type & ~0xFFFF) == 0); 1184 if ((ctrl_type & ~0xFFFF) != 0) { 1185 NPI_ERROR_MSG((handle.function, 1186 NPI_ERR_CTL, 1187 " npi_mac_port_attr" 1188 " BMAC_PORT_CTRL_TYPE:" 1189 " Invalid Input:" 1190 " ctrl_type <0x%x>", 1191 ctrl_type)); 1192 return (NPI_FAILURE | 1193 NPI_MAC_PORT_ATTR_INVALID(portn)); 1194 } 1195 BMAC_REG_WR(handle, portn, MAC_CTRL_TYPE_REG, 1196 val); 1197 } else { 1198 BMAC_REG_RD(handle, portn, MAC_CTRL_TYPE_REG, 1199 &val); 1200 ctrl_type = (val & 0xFFFF); 1201 attrp->odata[0] = ctrl_type; 1202 } 1203 break; 1204 default: 1205 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1206 } 1207 break; 1208 } 1209 1210 case XMAC_10G_PORT_IPG: 1211 { 1212 uint32_t ipg0; 1213 1214 switch (portn) { 1215 case XMAC_PORT_0: 1216 case XMAC_PORT_1: 1217 if (op == OP_SET) { 1218 ipg0 = attrp->idata[0]; 1219 ASSERT((ipg0 == XGMII_IPG_12_15) || \ 1220 (ipg0 == XGMII_IPG_16_19) || \ 1221 (ipg0 == XGMII_IPG_20_23)); 1222 if ((ipg0 != XGMII_IPG_12_15) && 1223 (ipg0 != XGMII_IPG_16_19) && 1224 (ipg0 != XGMII_IPG_20_23)) { 1225 NPI_ERROR_MSG((handle.function, 1226 NPI_ERR_CTL, 1227 " npi_mac_port_attr" 1228 " MAC_10G_PORT_IPG:" 1229 " Invalid Input:" 1230 " xgmii_ipg <0x%x>", 1231 ipg0)); 1232 return (NPI_FAILURE | 1233 NPI_MAC_PORT_ATTR_INVALID(portn)); 1234 } 1235 1236 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1237 val &= ~(XMAC_IPG_VALUE_MASK | 1238 XMAC_IPG_VALUE1_MASK); 1239 1240 switch (ipg0) { 1241 case XGMII_IPG_12_15: 1242 val |= (IPG_12_15_BYTE << 1243 XMAC_IPG_VALUE_SHIFT); 1244 break; 1245 case XGMII_IPG_16_19: 1246 val |= (IPG_16_19_BYTE << 1247 XMAC_IPG_VALUE_SHIFT); 1248 break; 1249 case XGMII_IPG_20_23: 1250 val |= (IPG_20_23_BYTE << 1251 XMAC_IPG_VALUE_SHIFT); 1252 break; 1253 default: 1254 return (NPI_FAILURE | 1255 NPI_MAC_PORT_ATTR_INVALID(portn)); 1256 } 1257 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1258 } else { 1259 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1260 ipg0 = (val & XMAC_IPG_VALUE_MASK) >> 1261 XMAC_IPG_VALUE_SHIFT; 1262 switch (ipg0) { 1263 case IPG_12_15_BYTE: 1264 attrp->odata[0] = XGMII_IPG_12_15; 1265 break; 1266 case IPG_16_19_BYTE: 1267 attrp->odata[0] = XGMII_IPG_16_19; 1268 break; 1269 case IPG_20_23_BYTE: 1270 attrp->odata[0] = XGMII_IPG_20_23; 1271 break; 1272 default: 1273 return (NPI_FAILURE | 1274 NPI_MAC_PORT_ATTR_INVALID(portn)); 1275 } 1276 } 1277 break; 1278 case BMAC_PORT_0: 1279 case BMAC_PORT_1: 1280 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1281 " npi_mac_port_attr" "MAC_PORT_IPG:" 1282 " Invalid Input: portn <%d>", 1283 portn)); 1284 /* FALLTHROUGH */ 1285 default: 1286 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1287 } 1288 break; 1289 } 1290 1291 case XMAC_PORT_IPG: 1292 { 1293 uint32_t ipg1; 1294 switch (portn) { 1295 case XMAC_PORT_0: 1296 case XMAC_PORT_1: 1297 if (op == OP_SET) { 1298 ipg1 = attrp->idata[0]; 1299 ASSERT((ipg1 == MII_GMII_IPG_12) || \ 1300 (ipg1 == MII_GMII_IPG_13) || \ 1301 (ipg1 == MII_GMII_IPG_14) || \ 1302 (ipg1 == MII_GMII_IPG_15) || \ 1303 (ipg1 == MII_GMII_IPG_16)); 1304 if ((ipg1 != MII_GMII_IPG_12) && 1305 (ipg1 != MII_GMII_IPG_13) && 1306 (ipg1 != MII_GMII_IPG_14) && 1307 (ipg1 != MII_GMII_IPG_15) && 1308 (ipg1 != MII_GMII_IPG_16)) { 1309 NPI_ERROR_MSG((handle.function, 1310 NPI_ERR_CTL, 1311 " npi_mac_port_attr" 1312 " XMAC_PORT_IPG:" 1313 " Invalid Input:" 1314 " mii_gmii_ipg <0x%x>", 1315 ipg1)); 1316 return (NPI_FAILURE | 1317 NPI_MAC_PORT_ATTR_INVALID(portn)); 1318 } 1319 1320 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1321 val &= ~(XMAC_IPG_VALUE_MASK | 1322 XMAC_IPG_VALUE1_MASK); 1323 1324 switch (ipg1) { 1325 case MII_GMII_IPG_12: 1326 val |= (IPG1_12_BYTES << 1327 XMAC_IPG_VALUE1_SHIFT); 1328 break; 1329 case MII_GMII_IPG_13: 1330 val |= (IPG1_13_BYTES << 1331 XMAC_IPG_VALUE1_SHIFT); 1332 break; 1333 case MII_GMII_IPG_14: 1334 val |= (IPG1_14_BYTES << 1335 XMAC_IPG_VALUE1_SHIFT); 1336 break; 1337 case MII_GMII_IPG_15: 1338 val |= (IPG1_15_BYTES << 1339 XMAC_IPG_VALUE1_SHIFT); 1340 break; 1341 case MII_GMII_IPG_16: 1342 val |= (IPG1_16_BYTES << 1343 XMAC_IPG_VALUE1_SHIFT); 1344 break; 1345 default: 1346 return (NPI_FAILURE | 1347 NPI_MAC_PORT_ATTR_INVALID(portn)); 1348 } 1349 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1350 } else { 1351 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1352 ipg1 = (val & XMAC_IPG_VALUE1_MASK) >> 1353 XMAC_IPG_VALUE1_SHIFT; 1354 switch (ipg1) { 1355 case IPG1_12_BYTES: 1356 attrp->odata[1] = MII_GMII_IPG_12; 1357 break; 1358 case IPG1_13_BYTES: 1359 attrp->odata[1] = MII_GMII_IPG_13; 1360 break; 1361 case IPG1_14_BYTES: 1362 attrp->odata[1] = MII_GMII_IPG_14; 1363 break; 1364 case IPG1_15_BYTES: 1365 attrp->odata[1] = MII_GMII_IPG_15; 1366 break; 1367 case IPG1_16_BYTES: 1368 attrp->odata[1] = MII_GMII_IPG_16; 1369 break; 1370 default: 1371 return (NPI_FAILURE | 1372 NPI_MAC_PORT_ATTR_INVALID(portn)); 1373 } 1374 } 1375 break; 1376 case BMAC_PORT_0: 1377 case BMAC_PORT_1: 1378 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1379 " npi_mac_port_attr" 1380 " MAC_PORT_IPG:" 1381 " Invalid Input: portn <%d>", 1382 portn)); 1383 /* FALLTHROUGH */ 1384 default: 1385 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1386 } 1387 break; 1388 } 1389 1390 case MAC_PORT_ADDR: { 1391 uint32_t addr0; 1392 uint32_t addr1; 1393 uint32_t addr2; 1394 1395 switch (portn) { 1396 case XMAC_PORT_0: 1397 case XMAC_PORT_1: 1398 if (op == OP_SET) { 1399 addr0 = attrp->idata[0]; 1400 addr1 = attrp->idata[1]; 1401 addr2 = attrp->idata[2]; 1402 ASSERT((addr0 & ~0xFFFF) == 0); 1403 if ((addr0 & ~0xFFFF) != 0) { 1404 NPI_ERROR_MSG((handle.function, 1405 NPI_ERR_CTL, 1406 " npi_mac_port_attr" 1407 " MAC_PORT_ADDR:" 1408 " Invalid Input:" 1409 " addr0 <0x%x>", addr0)); 1410 1411 return (NPI_FAILURE | 1412 NPI_MAC_PORT_ATTR_INVALID(portn)); 1413 } 1414 ASSERT((addr1 & ~0xFFFF) == 0); 1415 if ((addr1 & ~0xFFFF) != 0) { 1416 NPI_ERROR_MSG((handle.function, 1417 NPI_ERR_CTL, 1418 " npi_mac_port_attr" 1419 " MAC_PORT_ADDR:" 1420 " Invalid Input:" 1421 " addr1 <0x%x>", addr1)); 1422 return (NPI_FAILURE | 1423 NPI_MAC_PORT_ATTR_INVALID(portn)); 1424 } 1425 ASSERT((addr2 & ~0xFFFF) == 0); 1426 if ((addr2 & ~0xFFFF) != 0) { 1427 NPI_ERROR_MSG((handle.function, 1428 NPI_ERR_CTL, 1429 " npi_mac_port_attr" 1430 " MAC_PORT_ADDR:" 1431 " Invalid Input:" 1432 " addr2 <0x%x.", 1433 addr2)); 1434 1435 return (NPI_FAILURE | 1436 NPI_MAC_PORT_ATTR_INVALID(portn)); 1437 } 1438 XMAC_REG_WR(handle, portn, XMAC_ADDR0_REG, 1439 addr0); 1440 XMAC_REG_WR(handle, portn, XMAC_ADDR1_REG, 1441 addr1); 1442 XMAC_REG_WR(handle, portn, XMAC_ADDR2_REG, 1443 addr2); 1444 } else { 1445 XMAC_REG_RD(handle, portn, XMAC_ADDR0_REG, 1446 &addr0); 1447 XMAC_REG_RD(handle, portn, XMAC_ADDR1_REG, 1448 &addr1); 1449 XMAC_REG_RD(handle, portn, XMAC_ADDR2_REG, 1450 &addr2); 1451 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1452 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1453 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1454 } 1455 break; 1456 case BMAC_PORT_0: 1457 case BMAC_PORT_1: 1458 if (op == OP_SET) { 1459 addr0 = attrp->idata[0]; 1460 addr1 = attrp->idata[1]; 1461 addr2 = attrp->idata[2]; 1462 ASSERT((addr0 & ~0xFFFF) == 0); 1463 if ((addr0 & ~0xFFFF) != 0) { 1464 NPI_ERROR_MSG((handle.function, 1465 NPI_ERR_CTL, 1466 " npi_mac_port_attr" 1467 " MAC_PORT_ADDR:" 1468 " Invalid Input:" 1469 " addr0 <0x%x>", 1470 addr0)); 1471 return (NPI_FAILURE | 1472 NPI_MAC_PORT_ATTR_INVALID(portn)); 1473 } 1474 ASSERT((addr1 & ~0xFFFF) == 0); 1475 if ((addr1 & ~0xFFFF) != 0) { 1476 NPI_ERROR_MSG((handle.function, 1477 NPI_ERR_CTL, 1478 " npi_mac_port_attr" 1479 " MAC_PORT_ADDR:" 1480 " Invalid Input:" 1481 " addr1 <0x%x>", 1482 addr1)); 1483 return (NPI_FAILURE | 1484 NPI_MAC_PORT_ATTR_INVALID(portn)); 1485 } 1486 ASSERT((addr2 & ~0xFFFF) == 0); 1487 if ((addr2 & ~0xFFFF) != 0) { 1488 NPI_ERROR_MSG((handle.function, 1489 NPI_ERR_CTL, 1490 " npi_mac_port_attr" 1491 " MAC_PORT_ADDR:" 1492 " Invalid Input:" 1493 " addr2 <0x%x>", 1494 addr2)); 1495 return (NPI_FAILURE | 1496 NPI_MAC_PORT_ATTR_INVALID(portn)); 1497 } 1498 BMAC_REG_WR(handle, portn, BMAC_ADDR0_REG, 1499 addr0); 1500 BMAC_REG_WR(handle, portn, BMAC_ADDR1_REG, 1501 addr1); 1502 BMAC_REG_WR(handle, portn, BMAC_ADDR2_REG, 1503 addr2); 1504 } else { 1505 BMAC_REG_RD(handle, portn, BMAC_ADDR0_REG, 1506 &addr0); 1507 BMAC_REG_RD(handle, portn, BMAC_ADDR1_REG, 1508 &addr1); 1509 BMAC_REG_RD(handle, portn, BMAC_ADDR2_REG, 1510 &addr2); 1511 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1512 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1513 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1514 } 1515 break; 1516 default: 1517 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1518 } 1519 break; 1520 } 1521 1522 case MAC_PORT_ADDR_FILTER: { 1523 uint32_t addr0; 1524 uint32_t addr1; 1525 uint32_t addr2; 1526 1527 switch (portn) { 1528 case XMAC_PORT_0: 1529 case XMAC_PORT_1: 1530 if (op == OP_SET) { 1531 addr0 = attrp->idata[0]; 1532 addr1 = attrp->idata[1]; 1533 addr2 = attrp->idata[2]; 1534 ASSERT((addr0 & ~0xFFFF) == 0); 1535 if ((addr0 & ~0xFFFF) != 0) { 1536 NPI_ERROR_MSG((handle.function, 1537 NPI_ERR_CTL, 1538 " npi_mac_port_attr" 1539 " MAC_PORT_ADDR_FILTER:" 1540 " Invalid Input:" 1541 " addr0 <0x%x>", 1542 addr0)); 1543 return (NPI_FAILURE | 1544 NPI_MAC_PORT_ATTR_INVALID(portn)); 1545 } 1546 ASSERT((addr1 & ~0xFFFF) == 0); 1547 if ((addr1 & ~0xFFFF) != 0) { 1548 NPI_ERROR_MSG((handle.function, 1549 NPI_ERR_CTL, 1550 " npi_mac_port_attr" 1551 " MAC_PORT_ADDR_FILTER:" 1552 " Invalid Input:" 1553 " addr1 <0x%x>", 1554 addr1)); 1555 return (NPI_FAILURE | 1556 NPI_MAC_PORT_ATTR_INVALID(portn)); 1557 } 1558 ASSERT((addr2 & ~0xFFFF) == 0); 1559 if ((addr2 & ~0xFFFF) != 0) { 1560 NPI_ERROR_MSG((handle.function, 1561 NPI_ERR_CTL, 1562 " npi_mac_port_attr" 1563 " MAC_PORT_ADDR_FILTER:" 1564 " Invalid Input:" 1565 " addr2 <0x%x>", 1566 addr2)); 1567 return (NPI_FAILURE | 1568 NPI_MAC_PORT_ATTR_INVALID(portn)); 1569 } 1570 XMAC_REG_WR(handle, portn, 1571 XMAC_ADDR_FILT0_REG, addr0); 1572 XMAC_REG_WR(handle, portn, 1573 XMAC_ADDR_FILT1_REG, addr1); 1574 XMAC_REG_WR(handle, portn, 1575 XMAC_ADDR_FILT2_REG, addr2); 1576 } else { 1577 XMAC_REG_RD(handle, portn, 1578 XMAC_ADDR_FILT0_REG, &addr0); 1579 XMAC_REG_RD(handle, portn, 1580 XMAC_ADDR_FILT1_REG, &addr1); 1581 XMAC_REG_RD(handle, portn, 1582 XMAC_ADDR_FILT2_REG, &addr2); 1583 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1584 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1585 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1586 } 1587 break; 1588 case BMAC_PORT_0: 1589 case BMAC_PORT_1: 1590 if (op == OP_SET) { 1591 addr0 = attrp->idata[0]; 1592 addr1 = attrp->idata[1]; 1593 addr2 = attrp->idata[2]; 1594 ASSERT((addr0 & ~0xFFFF) == 0); 1595 if ((addr0 & ~0xFFFF) != 0) { 1596 NPI_ERROR_MSG((handle.function, 1597 NPI_ERR_CTL, 1598 " npi_mac_port_attr" 1599 " MAC_PORT_ADDR_FILTER:" 1600 " addr0", 1601 addr0)); 1602 return (NPI_FAILURE | 1603 NPI_MAC_PORT_ATTR_INVALID(portn)); 1604 } 1605 ASSERT((addr1 & ~0xFFFF) == 0); 1606 if ((addr1 & ~0xFFFF) != 0) { 1607 NPI_ERROR_MSG((handle.function, 1608 NPI_ERR_CTL, 1609 " npi_mac_port_attr" 1610 " MAC_PORT_ADDR_FILTER:" 1611 " Invalid Input:" 1612 " addr1 <0x%x>", 1613 addr1)); 1614 return (NPI_FAILURE | 1615 NPI_MAC_PORT_ATTR_INVALID(portn)); 1616 } 1617 ASSERT((addr2 & ~0xFFFF) == 0); 1618 if ((addr2 & ~0xFFFF) != 0) { 1619 NPI_ERROR_MSG((handle.function, 1620 NPI_ERR_CTL, 1621 " npi_mac_port_attr" 1622 " MAC_PORT_ADDR_FILTER:" 1623 " Invalid Input:" 1624 " addr2 <0x%x>", 1625 addr2)); 1626 return (NPI_FAILURE | 1627 NPI_MAC_PORT_ATTR_INVALID(portn)); 1628 } 1629 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT0_REG, 1630 addr0); 1631 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT1_REG, 1632 addr1); 1633 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT2_REG, 1634 addr2); 1635 } else { 1636 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT0_REG, 1637 &addr0); 1638 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT1_REG, 1639 &addr1); 1640 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT2_REG, 1641 &addr2); 1642 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1643 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1644 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1645 } 1646 break; 1647 default: 1648 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1649 } 1650 break; 1651 } 1652 1653 case MAC_PORT_ADDR_FILTER_MASK: { 1654 uint32_t mask_1_2; 1655 uint32_t mask_0; 1656 1657 switch (portn) { 1658 case XMAC_PORT_0: 1659 case XMAC_PORT_1: 1660 if (op == OP_SET) { 1661 mask_0 = attrp->idata[0]; 1662 mask_1_2 = attrp->idata[1]; 1663 ASSERT((mask_0 & ~0xFFFF) == 0); 1664 if ((mask_0 & ~0xFFFF) != 0) { 1665 NPI_ERROR_MSG((handle.function, 1666 NPI_ERR_CTL, 1667 " npi_mac_port_attr" 1668 " MAC_ADDR_FILTER_MASK:" 1669 " Invalid Input:" 1670 " mask_0 <0x%x>", 1671 mask_0)); 1672 return (NPI_FAILURE | 1673 NPI_MAC_PORT_ATTR_INVALID(portn)); 1674 } 1675 ASSERT((mask_1_2 & ~0xFF) == 0); 1676 if ((mask_1_2 & ~0xFF) != 0) { 1677 NPI_ERROR_MSG((handle.function, 1678 NPI_ERR_CTL, 1679 " npi_mac_port_attr" 1680 " MAC_ADDR_FILTER_MASK:" 1681 " Invalid Input:" 1682 " mask_1_2 <0x%x>", 1683 mask_1_2)); 1684 return (NPI_FAILURE | 1685 NPI_MAC_PORT_ATTR_INVALID(portn)); 1686 } 1687 XMAC_REG_WR(handle, portn, 1688 XMAC_ADDR_FILT0_MASK_REG, mask_0); 1689 XMAC_REG_WR(handle, portn, 1690 XMAC_ADDR_FILT12_MASK_REG, mask_1_2); 1691 } else { 1692 XMAC_REG_RD(handle, portn, 1693 XMAC_ADDR_FILT0_MASK_REG, &mask_0); 1694 XMAC_REG_RD(handle, portn, 1695 XMAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1696 attrp->odata[0] = mask_0 & 0xFFFF; 1697 attrp->odata[1] = mask_1_2 & 0xFF; 1698 } 1699 break; 1700 case BMAC_PORT_0: 1701 case BMAC_PORT_1: 1702 if (op == OP_SET) { 1703 mask_0 = attrp->idata[0]; 1704 mask_1_2 = attrp->idata[1]; 1705 BMAC_REG_WR(handle, portn, 1706 MAC_ADDR_FILT00_MASK_REG, mask_0); 1707 BMAC_REG_WR(handle, portn, 1708 MAC_ADDR_FILT12_MASK_REG, mask_1_2); 1709 } else { 1710 BMAC_REG_RD(handle, portn, 1711 MAC_ADDR_FILT00_MASK_REG, &mask_0); 1712 BMAC_REG_RD(handle, portn, 1713 MAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1714 attrp->odata[0] = mask_0; 1715 attrp->odata[1] = mask_1_2; 1716 } 1717 break; 1718 default: 1719 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1720 } 1721 break; 1722 } 1723 1724 default: 1725 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1726 " npi_mac_port_attr" 1727 " Invalid Input:" 1728 " attr <0x%x>", attrp->type)); 1729 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1730 } 1731 1732 return (NPI_SUCCESS); 1733 } 1734 1735 npi_status_t 1736 npi_xmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 1737 { 1738 uint64_t val; 1739 boolean_t txmac = B_FALSE; 1740 1741 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1742 1743 switch (mode) { 1744 case XTX_MAC_REG_RESET: 1745 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_REG_RST); 1746 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1747 txmac = B_TRUE; 1748 break; 1749 case XRX_MAC_REG_RESET: 1750 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_REG_RST); 1751 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1752 break; 1753 case XTX_MAC_LOGIC_RESET: 1754 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_SOFT_RST); 1755 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1756 txmac = B_TRUE; 1757 break; 1758 case XRX_MAC_LOGIC_RESET: 1759 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_SOFT_RST); 1760 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1761 break; 1762 case XTX_MAC_RESET_ALL: 1763 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, 1764 XTXMAC_SOFT_RST | XTXMAC_REG_RST); 1765 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1766 txmac = B_TRUE; 1767 break; 1768 case XRX_MAC_RESET_ALL: 1769 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, 1770 XRXMAC_SOFT_RST | XRXMAC_REG_RST); 1771 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1772 break; 1773 default: 1774 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1775 " npi_mac_reset" 1776 " Invalid Input: mode <0x%x>", 1777 mode)); 1778 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 1779 } 1780 1781 if (val != 0) { 1782 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1783 " npi_xmac_reset" 1784 " HW ERROR: MAC_RESET failed <0x%x>", 1785 val)); 1786 1787 if (txmac) 1788 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 1789 else 1790 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 1791 } 1792 1793 return (NPI_SUCCESS); 1794 } 1795 1796 npi_status_t 1797 npi_xmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1798 xmac_xif_config_t config) 1799 { 1800 uint64_t val = 0; 1801 1802 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1803 1804 switch (op) { 1805 case ENABLE: 1806 case DISABLE: 1807 ASSERT((config != 0) && ((config & ~CFG_XMAC_XIF_ALL) == 0)); 1808 if ((config == 0) || (config & ~CFG_XMAC_XIF_ALL) != 0) { 1809 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1810 " npi_xmac_xif_config" 1811 " Invalid Input:" 1812 " config <0x%x>", config)); 1813 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1814 } 1815 if (op == ENABLE) { 1816 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1817 if (config & CFG_XMAC_XIF_LED_FORCE) 1818 val |= XMAC_XIF_FORCE_LED_ON; 1819 if (config & CFG_XMAC_XIF_LED_POLARITY) 1820 val |= XMAC_XIF_LED_POLARITY; 1821 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1822 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1823 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1824 val |= XMAC_XIF_TX_OUTPUT_EN; 1825 1826 if (config & CFG_XMAC_XIF_LOOPBACK) { 1827 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1828 val |= XMAC_XIF_LOOPBACK; 1829 } 1830 1831 if (config & CFG_XMAC_XIF_LFS) 1832 val &= ~XMAC_XIF_LFS_DISABLE; 1833 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1834 val |= XMAC_XIF_XPCS_BYPASS; 1835 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1836 val |= XMAC_XIF_1G_PCS_BYPASS; 1837 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1838 val |= XMAC_XIF_SEL_CLK_25MHZ; 1839 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1840 1841 } else { 1842 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1843 if (config & CFG_XMAC_XIF_LED_FORCE) 1844 val &= ~XMAC_XIF_FORCE_LED_ON; 1845 if (config & CFG_XMAC_XIF_LED_POLARITY) 1846 val &= ~XMAC_XIF_LED_POLARITY; 1847 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1848 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1849 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1850 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1851 if (config & CFG_XMAC_XIF_LOOPBACK) 1852 val &= ~XMAC_XIF_LOOPBACK; 1853 if (config & CFG_XMAC_XIF_LFS) 1854 val |= XMAC_XIF_LFS_DISABLE; 1855 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1856 val &= ~XMAC_XIF_XPCS_BYPASS; 1857 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1858 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1859 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1860 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1861 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1862 } 1863 break; 1864 case INIT: 1865 ASSERT((config & ~CFG_XMAC_XIF_ALL) == 0); 1866 if ((config & ~CFG_XMAC_XIF_ALL) != 0) { 1867 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1868 " npi_xmac_xif_config" 1869 " Invalid Input: config <0x%x>", 1870 config)); 1871 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1872 } 1873 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1874 1875 if (config & CFG_XMAC_XIF_LED_FORCE) 1876 val |= XMAC_XIF_FORCE_LED_ON; 1877 else 1878 val &= ~XMAC_XIF_FORCE_LED_ON; 1879 if (config & CFG_XMAC_XIF_LED_POLARITY) 1880 val |= XMAC_XIF_LED_POLARITY; 1881 else 1882 val &= ~XMAC_XIF_LED_POLARITY; 1883 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1884 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1885 else 1886 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1887 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1888 val |= XMAC_XIF_TX_OUTPUT_EN; 1889 else 1890 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1891 1892 if (config & CFG_XMAC_XIF_LOOPBACK) { 1893 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1894 val |= XMAC_XIF_LOOPBACK; 1895 #ifdef AXIS_DEBUG_LB 1896 val |= XMAC_RX_MAC2IPP_PKT_CNT_EN; 1897 #endif 1898 } else { 1899 val &= ~XMAC_XIF_LOOPBACK; 1900 } 1901 1902 if (config & CFG_XMAC_XIF_LFS) 1903 val &= ~XMAC_XIF_LFS_DISABLE; 1904 else 1905 val |= XMAC_XIF_LFS_DISABLE; 1906 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1907 val |= XMAC_XIF_XPCS_BYPASS; 1908 else 1909 val &= ~XMAC_XIF_XPCS_BYPASS; 1910 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1911 val |= XMAC_XIF_1G_PCS_BYPASS; 1912 else 1913 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1914 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1915 val |= XMAC_XIF_SEL_CLK_25MHZ; 1916 else 1917 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1918 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1919 1920 break; 1921 default: 1922 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1923 " npi_xmac_xif_config" 1924 " Invalid Input: op <0x%x>", op)); 1925 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1926 } 1927 1928 return (NPI_SUCCESS); 1929 } 1930 1931 npi_status_t 1932 npi_xmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1933 xmac_tx_config_t config) 1934 { 1935 uint64_t val = 0; 1936 1937 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1938 1939 switch (op) { 1940 case ENABLE: 1941 case DISABLE: 1942 ASSERT((config != 0) && ((config & ~CFG_XMAC_TX_ALL) == 0)); 1943 if ((config == 0) || (config & ~CFG_XMAC_TX_ALL) != 0) { 1944 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1945 " npi_xmac_tx_config" 1946 " Invalid Input: config <0x%x>", 1947 config)); 1948 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1949 } 1950 if (op == ENABLE) { 1951 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1952 if (config & CFG_XMAC_TX) 1953 val |= XMAC_TX_CFG_TX_ENABLE; 1954 if (config & CFG_XMAC_TX_STRETCH_MODE) 1955 val |= XMAC_TX_CFG_STRETCH_MD; 1956 if (config & CFG_XMAC_VAR_IPG) 1957 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1958 if (config & CFG_XMAC_TX_CRC) 1959 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 1960 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1961 } else { 1962 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1963 if (config & CFG_XMAC_TX) 1964 val &= ~XMAC_TX_CFG_TX_ENABLE; 1965 if (config & CFG_XMAC_TX_STRETCH_MODE) 1966 val &= ~XMAC_TX_CFG_STRETCH_MD; 1967 if (config & CFG_XMAC_VAR_IPG) 1968 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1969 if (config & CFG_XMAC_TX_CRC) 1970 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 1971 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1972 } 1973 break; 1974 case INIT: 1975 ASSERT((config & ~CFG_XMAC_TX_ALL) == 0); 1976 if ((config & ~CFG_XMAC_TX_ALL) != 0) { 1977 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1978 " npi_xmac_tx_config" 1979 " Invalid Input: config <0x%x>", 1980 config)); 1981 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1982 } 1983 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1984 if (config & CFG_XMAC_TX) 1985 val |= XMAC_TX_CFG_TX_ENABLE; 1986 else 1987 val &= ~XMAC_TX_CFG_TX_ENABLE; 1988 if (config & CFG_XMAC_TX_STRETCH_MODE) 1989 val |= XMAC_TX_CFG_STRETCH_MD; 1990 else 1991 val &= ~XMAC_TX_CFG_STRETCH_MD; 1992 if (config & CFG_XMAC_VAR_IPG) 1993 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1994 else 1995 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1996 if (config & CFG_XMAC_TX_CRC) 1997 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 1998 else 1999 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 2000 2001 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2002 break; 2003 default: 2004 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2005 " npi_xmac_tx_config" 2006 " Invalid Input: op <0x%x>", 2007 op)); 2008 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2009 } 2010 2011 return (NPI_SUCCESS); 2012 } 2013 2014 npi_status_t 2015 npi_xmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2016 xmac_rx_config_t config) 2017 { 2018 uint64_t val = 0; 2019 2020 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2021 2022 switch (op) { 2023 case ENABLE: 2024 case DISABLE: 2025 ASSERT((config != 0) && ((config & ~CFG_XMAC_RX_ALL) == 0)); 2026 if ((config == 0) || (config & ~CFG_XMAC_RX_ALL) != 0) { 2027 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2028 " npi_xmac_rx_config" 2029 " Invalid Input: config <0x%x>", 2030 config)); 2031 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2032 } 2033 if (op == ENABLE) { 2034 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2035 if (config & CFG_XMAC_RX) 2036 val |= XMAC_RX_CFG_RX_ENABLE; 2037 if (config & CFG_XMAC_RX_PROMISCUOUS) 2038 val |= XMAC_RX_CFG_PROMISC; 2039 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2040 val |= XMAC_RX_CFG_PROMISC_GROUP; 2041 if (config & CFG_XMAC_RX_ERRCHK) 2042 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2043 if (config & CFG_XMAC_RX_CRC_CHK) 2044 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2045 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2046 val |= XMAC_RX_CFG_RESERVED_MCAST; 2047 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2048 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2049 if (config & CFG_XMAC_RX_HASH_FILTER) 2050 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2051 if (config & CFG_XMAC_RX_ADDR_FILTER) 2052 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2053 if (config & CFG_XMAC_RX_STRIP_CRC) 2054 val |= XMAC_RX_CFG_STRIP_CRC; 2055 if (config & CFG_XMAC_RX_PAUSE) 2056 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2057 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2058 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2059 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2060 } else { 2061 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2062 if (config & CFG_XMAC_RX) 2063 val &= ~XMAC_RX_CFG_RX_ENABLE; 2064 if (config & CFG_XMAC_RX_PROMISCUOUS) 2065 val &= ~XMAC_RX_CFG_PROMISC; 2066 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2067 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2068 if (config & CFG_XMAC_RX_ERRCHK) 2069 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2070 if (config & CFG_XMAC_RX_CRC_CHK) 2071 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2072 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2073 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2074 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2075 val |= XMAC_RX_CFG_CD_VIO_CHK; 2076 if (config & CFG_XMAC_RX_HASH_FILTER) 2077 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2078 if (config & CFG_XMAC_RX_ADDR_FILTER) 2079 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2080 if (config & CFG_XMAC_RX_STRIP_CRC) 2081 val &= ~XMAC_RX_CFG_STRIP_CRC; 2082 if (config & CFG_XMAC_RX_PAUSE) 2083 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2084 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2085 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2086 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2087 } 2088 break; 2089 case INIT: 2090 ASSERT((config & ~CFG_XMAC_RX_ALL) == 0); 2091 if ((config & ~CFG_XMAC_RX_ALL) != 0) { 2092 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2093 " npi_xmac_rx_config" 2094 " Invalid Input: config <0x%x>", 2095 config)); 2096 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2097 } 2098 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2099 if (config & CFG_XMAC_RX) 2100 val |= XMAC_RX_CFG_RX_ENABLE; 2101 else 2102 val &= ~XMAC_RX_CFG_RX_ENABLE; 2103 if (config & CFG_XMAC_RX_PROMISCUOUS) 2104 val |= XMAC_RX_CFG_PROMISC; 2105 else 2106 val &= ~XMAC_RX_CFG_PROMISC; 2107 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2108 val |= XMAC_RX_CFG_PROMISC_GROUP; 2109 else 2110 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2111 if (config & CFG_XMAC_RX_ERRCHK) 2112 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2113 else 2114 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2115 if (config & CFG_XMAC_RX_CRC_CHK) 2116 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2117 else 2118 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2119 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2120 val |= XMAC_RX_CFG_RESERVED_MCAST; 2121 else 2122 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2123 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2124 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2125 else 2126 val |= XMAC_RX_CFG_CD_VIO_CHK; 2127 if (config & CFG_XMAC_RX_HASH_FILTER) 2128 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2129 else 2130 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2131 if (config & CFG_XMAC_RX_ADDR_FILTER) 2132 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2133 else 2134 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2135 if (config & CFG_XMAC_RX_PAUSE) 2136 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2137 else 2138 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2139 if (config & CFG_XMAC_RX_STRIP_CRC) 2140 val |= XMAC_RX_CFG_STRIP_CRC; 2141 else 2142 val &= ~XMAC_RX_CFG_STRIP_CRC; 2143 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2144 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2145 else 2146 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2147 2148 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2149 break; 2150 default: 2151 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2152 " npi_xmac_rx_config" 2153 " Invalid Input: op <0x%x>", op)); 2154 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2155 } 2156 2157 return (NPI_SUCCESS); 2158 } 2159 2160 npi_status_t 2161 npi_xmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2162 xmac_tx_iconfig_t iconfig) 2163 { 2164 uint64_t val = 0; 2165 2166 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2167 2168 switch (op) { 2169 case ENABLE: 2170 case DISABLE: 2171 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2172 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2173 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2174 " npi_xmac_tx_iconfig" 2175 " Invalid Input: iconfig <0x%x>", 2176 iconfig)); 2177 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2178 } 2179 XMAC_REG_RD(handle, portn, XTXMAC_STAT_MSK_REG, &val); 2180 if (op == ENABLE) 2181 val &= ~iconfig; 2182 else 2183 val |= iconfig; 2184 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, val); 2185 2186 break; 2187 case INIT: 2188 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2189 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2190 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2191 " npi_xmac_tx_iconfig" 2192 " Invalid Input: iconfig <0x%x>", 2193 iconfig)); 2194 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2195 } 2196 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, ~iconfig); 2197 2198 break; 2199 default: 2200 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2201 " npi_xmac_tx_iconfig" 2202 " Invalid Input: iconfig <0x%x>", 2203 iconfig)); 2204 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2205 } 2206 2207 return (NPI_SUCCESS); 2208 } 2209 2210 npi_status_t 2211 npi_xmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2212 xmac_rx_iconfig_t iconfig) 2213 { 2214 uint64_t val = 0; 2215 2216 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2217 2218 switch (op) { 2219 case ENABLE: 2220 case DISABLE: 2221 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_RX_ALL) == 0)); 2222 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2223 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2224 " npi_xmac_rx_iconfig" 2225 " Invalid Input: iconfig <0x%x>", 2226 iconfig)); 2227 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2228 } 2229 XMAC_REG_RD(handle, portn, XRXMAC_STAT_MSK_REG, &val); 2230 if (op == ENABLE) 2231 val &= ~iconfig; 2232 else 2233 val |= iconfig; 2234 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, val); 2235 2236 break; 2237 case INIT: 2238 ASSERT((iconfig & ~ICFG_XMAC_RX_ALL) == 0); 2239 if ((iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2240 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2241 " npi_xmac_rx_iconfig" 2242 " Invalid Input: iconfig <0x%x>", 2243 iconfig)); 2244 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2245 } 2246 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, ~iconfig); 2247 2248 break; 2249 default: 2250 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2251 " npi_xmac_rx_iconfig" 2252 " Invalid Input: iconfig <0x%x>", 2253 iconfig)); 2254 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2255 } 2256 2257 return (NPI_SUCCESS); 2258 } 2259 2260 npi_status_t 2261 npi_xmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2262 xmac_ctl_iconfig_t iconfig) 2263 { 2264 uint64_t val = 0; 2265 2266 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2267 2268 switch (op) { 2269 case ENABLE: 2270 case DISABLE: 2271 ASSERT((iconfig != 0) && \ 2272 ((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0)); 2273 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2274 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2275 " npi_xmac_ctl_iconfig" 2276 " Invalid Input: iconfig <0x%x>", 2277 iconfig)); 2278 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2279 } 2280 XMAC_REG_RD(handle, portn, XMAC_C_S_MSK_REG, &val); 2281 if (op == ENABLE) 2282 val &= ~iconfig; 2283 else 2284 val |= iconfig; 2285 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, val); 2286 2287 break; 2288 case INIT: 2289 ASSERT((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0); 2290 if ((iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2291 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2292 " npi_xmac_ctl_iconfig" 2293 " Invalid Input: iconfig <0x%x>", 2294 iconfig)); 2295 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2296 } 2297 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, ~iconfig); 2298 2299 break; 2300 default: 2301 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2302 " npi_xmac_ctl_iconfig" 2303 " Invalid Input: iconfig <0x%x>", 2304 iconfig)); 2305 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2306 } 2307 2308 return (NPI_SUCCESS); 2309 } 2310 2311 npi_status_t 2312 npi_xmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 2313 xmac_tx_iconfig_t *istatus) 2314 { 2315 uint64_t val; 2316 2317 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2318 2319 XMAC_REG_RD(handle, portn, XTXMAC_STATUS_REG, &val); 2320 *istatus = (uint32_t)val; 2321 2322 return (NPI_SUCCESS); 2323 } 2324 2325 npi_status_t 2326 npi_xmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 2327 xmac_rx_iconfig_t *istatus) 2328 { 2329 uint64_t val; 2330 2331 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2332 2333 XMAC_REG_RD(handle, portn, XRXMAC_STATUS_REG, &val); 2334 *istatus = (uint32_t)val; 2335 2336 return (NPI_SUCCESS); 2337 } 2338 2339 npi_status_t 2340 npi_xmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 2341 xmac_ctl_iconfig_t *istatus) 2342 { 2343 uint64_t val; 2344 2345 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2346 2347 XMAC_REG_RD(handle, portn, XMAC_CTRL_STAT_REG, &val); 2348 *istatus = (uint32_t)val; 2349 2350 return (NPI_SUCCESS); 2351 } 2352 2353 npi_status_t 2354 npi_xmac_xpcs_reset(npi_handle_t handle, uint8_t portn) 2355 { 2356 uint64_t val; 2357 int delay = 100; 2358 2359 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2360 2361 XPCS_REG_RD(handle, portn, XPCS_CTRL_1_REG, &val); 2362 val |= XPCS_CTRL1_RST; 2363 XPCS_REG_WR(handle, portn, XPCS_CTRL_1_REG, val); 2364 2365 while ((--delay) && (val & XPCS_CTRL1_RST)) { 2366 NXGE_DELAY(10); 2367 XPCS_REG_RD(handle, portn, XPCS_CTRL_1_REG, &val); 2368 } 2369 2370 if (delay == 0) { 2371 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2372 " npi_xmac_xpcs_reset portn <%d> failed", portn)); 2373 return (NPI_FAILURE); 2374 } 2375 2376 return (NPI_SUCCESS); 2377 } 2378 2379 npi_status_t 2380 npi_xmac_xpcs_enable(npi_handle_t handle, uint8_t portn) 2381 { 2382 uint64_t val; 2383 2384 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2385 2386 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2387 val |= XPCS_CFG_XPCS_ENABLE; 2388 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2389 2390 return (NPI_SUCCESS); 2391 } 2392 2393 npi_status_t 2394 npi_xmac_xpcs_disable(npi_handle_t handle, uint8_t portn) 2395 { 2396 uint64_t val; 2397 2398 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2399 2400 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2401 val &= ~XPCS_CFG_XPCS_ENABLE; 2402 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2403 2404 return (NPI_SUCCESS); 2405 } 2406 2407 npi_status_t 2408 npi_xmac_xpcs_read(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2409 uint32_t *value) 2410 { 2411 uint32_t reg; 2412 uint64_t val; 2413 2414 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2415 2416 switch (xpcs_reg) { 2417 case XPCS_REG_CONTROL1: 2418 reg = XPCS_CTRL_1_REG; 2419 break; 2420 case XPCS_REG_STATUS1: 2421 reg = XPCS_STATUS_1_REG; 2422 break; 2423 case XPCS_REG_DEVICE_ID: 2424 reg = XPCS_DEV_ID_REG; 2425 break; 2426 case XPCS_REG_SPEED_ABILITY: 2427 reg = XPCS_SPEED_ABILITY_REG; 2428 break; 2429 case XPCS_REG_DEVICE_IN_PKG: 2430 reg = XPCS_DEV_IN_PKG_REG; 2431 break; 2432 case XPCS_REG_CONTROL2: 2433 reg = XPCS_CTRL_2_REG; 2434 break; 2435 case XPCS_REG_STATUS2: 2436 reg = XPCS_STATUS_2_REG; 2437 break; 2438 case XPCS_REG_PKG_ID: 2439 reg = XPCS_PKG_ID_REG; 2440 break; 2441 case XPCS_REG_STATUS: 2442 reg = XPCS_STATUS_REG; 2443 break; 2444 case XPCS_REG_TEST_CONTROL: 2445 reg = XPCS_TEST_CTRL_REG; 2446 break; 2447 case XPCS_REG_CONFIG_VENDOR1: 2448 reg = XPCS_CFG_VENDOR_1_REG; 2449 break; 2450 case XPCS_REG_DIAG_VENDOR2: 2451 reg = XPCS_DIAG_VENDOR_2_REG; 2452 break; 2453 case XPCS_REG_MASK1: 2454 reg = XPCS_MASK_1_REG; 2455 break; 2456 case XPCS_REG_PACKET_COUNTER: 2457 reg = XPCS_PKT_CNTR_REG; 2458 break; 2459 case XPCS_REG_TX_STATEMACHINE: 2460 reg = XPCS_TX_STATE_MC_REG; 2461 break; 2462 case XPCS_REG_DESCWERR_COUNTER: 2463 reg = XPCS_DESKEW_ERR_CNTR_REG; 2464 break; 2465 case XPCS_REG_SYMBOL_ERR_L0_1_COUNTER: 2466 reg = XPCS_SYM_ERR_CNTR_L0_L1_REG; 2467 break; 2468 case XPCS_REG_SYMBOL_ERR_L2_3_COUNTER: 2469 reg = XPCS_SYM_ERR_CNTR_L2_L3_REG; 2470 break; 2471 case XPCS_REG_TRAINING_VECTOR: 2472 reg = XPCS_TRAINING_VECTOR_REG; 2473 break; 2474 default: 2475 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2476 " npi_xmac_xpcs_read" 2477 " Invalid Input: xpcs_reg <0x%x>", 2478 xpcs_reg)); 2479 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 2480 } 2481 XPCS_REG_RD(handle, portn, reg, &val); 2482 *value = val & 0xFFFFFFFF; 2483 2484 return (NPI_SUCCESS); 2485 } 2486 2487 npi_status_t 2488 npi_xmac_xpcs_write(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2489 uint32_t value) 2490 { 2491 uint32_t reg; 2492 uint64_t val; 2493 2494 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2495 2496 switch (xpcs_reg) { 2497 case XPCS_REG_CONTROL1: 2498 reg = XPCS_CTRL_1_REG; 2499 break; 2500 case XPCS_REG_TEST_CONTROL: 2501 reg = XPCS_TEST_CTRL_REG; 2502 break; 2503 case XPCS_REG_CONFIG_VENDOR1: 2504 reg = XPCS_CFG_VENDOR_1_REG; 2505 break; 2506 case XPCS_REG_DIAG_VENDOR2: 2507 reg = XPCS_DIAG_VENDOR_2_REG; 2508 break; 2509 case XPCS_REG_MASK1: 2510 reg = XPCS_MASK_1_REG; 2511 break; 2512 case XPCS_REG_PACKET_COUNTER: 2513 reg = XPCS_PKT_CNTR_REG; 2514 break; 2515 case XPCS_REG_DESCWERR_COUNTER: 2516 reg = XPCS_DESKEW_ERR_CNTR_REG; 2517 break; 2518 case XPCS_REG_TRAINING_VECTOR: 2519 reg = XPCS_TRAINING_VECTOR_REG; 2520 break; 2521 default: 2522 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2523 " npi_xmac_xpcs_write" 2524 " Invalid Input: xpcs_reg <0x%x>", 2525 xpcs_reg)); 2526 return (NPI_FAILURE | NPI_MAC_PCS_REG_INVALID(portn)); 2527 } 2528 val = value; 2529 2530 XPCS_REG_WR(handle, portn, reg, val); 2531 2532 return (NPI_SUCCESS); 2533 } 2534 2535 npi_status_t 2536 npi_bmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 2537 { 2538 uint64_t val = 0; 2539 boolean_t txmac = B_FALSE; 2540 2541 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2542 2543 switch (mode) { 2544 case TX_MAC_RESET: 2545 BMAC_REG_WR(handle, portn, BTXMAC_SW_RST_REG, 0x1); 2546 BMAC_WAIT_REG(handle, portn, BTXMAC_SW_RST_REG, val); 2547 txmac = B_TRUE; 2548 break; 2549 case RX_MAC_RESET: 2550 BMAC_REG_WR(handle, portn, BRXMAC_SW_RST_REG, 0x1); 2551 BMAC_WAIT_REG(handle, portn, BRXMAC_SW_RST_REG, val); 2552 break; 2553 default: 2554 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2555 " npi_bmac_reset" 2556 " Invalid Input: mode <0x%x>", 2557 mode)); 2558 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 2559 } 2560 2561 if (val != 0) { 2562 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2563 " npi_bmac_reset" 2564 " BMAC_RESET HW Error: ret <0x%x>", 2565 val)); 2566 if (txmac) 2567 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 2568 else 2569 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 2570 } 2571 2572 return (NPI_SUCCESS); 2573 } 2574 2575 npi_status_t 2576 npi_mac_pcs_reset(npi_handle_t handle, uint8_t portn) 2577 { 2578 /* what to do here ? */ 2579 uint64_t val = 0; 2580 int delay = 100; 2581 2582 ASSERT(IS_PORT_NUM_VALID(portn)); 2583 2584 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 2585 val |= PCS_MII_RESET; 2586 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 2587 while ((delay) && (val & PCS_MII_RESET)) { 2588 NXGE_DELAY(10); 2589 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 2590 delay--; 2591 } 2592 if (delay == 0) { 2593 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2594 " npi_bmac_pcs_reset portn <%d> failed", portn)); 2595 return (NPI_FAILURE); 2596 } 2597 return (NPI_SUCCESS); 2598 } 2599 2600 npi_status_t 2601 npi_mac_get_link_status(npi_handle_t handle, uint8_t portn, 2602 boolean_t *link_up) 2603 { 2604 uint64_t val; 2605 2606 ASSERT(IS_PORT_NUM_VALID(portn)); 2607 2608 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 2609 2610 if (val & PCS_MII_STATUS_LINK_STATUS) { 2611 *link_up = B_TRUE; 2612 } else { 2613 *link_up = B_FALSE; 2614 } 2615 2616 return (NPI_SUCCESS); 2617 } 2618 2619 npi_status_t 2620 npi_bmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2621 bmac_tx_config_t config) 2622 { 2623 uint64_t val = 0; 2624 2625 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2626 2627 switch (op) { 2628 case ENABLE: 2629 case DISABLE: 2630 ASSERT((config != 0) && ((config & ~CFG_BMAC_TX_ALL) == 0)); 2631 if ((config == 0) || (config & ~CFG_BMAC_TX_ALL) != 0) { 2632 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2633 " npi_bmac_tx_config" 2634 " Invalid Input: config <0x%x>", 2635 config)); 2636 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2637 } 2638 if (op == ENABLE) { 2639 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2640 if (config & CFG_BMAC_TX) 2641 val |= MAC_TX_CFG_TXMAC_ENABLE; 2642 if (config & CFG_BMAC_TX_CRC) 2643 val &= ~MAC_TX_CFG_NO_FCS; 2644 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2645 } else { 2646 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2647 if (config & CFG_BMAC_TX) 2648 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2649 if (config & CFG_BMAC_TX_CRC) 2650 val |= MAC_TX_CFG_NO_FCS; 2651 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2652 } 2653 break; 2654 case INIT: 2655 ASSERT((config & ~CFG_BMAC_TX_ALL) == 0); 2656 if ((config & ~CFG_BMAC_TX_ALL) != 0) { 2657 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2658 " npi_bmac_tx_config" 2659 " Invalid Input: config <0x%x>", 2660 config)); 2661 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2662 } 2663 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2664 if (config & CFG_BMAC_TX) 2665 val |= MAC_TX_CFG_TXMAC_ENABLE; 2666 else 2667 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2668 if (config & CFG_BMAC_TX_CRC) 2669 val &= ~MAC_TX_CFG_NO_FCS; 2670 else 2671 val |= MAC_TX_CFG_NO_FCS; 2672 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2673 break; 2674 default: 2675 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2676 " npi_bmac_tx_config" 2677 " Invalid Input: op <0x%x>", 2678 op)); 2679 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2680 } 2681 2682 return (NPI_SUCCESS); 2683 } 2684 2685 npi_status_t 2686 npi_bmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2687 bmac_rx_config_t config) 2688 { 2689 uint64_t val = 0; 2690 2691 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2692 2693 switch (op) { 2694 case ENABLE: 2695 case DISABLE: 2696 ASSERT((config != 0) && ((config & ~CFG_BMAC_RX_ALL) == 0)); 2697 if ((config == 0) || (config & ~CFG_BMAC_RX_ALL) != 0) { 2698 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2699 " npi_bmac_rx_config" 2700 " Invalid Input: config <0x%x>", 2701 config)); 2702 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2703 } 2704 if (op == ENABLE) { 2705 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2706 if (config & CFG_BMAC_RX) 2707 val |= MAC_RX_CFG_RXMAC_ENABLE; 2708 if (config & CFG_BMAC_RX_STRIP_PAD) 2709 val |= MAC_RX_CFG_STRIP_PAD; 2710 if (config & CFG_BMAC_RX_STRIP_CRC) 2711 val |= MAC_RX_CFG_STRIP_FCS; 2712 if (config & CFG_BMAC_RX_PROMISCUOUS) 2713 val |= MAC_RX_CFG_PROMISC; 2714 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2715 val |= MAC_RX_CFG_PROMISC_GROUP; 2716 if (config & CFG_BMAC_RX_HASH_FILTER) 2717 val |= MAC_RX_CFG_HASH_FILTER_EN; 2718 if (config & CFG_BMAC_RX_ADDR_FILTER) 2719 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2720 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2721 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2722 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2723 } else { 2724 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2725 if (config & CFG_BMAC_RX) 2726 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2727 if (config & CFG_BMAC_RX_STRIP_PAD) 2728 val &= ~MAC_RX_CFG_STRIP_PAD; 2729 if (config & CFG_BMAC_RX_STRIP_CRC) 2730 val &= ~MAC_RX_CFG_STRIP_FCS; 2731 if (config & CFG_BMAC_RX_PROMISCUOUS) 2732 val &= ~MAC_RX_CFG_PROMISC; 2733 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2734 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2735 if (config & CFG_BMAC_RX_HASH_FILTER) 2736 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2737 if (config & CFG_BMAC_RX_ADDR_FILTER) 2738 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2739 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2740 val |= MAC_RX_CFG_DISABLE_DISCARD; 2741 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2742 } 2743 break; 2744 case INIT: 2745 ASSERT((config & ~CFG_BMAC_RX_ALL) == 0); 2746 if ((config & ~CFG_BMAC_RX_ALL) != 0) { 2747 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2748 " npi_bmac_rx_config" 2749 " Invalid Input: config <0x%x>", 2750 config)); 2751 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2752 } 2753 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2754 if (config & CFG_BMAC_RX) 2755 val |= MAC_RX_CFG_RXMAC_ENABLE; 2756 else 2757 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2758 if (config & CFG_BMAC_RX_STRIP_PAD) 2759 val |= MAC_RX_CFG_STRIP_PAD; 2760 else 2761 val &= ~MAC_RX_CFG_STRIP_PAD; 2762 if (config & CFG_BMAC_RX_STRIP_CRC) 2763 val |= MAC_RX_CFG_STRIP_FCS; 2764 else 2765 val &= ~MAC_RX_CFG_STRIP_FCS; 2766 if (config & CFG_BMAC_RX_PROMISCUOUS) 2767 val |= MAC_RX_CFG_PROMISC; 2768 else 2769 val &= ~MAC_RX_CFG_PROMISC; 2770 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2771 val |= MAC_RX_CFG_PROMISC_GROUP; 2772 else 2773 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2774 if (config & CFG_BMAC_RX_HASH_FILTER) 2775 val |= MAC_RX_CFG_HASH_FILTER_EN; 2776 else 2777 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2778 if (config & CFG_BMAC_RX_ADDR_FILTER) 2779 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2780 else 2781 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2782 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2783 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2784 else 2785 val |= MAC_RX_CFG_DISABLE_DISCARD; 2786 2787 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2788 break; 2789 default: 2790 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2791 " npi_bmac_rx_config" 2792 " Invalid Input: op <0x%x>", op)); 2793 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2794 } 2795 2796 return (NPI_SUCCESS); 2797 } 2798 2799 npi_status_t 2800 npi_bmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2801 bmac_rx_iconfig_t iconfig) 2802 { 2803 uint64_t val = 0; 2804 2805 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2806 2807 switch (op) { 2808 case ENABLE: 2809 case DISABLE: 2810 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_RX_ALL) == 0)); 2811 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2812 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2813 " npi_bmac_rx_iconfig" 2814 " Invalid Input: iconfig <0x%x>", 2815 iconfig)); 2816 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2817 } 2818 BMAC_REG_RD(handle, portn, BRXMAC_STAT_MSK_REG, &val); 2819 if (op == ENABLE) 2820 val &= ~iconfig; 2821 else 2822 val |= iconfig; 2823 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, val); 2824 2825 break; 2826 case INIT: 2827 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 2828 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2829 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2830 " npi_bmac_rx_iconfig" 2831 " Invalid Input: iconfig <0x%x>", 2832 iconfig)); 2833 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2834 } 2835 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, ~iconfig); 2836 2837 break; 2838 default: 2839 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2840 " npi_bmac_rx_iconfig" 2841 " Invalid Input: iconfig <0x%x>", 2842 iconfig)); 2843 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2844 } 2845 2846 return (NPI_SUCCESS); 2847 } 2848 2849 npi_status_t 2850 npi_bmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2851 bmac_xif_config_t config) 2852 { 2853 uint64_t val = 0; 2854 2855 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2856 2857 switch (op) { 2858 case ENABLE: 2859 case DISABLE: 2860 ASSERT((config != 0) && ((config & ~CFG_BMAC_XIF_ALL) == 0)); 2861 if ((config == 0) || (config & ~CFG_BMAC_XIF_ALL) != 0) { 2862 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2863 " npi_bmac_xif_config" 2864 " Invalid Input: config <0x%x>", 2865 config)); 2866 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2867 } 2868 if (op == ENABLE) { 2869 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2870 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2871 val |= MAC_XIF_TX_OUTPUT_EN; 2872 if (config & CFG_BMAC_XIF_LOOPBACK) 2873 val |= MAC_XIF_MII_INT_LOOPBACK; 2874 if (config & CFG_BMAC_XIF_GMII_MODE) 2875 val |= MAC_XIF_GMII_MODE; 2876 if (config & CFG_BMAC_XIF_LINKLED) 2877 val |= MAC_XIF_LINK_LED; 2878 if (config & CFG_BMAC_XIF_LED_POLARITY) 2879 val |= MAC_XIF_LED_POLARITY; 2880 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2881 val |= MAC_XIF_SEL_CLK_25MHZ; 2882 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2883 } else { 2884 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2885 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2886 val &= ~MAC_XIF_TX_OUTPUT_EN; 2887 if (config & CFG_BMAC_XIF_LOOPBACK) 2888 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2889 if (config & CFG_BMAC_XIF_GMII_MODE) 2890 val &= ~MAC_XIF_GMII_MODE; 2891 if (config & CFG_BMAC_XIF_LINKLED) 2892 val &= ~MAC_XIF_LINK_LED; 2893 if (config & CFG_BMAC_XIF_LED_POLARITY) 2894 val &= ~MAC_XIF_LED_POLARITY; 2895 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2896 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2897 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2898 } 2899 break; 2900 case INIT: 2901 ASSERT((config & ~CFG_BMAC_XIF_ALL) == 0); 2902 if ((config & ~CFG_BMAC_XIF_ALL) != 0) { 2903 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2904 " npi_bmac_xif_config" 2905 " Invalid Input: config <0x%x>", 2906 config)); 2907 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2908 } 2909 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2910 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2911 val |= MAC_XIF_TX_OUTPUT_EN; 2912 else 2913 val &= ~MAC_XIF_TX_OUTPUT_EN; 2914 if (config & CFG_BMAC_XIF_LOOPBACK) 2915 val |= MAC_XIF_MII_INT_LOOPBACK; 2916 else 2917 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2918 if (config & CFG_BMAC_XIF_GMII_MODE) 2919 val |= MAC_XIF_GMII_MODE; 2920 else 2921 val &= ~MAC_XIF_GMII_MODE; 2922 if (config & CFG_BMAC_XIF_LINKLED) 2923 val |= MAC_XIF_LINK_LED; 2924 else 2925 val &= ~MAC_XIF_LINK_LED; 2926 if (config & CFG_BMAC_XIF_LED_POLARITY) 2927 val |= MAC_XIF_LED_POLARITY; 2928 else 2929 val &= ~MAC_XIF_LED_POLARITY; 2930 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2931 val |= MAC_XIF_SEL_CLK_25MHZ; 2932 else 2933 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2934 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2935 break; 2936 default: 2937 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2938 " npi_bmac_xif_config" 2939 " Invalid Input: op <0x%x>", 2940 op)); 2941 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2942 } 2943 2944 return (NPI_SUCCESS); 2945 } 2946 2947 npi_status_t 2948 npi_bmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2949 bmac_tx_iconfig_t iconfig) 2950 { 2951 uint64_t val = 0; 2952 2953 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2954 2955 switch (op) { 2956 case ENABLE: 2957 case DISABLE: 2958 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2959 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2960 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2961 " npi_bmac_tx_iconfig" 2962 " Invalid Input: iconfig <0x%x>", 2963 iconfig)); 2964 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2965 } 2966 BMAC_REG_RD(handle, portn, BTXMAC_STAT_MSK_REG, &val); 2967 if (op == ENABLE) 2968 val &= ~iconfig; 2969 else 2970 val |= iconfig; 2971 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, val); 2972 2973 break; 2974 case INIT: 2975 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2976 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2977 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2978 " npi_bmac_tx_iconfig" 2979 " Invalid Input: iconfig <0x%x>", 2980 iconfig)); 2981 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2982 } 2983 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, ~iconfig); 2984 2985 break; 2986 default: 2987 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2988 " npi_bmac_tx_iconfig" 2989 " Invalid Input: iconfig <0x%x>", 2990 iconfig)); 2991 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2992 } 2993 2994 return (NPI_SUCCESS); 2995 } 2996 2997 npi_status_t 2998 npi_bmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2999 bmac_ctl_iconfig_t iconfig) 3000 { 3001 uint64_t val = 0; 3002 3003 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3004 3005 switch (op) { 3006 case ENABLE: 3007 case DISABLE: 3008 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_CTL_ALL) == 0)); 3009 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_CTL_ALL) != 0) { 3010 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3011 " npi_bmac_ctl_iconfig" 3012 " Invalid Input: iconfig <0x%x>", 3013 iconfig)); 3014 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 3015 } 3016 BMAC_REG_RD(handle, portn, BMAC_C_S_MSK_REG, &val); 3017 if (op == ENABLE) 3018 val &= ~iconfig; 3019 else 3020 val |= iconfig; 3021 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, val); 3022 3023 break; 3024 case INIT: 3025 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 3026 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 3027 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3028 " npi_bmac_ctl_iconfig" 3029 " Invalid Input: iconfig <0x%x>", 3030 iconfig)); 3031 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 3032 } 3033 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, ~iconfig); 3034 3035 break; 3036 default: 3037 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3038 " npi_bmac_ctl_iconfig" 3039 " Invalid Input: iconfig <0x%x>", 3040 iconfig)); 3041 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 3042 } 3043 3044 return (NPI_SUCCESS); 3045 } 3046 3047 npi_status_t 3048 npi_bmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 3049 bmac_tx_iconfig_t *istatus) 3050 { 3051 uint64_t val = 0; 3052 3053 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3054 3055 BMAC_REG_RD(handle, portn, BTXMAC_STATUS_REG, &val); 3056 *istatus = (uint32_t)val; 3057 3058 return (NPI_SUCCESS); 3059 } 3060 3061 npi_status_t 3062 npi_bmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 3063 bmac_rx_iconfig_t *istatus) 3064 { 3065 uint64_t val = 0; 3066 3067 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3068 3069 BMAC_REG_RD(handle, portn, BRXMAC_STATUS_REG, &val); 3070 *istatus = (uint32_t)val; 3071 3072 return (NPI_SUCCESS); 3073 } 3074 3075 npi_status_t 3076 npi_bmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 3077 bmac_ctl_iconfig_t *istatus) 3078 { 3079 uint64_t val = 0; 3080 3081 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3082 3083 BMAC_REG_RD(handle, portn, BMAC_CTRL_STAT_REG, &val); 3084 *istatus = (uint32_t)val; 3085 3086 return (NPI_SUCCESS); 3087 } 3088 3089 npi_status_t 3090 npi_mac_mif_mdio_read(npi_handle_t handle, uint8_t portn, uint8_t device, 3091 uint16_t xcvr_reg, uint16_t *value) 3092 { 3093 mif_frame_t frame; 3094 uint_t delay; 3095 3096 frame.value = 0; 3097 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3098 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select address */ 3099 frame.bits.w0.phyad = portn; /* Port number */ 3100 frame.bits.w0.regad = device; /* Device number */ 3101 frame.bits.w0.ta_msb = 1; 3102 frame.bits.w0.ta_lsb = 0; 3103 frame.bits.w0.data = xcvr_reg; /* register address */ 3104 3105 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3106 "mdio read port %d addr val=0x%x\n", portn, frame.value)); 3107 3108 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3109 3110 delay = 0; 3111 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3112 3113 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3114 "mdio read port %d addr poll=0x%x\n", portn, frame.value)); 3115 3116 if (delay == MIF_DELAY) { 3117 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3118 "mdio read no response1\n")); 3119 } 3120 3121 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3122 frame.bits.w0.op = FRAME45_OP_READ; /* Read */ 3123 frame.bits.w0.phyad = portn; /* Port Number */ 3124 frame.bits.w0.regad = device; /* Device Number */ 3125 frame.bits.w0.ta_msb = 1; 3126 frame.bits.w0.ta_lsb = 0; 3127 3128 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3129 "mdio read port %d data frame=0x%x\n", portn, frame.value)); 3130 3131 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3132 3133 delay = 0; 3134 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3135 3136 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3137 "mdio read port %d data poll=0x%x\n", portn, frame.value)); 3138 3139 *value = frame.bits.w0.data; 3140 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3141 "mdio read port=%d val=0x%x\n", portn, *value)); 3142 3143 if (delay == MIF_DELAY) { 3144 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3145 "mdio read no response2\n")); 3146 } 3147 3148 return (NPI_SUCCESS); 3149 } 3150 3151 npi_status_t 3152 npi_mac_mif_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3153 uint16_t *value) 3154 { 3155 mif_frame_t frame; 3156 uint_t delay; 3157 3158 frame.bits.w0.st = 0x1; /* Clause 22 */ 3159 frame.bits.w0.op = 0x2; 3160 frame.bits.w0.phyad = portn; 3161 frame.bits.w0.regad = xcvr_reg; 3162 frame.bits.w0.ta_msb = 1; 3163 frame.bits.w0.ta_lsb = 0; 3164 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3165 3166 delay = 0; 3167 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3168 3169 if (delay == MAX_PIO_RETRIES) 3170 return (NPI_FAILURE | NPI_MAC_MII_READ_FAILED(portn)); 3171 3172 *value = frame.bits.w0.data; 3173 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3174 "mif mii read port %d reg=0x%x frame=0x%x\n", portn, 3175 xcvr_reg, frame.bits.w0.data)); 3176 3177 return (NPI_SUCCESS); 3178 } 3179 3180 npi_status_t 3181 npi_mac_mif_mdio_write(npi_handle_t handle, uint8_t portn, uint8_t device, 3182 uint16_t xcvr_reg, uint16_t value) 3183 { 3184 mif_frame_t frame; 3185 uint_t delay; 3186 3187 frame.value = 0; 3188 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3189 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select Address */ 3190 frame.bits.w0.phyad = portn; /* Port Number */ 3191 frame.bits.w0.regad = device; /* Device Number */ 3192 frame.bits.w0.ta_msb = 1; 3193 frame.bits.w0.ta_lsb = 0; 3194 frame.bits.w0.data = xcvr_reg; /* register address */ 3195 3196 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3197 3198 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3199 "mdio write port %d addr val=0x%x\n", portn, frame.value)); 3200 3201 delay = 0; 3202 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3203 3204 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3205 "mdio write port %d addr poll=0x%x\n", portn, frame.value)); 3206 3207 if (delay == MIF_DELAY) { 3208 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3209 "mdio write no response1\n")); 3210 } 3211 3212 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3213 frame.bits.w0.op = FRAME45_OP_WRITE; /* Write */ 3214 frame.bits.w0.phyad = portn; /* Port number */ 3215 frame.bits.w0.regad = device; /* Device number */ 3216 frame.bits.w0.ta_msb = 1; 3217 frame.bits.w0.ta_lsb = 0; 3218 frame.bits.w0.data = value; 3219 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3220 3221 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3222 "mdio write port %d data val=0x%x\n", portn, frame.value)); 3223 3224 delay = 0; 3225 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3226 3227 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3228 "mdio write port %d data poll=0x%x\n", portn, frame.value)); 3229 3230 if (delay == MIF_DELAY) { 3231 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3232 "mdio write no response2\n")); 3233 } 3234 3235 return (NPI_SUCCESS); 3236 } 3237 3238 npi_status_t 3239 npi_mac_mif_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3240 uint16_t value) 3241 { 3242 mif_frame_t frame; 3243 uint_t delay; 3244 3245 frame.bits.w0.st = 0x1; /* Clause 22 */ 3246 frame.bits.w0.op = 0x1; 3247 frame.bits.w0.phyad = portn; 3248 frame.bits.w0.regad = xcvr_reg; 3249 frame.bits.w0.ta_msb = 1; 3250 frame.bits.w0.ta_lsb = 0; 3251 frame.bits.w0.data = value; 3252 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3253 3254 delay = 0; 3255 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3256 3257 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3258 "mif mii write port %d reg=0x%x frame=0x%x\n", portn, 3259 xcvr_reg, frame.value)); 3260 3261 if (delay == MAX_PIO_RETRIES) 3262 return (NPI_FAILURE | NPI_MAC_MII_WRITE_FAILED(portn)); 3263 3264 return (NPI_SUCCESS); 3265 } 3266 3267 npi_status_t 3268 npi_mac_pcs_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3269 uint16_t *value) 3270 { 3271 pcs_anar_t pcs_anar; 3272 pcs_anar_t pcs_anlpar; 3273 pcs_stat_t pcs_stat; 3274 pcs_stat_mc_t pcs_stat_mc; 3275 mii_anar_t anar; 3276 mii_anar_t anlpar; 3277 mii_aner_t aner; 3278 mii_esr_t esr; 3279 mii_gsr_t gsr; 3280 uint64_t val = 0; 3281 3282 ASSERT(IS_PORT_NUM_VALID(portn)); 3283 3284 switch (xcvr_reg) { 3285 case MII_CONTROL: 3286 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 3287 *value = (uint16_t)val; 3288 break; 3289 case MII_STATUS: 3290 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 3291 pcs_stat.value = val; 3292 PCS_REG_RD(handle, portn, PCS_STATE_MACHINE_REG, &val); 3293 pcs_stat_mc.value = val; 3294 if ((pcs_stat_mc.bits.w0.link_cfg_stat == 0xB) && 3295 (pcs_stat_mc.bits.w0.word_sync != 0)) { 3296 pcs_stat.bits.w0.link_stat = 1; 3297 } else if (pcs_stat_mc.bits.w0.link_cfg_stat != 0xB) { 3298 pcs_stat.bits.w0.link_stat = 0; 3299 } 3300 *value = (uint16_t)pcs_stat.value; 3301 break; 3302 case NXGE_MII_ESR: 3303 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3304 pcs_anar.value = (uint16_t)val; 3305 esr.value = 0; 3306 esr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3307 esr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3308 *value = esr.value; 3309 break; 3310 case MII_AN_ADVERT: 3311 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3312 pcs_anar.value = (uint16_t)val; 3313 anar.value = 0; 3314 anar.bits.cap_pause = pcs_anar.bits.w0.pause; 3315 anar.bits.cap_asmpause = pcs_anar.bits.w0.asm_pause; 3316 *value = anar.value; 3317 break; 3318 case MII_AN_LPABLE: 3319 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3320 pcs_anlpar.value = (uint16_t)val; 3321 anlpar.bits.cap_pause = pcs_anlpar.bits.w0.pause; 3322 anlpar.bits.cap_asmpause = pcs_anlpar.bits.w0.asm_pause; 3323 *value = anlpar.value; 3324 break; 3325 case MII_AN_EXPANSION: 3326 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3327 pcs_anar.value = (uint16_t)val; 3328 aner.value = 0; 3329 aner.bits.lp_an_able = pcs_anar.bits.w0.full_duplex | 3330 pcs_anar.bits.w0.half_duplex; 3331 *value = aner.value; 3332 break; 3333 case NXGE_MII_GSR: 3334 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3335 pcs_anar.value = (uint16_t)val; 3336 gsr.value = 0; 3337 gsr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3338 gsr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3339 *value = gsr.value; 3340 break; 3341 default: 3342 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3343 " npi_mac_pcs_mii_read" 3344 " Invalid Input: xcvr_reg <0x%x>", 3345 xcvr_reg)); 3346 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3347 } 3348 3349 return (NPI_SUCCESS); 3350 } 3351 3352 npi_status_t 3353 npi_mac_pcs_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3354 uint16_t value) 3355 { 3356 pcs_anar_t pcs_anar; 3357 mii_anar_t anar; 3358 mii_gcr_t gcr; 3359 uint64_t val; 3360 3361 ASSERT(IS_PORT_NUM_VALID(portn)); 3362 3363 switch (xcvr_reg) { 3364 case MII_CONTROL: 3365 val = (uint16_t)value; 3366 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 3367 break; 3368 case MII_AN_ADVERT: 3369 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3370 pcs_anar.value = (uint16_t)val; 3371 anar.value = value; 3372 pcs_anar.bits.w0.asm_pause = anar.bits.cap_asmpause; 3373 pcs_anar.bits.w0.pause = anar.bits.cap_pause; 3374 val = pcs_anar.value; 3375 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3376 break; 3377 case NXGE_MII_GCR: 3378 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3379 pcs_anar.value = (uint16_t)val; 3380 gcr.value = value; 3381 pcs_anar.bits.w0.full_duplex = gcr.bits.link_1000fdx; 3382 pcs_anar.bits.w0.half_duplex = gcr.bits.link_1000hdx; 3383 val = pcs_anar.value; 3384 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3385 break; 3386 default: 3387 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3388 " npi_mac_pcs_mii_write" 3389 " Invalid Input: xcvr_reg <0x%x>", 3390 xcvr_reg)); 3391 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3392 } 3393 3394 return (NPI_SUCCESS); 3395 } 3396 3397 npi_status_t 3398 npi_mac_mif_link_intr_enable(npi_handle_t handle, uint8_t portn, 3399 uint8_t xcvr_reg, uint16_t mask) 3400 { 3401 mif_cfg_t mif_cfg; 3402 3403 ASSERT(IS_PORT_NUM_VALID(portn)); 3404 3405 ASSERT(xcvr_reg <= NXGE_MAX_MII_REGS); 3406 if (xcvr_reg > NXGE_MAX_MII_REGS) { 3407 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3408 " npi_mac_mif_link_intr_enable" 3409 " Invalid Input: xcvr_reg <0x%x>", 3410 xcvr_reg)); 3411 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3412 } 3413 3414 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3415 3416 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3417 mif_cfg.bits.w0.reg_addr = xcvr_reg; /* Register address */ 3418 mif_cfg.bits.w0.indirect_md = 0; /* Clause 22 */ 3419 mif_cfg.bits.w0.poll_en = 1; 3420 3421 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3422 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3423 3424 NXGE_DELAY(20); 3425 3426 return (NPI_SUCCESS); 3427 } 3428 3429 npi_status_t 3430 npi_mac_mif_mdio_link_intr_enable(npi_handle_t handle, uint8_t portn, 3431 uint8_t device, uint16_t xcvr_reg, uint16_t mask) 3432 { 3433 mif_cfg_t mif_cfg; 3434 mif_frame_t frame; 3435 uint_t delay; 3436 3437 ASSERT(IS_PORT_NUM_VALID(portn)); 3438 3439 frame.bits.w0.st = 0; /* Clause 45 */ 3440 frame.bits.w0.op = 0; /* Select address */ 3441 frame.bits.w0.phyad = portn; /* Port number */ 3442 frame.bits.w0.regad = device; /* Device number */ 3443 frame.bits.w0.ta_msb = 1; 3444 frame.bits.w0.ta_lsb = 0; 3445 frame.bits.w0.data = xcvr_reg; /* register address */ 3446 3447 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3448 3449 delay = 0; 3450 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3451 if (delay == MAX_PIO_RETRIES) 3452 return (NPI_FAILURE); 3453 3454 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3455 3456 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3457 mif_cfg.bits.w0.reg_addr = device; /* Register address */ 3458 mif_cfg.bits.w0.indirect_md = 1; /* Clause 45 */ 3459 mif_cfg.bits.w0.poll_en = 1; 3460 3461 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3462 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3463 3464 NXGE_DELAY(20); 3465 3466 return (NPI_SUCCESS); 3467 } 3468 3469 void 3470 npi_mac_mif_set_indirect_mode(npi_handle_t handle, boolean_t on_off) 3471 { 3472 mif_cfg_t mif_cfg; 3473 3474 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3475 mif_cfg.bits.w0.indirect_md = on_off; 3476 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3477 } 3478 3479 void 3480 npi_mac_mif_set_atca_mode(npi_handle_t handle, boolean_t on_off) 3481 { 3482 mif_cfg_t mif_cfg; 3483 3484 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3485 mif_cfg.bits.w0.atca_ge = on_off; 3486 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3487 } 3488 3489 npi_status_t 3490 npi_bmac_send_pause(npi_handle_t handle, uint8_t portn, uint16_t pause_time) 3491 { 3492 uint64_t val; 3493 3494 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3495 3496 val = MAC_SEND_PAUSE_SEND | pause_time; 3497 BMAC_REG_WR(handle, portn, MAC_SEND_PAUSE_REG, val); 3498 3499 return (NPI_SUCCESS); 3500 } 3501 3502 npi_status_t 3503 npi_xmac_xif_led(npi_handle_t handle, uint8_t portn, boolean_t on_off) 3504 { 3505 uint64_t val = 0; 3506 3507 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3508 3509 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 3510 3511 if (on_off) { 3512 val |= XMAC_XIF_LED_POLARITY; 3513 val &= ~XMAC_XIF_FORCE_LED_ON; 3514 } else { 3515 val &= ~XMAC_XIF_LED_POLARITY; 3516 val |= XMAC_XIF_FORCE_LED_ON; 3517 } 3518 3519 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 3520 3521 return (NPI_SUCCESS); 3522 } 3523 3524 npi_status_t 3525 npi_xmac_zap_tx_counters(npi_handle_t handle, uint8_t portn) 3526 { 3527 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3528 3529 XMAC_REG_WR(handle, portn, XTXMAC_FRM_CNT_REG, 0); 3530 XMAC_REG_WR(handle, portn, XTXMAC_BYTE_CNT_REG, 0); 3531 3532 return (NPI_SUCCESS); 3533 } 3534 3535 npi_status_t 3536 npi_xmac_zap_rx_counters(npi_handle_t handle, uint8_t portn) 3537 { 3538 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3539 3540 XMAC_REG_WR(handle, portn, XRXMAC_BT_CNT_REG, 0); 3541 XMAC_REG_WR(handle, portn, XRXMAC_BC_FRM_CNT_REG, 0); 3542 XMAC_REG_WR(handle, portn, XRXMAC_MC_FRM_CNT_REG, 0); 3543 XMAC_REG_WR(handle, portn, XRXMAC_FRAG_CNT_REG, 0); 3544 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT1_REG, 0); 3545 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT2_REG, 0); 3546 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT3_REG, 0); 3547 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT4_REG, 0); 3548 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT5_REG, 0); 3549 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT6_REG, 0); 3550 XMAC_REG_WR(handle, portn, XRXMAC_MPSZER_CNT_REG, 0); 3551 XMAC_REG_WR(handle, portn, XRXMAC_CRC_ER_CNT_REG, 0); 3552 XMAC_REG_WR(handle, portn, XRXMAC_CD_VIO_CNT_REG, 0); 3553 XMAC_REG_WR(handle, portn, XRXMAC_AL_ER_CNT_REG, 0); 3554 XMAC_REG_WR(handle, portn, XMAC_LINK_FLT_CNT_REG, 0); 3555 3556 return (NPI_SUCCESS); 3557 } 3558