1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <npi_mac.h> 27 28 #define MIF_DELAY 500 29 30 #define MAX_FRAME_SZ1 0x5EE 31 #define MAX_FRAME_SZ2 0x5F6 32 #define MAX_FRAME_SZ3 0x7D6 33 #define MAX_FRAME_SZ4 0x232E 34 #define MAX_FRAME_SZ5 0x2406 35 36 #define XMAC_WAIT_REG(handle, portn, reg, val) {\ 37 uint32_t cnt = MAX_PIO_RETRIES;\ 38 do {\ 39 NXGE_DELAY(MAC_RESET_WAIT);\ 40 XMAC_REG_RD(handle, portn, reg, &val);\ 41 cnt--;\ 42 } while (((val & 0x3) != 0) && (cnt > 0));\ 43 } 44 45 #define BMAC_WAIT_REG(handle, portn, reg, val) {\ 46 uint32_t cnt = MAX_PIO_RETRIES;\ 47 do {\ 48 NXGE_DELAY(MAC_RESET_WAIT);\ 49 BMAC_REG_RD(handle, portn, reg, &val);\ 50 cnt--;\ 51 } while (((val & 0x3) != 0) && (cnt > 0));\ 52 } 53 54 #define MIF_WAIT_REG(handle, m_frame, t_delay, interval, max_delay) { \ 55 do { \ 56 NXGE_DELAY(interval); \ 57 MIF_REG_RD(handle, MIF_OUTPUT_FRAME_REG, &m_frame.value); \ 58 t_delay++; \ 59 } while ((m_frame.bits.w0.ta_lsb == 0) && t_delay < max_delay); \ 60 } 61 62 uint64_t xmac_offset[] = { 63 XTXMAC_SW_RST_REG, 64 XRXMAC_SW_RST_REG, 65 XTXMAC_STATUS_REG, 66 XRXMAC_STATUS_REG, 67 XMAC_CTRL_STAT_REG, 68 XTXMAC_STAT_MSK_REG, 69 XRXMAC_STAT_MSK_REG, 70 XMAC_C_S_MSK_REG, 71 XMAC_CONFIG_REG, 72 XMAC_IPG_REG, 73 XMAC_MIN_REG, 74 XMAC_MAX_REG, 75 XMAC_ADDR0_REG, 76 XMAC_ADDR1_REG, 77 XMAC_ADDR2_REG, 78 XRXMAC_BT_CNT_REG, 79 XRXMAC_BC_FRM_CNT_REG, 80 XRXMAC_MC_FRM_CNT_REG, 81 XRXMAC_FRAG_CNT_REG, 82 XRXMAC_HIST_CNT1_REG, 83 XRXMAC_HIST_CNT2_REG, 84 XRXMAC_HIST_CNT3_REG, 85 XRXMAC_HIST_CNT4_REG, 86 XRXMAC_HIST_CNT5_REG, 87 XRXMAC_HIST_CNT6_REG, 88 XRXMAC_MPSZER_CNT_REG, 89 XRXMAC_CRC_ER_CNT_REG, 90 XRXMAC_CD_VIO_CNT_REG, 91 XRXMAC_AL_ER_CNT_REG, 92 XTXMAC_FRM_CNT_REG, 93 XTXMAC_BYTE_CNT_REG, 94 XMAC_LINK_FLT_CNT_REG, 95 XRXMAC_HIST_CNT7_REG, 96 XMAC_SM_REG, 97 XMAC_INTERN1_REG, 98 XMAC_INTERN2_REG, 99 XMAC_ADDR_CMPEN_REG, 100 XMAC_ADDR3_REG, 101 XMAC_ADDR4_REG, 102 XMAC_ADDR5_REG, 103 XMAC_ADDR6_REG, 104 XMAC_ADDR7_REG, 105 XMAC_ADDR8_REG, 106 XMAC_ADDR9_REG, 107 XMAC_ADDR10_REG, 108 XMAC_ADDR11_REG, 109 XMAC_ADDR12_REG, 110 XMAC_ADDR13_REG, 111 XMAC_ADDR14_REG, 112 XMAC_ADDR15_REG, 113 XMAC_ADDR16_REG, 114 XMAC_ADDR17_REG, 115 XMAC_ADDR18_REG, 116 XMAC_ADDR19_REG, 117 XMAC_ADDR20_REG, 118 XMAC_ADDR21_REG, 119 XMAC_ADDR22_REG, 120 XMAC_ADDR23_REG, 121 XMAC_ADDR24_REG, 122 XMAC_ADDR25_REG, 123 XMAC_ADDR26_REG, 124 XMAC_ADDR27_REG, 125 XMAC_ADDR28_REG, 126 XMAC_ADDR29_REG, 127 XMAC_ADDR30_REG, 128 XMAC_ADDR31_REG, 129 XMAC_ADDR32_REG, 130 XMAC_ADDR33_REG, 131 XMAC_ADDR34_REG, 132 XMAC_ADDR35_REG, 133 XMAC_ADDR36_REG, 134 XMAC_ADDR37_REG, 135 XMAC_ADDR38_REG, 136 XMAC_ADDR39_REG, 137 XMAC_ADDR40_REG, 138 XMAC_ADDR41_REG, 139 XMAC_ADDR42_REG, 140 XMAC_ADDR43_REG, 141 XMAC_ADDR44_REG, 142 XMAC_ADDR45_REG, 143 XMAC_ADDR46_REG, 144 XMAC_ADDR47_REG, 145 XMAC_ADDR48_REG, 146 XMAC_ADDR49_REG, 147 XMAC_ADDR50_REG, 148 XMAC_ADDR_FILT0_REG, 149 XMAC_ADDR_FILT1_REG, 150 XMAC_ADDR_FILT2_REG, 151 XMAC_ADDR_FILT12_MASK_REG, 152 XMAC_ADDR_FILT0_MASK_REG, 153 XMAC_HASH_TBL0_REG, 154 XMAC_HASH_TBL1_REG, 155 XMAC_HASH_TBL2_REG, 156 XMAC_HASH_TBL3_REG, 157 XMAC_HASH_TBL4_REG, 158 XMAC_HASH_TBL5_REG, 159 XMAC_HASH_TBL6_REG, 160 XMAC_HASH_TBL7_REG, 161 XMAC_HASH_TBL8_REG, 162 XMAC_HASH_TBL9_REG, 163 XMAC_HASH_TBL10_REG, 164 XMAC_HASH_TBL11_REG, 165 XMAC_HASH_TBL12_REG, 166 XMAC_HASH_TBL13_REG, 167 XMAC_HASH_TBL14_REG, 168 XMAC_HASH_TBL15_REG, 169 XMAC_HOST_INF0_REG, 170 XMAC_HOST_INF1_REG, 171 XMAC_HOST_INF2_REG, 172 XMAC_HOST_INF3_REG, 173 XMAC_HOST_INF4_REG, 174 XMAC_HOST_INF5_REG, 175 XMAC_HOST_INF6_REG, 176 XMAC_HOST_INF7_REG, 177 XMAC_HOST_INF8_REG, 178 XMAC_HOST_INF9_REG, 179 XMAC_HOST_INF10_REG, 180 XMAC_HOST_INF11_REG, 181 XMAC_HOST_INF12_REG, 182 XMAC_HOST_INF13_REG, 183 XMAC_HOST_INF14_REG, 184 XMAC_HOST_INF15_REG, 185 XMAC_HOST_INF16_REG, 186 XMAC_HOST_INF17_REG, 187 XMAC_HOST_INF18_REG, 188 XMAC_HOST_INF19_REG, 189 XMAC_PA_DATA0_REG, 190 XMAC_PA_DATA1_REG, 191 XMAC_DEBUG_SEL_REG, 192 XMAC_TRAINING_VECT_REG, 193 }; 194 195 const char *xmac_name[] = { 196 "XTXMAC_SW_RST_REG", 197 "XRXMAC_SW_RST_REG", 198 "XTXMAC_STATUS_REG", 199 "XRXMAC_STATUS_REG", 200 "XMAC_CTRL_STAT_REG", 201 "XTXMAC_STAT_MSK_REG", 202 "XRXMAC_STAT_MSK_REG", 203 "XMAC_C_S_MSK_REG", 204 "XMAC_CONFIG_REG", 205 "XMAC_IPG_REG", 206 "XMAC_MIN_REG", 207 "XMAC_MAX_REG", 208 "XMAC_ADDR0_REG", 209 "XMAC_ADDR1_REG", 210 "XMAC_ADDR2_REG", 211 "XRXMAC_BT_CNT_REG", 212 "XRXMAC_BC_FRM_CNT_REG", 213 "XRXMAC_MC_FRM_CNT_REG", 214 "XRXMAC_FRAG_CNT_REG", 215 "XRXMAC_HIST_CNT1_REG", 216 "XRXMAC_HIST_CNT2_REG", 217 "XRXMAC_HIST_CNT3_REG", 218 "XRXMAC_HIST_CNT4_REG", 219 "XRXMAC_HIST_CNT5_REG", 220 "XRXMAC_HIST_CNT6_REG", 221 "XRXMAC_MPSZER_CNT_REG", 222 "XRXMAC_CRC_ER_CNT_REG", 223 "XRXMAC_CD_VIO_CNT_REG", 224 "XRXMAC_AL_ER_CNT_REG", 225 "XTXMAC_FRM_CNT_REG", 226 "XTXMAC_BYTE_CNT_REG", 227 "XMAC_LINK_FLT_CNT_REG", 228 "XRXMAC_HIST_CNT7_REG", 229 "XMAC_SM_REG", 230 "XMAC_INTERN1_REG", 231 "XMAC_INTERN2_REG", 232 "XMAC_ADDR_CMPEN_REG", 233 "XMAC_ADDR3_REG", 234 "XMAC_ADDR4_REG", 235 "XMAC_ADDR5_REG", 236 "XMAC_ADDR6_REG", 237 "XMAC_ADDR7_REG", 238 "XMAC_ADDR8_REG", 239 "XMAC_ADDR9_REG", 240 "XMAC_ADDR10_REG", 241 "XMAC_ADDR11_REG", 242 "XMAC_ADDR12_REG", 243 "XMAC_ADDR13_REG", 244 "XMAC_ADDR14_REG", 245 "XMAC_ADDR15_REG", 246 "XMAC_ADDR16_REG", 247 "XMAC_ADDR17_REG", 248 "XMAC_ADDR18_REG", 249 "XMAC_ADDR19_REG", 250 "XMAC_ADDR20_REG", 251 "XMAC_ADDR21_REG", 252 "XMAC_ADDR22_REG", 253 "XMAC_ADDR23_REG", 254 "XMAC_ADDR24_REG", 255 "XMAC_ADDR25_REG", 256 "XMAC_ADDR26_REG", 257 "XMAC_ADDR27_REG", 258 "XMAC_ADDR28_REG", 259 "XMAC_ADDR29_REG", 260 "XMAC_ADDR30_REG", 261 "XMAC_ADDR31_REG", 262 "XMAC_ADDR32_REG", 263 "XMAC_ADDR33_REG", 264 "XMAC_ADDR34_REG", 265 "XMAC_ADDR35_REG", 266 "XMAC_ADDR36_REG", 267 "XMAC_ADDR37_REG", 268 "XMAC_ADDR38_REG", 269 "XMAC_ADDR39_REG", 270 "XMAC_ADDR40_REG", 271 "XMAC_ADDR41_REG", 272 "XMAC_ADDR42_REG", 273 "XMAC_ADDR43_REG", 274 "XMAC_ADDR44_REG", 275 "XMAC_ADDR45_REG", 276 "XMAC_ADDR46_REG", 277 "XMAC_ADDR47_REG", 278 "XMAC_ADDR48_REG", 279 "XMAC_ADDR49_REG", 280 "XMAC_ADDR50_RE", 281 "XMAC_ADDR_FILT0_REG", 282 "XMAC_ADDR_FILT1_REG", 283 "XMAC_ADDR_FILT2_REG", 284 "XMAC_ADDR_FILT12_MASK_REG", 285 "XMAC_ADDR_FILT0_MASK_REG", 286 "XMAC_HASH_TBL0_REG", 287 "XMAC_HASH_TBL1_REG", 288 "XMAC_HASH_TBL2_REG", 289 "XMAC_HASH_TBL3_REG", 290 "XMAC_HASH_TBL4_REG", 291 "XMAC_HASH_TBL5_REG", 292 "XMAC_HASH_TBL6_REG", 293 "XMAC_HASH_TBL7_REG", 294 "XMAC_HASH_TBL8_REG", 295 "XMAC_HASH_TBL9_REG", 296 "XMAC_HASH_TBL10_REG", 297 "XMAC_HASH_TBL11_REG", 298 "XMAC_HASH_TBL12_REG", 299 "XMAC_HASH_TBL13_REG", 300 "XMAC_HASH_TBL14_REG", 301 "XMAC_HASH_TBL15_REG", 302 "XMAC_HOST_INF0_REG", 303 "XMAC_HOST_INF1_REG", 304 "XMAC_HOST_INF2_REG", 305 "XMAC_HOST_INF3_REG", 306 "XMAC_HOST_INF4_REG", 307 "XMAC_HOST_INF5_REG", 308 "XMAC_HOST_INF6_REG", 309 "XMAC_HOST_INF7_REG", 310 "XMAC_HOST_INF8_REG", 311 "XMAC_HOST_INF9_REG", 312 "XMAC_HOST_INF10_REG", 313 "XMAC_HOST_INF11_REG", 314 "XMAC_HOST_INF12_REG", 315 "XMAC_HOST_INF13_REG", 316 "XMAC_HOST_INF14_REG", 317 "XMAC_HOST_INF15_REG", 318 "XMAC_HOST_INF16_REG", 319 "XMAC_HOST_INF17_REG", 320 "XMAC_HOST_INF18_REG", 321 "XMAC_HOST_INF19_REG", 322 "XMAC_PA_DATA0_REG", 323 "XMAC_PA_DATA1_REG", 324 "XMAC_DEBUG_SEL_REG", 325 "XMAC_TRAINING_VECT_REG", 326 }; 327 328 uint64_t bmac_offset[] = { 329 BTXMAC_SW_RST_REG, 330 BRXMAC_SW_RST_REG, 331 MAC_SEND_PAUSE_REG, 332 BTXMAC_STATUS_REG, 333 BRXMAC_STATUS_REG, 334 BMAC_CTRL_STAT_REG, 335 BTXMAC_STAT_MSK_REG, 336 BRXMAC_STAT_MSK_REG, 337 BMAC_C_S_MSK_REG, 338 TXMAC_CONFIG_REG, 339 RXMAC_CONFIG_REG, 340 MAC_CTRL_CONFIG_REG, 341 MAC_XIF_CONFIG_REG, 342 BMAC_MIN_REG, 343 BMAC_MAX_REG, 344 MAC_PA_SIZE_REG, 345 MAC_CTRL_TYPE_REG, 346 BMAC_ADDR0_REG, 347 BMAC_ADDR1_REG, 348 BMAC_ADDR2_REG, 349 BMAC_ADDR3_REG, 350 BMAC_ADDR4_REG, 351 BMAC_ADDR5_REG, 352 BMAC_ADDR6_REG, 353 BMAC_ADDR7_REG, 354 BMAC_ADDR8_REG, 355 BMAC_ADDR9_REG, 356 BMAC_ADDR10_REG, 357 BMAC_ADDR11_REG, 358 BMAC_ADDR12_REG, 359 BMAC_ADDR13_REG, 360 BMAC_ADDR14_REG, 361 BMAC_ADDR15_REG, 362 BMAC_ADDR16_REG, 363 BMAC_ADDR17_REG, 364 BMAC_ADDR18_REG, 365 BMAC_ADDR19_REG, 366 BMAC_ADDR20_REG, 367 BMAC_ADDR21_REG, 368 BMAC_ADDR22_REG, 369 BMAC_ADDR23_REG, 370 MAC_FC_ADDR0_REG, 371 MAC_FC_ADDR1_REG, 372 MAC_FC_ADDR2_REG, 373 MAC_ADDR_FILT0_REG, 374 MAC_ADDR_FILT1_REG, 375 MAC_ADDR_FILT2_REG, 376 MAC_ADDR_FILT12_MASK_REG, 377 MAC_ADDR_FILT00_MASK_REG, 378 MAC_HASH_TBL0_REG, 379 MAC_HASH_TBL1_REG, 380 MAC_HASH_TBL2_REG, 381 MAC_HASH_TBL3_REG, 382 MAC_HASH_TBL4_REG, 383 MAC_HASH_TBL5_REG, 384 MAC_HASH_TBL6_REG, 385 MAC_HASH_TBL7_REG, 386 MAC_HASH_TBL8_REG, 387 MAC_HASH_TBL9_REG, 388 MAC_HASH_TBL10_REG, 389 MAC_HASH_TBL11_REG, 390 MAC_HASH_TBL12_REG, 391 MAC_HASH_TBL13_REG, 392 MAC_HASH_TBL14_REG, 393 MAC_HASH_TBL15_REG, 394 RXMAC_FRM_CNT_REG, 395 MAC_LEN_ER_CNT_REG, 396 BMAC_AL_ER_CNT_REG, 397 BMAC_CRC_ER_CNT_REG, 398 BMAC_CD_VIO_CNT_REG, 399 BMAC_SM_REG, 400 BMAC_ALTAD_CMPEN_REG, 401 BMAC_HOST_INF0_REG, 402 BMAC_HOST_INF1_REG, 403 BMAC_HOST_INF2_REG, 404 BMAC_HOST_INF3_REG, 405 BMAC_HOST_INF4_REG, 406 BMAC_HOST_INF5_REG, 407 BMAC_HOST_INF6_REG, 408 BMAC_HOST_INF7_REG, 409 BMAC_HOST_INF8_REG, 410 BTXMAC_BYTE_CNT_REG, 411 BTXMAC_FRM_CNT_REG, 412 BRXMAC_BYTE_CNT_REG, 413 }; 414 415 const char *bmac_name[] = { 416 "BTXMAC_SW_RST_REG", 417 "BRXMAC_SW_RST_REG", 418 "MAC_SEND_PAUSE_REG", 419 "BTXMAC_STATUS_REG", 420 "BRXMAC_STATUS_REG", 421 "BMAC_CTRL_STAT_REG", 422 "BTXMAC_STAT_MSK_REG", 423 "BRXMAC_STAT_MSK_REG", 424 "BMAC_C_S_MSK_REG", 425 "TXMAC_CONFIG_REG", 426 "RXMAC_CONFIG_REG", 427 "MAC_CTRL_CONFIG_REG", 428 "MAC_XIF_CONFIG_REG", 429 "BMAC_MIN_REG", 430 "BMAC_MAX_REG", 431 "MAC_PA_SIZE_REG", 432 "MAC_CTRL_TYPE_REG", 433 "BMAC_ADDR0_REG", 434 "BMAC_ADDR1_REG", 435 "BMAC_ADDR2_REG", 436 "BMAC_ADDR3_REG", 437 "BMAC_ADDR4_REG", 438 "BMAC_ADDR5_REG", 439 "BMAC_ADDR6_REG", 440 "BMAC_ADDR7_REG", 441 "BMAC_ADDR8_REG", 442 "BMAC_ADDR9_REG", 443 "BMAC_ADDR10_REG", 444 "BMAC_ADDR11_REG", 445 "BMAC_ADDR12_REG", 446 "BMAC_ADDR13_REG", 447 "BMAC_ADDR14_REG", 448 "BMAC_ADDR15_REG", 449 "BMAC_ADDR16_REG", 450 "BMAC_ADDR17_REG", 451 "BMAC_ADDR18_REG", 452 "BMAC_ADDR19_REG", 453 "BMAC_ADDR20_REG", 454 "BMAC_ADDR21_REG", 455 "BMAC_ADDR22_REG", 456 "BMAC_ADDR23_REG", 457 "MAC_FC_ADDR0_REG", 458 "MAC_FC_ADDR1_REG", 459 "MAC_FC_ADDR2_REG", 460 "MAC_ADDR_FILT0_REG", 461 "MAC_ADDR_FILT1_REG", 462 "MAC_ADDR_FILT2_REG", 463 "MAC_ADDR_FILT12_MASK_REG", 464 "MAC_ADDR_FILT00_MASK_REG", 465 "MAC_HASH_TBL0_REG", 466 "MAC_HASH_TBL1_REG", 467 "MAC_HASH_TBL2_REG", 468 "MAC_HASH_TBL3_REG", 469 "MAC_HASH_TBL4_REG", 470 "MAC_HASH_TBL5_REG", 471 "MAC_HASH_TBL6_REG", 472 "MAC_HASH_TBL7_REG", 473 "MAC_HASH_TBL8_REG", 474 "MAC_HASH_TBL9_REG", 475 "MAC_HASH_TBL10_REG", 476 "MAC_HASH_TBL11_REG", 477 "MAC_HASH_TBL12_REG", 478 "MAC_HASH_TBL13_REG", 479 "MAC_HASH_TBL14_REG", 480 "MAC_HASH_TBL15_REG", 481 "RXMAC_FRM_CNT_REG", 482 "MAC_LEN_ER_CNT_REG", 483 "BMAC_AL_ER_CNT_REG", 484 "BMAC_CRC_ER_CNT_REG", 485 "BMAC_CD_VIO_CNT_REG", 486 "BMAC_SM_REG", 487 "BMAC_ALTAD_CMPEN_REG", 488 "BMAC_HOST_INF0_REG", 489 "BMAC_HOST_INF1_REG", 490 "BMAC_HOST_INF2_REG", 491 "BMAC_HOST_INF3_REG", 492 "BMAC_HOST_INF4_REG", 493 "BMAC_HOST_INF5_REG", 494 "BMAC_HOST_INF6_REG", 495 "BMAC_HOST_INF7_REG", 496 "BMAC_HOST_INF8_REG", 497 "BTXMAC_BYTE_CNT_REG", 498 "BTXMAC_FRM_CNT_REG", 499 "BRXMAC_BYTE_CNT_REG", 500 }; 501 502 npi_status_t 503 npi_mac_dump_regs(npi_handle_t handle, uint8_t port) 504 { 505 506 uint64_t value; 507 int num_regs, i; 508 509 ASSERT(IS_PORT_NUM_VALID(port)); 510 511 switch (port) { 512 case 0: 513 case 1: 514 num_regs = sizeof (xmac_offset) / sizeof (uint64_t); 515 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 516 "\nXMAC Register Dump for port %d\n", 517 port)); 518 for (i = 0; i < num_regs; i++) { 519 #if defined(__i386) 520 XMAC_REG_RD(handle, port, (uint32_t)xmac_offset[i], 521 &value); 522 #else 523 XMAC_REG_RD(handle, port, xmac_offset[i], &value); 524 #endif 525 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 526 "%08llx %s\t %08llx \n", 527 (XMAC_REG_ADDR((port), (xmac_offset[i]))), 528 xmac_name[i], value)); 529 } 530 531 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 532 "\n XMAC Register Dump for port %d done\n", 533 port)); 534 break; 535 536 case 2: 537 case 3: 538 num_regs = sizeof (bmac_offset) / sizeof (uint64_t); 539 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 540 "\nBMAC Register Dump for port %d\n", 541 port)); 542 for (i = 0; i < num_regs; i++) { 543 #if defined(__i386) 544 BMAC_REG_RD(handle, port, (uint32_t)bmac_offset[i], 545 &value); 546 #else 547 BMAC_REG_RD(handle, port, bmac_offset[i], &value); 548 #endif 549 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 550 "%08llx %s\t %08llx \n", 551 (BMAC_REG_ADDR((port), (bmac_offset[i]))), 552 bmac_name[i], value)); 553 } 554 555 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 556 "\n BMAC Register Dump for port %d done\n", 557 port)); 558 break; 559 } 560 561 return (NPI_SUCCESS); 562 } 563 564 npi_status_t 565 npi_mac_pcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 566 { 567 pcs_cfg_t pcs_cfg; 568 569 ASSERT(IS_PORT_NUM_VALID(portn)); 570 571 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.value); 572 pcs_cfg.bits.w0.mask = 0; 573 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.value); 574 575 return (NPI_SUCCESS); 576 } 577 578 npi_status_t 579 npi_mac_pcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 580 { 581 pcs_cfg_t pcs_cfg; 582 583 ASSERT(IS_PORT_NUM_VALID(portn)); 584 585 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.val.lsw); 586 pcs_cfg.bits.w0.mask = 1; 587 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.val.lsw); 588 589 return (NPI_SUCCESS); 590 } 591 592 npi_status_t 593 npi_xmac_xpcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 594 { 595 xpcs_stat1_t xpcs_mask1; 596 597 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 598 599 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 600 xpcs_mask1.bits.w0.csr_rx_link_stat = 1; 601 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 602 603 return (NPI_SUCCESS); 604 } 605 606 npi_status_t 607 npi_xmac_xpcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 608 { 609 xpcs_stat1_t xpcs_mask1; 610 611 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 612 613 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 614 xpcs_mask1.bits.w0.csr_rx_link_stat = 0; 615 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 616 617 return (NPI_SUCCESS); 618 } 619 620 npi_status_t 621 npi_mac_mif_link_intr_disable(npi_handle_t handle, uint8_t portn) 622 { 623 mif_cfg_t mif_cfg; 624 625 ASSERT(IS_PORT_NUM_VALID(portn)); 626 627 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.val.lsw); 628 629 mif_cfg.bits.w0.phy_addr = portn; 630 mif_cfg.bits.w0.poll_en = 0; 631 632 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.val.lsw); 633 634 NXGE_DELAY(20); 635 636 return (NPI_SUCCESS); 637 } 638 639 npi_status_t 640 npi_mac_hashtab_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 641 uint8_t entryn, uint16_t *data) 642 { 643 uint64_t val; 644 645 ASSERT((op == OP_GET) || (op == OP_SET)); 646 ASSERT(IS_PORT_NUM_VALID(portn)); 647 648 ASSERT(entryn < MAC_MAX_HASH_ENTRY); 649 if (entryn >= MAC_MAX_HASH_ENTRY) { 650 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 651 " npi_mac_hashtab_entry" 652 " Invalid Input: entryn <0x%x>", 653 entryn)); 654 return (NPI_FAILURE | NPI_MAC_HASHTAB_ENTRY_INVALID(portn)); 655 } 656 657 if (op == OP_SET) { 658 val = *data; 659 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 660 XMAC_REG_WR(handle, portn, 661 XMAC_HASH_TBLN_REG_ADDR(entryn), val); 662 } else { 663 BMAC_REG_WR(handle, portn, 664 BMAC_HASH_TBLN_REG_ADDR(entryn), val); 665 } 666 } else { 667 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 668 XMAC_REG_RD(handle, portn, 669 XMAC_HASH_TBLN_REG_ADDR(entryn), &val); 670 } else { 671 BMAC_REG_RD(handle, portn, 672 BMAC_HASH_TBLN_REG_ADDR(entryn), &val); 673 } 674 *data = val & 0xFFFF; 675 } 676 677 return (NPI_SUCCESS); 678 } 679 680 npi_status_t 681 npi_mac_hostinfo_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 682 uint8_t entryn, hostinfo_t *hostinfo) 683 { 684 ASSERT((op == OP_GET) || (op == OP_SET)); 685 ASSERT(IS_PORT_NUM_VALID(portn)); 686 687 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 688 ASSERT(entryn < XMAC_MAX_HOST_INFO_ENTRY); 689 if (entryn >= XMAC_MAX_HOST_INFO_ENTRY) { 690 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 691 " npi_mac_hostinfo_entry" 692 " Invalid Input: entryn <0x%x>", 693 entryn)); 694 return (NPI_FAILURE | 695 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 696 } 697 } else { 698 ASSERT(entryn < BMAC_MAX_HOST_INFO_ENTRY); 699 if (entryn >= BMAC_MAX_HOST_INFO_ENTRY) { 700 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 701 " npi_mac_hostinfo_entry" 702 " Invalid Input: entryn <0x%x>", 703 entryn)); 704 return (NPI_FAILURE | 705 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 706 } 707 } 708 709 if (op == OP_SET) { 710 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 711 XMAC_REG_WR(handle, portn, 712 XMAC_HOST_INFN_REG_ADDR(entryn), 713 hostinfo->value); 714 } else { 715 BMAC_REG_WR(handle, portn, 716 BMAC_HOST_INFN_REG_ADDR(entryn), 717 hostinfo->value); 718 } 719 } else { 720 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 721 XMAC_REG_RD(handle, portn, 722 XMAC_HOST_INFN_REG_ADDR(entryn), 723 &hostinfo->value); 724 } else { 725 BMAC_REG_RD(handle, portn, 726 BMAC_HOST_INFN_REG_ADDR(entryn), 727 &hostinfo->value); 728 } 729 } 730 731 return (NPI_SUCCESS); 732 } 733 734 npi_status_t 735 npi_mac_altaddr_enable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 736 { 737 uint64_t val; 738 739 ASSERT(IS_PORT_NUM_VALID(portn)); 740 741 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 742 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 743 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 744 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 745 " npi_mac_altaddr_enable" 746 " Invalid Input: addrn <0x%x>", 747 addrn)); 748 return (NPI_FAILURE | 749 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 750 } 751 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 752 val |= (1 << addrn); 753 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 754 } else { 755 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 756 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 757 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 758 " npi_mac_altaddr_enable" 759 " Invalid Input: addrn <0x%x>", 760 addrn)); 761 return (NPI_FAILURE | 762 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 763 } 764 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 765 val |= (1 << addrn); 766 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 767 } 768 769 return (NPI_SUCCESS); 770 } 771 772 /* 773 * While all bits of XMAC_ADDR_CMPEN_REG are for alternate MAC addresses, 774 * bit0 of BMAC_ALTAD_CMPEN_REG is for unique MAC address. 775 */ 776 npi_status_t 777 npi_mac_altaddr_disable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 778 { 779 uint64_t val; 780 781 ASSERT(IS_PORT_NUM_VALID(portn)); 782 783 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 784 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 785 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 786 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 787 " npi_mac_altaddr_disable" 788 " Invalid Input: addrn <0x%x>", 789 addrn)); 790 return (NPI_FAILURE | 791 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 792 } 793 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 794 val &= ~(1 << addrn); 795 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 796 } else { 797 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 798 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 799 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 800 " npi_mac_altaddr_disable" 801 " Invalid Input: addrn <0x%x>", 802 addrn)); 803 return (NPI_FAILURE | 804 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 805 } 806 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 807 val &= ~(1 << addrn); 808 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 809 } 810 811 return (NPI_SUCCESS); 812 } 813 814 npi_status_t 815 npi_mac_altaddr_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 816 uint8_t entryn, npi_mac_addr_t *data) 817 { 818 uint64_t val0, val1, val2; 819 820 ASSERT(IS_PORT_NUM_VALID(portn)); 821 ASSERT((op == OP_GET) || (op == OP_SET)); 822 823 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 824 ASSERT(entryn <= XMAC_MAX_ALT_ADDR_ENTRY); 825 if (entryn > XMAC_MAX_ALT_ADDR_ENTRY) { 826 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 827 " npi_mac_altaddr_entry" 828 " Invalid Input: entryn <0x%x>", 829 entryn)); 830 return (NPI_FAILURE | 831 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 832 } 833 if (op == OP_SET) { 834 val0 = data->w0; 835 val1 = data->w1; 836 val2 = data->w2; 837 XMAC_REG_WR(handle, portn, 838 XMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 839 XMAC_REG_WR(handle, portn, 840 XMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 841 XMAC_REG_WR(handle, portn, 842 XMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 843 } else { 844 XMAC_REG_RD(handle, portn, 845 XMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 846 XMAC_REG_RD(handle, portn, 847 XMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 848 XMAC_REG_RD(handle, portn, 849 XMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 850 data->w0 = val0 & 0xFFFF; 851 data->w1 = val1 & 0xFFFF; 852 data->w2 = val2 & 0xFFFF; 853 } 854 } else { 855 ASSERT(entryn <= BMAC_MAX_ALT_ADDR_ENTRY); 856 if (entryn > BMAC_MAX_ALT_ADDR_ENTRY) { 857 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 858 " npi_mac_altaddr_entry" 859 " Invalid Input: entryn <0x%x>", 860 entryn)); 861 return (NPI_FAILURE | 862 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 863 } 864 if (op == OP_SET) { 865 val0 = data->w0; 866 val1 = data->w1; 867 val2 = data->w2; 868 BMAC_REG_WR(handle, portn, 869 BMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 870 BMAC_REG_WR(handle, portn, 871 BMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 872 BMAC_REG_WR(handle, portn, 873 BMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 874 } else { 875 BMAC_REG_RD(handle, portn, 876 BMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 877 BMAC_REG_RD(handle, portn, 878 BMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 879 BMAC_REG_RD(handle, portn, 880 BMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 881 data->w0 = val0 & 0xFFFF; 882 data->w1 = val1 & 0xFFFF; 883 data->w2 = val2 & 0xFFFF; 884 } 885 } 886 887 return (NPI_SUCCESS); 888 } 889 890 npi_status_t 891 npi_mac_port_attr(npi_handle_t handle, io_op_t op, uint8_t portn, 892 npi_attr_t *attrp) 893 { 894 uint64_t val = 0; 895 uint32_t attr; 896 897 ASSERT(IS_PORT_NUM_VALID(portn)); 898 ASSERT((op == OP_GET) || (op == OP_SET)); 899 900 switch (attrp->type) { 901 case MAC_PORT_MODE: 902 switch (portn) { 903 case XMAC_PORT_0: 904 case XMAC_PORT_1: 905 if (op == OP_SET) { 906 attr = attrp->idata[0]; 907 ASSERT((attr == MAC_MII_MODE) || \ 908 (attr == MAC_GMII_MODE) || \ 909 (attr == MAC_XGMII_MODE)); 910 if ((attr != MAC_MII_MODE) && 911 (attr != MAC_GMII_MODE) && 912 (attr != MAC_XGMII_MODE)) { 913 NPI_ERROR_MSG((handle.function, 914 NPI_ERR_CTL, 915 " npi_mac_port_attr" 916 " Invalid Input:" 917 " MAC_PORT_MODE <0x%x>", 918 attr)); 919 return (NPI_FAILURE | 920 NPI_MAC_PORT_ATTR_INVALID(portn)); 921 } 922 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 923 &val); 924 val &= ~XMAC_XIF_MII_MODE_MASK; 925 switch (attr) { 926 case MAC_MII_MODE: 927 val |= (XMAC_XIF_MII_MODE << 928 XMAC_XIF_MII_MODE_SHIFT); 929 break; 930 case MAC_GMII_MODE: 931 val |= (XMAC_XIF_GMII_MODE << 932 XMAC_XIF_MII_MODE_SHIFT); 933 break; 934 case MAC_XGMII_MODE: 935 val |= (XMAC_XIF_XGMII_MODE << 936 XMAC_XIF_MII_MODE_SHIFT); 937 break; 938 default: 939 return (NPI_FAILURE | 940 NPI_MAC_PORT_ATTR_INVALID(portn)); 941 } 942 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, 943 val); 944 } else { 945 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 946 &val); 947 val &= XMAC_XIF_MII_MODE_MASK; 948 attr = val >> XMAC_XIF_MII_MODE_SHIFT; 949 attrp->odata[0] = attr; 950 } 951 break; 952 case BMAC_PORT_0: 953 case BMAC_PORT_1: 954 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 955 " npi_mac_port_attr" 956 " Invalid Input:" 957 " MAC_PORT_MODE <0x%x>", 958 attrp->type)); 959 return (NPI_FAILURE | 960 NPI_MAC_PORT_ATTR_INVALID(portn)); 961 default: 962 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 963 } 964 break; 965 966 case MAC_PORT_FRAME_SIZE: { 967 uint32_t min_fsize; 968 uint32_t max_fsize; 969 970 switch (portn) { 971 case XMAC_PORT_0: 972 case XMAC_PORT_1: 973 if (op == OP_SET) { 974 min_fsize = attrp->idata[0]; 975 max_fsize = attrp->idata[1]; 976 ASSERT((min_fsize & \ 977 ~XMAC_MIN_TX_FRM_SZ_MASK) == 0); 978 if ((min_fsize & ~XMAC_MIN_TX_FRM_SZ_MASK) 979 != 0) { 980 NPI_ERROR_MSG((handle.function, 981 NPI_ERR_CTL, 982 " npi_mac_port_attr" 983 " MAC_PORT_FRAME_SIZE:" 984 " Invalid Input:" 985 " xmac_min_fsize <0x%x>", 986 min_fsize)); 987 return (NPI_FAILURE | 988 NPI_MAC_PORT_ATTR_INVALID(portn)); 989 } 990 ASSERT((max_fsize & \ 991 ~XMAC_MAX_FRM_SZ_MASK) == 0); 992 if ((max_fsize & ~XMAC_MAX_FRM_SZ_MASK) 993 != 0) { 994 NPI_ERROR_MSG((handle.function, 995 NPI_ERR_CTL, 996 " npi_mac_port_attr" 997 " MAC_PORT_FRAME_SIZE:" 998 " Invalid Input:" 999 " xmac_max_fsize <0x%x>", 1000 max_fsize)); 1001 return (NPI_FAILURE | 1002 NPI_MAC_PORT_ATTR_INVALID(portn)); 1003 } 1004 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1005 val &= ~(XMAC_MIN_TX_FRM_SZ_MASK | 1006 XMAC_MIN_RX_FRM_SZ_MASK); 1007 val |= (min_fsize << XMAC_MIN_TX_FRM_SZ_SHIFT); 1008 val |= (min_fsize << XMAC_MIN_RX_FRM_SZ_SHIFT); 1009 XMAC_REG_WR(handle, portn, XMAC_MIN_REG, val); 1010 XMAC_REG_WR(handle, portn, XMAC_MAX_REG, 1011 max_fsize); 1012 } else { 1013 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1014 min_fsize = (val & XMAC_MIN_TX_FRM_SZ_MASK) 1015 >> XMAC_MIN_TX_FRM_SZ_SHIFT; 1016 XMAC_REG_RD(handle, portn, XMAC_MAX_REG, &val); 1017 attrp->odata[0] = min_fsize; 1018 attrp->odata[1] = max_fsize; 1019 } 1020 break; 1021 case BMAC_PORT_0: 1022 case BMAC_PORT_1: 1023 if (op == OP_SET) { 1024 min_fsize = attrp->idata[0]; 1025 max_fsize = attrp->idata[1]; 1026 ASSERT((min_fsize & ~BMAC_MIN_FRAME_MASK) == 0); 1027 if ((min_fsize & ~BMAC_MIN_FRAME_MASK) 1028 != 0) { 1029 NPI_ERROR_MSG((handle.function, 1030 NPI_ERR_CTL, 1031 " npi_mac_port_attr" 1032 " MAC_FRAME_SIZE:" 1033 " Invalid Input:" 1034 " bmac_min_fsize <0x%x>", 1035 min_fsize)); 1036 return (NPI_FAILURE | 1037 NPI_MAC_PORT_ATTR_INVALID(portn)); 1038 } 1039 ASSERT((max_fsize & ~BMAC_MAX_FRAME_MASK) == 0); 1040 if ((max_fsize & ~BMAC_MAX_FRAME_MASK) 1041 != 0) { 1042 NPI_ERROR_MSG((handle.function, 1043 NPI_ERR_CTL, 1044 " npi_mac_port_attr" 1045 " MAC_FRAME_SIZE:" 1046 " Invalid Input:" 1047 " bmac_max_fsize <0x%x>", 1048 max_fsize)); 1049 return (NPI_FAILURE | 1050 NPI_MAC_PORT_ATTR_INVALID(portn)); 1051 } 1052 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1053 val &= ~BMAC_MAX_FRAME_MASK; 1054 if (max_fsize <= MAX_FRAME_SZ1) 1055 val |= MAX_FRAME_SZ1; 1056 else if ((max_fsize > MAX_FRAME_SZ1) && 1057 (max_fsize <= MAX_FRAME_SZ2)) 1058 val |= MAX_FRAME_SZ2; 1059 else if ((max_fsize > MAX_FRAME_SZ2) && 1060 (max_fsize <= MAX_FRAME_SZ3)) 1061 val |= MAX_FRAME_SZ3; 1062 else if ((max_fsize > MAX_FRAME_SZ3) && 1063 (max_fsize <= MAX_FRAME_SZ4)) 1064 val |= MAX_FRAME_SZ4; 1065 else if ((max_fsize > MAX_FRAME_SZ4) && 1066 (max_fsize <= MAX_FRAME_SZ5)) 1067 val |= MAX_FRAME_SZ5; 1068 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1069 BMAC_REG_WR(handle, portn, BMAC_MIN_REG, 1070 min_fsize); 1071 } else { 1072 BMAC_REG_RD(handle, portn, BMAC_MIN_REG, &val); 1073 min_fsize = val & BMAC_MIN_FRAME_MASK; 1074 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1075 max_fsize = val & BMAC_MAX_FRAME_MASK; 1076 attrp->odata[0] = min_fsize; 1077 attrp->odata[1] = max_fsize; 1078 } 1079 break; 1080 default: 1081 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1082 } 1083 break; 1084 } 1085 1086 case BMAC_PORT_MAX_BURST_SIZE: { 1087 uint32_t burst_size; 1088 switch (portn) { 1089 case XMAC_PORT_0: 1090 case XMAC_PORT_1: 1091 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1092 " npi_mac_port_attr" 1093 " BMAC_PORT_MAX_BURST_SIZE:" 1094 " Invalid Input: portn <%d>", 1095 portn)); 1096 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1097 case BMAC_PORT_0: 1098 case BMAC_PORT_1: 1099 /* NOTE: Not used in Full duplex mode */ 1100 if (op == OP_SET) { 1101 burst_size = attrp->idata[0]; 1102 ASSERT((burst_size & ~0x7FFF) == 0); 1103 if ((burst_size & ~0x7FFF) != 0) { 1104 NPI_ERROR_MSG((handle.function, 1105 NPI_ERR_CTL, 1106 " npi_mac_port_attr" 1107 " BMAC_MAX_BURST_SIZE:" 1108 " Invalid Input:" 1109 " burst_size <0x%x>", 1110 burst_size)); 1111 return (NPI_FAILURE | 1112 NPI_MAC_PORT_ATTR_INVALID(portn)); 1113 } 1114 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1115 val &= ~BMAC_MAX_BURST_MASK; 1116 val |= (burst_size << BMAC_MAX_BURST_SHIFT); 1117 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1118 } else { 1119 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1120 burst_size = (val & BMAC_MAX_BURST_MASK) 1121 >> BMAC_MAX_BURST_SHIFT; 1122 attrp->odata[0] = burst_size; 1123 } 1124 break; 1125 default: 1126 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1127 } 1128 break; 1129 } 1130 1131 case BMAC_PORT_PA_SIZE: { 1132 uint32_t pa_size; 1133 switch (portn) { 1134 case XMAC_PORT_0: 1135 case XMAC_PORT_1: 1136 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1137 " npi_mac_port_attr" 1138 " BMAC_PORT_PA_SIZE:" 1139 " Invalid Input: portn <%d>", 1140 portn)); 1141 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1142 case BMAC_PORT_0: 1143 case BMAC_PORT_1: 1144 if (op == OP_SET) { 1145 pa_size = attrp->idata[0]; 1146 ASSERT((pa_size & ~0x3FF) == 0); 1147 if ((pa_size & ~0x3FF) != 0) { 1148 NPI_ERROR_MSG((handle.function, 1149 NPI_ERR_CTL, 1150 " npi_mac_port_attr" 1151 " BMAC_PORT_PA_SIZE:" 1152 " Invalid Input: pa_size <0x%x>", 1153 pa_size)); 1154 1155 return (NPI_FAILURE | 1156 NPI_MAC_PORT_ATTR_INVALID(portn)); 1157 } 1158 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1159 &val); 1160 val &= ~BMAC_PA_SIZE_MASK; 1161 val |= (pa_size << 0); 1162 BMAC_REG_WR(handle, portn, MAC_PA_SIZE_REG, 1163 val); 1164 } else { 1165 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1166 &val); 1167 pa_size = (val & BMAC_PA_SIZE_MASK) >> 0; 1168 attrp->odata[0] = pa_size; 1169 } 1170 break; 1171 default: 1172 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1173 } 1174 break; 1175 } 1176 1177 case BMAC_PORT_CTRL_TYPE: { 1178 uint32_t ctrl_type; 1179 switch (portn) { 1180 case XMAC_PORT_0: 1181 case XMAC_PORT_1: 1182 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1183 " npi_mac_port_attr" 1184 " BMAC_PORT_CTRL_TYPE:" 1185 " Invalid Input: portn <%d>", 1186 portn)); 1187 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1188 case BMAC_PORT_0: 1189 case BMAC_PORT_1: 1190 if (op == OP_SET) { 1191 ctrl_type = attrp->idata[0]; 1192 ASSERT((ctrl_type & ~0xFFFF) == 0); 1193 if ((ctrl_type & ~0xFFFF) != 0) { 1194 NPI_ERROR_MSG((handle.function, 1195 NPI_ERR_CTL, 1196 " npi_mac_port_attr" 1197 " BMAC_PORT_CTRL_TYPE:" 1198 " Invalid Input:" 1199 " ctrl_type <0x%x>", 1200 ctrl_type)); 1201 return (NPI_FAILURE | 1202 NPI_MAC_PORT_ATTR_INVALID(portn)); 1203 } 1204 BMAC_REG_WR(handle, portn, MAC_CTRL_TYPE_REG, 1205 val); 1206 } else { 1207 BMAC_REG_RD(handle, portn, MAC_CTRL_TYPE_REG, 1208 &val); 1209 ctrl_type = (val & 0xFFFF); 1210 attrp->odata[0] = ctrl_type; 1211 } 1212 break; 1213 default: 1214 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1215 } 1216 break; 1217 } 1218 1219 case XMAC_10G_PORT_IPG: 1220 { 1221 uint32_t ipg0; 1222 1223 switch (portn) { 1224 case XMAC_PORT_0: 1225 case XMAC_PORT_1: 1226 if (op == OP_SET) { 1227 ipg0 = attrp->idata[0]; 1228 ASSERT((ipg0 == XGMII_IPG_12_15) || \ 1229 (ipg0 == XGMII_IPG_16_19) || \ 1230 (ipg0 == XGMII_IPG_20_23)); 1231 if ((ipg0 != XGMII_IPG_12_15) && 1232 (ipg0 != XGMII_IPG_16_19) && 1233 (ipg0 != XGMII_IPG_20_23)) { 1234 NPI_ERROR_MSG((handle.function, 1235 NPI_ERR_CTL, 1236 " npi_mac_port_attr" 1237 " MAC_10G_PORT_IPG:" 1238 " Invalid Input:" 1239 " xgmii_ipg <0x%x>", 1240 ipg0)); 1241 return (NPI_FAILURE | 1242 NPI_MAC_PORT_ATTR_INVALID(portn)); 1243 } 1244 1245 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1246 val &= ~(XMAC_IPG_VALUE_MASK | 1247 XMAC_IPG_VALUE1_MASK); 1248 1249 switch (ipg0) { 1250 case XGMII_IPG_12_15: 1251 val |= (IPG_12_15_BYTE << 1252 XMAC_IPG_VALUE_SHIFT); 1253 break; 1254 case XGMII_IPG_16_19: 1255 val |= (IPG_16_19_BYTE << 1256 XMAC_IPG_VALUE_SHIFT); 1257 break; 1258 case XGMII_IPG_20_23: 1259 val |= (IPG_20_23_BYTE << 1260 XMAC_IPG_VALUE_SHIFT); 1261 break; 1262 default: 1263 return (NPI_FAILURE | 1264 NPI_MAC_PORT_ATTR_INVALID(portn)); 1265 } 1266 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1267 } else { 1268 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1269 ipg0 = (val & XMAC_IPG_VALUE_MASK) >> 1270 XMAC_IPG_VALUE_SHIFT; 1271 switch (ipg0) { 1272 case IPG_12_15_BYTE: 1273 attrp->odata[0] = XGMII_IPG_12_15; 1274 break; 1275 case IPG_16_19_BYTE: 1276 attrp->odata[0] = XGMII_IPG_16_19; 1277 break; 1278 case IPG_20_23_BYTE: 1279 attrp->odata[0] = XGMII_IPG_20_23; 1280 break; 1281 default: 1282 return (NPI_FAILURE | 1283 NPI_MAC_PORT_ATTR_INVALID(portn)); 1284 } 1285 } 1286 break; 1287 case BMAC_PORT_0: 1288 case BMAC_PORT_1: 1289 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1290 " npi_mac_port_attr" "MAC_PORT_IPG:" 1291 " Invalid Input: portn <%d>", 1292 portn)); 1293 /* FALLTHROUGH */ 1294 default: 1295 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1296 } 1297 break; 1298 } 1299 1300 case XMAC_PORT_IPG: 1301 { 1302 uint32_t ipg1; 1303 switch (portn) { 1304 case XMAC_PORT_0: 1305 case XMAC_PORT_1: 1306 if (op == OP_SET) { 1307 ipg1 = attrp->idata[0]; 1308 ASSERT((ipg1 == MII_GMII_IPG_12) || \ 1309 (ipg1 == MII_GMII_IPG_13) || \ 1310 (ipg1 == MII_GMII_IPG_14) || \ 1311 (ipg1 == MII_GMII_IPG_15) || \ 1312 (ipg1 == MII_GMII_IPG_16)); 1313 if ((ipg1 != MII_GMII_IPG_12) && 1314 (ipg1 != MII_GMII_IPG_13) && 1315 (ipg1 != MII_GMII_IPG_14) && 1316 (ipg1 != MII_GMII_IPG_15) && 1317 (ipg1 != MII_GMII_IPG_16)) { 1318 NPI_ERROR_MSG((handle.function, 1319 NPI_ERR_CTL, 1320 " npi_mac_port_attr" 1321 " XMAC_PORT_IPG:" 1322 " Invalid Input:" 1323 " mii_gmii_ipg <0x%x>", 1324 ipg1)); 1325 return (NPI_FAILURE | 1326 NPI_MAC_PORT_ATTR_INVALID(portn)); 1327 } 1328 1329 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1330 val &= ~(XMAC_IPG_VALUE_MASK | 1331 XMAC_IPG_VALUE1_MASK); 1332 1333 switch (ipg1) { 1334 case MII_GMII_IPG_12: 1335 val |= (IPG1_12_BYTES << 1336 XMAC_IPG_VALUE1_SHIFT); 1337 break; 1338 case MII_GMII_IPG_13: 1339 val |= (IPG1_13_BYTES << 1340 XMAC_IPG_VALUE1_SHIFT); 1341 break; 1342 case MII_GMII_IPG_14: 1343 val |= (IPG1_14_BYTES << 1344 XMAC_IPG_VALUE1_SHIFT); 1345 break; 1346 case MII_GMII_IPG_15: 1347 val |= (IPG1_15_BYTES << 1348 XMAC_IPG_VALUE1_SHIFT); 1349 break; 1350 case MII_GMII_IPG_16: 1351 val |= (IPG1_16_BYTES << 1352 XMAC_IPG_VALUE1_SHIFT); 1353 break; 1354 default: 1355 return (NPI_FAILURE | 1356 NPI_MAC_PORT_ATTR_INVALID(portn)); 1357 } 1358 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1359 } else { 1360 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1361 ipg1 = (val & XMAC_IPG_VALUE1_MASK) >> 1362 XMAC_IPG_VALUE1_SHIFT; 1363 switch (ipg1) { 1364 case IPG1_12_BYTES: 1365 attrp->odata[1] = MII_GMII_IPG_12; 1366 break; 1367 case IPG1_13_BYTES: 1368 attrp->odata[1] = MII_GMII_IPG_13; 1369 break; 1370 case IPG1_14_BYTES: 1371 attrp->odata[1] = MII_GMII_IPG_14; 1372 break; 1373 case IPG1_15_BYTES: 1374 attrp->odata[1] = MII_GMII_IPG_15; 1375 break; 1376 case IPG1_16_BYTES: 1377 attrp->odata[1] = MII_GMII_IPG_16; 1378 break; 1379 default: 1380 return (NPI_FAILURE | 1381 NPI_MAC_PORT_ATTR_INVALID(portn)); 1382 } 1383 } 1384 break; 1385 case BMAC_PORT_0: 1386 case BMAC_PORT_1: 1387 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1388 " npi_mac_port_attr" 1389 " MAC_PORT_IPG:" 1390 " Invalid Input: portn <%d>", 1391 portn)); 1392 /* FALLTHROUGH */ 1393 default: 1394 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1395 } 1396 break; 1397 } 1398 1399 case MAC_PORT_ADDR: { 1400 uint32_t addr0; 1401 uint32_t addr1; 1402 uint32_t addr2; 1403 1404 switch (portn) { 1405 case XMAC_PORT_0: 1406 case XMAC_PORT_1: 1407 if (op == OP_SET) { 1408 addr0 = attrp->idata[0]; 1409 addr1 = attrp->idata[1]; 1410 addr2 = attrp->idata[2]; 1411 ASSERT((addr0 & ~0xFFFF) == 0); 1412 if ((addr0 & ~0xFFFF) != 0) { 1413 NPI_ERROR_MSG((handle.function, 1414 NPI_ERR_CTL, 1415 " npi_mac_port_attr" 1416 " MAC_PORT_ADDR:" 1417 " Invalid Input:" 1418 " addr0 <0x%x>", addr0)); 1419 1420 return (NPI_FAILURE | 1421 NPI_MAC_PORT_ATTR_INVALID(portn)); 1422 } 1423 ASSERT((addr1 & ~0xFFFF) == 0); 1424 if ((addr1 & ~0xFFFF) != 0) { 1425 NPI_ERROR_MSG((handle.function, 1426 NPI_ERR_CTL, 1427 " npi_mac_port_attr" 1428 " MAC_PORT_ADDR:" 1429 " Invalid Input:" 1430 " addr1 <0x%x>", addr1)); 1431 return (NPI_FAILURE | 1432 NPI_MAC_PORT_ATTR_INVALID(portn)); 1433 } 1434 ASSERT((addr2 & ~0xFFFF) == 0); 1435 if ((addr2 & ~0xFFFF) != 0) { 1436 NPI_ERROR_MSG((handle.function, 1437 NPI_ERR_CTL, 1438 " npi_mac_port_attr" 1439 " MAC_PORT_ADDR:" 1440 " Invalid Input:" 1441 " addr2 <0x%x.", 1442 addr2)); 1443 1444 return (NPI_FAILURE | 1445 NPI_MAC_PORT_ATTR_INVALID(portn)); 1446 } 1447 XMAC_REG_WR(handle, portn, XMAC_ADDR0_REG, 1448 addr0); 1449 XMAC_REG_WR(handle, portn, XMAC_ADDR1_REG, 1450 addr1); 1451 XMAC_REG_WR(handle, portn, XMAC_ADDR2_REG, 1452 addr2); 1453 } else { 1454 XMAC_REG_RD(handle, portn, XMAC_ADDR0_REG, 1455 &addr0); 1456 XMAC_REG_RD(handle, portn, XMAC_ADDR1_REG, 1457 &addr1); 1458 XMAC_REG_RD(handle, portn, XMAC_ADDR2_REG, 1459 &addr2); 1460 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1461 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1462 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1463 } 1464 break; 1465 case BMAC_PORT_0: 1466 case BMAC_PORT_1: 1467 if (op == OP_SET) { 1468 addr0 = attrp->idata[0]; 1469 addr1 = attrp->idata[1]; 1470 addr2 = attrp->idata[2]; 1471 ASSERT((addr0 & ~0xFFFF) == 0); 1472 if ((addr0 & ~0xFFFF) != 0) { 1473 NPI_ERROR_MSG((handle.function, 1474 NPI_ERR_CTL, 1475 " npi_mac_port_attr" 1476 " MAC_PORT_ADDR:" 1477 " Invalid Input:" 1478 " addr0 <0x%x>", 1479 addr0)); 1480 return (NPI_FAILURE | 1481 NPI_MAC_PORT_ATTR_INVALID(portn)); 1482 } 1483 ASSERT((addr1 & ~0xFFFF) == 0); 1484 if ((addr1 & ~0xFFFF) != 0) { 1485 NPI_ERROR_MSG((handle.function, 1486 NPI_ERR_CTL, 1487 " npi_mac_port_attr" 1488 " MAC_PORT_ADDR:" 1489 " Invalid Input:" 1490 " addr1 <0x%x>", 1491 addr1)); 1492 return (NPI_FAILURE | 1493 NPI_MAC_PORT_ATTR_INVALID(portn)); 1494 } 1495 ASSERT((addr2 & ~0xFFFF) == 0); 1496 if ((addr2 & ~0xFFFF) != 0) { 1497 NPI_ERROR_MSG((handle.function, 1498 NPI_ERR_CTL, 1499 " npi_mac_port_attr" 1500 " MAC_PORT_ADDR:" 1501 " Invalid Input:" 1502 " addr2 <0x%x>", 1503 addr2)); 1504 return (NPI_FAILURE | 1505 NPI_MAC_PORT_ATTR_INVALID(portn)); 1506 } 1507 BMAC_REG_WR(handle, portn, BMAC_ADDR0_REG, 1508 addr0); 1509 BMAC_REG_WR(handle, portn, BMAC_ADDR1_REG, 1510 addr1); 1511 BMAC_REG_WR(handle, portn, BMAC_ADDR2_REG, 1512 addr2); 1513 } else { 1514 BMAC_REG_RD(handle, portn, BMAC_ADDR0_REG, 1515 &addr0); 1516 BMAC_REG_RD(handle, portn, BMAC_ADDR1_REG, 1517 &addr1); 1518 BMAC_REG_RD(handle, portn, BMAC_ADDR2_REG, 1519 &addr2); 1520 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1521 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1522 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1523 } 1524 break; 1525 default: 1526 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1527 } 1528 break; 1529 } 1530 1531 case MAC_PORT_ADDR_FILTER: { 1532 uint32_t addr0; 1533 uint32_t addr1; 1534 uint32_t addr2; 1535 1536 switch (portn) { 1537 case XMAC_PORT_0: 1538 case XMAC_PORT_1: 1539 if (op == OP_SET) { 1540 addr0 = attrp->idata[0]; 1541 addr1 = attrp->idata[1]; 1542 addr2 = attrp->idata[2]; 1543 ASSERT((addr0 & ~0xFFFF) == 0); 1544 if ((addr0 & ~0xFFFF) != 0) { 1545 NPI_ERROR_MSG((handle.function, 1546 NPI_ERR_CTL, 1547 " npi_mac_port_attr" 1548 " MAC_PORT_ADDR_FILTER:" 1549 " Invalid Input:" 1550 " addr0 <0x%x>", 1551 addr0)); 1552 return (NPI_FAILURE | 1553 NPI_MAC_PORT_ATTR_INVALID(portn)); 1554 } 1555 ASSERT((addr1 & ~0xFFFF) == 0); 1556 if ((addr1 & ~0xFFFF) != 0) { 1557 NPI_ERROR_MSG((handle.function, 1558 NPI_ERR_CTL, 1559 " npi_mac_port_attr" 1560 " MAC_PORT_ADDR_FILTER:" 1561 " Invalid Input:" 1562 " addr1 <0x%x>", 1563 addr1)); 1564 return (NPI_FAILURE | 1565 NPI_MAC_PORT_ATTR_INVALID(portn)); 1566 } 1567 ASSERT((addr2 & ~0xFFFF) == 0); 1568 if ((addr2 & ~0xFFFF) != 0) { 1569 NPI_ERROR_MSG((handle.function, 1570 NPI_ERR_CTL, 1571 " npi_mac_port_attr" 1572 " MAC_PORT_ADDR_FILTER:" 1573 " Invalid Input:" 1574 " addr2 <0x%x>", 1575 addr2)); 1576 return (NPI_FAILURE | 1577 NPI_MAC_PORT_ATTR_INVALID(portn)); 1578 } 1579 XMAC_REG_WR(handle, portn, 1580 XMAC_ADDR_FILT0_REG, addr0); 1581 XMAC_REG_WR(handle, portn, 1582 XMAC_ADDR_FILT1_REG, addr1); 1583 XMAC_REG_WR(handle, portn, 1584 XMAC_ADDR_FILT2_REG, addr2); 1585 } else { 1586 XMAC_REG_RD(handle, portn, 1587 XMAC_ADDR_FILT0_REG, &addr0); 1588 XMAC_REG_RD(handle, portn, 1589 XMAC_ADDR_FILT1_REG, &addr1); 1590 XMAC_REG_RD(handle, portn, 1591 XMAC_ADDR_FILT2_REG, &addr2); 1592 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1593 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1594 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1595 } 1596 break; 1597 case BMAC_PORT_0: 1598 case BMAC_PORT_1: 1599 if (op == OP_SET) { 1600 addr0 = attrp->idata[0]; 1601 addr1 = attrp->idata[1]; 1602 addr2 = attrp->idata[2]; 1603 ASSERT((addr0 & ~0xFFFF) == 0); 1604 if ((addr0 & ~0xFFFF) != 0) { 1605 NPI_ERROR_MSG((handle.function, 1606 NPI_ERR_CTL, 1607 " npi_mac_port_attr" 1608 " MAC_PORT_ADDR_FILTER:" 1609 " addr0", 1610 addr0)); 1611 return (NPI_FAILURE | 1612 NPI_MAC_PORT_ATTR_INVALID(portn)); 1613 } 1614 ASSERT((addr1 & ~0xFFFF) == 0); 1615 if ((addr1 & ~0xFFFF) != 0) { 1616 NPI_ERROR_MSG((handle.function, 1617 NPI_ERR_CTL, 1618 " npi_mac_port_attr" 1619 " MAC_PORT_ADDR_FILTER:" 1620 " Invalid Input:" 1621 " addr1 <0x%x>", 1622 addr1)); 1623 return (NPI_FAILURE | 1624 NPI_MAC_PORT_ATTR_INVALID(portn)); 1625 } 1626 ASSERT((addr2 & ~0xFFFF) == 0); 1627 if ((addr2 & ~0xFFFF) != 0) { 1628 NPI_ERROR_MSG((handle.function, 1629 NPI_ERR_CTL, 1630 " npi_mac_port_attr" 1631 " MAC_PORT_ADDR_FILTER:" 1632 " Invalid Input:" 1633 " addr2 <0x%x>", 1634 addr2)); 1635 return (NPI_FAILURE | 1636 NPI_MAC_PORT_ATTR_INVALID(portn)); 1637 } 1638 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT0_REG, 1639 addr0); 1640 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT1_REG, 1641 addr1); 1642 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT2_REG, 1643 addr2); 1644 } else { 1645 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT0_REG, 1646 &addr0); 1647 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT1_REG, 1648 &addr1); 1649 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT2_REG, 1650 &addr2); 1651 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1652 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1653 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1654 } 1655 break; 1656 default: 1657 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1658 } 1659 break; 1660 } 1661 1662 case MAC_PORT_ADDR_FILTER_MASK: { 1663 uint32_t mask_1_2; 1664 uint32_t mask_0; 1665 1666 switch (portn) { 1667 case XMAC_PORT_0: 1668 case XMAC_PORT_1: 1669 if (op == OP_SET) { 1670 mask_0 = attrp->idata[0]; 1671 mask_1_2 = attrp->idata[1]; 1672 ASSERT((mask_0 & ~0xFFFF) == 0); 1673 if ((mask_0 & ~0xFFFF) != 0) { 1674 NPI_ERROR_MSG((handle.function, 1675 NPI_ERR_CTL, 1676 " npi_mac_port_attr" 1677 " MAC_ADDR_FILTER_MASK:" 1678 " Invalid Input:" 1679 " mask_0 <0x%x>", 1680 mask_0)); 1681 return (NPI_FAILURE | 1682 NPI_MAC_PORT_ATTR_INVALID(portn)); 1683 } 1684 ASSERT((mask_1_2 & ~0xFF) == 0); 1685 if ((mask_1_2 & ~0xFF) != 0) { 1686 NPI_ERROR_MSG((handle.function, 1687 NPI_ERR_CTL, 1688 " npi_mac_port_attr" 1689 " MAC_ADDR_FILTER_MASK:" 1690 " Invalid Input:" 1691 " mask_1_2 <0x%x>", 1692 mask_1_2)); 1693 return (NPI_FAILURE | 1694 NPI_MAC_PORT_ATTR_INVALID(portn)); 1695 } 1696 XMAC_REG_WR(handle, portn, 1697 XMAC_ADDR_FILT0_MASK_REG, mask_0); 1698 XMAC_REG_WR(handle, portn, 1699 XMAC_ADDR_FILT12_MASK_REG, mask_1_2); 1700 } else { 1701 XMAC_REG_RD(handle, portn, 1702 XMAC_ADDR_FILT0_MASK_REG, &mask_0); 1703 XMAC_REG_RD(handle, portn, 1704 XMAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1705 attrp->odata[0] = mask_0 & 0xFFFF; 1706 attrp->odata[1] = mask_1_2 & 0xFF; 1707 } 1708 break; 1709 case BMAC_PORT_0: 1710 case BMAC_PORT_1: 1711 if (op == OP_SET) { 1712 mask_0 = attrp->idata[0]; 1713 mask_1_2 = attrp->idata[1]; 1714 BMAC_REG_WR(handle, portn, 1715 MAC_ADDR_FILT00_MASK_REG, mask_0); 1716 BMAC_REG_WR(handle, portn, 1717 MAC_ADDR_FILT12_MASK_REG, mask_1_2); 1718 } else { 1719 BMAC_REG_RD(handle, portn, 1720 MAC_ADDR_FILT00_MASK_REG, &mask_0); 1721 BMAC_REG_RD(handle, portn, 1722 MAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1723 attrp->odata[0] = mask_0; 1724 attrp->odata[1] = mask_1_2; 1725 } 1726 break; 1727 default: 1728 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1729 } 1730 break; 1731 } 1732 1733 default: 1734 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1735 " npi_mac_port_attr" 1736 " Invalid Input:" 1737 " attr <0x%x>", attrp->type)); 1738 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1739 } 1740 1741 return (NPI_SUCCESS); 1742 } 1743 1744 npi_status_t 1745 npi_xmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 1746 { 1747 uint64_t val; 1748 boolean_t txmac = B_FALSE; 1749 1750 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1751 1752 switch (mode) { 1753 case XTX_MAC_REG_RESET: 1754 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_REG_RST); 1755 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1756 txmac = B_TRUE; 1757 break; 1758 case XRX_MAC_REG_RESET: 1759 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_REG_RST); 1760 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1761 break; 1762 case XTX_MAC_LOGIC_RESET: 1763 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_SOFT_RST); 1764 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1765 txmac = B_TRUE; 1766 break; 1767 case XRX_MAC_LOGIC_RESET: 1768 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_SOFT_RST); 1769 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1770 break; 1771 case XTX_MAC_RESET_ALL: 1772 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, 1773 XTXMAC_SOFT_RST | XTXMAC_REG_RST); 1774 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1775 txmac = B_TRUE; 1776 break; 1777 case XRX_MAC_RESET_ALL: 1778 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, 1779 XRXMAC_SOFT_RST | XRXMAC_REG_RST); 1780 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1781 break; 1782 default: 1783 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1784 " npi_mac_reset" 1785 " Invalid Input: mode <0x%x>", 1786 mode)); 1787 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 1788 } 1789 1790 if (val != 0) { 1791 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1792 " npi_xmac_reset" 1793 " HW ERROR: MAC_RESET failed <0x%x>", 1794 val)); 1795 1796 if (txmac) 1797 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 1798 else 1799 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 1800 } 1801 1802 return (NPI_SUCCESS); 1803 } 1804 1805 npi_status_t 1806 npi_xmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1807 xmac_xif_config_t config) 1808 { 1809 uint64_t val = 0; 1810 1811 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1812 1813 switch (op) { 1814 case ENABLE: 1815 case DISABLE: 1816 ASSERT((config != 0) && ((config & ~CFG_XMAC_XIF_ALL) == 0)); 1817 if ((config == 0) || (config & ~CFG_XMAC_XIF_ALL) != 0) { 1818 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1819 " npi_xmac_xif_config" 1820 " Invalid Input:" 1821 " config <0x%x>", config)); 1822 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1823 } 1824 if (op == ENABLE) { 1825 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1826 if (config & CFG_XMAC_XIF_LED_FORCE) 1827 val |= XMAC_XIF_FORCE_LED_ON; 1828 if (config & CFG_XMAC_XIF_LED_POLARITY) 1829 val |= XMAC_XIF_LED_POLARITY; 1830 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1831 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1832 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1833 val |= XMAC_XIF_TX_OUTPUT_EN; 1834 1835 if (config & CFG_XMAC_XIF_LOOPBACK) { 1836 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1837 val |= XMAC_XIF_LOOPBACK; 1838 } 1839 1840 if (config & CFG_XMAC_XIF_LFS) 1841 val &= ~XMAC_XIF_LFS_DISABLE; 1842 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1843 val |= XMAC_XIF_XPCS_BYPASS; 1844 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1845 val |= XMAC_XIF_1G_PCS_BYPASS; 1846 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1847 val |= XMAC_XIF_SEL_CLK_25MHZ; 1848 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1849 1850 } else { 1851 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1852 if (config & CFG_XMAC_XIF_LED_FORCE) 1853 val &= ~XMAC_XIF_FORCE_LED_ON; 1854 if (config & CFG_XMAC_XIF_LED_POLARITY) 1855 val &= ~XMAC_XIF_LED_POLARITY; 1856 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1857 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1858 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1859 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1860 if (config & CFG_XMAC_XIF_LOOPBACK) 1861 val &= ~XMAC_XIF_LOOPBACK; 1862 if (config & CFG_XMAC_XIF_LFS) 1863 val |= XMAC_XIF_LFS_DISABLE; 1864 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1865 val &= ~XMAC_XIF_XPCS_BYPASS; 1866 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1867 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1868 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1869 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1870 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1871 } 1872 break; 1873 case INIT: 1874 ASSERT((config & ~CFG_XMAC_XIF_ALL) == 0); 1875 if ((config & ~CFG_XMAC_XIF_ALL) != 0) { 1876 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1877 " npi_xmac_xif_config" 1878 " Invalid Input: config <0x%x>", 1879 config)); 1880 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1881 } 1882 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1883 1884 if (config & CFG_XMAC_XIF_LED_FORCE) 1885 val |= XMAC_XIF_FORCE_LED_ON; 1886 else 1887 val &= ~XMAC_XIF_FORCE_LED_ON; 1888 if (config & CFG_XMAC_XIF_LED_POLARITY) 1889 val |= XMAC_XIF_LED_POLARITY; 1890 else 1891 val &= ~XMAC_XIF_LED_POLARITY; 1892 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1893 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1894 else 1895 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1896 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1897 val |= XMAC_XIF_TX_OUTPUT_EN; 1898 else 1899 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1900 1901 if (config & CFG_XMAC_XIF_LOOPBACK) { 1902 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1903 val |= XMAC_XIF_LOOPBACK; 1904 #ifdef AXIS_DEBUG_LB 1905 val |= XMAC_RX_MAC2IPP_PKT_CNT_EN; 1906 #endif 1907 } else { 1908 val &= ~XMAC_XIF_LOOPBACK; 1909 } 1910 1911 if (config & CFG_XMAC_XIF_LFS) 1912 val &= ~XMAC_XIF_LFS_DISABLE; 1913 else 1914 val |= XMAC_XIF_LFS_DISABLE; 1915 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1916 val |= XMAC_XIF_XPCS_BYPASS; 1917 else 1918 val &= ~XMAC_XIF_XPCS_BYPASS; 1919 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1920 val |= XMAC_XIF_1G_PCS_BYPASS; 1921 else 1922 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1923 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1924 val |= XMAC_XIF_SEL_CLK_25MHZ; 1925 else 1926 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1927 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1928 1929 break; 1930 default: 1931 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1932 " npi_xmac_xif_config" 1933 " Invalid Input: op <0x%x>", op)); 1934 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1935 } 1936 1937 return (NPI_SUCCESS); 1938 } 1939 1940 npi_status_t 1941 npi_xmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1942 xmac_tx_config_t config) 1943 { 1944 uint64_t val = 0; 1945 1946 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1947 1948 switch (op) { 1949 case ENABLE: 1950 case DISABLE: 1951 ASSERT((config != 0) && ((config & ~CFG_XMAC_TX_ALL) == 0)); 1952 if ((config == 0) || (config & ~CFG_XMAC_TX_ALL) != 0) { 1953 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1954 " npi_xmac_tx_config" 1955 " Invalid Input: config <0x%x>", 1956 config)); 1957 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1958 } 1959 if (op == ENABLE) { 1960 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1961 if (config & CFG_XMAC_TX) 1962 val |= XMAC_TX_CFG_TX_ENABLE; 1963 if (config & CFG_XMAC_TX_STRETCH_MODE) 1964 val |= XMAC_TX_CFG_STRETCH_MD; 1965 if (config & CFG_XMAC_VAR_IPG) 1966 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1967 if (config & CFG_XMAC_TX_CRC) 1968 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 1969 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1970 } else { 1971 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1972 if (config & CFG_XMAC_TX) 1973 val &= ~XMAC_TX_CFG_TX_ENABLE; 1974 if (config & CFG_XMAC_TX_STRETCH_MODE) 1975 val &= ~XMAC_TX_CFG_STRETCH_MD; 1976 if (config & CFG_XMAC_VAR_IPG) 1977 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1978 if (config & CFG_XMAC_TX_CRC) 1979 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 1980 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1981 } 1982 break; 1983 case INIT: 1984 ASSERT((config & ~CFG_XMAC_TX_ALL) == 0); 1985 if ((config & ~CFG_XMAC_TX_ALL) != 0) { 1986 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1987 " npi_xmac_tx_config" 1988 " Invalid Input: config <0x%x>", 1989 config)); 1990 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1991 } 1992 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1993 if (config & CFG_XMAC_TX) 1994 val |= XMAC_TX_CFG_TX_ENABLE; 1995 else 1996 val &= ~XMAC_TX_CFG_TX_ENABLE; 1997 if (config & CFG_XMAC_TX_STRETCH_MODE) 1998 val |= XMAC_TX_CFG_STRETCH_MD; 1999 else 2000 val &= ~XMAC_TX_CFG_STRETCH_MD; 2001 if (config & CFG_XMAC_VAR_IPG) 2002 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 2003 else 2004 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 2005 if (config & CFG_XMAC_TX_CRC) 2006 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 2007 else 2008 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 2009 2010 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2011 break; 2012 default: 2013 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2014 " npi_xmac_tx_config" 2015 " Invalid Input: op <0x%x>", 2016 op)); 2017 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2018 } 2019 2020 return (NPI_SUCCESS); 2021 } 2022 2023 npi_status_t 2024 npi_xmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2025 xmac_rx_config_t config) 2026 { 2027 uint64_t val = 0; 2028 2029 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2030 2031 switch (op) { 2032 case ENABLE: 2033 case DISABLE: 2034 ASSERT((config != 0) && ((config & ~CFG_XMAC_RX_ALL) == 0)); 2035 if ((config == 0) || (config & ~CFG_XMAC_RX_ALL) != 0) { 2036 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2037 " npi_xmac_rx_config" 2038 " Invalid Input: config <0x%x>", 2039 config)); 2040 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2041 } 2042 if (op == ENABLE) { 2043 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2044 if (config & CFG_XMAC_RX) 2045 val |= XMAC_RX_CFG_RX_ENABLE; 2046 if (config & CFG_XMAC_RX_PROMISCUOUS) 2047 val |= XMAC_RX_CFG_PROMISC; 2048 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2049 val |= XMAC_RX_CFG_PROMISC_GROUP; 2050 if (config & CFG_XMAC_RX_ERRCHK) 2051 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2052 if (config & CFG_XMAC_RX_CRC_CHK) 2053 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2054 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2055 val |= XMAC_RX_CFG_RESERVED_MCAST; 2056 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2057 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2058 if (config & CFG_XMAC_RX_HASH_FILTER) 2059 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2060 if (config & CFG_XMAC_RX_ADDR_FILTER) 2061 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2062 if (config & CFG_XMAC_RX_STRIP_CRC) 2063 val |= XMAC_RX_CFG_STRIP_CRC; 2064 if (config & CFG_XMAC_RX_PAUSE) 2065 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2066 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2067 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2068 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2069 } else { 2070 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2071 if (config & CFG_XMAC_RX) 2072 val &= ~XMAC_RX_CFG_RX_ENABLE; 2073 if (config & CFG_XMAC_RX_PROMISCUOUS) 2074 val &= ~XMAC_RX_CFG_PROMISC; 2075 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2076 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2077 if (config & CFG_XMAC_RX_ERRCHK) 2078 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2079 if (config & CFG_XMAC_RX_CRC_CHK) 2080 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2081 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2082 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2083 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2084 val |= XMAC_RX_CFG_CD_VIO_CHK; 2085 if (config & CFG_XMAC_RX_HASH_FILTER) 2086 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2087 if (config & CFG_XMAC_RX_ADDR_FILTER) 2088 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2089 if (config & CFG_XMAC_RX_STRIP_CRC) 2090 val &= ~XMAC_RX_CFG_STRIP_CRC; 2091 if (config & CFG_XMAC_RX_PAUSE) 2092 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2093 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2094 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2095 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2096 } 2097 break; 2098 case INIT: 2099 ASSERT((config & ~CFG_XMAC_RX_ALL) == 0); 2100 if ((config & ~CFG_XMAC_RX_ALL) != 0) { 2101 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2102 " npi_xmac_rx_config" 2103 " Invalid Input: config <0x%x>", 2104 config)); 2105 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2106 } 2107 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2108 if (config & CFG_XMAC_RX) 2109 val |= XMAC_RX_CFG_RX_ENABLE; 2110 else 2111 val &= ~XMAC_RX_CFG_RX_ENABLE; 2112 if (config & CFG_XMAC_RX_PROMISCUOUS) 2113 val |= XMAC_RX_CFG_PROMISC; 2114 else 2115 val &= ~XMAC_RX_CFG_PROMISC; 2116 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2117 val |= XMAC_RX_CFG_PROMISC_GROUP; 2118 else 2119 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2120 if (config & CFG_XMAC_RX_ERRCHK) 2121 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2122 else 2123 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2124 if (config & CFG_XMAC_RX_CRC_CHK) 2125 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2126 else 2127 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2128 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2129 val |= XMAC_RX_CFG_RESERVED_MCAST; 2130 else 2131 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2132 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2133 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2134 else 2135 val |= XMAC_RX_CFG_CD_VIO_CHK; 2136 if (config & CFG_XMAC_RX_HASH_FILTER) 2137 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2138 else 2139 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2140 if (config & CFG_XMAC_RX_ADDR_FILTER) 2141 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2142 else 2143 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2144 if (config & CFG_XMAC_RX_PAUSE) 2145 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2146 else 2147 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2148 if (config & CFG_XMAC_RX_STRIP_CRC) 2149 val |= XMAC_RX_CFG_STRIP_CRC; 2150 else 2151 val &= ~XMAC_RX_CFG_STRIP_CRC; 2152 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2153 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2154 else 2155 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2156 2157 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2158 break; 2159 default: 2160 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2161 " npi_xmac_rx_config" 2162 " Invalid Input: op <0x%x>", op)); 2163 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2164 } 2165 2166 return (NPI_SUCCESS); 2167 } 2168 2169 npi_status_t 2170 npi_xmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2171 xmac_tx_iconfig_t iconfig) 2172 { 2173 uint64_t val = 0; 2174 2175 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2176 2177 switch (op) { 2178 case ENABLE: 2179 case DISABLE: 2180 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2181 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2182 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2183 " npi_xmac_tx_iconfig" 2184 " Invalid Input: iconfig <0x%x>", 2185 iconfig)); 2186 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2187 } 2188 XMAC_REG_RD(handle, portn, XTXMAC_STAT_MSK_REG, &val); 2189 if (op == ENABLE) 2190 val &= ~iconfig; 2191 else 2192 val |= iconfig; 2193 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, val); 2194 2195 break; 2196 case INIT: 2197 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2198 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2199 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2200 " npi_xmac_tx_iconfig" 2201 " Invalid Input: iconfig <0x%x>", 2202 iconfig)); 2203 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2204 } 2205 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, ~iconfig); 2206 2207 break; 2208 default: 2209 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2210 " npi_xmac_tx_iconfig" 2211 " Invalid Input: iconfig <0x%x>", 2212 iconfig)); 2213 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2214 } 2215 2216 return (NPI_SUCCESS); 2217 } 2218 2219 npi_status_t 2220 npi_xmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2221 xmac_rx_iconfig_t iconfig) 2222 { 2223 uint64_t val = 0; 2224 2225 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2226 2227 switch (op) { 2228 case ENABLE: 2229 case DISABLE: 2230 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_RX_ALL) == 0)); 2231 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2232 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2233 " npi_xmac_rx_iconfig" 2234 " Invalid Input: iconfig <0x%x>", 2235 iconfig)); 2236 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2237 } 2238 XMAC_REG_RD(handle, portn, XRXMAC_STAT_MSK_REG, &val); 2239 if (op == ENABLE) 2240 val &= ~iconfig; 2241 else 2242 val |= iconfig; 2243 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, val); 2244 2245 break; 2246 case INIT: 2247 ASSERT((iconfig & ~ICFG_XMAC_RX_ALL) == 0); 2248 if ((iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2249 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2250 " npi_xmac_rx_iconfig" 2251 " Invalid Input: iconfig <0x%x>", 2252 iconfig)); 2253 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2254 } 2255 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, ~iconfig); 2256 2257 break; 2258 default: 2259 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2260 " npi_xmac_rx_iconfig" 2261 " Invalid Input: iconfig <0x%x>", 2262 iconfig)); 2263 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2264 } 2265 2266 return (NPI_SUCCESS); 2267 } 2268 2269 npi_status_t 2270 npi_xmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2271 xmac_ctl_iconfig_t iconfig) 2272 { 2273 uint64_t val = 0; 2274 2275 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2276 2277 switch (op) { 2278 case ENABLE: 2279 case DISABLE: 2280 ASSERT((iconfig != 0) && \ 2281 ((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0)); 2282 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2283 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2284 " npi_xmac_ctl_iconfig" 2285 " Invalid Input: iconfig <0x%x>", 2286 iconfig)); 2287 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2288 } 2289 XMAC_REG_RD(handle, portn, XMAC_C_S_MSK_REG, &val); 2290 if (op == ENABLE) 2291 val &= ~iconfig; 2292 else 2293 val |= iconfig; 2294 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, val); 2295 2296 break; 2297 case INIT: 2298 ASSERT((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0); 2299 if ((iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2300 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2301 " npi_xmac_ctl_iconfig" 2302 " Invalid Input: iconfig <0x%x>", 2303 iconfig)); 2304 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2305 } 2306 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, ~iconfig); 2307 2308 break; 2309 default: 2310 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2311 " npi_xmac_ctl_iconfig" 2312 " Invalid Input: iconfig <0x%x>", 2313 iconfig)); 2314 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2315 } 2316 2317 return (NPI_SUCCESS); 2318 } 2319 2320 npi_status_t 2321 npi_xmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 2322 xmac_tx_iconfig_t *istatus) 2323 { 2324 uint64_t val; 2325 2326 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2327 2328 XMAC_REG_RD(handle, portn, XTXMAC_STATUS_REG, &val); 2329 *istatus = (uint32_t)val; 2330 2331 return (NPI_SUCCESS); 2332 } 2333 2334 npi_status_t 2335 npi_xmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 2336 xmac_rx_iconfig_t *istatus) 2337 { 2338 uint64_t val; 2339 2340 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2341 2342 XMAC_REG_RD(handle, portn, XRXMAC_STATUS_REG, &val); 2343 *istatus = (uint32_t)val; 2344 2345 return (NPI_SUCCESS); 2346 } 2347 2348 npi_status_t 2349 npi_xmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 2350 xmac_ctl_iconfig_t *istatus) 2351 { 2352 uint64_t val; 2353 2354 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2355 2356 XMAC_REG_RD(handle, portn, XMAC_CTRL_STAT_REG, &val); 2357 *istatus = (uint32_t)val; 2358 2359 return (NPI_SUCCESS); 2360 } 2361 2362 npi_status_t 2363 npi_xmac_xpcs_reset(npi_handle_t handle, uint8_t portn) 2364 { 2365 uint64_t val; 2366 int delay = 100; 2367 2368 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2369 2370 XPCS_REG_RD(handle, portn, XPCS_CTRL_1_REG, &val); 2371 val |= XPCS_CTRL1_RST; 2372 XPCS_REG_WR(handle, portn, XPCS_CTRL_1_REG, val); 2373 2374 while ((--delay) && (val & XPCS_CTRL1_RST)) { 2375 NXGE_DELAY(10); 2376 XPCS_REG_RD(handle, portn, XPCS_CTRL_1_REG, &val); 2377 } 2378 2379 if (delay == 0) { 2380 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2381 " npi_xmac_xpcs_reset portn <%d> failed", portn)); 2382 return (NPI_FAILURE); 2383 } 2384 2385 return (NPI_SUCCESS); 2386 } 2387 2388 npi_status_t 2389 npi_xmac_xpcs_enable(npi_handle_t handle, uint8_t portn) 2390 { 2391 uint64_t val; 2392 2393 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2394 2395 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2396 val |= XPCS_CFG_XPCS_ENABLE; 2397 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2398 2399 return (NPI_SUCCESS); 2400 } 2401 2402 npi_status_t 2403 npi_xmac_xpcs_disable(npi_handle_t handle, uint8_t portn) 2404 { 2405 uint64_t val; 2406 2407 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2408 2409 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2410 val &= ~XPCS_CFG_XPCS_ENABLE; 2411 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2412 2413 return (NPI_SUCCESS); 2414 } 2415 2416 npi_status_t 2417 npi_xmac_xpcs_read(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2418 uint32_t *value) 2419 { 2420 uint32_t reg; 2421 uint64_t val; 2422 2423 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2424 2425 switch (xpcs_reg) { 2426 case XPCS_REG_CONTROL1: 2427 reg = XPCS_CTRL_1_REG; 2428 break; 2429 case XPCS_REG_STATUS1: 2430 reg = XPCS_STATUS_1_REG; 2431 break; 2432 case XPCS_REG_DEVICE_ID: 2433 reg = XPCS_DEV_ID_REG; 2434 break; 2435 case XPCS_REG_SPEED_ABILITY: 2436 reg = XPCS_SPEED_ABILITY_REG; 2437 break; 2438 case XPCS_REG_DEVICE_IN_PKG: 2439 reg = XPCS_DEV_IN_PKG_REG; 2440 break; 2441 case XPCS_REG_CONTROL2: 2442 reg = XPCS_CTRL_2_REG; 2443 break; 2444 case XPCS_REG_STATUS2: 2445 reg = XPCS_STATUS_2_REG; 2446 break; 2447 case XPCS_REG_PKG_ID: 2448 reg = XPCS_PKG_ID_REG; 2449 break; 2450 case XPCS_REG_STATUS: 2451 reg = XPCS_STATUS_REG; 2452 break; 2453 case XPCS_REG_TEST_CONTROL: 2454 reg = XPCS_TEST_CTRL_REG; 2455 break; 2456 case XPCS_REG_CONFIG_VENDOR1: 2457 reg = XPCS_CFG_VENDOR_1_REG; 2458 break; 2459 case XPCS_REG_DIAG_VENDOR2: 2460 reg = XPCS_DIAG_VENDOR_2_REG; 2461 break; 2462 case XPCS_REG_MASK1: 2463 reg = XPCS_MASK_1_REG; 2464 break; 2465 case XPCS_REG_PACKET_COUNTER: 2466 reg = XPCS_PKT_CNTR_REG; 2467 break; 2468 case XPCS_REG_TX_STATEMACHINE: 2469 reg = XPCS_TX_STATE_MC_REG; 2470 break; 2471 case XPCS_REG_DESCWERR_COUNTER: 2472 reg = XPCS_DESKEW_ERR_CNTR_REG; 2473 break; 2474 case XPCS_REG_SYMBOL_ERR_L0_1_COUNTER: 2475 reg = XPCS_SYM_ERR_CNTR_L0_L1_REG; 2476 break; 2477 case XPCS_REG_SYMBOL_ERR_L2_3_COUNTER: 2478 reg = XPCS_SYM_ERR_CNTR_L2_L3_REG; 2479 break; 2480 case XPCS_REG_TRAINING_VECTOR: 2481 reg = XPCS_TRAINING_VECTOR_REG; 2482 break; 2483 default: 2484 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2485 " npi_xmac_xpcs_read" 2486 " Invalid Input: xpcs_reg <0x%x>", 2487 xpcs_reg)); 2488 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 2489 } 2490 XPCS_REG_RD(handle, portn, reg, &val); 2491 *value = val & 0xFFFFFFFF; 2492 2493 return (NPI_SUCCESS); 2494 } 2495 2496 npi_status_t 2497 npi_xmac_xpcs_write(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2498 uint32_t value) 2499 { 2500 uint32_t reg; 2501 uint64_t val; 2502 2503 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2504 2505 switch (xpcs_reg) { 2506 case XPCS_REG_CONTROL1: 2507 reg = XPCS_CTRL_1_REG; 2508 break; 2509 case XPCS_REG_TEST_CONTROL: 2510 reg = XPCS_TEST_CTRL_REG; 2511 break; 2512 case XPCS_REG_CONFIG_VENDOR1: 2513 reg = XPCS_CFG_VENDOR_1_REG; 2514 break; 2515 case XPCS_REG_DIAG_VENDOR2: 2516 reg = XPCS_DIAG_VENDOR_2_REG; 2517 break; 2518 case XPCS_REG_MASK1: 2519 reg = XPCS_MASK_1_REG; 2520 break; 2521 case XPCS_REG_PACKET_COUNTER: 2522 reg = XPCS_PKT_CNTR_REG; 2523 break; 2524 case XPCS_REG_DESCWERR_COUNTER: 2525 reg = XPCS_DESKEW_ERR_CNTR_REG; 2526 break; 2527 case XPCS_REG_TRAINING_VECTOR: 2528 reg = XPCS_TRAINING_VECTOR_REG; 2529 break; 2530 default: 2531 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2532 " npi_xmac_xpcs_write" 2533 " Invalid Input: xpcs_reg <0x%x>", 2534 xpcs_reg)); 2535 return (NPI_FAILURE | NPI_MAC_PCS_REG_INVALID(portn)); 2536 } 2537 val = value; 2538 2539 XPCS_REG_WR(handle, portn, reg, val); 2540 2541 return (NPI_SUCCESS); 2542 } 2543 2544 npi_status_t 2545 npi_bmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 2546 { 2547 uint64_t val = 0; 2548 boolean_t txmac = B_FALSE; 2549 2550 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2551 2552 switch (mode) { 2553 case TX_MAC_RESET: 2554 BMAC_REG_WR(handle, portn, BTXMAC_SW_RST_REG, 0x1); 2555 BMAC_WAIT_REG(handle, portn, BTXMAC_SW_RST_REG, val); 2556 txmac = B_TRUE; 2557 break; 2558 case RX_MAC_RESET: 2559 BMAC_REG_WR(handle, portn, BRXMAC_SW_RST_REG, 0x1); 2560 BMAC_WAIT_REG(handle, portn, BRXMAC_SW_RST_REG, val); 2561 break; 2562 default: 2563 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2564 " npi_bmac_reset" 2565 " Invalid Input: mode <0x%x>", 2566 mode)); 2567 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 2568 } 2569 2570 if (val != 0) { 2571 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2572 " npi_bmac_reset" 2573 " BMAC_RESET HW Error: ret <0x%x>", 2574 val)); 2575 if (txmac) 2576 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 2577 else 2578 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 2579 } 2580 2581 return (NPI_SUCCESS); 2582 } 2583 2584 npi_status_t 2585 npi_mac_pcs_reset(npi_handle_t handle, uint8_t portn) 2586 { 2587 /* what to do here ? */ 2588 uint64_t val = 0; 2589 int delay = 100; 2590 2591 ASSERT(IS_PORT_NUM_VALID(portn)); 2592 2593 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 2594 val |= PCS_MII_RESET; 2595 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 2596 while ((delay) && (val & PCS_MII_RESET)) { 2597 NXGE_DELAY(10); 2598 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 2599 delay--; 2600 } 2601 if (delay == 0) { 2602 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2603 " npi_bmac_pcs_reset portn <%d> failed", portn)); 2604 return (NPI_FAILURE); 2605 } 2606 return (NPI_SUCCESS); 2607 } 2608 2609 npi_status_t 2610 npi_mac_get_link_status(npi_handle_t handle, uint8_t portn, 2611 boolean_t *link_up) 2612 { 2613 uint64_t val; 2614 2615 ASSERT(IS_PORT_NUM_VALID(portn)); 2616 2617 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 2618 2619 if (val & PCS_MII_STATUS_LINK_STATUS) { 2620 *link_up = B_TRUE; 2621 } else { 2622 *link_up = B_FALSE; 2623 } 2624 2625 return (NPI_SUCCESS); 2626 } 2627 2628 npi_status_t 2629 npi_bmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2630 bmac_tx_config_t config) 2631 { 2632 uint64_t val = 0; 2633 2634 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2635 2636 switch (op) { 2637 case ENABLE: 2638 case DISABLE: 2639 ASSERT((config != 0) && ((config & ~CFG_BMAC_TX_ALL) == 0)); 2640 if ((config == 0) || (config & ~CFG_BMAC_TX_ALL) != 0) { 2641 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2642 " npi_bmac_tx_config" 2643 " Invalid Input: config <0x%x>", 2644 config)); 2645 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2646 } 2647 if (op == ENABLE) { 2648 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2649 if (config & CFG_BMAC_TX) 2650 val |= MAC_TX_CFG_TXMAC_ENABLE; 2651 if (config & CFG_BMAC_TX_CRC) 2652 val &= ~MAC_TX_CFG_NO_FCS; 2653 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2654 } else { 2655 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2656 if (config & CFG_BMAC_TX) 2657 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2658 if (config & CFG_BMAC_TX_CRC) 2659 val |= MAC_TX_CFG_NO_FCS; 2660 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2661 } 2662 break; 2663 case INIT: 2664 ASSERT((config & ~CFG_BMAC_TX_ALL) == 0); 2665 if ((config & ~CFG_BMAC_TX_ALL) != 0) { 2666 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2667 " npi_bmac_tx_config" 2668 " Invalid Input: config <0x%x>", 2669 config)); 2670 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2671 } 2672 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2673 if (config & CFG_BMAC_TX) 2674 val |= MAC_TX_CFG_TXMAC_ENABLE; 2675 else 2676 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2677 if (config & CFG_BMAC_TX_CRC) 2678 val &= ~MAC_TX_CFG_NO_FCS; 2679 else 2680 val |= MAC_TX_CFG_NO_FCS; 2681 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2682 break; 2683 default: 2684 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2685 " npi_bmac_tx_config" 2686 " Invalid Input: op <0x%x>", 2687 op)); 2688 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2689 } 2690 2691 return (NPI_SUCCESS); 2692 } 2693 2694 npi_status_t 2695 npi_bmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2696 bmac_rx_config_t config) 2697 { 2698 uint64_t val = 0; 2699 2700 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2701 2702 switch (op) { 2703 case ENABLE: 2704 case DISABLE: 2705 ASSERT((config != 0) && ((config & ~CFG_BMAC_RX_ALL) == 0)); 2706 if ((config == 0) || (config & ~CFG_BMAC_RX_ALL) != 0) { 2707 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2708 " npi_bmac_rx_config" 2709 " Invalid Input: config <0x%x>", 2710 config)); 2711 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2712 } 2713 if (op == ENABLE) { 2714 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2715 if (config & CFG_BMAC_RX) 2716 val |= MAC_RX_CFG_RXMAC_ENABLE; 2717 if (config & CFG_BMAC_RX_STRIP_PAD) 2718 val |= MAC_RX_CFG_STRIP_PAD; 2719 if (config & CFG_BMAC_RX_STRIP_CRC) 2720 val |= MAC_RX_CFG_STRIP_FCS; 2721 if (config & CFG_BMAC_RX_PROMISCUOUS) 2722 val |= MAC_RX_CFG_PROMISC; 2723 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2724 val |= MAC_RX_CFG_PROMISC_GROUP; 2725 if (config & CFG_BMAC_RX_HASH_FILTER) 2726 val |= MAC_RX_CFG_HASH_FILTER_EN; 2727 if (config & CFG_BMAC_RX_ADDR_FILTER) 2728 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2729 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2730 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2731 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2732 } else { 2733 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2734 if (config & CFG_BMAC_RX) 2735 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2736 if (config & CFG_BMAC_RX_STRIP_PAD) 2737 val &= ~MAC_RX_CFG_STRIP_PAD; 2738 if (config & CFG_BMAC_RX_STRIP_CRC) 2739 val &= ~MAC_RX_CFG_STRIP_FCS; 2740 if (config & CFG_BMAC_RX_PROMISCUOUS) 2741 val &= ~MAC_RX_CFG_PROMISC; 2742 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2743 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2744 if (config & CFG_BMAC_RX_HASH_FILTER) 2745 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2746 if (config & CFG_BMAC_RX_ADDR_FILTER) 2747 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2748 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2749 val |= MAC_RX_CFG_DISABLE_DISCARD; 2750 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2751 } 2752 break; 2753 case INIT: 2754 ASSERT((config & ~CFG_BMAC_RX_ALL) == 0); 2755 if ((config & ~CFG_BMAC_RX_ALL) != 0) { 2756 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2757 " npi_bmac_rx_config" 2758 " Invalid Input: config <0x%x>", 2759 config)); 2760 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2761 } 2762 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2763 if (config & CFG_BMAC_RX) 2764 val |= MAC_RX_CFG_RXMAC_ENABLE; 2765 else 2766 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2767 if (config & CFG_BMAC_RX_STRIP_PAD) 2768 val |= MAC_RX_CFG_STRIP_PAD; 2769 else 2770 val &= ~MAC_RX_CFG_STRIP_PAD; 2771 if (config & CFG_BMAC_RX_STRIP_CRC) 2772 val |= MAC_RX_CFG_STRIP_FCS; 2773 else 2774 val &= ~MAC_RX_CFG_STRIP_FCS; 2775 if (config & CFG_BMAC_RX_PROMISCUOUS) 2776 val |= MAC_RX_CFG_PROMISC; 2777 else 2778 val &= ~MAC_RX_CFG_PROMISC; 2779 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2780 val |= MAC_RX_CFG_PROMISC_GROUP; 2781 else 2782 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2783 if (config & CFG_BMAC_RX_HASH_FILTER) 2784 val |= MAC_RX_CFG_HASH_FILTER_EN; 2785 else 2786 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2787 if (config & CFG_BMAC_RX_ADDR_FILTER) 2788 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2789 else 2790 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2791 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2792 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2793 else 2794 val |= MAC_RX_CFG_DISABLE_DISCARD; 2795 2796 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2797 break; 2798 default: 2799 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2800 " npi_bmac_rx_config" 2801 " Invalid Input: op <0x%x>", op)); 2802 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2803 } 2804 2805 return (NPI_SUCCESS); 2806 } 2807 2808 npi_status_t 2809 npi_bmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2810 bmac_rx_iconfig_t iconfig) 2811 { 2812 uint64_t val = 0; 2813 2814 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2815 2816 switch (op) { 2817 case ENABLE: 2818 case DISABLE: 2819 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_RX_ALL) == 0)); 2820 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2821 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2822 " npi_bmac_rx_iconfig" 2823 " Invalid Input: iconfig <0x%x>", 2824 iconfig)); 2825 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2826 } 2827 BMAC_REG_RD(handle, portn, BRXMAC_STAT_MSK_REG, &val); 2828 if (op == ENABLE) 2829 val &= ~iconfig; 2830 else 2831 val |= iconfig; 2832 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, val); 2833 2834 break; 2835 case INIT: 2836 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 2837 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2838 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2839 " npi_bmac_rx_iconfig" 2840 " Invalid Input: iconfig <0x%x>", 2841 iconfig)); 2842 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2843 } 2844 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, ~iconfig); 2845 2846 break; 2847 default: 2848 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2849 " npi_bmac_rx_iconfig" 2850 " Invalid Input: iconfig <0x%x>", 2851 iconfig)); 2852 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2853 } 2854 2855 return (NPI_SUCCESS); 2856 } 2857 2858 npi_status_t 2859 npi_bmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2860 bmac_xif_config_t config) 2861 { 2862 uint64_t val = 0; 2863 2864 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2865 2866 switch (op) { 2867 case ENABLE: 2868 case DISABLE: 2869 ASSERT((config != 0) && ((config & ~CFG_BMAC_XIF_ALL) == 0)); 2870 if ((config == 0) || (config & ~CFG_BMAC_XIF_ALL) != 0) { 2871 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2872 " npi_bmac_xif_config" 2873 " Invalid Input: config <0x%x>", 2874 config)); 2875 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2876 } 2877 if (op == ENABLE) { 2878 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2879 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2880 val |= MAC_XIF_TX_OUTPUT_EN; 2881 if (config & CFG_BMAC_XIF_LOOPBACK) 2882 val |= MAC_XIF_MII_INT_LOOPBACK; 2883 if (config & CFG_BMAC_XIF_GMII_MODE) 2884 val |= MAC_XIF_GMII_MODE; 2885 if (config & CFG_BMAC_XIF_LINKLED) 2886 val |= MAC_XIF_LINK_LED; 2887 if (config & CFG_BMAC_XIF_LED_POLARITY) 2888 val |= MAC_XIF_LED_POLARITY; 2889 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2890 val |= MAC_XIF_SEL_CLK_25MHZ; 2891 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2892 } else { 2893 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2894 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2895 val &= ~MAC_XIF_TX_OUTPUT_EN; 2896 if (config & CFG_BMAC_XIF_LOOPBACK) 2897 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2898 if (config & CFG_BMAC_XIF_GMII_MODE) 2899 val &= ~MAC_XIF_GMII_MODE; 2900 if (config & CFG_BMAC_XIF_LINKLED) 2901 val &= ~MAC_XIF_LINK_LED; 2902 if (config & CFG_BMAC_XIF_LED_POLARITY) 2903 val &= ~MAC_XIF_LED_POLARITY; 2904 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2905 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2906 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2907 } 2908 break; 2909 case INIT: 2910 ASSERT((config & ~CFG_BMAC_XIF_ALL) == 0); 2911 if ((config & ~CFG_BMAC_XIF_ALL) != 0) { 2912 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2913 " npi_bmac_xif_config" 2914 " Invalid Input: config <0x%x>", 2915 config)); 2916 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2917 } 2918 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2919 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2920 val |= MAC_XIF_TX_OUTPUT_EN; 2921 else 2922 val &= ~MAC_XIF_TX_OUTPUT_EN; 2923 if (config & CFG_BMAC_XIF_LOOPBACK) 2924 val |= MAC_XIF_MII_INT_LOOPBACK; 2925 else 2926 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2927 if (config & CFG_BMAC_XIF_GMII_MODE) 2928 val |= MAC_XIF_GMII_MODE; 2929 else 2930 val &= ~MAC_XIF_GMII_MODE; 2931 if (config & CFG_BMAC_XIF_LINKLED) 2932 val |= MAC_XIF_LINK_LED; 2933 else 2934 val &= ~MAC_XIF_LINK_LED; 2935 if (config & CFG_BMAC_XIF_LED_POLARITY) 2936 val |= MAC_XIF_LED_POLARITY; 2937 else 2938 val &= ~MAC_XIF_LED_POLARITY; 2939 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2940 val |= MAC_XIF_SEL_CLK_25MHZ; 2941 else 2942 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2943 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2944 break; 2945 default: 2946 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2947 " npi_bmac_xif_config" 2948 " Invalid Input: op <0x%x>", 2949 op)); 2950 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2951 } 2952 2953 return (NPI_SUCCESS); 2954 } 2955 2956 npi_status_t 2957 npi_bmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2958 bmac_tx_iconfig_t iconfig) 2959 { 2960 uint64_t val = 0; 2961 2962 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2963 2964 switch (op) { 2965 case ENABLE: 2966 case DISABLE: 2967 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2968 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2969 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2970 " npi_bmac_tx_iconfig" 2971 " Invalid Input: iconfig <0x%x>", 2972 iconfig)); 2973 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2974 } 2975 BMAC_REG_RD(handle, portn, BTXMAC_STAT_MSK_REG, &val); 2976 if (op == ENABLE) 2977 val &= ~iconfig; 2978 else 2979 val |= iconfig; 2980 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, val); 2981 2982 break; 2983 case INIT: 2984 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2985 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2986 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2987 " npi_bmac_tx_iconfig" 2988 " Invalid Input: iconfig <0x%x>", 2989 iconfig)); 2990 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2991 } 2992 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, ~iconfig); 2993 2994 break; 2995 default: 2996 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2997 " npi_bmac_tx_iconfig" 2998 " Invalid Input: iconfig <0x%x>", 2999 iconfig)); 3000 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 3001 } 3002 3003 return (NPI_SUCCESS); 3004 } 3005 3006 npi_status_t 3007 npi_bmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 3008 bmac_ctl_iconfig_t iconfig) 3009 { 3010 uint64_t val = 0; 3011 3012 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3013 3014 switch (op) { 3015 case ENABLE: 3016 case DISABLE: 3017 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_CTL_ALL) == 0)); 3018 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_CTL_ALL) != 0) { 3019 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3020 " npi_bmac_ctl_iconfig" 3021 " Invalid Input: iconfig <0x%x>", 3022 iconfig)); 3023 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 3024 } 3025 BMAC_REG_RD(handle, portn, BMAC_C_S_MSK_REG, &val); 3026 if (op == ENABLE) 3027 val &= ~iconfig; 3028 else 3029 val |= iconfig; 3030 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, val); 3031 3032 break; 3033 case INIT: 3034 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 3035 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 3036 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3037 " npi_bmac_ctl_iconfig" 3038 " Invalid Input: iconfig <0x%x>", 3039 iconfig)); 3040 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 3041 } 3042 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, ~iconfig); 3043 3044 break; 3045 default: 3046 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3047 " npi_bmac_ctl_iconfig" 3048 " Invalid Input: iconfig <0x%x>", 3049 iconfig)); 3050 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 3051 } 3052 3053 return (NPI_SUCCESS); 3054 } 3055 3056 npi_status_t 3057 npi_bmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 3058 bmac_tx_iconfig_t *istatus) 3059 { 3060 uint64_t val = 0; 3061 3062 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3063 3064 BMAC_REG_RD(handle, portn, BTXMAC_STATUS_REG, &val); 3065 *istatus = (uint32_t)val; 3066 3067 return (NPI_SUCCESS); 3068 } 3069 3070 npi_status_t 3071 npi_bmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 3072 bmac_rx_iconfig_t *istatus) 3073 { 3074 uint64_t val = 0; 3075 3076 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3077 3078 BMAC_REG_RD(handle, portn, BRXMAC_STATUS_REG, &val); 3079 *istatus = (uint32_t)val; 3080 3081 return (NPI_SUCCESS); 3082 } 3083 3084 npi_status_t 3085 npi_bmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 3086 bmac_ctl_iconfig_t *istatus) 3087 { 3088 uint64_t val = 0; 3089 3090 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3091 3092 BMAC_REG_RD(handle, portn, BMAC_CTRL_STAT_REG, &val); 3093 *istatus = (uint32_t)val; 3094 3095 return (NPI_SUCCESS); 3096 } 3097 3098 npi_status_t 3099 npi_mac_mif_mdio_read(npi_handle_t handle, uint8_t portn, uint8_t device, 3100 uint16_t xcvr_reg, uint16_t *value) 3101 { 3102 mif_frame_t frame; 3103 uint_t delay; 3104 3105 frame.value = 0; 3106 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3107 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select address */ 3108 frame.bits.w0.phyad = portn; /* Port number */ 3109 frame.bits.w0.regad = device; /* Device number */ 3110 frame.bits.w0.ta_msb = 1; 3111 frame.bits.w0.ta_lsb = 0; 3112 frame.bits.w0.data = xcvr_reg; /* register address */ 3113 3114 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3115 "mdio read port %d addr val=0x%x\n", portn, frame.value)); 3116 3117 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3118 3119 delay = 0; 3120 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3121 3122 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3123 "mdio read port %d addr poll=0x%x\n", portn, frame.value)); 3124 3125 if (delay == MIF_DELAY) { 3126 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3127 "mdio read no response1\n")); 3128 } 3129 3130 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3131 frame.bits.w0.op = FRAME45_OP_READ; /* Read */ 3132 frame.bits.w0.phyad = portn; /* Port Number */ 3133 frame.bits.w0.regad = device; /* Device Number */ 3134 frame.bits.w0.ta_msb = 1; 3135 frame.bits.w0.ta_lsb = 0; 3136 3137 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3138 "mdio read port %d data frame=0x%x\n", portn, frame.value)); 3139 3140 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3141 3142 delay = 0; 3143 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3144 3145 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3146 "mdio read port %d data poll=0x%x\n", portn, frame.value)); 3147 3148 *value = frame.bits.w0.data; 3149 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3150 "mdio read port=%d val=0x%x\n", portn, *value)); 3151 3152 if (delay == MIF_DELAY) { 3153 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3154 "mdio read no response2\n")); 3155 } 3156 3157 return (NPI_SUCCESS); 3158 } 3159 3160 npi_status_t 3161 npi_mac_mif_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3162 uint16_t *value) 3163 { 3164 mif_frame_t frame; 3165 uint_t delay; 3166 3167 frame.bits.w0.st = 0x1; /* Clause 22 */ 3168 frame.bits.w0.op = 0x2; 3169 frame.bits.w0.phyad = portn; 3170 frame.bits.w0.regad = xcvr_reg; 3171 frame.bits.w0.ta_msb = 1; 3172 frame.bits.w0.ta_lsb = 0; 3173 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3174 3175 delay = 0; 3176 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3177 3178 if (delay == MAX_PIO_RETRIES) 3179 return (NPI_FAILURE | NPI_MAC_MII_READ_FAILED(portn)); 3180 3181 *value = frame.bits.w0.data; 3182 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3183 "mif mii read port %d reg=0x%x frame=0x%x\n", portn, 3184 xcvr_reg, frame.bits.w0.data)); 3185 3186 return (NPI_SUCCESS); 3187 } 3188 3189 npi_status_t 3190 npi_mac_mif_mdio_write(npi_handle_t handle, uint8_t portn, uint8_t device, 3191 uint16_t xcvr_reg, uint16_t value) 3192 { 3193 mif_frame_t frame; 3194 uint_t delay; 3195 3196 frame.value = 0; 3197 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3198 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select Address */ 3199 frame.bits.w0.phyad = portn; /* Port Number */ 3200 frame.bits.w0.regad = device; /* Device Number */ 3201 frame.bits.w0.ta_msb = 1; 3202 frame.bits.w0.ta_lsb = 0; 3203 frame.bits.w0.data = xcvr_reg; /* register address */ 3204 3205 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3206 3207 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3208 "mdio write port %d addr val=0x%x\n", portn, frame.value)); 3209 3210 delay = 0; 3211 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3212 3213 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3214 "mdio write port %d addr poll=0x%x\n", portn, frame.value)); 3215 3216 if (delay == MIF_DELAY) { 3217 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3218 "mdio write no response1\n")); 3219 } 3220 3221 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3222 frame.bits.w0.op = FRAME45_OP_WRITE; /* Write */ 3223 frame.bits.w0.phyad = portn; /* Port number */ 3224 frame.bits.w0.regad = device; /* Device number */ 3225 frame.bits.w0.ta_msb = 1; 3226 frame.bits.w0.ta_lsb = 0; 3227 frame.bits.w0.data = value; 3228 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3229 3230 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3231 "mdio write port %d data val=0x%x\n", portn, frame.value)); 3232 3233 delay = 0; 3234 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3235 3236 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3237 "mdio write port %d data poll=0x%x\n", portn, frame.value)); 3238 3239 if (delay == MIF_DELAY) { 3240 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3241 "mdio write no response2\n")); 3242 } 3243 3244 return (NPI_SUCCESS); 3245 } 3246 3247 npi_status_t 3248 npi_mac_mif_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3249 uint16_t value) 3250 { 3251 mif_frame_t frame; 3252 uint_t delay; 3253 3254 frame.bits.w0.st = 0x1; /* Clause 22 */ 3255 frame.bits.w0.op = 0x1; 3256 frame.bits.w0.phyad = portn; 3257 frame.bits.w0.regad = xcvr_reg; 3258 frame.bits.w0.ta_msb = 1; 3259 frame.bits.w0.ta_lsb = 0; 3260 frame.bits.w0.data = value; 3261 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3262 3263 delay = 0; 3264 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3265 3266 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3267 "mif mii write port %d reg=0x%x frame=0x%x\n", portn, 3268 xcvr_reg, frame.value)); 3269 3270 if (delay == MAX_PIO_RETRIES) 3271 return (NPI_FAILURE | NPI_MAC_MII_WRITE_FAILED(portn)); 3272 3273 return (NPI_SUCCESS); 3274 } 3275 3276 npi_status_t 3277 npi_mac_pcs_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3278 uint16_t *value) 3279 { 3280 pcs_anar_t pcs_anar; 3281 pcs_anar_t pcs_anlpar; 3282 pcs_stat_t pcs_stat; 3283 pcs_stat_mc_t pcs_stat_mc; 3284 mii_anar_t anar; 3285 mii_anar_t anlpar; 3286 mii_aner_t aner; 3287 mii_esr_t esr; 3288 mii_gsr_t gsr; 3289 uint64_t val = 0; 3290 3291 ASSERT(IS_PORT_NUM_VALID(portn)); 3292 3293 switch (xcvr_reg) { 3294 case MII_CONTROL: 3295 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 3296 *value = (uint16_t)val; 3297 break; 3298 case MII_STATUS: 3299 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 3300 pcs_stat.value = val; 3301 PCS_REG_RD(handle, portn, PCS_STATE_MACHINE_REG, &val); 3302 pcs_stat_mc.value = val; 3303 if ((pcs_stat_mc.bits.w0.link_cfg_stat == 0xB) && 3304 (pcs_stat_mc.bits.w0.word_sync != 0)) { 3305 pcs_stat.bits.w0.link_stat = 1; 3306 } else if (pcs_stat_mc.bits.w0.link_cfg_stat != 0xB) { 3307 pcs_stat.bits.w0.link_stat = 0; 3308 } 3309 *value = (uint16_t)pcs_stat.value; 3310 break; 3311 case NXGE_MII_ESR: 3312 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3313 pcs_anar.value = (uint16_t)val; 3314 esr.value = 0; 3315 esr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3316 esr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3317 *value = esr.value; 3318 break; 3319 case MII_AN_ADVERT: 3320 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3321 pcs_anar.value = (uint16_t)val; 3322 anar.value = 0; 3323 anar.bits.cap_pause = pcs_anar.bits.w0.pause; 3324 anar.bits.cap_asmpause = pcs_anar.bits.w0.asm_pause; 3325 *value = anar.value; 3326 break; 3327 case MII_AN_LPABLE: 3328 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3329 pcs_anlpar.value = (uint16_t)val; 3330 anlpar.bits.cap_pause = pcs_anlpar.bits.w0.pause; 3331 anlpar.bits.cap_asmpause = pcs_anlpar.bits.w0.asm_pause; 3332 *value = anlpar.value; 3333 break; 3334 case MII_AN_EXPANSION: 3335 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3336 pcs_anar.value = (uint16_t)val; 3337 aner.value = 0; 3338 aner.bits.lp_an_able = pcs_anar.bits.w0.full_duplex | 3339 pcs_anar.bits.w0.half_duplex; 3340 *value = aner.value; 3341 break; 3342 case NXGE_MII_GSR: 3343 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3344 pcs_anar.value = (uint16_t)val; 3345 gsr.value = 0; 3346 gsr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3347 gsr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3348 *value = gsr.value; 3349 break; 3350 default: 3351 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3352 " npi_mac_pcs_mii_read" 3353 " Invalid Input: xcvr_reg <0x%x>", 3354 xcvr_reg)); 3355 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3356 } 3357 3358 return (NPI_SUCCESS); 3359 } 3360 3361 npi_status_t 3362 npi_mac_pcs_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3363 uint16_t value) 3364 { 3365 pcs_anar_t pcs_anar; 3366 mii_anar_t anar; 3367 mii_gcr_t gcr; 3368 uint64_t val; 3369 3370 ASSERT(IS_PORT_NUM_VALID(portn)); 3371 3372 switch (xcvr_reg) { 3373 case MII_CONTROL: 3374 val = (uint16_t)value; 3375 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 3376 break; 3377 case MII_AN_ADVERT: 3378 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3379 pcs_anar.value = (uint16_t)val; 3380 anar.value = value; 3381 pcs_anar.bits.w0.asm_pause = anar.bits.cap_asmpause; 3382 pcs_anar.bits.w0.pause = anar.bits.cap_pause; 3383 val = pcs_anar.value; 3384 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3385 break; 3386 case NXGE_MII_GCR: 3387 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3388 pcs_anar.value = (uint16_t)val; 3389 gcr.value = value; 3390 pcs_anar.bits.w0.full_duplex = gcr.bits.link_1000fdx; 3391 pcs_anar.bits.w0.half_duplex = gcr.bits.link_1000hdx; 3392 val = pcs_anar.value; 3393 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3394 break; 3395 default: 3396 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3397 " npi_mac_pcs_mii_write" 3398 " Invalid Input: xcvr_reg <0x%x>", 3399 xcvr_reg)); 3400 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3401 } 3402 3403 return (NPI_SUCCESS); 3404 } 3405 3406 npi_status_t 3407 npi_mac_mif_link_intr_enable(npi_handle_t handle, uint8_t portn, 3408 uint8_t xcvr_reg, uint16_t mask) 3409 { 3410 mif_cfg_t mif_cfg; 3411 3412 ASSERT(IS_PORT_NUM_VALID(portn)); 3413 3414 ASSERT(xcvr_reg <= NXGE_MAX_MII_REGS); 3415 if (xcvr_reg > NXGE_MAX_MII_REGS) { 3416 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3417 " npi_mac_mif_link_intr_enable" 3418 " Invalid Input: xcvr_reg <0x%x>", 3419 xcvr_reg)); 3420 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3421 } 3422 3423 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3424 3425 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3426 mif_cfg.bits.w0.reg_addr = xcvr_reg; /* Register address */ 3427 mif_cfg.bits.w0.indirect_md = 0; /* Clause 22 */ 3428 mif_cfg.bits.w0.poll_en = 1; 3429 3430 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3431 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3432 3433 NXGE_DELAY(20); 3434 3435 return (NPI_SUCCESS); 3436 } 3437 3438 npi_status_t 3439 npi_mac_mif_mdio_link_intr_enable(npi_handle_t handle, uint8_t portn, 3440 uint8_t device, uint16_t xcvr_reg, uint16_t mask) 3441 { 3442 mif_cfg_t mif_cfg; 3443 mif_frame_t frame; 3444 uint_t delay; 3445 3446 ASSERT(IS_PORT_NUM_VALID(portn)); 3447 3448 frame.bits.w0.st = 0; /* Clause 45 */ 3449 frame.bits.w0.op = 0; /* Select address */ 3450 frame.bits.w0.phyad = portn; /* Port number */ 3451 frame.bits.w0.regad = device; /* Device number */ 3452 frame.bits.w0.ta_msb = 1; 3453 frame.bits.w0.ta_lsb = 0; 3454 frame.bits.w0.data = xcvr_reg; /* register address */ 3455 3456 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3457 3458 delay = 0; 3459 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3460 if (delay == MAX_PIO_RETRIES) 3461 return (NPI_FAILURE); 3462 3463 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3464 3465 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3466 mif_cfg.bits.w0.reg_addr = device; /* Register address */ 3467 mif_cfg.bits.w0.indirect_md = 1; /* Clause 45 */ 3468 mif_cfg.bits.w0.poll_en = 1; 3469 3470 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3471 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3472 3473 NXGE_DELAY(20); 3474 3475 return (NPI_SUCCESS); 3476 } 3477 3478 void 3479 npi_mac_mif_set_indirect_mode(npi_handle_t handle, boolean_t on_off) 3480 { 3481 mif_cfg_t mif_cfg; 3482 3483 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3484 mif_cfg.bits.w0.indirect_md = on_off; 3485 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3486 } 3487 3488 void 3489 npi_mac_mif_set_atca_mode(npi_handle_t handle, boolean_t on_off) 3490 { 3491 mif_cfg_t mif_cfg; 3492 3493 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3494 mif_cfg.bits.w0.atca_ge = on_off; 3495 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3496 } 3497 3498 npi_status_t 3499 npi_bmac_send_pause(npi_handle_t handle, uint8_t portn, uint16_t pause_time) 3500 { 3501 uint64_t val; 3502 3503 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3504 3505 val = MAC_SEND_PAUSE_SEND | pause_time; 3506 BMAC_REG_WR(handle, portn, MAC_SEND_PAUSE_REG, val); 3507 3508 return (NPI_SUCCESS); 3509 } 3510 3511 npi_status_t 3512 npi_xmac_xif_led(npi_handle_t handle, uint8_t portn, boolean_t on_off) 3513 { 3514 uint64_t val = 0; 3515 3516 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3517 3518 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 3519 3520 if (on_off) { 3521 val |= XMAC_XIF_LED_POLARITY; 3522 val &= ~XMAC_XIF_FORCE_LED_ON; 3523 } else { 3524 val &= ~XMAC_XIF_LED_POLARITY; 3525 val |= XMAC_XIF_FORCE_LED_ON; 3526 } 3527 3528 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 3529 3530 return (NPI_SUCCESS); 3531 } 3532 3533 npi_status_t 3534 npi_xmac_zap_tx_counters(npi_handle_t handle, uint8_t portn) 3535 { 3536 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3537 3538 XMAC_REG_WR(handle, portn, XTXMAC_FRM_CNT_REG, 0); 3539 XMAC_REG_WR(handle, portn, XTXMAC_BYTE_CNT_REG, 0); 3540 3541 return (NPI_SUCCESS); 3542 } 3543 3544 npi_status_t 3545 npi_xmac_zap_rx_counters(npi_handle_t handle, uint8_t portn) 3546 { 3547 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3548 3549 XMAC_REG_WR(handle, portn, XRXMAC_BT_CNT_REG, 0); 3550 XMAC_REG_WR(handle, portn, XRXMAC_BC_FRM_CNT_REG, 0); 3551 XMAC_REG_WR(handle, portn, XRXMAC_MC_FRM_CNT_REG, 0); 3552 XMAC_REG_WR(handle, portn, XRXMAC_FRAG_CNT_REG, 0); 3553 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT1_REG, 0); 3554 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT2_REG, 0); 3555 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT3_REG, 0); 3556 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT4_REG, 0); 3557 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT5_REG, 0); 3558 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT6_REG, 0); 3559 XMAC_REG_WR(handle, portn, XRXMAC_MPSZER_CNT_REG, 0); 3560 XMAC_REG_WR(handle, portn, XRXMAC_CRC_ER_CNT_REG, 0); 3561 XMAC_REG_WR(handle, portn, XRXMAC_CD_VIO_CNT_REG, 0); 3562 XMAC_REG_WR(handle, portn, XRXMAC_AL_ER_CNT_REG, 0); 3563 XMAC_REG_WR(handle, portn, XMAC_LINK_FLT_CNT_REG, 0); 3564 3565 return (NPI_SUCCESS); 3566 } 3567