1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include <npi_mac.h> 27 28 #define MIF_DELAY 500 29 30 #define MAX_FRAME_SZ1 0x5EE 31 #define MAX_FRAME_SZ2 0x5F6 32 #define MAX_FRAME_SZ3 0x7D6 33 #define MAX_FRAME_SZ4 0x232E 34 #define MAX_FRAME_SZ5 0x2406 35 36 #define XMAC_WAIT_REG(handle, portn, reg, val) {\ 37 uint32_t cnt = MAX_PIO_RETRIES;\ 38 do {\ 39 NXGE_DELAY(MAC_RESET_WAIT);\ 40 XMAC_REG_RD(handle, portn, reg, &val);\ 41 cnt--;\ 42 } while (((val & 0x3) != 0) && (cnt > 0));\ 43 } 44 45 #define BMAC_WAIT_REG(handle, portn, reg, val) {\ 46 uint32_t cnt = MAX_PIO_RETRIES;\ 47 do {\ 48 NXGE_DELAY(MAC_RESET_WAIT);\ 49 BMAC_REG_RD(handle, portn, reg, &val);\ 50 cnt--;\ 51 } while (((val & 0x3) != 0) && (cnt > 0));\ 52 } 53 54 #define MIF_WAIT_REG(handle, m_frame, t_delay, interval, max_delay) { \ 55 do { \ 56 NXGE_DELAY(interval); \ 57 MIF_REG_RD(handle, MIF_OUTPUT_FRAME_REG, &m_frame.value); \ 58 t_delay++; \ 59 } while ((m_frame.bits.w0.ta_lsb == 0) && t_delay < max_delay); \ 60 } 61 62 uint64_t xmac_offset[] = { 63 XTXMAC_SW_RST_REG, 64 XRXMAC_SW_RST_REG, 65 XTXMAC_STATUS_REG, 66 XRXMAC_STATUS_REG, 67 XMAC_CTRL_STAT_REG, 68 XTXMAC_STAT_MSK_REG, 69 XRXMAC_STAT_MSK_REG, 70 XMAC_C_S_MSK_REG, 71 XMAC_CONFIG_REG, 72 XMAC_IPG_REG, 73 XMAC_MIN_REG, 74 XMAC_MAX_REG, 75 XMAC_ADDR0_REG, 76 XMAC_ADDR1_REG, 77 XMAC_ADDR2_REG, 78 XRXMAC_BT_CNT_REG, 79 XRXMAC_BC_FRM_CNT_REG, 80 XRXMAC_MC_FRM_CNT_REG, 81 XRXMAC_FRAG_CNT_REG, 82 XRXMAC_HIST_CNT1_REG, 83 XRXMAC_HIST_CNT2_REG, 84 XRXMAC_HIST_CNT3_REG, 85 XRXMAC_HIST_CNT4_REG, 86 XRXMAC_HIST_CNT5_REG, 87 XRXMAC_HIST_CNT6_REG, 88 XRXMAC_MPSZER_CNT_REG, 89 XRXMAC_CRC_ER_CNT_REG, 90 XRXMAC_CD_VIO_CNT_REG, 91 XRXMAC_AL_ER_CNT_REG, 92 XTXMAC_FRM_CNT_REG, 93 XTXMAC_BYTE_CNT_REG, 94 XMAC_LINK_FLT_CNT_REG, 95 XRXMAC_HIST_CNT7_REG, 96 XMAC_SM_REG, 97 XMAC_INTERN1_REG, 98 XMAC_INTERN2_REG, 99 XMAC_ADDR_CMPEN_REG, 100 XMAC_ADDR3_REG, 101 XMAC_ADDR4_REG, 102 XMAC_ADDR5_REG, 103 XMAC_ADDR6_REG, 104 XMAC_ADDR7_REG, 105 XMAC_ADDR8_REG, 106 XMAC_ADDR9_REG, 107 XMAC_ADDR10_REG, 108 XMAC_ADDR11_REG, 109 XMAC_ADDR12_REG, 110 XMAC_ADDR13_REG, 111 XMAC_ADDR14_REG, 112 XMAC_ADDR15_REG, 113 XMAC_ADDR16_REG, 114 XMAC_ADDR17_REG, 115 XMAC_ADDR18_REG, 116 XMAC_ADDR19_REG, 117 XMAC_ADDR20_REG, 118 XMAC_ADDR21_REG, 119 XMAC_ADDR22_REG, 120 XMAC_ADDR23_REG, 121 XMAC_ADDR24_REG, 122 XMAC_ADDR25_REG, 123 XMAC_ADDR26_REG, 124 XMAC_ADDR27_REG, 125 XMAC_ADDR28_REG, 126 XMAC_ADDR29_REG, 127 XMAC_ADDR30_REG, 128 XMAC_ADDR31_REG, 129 XMAC_ADDR32_REG, 130 XMAC_ADDR33_REG, 131 XMAC_ADDR34_REG, 132 XMAC_ADDR35_REG, 133 XMAC_ADDR36_REG, 134 XMAC_ADDR37_REG, 135 XMAC_ADDR38_REG, 136 XMAC_ADDR39_REG, 137 XMAC_ADDR40_REG, 138 XMAC_ADDR41_REG, 139 XMAC_ADDR42_REG, 140 XMAC_ADDR43_REG, 141 XMAC_ADDR44_REG, 142 XMAC_ADDR45_REG, 143 XMAC_ADDR46_REG, 144 XMAC_ADDR47_REG, 145 XMAC_ADDR48_REG, 146 XMAC_ADDR49_REG, 147 XMAC_ADDR50_REG, 148 XMAC_ADDR_FILT0_REG, 149 XMAC_ADDR_FILT1_REG, 150 XMAC_ADDR_FILT2_REG, 151 XMAC_ADDR_FILT12_MASK_REG, 152 XMAC_ADDR_FILT0_MASK_REG, 153 XMAC_HASH_TBL0_REG, 154 XMAC_HASH_TBL1_REG, 155 XMAC_HASH_TBL2_REG, 156 XMAC_HASH_TBL3_REG, 157 XMAC_HASH_TBL4_REG, 158 XMAC_HASH_TBL5_REG, 159 XMAC_HASH_TBL6_REG, 160 XMAC_HASH_TBL7_REG, 161 XMAC_HASH_TBL8_REG, 162 XMAC_HASH_TBL9_REG, 163 XMAC_HASH_TBL10_REG, 164 XMAC_HASH_TBL11_REG, 165 XMAC_HASH_TBL12_REG, 166 XMAC_HASH_TBL13_REG, 167 XMAC_HASH_TBL14_REG, 168 XMAC_HASH_TBL15_REG, 169 XMAC_HOST_INF0_REG, 170 XMAC_HOST_INF1_REG, 171 XMAC_HOST_INF2_REG, 172 XMAC_HOST_INF3_REG, 173 XMAC_HOST_INF4_REG, 174 XMAC_HOST_INF5_REG, 175 XMAC_HOST_INF6_REG, 176 XMAC_HOST_INF7_REG, 177 XMAC_HOST_INF8_REG, 178 XMAC_HOST_INF9_REG, 179 XMAC_HOST_INF10_REG, 180 XMAC_HOST_INF11_REG, 181 XMAC_HOST_INF12_REG, 182 XMAC_HOST_INF13_REG, 183 XMAC_HOST_INF14_REG, 184 XMAC_HOST_INF15_REG, 185 XMAC_HOST_INF16_REG, 186 XMAC_HOST_INF17_REG, 187 XMAC_HOST_INF18_REG, 188 XMAC_HOST_INF19_REG, 189 XMAC_PA_DATA0_REG, 190 XMAC_PA_DATA1_REG, 191 XMAC_DEBUG_SEL_REG, 192 XMAC_TRAINING_VECT_REG, 193 }; 194 195 const char *xmac_name[] = { 196 "XTXMAC_SW_RST_REG", 197 "XRXMAC_SW_RST_REG", 198 "XTXMAC_STATUS_REG", 199 "XRXMAC_STATUS_REG", 200 "XMAC_CTRL_STAT_REG", 201 "XTXMAC_STAT_MSK_REG", 202 "XRXMAC_STAT_MSK_REG", 203 "XMAC_C_S_MSK_REG", 204 "XMAC_CONFIG_REG", 205 "XMAC_IPG_REG", 206 "XMAC_MIN_REG", 207 "XMAC_MAX_REG", 208 "XMAC_ADDR0_REG", 209 "XMAC_ADDR1_REG", 210 "XMAC_ADDR2_REG", 211 "XRXMAC_BT_CNT_REG", 212 "XRXMAC_BC_FRM_CNT_REG", 213 "XRXMAC_MC_FRM_CNT_REG", 214 "XRXMAC_FRAG_CNT_REG", 215 "XRXMAC_HIST_CNT1_REG", 216 "XRXMAC_HIST_CNT2_REG", 217 "XRXMAC_HIST_CNT3_REG", 218 "XRXMAC_HIST_CNT4_REG", 219 "XRXMAC_HIST_CNT5_REG", 220 "XRXMAC_HIST_CNT6_REG", 221 "XRXMAC_MPSZER_CNT_REG", 222 "XRXMAC_CRC_ER_CNT_REG", 223 "XRXMAC_CD_VIO_CNT_REG", 224 "XRXMAC_AL_ER_CNT_REG", 225 "XTXMAC_FRM_CNT_REG", 226 "XTXMAC_BYTE_CNT_REG", 227 "XMAC_LINK_FLT_CNT_REG", 228 "XRXMAC_HIST_CNT7_REG", 229 "XMAC_SM_REG", 230 "XMAC_INTERN1_REG", 231 "XMAC_INTERN2_REG", 232 "XMAC_ADDR_CMPEN_REG", 233 "XMAC_ADDR3_REG", 234 "XMAC_ADDR4_REG", 235 "XMAC_ADDR5_REG", 236 "XMAC_ADDR6_REG", 237 "XMAC_ADDR7_REG", 238 "XMAC_ADDR8_REG", 239 "XMAC_ADDR9_REG", 240 "XMAC_ADDR10_REG", 241 "XMAC_ADDR11_REG", 242 "XMAC_ADDR12_REG", 243 "XMAC_ADDR13_REG", 244 "XMAC_ADDR14_REG", 245 "XMAC_ADDR15_REG", 246 "XMAC_ADDR16_REG", 247 "XMAC_ADDR17_REG", 248 "XMAC_ADDR18_REG", 249 "XMAC_ADDR19_REG", 250 "XMAC_ADDR20_REG", 251 "XMAC_ADDR21_REG", 252 "XMAC_ADDR22_REG", 253 "XMAC_ADDR23_REG", 254 "XMAC_ADDR24_REG", 255 "XMAC_ADDR25_REG", 256 "XMAC_ADDR26_REG", 257 "XMAC_ADDR27_REG", 258 "XMAC_ADDR28_REG", 259 "XMAC_ADDR29_REG", 260 "XMAC_ADDR30_REG", 261 "XMAC_ADDR31_REG", 262 "XMAC_ADDR32_REG", 263 "XMAC_ADDR33_REG", 264 "XMAC_ADDR34_REG", 265 "XMAC_ADDR35_REG", 266 "XMAC_ADDR36_REG", 267 "XMAC_ADDR37_REG", 268 "XMAC_ADDR38_REG", 269 "XMAC_ADDR39_REG", 270 "XMAC_ADDR40_REG", 271 "XMAC_ADDR41_REG", 272 "XMAC_ADDR42_REG", 273 "XMAC_ADDR43_REG", 274 "XMAC_ADDR44_REG", 275 "XMAC_ADDR45_REG", 276 "XMAC_ADDR46_REG", 277 "XMAC_ADDR47_REG", 278 "XMAC_ADDR48_REG", 279 "XMAC_ADDR49_REG", 280 "XMAC_ADDR50_RE", 281 "XMAC_ADDR_FILT0_REG", 282 "XMAC_ADDR_FILT1_REG", 283 "XMAC_ADDR_FILT2_REG", 284 "XMAC_ADDR_FILT12_MASK_REG", 285 "XMAC_ADDR_FILT0_MASK_REG", 286 "XMAC_HASH_TBL0_REG", 287 "XMAC_HASH_TBL1_REG", 288 "XMAC_HASH_TBL2_REG", 289 "XMAC_HASH_TBL3_REG", 290 "XMAC_HASH_TBL4_REG", 291 "XMAC_HASH_TBL5_REG", 292 "XMAC_HASH_TBL6_REG", 293 "XMAC_HASH_TBL7_REG", 294 "XMAC_HASH_TBL8_REG", 295 "XMAC_HASH_TBL9_REG", 296 "XMAC_HASH_TBL10_REG", 297 "XMAC_HASH_TBL11_REG", 298 "XMAC_HASH_TBL12_REG", 299 "XMAC_HASH_TBL13_REG", 300 "XMAC_HASH_TBL14_REG", 301 "XMAC_HASH_TBL15_REG", 302 "XMAC_HOST_INF0_REG", 303 "XMAC_HOST_INF1_REG", 304 "XMAC_HOST_INF2_REG", 305 "XMAC_HOST_INF3_REG", 306 "XMAC_HOST_INF4_REG", 307 "XMAC_HOST_INF5_REG", 308 "XMAC_HOST_INF6_REG", 309 "XMAC_HOST_INF7_REG", 310 "XMAC_HOST_INF8_REG", 311 "XMAC_HOST_INF9_REG", 312 "XMAC_HOST_INF10_REG", 313 "XMAC_HOST_INF11_REG", 314 "XMAC_HOST_INF12_REG", 315 "XMAC_HOST_INF13_REG", 316 "XMAC_HOST_INF14_REG", 317 "XMAC_HOST_INF15_REG", 318 "XMAC_HOST_INF16_REG", 319 "XMAC_HOST_INF17_REG", 320 "XMAC_HOST_INF18_REG", 321 "XMAC_HOST_INF19_REG", 322 "XMAC_PA_DATA0_REG", 323 "XMAC_PA_DATA1_REG", 324 "XMAC_DEBUG_SEL_REG", 325 "XMAC_TRAINING_VECT_REG", 326 }; 327 328 uint64_t bmac_offset[] = { 329 BTXMAC_SW_RST_REG, 330 BRXMAC_SW_RST_REG, 331 MAC_SEND_PAUSE_REG, 332 BTXMAC_STATUS_REG, 333 BRXMAC_STATUS_REG, 334 BMAC_CTRL_STAT_REG, 335 BTXMAC_STAT_MSK_REG, 336 BRXMAC_STAT_MSK_REG, 337 BMAC_C_S_MSK_REG, 338 TXMAC_CONFIG_REG, 339 RXMAC_CONFIG_REG, 340 MAC_CTRL_CONFIG_REG, 341 MAC_XIF_CONFIG_REG, 342 BMAC_MIN_REG, 343 BMAC_MAX_REG, 344 MAC_PA_SIZE_REG, 345 MAC_CTRL_TYPE_REG, 346 BMAC_ADDR0_REG, 347 BMAC_ADDR1_REG, 348 BMAC_ADDR2_REG, 349 BMAC_ADDR3_REG, 350 BMAC_ADDR4_REG, 351 BMAC_ADDR5_REG, 352 BMAC_ADDR6_REG, 353 BMAC_ADDR7_REG, 354 BMAC_ADDR8_REG, 355 BMAC_ADDR9_REG, 356 BMAC_ADDR10_REG, 357 BMAC_ADDR11_REG, 358 BMAC_ADDR12_REG, 359 BMAC_ADDR13_REG, 360 BMAC_ADDR14_REG, 361 BMAC_ADDR15_REG, 362 BMAC_ADDR16_REG, 363 BMAC_ADDR17_REG, 364 BMAC_ADDR18_REG, 365 BMAC_ADDR19_REG, 366 BMAC_ADDR20_REG, 367 BMAC_ADDR21_REG, 368 BMAC_ADDR22_REG, 369 BMAC_ADDR23_REG, 370 MAC_FC_ADDR0_REG, 371 MAC_FC_ADDR1_REG, 372 MAC_FC_ADDR2_REG, 373 MAC_ADDR_FILT0_REG, 374 MAC_ADDR_FILT1_REG, 375 MAC_ADDR_FILT2_REG, 376 MAC_ADDR_FILT12_MASK_REG, 377 MAC_ADDR_FILT00_MASK_REG, 378 MAC_HASH_TBL0_REG, 379 MAC_HASH_TBL1_REG, 380 MAC_HASH_TBL2_REG, 381 MAC_HASH_TBL3_REG, 382 MAC_HASH_TBL4_REG, 383 MAC_HASH_TBL5_REG, 384 MAC_HASH_TBL6_REG, 385 MAC_HASH_TBL7_REG, 386 MAC_HASH_TBL8_REG, 387 MAC_HASH_TBL9_REG, 388 MAC_HASH_TBL10_REG, 389 MAC_HASH_TBL11_REG, 390 MAC_HASH_TBL12_REG, 391 MAC_HASH_TBL13_REG, 392 MAC_HASH_TBL14_REG, 393 MAC_HASH_TBL15_REG, 394 RXMAC_FRM_CNT_REG, 395 MAC_LEN_ER_CNT_REG, 396 BMAC_AL_ER_CNT_REG, 397 BMAC_CRC_ER_CNT_REG, 398 BMAC_CD_VIO_CNT_REG, 399 BMAC_SM_REG, 400 BMAC_ALTAD_CMPEN_REG, 401 BMAC_HOST_INF0_REG, 402 BMAC_HOST_INF1_REG, 403 BMAC_HOST_INF2_REG, 404 BMAC_HOST_INF3_REG, 405 BMAC_HOST_INF4_REG, 406 BMAC_HOST_INF5_REG, 407 BMAC_HOST_INF6_REG, 408 BMAC_HOST_INF7_REG, 409 BMAC_HOST_INF8_REG, 410 BTXMAC_BYTE_CNT_REG, 411 BTXMAC_FRM_CNT_REG, 412 BRXMAC_BYTE_CNT_REG, 413 }; 414 415 const char *bmac_name[] = { 416 "BTXMAC_SW_RST_REG", 417 "BRXMAC_SW_RST_REG", 418 "MAC_SEND_PAUSE_REG", 419 "BTXMAC_STATUS_REG", 420 "BRXMAC_STATUS_REG", 421 "BMAC_CTRL_STAT_REG", 422 "BTXMAC_STAT_MSK_REG", 423 "BRXMAC_STAT_MSK_REG", 424 "BMAC_C_S_MSK_REG", 425 "TXMAC_CONFIG_REG", 426 "RXMAC_CONFIG_REG", 427 "MAC_CTRL_CONFIG_REG", 428 "MAC_XIF_CONFIG_REG", 429 "BMAC_MIN_REG", 430 "BMAC_MAX_REG", 431 "MAC_PA_SIZE_REG", 432 "MAC_CTRL_TYPE_REG", 433 "BMAC_ADDR0_REG", 434 "BMAC_ADDR1_REG", 435 "BMAC_ADDR2_REG", 436 "BMAC_ADDR3_REG", 437 "BMAC_ADDR4_REG", 438 "BMAC_ADDR5_REG", 439 "BMAC_ADDR6_REG", 440 "BMAC_ADDR7_REG", 441 "BMAC_ADDR8_REG", 442 "BMAC_ADDR9_REG", 443 "BMAC_ADDR10_REG", 444 "BMAC_ADDR11_REG", 445 "BMAC_ADDR12_REG", 446 "BMAC_ADDR13_REG", 447 "BMAC_ADDR14_REG", 448 "BMAC_ADDR15_REG", 449 "BMAC_ADDR16_REG", 450 "BMAC_ADDR17_REG", 451 "BMAC_ADDR18_REG", 452 "BMAC_ADDR19_REG", 453 "BMAC_ADDR20_REG", 454 "BMAC_ADDR21_REG", 455 "BMAC_ADDR22_REG", 456 "BMAC_ADDR23_REG", 457 "MAC_FC_ADDR0_REG", 458 "MAC_FC_ADDR1_REG", 459 "MAC_FC_ADDR2_REG", 460 "MAC_ADDR_FILT0_REG", 461 "MAC_ADDR_FILT1_REG", 462 "MAC_ADDR_FILT2_REG", 463 "MAC_ADDR_FILT12_MASK_REG", 464 "MAC_ADDR_FILT00_MASK_REG", 465 "MAC_HASH_TBL0_REG", 466 "MAC_HASH_TBL1_REG", 467 "MAC_HASH_TBL2_REG", 468 "MAC_HASH_TBL3_REG", 469 "MAC_HASH_TBL4_REG", 470 "MAC_HASH_TBL5_REG", 471 "MAC_HASH_TBL6_REG", 472 "MAC_HASH_TBL7_REG", 473 "MAC_HASH_TBL8_REG", 474 "MAC_HASH_TBL9_REG", 475 "MAC_HASH_TBL10_REG", 476 "MAC_HASH_TBL11_REG", 477 "MAC_HASH_TBL12_REG", 478 "MAC_HASH_TBL13_REG", 479 "MAC_HASH_TBL14_REG", 480 "MAC_HASH_TBL15_REG", 481 "RXMAC_FRM_CNT_REG", 482 "MAC_LEN_ER_CNT_REG", 483 "BMAC_AL_ER_CNT_REG", 484 "BMAC_CRC_ER_CNT_REG", 485 "BMAC_CD_VIO_CNT_REG", 486 "BMAC_SM_REG", 487 "BMAC_ALTAD_CMPEN_REG", 488 "BMAC_HOST_INF0_REG", 489 "BMAC_HOST_INF1_REG", 490 "BMAC_HOST_INF2_REG", 491 "BMAC_HOST_INF3_REG", 492 "BMAC_HOST_INF4_REG", 493 "BMAC_HOST_INF5_REG", 494 "BMAC_HOST_INF6_REG", 495 "BMAC_HOST_INF7_REG", 496 "BMAC_HOST_INF8_REG", 497 "BTXMAC_BYTE_CNT_REG", 498 "BTXMAC_FRM_CNT_REG", 499 "BRXMAC_BYTE_CNT_REG", 500 }; 501 502 npi_status_t 503 npi_mac_dump_regs(npi_handle_t handle, uint8_t port) 504 { 505 506 uint64_t value; 507 int num_regs, i; 508 509 ASSERT(IS_PORT_NUM_VALID(port)); 510 511 switch (port) { 512 case 0: 513 case 1: 514 num_regs = sizeof (xmac_offset) / sizeof (uint64_t); 515 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 516 "\nXMAC Register Dump for port %d\n", 517 port)); 518 for (i = 0; i < num_regs; i++) { 519 #if defined(__i386) 520 XMAC_REG_RD(handle, port, (uint32_t)xmac_offset[i], 521 &value); 522 #else 523 XMAC_REG_RD(handle, port, xmac_offset[i], &value); 524 #endif 525 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 526 "%08llx %s\t %08llx \n", 527 (XMAC_REG_ADDR((port), (xmac_offset[i]))), 528 xmac_name[i], value)); 529 } 530 531 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 532 "\n XMAC Register Dump for port %d done\n", 533 port)); 534 break; 535 536 case 2: 537 case 3: 538 num_regs = sizeof (bmac_offset) / sizeof (uint64_t); 539 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 540 "\nBMAC Register Dump for port %d\n", 541 port)); 542 for (i = 0; i < num_regs; i++) { 543 #if defined(__i386) 544 BMAC_REG_RD(handle, port, (uint32_t)bmac_offset[i], 545 &value); 546 #else 547 BMAC_REG_RD(handle, port, bmac_offset[i], &value); 548 #endif 549 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 550 "%08llx %s\t %08llx \n", 551 (BMAC_REG_ADDR((port), (bmac_offset[i]))), 552 bmac_name[i], value)); 553 } 554 555 NPI_REG_DUMP_MSG((handle.function, NPI_REG_CTL, 556 "\n BMAC Register Dump for port %d done\n", 557 port)); 558 break; 559 } 560 561 return (NPI_SUCCESS); 562 } 563 564 npi_status_t 565 npi_mac_pcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 566 { 567 pcs_cfg_t pcs_cfg; 568 569 ASSERT(IS_PORT_NUM_VALID(portn)); 570 571 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.value); 572 pcs_cfg.bits.w0.mask = 0; 573 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.value); 574 575 return (NPI_SUCCESS); 576 } 577 578 npi_status_t 579 npi_mac_pcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 580 { 581 pcs_cfg_t pcs_cfg; 582 583 ASSERT(IS_PORT_NUM_VALID(portn)); 584 585 PCS_REG_RD(handle, portn, PCS_CONFIG_REG, &pcs_cfg.val.lsw); 586 pcs_cfg.bits.w0.mask = 1; 587 PCS_REG_WR(handle, portn, PCS_CONFIG_REG, pcs_cfg.val.lsw); 588 589 return (NPI_SUCCESS); 590 } 591 592 npi_status_t 593 npi_xmac_xpcs_link_intr_enable(npi_handle_t handle, uint8_t portn) 594 { 595 xpcs_stat1_t xpcs_mask1; 596 597 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 598 599 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 600 xpcs_mask1.bits.w0.csr_rx_link_stat = 1; 601 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 602 603 return (NPI_SUCCESS); 604 } 605 606 npi_status_t 607 npi_xmac_xpcs_link_intr_disable(npi_handle_t handle, uint8_t portn) 608 { 609 xpcs_stat1_t xpcs_mask1; 610 611 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 612 613 XPCS_REG_RD(handle, portn, XPCS_MASK_1_REG, &xpcs_mask1.val.lsw); 614 xpcs_mask1.bits.w0.csr_rx_link_stat = 0; 615 XPCS_REG_WR(handle, portn, XPCS_MASK_1_REG, xpcs_mask1.val.lsw); 616 617 return (NPI_SUCCESS); 618 } 619 620 npi_status_t 621 npi_mac_mif_link_intr_disable(npi_handle_t handle, uint8_t portn) 622 { 623 mif_cfg_t mif_cfg; 624 625 ASSERT(IS_PORT_NUM_VALID(portn)); 626 627 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.val.lsw); 628 629 mif_cfg.bits.w0.phy_addr = portn; 630 mif_cfg.bits.w0.poll_en = 0; 631 632 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.val.lsw); 633 634 NXGE_DELAY(20); 635 636 return (NPI_SUCCESS); 637 } 638 639 npi_status_t 640 npi_mac_hashtab_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 641 uint8_t entryn, uint16_t *data) 642 { 643 uint64_t val; 644 645 ASSERT((op == OP_GET) || (op == OP_SET)); 646 ASSERT(IS_PORT_NUM_VALID(portn)); 647 648 ASSERT(entryn < MAC_MAX_HASH_ENTRY); 649 if (entryn >= MAC_MAX_HASH_ENTRY) { 650 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 651 " npi_mac_hashtab_entry" 652 " Invalid Input: entryn <0x%x>", 653 entryn)); 654 return (NPI_FAILURE | NPI_MAC_HASHTAB_ENTRY_INVALID(portn)); 655 } 656 657 if (op == OP_SET) { 658 val = *data; 659 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 660 XMAC_REG_WR(handle, portn, 661 XMAC_HASH_TBLN_REG_ADDR(entryn), val); 662 } else { 663 BMAC_REG_WR(handle, portn, 664 BMAC_HASH_TBLN_REG_ADDR(entryn), val); 665 } 666 } else { 667 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 668 XMAC_REG_RD(handle, portn, 669 XMAC_HASH_TBLN_REG_ADDR(entryn), &val); 670 } else { 671 BMAC_REG_RD(handle, portn, 672 BMAC_HASH_TBLN_REG_ADDR(entryn), &val); 673 } 674 *data = val & 0xFFFF; 675 } 676 677 return (NPI_SUCCESS); 678 } 679 680 npi_status_t 681 npi_mac_hostinfo_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 682 uint8_t entryn, hostinfo_t *hostinfo) 683 { 684 ASSERT((op == OP_GET) || (op == OP_SET)); 685 ASSERT(IS_PORT_NUM_VALID(portn)); 686 687 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 688 ASSERT(entryn < XMAC_MAX_HOST_INFO_ENTRY); 689 if (entryn >= XMAC_MAX_HOST_INFO_ENTRY) { 690 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 691 " npi_mac_hostinfo_entry" 692 " Invalid Input: entryn <0x%x>", 693 entryn)); 694 return (NPI_FAILURE | 695 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 696 } 697 } else { 698 ASSERT(entryn < BMAC_MAX_HOST_INFO_ENTRY); 699 if (entryn >= BMAC_MAX_HOST_INFO_ENTRY) { 700 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 701 " npi_mac_hostinfo_entry" 702 " Invalid Input: entryn <0x%x>", 703 entryn)); 704 return (NPI_FAILURE | 705 NPI_MAC_HOSTINFO_ENTRY_INVALID(portn)); 706 } 707 } 708 709 if (op == OP_SET) { 710 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 711 XMAC_REG_WR(handle, portn, 712 XMAC_HOST_INFN_REG_ADDR(entryn), 713 hostinfo->value); 714 } else { 715 BMAC_REG_WR(handle, portn, 716 BMAC_HOST_INFN_REG_ADDR(entryn), 717 hostinfo->value); 718 } 719 } else { 720 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 721 XMAC_REG_RD(handle, portn, 722 XMAC_HOST_INFN_REG_ADDR(entryn), 723 &hostinfo->value); 724 } else { 725 BMAC_REG_RD(handle, portn, 726 BMAC_HOST_INFN_REG_ADDR(entryn), 727 &hostinfo->value); 728 } 729 } 730 731 return (NPI_SUCCESS); 732 } 733 734 npi_status_t 735 npi_mac_altaddr_enable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 736 { 737 uint64_t val; 738 739 ASSERT(IS_PORT_NUM_VALID(portn)); 740 741 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 742 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 743 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 744 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 745 " npi_mac_altaddr_enable" 746 " Invalid Input: addrn <0x%x>", 747 addrn)); 748 return (NPI_FAILURE | 749 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 750 } 751 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 752 val |= (1 << addrn); 753 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 754 } else { 755 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 756 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 757 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 758 " npi_mac_altaddr_enable" 759 " Invalid Input: addrn <0x%x>", 760 addrn)); 761 return (NPI_FAILURE | 762 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 763 } 764 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 765 val |= (1 << addrn); 766 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 767 } 768 769 return (NPI_SUCCESS); 770 } 771 772 /* 773 * While all bits of XMAC_ADDR_CMPEN_REG are for alternate MAC addresses, 774 * bit0 of BMAC_ALTAD_CMPEN_REG is for unique MAC address. 775 */ 776 npi_status_t 777 npi_mac_altaddr_disable(npi_handle_t handle, uint8_t portn, uint8_t addrn) 778 { 779 uint64_t val; 780 781 ASSERT(IS_PORT_NUM_VALID(portn)); 782 783 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 784 ASSERT(addrn <= XMAC_MAX_ALT_ADDR_ENTRY); 785 if (addrn > XMAC_MAX_ALT_ADDR_ENTRY) { 786 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 787 " npi_mac_altaddr_disable" 788 " Invalid Input: addrn <0x%x>", 789 addrn)); 790 return (NPI_FAILURE | 791 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 792 } 793 XMAC_REG_RD(handle, portn, XMAC_ADDR_CMPEN_REG, &val); 794 val &= ~(1 << addrn); 795 XMAC_REG_WR(handle, portn, XMAC_ADDR_CMPEN_REG, val); 796 } else { 797 ASSERT(addrn <= BMAC_MAX_ALT_ADDR_ENTRY); 798 if (addrn > BMAC_MAX_ALT_ADDR_ENTRY) { 799 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 800 " npi_mac_altaddr_disable" 801 " Invalid Input: addrn <0x%x>", 802 addrn)); 803 return (NPI_FAILURE | 804 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 805 } 806 BMAC_REG_RD(handle, portn, BMAC_ALTAD_CMPEN_REG, &val); 807 val &= ~(1 << addrn); 808 BMAC_REG_WR(handle, portn, BMAC_ALTAD_CMPEN_REG, val); 809 } 810 811 return (NPI_SUCCESS); 812 } 813 814 npi_status_t 815 npi_mac_altaddr_entry(npi_handle_t handle, io_op_t op, uint8_t portn, 816 uint8_t entryn, npi_mac_addr_t *data) 817 { 818 uint64_t val0, val1, val2; 819 820 ASSERT(IS_PORT_NUM_VALID(portn)); 821 ASSERT((op == OP_GET) || (op == OP_SET)); 822 823 if ((portn == XMAC_PORT_0) || (portn == XMAC_PORT_1)) { 824 ASSERT(entryn <= XMAC_MAX_ALT_ADDR_ENTRY); 825 if (entryn > XMAC_MAX_ALT_ADDR_ENTRY) { 826 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 827 " npi_mac_altaddr_entry" 828 " Invalid Input: entryn <0x%x>", 829 entryn)); 830 return (NPI_FAILURE | 831 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 832 } 833 if (op == OP_SET) { 834 val0 = data->w0; 835 val1 = data->w1; 836 val2 = data->w2; 837 XMAC_REG_WR(handle, portn, 838 XMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 839 XMAC_REG_WR(handle, portn, 840 XMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 841 XMAC_REG_WR(handle, portn, 842 XMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 843 } else { 844 XMAC_REG_RD(handle, portn, 845 XMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 846 XMAC_REG_RD(handle, portn, 847 XMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 848 XMAC_REG_RD(handle, portn, 849 XMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 850 data->w0 = val0 & 0xFFFF; 851 data->w1 = val1 & 0xFFFF; 852 data->w2 = val2 & 0xFFFF; 853 } 854 } else { 855 ASSERT(entryn <= BMAC_MAX_ALT_ADDR_ENTRY); 856 if (entryn > BMAC_MAX_ALT_ADDR_ENTRY) { 857 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 858 " npi_mac_altaddr_entry" 859 " Invalid Input: entryn <0x%x>", 860 entryn)); 861 return (NPI_FAILURE | 862 NPI_MAC_ALT_ADDR_ENTRY_INVALID(portn)); 863 } 864 if (op == OP_SET) { 865 val0 = data->w0; 866 val1 = data->w1; 867 val2 = data->w2; 868 BMAC_REG_WR(handle, portn, 869 BMAC_ALT_ADDR0N_REG_ADDR(entryn), val0); 870 BMAC_REG_WR(handle, portn, 871 BMAC_ALT_ADDR1N_REG_ADDR(entryn), val1); 872 BMAC_REG_WR(handle, portn, 873 BMAC_ALT_ADDR2N_REG_ADDR(entryn), val2); 874 } else { 875 BMAC_REG_RD(handle, portn, 876 BMAC_ALT_ADDR0N_REG_ADDR(entryn), &val0); 877 BMAC_REG_RD(handle, portn, 878 BMAC_ALT_ADDR1N_REG_ADDR(entryn), &val1); 879 BMAC_REG_RD(handle, portn, 880 BMAC_ALT_ADDR2N_REG_ADDR(entryn), &val2); 881 data->w0 = val0 & 0xFFFF; 882 data->w1 = val1 & 0xFFFF; 883 data->w2 = val2 & 0xFFFF; 884 } 885 } 886 887 return (NPI_SUCCESS); 888 } 889 890 npi_status_t 891 npi_mac_port_attr(npi_handle_t handle, io_op_t op, uint8_t portn, 892 npi_attr_t *attrp) 893 { 894 uint64_t val = 0; 895 uint32_t attr; 896 897 ASSERT(IS_PORT_NUM_VALID(portn)); 898 ASSERT((op == OP_GET) || (op == OP_SET)); 899 900 switch (attrp->type) { 901 case MAC_PORT_MODE: 902 switch (portn) { 903 case XMAC_PORT_0: 904 case XMAC_PORT_1: 905 if (op == OP_SET) { 906 attr = attrp->idata[0]; 907 ASSERT((attr == MAC_MII_MODE) || \ 908 (attr == MAC_GMII_MODE) || \ 909 (attr == MAC_XGMII_MODE)); 910 if ((attr != MAC_MII_MODE) && 911 (attr != MAC_GMII_MODE) && 912 (attr != MAC_XGMII_MODE)) { 913 NPI_ERROR_MSG((handle.function, 914 NPI_ERR_CTL, 915 " npi_mac_port_attr" 916 " Invalid Input:" 917 " MAC_PORT_MODE <0x%x>", 918 attr)); 919 return (NPI_FAILURE | 920 NPI_MAC_PORT_ATTR_INVALID(portn)); 921 } 922 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 923 &val); 924 val &= ~XMAC_XIF_MII_MODE_MASK; 925 switch (attr) { 926 case MAC_MII_MODE: 927 val |= (XMAC_XIF_MII_MODE << 928 XMAC_XIF_MII_MODE_SHIFT); 929 break; 930 case MAC_GMII_MODE: 931 val |= (XMAC_XIF_GMII_MODE << 932 XMAC_XIF_MII_MODE_SHIFT); 933 break; 934 case MAC_XGMII_MODE: 935 val |= (XMAC_XIF_XGMII_MODE << 936 XMAC_XIF_MII_MODE_SHIFT); 937 break; 938 default: 939 return (NPI_FAILURE | 940 NPI_MAC_PORT_ATTR_INVALID(portn)); 941 } 942 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, 943 val); 944 } else { 945 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, 946 &val); 947 val &= XMAC_XIF_MII_MODE_MASK; 948 attr = val >> XMAC_XIF_MII_MODE_SHIFT; 949 attrp->odata[0] = attr; 950 } 951 break; 952 case BMAC_PORT_0: 953 case BMAC_PORT_1: 954 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 955 " npi_mac_port_attr" 956 " Invalid Input:" 957 " MAC_PORT_MODE <0x%x>", 958 attrp->type)); 959 return (NPI_FAILURE | 960 NPI_MAC_PORT_ATTR_INVALID(portn)); 961 default: 962 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 963 } 964 break; 965 966 case MAC_PORT_FRAME_SIZE: { 967 uint32_t min_fsize; 968 uint32_t max_fsize; 969 970 switch (portn) { 971 case XMAC_PORT_0: 972 case XMAC_PORT_1: 973 if (op == OP_SET) { 974 min_fsize = attrp->idata[0]; 975 max_fsize = attrp->idata[1]; 976 ASSERT((min_fsize & \ 977 ~XMAC_MIN_TX_FRM_SZ_MASK) == 0); 978 if ((min_fsize & ~XMAC_MIN_TX_FRM_SZ_MASK) 979 != 0) { 980 NPI_ERROR_MSG((handle.function, 981 NPI_ERR_CTL, 982 " npi_mac_port_attr" 983 " MAC_PORT_FRAME_SIZE:" 984 " Invalid Input:" 985 " xmac_min_fsize <0x%x>", 986 min_fsize)); 987 return (NPI_FAILURE | 988 NPI_MAC_PORT_ATTR_INVALID(portn)); 989 } 990 ASSERT((max_fsize & \ 991 ~XMAC_MAX_FRM_SZ_MASK) == 0); 992 if ((max_fsize & ~XMAC_MAX_FRM_SZ_MASK) 993 != 0) { 994 NPI_ERROR_MSG((handle.function, 995 NPI_ERR_CTL, 996 " npi_mac_port_attr" 997 " MAC_PORT_FRAME_SIZE:" 998 " Invalid Input:" 999 " xmac_max_fsize <0x%x>", 1000 max_fsize)); 1001 return (NPI_FAILURE | 1002 NPI_MAC_PORT_ATTR_INVALID(portn)); 1003 } 1004 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1005 val &= ~(XMAC_MIN_TX_FRM_SZ_MASK | 1006 XMAC_MIN_RX_FRM_SZ_MASK); 1007 val |= (min_fsize << XMAC_MIN_TX_FRM_SZ_SHIFT); 1008 val |= (min_fsize << XMAC_MIN_RX_FRM_SZ_SHIFT); 1009 XMAC_REG_WR(handle, portn, XMAC_MIN_REG, val); 1010 XMAC_REG_WR(handle, portn, XMAC_MAX_REG, 1011 max_fsize); 1012 } else { 1013 XMAC_REG_RD(handle, portn, XMAC_MIN_REG, &val); 1014 min_fsize = (val & XMAC_MIN_TX_FRM_SZ_MASK) 1015 >> XMAC_MIN_TX_FRM_SZ_SHIFT; 1016 XMAC_REG_RD(handle, portn, XMAC_MAX_REG, &val); 1017 max_fsize = val & XMAC_MAX_FRM_SZ_MASK; 1018 attrp->odata[0] = min_fsize; 1019 attrp->odata[1] = max_fsize; 1020 } 1021 break; 1022 case BMAC_PORT_0: 1023 case BMAC_PORT_1: 1024 if (op == OP_SET) { 1025 min_fsize = attrp->idata[0]; 1026 max_fsize = attrp->idata[1]; 1027 ASSERT((min_fsize & ~BMAC_MIN_FRAME_MASK) == 0); 1028 if ((min_fsize & ~BMAC_MIN_FRAME_MASK) 1029 != 0) { 1030 NPI_ERROR_MSG((handle.function, 1031 NPI_ERR_CTL, 1032 " npi_mac_port_attr" 1033 " MAC_FRAME_SIZE:" 1034 " Invalid Input:" 1035 " bmac_min_fsize <0x%x>", 1036 min_fsize)); 1037 return (NPI_FAILURE | 1038 NPI_MAC_PORT_ATTR_INVALID(portn)); 1039 } 1040 ASSERT((max_fsize & ~BMAC_MAX_FRAME_MASK) == 0); 1041 if ((max_fsize & ~BMAC_MAX_FRAME_MASK) 1042 != 0) { 1043 NPI_ERROR_MSG((handle.function, 1044 NPI_ERR_CTL, 1045 " npi_mac_port_attr" 1046 " MAC_FRAME_SIZE:" 1047 " Invalid Input:" 1048 " bmac_max_fsize <0x%x>", 1049 max_fsize)); 1050 return (NPI_FAILURE | 1051 NPI_MAC_PORT_ATTR_INVALID(portn)); 1052 } 1053 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1054 val &= ~BMAC_MAX_FRAME_MASK; 1055 if (max_fsize <= MAX_FRAME_SZ1) 1056 val |= MAX_FRAME_SZ1; 1057 else if ((max_fsize > MAX_FRAME_SZ1) && 1058 (max_fsize <= MAX_FRAME_SZ2)) 1059 val |= MAX_FRAME_SZ2; 1060 else if ((max_fsize > MAX_FRAME_SZ2) && 1061 (max_fsize <= MAX_FRAME_SZ3)) 1062 val |= MAX_FRAME_SZ3; 1063 else if ((max_fsize > MAX_FRAME_SZ3) && 1064 (max_fsize <= MAX_FRAME_SZ4)) 1065 val |= MAX_FRAME_SZ4; 1066 else if ((max_fsize > MAX_FRAME_SZ4) && 1067 (max_fsize <= MAX_FRAME_SZ5)) 1068 val |= MAX_FRAME_SZ5; 1069 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1070 BMAC_REG_WR(handle, portn, BMAC_MIN_REG, 1071 min_fsize); 1072 } else { 1073 BMAC_REG_RD(handle, portn, BMAC_MIN_REG, &val); 1074 min_fsize = val & BMAC_MIN_FRAME_MASK; 1075 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1076 max_fsize = val & BMAC_MAX_FRAME_MASK; 1077 attrp->odata[0] = min_fsize; 1078 attrp->odata[1] = max_fsize; 1079 } 1080 break; 1081 default: 1082 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1083 } 1084 break; 1085 } 1086 1087 case BMAC_PORT_MAX_BURST_SIZE: { 1088 uint32_t burst_size; 1089 switch (portn) { 1090 case XMAC_PORT_0: 1091 case XMAC_PORT_1: 1092 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1093 " npi_mac_port_attr" 1094 " BMAC_PORT_MAX_BURST_SIZE:" 1095 " Invalid Input: portn <%d>", 1096 portn)); 1097 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1098 case BMAC_PORT_0: 1099 case BMAC_PORT_1: 1100 /* NOTE: Not used in Full duplex mode */ 1101 if (op == OP_SET) { 1102 burst_size = attrp->idata[0]; 1103 ASSERT((burst_size & ~0x7FFF) == 0); 1104 if ((burst_size & ~0x7FFF) != 0) { 1105 NPI_ERROR_MSG((handle.function, 1106 NPI_ERR_CTL, 1107 " npi_mac_port_attr" 1108 " BMAC_MAX_BURST_SIZE:" 1109 " Invalid Input:" 1110 " burst_size <0x%x>", 1111 burst_size)); 1112 return (NPI_FAILURE | 1113 NPI_MAC_PORT_ATTR_INVALID(portn)); 1114 } 1115 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1116 val &= ~BMAC_MAX_BURST_MASK; 1117 val |= (burst_size << BMAC_MAX_BURST_SHIFT); 1118 BMAC_REG_WR(handle, portn, BMAC_MAX_REG, val); 1119 } else { 1120 BMAC_REG_RD(handle, portn, BMAC_MAX_REG, &val); 1121 burst_size = (val & BMAC_MAX_BURST_MASK) 1122 >> BMAC_MAX_BURST_SHIFT; 1123 attrp->odata[0] = burst_size; 1124 } 1125 break; 1126 default: 1127 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1128 } 1129 break; 1130 } 1131 1132 case BMAC_PORT_PA_SIZE: { 1133 uint32_t pa_size; 1134 switch (portn) { 1135 case XMAC_PORT_0: 1136 case XMAC_PORT_1: 1137 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1138 " npi_mac_port_attr" 1139 " BMAC_PORT_PA_SIZE:" 1140 " Invalid Input: portn <%d>", 1141 portn)); 1142 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1143 case BMAC_PORT_0: 1144 case BMAC_PORT_1: 1145 if (op == OP_SET) { 1146 pa_size = attrp->idata[0]; 1147 ASSERT((pa_size & ~0x3FF) == 0); 1148 if ((pa_size & ~0x3FF) != 0) { 1149 NPI_ERROR_MSG((handle.function, 1150 NPI_ERR_CTL, 1151 " npi_mac_port_attr" 1152 " BMAC_PORT_PA_SIZE:" 1153 " Invalid Input: pa_size <0x%x>", 1154 pa_size)); 1155 1156 return (NPI_FAILURE | 1157 NPI_MAC_PORT_ATTR_INVALID(portn)); 1158 } 1159 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1160 &val); 1161 val &= ~BMAC_PA_SIZE_MASK; 1162 val |= (pa_size << 0); 1163 BMAC_REG_WR(handle, portn, MAC_PA_SIZE_REG, 1164 val); 1165 } else { 1166 BMAC_REG_RD(handle, portn, MAC_PA_SIZE_REG, 1167 &val); 1168 pa_size = (val & BMAC_PA_SIZE_MASK) >> 0; 1169 attrp->odata[0] = pa_size; 1170 } 1171 break; 1172 default: 1173 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1174 } 1175 break; 1176 } 1177 1178 case BMAC_PORT_CTRL_TYPE: { 1179 uint32_t ctrl_type; 1180 switch (portn) { 1181 case XMAC_PORT_0: 1182 case XMAC_PORT_1: 1183 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1184 " npi_mac_port_attr" 1185 " BMAC_PORT_CTRL_TYPE:" 1186 " Invalid Input: portn <%d>", 1187 portn)); 1188 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1189 case BMAC_PORT_0: 1190 case BMAC_PORT_1: 1191 if (op == OP_SET) { 1192 ctrl_type = attrp->idata[0]; 1193 ASSERT((ctrl_type & ~0xFFFF) == 0); 1194 if ((ctrl_type & ~0xFFFF) != 0) { 1195 NPI_ERROR_MSG((handle.function, 1196 NPI_ERR_CTL, 1197 " npi_mac_port_attr" 1198 " BMAC_PORT_CTRL_TYPE:" 1199 " Invalid Input:" 1200 " ctrl_type <0x%x>", 1201 ctrl_type)); 1202 return (NPI_FAILURE | 1203 NPI_MAC_PORT_ATTR_INVALID(portn)); 1204 } 1205 BMAC_REG_WR(handle, portn, MAC_CTRL_TYPE_REG, 1206 val); 1207 } else { 1208 BMAC_REG_RD(handle, portn, MAC_CTRL_TYPE_REG, 1209 &val); 1210 ctrl_type = (val & 0xFFFF); 1211 attrp->odata[0] = ctrl_type; 1212 } 1213 break; 1214 default: 1215 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1216 } 1217 break; 1218 } 1219 1220 case XMAC_10G_PORT_IPG: 1221 { 1222 uint32_t ipg0; 1223 1224 switch (portn) { 1225 case XMAC_PORT_0: 1226 case XMAC_PORT_1: 1227 if (op == OP_SET) { 1228 ipg0 = attrp->idata[0]; 1229 ASSERT((ipg0 == XGMII_IPG_12_15) || \ 1230 (ipg0 == XGMII_IPG_16_19) || \ 1231 (ipg0 == XGMII_IPG_20_23)); 1232 if ((ipg0 != XGMII_IPG_12_15) && 1233 (ipg0 != XGMII_IPG_16_19) && 1234 (ipg0 != XGMII_IPG_20_23)) { 1235 NPI_ERROR_MSG((handle.function, 1236 NPI_ERR_CTL, 1237 " npi_mac_port_attr" 1238 " MAC_10G_PORT_IPG:" 1239 " Invalid Input:" 1240 " xgmii_ipg <0x%x>", 1241 ipg0)); 1242 return (NPI_FAILURE | 1243 NPI_MAC_PORT_ATTR_INVALID(portn)); 1244 } 1245 1246 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1247 val &= ~(XMAC_IPG_VALUE_MASK | 1248 XMAC_IPG_VALUE1_MASK); 1249 1250 switch (ipg0) { 1251 case XGMII_IPG_12_15: 1252 val |= (IPG_12_15_BYTE << 1253 XMAC_IPG_VALUE_SHIFT); 1254 break; 1255 case XGMII_IPG_16_19: 1256 val |= (IPG_16_19_BYTE << 1257 XMAC_IPG_VALUE_SHIFT); 1258 break; 1259 case XGMII_IPG_20_23: 1260 val |= (IPG_20_23_BYTE << 1261 XMAC_IPG_VALUE_SHIFT); 1262 break; 1263 default: 1264 return (NPI_FAILURE | 1265 NPI_MAC_PORT_ATTR_INVALID(portn)); 1266 } 1267 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1268 } else { 1269 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1270 ipg0 = (val & XMAC_IPG_VALUE_MASK) >> 1271 XMAC_IPG_VALUE_SHIFT; 1272 switch (ipg0) { 1273 case IPG_12_15_BYTE: 1274 attrp->odata[0] = XGMII_IPG_12_15; 1275 break; 1276 case IPG_16_19_BYTE: 1277 attrp->odata[0] = XGMII_IPG_16_19; 1278 break; 1279 case IPG_20_23_BYTE: 1280 attrp->odata[0] = XGMII_IPG_20_23; 1281 break; 1282 default: 1283 return (NPI_FAILURE | 1284 NPI_MAC_PORT_ATTR_INVALID(portn)); 1285 } 1286 } 1287 break; 1288 case BMAC_PORT_0: 1289 case BMAC_PORT_1: 1290 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1291 " npi_mac_port_attr" "MAC_PORT_IPG:" 1292 " Invalid Input: portn <%d>", 1293 portn)); 1294 /* FALLTHROUGH */ 1295 default: 1296 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1297 } 1298 break; 1299 } 1300 1301 case XMAC_PORT_IPG: 1302 { 1303 uint32_t ipg1; 1304 switch (portn) { 1305 case XMAC_PORT_0: 1306 case XMAC_PORT_1: 1307 if (op == OP_SET) { 1308 ipg1 = attrp->idata[0]; 1309 ASSERT((ipg1 == MII_GMII_IPG_12) || \ 1310 (ipg1 == MII_GMII_IPG_13) || \ 1311 (ipg1 == MII_GMII_IPG_14) || \ 1312 (ipg1 == MII_GMII_IPG_15) || \ 1313 (ipg1 == MII_GMII_IPG_16)); 1314 if ((ipg1 != MII_GMII_IPG_12) && 1315 (ipg1 != MII_GMII_IPG_13) && 1316 (ipg1 != MII_GMII_IPG_14) && 1317 (ipg1 != MII_GMII_IPG_15) && 1318 (ipg1 != MII_GMII_IPG_16)) { 1319 NPI_ERROR_MSG((handle.function, 1320 NPI_ERR_CTL, 1321 " npi_mac_port_attr" 1322 " XMAC_PORT_IPG:" 1323 " Invalid Input:" 1324 " mii_gmii_ipg <0x%x>", 1325 ipg1)); 1326 return (NPI_FAILURE | 1327 NPI_MAC_PORT_ATTR_INVALID(portn)); 1328 } 1329 1330 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1331 val &= ~(XMAC_IPG_VALUE_MASK | 1332 XMAC_IPG_VALUE1_MASK); 1333 1334 switch (ipg1) { 1335 case MII_GMII_IPG_12: 1336 val |= (IPG1_12_BYTES << 1337 XMAC_IPG_VALUE1_SHIFT); 1338 break; 1339 case MII_GMII_IPG_13: 1340 val |= (IPG1_13_BYTES << 1341 XMAC_IPG_VALUE1_SHIFT); 1342 break; 1343 case MII_GMII_IPG_14: 1344 val |= (IPG1_14_BYTES << 1345 XMAC_IPG_VALUE1_SHIFT); 1346 break; 1347 case MII_GMII_IPG_15: 1348 val |= (IPG1_15_BYTES << 1349 XMAC_IPG_VALUE1_SHIFT); 1350 break; 1351 case MII_GMII_IPG_16: 1352 val |= (IPG1_16_BYTES << 1353 XMAC_IPG_VALUE1_SHIFT); 1354 break; 1355 default: 1356 return (NPI_FAILURE | 1357 NPI_MAC_PORT_ATTR_INVALID(portn)); 1358 } 1359 XMAC_REG_WR(handle, portn, XMAC_IPG_REG, val); 1360 } else { 1361 XMAC_REG_RD(handle, portn, XMAC_IPG_REG, &val); 1362 ipg1 = (val & XMAC_IPG_VALUE1_MASK) >> 1363 XMAC_IPG_VALUE1_SHIFT; 1364 switch (ipg1) { 1365 case IPG1_12_BYTES: 1366 attrp->odata[1] = MII_GMII_IPG_12; 1367 break; 1368 case IPG1_13_BYTES: 1369 attrp->odata[1] = MII_GMII_IPG_13; 1370 break; 1371 case IPG1_14_BYTES: 1372 attrp->odata[1] = MII_GMII_IPG_14; 1373 break; 1374 case IPG1_15_BYTES: 1375 attrp->odata[1] = MII_GMII_IPG_15; 1376 break; 1377 case IPG1_16_BYTES: 1378 attrp->odata[1] = MII_GMII_IPG_16; 1379 break; 1380 default: 1381 return (NPI_FAILURE | 1382 NPI_MAC_PORT_ATTR_INVALID(portn)); 1383 } 1384 } 1385 break; 1386 case BMAC_PORT_0: 1387 case BMAC_PORT_1: 1388 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1389 " npi_mac_port_attr" 1390 " MAC_PORT_IPG:" 1391 " Invalid Input: portn <%d>", 1392 portn)); 1393 /* FALLTHROUGH */ 1394 default: 1395 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1396 } 1397 break; 1398 } 1399 1400 case MAC_PORT_ADDR: { 1401 uint32_t addr0; 1402 uint32_t addr1; 1403 uint32_t addr2; 1404 1405 switch (portn) { 1406 case XMAC_PORT_0: 1407 case XMAC_PORT_1: 1408 if (op == OP_SET) { 1409 addr0 = attrp->idata[0]; 1410 addr1 = attrp->idata[1]; 1411 addr2 = attrp->idata[2]; 1412 ASSERT((addr0 & ~0xFFFF) == 0); 1413 if ((addr0 & ~0xFFFF) != 0) { 1414 NPI_ERROR_MSG((handle.function, 1415 NPI_ERR_CTL, 1416 " npi_mac_port_attr" 1417 " MAC_PORT_ADDR:" 1418 " Invalid Input:" 1419 " addr0 <0x%x>", addr0)); 1420 1421 return (NPI_FAILURE | 1422 NPI_MAC_PORT_ATTR_INVALID(portn)); 1423 } 1424 ASSERT((addr1 & ~0xFFFF) == 0); 1425 if ((addr1 & ~0xFFFF) != 0) { 1426 NPI_ERROR_MSG((handle.function, 1427 NPI_ERR_CTL, 1428 " npi_mac_port_attr" 1429 " MAC_PORT_ADDR:" 1430 " Invalid Input:" 1431 " addr1 <0x%x>", addr1)); 1432 return (NPI_FAILURE | 1433 NPI_MAC_PORT_ATTR_INVALID(portn)); 1434 } 1435 ASSERT((addr2 & ~0xFFFF) == 0); 1436 if ((addr2 & ~0xFFFF) != 0) { 1437 NPI_ERROR_MSG((handle.function, 1438 NPI_ERR_CTL, 1439 " npi_mac_port_attr" 1440 " MAC_PORT_ADDR:" 1441 " Invalid Input:" 1442 " addr2 <0x%x.", 1443 addr2)); 1444 1445 return (NPI_FAILURE | 1446 NPI_MAC_PORT_ATTR_INVALID(portn)); 1447 } 1448 XMAC_REG_WR(handle, portn, XMAC_ADDR0_REG, 1449 addr0); 1450 XMAC_REG_WR(handle, portn, XMAC_ADDR1_REG, 1451 addr1); 1452 XMAC_REG_WR(handle, portn, XMAC_ADDR2_REG, 1453 addr2); 1454 } else { 1455 XMAC_REG_RD(handle, portn, XMAC_ADDR0_REG, 1456 &addr0); 1457 XMAC_REG_RD(handle, portn, XMAC_ADDR1_REG, 1458 &addr1); 1459 XMAC_REG_RD(handle, portn, XMAC_ADDR2_REG, 1460 &addr2); 1461 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1462 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1463 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1464 } 1465 break; 1466 case BMAC_PORT_0: 1467 case BMAC_PORT_1: 1468 if (op == OP_SET) { 1469 addr0 = attrp->idata[0]; 1470 addr1 = attrp->idata[1]; 1471 addr2 = attrp->idata[2]; 1472 ASSERT((addr0 & ~0xFFFF) == 0); 1473 if ((addr0 & ~0xFFFF) != 0) { 1474 NPI_ERROR_MSG((handle.function, 1475 NPI_ERR_CTL, 1476 " npi_mac_port_attr" 1477 " MAC_PORT_ADDR:" 1478 " Invalid Input:" 1479 " addr0 <0x%x>", 1480 addr0)); 1481 return (NPI_FAILURE | 1482 NPI_MAC_PORT_ATTR_INVALID(portn)); 1483 } 1484 ASSERT((addr1 & ~0xFFFF) == 0); 1485 if ((addr1 & ~0xFFFF) != 0) { 1486 NPI_ERROR_MSG((handle.function, 1487 NPI_ERR_CTL, 1488 " npi_mac_port_attr" 1489 " MAC_PORT_ADDR:" 1490 " Invalid Input:" 1491 " addr1 <0x%x>", 1492 addr1)); 1493 return (NPI_FAILURE | 1494 NPI_MAC_PORT_ATTR_INVALID(portn)); 1495 } 1496 ASSERT((addr2 & ~0xFFFF) == 0); 1497 if ((addr2 & ~0xFFFF) != 0) { 1498 NPI_ERROR_MSG((handle.function, 1499 NPI_ERR_CTL, 1500 " npi_mac_port_attr" 1501 " MAC_PORT_ADDR:" 1502 " Invalid Input:" 1503 " addr2 <0x%x>", 1504 addr2)); 1505 return (NPI_FAILURE | 1506 NPI_MAC_PORT_ATTR_INVALID(portn)); 1507 } 1508 BMAC_REG_WR(handle, portn, BMAC_ADDR0_REG, 1509 addr0); 1510 BMAC_REG_WR(handle, portn, BMAC_ADDR1_REG, 1511 addr1); 1512 BMAC_REG_WR(handle, portn, BMAC_ADDR2_REG, 1513 addr2); 1514 } else { 1515 BMAC_REG_RD(handle, portn, BMAC_ADDR0_REG, 1516 &addr0); 1517 BMAC_REG_RD(handle, portn, BMAC_ADDR1_REG, 1518 &addr1); 1519 BMAC_REG_RD(handle, portn, BMAC_ADDR2_REG, 1520 &addr2); 1521 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1522 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1523 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1524 } 1525 break; 1526 default: 1527 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1528 } 1529 break; 1530 } 1531 1532 case MAC_PORT_ADDR_FILTER: { 1533 uint32_t addr0; 1534 uint32_t addr1; 1535 uint32_t addr2; 1536 1537 switch (portn) { 1538 case XMAC_PORT_0: 1539 case XMAC_PORT_1: 1540 if (op == OP_SET) { 1541 addr0 = attrp->idata[0]; 1542 addr1 = attrp->idata[1]; 1543 addr2 = attrp->idata[2]; 1544 ASSERT((addr0 & ~0xFFFF) == 0); 1545 if ((addr0 & ~0xFFFF) != 0) { 1546 NPI_ERROR_MSG((handle.function, 1547 NPI_ERR_CTL, 1548 " npi_mac_port_attr" 1549 " MAC_PORT_ADDR_FILTER:" 1550 " Invalid Input:" 1551 " addr0 <0x%x>", 1552 addr0)); 1553 return (NPI_FAILURE | 1554 NPI_MAC_PORT_ATTR_INVALID(portn)); 1555 } 1556 ASSERT((addr1 & ~0xFFFF) == 0); 1557 if ((addr1 & ~0xFFFF) != 0) { 1558 NPI_ERROR_MSG((handle.function, 1559 NPI_ERR_CTL, 1560 " npi_mac_port_attr" 1561 " MAC_PORT_ADDR_FILTER:" 1562 " Invalid Input:" 1563 " addr1 <0x%x>", 1564 addr1)); 1565 return (NPI_FAILURE | 1566 NPI_MAC_PORT_ATTR_INVALID(portn)); 1567 } 1568 ASSERT((addr2 & ~0xFFFF) == 0); 1569 if ((addr2 & ~0xFFFF) != 0) { 1570 NPI_ERROR_MSG((handle.function, 1571 NPI_ERR_CTL, 1572 " npi_mac_port_attr" 1573 " MAC_PORT_ADDR_FILTER:" 1574 " Invalid Input:" 1575 " addr2 <0x%x>", 1576 addr2)); 1577 return (NPI_FAILURE | 1578 NPI_MAC_PORT_ATTR_INVALID(portn)); 1579 } 1580 XMAC_REG_WR(handle, portn, 1581 XMAC_ADDR_FILT0_REG, addr0); 1582 XMAC_REG_WR(handle, portn, 1583 XMAC_ADDR_FILT1_REG, addr1); 1584 XMAC_REG_WR(handle, portn, 1585 XMAC_ADDR_FILT2_REG, addr2); 1586 } else { 1587 XMAC_REG_RD(handle, portn, 1588 XMAC_ADDR_FILT0_REG, &addr0); 1589 XMAC_REG_RD(handle, portn, 1590 XMAC_ADDR_FILT1_REG, &addr1); 1591 XMAC_REG_RD(handle, portn, 1592 XMAC_ADDR_FILT2_REG, &addr2); 1593 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1594 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1595 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1596 } 1597 break; 1598 case BMAC_PORT_0: 1599 case BMAC_PORT_1: 1600 if (op == OP_SET) { 1601 addr0 = attrp->idata[0]; 1602 addr1 = attrp->idata[1]; 1603 addr2 = attrp->idata[2]; 1604 ASSERT((addr0 & ~0xFFFF) == 0); 1605 if ((addr0 & ~0xFFFF) != 0) { 1606 NPI_ERROR_MSG((handle.function, 1607 NPI_ERR_CTL, 1608 " npi_mac_port_attr" 1609 " MAC_PORT_ADDR_FILTER:" 1610 " addr0", 1611 addr0)); 1612 return (NPI_FAILURE | 1613 NPI_MAC_PORT_ATTR_INVALID(portn)); 1614 } 1615 ASSERT((addr1 & ~0xFFFF) == 0); 1616 if ((addr1 & ~0xFFFF) != 0) { 1617 NPI_ERROR_MSG((handle.function, 1618 NPI_ERR_CTL, 1619 " npi_mac_port_attr" 1620 " MAC_PORT_ADDR_FILTER:" 1621 " Invalid Input:" 1622 " addr1 <0x%x>", 1623 addr1)); 1624 return (NPI_FAILURE | 1625 NPI_MAC_PORT_ATTR_INVALID(portn)); 1626 } 1627 ASSERT((addr2 & ~0xFFFF) == 0); 1628 if ((addr2 & ~0xFFFF) != 0) { 1629 NPI_ERROR_MSG((handle.function, 1630 NPI_ERR_CTL, 1631 " npi_mac_port_attr" 1632 " MAC_PORT_ADDR_FILTER:" 1633 " Invalid Input:" 1634 " addr2 <0x%x>", 1635 addr2)); 1636 return (NPI_FAILURE | 1637 NPI_MAC_PORT_ATTR_INVALID(portn)); 1638 } 1639 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT0_REG, 1640 addr0); 1641 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT1_REG, 1642 addr1); 1643 BMAC_REG_WR(handle, portn, MAC_ADDR_FILT2_REG, 1644 addr2); 1645 } else { 1646 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT0_REG, 1647 &addr0); 1648 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT1_REG, 1649 &addr1); 1650 BMAC_REG_RD(handle, portn, MAC_ADDR_FILT2_REG, 1651 &addr2); 1652 attrp->odata[0] = addr0 & MAC_ADDR_REG_MASK; 1653 attrp->odata[1] = addr1 & MAC_ADDR_REG_MASK; 1654 attrp->odata[2] = addr2 & MAC_ADDR_REG_MASK; 1655 } 1656 break; 1657 default: 1658 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1659 } 1660 break; 1661 } 1662 1663 case MAC_PORT_ADDR_FILTER_MASK: { 1664 uint32_t mask_1_2; 1665 uint32_t mask_0; 1666 1667 switch (portn) { 1668 case XMAC_PORT_0: 1669 case XMAC_PORT_1: 1670 if (op == OP_SET) { 1671 mask_0 = attrp->idata[0]; 1672 mask_1_2 = attrp->idata[1]; 1673 ASSERT((mask_0 & ~0xFFFF) == 0); 1674 if ((mask_0 & ~0xFFFF) != 0) { 1675 NPI_ERROR_MSG((handle.function, 1676 NPI_ERR_CTL, 1677 " npi_mac_port_attr" 1678 " MAC_ADDR_FILTER_MASK:" 1679 " Invalid Input:" 1680 " mask_0 <0x%x>", 1681 mask_0)); 1682 return (NPI_FAILURE | 1683 NPI_MAC_PORT_ATTR_INVALID(portn)); 1684 } 1685 ASSERT((mask_1_2 & ~0xFF) == 0); 1686 if ((mask_1_2 & ~0xFF) != 0) { 1687 NPI_ERROR_MSG((handle.function, 1688 NPI_ERR_CTL, 1689 " npi_mac_port_attr" 1690 " MAC_ADDR_FILTER_MASK:" 1691 " Invalid Input:" 1692 " mask_1_2 <0x%x>", 1693 mask_1_2)); 1694 return (NPI_FAILURE | 1695 NPI_MAC_PORT_ATTR_INVALID(portn)); 1696 } 1697 XMAC_REG_WR(handle, portn, 1698 XMAC_ADDR_FILT0_MASK_REG, mask_0); 1699 XMAC_REG_WR(handle, portn, 1700 XMAC_ADDR_FILT12_MASK_REG, mask_1_2); 1701 } else { 1702 XMAC_REG_RD(handle, portn, 1703 XMAC_ADDR_FILT0_MASK_REG, &mask_0); 1704 XMAC_REG_RD(handle, portn, 1705 XMAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1706 attrp->odata[0] = mask_0 & 0xFFFF; 1707 attrp->odata[1] = mask_1_2 & 0xFF; 1708 } 1709 break; 1710 case BMAC_PORT_0: 1711 case BMAC_PORT_1: 1712 if (op == OP_SET) { 1713 mask_0 = attrp->idata[0]; 1714 mask_1_2 = attrp->idata[1]; 1715 BMAC_REG_WR(handle, portn, 1716 MAC_ADDR_FILT00_MASK_REG, mask_0); 1717 BMAC_REG_WR(handle, portn, 1718 MAC_ADDR_FILT12_MASK_REG, mask_1_2); 1719 } else { 1720 BMAC_REG_RD(handle, portn, 1721 MAC_ADDR_FILT00_MASK_REG, &mask_0); 1722 BMAC_REG_RD(handle, portn, 1723 MAC_ADDR_FILT12_MASK_REG, &mask_1_2); 1724 attrp->odata[0] = mask_0; 1725 attrp->odata[1] = mask_1_2; 1726 } 1727 break; 1728 default: 1729 return (NPI_FAILURE | NPI_MAC_PORT_INVALID(portn)); 1730 } 1731 break; 1732 } 1733 1734 default: 1735 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1736 " npi_mac_port_attr" 1737 " Invalid Input:" 1738 " attr <0x%x>", attrp->type)); 1739 return (NPI_FAILURE | NPI_MAC_PORT_ATTR_INVALID(portn)); 1740 } 1741 1742 return (NPI_SUCCESS); 1743 } 1744 1745 npi_status_t 1746 npi_xmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 1747 { 1748 uint64_t val; 1749 boolean_t txmac = B_FALSE; 1750 1751 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1752 1753 switch (mode) { 1754 case XTX_MAC_REG_RESET: 1755 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_REG_RST); 1756 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1757 txmac = B_TRUE; 1758 break; 1759 case XRX_MAC_REG_RESET: 1760 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_REG_RST); 1761 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1762 break; 1763 case XTX_MAC_LOGIC_RESET: 1764 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, XTXMAC_SOFT_RST); 1765 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1766 txmac = B_TRUE; 1767 break; 1768 case XRX_MAC_LOGIC_RESET: 1769 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, XRXMAC_SOFT_RST); 1770 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1771 break; 1772 case XTX_MAC_RESET_ALL: 1773 XMAC_REG_WR(handle, portn, XTXMAC_SW_RST_REG, 1774 XTXMAC_SOFT_RST | XTXMAC_REG_RST); 1775 XMAC_WAIT_REG(handle, portn, XTXMAC_SW_RST_REG, val); 1776 txmac = B_TRUE; 1777 break; 1778 case XRX_MAC_RESET_ALL: 1779 XMAC_REG_WR(handle, portn, XRXMAC_SW_RST_REG, 1780 XRXMAC_SOFT_RST | XRXMAC_REG_RST); 1781 XMAC_WAIT_REG(handle, portn, XRXMAC_SW_RST_REG, val); 1782 break; 1783 default: 1784 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1785 " npi_mac_reset" 1786 " Invalid Input: mode <0x%x>", 1787 mode)); 1788 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 1789 } 1790 1791 if (val != 0) { 1792 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1793 " npi_xmac_reset" 1794 " HW ERROR: MAC_RESET failed <0x%x>", 1795 val)); 1796 1797 if (txmac) 1798 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 1799 else 1800 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 1801 } 1802 1803 return (NPI_SUCCESS); 1804 } 1805 1806 npi_status_t 1807 npi_xmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1808 xmac_xif_config_t config) 1809 { 1810 uint64_t val = 0; 1811 1812 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1813 1814 switch (op) { 1815 case ENABLE: 1816 case DISABLE: 1817 ASSERT((config != 0) && ((config & ~CFG_XMAC_XIF_ALL) == 0)); 1818 if ((config == 0) || (config & ~CFG_XMAC_XIF_ALL) != 0) { 1819 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1820 " npi_xmac_xif_config" 1821 " Invalid Input:" 1822 " config <0x%x>", config)); 1823 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1824 } 1825 if (op == ENABLE) { 1826 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1827 if (config & CFG_XMAC_XIF_LED_FORCE) 1828 val |= XMAC_XIF_FORCE_LED_ON; 1829 if (config & CFG_XMAC_XIF_LED_POLARITY) 1830 val |= XMAC_XIF_LED_POLARITY; 1831 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1832 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1833 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1834 val |= XMAC_XIF_TX_OUTPUT_EN; 1835 1836 if (config & CFG_XMAC_XIF_LOOPBACK) { 1837 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1838 val |= XMAC_XIF_LOOPBACK; 1839 } 1840 1841 if (config & CFG_XMAC_XIF_LFS) 1842 val &= ~XMAC_XIF_LFS_DISABLE; 1843 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1844 val |= XMAC_XIF_XPCS_BYPASS; 1845 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1846 val |= XMAC_XIF_1G_PCS_BYPASS; 1847 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1848 val |= XMAC_XIF_SEL_CLK_25MHZ; 1849 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1850 1851 } else { 1852 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1853 if (config & CFG_XMAC_XIF_LED_FORCE) 1854 val &= ~XMAC_XIF_FORCE_LED_ON; 1855 if (config & CFG_XMAC_XIF_LED_POLARITY) 1856 val &= ~XMAC_XIF_LED_POLARITY; 1857 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1858 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1859 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1860 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1861 if (config & CFG_XMAC_XIF_LOOPBACK) 1862 val &= ~XMAC_XIF_LOOPBACK; 1863 if (config & CFG_XMAC_XIF_LFS) 1864 val |= XMAC_XIF_LFS_DISABLE; 1865 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1866 val &= ~XMAC_XIF_XPCS_BYPASS; 1867 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1868 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1869 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1870 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1871 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1872 } 1873 break; 1874 case INIT: 1875 ASSERT((config & ~CFG_XMAC_XIF_ALL) == 0); 1876 if ((config & ~CFG_XMAC_XIF_ALL) != 0) { 1877 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1878 " npi_xmac_xif_config" 1879 " Invalid Input: config <0x%x>", 1880 config)); 1881 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1882 } 1883 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1884 1885 if (config & CFG_XMAC_XIF_LED_FORCE) 1886 val |= XMAC_XIF_FORCE_LED_ON; 1887 else 1888 val &= ~XMAC_XIF_FORCE_LED_ON; 1889 if (config & CFG_XMAC_XIF_LED_POLARITY) 1890 val |= XMAC_XIF_LED_POLARITY; 1891 else 1892 val &= ~XMAC_XIF_LED_POLARITY; 1893 if (config & CFG_XMAC_XIF_SEL_POR_CLK_SRC) 1894 val |= XMAC_XIF_SEL_POR_CLK_SRC; 1895 else 1896 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1897 if (config & CFG_XMAC_XIF_TX_OUTPUT) 1898 val |= XMAC_XIF_TX_OUTPUT_EN; 1899 else 1900 val &= ~XMAC_XIF_TX_OUTPUT_EN; 1901 1902 if (config & CFG_XMAC_XIF_LOOPBACK) { 1903 val &= ~XMAC_XIF_SEL_POR_CLK_SRC; 1904 val |= XMAC_XIF_LOOPBACK; 1905 #ifdef AXIS_DEBUG_LB 1906 val |= XMAC_RX_MAC2IPP_PKT_CNT_EN; 1907 #endif 1908 } else { 1909 val &= ~XMAC_XIF_LOOPBACK; 1910 } 1911 1912 if (config & CFG_XMAC_XIF_LFS) 1913 val &= ~XMAC_XIF_LFS_DISABLE; 1914 else 1915 val |= XMAC_XIF_LFS_DISABLE; 1916 if (config & CFG_XMAC_XIF_XPCS_BYPASS) 1917 val |= XMAC_XIF_XPCS_BYPASS; 1918 else 1919 val &= ~XMAC_XIF_XPCS_BYPASS; 1920 if (config & CFG_XMAC_XIF_1G_PCS_BYPASS) 1921 val |= XMAC_XIF_1G_PCS_BYPASS; 1922 else 1923 val &= ~XMAC_XIF_1G_PCS_BYPASS; 1924 if (config & CFG_XMAC_XIF_SEL_CLK_25MHZ) 1925 val |= XMAC_XIF_SEL_CLK_25MHZ; 1926 else 1927 val &= ~XMAC_XIF_SEL_CLK_25MHZ; 1928 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1929 1930 break; 1931 default: 1932 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1933 " npi_xmac_xif_config" 1934 " Invalid Input: op <0x%x>", op)); 1935 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1936 } 1937 1938 return (NPI_SUCCESS); 1939 } 1940 1941 npi_status_t 1942 npi_xmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 1943 xmac_tx_config_t config) 1944 { 1945 uint64_t val = 0; 1946 1947 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 1948 1949 switch (op) { 1950 case ENABLE: 1951 case DISABLE: 1952 ASSERT((config != 0) && ((config & ~CFG_XMAC_TX_ALL) == 0)); 1953 if ((config == 0) || (config & ~CFG_XMAC_TX_ALL) != 0) { 1954 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1955 " npi_xmac_tx_config" 1956 " Invalid Input: config <0x%x>", 1957 config)); 1958 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 1959 } 1960 if (op == ENABLE) { 1961 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1962 if (config & CFG_XMAC_TX) 1963 val |= XMAC_TX_CFG_TX_ENABLE; 1964 if (config & CFG_XMAC_TX_STRETCH_MODE) 1965 val |= XMAC_TX_CFG_STRETCH_MD; 1966 if (config & CFG_XMAC_VAR_IPG) 1967 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 1968 if (config & CFG_XMAC_TX_CRC) 1969 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 1970 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1971 } else { 1972 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1973 if (config & CFG_XMAC_TX) 1974 val &= ~XMAC_TX_CFG_TX_ENABLE; 1975 if (config & CFG_XMAC_TX_STRETCH_MODE) 1976 val &= ~XMAC_TX_CFG_STRETCH_MD; 1977 if (config & CFG_XMAC_VAR_IPG) 1978 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 1979 if (config & CFG_XMAC_TX_CRC) 1980 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 1981 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 1982 } 1983 break; 1984 case INIT: 1985 ASSERT((config & ~CFG_XMAC_TX_ALL) == 0); 1986 if ((config & ~CFG_XMAC_TX_ALL) != 0) { 1987 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 1988 " npi_xmac_tx_config" 1989 " Invalid Input: config <0x%x>", 1990 config)); 1991 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 1992 } 1993 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 1994 if (config & CFG_XMAC_TX) 1995 val |= XMAC_TX_CFG_TX_ENABLE; 1996 else 1997 val &= ~XMAC_TX_CFG_TX_ENABLE; 1998 if (config & CFG_XMAC_TX_STRETCH_MODE) 1999 val |= XMAC_TX_CFG_STRETCH_MD; 2000 else 2001 val &= ~XMAC_TX_CFG_STRETCH_MD; 2002 if (config & CFG_XMAC_VAR_IPG) 2003 val |= XMAC_TX_CFG_VAR_MIN_IPG_EN; 2004 else 2005 val &= ~XMAC_TX_CFG_VAR_MIN_IPG_EN; 2006 if (config & CFG_XMAC_TX_CRC) 2007 val &= ~XMAC_TX_CFG_ALWAYS_NO_CRC; 2008 else 2009 val |= XMAC_TX_CFG_ALWAYS_NO_CRC; 2010 2011 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2012 break; 2013 default: 2014 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2015 " npi_xmac_tx_config" 2016 " Invalid Input: op <0x%x>", 2017 op)); 2018 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2019 } 2020 2021 return (NPI_SUCCESS); 2022 } 2023 2024 npi_status_t 2025 npi_xmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2026 xmac_rx_config_t config) 2027 { 2028 uint64_t val = 0; 2029 2030 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2031 2032 switch (op) { 2033 case ENABLE: 2034 case DISABLE: 2035 ASSERT((config != 0) && ((config & ~CFG_XMAC_RX_ALL) == 0)); 2036 if ((config == 0) || (config & ~CFG_XMAC_RX_ALL) != 0) { 2037 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2038 " npi_xmac_rx_config" 2039 " Invalid Input: config <0x%x>", 2040 config)); 2041 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2042 } 2043 if (op == ENABLE) { 2044 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2045 if (config & CFG_XMAC_RX) 2046 val |= XMAC_RX_CFG_RX_ENABLE; 2047 if (config & CFG_XMAC_RX_PROMISCUOUS) 2048 val |= XMAC_RX_CFG_PROMISC; 2049 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2050 val |= XMAC_RX_CFG_PROMISC_GROUP; 2051 if (config & CFG_XMAC_RX_ERRCHK) 2052 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2053 if (config & CFG_XMAC_RX_CRC_CHK) 2054 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2055 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2056 val |= XMAC_RX_CFG_RESERVED_MCAST; 2057 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2058 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2059 if (config & CFG_XMAC_RX_HASH_FILTER) 2060 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2061 if (config & CFG_XMAC_RX_ADDR_FILTER) 2062 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2063 if (config & CFG_XMAC_RX_STRIP_CRC) 2064 val |= XMAC_RX_CFG_STRIP_CRC; 2065 if (config & CFG_XMAC_RX_PAUSE) 2066 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2067 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2068 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2069 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2070 } else { 2071 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2072 if (config & CFG_XMAC_RX) 2073 val &= ~XMAC_RX_CFG_RX_ENABLE; 2074 if (config & CFG_XMAC_RX_PROMISCUOUS) 2075 val &= ~XMAC_RX_CFG_PROMISC; 2076 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2077 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2078 if (config & CFG_XMAC_RX_ERRCHK) 2079 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2080 if (config & CFG_XMAC_RX_CRC_CHK) 2081 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2082 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2083 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2084 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2085 val |= XMAC_RX_CFG_CD_VIO_CHK; 2086 if (config & CFG_XMAC_RX_HASH_FILTER) 2087 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2088 if (config & CFG_XMAC_RX_ADDR_FILTER) 2089 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2090 if (config & CFG_XMAC_RX_STRIP_CRC) 2091 val &= ~XMAC_RX_CFG_STRIP_CRC; 2092 if (config & CFG_XMAC_RX_PAUSE) 2093 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2094 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2095 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2096 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2097 } 2098 break; 2099 case INIT: 2100 ASSERT((config & ~CFG_XMAC_RX_ALL) == 0); 2101 if ((config & ~CFG_XMAC_RX_ALL) != 0) { 2102 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2103 " npi_xmac_rx_config" 2104 " Invalid Input: config <0x%x>", 2105 config)); 2106 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2107 } 2108 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 2109 if (config & CFG_XMAC_RX) 2110 val |= XMAC_RX_CFG_RX_ENABLE; 2111 else 2112 val &= ~XMAC_RX_CFG_RX_ENABLE; 2113 if (config & CFG_XMAC_RX_PROMISCUOUS) 2114 val |= XMAC_RX_CFG_PROMISC; 2115 else 2116 val &= ~XMAC_RX_CFG_PROMISC; 2117 if (config & CFG_XMAC_RX_PROMISCUOUSGROUP) 2118 val |= XMAC_RX_CFG_PROMISC_GROUP; 2119 else 2120 val &= ~XMAC_RX_CFG_PROMISC_GROUP; 2121 if (config & CFG_XMAC_RX_ERRCHK) 2122 val &= ~XMAC_RX_CFG_ERR_CHK_DISABLE; 2123 else 2124 val |= XMAC_RX_CFG_ERR_CHK_DISABLE; 2125 if (config & CFG_XMAC_RX_CRC_CHK) 2126 val &= ~XMAC_RX_CFG_CRC_CHK_DISABLE; 2127 else 2128 val |= XMAC_RX_CFG_CRC_CHK_DISABLE; 2129 if (config & CFG_XMAC_RX_RESV_MULTICAST) 2130 val |= XMAC_RX_CFG_RESERVED_MCAST; 2131 else 2132 val &= ~XMAC_RX_CFG_RESERVED_MCAST; 2133 if (config & CFG_XMAC_RX_CODE_VIO_CHK) 2134 val &= ~XMAC_RX_CFG_CD_VIO_CHK; 2135 else 2136 val |= XMAC_RX_CFG_CD_VIO_CHK; 2137 if (config & CFG_XMAC_RX_HASH_FILTER) 2138 val |= XMAC_RX_CFG_HASH_FILTER_EN; 2139 else 2140 val &= ~XMAC_RX_CFG_HASH_FILTER_EN; 2141 if (config & CFG_XMAC_RX_ADDR_FILTER) 2142 val |= XMAC_RX_CFG_ADDR_FILTER_EN; 2143 else 2144 val &= ~XMAC_RX_CFG_ADDR_FILTER_EN; 2145 if (config & CFG_XMAC_RX_PAUSE) 2146 val |= XMAC_RX_CFG_RX_PAUSE_EN; 2147 else 2148 val &= ~XMAC_RX_CFG_RX_PAUSE_EN; 2149 if (config & CFG_XMAC_RX_STRIP_CRC) 2150 val |= XMAC_RX_CFG_STRIP_CRC; 2151 else 2152 val &= ~XMAC_RX_CFG_STRIP_CRC; 2153 if (config & CFG_XMAC_RX_PASS_FC_FRAME) 2154 val |= XMAC_RX_CFG_PASS_FLOW_CTRL; 2155 else 2156 val &= ~XMAC_RX_CFG_PASS_FLOW_CTRL; 2157 2158 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 2159 break; 2160 default: 2161 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2162 " npi_xmac_rx_config" 2163 " Invalid Input: op <0x%x>", op)); 2164 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2165 } 2166 2167 return (NPI_SUCCESS); 2168 } 2169 2170 npi_status_t 2171 npi_xmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2172 xmac_tx_iconfig_t iconfig) 2173 { 2174 uint64_t val = 0; 2175 2176 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2177 2178 switch (op) { 2179 case ENABLE: 2180 case DISABLE: 2181 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2182 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2183 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2184 " npi_xmac_tx_iconfig" 2185 " Invalid Input: iconfig <0x%x>", 2186 iconfig)); 2187 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2188 } 2189 XMAC_REG_RD(handle, portn, XTXMAC_STAT_MSK_REG, &val); 2190 if (op == ENABLE) 2191 val &= ~iconfig; 2192 else 2193 val |= iconfig; 2194 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, val); 2195 2196 break; 2197 case INIT: 2198 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2199 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2200 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2201 " npi_xmac_tx_iconfig" 2202 " Invalid Input: iconfig <0x%x>", 2203 iconfig)); 2204 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2205 } 2206 XMAC_REG_WR(handle, portn, XTXMAC_STAT_MSK_REG, ~iconfig); 2207 2208 break; 2209 default: 2210 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2211 " npi_xmac_tx_iconfig" 2212 " Invalid Input: iconfig <0x%x>", 2213 iconfig)); 2214 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2215 } 2216 2217 return (NPI_SUCCESS); 2218 } 2219 2220 npi_status_t 2221 npi_xmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2222 xmac_rx_iconfig_t iconfig) 2223 { 2224 uint64_t val = 0; 2225 2226 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2227 2228 switch (op) { 2229 case ENABLE: 2230 case DISABLE: 2231 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_RX_ALL) == 0)); 2232 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2233 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2234 " npi_xmac_rx_iconfig" 2235 " Invalid Input: iconfig <0x%x>", 2236 iconfig)); 2237 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2238 } 2239 XMAC_REG_RD(handle, portn, XRXMAC_STAT_MSK_REG, &val); 2240 if (op == ENABLE) 2241 val &= ~iconfig; 2242 else 2243 val |= iconfig; 2244 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, val); 2245 2246 break; 2247 case INIT: 2248 ASSERT((iconfig & ~ICFG_XMAC_RX_ALL) == 0); 2249 if ((iconfig & ~ICFG_XMAC_RX_ALL) != 0) { 2250 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2251 " npi_xmac_rx_iconfig" 2252 " Invalid Input: iconfig <0x%x>", 2253 iconfig)); 2254 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2255 } 2256 XMAC_REG_WR(handle, portn, XRXMAC_STAT_MSK_REG, ~iconfig); 2257 2258 break; 2259 default: 2260 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2261 " npi_xmac_rx_iconfig" 2262 " Invalid Input: iconfig <0x%x>", 2263 iconfig)); 2264 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2265 } 2266 2267 return (NPI_SUCCESS); 2268 } 2269 2270 npi_status_t 2271 npi_xmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2272 xmac_ctl_iconfig_t iconfig) 2273 { 2274 uint64_t val = 0; 2275 2276 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2277 2278 switch (op) { 2279 case ENABLE: 2280 case DISABLE: 2281 ASSERT((iconfig != 0) && \ 2282 ((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0)); 2283 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2284 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2285 " npi_xmac_ctl_iconfig" 2286 " Invalid Input: iconfig <0x%x>", 2287 iconfig)); 2288 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2289 } 2290 XMAC_REG_RD(handle, portn, XMAC_C_S_MSK_REG, &val); 2291 if (op == ENABLE) 2292 val &= ~iconfig; 2293 else 2294 val |= iconfig; 2295 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, val); 2296 2297 break; 2298 case INIT: 2299 ASSERT((iconfig & ~ICFG_XMAC_CTRL_ALL) == 0); 2300 if ((iconfig & ~ICFG_XMAC_CTRL_ALL) != 0) { 2301 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2302 " npi_xmac_ctl_iconfig" 2303 " Invalid Input: iconfig <0x%x>", 2304 iconfig)); 2305 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2306 } 2307 XMAC_REG_WR(handle, portn, XMAC_C_S_MSK_REG, ~iconfig); 2308 2309 break; 2310 default: 2311 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2312 " npi_xmac_ctl_iconfig" 2313 " Invalid Input: iconfig <0x%x>", 2314 iconfig)); 2315 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2316 } 2317 2318 return (NPI_SUCCESS); 2319 } 2320 2321 npi_status_t 2322 npi_xmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 2323 xmac_tx_iconfig_t *istatus) 2324 { 2325 uint64_t val; 2326 2327 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2328 2329 XMAC_REG_RD(handle, portn, XTXMAC_STATUS_REG, &val); 2330 *istatus = (uint32_t)val; 2331 2332 return (NPI_SUCCESS); 2333 } 2334 2335 npi_status_t 2336 npi_xmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 2337 xmac_rx_iconfig_t *istatus) 2338 { 2339 uint64_t val; 2340 2341 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2342 2343 XMAC_REG_RD(handle, portn, XRXMAC_STATUS_REG, &val); 2344 *istatus = (uint32_t)val; 2345 2346 return (NPI_SUCCESS); 2347 } 2348 2349 npi_status_t 2350 npi_xmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 2351 xmac_ctl_iconfig_t *istatus) 2352 { 2353 uint64_t val; 2354 2355 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2356 2357 XMAC_REG_RD(handle, portn, XMAC_CTRL_STAT_REG, &val); 2358 *istatus = (uint32_t)val; 2359 2360 return (NPI_SUCCESS); 2361 } 2362 2363 npi_status_t 2364 npi_xmac_xpcs_reset(npi_handle_t handle, uint8_t portn) 2365 { 2366 uint64_t val; 2367 int delay = 100; 2368 2369 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2370 2371 XPCS_REG_RD(handle, portn, XPCS_CTRL_1_REG, &val); 2372 val |= XPCS_CTRL1_RST; 2373 XPCS_REG_WR(handle, portn, XPCS_CTRL_1_REG, val); 2374 2375 while ((--delay) && (val & XPCS_CTRL1_RST)) { 2376 NXGE_DELAY(10); 2377 XPCS_REG_RD(handle, portn, XPCS_CTRL_1_REG, &val); 2378 } 2379 2380 if (delay == 0) { 2381 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2382 " npi_xmac_xpcs_reset portn <%d> failed", portn)); 2383 return (NPI_FAILURE); 2384 } 2385 2386 return (NPI_SUCCESS); 2387 } 2388 2389 npi_status_t 2390 npi_xmac_xpcs_enable(npi_handle_t handle, uint8_t portn) 2391 { 2392 uint64_t val; 2393 2394 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2395 2396 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2397 val |= XPCS_CFG_XPCS_ENABLE; 2398 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2399 2400 return (NPI_SUCCESS); 2401 } 2402 2403 npi_status_t 2404 npi_xmac_xpcs_disable(npi_handle_t handle, uint8_t portn) 2405 { 2406 uint64_t val; 2407 2408 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2409 2410 XPCS_REG_RD(handle, portn, XPCS_CFG_VENDOR_1_REG, &val); 2411 val &= ~XPCS_CFG_XPCS_ENABLE; 2412 XPCS_REG_WR(handle, portn, XPCS_CFG_VENDOR_1_REG, val); 2413 2414 return (NPI_SUCCESS); 2415 } 2416 2417 npi_status_t 2418 npi_xmac_xpcs_read(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2419 uint32_t *value) 2420 { 2421 uint32_t reg; 2422 uint64_t val; 2423 2424 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2425 2426 switch (xpcs_reg) { 2427 case XPCS_REG_CONTROL1: 2428 reg = XPCS_CTRL_1_REG; 2429 break; 2430 case XPCS_REG_STATUS1: 2431 reg = XPCS_STATUS_1_REG; 2432 break; 2433 case XPCS_REG_DEVICE_ID: 2434 reg = XPCS_DEV_ID_REG; 2435 break; 2436 case XPCS_REG_SPEED_ABILITY: 2437 reg = XPCS_SPEED_ABILITY_REG; 2438 break; 2439 case XPCS_REG_DEVICE_IN_PKG: 2440 reg = XPCS_DEV_IN_PKG_REG; 2441 break; 2442 case XPCS_REG_CONTROL2: 2443 reg = XPCS_CTRL_2_REG; 2444 break; 2445 case XPCS_REG_STATUS2: 2446 reg = XPCS_STATUS_2_REG; 2447 break; 2448 case XPCS_REG_PKG_ID: 2449 reg = XPCS_PKG_ID_REG; 2450 break; 2451 case XPCS_REG_STATUS: 2452 reg = XPCS_STATUS_REG; 2453 break; 2454 case XPCS_REG_TEST_CONTROL: 2455 reg = XPCS_TEST_CTRL_REG; 2456 break; 2457 case XPCS_REG_CONFIG_VENDOR1: 2458 reg = XPCS_CFG_VENDOR_1_REG; 2459 break; 2460 case XPCS_REG_DIAG_VENDOR2: 2461 reg = XPCS_DIAG_VENDOR_2_REG; 2462 break; 2463 case XPCS_REG_MASK1: 2464 reg = XPCS_MASK_1_REG; 2465 break; 2466 case XPCS_REG_PACKET_COUNTER: 2467 reg = XPCS_PKT_CNTR_REG; 2468 break; 2469 case XPCS_REG_TX_STATEMACHINE: 2470 reg = XPCS_TX_STATE_MC_REG; 2471 break; 2472 case XPCS_REG_DESCWERR_COUNTER: 2473 reg = XPCS_DESKEW_ERR_CNTR_REG; 2474 break; 2475 case XPCS_REG_SYMBOL_ERR_L0_1_COUNTER: 2476 reg = XPCS_SYM_ERR_CNTR_L0_L1_REG; 2477 break; 2478 case XPCS_REG_SYMBOL_ERR_L2_3_COUNTER: 2479 reg = XPCS_SYM_ERR_CNTR_L2_L3_REG; 2480 break; 2481 case XPCS_REG_TRAINING_VECTOR: 2482 reg = XPCS_TRAINING_VECTOR_REG; 2483 break; 2484 default: 2485 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2486 " npi_xmac_xpcs_read" 2487 " Invalid Input: xpcs_reg <0x%x>", 2488 xpcs_reg)); 2489 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 2490 } 2491 XPCS_REG_RD(handle, portn, reg, &val); 2492 *value = val & 0xFFFFFFFF; 2493 2494 return (NPI_SUCCESS); 2495 } 2496 2497 npi_status_t 2498 npi_xmac_xpcs_write(npi_handle_t handle, uint8_t portn, uint8_t xpcs_reg, 2499 uint32_t value) 2500 { 2501 uint32_t reg; 2502 uint64_t val; 2503 2504 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 2505 2506 switch (xpcs_reg) { 2507 case XPCS_REG_CONTROL1: 2508 reg = XPCS_CTRL_1_REG; 2509 break; 2510 case XPCS_REG_TEST_CONTROL: 2511 reg = XPCS_TEST_CTRL_REG; 2512 break; 2513 case XPCS_REG_CONFIG_VENDOR1: 2514 reg = XPCS_CFG_VENDOR_1_REG; 2515 break; 2516 case XPCS_REG_DIAG_VENDOR2: 2517 reg = XPCS_DIAG_VENDOR_2_REG; 2518 break; 2519 case XPCS_REG_MASK1: 2520 reg = XPCS_MASK_1_REG; 2521 break; 2522 case XPCS_REG_PACKET_COUNTER: 2523 reg = XPCS_PKT_CNTR_REG; 2524 break; 2525 case XPCS_REG_DESCWERR_COUNTER: 2526 reg = XPCS_DESKEW_ERR_CNTR_REG; 2527 break; 2528 case XPCS_REG_TRAINING_VECTOR: 2529 reg = XPCS_TRAINING_VECTOR_REG; 2530 break; 2531 default: 2532 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2533 " npi_xmac_xpcs_write" 2534 " Invalid Input: xpcs_reg <0x%x>", 2535 xpcs_reg)); 2536 return (NPI_FAILURE | NPI_MAC_PCS_REG_INVALID(portn)); 2537 } 2538 val = value; 2539 2540 XPCS_REG_WR(handle, portn, reg, val); 2541 2542 return (NPI_SUCCESS); 2543 } 2544 2545 npi_status_t 2546 npi_bmac_reset(npi_handle_t handle, uint8_t portn, npi_mac_reset_t mode) 2547 { 2548 uint64_t val = 0; 2549 boolean_t txmac = B_FALSE; 2550 2551 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2552 2553 switch (mode) { 2554 case TX_MAC_RESET: 2555 BMAC_REG_WR(handle, portn, BTXMAC_SW_RST_REG, 0x1); 2556 BMAC_WAIT_REG(handle, portn, BTXMAC_SW_RST_REG, val); 2557 txmac = B_TRUE; 2558 break; 2559 case RX_MAC_RESET: 2560 BMAC_REG_WR(handle, portn, BRXMAC_SW_RST_REG, 0x1); 2561 BMAC_WAIT_REG(handle, portn, BRXMAC_SW_RST_REG, val); 2562 break; 2563 default: 2564 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2565 " npi_bmac_reset" 2566 " Invalid Input: mode <0x%x>", 2567 mode)); 2568 return (NPI_FAILURE | NPI_MAC_RESET_MODE_INVALID(portn)); 2569 } 2570 2571 if (val != 0) { 2572 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2573 " npi_bmac_reset" 2574 " BMAC_RESET HW Error: ret <0x%x>", 2575 val)); 2576 if (txmac) 2577 return (NPI_FAILURE | NPI_TXMAC_RESET_FAILED(portn)); 2578 else 2579 return (NPI_FAILURE | NPI_RXMAC_RESET_FAILED(portn)); 2580 } 2581 2582 return (NPI_SUCCESS); 2583 } 2584 2585 npi_status_t 2586 npi_mac_pcs_reset(npi_handle_t handle, uint8_t portn) 2587 { 2588 /* what to do here ? */ 2589 uint64_t val = 0; 2590 int delay = 100; 2591 2592 ASSERT(IS_PORT_NUM_VALID(portn)); 2593 2594 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 2595 val |= PCS_MII_RESET; 2596 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 2597 while ((delay) && (val & PCS_MII_RESET)) { 2598 NXGE_DELAY(10); 2599 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 2600 delay--; 2601 } 2602 if (delay == 0) { 2603 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2604 " npi_bmac_pcs_reset portn <%d> failed", portn)); 2605 return (NPI_FAILURE); 2606 } 2607 return (NPI_SUCCESS); 2608 } 2609 2610 npi_status_t 2611 npi_mac_get_link_status(npi_handle_t handle, uint8_t portn, 2612 boolean_t *link_up) 2613 { 2614 uint64_t val; 2615 2616 ASSERT(IS_PORT_NUM_VALID(portn)); 2617 2618 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 2619 2620 if (val & PCS_MII_STATUS_LINK_STATUS) { 2621 *link_up = B_TRUE; 2622 } else { 2623 *link_up = B_FALSE; 2624 } 2625 2626 return (NPI_SUCCESS); 2627 } 2628 2629 npi_status_t 2630 npi_bmac_tx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2631 bmac_tx_config_t config) 2632 { 2633 uint64_t val = 0; 2634 2635 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2636 2637 switch (op) { 2638 case ENABLE: 2639 case DISABLE: 2640 ASSERT((config != 0) && ((config & ~CFG_BMAC_TX_ALL) == 0)); 2641 if ((config == 0) || (config & ~CFG_BMAC_TX_ALL) != 0) { 2642 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2643 " npi_bmac_tx_config" 2644 " Invalid Input: config <0x%x>", 2645 config)); 2646 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2647 } 2648 if (op == ENABLE) { 2649 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2650 if (config & CFG_BMAC_TX) 2651 val |= MAC_TX_CFG_TXMAC_ENABLE; 2652 if (config & CFG_BMAC_TX_CRC) 2653 val &= ~MAC_TX_CFG_NO_FCS; 2654 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2655 } else { 2656 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2657 if (config & CFG_BMAC_TX) 2658 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2659 if (config & CFG_BMAC_TX_CRC) 2660 val |= MAC_TX_CFG_NO_FCS; 2661 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2662 } 2663 break; 2664 case INIT: 2665 ASSERT((config & ~CFG_BMAC_TX_ALL) == 0); 2666 if ((config & ~CFG_BMAC_TX_ALL) != 0) { 2667 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2668 " npi_bmac_tx_config" 2669 " Invalid Input: config <0x%x>", 2670 config)); 2671 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2672 } 2673 BMAC_REG_RD(handle, portn, TXMAC_CONFIG_REG, &val); 2674 if (config & CFG_BMAC_TX) 2675 val |= MAC_TX_CFG_TXMAC_ENABLE; 2676 else 2677 val &= ~MAC_TX_CFG_TXMAC_ENABLE; 2678 if (config & CFG_BMAC_TX_CRC) 2679 val &= ~MAC_TX_CFG_NO_FCS; 2680 else 2681 val |= MAC_TX_CFG_NO_FCS; 2682 BMAC_REG_WR(handle, portn, TXMAC_CONFIG_REG, val); 2683 break; 2684 default: 2685 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2686 " npi_bmac_tx_config" 2687 " Invalid Input: op <0x%x>", 2688 op)); 2689 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2690 } 2691 2692 return (NPI_SUCCESS); 2693 } 2694 2695 npi_status_t 2696 npi_bmac_rx_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2697 bmac_rx_config_t config) 2698 { 2699 uint64_t val = 0; 2700 2701 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2702 2703 switch (op) { 2704 case ENABLE: 2705 case DISABLE: 2706 ASSERT((config != 0) && ((config & ~CFG_BMAC_RX_ALL) == 0)); 2707 if ((config == 0) || (config & ~CFG_BMAC_RX_ALL) != 0) { 2708 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2709 " npi_bmac_rx_config" 2710 " Invalid Input: config <0x%x>", 2711 config)); 2712 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2713 } 2714 if (op == ENABLE) { 2715 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2716 if (config & CFG_BMAC_RX) 2717 val |= MAC_RX_CFG_RXMAC_ENABLE; 2718 if (config & CFG_BMAC_RX_STRIP_PAD) 2719 val |= MAC_RX_CFG_STRIP_PAD; 2720 if (config & CFG_BMAC_RX_STRIP_CRC) 2721 val |= MAC_RX_CFG_STRIP_FCS; 2722 if (config & CFG_BMAC_RX_PROMISCUOUS) 2723 val |= MAC_RX_CFG_PROMISC; 2724 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2725 val |= MAC_RX_CFG_PROMISC_GROUP; 2726 if (config & CFG_BMAC_RX_HASH_FILTER) 2727 val |= MAC_RX_CFG_HASH_FILTER_EN; 2728 if (config & CFG_BMAC_RX_ADDR_FILTER) 2729 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2730 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2731 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2732 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2733 } else { 2734 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2735 if (config & CFG_BMAC_RX) 2736 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2737 if (config & CFG_BMAC_RX_STRIP_PAD) 2738 val &= ~MAC_RX_CFG_STRIP_PAD; 2739 if (config & CFG_BMAC_RX_STRIP_CRC) 2740 val &= ~MAC_RX_CFG_STRIP_FCS; 2741 if (config & CFG_BMAC_RX_PROMISCUOUS) 2742 val &= ~MAC_RX_CFG_PROMISC; 2743 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2744 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2745 if (config & CFG_BMAC_RX_HASH_FILTER) 2746 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2747 if (config & CFG_BMAC_RX_ADDR_FILTER) 2748 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2749 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2750 val |= MAC_RX_CFG_DISABLE_DISCARD; 2751 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2752 } 2753 break; 2754 case INIT: 2755 ASSERT((config & ~CFG_BMAC_RX_ALL) == 0); 2756 if ((config & ~CFG_BMAC_RX_ALL) != 0) { 2757 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2758 " npi_bmac_rx_config" 2759 " Invalid Input: config <0x%x>", 2760 config)); 2761 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2762 } 2763 BMAC_REG_RD(handle, portn, RXMAC_CONFIG_REG, &val); 2764 if (config & CFG_BMAC_RX) 2765 val |= MAC_RX_CFG_RXMAC_ENABLE; 2766 else 2767 val &= ~MAC_RX_CFG_RXMAC_ENABLE; 2768 if (config & CFG_BMAC_RX_STRIP_PAD) 2769 val |= MAC_RX_CFG_STRIP_PAD; 2770 else 2771 val &= ~MAC_RX_CFG_STRIP_PAD; 2772 if (config & CFG_BMAC_RX_STRIP_CRC) 2773 val |= MAC_RX_CFG_STRIP_FCS; 2774 else 2775 val &= ~MAC_RX_CFG_STRIP_FCS; 2776 if (config & CFG_BMAC_RX_PROMISCUOUS) 2777 val |= MAC_RX_CFG_PROMISC; 2778 else 2779 val &= ~MAC_RX_CFG_PROMISC; 2780 if (config & CFG_BMAC_RX_PROMISCUOUSGROUP) 2781 val |= MAC_RX_CFG_PROMISC_GROUP; 2782 else 2783 val &= ~MAC_RX_CFG_PROMISC_GROUP; 2784 if (config & CFG_BMAC_RX_HASH_FILTER) 2785 val |= MAC_RX_CFG_HASH_FILTER_EN; 2786 else 2787 val &= ~MAC_RX_CFG_HASH_FILTER_EN; 2788 if (config & CFG_BMAC_RX_ADDR_FILTER) 2789 val |= MAC_RX_CFG_ADDR_FILTER_EN; 2790 else 2791 val &= ~MAC_RX_CFG_ADDR_FILTER_EN; 2792 if (config & CFG_BMAC_RX_DISCARD_ON_ERR) 2793 val &= ~MAC_RX_CFG_DISABLE_DISCARD; 2794 else 2795 val |= MAC_RX_CFG_DISABLE_DISCARD; 2796 2797 BMAC_REG_WR(handle, portn, RXMAC_CONFIG_REG, val); 2798 break; 2799 default: 2800 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2801 " npi_bmac_rx_config" 2802 " Invalid Input: op <0x%x>", op)); 2803 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2804 } 2805 2806 return (NPI_SUCCESS); 2807 } 2808 2809 npi_status_t 2810 npi_bmac_rx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2811 bmac_rx_iconfig_t iconfig) 2812 { 2813 uint64_t val = 0; 2814 2815 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2816 2817 switch (op) { 2818 case ENABLE: 2819 case DISABLE: 2820 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_RX_ALL) == 0)); 2821 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2822 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2823 " npi_bmac_rx_iconfig" 2824 " Invalid Input: iconfig <0x%x>", 2825 iconfig)); 2826 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2827 } 2828 BMAC_REG_RD(handle, portn, BRXMAC_STAT_MSK_REG, &val); 2829 if (op == ENABLE) 2830 val &= ~iconfig; 2831 else 2832 val |= iconfig; 2833 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, val); 2834 2835 break; 2836 case INIT: 2837 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 2838 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 2839 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2840 " npi_bmac_rx_iconfig" 2841 " Invalid Input: iconfig <0x%x>", 2842 iconfig)); 2843 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2844 } 2845 BMAC_REG_WR(handle, portn, BRXMAC_STAT_MSK_REG, ~iconfig); 2846 2847 break; 2848 default: 2849 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2850 " npi_bmac_rx_iconfig" 2851 " Invalid Input: iconfig <0x%x>", 2852 iconfig)); 2853 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2854 } 2855 2856 return (NPI_SUCCESS); 2857 } 2858 2859 npi_status_t 2860 npi_bmac_xif_config(npi_handle_t handle, config_op_t op, uint8_t portn, 2861 bmac_xif_config_t config) 2862 { 2863 uint64_t val = 0; 2864 2865 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2866 2867 switch (op) { 2868 case ENABLE: 2869 case DISABLE: 2870 ASSERT((config != 0) && ((config & ~CFG_BMAC_XIF_ALL) == 0)); 2871 if ((config == 0) || (config & ~CFG_BMAC_XIF_ALL) != 0) { 2872 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2873 " npi_bmac_xif_config" 2874 " Invalid Input: config <0x%x>", 2875 config)); 2876 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2877 } 2878 if (op == ENABLE) { 2879 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2880 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2881 val |= MAC_XIF_TX_OUTPUT_EN; 2882 if (config & CFG_BMAC_XIF_LOOPBACK) 2883 val |= MAC_XIF_MII_INT_LOOPBACK; 2884 if (config & CFG_BMAC_XIF_GMII_MODE) 2885 val |= MAC_XIF_GMII_MODE; 2886 if (config & CFG_BMAC_XIF_LINKLED) 2887 val |= MAC_XIF_LINK_LED; 2888 if (config & CFG_BMAC_XIF_LED_POLARITY) 2889 val |= MAC_XIF_LED_POLARITY; 2890 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2891 val |= MAC_XIF_SEL_CLK_25MHZ; 2892 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2893 } else { 2894 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2895 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2896 val &= ~MAC_XIF_TX_OUTPUT_EN; 2897 if (config & CFG_BMAC_XIF_LOOPBACK) 2898 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2899 if (config & CFG_BMAC_XIF_GMII_MODE) 2900 val &= ~MAC_XIF_GMII_MODE; 2901 if (config & CFG_BMAC_XIF_LINKLED) 2902 val &= ~MAC_XIF_LINK_LED; 2903 if (config & CFG_BMAC_XIF_LED_POLARITY) 2904 val &= ~MAC_XIF_LED_POLARITY; 2905 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2906 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2907 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2908 } 2909 break; 2910 case INIT: 2911 ASSERT((config & ~CFG_BMAC_XIF_ALL) == 0); 2912 if ((config & ~CFG_BMAC_XIF_ALL) != 0) { 2913 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2914 " npi_bmac_xif_config" 2915 " Invalid Input: config <0x%x>", 2916 config)); 2917 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2918 } 2919 BMAC_REG_RD(handle, portn, MAC_XIF_CONFIG_REG, &val); 2920 if (config & CFG_BMAC_XIF_TX_OUTPUT) 2921 val |= MAC_XIF_TX_OUTPUT_EN; 2922 else 2923 val &= ~MAC_XIF_TX_OUTPUT_EN; 2924 if (config & CFG_BMAC_XIF_LOOPBACK) 2925 val |= MAC_XIF_MII_INT_LOOPBACK; 2926 else 2927 val &= ~MAC_XIF_MII_INT_LOOPBACK; 2928 if (config & CFG_BMAC_XIF_GMII_MODE) 2929 val |= MAC_XIF_GMII_MODE; 2930 else 2931 val &= ~MAC_XIF_GMII_MODE; 2932 if (config & CFG_BMAC_XIF_LINKLED) 2933 val |= MAC_XIF_LINK_LED; 2934 else 2935 val &= ~MAC_XIF_LINK_LED; 2936 if (config & CFG_BMAC_XIF_LED_POLARITY) 2937 val |= MAC_XIF_LED_POLARITY; 2938 else 2939 val &= ~MAC_XIF_LED_POLARITY; 2940 if (config & CFG_BMAC_XIF_SEL_CLK_25MHZ) 2941 val |= MAC_XIF_SEL_CLK_25MHZ; 2942 else 2943 val &= ~MAC_XIF_SEL_CLK_25MHZ; 2944 BMAC_REG_WR(handle, portn, MAC_XIF_CONFIG_REG, val); 2945 break; 2946 default: 2947 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2948 " npi_bmac_xif_config" 2949 " Invalid Input: op <0x%x>", 2950 op)); 2951 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 2952 } 2953 2954 return (NPI_SUCCESS); 2955 } 2956 2957 npi_status_t 2958 npi_bmac_tx_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 2959 bmac_tx_iconfig_t iconfig) 2960 { 2961 uint64_t val = 0; 2962 2963 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 2964 2965 switch (op) { 2966 case ENABLE: 2967 case DISABLE: 2968 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_XMAC_TX_ALL) == 0)); 2969 if ((iconfig == 0) || (iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2970 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2971 " npi_bmac_tx_iconfig" 2972 " Invalid Input: iconfig <0x%x>", 2973 iconfig)); 2974 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2975 } 2976 BMAC_REG_RD(handle, portn, BTXMAC_STAT_MSK_REG, &val); 2977 if (op == ENABLE) 2978 val &= ~iconfig; 2979 else 2980 val |= iconfig; 2981 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, val); 2982 2983 break; 2984 case INIT: 2985 ASSERT((iconfig & ~ICFG_XMAC_TX_ALL) == 0); 2986 if ((iconfig & ~ICFG_XMAC_TX_ALL) != 0) { 2987 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2988 " npi_bmac_tx_iconfig" 2989 " Invalid Input: iconfig <0x%x>", 2990 iconfig)); 2991 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 2992 } 2993 BMAC_REG_WR(handle, portn, BTXMAC_STAT_MSK_REG, ~iconfig); 2994 2995 break; 2996 default: 2997 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 2998 " npi_bmac_tx_iconfig" 2999 " Invalid Input: iconfig <0x%x>", 3000 iconfig)); 3001 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 3002 } 3003 3004 return (NPI_SUCCESS); 3005 } 3006 3007 npi_status_t 3008 npi_bmac_ctl_iconfig(npi_handle_t handle, config_op_t op, uint8_t portn, 3009 bmac_ctl_iconfig_t iconfig) 3010 { 3011 uint64_t val = 0; 3012 3013 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3014 3015 switch (op) { 3016 case ENABLE: 3017 case DISABLE: 3018 ASSERT((iconfig != 0) && ((iconfig & ~ICFG_BMAC_CTL_ALL) == 0)); 3019 if ((iconfig == 0) || (iconfig & ~ICFG_BMAC_CTL_ALL) != 0) { 3020 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3021 " npi_bmac_ctl_iconfig" 3022 " Invalid Input: iconfig <0x%x>", 3023 iconfig)); 3024 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 3025 } 3026 BMAC_REG_RD(handle, portn, BMAC_C_S_MSK_REG, &val); 3027 if (op == ENABLE) 3028 val &= ~iconfig; 3029 else 3030 val |= iconfig; 3031 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, val); 3032 3033 break; 3034 case INIT: 3035 ASSERT((iconfig & ~ICFG_BMAC_RX_ALL) == 0); 3036 if ((iconfig & ~ICFG_BMAC_RX_ALL) != 0) { 3037 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3038 " npi_bmac_ctl_iconfig" 3039 " Invalid Input: iconfig <0x%x>", 3040 iconfig)); 3041 return (NPI_FAILURE | NPI_MAC_CONFIG_INVALID(portn)); 3042 } 3043 BMAC_REG_WR(handle, portn, BMAC_C_S_MSK_REG, ~iconfig); 3044 3045 break; 3046 default: 3047 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3048 " npi_bmac_ctl_iconfig" 3049 " Invalid Input: iconfig <0x%x>", 3050 iconfig)); 3051 return (NPI_FAILURE | NPI_MAC_OPCODE_INVALID(portn)); 3052 } 3053 3054 return (NPI_SUCCESS); 3055 } 3056 3057 npi_status_t 3058 npi_bmac_tx_get_istatus(npi_handle_t handle, uint8_t portn, 3059 bmac_tx_iconfig_t *istatus) 3060 { 3061 uint64_t val = 0; 3062 3063 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3064 3065 BMAC_REG_RD(handle, portn, BTXMAC_STATUS_REG, &val); 3066 *istatus = (uint32_t)val; 3067 3068 return (NPI_SUCCESS); 3069 } 3070 3071 npi_status_t 3072 npi_bmac_rx_get_istatus(npi_handle_t handle, uint8_t portn, 3073 bmac_rx_iconfig_t *istatus) 3074 { 3075 uint64_t val = 0; 3076 3077 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3078 3079 BMAC_REG_RD(handle, portn, BRXMAC_STATUS_REG, &val); 3080 *istatus = (uint32_t)val; 3081 3082 return (NPI_SUCCESS); 3083 } 3084 3085 npi_status_t 3086 npi_bmac_ctl_get_istatus(npi_handle_t handle, uint8_t portn, 3087 bmac_ctl_iconfig_t *istatus) 3088 { 3089 uint64_t val = 0; 3090 3091 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3092 3093 BMAC_REG_RD(handle, portn, BMAC_CTRL_STAT_REG, &val); 3094 *istatus = (uint32_t)val; 3095 3096 return (NPI_SUCCESS); 3097 } 3098 3099 npi_status_t 3100 npi_mac_mif_mdio_read(npi_handle_t handle, uint8_t portn, uint8_t device, 3101 uint16_t xcvr_reg, uint16_t *value) 3102 { 3103 mif_frame_t frame; 3104 uint_t delay; 3105 3106 frame.value = 0; 3107 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3108 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select address */ 3109 frame.bits.w0.phyad = portn; /* Port number */ 3110 frame.bits.w0.regad = device; /* Device number */ 3111 frame.bits.w0.ta_msb = 1; 3112 frame.bits.w0.ta_lsb = 0; 3113 frame.bits.w0.data = xcvr_reg; /* register address */ 3114 3115 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3116 "mdio read port %d addr val=0x%x\n", portn, frame.value)); 3117 3118 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3119 3120 delay = 0; 3121 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3122 3123 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3124 "mdio read port %d addr poll=0x%x\n", portn, frame.value)); 3125 3126 if (delay == MIF_DELAY) { 3127 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3128 "mdio read no response1\n")); 3129 } 3130 3131 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3132 frame.bits.w0.op = FRAME45_OP_READ; /* Read */ 3133 frame.bits.w0.phyad = portn; /* Port Number */ 3134 frame.bits.w0.regad = device; /* Device Number */ 3135 frame.bits.w0.ta_msb = 1; 3136 frame.bits.w0.ta_lsb = 0; 3137 3138 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3139 "mdio read port %d data frame=0x%x\n", portn, frame.value)); 3140 3141 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3142 3143 delay = 0; 3144 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3145 3146 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3147 "mdio read port %d data poll=0x%x\n", portn, frame.value)); 3148 3149 *value = frame.bits.w0.data; 3150 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3151 "mdio read port=%d val=0x%x\n", portn, *value)); 3152 3153 if (delay == MIF_DELAY) { 3154 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3155 "mdio read no response2\n")); 3156 } 3157 3158 return (NPI_SUCCESS); 3159 } 3160 3161 npi_status_t 3162 npi_mac_mif_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3163 uint16_t *value) 3164 { 3165 mif_frame_t frame; 3166 uint_t delay; 3167 3168 frame.bits.w0.st = 0x1; /* Clause 22 */ 3169 frame.bits.w0.op = 0x2; 3170 frame.bits.w0.phyad = portn; 3171 frame.bits.w0.regad = xcvr_reg; 3172 frame.bits.w0.ta_msb = 1; 3173 frame.bits.w0.ta_lsb = 0; 3174 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3175 3176 delay = 0; 3177 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3178 3179 if (delay == MAX_PIO_RETRIES) 3180 return (NPI_FAILURE | NPI_MAC_MII_READ_FAILED(portn)); 3181 3182 *value = frame.bits.w0.data; 3183 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3184 "mif mii read port %d reg=0x%x frame=0x%x\n", portn, 3185 xcvr_reg, frame.bits.w0.data)); 3186 3187 return (NPI_SUCCESS); 3188 } 3189 3190 npi_status_t 3191 npi_mac_mif_mdio_write(npi_handle_t handle, uint8_t portn, uint8_t device, 3192 uint16_t xcvr_reg, uint16_t value) 3193 { 3194 mif_frame_t frame; 3195 uint_t delay; 3196 3197 frame.value = 0; 3198 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3199 frame.bits.w0.op = FRAME45_OP_ADDR; /* Select Address */ 3200 frame.bits.w0.phyad = portn; /* Port Number */ 3201 frame.bits.w0.regad = device; /* Device Number */ 3202 frame.bits.w0.ta_msb = 1; 3203 frame.bits.w0.ta_lsb = 0; 3204 frame.bits.w0.data = xcvr_reg; /* register address */ 3205 3206 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3207 3208 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3209 "mdio write port %d addr val=0x%x\n", portn, frame.value)); 3210 3211 delay = 0; 3212 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3213 3214 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3215 "mdio write port %d addr poll=0x%x\n", portn, frame.value)); 3216 3217 if (delay == MIF_DELAY) { 3218 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3219 "mdio write no response1\n")); 3220 } 3221 3222 frame.bits.w0.st = FRAME45_ST; /* Clause 45 */ 3223 frame.bits.w0.op = FRAME45_OP_WRITE; /* Write */ 3224 frame.bits.w0.phyad = portn; /* Port number */ 3225 frame.bits.w0.regad = device; /* Device number */ 3226 frame.bits.w0.ta_msb = 1; 3227 frame.bits.w0.ta_lsb = 0; 3228 frame.bits.w0.data = value; 3229 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3230 3231 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3232 "mdio write port %d data val=0x%x\n", portn, frame.value)); 3233 3234 delay = 0; 3235 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MIF_DELAY); 3236 3237 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3238 "mdio write port %d data poll=0x%x\n", portn, frame.value)); 3239 3240 if (delay == MIF_DELAY) { 3241 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3242 "mdio write no response2\n")); 3243 } 3244 3245 return (NPI_SUCCESS); 3246 } 3247 3248 npi_status_t 3249 npi_mac_mif_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3250 uint16_t value) 3251 { 3252 mif_frame_t frame; 3253 uint_t delay; 3254 3255 frame.bits.w0.st = 0x1; /* Clause 22 */ 3256 frame.bits.w0.op = 0x1; 3257 frame.bits.w0.phyad = portn; 3258 frame.bits.w0.regad = xcvr_reg; 3259 frame.bits.w0.ta_msb = 1; 3260 frame.bits.w0.ta_lsb = 0; 3261 frame.bits.w0.data = value; 3262 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3263 3264 delay = 0; 3265 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3266 3267 NPI_DEBUG_MSG((handle.function, MIF_CTL, 3268 "mif mii write port %d reg=0x%x frame=0x%x\n", portn, 3269 xcvr_reg, frame.value)); 3270 3271 if (delay == MAX_PIO_RETRIES) 3272 return (NPI_FAILURE | NPI_MAC_MII_WRITE_FAILED(portn)); 3273 3274 return (NPI_SUCCESS); 3275 } 3276 3277 npi_status_t 3278 npi_mac_pcs_mii_read(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3279 uint16_t *value) 3280 { 3281 pcs_anar_t pcs_anar; 3282 pcs_anar_t pcs_anlpar; 3283 pcs_stat_t pcs_stat; 3284 pcs_stat_mc_t pcs_stat_mc; 3285 mii_anar_t anar; 3286 mii_anar_t anlpar; 3287 mii_aner_t aner; 3288 mii_esr_t esr; 3289 mii_gsr_t gsr; 3290 uint64_t val = 0; 3291 3292 ASSERT(IS_PORT_NUM_VALID(portn)); 3293 3294 switch (xcvr_reg) { 3295 case MII_CONTROL: 3296 PCS_REG_RD(handle, portn, PCS_MII_CTRL_REG, &val); 3297 *value = (uint16_t)val; 3298 break; 3299 case MII_STATUS: 3300 PCS_REG_RD(handle, portn, PCS_MII_STATUS_REG, &val); 3301 pcs_stat.value = val; 3302 PCS_REG_RD(handle, portn, PCS_STATE_MACHINE_REG, &val); 3303 pcs_stat_mc.value = val; 3304 if ((pcs_stat_mc.bits.w0.link_cfg_stat == 0xB) && 3305 (pcs_stat_mc.bits.w0.word_sync != 0)) { 3306 pcs_stat.bits.w0.link_stat = 1; 3307 } else if (pcs_stat_mc.bits.w0.link_cfg_stat != 0xB) { 3308 pcs_stat.bits.w0.link_stat = 0; 3309 } 3310 *value = (uint16_t)pcs_stat.value; 3311 break; 3312 case NXGE_MII_ESR: 3313 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3314 pcs_anar.value = (uint16_t)val; 3315 esr.value = 0; 3316 esr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3317 esr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3318 *value = esr.value; 3319 break; 3320 case MII_AN_ADVERT: 3321 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3322 pcs_anar.value = (uint16_t)val; 3323 anar.value = 0; 3324 anar.bits.cap_pause = pcs_anar.bits.w0.pause; 3325 anar.bits.cap_asmpause = pcs_anar.bits.w0.asm_pause; 3326 *value = anar.value; 3327 break; 3328 case MII_AN_LPABLE: 3329 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3330 pcs_anlpar.value = (uint16_t)val; 3331 anlpar.bits.cap_pause = pcs_anlpar.bits.w0.pause; 3332 anlpar.bits.cap_asmpause = pcs_anlpar.bits.w0.asm_pause; 3333 *value = anlpar.value; 3334 break; 3335 case MII_AN_EXPANSION: 3336 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3337 pcs_anar.value = (uint16_t)val; 3338 aner.value = 0; 3339 aner.bits.lp_an_able = pcs_anar.bits.w0.full_duplex | 3340 pcs_anar.bits.w0.half_duplex; 3341 *value = aner.value; 3342 break; 3343 case NXGE_MII_GSR: 3344 PCS_REG_RD(handle, portn, PCS_MII_LPA_REG, &val); 3345 pcs_anar.value = (uint16_t)val; 3346 gsr.value = 0; 3347 gsr.bits.link_1000fdx = pcs_anar.bits.w0.full_duplex; 3348 gsr.bits.link_1000hdx = pcs_anar.bits.w0.half_duplex; 3349 *value = gsr.value; 3350 break; 3351 default: 3352 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3353 " npi_mac_pcs_mii_read" 3354 " Invalid Input: xcvr_reg <0x%x>", 3355 xcvr_reg)); 3356 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3357 } 3358 3359 return (NPI_SUCCESS); 3360 } 3361 3362 npi_status_t 3363 npi_mac_pcs_mii_write(npi_handle_t handle, uint8_t portn, uint8_t xcvr_reg, 3364 uint16_t value) 3365 { 3366 pcs_anar_t pcs_anar; 3367 mii_anar_t anar; 3368 mii_gcr_t gcr; 3369 uint64_t val; 3370 3371 ASSERT(IS_PORT_NUM_VALID(portn)); 3372 3373 switch (xcvr_reg) { 3374 case MII_CONTROL: 3375 val = (uint16_t)value; 3376 PCS_REG_WR(handle, portn, PCS_MII_CTRL_REG, val); 3377 break; 3378 case MII_AN_ADVERT: 3379 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3380 pcs_anar.value = (uint16_t)val; 3381 anar.value = value; 3382 pcs_anar.bits.w0.asm_pause = anar.bits.cap_asmpause; 3383 pcs_anar.bits.w0.pause = anar.bits.cap_pause; 3384 val = pcs_anar.value; 3385 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3386 break; 3387 case NXGE_MII_GCR: 3388 PCS_REG_RD(handle, portn, PCS_MII_ADVERT_REG, &val); 3389 pcs_anar.value = (uint16_t)val; 3390 gcr.value = value; 3391 pcs_anar.bits.w0.full_duplex = gcr.bits.link_1000fdx; 3392 pcs_anar.bits.w0.half_duplex = gcr.bits.link_1000hdx; 3393 val = pcs_anar.value; 3394 PCS_REG_WR(handle, portn, PCS_MII_ADVERT_REG, val); 3395 break; 3396 default: 3397 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3398 " npi_mac_pcs_mii_write" 3399 " Invalid Input: xcvr_reg <0x%x>", 3400 xcvr_reg)); 3401 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3402 } 3403 3404 return (NPI_SUCCESS); 3405 } 3406 3407 npi_status_t 3408 npi_mac_mif_link_intr_enable(npi_handle_t handle, uint8_t portn, 3409 uint8_t xcvr_reg, uint16_t mask) 3410 { 3411 mif_cfg_t mif_cfg; 3412 3413 ASSERT(IS_PORT_NUM_VALID(portn)); 3414 3415 ASSERT(xcvr_reg <= NXGE_MAX_MII_REGS); 3416 if (xcvr_reg > NXGE_MAX_MII_REGS) { 3417 NPI_ERROR_MSG((handle.function, NPI_ERR_CTL, 3418 " npi_mac_mif_link_intr_enable" 3419 " Invalid Input: xcvr_reg <0x%x>", 3420 xcvr_reg)); 3421 return (NPI_FAILURE | NPI_MAC_REG_INVALID(portn)); 3422 } 3423 3424 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3425 3426 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3427 mif_cfg.bits.w0.reg_addr = xcvr_reg; /* Register address */ 3428 mif_cfg.bits.w0.indirect_md = 0; /* Clause 22 */ 3429 mif_cfg.bits.w0.poll_en = 1; 3430 3431 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3432 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3433 3434 NXGE_DELAY(20); 3435 3436 return (NPI_SUCCESS); 3437 } 3438 3439 npi_status_t 3440 npi_mac_mif_mdio_link_intr_enable(npi_handle_t handle, uint8_t portn, 3441 uint8_t device, uint16_t xcvr_reg, uint16_t mask) 3442 { 3443 mif_cfg_t mif_cfg; 3444 mif_frame_t frame; 3445 uint_t delay; 3446 3447 ASSERT(IS_PORT_NUM_VALID(portn)); 3448 3449 frame.bits.w0.st = 0; /* Clause 45 */ 3450 frame.bits.w0.op = 0; /* Select address */ 3451 frame.bits.w0.phyad = portn; /* Port number */ 3452 frame.bits.w0.regad = device; /* Device number */ 3453 frame.bits.w0.ta_msb = 1; 3454 frame.bits.w0.ta_lsb = 0; 3455 frame.bits.w0.data = xcvr_reg; /* register address */ 3456 3457 MIF_REG_WR(handle, MIF_OUTPUT_FRAME_REG, frame.value); 3458 3459 delay = 0; 3460 MIF_WAIT_REG(handle, frame, delay, MIF_DELAY, MAX_PIO_RETRIES); 3461 if (delay == MAX_PIO_RETRIES) 3462 return (NPI_FAILURE); 3463 3464 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3465 3466 mif_cfg.bits.w0.phy_addr = portn; /* Port number */ 3467 mif_cfg.bits.w0.reg_addr = device; /* Register address */ 3468 mif_cfg.bits.w0.indirect_md = 1; /* Clause 45 */ 3469 mif_cfg.bits.w0.poll_en = 1; 3470 3471 MIF_REG_WR(handle, MIF_MASK_REG, ~mask); 3472 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3473 3474 NXGE_DELAY(20); 3475 3476 return (NPI_SUCCESS); 3477 } 3478 3479 void 3480 npi_mac_mif_set_indirect_mode(npi_handle_t handle, boolean_t on_off) 3481 { 3482 mif_cfg_t mif_cfg; 3483 3484 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3485 mif_cfg.bits.w0.indirect_md = on_off; 3486 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3487 } 3488 3489 void 3490 npi_mac_mif_set_atca_mode(npi_handle_t handle, boolean_t on_off) 3491 { 3492 mif_cfg_t mif_cfg; 3493 3494 MIF_REG_RD(handle, MIF_CONFIG_REG, &mif_cfg.value); 3495 mif_cfg.bits.w0.atca_ge = on_off; 3496 MIF_REG_WR(handle, MIF_CONFIG_REG, mif_cfg.value); 3497 } 3498 3499 npi_status_t 3500 npi_bmac_send_pause(npi_handle_t handle, uint8_t portn, uint16_t pause_time) 3501 { 3502 uint64_t val; 3503 3504 ASSERT(IS_BMAC_PORT_NUM_VALID(portn)); 3505 3506 val = MAC_SEND_PAUSE_SEND | pause_time; 3507 BMAC_REG_WR(handle, portn, MAC_SEND_PAUSE_REG, val); 3508 3509 return (NPI_SUCCESS); 3510 } 3511 3512 npi_status_t 3513 npi_xmac_xif_led(npi_handle_t handle, uint8_t portn, boolean_t on_off) 3514 { 3515 uint64_t val = 0; 3516 3517 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3518 3519 XMAC_REG_RD(handle, portn, XMAC_CONFIG_REG, &val); 3520 3521 if (on_off) { 3522 val |= XMAC_XIF_LED_POLARITY; 3523 val &= ~XMAC_XIF_FORCE_LED_ON; 3524 } else { 3525 val &= ~XMAC_XIF_LED_POLARITY; 3526 val |= XMAC_XIF_FORCE_LED_ON; 3527 } 3528 3529 XMAC_REG_WR(handle, portn, XMAC_CONFIG_REG, val); 3530 3531 return (NPI_SUCCESS); 3532 } 3533 3534 npi_status_t 3535 npi_xmac_zap_tx_counters(npi_handle_t handle, uint8_t portn) 3536 { 3537 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3538 3539 XMAC_REG_WR(handle, portn, XTXMAC_FRM_CNT_REG, 0); 3540 XMAC_REG_WR(handle, portn, XTXMAC_BYTE_CNT_REG, 0); 3541 3542 return (NPI_SUCCESS); 3543 } 3544 3545 npi_status_t 3546 npi_xmac_zap_rx_counters(npi_handle_t handle, uint8_t portn) 3547 { 3548 ASSERT(IS_XMAC_PORT_NUM_VALID(portn)); 3549 3550 XMAC_REG_WR(handle, portn, XRXMAC_BT_CNT_REG, 0); 3551 XMAC_REG_WR(handle, portn, XRXMAC_BC_FRM_CNT_REG, 0); 3552 XMAC_REG_WR(handle, portn, XRXMAC_MC_FRM_CNT_REG, 0); 3553 XMAC_REG_WR(handle, portn, XRXMAC_FRAG_CNT_REG, 0); 3554 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT1_REG, 0); 3555 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT2_REG, 0); 3556 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT3_REG, 0); 3557 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT4_REG, 0); 3558 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT5_REG, 0); 3559 XMAC_REG_WR(handle, portn, XRXMAC_HIST_CNT6_REG, 0); 3560 XMAC_REG_WR(handle, portn, XRXMAC_MPSZER_CNT_REG, 0); 3561 XMAC_REG_WR(handle, portn, XRXMAC_CRC_ER_CNT_REG, 0); 3562 XMAC_REG_WR(handle, portn, XRXMAC_CD_VIO_CNT_REG, 0); 3563 XMAC_REG_WR(handle, portn, XRXMAC_AL_ER_CNT_REG, 0); 3564 XMAC_REG_WR(handle, portn, XMAC_LINK_FLT_CNT_REG, 0); 3565 3566 return (NPI_SUCCESS); 3567 } 3568