1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2016 Nexenta Systems, Inc. All rights reserved. 14 * Copyright 2016 The MathWorks, Inc. All rights reserved. 15 */ 16 17 #ifndef _NVME_VAR_H 18 #define _NVME_VAR_H 19 20 #include <sys/ddi.h> 21 #include <sys/sunddi.h> 22 #include <sys/blkdev.h> 23 #include <sys/taskq_impl.h> 24 25 /* 26 * NVMe driver state 27 */ 28 29 #ifdef __cplusplus 30 /* extern "C" { */ 31 #endif 32 33 #define NVME_FMA_INIT 0x1 34 #define NVME_REGS_MAPPED 0x2 35 #define NVME_ADMIN_QUEUE 0x4 36 #define NVME_CTRL_LIMITS 0x8 37 #define NVME_INTERRUPTS 0x10 38 39 #define NVME_MIN_ADMIN_QUEUE_LEN 16 40 #define NVME_MIN_IO_QUEUE_LEN 16 41 #define NVME_DEFAULT_ADMIN_QUEUE_LEN 256 42 #define NVME_DEFAULT_IO_QUEUE_LEN 1024 43 #define NVME_DEFAULT_ASYNC_EVENT_LIMIT 10 44 #define NVME_MIN_ASYNC_EVENT_LIMIT 1 45 46 47 typedef struct nvme nvme_t; 48 typedef struct nvme_namespace nvme_namespace_t; 49 typedef struct nvme_dma nvme_dma_t; 50 typedef struct nvme_cmd nvme_cmd_t; 51 typedef struct nvme_qpair nvme_qpair_t; 52 typedef struct nvme_task_arg nvme_task_arg_t; 53 54 struct nvme_dma { 55 ddi_dma_handle_t nd_dmah; 56 ddi_acc_handle_t nd_acch; 57 ddi_dma_cookie_t nd_cookie; 58 uint_t nd_ncookie; 59 caddr_t nd_memp; 60 size_t nd_len; 61 boolean_t nd_cached; 62 }; 63 64 struct nvme_cmd { 65 nvme_sqe_t nc_sqe; 66 nvme_cqe_t nc_cqe; 67 68 void (*nc_callback)(void *); 69 bd_xfer_t *nc_xfer; 70 boolean_t nc_completed; 71 uint16_t nc_sqid; 72 73 nvme_dma_t *nc_dma; 74 75 kmutex_t nc_mutex; 76 kcondvar_t nc_cv; 77 78 taskq_ent_t nc_tqent; 79 nvme_t *nc_nvme; 80 }; 81 82 struct nvme_qpair { 83 size_t nq_nentry; 84 85 nvme_dma_t *nq_sqdma; 86 nvme_sqe_t *nq_sq; 87 uint_t nq_sqhead; 88 uint_t nq_sqtail; 89 uintptr_t nq_sqtdbl; 90 91 nvme_dma_t *nq_cqdma; 92 nvme_cqe_t *nq_cq; 93 uint_t nq_cqhead; 94 uint_t nq_cqtail; 95 uintptr_t nq_cqhdbl; 96 97 nvme_cmd_t **nq_cmd; 98 uint16_t nq_next_cmd; 99 uint_t nq_active_cmds; 100 int nq_phase; 101 102 kmutex_t nq_mutex; 103 }; 104 105 struct nvme { 106 dev_info_t *n_dip; 107 int n_progress; 108 109 caddr_t n_regs; 110 ddi_acc_handle_t n_regh; 111 112 kmem_cache_t *n_cmd_cache; 113 kmem_cache_t *n_prp_cache; 114 115 size_t n_inth_sz; 116 ddi_intr_handle_t *n_inth; 117 int n_intr_cnt; 118 uint_t n_intr_pri; 119 int n_intr_cap; 120 int n_intr_type; 121 int n_intr_types; 122 123 char *n_product; 124 char *n_vendor; 125 126 boolean_t n_dead; 127 boolean_t n_strict_version; 128 boolean_t n_ignore_unknown_vendor_status; 129 uint32_t n_admin_queue_len; 130 uint32_t n_io_queue_len; 131 uint16_t n_async_event_limit; 132 uint16_t n_abort_command_limit; 133 uint64_t n_max_data_transfer_size; 134 boolean_t n_volatile_write_cache_enabled; 135 int n_error_log_len; 136 137 int n_nssr_supported; 138 int n_doorbell_stride; 139 int n_timeout; 140 int n_arbitration_mechanisms; 141 int n_cont_queues_reqd; 142 int n_max_queue_entries; 143 int n_pageshift; 144 int n_pagesize; 145 146 int n_namespace_count; 147 int n_ioq_count; 148 149 nvme_identify_ctrl_t *n_idctl; 150 151 nvme_qpair_t *n_adminq; 152 nvme_qpair_t **n_ioq; 153 154 nvme_namespace_t *n_ns; 155 156 ddi_dma_attr_t n_queue_dma_attr; 157 ddi_dma_attr_t n_prp_dma_attr; 158 ddi_dma_attr_t n_sgl_dma_attr; 159 ddi_device_acc_attr_t n_reg_acc_attr; 160 ddi_iblock_cookie_t n_fm_ibc; 161 int n_fm_cap; 162 163 ksema_t n_abort_sema; 164 165 ddi_taskq_t *n_cmd_taskq; 166 167 nvme_error_log_entry_t *n_error_log; 168 nvme_health_log_t *n_health_log; 169 nvme_fwslot_log_t *n_fwslot_log; 170 171 /* errors detected by driver */ 172 uint32_t n_dma_bind_err; 173 uint32_t n_abort_failed; 174 uint32_t n_cmd_timeout; 175 uint32_t n_cmd_aborted; 176 uint32_t n_async_resubmit_failed; 177 uint32_t n_wrong_logpage; 178 uint32_t n_unknown_logpage; 179 uint32_t n_too_many_cookies; 180 uint32_t n_admin_queue_full; 181 182 /* errors detected by hardware */ 183 uint32_t n_data_xfr_err; 184 uint32_t n_internal_err; 185 uint32_t n_abort_rq_err; 186 uint32_t n_abort_sq_del; 187 uint32_t n_nvm_cap_exc; 188 uint32_t n_nvm_ns_notrdy; 189 uint32_t n_inv_cq_err; 190 uint32_t n_inv_qid_err; 191 uint32_t n_max_qsz_exc; 192 uint32_t n_inv_int_vect; 193 uint32_t n_inv_log_page; 194 uint32_t n_inv_format; 195 uint32_t n_inv_q_del; 196 uint32_t n_cnfl_attr; 197 uint32_t n_inv_prot; 198 uint32_t n_readonly; 199 200 /* errors reported by asynchronous events */ 201 uint32_t n_diagfail_event; 202 uint32_t n_persistent_event; 203 uint32_t n_transient_event; 204 uint32_t n_fw_load_event; 205 uint32_t n_reliability_event; 206 uint32_t n_temperature_event; 207 uint32_t n_spare_event; 208 uint32_t n_vendor_event; 209 uint32_t n_unknown_event; 210 211 }; 212 213 struct nvme_namespace { 214 nvme_t *ns_nvme; 215 bd_handle_t ns_bd_hdl; 216 217 uint32_t ns_id; 218 size_t ns_block_count; 219 size_t ns_block_size; 220 size_t ns_best_block_size; 221 222 boolean_t ns_ignore; 223 224 nvme_identify_nsid_t *ns_idns; 225 226 /* 227 * Section 7.7 of the spec describes how to get a unique ID for 228 * the controller: the vendor ID, the model name and the serial 229 * number shall be unique when combined. 230 * 231 * We add the hex namespace ID to get a unique ID for the namespace. 232 */ 233 char ns_devid[4 + 1 + 20 + 1 + 40 + 1 + 8 + 1]; 234 }; 235 236 struct nvme_task_arg { 237 nvme_t *nt_nvme; 238 nvme_cmd_t *nt_cmd; 239 }; 240 241 #ifdef __cplusplus 242 /* } */ 243 #endif 244 245 #endif /* _NVME_VAR_H */ 246